From 1093e341a8d1f38149f147225dd9fc95a924c361 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Tue, 11 Jun 2019 11:26:44 -0600 Subject: [PATCH 01/84] Added additional architecure files --- Dockerfile | 10 + run_local.bat | 2 + .../vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml | 1453 +++++++++++++++++ .../vpr/ARCH/k6_N10_scan_chain_template.xml | 1453 +++++++++++++++++ .../vpr/ARCH/k6_N10_sram_chain_HC_6Input.xml | 1040 ++++++++++++ .../ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml | 882 ++++++++++ vpr7_x2p/vpr/ARCH/k6_N10_sram_ptm45nm_TT.xml | 1452 ++++++++++++++++ vpr7_x2p/vpr/ARCH/k6_ReRAM_Winbond.xml | 1453 +++++++++++++++++ vpr7_x2p/vpr/go_ganesh.sh | 33 + 9 files changed, 7778 insertions(+) create mode 100755 Dockerfile create mode 100755 run_local.bat create mode 100755 vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml create mode 100755 vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_template.xml create mode 100755 vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_6Input.xml create mode 100755 vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml create mode 100755 vpr7_x2p/vpr/ARCH/k6_N10_sram_ptm45nm_TT.xml create mode 100755 vpr7_x2p/vpr/ARCH/k6_ReRAM_Winbond.xml create mode 100755 vpr7_x2p/vpr/go_ganesh.sh diff --git a/Dockerfile b/Dockerfile new file mode 100755 index 000000000..c573dbbee --- /dev/null +++ b/Dockerfile @@ -0,0 +1,10 @@ +FROM ubuntu:16.04 + +RUN apt-get update -qq -y +RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev + +RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default + +RUN git clone https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA +RUN cd OpenFPGA && make + diff --git a/run_local.bat b/run_local.bat new file mode 100755 index 000000000..578f750ce --- /dev/null +++ b/run_local.bat @@ -0,0 +1,2 @@ +docker run -it --rm -v "%cd%":/localfile -w="/localfile/vpr7_x2p/vpr" goreganesh/open_fpga ./go_ganesh.sh +pause diff --git a/vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml b/vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml new file mode 100755 index 000000000..f7cc298a6 --- /dev/null +++ b/vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml @@ -0,0 +1,1453 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 0e-12 0e-12 + + + 10e-12 0e-12 0e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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127e-12 + 127e-12 + 127e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.I[19:0] clb.O[4:0] + clb.I[39:20] clb.O[9:5] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_6Input.xml b/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_6Input.xml new file mode 100755 index 000000000..d0e972fab --- /dev/null +++ b/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_HC_6Input.xml @@ -0,0 +1,1040 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 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/dev/null +++ b/vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml @@ -0,0 +1,882 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + + + + + + + + + 10e-12 0e-12 0e-12 + + + 10e-12 0e-12 0e-12 + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + 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b/vpr7_x2p/vpr/ARCH/k6_N10_sram_ptm45nm_TT.xml @@ -0,0 +1,1452 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 0e-12 0e-12 + + + 10e-12 0e-12 0e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + 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file mode 100755 index 000000000..7caaa4f09 --- /dev/null +++ b/vpr7_x2p/vpr/go_ganesh.sh @@ -0,0 +1,33 @@ +#!/bin/bash +echo "#################################################" +echo "The current shell environment is the following:" +echo $0 +echo "#################################################" + +# Example of how to run vprset circuit_name = pip_add +#set circuit_name = pip_add +circuit_name=sync_4bits_add +circuit_blif=${PWD}/Circuits/${circuit_name}.blif +arch_file=${PWD}/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml +arch_file_template=${PWD}/ARCH/k6_N10_sram_chain_HC_template.xml +circuit_act=${PWD}/Circuits/${circuit_name}.act +circuit_verilog=${PWD}/Circuits/${circuit_name}.v +spice_output=${PWD}/spice_demo +verilog_output=${PWD}/verilog_demo +modelsim_ini=/uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini +openfpga_path=${PWD}/../.. + +# Make sure a clean start +rm -rf ${spice_output} +rm -rf ${verilog_output} + +echo "*******************************" +echo "THIS SCRIPT NEEDS TO BE SOURCED" +echo "source ./go.sh" +echo "*******************************" + +sed "s:OPENFPGAPATH:${openfpga_path}:g" ${arch_file_template} > ${arch_file} + +# Pack, place, and route a heterogeneous FPGA +# Packing uses the AAPack algorithm +./vpr ${arch_file} ${circuit_blif} --full_stats --nodisp --activity_file ${circuit_act} --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ${spice_output} --fpga_spice_print_top_testbench From 87ddca9f57428934c9c8b67b53f26a55e1500a00 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Wed, 26 Jun 2019 14:22:02 -0600 Subject: [PATCH 02/84] commiting current work. Stable but function not implemented yet --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 - .../fpga_x2p/verilog/verilog_report_timing.c | 531 +----------------- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 4 + 3 files changed, 23 insertions(+), 514 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index f4888c25f..0ea4fc420 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -288,8 +288,6 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); } - /* dump_verilog_sdc_file(); */ - /* dump verilog testbench only for input blif */ if (TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.print_input_blif_testbench) { blif_testbench_file_name = my_strcat(chomped_circuit_name, blif_testbench_verilog_file_postfix); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c index 495184f34..c8f5088ec 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c @@ -1016,6 +1016,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -unconstrained"); break; + /* All the types are verified before */ default: break; } @@ -1062,6 +1063,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + break; + /* All the types are verified before */ + default: break; } } @@ -1107,6 +1111,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + break; + /* All the types are verified before */ + default: break; } } @@ -1152,6 +1159,9 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + break; + /* All the types are verified before */ + default: break; } } @@ -1185,7 +1195,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, int path_cnt) { int L_wire; int ix, iy; - int cur_sb_x, cur_sb_y; int end_sb_x, end_sb_y; t_cb* next_cb = NULL; t_sb* next_sb = NULL; @@ -1368,6 +1377,8 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } @@ -1403,6 +1414,8 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } @@ -1438,6 +1451,8 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } @@ -1473,12 +1488,14 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, " -point_to_point"); fprintf(fp, " -unconstrained"); + default: + break; } } } } - if (NULL != rpt_name) { + if (NULL != rpt_name) { fprintf(fp, " > %s\n", rpt_name); } else { fprintf(fp, "\n"); @@ -1490,516 +1507,6 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, return; } -///* Print the pins of SBs that a routing wire will go through -// * from the src_rr_node to the des_rr_node -// */ -//static -//void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, -// t_syn_verilog_opts fpga_verilog_opts, -// const RRGSB& src_sb, -// t_rr_node* drive_rr_node, -// t_rr_node* src_rr_node, -// t_rr_node* des_rr_node, -// int path_cnt) { -// int L_wire; -// int cur_sb_x, cur_sb_y; -// int end_sb_x, end_sb_y; -// t_cb* next_cb = NULL; -// char* rpt_name = NULL; -// DeviceCoordinator next_sb_coordinator; -// RRGSB next_sb; -// -// /* Check the file handler */ -// if (NULL == fp) { -// vpr_printf(TIO_MESSAGE_ERROR, -// "(FILE:%s,LINE[%d])Invalid file handler for SDC generation", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Check */ -// assert ((INC_DIRECTION == src_rr_node->direction) -// ||(DEC_DIRECTION == src_rr_node->direction)); -// assert ((CHANX == src_rr_node->type) -// ||(CHANY == src_rr_node->type)); -// -// L_wire = get_rr_node_wire_length(src_rr_node); -// -// /* Get report name */ -// rpt_name = gen_verilog_one_routing_report_timing_rpt_name(fpga_verilog_opts.report_timing_path, -// L_wire, path_cnt); -// -// /* Start printing report timing info */ -// fprintf(fp, "# L%d wire, Path ID: %d\n", -// L_wire, -// path_cnt); -// /* Report timing for the SB MUX delay, from the drive_rr_node to the wire_rr_node */ -// verilog_generate_one_report_timing_within_sb(fp, src_sb, -// drive_rr_node, -// src_rr_node); -// if (NULL != rpt_name) { -// fprintf(fp, " > %s\n", rpt_name); -// } else { -// fprintf(fp, "\n"); -// } -// -// /* Switch depends on the type of des_rr_node */ -// switch(des_rr_node->type) { -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y] | -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_cb|<---| src_sb |--->|thru_cb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x][y] | -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case IPIN: -// /* Get the coordinate of ending CB */ -// next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node); -// assert(next_cb->type == src_rr_node->type); -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x - 1; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y - 1; -// } -// break; -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y+1]| -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_sb|<---| src_sb |--->|thru_sb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x+1][y]| -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case CHANX: -// case CHANY: -// /* Get the coordinate of ending CB */ -// next_sb_coordinator = get_chan_node_ending_sb_coordinator(src_rr_node, des_rr_node); -// next_sb = device_rr_gsb.get_gsb(next_sb_coordinator); -// end_sb_x = next_sb.get_sb_x(); -// end_sb_y = next_sb.get_sb_y(); -// break; -// default: -// vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Get the base coordinate of src_sb */ -// cur_sb_x = src_sb.get_sb_x(); -// cur_sb_y = src_sb.get_sb_y(); -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (int ix = src_sb.get_sb_x(); ix < end_sb_x; ix++) { -// DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(ix + 1, cur_sb_y); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (int iy = src_sb.get_sb_y(); iy < end_sb_y; iy++) { -// DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(cur_sb_x, iy + 1); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (int ix = src_sb.get_sb_x() - 1; ix > end_sb_x; ix--) { -// DeviceCoordinator begin_sb_coordinator(ix, cur_sb_y); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(ix - 1, cur_sb_y); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (int iy = src_sb.get_sb_y() - 1; iy > end_sb_y; iy--) { -// DeviceCoordinator begin_sb_coordinator(cur_sb_x, iy); -// RRGSB begin_sb = device_rr_gsb.get_gsb(begin_sb_coordinator); -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// begin_sb, src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// DeviceCoordinator end_sb_coordinator(cur_sb_x, iy - 1); -// RRGSB end_sb = device_rr_gsb.get_gsb(end_sb_coordinator); -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// begin_sb, src_rr_node, -// end_sb, src_rr_node, -// rpt_name); -// } -// } -// -// /* Free */ -// my_free(rpt_name); -// -// return; -//} -// -// -///* Print the pins of SBs that a routing wire will go through -// * from the src_rr_node to the des_rr_node -// */ -//static -//void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, -// t_syn_verilog_opts fpga_verilog_opts, -// t_sb* src_sb_info, -// t_rr_node* drive_rr_node, -// t_rr_node* src_rr_node, -// t_rr_node* des_rr_node, -// int path_cnt) { -// int L_wire; -// int ix, iy; -// int cur_sb_x, cur_sb_y; -// int end_sb_x, end_sb_y; -// t_cb* next_cb = NULL; -// t_sb* next_sb = NULL; -// char* rpt_name = NULL; -// -// /* Check the file handler */ -// if (NULL == fp) { -// vpr_printf(TIO_MESSAGE_ERROR, -// "(FILE:%s,LINE[%d])Invalid file handler for SDC generation", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Check */ -// assert ((INC_DIRECTION == src_rr_node->direction) -// ||(DEC_DIRECTION == src_rr_node->direction)); -// assert ((CHANX == src_rr_node->type) -// ||(CHANY == src_rr_node->type)); -// -// L_wire = get_rr_node_wire_length(src_rr_node); -// -// /* Get report name */ -// rpt_name = gen_verilog_one_routing_report_timing_rpt_name(fpga_verilog_opts.report_timing_path, -// L_wire, path_cnt); -// -// /* Start printing report timing info */ -// fprintf(fp, "# L%d wire, Path ID: %d\n", -// L_wire, -// path_cnt); -// /* Report timing for the SB MUX delay, from the drive_rr_node to the wire_rr_node */ -// verilog_generate_one_report_timing_within_sb(fp, src_sb_info, -// drive_rr_node, -// src_rr_node); -// if (NULL != rpt_name) { -// fprintf(fp, " > %s\n", rpt_name); -// } else { -// fprintf(fp, "\n"); -// } -// -// /* Switch depends on the type of des_rr_node */ -// switch(des_rr_node->type) { -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y] | -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_cb|<---| src_sb |--->|thru_cb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x][y] | -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_cb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case IPIN: -// /* Get the coordinate of ending CB */ -// next_cb = get_chan_rr_node_ending_cb(src_rr_node, des_rr_node); -// assert(next_cb->type == src_rr_node->type); -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// end_sb_x = next_cb->x - 1; -// end_sb_y = next_cb->y; -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// end_sb_x = next_cb->x; -// end_sb_y = next_cb->y - 1; -// } -// break; -// /* Range of SBs that on the path -// * --------- -// * | | -// * | des_sb | -// * | [x][y+1]| -// * --------- -// * /|\ -// * | -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * /|\ -// * | -// * -------- ------- --------- ------- -------- -// * | | | | | | | | | | -// * | des_sb |<---|thru_sb|<---| src_sb |--->|thru_sb|--->| des_sb | -// * |[x-1][y]| | [x][y]| | | | [x][y]| |[x+1][y]| -// * -------- ------- --------- ------- -------- -// * | -// * \|/ -// * --------- -// * | | -// * | thru_sb | -// * | | -// * --------- -// * | -// * \|/ -// * --------- -// * | | -// * | des_sb | -// * | [x][y-1]| -// * --------- -// */ -// case CHANX: -// case CHANY: -// /* Get the coordinate of ending CB */ -// next_sb = get_chan_rr_node_ending_sb(src_rr_node, des_rr_node); -// end_sb_x = next_sb->x; -// end_sb_y = next_sb->y; -// break; -// default: -// vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid type of rr_node!\n", -// __FILE__, __LINE__); -// exit(1); -// } -// -// /* Get the base coordinate of src_sb */ -// cur_sb_x = src_sb_info->x; -// cur_sb_y = src_sb_info->y; -// /* 4 cases: */ -// if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (ix = src_sb_info->x; ix < end_sb_x; ix++) { -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// des_rr_node, -// rpt_name); -// -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// &(sb_info[ix + 1][cur_sb_y]), src_rr_node, -// rpt_name); -// } -// } else if ((INC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (iy = src_sb_info->y; iy < end_sb_y; iy++) { -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y - 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// &(sb_info[cur_sb_x][iy + 1]), src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANX == src_rr_node->type)) { -// /* Follow the graph above, go through X channel */ -// for (ix = src_sb_info->x - 1; ix > end_sb_x; ix--) { -// /* If this is the ending point, we add a ending segment */ -// if (ix == end_sb_x + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[ix][cur_sb_y]), src_rr_node, -// &(sb_info[ix - 1][cur_sb_y]), src_rr_node, -// rpt_name); -// } -// } else if ((DEC_DIRECTION == src_rr_node->direction) -// &&(CHANY == src_rr_node->type)) { -// /* Follow the graph above, go through Y channel */ -// for (iy = src_sb_info->y - 1; iy > end_sb_y; iy--) { -// /* If this is the ending point, we add a ending segment */ -// if (iy == end_sb_y + 1) { -// verilog_generate_report_timing_one_sb_ending_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// des_rr_node, -// rpt_name); -// continue; -// } -// /* Report timing for the downstream segements, from a SB output to an adjacent CB input */ -// verilog_generate_report_timing_one_sb_thru_segments(fp, -// &(sb_info[cur_sb_x][iy]), src_rr_node, -// &(sb_info[cur_sb_x][iy - 1]), src_rr_node, -// rpt_name); -// } -// } -// -// /* Free */ -// my_free(rpt_name); -// -// return; -//} - /* Print the pins of SBs that a routing wire will go through * from the src_rr_node to the des_rr_node */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index abdfbba53..6e21f776e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -958,6 +958,8 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, /* fprintf(fp, "//----- BEGIN Global ports -----\n"); */ while(NULL != temp) { cur_global_port = (t_spice_model_port*)(temp->dptr); + fprintf(fp, ".%s(", + cur_global_port->prefix); if (TRUE == dump_port_type) { fprintf(fp, "%s [0:%d] %s", verilog_convert_port_type_to_string(cur_global_port->type), @@ -968,6 +970,8 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, cur_global_port->prefix, cur_global_port->size - 1); } + fprintf(fp, ")"); + /* if this is the tail, we do not dump a comma */ if (NULL != temp->next) { fprintf(fp, ", //---- global port \n"); From 0ce9846e47e06222cb893d8e204da172649b350e Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Wed, 26 Jun 2019 16:54:41 -0600 Subject: [PATCH 03/84] Stable, unfinished --- vpr7_x2p/vpr/SRC/base/OptionTokens.c | 1 + vpr7_x2p/vpr/SRC/base/OptionTokens.h | 1 + vpr7_x2p/vpr/SRC/base/ReadOptions.c | 2 + vpr7_x2p/vpr/SRC/base/SetupVPR.c | 5 +++ vpr7_x2p/vpr/SRC/base/vpr_api.c | 1 + vpr7_x2p/vpr/SRC/base/vpr_types.h | 1 + .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 +- .../fpga_x2p/verilog/verilog_report_timing.c | 1 + .../SRC/fpga_x2p/verilog/verilog_routing.c | 27 +++++++----- .../SRC/fpga_x2p/verilog/verilog_routing.h | 2 +- .../verilog/verilog_top_netlist_utils.c | 2 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 43 ++++++++++++++++++- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 3 ++ 13 files changed, 77 insertions(+), 14 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c index cb71d400c..f3984d4c7 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.c @@ -84,6 +84,7 @@ struct s_TokenPair OptionBaseTokenList[] = { /* Xifan TANG: Synthsizable Verilog */ { "fpga_verilog", OT_FPGA_VERILOG_SYN }, { "fpga_verilog_dir", OT_FPGA_VERILOG_SYN_DIR }, + { "fpga_verilog_explicit_mapping", OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING }, { "fpga_verilog_print_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH }, { "fpga_verilog_print_autocheck_top_testbench", OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH }, { "fpga_verilog_print_input_blif_testbench", OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH }, diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.h b/vpr7_x2p/vpr/SRC/base/OptionTokens.h index 6f426b26f..f31630281 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.h +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.h @@ -101,6 +101,7 @@ enum e_OptionBaseToken { /* Xifan TANG: Verilog Generation */ OT_FPGA_VERILOG_SYN, /* Xifan TANG: Synthesizable Verilog Dump */ OT_FPGA_VERILOG_SYN_DIR, /* Xifan TANG: Synthesizable Verilog Dump */ + OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING, /* Baudouin Chauviere: explicit pin mapping during verilog generation */ OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist */ OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for top-level netlist */ OT_FPGA_VERILOG_SYN_PRINT_INPUT_BLIF_TESTBENCH, /* Xifan Tang: Synthesizable Verilog, turn on option: output testbench for the orignial input blif */ diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c index 14ba29921..29096fae3 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c @@ -527,6 +527,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) { return Args; case OT_FPGA_VERILOG_SYN_DIR: return ReadString(Args, &Options->fpga_syn_verilog_dir); + case OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING: + return Args; case OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH: return Args; case OT_FPGA_VERILOG_SYN_PRINT_AUTOCHECK_TOP_TESTBENCH: diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 09441daa1..c63bbeb17 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -1088,6 +1088,7 @@ static void SetupSynVerilogOpts(t_options Options, /* Initialize */ syn_verilog_opts->dump_syn_verilog = FALSE; syn_verilog_opts->syn_verilog_dump_dir = NULL; + syn_verilog_opts->dump_explicit_verilog = FALSE; syn_verilog_opts->print_top_testbench = FALSE; syn_verilog_opts->print_autocheck_top_testbench = FALSE; syn_verilog_opts->reference_verilog_benchmark_file = NULL; @@ -1114,6 +1115,10 @@ static void SetupSynVerilogOpts(t_options Options, syn_verilog_opts->syn_verilog_dump_dir = my_strdup(Options.fpga_syn_verilog_dir); } + if (Options.Count[OT_FPGA_VERILOG_SYN_EXPLICIT_MAPPING]) { + syn_verilog_opts->dump_explicit_verilog = TRUE; + } + if (Options.Count[OT_FPGA_VERILOG_SYN_PRINT_TOP_TESTBENCH]) { syn_verilog_opts->print_top_testbench = TRUE; } diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 6827e010f..96353023b 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -194,6 +194,7 @@ void vpr_print_usage(void) { vpr_printf(TIO_MESSAGE_INFO, "Synthesizable Verilog Generator Options:\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_dir \n"); + vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_explicit_mapping\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_top_testbench\n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_autocheck_top_testbench \n"); vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_input_blif_testbench\n"); diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 02a0d3657..2a3089271 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -1253,6 +1253,7 @@ struct s_spice_opts { typedef struct s_syn_verilog_opts t_syn_verilog_opts; struct s_syn_verilog_opts { boolean dump_syn_verilog; + boolean dump_explicit_verilog; char* syn_verilog_dump_dir; boolean print_top_testbench; boolean print_input_blif_testbench; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 0ea4fc420..b98d07224 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -255,7 +255,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, /* Dump routing resources: switch blocks, connection blocks and channel tracks */ dump_verilog_routing_resources(sram_verilog_orgz_info, src_dir_path, rr_dir_path, Arch, &vpr_setup.RoutingArch, num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data, - vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); + vpr_setup.FPGA_SPICE_Opts); /* Dump logic blocks * Branches to go: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c index c8f5088ec..3961e2619 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c @@ -1195,6 +1195,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, int path_cnt) { int L_wire; int ix, iy; + int cur_sb_x, cur_sb_y; int end_sb_x, end_sb_y; t_cb* next_cb = NULL; t_sb* next_sb = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 47a1efec5..9616461b2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -941,7 +941,8 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, t_rr_node* cur_rr_node, int mux_size, t_rr_node** drive_rr_nodes, - int switch_index) { + int switch_index, + boolean is_explicit_mapping) { int input_cnt = 0; t_spice_model* verilog_model = NULL; int mux_level, path_id, cur_num_sram; @@ -1063,7 +1064,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -1382,7 +1383,8 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_sb, enum e_side chan_side, - size_t chan_node_id) { + size_t chan_node_id, + boolean is_explicit_mapping) { int num_drive_rr_nodes = 0; t_rr_node** drive_rr_nodes = NULL; @@ -1418,7 +1420,8 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, /* Print the multiplexer, fan_in >= 2 */ dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node, num_drive_rr_nodes, drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); + cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], + is_explicit_mapping); } /*Nothing should be done else*/ /* Free */ @@ -1778,7 +1781,8 @@ static void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, size_t module_id, size_t seg_id, - const RRGSB& rr_sb, enum e_side side) { + const RRGSB& rr_sb, enum e_side side, + boolean is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; Side side_manager(side); @@ -1874,7 +1878,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr } dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb, side_manager.get_side(), - itrack); + itrack, is_explicit_mapping); } } @@ -2166,7 +2170,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or static void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - const RRGSB& rr_sb) { + const RRGSB& rr_sb, + boolean is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; @@ -2284,7 +2289,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or if (OUT_PORT == rr_gsb.get_chan_node_direction(side_manager.get_side(), itrack)) { dump_verilog_unique_switch_box_interc(cur_sram_orgz_info, fp, rr_sb, side_manager.get_side(), - itrack); + itrack, is_explicit_mapping); } } } @@ -3764,9 +3769,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - boolean compact_routing_hierarchy) { + t_fpga_spice_opts FPGA_SPICE_Opts) { assert(UNI_DIRECTIONAL == routing_arch->directionality); + boolean compact_routing_hierarchy = FPGA_SPICE_Opts.compact_routing_hierarchy; + boolean explicit_port_mapping = FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog; /* Two major tasks: * 1. Generate sub-circuits for Routing Channels * 2. Generate sub-circuits for Switch Boxes @@ -3832,7 +3839,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_submodule(side_manager.get_side(), iseg); ++isb) { const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_submodule(isb, side_manager.get_side(), iseg); size_t seg_id = device_rr_gsb.get_segment_id(iseg); - dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side()); + dump_verilog_routing_switch_box_unique_side_module(cur_sram_orgz_info, verilog_dir, subckt_dir, isb, seg_id, unique_mirror, side_manager.get_side(), explicit_port_mapping); } } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index d5a2433ea..1cfd449b4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -132,6 +132,6 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - boolean compact_routing_hierarchy); + t_fpga_spice_opts FPGA_SPICE_Opts); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index b8c0933c4..90fdf268d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -477,7 +477,7 @@ void dump_verilog_defined_one_channel(FILE* fp, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports_explicit(fp, global_ports_head, FALSE)) { fprintf(fp, ",\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 6e21f776e..58f30aa43 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -958,8 +958,49 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, /* fprintf(fp, "//----- BEGIN Global ports -----\n"); */ while(NULL != temp) { cur_global_port = (t_spice_model_port*)(temp->dptr); - fprintf(fp, ".%s(", + if (TRUE == dump_port_type) { + fprintf(fp, "%s [0:%d] %s", + verilog_convert_port_type_to_string(cur_global_port->type), + cur_global_port->size - 1, cur_global_port->prefix); + } else { + fprintf(fp, "%s[0:%d]", + cur_global_port->prefix, + cur_global_port->size - 1); + } + + /* if this is the tail, we do not dump a comma */ + if (NULL != temp->next) { + fprintf(fp, ", //---- global port \n"); + } + /* Update counter */ + dumped_port_cnt++; + /* Go to the next */ + temp = temp->next; + } + /* fprintf(fp, "//----- END Global ports -----\n"); */ + + return dumped_port_cnt; +} + +/* Dump all the global ports that are stored in the linked list */ +int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head, + boolean dump_port_type) { + t_llist* temp = head; + t_spice_model_port* cur_global_port = NULL; + int dumped_port_cnt = 0; + + /* Check the file handler*/ + if (NULL == fp) { + vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", + __FILE__, __LINE__); + } + + /* fprintf(fp, "//----- BEGIN Global ports -----\n"); */ + while(NULL != temp) { + cur_global_port = (t_spice_model_port*)(temp->dptr); + fprintf(fp, ".%s(", + cur_global_port->prefix); if (TRUE == dump_port_type) { fprintf(fp, "%s [0:%d] %s", verilog_convert_port_type_to_string(cur_global_port->type), diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 5fdd6821a..282f4cfaa 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -78,6 +78,9 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, int dump_verilog_global_ports(FILE* fp, t_llist* head, boolean dump_port_type); +int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head, + boolean dump_port_type); + void dump_verilog_mux_sram_one_outport(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, t_spice_model* cur_mux_spice_model, int mux_size, From 7c742f1cbbc4c648a630e4cd875e62a8569df632 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 27 Jun 2019 10:29:57 -0600 Subject: [PATCH 04/84] Stable, is_explicit propagated through the code. Not implemented though except for muxes --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 4 +- .../verilog/verilog_compact_netlist.c | 18 ++- .../verilog/verilog_compact_netlist.h | 6 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 67 +++++++---- .../SRC/fpga_x2p/verilog/verilog_pbtypes.h | 18 ++- .../SRC/fpga_x2p/verilog/verilog_routing.c | 106 +++++++++++++----- .../SRC/fpga_x2p/verilog/verilog_routing.h | 18 ++- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 46 ++++++-- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 6 +- 9 files changed, 206 insertions(+), 83 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index b98d07224..20ea51ecd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -262,7 +262,9 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, * 1. a compact output * 2. a full-size output */ - dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, lb_dir_path, &Arch); + dump_compact_verilog_logic_blocks(sram_verilog_orgz_info, src_dir_path, + lb_dir_path, &Arch, + vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Dump internal structures of submodules */ dump_verilog_submodules(sram_verilog_orgz_info, src_dir_path, submodule_dir_path, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 064cb2623..5d20c5f2a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -281,7 +281,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf char* verilog_dir_path, char* subckt_dir_path, t_type_ptr phy_block_type, - int border_side) { + int border_side, + boolean is_explicit_mapping) { int iz; int temp_reserved_conf_bits_msb; int temp_iopad_lsb, temp_iopad_msb; @@ -343,7 +344,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "//----- Submodule of type_descriptor: %s -----\n", phy_block_type->name); /* Print a NULL logic block...*/ dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name_prefix, - phy_block_type->pb_graph_head, iz); + phy_block_type->pb_graph_head, iz, + is_explicit_mapping); fprintf(fp, "//----- END -----\n\n"); /* Switch Flag on dumping verilog module */ verilog_module_dumped = TRUE; @@ -512,7 +514,8 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - t_arch* arch) { + t_arch* arch, + boolean is_explicit_mapping) { int itype, iside, num_sides; int* stamped_spice_model_cnt = NULL; t_sram_orgz_info* stamped_sram_orgz_info = NULL; @@ -534,20 +537,23 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (iside = 0; iside < num_sides; iside++) { dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, - &type_descriptors[itype], iside); + &type_descriptors[itype], iside, + is_explicit_mapping); } continue; } else if (FILL_TYPE == &type_descriptors[itype]) { /* For CLB */ dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, - &type_descriptors[itype], -1); + &type_descriptors[itype], -1, + is_explicit_mapping); continue; } else { /* For heterogenenous blocks */ dump_compact_verilog_one_physical_block(cur_sram_orgz_info, verilog_dir, subckt_dir, - &type_descriptors[itype], -1); + &type_descriptors[itype], -1, + is_explicit_mapping); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index 87eb33f78..852415d67 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -5,12 +5,14 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf char* verilog_dir_path, char* subckt_dir_path, t_type_ptr phy_block_type, - int border_side); + int border_side, + boolean is_explicit_mapping); void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - t_arch* arch); + t_arch* arch, + boolean is_explicit_mapping); void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index ea01fc03e..51a85edc8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1037,7 +1037,8 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, char* parent_pin_prefix, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode) { + t_mode* cur_mode, + boolean is_explicit_mapping) { int iedge, ipin; int fan_in = 0; t_interconnect* cur_interc = NULL; @@ -1261,7 +1262,8 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, cur_interc->spice_model, cur_sram_orgz_info, - fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + fan_in, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits, + is_explicit_mapping); fprintf(fp, ");\n"); @@ -1318,7 +1320,8 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, char* formatted_pin_prefix, t_pb_graph_node* cur_pb_graph_node, enum e_spice_pb_port_type pb_port_type, - t_mode* cur_mode) { + t_mode* cur_mode, + boolean is_explicit_mapping) { int iport, ipin; /* Check the file handler*/ @@ -1339,7 +1342,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, formatted_pin_prefix, /* parent_pin_prefix */ INPUT2INPUT_INTERC, &(cur_pb_graph_node->input_pins[iport][ipin]), - cur_mode); + cur_mode, is_explicit_mapping); } } break; @@ -1351,7 +1354,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, formatted_pin_prefix, /* parent_pin_prefix */ OUTPUT2OUTPUT_INTERC, &(cur_pb_graph_node->output_pins[iport][ipin]), - cur_mode); + cur_mode, is_explicit_mapping); } } break; @@ -1363,7 +1366,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, formatted_pin_prefix, /* parent_pin_prefix */ INPUT2INPUT_INTERC, &(cur_pb_graph_node->clock_pins[iport][ipin]), - cur_mode); + cur_mode, is_explicit_mapping); } } break; @@ -1382,7 +1385,8 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* pin_prefix, t_pb_graph_node* cur_pb_graph_node, - int select_mode_index) { + int select_mode_index, + boolean is_explicit_mapping) { int ipb, jpb; t_mode* cur_mode = NULL; t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; @@ -1416,7 +1420,7 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix, cur_pb_graph_node, SPICE_PB_PORT_OUTPUT, - cur_mode); + cur_mode, is_explicit_mapping); /* We check input_pins of child_pb_graph_node and its the input_edges * Built the interconnections between inputs of cur_pb_graph_node and inputs of child_pb_graph_node @@ -1432,12 +1436,12 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix, child_pb_graph_node, SPICE_PB_PORT_INPUT, - cur_mode); + cur_mode, is_explicit_mapping); /* TODO: for clock pins, we should do the same work */ dump_verilog_pb_graph_port_interc(cur_sram_orgz_info, fp, formatted_pin_prefix, child_pb_graph_node, SPICE_PB_PORT_CLOCK, - cur_mode); + cur_mode, is_explicit_mapping); } } @@ -1582,7 +1586,8 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* subckt_prefix, t_pb_graph_node* cur_pb_graph_node, - int pb_type_index) { + int pb_type_index, + boolean is_explicit_mapping) { int mode_index, ipb, jpb, child_mode_index; t_pb_type* cur_pb_type = NULL; char* subckt_name = NULL; @@ -1645,8 +1650,10 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* Recursive*/ /* Refer to pack/output_clustering.c [LINE 392] */ /* Find the child pb that is mapped, and the mapping info is not stored in the physical mode ! */ - dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, pass_on_prefix, - &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), jpb); + dump_verilog_phy_pb_graph_node_rec( + cur_sram_orgz_info, fp, pass_on_prefix, + &(cur_pb_graph_node->child_pb_graph_nodes[mode_index][ipb][jpb]), + jpb, is_explicit_mapping); /* Free */ my_free(pass_on_prefix); /* Make the current module has been dumped */ @@ -1872,7 +1879,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, } } /* Print interconnections, set is_idle as TRUE*/ - dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, cur_pb_graph_node, mode_index); + dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, + cur_pb_graph_node, mode_index, + is_explicit_mapping); /* Check each pins of pb_graph_node */ /* Check and update stamped_sram_cnt */ /* Now we only dump one Verilog for each pb_type, and instance them when num_pb > 1 @@ -1951,7 +1960,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, int x, int y, int z, - t_type_ptr type_descriptor) { + t_type_ptr type_descriptor, + boolean is_explicit_mapping) { t_pb_graph_node* top_pb_graph_node = NULL; t_block* mapped_block = NULL; t_pb* top_pb = NULL; @@ -1978,7 +1988,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, } /* Recursively find all idle mode and print netlist*/ - dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name, top_pb_graph_node, z); + dump_verilog_phy_pb_graph_node_rec(cur_sram_orgz_info, fp, subckt_name, + top_pb_graph_node, z, is_explicit_mapping); return; } @@ -2464,7 +2475,8 @@ void dump_verilog_io_grid_block_subckt_pins(FILE* fp, void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, int ix, int iy, - t_arch* arch) { + t_arch* arch, + boolean is_explicit_mapping) { int subckt_name_str_len = 0; char* subckt_name = NULL; int iz; @@ -2517,7 +2529,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, /* Comments: Grid [x][y]*/ fprintf(fp, "//----- Grid[%d][%d] type_descriptor: %s[%d] -----\n", ix, iy, grid[ix][iy].type->name, iz); /* Print a NULL logic block...*/ - dump_verilog_physical_block(cur_sram_orgz_info, fp, subckt_name, ix, iy, iz, grid[ix][iy].type); + dump_verilog_physical_block(cur_sram_orgz_info, fp, subckt_name, ix, iy, iz, + grid[ix][iy].type, is_explicit_mapping); fprintf(fp, "//----- END -----\n\n"); } @@ -2687,7 +2700,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, */ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, - t_arch* arch) { + t_arch* arch, + boolean is_explicit_mapping) { int ix, iy; /* Check the grid*/ @@ -2709,7 +2723,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, assert(IO_TYPE != grid[ix][iy].type); /* Ensure a valid usage */ assert((0 == grid[ix][iy].usage)||(0 < grid[ix][iy].usage)); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } } @@ -2720,7 +2735,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (ix = 1; ix < (nx + 1); ix++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Right side : x = nx + 1, y = 1 .. ny*/ @@ -2728,7 +2744,8 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (iy = 1; iy < (ny + 1); iy++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Bottom side : x = 1 .. nx + 1, y = 0 */ @@ -2736,14 +2753,16 @@ void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, for (ix = 1; ix < (nx + 1); ix++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Left side: x = 0, y = 1 .. ny*/ ix = 0; for (iy = 1; iy < (ny + 1); iy++) { /* Ensure this is a io */ assert(IO_TYPE == grid[ix][iy].type); - dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, arch); + dump_verilog_physical_grid_blocks(cur_sram_orgz_info, subckt_dir, ix, iy, + arch, is_explicit_mapping); } /* Output a header file for all the logic blocks */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h index 42db03fb0..f5e45c2a7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h @@ -58,13 +58,15 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, char* parent_pin_prefix, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, - t_mode* cur_mode); + t_mode* cur_mode, + boolean is_explicit_mapping); void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* pin_prefix, t_pb_graph_node* cur_pb_graph_node, - int select_mode_index); + int select_mode_index, + boolean is_explicit_mapping); void dump_verilog_pb_graph_primitive_node(FILE* fp, char* subckt_prefix, @@ -84,7 +86,8 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* subckt_prefix, t_pb_graph_node* cur_pb_graph_node, - int pb_type_index); + int pb_type_index, + boolean is_explicit_mapping); void dump_verilog_block(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -101,7 +104,8 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, int x, int y, int z, - t_type_ptr type_descriptor); + t_type_ptr type_descriptor, + boolean is_explicit_mapping); void dump_verilog_grid_pins(FILE* fp, int x, int y, @@ -138,7 +142,8 @@ void dump_verilog_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, int ix, int iy, - t_arch* arch); + t_arch* arch, + boolean is_explicit_mapping); void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -147,7 +152,8 @@ void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info, t_type_ptr type_descriptor); void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, - char* subckt_dir, t_arch* arch); + char* subckt_dir, t_arch* arch, + boolean is_explicit_mapping); void rec_copy_name_mux_in_node(t_pb_graph_node* master_node, t_pb_graph_node* target_node); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 9616461b2..03a749747 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -694,7 +694,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, t_rr_node* cur_rr_node, int mux_size, t_rr_node** drive_rr_nodes, - int switch_index) { + int switch_index, + boolean is_explicit_mapping) { int inode, side, index, input_cnt = 0; int grid_x, grid_y; t_spice_model* verilog_model = NULL; @@ -837,7 +838,9 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, num_mux_conf_bits, + is_explicit_mapping); fprintf(fp, ");\n"); @@ -1068,17 +1071,31 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ",\n"); } + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".in("); + fprintf(fp, "%s_size%d_%d_inbus), ", + verilog_model->prefix, mux_size, verilog_model->cnt); + } + else { fprintf(fp, "%s_size%d_%d_inbus, ", verilog_model->prefix, mux_size, verilog_model->cnt); - + } /* Output port */ - dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".out("); + dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT); + fprintf(fp, ")"); + } + else { + dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT); + } /* Add a comma because dump_verilog_switch_box_chan_port does not add so */ fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); fprintf(fp, ");\n"); @@ -1327,7 +1344,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_sb* cur_sb_info, int chan_side, - t_rr_node* cur_rr_node) { + t_rr_node* cur_rr_node, + boolean is_explicit_mapping) { int sb_x, sb_y; int num_drive_rr_nodes = 0; t_rr_node** drive_rr_nodes = NULL; @@ -1370,7 +1388,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, /* Print the multiplexer, fan_in >= 2 */ dump_verilog_switch_box_mux(cur_sram_orgz_info, fp, cur_sb_info, chan_side, cur_rr_node, num_drive_rr_nodes, drive_rr_nodes, - cur_rr_node->drive_switches[DEFAULT_SWITCH_ID]); + cur_rr_node->drive_switches[DEFAULT_SWITCH_ID], + is_explicit_mapping); } /*Nothing should be done else*/ /* Free */ @@ -2352,7 +2371,8 @@ static void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_sb* cur_sb_info, - boolean compact_routing_hierarchy) { + boolean compact_routing_hierarchy, + boolean is_explicit_mapping) { int itrack, inode, side, ix, iy, x, y; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; FILE* fp = NULL; @@ -2485,7 +2505,9 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info ||(CHANY == cur_sb_info->chan_rr_node[side][itrack]->type)); /* We care INC_DIRECTION tracks at this side*/ if (OUT_PORT == cur_sb_info->chan_rr_node_direction[side][itrack]) { - dump_verilog_switch_box_interc(cur_sram_orgz_info, fp, cur_sb_info, side, cur_sb_info->chan_rr_node[side][itrack]); + dump_verilog_switch_box_interc(cur_sram_orgz_info, fp, cur_sb_info, side, + cur_sb_info->chan_rr_node[side][itrack], + is_explicit_mapping); } } } @@ -2768,7 +2790,8 @@ static void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { int mux_size, cur_num_sram, input_cnt = 0; t_rr_node** drive_rr_nodes = NULL; int mux_level, path_id, switch_index; @@ -2907,7 +2930,9 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); fprintf(fp, ");\n"); @@ -2995,7 +3020,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { int mux_size, cur_num_sram, input_cnt = 0; t_rr_node** drive_rr_nodes = NULL; int inode, mux_level, path_id, switch_index; @@ -3137,7 +3163,9 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, /* Different design technology requires different configuration bus! */ dump_verilog_mux_config_bus_ports(fp, verilog_model, cur_sram_orgz_info, - mux_size, cur_num_sram, num_mux_reserved_conf_bits, num_mux_conf_bits); + mux_size, cur_num_sram, + num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); fprintf(fp, ");\n"); @@ -3224,7 +3252,8 @@ static void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3237,7 +3266,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ - dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, src_rr_node); + dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, + src_rr_node, is_explicit_mapping); } /*Nothing should be done else*/ return; @@ -3247,7 +3277,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3264,7 +3295,8 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ - dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, src_rr_node); + dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, + src_rr_node, is_explicit_mapping); } /*Nothing should be done else*/ return; @@ -3389,7 +3421,8 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o static void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - const RRGSB& rr_cb, t_rr_type cb_type) { + const RRGSB& rr_cb, t_rr_type cb_type, + boolean is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; @@ -3499,7 +3532,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra enum e_side cb_ipin_side = cb_ipin_sides[iside]; for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { dump_verilog_connection_box_interc(cur_sram_orgz_info, fp, rr_gsb, cb_type, - rr_gsb.get_ipin_node(cb_ipin_side, inode)); + rr_gsb.get_ipin_node(cb_ipin_side, inode), + is_explicit_mapping); } } @@ -3552,7 +3586,8 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_cb* cur_cb_info, - boolean compact_routing_hierarchy) { + boolean compact_routing_hierarchy, + boolean is_explicit_mapping) { int itrack, inode, side, x, y; int side_cnt = 0; FILE* fp = NULL; @@ -3725,7 +3760,8 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ assert(NULL != cur_cb_info->ipin_rr_node[side]); for (inode = 0; inode < cur_cb_info->num_ipin_rr_nodes[side]; inode++) { dump_verilog_connection_box_interc(cur_sram_orgz_info, fp, cur_cb_info, - cur_cb_info->ipin_rr_node[side][inode]); + cur_cb_info->ipin_rr_node[side][inode], + is_explicit_mapping); } } @@ -3867,8 +3903,10 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (int iy = 0; iy < (ny + 1); iy++) { /* vpr_printf(TIO_MESSAGE_INFO, "Writing Switch Boxes[%d][%d]...\n", ix, iy); */ update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); - dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(sb_info[ix][iy]), - compact_routing_hierarchy); + dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, + subckt_dir, &(sb_info[ix][iy]), + compact_routing_hierarchy, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); } } @@ -3886,7 +3924,9 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* X - channels [1...nx][0..ny]*/ for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) { const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb); - dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX); + dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, + verilog_dir, subckt_dir, unique_mirror, CHANX, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } /* TODO: when we follow a tile organization, * updating the conf bits should follow a tile organization: CLB, SB and CBX, CBY */ @@ -3900,7 +3940,9 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* Y - channels [1...ny][0..nx]*/ for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) { const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb); - dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY); + dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, + verilog_dir, subckt_dir, unique_mirror, CHANY, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } for (size_t ix = 0; ix < cb_range.get_x(); ++ix) { @@ -3919,8 +3961,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, update_spice_models_routing_index_low(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); if ((TRUE == is_cb_exist(CHANX, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cbx_info[ix][iy]), - compact_routing_hierarchy); + dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, + verilog_dir, subckt_dir, + &(cbx_info[ix][iy]), + compact_routing_hierarchy, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); } @@ -3932,8 +3977,11 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, update_spice_models_routing_index_low(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); if ((TRUE == is_cb_exist(CHANY, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(cby_info[ix][iy]), - compact_routing_hierarchy); + dump_verilog_routing_connection_box_subckt(cur_sram_orgz_info, + verilog_dir, subckt_dir, + &(cby_info[ix][iy]), + compact_routing_hierarchy, + FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); } update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 1cfd449b4..52ac54cc7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -40,7 +40,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, t_rr_node* cur_rr_node, int mux_size, t_rr_node** drive_rr_nodes, - int switch_index); + int switch_index, + boolean is_explicit_mapping); int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, t_sb cur_sb_info, int chan_side, @@ -54,7 +55,8 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_sb* cur_sb_info, int chan_side, - t_rr_node* cur_rr_node); + t_rr_node* cur_rr_node, + boolean is_explicit_mapping); int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, t_sb cur_sb_info); @@ -68,7 +70,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_syn_verilog_opts fpga_verilog_opts, - boolean compact_routing_hierarchy); + boolean compact_routing_hierarchy, + boolean is_explicit_mapping); void dump_verilog_connection_box_short_interc(FILE* fp, @@ -78,12 +81,14 @@ void dump_verilog_connection_box_short_interc(FILE* fp, void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node); + t_rr_node* src_rr_node, + boolean is_explicit_mapping); void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node); + t_rr_node* src_rr_node, + boolean is_explicit_mapping); int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, @@ -121,7 +126,8 @@ int count_verilog_connection_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_o void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_cb* cur_cb_info, - boolean compact_routing_hierarchy); + boolean compact_routing_hierarchy, + boolean is_explicit_mapping); void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 58f30aa43..fefad5466 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2549,7 +2549,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits) { + int num_mux_conf_bits, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -2569,30 +2570,58 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m /* FOR Scan-chain, we need regular output of a scan-chain FF * We do not need a prefix implying MUX name, size and index */ + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 0, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram_inv("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 1, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } break; case SPICE_SRAM_MEMORY_BANK: /* configuration wire bus */ /* First bus is for sram_out in CMOS MUX * We need a prefix implying MUX name, size and index */ + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 0, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ".sram_inv("); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, mux_spice_model, mux_size, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + cur_num_sram, + cur_num_sram + num_mux_conf_bits - 1, 1, VERILOG_PORT_CONKT); + if (TRUE == is_explicit_mapping) { + fprintf(fp, ")"); + } break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid SRAM organization!\n", @@ -2608,7 +2637,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits) { + int num_mux_conf_bits, + boolean is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -2628,9 +2658,11 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, case SPICE_MODEL_DESIGN_CMOS: dump_verilog_cmos_mux_config_bus_ports(fp, mux_spice_model, cur_sram_orgz_info, mux_size, cur_num_sram, - num_mux_reserved_conf_bits, num_mux_conf_bits); + num_mux_reserved_conf_bits, + num_mux_conf_bits, is_explicit_mapping); break; case SPICE_MODEL_DESIGN_RRAM: + /*TODO: Do explicit mapping for the RRAM*/ /* configuration wire bus */ fprintf(fp, "%s_size%d_%d_configbus0, ", mux_spice_model->prefix, mux_size, mux_spice_model->cnt); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 282f4cfaa..5485ad97f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -187,13 +187,15 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits); + int num_mux_conf_bits, + boolean is_explicit_mapping); void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, - int num_mux_conf_bits); + int num_mux_conf_bits, + boolean is_explicit_mapping); void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, char* general_port_prefix, int lsb, int msb, From 54f6ca2687d29de621253b1c206fb405dec5c195 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 1 Jul 2019 11:07:23 -0600 Subject: [PATCH 05/84] Added lattice benchmark settings --- .gitignore | 4 + .../k6_N10_rram_memory_bank_SC_winbond90.xml | 553 +++++++ .../benchmarks/List/lattice_benchmark.txt | 2 + fpga_flow/benchmarks/Verilog/.gitignore | 1 + .../Verilog/lattice_ultra_example/.gitignore | 8 + .../PID/16x16bit_multiplier_pipelined.v | 1413 +++++++++++++++++ .../PID_Controller/PID/CLA_fixed.v | 259 +++ .../PID_Controller/PID/PID.v | 434 +++++ .../PID_Controller/PID/PID_defines.v | 8 + .../PID_Controller/PID/booth.v | 37 + .../source/top_module/delay_gen_ihd_ipd_isd.v | 207 +++ .../hardware/source/top_module/i2c_defines.v | 369 +++++ .../source/top_module/i2c_slave_data_fsm.v | 649 ++++++++ .../source/top_module/led_driver_19022014.v | 203 +++ .../top_module/mobeam_control_fsm_19022014.v | 1009 ++++++++++++ .../source/top_module/mobeam_delay_gen.v | 160 ++ .../mobeam_i2c_reg_interface_19022014.v | 377 +++++ .../source/top_module/testpll_pll_20_25Mhz.v | 82 + .../hardware/source/top_module/top_module.v | 334 ++++ .../user_logic_control_reg_i2c_data_buf.v | 138 ++ fpga_flow/configs/lattice_benchmark.conf | 31 + fpga_flow/run_benchmark.sh | 71 + fpga_flow/scripts/fpga_flow.pl | 504 +++--- fpga_flow/scripts/rewrite_path_in_file.pl | 138 -- fpga_flow/tech/.gitignore | 1 + 25 files changed, 6602 insertions(+), 390 deletions(-) create mode 100644 fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml create mode 100644 fpga_flow/benchmarks/List/lattice_benchmark.txt create mode 100644 fpga_flow/benchmarks/Verilog/.gitignore create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v create mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v create mode 100644 fpga_flow/configs/lattice_benchmark.conf create mode 100644 fpga_flow/run_benchmark.sh delete mode 100644 fpga_flow/scripts/rewrite_path_in_file.pl create mode 100644 fpga_flow/tech/.gitignore diff --git a/.gitignore b/.gitignore index 4205795c4..5651b1ed0 100644 --- a/.gitignore +++ b/.gitignore @@ -32,3 +32,7 @@ vpr7_x2p/vpr/vpr vpr7_x2p/printhandler/printhandlerdemo vpr7_x2p/libarchfpga/read_arch vpr7_x2p/pcre/pcredemo + +# Some local temporary files +.vscode +*_local.bat \ No newline at end of file diff --git a/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml b/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml new file mode 100644 index 000000000..bfd21a6d8 --- /dev/null +++ b/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml @@ -0,0 +1,553 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + 127e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk + clb.I[19:0] clb.O[4:0] + clb.I[39:20] clb.O[9:5] + + + + + + + + + + + + + + + + + + + diff --git a/fpga_flow/benchmarks/List/lattice_benchmark.txt b/fpga_flow/benchmarks/List/lattice_benchmark.txt new file mode 100644 index 000000000..912818af7 --- /dev/null +++ b/fpga_flow/benchmarks/List/lattice_benchmark.txt @@ -0,0 +1,2 @@ +# Circuit Names, fixed routing channel width, +PID/*.v, 120 \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/.gitignore b/fpga_flow/benchmarks/Verilog/.gitignore new file mode 100644 index 000000000..2e39c18d2 --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/.gitignore @@ -0,0 +1 @@ +lattice_ultra_example_source/ diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore new file mode 100644 index 000000000..7e0debc3e --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore @@ -0,0 +1,8 @@ +# Ignore everything +* +# But descend into directories +!*/ +!.gitignore +# Recursively allow files under subtree +!/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/** +!/PID_Controller/** diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v new file mode 100644 index 000000000..7e9f45680 --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v @@ -0,0 +1,1413 @@ +/*16x16-bit multiplier +Author: Zhu Xu +Email: m99a1@yahoo.cn +*/ + +//Booth Encoder Array +module booth_array( +input [15:0]multiplier, +output [7:0]zero, +output [7:0]double, +output [7:0]negation +); + +booth_radix4 booth_radix4_0( +{multiplier[1:0],1'b0}, +zero[0], +double[0], +negation[0] +); + +booth_radix4 booth_radix4_1( +multiplier[3:1], +zero[1], +double[1], +negation[1] +); + +booth_radix4 booth_radix4_2( +multiplier[5:3], +zero[2], +double[2], +negation[2] +); +booth_radix4 booth_radix4_3( +multiplier[7:5], +zero[3], +double[3], +negation[3] +); + +booth_radix4 booth_radix4_4( +multiplier[9:7], +zero[4], +double[4], +negation[4] +); + +booth_radix4 booth_radix4_5( +multiplier[11:9], +zero[5], +double[5], +negation[5] +); +booth_radix4 booth_radix4_6( +multiplier[13:11], +zero[6], +double[6], +negation[6] +); + +booth_radix4 booth_radix4_7( +multiplier[15:13], +zero[7], +double[7], +negation[7] +); + +endmodule + +/*partial product generator unit +generate one 17-bit partial with inversed MSB without correction bit for negation +*/ +module partial_product_gen( +input [15:0]md, //multiplicand +input zero, +input double, +input negation, +output [16:0]pp +); + +wire [15:0]nmd; +assign nmd=negation?~md:md; + +wire [15:0]zmd; +assign zmd=zero?0:nmd; + +assign pp=double?{~zmd[15],zmd[14:0],negation}:{~zmd[15],zmd[15:0]}; + +endmodule + +module half_adder( +input A, +input B, +output S, +output carry +); +assign S=A^B; +assign carry=A&B; +endmodule + +module full_adder( +input A, +input B, +input cin, +output S, +output cout +); +wire AB; +assign AB=A&B; +wire AxorB; +assign AxorB=A^B; +assign S=AxorB^cin; +assign cout=AB|(AxorB&cin); +endmodule + +module compressor42( +input A, +input B, +input C, +input D, +input cin, +output S, +output carry, +output cout +); +wire AB; +assign AB=A&B; +wire AxorB; +assign AxorB=A^B; +wire CD; +assign CD=C&D; +wire CxorD; +assign CxorD=C^D; + +wire AxBxCxD=AxorB^CxorD; + +assign cout=AB|CD; +assign carry=(AB&CD)|(AxorB&CxorD)|((AxBxCxD)&cin); + +assign S=AxBxCxD^cin; + +endmodule + + +module multiplier_16x16bit_pipelined( +input i_clk, +input i_rst, +input i_start, +input [15:0]i_md, +input [15:0]i_mr, +output [31:0]o_product, +output o_ready +); +/////////////////////////////////////////////////////////////stage 0/////////////////////////////////////////////////// + +reg [15:0]md; +reg [15:0]mr; +reg stage_0_ready; + +always @(posedge i_clk or negedge i_rst)begin + if(!i_rst)begin + md<=0; + mr<=0; + stage_0_ready<=0; + end + else begin + if(i_start)begin + md<=i_md; + mr<=i_mr; + end + stage_0_ready<=i_start; + end + +end + +wire [7:0]zero; +wire [7:0]double; +wire [7:0]negation; + +booth_array booth_array_0( +mr, +zero, +double, +negation +); + + +//layer 0 +wire layer_0_w0[1:0]; +wire layer_0_w1; +wire layer_0_w2[2:0]; +wire layer_0_w3[1:0]; +wire layer_0_w4[3:0]; +wire layer_0_w5[2:0]; +wire layer_0_w6[4:0]; +wire layer_0_w7[3:0]; +wire layer_0_w8[5:0]; +wire layer_0_w9[4:0]; +wire layer_0_w10[6:0]; +wire layer_0_w11[5:0]; +wire layer_0_w12[7:0]; +wire layer_0_w13[6:0]; +wire layer_0_w14[8:0]; +wire layer_0_w15[7:0]; +wire layer_0_w16[8:0]; +wire layer_0_w17[7:0]; +wire layer_0_w18[6:0]; +wire layer_0_w19[6:0]; +wire layer_0_w20[5:0]; +wire layer_0_w21[5:0]; +wire layer_0_w22[4:0]; +wire layer_0_w23[4:0]; +wire layer_0_w24[3:0]; +wire layer_0_w25[3:0]; +wire layer_0_w26[2:0]; +wire layer_0_w27[2:0]; +wire layer_0_w28[1:0]; +wire layer_0_w29[1:0]; +wire layer_0_w30; +wire layer_0_w31; +partial_product_gen partial_product_gen_0( +md, +zero[0], +double[0], +negation[0], +{layer_0_w16[0],layer_0_w15[0],layer_0_w14[0],layer_0_w13[0],layer_0_w12[0],layer_0_w11[0],layer_0_w10[0],layer_0_w9[0],layer_0_w8[0],layer_0_w7[0],layer_0_w6[0],layer_0_w5[0],layer_0_w4[0],layer_0_w3[0],layer_0_w2[0],layer_0_w1,layer_0_w0[0]} +); +partial_product_gen partial_product_gen_1( +md, +zero[1], +double[1], +negation[1], +{layer_0_w18[0],layer_0_w17[0],layer_0_w16[1],layer_0_w15[1],layer_0_w14[1],layer_0_w13[1],layer_0_w12[1],layer_0_w11[1],layer_0_w10[1],layer_0_w9[1],layer_0_w8[1],layer_0_w7[1],layer_0_w6[1],layer_0_w5[1],layer_0_w4[1],layer_0_w3[1],layer_0_w2[1]} +); +partial_product_gen partial_product_gen_2( +md, +zero[2], +double[2], +negation[2], +{layer_0_w20[0],layer_0_w19[0],layer_0_w18[1],layer_0_w17[1],layer_0_w16[2],layer_0_w15[2],layer_0_w14[2],layer_0_w13[2],layer_0_w12[2],layer_0_w11[2],layer_0_w10[2],layer_0_w9[2],layer_0_w8[2],layer_0_w7[2],layer_0_w6[2],layer_0_w5[2],layer_0_w4[2]} +); +partial_product_gen partial_product_gen_3( +md, +zero[3], +double[3], +negation[3], +{layer_0_w22[0],layer_0_w21[0],layer_0_w20[1],layer_0_w19[1],layer_0_w18[2],layer_0_w17[2],layer_0_w16[3],layer_0_w15[3],layer_0_w14[3],layer_0_w13[3],layer_0_w12[3],layer_0_w11[3],layer_0_w10[3],layer_0_w9[3],layer_0_w8[3],layer_0_w7[3],layer_0_w6[3]} +); +partial_product_gen partial_product_gen_4( +md, +zero[4], +double[4], +negation[4], +{layer_0_w24[0],layer_0_w23[0],layer_0_w22[1],layer_0_w21[1],layer_0_w20[2],layer_0_w19[2],layer_0_w18[3],layer_0_w17[3],layer_0_w16[4],layer_0_w15[4],layer_0_w14[4],layer_0_w13[4],layer_0_w12[4],layer_0_w11[4],layer_0_w10[4],layer_0_w9[4],layer_0_w8[4]} +); +partial_product_gen partial_product_gen_5( +md, +zero[5], +double[5], +negation[5], +{layer_0_w26[0],layer_0_w25[0],layer_0_w24[1],layer_0_w23[1],layer_0_w22[2],layer_0_w21[2],layer_0_w20[3],layer_0_w19[3],layer_0_w18[4],layer_0_w17[4],layer_0_w16[5],layer_0_w15[5],layer_0_w14[5],layer_0_w13[5],layer_0_w12[5],layer_0_w11[5],layer_0_w10[5]} +); +partial_product_gen partial_product_gen_6( +md, +zero[6], +double[6], +negation[6], +{layer_0_w28[0],layer_0_w27[0],layer_0_w26[1],layer_0_w25[1],layer_0_w24[2],layer_0_w23[2],layer_0_w22[3],layer_0_w21[3],layer_0_w20[4],layer_0_w19[4],layer_0_w18[5],layer_0_w17[5],layer_0_w16[6],layer_0_w15[6],layer_0_w14[6],layer_0_w13[6],layer_0_w12[6]} +); +partial_product_gen partial_product_gen_7( +md, +zero[7], +double[7], +negation[7], +{layer_0_w30,layer_0_w29[0],layer_0_w28[1],layer_0_w27[1],layer_0_w26[2],layer_0_w25[2],layer_0_w24[3],layer_0_w23[3],layer_0_w22[4],layer_0_w21[4],layer_0_w20[5],layer_0_w19[5],layer_0_w18[6],layer_0_w17[6],layer_0_w16[7],layer_0_w15[7],layer_0_w14[7]} +); +//correction for negation +assign layer_0_w0[1]=negation[0]; +//sign extension +assign layer_0_w16[8]=1; +assign layer_0_w17[7]=1; +//correction for negation +assign layer_0_w2[2]=negation[1]; +//sign extension +assign layer_0_w19[6]=1; +//correction for negation +assign layer_0_w4[3]=negation[2]; +//sign extension +assign layer_0_w21[5]=1; +//correction for negation +assign layer_0_w6[4]=negation[3]; +//sign extension +assign layer_0_w23[4]=1; +//correction for negation +assign layer_0_w8[5]=negation[4]; +//sign extension +assign layer_0_w25[3]=1; +//correction for negation +assign layer_0_w10[6]=negation[5]; +//sign extension +assign layer_0_w27[2]=1; +//correction for negation +assign layer_0_w12[7]=negation[6]; +//sign extension +assign layer_0_w29[1]=1; +//correction for negation +assign layer_0_w14[8]=negation[7]; +//sign extension +assign layer_0_w31=1; + +//layer 1 +wire layer_1_w0[1:0]; +wire layer_1_w1; +wire layer_1_w2[2:0]; +wire layer_1_w3[1:0]; +wire layer_1_w4[1:0]; +wire layer_1_w5[1:0]; +wire layer_1_w6[1:0]; +wire layer_1_w7[3:0]; +wire layer_1_w8[2:0]; +wire layer_1_w9[2:0]; +wire layer_1_w10[4:0]; +wire layer_1_w11[3:0]; +wire layer_1_w12[3:0]; +wire layer_1_w13[5:0]; +wire layer_1_w14[4:0]; +wire layer_1_w15[4:0]; +wire layer_1_w16[5:0]; +wire layer_1_w17[4:0]; +wire layer_1_w18[5:0]; +wire layer_1_w19[4:0]; +wire layer_1_w20[3:0]; +wire layer_1_w21[3:0]; +wire layer_1_w22[2:0]; +wire layer_1_w23[2:0]; +wire layer_1_w24[3:0]; +wire layer_1_w25[2:0]; +wire layer_1_w26[1:0]; +wire layer_1_w27[1:0]; +wire layer_1_w28[2:0]; +wire layer_1_w29[1:0]; +wire layer_1_w30; +wire layer_1_w31; +assign layer_1_w0[0]=layer_0_w0[0]; +assign layer_1_w0[1]=layer_0_w0[1]; +assign layer_1_w1=layer_0_w1; +assign layer_1_w2[0]=layer_0_w2[0]; +assign layer_1_w2[1]=layer_0_w2[1]; +assign layer_1_w2[2]=layer_0_w2[2]; +assign layer_1_w3[0]=layer_0_w3[0]; +assign layer_1_w3[1]=layer_0_w3[1]; +full_adder layer_1_full_adder_0( +layer_0_w4[0], +layer_0_w4[1], +layer_0_w4[2], +layer_1_w4[0], +layer_1_w5[0] +); +assign layer_1_w4[1]=layer_0_w4[3]; +full_adder layer_1_full_adder_1( +layer_0_w5[0], +layer_0_w5[1], +layer_0_w5[2], +layer_1_w5[1], +layer_1_w6[0] +); +compressor42 layer_1_compressor42_0( +layer_0_w6[0], +layer_0_w6[1], +layer_0_w6[2], +layer_0_w6[3], +layer_0_w6[4], +layer_1_w6[1], +layer_1_w7[0], +layer_1_w7[1] +); +full_adder layer_1_full_adder_2( +layer_0_w7[0], +layer_0_w7[1], +layer_0_w7[2], +layer_1_w7[2], +layer_1_w8[0] +); +assign layer_1_w7[3]=layer_0_w7[3]; +compressor42 layer_1_compressor42_1( +layer_0_w8[0], +layer_0_w8[1], +layer_0_w8[2], +layer_0_w8[3], +layer_0_w8[4], +layer_1_w8[1], +layer_1_w9[0], +layer_1_w9[1] +); +assign layer_1_w8[2]=layer_0_w8[5]; +compressor42 layer_1_compressor42_2( +layer_0_w9[0], +layer_0_w9[1], +layer_0_w9[2], +layer_0_w9[3], +layer_0_w9[4], +layer_1_w9[2], +layer_1_w10[0], +layer_1_w10[1] +); +compressor42 layer_1_compressor42_3( +layer_0_w10[0], +layer_0_w10[1], +layer_0_w10[2], +layer_0_w10[3], +layer_0_w10[4], +layer_1_w10[2], +layer_1_w11[0], +layer_1_w11[1] +); +assign layer_1_w10[3]=layer_0_w10[5]; +assign layer_1_w10[4]=layer_0_w10[6]; +compressor42 layer_1_compressor42_4( +layer_0_w11[0], +layer_0_w11[1], +layer_0_w11[2], +layer_0_w11[3], +layer_0_w11[4], +layer_1_w11[2], +layer_1_w12[0], +layer_1_w12[1] +); +assign layer_1_w11[3]=layer_0_w11[5]; +compressor42 layer_1_compressor42_5( +layer_0_w12[0], +layer_0_w12[1], +layer_0_w12[2], +layer_0_w12[3], +layer_0_w12[4], +layer_1_w12[2], +layer_1_w13[0], +layer_1_w13[1] +); +full_adder layer_1_full_adder_3( +layer_0_w12[5], +layer_0_w12[6], +layer_0_w12[7], +layer_1_w12[3], +layer_1_w13[2] +); +compressor42 layer_1_compressor42_6( +layer_0_w13[0], +layer_0_w13[1], +layer_0_w13[2], +layer_0_w13[3], +layer_0_w13[4], +layer_1_w13[3], +layer_1_w14[0], +layer_1_w14[1] +); +assign layer_1_w13[4]=layer_0_w13[5]; +assign layer_1_w13[5]=layer_0_w13[6]; +compressor42 layer_1_compressor42_7( +layer_0_w14[0], +layer_0_w14[1], +layer_0_w14[2], +layer_0_w14[3], +layer_0_w14[4], +layer_1_w14[2], +layer_1_w15[0], +layer_1_w15[1] +); +full_adder layer_1_full_adder_4( +layer_0_w14[5], +layer_0_w14[6], +layer_0_w14[7], +layer_1_w14[3], +layer_1_w15[2] +); +assign layer_1_w14[4]=layer_0_w14[8]; +compressor42 layer_1_compressor42_8( +layer_0_w15[0], +layer_0_w15[1], +layer_0_w15[2], +layer_0_w15[3], +layer_0_w15[4], +layer_1_w15[3], +layer_1_w16[0], +layer_1_w16[1] +); +full_adder layer_1_full_adder_5( +layer_0_w15[5], +layer_0_w15[6], +layer_0_w15[7], +layer_1_w15[4], +layer_1_w16[2] +); +compressor42 layer_1_compressor42_9( +layer_0_w16[0], +layer_0_w16[1], +layer_0_w16[2], +layer_0_w16[3], +layer_0_w16[4], +layer_1_w16[3], +layer_1_w17[0], +layer_1_w17[1] +); +full_adder layer_1_full_adder_6( +layer_0_w16[5], +layer_0_w16[6], +layer_0_w16[7], +layer_1_w16[4], +layer_1_w17[2] +); +assign layer_1_w16[5]=layer_0_w16[8]; +compressor42 layer_1_compressor42_10( +layer_0_w17[0], +layer_0_w17[1], +layer_0_w17[2], +layer_0_w17[3], +layer_0_w17[4], +layer_1_w17[3], +layer_1_w18[0], +layer_1_w18[1] +); +full_adder layer_1_full_adder_7( +layer_0_w17[5], +layer_0_w17[6], +layer_0_w17[7], +layer_1_w17[4], +layer_1_w18[2] +); +compressor42 layer_1_compressor42_11( +layer_0_w18[0], +layer_0_w18[1], +layer_0_w18[2], +layer_0_w18[3], +layer_0_w18[4], +layer_1_w18[3], +layer_1_w19[0], +layer_1_w19[1] +); +assign layer_1_w18[4]=layer_0_w18[5]; +assign layer_1_w18[5]=layer_0_w18[6]; +compressor42 layer_1_compressor42_12( +layer_0_w19[0], +layer_0_w19[1], +layer_0_w19[2], +layer_0_w19[3], +layer_0_w19[4], +layer_1_w19[2], +layer_1_w20[0], +layer_1_w20[1] +); +assign layer_1_w19[3]=layer_0_w19[5]; +assign layer_1_w19[4]=layer_0_w19[6]; +compressor42 layer_1_compressor42_13( +layer_0_w20[0], +layer_0_w20[1], +layer_0_w20[2], +layer_0_w20[3], +layer_0_w20[4], +layer_1_w20[2], +layer_1_w21[0], +layer_1_w21[1] +); +assign layer_1_w20[3]=layer_0_w20[5]; +compressor42 layer_1_compressor42_14( +layer_0_w21[0], +layer_0_w21[1], +layer_0_w21[2], +layer_0_w21[3], +layer_0_w21[4], +layer_1_w21[2], +layer_1_w22[0], +layer_1_w22[1] +); +assign layer_1_w21[3]=layer_0_w21[5]; +compressor42 layer_1_compressor42_15( +layer_0_w22[0], +layer_0_w22[1], +layer_0_w22[2], +layer_0_w22[3], +layer_0_w22[4], +layer_1_w22[2], +layer_1_w23[0], +layer_1_w23[1] +); +compressor42 layer_1_compressor42_16( +layer_0_w23[0], +layer_0_w23[1], +layer_0_w23[2], +layer_0_w23[3], +layer_0_w23[4], +layer_1_w23[2], +layer_1_w24[0], +layer_1_w24[1] +); +full_adder layer_1_full_adder_8( +layer_0_w24[0], +layer_0_w24[1], +layer_0_w24[2], +layer_1_w24[2], +layer_1_w25[0] +); +assign layer_1_w24[3]=layer_0_w24[3]; +full_adder layer_1_full_adder_9( +layer_0_w25[0], +layer_0_w25[1], +layer_0_w25[2], +layer_1_w25[1], +layer_1_w26[0] +); +assign layer_1_w25[2]=layer_0_w25[3]; +full_adder layer_1_full_adder_10( +layer_0_w26[0], +layer_0_w26[1], +layer_0_w26[2], +layer_1_w26[1], +layer_1_w27[0] +); +full_adder layer_1_full_adder_11( +layer_0_w27[0], +layer_0_w27[1], +layer_0_w27[2], +layer_1_w27[1], +layer_1_w28[0] +); +assign layer_1_w28[1]=layer_0_w28[0]; +assign layer_1_w28[2]=layer_0_w28[1]; +assign layer_1_w29[0]=layer_0_w29[0]; +assign layer_1_w29[1]=layer_0_w29[1]; +assign layer_1_w30=layer_0_w30; +assign layer_1_w31=layer_0_w31; + +//layer 2 +wire [1:0]layer_2_w0; +wire layer_2_w1; +wire [2:0]layer_2_w2; +wire [1:0]layer_2_w3; +wire [1:0]layer_2_w4; +wire [1:0]layer_2_w5; +wire [1:0]layer_2_w6; +wire [1:0]layer_2_w7; +wire [1:0]layer_2_w8; +wire [1:0]layer_2_w9; +wire [1:0]layer_2_w10; +wire [3:0]layer_2_w11; +wire [2:0]layer_2_w12; +wire [2:0]layer_2_w13; +wire [2:0]layer_2_w14; +wire [2:0]layer_2_w15; +wire [3:0]layer_2_w16; +wire [2:0]layer_2_w17; +wire [3:0]layer_2_w18; +wire [2:0]layer_2_w19; +wire [3:0]layer_2_w20; +wire [2:0]layer_2_w21; +wire [1:0]layer_2_w22; +wire [1:0]layer_2_w23; +wire [2:0]layer_2_w24; +wire [1:0]layer_2_w25; +wire [2:0]layer_2_w26; +wire [1:0]layer_2_w27; +wire layer_2_w28; +wire [2:0]layer_2_w29; +wire layer_2_w30; +wire layer_2_w31; +assign layer_2_w0[0]=layer_1_w0[0]; +assign layer_2_w0[1]=layer_1_w0[1]; +assign layer_2_w1=layer_1_w1; +assign layer_2_w2[0]=layer_1_w2[0]; +assign layer_2_w2[1]=layer_1_w2[1]; +assign layer_2_w2[2]=layer_1_w2[2]; +assign layer_2_w3[0]=layer_1_w3[0]; +assign layer_2_w3[1]=layer_1_w3[1]; +assign layer_2_w4[0]=layer_1_w4[0]; +assign layer_2_w4[1]=layer_1_w4[1]; +assign layer_2_w5[0]=layer_1_w5[0]; +assign layer_2_w5[1]=layer_1_w5[1]; +assign layer_2_w6[0]=layer_1_w6[0]; +assign layer_2_w6[1]=layer_1_w6[1]; +full_adder layer_2_full_adder_0( +layer_1_w7[0], +layer_1_w7[1], +layer_1_w7[2], +layer_2_w7[0], +layer_2_w8[0] +); +assign layer_2_w7[1]=layer_1_w7[3]; +full_adder layer_2_full_adder_1( +layer_1_w8[0], +layer_1_w8[1], +layer_1_w8[2], +layer_2_w8[1], +layer_2_w9[0] +); +full_adder layer_2_full_adder_2( +layer_1_w9[0], +layer_1_w9[1], +layer_1_w9[2], +layer_2_w9[1], +layer_2_w10[0] +); +compressor42 layer_2_compressor42_0( +layer_1_w10[0], +layer_1_w10[1], +layer_1_w10[2], +layer_1_w10[3], +layer_1_w10[4], +layer_2_w10[1], +layer_2_w11[0], +layer_2_w11[1] +); +full_adder layer_2_full_adder_3( +layer_1_w11[0], +layer_1_w11[1], +layer_1_w11[2], +layer_2_w11[2], +layer_2_w12[0] +); +assign layer_2_w11[3]=layer_1_w11[3]; +full_adder layer_2_full_adder_4( +layer_1_w12[0], +layer_1_w12[1], +layer_1_w12[2], +layer_2_w12[1], +layer_2_w13[0] +); +assign layer_2_w12[2]=layer_1_w12[3]; +compressor42 layer_2_compressor42_1( +layer_1_w13[0], +layer_1_w13[1], +layer_1_w13[2], +layer_1_w13[3], +layer_1_w13[4], +layer_2_w13[1], +layer_2_w14[0], +layer_2_w14[1] +); +assign layer_2_w13[2]=layer_1_w13[5]; +compressor42 layer_2_compressor42_2( +layer_1_w14[0], +layer_1_w14[1], +layer_1_w14[2], +layer_1_w14[3], +layer_1_w14[4], +layer_2_w14[2], +layer_2_w15[0], +layer_2_w15[1] +); +compressor42 layer_2_compressor42_3( +layer_1_w15[0], +layer_1_w15[1], +layer_1_w15[2], +layer_1_w15[3], +layer_1_w15[4], +layer_2_w15[2], +layer_2_w16[0], +layer_2_w16[1] +); +compressor42 layer_2_compressor42_4( +layer_1_w16[0], +layer_1_w16[1], +layer_1_w16[2], +layer_1_w16[3], +layer_1_w16[4], +layer_2_w16[2], +layer_2_w17[0], +layer_2_w17[1] +); +assign layer_2_w16[3]=layer_1_w16[5]; +compressor42 layer_2_compressor42_5( +layer_1_w17[0], +layer_1_w17[1], +layer_1_w17[2], +layer_1_w17[3], +layer_1_w17[4], +layer_2_w17[2], +layer_2_w18[0], +layer_2_w18[1] +); +compressor42 layer_2_compressor42_6( +layer_1_w18[0], +layer_1_w18[1], +layer_1_w18[2], +layer_1_w18[3], +layer_1_w18[4], +layer_2_w18[2], +layer_2_w19[0], +layer_2_w19[1] +); +assign layer_2_w18[3]=layer_1_w18[5]; +compressor42 layer_2_compressor42_7( +layer_1_w19[0], +layer_1_w19[1], +layer_1_w19[2], +layer_1_w19[3], +layer_1_w19[4], +layer_2_w19[2], +layer_2_w20[0], +layer_2_w20[1] +); +full_adder layer_2_full_adder_5( +layer_1_w20[0], +layer_1_w20[1], +layer_1_w20[2], +layer_2_w20[2], +layer_2_w21[0] +); +assign layer_2_w20[3]=layer_1_w20[3]; +full_adder layer_2_full_adder_6( +layer_1_w21[0], +layer_1_w21[1], +layer_1_w21[2], +layer_2_w21[1], +layer_2_w22[0] +); +assign layer_2_w21[2]=layer_1_w21[3]; +full_adder layer_2_full_adder_7( +layer_1_w22[0], +layer_1_w22[1], +layer_1_w22[2], +layer_2_w22[1], +layer_2_w23[0] +); +full_adder layer_2_full_adder_8( +layer_1_w23[0], +layer_1_w23[1], +layer_1_w23[2], +layer_2_w23[1], +layer_2_w24[0] +); +full_adder layer_2_full_adder_9( +layer_1_w24[0], +layer_1_w24[1], +layer_1_w24[2], +layer_2_w24[1], +layer_2_w25[0] +); +assign layer_2_w24[2]=layer_1_w24[3]; +full_adder layer_2_full_adder_10( +layer_1_w25[0], +layer_1_w25[1], +layer_1_w25[2], +layer_2_w25[1], +layer_2_w26[0] +); +assign layer_2_w26[1]=layer_1_w26[0]; +assign layer_2_w26[2]=layer_1_w26[1]; +assign layer_2_w27[0]=layer_1_w27[0]; +assign layer_2_w27[1]=layer_1_w27[1]; +full_adder layer_2_full_adder_11( +layer_1_w28[0], +layer_1_w28[1], +layer_1_w28[2], +layer_2_w28, +layer_2_w29[0] +); +assign layer_2_w29[1]=layer_1_w29[0]; +assign layer_2_w29[2]=layer_1_w29[1]; +assign layer_2_w30=layer_1_w30; +assign layer_2_w31=layer_1_w31; + + +///////////////////////////////////////////////////////stage 1/////////////////////////////////////////////////////// +reg [1:0]reg_layer_2_w0; +reg reg_layer_2_w1; +reg [2:0]reg_layer_2_w2; +reg [1:0]reg_layer_2_w3; +reg [1:0]reg_layer_2_w4; +reg [1:0]reg_layer_2_w5; +reg [1:0]reg_layer_2_w6; +reg [1:0]reg_layer_2_w7; +reg [1:0]reg_layer_2_w8; +reg [1:0]reg_layer_2_w9; +reg [1:0]reg_layer_2_w10; +reg [3:0]reg_layer_2_w11; +reg [2:0]reg_layer_2_w12; +reg [2:0]reg_layer_2_w13; +reg [2:0]reg_layer_2_w14; +reg [2:0]reg_layer_2_w15; +reg [3:0]reg_layer_2_w16; +reg [2:0]reg_layer_2_w17; +reg [3:0]reg_layer_2_w18; +reg [2:0]reg_layer_2_w19; +reg [3:0]reg_layer_2_w20; +reg [2:0]reg_layer_2_w21; +reg [1:0]reg_layer_2_w22; +reg [1:0]reg_layer_2_w23; +reg [2:0]reg_layer_2_w24; +reg [1:0]reg_layer_2_w25; +reg [2:0]reg_layer_2_w26; +reg [1:0]reg_layer_2_w27; +reg reg_layer_2_w28; +reg [2:0]reg_layer_2_w29; +reg reg_layer_2_w30; +reg reg_layer_2_w31; +reg stage_1_ready; +assign o_ready=stage_1_ready; + +always @(posedge i_clk or negedge i_rst)begin + if(!i_rst)begin + stage_1_ready<=0; + reg_layer_2_w0<=0; + reg_layer_2_w1<=0; + reg_layer_2_w2<=0; + reg_layer_2_w3<=0; + reg_layer_2_w4<=0; + reg_layer_2_w5<=0; + reg_layer_2_w6<=0; + reg_layer_2_w7<=0; + reg_layer_2_w8<=0; + reg_layer_2_w9<=0; + reg_layer_2_w10<=0; + reg_layer_2_w11<=0; + reg_layer_2_w12<=0; + reg_layer_2_w13<=0; + reg_layer_2_w14<=0; + reg_layer_2_w15<=0; + reg_layer_2_w16<=0; + reg_layer_2_w17<=0; + reg_layer_2_w18<=0; + reg_layer_2_w19<=0; + reg_layer_2_w20<=0; + reg_layer_2_w21<=0; + reg_layer_2_w22<=0; + reg_layer_2_w23<=0; + reg_layer_2_w24<=0; + reg_layer_2_w25<=0; + reg_layer_2_w26<=0; + reg_layer_2_w27<=0; + reg_layer_2_w28<=0; + reg_layer_2_w29<=0; + reg_layer_2_w30<=0; + reg_layer_2_w31<=0; + end + else begin + if(stage_0_ready)begin + reg_layer_2_w0<=layer_2_w0; + reg_layer_2_w1<=layer_2_w1; + reg_layer_2_w2<=layer_2_w2; + reg_layer_2_w3<=layer_2_w3; + reg_layer_2_w4<=layer_2_w4; + reg_layer_2_w5<=layer_2_w5; + reg_layer_2_w6<=layer_2_w6; + reg_layer_2_w7<=layer_2_w7; + reg_layer_2_w8<=layer_2_w8; + reg_layer_2_w9<=layer_2_w9; + reg_layer_2_w10<=layer_2_w10; + reg_layer_2_w11<=layer_2_w11; + reg_layer_2_w12<=layer_2_w12; + reg_layer_2_w13<=layer_2_w13; + reg_layer_2_w14<=layer_2_w14; + reg_layer_2_w15<=layer_2_w15; + reg_layer_2_w16<=layer_2_w16; + reg_layer_2_w17<=layer_2_w17; + reg_layer_2_w18<=layer_2_w18; + reg_layer_2_w19<=layer_2_w19; + reg_layer_2_w20<=layer_2_w20; + reg_layer_2_w21<=layer_2_w21; + reg_layer_2_w22<=layer_2_w22; + reg_layer_2_w23<=layer_2_w23; + reg_layer_2_w24<=layer_2_w24; + reg_layer_2_w25<=layer_2_w25; + reg_layer_2_w26<=layer_2_w26; + reg_layer_2_w27<=layer_2_w27; + reg_layer_2_w28<=layer_2_w28; + reg_layer_2_w29<=layer_2_w29; + reg_layer_2_w30<=layer_2_w30; + reg_layer_2_w31<=layer_2_w31; + end + stage_1_ready<=stage_0_ready; + end +end + +//layer 3 +wire layer_3_w0[1:0]; +wire layer_3_w1; +wire layer_3_w2[2:0]; +wire layer_3_w3[1:0]; +wire layer_3_w4[1:0]; +wire layer_3_w5[1:0]; +wire layer_3_w6[1:0]; +wire layer_3_w7[1:0]; +wire layer_3_w8[1:0]; +wire layer_3_w9[1:0]; +wire layer_3_w10[1:0]; +wire layer_3_w11[1:0]; +wire layer_3_w12[1:0]; +wire layer_3_w13[1:0]; +wire layer_3_w14[1:0]; +wire layer_3_w15[1:0]; +wire layer_3_w16[2:0]; +wire layer_3_w17[1:0]; +wire layer_3_w18[2:0]; +wire layer_3_w19[1:0]; +wire layer_3_w20[2:0]; +wire layer_3_w21[1:0]; +wire layer_3_w22[2:0]; +wire layer_3_w23[1:0]; +wire layer_3_w24; +wire layer_3_w25[2:0]; +wire layer_3_w26; +wire layer_3_w27[2:0]; +wire layer_3_w28; +wire layer_3_w29; +wire layer_3_w30[1:0]; +wire layer_3_w31; +assign layer_3_w0[0]=reg_layer_2_w0[0]; +assign layer_3_w0[1]=reg_layer_2_w0[1]; +assign layer_3_w1=reg_layer_2_w1; +assign layer_3_w2[0]=reg_layer_2_w2[0]; +assign layer_3_w2[1]=reg_layer_2_w2[1]; +assign layer_3_w2[2]=reg_layer_2_w2[2]; +assign layer_3_w3[0]=reg_layer_2_w3[0]; +assign layer_3_w3[1]=reg_layer_2_w3[1]; +assign layer_3_w4[0]=reg_layer_2_w4[0]; +assign layer_3_w4[1]=reg_layer_2_w4[1]; +assign layer_3_w5[0]=reg_layer_2_w5[0]; +assign layer_3_w5[1]=reg_layer_2_w5[1]; +assign layer_3_w6[0]=reg_layer_2_w6[0]; +assign layer_3_w6[1]=reg_layer_2_w6[1]; +assign layer_3_w7[0]=reg_layer_2_w7[0]; +assign layer_3_w7[1]=reg_layer_2_w7[1]; +assign layer_3_w8[0]=reg_layer_2_w8[0]; +assign layer_3_w8[1]=reg_layer_2_w8[1]; +assign layer_3_w9[0]=reg_layer_2_w9[0]; +assign layer_3_w9[1]=reg_layer_2_w9[1]; +assign layer_3_w10[0]=reg_layer_2_w10[0]; +assign layer_3_w10[1]=reg_layer_2_w10[1]; +full_adder layer_3_full_adder_0( +reg_layer_2_w11[0], +reg_layer_2_w11[1], +reg_layer_2_w11[2], +layer_3_w11[0], +layer_3_w12[0] +); +assign layer_3_w11[1]=reg_layer_2_w11[3]; +full_adder layer_3_full_adder_1( +reg_layer_2_w12[0], +reg_layer_2_w12[1], +reg_layer_2_w12[2], +layer_3_w12[1], +layer_3_w13[0] +); +full_adder layer_3_full_adder_2( +reg_layer_2_w13[0], +reg_layer_2_w13[1], +reg_layer_2_w13[2], +layer_3_w13[1], +layer_3_w14[0] +); +full_adder layer_3_full_adder_3( +reg_layer_2_w14[0], +reg_layer_2_w14[1], +reg_layer_2_w14[2], +layer_3_w14[1], +layer_3_w15[0] +); +full_adder layer_3_full_adder_4( +reg_layer_2_w15[0], +reg_layer_2_w15[1], +reg_layer_2_w15[2], +layer_3_w15[1], +layer_3_w16[0] +); +full_adder layer_3_full_adder_5( +reg_layer_2_w16[0], +reg_layer_2_w16[1], +reg_layer_2_w16[2], +layer_3_w16[1], +layer_3_w17[0] +); +assign layer_3_w16[2]=reg_layer_2_w16[3]; +full_adder layer_3_full_adder_6( +reg_layer_2_w17[0], +reg_layer_2_w17[1], +reg_layer_2_w17[2], +layer_3_w17[1], +layer_3_w18[0] +); +full_adder layer_3_full_adder_7( +reg_layer_2_w18[0], +reg_layer_2_w18[1], +reg_layer_2_w18[2], +layer_3_w18[1], +layer_3_w19[0] +); +assign layer_3_w18[2]=reg_layer_2_w18[3]; +full_adder layer_3_full_adder_8( +reg_layer_2_w19[0], +reg_layer_2_w19[1], +reg_layer_2_w19[2], +layer_3_w19[1], +layer_3_w20[0] +); +full_adder layer_3_full_adder_9( +reg_layer_2_w20[0], +reg_layer_2_w20[1], +reg_layer_2_w20[2], +layer_3_w20[1], +layer_3_w21[0] +); +assign layer_3_w20[2]=reg_layer_2_w20[3]; +full_adder layer_3_full_adder_10( +reg_layer_2_w21[0], +reg_layer_2_w21[1], +reg_layer_2_w21[2], +layer_3_w21[1], +layer_3_w22[0] +); +assign layer_3_w22[1]=reg_layer_2_w22[0]; +assign layer_3_w22[2]=reg_layer_2_w22[1]; +assign layer_3_w23[0]=reg_layer_2_w23[0]; +assign layer_3_w23[1]=reg_layer_2_w23[1]; +full_adder layer_3_full_adder_11( +reg_layer_2_w24[0], +reg_layer_2_w24[1], +reg_layer_2_w24[2], +layer_3_w24, +layer_3_w25[0] +); +assign layer_3_w25[1]=reg_layer_2_w25[0]; +assign layer_3_w25[2]=reg_layer_2_w25[1]; +full_adder layer_3_full_adder_12( +reg_layer_2_w26[0], +reg_layer_2_w26[1], +reg_layer_2_w26[2], +layer_3_w26, +layer_3_w27[0] +); +assign layer_3_w27[1]=reg_layer_2_w27[0]; +assign layer_3_w27[2]=reg_layer_2_w27[1]; +assign layer_3_w28=reg_layer_2_w28; +full_adder layer_3_full_adder_13( +reg_layer_2_w29[0], +reg_layer_2_w29[1], +reg_layer_2_w29[2], +layer_3_w29, +layer_3_w30[0] +); +assign layer_3_w30[1]=reg_layer_2_w30; +assign layer_3_w31=reg_layer_2_w31; + +//layer 4 +wire layer_4_w0[1:0]; +wire layer_4_w1; +wire layer_4_w2; +wire layer_4_w3[1:0]; +wire layer_4_w4[1:0]; +wire layer_4_w5[1:0]; +wire layer_4_w6[1:0]; +wire layer_4_w7[1:0]; +wire layer_4_w8[1:0]; +wire layer_4_w9[1:0]; +wire layer_4_w10[1:0]; +wire layer_4_w11[1:0]; +wire layer_4_w12[1:0]; +wire layer_4_w13[1:0]; +wire layer_4_w14[1:0]; +wire layer_4_w15[1:0]; +wire layer_4_w16[1:0]; +wire layer_4_w17[1:0]; +wire layer_4_w18[1:0]; +wire layer_4_w19[1:0]; +wire layer_4_w20[1:0]; +wire layer_4_w21[1:0]; +wire layer_4_w22[1:0]; +wire layer_4_w23[1:0]; +wire layer_4_w24[1:0]; +wire layer_4_w25; +wire layer_4_w26[1:0]; +wire layer_4_w27; +wire layer_4_w28[1:0]; +wire layer_4_w29; +wire layer_4_w30[1:0]; +wire layer_4_w31; +assign layer_4_w0[0]=layer_3_w0[0]; +assign layer_4_w0[1]=layer_3_w0[1]; +assign layer_4_w1=layer_3_w1; +full_adder layer_4_full_adder_0( +layer_3_w2[0], +layer_3_w2[1], +layer_3_w2[2], +layer_4_w2, +layer_4_w3[0] +); +half_adder layer_4_half_adder_0( +layer_3_w3[0], +layer_3_w3[1], +layer_4_w3[1], +layer_4_w4[0] +); +half_adder layer_4_half_adder_1( +layer_3_w4[0], +layer_3_w4[1], +layer_4_w4[1], +layer_4_w5[0] +); +half_adder layer_4_half_adder_2( +layer_3_w5[0], +layer_3_w5[1], +layer_4_w5[1], +layer_4_w6[0] +); +half_adder layer_4_half_adder_3( +layer_3_w6[0], +layer_3_w6[1], +layer_4_w6[1], +layer_4_w7[0] +); +half_adder layer_4_half_adder_4( +layer_3_w7[0], +layer_3_w7[1], +layer_4_w7[1], +layer_4_w8[0] +); +half_adder layer_4_half_adder_5( +layer_3_w8[0], +layer_3_w8[1], +layer_4_w8[1], +layer_4_w9[0] +); +half_adder layer_4_half_adder_6( +layer_3_w9[0], +layer_3_w9[1], +layer_4_w9[1], +layer_4_w10[0] +); +half_adder layer_4_half_adder_7( +layer_3_w10[0], +layer_3_w10[1], +layer_4_w10[1], +layer_4_w11[0] +); +half_adder layer_4_half_adder_8( +layer_3_w11[0], +layer_3_w11[1], +layer_4_w11[1], +layer_4_w12[0] +); +half_adder layer_4_half_adder_9( +layer_3_w12[0], +layer_3_w12[1], +layer_4_w12[1], +layer_4_w13[0] +); +half_adder layer_4_half_adder_10( +layer_3_w13[0], +layer_3_w13[1], +layer_4_w13[1], +layer_4_w14[0] +); +half_adder layer_4_half_adder_11( +layer_3_w14[0], +layer_3_w14[1], +layer_4_w14[1], +layer_4_w15[0] +); +half_adder layer_4_half_adder_12( +layer_3_w15[0], +layer_3_w15[1], +layer_4_w15[1], +layer_4_w16[0] +); +full_adder layer_4_full_adder_1( +layer_3_w16[0], +layer_3_w16[1], +layer_3_w16[2], +layer_4_w16[1], +layer_4_w17[0] +); +half_adder layer_4_half_adder_13( +layer_3_w17[0], +layer_3_w17[1], +layer_4_w17[1], +layer_4_w18[0] +); +full_adder layer_4_full_adder_2( +layer_3_w18[0], +layer_3_w18[1], +layer_3_w18[2], +layer_4_w18[1], +layer_4_w19[0] +); +half_adder layer_4_half_adder_14( +layer_3_w19[0], +layer_3_w19[1], +layer_4_w19[1], +layer_4_w20[0] +); +full_adder layer_4_full_adder_3( +layer_3_w20[0], +layer_3_w20[1], +layer_3_w20[2], +layer_4_w20[1], +layer_4_w21[0] +); +half_adder layer_4_half_adder_15( +layer_3_w21[0], +layer_3_w21[1], +layer_4_w21[1], +layer_4_w22[0] +); +full_adder layer_4_full_adder_4( +layer_3_w22[0], +layer_3_w22[1], +layer_3_w22[2], +layer_4_w22[1], +layer_4_w23[0] +); +half_adder layer_4_half_adder_16( +layer_3_w23[0], +layer_3_w23[1], +layer_4_w23[1], +layer_4_w24[0] +); +assign layer_4_w24[1]=layer_3_w24; +full_adder layer_4_full_adder_5( +layer_3_w25[0], +layer_3_w25[1], +layer_3_w25[2], +layer_4_w25, +layer_4_w26[0] +); +assign layer_4_w26[1]=layer_3_w26; +full_adder layer_4_full_adder_6( +layer_3_w27[0], +layer_3_w27[1], +layer_3_w27[2], +layer_4_w27, +layer_4_w28[0] +); +assign layer_4_w28[1]=layer_3_w28; +assign layer_4_w29=layer_3_w29; +assign layer_4_w30[0]=layer_3_w30[0]; +assign layer_4_w30[1]=layer_3_w30[1]; +assign layer_4_w31=layer_3_w31; + +//group reduction results into 2 numbers +wire [31:0]A,B; +assign A[0]=layer_4_w0[0]; +assign B[0]=layer_4_w0[1]; +assign A[1]=layer_4_w1; +assign B[1]=0; +assign A[2]=layer_4_w2; +assign B[2]=0; +assign A[3]=layer_4_w3[0]; +assign B[3]=layer_4_w3[1]; +assign A[4]=layer_4_w4[0]; +assign B[4]=layer_4_w4[1]; +assign A[5]=layer_4_w5[0]; +assign B[5]=layer_4_w5[1]; +assign A[6]=layer_4_w6[0]; +assign B[6]=layer_4_w6[1]; +assign A[7]=layer_4_w7[0]; +assign B[7]=layer_4_w7[1]; +assign A[8]=layer_4_w8[0]; +assign B[8]=layer_4_w8[1]; +assign A[9]=layer_4_w9[0]; +assign B[9]=layer_4_w9[1]; +assign A[10]=layer_4_w10[0]; +assign B[10]=layer_4_w10[1]; +assign A[11]=layer_4_w11[0]; +assign B[11]=layer_4_w11[1]; +assign A[12]=layer_4_w12[0]; +assign B[12]=layer_4_w12[1]; +assign A[13]=layer_4_w13[0]; +assign B[13]=layer_4_w13[1]; +assign A[14]=layer_4_w14[0]; +assign B[14]=layer_4_w14[1]; +assign A[15]=layer_4_w15[0]; +assign B[15]=layer_4_w15[1]; +assign A[16]=layer_4_w16[0]; +assign B[16]=layer_4_w16[1]; +assign A[17]=layer_4_w17[0]; +assign B[17]=layer_4_w17[1]; +assign A[18]=layer_4_w18[0]; +assign B[18]=layer_4_w18[1]; +assign A[19]=layer_4_w19[0]; +assign B[19]=layer_4_w19[1]; +assign A[20]=layer_4_w20[0]; +assign B[20]=layer_4_w20[1]; +assign A[21]=layer_4_w21[0]; +assign B[21]=layer_4_w21[1]; +assign A[22]=layer_4_w22[0]; +assign B[22]=layer_4_w22[1]; +assign A[23]=layer_4_w23[0]; +assign B[23]=layer_4_w23[1]; +assign A[24]=layer_4_w24[0]; +assign B[24]=layer_4_w24[1]; +assign A[25]=layer_4_w25; +assign B[25]=0; +assign A[26]=layer_4_w26[0]; +assign B[26]=layer_4_w26[1]; +assign A[27]=layer_4_w27; +assign B[27]=0; +assign A[28]=layer_4_w28[0]; +assign B[28]=layer_4_w28[1]; +assign A[29]=layer_4_w29; +assign B[29]=0; +assign A[30]=layer_4_w30[0]; +assign B[30]=layer_4_w30[1]; +assign A[31]=layer_4_w31; +assign B[31]=0; + +wire carry; +adder_32bit adder_32bit( +A, +B, +1'b0, +o_product, +carry +); + + +endmodule diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v new file mode 100644 index 000000000..bd68e0204 --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v @@ -0,0 +1,259 @@ +/*Carry look-ahead adder +Author: Zhu Xu +Email: m99a1@yahoo.cn +*/ + +module operator_A( +input A, +input B, +output P, +output G +); + +assign P=A^B; +assign G=A&B; + +endmodule + +module operator_B( +input P,G,P1,G1, +output Po,Go +); + +assign Po=P&P1; +assign Go=G|(P&G1); + +endmodule + +module operator_C( +input P,G,G1, +output Go +); + +assign Go=G|(P&G1); + +endmodule + + +/* 32-bit prefix-2 Han-Carlson adder +stage 0: Number of Generation=32, NP=32, NOA=32, NOB=0, NOC=0. +stage 1: NG=16, NP=15, NOA=0, NOB=15, NOC=1. +stage 2: NG=16, NP=14, NOA=0, NOB=14, NOC=1. +stage 3: NG=16, NP=12, NOA=0, NOB=12, NOC=2. +stage 4: NG=16, NP=8, NOA=0, NOB=8, NOC=4. +stage 5: NG=16, NP=0, NOA=0, NOB=0, NOC=8. +stage 6; NG=32, NP=0, NOA=0, NOB=0, NOC=15. +*/ +module adder_32bit( +input [31:0]i_a,i_b, +input i_c, +output [31:0]o_s, +output o_c +); + +//stage 0 +wire [31:0]P0,G0; +operator_A operator_A_0(i_a[0],i_b[0],P0[0],G0[0]); +operator_A operator_A_1(i_a[1],i_b[1],P0[1],G0[1]); +operator_A operator_A_2(i_a[2],i_b[2],P0[2],G0[2]); +operator_A operator_A_3(i_a[3],i_b[3],P0[3],G0[3]); +operator_A operator_A_4(i_a[4],i_b[4],P0[4],G0[4]); +operator_A operator_A_5(i_a[5],i_b[5],P0[5],G0[5]); +operator_A operator_A_6(i_a[6],i_b[6],P0[6],G0[6]); +operator_A operator_A_7(i_a[7],i_b[7],P0[7],G0[7]); +operator_A operator_A_8(i_a[8],i_b[8],P0[8],G0[8]); +operator_A operator_A_9(i_a[9],i_b[9],P0[9],G0[9]); +operator_A operator_A_10(i_a[10],i_b[10],P0[10],G0[10]); +operator_A operator_A_11(i_a[11],i_b[11],P0[11],G0[11]); +operator_A operator_A_12(i_a[12],i_b[12],P0[12],G0[12]); +operator_A operator_A_13(i_a[13],i_b[13],P0[13],G0[13]); +operator_A operator_A_14(i_a[14],i_b[14],P0[14],G0[14]); +operator_A operator_A_15(i_a[15],i_b[15],P0[15],G0[15]); +operator_A operator_A_16(i_a[16],i_b[16],P0[16],G0[16]); +operator_A operator_A_17(i_a[17],i_b[17],P0[17],G0[17]); +operator_A operator_A_18(i_a[18],i_b[18],P0[18],G0[18]); +operator_A operator_A_19(i_a[19],i_b[19],P0[19],G0[19]); +operator_A operator_A_20(i_a[20],i_b[20],P0[20],G0[20]); +operator_A operator_A_21(i_a[21],i_b[21],P0[21],G0[21]); +operator_A operator_A_22(i_a[22],i_b[22],P0[22],G0[22]); +operator_A operator_A_23(i_a[23],i_b[23],P0[23],G0[23]); +operator_A operator_A_24(i_a[24],i_b[24],P0[24],G0[24]); +operator_A operator_A_25(i_a[25],i_b[25],P0[25],G0[25]); +operator_A operator_A_26(i_a[26],i_b[26],P0[26],G0[26]); +operator_A operator_A_27(i_a[27],i_b[27],P0[27],G0[27]); +operator_A operator_A_28(i_a[28],i_b[28],P0[28],G0[28]); +operator_A operator_A_29(i_a[29],i_b[29],P0[29],G0[29]); +operator_A operator_A_30(i_a[30],i_b[30],P0[30],G0[30]); +operator_A operator_A_31(i_a[31],i_b[31],P0[31],G0[31]); + +//stage 1 +wire [15:0]G1; +wire [15:1]P1; +operator_C operator_C_stage_1_0(P0[0],G0[0],i_c,G1[0]); +operator_B operator_B_stage_1_1(P0[2],G0[2],P0[1],G0[1],P1[1],G1[1]); +operator_B operator_B_stage_1_2(P0[4],G0[4],P0[3],G0[3],P1[2],G1[2]); +operator_B operator_B_stage_1_3(P0[6],G0[6],P0[5],G0[5],P1[3],G1[3]); +operator_B operator_B_stage_1_4(P0[8],G0[8],P0[7],G0[7],P1[4],G1[4]); +operator_B operator_B_stage_1_5(P0[10],G0[10],P0[9],G0[9],P1[5],G1[5]); +operator_B operator_B_stage_1_6(P0[12],G0[12],P0[11],G0[11],P1[6],G1[6]); +operator_B operator_B_stage_1_7(P0[14],G0[14],P0[13],G0[13],P1[7],G1[7]); +operator_B operator_B_stage_1_8(P0[16],G0[16],P0[15],G0[15],P1[8],G1[8]); +operator_B operator_B_stage_1_9(P0[18],G0[18],P0[17],G0[17],P1[9],G1[9]); +operator_B operator_B_stage_1_10(P0[20],G0[20],P0[19],G0[19],P1[10],G1[10]); +operator_B operator_B_stage_1_11(P0[22],G0[22],P0[21],G0[21],P1[11],G1[11]); +operator_B operator_B_stage_1_12(P0[24],G0[24],P0[23],G0[23],P1[12],G1[12]); +operator_B operator_B_stage_1_13(P0[26],G0[26],P0[25],G0[25],P1[13],G1[13]); +operator_B operator_B_stage_1_14(P0[28],G0[28],P0[27],G0[27],P1[14],G1[14]); +operator_B operator_B_stage_1_15(P0[30],G0[30],P0[29],G0[29],P1[15],G1[15]); + + + +//stage 2 +wire [15:0]G2; +wire [15:2]P2; +assign G2[0]=G1[0]; +operator_C operator_C_stage_2_1(P1[1],G1[1],G1[0],G2[1]); +operator_B operator_B_stage_2_2(P1[2], G1[2],P1[1],G1[1],P2[2],G2[2]); +operator_B operator_B_stage_2_3(P1[3], G1[3],P1[2],G1[2],P2[3],G2[3]); +operator_B operator_B_stage_2_4(P1[4], G1[4],P1[3],G1[3],P2[4],G2[4]); +operator_B operator_B_stage_2_5(P1[5], G1[5],P1[4],G1[4],P2[5],G2[5]); +operator_B operator_B_stage_2_6(P1[6], G1[6],P1[5],G1[5],P2[6],G2[6]); +operator_B operator_B_stage_2_7(P1[7], G1[7],P1[6],G1[6],P2[7],G2[7]); +operator_B operator_B_stage_2_8(P1[8], G1[8],P1[7],G1[7],P2[8],G2[8]); +operator_B operator_B_stage_2_9(P1[9], G1[9],P1[8],G1[8],P2[9],G2[9]); +operator_B operator_B_stage_2_10(P1[10], G1[10],P1[9],G1[9],P2[10],G2[10]); +operator_B operator_B_stage_2_11(P1[11], G1[11],P1[10],G1[10],P2[11],G2[11]); +operator_B operator_B_stage_2_12(P1[12], G1[12],P1[11],G1[11],P2[12],G2[12]); +operator_B operator_B_stage_2_13(P1[13], G1[13],P1[12],G1[12],P2[13],G2[13]); +operator_B operator_B_stage_2_14(P1[14], G1[14],P1[13],G1[13],P2[14],G2[14]); +operator_B operator_B_stage_2_15(P1[15], G1[15],P1[14],G1[14],P2[15],G2[15]); + +//stage 3 +wire [15:0]G3; +wire [15:4]P3; +assign G3[0]=G2[0]; +assign G3[1]=G2[1]; +operator_C operator_C_stage_3_2(P2[2],G2[2],G2[0],G3[2]); +operator_C operator_C_stage_3_3(P2[3],G2[3],G2[1],G3[3]); +operator_B operator_B_stage_3_4(P2[4], G2[4],P2[2],G2[2],P3[4],G3[4]); +operator_B operator_B_stage_3_5(P2[5], G2[5],P2[3],G2[3],P3[5],G3[5]); +operator_B operator_B_stage_3_6(P2[6], G2[6],P2[4],G2[4],P3[6],G3[6]); +operator_B operator_B_stage_3_7(P2[7], G2[7],P2[5],G2[5],P3[7],G3[7]); +operator_B operator_B_stage_3_8(P2[8], G2[8],P2[6],G2[6],P3[8],G3[8]); +operator_B operator_B_stage_3_9(P2[9], G2[9],P2[7],G2[7],P3[9],G3[9]); +operator_B operator_B_stage_3_10(P2[10], G2[10],P2[8],G2[8],P3[10],G3[10]); +operator_B operator_B_stage_3_11(P2[11], G2[11],P2[9],G2[9],P3[11],G3[11]); +operator_B operator_B_stage_3_12(P2[12], G2[12],P2[10],G2[10],P3[12],G3[12]); +operator_B operator_B_stage_3_13(P2[13], G2[13],P2[11],G2[11],P3[13],G3[13]); +operator_B operator_B_stage_3_14(P2[14], G2[14],P2[12],G2[12],P3[14],G3[14]); +operator_B operator_B_stage_3_15(P2[15], G2[15],P2[13],G2[13],P3[15],G3[15]); + +//stage 4 +wire [15:0]G4; +wire [15:8]P4; +assign G4[0]=G3[0]; +assign G4[1]=G3[1]; +assign G4[2]=G3[2]; +assign G4[3]=G3[3]; +operator_C operator_C_stage_4_4(P3[4],G3[4],G3[0],G4[4]); +operator_C operator_C_stage_4_5(P3[5],G3[5],G3[1],G4[5]); +operator_C operator_C_stage_4_6(P3[6],G3[6],G3[2],G4[6]); +operator_C operator_C_stage_4_7(P3[7],G3[7],G3[3],G4[7]); +operator_B operator_B_stage_4_8(P3[8], G3[8],P3[4],G3[4],P4[8],G4[8]); +operator_B operator_B_stage_4_9(P3[9], G3[9],P3[5],G3[5],P4[9],G4[9]); +operator_B operator_B_stage_4_10(P3[10], G3[10],P3[6],G3[6],P4[10],G4[10]); +operator_B operator_B_stage_4_11(P3[11], G3[11],P3[7],G3[7],P4[11],G4[11]); +operator_B operator_B_stage_4_12(P3[12], G3[12],P3[8],G3[8],P4[12],G4[12]); +operator_B operator_B_stage_4_13(P3[13], G3[13],P3[9],G3[9],P4[13],G4[13]); +operator_B operator_B_stage_4_14(P3[14], G3[14],P3[10],G3[10],P4[14],G4[14]); +operator_B operator_B_stage_4_15(P3[15], G3[15],P3[11],G3[11],P4[15],G4[15]); + +//stage 5 +wire [15:0]G5; +assign G5[0]=G4[0]; +assign G5[1]=G4[1]; +assign G5[2]=G4[2]; +assign G5[3]=G4[3]; +assign G5[4]=G4[4]; +assign G5[5]=G4[5]; +assign G5[6]=G4[6]; +assign G5[7]=G4[7]; +operator_C operator_C_stage_5_8(P4[8],G4[8],G4[0],G5[8]); +operator_C operator_C_stage_5_9(P4[9],G4[9],G4[1],G5[9]); +operator_C operator_C_stage_5_10(P4[10],G4[10],G4[2],G5[10]); +operator_C operator_C_stage_5_11(P4[11],G4[11],G4[3],G5[11]); +operator_C operator_C_stage_5_12(P4[12],G4[12],G4[4],G5[12]); +operator_C operator_C_stage_5_13(P4[13],G4[13],G4[5],G5[13]); +operator_C operator_C_stage_5_14(P4[14],G4[14],G4[6],G5[14]); +operator_C operator_C_stage_5_15(P4[15],G4[15],G4[7],G5[15]); + +//stage 6 +wire [31:0]G6; +assign G6[0]=G5[0]; +assign G6[2]=G5[1]; +assign G6[4]=G5[2]; +assign G6[6]=G5[3]; +assign G6[8]=G5[4]; +assign G6[10]=G5[5]; +assign G6[12]=G5[6]; +assign G6[14]=G5[7]; +assign G6[16]=G5[8]; +assign G6[18]=G5[9]; +assign G6[20]=G5[10]; +assign G6[22]=G5[11]; +assign G6[24]=G5[12]; +assign G6[26]=G5[13]; +assign G6[28]=G5[14]; +assign G6[30]=G5[15]; +operator_C operator_C_stage_6_0(P0[1],G0[1],G5[0],G6[1]); +operator_C operator_C_stage_6_1(P0[3],G0[3],G5[1],G6[3]); +operator_C operator_C_stage_6_2(P0[5],G0[5],G5[2],G6[5]); +operator_C operator_C_stage_6_3(P0[7],G0[7],G5[3],G6[7]); +operator_C operator_C_stage_6_4(P0[9],G0[9],G5[4],G6[9]); +operator_C operator_C_stage_6_5(P0[11],G0[11],G5[5],G6[11]); +operator_C operator_C_stage_6_6(P0[13],G0[13],G5[6],G6[13]); +operator_C operator_C_stage_6_7(P0[15],G0[15],G5[7],G6[15]); +operator_C operator_C_stage_6_8(P0[17],G0[17],G5[8],G6[17]); +operator_C operator_C_stage_6_9(P0[19],G0[19],G5[9],G6[19]); +operator_C operator_C_stage_6_10(P0[21],G0[21],G5[10],G6[21]); +operator_C operator_C_stage_6_11(P0[23],G0[23],G5[11],G6[23]); +operator_C operator_C_stage_6_12(P0[25],G0[25],G5[12],G6[25]); +operator_C operator_C_stage_6_13(P0[27],G0[27],G5[13],G6[27]); +operator_C operator_C_stage_6_14(P0[29],G0[29],G5[14],G6[29]); +operator_C operator_C_stage_6_15(P0[31],G0[31],G5[15],G6[31]); + +assign o_s[0]=P0[0]^i_c; +assign o_s[1]=P0[1]^G6[0]; +assign o_s[2]=P0[2]^G6[1]; +assign o_s[3]=P0[3]^G6[2]; +assign o_s[4]=P0[4]^G6[3]; +assign o_s[5]=P0[5]^G6[4]; +assign o_s[6]=P0[6]^G6[5]; +assign o_s[7]=P0[7]^G6[6]; +assign o_s[8]=P0[8]^G6[7]; +assign o_s[9]=P0[9]^G6[8]; +assign o_s[10]=P0[10]^G6[9]; +assign o_s[11]=P0[11]^G6[10]; +assign o_s[12]=P0[12]^G6[11]; +assign o_s[13]=P0[13]^G6[12]; +assign o_s[14]=P0[14]^G6[13]; +assign o_s[15]=P0[15]^G6[14]; +assign o_s[16]=P0[16]^G6[15]; +assign o_s[17]=P0[17]^G6[16]; +assign o_s[18]=P0[18]^G6[17]; +assign o_s[19]=P0[19]^G6[18]; +assign o_s[20]=P0[20]^G6[19]; +assign o_s[21]=P0[21]^G6[20]; +assign o_s[22]=P0[22]^G6[21]; +assign o_s[23]=P0[23]^G6[22]; +assign o_s[24]=P0[24]^G6[23]; +assign o_s[25]=P0[25]^G6[24]; +assign o_s[26]=P0[26]^G6[25]; +assign o_s[27]=P0[27]^G6[26]; +assign o_s[28]=P0[28]^G6[27]; +assign o_s[29]=P0[29]^G6[28]; +assign o_s[30]=P0[30]^G6[29]; +assign o_s[31]=P0[31]^G6[30]; +assign o_c=G6[31]; + +endmodule \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v new file mode 100644 index 000000000..086156ddd --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v @@ -0,0 +1,434 @@ +/* PID controller + +sigma=Ki*e(n)+sigma +u(n)=(Kp+Kd)*e(n)+sigma+Kd*(-e(n-1)) + +Data width of Wishbone slave port can be can be toggled between 64-bit, 32-bit and 16-bit. +Address width of Wishbone slave port can be can be modified by changing parameter adr_wb_nb. + +Wishbone compliant +Work as Wishbone slave, support Classic standard SINGLE/BLOCK READ/WRITE Cycle + +registers or wires +[15:0]kp,ki,kd,sp,pv; can be both read and written +[15:0]kpd; read only +[15:0]err[0:1]; read only +[15:0]mr,md; not accessable +[31:0]p,b; not accessable +[31:0]un,sigma; read only +RS write 0 to RS will reset err[0], OF, un and sigma + + + +[4:0]of; overflow register, read only through Wishbone interface, address: 0x40 +of[0]==1 : kpd overflow +of[1]==1 : err[0] overflow +of[2]==1 : err[1] overflow +of[3]==1 : un overflow +of[4]==1 : sigma overflow +[0:15]rl; read lock, when asserted corelated reagister can not be read through Wishbone interface +[0:7]wl; write lock, when asserted corelated reagister can not be written through Wishbone interface + + + +*/ + +`include "PID_defines.v" + +module PID #( +`ifdef wb_16bit +parameter wb_nb=16, +`endif +`ifdef wb_32bit +parameter wb_nb=32, +`endif +`ifdef wb_64bit +parameter wb_nb=64, +`endif + adr_wb_nb=16, + kp_adr = 0, + ki_adr = 1, + kd_adr = 2, + sp_adr = 3, + pv_adr = 4, + kpd_adr = 5, + err_0_adr = 6, + err_1_adr = 7, + un_adr = 8, + sigma_adr = 9, + of_adr = 10, + RS_adr = 11 +)( +input i_clk, +input i_rst, //reset when high +//Wishbone Slave port +input i_wb_cyc, +input i_wb_stb, +input i_wb_we, +input [adr_wb_nb-1:0]i_wb_adr, +input [wb_nb-1:0]i_wb_data, +output o_wb_ack, +output [wb_nb-1:0]o_wb_data, + +//u(n) output +output [31:0]o_un, +output o_valid +); + + + +reg [15:0]kp,ki,kd,sp,pv; +reg wla,wlb; // write locks +wire wlRS; +assign wlRS=wla|wlb; +wire [0:7]wl={{3{wla}},{2{wlb}},3'h0}; + +reg wack; //write acknowledged + +wire [2:0]adr; // address for write +`ifdef wb_16bit +assign adr=i_wb_adr[3:1]; +`endif +`ifdef wb_32bit +assign adr=i_wb_adr[4:2]; +`endif +`ifdef wb_64bit +assign adr=i_wb_adr[5:3]; +`endif + +wire [3:0]adr_1; // address for read +`ifdef wb_32bit +assign adr_1=i_wb_adr[5:2]; +`endif +`ifdef wb_16bit +assign adr_1=i_wb_adr[4:1]; +`endif +`ifdef wb_64bit +assign adr_1=i_wb_adr[6:3]; +`endif + + +wire we; // write enable +assign we=i_wb_cyc&i_wb_we&i_wb_stb; +wire re; //read enable +assign re=i_wb_cyc&(~i_wb_we)&i_wb_stb; + +reg state_0; //state machine No.1's state register + +wire adr_check_1; // A '1' means address is within the range of adr_1 +`ifdef wb_32bit +assign adr_check_1=i_wb_adr[adr_wb_nb-1:6]==0; +`endif +`ifdef wb_16bit +assign adr_check_1=i_wb_adr[adr_wb_nb-1:5]==0; +`endif +`ifdef wb_64bit +assign adr_check_1=i_wb_adr[adr_wb_nb-1:7]==0; +`endif + +wire adr_check; // A '1' means address is within the range of adr +`ifdef wb_16bit +assign adr_check=i_wb_adr[4]==0&&adr_check_1; +`endif +`ifdef wb_32bit +assign adr_check=i_wb_adr[5]==0&&adr_check_1; +`endif +`ifdef wb_64bit +assign adr_check=i_wb_adr[6]==0&&adr_check_1; +`endif + + //state machine No.1 +reg RS; +always@(posedge i_clk or posedge i_rst) + if(i_rst)begin + state_0<=0; + wack<=0; + kp<=0; + ki<=0; + kd<=0; + sp<=0; + pv<=0; + RS<=0; + end + else begin + if(wack&&(!i_wb_stb)) wack<=0; + if(RS)RS<=0; + case(state_0) + 0: begin + if(we&&(!wack)) state_0<=1; + end + 1: begin + if(adr_check)begin + if(!wl[adr])begin + wack<=1; + state_0<=0; + case(adr) + 0: begin + kp<=i_wb_data[15:0]; + end + 1: begin + ki<=i_wb_data[15:0]; + end + 2: begin + kd<=i_wb_data[15:0]; + end + 3: begin + sp<=i_wb_data[15:0]; + end + 4: begin + pv<=i_wb_data[15:0]; + end + endcase + + end + end + else if((adr_1==RS_adr)&&(!wlRS)&&(i_wb_data==0))begin + wack<=1; + state_0<=0; + RS<=1; + end + else begin + wack<=1; + state_0<=0; + end + end + endcase + end + + + //state machine No.2 +reg [9:0]state_1; + +wire update_kpd; +assign update_kpd=wack&&(~adr[2])&&(~adr[0])&&adr_check; //adr==0||adr==2 + +wire update_esu; //update e(n), sigma and u(n) +assign update_esu=wack&&(adr==4)&&adr_check; + +reg rla; // read locks +reg rlb; + + +reg [4:0]of; +reg [15:0]kpd; +reg [15:0]err[0:1]; + +wire [15:0]mr,md; + +reg [31:0]p; +reg [31:0]a,sigma,un; + +reg cout; +wire cin; +wire [31:0]sum; +wire [31:0]product; + +reg start; //start signal for multiplier + +reg [1:0]mr_index; +reg [1:0]md_index; +assign mr= mr_index==1?kpd: + mr_index==2?kd:ki; +assign md= md_index==2?err[1]: + md_index==1?err[0]:sum[15:0]; + + +wire of_addition[0:1]; +assign of_addition[0]=(p[15]&&a[15]&&(!sum[15]))||((!p[15])&&(!a[15])&&sum[15]); +assign of_addition[1]=(p[31]&&a[31]&&(!sum[31]))||((!p[31])&&(!a[31])&&sum[31]); + +always@(posedge i_clk or posedge i_rst) + if(i_rst)begin + state_1<=12'b000000000001; + wla<=0; + wlb<=0; + rla<=0; + rlb<=0; + of<=0; + kpd<=0; + err[0]<=0; + err[1]<=0; + p<=0; + a<=0; + sigma<=0; + un<=0; + start<=0; + mr_index<=0; + md_index<=0; + cout<=0; + end + else begin + case(state_1) + 10'b0000000001: begin + if(update_kpd)begin + state_1<=10'b0000000010; + wla<=1; + rla<=1; + end + else if(update_esu)begin + state_1<=10'b0000001000; + wla<=1; + wlb<=1; + rlb<=1; + end + else if(RS)begin //start a new sequance of U(n) + un<=0; + sigma<=0; + of<=0; + err[0]<=0; + end + end + 10'b0000000010: begin + p<={{16{kp[15]}},kp}; + a<={{16{kd[15]}},kd}; + state_1<=10'b0000000100; + end + 10'b0000000100: begin + kpd<=sum[15:0]; + wla<=0; + rla<=0; + of[0]<=of_addition[0]; + state_1<=10'b0000000001; + end + 10'b0000001000: begin + p<={{16{sp[15]}},sp}; + a<={{16{~pv[15]}},~pv}; + cout<=1; + start<=1; // start calculate err0 * ki + state_1<=10'b0000010000; + end + 10'b0000010000: begin + err[0]<=sum[15:0]; + of[1]<=of_addition[0]; + of[2]<=of[1]; + p<={{16{~err[0][15]}},~err[0]}; + a<={31'b0,1'b1}; + cout<=0; + mr_index<=1; // start calculate err0 * kpd + md_index<=1; + state_1<=10'b0000100000; + end + 10'b0000100000: begin + err[1]<=sum[15:0]; + mr_index<=2; // start calculate err1 * kd + md_index<=2; + state_1<=10'b0001000000; + end + 10'b0001000000: begin + mr_index<=0; + md_index<=0; + start<=0; + p<=product; // start calculate err0*ki + sigma_last + a<=sigma; + state_1<=10'b0010000000; + end + 10'b0010000000: begin + a<=sum; // start calculate err0*kpd + sigma_recent + sigma<=sum; + of[3]<=of[4]|of_addition[1]; + of[4]<=of[4]|of_addition[1]; + p<=product; + state_1<=10'b0100000000; + end + 10'b0100000000: begin + a<=sum; // start calculate err0*kpd + sigma_recent+err1*kd + of[3]<=of[3]|of_addition[1]; + p<=product; + state_1<=10'b1000000000; + end + 10'b1000000000: begin + un<=sum; + of[3]<=of[3]|of_addition[1]; + state_1<=10'b0000000001; + wla<=0; + wlb<=0; + rlb<=0; + end + endcase + end + + +wire ready; +multiplier_16x16bit_pipelined multiplier_16x16bit_pipelined( +i_clk, +~i_rst, +start, +md, +mr, +product, +ready +); + +adder_32bit adder_32bit_0( +a, +p, +cout, +sum, +cin +); + + +wire [wb_nb-1:0]rdata[0:15]; //wishbone read data array +`ifdef wb_16bit +assign rdata[0]=kp; +assign rdata[1]=ki; +assign rdata[2]=kd; +assign rdata[3]=sp; +assign rdata[4]=pv; +assign rdata[5]=kpd; +assign rdata[6]=err[0]; +assign rdata[7]=err[1]; +assign rdata[8]=un[15:0]; +assign rdata[9]=sigma[15:0]; +assign rdata[10]={11'b0,of}; +`endif + +`ifdef wb_32bit +assign rdata[0]={{16{kp[15]}},kp}; +assign rdata[1]={{16{ki[15]}},ki}; +assign rdata[2]={{16{kd[15]}},kd}; +assign rdata[3]={{16{sp[15]}},sp}; +assign rdata[4]={{16{pv[15]}},pv}; +assign rdata[5]={{16{kpd[15]}},kpd}; +assign rdata[6]={{16{err[0][15]}},err[0]}; +assign rdata[7]={{16{err[1][15]}},err[1]}; +assign rdata[8]=un; +assign rdata[9]=sigma; +assign rdata[10]={27'b0,of}; +`endif + +`ifdef wb_64bit +assign rdata[0]={{48{kp[15]}},kp}; +assign rdata[1]={{48{ki[15]}},ki}; +assign rdata[2]={{48{kd[15]}},kd}; +assign rdata[3]={{48{sp[15]}},sp}; +assign rdata[4]={{48{pv[15]}},pv}; +assign rdata[5]={{48{kpd[15]}},kpd}; +assign rdata[6]={{48{err[0][15]}},err[0]}; +assign rdata[7]={{48{err[1][15]}},err[1]}; +assign rdata[8]={{32{un[31]}},un}; +assign rdata[9]={{32{sigma[31]}},sigma}; +assign rdata[10]={59'b0,of}; +`endif + +assign rdata[11]=0; +assign rdata[12]=0; +assign rdata[13]=0; +assign rdata[14]=0; +assign rdata[15]=0; + + +wire [0:15]rl; +assign rl={5'b0,rla,{4{rlb}},rla|rlb,5'b0}; + +wire rack; // wishbone read acknowledged +assign rack=(re&adr_check_1&(~rl[adr_1]))|(re&(~adr_check_1)); + +assign o_wb_ack=(wack|rack)&i_wb_stb; + +assign o_wb_data=adr_check_1?rdata[adr_1]:0; +assign o_un=un; +assign o_valid=~rlb; + + +endmodule \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v new file mode 100644 index 000000000..a43f6b38d --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v @@ -0,0 +1,8 @@ +//`define wb_16bit +`define wb_32bit +//`define wb_64bit + + +//`define PID_test + +//`define PID_direct_test \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v new file mode 100644 index 000000000..f33b3d80e --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v @@ -0,0 +1,37 @@ +/*Booth Encoder +Author: Zhu Xu +Email: m99a1@yahoo.cn +*/ +module booth_radix4( +input [2:0]codes, +output zero, +output double, +output negation +); + +wire A; +assign A=codes[2]; +wire B; +assign B=codes[1]; +wire C; +assign C=codes[0]; +wire nB,nC,nA; +assign nB=~B; +assign nC=~C; +assign nA=~A; + +wire BC; +assign BC=B&C; +wire nBnC; +assign nBnC=nB&nC; +wire nBanC; +assign nBanC=nB|nC; + +assign double=(nBnC&A)|(BC&nA); +assign negation=A&nBanC; +assign zero=(A&BC)|(nA&nBnC); + + + + +endmodule \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v new file mode 100644 index 000000000..ff94461cd --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v @@ -0,0 +1,207 @@ +//================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// ------------------------------------------------------------------ +// Copyright (c) 2014 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code for use +// in synthesis for any Lattice programmable logic product. Other +// use of this code, including the selling or duplication of any +// portion is strictly prohibited. + +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// + + +module delay_gen_ihd_ipd_isd( + input clk, + input rst, + input start_stop, + input [15:0] isd_val, + input [15:0] ipd_val, + input config_reg_done, + input symbol_shift_done, + input packet_shift_done, + input hop_shift_done, + output reg isd_delay_en, + output reg ipd_delay_en +); + +reg [15:0] isd_val_temp; +reg [15:0] ipd_val_temp; +reg [15:0] isd_count; +reg [15:0] ipd_count; +wire [20:0] max_count; +wire [20:0] max_count_pkt /* synthesis syn_multstyle = logic */; +reg clk_count,clk_count_pkt; +reg count_done,count_done_pkt; + +parameter const_fact=20; +assign max_count=isd_val_temp * const_fact; +assign max_count_pkt=ipd_val_temp * const_fact; + +//wire count_enable,count_enable_pkt; +reg count_enable,count_enable_pkt; +//wire config_done; +//assign config_done= !rst_n ? 0 : config_reg_done ? 1 : config_done; //orignal +//assign count_enable= rst ? 0 : count_done ? 0 : symbol_shift_done ? 1 : count_enable; //orignal +//assign count_enable_pkt= rst ? 0 : count_done_pkt ? 0 : (packet_shift_done || hop_shift_done) ? 1 : count_enable_pkt; + +//assign isd_delay_en=symbol_shift_done ? 1 : (isd_count==max_count-1) : + +///////**********modified 11/feb/2014*************** ///////// + always @(posedge clk or posedge rst) begin + if(rst || !start_stop) begin + count_enable=0; + end + else begin + if(count_done) + count_enable=0; + else if(symbol_shift_done) + count_enable=1; + else + count_enable=count_enable; + + end +end + +always @(posedge clk or posedge rst) begin + if(rst || !start_stop) begin + count_enable_pkt=0; + end + else begin + if(count_done_pkt) + count_enable_pkt=0; + else if(packet_shift_done || hop_shift_done) + count_enable_pkt=1; + else + count_enable_pkt=count_enable_pkt; + end +end + +/////////////////******************************////////// + + + + +///////////////////////symbol//////////////////////////////////// +always @(posedge clk or posedge rst) begin + if(rst || !start_stop) begin + isd_count<=0; + count_done<=0; + isd_delay_en<=0; + end + else begin + count_done<=0; + if(count_enable) begin + if(isd_count==max_count) begin + isd_count<=0; + count_done<=1; + isd_delay_en<=0; + end + else begin + isd_delay_en<=1; + isd_count<=isd_count+1; + end + end + else begin + isd_delay_en<=0; + isd_count<=0; + end + end +end + +always @(posedge clk or posedge rst) begin + if(rst || !start_stop) begin + isd_val_temp<=0; + clk_count<=0; + end + else begin + if(!config_reg_done) begin + isd_val_temp<=isd_val; + clk_count<=0; + end + else if(config_reg_done) begin + clk_count<=clk_count+1; + isd_val_temp<=isd_val; + end + else begin + isd_val_temp<=isd_val_temp; + end + end +end +///////////////packet////////////////////// +always @(posedge clk or posedge rst) begin + if(rst || !start_stop) begin + ipd_count<=0; + count_done_pkt<=0; + ipd_delay_en<=0; + end + else begin + count_done_pkt<=0; + if(count_enable_pkt) begin + if(ipd_count==max_count_pkt) begin + ipd_count<=0; + count_done_pkt<=1; + ipd_delay_en<=0; + end + else begin + ipd_delay_en<=1; + ipd_count<=ipd_count+1; + end + end + else begin + ipd_delay_en<=0; + ipd_count<=0; + end + end +end + +always @(posedge clk or posedge rst) begin + if(rst || !start_stop) begin + ipd_val_temp<=0; + clk_count_pkt<=0; + end +else begin + if(!config_reg_done) begin + ipd_val_temp<=ipd_val; + clk_count_pkt<=0; + end + else if(config_reg_done) begin + clk_count_pkt<=clk_count_pkt+1; + ipd_val_temp<=ipd_val; + end + else begin // if(!config_reg_done) begin + ipd_val_temp<=ipd_val_temp; + end + end +end + +endmodule diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v new file mode 100644 index 000000000..a1ccc5fdc --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v @@ -0,0 +1,369 @@ +//================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// ------------------------------------------------------------------ +// Copyright (c) 2014 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code for use +// in synthesis for any Lattice programmable logic product. Other +// use of this code, including the selling or duplication of any +// portion is strictly prohibited. + +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// + + + +/*********************************************************************** + * * + * EFB REGISTER SET * + * * + ***********************************************************************/ + + +`define MICO_EFB_I2C_CR 8'h08 +`define MICO_EFB_I2C_CMDR 8'h09 +`define MICO_EFB_I2C_BLOR 8'h0a +`define MICO_EFB_I2C_BHIR 8'h0b +`define MICO_EFB_I2C_TXDR 8'h0d +`define MICO_EFB_I2C_SR 8'h0c +`define MICO_EFB_I2C_GCDR 8'h0f +`define MICO_EFB_I2C_RXDR 8'h0e +`define MICO_EFB_I2C_IRQSR 8'h06 +`define MICO_EFB_I2C_IRQENR 8'h09 + +/*********************************************************************** + * * + * EFB I2C CONTROLLER PHYSICAL DEVICE SPECIFIC INFORMATION * + * * + ***********************************************************************/ + + + +// Control Register Bit Masks +`define MICO_EFB_I2C_CR_I2CEN 8'h80 +`define MICO_EFB_I2C_CR_GCEN 8'h40 +`define MICO_EFB_I2C_CR_WKUPEN 8'h20 +// Status Register Bit Masks +`define MICO_EFB_I2C_SR_TIP 8'h80 +`define MICO_EFB_I2C_SR_BUSY 8'h40 +`define MICO_EFB_I2C_SR_RARC 8'h20 +`define MICO_EFB_I2C_SR_SRW 8'h10 +`define MICO_EFB_I2C_SR_ARBL 8'h08 +`define MICO_EFB_I2C_SR_TRRDY 8'h04 +`define MICO_EFB_I2C_SR_TROE 8'h02 +`define MICO_EFB_I2C_SR_HGC 8'h01 +// Command Register Bit Masks +`define MICO_EFB_I2C_CMDR_STA 8'h80 +`define MICO_EFB_I2C_CMDR_STO 8'h40 +`define MICO_EFB_I2C_CMDR_RD 8'h20 +`define MICO_EFB_I2C_CMDR_WR 8'h10 +`define MICO_EFB_I2C_CMDR_NACK 8'h08 +`define MICO_EFB_I2C_CMDR_CKSDIS 8'h04 + + +/*********************************************************************** + * * + * CODE SPECIFIC * + * * + ***********************************************************************/ + + `define ALL_ZERO 8'h00 + `define READ 1'b0 + `define READ 1'b0 + `define HIGH 1'b1 + `define WRITE 1'b1 + `define LOW 1'b0 + `define READ_STATUS 1'b0 + `define READ_DATA 1'b0 + +/*********************************************************************** + * * + * State Machine Variables * + * * + ***********************************************************************/ + +`define state0 8'd00 +`define state1 8'd01 +`define state2 8'd02 +`define state3 8'd03 +`define state4 8'd04 +`define state5 8'd05 +`define state6 8'd06 +`define state7 8'd07 +`define state8 8'd08 +`define state9 8'd09 +`define state10 8'd10 +`define state11 8'd11 +`define state12 8'd12 +`define state13 8'd13 +`define state14 8'd14 +`define state15 8'd15 +`define state16 8'd16 +`define state17 8'd17 +`define state18 8'd18 +`define state19 8'd19 +`define state20 8'd20 +`define state21 8'd21 +`define state22 8'd22 +`define state23 8'd23 +`define state24 8'd24 +`define state25 8'd25 +`define state26 8'd26 +`define state27 8'd27 +`define state28 8'd28 +`define state29 8'd29 +`define state30 8'd30 +`define state31 8'd31 +`define state32 8'd32 +`define state33 8'd33 +`define state34 8'd34 +`define state35 8'd35 +`define state36 8'd36 +`define state37 8'd37 +`define state38 8'd38 +`define state39 8'd39 +`define state40 8'd40 +`define state41 8'd41 +`define state42 8'd42 +`define state43 8'd43 +`define state44 8'd44 +`define state45 8'd45 +`define state46 8'd46 +`define state47 8'd47 +`define state48 8'd48 +`define state49 8'd49 +`define state50 8'd50 +`define state51 8'd51 +`define state52 8'd52 +`define state53 8'd53 +`define state54 8'd54 +`define state55 8'd55 +`define state56 8'd56 +`define state57 8'd57 +`define state58 8'd58 +`define state59 8'd59 +`define state60 8'd60 +`define state61 8'd61 +`define state62 8'd62 +`define state63 8'd63 +`define state64 8'd64 +`define state65 8'd65 +`define state66 8'd66 +`define state67 8'd67 +`define state68 8'd68 +`define state69 8'd69 +`define state70 8'd70 +`define state71 8'd71 +`define state72 8'd72 +`define state73 8'd73 +`define state74 8'd74 +`define state75 8'd75 +`define state76 8'd76 +`define state77 8'd77 +`define state78 8'd78 +`define state79 8'd79 +`define state80 8'd80 +`define state81 8'd81 +`define state82 8'd82 +`define state83 8'd83 +`define state84 8'd84 +`define state85 8'd85 +`define state86 8'd86 +`define state87 8'd87 +`define state88 8'd88 +`define state89 8'd89 +`define state90 8'd90 +`define state91 8'd91 +`define state92 8'd92 +`define state93 8'd93 +`define state94 8'd94 +`define state95 8'd95 +`define state96 8'd96 +`define state97 8'd97 +`define state98 8'd98 +`define state99 8'd99 +`define state100 8'd100 +`define state101 8'd101 +`define state102 8'd102 +`define state103 8'd103 +`define state104 8'd104 +`define state105 8'd105 +`define state106 8'd106 +`define state107 8'd107 +`define state108 8'd108 +`define state109 8'd109 +`define state110 8'd110 +`define state111 8'd111 +`define state112 8'd112 +`define state113 8'd113 +`define state114 8'd114 +`define state115 8'd115 +`define state116 8'd116 +`define state117 8'd117 +`define state118 8'd118 +`define state119 8'd119 +`define state120 8'd120 +`define state121 8'd121 +`define state122 8'd122 +`define state123 8'd123 +`define state124 8'd124 +`define state125 8'd125 +`define state126 8'd126 +`define state127 8'd127 +`define state128 8'd128 +`define state129 8'd129 +`define state130 8'd130 +`define state131 8'd131 +`define state132 8'd132 +`define state133 8'd133 +`define state134 8'd134 +`define state135 8'd135 +`define state136 8'd136 +`define state137 8'd137 +`define state138 8'd138 +`define state139 8'd139 +`define state140 8'd140 +`define state141 8'd141 +`define state142 8'd142 +`define state143 8'd143 +`define state144 8'd144 +`define state145 8'd145 +`define state146 8'd146 +`define state147 8'd147 +`define state148 8'd148 +`define state149 8'd149 +`define state150 8'd150 +`define state151 8'd151 +`define state152 8'd152 +`define state153 8'd153 +`define state154 8'd154 +`define state155 8'd155 +`define state156 8'd156 +`define state157 8'd157 +`define state158 8'd158 +`define state159 8'd159 +`define state160 8'd160 +`define state161 8'd161 +`define state162 8'd162 +`define state163 8'd163 +`define state164 8'd164 +`define state165 8'd165 +`define state166 8'd166 +`define state167 8'd167 +`define state168 8'd168 +`define state169 8'd169 +`define state170 8'd170 +`define state171 8'd171 +`define state172 8'd172 +`define state173 8'd173 +`define state174 8'd174 +`define state175 8'd175 +`define state176 8'd176 +`define state177 8'd177 +`define state178 8'd178 +`define state179 8'd179 +`define state180 8'd180 +`define state181 8'd181 +`define state182 8'd182 +`define state183 8'd183 +`define state184 8'd184 +`define state185 8'd185 +`define state186 8'd186 +`define state187 8'd187 +`define state188 8'd188 +`define state189 8'd189 +`define state190 8'd190 +`define state191 8'd191 +`define state192 8'd192 +`define state193 8'd193 +`define state194 8'd194 +`define state195 8'd195 +`define state196 8'd196 +`define state197 8'd197 +`define state198 8'd198 +`define state199 8'd199 +`define state200 8'd200 +`define state201 8'd201 +`define state202 8'd202 +`define state203 8'd203 +`define state204 8'd204 +`define state205 8'd205 +`define state206 8'd206 +`define state207 8'd207 +`define state208 8'd208 +`define state209 8'd209 +`define state210 8'd210 +`define state211 8'd211 +`define state212 8'd212 +`define state213 8'd213 +`define state214 8'd214 +`define state215 8'd215 +`define state216 8'd216 +`define state217 8'd217 +`define state218 8'd218 +`define state219 8'd219 +`define state220 8'd220 +`define state221 8'd221 +`define state222 8'd222 +`define state223 8'd223 +`define state224 8'd224 +`define state225 8'd225 +`define state226 8'd226 +`define state227 8'd227 +`define state228 8'd228 +`define state229 8'd229 +`define state230 8'd230 +`define state231 8'd231 +`define state232 8'd232 +`define state233 8'd233 +`define state234 8'd234 +`define state235 8'd235 +`define state236 8'd236 +`define state237 8'd237 +`define state238 8'd238 +`define state239 8'd239 +`define state240 8'd240 +`define state241 8'd241 +`define state242 8'd242 +`define state243 8'd243 +`define state244 8'd244 +`define state245 8'd245 +`define state246 8'd246 +`define state247 8'd247 +`define state248 8'd248 +`define state249 8'd249 +`define state250 8'd250 +`define state251 8'd251 +`define state252 8'd252 +`define state253 8'd253 +`define state254 8'd254 +`define state255 8'd255 + diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v new file mode 100644 index 000000000..e1aac59ec --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v @@ -0,0 +1,649 @@ +//================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// ------------------------------------------------------------------ +// Copyright (c) 2014 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code for use +// in synthesis for any Lattice programmable logic product. Other +// use of this code, including the selling or duplication of any +// portion is strictly prohibited. + +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// + +`include "i2c_defines.v" +`include "i2c_new_reg.v" +`timescale 1 ns / 1 ns + + +module serialInterface (/*AUTOARG*/ + // Outputs + dataOut, regAddr, sdaOut, writeEn, readEn, i2c_start, + // Inputs + clk, dataIn, rst, scl, sdaIn + ); + input clk; + input [7:0] dataIn; + input rst; + input scl; + input sdaIn; + output [7:0] dataOut; + output [7:0] regAddr; + output sdaOut; + output writeEn; + output readEn; + output i2c_start; + + // I2C_SLAVE_INIT_ADDR: Upper Bits <9:2> can be changed. Lower bits <1:0> are fixed. + // For I2C Hard IP located in Upper Left <1:0> must be set to "01". + // For I2C Hard IP located in Upper Right <1:0> must be set to "10". + parameter I2C_SLAVE_INIT_ADDR = "0b1111100001"; //Upper Left + //parameter I2C_SLAVE_INIT_ADDR = "0b1111100010"; //Upper Right + + // BUS_ADDR74: Fixed value. SBADRI [7:4] bits also should match with this value to + // activate the IP. + // For I2C Hard IP located in Upper Left [7:4] must be set to "0001". + // For I2C Hard IP located in Upper Right [7:4] must be set to "0011". + parameter BUS_ADDR74_STRING = "0b0001"; //Upper Left + //parameter BUS_ADDR74_STRING = "0b0011"; //Upper Right + + // These are for the "OR" function with "wb_adr_i". Note that bits [7:4] are copies + // of BUS_ADDR74_STRING. + parameter BUS_ADDR74 = 8'b0001_0000; //Upper Left + //parameter BUS_ADDR74 = 8'b0011_0000; //Upper Right + + reg [7:0] regAddr; + reg writeEn; + wire [7:0] dataOut; + reg i2c_start; + + /* + * System bus interface signals + */ + reg [7:0] wb_dat_i; + reg wb_stb_i; + reg [7:0] wb_adr_i; + reg wb_we_i; + wire [7:0] wb_dat_o; + wire wb_ack_o; + /* + * Data Read and Write Register + */ + reg [7:0] temp0; + reg [7:0] temp1; + reg [7:0] temp2; + reg [7:0] temp3; + reg [7:0] n_temp0; + reg [7:0] n_temp1; + reg [7:0] n_temp2; + reg [7:0] n_temp3; + reg readEn; + + + /* + * i2c Module Instanitiation + */ + + + i2c UUT1 ( + .wb_clk_i (clk), + .wb_dat_i (wb_dat_i), + .wb_stb_i (wb_stb_i), + .wb_adr_i (wb_adr_i | BUS_ADDR74), + .wb_we_i (wb_we_i), + .wb_dat_o (wb_dat_o), + .wb_ack_o (wb_ack_o), + .i2c_irqo ( ), + .i2c_scl (scl), + .i2c_sda (sdaOut), + .i2c_sda_in (sdaIn), + .rst_i(rst) + ); + + defparam UUT1.I2C_SLAVE_INIT_ADDR = I2C_SLAVE_INIT_ADDR; + defparam UUT1.BUS_ADDR74_STRING = BUS_ADDR74_STRING; + + /* + * Signal & wire Declartion + */ + reg efb_flag; + reg n_efb_flag; + reg [7:0] n_wb_dat_i; + reg n_wb_stb_i; + reg [7:0] n_wb_adr_i; + reg n_wb_we_i; + reg [7:0] c_state; + reg [7:0] n_state; + reg n_count_en; + reg count_en; + wire invalid_command = 0; + + /* + * Output generation + */ + + assign dataOut = temp3; + + always @(posedge clk or posedge rst)begin + if (rst)begin + writeEn <= 0; + readEn <= 0; + end else begin + if(c_state == `state14)begin + writeEn <= 1'b1; + end else begin + writeEn <= 1'b0; + end + + if(c_state == `state15)begin + readEn <= 1'b1; + end else if (c_state == `state13) begin //** + if (n_temp2 & (`MICO_EFB_I2C_SR_SRW)) begin + readEn <= 1'b1; + end else begin + readEn <= 1'b0; + end + end else begin + readEn <= 1'b0; + end + end + end + + always @(posedge clk or posedge rst)begin + if (rst)begin + regAddr <= 0; + end else begin + if(c_state == `state2)begin + regAddr <= 8'd0; + end else if(c_state == `state9)begin + regAddr <= temp1; + //end else if(writeEn || readEn)begin + // regAddr <= regAddr + 1; + end + end + end + + //slave start detect + always @(posedge clk or posedge rst) begin + if (rst) begin + i2c_start <= 0; + end else begin + if (c_state == `state12) begin + i2c_start <= 0; + end else if (c_state == `state9) begin + i2c_start <= 1; + end + end + end + + /* + * Main state machine + */ + always @ (posedge clk or posedge rst) begin + if(rst) begin + wb_dat_i <= 8'h00; + wb_stb_i <= 1'b0 ; + wb_adr_i <= 8'h00; + wb_we_i <= 1'b0; + end else begin + wb_dat_i <= #1 n_wb_dat_i; + wb_stb_i <= #1 n_wb_stb_i; + wb_adr_i <= #1 n_wb_adr_i; + wb_we_i <= #1 n_wb_we_i ; + end + end + + always @ (posedge clk or posedge rst) begin + if(rst) begin + c_state <= 10'h000; + efb_flag <= 1'b0 ; + count_en <= 1'b0; + end else begin + c_state <= n_state ; + efb_flag <= n_efb_flag; + count_en <= n_count_en; + end + end + + always @ (posedge clk or posedge rst) begin + if(rst) begin + temp0 <= 8'h00 ; + temp1 <= 8'h00 ; + temp2 <= 8'h00 ; + temp3 <= 8'h00 ; + end else begin + temp0 <= n_temp0 ; + temp1 <= n_temp1 ; + temp2 <= n_temp2 ; + temp3 <= n_temp3 ; + end + end + + always @(posedge clk or posedge rst) begin + if (rst) begin + n_temp2 <= 0; + end else begin + n_temp2 <= wb_dat_o; //** + end + end + + /* + * FSM combinational block + */ + always @ ( * ) begin + n_efb_flag = 1'b0 ; + n_state = c_state ; + n_wb_dat_i = 8'h00; + n_wb_stb_i = 1'b0 ; + n_wb_adr_i = 8'h00; + n_wb_we_i = 1'b0; + n_count_en = 1'b0; + n_temp0 = temp0; + n_temp1 = temp1; + n_temp3 = temp3; + + case(c_state) + `state0: begin + n_wb_dat_i = 8'h00; + n_wb_stb_i = 1'b0 ; + n_wb_adr_i = 8'h00; + n_wb_we_i = 1'b0; + n_wb_stb_i = 1'b0 ; + n_state = `state1 ; + end + + `state1: begin // Enable I2C Interface + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + n_state = `state2; + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `WRITE; + n_wb_adr_i = `MICO_EFB_I2C_CR; + n_wb_dat_i = 8'h80; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state2: begin // Clock Disable + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + n_state = `state3; + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `WRITE; + n_wb_adr_i = `MICO_EFB_I2C_CMDR; + n_wb_dat_i = 8'h04; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state3: begin // Wait for not BUSY + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + if(wb_dat_o & (`MICO_EFB_I2C_SR_BUSY))begin + n_state = `state4; + end else begin + n_state = c_state; + end + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_STATUS; + n_wb_adr_i = `MICO_EFB_I2C_SR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state4: begin // Discard data 1 + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + n_temp0 = wb_dat_o; + n_state = `state5; + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_DATA; + n_wb_adr_i = `MICO_EFB_I2C_RXDR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state5: begin // Discard data 2 + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + n_temp0 = wb_dat_o; + n_state = `state6; + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_DATA; + n_wb_adr_i = `MICO_EFB_I2C_RXDR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state6: begin // Clock Enable + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + n_state = `state7; + end else begin + n_efb_flag = `HIGH; + n_wb_we_i = `WRITE; + n_wb_adr_i = `MICO_EFB_I2C_CMDR; + n_wb_dat_i = 8'h00; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state7: begin // wait for data to come + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + n_temp1 = 8'h00; + if((wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY)))begin + n_state = `state8; // Slave acknowledged + end else if (~wb_dat_o[6])begin + n_state = `state2; // Disable clock + end else begin + n_state = c_state; + end + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_STATUS; + n_wb_adr_i = `MICO_EFB_I2C_SR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state8: begin // Store i2C Command Information + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + n_temp1 = wb_dat_o; + n_state = `state9; + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_DATA; + n_wb_adr_i = `MICO_EFB_I2C_RXDR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state9: begin // Send ACK or NACK Based upon Command Receive & Wait for Stop `state 17 + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + if(invalid_command)begin // This is tied to '0' at present + n_state = `state17; + end else begin + n_state = `state12; + end + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `WRITE; + n_wb_adr_i = `MICO_EFB_I2C_CMDR; + n_wb_dat_i = {4'h0,invalid_command,3'b000}; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state12: begin // Wait for TRRDY Bit + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY))begin + n_state = `state13; + end else if (~wb_dat_o[6])begin + n_state = `state2; + end else begin + n_state = c_state; + end + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_STATUS; + n_wb_adr_i = `MICO_EFB_I2C_SR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state13: begin // Check for read or write operation + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + if(wb_dat_o & (`MICO_EFB_I2C_SR_SRW))begin + n_state = `state15; //Read from slave + end else begin + n_state = `state14; //Write to slave + end + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_STATUS; + n_wb_adr_i = `MICO_EFB_I2C_SR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state14: begin // Write data + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + n_temp3 = wb_dat_o; + n_state = `state19; + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_DATA; + n_wb_adr_i = `MICO_EFB_I2C_RXDR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state15: begin // Send Data to Master + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + n_state = `state18; + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `WRITE; + n_wb_adr_i = `MICO_EFB_I2C_TXDR; + n_wb_dat_i = dataIn; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state17: begin // Wait till Stop is Send + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + if(~wb_dat_o[6])begin + n_state = `state2; + end else begin + n_state = c_state; + end + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_STATUS; + n_wb_adr_i = `MICO_EFB_I2C_SR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + `state18: begin // Wait for TxRDY flag and send data again if required + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY))begin + n_state = `state15; // Send Data + end else if (~wb_dat_o[6]) begin// If Stop go to beginning + n_state = `state2; + end else begin + n_state = c_state; + end + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_STATUS; + n_wb_adr_i = `MICO_EFB_I2C_SR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + + + `state19: begin // Wait for TRRDY bit + if (wb_ack_o && efb_flag) begin + n_wb_dat_i = `ALL_ZERO ; + n_wb_adr_i = `ALL_ZERO ; + n_wb_we_i = `LOW ; + n_wb_stb_i = `LOW ; + n_efb_flag = `LOW ; + n_count_en = `LOW ; + if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY)) begin + n_state = `state14; + end else if (~wb_dat_o[6])begin + n_state = `state2; + end else begin + n_state = c_state; + end + end else begin + n_efb_flag = `HIGH ; + n_wb_we_i = `READ_STATUS; + n_wb_adr_i = `MICO_EFB_I2C_SR; + n_wb_dat_i = 0 ; + n_wb_stb_i = `HIGH ; + n_state = c_state; + end + end + endcase + end + + +endmodule diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v new file mode 100644 index 000000000..0ca379453 --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v @@ -0,0 +1,203 @@ +//================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// ------------------------------------------------------------------ +// Copyright (c) 2014 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code for use +// in synthesis for any Lattice programmable logic product. Other +// use of this code, including the selling or duplication of any +// portion is strictly prohibited. + +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// + + +module led_driver ( + input sys_clk, + input rst_n, + input txn_start, + input mobeam_start_stop, + input led_polarity, + input [7:0] bar_width, + input [7:0] barcode_array, + output drive_on, + output byte_done, + output bit_done, + output oled + //output dynamic_clk); + ); + + //reg [15:0] clk_count; + + /* + always @(posedge sys_clk or negedge rst_n) + begin + if (~rst_n) + clk_count <= 16'b0; + else + if (clk_count==16'd4) + clk_count<= 0; + else + clk_count <= clk_count + 1'b1; + + end */// always @ (posedge sys_clk or negedge rst_n) + + // assign dynamic_clk = (clk_count==16'd4); + + + reg oled,drive_on; + reg oled_int; + reg [15:0] bw_count; + reg [7:0] ba_reg = 8'b10011001; + reg reload_ba_reg; + reg driver_busy; + + wire [7:0] BW; + reg [15:0] BWx10 /* synthesis syn_multstyle = logic */; + reg [2:0] bit_cnt; + reg byte_done_int; + reg txn_start_d; + /////////////////TXN_Start edge detect///////////////// + + always @(posedge sys_clk or negedge rst_n) + begin + if (~rst_n || !mobeam_start_stop) begin + txn_start_d<= 1'b0; + end + else + txn_start_d<=txn_start; + + end + assign txn_start_pos = txn_start & (~txn_start_d); + + + + +assign BW =bar_width; +//assign byte_done_mod= (&bit_cnt) & reload_ba_reg; +//assign byte_done_mod= (&bit_cnt) && (bw_count==1'b1); +assign byte_done_mod= (BWx10==16'd4)?(&bit_cnt) && (bw_count==1'b1):byte_done_int; +assign byte_done = byte_done_mod; +assign bit_done = reload_ba_reg; + // assign BWx10 = BW * 10 - 1'b1; + + always @(posedge sys_clk or negedge rst_n) + begin + if (~rst_n || !mobeam_start_stop) begin + ba_reg <= 8'd0; + BWx10<=16'd4; + byte_done_int<= 1'b0; + bit_cnt<= 3'd0; + end + else begin + if (BW==0) + BWx10<= 4; + else begin + BWx10 <= BW * 10 - 1'b1; + // BWX5 <= BW * 5 - 1'b1; //for 25% duty cycle + // BWX15 <= + end + + //if (txn_start_pos) begin + if (txn_start && bit_cnt==3'd0) begin + ba_reg <=barcode_array; + end + if (reload_ba_reg) begin + //ba_reg <= {ba_reg[0],ba_reg[7:1]}; //lsb first + ba_reg <= {ba_reg[6:0],ba_reg[7]}; //msb first + if (bit_cnt==3'd7) + byte_done_int<=1'b1; + else + byte_done_int<=1'b0; + + if (&bit_cnt) begin + //byte_done_int<=1'b1; + bit_cnt<= 3'd0; + end + else begin + // byte_done_int<= 1'b0; + bit_cnt<= bit_cnt + 1'b1; + end + + end + else + byte_done_int<= 1'b0; + end + end + + always @(posedge sys_clk or negedge rst_n) + begin + if (~rst_n || !mobeam_start_stop) + begin + oled_int <= 1'b0; + bw_count <= 16'b0; + reload_ba_reg <= 1'b0; + driver_busy<= 1'b0; + + end + else + if (txn_start) begin + // driver_busy<= 1'b1; + if (bw_count == BWx10) + begin + //oled<=ba_reg[0]; //lsb_first + oled_int<=ba_reg[7]; //msb first + bw_count<=16'b0; + reload_ba_reg <= 1'b1; + end + + else begin + oled_int<= oled_int; + bw_count<= bw_count + 1'b1; + reload_ba_reg <= 1'b0; + end + end + else + reload_ba_reg <= 1'b0; + end // always @ (posedge sys_clk or negedge rst_n) + + always @(posedge sys_clk ) begin + if (~rst_n || !mobeam_start_stop) begin + oled<=0; + end else begin + if(led_polarity)begin + oled <= oled_int; + drive_on<=oled_int; + end else begin + oled <= ~oled_int; + drive_on<=~oled_int; + end + end + + end + +endmodule // clk_gen + diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v new file mode 100644 index 000000000..d824cda12 --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v @@ -0,0 +1,1009 @@ +//================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// ------------------------------------------------------------------ +// Copyright (c) 2014 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code for use +// in synthesis for any Lattice programmable logic product. Other +// use of this code, including the selling or duplication of any +// portion is strictly prohibited. + +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// + + +module mobeam_control_fsm( + //`ifndef SIM + input shift_done, + input bit_done, + // `endif + input sys_clk_i, + input rst_mobeam, +// input new_data_rd, +// input data_strobe, + input start_stop, + +// output reg config_reg_done, +// output reg write_to_bsr_buffer, + + //bsr memory signals + input [7:0] bsr_mem_data, + output bsr_mem_clk, + output reg [8:0] bsr_mem_addr, + output reg bsr_mem_rd_en, + + //ba memory signals + input [15:0] ba_mem_data , + output ba_mem_clk, + output reg [7:0] ba_mem_addr, + output reg ba_mem_rd_en, + + //TO LED DRIVER + output [7:0] o_byte_data, + output txn_start, +// output reg bsr_load_done, + output reg [7:0] bsr_bw +); + +`define IDLE_BSR 0 +`define LB_READ 1 +`define LB_READ_LATENCY 2 +`define LP_READ 3 +`define LP_READ_LATENCY 4 +`define BL_READ 5 +`define BL_READ_LATENCY 6 +`define NH_READ 7 +`define NH_READ_LATENCY 8 +`define NR_READ 9 +`define NR_READ_LATENCY 10 + +`define BSR_READ 11 +`define BSR_READ_LATENCY 12 +`define START_HOP 13 +//`define BEAM_START_STOP +//`define BEAM_START_STOP_LATENCY 10 + +`define IDLE_STATE 14 +`define READ_WORD 15 +`define READ_BYTE_LATENCY_1 16 +`define DELAY_STATE 17 +`define SHIFT_WORD 18 + + + +// ============================================================================== +// state assignments & defines +// ============================================================================== +parameter BSR_ADDR_WIDTH = 3 ; +parameter BSR_MEM_DEPTH = 1 << BSR_ADDR_WIDTH ; +///mobeam reg addresses//////////// +//parameter revision_code_addr=8'hEE; //EE +parameter rst_mobeam_addr=8'hF1; //ED +parameter lb_addr=8'hEA; //F0 +parameter lp_addr=8'hEB; //EF +parameter bl_addr=8'hEC; //E9 +parameter nh_addr=8'hED; //EA +parameter nr_addr=8'hEE; //EB +parameter bsr_addr=8'h80; +parameter ba_addr=8'h00; +parameter beam_start_stop_addr=8'hF0; //EC + + + +integer bsr_data_count; +reg rd_done; +reg i,i_2; + +reg [7:0] o_lb_data; +reg [7:0] o_lp_data; +reg [7:0] o_nh_data; +reg [7:0] o_nr_data; +reg [7:0] o_bl_data; +reg [7:0] o_bsr_data; +reg [4:0] ba_state; +reg [4:0] bsr_state; +reg [7:0] bsr_buffer [0:6]; +reg config_reg_done; +//reg write_to_bsr_buffer; + + +//reg start_stop; //from mobeam reg set +//wire shift_done; //from led control logic + + + + +//////////////////////////BA FSM//////////////////////////////////////////////// + + assign ba_mem_clk=sys_clk_i; + reg [7:0] byte_data; + wire bl_done; + reg [1:0]check_shift_done_count_d; + + always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam || !start_stop) begin + //check_clk_1=0; + //check_clk_2=0; + byte_data <= 8'd0; + check_shift_done_count_d<=0; + end + else begin + check_shift_done_count_d<=check_shift_done_count; + // if(ba_state!=`IDLE_STATE) begin + + if(check_shift_done_count_d==2'b01) begin + //if(check_clk_1==1) begin + byte_data<=ba_mem_data[15:8]; + //check_clk_1=0; + //end + //else + //check_clk_1=1; + end + else if(check_shift_done_count_d==2'b00) begin + //if(check_clk_2==1) begin + byte_data<=ba_mem_data[7:0]; + //check_clk_2=0; + //end + //else + //check_clk_2=1; + end + else + byte_data<=byte_data; + end + end + + + + + ////*****count shift_done's***************//// + + reg [1:0] check_shift_done_count; + reg clk_count_2,clk_count_3; + + always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam || !start_stop) begin + clk_count_2<=0; + clk_count_3<=0; + check_shift_done_count<=2'b00; + end + else begin + if(/*tx_out_en_high_dtc*/symbol_shift_done) + check_shift_done_count<=0; + else if(shift_done) begin + // if(clk_count_2==1) begin + // clk_count_2<=0; + check_shift_done_count<=check_shift_done_count + 1; + // end + // else begin + // check_shift_done_count<=check_shift_done_count; + // end + // clk_count_2<=clk_count_2 + 1; + end + else if(check_shift_done_count==2'b10) begin + // if(clk_count_3==1) begin + check_shift_done_count<=0; + // clk_count_3<=0; + // end + // else begin + // check_shift_done_count<=check_shift_done_count; + // end + // clk_count_3<=clk_count_3+1; + end + else + check_shift_done_count<=check_shift_done_count; + end + end + + /* + always @(posedge sys_clk_i or negedge rst_mobeam_n) begin + if(!rst_mobeam_n) begin + clk_count_2<=0; + clk_count_3<=0; + check_shift_done_count<=2'b00; + end + else begin + + if(shift_done) begin + if(clk_count_2==1) begin + clk_count_2<=0; + check_shift_done_count<=check_shift_done_count + 1; + end + else begin + check_shift_done_count<=check_shift_done_count; + end + clk_count_2<=clk_count_2 + 1; + end + else if(check_shift_done_count==2'b10) begin + if(clk_count_3==1) begin + check_shift_done_count<=0; + clk_count_3<=0; + end + else begin + check_shift_done_count<=check_shift_done_count; + end + clk_count_3<=clk_count_3+1; + end + else + check_shift_done_count<=check_shift_done_count; + end + end + */ + //assign check_shift_done_count= (!rst_mobeam_n) ? 3'b000 : shift_done ? (check_shift_done_count + 1) : check_shift_done_count; + + wire incr_ba_mem_addr; + reg q_tx_out_en_0,q_tx_out_en_1; + assign incr_ba_mem_addr=(check_shift_done_count==2'b10) ? 1 : 0; + //assign bl_done=(bl_byte_count_3==o_bl_data + 1) ? 1 : 0; + //assign o_byte_data=((bl_byte_count_3 >0) && !bl_done) ? byte_data : 8'bz; + //assign o_byte_data= ba_mem_rd_en ? (/*(isd_delay_en || ipd_delay_en)*/ !tx_out_en ? 8'bz : byte_data) : 0; + + assign o_byte_data= byte_data; + assign txn_start = q_tx_out_en_1; + + + //assign txn_start = tx_out_en; //orignal + + always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam || !start_stop) begin + q_tx_out_en_0<=0; + q_tx_out_en_1<=0; + end + else begin + q_tx_out_en_0<=tx_out_en; + q_tx_out_en_1<=q_tx_out_en_0; + end + end + wire tx_out_en_high_dtc; + + assign tx_out_en_high_dtc= ~q_tx_out_en_0 && tx_out_en; + +//////////////BA FSM///////////////////////////////////////////// + always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam) begin + ba_mem_addr<=0; + ba_mem_rd_en<=0; + ba_state<=`IDLE_STATE; + end + else begin + case(ba_state) + `IDLE_STATE: begin + ba_mem_addr<=0; + ba_mem_rd_en<=0; + if(/*start_stop*/ config_reg_done) + ba_state<=`READ_WORD; + else + ba_state<=`IDLE_STATE; + end + + `READ_WORD:begin + ba_mem_rd_en<=1; + if(!start_stop) + ba_state<=`IDLE_STATE; + else if(symbol_shift_done) //make address=0 when #shift_done's == o_bl_data + ba_mem_addr<=0; + else if(!tx_out_en) + ba_state<=`DELAY_STATE; + else if(incr_ba_mem_addr) begin + ba_mem_addr<=ba_mem_addr + 1; + ba_state<=`READ_BYTE_LATENCY_1; + end + else begin + ba_mem_addr<=ba_mem_addr; + ba_state<=`READ_WORD; + end + end + + `READ_BYTE_LATENCY_1:begin + if(!start_stop) + ba_state<=`IDLE_STATE; + else + ba_state<=`READ_WORD; + end + + `DELAY_STATE:begin + if(!start_stop) + ba_state<=`IDLE_STATE; + else begin + ba_mem_addr<=ba_mem_addr; + if(tx_out_en) + ba_state<=`READ_WORD; + else + ba_state<=`DELAY_STATE; + end + end + + endcase + end //else begin + end //else always +///////////////////////////////////////////////////////////////// + reg start_stop_count; + + always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam) begin + start_stop_count=0; + end + else begin + if(start_stop) + start_stop_count=1; + end + end + + +//////////////////BSR FSM/////////////////////////////////////// + + + +assign bsr_mem_clk=sys_clk_i; +reg state_count; +reg init_addr_read_done; +reg [8:0] prev_mem_rd_addr; +reg [8:0] next_mem_rd_addr; + + always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam) begin + bsr_state<=`IDLE_BSR; + i<=0; + i_2<=0; + bsr_data_count<=0; + // write_to_bsr_buffer<=0; + state_count<=0; + config_reg_done<=0; + next_mem_rd_addr<=0; + bsr_mem_addr<=0; + prev_mem_rd_addr<=0; + bsr_mem_rd_en<=1'b1; + // bsr_load_done<=0; + init_addr_read_done<=0; + rd_done<=1'b0; + o_lb_data<=0; + o_lp_data<=0; + o_nh_data<=0; + o_nr_data<=0; + o_bl_data<=0; + o_bsr_data<=0; + end + else begin + + case(bsr_state) + `IDLE_BSR:begin + i<=0; + i_2<=0; + bsr_data_count<=0; + // write_to_bsr_buffer<=0; + state_count<=0; + config_reg_done<=0; + next_mem_rd_addr<=0; + bsr_mem_addr<=0; + prev_mem_rd_addr<=0; + bsr_mem_rd_en<=1'b1; + // bsr_load_done<=0; + init_addr_read_done<=0; + rd_done<=1'b0; + if (start_stop==1) + bsr_state<=`LB_READ; + else + bsr_state<=`IDLE_BSR; + end + + + `LB_READ:begin + bsr_mem_addr<=lb_addr; + bsr_mem_rd_en<=1'b1; + bsr_state<=`LB_READ_LATENCY; + end + + `LB_READ_LATENCY:begin + state_count<=state_count + 1; + if(state_count==1) begin + o_lb_data<=bsr_mem_data; + state_count<=0; + bsr_state<=`LP_READ; + end + else + bsr_state<=`LB_READ_LATENCY; + end + + `LP_READ:begin + bsr_mem_addr<=lp_addr; + bsr_mem_rd_en<=1'b1; + bsr_state<=`LP_READ_LATENCY; + end + + `LP_READ_LATENCY:begin + state_count<=state_count + 1; + if(state_count==1) begin + o_lp_data<=bsr_mem_data; + state_count<=0; + bsr_state<=`BL_READ; + end + else + bsr_state<=`LP_READ_LATENCY; + end + + `BL_READ:begin + bsr_mem_addr<=bl_addr; + bsr_mem_rd_en<=1'b1; + bsr_state<=`BL_READ_LATENCY; + + end + + `BL_READ_LATENCY:begin + state_count<=state_count + 1; + if(state_count==1) begin + o_bl_data<=bsr_mem_data; + state_count<=0; + bsr_state<=`NH_READ; + end + else + bsr_state<=`BL_READ_LATENCY; + end + + `NH_READ:begin + bsr_mem_addr<=nh_addr; + bsr_mem_rd_en<=1'b1; + bsr_state<=`NH_READ_LATENCY; + end + + `NH_READ_LATENCY:begin + state_count<=state_count + 1; + if(state_count==1) begin + o_nh_data<=bsr_mem_data; + state_count<=0; + bsr_state<=`NR_READ; + end + else + bsr_state<=`NH_READ_LATENCY; + end + + `NR_READ:begin + bsr_mem_addr<=nr_addr; + bsr_mem_rd_en<=1'b1; + rd_done<=1'b1; + bsr_state<=`NR_READ_LATENCY; + end + + `NR_READ_LATENCY:begin + state_count<=state_count + 1; + if(state_count==1) begin + o_nr_data<=bsr_mem_data; + state_count<=0; + bsr_state<=`BSR_READ; + end + else + bsr_state<=`NR_READ_LATENCY; + end + + + `BSR_READ:begin + if (i==0) begin + i<=1'b1; + bsr_data_count<=0; + + if(init_addr_read_done==0 || nh_hop_shift_done_2) + bsr_mem_addr<=bsr_addr; + else if(hop_shift_done_3) begin //if shift_count==np*ns then next 8 bytes else + //config_reg_done<=0; + bsr_mem_addr<=next_mem_rd_addr+1; + end + else + bsr_mem_addr<=prev_mem_rd_addr; + + bsr_mem_rd_en<=1'b1; + bsr_state<=`BSR_READ_LATENCY; + end + else begin + bsr_mem_addr<=bsr_mem_addr+1; + bsr_data_count<=bsr_data_count+1; + if (bsr_data_count==6) begin //read all 8 bytes of bsr data,increament hop_count + // bsr_data_count<=0; + next_mem_rd_addr<=bsr_mem_addr; + // write_to_bsr_buffer<=0; + // bsr_load_done<=1; + config_reg_done<=1; + //bsr_state<=`BEAM_START_STOP; + bsr_state<=`START_HOP; + end + else begin + config_reg_done<=config_reg_done; + bsr_state<=`BSR_READ_LATENCY; + end + end + end + + `BSR_READ_LATENCY:begin + if(i_2==1'b0) begin /*store first address in temp register*/ + i_2<=1'b1; + prev_mem_rd_addr<=bsr_mem_addr; + end + state_count<=state_count + 1; + // write_to_bsr_buffer<=1; + if(state_count==1) begin + o_bsr_data<=bsr_mem_data; + bsr_buffer[bsr_data_count]<=bsr_mem_data; + state_count<=0; + bsr_state<=`BSR_READ; + end + else begin + bsr_state<=`BSR_READ_LATENCY; + // write_to_bsr_buffer<=0; + end + end + + `START_HOP: begin + i<=1'b0; + i_2<=1'b0; + // bsr_load_done<=0; + init_addr_read_done<=1; + if(!start_stop && start_stop_count) + bsr_state<=`IDLE_BSR; + else if(hop_shift_done) + bsr_state<=`BSR_READ; + else + bsr_state<=`START_HOP; + end + + + // `BEAM_START_STOP: begin + // i<=1'b0; + // i_2<=1'b0; + // init_addr_read_done<=1; + // bsr_load_done<=0; + // rd_done<=1'b0; + // bsr_mem_addr<=beam_start_stop_addr; + // bsr_mem_rd_en<=1'b1; + // if(hop_shift_done/*symbol_shift_done*/) + // bsr_state<=`BSR_READ; + // else + // bsr_state<=`BEAM_START_STOP_LATENCY; + // end + + // `BEAM_START_STOP_LATENCY:begin + // state_count<=state_count + 1; + // if(state_count==1) begin + // state_count<=0; + // if (bsr_mem_data==8'b00000001) begin + // start_stop<=1'b1; + // if(hop_shift_done/*symbol_shift_done*/) + // bsr_state<=`BSR_READ; + // else + // bsr_state<=`BEAM_START_STOP; + // end + // else begin + // start_stop<=1'b0; + // bsr_state<=`IDLE_BSR; + // end + // end + // else + // bsr_state<=`BEAM_START_STOP_LATENCY; + // end + + endcase + + end + end + + /////*********edge detection for config_reg_done***********//////////// + reg q_config_reg_done; + always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam) + q_config_reg_done<=0; + else + q_config_reg_done<=config_reg_done; + end + + assign config_reg_done_pos_dtc= config_reg_done && (~q_config_reg_done); + + +////**************LOGIC TO FIND PACKET AND SYMBOL COUNT*************///////// + reg [7:0] packet_count; + reg [3:0] hop_count; + reg [7:0] symbol_count; + reg [7:0] shift_done_count; + reg symbol_shift_done,symbol_shift_done_2,symbol_shift_done_3; + reg packet_shift_done; + reg hop_shift_done,hop_shift_done_2,hop_shift_done_3; + reg clk_count,clk_count_4; + reg nh_hop_shift_done,nh_hop_shift_done_2,nh_hop_shift_done_3; + + assign nh_hop_shift_done_led=nh_hop_shift_done_3; + + + always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam) begin + packet_count=0; + hop_count=0; + hop_shift_done=0; + shift_done_count=0; + symbol_count=0; + clk_count<=0; + clk_count_4<=0; + hop_shift_done_2<=0; + hop_shift_done_3<=0; + nh_hop_shift_done<=0; + nh_hop_shift_done_2<=0; + nh_hop_shift_done_3<=0; + symbol_shift_done<=0; + symbol_shift_done_2<=0; + symbol_shift_done_3<=0; + packet_shift_done=0; + end + else begin + if(start_stop) begin + hop_shift_done=0; + nh_hop_shift_done<=0; + symbol_shift_done<=0; + packet_shift_done=0; + if(shift_done) begin + //clk_count<=clk_count+1; + //if(clk_count==1'b1) begin //orignal + //clk_count<=0; + if(shift_done_count==(o_bl_data-1)) begin //bl check + shift_done_count=0; + symbol_shift_done<=1; + if(symbol_count==(bsr_ns-1)) begin //symbol_check + symbol_count=0; + packet_shift_done=1; + if(packet_count==(bsr_np-1)) begin //packet check + packet_count=0; + hop_shift_done=1; + if(hop_count==(o_nh_data-1)) begin //hop_check + hop_count=0; + nh_hop_shift_done<=1; + end + else begin + hop_count=hop_count + 1; //hop_check + end + end + else begin //packet check + packet_count=packet_count+1; + hop_shift_done=0; + end + end + else begin + symbol_count=symbol_count+1; + end + end + else + shift_done_count=shift_done_count+1; //bl check + end + else + //shift_done_count=shift_done_count+1; //orignal + shift_done_count=shift_done_count; + //end //orignal + + nh_hop_shift_done_2<=nh_hop_shift_done; + nh_hop_shift_done_3<=nh_hop_shift_done_2; + hop_shift_done_2<=hop_shift_done; + hop_shift_done_3<=hop_shift_done_2; + symbol_shift_done_2<=symbol_shift_done; + symbol_shift_done_3<=symbol_shift_done_2; + end + else begin + packet_count=0; + hop_count=0; + hop_shift_done=0; + shift_done_count=0; + symbol_count=0; + clk_count<=0; + clk_count_4<=0; + hop_shift_done_2<=0; + hop_shift_done_3<=0; + nh_hop_shift_done<=0; + nh_hop_shift_done_2<=0; + nh_hop_shift_done_3<=0; + symbol_shift_done<=0; + symbol_shift_done_2<=0; + symbol_shift_done_3<=0; + packet_shift_done=0; + end + end +end + /* + + always @(posedge sys_clk_i or negedge rst_mobeam_n) begin + if(!rst_mobeam_n) begin + packet_count=0; + hop_count=0; + hop_shift_done=0; + shift_done_count=0; + clk_count<=0; + nh_hop_shift_done=0; + end + else begin + if(start_stop) begin + hop_shift_done=0; + nh_hop_shift_done=0; + if(shift_done) begin + clk_count<=clk_count+1; + if(clk_count==1'b1) begin + clk_count<=0; + if(shift_done_count==(bsr_ns-1)) begin + shift_done_count=0; + if(packet_count==(bsr_np-1)) begin + packet_count=0; + if(hop_count==(o_nh_data-1)) begin + hop_count=0; + nh_hop_shift_done=1; + // hop_shift_done=1; + end + else begin + hop_shift_done=1; + hop_count=hop_count + 1; + end + end + else begin + packet_count=packet_count+1; + hop_shift_done=0; + end + end + else + shift_done_count=shift_done_count+1; + end + end + else + shift_done_count=shift_done_count; + end + else begin + shift_done_count=0; + packet_count=0; + hop_count=0; + hop_shift_done=0; + end + end +end +*/ +/////////*******BSR CONTROL REGSITER DATA******************//////// + +wire [7:0] bsr_bw_int; //bar width +wire [7:0] bsr_ns; //number of symbols +wire [15:0] bsr_isd; //inter symbol distance +wire [7:0] bsr_np; //number of packets +wire [15:0] bsr_ipd; //inter packet distance +//wire [55:0] control_reg; + +//assign bsr_bw = bsr_bw_int; //orignal + +always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam || !start_stop) begin + bsr_bw<= 0; + end +else + if (hop_after_txn_neg || config_reg_done_pos_dtc) //added "|| config_reg_done_pos_dtc" on 13/feb/2014 + bsr_bw <= bsr_bw_int; + //else + //bsr_bw <= bsr_bw; + end + + + + +//assign bsr_bw = (bsr_data_count==31'd7) ? (hop_after_txn_neg ? bsr_bw_int : bsr_bw) : 0 ; + + +assign bsr_bw_int=(bsr_data_count==31'd7) ? {bsr_buffer[0][7:0]} : 0; +assign bsr_ns=(bsr_data_count==31'd7) ? bsr_buffer[1][7:0] : 0; +assign bsr_isd=(bsr_data_count==31'd7) ?{bsr_buffer[3][7:0],bsr_buffer[2][7:0]} : 0; +assign bsr_np=(bsr_data_count==31'd7) ? bsr_buffer[4][7:0] : 0; +assign bsr_ipd=(bsr_data_count==31'd7) ? {bsr_buffer[6][7:0],bsr_buffer[5][7:0]}: 0; + +//assign control_reg=!rst_mobeam ? 56'bz : bsr_load_done ? {bsr_ipd,bsr_np,bsr_isd,bsr_ns,bsr_bw}:control_reg; + +//assign o_ba_mem_data=start_stop ? ba_mem_data : 16'bz; +//assign o_ba_mem_data=(ba_state==`SHIFT_WORD) ? ba_mem_data : 16'bz; + +/************************************************************************/ + + + + +/////***************FSM DECODE********************////////////// + /*AUTOASCIIENUM("bsr_state" "state_ASCII")*/ + // Beginning of automatic ASCII enum decoding + reg [111:0] state_ASCII; // Decode of bsr_state + always @(bsr_state) begin + case ({bsr_state}) + `IDLE_BSR : state_ASCII = "IDLE_BSR "; + `NH_READ : state_ASCII = "NH_READ"; + `NH_READ_LATENCY: state_ASCII = "NH_READ_LATENCY "; + `NR_READ : state_ASCII = "NR_READ "; + `NR_READ_LATENCY: state_ASCII = "NR_READ_LATENCY "; + `BL_READ : state_ASCII = "BL_READ "; + `BL_READ_LATENCY: state_ASCII = "BL_READ_LATENCY "; + `BSR_READ : state_ASCII = "BSR_READ "; + `BSR_READ_LATENCY: state_ASCII = "BSR_READ_LATENCY "; + `START_HOP : state_ASCII = "START_HOP "; + `LB_READ : state_ASCII = "LB_READ "; + `LB_READ_LATENCY: state_ASCII = "LB_READ_LATENCY "; + `LP_READ : state_ASCII = "LP_READ "; + `LP_READ_LATENCY: state_ASCII = "LP_READ_LATENCY "; + + //`BEAM_START_STOP : state_ASCII = "BEAM_START_STOP "; + //`BEAM_START_STOP_LATENCY: state_ASCII = "BEAM_START_STOP_LATENCY "; + default: state_ASCII = "%Error "; + endcase + end + // End of automatics + + /*AUTOASCIIENUM("ba_state" "state_ASCII")*/ + // Beginning of automatic ASCII enum decoding + reg [111:0] ba_state_ASCII; // Decode of ba_state + always @(ba_state) begin + case ({ba_state}) + `IDLE_STATE : ba_state_ASCII = "IDLE_STATE "; + `READ_WORD : ba_state_ASCII = "READ_WORD"; + `READ_BYTE_LATENCY_1: ba_state_ASCII = "READ_BYTE_LATENCY_1 "; + `DELAY_STATE : ba_state_ASCII = "DELAY_STATE "; + + `SHIFT_WORD : ba_state_ASCII = "SHIFT_WORD "; + default: ba_state_ASCII = "%Error "; + endcase + end + // End of automatics +////////////////********************************//////////////////// + /* +wire isd_delay_en; +wire ipd_delay_en; +wire low_isd_delay_en_dtc; +wire tx_out_en; + + +reg q1_isd_delay_en,q2_isd_delay_en; + + +always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam) begin + q1_isd_delay_en<=0; + q2_isd_delay_en<=0; + end + else begin + q1_isd_delay_en<=isd_delay_en; + q2_isd_delay_en<=q1_isd_delay_en; + end + end + */ +// assign low_isd_delay_en_dtc= q1_isd_delay_en && ~isd_delay_en ;///*&& q2_isd_delay_en*/; + +wire isd_delay_en; +wire ipd_delay_en; +wire low_isd_delay_en_dtc; + + +//assign tx_out_en= ba_mem_rd_en ? ((isd_delay_en || ipd_delay_en) ? 0 : 1) : 0; + +//assign dummy_tx_out_en= ba_mem_rd_en ? ( (isd_delay_en && ipd_delay_en) ? (ipd_delay_en ? 1 : 0) : (isd_delay_en ? 1 : 0)) : 0 ; + +//assign dummy_tx_out_en= ba_mem_rd_en ? (isd_delay_en_rise_dtc ? ((isd_delay_en_rise_dtc && ipd_delay_en_rise_dtc) ? (ipd_delay_en ? 1 : 0) : ipd_delay_en) : (isd_delay_en ? 1 : 0)) : 0 ; //(isd_delay_en ? 1 : 0)) : 0 ; + +reg q1_isd_delay_en,q1_ipd_delay_en; + +always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam || !start_stop) begin + q1_isd_delay_en<=0; + q1_ipd_delay_en<=0; + end + else begin + q1_isd_delay_en<=isd_delay_en; + q1_ipd_delay_en<=ipd_delay_en; + end +end + +reg tx_out_en; + + +always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam || !start_stop) begin + tx_out_en<=0; + end +else begin + if(ba_mem_rd_en) begin + if(isd_delay_en_rise_dtc && ipd_delay_en_rise_dtc) + tx_out_en<=0; + else if(isd_delay_en_rise_dtc) + tx_out_en<=0; + else if(isd_delay_en_fall_dtc && ipd_delay_en) // + tx_out_en<=0; + else if(ipd_delay_en_fall_dtc) + tx_out_en<=1; + else if(!isd_delay_en && !ipd_delay_en) // + tx_out_en<=1; + else + tx_out_en<=tx_out_en; + end + else + tx_out_en<=0; + end +end + +assign isd_delay_en_rise_dtc=~q1_isd_delay_en && isd_delay_en; +assign ipd_delay_en_rise_dtc=~q1_ipd_delay_en && ipd_delay_en; +assign isd_delay_en_fall_dtc=q1_isd_delay_en && ~isd_delay_en; +assign ipd_delay_en_fall_dtc=q1_ipd_delay_en && ~ipd_delay_en; +assign low_isd_delay_en_dtc= q1_isd_delay_en && ~isd_delay_en ;///*&& q2_isd_delay_en*/; + + +reg hop_after_txn,q_hop_after_txn; + +always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam || !start_stop) begin + hop_after_txn<=0; + end + else begin + if(hop_shift_done) + hop_after_txn<=1; + else if(tx_out_en && bit_done) + hop_after_txn<=0; + else + hop_after_txn<=hop_after_txn; + end +end + +always @(posedge sys_clk_i or posedge rst_mobeam) begin + if(rst_mobeam || !start_stop) begin + q_hop_after_txn<=0; + end + else + q_hop_after_txn<=hop_after_txn; +end + + assign hop_after_txn_neg= (~hop_after_txn) & q_hop_after_txn; + + +delay_gen_ihd_ipd_isd mobeam_delay_gen_inst( + .clk(sys_clk_i), + .rst(rst_mobeam), + .isd_val(bsr_isd), + .ipd_val(bsr_ipd), + .start_stop(start_stop), + .config_reg_done(config_reg_done), + .hop_shift_done(hop_shift_done), + .packet_shift_done(packet_shift_done), + .symbol_shift_done(symbol_shift_done), + .isd_delay_en(isd_delay_en), + .ipd_delay_en(ipd_delay_en) + ) ; + + /* + `ifdef SIM + reg shift_done; + initial begin + shift_done=0; + #160000 + repeat(1000) begin + #40000 + shift_done=1; + #50 + shift_done=0; + end + + end + `endif + */ +endmodule \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v new file mode 100644 index 000000000..5100e5fe9 --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v @@ -0,0 +1,160 @@ +//================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// ------------------------------------------------------------------ +// Copyright (c) 2014 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code for use +// in synthesis for any Lattice programmable logic product. Other +// use of this code, including the selling or duplication of any +// portion is strictly prohibited. + +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// + + +module mobeam_delay_gen( + input clk, + input rst_n, + input [15:0] isd_val, + input [15:0] ipd_val, + input config_reg_done, + input symbol_shift_done, + input packet_shift_done, + output reg isd_delay_en, + output reg ipd_delay_en +); + +reg [15:0] isd_val_temp; +reg [15:0] ipd_val_temp; +reg [15:0] isd_count; +reg [15:0] ipd_count; +wire [15:0] max_count,max_count_pkt; +reg clk_count,clk_count_pkt; +reg count_done,count_done_pkt; + +parameter const=10; +assign max_count=isd_val_temp * const; +assign max_count_pkt=ipd_val_temp * const; + +wire count_enable,count_enable_pkt; +//wire config_done; +//assign config_done= !rst_n ? 0 : config_reg_done ? 1 : config_done; +assign count_enable= !rst_n ? 0 : count_done ? 0 : symbol_shift_done ? 1 : count_enable; +assign count_enable_pkt= !rst_n ? 0 : count_done_pkt ? 0 : packet_shift_done ? 1 : count_enable_pkt; + +//assign isd_delay_en=symbol_shift_done ? 1 : (isd_count==max_count-1) : + +///////////////////////symbol//////////////////////////////////// +always @(posedge clk or negedge rst_n) begin + if(!rst_n) begin + isd_count<=0; + count_done<=0; + end + else begin + count_done<=0; + if(count_enable) begin + if(isd_count==max_count-1) begin + isd_count<=0; + count_done<=1; + isd_delay_en<=0; + end + else begin + isd_delay_en<=1; + isd_count<=isd_count+1; + end + end + else begin + isd_delay_en<=0; + isd_count<=0; + end + end +end + +always @(posedge clk or negedge rst_n) begin + if(!rst_n) begin + isd_val_temp<=0; + clk_count<=0; + end + else begin + if(clk_count) + isd_val_temp<=isd_val_temp; + else if(config_reg_done) begin + clk_count<=clk_count+1; + isd_val_temp<=isd_val; + end + else + isd_val_temp<=isd_val_temp; + end +end +///////////////packet////////////////////// +always @(posedge clk or negedge rst_n) begin + if(!rst_n) begin + ipd_count<=0; + count_done_pkt<=0; + end + else begin + count_done_pkt<=0; + if(count_enable_pkt) begin + if(ipd_count==max_count_pkt-1) begin + ipd_count<=0; + count_done_pkt<=1; + ipd_delay_en<=0; + end + else begin + ipd_delay_en<=1; + ipd_count<=ipd_count+1; + end + end + else begin + ipd_delay_en<=0; + ipd_count<=0; + end + end +end + +always @(posedge clk or negedge rst_n) begin + if(!rst_n) begin + ipd_val_temp<=0; + clk_count_pkt<=0; + end + else begin + if(clk_count_pkt) + ipd_val_temp<=ipd_val_temp; + else if(config_reg_done) begin + clk_count_pkt<=clk_count_pkt+1; + ipd_val_temp<=ipd_val; + end + else + ipd_val_temp<=ipd_val_temp; + end +end + +endmodule diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v new file mode 100644 index 000000000..c8d1494e8 --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v @@ -0,0 +1,377 @@ +//================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// ------------------------------------------------------------------ +// Copyright (c) 2014 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code for use +// in synthesis for any Lattice programmable logic product. Other +// use of this code, including the selling or duplication of any +// portion is strictly prohibited. + +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// + + +module mobeam_i2c_reg_interface( + rst_i, + clk_i, + //i2c slave interface signals/// + i2c_master_to_slave_data_i, + i2c_slave_to_master_data_o, + i2c_slave_data_address_i, + wr_en_i, + rd_en_i, + i2c_start_i, + //MoBeam control logic interface// + rd_revision_code, + rst_mobeam, + mobeam_start_stop, + led_polarity, + o_ba_mem_data, + i_ba_mem_addr, + i_ba_mem_rd_en, + i_ba_mem_rd_clk, + o_bsr_mem_data, + i_bsr_mem_addr, + i_bsr_mem_rd_en, + i_bsr_mem_rd_clk + // i_config_reg_done, + // o_new_data_rd, + // o_data_strobe + ); +//i2c slave interface signals/// +input [7:0] i2c_master_to_slave_data_i; +output reg [7:0]i2c_slave_to_master_data_o; +input [7:0] i2c_slave_data_address_i; +input wr_en_i; +input rd_en_i; +input i2c_start_i; +input rst_i; +input clk_i; +//mobeam control logic interface// +output [15:0] o_ba_mem_data; +input [7:0] i_ba_mem_addr; +input i_ba_mem_rd_en; +input i_ba_mem_rd_clk; +output reg rd_revision_code=0; +output reg rst_mobeam=0; +//input[7:0] i_revision_code_data; +//input rd_revision_code; +output [7:0] o_bsr_mem_data; +//output reg [15:0] mem_data_buf16; +input [8:0] i_bsr_mem_addr; +input i_bsr_mem_rd_en; +input i_bsr_mem_rd_clk; +output reg mobeam_start_stop=1'b0; +output reg led_polarity=1'b0; +//output reg o_new_data_rd=1'b0; +//output reg o_data_strobe=1'b0; +//input i_config_reg_done; + + + + + + + + +//////////////wire & reg declarations////////////////// +wire wr_en; +wire rd_en; +reg d1_wr_en_i; +reg d2_wr_en_i; +reg d1_rd_en_i; +reg d2_rd_en_i; + +parameter revision_code=8'hF1; + + + + +/////////////////////BSR and CONFIG data memory////////////// + +SB_RAM512x8 ram512x8_inst +( + .RDATA(o_bsr_mem_data),// EBR512x8_data + .RADDR(i_bsr_mem_addr),// EBR512x8_addr + .RCLK(i_bsr_mem_rd_clk), + .RCLKE(i_bsr_mem_rd_en), + .RE(i_bsr_mem_rd_en),// EBR512x8_re + .WADDR({1'b0,bsr_mem_addr_in}), + .WCLK(clk_i), + .WCLKE(1'b1),///*bsr_wr_en/*wr_en*/), + .WDATA(i2c_master_to_slave_data_i), + .WE(bsr_wr_en) ////*bsr_wr_en/*wr_en*/) +); + +defparam ram512x8_inst.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +//ICE Technology Library 66 +//Lattice Semiconductor Corporation Confidential +defparam ram512x8_inst.INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram512x8_inst.INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + +///////////////////////BA i.e. beamable data memory////////////// +SB_RAM256x16 ram256x16_inst ( +.RDATA(o_ba_mem_data), +.RADDR(i_ba_mem_addr), +.RCLK(i_ba_mem_rd_clk), +.RCLKE(i_ba_mem_rd_en), +.RE(i_ba_mem_rd_en), +.WADDR(ba_mem_addr_in_delayed_1), +.WCLK(clk_i), +.WCLKE(1'b1),///*ba_wr_en/*wr_en*/), +.WDATA(ba_mem_data_buffer), +.WE(ba_wr_en_delayed),///*wr_en*/), +.MASK(16'd0) +); +defparam ram256x16_inst.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; +defparam ram256x16_inst.INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + +// Write valid pulse +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + d1_wr_en_i <= 0; + d2_wr_en_i <= 0; + end else begin + d1_wr_en_i <= wr_en_i; + d2_wr_en_i <= d1_wr_en_i; + end +end + +assign wr_en = d2_wr_en_i && ~d1_wr_en_i; + +// Read enable pulse +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + d1_rd_en_i <= 0; + d2_rd_en_i <= 0; + end else begin + d1_rd_en_i <= rd_en_i; + d2_rd_en_i <= d1_rd_en_i; + end +end + + +assign rd_en = ~d2_rd_en_i && d1_rd_en_i; + +reg [7:0] bsr_mem_addr_in; + +reg [7:0] ba_mem_addr_in; +reg ba_wr_en; + + +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + bsr_mem_addr_in <= 9'd0; + + end +else + if (i2c_start_i) + bsr_mem_addr_in <= i2c_slave_data_address_i; + + else if (i2c_slave_data_address_i == 8'h80) begin + if (wr_en) begin + bsr_mem_addr_in <=bsr_mem_addr_in + 1'b1; + + end + + end +end + +assign bsr_wr_en = (i2c_slave_data_address_i == 8'h00)?1'b0:wr_en; + +//MOBEAM START-STOP +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + mobeam_start_stop<=1'b0; + + end +else + if (i2c_slave_data_address_i == 8'hF0) //8'hEC + if (wr_en & (i2c_master_to_slave_data_i==8'b00000001))begin + mobeam_start_stop<=1'b1; + end + else if(wr_en & (i2c_master_to_slave_data_i==8'b00000000))begin + mobeam_start_stop<=1'b0; + end + +end + + +//MOBEAM RESET +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + rst_mobeam<=1'b0; + + end +else + if (i2c_slave_data_address_i == 8'hF1) + if (wr_en & (i2c_master_to_slave_data_i==8'b00000001))begin + rst_mobeam<=1'b1; + end + else if(wr_en & (i2c_master_to_slave_data_i==8'b00000000))begin + rst_mobeam<=1'b0; + end + +end + +//REVISION CODE +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + rd_revision_code<=1'b0; + + end +else + if (rd_en)begin + if (i2c_slave_data_address_i == 8'hF2) begin + rd_revision_code<=1'b1; + i2c_slave_to_master_data_o<=revision_code; + end + else begin + rd_revision_code<=1'b0; + i2c_slave_to_master_data_o<=0; + end + end + else + i2c_slave_to_master_data_o<=0; + +end + +//LED POLARITY +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + led_polarity<=1'b0; + + end else begin + //if (wr_en)begin + //if (i2c_slave_data_address_i == 8'hEB)begin + //if (i2c_master_to_slave_data_i==8'b00000001)begin + led_polarity<=1'b1; + //end else begin + //led_polarity<=1'b0; + //end + //end + //end + end +end + +reg ba_wr_en_delayed; +reg wr_en_cnt; +reg [7:0] ba_mem_addr_in_delayed,ba_mem_addr_in_delayed_1; +reg [7:0] data_buffer; +reg [15:0] ba_mem_data_buffer; + + +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + ba_mem_addr_in_delayed<=8'd0; + ba_mem_addr_in_delayed_1<=8'd0; + ba_wr_en_delayed<= 1'b0; + + end +else begin + ba_mem_addr_in_delayed<= ba_mem_addr_in; + ba_mem_addr_in_delayed_1<= ba_mem_addr_in_delayed; + ba_wr_en_delayed<= ba_wr_en; + +end +end + + + + + +//assign ba_mem_data_buffer = { i2c_master_to_slave_data_i,data_buffer}; +always @(posedge clk_i or posedge rst_i) begin + if (rst_i) begin + ba_mem_addr_in <= 9'd0; + ba_wr_en<= 1'b0; + wr_en_cnt<= 1'b0; + end +else + + if (i2c_slave_data_address_i == 8'h00) begin + + if (wr_en_cnt) begin + ba_mem_data_buffer <= { i2c_master_to_slave_data_i,data_buffer}; + end + + + if (wr_en) begin + wr_en_cnt<= wr_en_cnt + 1'b1; + ba_wr_en<= 1'b1; + if (~wr_en_cnt)begin + data_buffer <= i2c_master_to_slave_data_i; + end + else + ba_mem_addr_in <= ba_mem_addr_in + 1'b1; + end + else + ba_wr_en<= 1'b0; + + end + else begin + ba_mem_addr_in<=0; + ba_wr_en<= 1'b0; + wr_en_cnt<=0; + end + +end +endmodule \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v new file mode 100644 index 000000000..f2d0b0a68 --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v @@ -0,0 +1,82 @@ +//================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// ------------------------------------------------------------------ +// Copyright (c) 2014 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code for use +// in synthesis for any Lattice programmable logic product. Other +// use of this code, including the selling or duplication of any +// portion is strictly prohibited. + +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// + + +module testpll_pll(REFERENCECLK, + PLLOUTCORE, + PLLOUTGLOBAL, + RESET, + LOCK); + +input REFERENCECLK; +input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ +output PLLOUTCORE; +output PLLOUTGLOBAL; +output LOCK; + +SB_PLL40_CORE testpll_pll_inst(.REFERENCECLK(REFERENCECLK), + .PLLOUTCORE(PLLOUTCORE), + .PLLOUTGLOBAL(PLLOUTGLOBAL), + .EXTFEEDBACK(), + .DYNAMICDELAY(), + .RESETB(RESET), + .BYPASS(1'b0), + .LATCHINPUTVALUE(), + .LOCK(LOCK), + .SDI(), + .SDO(), + .SCLK()); + +//\\ Fin=27, Fout=20.05; +defparam testpll_pll_inst.DIVR = 4'b0000; +defparam testpll_pll_inst.DIVF = 7'b0010111; +defparam testpll_pll_inst.DIVQ = 3'b101; +defparam testpll_pll_inst.FILTER_RANGE = 3'b011; +defparam testpll_pll_inst.FEEDBACK_PATH = "SIMPLE"; +defparam testpll_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; +defparam testpll_pll_inst.FDA_FEEDBACK = 4'b0000; +defparam testpll_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; +defparam testpll_pll_inst.FDA_RELATIVE = 4'b0000; +defparam testpll_pll_inst.SHIFTREG_DIV_MODE = 2'b00; +defparam testpll_pll_inst.PLLOUT_SELECT = "GENCLK"; +defparam testpll_pll_inst.ENABLE_ICEGATE = 1'b0; + +endmodule diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v new file mode 100644 index 000000000..77af4ca73 --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v @@ -0,0 +1,334 @@ +//================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// ------------------------------------------------------------------ +// Copyright (c) 2014 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code for use +// in synthesis for any Lattice programmable logic product. Other +// use of this code, including the selling or duplication of any +// portion is strictly prohibited. + +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// + +//`define SIM +`define i2c +//`define spi +//`define uart + + + +module top_module + // Outputs + ( o_led, + // Inouts + `ifdef i2c + io_i2c_scl, io_i2c_sda, + `endif + //spi signals + `ifdef spi + i_sck, i_csn, i_mosi,o_miso, + `endif + `ifdef uart + o_tx,i_rx, + `endif + //testpoints + drive_on, + // Inputs + i_clk + )/*synthesis syn_dspstyle=logic*/; + + //input i_rst; + + output wire o_led; + output drive_on; + input i_clk; +`ifdef i2c + inout io_i2c_scl; + inout io_i2c_sda; +`endif +`ifdef spi + input i_sck; + input i_csn; + input i_mosi; + output o_miso; +`endif +`ifdef uart + output o_tx; + input i_rx; +`endif + wire sclin_i; + wire sdain_i; + wire sdaout_i; + wire [7:0] datain_i; + wire write_en_i; + wire [7:0] dataout_i; + wire [7:0] regaddr_i; + wire read_en_i; + reg [15:0] poweron_reset_count_i = 0; //initialized for simulation + reg poweron_reset_n_i = 0; // initialized for simulation + wire rst_i; + +//mobeam control logic interface// +wire [15:0] o_ba_mem_data; +wire [7:0] i_ba_mem_addr; +wire i_ba_mem_rd_en; +wire i_ba_mem_rd_clk; +wire rd_revision_code; +wire rst_mobeam; +wire [7:0] o_bsr_mem_data; +wire [8:0] i_bsr_mem_addr; +wire i_bsr_mem_rd_en; +wire i_bsr_mem_rd_clk; +wire o_new_data_rd; +wire o_bsr_data_strobe; +wire i_config_reg_done; +//////////////////////////////// +wire clk_20mhz_g; + +testpll_pll testpll_pll_inst(.REFERENCECLK(i_clk), + .PLLOUTCORE(), + .PLLOUTGLOBAL(clk_20mhz_g), + .RESET(~rst_i/*1'b1*/), + .LOCK()); + +//selection of SPI or I2C/// +`ifdef spi +user_logic_control_reg_spidata_buf spi_mobeam_logic_interface +( +///spi Signal///// + .i_sys_clk(i_clk), + .rst(rst_i), + .i_sck(i_sck), + .i_csn(i_csn), + .i_mosi(i_mosi), + .o_miso(o_miso), +///Mobeam Control Signals/// + .rd_revision_code(rd_revision_code), + .rst_mobeam(rst_mobeam), + .led_polarity(led_polarity), + .mobeam_start_stop(mobeam_start_stop), + .o_ba_mem_data(o_ba_mem_data), + .i_ba_mem_addr(i_ba_mem_addr), + .i_ba_mem_rd_en(i_ba_mem_rd_en), + .i_ba_mem_rd_clk(i_ba_mem_rd_clk), + .o_bsr_mem_data(o_bsr_mem_data), + .i_bsr_mem_addr(i_bsr_mem_addr), + .i_bsr_mem_rd_en(i_bsr_mem_rd_en), + .i_bsr_mem_rd_clk(i_bsr_mem_rd_clk) +// .i_config_reg_done(i_config_reg_done), +// .o_new_data_rd(o_new_data_rd), +// .o_data_strobe(o_bsr_data_strobe) +); +`endif + +`ifdef i2c +user_logic_control_reg_data_buf i2c_mobeam_logic_interface +( +///i2c Signal///// + .clk(clk_20mhz_g), + .rst(rst_i), + .scl(sclin_i), + .sdaout(sdaout_i), + .sdaIn(sdain_i), +///Mobeam Control Signals/// + .rd_revision_code(rd_revision_code), + .rst_mobeam(rst_mobeam), + .led_polarity(led_polarity), + .mobeam_start_stop(mobeam_start_stop), + .o_ba_mem_data(o_ba_mem_data), + .i_ba_mem_addr(i_ba_mem_addr), + .i_ba_mem_rd_en(i_ba_mem_rd_en), + .i_ba_mem_rd_clk(i_ba_mem_rd_clk), + .o_bsr_mem_data(o_bsr_mem_data), + .i_bsr_mem_addr(i_bsr_mem_addr), + .i_bsr_mem_rd_en(i_bsr_mem_rd_en), + .i_bsr_mem_rd_clk(i_bsr_mem_rd_clk) +// .i_config_reg_done(i_config_reg_done), +// .o_new_data_rd(o_new_data_rd), +// .o_data_strobe(o_bsr_data_strobe) +); +`endif + +//-------------------------------------------------------------- + //uart module instantiation +`ifdef uart + uart_top u_inst( + .i_sys_clk (clk_20mhz_g), + .i_sys_rst (rst_i), + .i_rx (i_rx), + //outputs + .o_tx (o_tx), + .o_done (done_i), + ///Mobeam Control Signals + .rd_revision_code (rd_revision_code), + .rst_mobeam (rst_mobeam), + .led_polarity (led_polarity), + .mobeam_start_stop (mobeam_start_stop), + .o_ba_mem_data (o_ba_mem_data), + .i_ba_mem_addr (i_ba_mem_addr), + .i_ba_mem_rd_en (i_ba_mem_rd_en), + .i_ba_mem_rd_clk (i_ba_mem_rd_clk), + .o_bsr_mem_data (o_bsr_mem_data), + .i_bsr_mem_addr (i_bsr_mem_addr), + .i_bsr_mem_rd_en (i_bsr_mem_rd_en), + .i_bsr_mem_rd_clk (i_bsr_mem_rd_clk) + ); +`endif +/////////////////////////////////////////////////////// + +////MobeamControlFSM////// +mobeam_control_fsm fsm_mobeam( + .sys_clk_i(clk_20mhz_g), + ///Mobeam Control Signals/// + .start_stop(mobeam_start_stop), + .rst_mobeam(rst_mobeam|rst_i), + //bsr memory signals + .bsr_mem_data(o_bsr_mem_data), + .bsr_mem_clk(i_bsr_mem_rd_clk), + .bsr_mem_addr(i_bsr_mem_addr), + .bsr_mem_rd_en(i_bsr_mem_rd_en), + + //ba memory signals + .ba_mem_data(o_ba_mem_data), + .ba_mem_clk(i_ba_mem_rd_clk), + .ba_mem_addr(i_ba_mem_addr), + .ba_mem_rd_en(i_ba_mem_rd_en), + + //TO LED DRIVER + .o_byte_data(barcode_array), + .shift_done(byte_done), + .bit_done(bit_done), + .txn_start(txn_start), + // .bsr_load_done(), + .bsr_bw(bar_width) + +); + +wire [7:0] bar_width, barcode_array; +/////LED Driver////// +led_driver led_drive_inst ( + .sys_clk(clk_20mhz_g), + .mobeam_start_stop(mobeam_start_stop), + .led_polarity(led_polarity), + .rst_n(~rst_i|rst_mobeam), + .txn_start(txn_start), + .bar_width(bar_width), + .barcode_array(barcode_array), + .byte_done(byte_done), + .bit_done(bit_done), + .drive_on(drive_on), + .oled(o_led) + //output dynamic_clk); + ); +//////////////////////////////////////// + +//////////////////////////////////////////////// +/////oled data verification///////////////////// + `ifdef SIM + +reg [7:0] capture_oled=0; +reg [7:0] oled_check=0; +integer i=8; +integer mon; + + +initial begin + mon = $fopen("monitor.txt","w"); //file to write +end + +always @(posedge i_clk) begin +// $fwrite(mon,"%h \n",oled_check); + if(txn_start && /*rise_reload_ba_reg_dtc*/fall_reload_ba_reg_dtc) begin + //if(led_polarity) + capture_oled[i]= o_led; + //else + // capture_oled[i]= ~o_led; + end + end + + always @( negedge fall_reload_ba_reg_dtc) begin + if(i==0) begin + oled_check=capture_oled; + + i<=7; + end + else + + i<=i-1; + end + + +always @(posedge i_clk) begin + if(txn_start && byte_done) + $fwrite(mon,"%h \n",oled_check); + end + + + reg q_reload_ba_reg; +always @(posedge i_clk or posedge rst_i) begin + if(rst_i) + q_reload_ba_reg<=0; + else + q_reload_ba_reg<=led_drive_inst.reload_ba_reg; + end +assign rise_reload_ba_reg_dtc=(~q_reload_ba_reg) && led_drive_inst.reload_ba_reg; + +assign fall_reload_ba_reg_dtc=(q_reload_ba_reg) && (~led_drive_inst.reload_ba_reg); + +`endif + +//end +/////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////// +`ifdef i2c + assign io_i2c_sda = (sdaout_i == 1'b0) ? 1'b0 : 1'bz; + assign sdain_i = io_i2c_sda; + assign sclin_i = io_i2c_scl; +`endif + + always @(posedge i_clk)begin + if(poweron_reset_count_i == 256)begin + poweron_reset_count_i <= 256; + end else begin + poweron_reset_count_i <= poweron_reset_count_i + 1; + end + end + + always @(posedge i_clk)begin + if(poweron_reset_count_i == 256)begin + poweron_reset_n_i <= 1; + end else begin + poweron_reset_n_i <= 0; + end + end + assign rst_i = ~poweron_reset_n_i; +endmodule // i2c_slave \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v new file mode 100644 index 000000000..e3b434533 --- /dev/null +++ b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v @@ -0,0 +1,138 @@ +//================================================================== +// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// ------------------------------------------------------------------ +// Copyright (c) 2014 by Lattice Semiconductor Corporation +// ALL RIGHTS RESERVED +// ------------------------------------------------------------------ +// +// Permission: +// +// Lattice SG Pte. Ltd. grants permission to use this code for use +// in synthesis for any Lattice programmable logic product. Other +// use of this code, including the selling or duplication of any +// portion is strictly prohibited. + +// +// Disclaimer: +// +// This VHDL or Verilog source code is intended as a design reference +// which illustrates how these types of functions can be implemented. +// It is the user's responsibility to verify their design for +// consistency and functionality through the use of formal +// verification methods. Lattice provides no warranty +// regarding the use or functionality of this code. +// +// -------------------------------------------------------------------- +// +// Lattice SG Pte. Ltd. +// 101 Thomson Road, United Square #07-02 +// Singapore 307591 +// +// +// TEL: 1-800-Lattice (USA and Canada) +// +65-6631-2000 (Singapore) +// +1-503-268-8001 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// + + +module user_logic_control_reg_data_buf +( +///i2c signal///// + clk, + rst, + scl, + sdaout, + sdaIn, +///mobeam control signals/// + rd_revision_code, + rst_mobeam, + led_polarity, + mobeam_start_stop, + o_ba_mem_data, + i_ba_mem_addr, + i_ba_mem_rd_en, + i_ba_mem_rd_clk, + o_bsr_mem_data, + i_bsr_mem_addr, + i_bsr_mem_rd_en, + i_bsr_mem_rd_clk +); +///////i2c signals interface/////// +input clk; +input rst; +inout scl; +output sdaout; +input sdaIn; +////////////////////////////////// +//mobeam control logic interface// +output [15:0] o_ba_mem_data; +input [7:0] i_ba_mem_addr; +input i_ba_mem_rd_en; +input i_ba_mem_rd_clk; +output rd_revision_code; +output rst_mobeam; +output mobeam_start_stop; +output [7:0] o_bsr_mem_data; +input [8:0] i_bsr_mem_addr; +input i_bsr_mem_rd_en; +input i_bsr_mem_rd_clk; + +output led_polarity; + +////////////////////////////////// +///////wires and reg declarations//// +wire[7:0]dataOut; +wire[7:0]regAddr; +wire writeEn; +wire readEn; +wire i2c_start; +wire[7:0]dataIn; +/////////////////////////////////////// +serialInterface i2cslavedatafsm(/*AUTOARG*/ + // Outputs + .dataOut(dataOut), + .regAddr(regAddr), + .sdaOut(sdaout), + .writeEn(writeEn), + .readEn(readEn), + .i2c_start(i2c_start), + // Inputs + .clk(clk), + .dataIn(dataIn), + .rst(rst), + .scl(scl), + .sdaIn(sdaIn) + ); + + + /*mobeam_reg_sets*/mobeam_i2c_reg_interface mobeam_registers( + .rst_i(rst), + .clk_i(clk), + //i2c slave interface signals/// + .i2c_master_to_slave_data_i(dataOut), + .i2c_slave_to_master_data_o(dataIn), + .i2c_slave_data_address_i(regAddr), + .wr_en_i(writeEn), + .rd_en_i(readEn), + .i2c_start_i(i2c_start), + //MoBeam control logic interface// + .rd_revision_code(rd_revision_code), + .rst_mobeam(rst_mobeam), + .led_polarity(led_polarity), + .mobeam_start_stop(mobeam_start_stop), + .o_ba_mem_data(o_ba_mem_data), + .i_ba_mem_addr(i_ba_mem_addr), + .i_ba_mem_rd_en(i_ba_mem_rd_en), + .i_ba_mem_rd_clk(i_ba_mem_rd_clk), + .o_bsr_mem_data(o_bsr_mem_data), + .i_bsr_mem_addr(i_bsr_mem_addr), + .i_bsr_mem_rd_en(i_bsr_mem_rd_en), + .i_bsr_mem_rd_clk(i_bsr_mem_rd_clk) + ); + +endmodule \ No newline at end of file diff --git a/fpga_flow/configs/lattice_benchmark.conf b/fpga_flow/configs/lattice_benchmark.conf new file mode 100644 index 000000000..7d270f6e3 --- /dev/null +++ b/fpga_flow/configs/lattice_benchmark.conf @@ -0,0 +1,31 @@ +# Standard Configuration Example +[dir_path] +script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/ +benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller +yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys +odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe +cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit +abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc +abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc +abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc +mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1 +m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net +mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2 +vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr +rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results +ace_path = OPENFPGAPATHKEYWORD/ace2/ace + +[flow_conf] +#Flow Types standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr +flow_type = yosys_vpr +vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml +mpack1_abc_stdlib = Not_Required +m2net_conf = Not_Required +mpack2_arch = Not_Required +power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml + +[csv_tags] +mpack1_tags = Global mapping efficiency: | efficiency: | occupancy wo buf: | efficiency wo buf: +mpack2_tags = BLE Number: | BLE Fill Rate: +vpr_tags = Netlist clb blocks: | Final critical path: | Total logic delay: | total net delay: | Total routing area: | Total used logic block area: | Total wirelength: | Packing took | Placement took | Routing took | Average net density: | Median net density: | Recommend no. of clock cycles: +vpr_power_tags = PB Types | Routing | Switch Box | Connection Box | Primitives | Interc Structures | lut6 | ff diff --git a/fpga_flow/run_benchmark.sh b/fpga_flow/run_benchmark.sh new file mode 100644 index 000000000..c039011b5 --- /dev/null +++ b/fpga_flow/run_benchmark.sh @@ -0,0 +1,71 @@ +#! /bin/bash +# Exit if error occurs +set -e +# Make sure a clear start +default_task='lattice_benchmark' +pwd_path="$PWD" +task_name=${1:-$default_task} # run task defined in argument else run default task +config_file="$PWD/configs/${task_name}.conf" +bench_txt="$PWD/benchmarks/List/${task_name}.txt" +rpt_file="$PWD/csv_rpts/fpga_spice/${task_name}.csv" +task_file="$PWD/vpr_fpga_spice_task_lists/${task_name}" + +verilog_path="${PWD}/regression_${task_name}" + +config_file_final=$(echo ${config_file/.conf/_final.conf}) + +# List of argument passed to FPGA flow +vpr_config_flags=( + '-N 10' + '-K 6' + '-ace_d 0.5' + '-multi_thread 1' + '-vpr_fpga_x2p_rename_illegal_port' + '-vpr_fpga_verilog' + '-vpr_fpga_bitstream_generator' + '-vpr_fpga_verilog_print_autocheck_top_testbench' + '-vpr_fpga_verilog_include_timing' + '-vpr_fpga_verilog_include_signal_init' + '-vpr_fpga_verilog_formal_verification_top_netlist' + '-fix_route_chan_width' + '-vpr_fpga_verilog_include_icarus_simulator' + '-power' +) +# vpr_config_flags+=("$@") # Append provided arguments + +#=============== Argument Sanity Check ===================== +#Check if script running in correct (OpenFPGA/fpga_flow) folder +if [[ $pwd_path != *"OpenFPGA/fpga_flow"* ]]; then + echo "Error : Execute script from OpenFPGA/fpga_flow project folder" + exitflag=1 +fi + +#Check if fconfig and benchmark_list file exists +for filepath in $config_file $bench_txt; do + if [ ! -f $filepath ]; then + echo "$filepath File not found!" + exitflag=1 + fi +done +if [ -n "$exitflag" ]; then + echo "Terminating script . . . . . . " + exit 1 +fi +#======================================================= +#======== Replace variables in config file ============= + +#Extract OpenFPGA Project Path and Escape +OPENFPGAPATHKEYWORD=$(echo "$(echo $pwd_path | sed 's/.OpenFPGA.*$//')/OpenFPGA" | sed 's/\//\\\//g') + +# Create final config file with replaced keywords replaced variables +sed 's/OPENFPGAPATHKEYWORD/'"${OPENFPGAPATHKEYWORD}"'/g' $config_file >$config_file_final + +#==================Clean result, change directory and execute =============== +cd ${pwd_path}/scripts + +# perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -vpr_fpga_verilog_dir $verilog_path $(echo "${vpr_config_flags[@]}") + +perl fpga_flow.pl -conf ${config_file_final} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power + +echo "Netlists successfully generated and simulated" +exit 0 diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 5291b508a..f1ea28fb6 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -15,20 +15,20 @@ use threads; use threads::shared; # Date -my $mydate = gmctime(); +my $mydate = gmctime(); # Current Path my $cwd = getcwd(); # Global Variants # input Option Hash -my %opt_h; +my %opt_h; my $opt_ptr = \%opt_h; # configurate file hash my %conf_h; my $conf_ptr = \%conf_h; # reports has my %rpt_h; -my $rpt_ptr = \%rpt_h; +my $rpt_ptr = \%rpt_h; # Benchmarks my @benchmark_names; @@ -37,7 +37,7 @@ my $benchmarks_ptr = \%benchmarks; my $verilog_benchmark; # Supported flows -my @supported_flows = ("standard", +my @supported_flows = ("standard", "vtr_mccl", "mccl", "mig_mccl", @@ -96,17 +96,17 @@ sub tab_print($ $ $) { my ($FILE,$str,$num_tab) = @_; my ($my_tab) = (" "); - + for (my $i = 0; $i < $num_tab; $i++) { print $FILE "$my_tab"; } - print $FILE "$str"; + print $FILE "$str"; } # Create paths if it does not exist. sub generate_path($) { - my ($mypath) = @_; + my ($mypath) = @_; if (!(-e "$mypath")) { mkpath "$mypath"; @@ -122,7 +122,7 @@ sub print_usage() print " fpga_flow [-options ]\n"; print " Mandatory options: \n"; print " -conf : specify the basic configuration files for fpga_flow\n"; - print " -benchmark : the configuration file contains benchmark file names\n"; + print " -benchmark : the configuration file contains benchmark file names\n"; print " -rpt : CSV file consists of data\n"; print " -N : N-LUT/Matrix\n"; print " Other Options:\n"; @@ -189,7 +189,7 @@ sub print_usage() exit(1); return 1; } - + sub spot_option($ $) { my ($start,$target) = @_; @@ -201,7 +201,7 @@ sub spot_option($ $) if ("found" eq $flag) { print "Error: Repeated Arguments!(IndexA: $arg_no,IndexB: $iarg)\n"; - &print_usage(); + &print_usage(); } else { @@ -212,7 +212,7 @@ sub spot_option($ $) } # return the arg_no if target is found # or return -1 when target is missing - return $arg_no; + return $arg_no; } # Specify in the input list, @@ -232,14 +232,14 @@ sub read_opt_into_hash($ $ $) { if ($ARGV[$argfd+1] =~ m/^-/) { - print "The next argument cannot start with '-'!\n"; + print "The next argument cannot start with '-'!\n"; print "it implies an option!\n"; } else { $opt_ptr->{"$opt_name\_val"} = $ARGV[$argfd+1]; $opt_ptr->{"$opt_name"} = "on"; - } + } } else { @@ -265,7 +265,7 @@ sub read_opt_into_hash($ $ $) print "Mandatory option: $opt_fact is missing!\n"; &print_usage(); } - } + } } return 1; } @@ -287,13 +287,13 @@ sub opts_read() print "Analyzing your options...\n"; # Read the options with internal options my $argfd; - # Check help fist + # Check help fist $argfd = &spot_option($cur_arg,"-help"); if (-1 != $argfd) { print "Help desk:\n"; &print_usage(); - } + } # Then Check the debug with highest priority $argfd = &spot_option($cur_arg,"-debug"); if (-1 != $argfd) @@ -330,8 +330,8 @@ sub opts_read() &read_opt_into_hash("multi_task","on","off"); &read_opt_into_hash("multi_thread","on","off"); &read_opt_into_hash("parse_results_only","off","off"); - - # VTR/VTR_MCCL/VTR_MIG_MCCL flow options + + # VTR/VTR_MCCL/VTR_MIG_MCCL flow options # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" &read_opt_into_hash("min_hard_adder_size","on","off"); &read_opt_into_hash("mem_size","on","off"); @@ -373,16 +373,16 @@ sub opts_read() # Regression test option &read_opt_into_hash("end_flow_with_test","off","off"); - &print_opts(); + &print_opts(); return 1; } - + # List the options sub print_opts() { - print "List your options\n"; - + print "List your options\n"; + while(my ($key,$value) = each(%opt_h)) {print "$key : $value\n";} @@ -410,8 +410,8 @@ sub read_line($ $) { $chars[0] =~ s/^(\s+)//g; $chars[0] =~ s/(\s+)$//g; - } - return $chars[0]; + } + return $chars[0]; } # Check each keywords has been defined in configuration file @@ -449,10 +449,10 @@ sub read_conf() while(defined($line = )) { chomp $line; - $post_line = &read_line($line,"#"); + $post_line = &read_line($line,"#"); if (defined($post_line)) { - if ($post_line =~ m/\[(\w+)\]/) + if ($post_line =~ m/\[(\w+)\]/) {$cur = $1;} elsif ("unknown" eq $cur) { @@ -462,13 +462,13 @@ sub read_conf() { $post_line =~ s/\s//g; @equation = split /=/,$post_line; - $conf_ptr->{$cur}->{$equation[0]}->{val} = $equation[1]; + $conf_ptr->{$cur}->{$equation[0]}->{val} = $equation[1]; } } } # Check these key words print "Read complete!\n"; - &check_keywords_conf(); + &check_keywords_conf(); print "Checking these keywords..."; print "Successfully\n"; close(CONF); @@ -489,17 +489,17 @@ sub read_benchmarks() if (defined($post_line)) { $post_line =~ s/\s+//g; my @tokens = split(",",$post_line); - # first is the benchmark name, + # first is the benchmark name, #the second is the channel width, if applicable if ($tokens[0]) { - $benchmark_names[$cur] = $tokens[0]; + $benchmark_names[$cur] = $tokens[0]; } else { die "ERROR: invalid definition for benchmarks!\n"; - } + } $benchmarks_ptr->{"$benchmark_names[$cur]"}->{fix_route_chan_width} = $tokens[1]; $cur++; - } - } + } + } print "Benchmarks(total $cur):\n"; foreach my $temp(@benchmark_names) {print "$temp\n";} @@ -510,19 +510,19 @@ sub read_benchmarks() # Input program path is like "~/program_dir/program_name" # We split it from the scalar sub split_prog_path($) -{ +{ my ($prog_path) = @_; my @path_elements = split /\//,$prog_path; my ($prog_dir,$prog_name); - - $prog_name = $path_elements[$#path_elements]; + + $prog_name = $path_elements[$#path_elements]; $prog_dir = $prog_path; $prog_dir =~ s/$prog_name$//g; - + return ($prog_dir,$prog_name); } -sub check_blif_type($) +sub check_blif_type($) { my ($blif) = @_; my ($line); @@ -541,7 +541,7 @@ sub check_blif_type($) # Check Options sub check_opts() { # Task 1: min_chan_width > 1 - if (("on" eq $opt_ptr->{min_route_chan_width}) + if (("on" eq $opt_ptr->{min_route_chan_width}) &&(1. > $opt_ptr->{min_route_chan_width_val})) { die "ERROR: Invalid -min_chan_width, should be at least 1.0!\n"; } @@ -581,7 +581,7 @@ sub run_abc_libmap($ $ $) my ($bm,$blif_out,$log) = @_; # Get ABC path my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_path}->{val}); - + chdir $abc_dir; my ($mpack1_stdlib) = ($conf_ptr->{flow_conf}->{mpack1_abc_stdlib}->{val}); # Run MPACK ABC @@ -622,7 +622,7 @@ sub run_rewrite_verilog($ $ $ $ $) { close($YOSYS_CMD_FH); # - # Create a local copy for the commands + # Create a local copy for the commands system("./$yosys_name $cmd_log > $log"); @@ -636,7 +636,7 @@ sub run_rewrite_verilog($ $ $ $ $) { return ($new_verilog); } -# Run yosys synthesis with ABC LUT mapping +# Run yosys synthesis with ABC LUT mapping sub run_yosys_fpgamap($ $ $ $) { my ($bm, $bm_path, $blif_out, $log) = @_; my ($cmd_log) = ($log); @@ -687,7 +687,7 @@ sub run_yosys_fpgamap($ $ $ $) { close($YOSYS_CMD_FH); # - # Create a local copy for the commands + # Create a local copy for the commands system("./$yosys_name $cmd_log > $log"); @@ -700,7 +700,7 @@ sub run_yosys_fpgamap($ $ $ $) { } # Run ABC by FPGA-oriented synthesis -sub run_abc_fpgamap($ $ $) +sub run_abc_fpgamap($ $ $) { my ($bm,$blif_out,$log) = @_; my ($cmd_log) = ($log."cmd"); @@ -735,7 +735,7 @@ sub run_abc_fpgamap($ $ $) close($ABC_CMD_FH); # - # Create a local copy for the commands + # Create a local copy for the commands system("./$abc_name -F $cmd_log > $log"); @@ -786,7 +786,7 @@ sub run_abc_bb_fpgamap($ $ $) { } # Run ABC Carry-chain premapping by FPGA-oriented synthesis -sub run_abc_mccl_fpgamap($ $ $) +sub run_abc_mccl_fpgamap($ $ $) { my ($bm,$blif_out,$log) = @_; # Get ABC path @@ -802,7 +802,7 @@ sub run_abc_mccl_fpgamap($ $ $) #my ($fpga_synthesis_method) = ("fpga"); # Name the intermediate file - my ($fadds_blif, $interm_blif) = ($blif_out, $blif_out); + my ($fadds_blif, $interm_blif) = ($blif_out, $blif_out); $fadds_blif =~ s/\.blif$/_fadds.blif/; $interm_blif =~ s/\.blif$/_interm.blif/; @@ -825,7 +825,7 @@ sub run_abc_mccl_fpgamap($ $ $) chdir $abc_bb_dir; print "INFO: entering abc_with_bb_support directory: $abc_bb_dir \n"; - # 3rd time: run abc_with_bb_support: read the pre-processed blif and do cleanup and recover + # 3rd time: run abc_with_bb_support: read the pre-processed blif and do cleanup and recover system("./$abc_bb_name -c \"read $interm_blif; $abc_seq_optimize sweep; write_hie $interm_blif $blif_out; quit;\" > $log"); if (!(-e $blif_out)) { @@ -836,7 +836,7 @@ sub run_abc_mccl_fpgamap($ $ $) } # Run ABC MIG Carry-chain premapping by FPGA-oriented synthesis -sub run_abc_mig_mccl_fpgamap($ $ $) +sub run_abc_mig_mccl_fpgamap($ $ $) { my ($bm,$blif_out,$log) = @_; # Get ABC path @@ -853,7 +853,7 @@ sub run_abc_mig_mccl_fpgamap($ $ $) #my ($fpga_synthesis_method) = ("fpga"); # Name the intermediate file - my ($fadds_blif, $interm_blif) = ($bm, $bm); + my ($fadds_blif, $interm_blif) = ($bm, $bm); $fadds_blif =~ s/\.blif$/_fadds.blif/; $interm_blif =~ s/\.blif$/_interm.blif/; @@ -877,7 +877,7 @@ sub run_abc_mig_mccl_fpgamap($ $ $) chdir $abc_bb_dir; print "INFO: entering abc_with_bb_support directory: $abc_bb_dir \n"; - # 3rd time: run abc_with_bb_support: read the pre-processed blif and do cleanup and recover + # 3rd time: run abc_with_bb_support: read the pre-processed blif and do cleanup and recover system("./$abc_bb_name -c \"read $interm_blif; $abc_seq_optimize sweep; write_hie $interm_blif $blif_out; quit;\" > $log"); if (!(-e $blif_out)) { @@ -887,7 +887,7 @@ sub run_abc_mig_mccl_fpgamap($ $ $) chdir $cwd; } -sub run_mpack1p5($ $ $ $ $) +sub run_mpack1p5($ $ $ $ $) { my ($blif_in,$blif_prefix,$matrix_size,$cell_size,$log) = @_; # Get MPACK path @@ -896,10 +896,10 @@ sub run_mpack1p5($ $ $ $ $) # Run MPACK system("./$mpack1_name $blif_in $blif_prefix -matrix_depth $matrix_size -matrix_width $matrix_size -cell_size $cell_size > $log"); chdir $cwd; - + } -sub run_mpack2($ $ $ $ $ $ $) +sub run_mpack2($ $ $ $ $ $ $) { my ($blif_in,$blif_out,$mpack2_arch,$net,$stats,$vpr_arch,$log) = @_; # Get MPACK path @@ -912,14 +912,14 @@ sub run_mpack2($ $ $ $ $ $ $) } # Extract Mpack2 stats -sub extract_mpack2_stats($ $ $) +sub extract_mpack2_stats($ $ $) { my ($tag,$bm,$mstats) = @_; my ($line); my @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack2_tags}->{val}; open (MSTATS, "< $mstats") or die "ERROR: Fail to open $mstats!\n"; while(defined($line = )) { - chomp $line; + chomp $line; $line =~ s/\s//g; foreach my $tmp(@keywords) { $tmp =~ s/\s//g; @@ -932,14 +932,14 @@ sub extract_mpack2_stats($ $ $) } # Extract Mpack1 stats -sub extract_mpack1_stats($ $ $) +sub extract_mpack1_stats($ $ $) { my ($tag,$bm,$mstats) = @_; my ($line); my @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack1_tags}->{val}; open (MSTATS, "< $mstats") or die "ERROR: Fail to open $mstats!\n"; while(defined($line = )) { - chomp $line; + chomp $line; $line =~ s/\s//g; foreach my $tmp(@keywords) { $tmp =~ s/\s//g; @@ -952,7 +952,7 @@ sub extract_mpack1_stats($ $ $) } # Black Box blif for ACE -sub black_box_blif($ $) +sub black_box_blif($ $) { my ($blif_in,$blif_out) = @_; my ($line); @@ -969,10 +969,10 @@ sub black_box_blif($ $) my $i1 = $i - 1; if ($i < $#components) { $line = $line."I[$i1]=$components[$i] "; - } + } else { $line = $line."I[$i1]=unconn "; - } + } } $line = $line."O[0]=$components[$#components] "; } @@ -994,18 +994,18 @@ sub black_box_blif($ $) } # Extract VPR Power Esti -sub extract_vpr_power_esti($ $ $ $) +sub extract_vpr_power_esti($ $ $ $) { my ($tag,$ace_vpr_blif,$bm,$type) = @_; my ($line,$tmp,$line_num); my @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; my ($vpr_power_stats) = $ace_vpr_blif; - - $line_num = 0; + + $line_num = 0; $vpr_power_stats =~ s/blif$/power/; open (VSTATS, "< $vpr_power_stats") or die "Fail to open $vpr_power_stats!\n"; while(defined($line = )) { - chomp $line; + chomp $line; $line_num++; if ($line =~ m/^Total/i) { my @power_info = split /\s+/,$line; @@ -1040,13 +1040,13 @@ sub extract_vpr_power_esti($ $ $ $) } # Extract AAPack stats -sub extract_aapack_stats($ $ $ $ $) +sub extract_aapack_stats($ $ $ $ $) { my ($tag,$bm,$vstats,$type,$keywords) = @_; my ($line,$tmp); open (VSTATS, "< $vstats") or die "Fail to open $vstats!\n"; while(defined($line = )) { - chomp $line; + chomp $line; #$line =~ s/\s//g; foreach my $tmpkw(@{$keywords}) { $tmp = $tmpkw; @@ -1062,13 +1062,13 @@ sub extract_aapack_stats($ $ $ $ $) } # Extract min_channel_width VPR stats -sub extract_min_chan_width_vpr_stats($ $ $ $ $ $) +sub extract_min_chan_width_vpr_stats($ $ $ $ $ $) { my ($tag,$bm,$vstats,$type,$min_route_chan_width,$parse_results) = @_; my ($line,$tmp, $min_chan_width, $chan_width_tag); my @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; - if ("on" eq $min_route_chan_width) { + if ("on" eq $min_route_chan_width) { $tmp = "Best routing used a channel width factor of"; $chan_width_tag = "min_route_chan_width"; } else { @@ -1079,7 +1079,7 @@ sub extract_min_chan_width_vpr_stats($ $ $ $ $ $) open (VSTATS, "< $vstats") or die "ERROR: Fail to open $vstats!\n"; while(defined($line = )) { - chomp $line; + chomp $line; if (($line =~ m/\s+([0-9]+)\s+of\s+type\s+names/i) &&(1 == $parse_results)) { $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} = $1; @@ -1087,7 +1087,7 @@ sub extract_min_chan_width_vpr_stats($ $ $ $ $ $) } $line =~ s/\s//g; if ($line =~ m/$tmp\s*([0-9E\-+.]+)/i) { - $min_chan_width = $1; + $min_chan_width = $1; $min_chan_width =~ s/\.$//; if (1 == $parse_results) { $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{$chan_width_tag} = $min_chan_width; @@ -1100,14 +1100,14 @@ sub extract_min_chan_width_vpr_stats($ $ $ $ $ $) # Extract VPR stats -sub extract_vpr_stats($ $ $ $) +sub extract_vpr_stats($ $ $ $) { my ($tag,$bm,$vstats,$type) = @_; my ($line,$tmp); my @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; open (VSTATS, "< $vstats") or die "Fail to open $vstats!\n"; while(defined($line = )) { - chomp $line; + chomp $line; if ($line =~ m/\s+([0-9]+)\s+of\s+type\s+names/i) { $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} = $1; $rpt_h{$tag}->{$bm}->{$opt_ptr->{N_val}}->{$type}->{LUTs} =~ s/\.$//; @@ -1213,7 +1213,7 @@ sub run_pro_blif($ $) { sub run_ace($ $ $ $) { my ($mpack_vpr_blif,$act_file,$ace_new_blif,$log) = @_; my ($ace_dir,$ace_name) = &split_prog_path($conf_ptr->{dir_path}->{ace_path}->{val}); - my ($ace_customized_opts) = (""); + my ($ace_customized_opts) = (""); if ("on" eq $opt_ptr->{ace_d}) { $ace_customized_opts .= " -d $opt_ptr->{ace_d_val}"; @@ -1222,7 +1222,7 @@ sub run_ace($ $ $ $) { if ("on" eq $opt_ptr->{ace_p}) { $ace_customized_opts .= " -p $opt_ptr->{ace_p_val}"; } - + print "Entering $ace_dir\n"; chdir $ace_dir; system("./$ace_name -b $mpack_vpr_blif -o $act_file -n $ace_new_blif -c clk $ace_customized_opts >> $log"); @@ -1234,7 +1234,7 @@ sub run_ace($ $ $ $) { print "Leaving $ace_dir\n"; chdir $cwd; -} +} # Run Icarus Verilog Simulation sub run_icarus_verilog($ $ $ $ $) @@ -1295,12 +1295,12 @@ sub run_netlists_verification($) return; } -sub run_std_vpr($ $ $ $ $ $ $ $ $) +sub run_std_vpr($ $ $ $ $ $ $ $ $) { my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_; my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); chdir $vpr_dir; - + my ($power_opts); if ("on" eq $opt_ptr->{power}) { $power_opts = "--power --activity_file $act_file --tech_properties $conf_ptr->{flow_conf}->{power_tech_xml}->{val}"; @@ -1409,17 +1409,17 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) } } - # FPGA Bitstream Generator Options + # FPGA Bitstream Generator Options if ("on" eq $opt_ptr->{vpr_fpga_bitstream_generator}) { $vpr_spice_opts = $vpr_spice_opts." --fpga_bitstream_generator"; } if (("on" eq $opt_ptr->{vpr_fpga_x2p_rename_illegal_port}) - || ("on" eq $opt_ptr->{vpr_fpga_spice}) + || ("on" eq $opt_ptr->{vpr_fpga_spice}) || ("on" eq $opt_ptr->{vpr_fpga_verilog})) { $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_rename_illegal_port"; } - + my ($other_opt) = (""); if ("on" eq $opt_ptr->{vpr_place_clb_pin_remap}) { $other_opt = "--place_clb_pin_remap "; @@ -1449,12 +1449,12 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) # foreach my $file (0..$#files){ # print "$files[$file]\t"; # } - 3 print "\n"; + # print "\n"; #} chdir $cwd; } -sub run_vpr_route($ $ $ $ $ $ $ $ $) +sub run_vpr_route($ $ $ $ $ $ $ $ $) { my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_; my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); @@ -1503,7 +1503,7 @@ sub run_vpr_route($ $ $ $ $ $ $ $ $) $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_rename_illegal_port"; } } - + my ($other_opt) = (""); if ("on" eq $opt_ptr->{vpr_max_router_iteration}) { $other_opt .= "--max_router_iterations $opt_ptr->{vpr_max_router_iteration_val} "; @@ -1517,7 +1517,7 @@ sub run_vpr_route($ $ $ $ $ $ $ $ $) chdir $cwd; } -sub run_mpack1_vpr($ $ $ $ $ $ $) +sub run_mpack1_vpr($ $ $ $ $ $ $) { my ($blif,$arch,$net,$place,$route,$log,$act_file) = @_; my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); @@ -1530,7 +1530,7 @@ sub run_mpack1_vpr($ $ $ $ $ $ $) chdir $cwd; } -sub run_mpack2_vpr($ $ $ $ $ $ $) +sub run_mpack2_vpr($ $ $ $ $ $ $) { my ($blif,$arch,$net,$place,$route,$min_chan_width,$log) = @_; my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); @@ -1554,19 +1554,19 @@ sub run_mpack2_vpr($ $ $ $ $ $ $) } -sub run_aapack($ $ $ $) +sub run_aapack($ $ $ $) { - my ($blif,$arch,$net,$aapack_log) = @_; + my ($blif,$arch,$net,$aapack_log) = @_; my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); - + chdir $vpr_dir; system("./$vpr_name $arch $blif --net_file $net --pack --timing_analysis off --nodisp > $aapack_log"); - chdir $cwd; + chdir $cwd; } -sub run_m2net_pack_arch($ $ $ $ $ $) +sub run_m2net_pack_arch($ $ $ $ $ $) { my ($m2net_conf,$mpack1_rpt,$pack_arch,$N,$I,$m2net_pack_arch_log) = @_; my ($m2net_dir,$m2net_name) = &split_prog_path($conf_ptr->{dir_path}->{m2net_path}->{val}); @@ -1576,9 +1576,9 @@ sub run_m2net_pack_arch($ $ $ $ $ $) system("perl $m2net_name -conf $m2net_conf -mpack1_rpt $mpack1_rpt -mode pack_arch -N $N -I $I -arch_file_pack $pack_arch > $m2net_pack_arch_log"); chdir $cwd; -} +} -sub run_m2net_m2net($ $ $ $ $) +sub run_m2net_m2net($ $ $ $ $) { my ($m2net_conf,$mpack1_rpt,$aapack_net,$vpr_net,$vpr_arch,$N,$I,$m2net_m2net_log) = @_; my ($m2net_dir,$m2net_name) = &split_prog_path($conf_ptr->{dir_path}->{m2net_path}->{val}); @@ -1590,11 +1590,11 @@ sub run_m2net_m2net($ $ $ $ $) if ("on" eq $opt_ptr->{power}) { $power_opt = "-power"; } - + system("perl $m2net_name -conf $m2net_conf -mpack1_rpt $mpack1_rpt -mode m2net -N $N -I $I -net_file_in $aapack_net -net_file_out $vpr_net -arch_file_vpr $vpr_arch $power_opt > $m2net_m2net_log"); chdir $cwd; -} +} sub run_cirkit_mig_mccl_map($ $ $) { my ($bm,$blif_out,$log) = @_; @@ -1603,8 +1603,8 @@ sub run_cirkit_mig_mccl_map($ $ $) { $bm_aig =~ s/blif$/aig/; $bm_v =~ s/blif$/v/; - $abc_cmd_log =~ s/\.blif$/_abc.cmd/g; - $cirkit_cmd_log =~ s/\.blif$/_cirkit.cmd/g; + $abc_cmd_log =~ s/\.blif$/_abc.cmd/g; + $cirkit_cmd_log =~ s/\.blif$/_cirkit.cmd/g; # Get ABC path my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_path}->{val}); @@ -1620,7 +1620,7 @@ sub run_cirkit_mig_mccl_map($ $ $) { } my ($fpga_synthesis_method) = ("if"); #my ($fpga_synthesis_method) = ("fpga"); - + my ($ABC_CMD_FH) = (FileHandle->new); if ($ABC_CMD_FH->open("> $abc_cmd_log")) { print "INFO: auto generating cmds for ABC ($abc_cmd_log) ...\n"; @@ -1672,13 +1672,13 @@ sub init_fpga_spice_task($) { } else { die "ERROR: fail to create task file ($task_file)!\n"; } - + print $TASKFH "# FPGA SPICE TASKs to run\n"; print $TASKFH "# Task line format:\n"; print $TASKFH "# ,,\n"; - # Close the file handler - close($TASKFH); + # Close the file handler + close($TASKFH); } # Print a line into task file which contains task info of FPGA SPICE. @@ -1692,7 +1692,7 @@ sub output_fpga_spice_task($ $ $ $) { } else { die "ERROR: fail to generate a line for task($benchmark) in task file ($task_file) ...\n"; } - + ($blif_path,$blif_prefix) = &split_prog_path($blif_name); $blif_prefix =~ s/\.blif$//; $spice_dir = $rpt_dir; @@ -1701,9 +1701,9 @@ sub output_fpga_spice_task($ $ $ $) { # Output a line print $TASKFH "# TaskInfo: $benchmark\n"; print $TASKFH "$benchmark,$blif_prefix,$spice_dir\n"; - - # Close the file handler - close($TASKFH); + + # Close the file handler + close($TASKFH); } sub run_ace_in_flow($ $ $ $ $ $ $) { @@ -1712,7 +1712,7 @@ sub run_ace_in_flow($ $ $ $ $ $ $) { if ("on" eq $opt_ptr->{power}) { if ("on" eq $opt_ptr->{black_box_ace}) { my ($tmp_blif) = ($prefix."_ace_new.blif"); - &black_box_blif($abc_blif_out,$tmp_blif); + &black_box_blif($abc_blif_out,$tmp_blif); &run_ace($tmp_blif,$act_file,$ace_new_blif ,$ace_log); } else { &run_ace($abc_blif_out,$act_file,$ace_new_blif,$ace_log); @@ -1740,7 +1740,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { if (-e $vpr_route) { `rm $vpr_route`; } - # Keep increase min_chan_width until route success + # Keep increase min_chan_width until route success # Extract data from VPR stats #&run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_log,$act_file); while (1) { @@ -1765,7 +1765,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { if (-e $vpr_route) { `rm $vpr_route`; } - # Keep increase min_chan_width until route success + # Keep increase min_chan_width until route success &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); while (1) { # TODO: Only run the routing stage @@ -1813,8 +1813,8 @@ sub run_mig_mccl_flow($ $ $ $) { my ($benchmark, $rpt_dir,$prefix); my ($cirkit_bm,$cirkit_blif_out,$cirkit_log,$cirkit_blif_out_bak); - $benchmark = $benchmark_file; - $benchmark =~ s/\.blif$//g; + $benchmark = $benchmark_file; + $benchmark =~ s/\.blif$//g; # Run Standard flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); @@ -1833,26 +1833,26 @@ sub run_mig_mccl_flow($ $ $ $) { $vpr_route = "$prefix"."vpr.route"; $vpr_log = "$prefix"."vpr.log"; $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - + &run_cirkit_mig_mccl_map($cirkit_bm,$cirkit_blif_out,$cirkit_log); if (!(-e $cirkit_blif_out)) { die "ERROR: Fail Cirkit for benchmark $cirkit_blif_out.\n"; } - + #`perl pro_blif.pl -i $abc_blif_out_bak -o $abc_blif_out`; #if (!(-e $abc_blif_out)) { # die "ERROR: Fail pro_blif.pl for benchmark $abc_blif_out.\n"; #} - + &run_ace_in_flow($prefix, $cirkit_blif_out, $act_file, $ace_new_blif, $ace_log); &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $cirkit_blif_out, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); - return; + return; } # Run Yosys-VPR flow -sub run_yosys_vpr_flow($ $ $ $ $) +sub run_yosys_vpr_flow($ $ $ $ $) { my ($tag,$benchmark_file,$vpr_arch,$flow_enhance, $parse_results) = @_; @@ -1862,7 +1862,7 @@ sub run_yosys_vpr_flow($ $ $ $ $) my @tokens = split('/', $benchmark_file); $benchmark = $tokens[0]; - # Prepare for the output folder + # Prepare for the output folder $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); @@ -1877,7 +1877,7 @@ sub run_yosys_vpr_flow($ $ $ $ $) &run_yosys_fpgamap($benchmark, $yosys_bm, $yosys_blif_out, $yosys_log); - # Files for ace + # Files for ace my ($act_file,$ace_new_blif,$ace_log, $corrected_ace_blif) = ("$rpt_dir/$benchmark".".act","$rpt_dir/$benchmark"."ace.blif","$prefix"."ace.log","$rpt_dir/$benchmark".".blif"); &run_ace_in_flow($prefix, $yosys_blif_out, $act_file, $ace_new_blif, $ace_log); @@ -1905,7 +1905,7 @@ sub run_yosys_vpr_flow($ $ $ $ $) } # Parse Yosys-VPR flow -sub parse_yosys_vpr_flow_results($ $ $ $) +sub parse_yosys_vpr_flow_results($ $ $ $) { my ($tag,$benchmark_file,$vpr_arch,$flow_enhance) = @_; @@ -1915,7 +1915,7 @@ sub parse_yosys_vpr_flow_results($ $ $ $) my @tokens = split('/', $benchmark_file); $benchmark = $tokens[0]; - # Prepare for the output folder + # Prepare for the output folder $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); @@ -1925,7 +1925,7 @@ sub parse_yosys_vpr_flow_results($ $ $ $) $yosys_blif_out = "$rpt_dir/$benchmark".".blif"; $yosys_log = "$prefix"."yosys.log"; - # Files for ace + # Files for ace my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); # Files for VPR @@ -1953,7 +1953,7 @@ sub parse_yosys_vpr_flow_results($ $ $ $) &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"on",1); &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); } - + # Extract data from VPR Power stats if ("on" eq $opt_ptr->{power}) { &extract_vpr_power_esti($tag,$yosys_blif_out,$benchmark,$opt_ptr->{K_val}); @@ -1961,7 +1961,7 @@ sub parse_yosys_vpr_flow_results($ $ $ $) # TODO: HOW TO DEAL WITH SPICE NETLISTS??? # Output a file contain information of SPICE Netlists - if ("on" eq $opt_ptr->{vpr_fpga_spice}) { + if ("on" eq $opt_ptr->{vpr_fpga_spice}) { &output_fpga_spice_task("$opt_ptr->{vpr_fpga_spice_val}"."_$tag.txt", $benchmark, $yosys_blif_out, $rpt_dir); } @@ -1970,7 +1970,7 @@ sub parse_yosys_vpr_flow_results($ $ $ $) } -sub run_standard_flow($ $ $ $ $) +sub run_standard_flow($ $ $ $ $) { my ($tag,$benchmark_file,$vpr_arch,$flow_enhance, $parse_results) = @_; my ($benchmark, $rpt_dir,$prefix); @@ -1978,8 +1978,8 @@ sub run_standard_flow($ $ $ $ $) my ($mpack_blif_out,$mpack_stats,$mpack_log); my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - $benchmark = $benchmark_file; - $benchmark =~ s/\.blif$//g; + $benchmark = $benchmark_file; + $benchmark =~ s/\.blif$//g; # Run Standard flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); @@ -1998,7 +1998,7 @@ sub run_standard_flow($ $ $ $ $) $vpr_log = "$prefix"."vpr.log"; $vpr_reroute_log = "$prefix"."vpr_reroute.log"; - + if ("abc_black_box" eq $flow_enhance) { my ($pre_abc_blif) = ("$prefix"."pre_abc.blif"); &run_pro_blif($abc_bm, $pre_abc_blif); @@ -2016,7 +2016,7 @@ sub run_standard_flow($ $ $ $ $) return; } -sub parse_standard_flow_results($ $ $ $) +sub parse_standard_flow_results($ $ $ $) { my ($tag,$benchmark_file,$vpr_arch,$flow_enhance) = @_; my ($rpt_dir,$prefix); @@ -2025,7 +2025,7 @@ sub parse_standard_flow_results($ $ $ $) my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.blif$//g; + $benchmark =~ s/\.blif$//g; # Run Standard flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); @@ -2033,7 +2033,7 @@ sub parse_standard_flow_results($ $ $ $) $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; $abc_blif_out = "$prefix"."abc.blif"; $abc_log = "$prefix"."abc.log"; - + if ("abc_black_box" eq $flow_enhance) { rename $abc_blif_out,"$abc_blif_out".".bak"; } elsif ("classic" eq $flow_enhance) { @@ -2063,7 +2063,7 @@ sub parse_standard_flow_results($ $ $ $) &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val},"on",1); &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); } - + # Extract data from VPR Power stats if ("on" eq $opt_ptr->{power}) { &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); @@ -2071,22 +2071,22 @@ sub parse_standard_flow_results($ $ $ $) # TODO: HOW TO DEAL WITH SPICE NETLISTS??? # Output a file contain information of SPICE Netlists - if ("on" eq $opt_ptr->{vpr_fpga_spice}) { + if ("on" eq $opt_ptr->{vpr_fpga_spice}) { &output_fpga_spice_task("$opt_ptr->{vpr_fpga_spice_val}"."_standard.txt", $benchmark, $abc_blif_out, $rpt_dir); } return; } -sub run_mpack2_flow($ $ $ $) +sub run_mpack2_flow($ $ $ $) { my ($tag,$benchmark_file,$mpack2_arch,$parse_results) = @_; my ($rpt_dir,$prefix); my ($abc_bm,$abc_blif_out,$abc_log,$abc_blif_out_bak); my ($mpack2_blif_out,$mpack2_vpr_net,$mpack2_stats,$mpack2_log,$mpack2_vpr_arch); my ($vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log,$act_file); - - # Check necessary options + + # Check necessary options if (!($opt_ptr->{N_val})) { die "ERROR: (mpack2_flow) -N should be specified!\n"; } @@ -2095,7 +2095,7 @@ sub run_mpack2_flow($ $ $ $) } my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.blif$//g; + $benchmark =~ s/\.blif$//g; # Run MPACK2-oriented flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); @@ -2124,7 +2124,7 @@ sub run_mpack2_flow($ $ $ $) if (1 == $parse_results) { &extract_mpack2_stats($tag,$benchmark,$mpack2_stats); } - + # RUN VPR $vpr_place = "$prefix"."vpr.place"; $vpr_route = "$prefix"."vpr.route"; @@ -2139,10 +2139,10 @@ sub run_mpack2_flow($ $ $ $) if (0 != $min_chan_width%2) { $min_chan_width += 1; } - + # Remove previous route results `rm $vpr_route`; - # Keep increase min_chan_width until route success + # Keep increase min_chan_width until route success # Extract data from VPR stats while (1) { &run_vpr_route($mpack2_blif_out,$benchmark,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,$min_chan_width,$vpr_reroute_log,$act_file); @@ -2166,7 +2166,7 @@ sub run_mpack2_flow($ $ $ $) if (-e $vpr_route) { `rm $vpr_route`; } - # Keep increase min_chan_width until route success + # Keep increase min_chan_width until route success # Extract data from VPR stats &run_mpack2_vpr($mpack2_blif_out,$mpack2_vpr_arch,$mpack2_vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log); while (1) { @@ -2201,15 +2201,15 @@ sub run_mpack2_flow($ $ $ $) return; } -sub parse_mpack2_flow_results($ $ $) +sub parse_mpack2_flow_results($ $ $) { my ($tag,$benchmark_file,$mpack2_arch) = @_; my ($rpt_dir,$prefix); my ($abc_bm,$abc_blif_out,$abc_log); my ($mpack2_blif_out,$mpack2_vpr_net,$mpack2_stats,$mpack2_log,$mpack2_vpr_arch); my ($vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - - # Check necessary options + + # Check necessary options if (!($opt_ptr->{N_val})) { die "ERROR: (mpack2_flow) -N should be specified!\n"; } @@ -2218,7 +2218,7 @@ sub parse_mpack2_flow_results($ $ $) } my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.blif$//g; + $benchmark =~ s/\.blif$//g; # Run MPACK2-oriented flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); @@ -2237,7 +2237,7 @@ sub parse_mpack2_flow_results($ $ $) $mpack2_vpr_arch = "$prefix"."mpack2_vpr_arch.xml"; # Extract data from MPACK stats &extract_mpack2_stats($tag,$benchmark,$mpack2_stats); - + # RUN VPR $vpr_place = "$prefix"."vpr.place"; $vpr_route = "$prefix"."vpr.route"; @@ -2262,11 +2262,11 @@ sub parse_mpack2_flow_results($ $ $) &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "on", 1); &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); } - + return; } -sub run_mpack1_flow($ $ $) +sub run_mpack1_flow($ $ $) { my ($tag,$benchmark_file, $parse_results) = @_; my ($rpt_dir,$prefix); @@ -2283,7 +2283,7 @@ sub run_mpack1_flow($ $ $) } my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.blif$//g; + $benchmark =~ s/\.blif$//g; # Run MPACK1-oriented flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); @@ -2300,12 +2300,12 @@ sub run_mpack1_flow($ $ $) my ($mpack1_rpt) = ("$prefix"."_mapped.net"); my ($mpack1_log) = ("$prefix"."mpack1p5.log"); &run_mpack1p5("$abc_blif_out","$prefix",$M_val,$cell_size,$mpack1_log); - + # Extract data from MPACK stats if (1 == $parse_results) { &extract_mpack1_stats($tag,$benchmark,$mpack1_log); } - + # Generate Architecture XML my ($aapack_arch) = ("$prefix"."aapack_arch.xml"); my ($m2net_pack_arch_log) = ("$prefix"."m2net_pack_arch.log"); @@ -2319,13 +2319,13 @@ sub run_mpack1_flow($ $ $) if (1 == $parse_results) { &extract_aapack_stats($tag,$benchmark,$aapack_log,$M_val,\@aapack_stats); } - + $vpr_net = "$prefix"."mpack.net"; $vpr_place = "$prefix"."vpr.place"; $vpr_route = "$prefix"."vpr.route"; $vpr_log = "$prefix"."vpr.log"; - # Run m2net.pl + # Run m2net.pl my ($vpr_arch) = ("$prefix"."vpr_arch.xml"); my ($m2net_m2net_log) = ("$prefix"."m2net_m2net.log"); &run_m2net_m2net($m2net_conf,$mpack1_rpt,$aapack_net,$vpr_net,$vpr_arch,$N_val,$I_val,$m2net_m2net_log); @@ -2340,7 +2340,7 @@ sub run_mpack1_flow($ $ $) if (!(-e $vpr_route)) { die "ERROR: Route Fail for $mpack1_vpr_blif_out!\n"; } - + # Extract data from VPR stats if (1 == $parse_results) { &extract_vpr_stats($tag,$benchmark,$vpr_log,$M_val); @@ -2368,7 +2368,7 @@ sub parse_mpack1_flow_results($ $) { } my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.blif$//g; + $benchmark =~ s/\.blif$//g; # Run MPACK1-oriented flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); @@ -2381,10 +2381,10 @@ sub parse_mpack1_flow_results($ $) { my ($mpack1_vpr_blif_out) = ("$prefix"."_formatted.blif"); my ($mpack1_rpt) = ("$prefix"."_mapped.net"); my ($mpack1_log) = ("$prefix"."mpack1p5.log"); - + # Extract data from MPACK stats &extract_mpack1_stats($tag,$benchmark,$mpack1_log); - + # Generate Architecture XML my ($aapack_arch) = ("$prefix"."aapack_arch.xml"); my ($m2net_pack_arch_log) = ("$prefix"."m2net_pack_arch.log"); @@ -2394,13 +2394,13 @@ sub parse_mpack1_flow_results($ $) { my ($aapack_net) = ("$prefix"."aapack.net"); my @aapack_stats = ("MATRIX"); &extract_aapack_stats($tag,$benchmark,$aapack_log,$M_val,\@aapack_stats); - + $vpr_net = "$prefix"."mpack.net"; $vpr_place = "$prefix"."vpr.place"; $vpr_route = "$prefix"."vpr.route"; $vpr_log = "$prefix"."vpr.log"; - # Run m2net.pl + # Run m2net.pl my ($vpr_arch) = ("$prefix"."vpr_arch.xml"); my ($m2net_m2net_log) = ("$prefix"."m2net_m2net.log"); my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace_new.blif","$prefix"."ace.log"); @@ -2423,24 +2423,24 @@ sub run_vtr_flow($ $ $ $) { # The input of VTR flow is verilog file my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.v$//g; - # Run Verilog To Routiing flow + $benchmark =~ s/\.v$//g; + # Run Verilog To Routiing flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); - # ODIN II output blif + # ODIN II output blif $odin2_verilog = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; # ODIN II config XML $odin2_config = "$prefix"."odin2_config.xml"; - $odin2_log = "$prefix"."odin2.log"; - # ODIN II output blif + $odin2_log = "$prefix"."odin2.log"; + # ODIN II output blif $abc_bm = "$prefix"."odin2.blif"; - # ABC II output blif + # ABC II output blif $abc_blif_out = "$prefix"."abc.blif"; $abc_blif_out_bak = "$prefix"."abc_bak.blif"; $abc_log = "$prefix"."abc.log"; - # Initialize min_hard_adder_size + # Initialize min_hard_adder_size $min_hard_adder_size = 1; # Default value if ("on" eq $opt_ptr->{min_hard_adder_size}) { if (1 > $opt_ptr->{min_hard_adder_size_val}) { @@ -2451,12 +2451,12 @@ sub run_vtr_flow($ $ $ $) { } # TODO: Initialize the mem_size by parsing the ARCH XML? if ("on" eq $opt_ptr->{mem_size}) { - $mem_size = $opt_ptr->{mem_size_val}; + $mem_size = $opt_ptr->{mem_size_val}; } else { die "ERROR: -mem_size is mandatory when vtr flow is chosen!\n"; } # Auto-generate a configuration XML for ODIN2 - &gen_odin2_config_xml($odin2_config, $odin2_verilog, $abc_bm, $vpr_arch, $mem_size, $min_hard_adder_size); + &gen_odin2_config_xml($odin2_config, $odin2_verilog, $abc_bm, $vpr_arch, $mem_size, $min_hard_adder_size); # RUN ODIN II &run_odin2($odin2_config, "off", $odin2_log); @@ -2464,12 +2464,12 @@ sub run_vtr_flow($ $ $ $) { die "ERROR: Fail ODIN II for benchmark $benchmark.\n"; } - # RUN ABC + # RUN ABC &run_abc_bb_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); &run_pro_blif($abc_blif_out_bak, $abc_blif_out); - # Run ABC + # Run ABC my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); &run_ace_in_flow($prefix, $abc_blif_out,$act_file,$ace_new_blif,$ace_log); @@ -2493,22 +2493,22 @@ sub parse_vtr_flow_results($ $ $) { my ($mpack_blif_out,$mpack_stats,$mpack_log); my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - $benchmark =~ s/\.v$//g; + $benchmark =~ s/\.v$//g; # Run Standard flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); - # ODIN II output blif + # ODIN II output blif $odin2_verilog = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; # ODIN II config XML $odin2_config = "$prefix"."odin2_config.xml"; - $odin2_log = "$prefix"."odin2.log"; - # ODIN II output blif + $odin2_log = "$prefix"."odin2.log"; + # ODIN II output blif $abc_bm = "$prefix"."odin2.blif"; - # ABC output blif + # ABC output blif $abc_blif_out = "$prefix"."abc.blif"; $abc_log = "$prefix"."abc.log"; - + rename $abc_blif_out,"$abc_blif_out".".bak"; my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); @@ -2536,7 +2536,7 @@ sub parse_vtr_flow_results($ $ $) { &extract_min_chan_width_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}, "on", 1); &extract_vpr_stats($tag,$benchmark,$vpr_log,$opt_ptr->{K_val}); } - + # Extract data from VPR Power stats if ("on" eq $opt_ptr->{power}) { &extract_vpr_power_esti($tag,$abc_blif_out,$benchmark,$opt_ptr->{K_val}); @@ -2544,17 +2544,17 @@ sub parse_vtr_flow_results($ $ $) { # TODO: HOW TO DEAL WITH SPICE NETLISTS??? # Output a file contain information of SPICE Netlists - if ("on" eq $opt_ptr->{vpr_fpga_spice}) { + if ("on" eq $opt_ptr->{vpr_fpga_spice}) { &output_fpga_spice_task("$opt_ptr->{vpr_fpga_spice_val}"."_vtr.txt", $benchmark, $abc_blif_out, $rpt_dir); } return; } -# VTR_MCCL_flow: -# Differences from vtr_flow: +# VTR_MCCL_flow: +# Differences from vtr_flow: # 1. Need to turn off the carry-chain support for ODIN II -# 2. Use Carry-chain detection and Carry-chain LUTs pre-mapping in ABC scripts +# 2. Use Carry-chain detection and Carry-chain LUTs pre-mapping in ABC scripts sub run_vtr_mccl_flow($ $ $ $) { my ($tag,$benchmark_file,$vpr_arch,$parse_results) = @_; my ($rpt_dir,$prefix); @@ -2565,24 +2565,24 @@ sub run_vtr_mccl_flow($ $ $ $) { # The input of VTR flow is verilog file my ($benchmark) = ($benchmark_file); - $benchmark =~ s/\.v$//g; - # Run Verilog To Routiing flow + $benchmark =~ s/\.v$//g; + # Run Verilog To Routiing flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; &generate_path($rpt_dir); - # ODIN II output blif + # ODIN II output blif $odin2_verilog = "$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".v"; $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; # ODIN II config XML $odin2_config = "$prefix"."odin2_config.xml"; - $odin2_log = "$prefix"."odin2.log"; - # ODIN II output blif + $odin2_log = "$prefix"."odin2.log"; + # ODIN II output blif $abc_bm = "$prefix"."odin2.blif"; - # ABC II output blif + # ABC II output blif $abc_blif_out = "$prefix"."abc.blif"; $abc_blif_out_bak = "$prefix"."abc_bak.blif"; $abc_log = "$prefix"."abc.log"; - # Initialize min_hard_adder_size + # Initialize min_hard_adder_size $min_hard_adder_size = 1; # Default value if ("on" eq $opt_ptr->{min_hard_adder_size}) { if (1 > $opt_ptr->{min_hard_adder_size_val}) { @@ -2593,12 +2593,12 @@ sub run_vtr_mccl_flow($ $ $ $) { } # TODO: Initialize the mem_size by parsing the ARCH XML? if ("on" eq $opt_ptr->{mem_size}) { - $mem_size = $opt_ptr->{mem_size_val}; + $mem_size = $opt_ptr->{mem_size_val}; } else { die "ERROR: -mem_size is mandatory when vtr flow is chosen!\n"; } # Auto-generate a configuration XML for ODIN2 - &gen_odin2_config_xml($odin2_config, $odin2_verilog, $abc_bm, $vpr_arch, $mem_size, $min_hard_adder_size); + &gen_odin2_config_xml($odin2_config, $odin2_verilog, $abc_bm, $vpr_arch, $mem_size, $min_hard_adder_size); if ("on" eq $opt_ptr->{odin2_carry_chain_support}) { $odin2_carry_chain_support = ("on"); @@ -2610,7 +2610,7 @@ sub run_vtr_mccl_flow($ $ $ $) { die "ERROR: Fail ODIN II for benchmark $benchmark.\n"; } - # RUN ABC + # RUN ABC &run_abc_mccl_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); &run_pro_blif($abc_blif_out_bak, $abc_blif_out); @@ -2627,11 +2627,11 @@ sub run_vtr_mccl_flow($ $ $ $) { # Run VPR &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $abc_blif_out, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); - + return; } -sub run_mccl_flow($ $ $ $ $) +sub run_mccl_flow($ $ $ $ $) { my ($tag,$benchmark_file,$vpr_arch,$flow_enhance, $parse_results) = @_; my ($benchmark, $rpt_dir,$prefix); @@ -2639,7 +2639,7 @@ sub run_mccl_flow($ $ $ $ $) my ($mpack_blif_out,$mpack_stats,$mpack_log); my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); - $benchmark = $benchmark_file; + $benchmark = $benchmark_file; $benchmark =~ s/\.v$//g; # We use verilog format in mccl # Run Standard flow $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; @@ -2649,8 +2649,8 @@ sub run_mccl_flow($ $ $ $ $) $abc_blif_out = "$prefix"."abc.blif"; $abc_blif_out_bak = "$prefix"."abc_bak.blif"; $abc_log = "$prefix"."abc.log"; - - # RUN ABC + + # RUN ABC &run_abc_mccl_fpgamap($abc_bm,$abc_blif_out_bak,$abc_log); &run_pro_blif($abc_blif_out_bak, $abc_blif_out); @@ -2671,10 +2671,10 @@ sub run_mccl_flow($ $ $ $ $) return; } -sub run_benchmark_selected_flow($ $ $) +sub run_benchmark_selected_flow($ $ $) { my ($flow_type,$benchmark, $parse_results) = @_; - + if ($flow_type eq "standard") { &run_standard_flow("standard",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"classic", $parse_results); } elsif ($flow_type eq "mpack2") { @@ -2695,14 +2695,14 @@ sub run_benchmark_selected_flow($ $ $) &run_yosys_vpr_flow("yosys_vpr",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, "classic", $parse_results); } else { die "ERROR: unsupported flow type ($flow_type) is chosen!\n"; - } + } return; } sub parse_benchmark_selected_flow($ $) { my ($flow_type,$benchmark) = @_; - + if ($flow_type eq "standard") { &parse_standard_flow_results("standard",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"classic"); } elsif ($flow_type eq "mpack2") { @@ -2723,7 +2723,7 @@ sub parse_benchmark_selected_flow($ $) { &parse_yosys_vpr_flow_results("yosys_vpr",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"abc_black_box"); } else { die "ERROR: unsupported flow type ($flow_type) is chosen!\n"; - } + } } # Run EDA flow @@ -2757,7 +2757,7 @@ sub multitask_run_flows() { next; } print "FLOW TO RUN: $flow_to_run, Benchmark: $benchmark\n"; - # Mutli thread push + # Mutli thread push if ("on" eq $opt_ptr->{multi_task}) { my $pid = fork(); if (defined $pid) { @@ -2795,10 +2795,10 @@ sub multithread_run_flows($) { die "ERROR: cannot use threads package in Perl! Please check the installation of package...\n"; } - # Lauch threads up to the limited number of threads number + # Lauch threads up to the limited number of threads number if ($num_threads < 2) { $num_threads = 2; - } + } my ($num_thread_running) = (0); # Iterate until all the tasks has been assigned, finished @@ -2819,26 +2819,26 @@ sub multithread_run_flows($) { } # We have a thread id, check running or finished if ($thr_id->is_running()) { - # Update status + # Update status $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "running"; - } + } if ($thr_id->is_joinable()) { $num_thread_running--; $thr_id->join(); # Join the thread results - # Update status + # Update status $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; print "FLOW: $flow_to_run, Benchmark: $benchmark, Finished!\n"; - print "INFO: current running thread number = $num_thread_running.\n"; + print "INFO: current running thread number = $num_thread_running.\n"; &print_jobs_status(); - } - } else { + } + } else { # Not start a thread for this task, if (($num_thread_running == $num_threads) ||($num_thread_running > $num_threads)) { next; } #if there are still threads available, we try to start one - # Mutli thread push + # Mutli thread push my $thr_new = threads->create(\&run_benchmark_selected_flow,$flow_to_run,$benchmark, 0); # We have a valid thread... if ($thr_new) { @@ -2849,7 +2849,7 @@ sub multithread_run_flows($) { $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "running"; $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{thread_id} = $thr_new; $num_thread_running++; - print "INFO: current running thread number = $num_thread_running.\n"; + print "INFO: current running thread number = $num_thread_running.\n"; &print_jobs_status(); } # Check if it is detached... @@ -2859,14 +2859,14 @@ sub multithread_run_flows($) { $thr_new->join(); # Join the thread results $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status} = "done"; print "FLOW: $flow_to_run, Benchmark: $benchmark, Finished!\n"; - print "INFO: current running thread number = $num_thread_running.\n"; + print "INFO: current running thread number = $num_thread_running.\n"; &print_jobs_status(); } } else { - # Fail to create a new thread, wait... + # Fail to create a new thread, wait... print "INFO: Fail to alloc a new thread, wait...!"; } - } + } } } } @@ -2874,7 +2874,7 @@ sub multithread_run_flows($) { &parse_flows_benchmarks_results(); - return; + return; } sub parse_flows_benchmarks_results() { @@ -2888,18 +2888,18 @@ sub parse_flows_benchmarks_results() { } } } - - return; + + return; } sub print_jobs_status() { - my ($num_jobs_running, $num_jobs_to_run, $num_jobs_finish, $num_jobs) = (0, 0, 0, 0); - + my ($num_jobs_running, $num_jobs_to_run, $num_jobs_finish, $num_jobs) = (0, 0, 0, 0); + foreach my $benchmark(@benchmark_names) { foreach my $flow_to_run(@supported_flows) { if ("on" eq $selected_flows{$flow_to_run}->{flow_status}) { # Count the number of jobs - $num_jobs++; + $num_jobs++; # Count to do jobs if ("off" eq $selected_flows{$flow_to_run}->{benchmarks}->{$benchmark}->{status}) { $num_jobs_to_run++; @@ -2929,7 +2929,7 @@ sub print_jobs_status() { print " +num_jobs_finish($num_jobs_finish)\n"; die " +num_jobs_to_run($num_jobs_to_run)\n"; } - return; + return; } sub check_all_flows_all_benchmarks_done() { @@ -2960,13 +2960,13 @@ sub check_flow_all_benchmarks_done($) { if ("done" ne $selected_flows{$flow_name}->{benchmarks}->{$bm}->{status}) { $all_done = 0; last; - } + } } - + return $all_done; } -sub gen_csv_rpt_vtr_flow($ $) +sub gen_csv_rpt_vtr_flow($ $) { my ($tag,$CSVFH) = @_; my ($tmp,$ikw,$tmpkw); @@ -2974,7 +2974,7 @@ sub gen_csv_rpt_vtr_flow($ $) my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); # Print out Standard Stats First - print $CSVFH "$tag"; + print $CSVFH "$tag"; print $CSVFH ",LUTs"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",min_route_chan_width"; @@ -3000,7 +3000,7 @@ sub gen_csv_rpt_vtr_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.v$//g; + $tmp =~ s/\.v$//g; print $CSVFH "$tmp"; print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; if ("on" eq $opt_ptr->{min_route_chan_width}) { @@ -3015,14 +3015,14 @@ sub gen_csv_rpt_vtr_flow($ $) @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; } if ("on" eq $opt_ptr->{power}) { @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; } print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; @@ -3033,7 +3033,7 @@ sub gen_csv_rpt_vtr_flow($ $) } } -sub gen_csv_rpt_yosys_vpr_flow($ $) +sub gen_csv_rpt_yosys_vpr_flow($ $) { my ($tag,$CSVFH) = @_; my ($tmp,$ikw,$tmpkw); @@ -3041,7 +3041,7 @@ sub gen_csv_rpt_yosys_vpr_flow($ $) my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); # Print out Standard Stats First - print $CSVFH "$tag"; + print $CSVFH "$tag"; print $CSVFH ",LUTs"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",min_route_chan_width"; @@ -3083,14 +3083,14 @@ sub gen_csv_rpt_yosys_vpr_flow($ $) @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; } if ("on" eq $opt_ptr->{power}) { @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; } print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; @@ -3101,7 +3101,7 @@ sub gen_csv_rpt_yosys_vpr_flow($ $) } } -sub gen_csv_rpt_standard_flow($ $) +sub gen_csv_rpt_standard_flow($ $) { my ($tag,$CSVFH) = @_; my ($tmp,$ikw,$tmpkw); @@ -3109,7 +3109,7 @@ sub gen_csv_rpt_standard_flow($ $) my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); # Print out Standard Stats First - print $CSVFH "$tag"; + print $CSVFH "$tag"; print $CSVFH ",LUTs"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",min_route_chan_width"; @@ -3135,7 +3135,7 @@ sub gen_csv_rpt_standard_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; + $tmp =~ s/\.blif$//g; print $CSVFH "$tmp"; print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; if ("on" eq $opt_ptr->{min_route_chan_width}) { @@ -3150,14 +3150,14 @@ sub gen_csv_rpt_standard_flow($ $) @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; } if ("on" eq $opt_ptr->{power}) { @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; } print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; @@ -3168,7 +3168,7 @@ sub gen_csv_rpt_standard_flow($ $) } } -sub gen_csv_rpt_mpack2_flow($ $) +sub gen_csv_rpt_mpack2_flow($ $) { my ($tag,$CSVFH) = @_; my ($tmp,$ikw,$tmpkw); @@ -3176,7 +3176,7 @@ sub gen_csv_rpt_mpack2_flow($ $) my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); # Print out Mpack stats Second - print $CSVFH "$tag"; + print $CSVFH "$tag"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",min_route_chan_width"; print $CSVFH ",fix_route_chan_width"; @@ -3185,7 +3185,7 @@ sub gen_csv_rpt_mpack2_flow($ $) } else { print $CSVFH ",min_route_chan_width"; } - + @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack2_tags}->{val}; #foreach $tmpkw(@keywords) { for($ikw=0; $ikw < ($#keywords+1); $ikw++) { @@ -3207,7 +3207,7 @@ sub gen_csv_rpt_mpack2_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; + $tmp =~ s/\.blif$//g; print $CSVFH "$tmp"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; @@ -3221,20 +3221,20 @@ sub gen_csv_rpt_mpack2_flow($ $) @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack2_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; } @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{$keywords[$ikw]}"; } if ("on" eq $opt_ptr->{power}) { @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{$keywords[$ikw]}"; } print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{total}"; @@ -3245,7 +3245,7 @@ sub gen_csv_rpt_mpack2_flow($ $) } } -sub gen_csv_rpt_mpack1_flow($ $) +sub gen_csv_rpt_mpack1_flow($ $) { my ($tag,$CSVFH) = @_; my ($tmp,$ikw,$tmpkw); @@ -3253,7 +3253,7 @@ sub gen_csv_rpt_mpack1_flow($ $) my ($N_val,$M_val) = ($opt_ptr->{N_val},$opt_ptr->{M_val}); # Print out Mpack stats Second - print $CSVFH "$tag"; + print $CSVFH "$tag"; print $CSVFH ",MATRIX"; @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { @@ -3274,27 +3274,27 @@ sub gen_csv_rpt_mpack1_flow($ $) print $CSVFH "\n"; # Check log/stats one by one foreach $tmp(@benchmark_names) { - $tmp =~ s/\.blif$//g; + $tmp =~ s/\.blif$//g; print $CSVFH "$tmp"; #foreach $tmpkw(@keywords) { print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{MATRIX}"; @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{$keywords[$ikw]}"; } @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{$keywords[$ikw]}"; } # Print Power Results @keywords = split /\|/,$conf_ptr->{csv_tags}->{vpr_power_tags}->{val}; for($ikw=0; $ikw < ($#keywords+1); $ikw++) { $tmpkw = $keywords[$ikw]; - $tmpkw =~ s/\s//g; + $tmpkw =~ s/\s//g; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{$keywords[$ikw]}"; } print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{total}"; @@ -3305,7 +3305,7 @@ sub gen_csv_rpt_mpack1_flow($ $) } sub init_selected_flows() { - # For each flow type, mark the status to off + # For each flow type, mark the status to off foreach my $flow_type(@supported_flows) { $selected_flows{$flow_type}->{flow_status} = "off"; # For each benchmark, init the status to "off" @@ -3345,7 +3345,7 @@ sub mark_flows_benchmarks() { } } -sub gen_csv_rpt($) +sub gen_csv_rpt($) { my ($csv_file) = @_; @@ -3454,7 +3454,7 @@ sub main() &mark_flows_benchmarks(); &parse_flows_benchmarks_results(); } else { - &remove_designs(); + &remove_designs(); &plan_run_flows(); } &gen_csv_rpt($opt_ptr->{rpt_val}); diff --git a/fpga_flow/scripts/rewrite_path_in_file.pl b/fpga_flow/scripts/rewrite_path_in_file.pl deleted file mode 100644 index b65868f60..000000000 --- a/fpga_flow/scripts/rewrite_path_in_file.pl +++ /dev/null @@ -1,138 +0,0 @@ -#!usr/bin/perl -w -use strict; -use Cwd; -#use Shell; -use FileHandle; -#Use the time -use Time::gmtime; - -my $arch_file; -my $new_arch_file; -my $overwrite = "TRUE"; -my $keyword = "OPENFPGAPATHKEYWORD"; -my $default_keyword = "TRUE"; -my $change_to; -my $folder_top = "OpenFPGA"; - -sub print_usage() -{ - print "Usage:\n"; - print " perl [-options]\n"; - print " Options:(Mandatory!)\n"; - print " -i \n"; - print " Options:(Optional)\n"; - print " -o \n"; - print " -k \n"; - print "\n"; - return; -} - -sub opts_read() -{ - if ($#ARGV == -1){ - print "Error: Not enough input argument!\n"; - &print_usage(); - exit(1); - } else { - for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++){ - if ("-i" eq $ARGV[$iargv]){ - $arch_file = $ARGV[$iargv+1]; - $iargv++; - } elsif ("-o" eq $ARGV[$iargv]){ - $new_arch_file = $ARGV[$iargv+1]; - $overwrite = "FALSE"; - $iargv++; - } elsif ("-k" eq $ARGV[$iargv]){ - $keyword = $ARGV[$iargv+1]; - $change_to = $ARGV[$iargv+2]; - $default_keyword = "FALSE"; - $iargv++; - $iargv++; - } else { - die "WRONG ARGUMENT"; - } - } - } - return; -} - -sub rewriting_required_check($) -{ - my ($arch) = @_; - open(F, $arch); - my @lines=; - close F; - my $grep_result = grep ($keyword, @lines); - if($grep_result >= 1){ - print "Rewrite needed\n"; - return 1; - } else { - print "Rewrite NOT needed\n"; - return 0; - } -} - -sub save_original($) -{ - my ($template) = @_; - my $renamed_template = "$template".".bak"; - rename($template, $renamed_template); - - return $renamed_template; -} - -sub findPath(){ - my $path; - my $dir = cwd; - my @folders = split("/", $dir); - for(my $count = 0; $count < ($#folders -1); $count++){ - if($folders[$count] eq ""){ - } else { - $path = "$path"."/"."$folders[$count]"; - if($folders[$count] eq $folder_top){ - print "$path\n"; - return $path; - } - } - } - die "ERROR: Script launched from the outside of the $folder_top folder!\n"; -} - -sub rewrite_file($ $) -{ - my ($arch, $template) = @_; - open(IN, '<'.$template); - open(OUT, '>'.$arch); - - if($default_keyword eq "TRUE"){ - my $myPath = &findPath(); - while(){ - $_ =~ s/$keyword/$myPath/g; - print OUT $_; - } - } else { - while(){ - $_ =~ s/$keyword/$change_to/g; - print OUT $_; - } - } - return; -} - -sub main() -{ - &opts_read(); - my $rewrite_needed = &rewriting_required_check($arch_file); - if($rewrite_needed == 1){ - if($overwrite eq "TRUE"){ - my $template_file = &save_original($arch_file); - &rewrite_file($arch_file, $template_file); - } else { - &rewrite_file($new_arch_file, $arch_file); - } - } - return; -} - -&main(); -exit(1); diff --git a/fpga_flow/tech/.gitignore b/fpga_flow/tech/.gitignore new file mode 100644 index 000000000..4c839bb4c --- /dev/null +++ b/fpga_flow/tech/.gitignore @@ -0,0 +1 @@ +winbond90nm From 0e04b88c8ffb8be8eedfd9b847838af323f47a3c Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 1 Jul 2019 11:27:48 -0600 Subject: [PATCH 06/84] Include new files in the parameter spreading --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 10 +++ .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h | 1 + .../verilog/verilog_compact_netlist.c | 4 +- .../verilog/verilog_compact_netlist.h | 4 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 40 +++++++----- .../SRC/fpga_x2p/verilog/verilog_pbtypes.h | 14 ++-- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 18 ++--- .../SRC/fpga_x2p/verilog/verilog_primitives.h | 6 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 65 ++++++++++++------- .../SRC/fpga_x2p/verilog/verilog_routing.h | 12 ++-- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 11 ++-- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 7 +- 12 files changed, 117 insertions(+), 75 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index ac0072342..28e3563cd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -3476,3 +3476,13 @@ int my_strlen_int(int input_int) { return length_input; } + +boolean my_bool_to_boolean(bool my_bool) { + + if(true == my_bool) + return TRUE; + if(false == my_bool) + return FALSE; + vpr_printf(TIO_MESSAGE_ERROR,"Failure to convert bool to boolean. Parameter is neither true nor false.\n"); + exit(1); +} diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h index adc1cb8f9..2f28cbf2a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.h @@ -406,4 +406,5 @@ void get_fpga_x2p_global_all_clock_ports(t_llist* head, int my_strlen_int(int input_int); +boolean my_bool_to_boolean(bool my_bool); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 5d20c5f2a..4187a0904 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -282,7 +282,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf char* subckt_dir_path, t_type_ptr phy_block_type, int border_side, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int iz; int temp_reserved_conf_bits_msb; int temp_iopad_lsb, temp_iopad_msb; @@ -515,7 +515,7 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_arch* arch, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int itype, iside, num_sides; int* stamped_spice_model_cnt = NULL; t_sram_orgz_info* stamped_sram_orgz_info = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index 852415d67..cf3898dc8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -6,13 +6,13 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf char* subckt_dir_path, t_type_ptr phy_block_type, int border_side, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, t_arch* arch, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, char* circuit_name, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 51a85edc8..1551aa028 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1038,7 +1038,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, t_mode* cur_mode, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int iedge, ipin; int fan_in = 0; t_interconnect* cur_interc = NULL; @@ -1276,7 +1276,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, cur_interc->spice_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, cur_interc->spice_model, fan_in, - mem_model, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + mem_model, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, is_explicit_mapping); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); @@ -1321,7 +1321,7 @@ void dump_verilog_pb_graph_port_interc(t_sram_orgz_info* cur_sram_orgz_info, t_pb_graph_node* cur_pb_graph_node, enum e_spice_pb_port_type pb_port_type, t_mode* cur_mode, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int iport, ipin; /* Check the file handler*/ @@ -1386,7 +1386,7 @@ void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, char* pin_prefix, t_pb_graph_node* cur_pb_graph_node, int select_mode_index, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int ipb, jpb; t_mode* cur_mode = NULL; t_pb_type* cur_pb_type = cur_pb_graph_node->pb_type; @@ -1527,7 +1527,8 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf char* subckt_prefix, t_pb_graph_node* prim_pb_graph_node, int pb_index, - t_spice_model* verilog_model) { + t_spice_model* verilog_model, + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -1551,23 +1552,27 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf case SPICE_MODEL_LUT: /* If this is a idle block we should set sram_bits to zero*/ dump_verilog_pb_primitive_lut(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node, - pb_index, verilog_model); + pb_index, verilog_model, + my_bool_to_boolean(is_explicit_mapping)); break; case SPICE_MODEL_FF: assert(NULL != verilog_model->model_netlist); /* TODO : We should learn trigger type and initial value!!! and how to apply them!!! */ dump_verilog_pb_generic_primitive(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node, - pb_index, verilog_model); + pb_index, verilog_model, + my_bool_to_boolean(is_explicit_mapping)); break; case SPICE_MODEL_IOPAD: assert(NULL != verilog_model->model_netlist); dump_verilog_pb_generic_primitive (cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node, - pb_index, verilog_model); + pb_index, verilog_model, + my_bool_to_boolean(is_explicit_mapping)); break; case SPICE_MODEL_HARDLOGIC: assert(NULL != verilog_model->model_netlist); dump_verilog_pb_generic_primitive(cur_sram_orgz_info, fp, subckt_prefix, prim_pb_graph_node, - pb_index, verilog_model); + pb_index, verilog_model, + my_bool_to_boolean(is_explicit_mapping)); break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid type of verilog_model(%s), should be [LUT|FF|HARD_LOGIC|IO]!\n", @@ -1587,7 +1592,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_prefix, t_pb_graph_node* cur_pb_graph_node, int pb_type_index, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int mode_index, ipb, jpb, child_mode_index; t_pb_type* cur_pb_type = NULL; char* subckt_name = NULL; @@ -1668,21 +1673,24 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, case LUT_CLASS: dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, cur_pb_graph_node, pb_type_index, - cur_pb_type->spice_model); /* last param means idle */ + cur_pb_type->spice_model, + my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */ break; case LATCH_CLASS: assert(0 == cur_pb_type->num_modes); /* Consider the num_pb, create all the subckts*/ dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, cur_pb_graph_node, pb_type_index, - cur_pb_type->spice_model); /* last param means idle */ + cur_pb_type->spice_model, + my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */ break; case UNKNOWN_CLASS: case MEMORY_CLASS: /* Consider the num_pb, create all the subckts*/ dump_verilog_pb_primitive_verilog_model(cur_sram_orgz_info, fp, formatted_subckt_prefix, cur_pb_graph_node , pb_type_index, - cur_pb_type->spice_model); /* last param means idle */ + cur_pb_type->spice_model, + my_bool_to_boolean(is_explicit_mapping)); /* last param means idle */ break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Unknown class type of pb_type(%s)!\n", @@ -1961,7 +1969,7 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, int y, int z, t_type_ptr type_descriptor, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { t_pb_graph_node* top_pb_graph_node = NULL; t_block* mapped_block = NULL; t_pb* top_pb = NULL; @@ -2476,7 +2484,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, int ix, int iy, t_arch* arch, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int subckt_name_str_len = 0; char* subckt_name = NULL; int iz; @@ -2701,7 +2709,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, t_arch* arch, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int ix, iy; /* Check the grid*/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h index f5e45c2a7..3ad43e94c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h @@ -59,14 +59,14 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info, enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, t_mode* cur_mode, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_pb_graph_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* pin_prefix, t_pb_graph_node* cur_pb_graph_node, int select_mode_index, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_pb_graph_primitive_node(FILE* fp, char* subckt_prefix, @@ -80,14 +80,14 @@ void dump_verilog_pb_primitive_verilog_model(t_sram_orgz_info* cur_sram_orgz_inf t_pb_graph_node* prim_pb_graph_node, int pb_index, t_spice_model* verilog_model, - int is_idle); + bool is_explicit_mapping); void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* subckt_prefix, t_pb_graph_node* cur_pb_graph_node, int pb_type_index, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_block(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -105,7 +105,7 @@ void dump_verilog_physical_block(t_sram_orgz_info* cur_sram_orgz_info, int y, int z, t_type_ptr type_descriptor, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_grid_pins(FILE* fp, int x, int y, @@ -143,7 +143,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, int ix, int iy, t_arch* arch, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -153,7 +153,7 @@ void dump_verilog_idle_block(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_dir, t_arch* arch, - boolean is_explicit_mapping); + bool is_explicit_mapping); void rec_copy_name_mux_in_node(t_pb_graph_node* master_node, t_pb_graph_node* target_node); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index e306d5d9b..cad259077 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -43,7 +43,8 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_prefix, t_pb_graph_node* prim_pb_graph_node, int index, - t_spice_model* verilog_model) { + t_spice_model* verilog_model, + bool is_explicit_mapping) { int num_pad_port = 0; /* INOUT port */ t_spice_model_port** pad_ports = NULL; int num_input_port = 0; @@ -122,7 +123,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } @@ -228,7 +229,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, /* Only dump the global ports belonging to a spice_model * Disable recursive here ! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, TRUE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } @@ -370,7 +371,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, -1, - mem_model, cur_num_sram, cur_num_sram + num_sram - 1); + mem_model, cur_num_sram, cur_num_sram + num_sram - 1, my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_sram); @@ -404,7 +405,8 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_prefix, t_pb_graph_node* prim_pb_graph_node, int index, - t_spice_model* verilog_model) { + t_spice_model* verilog_model, + bool is_explicit_mapping) { int i; int lut_size = 0; int num_input_port = 0; @@ -525,7 +527,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, formatted_subckt_prefix, cur_pb_type->name); fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, TRUE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ @@ -602,7 +604,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, * Only dump the global ports belonging to a spice_model * DISABLE recursive here ! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } /* Connect inputs*/ @@ -680,7 +682,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, -1, - mem_model, cur_num_sram, cur_num_sram + num_sram - 1); + mem_model, cur_num_sram, cur_num_sram + num_sram - 1, is_explicit_mapping); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_sram); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h index 81788ad20..b7dec3a48 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.h @@ -5,11 +5,13 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, char* subckt_prefix, t_pb_graph_node* prim_pb_graph_node, int index, - t_spice_model* spice_model); + t_spice_model* spice_model, + bool is_explicit_mapping); void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, char* subckt_prefix, t_pb_graph_node* prim_pb_graph_node, int index, - t_spice_model* spice_model); + t_spice_model* spice_model, + bool is_explicit_mapping); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 68aa13f64..1e69c6998 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -695,7 +695,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, int mux_size, t_rr_node** drive_rr_nodes, int switch_index, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int inode, side, index, input_cnt = 0; int grid_x, grid_y; t_spice_model* verilog_model = NULL; @@ -824,15 +824,27 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } - - fprintf(fp, "%s_size%d_%d_inbus, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "%s_size%d_%d_inbus", verilog_model->prefix, mux_size, verilog_model->cnt); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, " ,"); /* Output port */ + if (true == is_explicit_mapping) { + fprintf(fp, ".out("); + } dump_verilog_switch_box_chan_port(fp, cur_sb_info, chan_side, cur_rr_node, OUT_PORT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* Add a comma because dump_verilog_switch_box_chan_port does not add so */ fprintf(fp, ", "); @@ -904,7 +916,8 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); @@ -945,7 +958,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, int mux_size, t_rr_node** drive_rr_nodes, int switch_index, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int input_cnt = 0; t_spice_model* verilog_model = NULL; int mux_level, path_id, cur_num_sram; @@ -1067,7 +1080,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, is_explicit_mapping)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } @@ -1158,8 +1171,10 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, mem_subckt_name = generate_verilog_mux_subckt_name(verilog_model, mux_size, verilog_mem_posfix); fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); - dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, + verilog_model, mux_size, mem_model, + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + is_explicit_mapping); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); @@ -1345,7 +1360,7 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, t_sb* cur_sb_info, int chan_side, t_rr_node* cur_rr_node, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int sb_x, sb_y; int num_drive_rr_nodes = 0; t_rr_node** drive_rr_nodes = NULL; @@ -1403,7 +1418,7 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, const RRGSB& rr_sb, enum e_side chan_side, size_t chan_node_id, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int num_drive_rr_nodes = 0; t_rr_node** drive_rr_nodes = NULL; @@ -1801,7 +1816,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr char* verilog_dir, char* subckt_dir, size_t module_id, size_t seg_id, const RRGSB& rr_sb, enum e_side side, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; Side side_manager(side); @@ -2190,7 +2205,7 @@ static void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, const RRGSB& rr_sb, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; @@ -2372,7 +2387,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info char* verilog_dir, char* subckt_dir, t_sb* cur_sb_info, boolean compact_routing_hierarchy, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int itrack, inode, side, ix, iy, x, y; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; FILE* fp = NULL; @@ -2791,7 +2806,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, t_rr_node* src_rr_node, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int mux_size, cur_num_sram, input_cnt = 0; t_rr_node** drive_rr_nodes = NULL; int mux_level, path_id, switch_index; @@ -2904,7 +2919,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } @@ -2985,7 +3000,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); @@ -3021,7 +3037,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, t_rr_node* src_rr_node, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int mux_size, cur_num_sram, input_cnt = 0; t_rr_node** drive_rr_nodes = NULL; int inode, mux_level, path_id, switch_index; @@ -3137,7 +3153,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } @@ -3218,7 +3234,8 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "%s %s_%d_ ( ", mem_subckt_name, mem_subckt_name, verilog_model->cnt); dump_verilog_mem_sram_submodule(fp, cur_sram_orgz_info, verilog_model, mux_size, mem_model, - cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); + cur_num_sram, cur_num_sram + num_mux_conf_bits - 1, + my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); /* update the number of memory bits */ update_sram_orgz_info_num_mem_bit(cur_sram_orgz_info, cur_num_sram + num_mux_conf_bits); @@ -3253,7 +3270,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, t_rr_node* src_rr_node, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3278,7 +3295,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, t_rr_node* src_rr_node, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3422,7 +3439,7 @@ static void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, const RRGSB& rr_cb, t_rr_type cb_type, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; int cur_num_sram, num_conf_bits, num_reserved_conf_bits, esti_sram_cnt; @@ -3587,7 +3604,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ char* verilog_dir, char* subckt_dir, t_cb* cur_cb_info, boolean compact_routing_hierarchy, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { int itrack, inode, side, x, y; int side_cnt = 0; FILE* fp = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index 52ac54cc7..e3038477b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -41,7 +41,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, int mux_size, t_rr_node** drive_rr_nodes, int switch_index, - boolean is_explicit_mapping); + bool is_explicit_mapping); int count_verilog_switch_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, t_sb cur_sb_info, int chan_side, @@ -56,7 +56,7 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, t_sb* cur_sb_info, int chan_side, t_rr_node* cur_rr_node, - boolean is_explicit_mapping); + bool is_explicit_mapping); int count_verilog_switch_box_reserved_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, t_sb cur_sb_info); @@ -71,7 +71,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info t_ivec*** LL_rr_node_indices, t_syn_verilog_opts fpga_verilog_opts, boolean compact_routing_hierarchy, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_connection_box_short_interc(FILE* fp, @@ -82,13 +82,13 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, t_rr_node* src_rr_node, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, t_cb* cur_cb_info, t_rr_node* src_rr_node, - boolean is_explicit_mapping); + bool is_explicit_mapping); int count_verilog_connection_box_interc_conf_bits(t_sram_orgz_info* cur_sram_orgz_info, @@ -127,7 +127,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ char* verilog_dir, char* subckt_dir, t_cb* cur_cb_info, boolean compact_routing_hierarchy, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index fefad5466..f120ddd7c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2550,7 +2550,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, int num_mux_conf_bits, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -2570,7 +2570,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m /* FOR Scan-chain, we need regular output of a scan-chain FF * We do not need a prefix implying MUX name, size and index */ - if (TRUE == is_explicit_mapping) { + if (true == is_explicit_mapping) { fprintf(fp, ".sram("); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, @@ -2638,7 +2638,7 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, int num_mux_conf_bits, - boolean is_explicit_mapping) { + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -3058,7 +3058,8 @@ void dump_verilog_mem_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, t_spice_model* cur_verilog_model, int mux_size, t_spice_model* cur_sram_verilog_model, - int lsb, int msb) { + int lsb, int msb, + bool is_explicit_mapping) { int cur_bl, cur_wl; int num_bl_ports, num_wl_ports; t_spice_model_port** bl_port = NULL; @@ -3106,7 +3107,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, } /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 5485ad97f..cf8427720 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -188,14 +188,14 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, int num_mux_conf_bits, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, t_sram_orgz_info* cur_sram_orgz_info, int mux_size, int cur_num_sram, int num_mux_reserved_conf_bits, int num_mux_conf_bits, - boolean is_explicit_mapping); + bool is_explicit_mapping); void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, char* general_port_prefix, int lsb, int msb, @@ -239,7 +239,8 @@ void dump_verilog_mem_sram_submodule(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, t_spice_model* cur_verilog_model, int mux_size, t_spice_model* cur_sram_verilog_model, - int lsb, int msb); + int lsb, int msb, + bool is_explicit_mapping); char* gen_verilog_grid_one_pin_name(int x, int y, int height, int side, int pin_index, From 863e8677c0f75e3d69c1906395b92385b10d628a Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 1 Jul 2019 12:12:36 -0600 Subject: [PATCH 07/84] Further add new functions to tree --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 39 ++++++++++++------- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 2 +- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 08f53ea0f..5bcc70cb8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1434,7 +1434,8 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, void dump_verilog_cmos_mux_submodule(FILE* fp, int mux_size, t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch) { + t_spice_mux_arch spice_mux_arch, + bool is_explicit_mapping) { int i, num_conf_bits, iport, ipin, num_mode_bits; int num_input_port = 0; int num_output_port = 0; @@ -1941,7 +1942,8 @@ void dump_verilog_rram_mux_onelevel_structure(FILE* fp, void dump_verilog_rram_mux_submodule(FILE* fp, int mux_size, t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch) { + t_spice_mux_arch spice_mux_arch, + bool is_explicit_mapping) { int i, num_conf_bits; int num_input_port = 0; int num_output_port = 0; @@ -2173,7 +2175,8 @@ void dump_verilog_rram_mux_submodule(FILE* fp, void dump_verilog_cmos_mux_mem_submodule(FILE* fp, int mux_size, t_spice_model spice_model, - t_spice_mux_arch spice_mux_arch) { + t_spice_mux_arch spice_mux_arch, + bool is_explicit_mapping) { int i, num_conf_bits; int num_sram_port = 0; @@ -2257,7 +2260,8 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp, * whatever structure it is: one-level, two-level or multi-level */ void dump_verilog_mux_mem_module(FILE* fp, - t_spice_mux_model* spice_mux_model) { + t_spice_mux_model* spice_mux_model, + bool is_explicit_mapping) { /* Make sure we have a valid file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); @@ -2287,7 +2291,8 @@ void dump_verilog_mux_mem_module(FILE* fp, case SPICE_MODEL_DESIGN_CMOS: dump_verilog_cmos_mux_mem_submodule(fp, spice_mux_model->size, *(spice_mux_model->spice_model), - *(spice_mux_model->spice_mux_arch)); + *(spice_mux_model->spice_mux_arch), + is_explicit_mapping); break; case SPICE_MODEL_DESIGN_RRAM: /* We do not need a memory submodule for RRAM MUX, @@ -2308,7 +2313,8 @@ void dump_verilog_mux_mem_module(FILE* fp, * whatever structure it is: one-level, two-level or multi-level */ void dump_verilog_mux_module(FILE* fp, - t_spice_mux_model* spice_mux_model) { + t_spice_mux_model* spice_mux_model, + bool is_explicit_mapping) { /* Make sure we have a valid file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); @@ -2347,12 +2353,14 @@ void dump_verilog_mux_module(FILE* fp, case SPICE_MODEL_DESIGN_CMOS: dump_verilog_cmos_mux_submodule(fp, spice_mux_model->size, *(spice_mux_model->spice_model), - *(spice_mux_model->spice_mux_arch)); + *(spice_mux_model->spice_mux_arch), + is_explicit_mapping); break; case SPICE_MODEL_DESIGN_RRAM: dump_verilog_rram_mux_submodule(fp, spice_mux_model->size, *(spice_mux_model->spice_model), - *(spice_mux_model->spice_mux_arch)); + *(spice_mux_model->spice_mux_arch), + is_explicit_mapping); break; default: vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid design_technology of MUX(name: %s)\n", @@ -2373,7 +2381,8 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, int num_switch, t_switch_inf* switches, t_spice* spice, - t_det_routing_arch* routing_arch) { + t_det_routing_arch* routing_arch, + bool is_explicit_mapping) { /* Statisitcs for input sizes and structures of MUXes * used in FPGA architecture @@ -2444,7 +2453,7 @@ void dump_verilog_submodule_muxes(t_sram_orgz_info* cur_sram_orgz_info, /* Let's have a N:1 MUX as basis*/ dump_verilog_mux_basis_module(fp, cur_spice_mux_model); /* Print the mux subckt */ - dump_verilog_mux_module(fp, cur_spice_mux_model); + dump_verilog_mux_module(fp, cur_spice_mux_model, is_explicit_mapping); /* Update the statistics*/ mux_cnt++; if ((-1 == max_mux_size)||(max_mux_size < cur_spice_mux_model->size)) { @@ -3234,7 +3243,8 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, int num_switch, t_switch_inf* switches, t_spice* spice, - t_det_routing_arch* routing_arch) { + t_det_routing_arch* routing_arch, + bool is_explicit_mapping) { /* Statisitcs for input sizes and structures of MUXes * used in FPGA architecture @@ -3308,7 +3318,8 @@ void dump_verilog_submodule_memories(t_sram_orgz_info* cur_sram_orgz_info, cur_spice_mux_model->spice_mux_arch = (t_spice_mux_arch*)my_malloc(sizeof(t_spice_mux_arch)); init_spice_mux_arch(cur_spice_mux_model->spice_model, cur_spice_mux_model->spice_mux_arch, cur_spice_mux_model->size); /* Print the mux mem subckt */ - dump_verilog_mux_mem_module(fp, cur_spice_mux_model); + dump_verilog_mux_mem_module(fp, cur_spice_mux_model, + is_explicit_mapping); /* Update the statistics*/ /* Move on to the next*/ temp = temp->next; @@ -3485,7 +3496,7 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, /* 1. MUXes */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of multiplexers...\n"); dump_verilog_submodule_muxes(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, - switch_inf, Arch.spice, routing_arch); + switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); /* 2. LUTes */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of LUTs...\n"); @@ -3502,7 +3513,7 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, /* 4. Memories */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of memories...\n"); dump_verilog_submodule_memories(cur_sram_orgz_info, verilog_dir, submodule_dir, routing_arch->num_switch, - switch_inf, Arch.spice, routing_arch); + switch_inf, Arch.spice, routing_arch, fpga_verilog_opts.dump_explicit_verilog); /* 5. Dump decoder modules only when memory bank is required */ dump_verilog_config_peripherals(cur_sram_orgz_info, verilog_dir, submodule_dir); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index f120ddd7c..3a5e134f5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -3166,7 +3166,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, break; case SPICE_SRAM_SCAN_CHAIN: /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } if (SPICE_MODEL_MUX == cur_verilog_model->type) { From 370ce23646e00197b79b572600e6fc9e5940c453 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 1 Jul 2019 13:58:24 -0600 Subject: [PATCH 08/84] Mux explicit verilog done --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 175 ++++++++++++++---- 1 file changed, 143 insertions(+), 32 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 5bcc70cb8..6b985dc70 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -1153,7 +1153,8 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, char* mux_basis_subckt_name, t_spice_model spice_model, t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { + int num_sram_port, t_spice_model_port** sram_port, + bool is_explicit_mapping) { int i, j, level, nextlevel; int nextj, out_idx; int mux_basis_cnt = 0; @@ -1225,17 +1226,41 @@ void dump_verilog_cmos_mux_tree_structure(FILE* fp, /* Each basis mux2to1: svdd sgnd */ fprintf(fp, "%s mux_basis_no%d (", mux_basis_subckt_name, mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } /* For intermediate buffers */ if (TRUE == inter_buf_loc[level]) { - fprintf(fp, "mux2_l%d_in_buf[%d:%d], ", level, j, nextj); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in_buf[%d:%d]", level, j, nextj); /* input0 input1 */ } else { - fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, nextj); /* input0 input1 */ + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, nextj); /* input0 input1 */ + } + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d]", sram_port[0]->prefix, i); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d]", sram_port[0]->prefix, i); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, "));\n"); + } else { + fprintf(fp, ");\n"); } - fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ - fprintf(fp, "%s[%d], %s_inv[%d]);\n", sram_port[0]->prefix, i, sram_port[0]->prefix, i); /* sram sram_inv */ /* For intermediate buffers */ if (TRUE == inter_buf_loc[nextlevel]) { /* Find the input port, output port, and sram port*/ @@ -1302,7 +1327,8 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, char* mux_special_basis_subckt_name, t_spice_model spice_model, t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { + int num_sram_port, t_spice_model_port** sram_port, + bool is_explicit_mapping) { int i, j, level, nextlevel, sram_idx; int out_idx; int mux_basis_cnt = 0; @@ -1348,14 +1374,36 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, /* Print the special basis */ fprintf(fp, "%s special_basis(", mux_special_basis_subckt_name); /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } - fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ - fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ - fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ", - sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1, + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d:%d]", sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ");\n"); special_basis_cnt++; } @@ -1365,16 +1413,38 @@ void dump_verilog_cmos_mux_multilevel_structure(FILE* fp, fprintf(fp, "%s ", mux_basis_subckt_name); /* subckt_name */ fprintf(fp, "mux_basis_no%d (", mux_basis_cnt); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } - fprintf(fp, "mux2_l%d_in[%d:%d], ", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ - fprintf(fp, "mux2_l%d_in[%d], ", nextlevel, out_idx); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "mux2_l%d_in[%d:%d]", level, j, j + cur_num_input_basis - 1); /* input0 input1 */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", nextlevel, out_idx); /* output */ /* Print number of sram bits for this basis */ - fprintf(fp, "%s[%d:%d], %s_inv[%d:%d] ", - sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1, + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s[%d:%d]", sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); - fprintf(fp, ");\n"); + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[%d:%d]", + sram_port[0]->prefix, sram_idx, sram_idx + cur_num_input_basis -1); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ");"); fprintf(fp, "\n"); /* Update the counter */ mux_basis_cnt++; @@ -1393,7 +1463,8 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, char* mux_basis_subckt_name, t_spice_model spice_model, t_spice_mux_arch spice_mux_arch, - int num_sram_port, t_spice_model_port** sram_port) { + int num_sram_port, t_spice_model_port** sram_port, + bool is_explicit_mapping) { /* Make sure we have a valid file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid file handler!\n",__FILE__, __LINE__); @@ -1407,23 +1478,61 @@ void dump_verilog_cmos_mux_onelevel_structure(FILE* fp, fprintf(fp, "%s mux_basis (\n", mux_basis_subckt_name); /* given_name */ /* Dump global ports */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, &spice_model, FALSE, FALSE, + my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } fprintf(fp, "//----- MUX inputs -----\n"); - fprintf(fp, "mux2_l%d_in[0:%d], ", 1, spice_mux_arch.num_input - 1); /* input0 */ - fprintf(fp, "mux2_l%d_in[%d], ", 0, 0); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "mux2_l%d_in[0:%d]", 1, spice_mux_arch.num_input - 1); /* input0 */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .out("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "mux2_l%d_in[%d]", 0, 0); /* output */ + if (true == is_explicit_mapping) { + fprintf(fp, "),"); + } else { + fprintf(fp, ","); + } fprintf(fp, "\n"); fprintf(fp, "//----- SRAM ports -----\n"); /* Special basis for 2-input MUX, there is only one configuration bit */ if (2 == spice_mux_arch.num_input) { - fprintf(fp, "%s[0:%d], %s_inv[0:%d] ", - sram_port[0]->prefix, 0, - sram_port[0]->prefix, 0); /* sram sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ".mem("); + } + fprintf(fp, "%s[0:%d]", + sram_port[0]->prefix, 0); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[0:%d]", + sram_port[0]->prefix, 0); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } } else { - fprintf(fp, "%s[0:%d], %s_inv[0:%d] ", - sram_port[0]->prefix, spice_mux_arch.num_input - 1, - sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ".mem("); + } + fprintf(fp, "%s[0:%d]", + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram */ + if (true == is_explicit_mapping) { + fprintf(fp, "), .mem_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_inv[0:%d]", + sram_port[0]->prefix, spice_mux_arch.num_input - 1); /* sram_inv */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } } fprintf(fp, "\n"); fprintf(fp, ");\n"); @@ -1542,7 +1651,7 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, } else { fprintf(fp, "//----- CMOS MUX info: spice_model_name=%s, size=%d, structure: %s -----\n", spice_model.name, mux_size, gen_str_spice_model_structure(spice_model.design_tech_info.mux_info->structure)); - fprintf(fp, "module %s (", + fprintf(fp, "module %s (\n", gen_verilog_one_mux_module_name(&spice_model, mux_size)); /* Print input ports*/ fprintf(fp, "input wire [0:%d] %s,\n", mux_size - 1, input_port[0]->prefix); @@ -1569,15 +1678,17 @@ void dump_verilog_cmos_mux_submodule(FILE* fp, switch (cur_mux_structure) { case SPICE_MODEL_STRUCTURE_TREE: dump_verilog_cmos_mux_tree_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); + spice_model, spice_mux_arch, num_sram_port, sram_port, is_explicit_mapping); break; case SPICE_MODEL_STRUCTURE_ONELEVEL: dump_verilog_cmos_mux_onelevel_structure(fp, mux_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); + spice_model, spice_mux_arch, + num_sram_port, sram_port, is_explicit_mapping); break; case SPICE_MODEL_STRUCTURE_MULTILEVEL: dump_verilog_cmos_mux_multilevel_structure(fp, mux_basis_subckt_name, mux_special_basis_subckt_name, - spice_model, spice_mux_arch, num_sram_port, sram_port); + spice_model, spice_mux_arch, num_sram_port, sram_port, + is_explicit_mapping); break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid structure for spice model (%s)!\n", From f189ef1d8fc9253502ef6324be2b5f4d4d8eb83f Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 1 Jul 2019 14:24:09 -0600 Subject: [PATCH 09/84] Done with the submodules --- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 47 +++++++++++++++---- 1 file changed, 39 insertions(+), 8 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 6b985dc70..269516054 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2683,7 +2683,8 @@ void dump_verilog_wire_module(FILE* fp, /* Dump one module of a LUT */ void dump_verilog_submodule_one_lut(FILE* fp, - t_spice_model* verilog_model) { + t_spice_model* verilog_model, + bool is_explicit_mapping) { int num_input_port = 0; int num_output_port = 0; int num_sram_port = 0; @@ -3055,19 +3056,47 @@ void dump_verilog_submodule_one_lut(FILE* fp, verilog_model->name, verilog_model->name); /* Connect MUX inputs to LUT configuration port */ assert(FALSE == sram_port[sram_port_index]->mode_select); - fprintf(fp, " %s_out,", + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "%s_out", sram_port[sram_port_index]->prefix); + if (true == is_explicit_mapping) { + fprintf(fp, "), "); + } else { + fprintf(fp, ", "); + } /* Connect MUX output to LUT output */ for (iport = 0; iport < num_output_port; iport++) { - fprintf(fp, " %s,", + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + output_port[iport]->prefix); + } + fprintf(fp, "%s", output_port[iport]->prefix); + if (true == is_explicit_mapping) { + fprintf(fp, "), "); + } else { + fprintf(fp, ", "); + } } /* Connect MUX configuration port to LUT inputs */ - fprintf(fp, " %s_buf,", + if (true == is_explicit_mapping) { + fprintf(fp, ".sram("); + } + fprintf(fp, "%s_buf", input_port[0]->prefix); /* Connect MUX inverted configuration port to inverted LUT inputs */ - fprintf(fp, " %s_b", + if (true == is_explicit_mapping) { + fprintf(fp, "), sram_inv("); + } else { + fprintf(fp, ", "); + } + fprintf(fp, "%s_b", input_port[0]->prefix); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* End of call LUT MUX */ fprintf(fp, ");\n"); @@ -3168,7 +3197,8 @@ void dump_verilog_submodule_luts(char* verilog_dir, int num_spice_model, t_spice_model* spice_models, boolean include_timing, - boolean include_signal_init) { + boolean include_signal_init, + bool is_explicit_mapping) { FILE* fp = NULL; char* verilog_name = my_strcat(submodule_dir, luts_verilog_file_name); int imodel; @@ -3190,7 +3220,7 @@ void dump_verilog_submodule_luts(char* verilog_dir, continue; } if (SPICE_MODEL_LUT == spice_models[imodel].type) { - dump_verilog_submodule_one_lut(fp, &(spice_models[imodel])); + dump_verilog_submodule_one_lut(fp, &(spice_models[imodel]), is_explicit_mapping); } } @@ -3614,7 +3644,8 @@ void dump_verilog_submodules(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_submodule_luts(verilog_dir, submodule_dir, Arch.spice->num_spice_model, Arch.spice->spice_models, fpga_verilog_opts.include_timing, - fpga_verilog_opts.include_signal_init); + fpga_verilog_opts.include_signal_init, + fpga_verilog_opts.dump_explicit_verilog); /* 3. Hardwires */ vpr_printf(TIO_MESSAGE_INFO, "Generating modules of hardwires...\n"); From 44301bfd773b2c066517007e876ed8f61b12ffee Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Jul 2019 09:01:52 -0600 Subject: [PATCH 10/84] updated SPICE generator to avoid issues on clb2clb_direct --- .../SRC/fpga_x2p/spice/spice_mux_testbench.c | 20 ++--- .../vpr/SRC/fpga_x2p/spice/spice_routing.c | 86 ++++++++++++++----- .../vpr/SRC/fpga_x2p/spice/spice_routing.h | 3 +- .../vpr/SRC/fpga_x2p/spice/spice_subckt.c | 3 +- vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c | 4 +- 5 files changed, 76 insertions(+), 40 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux_testbench.c index 88333dbd5..f28ba2ae1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_mux_testbench.c @@ -80,8 +80,7 @@ static void init_spice_mux_testbench_globals(t_spice spice) { } static -void fprint_spice_mux_testbench_global_ports(FILE* fp, - t_spice spice) { +void fprint_spice_mux_testbench_global_ports(FILE* fp) { /* A valid file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid File Handler!\n",__FILE__, __LINE__); @@ -641,7 +640,6 @@ void fprint_spice_mux_testbench_pb_pin_mux(FILE* fp, static void fprint_spice_mux_testbench_pb_graph_node_pin_interc(FILE* fp, - enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, t_mode* cur_mode, int select_path_id, @@ -734,7 +732,6 @@ static void fprint_spice_mux_testbench_pb_pin_interc(FILE* fp, t_rr_node* pb_rr_graph, t_phy_pb* des_pb, - enum e_spice_pin2pin_interc_type pin2pin_interc_type, t_pb_graph_pin* des_pb_graph_pin, t_mode* cur_mode, int select_path_id, @@ -856,7 +853,6 @@ void fprintf_spice_mux_testbench_pb_graph_port_interc(FILE* fp, assert(NULL == cur_pb); path_id = DEFAULT_PATH_ID; fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, - INPUT2INPUT_INTERC, &(cur_pb_graph_node->input_pins[iport][ipin]), cur_mode, path_id, @@ -878,7 +874,6 @@ void fprintf_spice_mux_testbench_pb_graph_port_interc(FILE* fp, assert(DEFAULT_PATH_ID != path_id); } fprint_spice_mux_testbench_pb_pin_interc(fp, pb_rr_nodes, cur_pb, /* TODO: find out the child_pb*/ - INPUT2INPUT_INTERC, &(cur_pb_graph_node->input_pins[iport][ipin]), cur_mode, path_id, @@ -896,7 +891,6 @@ void fprintf_spice_mux_testbench_pb_graph_port_interc(FILE* fp, assert(NULL == cur_pb); path_id = DEFAULT_PATH_ID; fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, - OUTPUT2OUTPUT_INTERC, &(cur_pb_graph_node->output_pins[iport][ipin]), cur_mode, path_id, @@ -918,7 +912,6 @@ void fprintf_spice_mux_testbench_pb_graph_port_interc(FILE* fp, assert(DEFAULT_PATH_ID != path_id); } fprint_spice_mux_testbench_pb_pin_interc(fp, pb_rr_nodes, cur_pb, /* TODO: find out the child_pb*/ - OUTPUT2OUTPUT_INTERC, &(cur_pb_graph_node->output_pins[iport][ipin]), cur_mode, path_id, @@ -936,7 +929,6 @@ void fprintf_spice_mux_testbench_pb_graph_port_interc(FILE* fp, assert(NULL == cur_pb); path_id = DEFAULT_PATH_ID; fprint_spice_mux_testbench_pb_graph_node_pin_interc(fp, - INPUT2INPUT_INTERC, &(cur_pb_graph_node->clock_pins[iport][ipin]), cur_mode, path_id, @@ -958,7 +950,6 @@ void fprintf_spice_mux_testbench_pb_graph_port_interc(FILE* fp, assert(DEFAULT_PATH_ID != path_id); } fprint_spice_mux_testbench_pb_pin_interc(fp, pb_rr_nodes, cur_pb, /* TODO: find out the child_pb*/ - INPUT2INPUT_INTERC, &(cur_pb_graph_node->clock_pins[iport][ipin]), cur_mode, path_id, @@ -1254,6 +1245,7 @@ void fprint_spice_mux_testbench_cb_one_mux(FILE* fp, return; } +static void fprint_spice_mux_testbench_cb_interc(FILE* fp, t_cb cur_cb_info, t_rr_node* src_rr_node, @@ -1481,8 +1473,7 @@ int fprint_spice_mux_testbench_sb_one_mux(FILE* fp, static int fprint_spice_mux_testbench_call_one_grid_sb_muxes(FILE* fp, - t_sb cur_sb_info, - t_ivec*** LL_rr_node_indices) { + t_sb cur_sb_info) { int itrack, side; int used = 0; @@ -1672,6 +1663,7 @@ void fprint_spice_mux_testbench_measurements(FILE* fp, } /* Top-level function in this source file */ +static int fprint_spice_one_mux_testbench(char* formatted_spice_dir, char* circuit_name, char* mux_testbench_name, @@ -1743,7 +1735,7 @@ int fprint_spice_one_mux_testbench(char* formatted_spice_dir, fprint_spice_options(fp, arch.spice->spice_params); /* Global nodes: Vdd for SRAMs, Logic Blocks(Include IO), Switch Boxes, Connection Boxes */ - fprint_spice_mux_testbench_global_ports(fp, *(arch.spice)); + fprint_spice_mux_testbench_global_ports(fp); /* Quote defined Logic blocks subckts (Grids) */ init_spice_mux_testbench_globals(*(arch.spice)); @@ -1798,7 +1790,7 @@ int fprint_spice_one_mux_testbench(char* formatted_spice_dir, case SPICE_SB_MUX_TB: total_sb_mux_input_density = 0.; /* Output a sb_mux testbench */ - used = fprint_spice_mux_testbench_call_one_grid_sb_muxes(fp, sb_info[grid_x][grid_y], LL_rr_node_indices); + used = fprint_spice_mux_testbench_call_one_grid_sb_muxes(fp, sb_info[grid_x][grid_y]); /* Check and output info. */ assert((0 == testbench_sb_mux_cnt)||(0 < testbench_sb_mux_cnt)); if (0 < testbench_sb_mux_cnt) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c index 5fb871061..78c0f18d4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c @@ -1,3 +1,45 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: rr_blocks.cpp + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/07/02 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ +/************************************************************************ + * This file contains functions to output SPICE netlists of routing resources + * i.e., Switch Block(SB), Connection Block (CB) and routing channels. + * Each module will be placed in an individual subckt, which be called + * through SPICE testbenches + * Note that each subckt is a configured module (SB, CB or Routing channals) + ***********************************************************************/ + /***********************************/ /* SPICE Modeling for VPR */ /* Xifan TANG, EPFL/LSI */ @@ -39,7 +81,7 @@ #include "fpga_x2p_backannotate_utils.h" #include "spice_routing.h" - +static void fprint_routing_chan_subckt(char* subckt_dir, int x, int y, t_rr_type chan_type, int LL_num_rr_nodes, t_rr_node* LL_rr_node, @@ -629,11 +671,9 @@ void fprint_switch_box_interc(FILE* fp, * For channels chanX with INC_DIRECTION on the right side, they should be marked as outputs * For channels chanX with DEC_DIRECTION on the right side, they should be marked as inputs */ +static void fprint_routing_switch_box_subckt(char* subckt_dir, - t_sb cur_sb_info, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - boolean compact_routing_hierarchy) { + t_sb cur_sb_info) { int itrack, inode, side, ix, iy, x, y; FILE* fp = NULL; char* fname = NULL; @@ -755,7 +795,15 @@ void fprint_connection_box_short_interc(FILE* fp, assert(1 == src_rr_node->fan_in); /* Check the driver*/ - drive_rr_node = &(rr_node[src_rr_node->prev_node]); + drive_rr_node = src_rr_node->drive_rr_nodes[0]; + /* We have OPINs since we may have direct connections: + * These connections should be handled by other functions in the compact_netlist.c + * So we just return here for OPINs + */ + if (OPIN == drive_rr_node->type) { + return; + } + assert((CHANX == drive_rr_node->type)||(CHANY == drive_rr_node->type)); check_flag = 0; for (iedge = 0; iedge < drive_rr_node->num_edges; iedge++) { @@ -996,11 +1044,9 @@ void fprint_connection_box_interc(FILE* fp, * | | Connection | | * --------------Box_Y[x][y-1]-------------- */ +static void fprint_routing_connection_box_subckt(char* subckt_dir, - t_cb cur_cb_info, - int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - boolean compact_routing_hierarchy) { + t_cb cur_cb_info) { int itrack, inode, side, x, y; int side_cnt = 0; @@ -1104,6 +1150,7 @@ void fprint_routing_connection_box_subckt(char* subckt_dir, fprintf(fp, "***** Head of scan-chain *****\n"); fprintf(fp, "Rcbx[%d][%d]_sc_head cbx[%d][%d]_sc_head %s[%d]->in 0\n", x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); + break; case CHANY: fprintf(fp, "***** Head of scan-chain *****\n"); fprintf(fp, "Rcby[%d][%d]_sc_head cby[%d][%d]_sc_head %s[%d]->in 0\n", @@ -1141,6 +1188,7 @@ void fprint_routing_connection_box_subckt(char* subckt_dir, fprintf(fp, "***** Tail of scan-chain *****\n"); fprintf(fp, "Rcbx[%d][%d]_sc_tail cbx[%d][%d]_sc_tail %s[%d]->in 0\n", x, y, x, y, sram_spice_model->prefix, sram_spice_model->cnt); + break; case CHANY: fprintf(fp, "***** Tail of scan-chain *****\n"); fprintf(fp, "Rcby[%d][%d]_sc_tail cby[%d][%d]_sc_tail %s[%d]->in 0\n", @@ -1173,8 +1221,7 @@ void generate_spice_routing_resources(char* subckt_dir, t_arch arch, t_det_routing_arch* routing_arch, int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - boolean compact_routing_hierarchy) { + t_ivec*** LL_rr_node_indices) { int ix, iy; assert(UNI_DIRECTIONAL == routing_arch->directionality); @@ -1221,9 +1268,7 @@ void generate_spice_routing_resources(char* subckt_dir, for (ix = 0; ix < (nx + 1); ix++) { for (iy = 0; iy < (ny + 1); iy++) { update_spice_models_routing_index_low(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); - fprint_routing_switch_box_subckt(subckt_dir, sb_info[ix][iy], - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - compact_routing_hierarchy); + fprint_routing_switch_box_subckt(subckt_dir, sb_info[ix][iy]); update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); } } @@ -1237,9 +1282,7 @@ void generate_spice_routing_resources(char* subckt_dir, /* Check if this cby_info exists, it may be covered by a heterogenous block */ if ((TRUE == is_cb_exist(CHANX, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - fprint_routing_connection_box_subckt(subckt_dir, cbx_info[ix][iy], - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - compact_routing_hierarchy); + fprint_routing_connection_box_subckt(subckt_dir, cbx_info[ix][iy]); } update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); } @@ -1251,9 +1294,7 @@ void generate_spice_routing_resources(char* subckt_dir, /* Check if this cby_info exists, it may be covered by a heterogenous block */ if ((TRUE == is_cb_exist(CHANY, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - fprint_routing_connection_box_subckt(subckt_dir, cby_info[ix][iy], - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, - compact_routing_hierarchy); + fprint_routing_connection_box_subckt(subckt_dir, cby_info[ix][iy]); } update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); } @@ -1267,3 +1308,6 @@ void generate_spice_routing_resources(char* subckt_dir, return; } +/************************************************************************ + * End of file : rr_blocks.cpp + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.h index 291bb3c08..bc7df15d4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.h @@ -67,6 +67,5 @@ void generate_spice_routing_resources(char* subckt_dir, t_arch arch, t_det_routing_arch* routing_arch, int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices, - boolean compact_routing_hierarchy); + t_ivec*** LL_rr_node_indices); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_subckt.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_subckt.c index a5753caf9..09ca2854e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_subckt.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_subckt.c @@ -737,8 +737,7 @@ void generate_spice_subckts(char* subckt_dir, /* 6. Generate Routing architecture*/ vpr_printf(TIO_MESSAGE_INFO, "Writing Routing Resources....\n"); generate_spice_routing_resources(subckt_dir, (*arch), routing_arch, - num_rr_nodes, rr_node, rr_node_indices, - compact_routing_hierarchy); + num_rr_nodes, rr_node, rr_node_indices); /* 7. Generate Logic Blocks */ vpr_printf(TIO_MESSAGE_INFO,"Writing Logic Blocks...\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c index e195d994b..d24a6bcba 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_utils.c @@ -1489,6 +1489,7 @@ void fprint_spice_toplevel_one_grid_side_pin_with_given_index(FILE* fp, } /* Apply a CLB to CLB direct connection to a SPICE netlist */ +static void fprint_spice_one_clb2clb_direct(FILE* fp, int from_grid_x, int from_grid_y, int to_grid_x, int to_grid_y, @@ -1505,7 +1506,7 @@ void fprint_spice_one_clb2clb_direct(FILE* fp, /* Check bandwidth match between from_clb and to_clb pins */ if (0 != (cur_direct->from_clb_pin_end_index - cur_direct->from_clb_pin_start_index - - cur_direct->to_clb_pin_end_index - cur_direct->to_clb_pin_start_index)) { + - (cur_direct->to_clb_pin_end_index - cur_direct->to_clb_pin_start_index))) { vpr_printf(TIO_MESSAGE_ERROR, "(%s, [LINE%d]) Unmatch pin bandwidth in direct connection (name=%s)!\n", __FILE__, __LINE__, cur_direct->name); exit(1); @@ -1619,6 +1620,7 @@ void fprint_spice_clb2clb_directs(FILE* fp, * 2. Their corresponding rr_node (SINK or IPIN) has 0 fan-in. * In these cases, we short connect them to global GND. */ +static void fprint_grid_float_port_stimulation(FILE* fp) { int inode; int num_float_port = 0; From 95674c4687e650d1485736e15b61993c670488b1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Jul 2019 10:00:02 -0600 Subject: [PATCH 11/84] added Switch Block SubType and SubFs for tileable rr_graph generation --- .../libarchfpga/SRC/include/physical_types.h | 2 + vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c | 65 +++++++++++++++- vpr7_x2p/vpr/SRC/base/SetupVPR.c | 2 + vpr7_x2p/vpr/SRC/base/place_and_route.c | 6 +- vpr7_x2p/vpr/SRC/base/vpr_types.h | 2 + .../rr_graph/tileable_rr_graph_builder.cpp | 10 ++- .../rr_graph/tileable_rr_graph_builder.h | 1 + .../device/rr_graph/tileable_rr_graph_gsb.cpp | 4 +- .../device/rr_graph/tileable_rr_graph_gsb.h | 2 + .../fpga_x2p/base/fpga_x2p_bitstream_utils.c | 75 ++++++++++++++----- .../fpga_x2p/base/fpga_x2p_bitstream_utils.h | 3 + .../bitstream/fpga_bitstream_pbtypes.c | 2 + .../vpr/SRC/fpga_x2p/router/fpga_x2p_router.c | 49 +++++++++++- .../vpr/SRC/fpga_x2p/spice/spice_routing.c | 4 +- vpr7_x2p/vpr/SRC/place/timing_place_lookup.c | 6 +- vpr7_x2p/vpr/SRC/route/route_common.c | 6 +- vpr7_x2p/vpr/SRC/route/rr_graph.c | 7 +- vpr7_x2p/vpr/SRC/route/rr_graph.h | 1 + 18 files changed, 209 insertions(+), 38 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/include/physical_types.h b/vpr7_x2p/libarchfpga/SRC/include/physical_types.h index bdc991718..6e7a064e7 100644 --- a/vpr7_x2p/libarchfpga/SRC/include/physical_types.h +++ b/vpr7_x2p/libarchfpga/SRC/include/physical_types.h @@ -931,9 +931,11 @@ struct s_arch { bool tileable; /* Xifan TANG: tileable rr_graph support */ t_chan_width_dist Chans; enum e_switch_block_type SBType; + enum e_switch_block_type SBSubType; float R_minW_nmos; float R_minW_pmos; int Fs; + int SubFs; float C_ipin_cblock; float T_ipin_cblock; /* mrFPGA: Xifan TANG */ diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c index ff8ececa1..e93a05914 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c @@ -1,4 +1,39 @@ -/* The XML parser processes an XML file into a tree data structure composed of * +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: rr_blocks.cpp + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/07/02 | Xifan Tang | Modified to support passing_track_type for switch blocks + * +-------------------------------------+ + ***********************************************************************/ +/************************************************************************ + * The XML parser processes an XML file into a tree data structure composed of * * ezxml_t nodes. Each ezxml_t node represents an XML element. For example * * will generate two ezxml_t nodes. One called "a" and its * * child "b". Each ezxml_t node can contain various XML data such as attribute * @@ -22,7 +57,7 @@ * Because of how the XML tree traversal works, we free everything when we're * * done reading an architecture file to make sure that there isn't some part * * of the architecture file that got missed. * - */ + ***********************************************************************/ #include #include @@ -2142,6 +2177,29 @@ static void ProcessDevice(INOUTP ezxml_t Node, OUTP struct s_arch *arch, arch->Fs = GetIntProperty(Cur, "fs", TRUE, 3); + /* SubType is the switch block type of passing tracks */ + /* By default, the subType is the same as the main type */ + Prop = FindProperty(Cur, "sub_type", FALSE); + if (NULL != Prop) { + if (strcmp(Prop, "wilton") == 0) { + arch->SBSubType = WILTON; + } else if (strcmp(Prop, "universal") == 0) { + arch->SBSubType = UNIVERSAL; + } else if (strcmp(Prop, "subset") == 0) { + arch->SBSubType = SUBSET; + } else { + vpr_printf(TIO_MESSAGE_ERROR, + "[LINE %d] Unknown property %s for switch block type x\n", + Cur->line, Prop); + exit(1); + } + } + ezxml_set_attr(Cur, "sub_type", NULL); + + /* SubFs is Fs for the switch block type of passing tracks */ + /* By default, the subFs is the same as the main Fs */ + arch->SubFs = GetIntProperty(Cur, "sub_fs", FALSE, arch->Fs); + FreeNode(Cur); } @@ -4132,3 +4190,6 @@ void SetupPinEquivalenceAutoDetect(ezxml_t Parent, t_type_descriptor* Type) { return; } +/************************************************************************ + * End of file : read_xml_arch_file.c + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 09441daa1..af240a0ea 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -536,9 +536,11 @@ static void SetupRoutingArch(INP t_arch Arch, OUTP struct s_det_routing_arch *RoutingArch) { RoutingArch->switch_block_type = Arch.SBType; + RoutingArch->switch_block_sub_type = Arch.SBSubType; RoutingArch->R_minW_nmos = Arch.R_minW_nmos; RoutingArch->R_minW_pmos = Arch.R_minW_pmos; RoutingArch->Fs = Arch.Fs; + RoutingArch->sub_Fs = Arch.SubFs; RoutingArch->directionality = BI_DIRECTIONAL; if (Arch.Segments) RoutingArch->directionality = Arch.Segments[0].directionality; diff --git a/vpr7_x2p/vpr/SRC/base/place_and_route.c b/vpr7_x2p/vpr/SRC/base/place_and_route.c index e314e0882..f4c53e72b 100644 --- a/vpr7_x2p/vpr/SRC/base/place_and_route.c +++ b/vpr7_x2p/vpr/SRC/base/place_and_route.c @@ -560,8 +560,10 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, free_rr_graph(); build_rr_graph(graph_type, num_types, type_descriptors, nx, ny, grid, - chan_width_x[0], NULL, det_routing_arch.switch_block_type, - det_routing_arch.Fs, det_routing_arch.num_segment, + chan_width_x[0], NULL, + det_routing_arch.switch_block_type, det_routing_arch.Fs, + det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, + det_routing_arch.num_segment, det_routing_arch.num_switch, segment_inf, det_routing_arch.global_route_switch, det_routing_arch.delayless_switch, timing_inf, diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 02a0d3657..cd163d111 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -807,6 +807,8 @@ struct s_det_routing_arch { enum e_directionality directionality; /* UDSD by AY */ int Fs; enum e_switch_block_type switch_block_type; + int sub_Fs; + enum e_switch_block_type switch_block_sub_type; int num_segment; short num_switch; short global_route_switch; diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp index 697a10166..2e56e693f 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp @@ -31,6 +31,8 @@ * +-------------------------------------+ * | 2019/06/11 | Xifan Tang | Created * +-------------------------------------+ + * | 2019/07/02 | Xifan Tang | Modified to support SB subtype and SubFs + * +-------------------------------------+ ***********************************************************************/ /************************************************************************ * This file contains a builder for the complex rr_graph data structure @@ -777,7 +779,8 @@ void build_rr_graph_edges(t_rr_graph* rr_graph, const std::vector device_chan_width, const std::vector segment_inf, int** Fc_in, int** Fc_out, - const enum e_switch_block_type sb_type, const int Fs) { + const enum e_switch_block_type sb_type, const int Fs, + const enum e_switch_block_type sb_subtype, const int subFs) { /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ build_rr_graph_edges_for_source_nodes(rr_graph, grids); @@ -804,7 +807,7 @@ void build_rr_graph_edges(t_rr_graph* rr_graph, /* adapt the switch_block_conn for the GSB nodes */ t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ - sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, sb_type, Fs, segment_inf); + sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, sb_type, Fs, sb_subtype, subFs, segment_inf); /* Build edges for a GSB */ build_edges_for_one_tileable_rr_gsb(rr_graph, &rr_gsb, @@ -904,6 +907,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, INP t_type_ptr types, INP const int L_nx, INP const int L_ny, INP struct s_grid_tile **L_grid, INP const int chan_width, INP const enum e_switch_block_type sb_type, INP const int Fs, + INP const enum e_switch_block_type sb_subtype, INP const int subFs, INP const int num_seg_types, INP const t_segment_inf * segment_inf, INP const int num_switches, INP const int delayless_switch, @@ -1021,7 +1025,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, /* Create edges for a tileable rr_graph */ build_rr_graph_edges(&rr_graph, device_size, grids, device_chan_width, segment_infs, Fc_in, Fc_out, - sb_type, Fs); + sb_type, Fs, sb_subtype, subFs); /************************************************************************ * 6.2 Build direction connection lists diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h index 827adbbc8..5844a55d5 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h @@ -9,6 +9,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, INP t_type_ptr types, INP const int L_nx, INP const int L_ny, INP struct s_grid_tile **L_grid, INP const int chan_width, INP const enum e_switch_block_type sb_type, INP const int Fs, + INP const enum e_switch_block_type sb_subtype, INP const int subFs, INP const int num_seg_types, INP const t_segment_inf * segment_inf, INP const int num_switches, INP const int delayless_switch, diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp index d0eaa901f..27f111091 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp @@ -475,6 +475,8 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, const RRGSB& rr_gsb, const enum e_switch_block_type sb_type, const int Fs, + const enum e_switch_block_type sb_subtype, + const int subFs, const std::vector segment_inf) { t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */ @@ -555,7 +557,7 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, * TODO: This can be improved with different patterns! */ build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, - sb_type, Fs, + sb_subtype, subFs, pass_tracks, start_tracks, &track2track_map); diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h index 6d98e1aa8..5f5a4cb49 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h @@ -23,6 +23,8 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, const RRGSB& rr_gsb, const enum e_switch_block_type sb_type, const int Fs, + const enum e_switch_block_type sb_subtype, + const int subFs, const std::vector segment_inf); RRGSB build_one_tileable_rr_gsb(const DeviceCoordinator& device_range, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c index fde3b52c7..a300ded24 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.c @@ -1,3 +1,41 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: fpga_x2p_bitstream_utils.c + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/07/02 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ +/************************************************************************ + * This file contains most utilized functions for the bitstream generator + ***********************************************************************/ + /***********************************/ /* Synthesizable Verilog Dumping */ /* Xifan TANG, EPFL/LSI */ @@ -30,11 +68,14 @@ #include "fpga_x2p_mux_utils.h" #include "fpga_x2p_globals.h" +#include "fpga_x2p_bitstream_utils.h" + /* Determine the size of input address of a decoder */ int determine_decoder_size(int num_addr_out) { return ceil(log(num_addr_out)/log(2.)); } +static int count_num_sram_bits_one_lut_spice_model(t_spice_model* cur_spice_model) { int num_sram_bits = 0; int iport; @@ -98,6 +139,7 @@ int count_num_sram_bits_one_lut_spice_model(t_spice_model* cur_spice_model) { return num_sram_bits; } +static int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model, int mux_size) { int num_sram_bits = 0; @@ -162,7 +204,7 @@ int count_num_sram_bits_one_mux_spice_model(t_spice_model* cur_spice_model, return num_sram_bits; } - +static int count_num_sram_bits_one_generic_spice_model(t_spice_model* cur_spice_model) { int iport; int num_sram_bits = 0; @@ -227,6 +269,7 @@ int count_num_sram_bits_one_spice_model(t_spice_model* cur_spice_model, return -1; } +static int count_num_mode_bits_one_generic_spice_model(t_spice_model* cur_spice_model) { int iport; int num_mode_bits = 0; @@ -424,20 +467,7 @@ int count_num_reserved_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_mo break; case SPICE_SRAM_SCAN_CHAIN: case SPICE_SRAM_STANDALONE: - /* 4T1R MUX requires more configuration bits */ - if (SPICE_MODEL_STRUCTURE_TREE == cur_spice_model->design_tech_info.mux_info->structure) { - /* For tree-structure: we need 3 times more config. bits */ - num_reserved_conf_bits = 0; - } else if (SPICE_MODEL_STRUCTURE_MULTILEVEL == cur_spice_model->design_tech_info.mux_info->structure) { - /* For multi-level structure: we need 1 more config. bits for each level */ - num_reserved_conf_bits = 0; - } else { - num_reserved_conf_bits = 0; - } - /* For 2:1 MUX, whatever structure, there is only one level */ - if (2 == num_input_size) { - num_reserved_conf_bits = 0; - } + num_reserved_conf_bits = 0; break; default: vpr_printf(TIO_MESSAGE_ERROR,"(FILE:%s,LINE[%d])Invalid type of SRAM organization!\n", @@ -533,7 +563,7 @@ int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model, return num_reserved_conf_bits; } - +static int count_num_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model, enum e_sram_orgz cur_sram_orgz_type) { int num_conf_bits = 0; @@ -611,7 +641,7 @@ int count_num_conf_bits_one_lut_spice_model(t_spice_model* cur_spice_model, return num_conf_bits; } - +static int count_num_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, enum e_sram_orgz cur_sram_orgz_type, int mux_size) { @@ -684,6 +714,7 @@ int count_num_conf_bits_one_mux_spice_model(t_spice_model* cur_spice_model, return num_conf_bits; } +static int count_num_conf_bits_one_generic_spice_model(t_spice_model* cur_spice_model, enum e_sram_orgz cur_sram_orgz_type) { int num_conf_bits = 0; @@ -1098,9 +1129,9 @@ add_mux_conf_bits_to_llist(int mux_size, } /* Add SCFF configutration bits to a linked list*/ -void -add_sram_scff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, - int num_sram_bits, int* sram_bits) { +static +void add_sram_scff_conf_bits_to_llist(t_sram_orgz_info* cur_sram_orgz_info, + int num_sram_bits, int* sram_bits) { int ibit, cur_mem_bit; t_conf_bit** sram_bit = NULL; t_spice_model* cur_sram_spice_model = NULL; @@ -1592,3 +1623,7 @@ void add_mux_conf_bits_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, return; } + +/************************************************************************ + * End of file : fpga_x2p_bitstream_utils.c + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h index a63af4565..6f8c7751d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h @@ -24,6 +24,9 @@ int count_num_reserved_conf_bits_one_spice_model(t_spice_model* cur_spice_model, enum e_sram_orgz cur_sram_orgz_type, int mux_size); +int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc, + enum e_sram_orgz cur_sram_orgz_type); + void add_mux_scff_conf_bits_to_llist(int mux_size, t_sram_orgz_info* cur_sram_orgz_info, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c index c752765a5..4741521fe 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/bitstream/fpga_bitstream_pbtypes.c @@ -30,6 +30,8 @@ #include "fpga_x2p_bitstream_utils.h" #include "fpga_bitstream_primitives.h" +#include "fpga_bitstream_pbtypes.h" + /***** Subroutines *****/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c index e2585a215..c6de5ced7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/router/fpga_x2p_router.c @@ -1,3 +1,41 @@ +/********************************************************** + * MIT License + * + * Copyright (c) 2018 LNIS - The University of Utah + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + ***********************************************************************/ + +/************************************************************************ + * Filename: fpga_x2p_router.c + * Created by: Xifan Tang + * Change history: + * +-------------------------------------+ + * | Date | Author | Notes + * +-------------------------------------+ + * | 2019/07/02 | Xifan Tang | Created + * +-------------------------------------+ + ***********************************************************************/ +/************************************************************************ + * This file contains a breadth-first router which is tailored for packer + ***********************************************************************/ + #include #include #include @@ -14,6 +52,8 @@ #include "fpga_x2p_rr_graph_utils.h" #include "fpga_x2p_pb_rr_graph.h" +#include "fpga_x2p_router.h" + void breadth_first_expand_rr_graph_trace_segment(t_rr_graph* local_rr_graph, t_trace *start_ptr, int remaining_connections_to_sink) { @@ -145,6 +185,7 @@ void breadth_first_add_source_to_rr_graph_heap(t_rr_graph* local_rr_graph, /* A copy of breath_first_add_source_to_heap_cluster * I remove all the use of global variables */ +static void breadth_first_add_one_source_to_rr_graph_heap(t_rr_graph* local_rr_graph, int src_net_index, int src_idx) { @@ -249,6 +290,7 @@ boolean breadth_first_route_one_net_pb_rr_graph(t_rr_graph* local_rr_graph, /* Adapt for the multi-source rr_graph routing */ +static boolean breadth_first_route_one_single_source_net_pb_rr_graph(t_rr_graph* local_rr_graph, int inet, int isrc, int start_isink, @@ -434,6 +476,7 @@ boolean breadth_first_route_one_single_source_net_pb_rr_graph(t_rr_graph* local_ /* Adapt for the multi-source rr_graph routing */ +static boolean breadth_first_route_one_multi_source_net_pb_rr_graph(t_rr_graph* local_rr_graph, int inet) { @@ -550,7 +593,7 @@ boolean breadth_first_route_one_multi_source_net_pb_rr_graph(t_rr_graph* local_r return route_success; } - +static boolean feasible_routing_rr_graph(t_rr_graph* local_rr_graph, boolean verbose) { @@ -845,5 +888,7 @@ boolean try_breadth_first_route_pb_rr_graph(t_rr_graph* local_rr_graph) { return (FALSE); } - +/************************************************************************ + * End of file : fpga_x2p_router.c + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c index 78c0f18d4..73353e59d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/spice/spice_routing.c @@ -23,7 +23,7 @@ ***********************************************************************/ /************************************************************************ - * Filename: rr_blocks.cpp + * Filename: spice_routing.c * Created by: Xifan Tang * Change history: * +-------------------------------------+ @@ -1309,5 +1309,5 @@ void generate_spice_routing_resources(char* subckt_dir, } /************************************************************************ - * End of file : rr_blocks.cpp + * End of file : spice_routing.c ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c b/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c index 88a4e7a29..b0d6bdbc9 100755 --- a/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c +++ b/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c @@ -459,8 +459,10 @@ static void alloc_routing_structs(struct s_router_opts router_opts, } build_rr_graph(graph_type, num_types, dummy_type_descriptors, nx, ny, grid, - chan_width_x[0], NULL, det_routing_arch.switch_block_type, - det_routing_arch.Fs, det_routing_arch.num_segment, + chan_width_x[0], NULL, + det_routing_arch.switch_block_type, det_routing_arch.Fs, + det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, + det_routing_arch.num_segment, det_routing_arch.num_switch, segment_inf, det_routing_arch.global_route_switch, det_routing_arch.delayless_switch, timing_inf, diff --git a/vpr7_x2p/vpr/SRC/route/route_common.c b/vpr7_x2p/vpr/SRC/route/route_common.c index 165b54f4a..58cbfca31 100755 --- a/vpr7_x2p/vpr/SRC/route/route_common.c +++ b/vpr7_x2p/vpr/SRC/route/route_common.c @@ -297,8 +297,10 @@ boolean try_route(int width_fac, struct s_router_opts router_opts, /* Set up the routing resource graph defined by this FPGA architecture. */ build_rr_graph(graph_type, num_types, type_descriptors, nx, ny, grid, - chan_width_x[0], NULL, det_routing_arch.switch_block_type, - det_routing_arch.Fs, det_routing_arch.num_segment, + chan_width_x[0], NULL, + det_routing_arch.switch_block_type, det_routing_arch.Fs, + det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, + det_routing_arch.num_segment, det_routing_arch.num_switch, segment_inf, det_routing_arch.global_route_switch, det_routing_arch.delayless_switch, timing_inf, diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph.c b/vpr7_x2p/vpr/SRC/route/rr_graph.c index ff6d76b3f..afe937e9a 100755 --- a/vpr7_x2p/vpr/SRC/route/rr_graph.c +++ b/vpr7_x2p/vpr/SRC/route/rr_graph.c @@ -211,7 +211,8 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types, INP t_type_ptr types, INP int L_nx, INP int L_ny, INP struct s_grid_tile **L_grid, INP int chan_width, INP struct s_chan_width_dist *chan_capacity_inf, - INP enum e_switch_block_type sb_type, INP int Fs, INP int num_seg_types, + INP enum e_switch_block_type sb_type, INP int Fs, + INP enum e_switch_block_type sb_sub_type, INP int sub_Fs, INP int num_seg_types, INP int num_switches, INP t_segment_inf * segment_inf, INP int global_route_switch, INP int delayless_switch, INP t_timing_inf timing_inf, INP int wire_to_ipin_switch, @@ -225,7 +226,9 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types, build_tileable_unidir_rr_graph(L_num_types, types, L_nx, L_ny, L_grid, chan_width, - sb_type, Fs, num_seg_types, segment_inf, + sb_type, Fs, + sb_sub_type, sub_Fs, + num_seg_types, segment_inf, num_switches, delayless_switch, timing_inf, wire_to_ipin_switch, base_cost_type, directs, num_directs, ignore_Fc_0, Warnings); diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph.h b/vpr7_x2p/vpr/SRC/route/rr_graph.h index 9e23b0187..1a84393b7 100755 --- a/vpr7_x2p/vpr/SRC/route/rr_graph.h +++ b/vpr7_x2p/vpr/SRC/route/rr_graph.h @@ -28,6 +28,7 @@ void build_rr_graph(INP t_graph_type graph_type, INP struct s_chan_width_dist *chan_capacity_inf, INP enum e_switch_block_type sb_type, INP int Fs, + INP enum e_switch_block_type sb_sub_type, INP int sub_Fs, INP int num_seg_types, INP int num_switches, INP t_segment_inf * segment_inf, From 8f5ad2eb67ac39e5e6ee1db83a98c058d9109a0e Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Tue, 2 Jul 2019 10:10:48 -0600 Subject: [PATCH 12/84] Snapshot of progress --- .../vpr/SRC/fpga_x2p/verilog/verilog_api.c | 2 +- .../verilog/verilog_compact_netlist.c | 32 +++--- .../verilog/verilog_compact_netlist.h | 3 +- .../fpga_x2p/verilog/verilog_report_timing.c | 21 ++-- .../SRC/fpga_x2p/verilog/verilog_routing.c | 98 ++++++++++++------- .../SRC/fpga_x2p/verilog/verilog_routing.h | 9 +- .../vpr/SRC/fpga_x2p/verilog/verilog_sdc.c | 18 ++-- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 2 +- .../SRC/fpga_x2p/verilog/verilog_tcl_utils.c | 10 +- .../SRC/fpga_x2p/verilog/verilog_tcl_utils.h | 6 +- .../verilog/verilog_top_netlist_utils.c | 23 +++-- .../verilog/verilog_top_netlist_utils.h | 4 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 28 +++++- 13 files changed, 162 insertions(+), 94 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index 20ea51ecd..41b2c634c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -277,7 +277,7 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, num_rr_nodes, rr_node, rr_node_indices, num_clocks, vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy, - *(Arch.spice)); + *(Arch.spice), vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); /* Dump SDC constraints */ /* Output SDC to contrain the P&R flow diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 4187a0904..5e83ecca7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -750,7 +750,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, static void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - const RRGSB& rr_sb) { + const RRGSB& rr_sb, + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -797,7 +798,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, - FALSE); /* Do not specify the direction of port */ + FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } fprintf(fp, "\n"); @@ -850,7 +851,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz static void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp) { + FILE* fp, bool is_explicit_mapping) { DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range(); /* Check the file handler*/ @@ -863,7 +864,7 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i for (size_t ix = 0; ix < sb_range.get_x(); ++ix) { for (size_t iy = 0; iy < sb_range.get_y(); ++iy) { const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy); - dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, rr_sb); + dump_compact_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, rr_sb, is_explicit_mapping); } } @@ -878,7 +879,8 @@ void dump_compact_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_i static void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - const RRGSB& rr_gsb, t_rr_type cb_type) { + const RRGSB& rr_gsb, t_rr_type cb_type, + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -928,7 +930,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), cur_ipin_node->xlow, cur_ipin_node->ylow, - FALSE); /* Do not specify direction of port */ + FALSE, is_explicit_mapping); /* Do not specify direction of port */ fprintf(fp, ", \n"); } } @@ -974,7 +976,8 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ /* Call the sub-circuits for connection boxes */ static void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp) { + FILE* fp, + bool is_explicit_mapping) { DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range(); /* Check the file handler*/ @@ -994,7 +997,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or /* X - channels [1...nx][0..ny]*/ if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x())) &&(true == rr_gsb.is_cb_exist(CHANX))) { - dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX); + dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX, is_explicit_mapping); } /* Get X-channel CB coordinator */ @@ -1002,7 +1005,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or /* Y - channels [1...ny][0..nx]*/ if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x())) &&(true == rr_gsb.is_cb_exist(CHANY))) { - dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY); + dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY, is_explicit_mapping); } } } @@ -1183,7 +1186,8 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, t_ivec*** LL_rr_node_indices, int num_clock, boolean compact_routing_hierarchy, - t_spice verilog) { + t_spice verilog, + bool is_explicit_mapping) { FILE* fp = NULL; char* formatted_dir_path = NULL; char* temp_include_file_path = NULL; @@ -1243,16 +1247,16 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, /* Quote Routing structures: Switch Boxes */ if (TRUE == compact_routing_hierarchy ) { - dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp); + dump_compact_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); } else { - dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp); + dump_verilog_defined_switch_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); /* BC: Explicit mapping not done because we will erase this in the future*/ } /* Quote Routing structures: Connection Boxes */ if (TRUE == compact_routing_hierarchy ) { - dump_compact_verilog_defined_connection_boxes(cur_sram_orgz_info, fp); + dump_compact_verilog_defined_connection_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); } else { - dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp); + dump_verilog_defined_connection_boxes(cur_sram_orgz_info, fp, is_explicit_mapping); } /* Quote defined Logic blocks subckts (Grids) */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h index cf3898dc8..5086722d2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.h @@ -26,5 +26,6 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, t_ivec*** LL_rr_node_indices, int num_clock, boolean compact_routing_hierarchy, - t_spice verilog); + t_spice verilog, + bool is_explicit_verilog); #endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c index f1f6ca6a7..87487220c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c @@ -284,7 +284,7 @@ void verilog_generate_one_report_timing_within_sb(FILE* fp, fprintf(fp, "%s/", rr_sb.gen_sb_verilog_instance_name()); /* Find which side the ending pin locates, and determine the coordinate */ - dump_verilog_one_sb_routing_pin(fp, rr_sb, src_rr_node); + dump_verilog_one_sb_routing_pin(fp, rr_sb, src_rr_node, false); fprintf(fp, " -to "); @@ -326,7 +326,7 @@ void verilog_generate_one_report_timing_within_sb(FILE* fp, fprintf(fp, "%s/", gen_verilog_one_sb_instance_name(cur_sb_info)); /* Find which side the ending pin locates, and determine the coordinate */ - dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node); + dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node, false); fprintf(fp, " -to "); @@ -906,7 +906,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, "%s/", src_sb.gen_sb_verilog_instance_name()); /* Find which side the ending pin locates, and determine the coordinate */ - dump_verilog_one_sb_routing_pin(fp, src_sb, drive_rr_node); + dump_verilog_one_sb_routing_pin(fp, src_sb, drive_rr_node, false); /* Switch depends on the type of des_rr_node */ switch(des_rr_node->type) { @@ -1287,7 +1287,7 @@ void dump_verilog_one_sb_wire_segemental_report_timing(FILE* fp, fprintf(fp, "%s/", gen_verilog_one_sb_instance_name(src_sb_info)); /* Find which side the ending pin locates, and determine the coordinate */ - dump_verilog_one_sb_routing_pin(fp, src_sb_info, drive_rr_node); + dump_verilog_one_sb_routing_pin(fp, src_sb_info, drive_rr_node, false); /* Switch depends on the type of des_rr_node */ switch(des_rr_node->type) { @@ -2079,7 +2079,7 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp, fprintf(fp, "%s/", rr_sb.gen_sb_verilog_instance_name()); /* output pin name */ dump_verilog_one_sb_routing_pin(fp, rr_sb, - wire_rr_node->drive_rr_nodes[iedge]); + wire_rr_node->drive_rr_nodes[iedge], false); fprintf(fp, " -to "); /* output instance name */ fprintf(fp, "%s/", @@ -2137,14 +2137,14 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp, rr_sb.gen_sb_verilog_instance_name()); /* output pin name */ dump_verilog_one_sb_routing_pin(fp, rr_sb, - wire_rr_node->drive_rr_nodes[iedge]); + wire_rr_node->drive_rr_nodes[iedge], false); fprintf(fp, " -to "); /* output instance name */ fprintf(fp, "%s/", next_sb.gen_sb_verilog_instance_name()); /* Find which side the ending pin locates, and determine the coordinate */ dump_verilog_one_sb_routing_pin(fp, next_sb, - wire_rr_node); + wire_rr_node, false); /* Print through pins */ if (TRUE == sdc_opts.print_thru_pins) { fprintf(fp, " -through_pins "); @@ -2245,7 +2245,8 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp, gen_verilog_one_sb_instance_name(cur_sb_info)); /* output pin name */ dump_verilog_one_sb_routing_pin(fp, cur_sb_info, - wire_rr_node->drive_rr_nodes[iedge]); + wire_rr_node->drive_rr_nodes[iedge], + false); fprintf(fp, " -to "); /* output instance name */ fprintf(fp, "%s/", @@ -2289,14 +2290,14 @@ void verilog_generate_one_routing_wire_report_timing(FILE* fp, gen_verilog_one_sb_instance_name(cur_sb_info)); /* output pin name */ dump_verilog_one_sb_routing_pin(fp, cur_sb_info, - wire_rr_node->drive_rr_nodes[iedge]); + wire_rr_node->drive_rr_nodes[iedge], false); fprintf(fp, " -to "); /* output instance name */ fprintf(fp, "%s/", gen_verilog_one_sb_instance_name(next_sb)); /* Find which side the ending pin locates, and determine the coordinate */ dump_verilog_one_sb_routing_pin(fp, next_sb, - wire_rr_node); + wire_rr_node, false); /* Print through pins */ if (TRUE == sdc_opts.print_thru_pins) { fprintf(fp, " -through_pins "); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 1e69c6998..e052d24b0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -311,7 +311,8 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, - boolean dump_port_type) { + boolean dump_port_type, + bool is_explicit_mapping) { int height; t_type_ptr type = NULL; char* verilog_port_type = NULL; @@ -355,7 +356,13 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, if (TRUE == dump_port_type) { fprintf(fp, "%s ", verilog_port_type); } + if (true == is_explicit_mapping) { + fprintf(fp, ".out("); + } fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } if (TRUE == dump_port_type) { fprintf(fp, ",\n"); } @@ -511,7 +518,8 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, enum e_side chan_side, t_rr_node* cur_rr_node, int actual_fan_in, - t_rr_node* drive_rr_node) { + t_rr_node* drive_rr_node, + bool is_explicit_mapping) { /* Check the file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n", @@ -554,7 +562,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_node), grid_x, grid_y, - FALSE); /* Do not dump the direction of the port! */ + FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ break; case CHANX: case CHANY: @@ -600,7 +608,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp, int chan_side, t_rr_node* cur_rr_node, int actual_fan_in, - t_rr_node* drive_rr_node) { + t_rr_node* drive_rr_node, + bool is_explicit_mapping) { int side, index; int grid_x, grid_y; char* chan_name = NULL; @@ -655,7 +664,7 @@ void dump_verilog_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], grid_x, grid_y, - FALSE); /* Do not dump the direction of the port! */ + FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ break; case CHANX: case CHANY: @@ -760,7 +769,7 @@ void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, cur_sb_info->opin_rr_node_grid_side[side][index], - grid_x, grid_y, FALSE); + grid_x, grid_y, FALSE, is_explicit_mapping); fprintf(fp, ";\n"); input_cnt++; break; @@ -1016,7 +1025,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]), - grid_x, grid_y, FALSE); + grid_x, grid_y, FALSE, is_explicit_mapping); fprintf(fp, ";\n"); input_cnt++; break; @@ -1394,11 +1403,12 @@ void dump_verilog_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (0 == num_drive_rr_nodes) { /* Print a special direct connection*/ dump_verilog_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node, - num_drive_rr_nodes, cur_rr_node); + num_drive_rr_nodes, cur_rr_node, is_explicit_mapping); } else if (1 == num_drive_rr_nodes) { /* Print a direct connection*/ dump_verilog_switch_box_short_interc(fp, cur_sb_info, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]); + num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID], + is_explicit_mapping); } else if (1 < num_drive_rr_nodes) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_switch_box_mux(cur_sram_orgz_info, fp, cur_sb_info, chan_side, cur_rr_node, @@ -1445,11 +1455,13 @@ void dump_verilog_unique_switch_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (0 == num_drive_rr_nodes) { /* Print a special direct connection*/ dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, cur_rr_node); + num_drive_rr_nodes, cur_rr_node, + is_explicit_mapping); } else if (1 == num_drive_rr_nodes) { /* Print a direct connection*/ dump_verilog_unique_switch_box_short_interc(fp, rr_sb, chan_side, cur_rr_node, - num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID]); + num_drive_rr_nodes, drive_rr_nodes[DEFAULT_SWITCH_ID], + is_explicit_mapping); } else if (1 < num_drive_rr_nodes) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_unique_switch_box_mux(cur_sram_orgz_info, fp, rr_sb, chan_side, cur_rr_node, @@ -1696,7 +1708,8 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, const RRGSB& rr_sb, enum e_side sb_side, size_t seg_id, - boolean dump_port_type) { + boolean dump_port_type, + bool is_explicit_mapping) { /* Check file handler*/ if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR, @@ -1764,7 +1777,7 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, rr_sb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_sb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_sb.get_opin_node(side_manager.get_side(), inode)->ylow, - dump_port_type); /* Dump the direction of the port ! */ + dump_port_type, is_explicit_mapping); /* Dump the direction of the port ! */ if (FALSE == dump_port_type) { fprintf(fp, ",\n"); } @@ -1861,7 +1874,9 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr fprintf(fp, ",\n"); } - dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, seg_id, TRUE); + dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, + seg_id, TRUE, + is_explicit_mapping); /* Put down configuration port */ /* output of each configuration bit */ @@ -1962,7 +1977,8 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr static void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_orgz_info, char* verilog_dir, char* subckt_dir, - const RRGSB& rr_sb) { + const RRGSB& rr_sb, + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; @@ -2029,7 +2045,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE); /* Dump the direction of the port ! */ + TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2110,7 +2126,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or fprintf(fp, ",\n"); } - dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE); + dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_gsb, side_manager.get_side(), seg_ids[iseg], FALSE, is_explicit_mapping); /* Put down configuration port */ /* output of each configuration bit */ @@ -2272,7 +2288,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or rr_gsb.get_opin_node_grid_side(side_manager.get_side(), inode), rr_gsb.get_opin_node(side_manager.get_side(), inode)->xlow, rr_gsb.get_opin_node(side_manager.get_side(), inode)->ylow, - TRUE); /* Dump the direction of the port ! */ + TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2474,7 +2490,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info cur_sb_info->opin_rr_node_grid_side[side][inode], cur_sb_info->opin_rr_node[side][inode]->xlow, cur_sb_info->opin_rr_node[side][inode]->ylow, - TRUE); /* Dump the direction of the port ! */ + TRUE, is_explicit_mapping); /* Dump the direction of the port ! */ } } @@ -2663,7 +2679,8 @@ int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* c static void dump_verilog_connection_box_short_interc(FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + bool is_explicit_mapping) { t_rr_node* drive_rr_node = NULL; int iedge, check_flag; int xlow, ylow, height, index; @@ -2717,7 +2734,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ - FALSE); /* Do not specify the direction of this pin */ + FALSE, is_explicit_mapping); /* Do not specify the direction of this pin */ /* End */ fprintf(fp, ";\n"); @@ -2729,7 +2746,8 @@ void dump_verilog_connection_box_short_interc(FILE* fp, /* SRC rr_node is the IPIN of a grid.*/ void dump_verilog_connection_box_short_interc(FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node) { + t_rr_node* src_rr_node, + bool is_explicit_mapping) { t_rr_node* drive_rr_node = NULL; int iedge, check_flag; int xlow, ylow, height, side, index; @@ -2793,7 +2811,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ - FALSE); /* Do not specify the direction of this pin */ + FALSE, is_explicit_mapping); /* Do not specify the direction of this pin */ /* End */ fprintf(fp, ";\n"); @@ -2940,7 +2958,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ - FALSE); /* Do not specify the direction of port */ + FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ @@ -3158,8 +3176,15 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, } /* connect to input bus*/ - fprintf(fp, "%s_size%d_%d_inbus,", + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "%s_size%d_%d_inbus", verilog_model->prefix, mux_size, verilog_model->cnt); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ", "); /* output port*/ xlow = src_rr_node->xlow; @@ -3174,7 +3199,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ - FALSE); /* Do not specify the direction of port */ + FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ @@ -3280,7 +3305,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (1 == src_rr_node->fan_in) { /* Print a direct connection*/ - dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node); + dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node, is_explicit_mapping); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, @@ -3309,7 +3334,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (1 == src_rr_node->fan_in) { /* Print a direct connection*/ - dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node); + dump_verilog_connection_box_short_interc(fp, cur_cb_info, src_rr_node, is_explicit_mapping); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, cur_cb_info, @@ -3500,7 +3525,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, - TRUE); + TRUE, is_explicit_mapping); } } @@ -3720,7 +3745,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, - TRUE); + TRUE, is_explicit_mapping); } } @@ -3900,7 +3925,8 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* Output unique modules */ for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) { const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb); - dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror); + dump_verilog_routing_switch_box_unique_module(cur_sram_orgz_info, verilog_dir, + subckt_dir, unique_mirror, explicit_port_mapping); } /* Restore sram_orgz_info to the base */ @@ -3923,7 +3949,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_routing_switch_box_subckt(cur_sram_orgz_info, verilog_dir, subckt_dir, &(sb_info[ix][iy]), compact_routing_hierarchy, - FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + explicit_port_mapping); update_spice_models_routing_index_high(ix, iy, SOURCE, arch.spice->num_spice_model, arch.spice->spice_models); } } @@ -3941,7 +3967,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb); dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANX, - FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + explicit_port_mapping); } /* Y - channels [1...ny][0..nx]*/ @@ -3949,7 +3975,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb); dump_verilog_routing_connection_box_unique_module(cur_sram_orgz_info, verilog_dir, subckt_dir, unique_mirror, CHANY, - FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + explicit_port_mapping); } /* Restore sram_orgz_info to the base */ @@ -3979,7 +4005,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, verilog_dir, subckt_dir, &(cbx_info[ix][iy]), compact_routing_hierarchy, - FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + explicit_port_mapping); } update_spice_models_routing_index_high(ix, iy, CHANX, arch.spice->num_spice_model, arch.spice->spice_models); } @@ -3995,7 +4021,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, verilog_dir, subckt_dir, &(cby_info[ix][iy]), compact_routing_hierarchy, - FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog); + explicit_port_mapping); } update_spice_models_routing_index_high(ix, iy, CHANY, arch.spice->num_spice_model, arch.spice->spice_models); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h index e3038477b..b126300e7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h @@ -14,7 +14,8 @@ void dump_verilog_routing_chan_subckt(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, int pin_index, int side, int x, int y, - boolean dump_port_type); + boolean dump_port_type, + bool is_explicit_mapping); void dump_verilog_grid_side_pins(FILE* fp, t_rr_type pin_type, int x, int y, int side, @@ -31,7 +32,8 @@ void dump_verilog_switch_box_short_interc(FILE* fp, int chan_side, t_rr_node* cur_rr_node, int actual_fan_in, - t_rr_node* drive_rr_node); + t_rr_node* drive_rr_node, + bool is_explicit_mapping); void dump_verilog_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, @@ -76,7 +78,8 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info void dump_verilog_connection_box_short_interc(FILE* fp, t_cb* cur_cb_info, - t_rr_node* src_rr_node); + t_rr_node* src_rr_node, + bool is_explicit_mapping); void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index 20a988a09..a57ff6416 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -468,7 +468,7 @@ void verilog_generate_sdc_constrain_one_sb_path(FILE* fp, fprintf(fp, " -from "); fprintf(fp, "%s/", gen_verilog_one_sb_instance_name(cur_sb_info)); - dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node); + dump_verilog_one_sb_routing_pin(fp, cur_sb_info, src_rr_node, false); fprintf(fp, " -to "); @@ -513,7 +513,7 @@ void verilog_generate_sdc_constrain_one_sb_path(FILE* fp, fprintf(fp, " -from "); fprintf(fp, "%s/", rr_gsb.gen_sb_verilog_instance_name()); - dump_verilog_one_sb_routing_pin(fp, rr_gsb, src_rr_node); + dump_verilog_one_sb_routing_pin(fp, rr_gsb, src_rr_node, false); fprintf(fp, " -to "); @@ -638,7 +638,7 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, des_rr_node->xlow, des_rr_node->ylow, - FALSE); + FALSE, false); /* If src_node == des_node, this is a metal wire */ fprintf(fp, " %.2g", tmax); @@ -721,7 +721,7 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, des_rr_node_grid_side, mirror_ipin_node->xlow, mirror_ipin_node->ylow, - FALSE); + FALSE, false); /* If src_node == des_node, this is a metal wire */ fprintf(fp, " %.2g", tmax); @@ -1639,7 +1639,8 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp) { fprintf(fp, "%s/", rr_sb.gen_sb_verilog_instance_name()); dump_verilog_one_sb_routing_pin(fp, rr_sb, - rr_sb.get_opin_node(side_manager.get_side(), inode)); + rr_sb.get_opin_node(side_manager.get_side(), + inode), false); fprintf(fp, "\n"); } } @@ -1708,7 +1709,8 @@ void verilog_generate_sdc_disable_unused_sbs(FILE* fp, fprintf(fp, "%s/", gen_verilog_one_sb_instance_name(cur_sb_info)); dump_verilog_one_sb_routing_pin(fp, cur_sb_info, - cur_sb_info->opin_rr_node[side][inode]); + cur_sb_info->opin_rr_node[side][inode], + false); fprintf(fp, "\n"); } } @@ -1758,7 +1760,7 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), ipin_node->xlow, ipin_node->ylow, - FALSE); /* Do not specify direction of port */ + FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } } @@ -1816,7 +1818,7 @@ void verilog_generate_sdc_disable_one_unused_cb(FILE* fp, cur_cb_info->ipin_rr_node_grid_side[side][inode], cur_cb_info->ipin_rr_node[side][inode]->xlow, cur_cb_info->ipin_rr_node[side][inode]->ylow, - FALSE); /* Do not specify direction of port */ + FALSE, false); /* Do not specify direction of port */ fprintf(fp, "\n"); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index 269516054..b91ffc3e6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -2345,7 +2345,7 @@ void dump_verilog_cmos_mux_mem_submodule(FILE* fp, * 3. output ports * 4. bl/wl ports */ - dump_verilog_mem_module_port_map(fp, mem_model, TRUE, 0, num_conf_bits, FALSE); + dump_verilog_mem_module_port_map(fp, mem_model, TRUE, 0, num_conf_bits, my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, ");\n"); /* Dump all the submodules */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c index 845bb7cf5..256f281a9 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.c @@ -145,7 +145,8 @@ void dump_verilog_one_sb_chan_pin(FILE* fp, /* Output the pin name of a routing wire in a SB */ void dump_verilog_one_sb_routing_pin(FILE* fp, const RRGSB& rr_sb, - t_rr_node* cur_rr_node) { + t_rr_node* cur_rr_node, + bool is_explicit_mapping) { int side; /* Check the file handler */ @@ -186,7 +187,7 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, mirror_node->xlow, mirror_node->ylow, - FALSE); /* Do not specify direction of port */ + FALSE,is_explicit_mapping); /* Do not specify direction of port */ break; } case CHANX: @@ -206,7 +207,8 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, /* Output the pin name of a routing wire in a SB */ void dump_verilog_one_sb_routing_pin(FILE* fp, t_sb* cur_sb_info, - t_rr_node* cur_rr_node) { + t_rr_node* cur_rr_node, + bool is_explicit_mapping) { int side; /* Check the file handler */ @@ -229,7 +231,7 @@ void dump_verilog_one_sb_routing_pin(FILE* fp, side, cur_rr_node->xlow, cur_rr_node->ylow, - FALSE); /* Do not specify direction of port */ + FALSE, is_explicit_mapping); /* Do not specify direction of port */ break; case CHANX: case CHANY: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h index e0b9652cf..1db242a40 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_tcl_utils.h @@ -20,11 +20,13 @@ void dump_verilog_one_sb_chan_pin(FILE* fp, void dump_verilog_one_sb_routing_pin(FILE* fp, const RRGSB& rr_sb, - t_rr_node* cur_rr_node); + t_rr_node* cur_rr_node, + bool is_explicit_mapping); void dump_verilog_one_sb_routing_pin(FILE* fp, t_sb* cur_sb_info, - t_rr_node* cur_rr_node); + t_rr_node* cur_rr_node, + bool is_explicit_mapping); DeviceCoordinator get_chan_node_ending_cb(t_rr_node* src_rr_node, t_rr_node* end_rr_node); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 90fdf268d..267dd2c4a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -607,7 +607,8 @@ void dump_verilog_defined_channels(FILE* fp, static void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - t_cb cur_cb_info) { + t_cb cur_cb_info, + bool is_explicit_mapping) { int itrack, inode, side, x, y; int side_cnt = 0; @@ -679,7 +680,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf cur_cb_info.ipin_rr_node_grid_side[side][inode], cur_cb_info.ipin_rr_node[side][inode]->xlow, cur_cb_info.ipin_rr_node[side][inode]->ylow, - FALSE); /* Do not specify direction of port */ + FALSE, is_explicit_mapping); /* Do not specify direction of port */ fprintf(fp, ", \n"); } } @@ -735,7 +736,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf /* Call the sub-circuits for connection boxes */ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp) { + FILE* fp, bool is_explicit_mapping) { int ix, iy; /* Check the file handler*/ @@ -750,7 +751,8 @@ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, for (ix = 1; ix < (nx + 1); ix++) { if ((TRUE == is_cb_exist(CHANX, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cbx_info[ix][iy]))) { - dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cbx_info[ix][iy]); + dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cbx_info[ix][iy], + is_explicit_mapping); } } } @@ -759,7 +761,8 @@ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, for (iy = 1; iy < (ny + 1); iy++) { if ((TRUE == is_cb_exist(CHANY, ix, iy)) &&(0 < count_cb_info_num_ipin_rr_nodes(cby_info[ix][iy]))) { - dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cby_info[ix][iy]); + dump_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, cby_info[ix][iy], + is_explicit_mapping); } } } @@ -774,7 +777,8 @@ void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, static void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - t_sb cur_sb_info) { + t_sb cur_sb_info, + bool is_explicit_mapping) { int ix, iy, side, itrack, x, y, inode; /* Check the file handler*/ @@ -823,7 +827,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, cur_sb_info.opin_rr_node_grid_side[side][inode], cur_sb_info.opin_rr_node[side][inode]->xlow, cur_sb_info.opin_rr_node[side][inode]->ylow, - FALSE); /* Do not specify the direction of port */ + FALSE, is_explicit_mapping); /* Do not specify the direction of port */ fprintf(fp, ",\n"); } fprintf(fp, "\n"); @@ -869,7 +873,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, } void dump_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp) { + FILE* fp, bool is_explicit_mapping) { int ix, iy; /* Check the file handler*/ @@ -881,7 +885,8 @@ void dump_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, for (ix = 0; ix < (nx + 1); ix++) { for (iy = 0; iy < (ny + 1); iy++) { - dump_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, sb_info[ix][iy]); + dump_verilog_defined_one_switch_box(cur_sram_orgz_info, fp, sb_info[ix][iy], + is_explicit_mapping); } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h index c25c42756..74549b8d6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h @@ -13,10 +13,10 @@ void dump_verilog_defined_channels(FILE* fp, t_ivec*** LL_rr_node_indices); void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp); + FILE* fp, bool is_explicit_mapping); void dump_verilog_defined_switch_boxes(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp); + FILE* fp, bool is_explicit_mapping); void dump_verilog_clb2clb_directs(FILE* fp, int num_directs, t_clb_to_clb_directs* direct); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 3a5e134f5..5b7f472c0 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -905,7 +905,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, if ((TRUE == require_explicit_port_map) && (TRUE == cur_spice_model->dump_explicit_port_map)) { fprintf(fp, ".%s(", - cur_spice_model_port->lib_name); + /* cur_spice_model_port->lib_name); /* Old version*/ + cur_spice_model_port->prefix); } fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix, @@ -3155,10 +3156,10 @@ void dump_verilog_mem_sram_submodule(FILE* fp, case SPICE_SRAM_STANDALONE: /* SRAM subckts*/ /* Only dump the global ports belonging to a spice_model */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } - fprintf(fp, "%s_out[%d:%d], ", + fprintf(fp, "%s_in[%d:%d], ", cur_sram_verilog_model->prefix, lsb, msb); /* Input*/ fprintf(fp, "%s_out[%d:%d], %s_outb[%d:%d] ", cur_sram_verilog_model->prefix, lsb, msb, @@ -3171,21 +3172,42 @@ void dump_verilog_mem_sram_submodule(FILE* fp, } if (SPICE_MODEL_MUX == cur_verilog_model->type) { /* Input of Scan-chain DFF, should be connected to the output of its precedent */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[0].prefix); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, -1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", \n"); // /* Output of Scan-chain DFF, should be connected to the output of its successor */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[1].prefix); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", \n"); // + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[2].prefix); + } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, 1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } break; } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ From 60f7ab046535a8f64941941e23f54ba66f4d5072 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Tue, 2 Jul 2019 10:16:10 -0600 Subject: [PATCH 13/84] Start heterogeneous dev --- ERI_demo/ERI.sh | 49 + ERI_demo/eri_demo.sh | 42 + ERI_demo/my_eri_demo.sh | 42 + ERI_demo/pipelined_1b_adder.act | 61 + ERI_demo/pipelined_1b_adder.blif | 152 +++ ERI_demo/pipelined_32b_adder.act | 331 +++++ ERI_demo/pipelined_32b_adder.blif | 278 ++++ ERI_demo/pipelined_32b_adder.v | 63 + ERI_demo/pipelined_32b_adder_ERI_demo_tb.v | 156 +++ .../k6_N10_sram_chain_HC_DPRAM_template.xml | 1155 +++++++++++++++++ 10 files changed, 2329 insertions(+) create mode 100755 ERI_demo/ERI.sh create mode 100644 ERI_demo/eri_demo.sh create mode 100644 ERI_demo/my_eri_demo.sh create mode 100644 ERI_demo/pipelined_1b_adder.act create mode 100644 ERI_demo/pipelined_1b_adder.blif create mode 100644 ERI_demo/pipelined_32b_adder.act create mode 100644 ERI_demo/pipelined_32b_adder.blif create mode 100644 ERI_demo/pipelined_32b_adder.v create mode 100644 ERI_demo/pipelined_32b_adder_ERI_demo_tb.v create mode 100644 fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml diff --git a/ERI_demo/ERI.sh b/ERI_demo/ERI.sh new file mode 100755 index 000000000..0492a5e2b --- /dev/null +++ b/ERI_demo/ERI.sh @@ -0,0 +1,49 @@ +#!/bin/bash +# Regression test version 1.0 + +# Set variables +my_pwd=$PWD +fpga_flow_scripts=${my_pwd}/fpga_flow/scripts +vpr_path=${my_pwd}/vpr7_x2p/vpr +benchmark="pipelined_32b_adder" +include_netlists="_include_netlists.v" +compiled_file="compiled_$benchmark" +tb_formal_postfix="_top_formal_verification_random_tb" +verilog_output_dirname="${benchmark}_Verilog" +log_file="${benchmark}_sim.log" +new_reg_sh="${PWD}/ERI_demo/my_eri_demo.sh" +template_sh="${PWD}/ERI_demo/eri_demo.sh" + + +# Remove former log file +rm -f $log_file +rm -f $compiled_file + +# Rewite script +cd $fpga_flow_scripts + +perl rewrite_path_in_file.pl -i $template_sh -o $new_reg_sh + +cd $my_pwd + +# Start the script -> run the fpga generation -> run the simulation -> check the log file +source $new_reg_sh # Leave us in vpr folder +iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix +vvp $compiled_file -j 16 >> $log_file + +result=`grep "Succeed" $log_file` +if ["$result" = ""]; then + result=`grep "Failed" $log_file` + if ["$result" = ""]; then + echo "Unexpected error, Verification didn't run" + cd $my_pwd + exit 1 + else + echo "Verification failed" + cd $my_pwd + exit 2 + fi +else + echo "Verification succeed" + cd $my_pwd +fi diff --git a/ERI_demo/eri_demo.sh b/ERI_demo/eri_demo.sh new file mode 100644 index 000000000..112078dc5 --- /dev/null +++ b/ERI_demo/eri_demo.sh @@ -0,0 +1,42 @@ +#!/bin/bash +# Example of how to run vpr + +# Set variables +# For FPGA-Verilog ONLY +benchmark="pipelined_32b_adder" +OpenFPGA_path="OPENFPGAPATHKEYWORD" +verilog_output_dirname="${benchmark}_Verilog" +verilog_output_dirpath="$vpr_path" +tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" +# VPR critical inputs +template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml" +arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml" +blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif" +act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act " +verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v" +vpr_route_chan_width="300" +fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts" +ff_path="$vpr_path/VerilogNetlists/ff.v" +new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" +ff_keyword="GENERATED_DIR_KEYWORD" +ff_include_path="$verilog_output_dirpath/$verilog_output_dirname" +arch_ff_keyword="FFPATHKEYWORD" + +# Remove previous designs +#rm -rf $verilog_output_dirpath/$verilog_output_dirname + +mkdir ${OpenFPGA_path}/fpga_flow/arch/generated + +cd $fpga_flow_scripts +perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file +perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path + +# Move to vpr folder +cd $vpr_path + +# Run VPR +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator #--fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy + +cd $fpga_flow_scripts +perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path +cd - diff --git a/ERI_demo/my_eri_demo.sh b/ERI_demo/my_eri_demo.sh new file mode 100644 index 000000000..2e6220ba3 --- /dev/null +++ b/ERI_demo/my_eri_demo.sh @@ -0,0 +1,42 @@ +#!/bin/bash +# Example of how to run vpr + +# Set variables +# For FPGA-Verilog ONLY +benchmark="pipelined_32b_adder" +OpenFPGA_path="/research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA" +verilog_output_dirname="${benchmark}_Verilog" +verilog_output_dirpath="$vpr_path" +tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" +# VPR critical inputs +template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml" +arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml" +blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif" +act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act " +verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v" +vpr_route_chan_width="300" +fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts" +ff_path="$vpr_path/VerilogNetlists/ff.v" +new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" +ff_keyword="GENERATED_DIR_KEYWORD" +ff_include_path="$verilog_output_dirpath/$verilog_output_dirname" +arch_ff_keyword="FFPATHKEYWORD" + +# Remove previous designs +#rm -rf $verilog_output_dirpath/$verilog_output_dirname + +mkdir ${OpenFPGA_path}/fpga_flow/arch/generated + +cd $fpga_flow_scripts +perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file +perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path + +# Move to vpr folder +cd $vpr_path + +# Run VPR +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator #--fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy + +cd $fpga_flow_scripts +perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path +cd - diff --git a/ERI_demo/pipelined_1b_adder.act b/ERI_demo/pipelined_1b_adder.act new file mode 100644 index 000000000..4b048d367 --- /dev/null +++ b/ERI_demo/pipelined_1b_adder.act @@ -0,0 +1,61 @@ +clk 0.5 0.2 +wen 0.5 0.2 +wen_st0 0.5 0.2 +wen_st1 0.5 0.2 +ren 0.5 0.2 +raddr[0] 0.5 0.2 +raddr[1] 0.5 0.2 +raddr[2] 0.5 0.2 +raddr[3] 0.5 0.2 +raddr[4] 0.5 0.2 +raddr[5] 0.5 0.2 +raddr[6] 0.5 0.2 +raddr[7] 0.5 0.2 +raddr[8] 0.5 0.2 +raddr[9] 0.5 0.2 +raddr[10] 0.5 0.2 +waddr[0] 0.5 0.2 +waddr[1] 0.5 0.2 +waddr[2] 0.5 0.2 +waddr[3] 0.5 0.2 +waddr[4] 0.5 0.2 +waddr[5] 0.5 0.2 +waddr[6] 0.5 0.2 +waddr[7] 0.5 0.2 +waddr[8] 0.5 0.2 +waddr[9] 0.5 0.2 +waddr[10] 0.5 0.2 +waddr_st0[0] 0.5 0.2 +waddr_st0[1] 0.5 0.2 +waddr_st0[2] 0.5 0.2 +waddr_st0[3] 0.5 0.2 +waddr_st0[4] 0.5 0.2 +waddr_st0[5] 0.5 0.2 +waddr_st0[6] 0.5 0.2 +waddr_st0[7] 0.5 0.2 +waddr_st0[8] 0.5 0.2 +waddr_st0[9] 0.5 0.2 +waddr_st0[10] 0.5 0.2 +waddr_st1[0] 0.5 0.2 +waddr_st1[1] 0.5 0.2 +waddr_st1[2] 0.5 0.2 +waddr_st1[3] 0.5 0.2 +waddr_st1[4] 0.5 0.2 +waddr_st1[5] 0.5 0.2 +waddr_st1[6] 0.5 0.2 +waddr_st1[7] 0.5 0.2 +waddr_st1[8] 0.5 0.2 +waddr_st1[9] 0.5 0.2 +waddr_st1[10] 0.5 0.2 +a[0] 0.5 0.2 +a_st0[0] 0.5 0.2 +a_st1[0] 0.5 0.2 +b[0] 0.5 0.2 +b_st0[0] 0.5 0.2 +b_st1[0] 0.5 0.2 +q[0] 0.5 0.2 +q[1] 0.5 0.2 +AplusB[0] 0.5 0.2 +AplusB[1] 0.5 0.2 +cint01 0.5 0.2 +zero00 0 0 diff --git a/ERI_demo/pipelined_1b_adder.blif b/ERI_demo/pipelined_1b_adder.blif new file mode 100644 index 000000000..447de5fa7 --- /dev/null +++ b/ERI_demo/pipelined_1b_adder.blif @@ -0,0 +1,152 @@ +# Benchmark pipelined_32b_adder +.model pipelined_32b_adder +.inputs clk wen ren \ + raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \ + waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] \ + a[0] b[0] +.outputs q[0] q[1] + +# Pipeline with #.latch +#.latch a[0] a_st0[0] re clk 0 +#.latch a_st0[0] a_st1[0] re clk 0 +#.latch b[0] b_st0[0] re clk 0 +#.latch b_st0[0] b_st1[0] re clk 0 +#.latch wen wen_st0 re clk 0 +#.latch wen_st0 wen_st1 re clk 0 +#.latch waddr[0] waddr_st0[0] re clk 0 +#.latch waddr_st0[0] waddr_st1[0] re clk 0 +#.latch waddr[1] waddr_st0[1] re clk 0 +#.latch waddr_st0[1] waddr_st1[1] re clk 0 +#.latch waddr[2] waddr_st0[2] re clk 0 +#.latch waddr_st0[2] waddr_st1[2] re clk 0 +#.latch waddr[3] waddr_st0[3] re clk 0 +#.latch waddr_st0[3] waddr_st1[3] re clk 0 +#.latch waddr[4] waddr_st0[4] re clk 0 +#.latch waddr_st0[4] waddr_st1[4] re clk 0 +#.latch waddr[5] waddr_st0[5] re clk 0 +#.latch waddr_st0[5] waddr_st1[5] re clk 0 +#.latch waddr[6] waddr_st0[6] re clk 0 +#.latch waddr_st0[6] waddr_st1[6] re clk 0 +#.latch waddr[7] waddr_st0[7] re clk 0 +#.latch waddr_st0[7] waddr_st1[7] re clk 0 +#.latch waddr[8] waddr_st0[8] re clk 0 +#.latch waddr_st0[8] waddr_st1[8] re clk 0 +#.latch waddr[9] waddr_st0[9] re clk 0 +#.latch waddr_st0[9] waddr_st1[9] re clk 0 +#.latch waddr[10] waddr_st0[10] re clk 0 +#.latch waddr_st0[10] waddr_st1[10] re clk 0 +# End pipeline with #.latch + +# Start pipeline +# Pipeline a +.subckt shift D=a[0] clk=clk Q=a_st0[0] +.subckt shift D=a_st0[0] clk=clk Q=a_st1[0] + +# Pipeline b +.subckt shift D=b[0] clk=clk Q=b_st0[0] +.subckt shift D=b_st0[0] clk=clk Q=b_st1[0] + +# Pipeline waddr +.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0] +.subckt shift D=waddr_st0[0] clk=clk Q=waddr_st1[0] +.subckt shift D=waddr[1] clk=clk Q=waddr_st0[1] +.subckt shift D=waddr_st0[1] clk=clk Q=waddr_st1[1] +.subckt shift D=waddr[2] clk=clk Q=waddr_st0[2] +.subckt shift D=waddr_st0[2] clk=clk Q=waddr_st1[2] +.subckt shift D=waddr[3] clk=clk Q=waddr_st0[3] +.subckt shift D=waddr_st0[3] clk=clk Q=waddr_st1[3] +.subckt shift D=waddr[4] clk=clk Q=waddr_st0[4] +.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4] +.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5] +.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5] +.subckt shift D=waddr[6] clk=clk Q=waddr_st0[6] +.subckt shift D=waddr_st0[6] clk=clk Q=waddr_st1[6] +.subckt shift D=waddr[7] clk=clk Q=waddr_st0[7] +.subckt shift D=waddr_st0[7] clk=clk Q=waddr_st1[7] +.subckt shift D=waddr[8] clk=clk Q=waddr_st0[8] +.subckt shift D=waddr_st0[8] clk=clk Q=waddr_st1[8] +.subckt shift D=waddr[9] clk=clk Q=waddr_st0[9] +.subckt shift D=waddr_st0[9] clk=clk Q=waddr_st1[9] +.subckt shift D=waddr[10] clk=clk Q=waddr_st0[10] +.subckt shift D=waddr_st0[10] clk=clk Q=waddr_st1[10] + +# Pipeline wen +.subckt shift D=wen clk=clk Q=wen_st0 +.subckt shift D=wen_st0 clk=clk Q=wen_st1 +# End pipeline + +# Start adder +.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0] +.subckt adder a=zero00 b=zero00 cin=cint01 cout=unconn sumout=AplusB[1] +# End adder + +# Start DPRAM +.subckt dpram clk=clk wen=wen_st1 ren=ren \ +waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \ +waddr[5]=waddr_st1[5] waddr[6]=waddr_st1[6] waddr[7]=waddr_st1[7] waddr[8]=waddr_st1[8] waddr[9]=waddr_st1[9] waddr[10]==waddr_st1[10] \ +raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \ +raddr[6]=raddr[6] raddr[7]=raddr[7] raddr[8]=raddr[8] raddr[9]=raddr[9] raddr[10]=raddr[10] \ +d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=zero00 d_in[3]=zero00 d_in[4]=zero00 d_in[5]=zero00 \ +d_in[6]=zero00 d_in[7]=zero00 d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \ +d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \ +d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \ +d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \ +d_in[30]=zero00 d_in[31]=zero00 \ +d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \ +d_out[0]=q[0] d_out[1]=q[1] d_out[2]=unconn d_out[3]=unconn d_out[4]=unconn d_out[5]=unconn \ +d_out[6]=unconn d_out[7]=unconn d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \ +d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \ +d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \ +d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \ +d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=unconn d_out[31]=unconn \ +d_out[32]=unconn d_out[33]=unconn d_out[34]=unconn d_out[35]=unconn d_out[36]=unconn d_out[37]=unconn d_out[38]=unconn d_out[39]=unconn d_out[40]=unconn d_out[41]=unconn d_out[42]=unconn d_out[43]=unconn d_out[44]=unconn d_out[45]=unconn d_out[46]=unconn d_out[47]=unconn d_out[48]=unconn d_out[49]=unconn d_out[50]=unconn d_out[51]=unconn d_out[52]=unconn d_out[53]=unconn d_out[54]=unconn d_out[55]=unconn d_out[56]=unconn d_out[57]=unconn d_out[58]=unconn d_out[59]=unconn d_out[60]=unconn d_out[61]=unconn d_out[62]=unconn d_out[63]=unconn +# End DPRAM + +# Start global variable +.names zero00 +0 +# End global variable + + +.end + +# Start blackbox definition +.model dpram +.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \ + waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] raddr[0] raddr[1] raddr[2] \ + raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \ + d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \ + d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \ + d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \ + d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] d_in[32] \ + d_in[33] d_in[34] d_in[35] d_in[36] d_in[37] d_in[38] d_in[39] d_in[40] \ + d_in[41] d_in[42] d_in[43] d_in[44] d_in[45] d_in[46] d_in[47] d_in[48] \ + d_in[49] d_in[50] d_in[51] d_in[52] d_in[53] d_in[54] d_in[55] d_in[56] \ + d_in[57] d_in[58] d_in[59] d_in[60] d_in[61] d_in[62] d_in[63] +.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \ + d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \ + d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \ + d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \ + d_out[28] d_out[29] d_out[30] d_out[31] d_out[32] d_out[33] d_out[34] \ + d_out[35] d_out[36] d_out[37] d_out[38] d_out[39] d_out[40] d_out[41] \ + d_out[42] d_out[43] d_out[44] d_out[45] d_out[46] d_out[47] d_out[48] \ + d_out[49] d_out[50] d_out[51] d_out[52] d_out[53] d_out[54] d_out[55] \ + d_out[56] d_out[57] d_out[58] d_out[59] d_out[60] d_out[61] d_out[62] \ + d_out[63] +.blackbox +.end + + +.model adder +.inputs a b cin +.outputs cout sumout +.blackbox +.end + + +.model shift +.inputs D clk +.outputs Q +.blackbox +.end +# End blackbox definition diff --git a/ERI_demo/pipelined_32b_adder.act b/ERI_demo/pipelined_32b_adder.act new file mode 100644 index 000000000..9093a7787 --- /dev/null +++ b/ERI_demo/pipelined_32b_adder.act @@ -0,0 +1,331 @@ +clk 0.5 0.2 +wen 0.5 0.2 +wen_st0 0.5 0.2 +wen_st1 0.5 0.2 +ren 0.5 0.2 +raddr[0] 0.5 0.2 +raddr[1] 0.5 0.2 +raddr[2] 0.5 0.2 +raddr[3] 0.5 0.2 +raddr[4] 0.5 0.2 +raddr[5] 0.5 0.2 +raddr[6] 0.5 0.2 +raddr[7] 0.5 0.2 +raddr[8] 0.5 0.2 +raddr[9] 0.5 0.2 +raddr[10] 0.5 0.2 +waddr[0] 0.5 0.2 +waddr[1] 0.5 0.2 +waddr[2] 0.5 0.2 +waddr[3] 0.5 0.2 +waddr[4] 0.5 0.2 +waddr[5] 0.5 0.2 +waddr[6] 0.5 0.2 +waddr[7] 0.5 0.2 +waddr[8] 0.5 0.2 +waddr[9] 0.5 0.2 +waddr[10] 0.5 0.2 +waddr_st0[0] 0.5 0.2 +waddr_st0[1] 0.5 0.2 +waddr_st0[2] 0.5 0.2 +waddr_st0[3] 0.5 0.2 +waddr_st0[4] 0.5 0.2 +waddr_st0[5] 0.5 0.2 +waddr_st0[6] 0.5 0.2 +waddr_st0[7] 0.5 0.2 +waddr_st0[8] 0.5 0.2 +waddr_st0[9] 0.5 0.2 +waddr_st0[10] 0.5 0.2 +waddr_st1[0] 0.5 0.2 +waddr_st1[1] 0.5 0.2 +waddr_st1[2] 0.5 0.2 +waddr_st1[3] 0.5 0.2 +waddr_st1[4] 0.5 0.2 +waddr_st1[5] 0.5 0.2 +waddr_st1[6] 0.5 0.2 +waddr_st1[7] 0.5 0.2 +waddr_st1[8] 0.5 0.2 +waddr_st1[9] 0.5 0.2 +waddr_st1[10] 0.5 0.2 +a[0] 0.5 0.2 +a[1] 0.5 0.2 +a[2] 0.5 0.2 +a[3] 0.5 0.2 +a[4] 0.5 0.2 +a[5] 0.5 0.2 +a[6] 0.5 0.2 +a[7] 0.5 0.2 +a[8] 0.5 0.2 +a[9] 0.5 0.2 +a[10] 0.5 0.2 +a[11] 0.5 0.2 +a[12] 0.5 0.2 +a[13] 0.5 0.2 +a[14] 0.5 0.2 +a[15] 0.5 0.2 +a[16] 0.5 0.2 +a[17] 0.5 0.2 +a[18] 0.5 0.2 +a[19] 0.5 0.2 +a[20] 0.5 0.2 +a[21] 0.5 0.2 +a[22] 0.5 0.2 +a[23] 0.5 0.2 +a[24] 0.5 0.2 +a[25] 0.5 0.2 +a[26] 0.5 0.2 +a[27] 0.5 0.2 +a[28] 0.5 0.2 +a[29] 0.5 0.2 +a[30] 0.5 0.2 +a_st0[0] 0.5 0.2 +a_st0[1] 0.5 0.2 +a_st0[2] 0.5 0.2 +a_st0[3] 0.5 0.2 +a_st0[4] 0.5 0.2 +a_st0[5] 0.5 0.2 +a_st0[6] 0.5 0.2 +a_st0[7] 0.5 0.2 +a_st0[8] 0.5 0.2 +a_st0[9] 0.5 0.2 +a_st0[10] 0.5 0.2 +a_st0[11] 0.5 0.2 +a_st0[12] 0.5 0.2 +a_st0[13] 0.5 0.2 +a_st0[14] 0.5 0.2 +a_st0[15] 0.5 0.2 +a_st0[16] 0.5 0.2 +a_st0[17] 0.5 0.2 +a_st0[18] 0.5 0.2 +a_st0[19] 0.5 0.2 +a_st0[20] 0.5 0.2 +a_st0[21] 0.5 0.2 +a_st0[22] 0.5 0.2 +a_st0[23] 0.5 0.2 +a_st0[24] 0.5 0.2 +a_st0[25] 0.5 0.2 +a_st0[26] 0.5 0.2 +a_st0[27] 0.5 0.2 +a_st0[28] 0.5 0.2 +a_st0[29] 0.5 0.2 +a_st0[30] 0.5 0.2 +a_st1[0] 0.5 0.2 +a_st1[1] 0.5 0.2 +a_st1[2] 0.5 0.2 +a_st1[3] 0.5 0.2 +a_st1[4] 0.5 0.2 +a_st1[5] 0.5 0.2 +a_st1[6] 0.5 0.2 +a_st1[7] 0.5 0.2 +a_st1[8] 0.5 0.2 +a_st1[9] 0.5 0.2 +a_st1[10] 0.5 0.2 +a_st1[11] 0.5 0.2 +a_st1[12] 0.5 0.2 +a_st1[13] 0.5 0.2 +a_st1[14] 0.5 0.2 +a_st1[15] 0.5 0.2 +a_st1[16] 0.5 0.2 +a_st1[17] 0.5 0.2 +a_st1[18] 0.5 0.2 +a_st1[19] 0.5 0.2 +a_st1[20] 0.5 0.2 +a_st1[21] 0.5 0.2 +a_st1[22] 0.5 0.2 +a_st1[23] 0.5 0.2 +a_st1[24] 0.5 0.2 +a_st1[25] 0.5 0.2 +a_st1[26] 0.5 0.2 +a_st1[27] 0.5 0.2 +a_st1[28] 0.5 0.2 +a_st1[29] 0.5 0.2 +a_st1[30] 0.5 0.2 +b[0] 0.5 0.2 +b[1] 0.5 0.2 +b[2] 0.5 0.2 +b[3] 0.5 0.2 +b[4] 0.5 0.2 +b[5] 0.5 0.2 +b[6] 0.5 0.2 +b[7] 0.5 0.2 +b[8] 0.5 0.2 +b[9] 0.5 0.2 +b[10] 0.5 0.2 +b[11] 0.5 0.2 +b[12] 0.5 0.2 +b[13] 0.5 0.2 +b[14] 0.5 0.2 +b[15] 0.5 0.2 +b[16] 0.5 0.2 +b[17] 0.5 0.2 +b[18] 0.5 0.2 +b[19] 0.5 0.2 +b[20] 0.5 0.2 +b[21] 0.5 0.2 +b[22] 0.5 0.2 +b[23] 0.5 0.2 +b[24] 0.5 0.2 +b[25] 0.5 0.2 +b[26] 0.5 0.2 +b[27] 0.5 0.2 +b[28] 0.5 0.2 +b[29] 0.5 0.2 +b[30] 0.5 0.2 +b_st0[0] 0.5 0.2 +b_st0[1] 0.5 0.2 +b_st0[2] 0.5 0.2 +b_st0[3] 0.5 0.2 +b_st0[4] 0.5 0.2 +b_st0[5] 0.5 0.2 +b_st0[6] 0.5 0.2 +b_st0[7] 0.5 0.2 +b_st0[8] 0.5 0.2 +b_st0[9] 0.5 0.2 +b_st0[10] 0.5 0.2 +b_st0[11] 0.5 0.2 +b_st0[12] 0.5 0.2 +b_st0[13] 0.5 0.2 +b_st0[14] 0.5 0.2 +b_st0[15] 0.5 0.2 +b_st0[16] 0.5 0.2 +b_st0[17] 0.5 0.2 +b_st0[18] 0.5 0.2 +b_st0[19] 0.5 0.2 +b_st0[20] 0.5 0.2 +b_st0[21] 0.5 0.2 +b_st0[22] 0.5 0.2 +b_st0[23] 0.5 0.2 +b_st0[24] 0.5 0.2 +b_st0[25] 0.5 0.2 +b_st0[26] 0.5 0.2 +b_st0[27] 0.5 0.2 +b_st0[28] 0.5 0.2 +b_st0[29] 0.5 0.2 +b_st0[30] 0.5 0.2 +b_st1[0] 0.5 0.2 +b_st1[1] 0.5 0.2 +b_st1[2] 0.5 0.2 +b_st1[3] 0.5 0.2 +b_st1[4] 0.5 0.2 +b_st1[5] 0.5 0.2 +b_st1[6] 0.5 0.2 +b_st1[7] 0.5 0.2 +b_st1[8] 0.5 0.2 +b_st1[9] 0.5 0.2 +b_st1[10] 0.5 0.2 +b_st1[11] 0.5 0.2 +b_st1[12] 0.5 0.2 +b_st1[13] 0.5 0.2 +b_st1[14] 0.5 0.2 +b_st1[15] 0.5 0.2 +b_st1[16] 0.5 0.2 +b_st1[17] 0.5 0.2 +b_st1[18] 0.5 0.2 +b_st1[19] 0.5 0.2 +b_st1[20] 0.5 0.2 +b_st1[21] 0.5 0.2 +b_st1[22] 0.5 0.2 +b_st1[23] 0.5 0.2 +b_st1[24] 0.5 0.2 +b_st1[25] 0.5 0.2 +b_st1[26] 0.5 0.2 +b_st1[27] 0.5 0.2 +b_st1[28] 0.5 0.2 +b_st1[29] 0.5 0.2 +b_st1[30] 0.5 0.2 +q[0] 0.5 0.2 +q[1] 0.5 0.2 +q[2] 0.5 0.2 +q[3] 0.5 0.2 +q[4] 0.5 0.2 +q[5] 0.5 0.2 +q[6] 0.5 0.2 +q[7] 0.5 0.2 +q[8] 0.5 0.2 +q[9] 0.5 0.2 +q[10] 0.5 0.2 +q[11] 0.5 0.2 +q[12] 0.5 0.2 +q[13] 0.5 0.2 +q[14] 0.5 0.2 +q[15] 0.5 0.2 +q[16] 0.5 0.2 +q[17] 0.5 0.2 +q[18] 0.5 0.2 +q[19] 0.5 0.2 +q[20] 0.5 0.2 +q[21] 0.5 0.2 +q[22] 0.5 0.2 +q[23] 0.5 0.2 +q[24] 0.5 0.2 +q[25] 0.5 0.2 +q[26] 0.5 0.2 +q[27] 0.5 0.2 +q[28] 0.5 0.2 +q[29] 0.5 0.2 +q[30] 0.5 0.2 +q[31] 0.5 0.2 +AplusB[0] 0.5 0.2 +AplusB[1] 0.5 0.2 +AplusB[2] 0.5 0.2 +AplusB[3] 0.5 0.2 +AplusB[4] 0.5 0.2 +AplusB[5] 0.5 0.2 +AplusB[6] 0.5 0.2 +AplusB[7] 0.5 0.2 +AplusB[8] 0.5 0.2 +AplusB[9] 0.5 0.2 +AplusB[10] 0.5 0.2 +AplusB[11] 0.5 0.2 +AplusB[12] 0.5 0.2 +AplusB[13] 0.5 0.2 +AplusB[14] 0.5 0.2 +AplusB[15] 0.5 0.2 +AplusB[16] 0.5 0.2 +AplusB[17] 0.5 0.2 +AplusB[18] 0.5 0.2 +AplusB[19] 0.5 0.2 +AplusB[20] 0.5 0.2 +AplusB[21] 0.5 0.2 +AplusB[22] 0.5 0.2 +AplusB[23] 0.5 0.2 +AplusB[24] 0.5 0.2 +AplusB[25] 0.5 0.2 +AplusB[26] 0.5 0.2 +AplusB[27] 0.5 0.2 +AplusB[28] 0.5 0.2 +AplusB[29] 0.5 0.2 +AplusB[30] 0.5 0.2 +AplusB[31] 0.5 0.2 +cint01 0.5 0.2 +cint02 0.5 0.2 +cint03 0.5 0.2 +cint04 0.5 0.2 +cint05 0.5 0.2 +cint06 0.5 0.2 +cint07 0.5 0.2 +cint08 0.5 0.2 +cint09 0.5 0.2 +cint10 0.5 0.2 +cint11 0.5 0.2 +cint12 0.5 0.2 +cint13 0.5 0.2 +cint14 0.5 0.2 +cint15 0.5 0.2 +cint16 0.5 0.2 +cint17 0.5 0.2 +cint18 0.5 0.2 +cint19 0.5 0.2 +cint20 0.5 0.2 +cint21 0.5 0.2 +cint22 0.5 0.2 +cint23 0.5 0.2 +cint24 0.5 0.2 +cint25 0.5 0.2 +cint26 0.5 0.2 +cint27 0.5 0.2 +cint28 0.5 0.2 +cint29 0.5 0.2 +cint30 0.5 0.2 +cint31 0.5 0.2 +zero00 0 0 diff --git a/ERI_demo/pipelined_32b_adder.blif b/ERI_demo/pipelined_32b_adder.blif new file mode 100644 index 000000000..8c8b3c408 --- /dev/null +++ b/ERI_demo/pipelined_32b_adder.blif @@ -0,0 +1,278 @@ +# Benchmark pipelined_32b_adder +.model pipelined_32b_adder +.inputs clk wen ren \ + raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \ + waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] \ + a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] \ + a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] \ + a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[30] \ + b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] \ + b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] \ + b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30] +.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7] q[8] q[9] q[10] \ + q[11] q[12] q[13] q[14] q[15] q[16] q[17] q[18] q[19] q[20] \ + q[21] q[22] q[23] q[24] q[25] q[26] q[27] q[28] q[29] q[30] q[31] + +# Start pipeline +# Pipeline a +.subckt shift D=a[0] clk=clk Q=a_st0[0] +.subckt shift D=a_st0[0] clk=clk Q=a_st1[0] +.subckt shift D=a[1] clk=clk Q=a_st0[1] +.subckt shift D=a_st0[1] clk=clk Q=a_st1[1] +.subckt shift D=a[2] clk=clk Q=a_st0[2] +.subckt shift D=a_st0[2] clk=clk Q=a_st1[2] +.subckt shift D=a[3] clk=clk Q=a_st0[3] +.subckt shift D=a_st0[3] clk=clk Q=a_st1[3] +.subckt shift D=a[4] clk=clk Q=a_st0[4] +.subckt shift D=a_st0[4] clk=clk Q=a_st1[4] +.subckt shift D=a[5] clk=clk Q=a_st0[5] +.subckt shift D=a_st0[5] clk=clk Q=a_st1[5] +.subckt shift D=a[6] clk=clk Q=a_st0[6] +.subckt shift D=a_st0[6] clk=clk Q=a_st1[6] +.subckt shift D=a[7] clk=clk Q=a_st0[7] +.subckt shift D=a_st0[7] clk=clk Q=a_st1[7] +.subckt shift D=a[8] clk=clk Q=a_st0[8] +.subckt shift D=a_st0[8] clk=clk Q=a_st1[8] +.subckt shift D=a[9] clk=clk Q=a_st0[9] +.subckt shift D=a_st0[9] clk=clk Q=a_st1[9] +.subckt shift D=a[10] clk=clk Q=a_st0[10] +.subckt shift D=a_st0[10] clk=clk Q=a_st1[10] +.subckt shift D=a[11] clk=clk Q=a_st0[11] +.subckt shift D=a_st0[11] clk=clk Q=a_st1[11] +.subckt shift D=a[12] clk=clk Q=a_st0[12] +.subckt shift D=a_st0[12] clk=clk Q=a_st1[12] +.subckt shift D=a[13] clk=clk Q=a_st0[13] +.subckt shift D=a_st0[13] clk=clk Q=a_st1[13] +.subckt shift D=a[14] clk=clk Q=a_st0[14] +.subckt shift D=a_st0[14] clk=clk Q=a_st1[14] +.subckt shift D=a[15] clk=clk Q=a_st0[15] +.subckt shift D=a_st0[15] clk=clk Q=a_st1[15] +.subckt shift D=a[16] clk=clk Q=a_st0[16] +.subckt shift D=a_st0[16] clk=clk Q=a_st1[16] +.subckt shift D=a[17] clk=clk Q=a_st0[17] +.subckt shift D=a_st0[17] clk=clk Q=a_st1[17] +.subckt shift D=a[18] clk=clk Q=a_st0[18] +.subckt shift D=a_st0[18] clk=clk Q=a_st1[18] +.subckt shift D=a[19] clk=clk Q=a_st0[19] +.subckt shift D=a_st0[19] clk=clk Q=a_st1[19] +.subckt shift D=a[20] clk=clk Q=a_st0[20] +.subckt shift D=a_st0[20] clk=clk Q=a_st1[20] +.subckt shift D=a[21] clk=clk Q=a_st0[21] +.subckt shift D=a_st0[21] clk=clk Q=a_st1[21] +.subckt shift D=a[22] clk=clk Q=a_st0[22] +.subckt shift D=a_st0[22] clk=clk Q=a_st1[22] +.subckt shift D=a[23] clk=clk Q=a_st0[23] +.subckt shift D=a_st0[23] clk=clk Q=a_st1[23] +.subckt shift D=a[24] clk=clk Q=a_st0[24] +.subckt shift D=a_st0[24] clk=clk Q=a_st1[24] +.subckt shift D=a[25] clk=clk Q=a_st0[25] +.subckt shift D=a_st0[25] clk=clk Q=a_st1[25] +.subckt shift D=a[26] clk=clk Q=a_st0[26] +.subckt shift D=a_st0[26] clk=clk Q=a_st1[26] +.subckt shift D=a[27] clk=clk Q=a_st0[27] +.subckt shift D=a_st0[27] clk=clk Q=a_st1[27] +.subckt shift D=a[28] clk=clk Q=a_st0[28] +.subckt shift D=a_st0[28] clk=clk Q=a_st1[28] +.subckt shift D=a[29] clk=clk Q=a_st0[29] +.subckt shift D=a_st0[29] clk=clk Q=a_st1[29] +.subckt shift D=a[30] clk=clk Q=a_st0[30] +.subckt shift D=a_st0[30] clk=clk Q=a_st1[30] + +# Pipeline b +.subckt shift D=b[0] clk=clk Q=b_st0[0] +.subckt shift D=b_st0[0] clk=clk Q=b_st1[0] +.subckt shift D=b[1] clk=clk Q=b_st0[1] +.subckt shift D=b_st0[1] clk=clk Q=b_st1[1] +.subckt shift D=b[2] clk=clk Q=b_st0[2] +.subckt shift D=b_st0[2] clk=clk Q=b_st1[2] +.subckt shift D=b[3] clk=clk Q=b_st0[3] +.subckt shift D=b_st0[3] clk=clk Q=b_st1[3] +.subckt shift D=b[4] clk=clk Q=b_st0[4] +.subckt shift D=b_st0[4] clk=clk Q=b_st1[4] +.subckt shift D=b[5] clk=clk Q=b_st0[5] +.subckt shift D=b_st0[5] clk=clk Q=b_st1[5] +.subckt shift D=b[6] clk=clk Q=b_st0[6] +.subckt shift D=b_st0[6] clk=clk Q=b_st1[6] +.subckt shift D=b[7] clk=clk Q=b_st0[7] +.subckt shift D=b_st0[7] clk=clk Q=b_st1[7] +.subckt shift D=b[8] clk=clk Q=b_st0[8] +.subckt shift D=b_st0[8] clk=clk Q=b_st1[8] +.subckt shift D=b[9] clk=clk Q=b_st0[9] +.subckt shift D=b_st0[9] clk=clk Q=b_st1[9] +.subckt shift D=b[10] clk=clk Q=b_st0[10] +.subckt shift D=b_st0[10] clk=clk Q=b_st1[10] +.subckt shift D=b[11] clk=clk Q=b_st0[11] +.subckt shift D=b_st0[11] clk=clk Q=b_st1[11] +.subckt shift D=b[12] clk=clk Q=b_st0[12] +.subckt shift D=b_st0[12] clk=clk Q=b_st1[12] +.subckt shift D=b[13] clk=clk Q=b_st0[13] +.subckt shift D=b_st0[13] clk=clk Q=b_st1[13] +.subckt shift D=b[14] clk=clk Q=b_st0[14] +.subckt shift D=b_st0[14] clk=clk Q=b_st1[14] +.subckt shift D=b[15] clk=clk Q=b_st0[15] +.subckt shift D=b_st0[15] clk=clk Q=b_st1[15] +.subckt shift D=b[16] clk=clk Q=b_st0[16] +.subckt shift D=b_st0[16] clk=clk Q=b_st1[16] +.subckt shift D=b[17] clk=clk Q=b_st0[17] +.subckt shift D=b_st0[17] clk=clk Q=b_st1[17] +.subckt shift D=b[18] clk=clk Q=b_st0[18] +.subckt shift D=b_st0[18] clk=clk Q=b_st1[18] +.subckt shift D=b[19] clk=clk Q=b_st0[19] +.subckt shift D=b_st0[19] clk=clk Q=b_st1[19] +.subckt shift D=b[20] clk=clk Q=b_st0[20] +.subckt shift D=b_st0[20] clk=clk Q=b_st1[20] +.subckt shift D=b[21] clk=clk Q=b_st0[21] +.subckt shift D=b_st0[21] clk=clk Q=b_st1[21] +.subckt shift D=b[22] clk=clk Q=b_st0[22] +.subckt shift D=b_st0[22] clk=clk Q=b_st1[22] +.subckt shift D=b[23] clk=clk Q=b_st0[23] +.subckt shift D=b_st0[23] clk=clk Q=b_st1[23] +.subckt shift D=b[24] clk=clk Q=b_st0[24] +.subckt shift D=b_st0[24] clk=clk Q=b_st1[24] +.subckt shift D=b[25] clk=clk Q=b_st0[25] +.subckt shift D=b_st0[25] clk=clk Q=b_st1[25] +.subckt shift D=b[26] clk=clk Q=b_st0[26] +.subckt shift D=b_st0[26] clk=clk Q=b_st1[26] +.subckt shift D=b[27] clk=clk Q=b_st0[27] +.subckt shift D=b_st0[27] clk=clk Q=b_st1[27] +.subckt shift D=b[28] clk=clk Q=b_st0[28] +.subckt shift D=b_st0[28] clk=clk Q=b_st1[28] +.subckt shift D=b[29] clk=clk Q=b_st0[29] +.subckt shift D=b_st0[29] clk=clk Q=b_st1[29] +.subckt shift D=b[30] clk=clk Q=b_st0[30] +.subckt shift D=b_st0[30] clk=clk Q=b_st1[30] + +# Pipeline waddr +.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0] +.subckt shift D=waddr_st0[0] clk=clk Q=waddr_st1[0] +.subckt shift D=waddr[1] clk=clk Q=waddr_st0[1] +.subckt shift D=waddr_st0[1] clk=clk Q=waddr_st1[1] +.subckt shift D=waddr[2] clk=clk Q=waddr_st0[2] +.subckt shift D=waddr_st0[2] clk=clk Q=waddr_st1[2] +.subckt shift D=waddr[3] clk=clk Q=waddr_st0[3] +.subckt shift D=waddr_st0[3] clk=clk Q=waddr_st1[3] +.subckt shift D=waddr[4] clk=clk Q=waddr_st0[4] +.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4] +.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5] +.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5] +.subckt shift D=waddr[6] clk=clk Q=waddr_st0[6] +.subckt shift D=waddr_st0[6] clk=clk Q=waddr_st1[6] +.subckt shift D=waddr[7] clk=clk Q=waddr_st0[7] +.subckt shift D=waddr_st0[7] clk=clk Q=waddr_st1[7] +.subckt shift D=waddr[8] clk=clk Q=waddr_st0[8] +.subckt shift D=waddr_st0[8] clk=clk Q=waddr_st1[8] +.subckt shift D=waddr[9] clk=clk Q=waddr_st0[9] +.subckt shift D=waddr_st0[9] clk=clk Q=waddr_st1[9] +.subckt shift D=waddr[10] clk=clk Q=waddr_st0[10] +.subckt shift D=waddr_st0[10] clk=clk Q=waddr_st1[10] + +# Pipeline wen +.subckt shift D=wen clk=clk Q=wen_st0 +.subckt shift D=wen_st0 clk=clk Q=wen_st1 +# End pipeline + +# Start adder +.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0] +.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1] +.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2] +.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3] +.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4] +.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5] +.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6] +.subckt adder a=a_st1[7] b=b_st1[7] cin=cint07 cout=cint08 sumout=AplusB[7] +.subckt adder a=a_st1[8] b=b_st1[8] cin=cint08 cout=cint09 sumout=AplusB[8] +.subckt adder a=a_st1[9] b=b_st1[9] cin=cint09 cout=cint10 sumout=AplusB[9] +.subckt adder a=a_st1[10] b=b_st1[10] cin=cint10 cout=cint11 sumout=AplusB[10] +.subckt adder a=a_st1[11] b=b_st1[11] cin=cint11 cout=cint12 sumout=AplusB[11] +.subckt adder a=a_st1[12] b=b_st1[12] cin=cint12 cout=cint13 sumout=AplusB[12] +.subckt adder a=a_st1[13] b=b_st1[13] cin=cint13 cout=cint14 sumout=AplusB[13] +.subckt adder a=a_st1[14] b=b_st1[14] cin=cint14 cout=cint15 sumout=AplusB[14] +.subckt adder a=a_st1[15] b=b_st1[15] cin=cint15 cout=cint16 sumout=AplusB[15] +.subckt adder a=a_st1[16] b=b_st1[16] cin=cint16 cout=cint17 sumout=AplusB[16] +.subckt adder a=a_st1[17] b=b_st1[17] cin=cint17 cout=cint18 sumout=AplusB[17] +.subckt adder a=a_st1[18] b=b_st1[18] cin=cint18 cout=cint19 sumout=AplusB[18] +.subckt adder a=a_st1[19] b=b_st1[19] cin=cint19 cout=cint20 sumout=AplusB[19] +.subckt adder a=a_st1[20] b=b_st1[20] cin=cint20 cout=cint21 sumout=AplusB[20] +.subckt adder a=a_st1[21] b=b_st1[21] cin=cint21 cout=cint22 sumout=AplusB[21] +.subckt adder a=a_st1[22] b=b_st1[22] cin=cint22 cout=cint23 sumout=AplusB[22] +.subckt adder a=a_st1[23] b=b_st1[23] cin=cint23 cout=cint24 sumout=AplusB[23] +.subckt adder a=a_st1[24] b=b_st1[24] cin=cint24 cout=cint25 sumout=AplusB[24] +.subckt adder a=a_st1[25] b=b_st1[25] cin=cint25 cout=cint26 sumout=AplusB[25] +.subckt adder a=a_st1[26] b=b_st1[26] cin=cint26 cout=cint27 sumout=AplusB[26] +.subckt adder a=a_st1[27] b=b_st1[27] cin=cint27 cout=cint28 sumout=AplusB[27] +.subckt adder a=a_st1[28] b=b_st1[28] cin=cint28 cout=cint29 sumout=AplusB[28] +.subckt adder a=a_st1[29] b=b_st1[29] cin=cint29 cout=cint30 sumout=AplusB[29] +.subckt adder a=a_st1[30] b=b_st1[30] cin=cint30 cout=cint31 sumout=AplusB[30] +.subckt adder a=zero00 b=zero00 cin=cint31 cout=unconn sumout=AplusB[31] +# End adder + +# Start DPRAM +.subckt dpram clk=clk wen=wen_st1 ren=ren \ +waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \ +waddr[5]=waddr_st1[5] waddr[6]=waddr_st1[6] waddr[7]=waddr_st1[7] waddr[8]=waddr_st1[8] waddr[9]=waddr_st1[9] waddr[10]==waddr_st1[10] \ +raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \ +raddr[6]=raddr[6] raddr[7]=raddr[7] raddr[8]=raddr[8] raddr[9]=raddr[9] raddr[10]=raddr[10] \ +d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \ +d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=AplusB[8] d_in[9]=AplusB[9] d_in[10]=AplusB[10] d_in[11]=AplusB[11] \ +d_in[12]=AplusB[12] d_in[13]=AplusB[13] d_in[14]=AplusB[14] d_in[15]=AplusB[15] d_in[16]=AplusB[16] d_in[17]=AplusB[17] \ +d_in[18]=AplusB[18] d_in[19]=AplusB[19] d_in[20]=AplusB[20] d_in[21]=AplusB[21] d_in[22]=AplusB[22] d_in[23]=AplusB[23] \ +d_in[24]=AplusB[24] d_in[25]=AplusB[25] d_in[26]=AplusB[26] d_in[27]=AplusB[27] d_in[28]=AplusB[28] d_in[29]=AplusB[29] \ +d_in[30]=AplusB[30] d_in[31]=AplusB[31] \ +d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \ +d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \ +d_out[6]=q[6] d_out[7]=q[7] d_out[8]=q[8] d_out[9]=q[9] d_out[10]=q[10] \ +d_out[11]=q[11] d_out[12]=q[12] d_out[13]=q[13] d_out[14]=q[14] d_out[15]=q[15] \ +d_out[16]=q[16] d_out[17]=q[17] d_out[18]=q[18] d_out[19]=q[19] d_out[20]=q[20] \ +d_out[21]=q[21] d_out[22]=q[22] d_out[23]=q[23] d_out[24]=q[24] d_out[25]=q[25] \ +d_out[26]=q[26] d_out[27]=q[27] d_out[28]=q[28] d_out[29]=q[29] d_out[30]=q[30] d_out[31]=q[31] \ +d_out[32]=unconn d_out[33]=unconn d_out[34]=unconn d_out[35]=unconn d_out[36]=unconn d_out[37]=unconn d_out[38]=unconn d_out[39]=unconn d_out[40]=unconn d_out[41]=unconn d_out[42]=unconn d_out[43]=unconn d_out[44]=unconn d_out[45]=unconn d_out[46]=unconn d_out[47]=unconn d_out[48]=unconn d_out[49]=unconn d_out[50]=unconn d_out[51]=unconn d_out[52]=unconn d_out[53]=unconn d_out[54]=unconn d_out[55]=unconn d_out[56]=unconn d_out[57]=unconn d_out[58]=unconn d_out[59]=unconn d_out[60]=unconn d_out[61]=unconn d_out[62]=unconn d_out[63]=unconn +# End DPRAM + +# Start global variable +.names zero00 +0 +# End global variable + + +.end + +# Start blackbox definition +.model dpram +.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \ + waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] raddr[0] raddr[1] raddr[2] \ + raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \ + d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \ + d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \ + d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \ + d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] d_in[32] \ + d_in[33] d_in[34] d_in[35] d_in[36] d_in[37] d_in[38] d_in[39] d_in[40] \ + d_in[41] d_in[42] d_in[43] d_in[44] d_in[45] d_in[46] d_in[47] d_in[48] \ + d_in[49] d_in[50] d_in[51] d_in[52] d_in[53] d_in[54] d_in[55] d_in[56] \ + d_in[57] d_in[58] d_in[59] d_in[60] d_in[61] d_in[62] d_in[63] +.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \ + d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \ + d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \ + d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \ + d_out[28] d_out[29] d_out[30] d_out[31] d_out[32] d_out[33] d_out[34] \ + d_out[35] d_out[36] d_out[37] d_out[38] d_out[39] d_out[40] d_out[41] \ + d_out[42] d_out[43] d_out[44] d_out[45] d_out[46] d_out[47] d_out[48] \ + d_out[49] d_out[50] d_out[51] d_out[52] d_out[53] d_out[54] d_out[55] \ + d_out[56] d_out[57] d_out[58] d_out[59] d_out[60] d_out[61] d_out[62] \ + d_out[63] +.blackbox +.end + + +.model adder +.inputs a b cin +.outputs cout sumout +.blackbox +.end + + +.model shift +.inputs D clk +.outputs Q +.blackbox +.end +# End blackbox definition diff --git a/ERI_demo/pipelined_32b_adder.v b/ERI_demo/pipelined_32b_adder.v new file mode 100644 index 000000000..ecf0007c0 --- /dev/null +++ b/ERI_demo/pipelined_32b_adder.v @@ -0,0 +1,63 @@ +///////////////////////////////////// +// // +// ERI summit demo-benchmark // +// pipelined_32b_adder.v // +// by Aurelien // +// // +///////////////////////////////////// + +`timescale 1 ns/ 1 ps + +module pipelined_32b_adder( + clk, + raddr, + waddr, + ren, + wen, + a, + b, + q ); + + input clk; + input[10:0] raddr; + input[10:0] waddr; + input ren; + input wen; + input[30:0] a; + input[30:0] b; + output[31:0] q; + + reg[2047:0] ram[31:0]; + reg[30:0] a_st0; + reg[30:0] a_st1; + reg[30:0] b_st0; + reg[30:0] b_st1; + reg[10:0] waddr_st0; + reg[10:0] waddr_st1; + reg wen_st0; + reg wen_st1; + reg[31:0] q_int; + + wire[31:0] AplusB; + + assign AplusB = a_st1 + b_st1; + assign q = q_int; + + always@(posedge clk) begin + waddr_st0 <= waddr; + waddr_st1 <= waddr_st0; + a_st0 <= a; + a_st1 <= a_st0; + b_st0 <= b; + b_st1 <= b_st0; + wen_st0 <= wen; + wen_st1 <= wen_st0; + if(wen_st1) begin + ram[waddr_st1] <= AplusB; + end + if(ren) begin + q_int <= ram[raddr]; + end + end + +endmodule : pipelined_32b_adder diff --git a/ERI_demo/pipelined_32b_adder_ERI_demo_tb.v b/ERI_demo/pipelined_32b_adder_ERI_demo_tb.v new file mode 100644 index 000000000..06f1f77a1 --- /dev/null +++ b/ERI_demo/pipelined_32b_adder_ERI_demo_tb.v @@ -0,0 +1,156 @@ +///////////////////////////////////// +// // +// ERI summit demo-benchmark // +// pipelined_32b_adder_tb // +// by Aurelien // +// // +///////////////////////////////////// + +`timescale 1 ns/ 1 ps + +module pipelined_32b_adder_ERI_demo_tb(); + reg clk; + reg[10:0] raddr; + reg[10:0] waddr; + reg ren; + reg wen; + reg[30:0] a; + reg[30:0] b; + wire[31:0] q_gfpga; + wire[31:0] q_bench; + reg[31:0] q_flag; + + pipelined_32b_adder_top_formal_verification DUT( + .clk_fm (clk), + .raddr_0_fm (raddr[0]), + .raddr_1_fm (raddr[1]), + .raddr_2_fm (raddr[2]), + .raddr_3_fm (raddr[3]), + .raddr_4_fm (raddr[4]), + .raddr_5_fm (raddr[5]), + .raddr_6_fm (raddr[6]), + .raddr_7_fm (raddr[7]), + .raddr_8_fm (raddr[8]), + .raddr_9_fm (raddr[9]), + .raddr_10_fm (raddr[10]), + .waddr_0_fm (waddr[0]), + .waddr_1_fm (waddr[1]), + .waddr_2_fm (waddr[2]), + .waddr_3_fm (waddr[3]), + .waddr_4_fm (waddr[4]), + .waddr_5_fm (waddr[5]), + .waddr_6_fm (waddr[6]), + .waddr_7_fm (waddr[7]), + .waddr_8_fm (waddr[8]), + .waddr_9_fm (waddr[9]), + .waddr_10_fm (waddr[10]), + .ren_fm (ren), + .wen_fm (wen), + .a_0_fm (a[0]), + .a_1_fm (a[1]), + .a_2_fm (a[2]), + .a_3_fm (a[3]), + .a_4_fm (a[4]), + .a_5_fm (a[5]), + .a_6_fm (a[6]), + .a_7_fm (a[7]), + .a_8_fm (a[8]), + .a_9_fm (a[9]), + .a_10_fm (a[10]), + .a_11_fm (a[11]), + .a_12_fm (a[12]), + .a_13_fm (a[13]), + .a_14_fm (a[14]), + .a_15_fm (a[15]), + .a_16_fm (a[16]), + .a_17_fm (a[17]), + .a_18_fm (a[18]), + .a_19_fm (a[19]), + .a_20_fm (a[20]), + .a_21_fm (a[21]), + .a_22_fm (a[22]), + .a_23_fm (a[23]), + .a_24_fm (a[24]), + .a_25_fm (a[25]), + .a_26_fm (a[26]), + .a_27_fm (a[27]), + .a_28_fm (a[28]), + .a_29_fm (a[29]), + .a_30_fm (a[30]), + .b_0_fm (b[0]), + .b_1_fm (b[1]), + .b_2_fm (b[2]), + .b_3_fm (b[3]), + .b_4_fm (b[4]), + .b_5_fm (b[5]), + .b_6_fm (b[6]), + .b_7_fm (b[7]), + .b_8_fm (b[8]), + .b_9_fm (b[9]), + .b_10_fm (b[10]), + .b_11_fm (b[11]), + .b_12_fm (b[12]), + .b_13_fm (b[13]), + .b_14_fm (b[14]), + .b_15_fm (b[15]), + .b_16_fm (b[16]), + .b_17_fm (b[17]), + .b_18_fm (b[18]), + .b_19_fm (b[19]), + .b_20_fm (b[20]), + .b_21_fm (b[21]), + .b_22_fm (b[22]), + .b_23_fm (b[23]), + .b_24_fm (b[24]), + .b_25_fm (b[25]), + .b_26_fm (b[26]), + .b_27_fm (b[27]), + .b_28_fm (b[28]), + .b_29_fm (b[29]), + .b_30_fm (b[30]), + .out_q_0_fm (q_gfpga[0]), + .out_q_1_fm (q_gfpga[1]), + .out_q_2_fm (q_gfpga[2]), + .out_q_3_fm (q_gfpga[3]), + .out_q_4_fm (q_gfpga[4]), + .out_q_5_fm (q_gfpga[5]), + .out_q_6_fm (q_gfpga[6]), + .out_q_7_fm (q_gfpga[7]), + .out_q_8_fm (q_gfpga[8]), + .out_q_9_fm (q_gfpga[9]), + .out_q_10_fm (q_gfpga[10]), + .out_q_11_fm (q_gfpga[11]), + .out_q_12_fm (q_gfpga[12]), + .out_q_13_fm (q_gfpga[13]), + .out_q_14_fm (q_gfpga[14]), + .out_q_15_fm (q_gfpga[15]), + .out_q_16_fm (q_gfpga[16]), + .out_q_17_fm (q_gfpga[17]), + .out_q_18_fm (q_gfpga[18]), + .out_q_19_fm (q_gfpga[19]), + .out_q_20_fm (q_gfpga[20]), + .out_q_21_fm (q_gfpga[21]), + .out_q_22_fm (q_gfpga[22]), + .out_q_23_fm (q_gfpga[23]), + .out_q_24_fm (q_gfpga[24]), + .out_q_25_fm (q_gfpga[25]), + .out_q_26_fm (q_gfpga[26]), + .out_q_27_fm (q_gfpga[27]), + .out_q_28_fm (q_gfpga[28]), + .out_q_29_fm (q_gfpga[29]), + .out_q_30_fm (q_gfpga[30]), + .out_q_31_fm (q_gfpga[31]) + ); + + pipelined_32b_adder ref0( + .clk (clk), + .raddr (raddr), + .waddr (waddr), + .ren (ren), + .wen (wen), + .a (a), + .b (b), + .q (q_bench) + ); + +endmodule : pipelined_32b_adder_ERI_demo_tb \ No newline at end of file diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml new file mode 100644 index 000000000..95f6f8f1f --- /dev/null +++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml @@ -0,0 +1,1155 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + 10e-12 10e-12 + + + 10e-12 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 255e-12 + 255e-12 + 255e-12 + 255e-12 + 255e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 202e-12 + 202e-12 + 202e-12 + 202e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.cin clb.cin_trick clb.regin clb.clk + clb.I0[9:0] clb.I1[9:0] clb.O[9:0] + clb.cout clb.regout clb.I2[9:0] clb.I3[9:0] clb.O[19:10] + + + + + + + + + + + + + + + + + + From b08513d9029c679e1984f7e58f265b232a643592 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Tue, 2 Jul 2019 14:12:42 -0600 Subject: [PATCH 14/84] Big chunk added on the routing part of the explicit mapping --- .../verilog/verilog_autocheck_top_testbench.c | 4 +- .../verilog/verilog_compact_netlist.c | 73 ++++++----- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 22 ++-- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 4 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 119 ++++++++++++------ .../verilog/verilog_top_netlist_utils.c | 44 ++++--- .../verilog/verilog_top_netlist_utils.h | 9 +- .../fpga_x2p/verilog/verilog_top_testbench.c | 7 +- .../fpga_x2p/verilog/verilog_top_testbench.h | 3 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 43 +++++-- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 9 +- .../verilog_verification_top_netlist.c | 6 +- 12 files changed, 222 insertions(+), 121 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c index 7fa549e9e..e3c234c08 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_autocheck_top_testbench.c @@ -354,6 +354,7 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, t_spice verilog) { FILE* fp = NULL; char* title = my_strcat("FPGA Verilog Testbench for Top-level netlist of Design: ", circuit_name); + bool is_explicit_mapping = fpga_verilog_opts.dump_explicit_verilog; /* Check if the path exists*/ fp = fopen(top_netlist_name,"w"); @@ -379,7 +380,8 @@ void dump_verilog_autocheck_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_top_auto_testbench_ports(fp, cur_sram_orgz_info, circuit_name, fpga_verilog_opts); /* Call defined top-level module */ - dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name); + dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, + circuit_name, is_explicit_mapping); /* Call defined benchmark */ dump_verilog_top_auto_testbench_call_benchmark(fp, circuit_name); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 5e83ecca7..57be783cf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -361,7 +361,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "module %s ( \n", subckt_name); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -406,7 +406,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, 0, temp_conf_bits_msb - 1, - VERILOG_PORT_INPUT); // Should be modified to be VERILOG_PORT_INPUT + VERILOG_PORT_INPUT, is_explicit_mapping); // Should be modified to be VERILOG_PORT_INPUT fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -430,7 +430,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, " %s (", gen_verilog_one_phy_block_instance_name(phy_block_type, iz)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } /* Print all the pins */ @@ -464,7 +464,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "//---- SRAM ----\n"); dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, temp_conf_bits_lsb, temp_conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ @@ -475,7 +475,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, temp_conf_bits_lsb, temp_conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -592,7 +592,8 @@ void dump_compact_verilog_logic_blocks(t_sram_orgz_info* cur_sram_orgz_info, static void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - int ix, int iy, int border_side) { + int ix, int iy, int border_side, + bool is_explicit_mapping) { char* subckt_name = NULL; if (NULL == fp) { @@ -616,7 +617,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -648,7 +649,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, cur_sram_orgz_info->grid_conf_bits_lsb[ix][iy], cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ @@ -660,7 +661,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sram_orgz_info->grid_conf_bits_lsb[ix][iy], cur_sram_orgz_info->grid_conf_bits_msb[ix][iy] - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -676,7 +677,8 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, */ static void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, - FILE* fp) { + FILE* fp, + bool is_explicit_mapping) { int ix, iy; if (NULL == fp) { @@ -692,7 +694,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, continue; } assert(IO_TYPE != grid[ix][iy].type); - dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, -1); + dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, + ix, iy, -1, is_explicit_mapping); } } @@ -705,7 +708,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, continue; } assert(IO_TYPE == grid[ix][iy].type); - dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 0); + dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, + ix, iy, 0, is_explicit_mapping); } /* RIGHT side */ ix = nx + 1; @@ -715,7 +719,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, continue; } assert(IO_TYPE == grid[ix][iy].type); - dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 1); + dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, + ix, iy, 1, is_explicit_mapping); } /* BOTTOM side */ @@ -726,7 +731,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, continue; } assert(IO_TYPE == grid[ix][iy].type); - dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 2); + dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, + ix, iy, 2, is_explicit_mapping); } /* LEFT side */ ix = 0; @@ -736,7 +742,8 @@ void dump_compact_verilog_defined_grids(t_sram_orgz_info* cur_sram_orgz_info, continue; } assert(IO_TYPE == grid[ix][iy].type); - dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, iy, 3); + dump_compact_verilog_defined_one_grid(cur_sram_orgz_info, fp, ix, + iy, 3, is_explicit_mapping); } @@ -775,7 +782,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -821,7 +828,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, rr_sb.get_sb_conf_bits_lsb(), rr_sb.get_sb_conf_bits_msb(), - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ @@ -833,7 +840,7 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_sb.get_sb_conf_bits_lsb(), rr_sb.get_sb_conf_bits_msb(), - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -901,7 +908,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -949,7 +956,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, rr_gsb.get_cb_conf_bits_lsb(cb_type), rr_gsb.get_cb_conf_bits_msb(cb_type), - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ if (0 < rr_gsb.get_cb_num_conf_bits(cb_type)) { @@ -959,7 +966,7 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_cb_conf_bits_lsb(cb_type), rr_gsb.get_cb_conf_bits_msb(cb_type), - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -1019,7 +1026,9 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or static void dump_compact_verilog_defined_one_channel(FILE* fp, int x, int y, - const RRChan& rr_chan, size_t subckt_id) { + const RRChan& rr_chan, + size_t subckt_id, + bool is_explicit_mapping) { if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); exit(1); @@ -1053,7 +1062,7 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -1140,7 +1149,8 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, /* Call the sub-circuits for channels : Channel X and Channel Y*/ static -void dump_compact_verilog_defined_channels(FILE* fp) { +void dump_compact_verilog_defined_channels(FILE* fp, + bool is_explicit_mapping) { int ix, iy; if (NULL == fp) { @@ -1153,7 +1163,8 @@ void dump_compact_verilog_defined_channels(FILE* fp) { for (ix = 1; ix < (nx + 1); ix++) { dump_compact_verilog_defined_one_channel(fp, ix, iy, device_rr_chan.get_module_with_coordinator(CHANX, ix, iy), - device_rr_chan.get_module_id(CHANX, ix, iy)); + device_rr_chan.get_module_id(CHANX, ix, iy), + is_explicit_mapping); } } @@ -1162,7 +1173,8 @@ void dump_compact_verilog_defined_channels(FILE* fp) { for (iy = 1; iy < (ny + 1); iy++) { dump_compact_verilog_defined_one_channel(fp, ix, iy, device_rr_chan.get_module_with_coordinator(CHANY, ix, iy), - device_rr_chan.get_module_id(CHANY, ix, iy)); + device_rr_chan.get_module_id(CHANY, ix, iy), + is_explicit_mapping); } } @@ -1234,15 +1246,16 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, my_free(temp_include_file_path); /* Print all global wires*/ - dump_verilog_top_netlist_ports(cur_sram_orgz_info, fp, num_clock, circuit_name, verilog); + dump_verilog_top_netlist_ports(cur_sram_orgz_info, fp, num_clock, + circuit_name, verilog, is_explicit_mapping); dump_verilog_top_netlist_internal_wires(cur_sram_orgz_info, fp); /* Quote Routing structures: Channels */ if (TRUE == compact_routing_hierarchy ) { - dump_compact_verilog_defined_channels(fp); + dump_compact_verilog_defined_channels(fp, is_explicit_mapping); } else { - dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + dump_verilog_defined_channels(fp, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping); } /* Quote Routing structures: Switch Boxes */ @@ -1260,7 +1273,7 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info, } /* Quote defined Logic blocks subckts (Grids) */ - dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp); + dump_compact_verilog_defined_grids(cur_sram_orgz_info, fp, is_explicit_mapping); /* Apply CLB to CLB direct connections */ dump_verilog_clb2clb_directs(fp, num_clb2clb_directs, clb2clb_direct); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 1551aa028..80ed46195 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1733,7 +1733,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, */ fprintf(fp, "\n"); /* dump global ports */ - if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { fprintf(fp, ",\n"); } /* Simplify the port prefix, make SPICE netlist readable */ @@ -1772,7 +1772,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, stamped_sram_cnt, stamped_sram_cnt + num_conf_bits - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -1819,7 +1819,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* dump global ports */ /* If the child node is a primitive, we only dump global ports belonging to this primitive */ if (NULL == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model) { - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } } else { @@ -1863,7 +1863,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, stamped_sram_cnt, stamped_sram_cnt + child_pb_num_conf_bits - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ if (0 < child_pb_num_conf_bits) { @@ -1873,7 +1873,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, stamped_sram_cnt, stamped_sram_cnt + child_pb_num_conf_bits - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2552,7 +2552,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "module %s ( \n", gen_verilog_one_grid_module_name(ix, iy)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -2596,7 +2596,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_num_mem_bit, get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info) - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, + false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2624,7 +2625,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, " %s (", gen_verilog_one_block_instance_name(ix, iy, iz)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } /* Print all the pins */ @@ -2659,7 +2660,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "//---- SRAM ----\n"); dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, temp_conf_bits_lsb, temp_conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ if (0 < (temp_conf_bits_msb - 1 - temp_conf_bits_lsb)) { @@ -2669,7 +2670,8 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, temp_conf_bits_lsb, temp_conf_bits_msb - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, + is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index cad259077..a735d36fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -173,7 +173,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_conf_bits - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -560,7 +560,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_conf_bits - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index e052d24b0..4ff427dcf 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -44,7 +44,8 @@ static void dump_verilog_routing_chan_subckt(char* verilog_dir, char* subckt_dir, size_t rr_chan_subckt_id, - const RRChan& rr_chan) { + const RRChan& rr_chan, + bool is_explicit_mapping) { FILE* fp = NULL; char* fname = NULL; @@ -78,7 +79,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, gen_verilog_one_routing_channel_module_name(rr_chan.get_type(), rr_chan_subckt_id, -1)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } /* Inputs and outputs, @@ -170,7 +171,8 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - int num_segment) { + int num_segment, + bool is_explicit_mapping) { int itrack, iseg, cost_index; int chan_width = 0; t_rr_node** chan_rr_nodes = NULL; @@ -215,7 +217,7 @@ void dump_verilog_routing_chan_subckt(char* verilog_dir, gen_verilog_one_routing_channel_module_name(chan_type, x, y)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } /* Inputs and outputs, @@ -355,9 +357,10 @@ void dump_verilog_grid_side_pin_with_given_index(FILE* fp, t_rr_type pin_type, /* fprintf(fp, "grid_%d__%d__pin_%d__%d__%d_ ", x, y, height, side, pin_index); */ if (TRUE == dump_port_type) { fprintf(fp, "%s ", verilog_port_type); + is_explicit_mapping = false; /* Both cannot be true at the same time */ } if (true == is_explicit_mapping) { - fprintf(fp, ".out("); + fprintf(fp, ".%s(", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); } fprintf(fp, "%s", gen_verilog_grid_one_pin_name(x, y, height, side, pin_index, TRUE)); if (true == is_explicit_mapping) { @@ -562,7 +565,7 @@ void dump_verilog_unique_switch_box_short_interc(FILE* fp, drive_rr_node->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_node), grid_x, grid_y, - FALSE, is_explicit_mapping); /* Do not dump the direction of the port! */ + FALSE, false); /* Do not dump the direction of the port! */ break; case CHANX: case CHANY: @@ -1025,7 +1028,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info, verilog_model->prefix, mux_size, verilog_model->cnt, input_cnt); dump_verilog_grid_side_pin_with_given_index(fp, IPIN, drive_rr_nodes[inode]->ptc_num, rr_sb.get_opin_node_grid_side(drive_rr_nodes[inode]), - grid_x, grid_y, FALSE, is_explicit_mapping); + grid_x, grid_y, FALSE, false); fprintf(fp, ";\n"); input_cnt++; break; @@ -1741,11 +1744,22 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, fprintf(fp, " "); if (TRUE == dump_port_type) { fprintf(fp, "output "); + is_explicit_mapping = false; /* Both cannot be true together */ } - fprintf(fp, "%s,\n", + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), port_coordinator.get_x(), port_coordinator.get_y(), itrack, rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + } + fprintf(fp, "%s", + gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), + port_coordinator.get_x(), port_coordinator.get_y(), itrack, + rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; case IN_PORT: /* if this is not the specified side, we only consider input ports */ @@ -1756,10 +1770,20 @@ void dump_verilog_routing_switch_box_unique_side_subckt_portmap(FILE* fp, if (TRUE == dump_port_type) { fprintf(fp, "input "); } - fprintf(fp, "%s,\n", + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), port_coordinator.get_x(), port_coordinator.get_y(), itrack, rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + } + fprintf(fp, "%s", + gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), + port_coordinator.get_x(), port_coordinator.get_y(), itrack, + rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; default: vpr_printf(TIO_MESSAGE_ERROR, @@ -1870,7 +1894,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", rr_sb.gen_sb_verilog_side_module_name(side, seg_id)); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -1902,7 +1926,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_num_sram, esti_sram_cnt - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2005,7 +2029,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -2076,7 +2100,8 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_sb_conf_bits_lsb(), rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, + is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2122,7 +2147,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or rr_gsb.gen_sb_verilog_side_module_name(side_manager.get_side(), seg_ids[iseg]), rr_gsb.gen_sb_verilog_side_instance_name(side_manager.get_side(), seg_ids[iseg])); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -2142,7 +2167,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, cur_sram_lsb, cur_sram_msb, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); /* Dump ports only visible during formal verification*/ if (0 < side_num_conf_bits) { @@ -2152,7 +2177,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sram_lsb, cur_sram_msb, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2249,7 +2274,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", rr_gsb.gen_sb_verilog_module_name()); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -2316,7 +2341,7 @@ void dump_verilog_routing_switch_box_unique_subckt(t_sram_orgz_info* cur_sram_or dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_sb_conf_bits_lsb(), rr_gsb.get_sb_conf_bits_msb(), - VERILOG_PORT_OUTPUT); + VERILOG_PORT_OUTPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2454,7 +2479,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info /* Print the definition of subckt*/ fprintf(fp, "module %s ( \n", gen_verilog_one_sb_module_name(cur_sb_info)); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -2517,7 +2542,7 @@ void dump_verilog_routing_switch_box_subckt(t_sram_orgz_info* cur_sram_orgz_info dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sb_info->conf_bits_lsb, cur_sb_info->conf_bits_msb - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2679,8 +2704,7 @@ int count_verilog_connection_box_one_side_reserved_conf_bits(t_sram_orgz_info* c static void dump_verilog_connection_box_short_interc(FILE* fp, const RRGSB& rr_gsb, t_rr_type cb_type, - t_rr_node* src_rr_node, - bool is_explicit_mapping) { + t_rr_node* src_rr_node) { t_rr_node* drive_rr_node = NULL; int iedge, check_flag; int xlow, ylow, height, index; @@ -2734,7 +2758,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ - FALSE, is_explicit_mapping); /* Do not specify the direction of this pin */ + FALSE, false); /* Do not specify the direction of this pin */ /* End */ fprintf(fp, ";\n"); @@ -2811,7 +2835,7 @@ void dump_verilog_connection_box_short_interc(FILE* fp, cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ - FALSE, is_explicit_mapping); /* Do not specify the direction of this pin */ + FALSE, false); /* Do not specify the direction of this pin */ /* End */ fprintf(fp, ";\n"); @@ -2942,8 +2966,15 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, } /* connect to input bus*/ - fprintf(fp, "%s_size%d_%d_inbus,", + if (true == is_explicit_mapping) { + fprintf(fp, ".in("); + } + fprintf(fp, "%s_size%d_%d_inbus", verilog_model->prefix, mux_size, verilog_model->cnt); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ", "); /* output port*/ xlow = src_rr_node->xlow; @@ -2954,11 +2985,17 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, rr_gsb.get_node_side_and_index(src_rr_node, OUT_PORT, &side, &index); /* We need to be sure that drive_rr_node is part of the CB */ assert((-1 != index)&&(NUM_SIDES != side)); + if (true == is_explicit_mapping) { + fprintf(fp, ".out("); + } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an output of a connection box */ rr_gsb.get_ipin_node(side, index)->ptc_num, rr_gsb.get_ipin_node_grid_side(side, index), xlow, ylow, /* Coordinator of Grid */ - FALSE, is_explicit_mapping); /* Do not specify the direction of port */ + FALSE, false); /* Do not specify the direction of port */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ @@ -3162,7 +3199,7 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_mux_conf_bits - 1); - fprintf(fp, "`endif\n"); + fprintf(fp, "is_explicit_mappingf\n"); /* Call the MUX SPICE model */ @@ -3195,11 +3232,17 @@ void dump_verilog_connection_box_mux(t_sram_orgz_info* cur_sram_orgz_info, get_rr_node_side_and_index_in_cb_info(src_rr_node, (*cur_cb_info), OUT_PORT, &side, &index); /* We need to be sure that drive_rr_node is part of the CB */ assert((-1 != index)&&(-1 != side)); + if (true == is_explicit_mapping) { + fprintf(fp, ".out("); + } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, /* This is an output of a connection box */ cur_cb_info->ipin_rr_node[side][index]->ptc_num, cur_cb_info->ipin_rr_node_grid_side[side][index], xlow, ylow, /* Coordinator of Grid */ - FALSE, is_explicit_mapping); /* Do not specify the direction of port */ + FALSE, false); /* Do not specify the direction of port */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); /* Different design technology requires different configuration bus! */ @@ -3305,7 +3348,7 @@ void dump_verilog_connection_box_interc(t_sram_orgz_info* cur_sram_orgz_info, if (1 == src_rr_node->fan_in) { /* Print a direct connection*/ - dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node, is_explicit_mapping); + dump_verilog_connection_box_short_interc(fp, rr_gsb, cb_type, src_rr_node); } else if (1 < src_rr_node->fan_in) { /* Print the multiplexer, fan_in >= 2 */ dump_verilog_connection_box_mux(cur_sram_orgz_info, fp, rr_gsb, cb_type, @@ -3502,7 +3545,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra fprintf(fp, "%s ", rr_gsb.gen_cb_verilog_module_name(cb_type)); fprintf(fp, "(\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } /* Print the ports of channels*/ @@ -3525,7 +3568,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), rr_gsb.get_ipin_node(cb_ipin_side, inode)->xlow, rr_gsb.get_ipin_node(cb_ipin_side, inode)->ylow, - TRUE, is_explicit_mapping); + TRUE, false); } } @@ -3554,7 +3597,7 @@ void dump_verilog_routing_connection_box_unique_module(t_sram_orgz_info* cur_sra dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, rr_gsb.get_cb_conf_bits_lsb(cb_type), rr_gsb.get_cb_conf_bits_msb(cb_type), - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -3704,7 +3747,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ fprintf(fp, "(\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } /* Print the ports of channels*/ @@ -3776,7 +3819,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_ dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_cb_info->conf_bits_lsb, cur_cb_info->conf_bits_msb - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -3876,13 +3919,13 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, /* X - channels [1...nx][0..ny]*/ for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANX); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, - ichan, device_rr_chan.get_module(CHANX, ichan)); + ichan, device_rr_chan.get_module(CHANX, ichan), explicit_port_mapping); } /* Y - channels [1...ny][0..nx]*/ vpr_printf(TIO_MESSAGE_INFO, "Writing Y-direction Channels...\n"); for (size_t ichan = 0; ichan < device_rr_chan.get_num_modules(CHANY); ++ichan) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, - ichan, device_rr_chan.get_module(CHANY, ichan)); + ichan, device_rr_chan.get_module(CHANY, ichan), explicit_port_mapping); } } else { /* Output the full array of routing channels */ @@ -3891,7 +3934,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (int ix = 1; ix < (nx + 1); ix++) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANX, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments); + arch.num_segments, explicit_port_mapping); } } /* Y - channels [1...ny][0..nx]*/ @@ -3900,7 +3943,7 @@ void dump_verilog_routing_resources(t_sram_orgz_info* cur_sram_orgz_info, for (int iy = 1; iy < (ny + 1); iy++) { dump_verilog_routing_chan_subckt(verilog_dir, subckt_dir, ix, iy, CHANY, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, LL_rr_indexed_data, - arch.num_segments); + arch.num_segments, explicit_port_mapping); } } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 267dd2c4a..830cbf02c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -131,7 +131,7 @@ void dump_verilog_top_netlist_memory_bank_internal_wires(t_sram_orgz_info* cur_s fprintf(fp, "`ifdef %s\n", verilog_formal_verification_preproc_flag); dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, 0, get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info) - 1, - VERILOG_PORT_WIRE); + VERILOG_PORT_WIRE, false); fprintf(fp, ";\n"); fprintf(fp, "`endif\n"); break; @@ -217,7 +217,7 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr fprintf(fp, " "); dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, 0, num_scffs - 1, - VERILOG_PORT_WIRE); + VERILOG_PORT_WIRE, false); fprintf(fp, ";\n"); fprintf(fp, "`endif\n"); @@ -249,7 +249,8 @@ void dump_verilog_top_netlist_scan_chain_internal_wires(t_sram_orgz_info* cur_sr /* Dump ports for the top-level module in Verilog netlist */ void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - enum e_dump_verilog_port_type dump_port_type) { + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping) { char* port_name = NULL; char split_sign; enum e_dump_verilog_port_type actual_dump_port_type; @@ -265,7 +266,7 @@ void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info, } /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, dump_global_port_type)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, dump_global_port_type, is_explicit_mapping)) { fprintf(fp, "%c\n", split_sign); } /* Inputs and outputs of I/O pads */ @@ -317,7 +318,8 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, int num_clocks, char* circuit_name, - t_spice verilog) { + t_spice verilog, + bool is_explicit_mapping) { /* int num_array_bl, num_array_wl; int bl_decoder_size, wl_decoder_size; @@ -334,7 +336,8 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "module %s_top (\n", circuit_name); fprintf(fp, "\n"); - dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT); + dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT, + is_explicit_mapping); fprintf(fp, ");\n"); @@ -367,7 +370,8 @@ void dump_verilog_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_inf static void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - int ix, int iy) { + int ix, int iy, + bool is_explicit_mapping) { if (NULL == fp) { vpr_printf(TIO_MESSAGE_ERROR, "(File:%s, [LINE%d])Invalid File Handler!\n", __FILE__, __LINE__); exit(1); @@ -387,7 +391,7 @@ void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -435,7 +439,8 @@ static void dump_verilog_defined_one_channel(FILE* fp, t_rr_type chan_type, int x, int y, int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { + t_ivec*** LL_rr_node_indices, + bool is_explicit_mapping) { int itrack; int chan_width = 0; t_rr_node** chan_rr_nodes = NULL; @@ -477,7 +482,7 @@ void dump_verilog_defined_one_channel(FILE* fp, fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports_explicit(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -572,7 +577,8 @@ void dump_verilog_defined_one_channel(FILE* fp, /* Call the sub-circuits for channels : Channel X and Channel Y*/ void dump_verilog_defined_channels(FILE* fp, int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices) { + t_ivec*** LL_rr_node_indices, + bool is_explicit_mapping) { int ix, iy; if (NULL == fp) { @@ -584,7 +590,7 @@ void dump_verilog_defined_channels(FILE* fp, for (iy = 0; iy < (ny + 1); iy++) { for (ix = 1; ix < (nx + 1); ix++) { dump_verilog_defined_one_channel(fp, CHANX, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping); } } @@ -592,7 +598,7 @@ void dump_verilog_defined_channels(FILE* fp, for (ix = 0; ix < (nx + 1); ix++) { for (iy = 1; iy < (ny + 1); iy++) { dump_verilog_defined_one_channel(fp, CHANY, ix, iy, - LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices); + LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, is_explicit_mapping); } } @@ -638,7 +644,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "("); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -699,7 +705,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf if (0 < (cur_cb_info.conf_bits_msb - cur_cb_info.conf_bits_lsb)) { dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, cur_cb_info.conf_bits_lsb, cur_cb_info.conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ if (0 < (cur_cb_info.conf_bits_msb - 1 - cur_cb_info.conf_bits_lsb)) { @@ -709,7 +715,7 @@ void dump_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_orgz_inf dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_cb_info.conf_bits_lsb, cur_cb_info.conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -805,7 +811,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, FALSE, is_explicit_mapping)) { fprintf(fp, ",\n"); } @@ -847,7 +853,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_sram_local_ports(fp, cur_sram_orgz_info, cur_sb_info.conf_bits_lsb, cur_sb_info.conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); } /* Dump ports only visible during formal verification*/ @@ -858,7 +864,7 @@ void dump_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_sb_info.conf_bits_lsb, cur_sb_info.conf_bits_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h index 74549b8d6..91b185e08 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h @@ -3,14 +3,16 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, int num_clocks, char* circuit_name, - t_spice verilog); + t_spice verilog, + bool is_explicit_mapping); void dump_verilog_top_netlist_internal_wires(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp); void dump_verilog_defined_channels(FILE* fp, int LL_num_rr_nodes, t_rr_node* LL_rr_node, - t_ivec*** LL_rr_node_indices); + t_ivec*** LL_rr_node_indices, + bool is_explicit_mapping); void dump_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, bool is_explicit_mapping); @@ -26,7 +28,8 @@ void dump_verilog_configuration_circuits(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - enum e_dump_verilog_port_type dump_port_type); + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping); void verilog_compact_generate_fake_xy_for_io_border_side(int border_side, int* ix, int* iy) ; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c index ce309d764..6671ec6e4 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.c @@ -312,7 +312,8 @@ void dump_verilog_top_testbench_ports(t_sram_orgz_info* cur_sram_orgz_info, void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - char* circuit_name) { + char* circuit_name, + bool is_explicit_mapping) { /* int iblock, iopad_idx; */ @@ -322,7 +323,7 @@ void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_ fprintf(fp, "//------Call defined Top-level Verilog Module -----\n"); fprintf(fp, "%s_top U0 (\n", circuit_name); - dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT); + dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, ");\n"); return; @@ -1354,7 +1355,7 @@ void dump_verilog_top_testbench(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_top_testbench_ports(cur_sram_orgz_info, fp, circuit_name); /* Call defined top-level module */ - dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name); + dump_verilog_top_testbench_call_top_module(cur_sram_orgz_info, fp, circuit_name, false); /* Add stimuli for reset, set, clock and iopad signals */ dump_verilog_top_testbench_stimuli(cur_sram_orgz_info, fp, verilog); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h index 320786a40..caf107479 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_testbench.h @@ -6,7 +6,8 @@ void dump_verilog_top_testbench_global_ports_stimuli(FILE* fp, t_llist* head); void dump_verilog_top_testbench_call_top_module(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, - char* circuit_name); + char* circuit_name, + bool is_explicit_mapping); void dump_verilog_top_testbench_stimuli(t_sram_orgz_info* cur_sram_orgz_info, FILE* fp, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 5b7f472c0..c3287e7a7 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -945,7 +945,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, /* Dump all the global ports that are stored in the linked list */ int dump_verilog_global_ports(FILE* fp, t_llist* head, - boolean dump_port_type) { + boolean dump_port_type, + bool is_explicit_mapping) { t_llist* temp = head; t_spice_model_port* cur_global_port = NULL; int dumped_port_cnt = 0; @@ -959,6 +960,10 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, /* fprintf(fp, "//----- BEGIN Global ports -----\n"); */ while(NULL != temp) { cur_global_port = (t_spice_model_port*)(temp->dptr); + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_global_port->prefix); + } if (TRUE == dump_port_type) { fprintf(fp, "%s [0:%d] %s", verilog_convert_port_type_to_string(cur_global_port->type), @@ -969,7 +974,9 @@ int dump_verilog_global_ports(FILE* fp, t_llist* head, cur_global_port->prefix, cur_global_port->size - 1); } - + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* if this is the tail, we do not dump a comma */ if (NULL != temp->next) { fprintf(fp, ", //---- global port \n"); @@ -1357,7 +1364,8 @@ void dump_verilog_sram_outports(FILE* fp, void dump_verilog_formal_verification_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int sram_lsb, int sram_msb, - enum e_dump_verilog_port_type dump_port_type) { + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping) { t_spice_model* mem_model = NULL; char* port_name = NULL; char* port_full_name = NULL; @@ -1394,8 +1402,14 @@ void dump_verilog_formal_verification_sram_ports(FILE* fp, /*Malloc and generate the full name of port */ port_full_name = (char*)my_malloc(sizeof(char)*(strlen(mem_model->prefix) + strlen(port_name) + 1 + 1)); sprintf(port_full_name, "%s_%s", mem_model->prefix, port_name); - + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + port_full_name); + } dump_verilog_generic_port(fp, dump_port_type, port_full_name, sram_lsb, sram_msb); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* Free */ /* Local variables such as port1_name and port2 name are automatically freed */ @@ -1508,7 +1522,7 @@ void dump_verilog_formal_verification_sram_ports_wiring(FILE* fp, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, sram_lsb, sram_msb, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, false); fprintf(fp, ";\n"); return; @@ -1530,7 +1544,7 @@ void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, sram_lsb, sram_msb, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, false); fprintf(fp, ";\n"); return; @@ -1540,7 +1554,8 @@ void dump_verilog_formal_verification_mux_sram_ports_wiring(FILE* fp, void dump_verilog_sram_local_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int sram_lsb, int sram_msb, - enum e_dump_verilog_port_type dump_port_type) { + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping) { /* Need to dump inverted BL/WL if needed */ int num_blb_ports, num_wlb_ports; t_spice_model_port** blb_port = NULL; @@ -1578,14 +1593,26 @@ void dump_verilog_sram_local_ports(FILE* fp, break; case SPICE_SRAM_SCAN_CHAIN: /* Dump the first port: SRAM_out of CMOS MUX or BL of RRAM MUX */ + if (true == is_explicit_mapping) { + fprintf(fp, ".scff_scff_head("); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, sram_lsb, sram_lsb, -1, dump_port_type); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ",\n"); /* Dump the first port: SRAM_outb of CMOS MUX or WL of RRAM MUX */ + if (true == is_explicit_mapping) { + fprintf(fp, ".scff_scff_tail("); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, sram_msb, sram_msb, 0, dump_port_type); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } break; default: vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization !\n", @@ -2582,7 +2609,7 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m if (TRUE == is_explicit_mapping) { fprintf(fp, ")"); } - fprintf(fp, ",\n"); + fprintf(fp, ", "); if (TRUE == is_explicit_mapping) { fprintf(fp, ".sram_inv("); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index cf8427720..8930d8068 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -76,7 +76,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, boolean require_explicit_port_map); int dump_verilog_global_ports(FILE* fp, t_llist* head, - boolean dump_port_type); + boolean dump_port_type, + bool is_explicit_mapping); int dump_verilog_global_ports_explicit(FILE* fp, t_llist* head, boolean dump_port_type); @@ -115,7 +116,8 @@ void dump_verilog_sram_outports(FILE* fp, void dump_verilog_formal_verification_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int sram_lsb, int sram_msb, - enum e_dump_verilog_port_type dump_port_type); + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping); void dump_verilog_sram_one_port(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, @@ -126,7 +128,8 @@ void dump_verilog_sram_one_port(FILE* fp, void dump_verilog_sram_local_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int sram_lsb, int sram_msb, - enum e_dump_verilog_port_type dump_port_type); + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping); void dump_verilog_sram_ports(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int sram_lsb, int sram_msb, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c index 573c821ac..74ac2317d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_verification_top_netlist.c @@ -187,7 +187,7 @@ void dump_verilog_formal_verfication_top_netlist_call_top_module(t_sram_orgz_inf circuit_name, formal_verification_top_module_uut_name); - dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT); + dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_CONKT, false); fprintf(fp, ");\n"); return; @@ -338,14 +338,14 @@ void dump_verilog_formal_verification_top_netlist_config_bitstream(t_sram_orgz_i case SPICE_SRAM_SCAN_CHAIN: dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_conf_bit->index, cur_conf_bit->index, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, false); fprintf(fp, " = 1'b%d", cur_conf_bit->sram_bit->val); break; case SPICE_SRAM_MEMORY_BANK: dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_conf_bit->bl->addr, cur_conf_bit->bl->addr, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, false); fprintf(fp, " = 1'b%d", cur_conf_bit->bl->val); break; From 4392c6bc3aa1030eed14a32a8ac115722856d30b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 2 Jul 2019 15:34:59 -0600 Subject: [PATCH 15/84] bug fixing in fpga_flow scripts and add more print-out message for VPR --- fpga_flow/scripts/fpga_flow.pl | 21 +- fpga_flow/scripts/pro_blif.pl | 10 +- fpga_flow/scripts/rewrite_path_in_file.pl | 4 +- .../rr_graph/rr_graph_builder_utils.cpp | 179 ++++++++++++++++++ .../device/rr_graph/rr_graph_builder_utils.h | 2 + .../rr_graph/tileable_rr_graph_builder.cpp | 2 +- vpr7_x2p/vpr/SRC/route/rr_graph.c | 4 + 7 files changed, 207 insertions(+), 15 deletions(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 92111bb87..79edc0d15 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -20,6 +20,7 @@ my $mydate = gmctime(); my $cwd = getcwd(); # Global Variants +my ($max_route_width_retry) = (1000); # input Option Hash my %opt_h; my $opt_ptr = \%opt_h; @@ -112,7 +113,7 @@ sub generate_path($) mkpath "$mypath"; print "Path($mypath) does not exist...Create it.\n"; } - return 1; + return 0; } # Print the usage @@ -267,7 +268,7 @@ sub read_opt_into_hash($ $ $) } } } - return 1; + return 0; } # Read options @@ -370,7 +371,7 @@ sub opts_read() &print_opts(); - return 1; + return 0; } # List the options @@ -381,7 +382,7 @@ sub print_opts() while(my ($key,$value) = each(%opt_h)) {print "$key : $value\n";} - return 1; + return 0; } @@ -429,7 +430,7 @@ sub check_keywords_conf() {die "Error: Keyword($mctgy[$imcg],$sctgy[$imcg]->[$iscg]) is missing!\n";} } } - return 1; + return 0; } # Read the configuration file @@ -467,7 +468,7 @@ sub read_conf() print "Checking these keywords..."; print "Successfully\n"; close(CONF); - return 1; + return 0; } sub read_benchmarks() @@ -499,7 +500,7 @@ sub read_benchmarks() foreach my $temp(@benchmark_names) {print "$temp\n";} close(FCONF); - return 1; + return 0; } # Input program path is like "~/program_dir/program_name" @@ -1744,6 +1745,9 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { if (-e $vpr_route) { print "INFO: try route_chan_width($min_chan_width) success!\n"; last; #Jump out + } elsif ($max_route_width_retry < $min_chan_width) { + # I set a threshold of 1000 as it is the limit of VPR + die "ERROR: Route Fail for $abc_blif_out with a min_chan_width of $min_chan_width!\n"; } else { print "INFO: try route_chan_width($min_chan_width) failed! Retry with +2...\n"; $min_chan_width += 2; @@ -1767,6 +1771,9 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { if (-e $vpr_route) { print "INFO: try route_chan_width($fix_chan_width) success!\n"; last; #Jump out + } elsif ($max_route_width_retry < $fix_chan_width) { + # I set a threshold of 1000 as it is the limit of VPR + die "ERROR: Route Fail for $abc_blif_out with a min_chan_width of $fix_chan_width!\n"; } else { print "INFO: try route_chan_width($fix_chan_width) failed! Retry with +2...\n"; $fix_chan_width += 2; diff --git a/fpga_flow/scripts/pro_blif.pl b/fpga_flow/scripts/pro_blif.pl index 25d44816f..d48bc54a5 100755 --- a/fpga_flow/scripts/pro_blif.pl +++ b/fpga_flow/scripts/pro_blif.pl @@ -29,7 +29,7 @@ sub print_usage() print " -add_default_clk\n"; print " -initial_blif \n"; print "\n"; - return 1; + return 0; } sub opts_read() @@ -53,7 +53,7 @@ sub opts_read() } } } - return 1; + return 0; } # Print a line of blif netlist @@ -432,15 +432,15 @@ sub scan_blif() } close($FIN2); close($FOUT); - return 1; + return 0; } sub main() { &opts_read(); &scan_blif(); - return 1; + return 0; } &main(); -exit(1); +exit(0); diff --git a/fpga_flow/scripts/rewrite_path_in_file.pl b/fpga_flow/scripts/rewrite_path_in_file.pl index b65868f60..5c2248913 100644 --- a/fpga_flow/scripts/rewrite_path_in_file.pl +++ b/fpga_flow/scripts/rewrite_path_in_file.pl @@ -90,7 +90,7 @@ sub findPath(){ } else { $path = "$path"."/"."$folders[$count]"; if($folders[$count] eq $folder_top){ - print "$path\n"; + #print "$path\n"; return $path; } } @@ -135,4 +135,4 @@ sub main() } &main(); -exit(1); +exit(0); diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp index 40d89ee6e..d7d2fcd34 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp @@ -506,3 +506,182 @@ void print_rr_graph_stats(const t_rr_graph& rr_graph) { return; } + +/************************************************************************ + * Print statistics of a rr_graph + * 1. We print number of nodes by types + * 2. Print the number of edges + ************************************************************************/ +void print_rr_graph_stats() { + + /* Print number of nodes */ + vpr_printf(TIO_MESSAGE_INFO, "Statistics on number of RR nodes (by node type): \n"); + + /* Count the number of nodes */ + std::vector num_nodes_per_type; + num_nodes_per_type.resize(NUM_RR_TYPES); + num_nodes_per_type.assign(NUM_RR_TYPES, 0); + + for (int inode = 0; inode < num_rr_nodes; ++inode) { + num_nodes_per_type[rr_node[inode].type]++; + } + + /* Get the largest string size of rr_node_typename */ + size_t max_str_typename = 0; + for (int type = 0; type < NUM_RR_TYPES; ++type) { + max_str_typename = std::max(max_str_typename, strlen(rr_node_typename[type])); + } + + /* Constant strings */ + char* type_str = " Type "; + char* total_str = " Total "; + char* node_str = " No. of nodes "; + char* edge_str = " No. of edges "; + + /* Count the number of characters per line: + * we check the string length of each node type + * Then we plus two reserved strings "type" and "total" + */ + size_t num_char_per_line = 0; + for (int type = 0; type < NUM_RR_TYPES; ++type) { + num_char_per_line += 6 + max_str_typename; + } + num_char_per_line += strlen(type_str); + num_char_per_line += strlen(total_str); + + /* Print splitter */ + for (size_t ichar = 0; ichar < num_char_per_line; ++ichar) { + vpr_printf(TIO_MESSAGE_INFO, "-"); + } + vpr_printf(TIO_MESSAGE_INFO, "\n"); + + /* Print node type */ + vpr_printf(TIO_MESSAGE_INFO, "%s", type_str); + for (int type = 0; type < NUM_RR_TYPES; ++type) { + vpr_printf(TIO_MESSAGE_INFO, " %s ", rr_node_typename[type]); + } + vpr_printf(TIO_MESSAGE_INFO, "%s", total_str); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + + /* Print node numbers */ + int total_num_nodes = 0; + vpr_printf(TIO_MESSAGE_INFO, "%s", node_str); + for (int type = 0; type < NUM_RR_TYPES; ++type) { + vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_nodes_per_type[type]); + total_num_nodes += num_nodes_per_type[type]; + } + vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_rr_nodes); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + + /* Check we have the same number as stated in rr_graph */ + assert (total_num_nodes == num_rr_nodes); + + /* Count the number of edges */ + size_t num_edges = 0; + std::vector num_edges_per_type; + num_edges_per_type.resize(NUM_RR_TYPES); + num_edges_per_type.assign(NUM_RR_TYPES, 0); + + for (int inode = 0; inode < num_rr_nodes; ++inode) { + num_edges_per_type[rr_node[inode].type] += rr_node[inode].num_edges; + } + for (int inode = 0; inode < num_rr_nodes; ++inode) { + num_edges += rr_node[inode].num_edges; + } + + /* Print number of edges */ + vpr_printf(TIO_MESSAGE_INFO, "%s", edge_str); + for (int type = 0; type < NUM_RR_TYPES; ++type) { + vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_edges_per_type[type]); + } + vpr_printf(TIO_MESSAGE_INFO, " %10lu ", num_edges); + vpr_printf(TIO_MESSAGE_INFO, "\n"); + + /* Print splitter */ + for (size_t ichar = 0; ichar < num_char_per_line; ++ichar) { + vpr_printf(TIO_MESSAGE_INFO, "-"); + } + vpr_printf(TIO_MESSAGE_INFO, "\n"); + + /* Print MUX size distribution */ + /* Get the maximum SB mux size */ + short max_sb_mux_size = 0; + for (int inode = 0; inode < num_rr_nodes; ++inode) { + /* MUX multiplexers for SBs */ + if ( (CHANX == rr_node[inode].type) + || (CHANY == rr_node[inode].type) ) { + max_sb_mux_size = std::max(rr_node[inode].fan_in, max_sb_mux_size); + } + } + /* Get the minimum SB mux size */ + short min_sb_mux_size = max_sb_mux_size; + for (int inode = 0; inode < num_rr_nodes; ++inode) { + /* MUX multiplexers for SBs */ + if ( (CHANX == rr_node[inode].type) + || (CHANY == rr_node[inode].type) ) { + min_sb_mux_size = std::min(rr_node[inode].fan_in, min_sb_mux_size); + } + } + + /* Get the minimum SB mux size */ + int num_sb_mux = 0; + short avg_sb_mux_size = 0; + for (int inode = 0; inode < num_rr_nodes; ++inode) { + /* MUX multiplexers for SBs */ + if ( (CHANX == rr_node[inode].type) + || (CHANY == rr_node[inode].type) ) { + avg_sb_mux_size += rr_node[inode].fan_in; + num_sb_mux++; + } + } + avg_sb_mux_size /= num_sb_mux; + /* Print statistics */ + vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); + vpr_printf(TIO_MESSAGE_INFO, "Total No. of Switch Block Multiplexer size:%d\n", num_sb_mux); + vpr_printf(TIO_MESSAGE_INFO, "Maximum Switch Block Multiplexer size:%d\n", max_sb_mux_size); + vpr_printf(TIO_MESSAGE_INFO, "Minimum Switch Block Multiplexer size:%d\n", min_sb_mux_size); + vpr_printf(TIO_MESSAGE_INFO, "Average Switch Block Multiplexer size:%d\n", avg_sb_mux_size); + vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); + + /* Get the maximum SB mux size */ + short max_cb_mux_size = 0; + for (int inode = 0; inode < num_rr_nodes; ++inode) { + /* MUX multiplexers for SBs */ + if (IPIN == rr_node[inode].type) { + max_cb_mux_size = std::max(rr_node[inode].fan_in, max_cb_mux_size); + } + } + /* Get the minimum SB mux size */ + short min_cb_mux_size = max_cb_mux_size; + for (int inode = 0; inode < num_rr_nodes; ++inode) { + /* MUX multiplexers for SBs */ + if (IPIN == rr_node[inode].type) { + min_cb_mux_size = std::min(rr_node[inode].fan_in, min_cb_mux_size); + } + } + + /* Get the minimum SB mux size */ + int num_cb_mux = 0; + short avg_cb_mux_size = 0; + for (int inode = 0; inode < num_rr_nodes; ++inode) { + /* MUX multiplexers for SBs */ + if (IPIN == rr_node[inode].type) { + avg_cb_mux_size += rr_node[inode].fan_in; + num_cb_mux++; + } + } + avg_cb_mux_size /= num_cb_mux; + vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); + vpr_printf(TIO_MESSAGE_INFO, "Total No. of Connection Block Multiplexer size:%d\n", num_cb_mux); + vpr_printf(TIO_MESSAGE_INFO, "Maximum Connection Block Multiplexer size:%d\n", max_cb_mux_size); + vpr_printf(TIO_MESSAGE_INFO, "Minimum Connection Block Multiplexer size:%d\n", min_cb_mux_size); + vpr_printf(TIO_MESSAGE_INFO, "Average Connection Block Multiplexer size:%d\n", avg_cb_mux_size); + vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); + + + return; +} + +/************************************************************************ + * End of file : rr_graph_builder_utils.cpp + ***********************************************************************/ diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h index 46021ee6b..c213546d5 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.h @@ -43,5 +43,7 @@ short get_track_rr_node_end_track_id(const t_rr_node* track_rr_node); void print_rr_graph_stats(const t_rr_graph& rr_graph); +void print_rr_graph_stats(); + #endif diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp index 2e56e693f..25fa5929a 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp @@ -1038,7 +1038,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, build_rr_graph_direct_connections(&rr_graph, device_size, grids, delayless_switch, num_directs, directs, clb_to_clb_directs); - print_rr_graph_stats(rr_graph); + //print_rr_graph_stats(rr_graph); /* Clear driver switches of the rr_graph */ clear_rr_graph_driver_switch(&rr_graph); diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph.c b/vpr7_x2p/vpr/SRC/route/rr_graph.c index afe937e9a..d6edcf7fd 100755 --- a/vpr7_x2p/vpr/SRC/route/rr_graph.c +++ b/vpr7_x2p/vpr/SRC/route/rr_graph.c @@ -17,6 +17,7 @@ #include "ReadOptions.h" #include "tileable_rr_graph_builder.h" +#include "rr_graph_builder_utils.h" /* Xifan TANG: SWSEG SUPPORT */ #include "rr_graph_swseg.h" @@ -245,6 +246,9 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types, } + /* Print statistics of RR graph */ + print_rr_graph_stats(); + return; } From 02398818a98392ff6b7174bd36bff9e5f11ff7b2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 10:33:02 -0600 Subject: [PATCH 16/84] update fpga_flow scripts to support matlab data format. Minor fix on rr_graph_area --- fpga_flow/scripts/fpga_flow.pl | 156 ++++++++++++++++-- .../fpga_x2p/base/fpga_x2p_bitstream_utils.h | 4 + .../fpga_x2p/base/fpga_x2p_pbtypes_utils.h | 5 +- vpr7_x2p/vpr/SRC/route/rr_graph_area.c | 2 +- 4 files changed, 151 insertions(+), 16 deletions(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 79edc0d15..50f063106 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -128,6 +128,7 @@ sub print_usage() print " -N : N-LUT/Matrix\n"; print " Other Options:\n"; print " [ General ] \n"; + print " \t-matlab_rpt : .m file consists of data compatible to matlab scripts. Specify the data name to be appeared in the script\n"; print " \t-I : Number of inputs of a CLB, mandatory when mpack1 flow is chosen\n"; print " \t-K : K-LUT, mandatory when standard flow is chosen\n"; print " \t-M : M-Matrix, mandatory when mpack1 flow is chosen\n"; @@ -306,6 +307,7 @@ sub opts_read() &read_opt_into_hash("conf","on","on"); &read_opt_into_hash("benchmark","on","on"); &read_opt_into_hash("rpt","on","on"); + &read_opt_into_hash("matlab_rpt","on","off"); # Add an option to output report file compatible to matlab scripts &read_opt_into_hash("N","on","on"); &read_opt_into_hash("K","on","off"); &read_opt_into_hash("I","on","off"); @@ -1295,7 +1297,6 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) { my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_; my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); - chdir $vpr_dir; my ($power_opts); if ("on" eq $opt_ptr->{power}) { @@ -1426,6 +1427,10 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) if ("on" eq $opt_ptr->{vpr_max_router_iteration}) { $other_opt .= "--max_router_iterations $opt_ptr->{vpr_max_router_iteration_val} "; } + + chdir $vpr_dir; + print "Entering $vpr_dir\n"; + print "./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log\n"; system("./$vpr_name $arch $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $packer_opts $chan_width_opt $vpr_spice_opts $other_opt > $log"); @@ -1454,7 +1459,6 @@ sub run_vpr_route($ $ $ $ $ $ $ $ $) { my ($blif,$bm,$arch,$net,$place,$route,$fix_chan_width,$log,$act_file) = @_; my ($vpr_dir,$vpr_name) = &split_prog_path($conf_ptr->{dir_path}->{vpr_path}->{val}); - chdir $vpr_dir; my ($power_opts); if ("on" eq $opt_ptr->{power}) { @@ -1508,7 +1512,12 @@ sub run_vpr_route($ $ $ $ $ $ $ $ $) $other_opt .= "--router_algorithm breadth_first "; } + chdir $vpr_dir; + print "Entering $vpr_dir\n"; + + print "./$vpr_name $arch $blif --route --blif_file $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $chan_width_opt $vpr_spice_opts $other_opt > $log\n"; system("./$vpr_name $arch $blif --route --blif_file $blif --net_file $net --place_file $place --route_file $route --full_stats --nodisp $power_opts $chan_width_opt $vpr_spice_opts $other_opt > $log"); + print "\n"; chdir $cwd; } @@ -2975,6 +2984,14 @@ sub gen_csv_rpt_vtr_flow($ $) my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); + # adapt to matlab format if the option is enabled + if ("on" eq $opt_ptr->{matlab_rpt}) { + # Print the data name + print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; + # We will set the stats line to be commented + print $CSVFH "%"; + } + # Print out Standard Stats First print $CSVFH "$tag"; print $CSVFH ",LUTs"; @@ -3003,7 +3020,14 @@ sub gen_csv_rpt_vtr_flow($ $) # Check log/stats one by one foreach $tmp(@benchmark_names) { $tmp =~ s/\.v$//g; - print $CSVFH "$tmp"; + + # For matlab script, we use {} for string + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "{'$tmp'}"; + } else { + print $CSVFH "$tmp"; + } + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; @@ -3031,7 +3055,17 @@ sub gen_csv_rpt_vtr_flow($ $) print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; } - print $CSVFH "\n"; + # For matlab script, we end with a semicolumn to be compatiable to matlab + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH ";\n"; + } else { + print $CSVFH "\n"; + } + } + + # For matlab script, we end with ]; + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "];\n"; } } @@ -3041,6 +3075,14 @@ sub gen_csv_rpt_yosys_vpr_flow($ $) my ($tmp,$ikw,$tmpkw); my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); + + # adapt to matlab format if the option is enabled + if ("on" eq $opt_ptr->{matlab_rpt}) { + # Print the data name + print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; + # We will set the stats line to be commented + print $CSVFH "%"; + } # Print out Standard Stats First print $CSVFH "$tag"; @@ -3071,7 +3113,14 @@ sub gen_csv_rpt_yosys_vpr_flow($ $) foreach $tmp(@benchmark_names) { my @tokens = split('/', $tmp); $tmp = $tokens[0]; - print $CSVFH "$tmp"; + + # For matlab script, we use {} for string + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "{'$tmp'}"; + } else { + print $CSVFH "$tmp"; + } + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; @@ -3099,7 +3148,17 @@ sub gen_csv_rpt_yosys_vpr_flow($ $) print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; } - print $CSVFH "\n"; + # For matlab script, we end with a semicolumn to be compatiable to matlab + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH ";\n"; + } else { + print $CSVFH "\n"; + } + } + + # For matlab script, we end with ]; + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "];\n"; } } @@ -3109,6 +3168,14 @@ sub gen_csv_rpt_standard_flow($ $) my ($tmp,$ikw,$tmpkw); my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); + + # adapt to matlab format if the option is enabled + if ("on" eq $opt_ptr->{matlab_rpt}) { + # Print the data name + print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; + # We will set the stats line to be commented + print $CSVFH "%"; + } # Print out Standard Stats First print $CSVFH "$tag"; @@ -3138,7 +3205,13 @@ sub gen_csv_rpt_standard_flow($ $) # Check log/stats one by one foreach $tmp(@benchmark_names) { $tmp =~ s/\.blif$//g; - print $CSVFH "$tmp"; + # For matlab script, we use {} for string + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "{'$tmp'}"; + } else { + print $CSVFH "$tmp"; + } + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; @@ -3170,7 +3243,18 @@ sub gen_csv_rpt_standard_flow($ $) print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; } - print $CSVFH "\n"; + + # For matlab script, we end with a semicolumn to be compatiable to matlab + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH ";\n"; + } else { + print $CSVFH "\n"; + } + } + + # For matlab script, we end with ]; + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "];\n"; } } @@ -3181,6 +3265,14 @@ sub gen_csv_rpt_mpack2_flow($ $) my @keywords; my ($K_val,$N_val) = ($opt_ptr->{K_val},$opt_ptr->{N_val}); + # adapt to matlab format if the option is enabled + if ("on" eq $opt_ptr->{matlab_rpt}) { + # Print the data name + print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; + # We will set the stats line to be commented + print $CSVFH "%"; + } + # Print out Mpack stats Second print $CSVFH "$tag"; if ("on" eq $opt_ptr->{min_route_chan_width}) { @@ -3214,7 +3306,13 @@ sub gen_csv_rpt_mpack2_flow($ $) # Check log/stats one by one foreach $tmp(@benchmark_names) { $tmp =~ s/\.blif$//g; - print $CSVFH "$tmp"; + # For matlab script, we use {} for string + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "{'$tmp'}"; + } else { + print $CSVFH "$tmp"; + } + if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{fix_route_chan_width}"; @@ -3247,7 +3345,17 @@ sub gen_csv_rpt_mpack2_flow($ $) print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{dynamic}"; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$K_val}->{power}->{leakage}"; } - print $CSVFH "\n"; + # For matlab script, we end with a semicolumn to be compatiable to matlab + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH ";\n"; + } else { + print $CSVFH "\n"; + } + } + + # For matlab script, we end with ]; + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "];\n"; } } @@ -3258,6 +3366,14 @@ sub gen_csv_rpt_mpack1_flow($ $) my @keywords; my ($N_val,$M_val) = ($opt_ptr->{N_val},$opt_ptr->{M_val}); + # adapt to matlab format if the option is enabled + if ("on" eq $opt_ptr->{matlab_rpt}) { + # Print the data name + print $CSVFH "$opt_ptr->{matlab_rpt_val} = [\n"; + # We will set the stats line to be commented + print $CSVFH "%"; + } + # Print out Mpack stats Second print $CSVFH "$tag"; print $CSVFH ",MATRIX"; @@ -3281,7 +3397,13 @@ sub gen_csv_rpt_mpack1_flow($ $) # Check log/stats one by one foreach $tmp(@benchmark_names) { $tmp =~ s/\.blif$//g; - print $CSVFH "$tmp"; + # For matlab script, we use {} for string + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "{'$tmp'}"; + } else { + print $CSVFH "$tmp"; + } + #foreach $tmpkw(@keywords) { print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{MATRIX}"; @keywords = split /\|/,$conf_ptr->{csv_tags}->{mpack_tags}->{val}; @@ -3306,7 +3428,17 @@ sub gen_csv_rpt_mpack1_flow($ $) print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{total}"; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{dynamic}"; print $CSVFH ",$rpt_ptr->{$tag}->{$tmp}->{$N_val}->{$M_val}->{power}->{leakage}"; - print $CSVFH "\n"; + # For matlab script, we end with a semicolumn to be compatiable to matlab + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH ";\n"; + } else { + print $CSVFH "\n"; + } + } + + # For matlab script, we end with ]; + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "];\n"; } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h index 6f8c7751d..2ce9546a5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h @@ -1,3 +1,5 @@ +#ifndef FPGA_X2P_BITSTREAM_UTILS_H +#define FPGA_X2P_BITSTREAM_UTILS_H int determine_decoder_size(int num_addr_out); @@ -81,3 +83,5 @@ void add_sram_conf_bits_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, void add_mux_conf_bits_to_sram_orgz_info(t_sram_orgz_info* cur_sram_orgz_info, t_spice_model* mux_spice_model, int mux_size) ; + +#endif diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h index 1413b0c41..34063fc95 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_pbtypes_utils.h @@ -1,6 +1,8 @@ #ifndef FPGA_X2P_PBTYPES_UTILS_H #define FPGA_X2P_PBTYPES_UTILS_H +#include "fpga_x2p_bitstream_utils.h" + void check_pb_graph_edge(t_pb_graph_edge pb_graph_edge); void check_pb_graph_pin_edges(t_pb_graph_pin pb_graph_pin); @@ -74,9 +76,6 @@ void mark_one_pb_parasitic_nets(t_phy_pb* cur_pb); int count_num_conf_bit_one_interc(t_interconnect* cur_interc, enum e_sram_orgz cur_sram_orgz_type); -int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc, - enum e_sram_orgz cur_sram_orgz_type); - int count_num_conf_bits_pb_type_mode_interc(t_mode* cur_pb_type_mode, enum e_sram_orgz cur_sram_orgz_type); diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph_area.c b/vpr7_x2p/vpr/SRC/route/rr_graph_area.c index 809bd4add..7790d57af 100755 --- a/vpr7_x2p/vpr/SRC/route/rr_graph_area.c +++ b/vpr7_x2p/vpr/SRC/route/rr_graph_area.c @@ -692,8 +692,8 @@ static float trans_per_mux(int num_inputs, float trans_sram_bit, break; case SPICE_MODEL_STRUCTURE_MULTILEVEL: assert(1 < target_switch.switch_num_level); - sram_trans = trans_sram_bit * target_switch.switch_num_level; mux_basis = determine_num_input_basis_multilevel_mux(num_inputs, target_switch.switch_num_level); + sram_trans = trans_sram_bit * target_switch.switch_num_level * mux_basis; num_second_stage_trans = (int)pow((double)mux_basis, (double)(target_switch.switch_num_level - 1)); pass_trans = ((num_second_stage_trans - 1) * mux_basis/(mux_basis-1)) * pass_trans_area + num_inputs * pass_trans_area; From e0793c891af24e4eaf9d6aed4712036e125d2f19 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 3 Jul 2019 12:04:55 -0600 Subject: [PATCH 17/84] Update demo --- ERI_demo/ERI.sh | 6 +- ERI_demo/eri_demo.sh | 18 +- ERI_demo/pipelined_1b_adder.act | 61 ---- ERI_demo/pipelined_32b_adder.act | 331 ------------------ ERI_demo/pipelined_32b_adder.blif | 278 --------------- ERI_demo/pipelined_32b_adder_ERI_demo_tb.v | 156 --------- ERI_demo/pipelined_8b_adder.act | 95 +++++ ..._1b_adder.blif => pipelined_8b_adder.blif} | 93 +++-- ...lined_32b_adder.v => pipelined_8b_adder.v} | 34 +- .../pipelined_8b_adder_formal_random_top_tb.v | 219 ++++++++++++ 10 files changed, 387 insertions(+), 904 deletions(-) delete mode 100644 ERI_demo/pipelined_1b_adder.act delete mode 100644 ERI_demo/pipelined_32b_adder.act delete mode 100644 ERI_demo/pipelined_32b_adder.blif delete mode 100644 ERI_demo/pipelined_32b_adder_ERI_demo_tb.v create mode 100644 ERI_demo/pipelined_8b_adder.act rename ERI_demo/{pipelined_1b_adder.blif => pipelined_8b_adder.blif} (65%) rename ERI_demo/{pipelined_32b_adder.v => pipelined_8b_adder.v} (65%) create mode 100644 ERI_demo/pipelined_8b_adder_formal_random_top_tb.v diff --git a/ERI_demo/ERI.sh b/ERI_demo/ERI.sh index 0492a5e2b..75211050a 100755 --- a/ERI_demo/ERI.sh +++ b/ERI_demo/ERI.sh @@ -5,11 +5,11 @@ my_pwd=$PWD fpga_flow_scripts=${my_pwd}/fpga_flow/scripts vpr_path=${my_pwd}/vpr7_x2p/vpr -benchmark="pipelined_32b_adder" +benchmark="pipelined_8b_adder" include_netlists="_include_netlists.v" compiled_file="compiled_$benchmark" tb_formal_postfix="_top_formal_verification_random_tb" -verilog_output_dirname="${benchmark}_Verilog" +verilog_output_dirname="${vpr_path}${benchmark}_Verilog" log_file="${benchmark}_sim.log" new_reg_sh="${PWD}/ERI_demo/my_eri_demo.sh" template_sh="${PWD}/ERI_demo/eri_demo.sh" @@ -29,7 +29,7 @@ cd $my_pwd # Start the script -> run the fpga generation -> run the simulation -> check the log file source $new_reg_sh # Leave us in vpr folder iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix -vvp $compiled_file -j 16 >> $log_file +vvp $compiled_file -j 64 >> $log_file result=`grep "Succeed" $log_file` if ["$result" = ""]; then diff --git a/ERI_demo/eri_demo.sh b/ERI_demo/eri_demo.sh index 112078dc5..807c5110b 100644 --- a/ERI_demo/eri_demo.sh +++ b/ERI_demo/eri_demo.sh @@ -3,7 +3,7 @@ # Set variables # For FPGA-Verilog ONLY -benchmark="pipelined_32b_adder" +benchmark="pipelined_8b_adder" OpenFPGA_path="OPENFPGAPATHKEYWORD" verilog_output_dirname="${benchmark}_Verilog" verilog_output_dirpath="$vpr_path" @@ -21,13 +21,17 @@ new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" ff_keyword="GENERATED_DIR_KEYWORD" ff_include_path="$verilog_output_dirpath/$verilog_output_dirname" arch_ff_keyword="FFPATHKEYWORD" +tb_formal_ext="_formal_random_top_tb.v" +formal_postfix="_top_formal_verification" +clk_unmapped="clk\[0:0\]" +clk_mapped="clk_fm" # Remove previous designs -#rm -rf $verilog_output_dirpath/$verilog_output_dirname +rm -rf $verilog_output_dirpath/$verilog_output_dirname mkdir ${OpenFPGA_path}/fpga_flow/arch/generated -cd $fpga_flow_scripts +#cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path @@ -35,8 +39,14 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd $vpr_path # Run VPR -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator #--fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy +./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --nodisp cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path + +rm $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext} +perl rewrite_path_in_file.pl -i ${OpenFPGA_path}/ERI_demo/${benchmark}${tb_formal_ext} -o $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext} cd - + +sed -i 's/^clk\[0:0\]/clk_fm/' $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${formal_postfix}.v + diff --git a/ERI_demo/pipelined_1b_adder.act b/ERI_demo/pipelined_1b_adder.act deleted file mode 100644 index 4b048d367..000000000 --- a/ERI_demo/pipelined_1b_adder.act +++ /dev/null @@ -1,61 +0,0 @@ -clk 0.5 0.2 -wen 0.5 0.2 -wen_st0 0.5 0.2 -wen_st1 0.5 0.2 -ren 0.5 0.2 -raddr[0] 0.5 0.2 -raddr[1] 0.5 0.2 -raddr[2] 0.5 0.2 -raddr[3] 0.5 0.2 -raddr[4] 0.5 0.2 -raddr[5] 0.5 0.2 -raddr[6] 0.5 0.2 -raddr[7] 0.5 0.2 -raddr[8] 0.5 0.2 -raddr[9] 0.5 0.2 -raddr[10] 0.5 0.2 -waddr[0] 0.5 0.2 -waddr[1] 0.5 0.2 -waddr[2] 0.5 0.2 -waddr[3] 0.5 0.2 -waddr[4] 0.5 0.2 -waddr[5] 0.5 0.2 -waddr[6] 0.5 0.2 -waddr[7] 0.5 0.2 -waddr[8] 0.5 0.2 -waddr[9] 0.5 0.2 -waddr[10] 0.5 0.2 -waddr_st0[0] 0.5 0.2 -waddr_st0[1] 0.5 0.2 -waddr_st0[2] 0.5 0.2 -waddr_st0[3] 0.5 0.2 -waddr_st0[4] 0.5 0.2 -waddr_st0[5] 0.5 0.2 -waddr_st0[6] 0.5 0.2 -waddr_st0[7] 0.5 0.2 -waddr_st0[8] 0.5 0.2 -waddr_st0[9] 0.5 0.2 -waddr_st0[10] 0.5 0.2 -waddr_st1[0] 0.5 0.2 -waddr_st1[1] 0.5 0.2 -waddr_st1[2] 0.5 0.2 -waddr_st1[3] 0.5 0.2 -waddr_st1[4] 0.5 0.2 -waddr_st1[5] 0.5 0.2 -waddr_st1[6] 0.5 0.2 -waddr_st1[7] 0.5 0.2 -waddr_st1[8] 0.5 0.2 -waddr_st1[9] 0.5 0.2 -waddr_st1[10] 0.5 0.2 -a[0] 0.5 0.2 -a_st0[0] 0.5 0.2 -a_st1[0] 0.5 0.2 -b[0] 0.5 0.2 -b_st0[0] 0.5 0.2 -b_st1[0] 0.5 0.2 -q[0] 0.5 0.2 -q[1] 0.5 0.2 -AplusB[0] 0.5 0.2 -AplusB[1] 0.5 0.2 -cint01 0.5 0.2 -zero00 0 0 diff --git a/ERI_demo/pipelined_32b_adder.act b/ERI_demo/pipelined_32b_adder.act deleted file mode 100644 index 9093a7787..000000000 --- a/ERI_demo/pipelined_32b_adder.act +++ /dev/null @@ -1,331 +0,0 @@ -clk 0.5 0.2 -wen 0.5 0.2 -wen_st0 0.5 0.2 -wen_st1 0.5 0.2 -ren 0.5 0.2 -raddr[0] 0.5 0.2 -raddr[1] 0.5 0.2 -raddr[2] 0.5 0.2 -raddr[3] 0.5 0.2 -raddr[4] 0.5 0.2 -raddr[5] 0.5 0.2 -raddr[6] 0.5 0.2 -raddr[7] 0.5 0.2 -raddr[8] 0.5 0.2 -raddr[9] 0.5 0.2 -raddr[10] 0.5 0.2 -waddr[0] 0.5 0.2 -waddr[1] 0.5 0.2 -waddr[2] 0.5 0.2 -waddr[3] 0.5 0.2 -waddr[4] 0.5 0.2 -waddr[5] 0.5 0.2 -waddr[6] 0.5 0.2 -waddr[7] 0.5 0.2 -waddr[8] 0.5 0.2 -waddr[9] 0.5 0.2 -waddr[10] 0.5 0.2 -waddr_st0[0] 0.5 0.2 -waddr_st0[1] 0.5 0.2 -waddr_st0[2] 0.5 0.2 -waddr_st0[3] 0.5 0.2 -waddr_st0[4] 0.5 0.2 -waddr_st0[5] 0.5 0.2 -waddr_st0[6] 0.5 0.2 -waddr_st0[7] 0.5 0.2 -waddr_st0[8] 0.5 0.2 -waddr_st0[9] 0.5 0.2 -waddr_st0[10] 0.5 0.2 -waddr_st1[0] 0.5 0.2 -waddr_st1[1] 0.5 0.2 -waddr_st1[2] 0.5 0.2 -waddr_st1[3] 0.5 0.2 -waddr_st1[4] 0.5 0.2 -waddr_st1[5] 0.5 0.2 -waddr_st1[6] 0.5 0.2 -waddr_st1[7] 0.5 0.2 -waddr_st1[8] 0.5 0.2 -waddr_st1[9] 0.5 0.2 -waddr_st1[10] 0.5 0.2 -a[0] 0.5 0.2 -a[1] 0.5 0.2 -a[2] 0.5 0.2 -a[3] 0.5 0.2 -a[4] 0.5 0.2 -a[5] 0.5 0.2 -a[6] 0.5 0.2 -a[7] 0.5 0.2 -a[8] 0.5 0.2 -a[9] 0.5 0.2 -a[10] 0.5 0.2 -a[11] 0.5 0.2 -a[12] 0.5 0.2 -a[13] 0.5 0.2 -a[14] 0.5 0.2 -a[15] 0.5 0.2 -a[16] 0.5 0.2 -a[17] 0.5 0.2 -a[18] 0.5 0.2 -a[19] 0.5 0.2 -a[20] 0.5 0.2 -a[21] 0.5 0.2 -a[22] 0.5 0.2 -a[23] 0.5 0.2 -a[24] 0.5 0.2 -a[25] 0.5 0.2 -a[26] 0.5 0.2 -a[27] 0.5 0.2 -a[28] 0.5 0.2 -a[29] 0.5 0.2 -a[30] 0.5 0.2 -a_st0[0] 0.5 0.2 -a_st0[1] 0.5 0.2 -a_st0[2] 0.5 0.2 -a_st0[3] 0.5 0.2 -a_st0[4] 0.5 0.2 -a_st0[5] 0.5 0.2 -a_st0[6] 0.5 0.2 -a_st0[7] 0.5 0.2 -a_st0[8] 0.5 0.2 -a_st0[9] 0.5 0.2 -a_st0[10] 0.5 0.2 -a_st0[11] 0.5 0.2 -a_st0[12] 0.5 0.2 -a_st0[13] 0.5 0.2 -a_st0[14] 0.5 0.2 -a_st0[15] 0.5 0.2 -a_st0[16] 0.5 0.2 -a_st0[17] 0.5 0.2 -a_st0[18] 0.5 0.2 -a_st0[19] 0.5 0.2 -a_st0[20] 0.5 0.2 -a_st0[21] 0.5 0.2 -a_st0[22] 0.5 0.2 -a_st0[23] 0.5 0.2 -a_st0[24] 0.5 0.2 -a_st0[25] 0.5 0.2 -a_st0[26] 0.5 0.2 -a_st0[27] 0.5 0.2 -a_st0[28] 0.5 0.2 -a_st0[29] 0.5 0.2 -a_st0[30] 0.5 0.2 -a_st1[0] 0.5 0.2 -a_st1[1] 0.5 0.2 -a_st1[2] 0.5 0.2 -a_st1[3] 0.5 0.2 -a_st1[4] 0.5 0.2 -a_st1[5] 0.5 0.2 -a_st1[6] 0.5 0.2 -a_st1[7] 0.5 0.2 -a_st1[8] 0.5 0.2 -a_st1[9] 0.5 0.2 -a_st1[10] 0.5 0.2 -a_st1[11] 0.5 0.2 -a_st1[12] 0.5 0.2 -a_st1[13] 0.5 0.2 -a_st1[14] 0.5 0.2 -a_st1[15] 0.5 0.2 -a_st1[16] 0.5 0.2 -a_st1[17] 0.5 0.2 -a_st1[18] 0.5 0.2 -a_st1[19] 0.5 0.2 -a_st1[20] 0.5 0.2 -a_st1[21] 0.5 0.2 -a_st1[22] 0.5 0.2 -a_st1[23] 0.5 0.2 -a_st1[24] 0.5 0.2 -a_st1[25] 0.5 0.2 -a_st1[26] 0.5 0.2 -a_st1[27] 0.5 0.2 -a_st1[28] 0.5 0.2 -a_st1[29] 0.5 0.2 -a_st1[30] 0.5 0.2 -b[0] 0.5 0.2 -b[1] 0.5 0.2 -b[2] 0.5 0.2 -b[3] 0.5 0.2 -b[4] 0.5 0.2 -b[5] 0.5 0.2 -b[6] 0.5 0.2 -b[7] 0.5 0.2 -b[8] 0.5 0.2 -b[9] 0.5 0.2 -b[10] 0.5 0.2 -b[11] 0.5 0.2 -b[12] 0.5 0.2 -b[13] 0.5 0.2 -b[14] 0.5 0.2 -b[15] 0.5 0.2 -b[16] 0.5 0.2 -b[17] 0.5 0.2 -b[18] 0.5 0.2 -b[19] 0.5 0.2 -b[20] 0.5 0.2 -b[21] 0.5 0.2 -b[22] 0.5 0.2 -b[23] 0.5 0.2 -b[24] 0.5 0.2 -b[25] 0.5 0.2 -b[26] 0.5 0.2 -b[27] 0.5 0.2 -b[28] 0.5 0.2 -b[29] 0.5 0.2 -b[30] 0.5 0.2 -b_st0[0] 0.5 0.2 -b_st0[1] 0.5 0.2 -b_st0[2] 0.5 0.2 -b_st0[3] 0.5 0.2 -b_st0[4] 0.5 0.2 -b_st0[5] 0.5 0.2 -b_st0[6] 0.5 0.2 -b_st0[7] 0.5 0.2 -b_st0[8] 0.5 0.2 -b_st0[9] 0.5 0.2 -b_st0[10] 0.5 0.2 -b_st0[11] 0.5 0.2 -b_st0[12] 0.5 0.2 -b_st0[13] 0.5 0.2 -b_st0[14] 0.5 0.2 -b_st0[15] 0.5 0.2 -b_st0[16] 0.5 0.2 -b_st0[17] 0.5 0.2 -b_st0[18] 0.5 0.2 -b_st0[19] 0.5 0.2 -b_st0[20] 0.5 0.2 -b_st0[21] 0.5 0.2 -b_st0[22] 0.5 0.2 -b_st0[23] 0.5 0.2 -b_st0[24] 0.5 0.2 -b_st0[25] 0.5 0.2 -b_st0[26] 0.5 0.2 -b_st0[27] 0.5 0.2 -b_st0[28] 0.5 0.2 -b_st0[29] 0.5 0.2 -b_st0[30] 0.5 0.2 -b_st1[0] 0.5 0.2 -b_st1[1] 0.5 0.2 -b_st1[2] 0.5 0.2 -b_st1[3] 0.5 0.2 -b_st1[4] 0.5 0.2 -b_st1[5] 0.5 0.2 -b_st1[6] 0.5 0.2 -b_st1[7] 0.5 0.2 -b_st1[8] 0.5 0.2 -b_st1[9] 0.5 0.2 -b_st1[10] 0.5 0.2 -b_st1[11] 0.5 0.2 -b_st1[12] 0.5 0.2 -b_st1[13] 0.5 0.2 -b_st1[14] 0.5 0.2 -b_st1[15] 0.5 0.2 -b_st1[16] 0.5 0.2 -b_st1[17] 0.5 0.2 -b_st1[18] 0.5 0.2 -b_st1[19] 0.5 0.2 -b_st1[20] 0.5 0.2 -b_st1[21] 0.5 0.2 -b_st1[22] 0.5 0.2 -b_st1[23] 0.5 0.2 -b_st1[24] 0.5 0.2 -b_st1[25] 0.5 0.2 -b_st1[26] 0.5 0.2 -b_st1[27] 0.5 0.2 -b_st1[28] 0.5 0.2 -b_st1[29] 0.5 0.2 -b_st1[30] 0.5 0.2 -q[0] 0.5 0.2 -q[1] 0.5 0.2 -q[2] 0.5 0.2 -q[3] 0.5 0.2 -q[4] 0.5 0.2 -q[5] 0.5 0.2 -q[6] 0.5 0.2 -q[7] 0.5 0.2 -q[8] 0.5 0.2 -q[9] 0.5 0.2 -q[10] 0.5 0.2 -q[11] 0.5 0.2 -q[12] 0.5 0.2 -q[13] 0.5 0.2 -q[14] 0.5 0.2 -q[15] 0.5 0.2 -q[16] 0.5 0.2 -q[17] 0.5 0.2 -q[18] 0.5 0.2 -q[19] 0.5 0.2 -q[20] 0.5 0.2 -q[21] 0.5 0.2 -q[22] 0.5 0.2 -q[23] 0.5 0.2 -q[24] 0.5 0.2 -q[25] 0.5 0.2 -q[26] 0.5 0.2 -q[27] 0.5 0.2 -q[28] 0.5 0.2 -q[29] 0.5 0.2 -q[30] 0.5 0.2 -q[31] 0.5 0.2 -AplusB[0] 0.5 0.2 -AplusB[1] 0.5 0.2 -AplusB[2] 0.5 0.2 -AplusB[3] 0.5 0.2 -AplusB[4] 0.5 0.2 -AplusB[5] 0.5 0.2 -AplusB[6] 0.5 0.2 -AplusB[7] 0.5 0.2 -AplusB[8] 0.5 0.2 -AplusB[9] 0.5 0.2 -AplusB[10] 0.5 0.2 -AplusB[11] 0.5 0.2 -AplusB[12] 0.5 0.2 -AplusB[13] 0.5 0.2 -AplusB[14] 0.5 0.2 -AplusB[15] 0.5 0.2 -AplusB[16] 0.5 0.2 -AplusB[17] 0.5 0.2 -AplusB[18] 0.5 0.2 -AplusB[19] 0.5 0.2 -AplusB[20] 0.5 0.2 -AplusB[21] 0.5 0.2 -AplusB[22] 0.5 0.2 -AplusB[23] 0.5 0.2 -AplusB[24] 0.5 0.2 -AplusB[25] 0.5 0.2 -AplusB[26] 0.5 0.2 -AplusB[27] 0.5 0.2 -AplusB[28] 0.5 0.2 -AplusB[29] 0.5 0.2 -AplusB[30] 0.5 0.2 -AplusB[31] 0.5 0.2 -cint01 0.5 0.2 -cint02 0.5 0.2 -cint03 0.5 0.2 -cint04 0.5 0.2 -cint05 0.5 0.2 -cint06 0.5 0.2 -cint07 0.5 0.2 -cint08 0.5 0.2 -cint09 0.5 0.2 -cint10 0.5 0.2 -cint11 0.5 0.2 -cint12 0.5 0.2 -cint13 0.5 0.2 -cint14 0.5 0.2 -cint15 0.5 0.2 -cint16 0.5 0.2 -cint17 0.5 0.2 -cint18 0.5 0.2 -cint19 0.5 0.2 -cint20 0.5 0.2 -cint21 0.5 0.2 -cint22 0.5 0.2 -cint23 0.5 0.2 -cint24 0.5 0.2 -cint25 0.5 0.2 -cint26 0.5 0.2 -cint27 0.5 0.2 -cint28 0.5 0.2 -cint29 0.5 0.2 -cint30 0.5 0.2 -cint31 0.5 0.2 -zero00 0 0 diff --git a/ERI_demo/pipelined_32b_adder.blif b/ERI_demo/pipelined_32b_adder.blif deleted file mode 100644 index 8c8b3c408..000000000 --- a/ERI_demo/pipelined_32b_adder.blif +++ /dev/null @@ -1,278 +0,0 @@ -# Benchmark pipelined_32b_adder -.model pipelined_32b_adder -.inputs clk wen ren \ - raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \ - waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] \ - a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] \ - a[11] a[12] a[13] a[14] a[15] a[16] a[17] a[18] a[19] a[20] \ - a[21] a[22] a[23] a[24] a[25] a[26] a[27] a[28] a[29] a[30] \ - b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] \ - b[11] b[12] b[13] b[14] b[15] b[16] b[17] b[18] b[19] b[20] \ - b[21] b[22] b[23] b[24] b[25] b[26] b[27] b[28] b[29] b[30] -.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7] q[8] q[9] q[10] \ - q[11] q[12] q[13] q[14] q[15] q[16] q[17] q[18] q[19] q[20] \ - q[21] q[22] q[23] q[24] q[25] q[26] q[27] q[28] q[29] q[30] q[31] - -# Start pipeline -# Pipeline a -.subckt shift D=a[0] clk=clk Q=a_st0[0] -.subckt shift D=a_st0[0] clk=clk Q=a_st1[0] -.subckt shift D=a[1] clk=clk Q=a_st0[1] -.subckt shift D=a_st0[1] clk=clk Q=a_st1[1] -.subckt shift D=a[2] clk=clk Q=a_st0[2] -.subckt shift D=a_st0[2] clk=clk Q=a_st1[2] -.subckt shift D=a[3] clk=clk Q=a_st0[3] -.subckt shift D=a_st0[3] clk=clk Q=a_st1[3] -.subckt shift D=a[4] clk=clk Q=a_st0[4] -.subckt shift D=a_st0[4] clk=clk Q=a_st1[4] -.subckt shift D=a[5] clk=clk Q=a_st0[5] -.subckt shift D=a_st0[5] clk=clk Q=a_st1[5] -.subckt shift D=a[6] clk=clk Q=a_st0[6] -.subckt shift D=a_st0[6] clk=clk Q=a_st1[6] -.subckt shift D=a[7] clk=clk Q=a_st0[7] -.subckt shift D=a_st0[7] clk=clk Q=a_st1[7] -.subckt shift D=a[8] clk=clk Q=a_st0[8] -.subckt shift D=a_st0[8] clk=clk Q=a_st1[8] -.subckt shift D=a[9] clk=clk Q=a_st0[9] -.subckt shift D=a_st0[9] clk=clk Q=a_st1[9] -.subckt shift D=a[10] clk=clk Q=a_st0[10] -.subckt shift D=a_st0[10] clk=clk Q=a_st1[10] -.subckt shift D=a[11] clk=clk Q=a_st0[11] -.subckt shift D=a_st0[11] clk=clk Q=a_st1[11] -.subckt shift D=a[12] clk=clk Q=a_st0[12] -.subckt shift D=a_st0[12] clk=clk Q=a_st1[12] -.subckt shift D=a[13] clk=clk Q=a_st0[13] -.subckt shift D=a_st0[13] clk=clk Q=a_st1[13] -.subckt shift D=a[14] clk=clk Q=a_st0[14] -.subckt shift D=a_st0[14] clk=clk Q=a_st1[14] -.subckt shift D=a[15] clk=clk Q=a_st0[15] -.subckt shift D=a_st0[15] clk=clk Q=a_st1[15] -.subckt shift D=a[16] clk=clk Q=a_st0[16] -.subckt shift D=a_st0[16] clk=clk Q=a_st1[16] -.subckt shift D=a[17] clk=clk Q=a_st0[17] -.subckt shift D=a_st0[17] clk=clk Q=a_st1[17] -.subckt shift D=a[18] clk=clk Q=a_st0[18] -.subckt shift D=a_st0[18] clk=clk Q=a_st1[18] -.subckt shift D=a[19] clk=clk Q=a_st0[19] -.subckt shift D=a_st0[19] clk=clk Q=a_st1[19] -.subckt shift D=a[20] clk=clk Q=a_st0[20] -.subckt shift D=a_st0[20] clk=clk Q=a_st1[20] -.subckt shift D=a[21] clk=clk Q=a_st0[21] -.subckt shift D=a_st0[21] clk=clk Q=a_st1[21] -.subckt shift D=a[22] clk=clk Q=a_st0[22] -.subckt shift D=a_st0[22] clk=clk Q=a_st1[22] -.subckt shift D=a[23] clk=clk Q=a_st0[23] -.subckt shift D=a_st0[23] clk=clk Q=a_st1[23] -.subckt shift D=a[24] clk=clk Q=a_st0[24] -.subckt shift D=a_st0[24] clk=clk Q=a_st1[24] -.subckt shift D=a[25] clk=clk Q=a_st0[25] -.subckt shift D=a_st0[25] clk=clk Q=a_st1[25] -.subckt shift D=a[26] clk=clk Q=a_st0[26] -.subckt shift D=a_st0[26] clk=clk Q=a_st1[26] -.subckt shift D=a[27] clk=clk Q=a_st0[27] -.subckt shift D=a_st0[27] clk=clk Q=a_st1[27] -.subckt shift D=a[28] clk=clk Q=a_st0[28] -.subckt shift D=a_st0[28] clk=clk Q=a_st1[28] -.subckt shift D=a[29] clk=clk Q=a_st0[29] -.subckt shift D=a_st0[29] clk=clk Q=a_st1[29] -.subckt shift D=a[30] clk=clk Q=a_st0[30] -.subckt shift D=a_st0[30] clk=clk Q=a_st1[30] - -# Pipeline b -.subckt shift D=b[0] clk=clk Q=b_st0[0] -.subckt shift D=b_st0[0] clk=clk Q=b_st1[0] -.subckt shift D=b[1] clk=clk Q=b_st0[1] -.subckt shift D=b_st0[1] clk=clk Q=b_st1[1] -.subckt shift D=b[2] clk=clk Q=b_st0[2] -.subckt shift D=b_st0[2] clk=clk Q=b_st1[2] -.subckt shift D=b[3] clk=clk Q=b_st0[3] -.subckt shift D=b_st0[3] clk=clk Q=b_st1[3] -.subckt shift D=b[4] clk=clk Q=b_st0[4] -.subckt shift D=b_st0[4] clk=clk Q=b_st1[4] -.subckt shift D=b[5] clk=clk Q=b_st0[5] -.subckt shift D=b_st0[5] clk=clk Q=b_st1[5] -.subckt shift D=b[6] clk=clk Q=b_st0[6] -.subckt shift D=b_st0[6] clk=clk Q=b_st1[6] -.subckt shift D=b[7] clk=clk Q=b_st0[7] -.subckt shift D=b_st0[7] clk=clk Q=b_st1[7] -.subckt shift D=b[8] clk=clk Q=b_st0[8] -.subckt shift D=b_st0[8] clk=clk Q=b_st1[8] -.subckt shift D=b[9] clk=clk Q=b_st0[9] -.subckt shift D=b_st0[9] clk=clk Q=b_st1[9] -.subckt shift D=b[10] clk=clk Q=b_st0[10] -.subckt shift D=b_st0[10] clk=clk Q=b_st1[10] -.subckt shift D=b[11] clk=clk Q=b_st0[11] -.subckt shift D=b_st0[11] clk=clk Q=b_st1[11] -.subckt shift D=b[12] clk=clk Q=b_st0[12] -.subckt shift D=b_st0[12] clk=clk Q=b_st1[12] -.subckt shift D=b[13] clk=clk Q=b_st0[13] -.subckt shift D=b_st0[13] clk=clk Q=b_st1[13] -.subckt shift D=b[14] clk=clk Q=b_st0[14] -.subckt shift D=b_st0[14] clk=clk Q=b_st1[14] -.subckt shift D=b[15] clk=clk Q=b_st0[15] -.subckt shift D=b_st0[15] clk=clk Q=b_st1[15] -.subckt shift D=b[16] clk=clk Q=b_st0[16] -.subckt shift D=b_st0[16] clk=clk Q=b_st1[16] -.subckt shift D=b[17] clk=clk Q=b_st0[17] -.subckt shift D=b_st0[17] clk=clk Q=b_st1[17] -.subckt shift D=b[18] clk=clk Q=b_st0[18] -.subckt shift D=b_st0[18] clk=clk Q=b_st1[18] -.subckt shift D=b[19] clk=clk Q=b_st0[19] -.subckt shift D=b_st0[19] clk=clk Q=b_st1[19] -.subckt shift D=b[20] clk=clk Q=b_st0[20] -.subckt shift D=b_st0[20] clk=clk Q=b_st1[20] -.subckt shift D=b[21] clk=clk Q=b_st0[21] -.subckt shift D=b_st0[21] clk=clk Q=b_st1[21] -.subckt shift D=b[22] clk=clk Q=b_st0[22] -.subckt shift D=b_st0[22] clk=clk Q=b_st1[22] -.subckt shift D=b[23] clk=clk Q=b_st0[23] -.subckt shift D=b_st0[23] clk=clk Q=b_st1[23] -.subckt shift D=b[24] clk=clk Q=b_st0[24] -.subckt shift D=b_st0[24] clk=clk Q=b_st1[24] -.subckt shift D=b[25] clk=clk Q=b_st0[25] -.subckt shift D=b_st0[25] clk=clk Q=b_st1[25] -.subckt shift D=b[26] clk=clk Q=b_st0[26] -.subckt shift D=b_st0[26] clk=clk Q=b_st1[26] -.subckt shift D=b[27] clk=clk Q=b_st0[27] -.subckt shift D=b_st0[27] clk=clk Q=b_st1[27] -.subckt shift D=b[28] clk=clk Q=b_st0[28] -.subckt shift D=b_st0[28] clk=clk Q=b_st1[28] -.subckt shift D=b[29] clk=clk Q=b_st0[29] -.subckt shift D=b_st0[29] clk=clk Q=b_st1[29] -.subckt shift D=b[30] clk=clk Q=b_st0[30] -.subckt shift D=b_st0[30] clk=clk Q=b_st1[30] - -# Pipeline waddr -.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0] -.subckt shift D=waddr_st0[0] clk=clk Q=waddr_st1[0] -.subckt shift D=waddr[1] clk=clk Q=waddr_st0[1] -.subckt shift D=waddr_st0[1] clk=clk Q=waddr_st1[1] -.subckt shift D=waddr[2] clk=clk Q=waddr_st0[2] -.subckt shift D=waddr_st0[2] clk=clk Q=waddr_st1[2] -.subckt shift D=waddr[3] clk=clk Q=waddr_st0[3] -.subckt shift D=waddr_st0[3] clk=clk Q=waddr_st1[3] -.subckt shift D=waddr[4] clk=clk Q=waddr_st0[4] -.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4] -.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5] -.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5] -.subckt shift D=waddr[6] clk=clk Q=waddr_st0[6] -.subckt shift D=waddr_st0[6] clk=clk Q=waddr_st1[6] -.subckt shift D=waddr[7] clk=clk Q=waddr_st0[7] -.subckt shift D=waddr_st0[7] clk=clk Q=waddr_st1[7] -.subckt shift D=waddr[8] clk=clk Q=waddr_st0[8] -.subckt shift D=waddr_st0[8] clk=clk Q=waddr_st1[8] -.subckt shift D=waddr[9] clk=clk Q=waddr_st0[9] -.subckt shift D=waddr_st0[9] clk=clk Q=waddr_st1[9] -.subckt shift D=waddr[10] clk=clk Q=waddr_st0[10] -.subckt shift D=waddr_st0[10] clk=clk Q=waddr_st1[10] - -# Pipeline wen -.subckt shift D=wen clk=clk Q=wen_st0 -.subckt shift D=wen_st0 clk=clk Q=wen_st1 -# End pipeline - -# Start adder -.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0] -.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1] -.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2] -.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3] -.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4] -.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5] -.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6] -.subckt adder a=a_st1[7] b=b_st1[7] cin=cint07 cout=cint08 sumout=AplusB[7] -.subckt adder a=a_st1[8] b=b_st1[8] cin=cint08 cout=cint09 sumout=AplusB[8] -.subckt adder a=a_st1[9] b=b_st1[9] cin=cint09 cout=cint10 sumout=AplusB[9] -.subckt adder a=a_st1[10] b=b_st1[10] cin=cint10 cout=cint11 sumout=AplusB[10] -.subckt adder a=a_st1[11] b=b_st1[11] cin=cint11 cout=cint12 sumout=AplusB[11] -.subckt adder a=a_st1[12] b=b_st1[12] cin=cint12 cout=cint13 sumout=AplusB[12] -.subckt adder a=a_st1[13] b=b_st1[13] cin=cint13 cout=cint14 sumout=AplusB[13] -.subckt adder a=a_st1[14] b=b_st1[14] cin=cint14 cout=cint15 sumout=AplusB[14] -.subckt adder a=a_st1[15] b=b_st1[15] cin=cint15 cout=cint16 sumout=AplusB[15] -.subckt adder a=a_st1[16] b=b_st1[16] cin=cint16 cout=cint17 sumout=AplusB[16] -.subckt adder a=a_st1[17] b=b_st1[17] cin=cint17 cout=cint18 sumout=AplusB[17] -.subckt adder a=a_st1[18] b=b_st1[18] cin=cint18 cout=cint19 sumout=AplusB[18] -.subckt adder a=a_st1[19] b=b_st1[19] cin=cint19 cout=cint20 sumout=AplusB[19] -.subckt adder a=a_st1[20] b=b_st1[20] cin=cint20 cout=cint21 sumout=AplusB[20] -.subckt adder a=a_st1[21] b=b_st1[21] cin=cint21 cout=cint22 sumout=AplusB[21] -.subckt adder a=a_st1[22] b=b_st1[22] cin=cint22 cout=cint23 sumout=AplusB[22] -.subckt adder a=a_st1[23] b=b_st1[23] cin=cint23 cout=cint24 sumout=AplusB[23] -.subckt adder a=a_st1[24] b=b_st1[24] cin=cint24 cout=cint25 sumout=AplusB[24] -.subckt adder a=a_st1[25] b=b_st1[25] cin=cint25 cout=cint26 sumout=AplusB[25] -.subckt adder a=a_st1[26] b=b_st1[26] cin=cint26 cout=cint27 sumout=AplusB[26] -.subckt adder a=a_st1[27] b=b_st1[27] cin=cint27 cout=cint28 sumout=AplusB[27] -.subckt adder a=a_st1[28] b=b_st1[28] cin=cint28 cout=cint29 sumout=AplusB[28] -.subckt adder a=a_st1[29] b=b_st1[29] cin=cint29 cout=cint30 sumout=AplusB[29] -.subckt adder a=a_st1[30] b=b_st1[30] cin=cint30 cout=cint31 sumout=AplusB[30] -.subckt adder a=zero00 b=zero00 cin=cint31 cout=unconn sumout=AplusB[31] -# End adder - -# Start DPRAM -.subckt dpram clk=clk wen=wen_st1 ren=ren \ -waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \ -waddr[5]=waddr_st1[5] waddr[6]=waddr_st1[6] waddr[7]=waddr_st1[7] waddr[8]=waddr_st1[8] waddr[9]=waddr_st1[9] waddr[10]==waddr_st1[10] \ -raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \ -raddr[6]=raddr[6] raddr[7]=raddr[7] raddr[8]=raddr[8] raddr[9]=raddr[9] raddr[10]=raddr[10] \ -d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \ -d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=AplusB[8] d_in[9]=AplusB[9] d_in[10]=AplusB[10] d_in[11]=AplusB[11] \ -d_in[12]=AplusB[12] d_in[13]=AplusB[13] d_in[14]=AplusB[14] d_in[15]=AplusB[15] d_in[16]=AplusB[16] d_in[17]=AplusB[17] \ -d_in[18]=AplusB[18] d_in[19]=AplusB[19] d_in[20]=AplusB[20] d_in[21]=AplusB[21] d_in[22]=AplusB[22] d_in[23]=AplusB[23] \ -d_in[24]=AplusB[24] d_in[25]=AplusB[25] d_in[26]=AplusB[26] d_in[27]=AplusB[27] d_in[28]=AplusB[28] d_in[29]=AplusB[29] \ -d_in[30]=AplusB[30] d_in[31]=AplusB[31] \ -d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \ -d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \ -d_out[6]=q[6] d_out[7]=q[7] d_out[8]=q[8] d_out[9]=q[9] d_out[10]=q[10] \ -d_out[11]=q[11] d_out[12]=q[12] d_out[13]=q[13] d_out[14]=q[14] d_out[15]=q[15] \ -d_out[16]=q[16] d_out[17]=q[17] d_out[18]=q[18] d_out[19]=q[19] d_out[20]=q[20] \ -d_out[21]=q[21] d_out[22]=q[22] d_out[23]=q[23] d_out[24]=q[24] d_out[25]=q[25] \ -d_out[26]=q[26] d_out[27]=q[27] d_out[28]=q[28] d_out[29]=q[29] d_out[30]=q[30] d_out[31]=q[31] \ -d_out[32]=unconn d_out[33]=unconn d_out[34]=unconn d_out[35]=unconn d_out[36]=unconn d_out[37]=unconn d_out[38]=unconn d_out[39]=unconn d_out[40]=unconn d_out[41]=unconn d_out[42]=unconn d_out[43]=unconn d_out[44]=unconn d_out[45]=unconn d_out[46]=unconn d_out[47]=unconn d_out[48]=unconn d_out[49]=unconn d_out[50]=unconn d_out[51]=unconn d_out[52]=unconn d_out[53]=unconn d_out[54]=unconn d_out[55]=unconn d_out[56]=unconn d_out[57]=unconn d_out[58]=unconn d_out[59]=unconn d_out[60]=unconn d_out[61]=unconn d_out[62]=unconn d_out[63]=unconn -# End DPRAM - -# Start global variable -.names zero00 -0 -# End global variable - - -.end - -# Start blackbox definition -.model dpram -.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \ - waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] raddr[0] raddr[1] raddr[2] \ - raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \ - d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \ - d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \ - d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \ - d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] d_in[32] \ - d_in[33] d_in[34] d_in[35] d_in[36] d_in[37] d_in[38] d_in[39] d_in[40] \ - d_in[41] d_in[42] d_in[43] d_in[44] d_in[45] d_in[46] d_in[47] d_in[48] \ - d_in[49] d_in[50] d_in[51] d_in[52] d_in[53] d_in[54] d_in[55] d_in[56] \ - d_in[57] d_in[58] d_in[59] d_in[60] d_in[61] d_in[62] d_in[63] -.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \ - d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \ - d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \ - d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \ - d_out[28] d_out[29] d_out[30] d_out[31] d_out[32] d_out[33] d_out[34] \ - d_out[35] d_out[36] d_out[37] d_out[38] d_out[39] d_out[40] d_out[41] \ - d_out[42] d_out[43] d_out[44] d_out[45] d_out[46] d_out[47] d_out[48] \ - d_out[49] d_out[50] d_out[51] d_out[52] d_out[53] d_out[54] d_out[55] \ - d_out[56] d_out[57] d_out[58] d_out[59] d_out[60] d_out[61] d_out[62] \ - d_out[63] -.blackbox -.end - - -.model adder -.inputs a b cin -.outputs cout sumout -.blackbox -.end - - -.model shift -.inputs D clk -.outputs Q -.blackbox -.end -# End blackbox definition diff --git a/ERI_demo/pipelined_32b_adder_ERI_demo_tb.v b/ERI_demo/pipelined_32b_adder_ERI_demo_tb.v deleted file mode 100644 index 06f1f77a1..000000000 --- a/ERI_demo/pipelined_32b_adder_ERI_demo_tb.v +++ /dev/null @@ -1,156 +0,0 @@ -///////////////////////////////////// -// // -// ERI summit demo-benchmark // -// pipelined_32b_adder_tb // -// by Aurelien // -// // -///////////////////////////////////// - -`timescale 1 ns/ 1 ps - -module pipelined_32b_adder_ERI_demo_tb(); - reg clk; - reg[10:0] raddr; - reg[10:0] waddr; - reg ren; - reg wen; - reg[30:0] a; - reg[30:0] b; - wire[31:0] q_gfpga; - wire[31:0] q_bench; - reg[31:0] q_flag; - - pipelined_32b_adder_top_formal_verification DUT( - .clk_fm (clk), - .raddr_0_fm (raddr[0]), - .raddr_1_fm (raddr[1]), - .raddr_2_fm (raddr[2]), - .raddr_3_fm (raddr[3]), - .raddr_4_fm (raddr[4]), - .raddr_5_fm (raddr[5]), - .raddr_6_fm (raddr[6]), - .raddr_7_fm (raddr[7]), - .raddr_8_fm (raddr[8]), - .raddr_9_fm (raddr[9]), - .raddr_10_fm (raddr[10]), - .waddr_0_fm (waddr[0]), - .waddr_1_fm (waddr[1]), - .waddr_2_fm (waddr[2]), - .waddr_3_fm (waddr[3]), - .waddr_4_fm (waddr[4]), - .waddr_5_fm (waddr[5]), - .waddr_6_fm (waddr[6]), - .waddr_7_fm (waddr[7]), - .waddr_8_fm (waddr[8]), - .waddr_9_fm (waddr[9]), - .waddr_10_fm (waddr[10]), - .ren_fm (ren), - .wen_fm (wen), - .a_0_fm (a[0]), - .a_1_fm (a[1]), - .a_2_fm (a[2]), - .a_3_fm (a[3]), - .a_4_fm (a[4]), - .a_5_fm (a[5]), - .a_6_fm (a[6]), - .a_7_fm (a[7]), - .a_8_fm (a[8]), - .a_9_fm (a[9]), - .a_10_fm (a[10]), - .a_11_fm (a[11]), - .a_12_fm (a[12]), - .a_13_fm (a[13]), - .a_14_fm (a[14]), - .a_15_fm (a[15]), - .a_16_fm (a[16]), - .a_17_fm (a[17]), - .a_18_fm (a[18]), - .a_19_fm (a[19]), - .a_20_fm (a[20]), - .a_21_fm (a[21]), - .a_22_fm (a[22]), - .a_23_fm (a[23]), - .a_24_fm (a[24]), - .a_25_fm (a[25]), - .a_26_fm (a[26]), - .a_27_fm (a[27]), - .a_28_fm (a[28]), - .a_29_fm (a[29]), - .a_30_fm (a[30]), - .b_0_fm (b[0]), - .b_1_fm (b[1]), - .b_2_fm (b[2]), - .b_3_fm (b[3]), - .b_4_fm (b[4]), - .b_5_fm (b[5]), - .b_6_fm (b[6]), - .b_7_fm (b[7]), - .b_8_fm (b[8]), - .b_9_fm (b[9]), - .b_10_fm (b[10]), - .b_11_fm (b[11]), - .b_12_fm (b[12]), - .b_13_fm (b[13]), - .b_14_fm (b[14]), - .b_15_fm (b[15]), - .b_16_fm (b[16]), - .b_17_fm (b[17]), - .b_18_fm (b[18]), - .b_19_fm (b[19]), - .b_20_fm (b[20]), - .b_21_fm (b[21]), - .b_22_fm (b[22]), - .b_23_fm (b[23]), - .b_24_fm (b[24]), - .b_25_fm (b[25]), - .b_26_fm (b[26]), - .b_27_fm (b[27]), - .b_28_fm (b[28]), - .b_29_fm (b[29]), - .b_30_fm (b[30]), - .out_q_0_fm (q_gfpga[0]), - .out_q_1_fm (q_gfpga[1]), - .out_q_2_fm (q_gfpga[2]), - .out_q_3_fm (q_gfpga[3]), - .out_q_4_fm (q_gfpga[4]), - .out_q_5_fm (q_gfpga[5]), - .out_q_6_fm (q_gfpga[6]), - .out_q_7_fm (q_gfpga[7]), - .out_q_8_fm (q_gfpga[8]), - .out_q_9_fm (q_gfpga[9]), - .out_q_10_fm (q_gfpga[10]), - .out_q_11_fm (q_gfpga[11]), - .out_q_12_fm (q_gfpga[12]), - .out_q_13_fm (q_gfpga[13]), - .out_q_14_fm (q_gfpga[14]), - .out_q_15_fm (q_gfpga[15]), - .out_q_16_fm (q_gfpga[16]), - .out_q_17_fm (q_gfpga[17]), - .out_q_18_fm (q_gfpga[18]), - .out_q_19_fm (q_gfpga[19]), - .out_q_20_fm (q_gfpga[20]), - .out_q_21_fm (q_gfpga[21]), - .out_q_22_fm (q_gfpga[22]), - .out_q_23_fm (q_gfpga[23]), - .out_q_24_fm (q_gfpga[24]), - .out_q_25_fm (q_gfpga[25]), - .out_q_26_fm (q_gfpga[26]), - .out_q_27_fm (q_gfpga[27]), - .out_q_28_fm (q_gfpga[28]), - .out_q_29_fm (q_gfpga[29]), - .out_q_30_fm (q_gfpga[30]), - .out_q_31_fm (q_gfpga[31]) - ); - - pipelined_32b_adder ref0( - .clk (clk), - .raddr (raddr), - .waddr (waddr), - .ren (ren), - .wen (wen), - .a (a), - .b (b), - .q (q_bench) - ); - -endmodule : pipelined_32b_adder_ERI_demo_tb \ No newline at end of file diff --git a/ERI_demo/pipelined_8b_adder.act b/ERI_demo/pipelined_8b_adder.act new file mode 100644 index 000000000..c7a502a2d --- /dev/null +++ b/ERI_demo/pipelined_8b_adder.act @@ -0,0 +1,95 @@ +clk 0.5 0.2 +wen 0.5 0.2 +wen_st0 0.5 0.2 +wen_st1 0.5 0.2 +ren 0.5 0.2 +raddr[0] 0.5 0.2 +raddr[1] 0.5 0.2 +raddr[2] 0.5 0.2 +raddr[3] 0.5 0.2 +raddr[4] 0.5 0.2 +raddr[5] 0.5 0.2 +waddr[0] 0.5 0.2 +waddr[1] 0.5 0.2 +waddr[2] 0.5 0.2 +waddr[3] 0.5 0.2 +waddr[4] 0.5 0.2 +waddr[5] 0.5 0.2 +waddr_st0[0] 0.5 0.2 +waddr_st0[1] 0.5 0.2 +waddr_st0[2] 0.5 0.2 +waddr_st0[3] 0.5 0.2 +waddr_st0[4] 0.5 0.2 +waddr_st0[5] 0.5 0.2 +waddr_st1[0] 0.5 0.2 +waddr_st1[1] 0.5 0.2 +waddr_st1[2] 0.5 0.2 +waddr_st1[3] 0.5 0.2 +waddr_st1[4] 0.5 0.2 +waddr_st1[5] 0.5 0.2 +a[0] 0.5 0.2 +a[1] 0.5 0.2 +a[2] 0.5 0.2 +a[3] 0.5 0.2 +a[4] 0.5 0.2 +a[5] 0.5 0.2 +a[6] 0.5 0.2 +a_st0[0] 0.5 0.2 +a_st0[1] 0.5 0.2 +a_st0[2] 0.5 0.2 +a_st0[3] 0.5 0.2 +a_st0[4] 0.5 0.2 +a_st0[5] 0.5 0.2 +a_st0[6] 0.5 0.2 +a_st1[0] 0.5 0.2 +a_st1[1] 0.5 0.2 +a_st1[2] 0.5 0.2 +a_st1[3] 0.5 0.2 +a_st1[4] 0.5 0.2 +a_st1[5] 0.5 0.2 +a_st1[6] 0.5 0.2 +b[0] 0.5 0.2 +b[1] 0.5 0.2 +b[2] 0.5 0.2 +b[3] 0.5 0.2 +b[4] 0.5 0.2 +b[5] 0.5 0.2 +b[6] 0.5 0.2 +b_st0[0] 0.5 0.2 +b_st0[1] 0.5 0.2 +b_st0[2] 0.5 0.2 +b_st0[3] 0.5 0.2 +b_st0[4] 0.5 0.2 +b_st0[5] 0.5 0.2 +b_st0[6] 0.5 0.2 +b_st1[0] 0.5 0.2 +b_st1[1] 0.5 0.2 +b_st1[2] 0.5 0.2 +b_st1[3] 0.5 0.2 +b_st1[4] 0.5 0.2 +b_st1[5] 0.5 0.2 +b_st1[6] 0.5 0.2 +q[0] 0.5 0.2 +q[1] 0.5 0.2 +q[2] 0.5 0.2 +q[3] 0.5 0.2 +q[4] 0.5 0.2 +q[5] 0.5 0.2 +q[6] 0.5 0.2 +q[7] 0.5 0.2 +AplusB[0] 0.5 0.2 +AplusB[1] 0.5 0.2 +AplusB[2] 0.5 0.2 +AplusB[3] 0.5 0.2 +AplusB[4] 0.5 0.2 +AplusB[5] 0.5 0.2 +AplusB[6] 0.5 0.2 +AplusB[7] 0.5 0.2 +cint01 0.5 0.2 +cint02 0.5 0.2 +cint03 0.5 0.2 +cint04 0.5 0.2 +cint05 0.5 0.2 +cint06 0.5 0.2 +cint07 0.5 0.2 +zero00 0 0 diff --git a/ERI_demo/pipelined_1b_adder.blif b/ERI_demo/pipelined_8b_adder.blif similarity index 65% rename from ERI_demo/pipelined_1b_adder.blif rename to ERI_demo/pipelined_8b_adder.blif index 447de5fa7..7f47b1661 100644 --- a/ERI_demo/pipelined_1b_adder.blif +++ b/ERI_demo/pipelined_8b_adder.blif @@ -1,50 +1,40 @@ # Benchmark pipelined_32b_adder .model pipelined_32b_adder -.inputs clk wen ren \ - raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \ - waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] \ - a[0] b[0] -.outputs q[0] q[1] - -# Pipeline with #.latch -#.latch a[0] a_st0[0] re clk 0 -#.latch a_st0[0] a_st1[0] re clk 0 -#.latch b[0] b_st0[0] re clk 0 -#.latch b_st0[0] b_st1[0] re clk 0 -#.latch wen wen_st0 re clk 0 -#.latch wen_st0 wen_st1 re clk 0 -#.latch waddr[0] waddr_st0[0] re clk 0 -#.latch waddr_st0[0] waddr_st1[0] re clk 0 -#.latch waddr[1] waddr_st0[1] re clk 0 -#.latch waddr_st0[1] waddr_st1[1] re clk 0 -#.latch waddr[2] waddr_st0[2] re clk 0 -#.latch waddr_st0[2] waddr_st1[2] re clk 0 -#.latch waddr[3] waddr_st0[3] re clk 0 -#.latch waddr_st0[3] waddr_st1[3] re clk 0 -#.latch waddr[4] waddr_st0[4] re clk 0 -#.latch waddr_st0[4] waddr_st1[4] re clk 0 -#.latch waddr[5] waddr_st0[5] re clk 0 -#.latch waddr_st0[5] waddr_st1[5] re clk 0 -#.latch waddr[6] waddr_st0[6] re clk 0 -#.latch waddr_st0[6] waddr_st1[6] re clk 0 -#.latch waddr[7] waddr_st0[7] re clk 0 -#.latch waddr_st0[7] waddr_st1[7] re clk 0 -#.latch waddr[8] waddr_st0[8] re clk 0 -#.latch waddr_st0[8] waddr_st1[8] re clk 0 -#.latch waddr[9] waddr_st0[9] re clk 0 -#.latch waddr_st0[9] waddr_st1[9] re clk 0 -#.latch waddr[10] waddr_st0[10] re clk 0 -#.latch waddr_st0[10] waddr_st1[10] re clk 0 -# End pipeline with #.latch +.inputs clk wen ren raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] a[0] a[1] a[2] a[3] a[4] a[5] a[6] b[0] b[1] b[2] b[3] b[4] b[5] b[6] +.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7] # Start pipeline # Pipeline a .subckt shift D=a[0] clk=clk Q=a_st0[0] .subckt shift D=a_st0[0] clk=clk Q=a_st1[0] +.subckt shift D=a[1] clk=clk Q=a_st0[1] +.subckt shift D=a_st0[1] clk=clk Q=a_st1[1] +.subckt shift D=a[2] clk=clk Q=a_st0[2] +.subckt shift D=a_st0[2] clk=clk Q=a_st1[2] +.subckt shift D=a[3] clk=clk Q=a_st0[3] +.subckt shift D=a_st0[3] clk=clk Q=a_st1[3] +.subckt shift D=a[4] clk=clk Q=a_st0[4] +.subckt shift D=a_st0[4] clk=clk Q=a_st1[4] +.subckt shift D=a[5] clk=clk Q=a_st0[5] +.subckt shift D=a_st0[5] clk=clk Q=a_st1[5] +.subckt shift D=a[6] clk=clk Q=a_st0[6] +.subckt shift D=a_st0[6] clk=clk Q=a_st1[6] # Pipeline b .subckt shift D=b[0] clk=clk Q=b_st0[0] .subckt shift D=b_st0[0] clk=clk Q=b_st1[0] +.subckt shift D=b[1] clk=clk Q=b_st0[1] +.subckt shift D=b_st0[1] clk=clk Q=b_st1[1] +.subckt shift D=b[2] clk=clk Q=b_st0[2] +.subckt shift D=b_st0[2] clk=clk Q=b_st1[2] +.subckt shift D=b[3] clk=clk Q=b_st0[3] +.subckt shift D=b_st0[3] clk=clk Q=b_st1[3] +.subckt shift D=b[4] clk=clk Q=b_st0[4] +.subckt shift D=b_st0[4] clk=clk Q=b_st1[4] +.subckt shift D=b[5] clk=clk Q=b_st0[5] +.subckt shift D=b_st0[5] clk=clk Q=b_st1[5] +.subckt shift D=b[6] clk=clk Q=b_st0[6] +.subckt shift D=b_st0[6] clk=clk Q=b_st1[6] # Pipeline waddr .subckt shift D=waddr[0] clk=clk Q=waddr_st0[0] @@ -59,17 +49,6 @@ .subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4] .subckt shift D=waddr[5] clk=clk Q=waddr_st0[5] .subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5] -.subckt shift D=waddr[6] clk=clk Q=waddr_st0[6] -.subckt shift D=waddr_st0[6] clk=clk Q=waddr_st1[6] -.subckt shift D=waddr[7] clk=clk Q=waddr_st0[7] -.subckt shift D=waddr_st0[7] clk=clk Q=waddr_st1[7] -.subckt shift D=waddr[8] clk=clk Q=waddr_st0[8] -.subckt shift D=waddr_st0[8] clk=clk Q=waddr_st1[8] -.subckt shift D=waddr[9] clk=clk Q=waddr_st0[9] -.subckt shift D=waddr_st0[9] clk=clk Q=waddr_st1[9] -.subckt shift D=waddr[10] clk=clk Q=waddr_st0[10] -.subckt shift D=waddr_st0[10] clk=clk Q=waddr_st1[10] - # Pipeline wen .subckt shift D=wen clk=clk Q=wen_st0 .subckt shift D=wen_st0 clk=clk Q=wen_st1 @@ -77,24 +56,30 @@ # Start adder .subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0] -.subckt adder a=zero00 b=zero00 cin=cint01 cout=unconn sumout=AplusB[1] +.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1] +.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2] +.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3] +.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4] +.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5] +.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6] +.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB[7] # End adder # Start DPRAM .subckt dpram clk=clk wen=wen_st1 ren=ren \ waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \ -waddr[5]=waddr_st1[5] waddr[6]=waddr_st1[6] waddr[7]=waddr_st1[7] waddr[8]=waddr_st1[8] waddr[9]=waddr_st1[9] waddr[10]==waddr_st1[10] \ +waddr[5]=waddr_st1[5] waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 waddr[9]=zero00 waddr[10]==zero00 \ raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \ -raddr[6]=raddr[6] raddr[7]=raddr[7] raddr[8]=raddr[8] raddr[9]=raddr[9] raddr[10]=raddr[10] \ -d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=zero00 d_in[3]=zero00 d_in[4]=zero00 d_in[5]=zero00 \ -d_in[6]=zero00 d_in[7]=zero00 d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \ +raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 raddr[9]=zero00 raddr[10]=zero00 \ +d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \ +d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \ d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \ d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \ d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \ d_in[30]=zero00 d_in[31]=zero00 \ d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \ -d_out[0]=q[0] d_out[1]=q[1] d_out[2]=unconn d_out[3]=unconn d_out[4]=unconn d_out[5]=unconn \ -d_out[6]=unconn d_out[7]=unconn d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \ +d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \ +d_out[6]=q[6] d_out[7]=q[7] d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \ d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \ d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \ d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \ diff --git a/ERI_demo/pipelined_32b_adder.v b/ERI_demo/pipelined_8b_adder.v similarity index 65% rename from ERI_demo/pipelined_32b_adder.v rename to ERI_demo/pipelined_8b_adder.v index ecf0007c0..4d8e975cd 100644 --- a/ERI_demo/pipelined_32b_adder.v +++ b/ERI_demo/pipelined_8b_adder.v @@ -1,14 +1,14 @@ ///////////////////////////////////// // // // ERI summit demo-benchmark // -// pipelined_32b_adder.v // +// pipelined_8b_adder.v // // by Aurelien // // // ///////////////////////////////////// `timescale 1 ns/ 1 ps -module pipelined_32b_adder( +module pipelined_8b_adder( clk, raddr, waddr, @@ -19,26 +19,26 @@ module pipelined_32b_adder( q ); input clk; - input[10:0] raddr; - input[10:0] waddr; + input[5:0] raddr; + input[5:0] waddr; input ren; input wen; - input[30:0] a; - input[30:0] b; - output[31:0] q; + input[6:0] a; + input[6:0] b; + output[7:0] q; - reg[2047:0] ram[31:0]; - reg[30:0] a_st0; - reg[30:0] a_st1; - reg[30:0] b_st0; - reg[30:0] b_st1; - reg[10:0] waddr_st0; - reg[10:0] waddr_st1; + reg[63:0] ram[7:0]; + reg[6:0] a_st0; + reg[6:0] a_st1; + reg[6:0] b_st0; + reg[6:0] b_st1; + reg[8:0] waddr_st0; + reg[8:0] waddr_st1; reg wen_st0; reg wen_st1; - reg[31:0] q_int; + reg[7:0] q_int; - wire[31:0] AplusB; + wire[7:0] AplusB; assign AplusB = a_st1 + b_st1; assign q = q_int; @@ -60,4 +60,4 @@ module pipelined_32b_adder( end end -endmodule : pipelined_32b_adder +endmodule diff --git a/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v b/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v new file mode 100644 index 000000000..d43a5b694 --- /dev/null +++ b/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v @@ -0,0 +1,219 @@ +`timescale 1 ns/ 100 ps + +`include "OPENFPGAPATHKEYWORD/ERI_demo/pipelined_8b_adder.v" + +module pipelined_8b_adder_top_formal_verification_random_tb(); + reg clk; + reg[5:0] raddr; + reg[5:0] waddr; + reg ren; + reg wen; + reg[6:0] a; + reg[6:0] b; + wire[7:0] q_gfpga; + wire[7:0] q_bench; + reg[7:0] q_flag; + + pipelined_8b_adder_top_formal_verification DUT( + .clk_fm (clk), + .raddr_0__fm (raddr[0]), + .raddr_1__fm (raddr[1]), + .raddr_2__fm (raddr[2]), + .raddr_3__fm (raddr[3]), + .raddr_4__fm (raddr[4]), + .raddr_5__fm (raddr[5]), + .waddr_0__fm (waddr[0]), + .waddr_1__fm (waddr[1]), + .waddr_2__fm (waddr[2]), + .waddr_3__fm (waddr[3]), + .waddr_4__fm (waddr[4]), + .waddr_5__fm (waddr[5]), + .ren_fm (ren), + .wen_fm (wen), + .a_0__fm (a[0]), + .a_1__fm (a[1]), + .a_2__fm (a[2]), + .a_3__fm (a[3]), + .a_4__fm (a[4]), + .a_5__fm (a[5]), + .a_6__fm (a[6]), + .b_0__fm (b[0]), + .b_1__fm (b[1]), + .b_2__fm (b[2]), + .b_3__fm (b[3]), + .b_4__fm (b[4]), + .b_5__fm (b[5]), + .b_6__fm (b[6]), + .out_q_0__fm (q_gfpga[0]), + .out_q_1__fm (q_gfpga[1]), + .out_q_2__fm (q_gfpga[2]), + .out_q_3__fm (q_gfpga[3]), + .out_q_4__fm (q_gfpga[4]), + .out_q_5__fm (q_gfpga[5]), + .out_q_6__fm (q_gfpga[6]), + .out_q_7__fm (q_gfpga[7]) + ); + + pipelined_8b_adder ref0( + .clk (clk), + .raddr (raddr), + .waddr (waddr), + .ren (ren), + .wen (wen), + .a (a), + .b (b), + .q (q_bench) + ); + + integer nb_error = 0; + integer count = 0; + integer lim_max = 64 - 1; + integer write_complete = 0; + +//----- Initialization + initial begin + clk <= 1'b0; + a <= 7'h00; + b <= 7'h00; + wen <= 1'b0; + ren <= 1'b0; + waddr <= 9'h000; + raddr <= 9'h000; + while(1) begin + #2.5 + clk <= !clk; + end + end + +//----- Input Stimulis + always@(negedge clk) begin + if(write_complete == 0) begin + wen <= 1'b1; + ren <= 1'b0; + count <= count + 1; + waddr <= waddr + 1; + if(count == lim_max) begin + write_complete = 1; + end + end else begin + wen <= $random; + ren <= $random; + waddr <= $random; + raddr <= $random; + end + a <= $random; + b <= $random; + end + + + always@(negedge clk) begin + if(!(q_gfpga[0] === q_bench[0]) && !(q_bench[0] === 1'bx)) begin + q_flag[0] <= 1'b1; + end else begin + q_flag[0] <= 1'b0; + end + if(!(q_gfpga[1] === q_bench[1]) && !(q_bench[1] === 1'bx)) begin + q_flag[1] <= 1'b1; + end else begin + q_flag[1] <= 1'b0; + end + if(!(q_gfpga[2] === q_bench[2]) && !(q_bench[2] === 1'bx)) begin + q_flag[2] <= 1'b1; + end else begin + q_flag[2] <= 1'b0; + end + if(!(q_gfpga[3] === q_bench[3]) && !(q_bench[3] === 1'bx)) begin + q_flag[3] <= 1'b1; + end else begin + q_flag[3] <= 1'b0; + end + if(!(q_gfpga[4] === q_bench[4]) && !(q_bench[4] === 1'bx)) begin + q_flag[4] <= 1'b1; + end else begin + q_flag[4] <= 1'b0; + end + if(!(q_gfpga[5] === q_bench[5]) && !(q_bench[5] === 1'bx)) begin + q_flag[5] <= 1'b1; + end else begin + q_flag[5] <= 1'b0; + end + if(!(q_gfpga[6] === q_bench[6]) && !(q_bench[6] === 1'bx)) begin + q_flag[6] <= 1'b1; + end else begin + q_flag[6] <= 1'b0; + end + if(!(q_gfpga[7] === q_bench[7]) && !(q_bench[7] === 1'bx)) begin + q_flag[7] <= 1'b1; + end else begin + q_flag[7] <= 1'b0; + end + end + + + always@(posedge q_flag[0]) begin + if(q_flag[0]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[0] at time = %t", $realtime); + end + end + always@(posedge q_flag[1]) begin + if(q_flag[1]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[1] at time = %t", $realtime); + end + end + always@(posedge q_flag[2]) begin + if(q_flag[2]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[2] at time = %t", $realtime); + end + end + always@(posedge q_flag[3]) begin + if(q_flag[3]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[3] at time = %t", $realtime); + end + end + always@(posedge q_flag[4]) begin + if(q_flag[4]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[4] at time = %t", $realtime); + end + end + always@(posedge q_flag[5]) begin + if(q_flag[5]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[5] at time = %t", $realtime); + end + end + always@(posedge q_flag[6]) begin + if(q_flag[6]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[6] at time = %t", $realtime); + end + end + always@(posedge q_flag[7]) begin + if(q_flag[7]) begin + nb_error = nb_error + 1; + $display("Mismatch on q_gfpga[7] at time = %t", $realtime); + end + end + + initial begin + $dumpfile("pipelined_8b_adder_formal.vcd"); + $dumpvars(1, pipelined_8b_adder_top_formal_verification_random_tb); + end + + initial begin + $timeformat(-9, 2, "ns", 20); + $display("Simulation start"); + #1500 // Can be changed by the user for his need + if(nb_error == 0) begin + $display("Simulation Succeed"); + end else begin + $display("Simulation Failed with %d error(s)", nb_error); + end + $finish; + end + +endmodule From 0c3e8bb70a31c8fa975e33b811e44b1575896177 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 12:11:48 -0600 Subject: [PATCH 18/84] add a new option to the router to enable conversion of route_chan_width to be tileable --- fpga_flow/scripts/fpga_flow.pl | 5 +++ vpr7_x2p/vpr/SRC/base/OptionTokens.c | 2 ++ vpr7_x2p/vpr/SRC/base/OptionTokens.h | 2 ++ vpr7_x2p/vpr/SRC/base/ReadOptions.c | 4 +++ vpr7_x2p/vpr/SRC/base/SetupVPR.c | 7 +++++ vpr7_x2p/vpr/SRC/base/ShowSetup.c | 2 ++ vpr7_x2p/vpr/SRC/base/place_and_route.c | 31 +++++++++++++++++++ vpr7_x2p/vpr/SRC/base/vpr_api.c | 3 ++ vpr7_x2p/vpr/SRC/base/vpr_types.h | 2 ++ .../tileable_chan_details_builder.cpp | 19 ++++++++++++ .../rr_graph/tileable_chan_details_builder.h | 2 ++ .../rr_graph/tileable_rr_graph_builder.h | 2 ++ 12 files changed, 81 insertions(+) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 50f063106..fe81f3b39 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -155,6 +155,7 @@ sub print_usage() print " \t-vpr_place_clb_pin_remap: turn on place_clb_pin_remap in VPR.\n"; print " \t-vpr_max_router_iteration : specify the max router iteration in VPR.\n"; print " \t-vpr_route_breadthfirst : use the breadth-first routing algorithm of VPR.\n"; + print " \t-vpr_use_tileable_route_chan_width: turn on the conversion to tileable_route_chan_width in VPR.\n"; print " \t-min_route_chan_width : turn on routing with * min_route_chan_width.\n"; print " \t-fix_route_chan_width : turn on routing with a fixed route_chan_width, defined in benchmark configuration file.\n"; print " [ VPR - FPGA-X2P Extension ] \n"; @@ -322,6 +323,7 @@ sub opts_read() &read_opt_into_hash("ace_d","on","off"); &read_opt_into_hash("vpr_timing_pack_off","off","off"); &read_opt_into_hash("vpr_route_breadthfirst","off","off"); + &read_opt_into_hash("vpr_use_tileable_route_chan_width","off","off"); &read_opt_into_hash("min_route_chan_width","on","off"); &read_opt_into_hash("fix_route_chan_width","off","off"); &read_opt_into_hash("vpr_max_router_iteration","on","off"); @@ -1313,6 +1315,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) if (($fix_chan_width > 0)||($fix_chan_width == 0)) { $chan_width_opt = "-route_chan_width $fix_chan_width"; } + if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) { + $chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width"; + } # FPGA SPICE options my ($vpr_spice_opts) = (""); diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c index cb71d400c..5d8ea1bfc 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.c @@ -57,6 +57,8 @@ struct s_TokenPair OptionBaseTokenList[] = { { "power_output_file", OT_POWER_OUT_FILE }, /* Output file for power results */ { "power", OT_POWER }, /* Run power estimation? */ { "tech_properties", OT_CMOS_TECH_BEHAVIOR_FILE }, /* Technology properties */ + /* Xifan Tang: Tileable routing support !!! */ + { "use_tileable_route_chan_width", OT_USE_TILEABLE_ROUTE_CHAN_WIDTH}, /* Enable adaption to tileable route chan_width */ /* General FPGA_X2P: FPGA-SPICE/Verilog/Bitstream Options */ { "fpga_x2p_rename_illegal_port", OT_FPGA_X2P_RENAME_ILLEGAL_PORT }, /* Xifan TANG: rename illegal port names */ { "fpga_x2p_signal_density_weight", OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT }, /* The weight of signal density */ diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.h b/vpr7_x2p/vpr/SRC/base/OptionTokens.h index 6f426b26f..f20845989 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.h +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.h @@ -74,6 +74,8 @@ enum e_OptionBaseToken { OT_ACTIVITY_FILE, OT_POWER_OUT_FILE, OT_CMOS_TECH_BEHAVIOR_FILE, + /* Xifan Tang: Tileable routing support !!! */ + OT_USE_TILEABLE_ROUTE_CHAN_WIDTH, /* General FPGA_X2P: FPGA-SPICE/Verilog/Bitstream Options */ OT_FPGA_X2P_RENAME_ILLEGAL_PORT, OT_FPGA_X2P_SIGNAL_DENSITY_WEIGHT, /* The weight of signal density in determining number of clock cycles in simulation */ diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c index 14ba29921..efe543974 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c @@ -474,6 +474,10 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) { case OT_CMOS_TECH_BEHAVIOR_FILE: return ReadString(Args, &Options->CmosTechFile); + /* Xifan Tang: Tileable routing support !!! */ + case OT_USE_TILEABLE_ROUTE_CHAN_WIDTH: + return Args; + /* Xifan Tang: FPGA X2P Options*/ case OT_FPGA_X2P_RENAME_ILLEGAL_PORT: return Args; diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index af240a0ea..531951966 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -626,6 +626,13 @@ static void SetupRouterOpts(INP t_options Options, INP boolean TimingEnabled, if (Options.Count[OT_SHOW_PASS_TRANS]) { is_show_pass_trans = TRUE; } + /* END */ + + /* Xifan Tang: Tileable routing support !!! */ + RouterOpts->use_tileable_route_chan_width = FALSE; + if (Options.Count[OT_USE_TILEABLE_ROUTE_CHAN_WIDTH]) { + RouterOpts->use_tileable_route_chan_width = TRUE; + } /* END */ /* Depends on RouterOpts->router_algorithm */ diff --git a/vpr7_x2p/vpr/SRC/base/ShowSetup.c b/vpr7_x2p/vpr/SRC/base/ShowSetup.c index 8614a3fcf..6980c1dc3 100644 --- a/vpr7_x2p/vpr/SRC/base/ShowSetup.c +++ b/vpr7_x2p/vpr/SRC/base/ShowSetup.c @@ -207,6 +207,7 @@ static void ShowRouterOpts(INP struct s_router_opts RouterOpts) { } else { vpr_printf(TIO_MESSAGE_INFO, "%d\n", RouterOpts.fixed_channel_width); } + vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.use_tileable_route_chan_width: %s\n", RouterOpts.use_tileable_route_chan_width ? "TRUE\n" : "FALSE\n"); vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.acc_fac: %f\n", RouterOpts.acc_fac); vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.bb_factor: %d\n", RouterOpts.bb_factor); @@ -260,6 +261,7 @@ static void ShowRouterOpts(INP struct s_router_opts RouterOpts) { } else { vpr_printf(TIO_MESSAGE_INFO, "%d\n", RouterOpts.fixed_channel_width); } + vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.use_tileable_route_chan_width: ", RouterOpts.use_tileable_route_chan_width ? "TRUE\n" : "FALSE\n"); vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.acc_fac: %f\n", RouterOpts.acc_fac); vpr_printf(TIO_MESSAGE_INFO, "RouterOpts.bb_factor: %d\n", RouterOpts.bb_factor); diff --git a/vpr7_x2p/vpr/SRC/base/place_and_route.c b/vpr7_x2p/vpr/SRC/base/place_and_route.c index f4c53e72b..1e2bad1f2 100644 --- a/vpr7_x2p/vpr/SRC/base/place_and_route.c +++ b/vpr7_x2p/vpr/SRC/base/place_and_route.c @@ -27,6 +27,8 @@ /* CLB PIN REMAP */ #include "place_clb_pin_remap.h" +#include "tileable_chan_details_builder.h" + /******************* Subroutines local to this module ************************/ static int binary_search_place_and_route(struct s_placer_opts placer_opts, @@ -326,14 +328,31 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, udsd_multiplier = 2; /* UDSD by AY End */ + if (router_opts.fixed_channel_width != NO_FIXED_CHANNEL_WIDTH) { current = router_opts.fixed_channel_width + 5 * udsd_multiplier; low = router_opts.fixed_channel_width - 1 * udsd_multiplier; } else { current = max_pins_per_clb + max_pins_per_clb % 2; /* Binary search part */ + /* End */ low = -1; } + /* Xifan Tang: W estimation for tileable routing architecture */ + /* Build the segment inf vector */ + std::vector segment_vec; + for (int iseg = 0; iseg < det_routing_arch.num_segment; ++iseg) { + segment_vec.push_back(segment_inf[iseg]); + } + + if (TRUE == router_opts.use_tileable_route_chan_width) { + int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec); + vpr_printf(TIO_MESSAGE_INFO, + "Adapt routing channel width (%d) to be tileable: %d\n", + current, adapted_W); + current = adapted_W; + } + /* Constraints must be checked to not break rr_graph generator */ if (det_routing_arch.directionality == UNI_DIRECTIONAL) { if (current % 2 != 0) { @@ -442,6 +461,7 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, if (low != -1) { current = (high + low) / 2; + } else { current = high / 2; /* haven't found lower bound yet */ } @@ -457,6 +477,7 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, final = high; current = (high + low) / 2; + } else { if (router_opts.fixed_channel_width != NO_FIXED_CHANNEL_WIDTH) { /* FOR Wneed = f(Fs) search */ @@ -468,10 +489,20 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, } } else { current = low * 2; /* Haven't found upper bound yet */ + } } } current = current + current % udsd_multiplier; + + /* Xifan Tang: W estimation for tileable routing architecture */ + if (TRUE == router_opts.use_tileable_route_chan_width) { + int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec); + vpr_printf(TIO_MESSAGE_INFO, + "Adapt routing channel width (%d) to be tileable: %d\n", + current, adapted_W); + current = adapted_W; + } } /* The binary search above occassionally does not find the minimum * diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 6827e010f..dd5daf871 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -146,6 +146,9 @@ void vpr_print_usage(void) { "\t[--acc_fac ] [--first_iter_pres_fac ]\n"); vpr_printf(TIO_MESSAGE_INFO, "\t[--bend_cost ] [--route_type global | detailed]\n"); + /* Xifan Tang: Tileable routing support !!! */ + vpr_printf(TIO_MESSAGE_INFO, + "\t[--use_tileable_route_chan_width ]\n"); vpr_printf(TIO_MESSAGE_INFO, "\t[--verify_binary_search] [--route_chan_width ]\n"); vpr_printf(TIO_MESSAGE_INFO, diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index cd163d111..717be3087 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -759,6 +759,8 @@ struct s_router_opts { boolean verify_binary_search; boolean full_stats; boolean doRouting; + /* Xifan Tang: option to enable adaption to tileable route channel width */ + boolean use_tileable_route_chan_width; }; /* All the parameters controlling the router's operation are in this * diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.cpp index 80854e9ef..c1c5ea611 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.cpp @@ -118,6 +118,25 @@ std::vector get_num_tracks_per_seg_type(const size_t chan_width, return result; } +/************************************************************************ + * Adapt the number of channel width to a tileable routing architecture + ***********************************************************************/ +int adapt_to_tileable_route_chan_width(int chan_width, + std::vector segment_infs) { + int tileable_chan_width = 0; + + /* Estimate the number of segments per type by the given ChanW*/ + std::vector num_tracks_per_seg_type = get_num_tracks_per_seg_type(chan_width, + segment_infs, + true); /* Force to use the full segment group */ + /* Sum-up the number of tracks */ + for (size_t iseg = 0; iseg < num_tracks_per_seg_type.size(); ++iseg) { + tileable_chan_width += num_tracks_per_seg_type[iseg]; + } + + return tileable_chan_width; +} + /************************************************************************ * Build details of routing tracks in a channel * The function will diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.h index 3031d3ef3..66cfa824a 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.h +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_chan_details_builder.h @@ -4,6 +4,8 @@ #include "vpr_types.h" #include "chan_node_details.h" +int adapt_to_tileable_route_chan_width(int chan_width, std::vector segment_inf); + ChanNodeDetails build_unidir_chan_node_details(const size_t chan_width, const size_t max_seg_length, const enum e_side device_side, const std::vector segment_inf); diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h index 5844a55d5..41ad7c485 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h @@ -5,6 +5,8 @@ #include "vpr_types.h" +int adapt_to_tileable_route_chan_width(int chanW, t_segment_inf* segment_inf); + void build_tileable_unidir_rr_graph(INP const int L_num_types, INP t_type_ptr types, INP const int L_nx, INP const int L_ny, INP struct s_grid_tile **L_grid, INP const int chan_width, From 53486b8a898a803aa9226125bfc1f0421ed1b4ab Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 3 Jul 2019 12:30:56 -0600 Subject: [PATCH 19/84] Added 'spice_simulator_path' in fpga_flow added vpr_fpga_spice_simulator_path in fpga-flow script --- fpga_flow/scripts/fpga_flow.pl | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index f1ea28fb6..bf2668554 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -168,6 +168,7 @@ sub print_usage() print " \t-vpr_fpga_spice_leakage_only : turn on leakage_only mode in VPR FPGA SPICE\n"; print " \t-vpr_fpga_spice_parasitic_net_estimation_off : turn off parasitic_net_estimation in VPR FPGA SPICE\n"; print " \t-vpr_fpga_spice_testbench_load_extraction_off : turn off testbench_load_extraction in VPR FPGA SPICE\n"; + print " \t-vpr_fpga_spice_simulator_path : Specify simulator path\n"; print " [ VPR - FPGA-Verilog Extension ] \n"; print " \t-vpr_fpga_verilog : turn on Verilog Generator of VPR FPGA SPICE\n"; print " \t-vpr_fpga_verilog_dir : provide the path where generated verilog files will be written\n"; @@ -274,8 +275,7 @@ sub read_opt_into_hash($ $ $) sub opts_read() { # if no arguments detected, print the usage. - if (-1 == $#ARGV) - { + if (-1 == $#ARGV) { print "Error : No input arguments!\n"; print "Help desk:\n"; &print_usage(); @@ -289,19 +289,15 @@ sub opts_read() my $argfd; # Check help fist $argfd = &spot_option($cur_arg,"-help"); - if (-1 != $argfd) - { + if (-1 != $argfd) { print "Help desk:\n"; &print_usage(); } # Then Check the debug with highest priority $argfd = &spot_option($cur_arg,"-debug"); - if (-1 != $argfd) - { + if (-1 != $argfd) { $opt_ptr->{"debug"} = "on"; - } - else - { + } else { $opt_ptr->{"debug"} = "off"; } # Check mandatory options @@ -350,6 +346,7 @@ sub opts_read() &read_opt_into_hash("vpr_fpga_spice_leakage_only","off","off"); &read_opt_into_hash("vpr_fpga_spice_parasitic_net_estimation_off","off","off"); &read_opt_into_hash("vpr_fpga_spice_testbench_load_extraction_off","off","off"); + &read_opt_into_hash("vpr_fpga_spice_simulator_path","on","off"); # FPGA-Verilog options # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" @@ -1331,6 +1328,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) { $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}"; } + if ("on" eq $opt_ptr->{vpr_fpga_spice_simulator_path}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_simulator_path $opt_ptr->{vpr_fpga_spice_simulator_path_val}"; + } if ("on" eq $opt_ptr->{vpr_fpga_spice_print_component_tb}) { $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_lut_testbench"; $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_hardlogic_testbench"; From 3c36a510115c6ad6d7a9e849c04d5a080ba0db95 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 3 Jul 2019 12:49:25 -0600 Subject: [PATCH 20/84] Added 'rewrite_path_in_file' back to repository --- fpga_flow/scripts/rewrite_path_in_file.pl | 138 ++++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 fpga_flow/scripts/rewrite_path_in_file.pl diff --git a/fpga_flow/scripts/rewrite_path_in_file.pl b/fpga_flow/scripts/rewrite_path_in_file.pl new file mode 100644 index 000000000..8a952e574 --- /dev/null +++ b/fpga_flow/scripts/rewrite_path_in_file.pl @@ -0,0 +1,138 @@ +#!usr/bin/perl -w +use strict; +use Cwd; +#use Shell; +use FileHandle; +#Use the time +use Time::gmtime; + +my $arch_file; +my $new_arch_file; +my $overwrite = "TRUE"; +my $keyword = "OPENFPGAPATHKEYWORD"; +my $default_keyword = "TRUE"; +my $change_to; +my $folder_top = "OpenFPGA"; + +sub print_usage() +{ + print "Usage:\n"; + print " perl [-options]\n"; + print " Options:(Mandatory!)\n"; + print " -i \n"; + print " Options:(Optional)\n"; + print " -o \n"; + print " -k \n"; + print "\n"; + return; +} + +sub opts_read() +{ + if ($#ARGV == -1){ + print "Error: Not enough input argument!\n"; + &print_usage(); + exit(1); + } else { + for (my $iargv = 0; $iargv < $#ARGV+1; $iargv++){ + if ("-i" eq $ARGV[$iargv]){ + $arch_file = $ARGV[$iargv+1]; + $iargv++; + } elsif ("-o" eq $ARGV[$iargv]){ + $new_arch_file = $ARGV[$iargv+1]; + $overwrite = "FALSE"; + $iargv++; + } elsif ("-k" eq $ARGV[$iargv]){ + $keyword = $ARGV[$iargv+1]; + $change_to = $ARGV[$iargv+2]; + $default_keyword = "FALSE"; + $iargv++; + $iargv++; + } else { + die "WRONG ARGUMENT"; + } + } + } + return; +} + +sub rewriting_required_check($) +{ + my ($arch) = @_; + open(F, $arch); + my @lines=; + close F; + my $grep_result = grep ($keyword, @lines); + if($grep_result >= 1){ + print "Rewrite needed\n"; + return 1; + } else { + print "Rewrite NOT needed\n"; + return 0; + } +} + +sub save_original($) +{ + my ($template) = @_; + my $renamed_template = "$template".".bak"; + rename($template, $renamed_template); + + return $renamed_template; +} + +sub findPath(){ + my $path; + my $dir = cwd; + my @folders = split("/", $dir); + for(my $count = 0; $count < ($#folders -1); $count++){ + if($folders[$count] eq ""){ + } else { + $path = "$path"."/"."$folders[$count]"; + if($folders[$count] eq $folder_top){ + print "$path\n"; + return $path; + } + } + } + die "ERROR: Script launched from the outside of the $folder_top folder!\n"; +} + +sub rewrite_file($ $) +{ + my ($arch, $template) = @_; + open(IN, '<'.$template); + open(OUT, '>'.$arch); + + if($default_keyword eq "TRUE"){ + my $myPath = &findPath(); + while(){ + $_ =~ s/$keyword/$myPath/g; + print OUT $_; + } + } else { + while(){ + $_ =~ s/$keyword/$change_to/g; + print OUT $_; + } + } + return; +} + +sub main() +{ + &opts_read(); + my $rewrite_needed = &rewriting_required_check($arch_file); + if($rewrite_needed == 1){ + if($overwrite eq "TRUE"){ + my $template_file = &save_original($arch_file); + &rewrite_file($arch_file, $template_file); + } else { + &rewrite_file($new_arch_file, $arch_file); + } + } + return; +} + +&main(); +exit(1); From 43e9d8afd1cad676a574ddce1bddf0ad576cb75c Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 3 Jul 2019 13:08:49 -0600 Subject: [PATCH 21/84] Add compact routing hierarchy option in fpga_flow --- fpga_flow/scripts/fpga_flow.pl | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 92111bb87..606692373 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -159,6 +159,7 @@ sub print_usage() print " \t-vpr_fpga_x2p_rename_illegal_port : turn on renaming illegal ports option of VPR FPGA SPICE\n"; print " \t-vpr_fpga_x2p_signal_density_weight : specify the option signal_density_weight of VPR FPGA SPICE\n"; print " \t-vpr_fpga_x2p_sim_window_size : specify the option sim_window_size of VPR FPGA SPICE\n"; + print " \t-vpr_fpga_x2p_compact_routing_hierarchy : allow routing block modularization\n"; print " [ VPR - FPGA-SPICE Extension ] \n"; print " \t-vpr_fpga_spice : turn on SPICE netlists print-out in VPR, specify a task file\n"; print " \t-vpr_fpga_spice_sim_mt_num : specify the option sim_mt_num of VPR FPGA SPICE\n"; @@ -168,6 +169,7 @@ sub print_usage() print " \t-vpr_fpga_spice_leakage_only : turn on leakage_only mode in VPR FPGA SPICE\n"; print " \t-vpr_fpga_spice_parasitic_net_estimation_off : turn off parasitic_net_estimation in VPR FPGA SPICE\n"; print " \t-vpr_fpga_spice_testbench_load_extraction_off : turn off testbench_load_extraction in VPR FPGA SPICE\n"; + print " \t-vpr_fpga_spice_simulator_path : Specify simulator path\n"; print " [ VPR - FPGA-Verilog Extension ] \n"; print " \t-vpr_fpga_verilog : turn on Verilog Generator of VPR FPGA SPICE\n"; print " \t-vpr_fpga_verilog_dir : provide the path where generated verilog files will be written\n"; @@ -338,6 +340,7 @@ sub opts_read() &read_opt_into_hash("vpr_fpga_x2p_rename_illegal_port","off","off"); &read_opt_into_hash("vpr_fpga_x2p_signal_density_weight","on","off"); &read_opt_into_hash("vpr_fpga_x2p_sim_window_size","on","off"); + &read_opt_into_hash("vpr_fpga_x2p_compact_routing_hierarchy","off","off"); &read_opt_into_hash("vpr_fpga_spice_sim_mt_num","on","off"); &read_opt_into_hash("vpr_fpga_spice_print_component_tb","off","off"); &read_opt_into_hash("vpr_fpga_spice_print_grid_tb","off","off"); @@ -345,6 +348,7 @@ sub opts_read() &read_opt_into_hash("vpr_fpga_spice_leakage_only","off","off"); &read_opt_into_hash("vpr_fpga_spice_parasitic_net_estimation_off","off","off"); &read_opt_into_hash("vpr_fpga_spice_testbench_load_extraction_off","off","off"); + &read_opt_into_hash("vpr_fpga_spice_simulator_path","on","off"); # FPGA-Verilog options # Read Opt into Hash(opt_ptr) : "opt_name","with_val","mandatory" @@ -1323,9 +1327,15 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) if ("on" eq $opt_ptr->{vpr_fpga_x2p_sim_window_size}) { $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_sim_window_size $opt_ptr->{vpr_fpga_x2p_sim_window_size_val}"; } + if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy"; + } if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) { $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}"; } + if ("on" eq $opt_ptr->{vpr_fpga_spice_simulator_path}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_simulator_path $opt_ptr->{vpr_fpga_spice_simulator_path_val}"; + } if ("on" eq $opt_ptr->{vpr_fpga_spice_print_component_tb}) { $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_lut_testbench"; $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_print_hardlogic_testbench"; From a539c6a2a7f36287f3e9caaf4170d39b1eb878ce Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 14:11:14 -0600 Subject: [PATCH 22/84] bug fixing in fpga_flow.pl --- fpga_flow/scripts/fpga_flow.pl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index fe81f3b39..23cb76067 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1476,6 +1476,9 @@ sub run_vpr_route($ $ $ $ $ $ $ $ $) if (($fix_chan_width > 0)||($fix_chan_width == 0)) { $chan_width_opt = "-route_chan_width $fix_chan_width"; } + if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) { + $chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width"; + } my ($vpr_spice_opts) = (""); if (("on" eq $opt_ptr->{power})&&("on" eq $opt_ptr->{vpr_fpga_spice})) { From 443a73954ffc48cfdc324c3d955a14c36f9ee8cb Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Wed, 3 Jul 2019 14:26:06 -0600 Subject: [PATCH 23/84] Removed all local files + Removed local configurations and scripts from previous commit --- .../k6_N10_rram_memory_bank_SC_winbond90.xml | 553 ------- .../benchmarks/List/lattice_benchmark.txt | 2 - .../Verilog/lattice_ultra_example/.gitignore | 8 - .../PID/16x16bit_multiplier_pipelined.v | 1413 ---------------- .../PID_Controller/PID/CLA_fixed.v | 259 --- .../PID_Controller/PID/PID.v | 434 ----- .../PID_Controller/PID/PID_defines.v | 8 - .../PID_Controller/PID/booth.v | 37 - .../source/top_module/delay_gen_ihd_ipd_isd.v | 207 --- .../hardware/source/top_module/i2c_defines.v | 369 ----- .../source/top_module/i2c_slave_data_fsm.v | 649 -------- .../source/top_module/led_driver_19022014.v | 203 --- .../top_module/mobeam_control_fsm_19022014.v | 1009 ------------ .../source/top_module/mobeam_delay_gen.v | 160 -- .../mobeam_i2c_reg_interface_19022014.v | 377 ----- .../source/top_module/testpll_pll_20_25Mhz.v | 82 - .../hardware/source/top_module/top_module.v | 334 ---- .../user_logic_control_reg_i2c_data_buf.v | 138 -- fpga_flow/configs/lattice_benchmark.conf | 31 - vpr7_x2p/vpr/ARCH/k6_ReRAM_Winbond.xml | 1453 ----------------- 20 files changed, 7726 deletions(-) delete mode 100644 fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml delete mode 100644 fpga_flow/benchmarks/List/lattice_benchmark.txt delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v delete mode 100644 fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v delete mode 100644 fpga_flow/configs/lattice_benchmark.conf delete mode 100755 vpr7_x2p/vpr/ARCH/k6_ReRAM_Winbond.xml diff --git a/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml b/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml deleted file mode 100644 index bfd21a6d8..000000000 --- a/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml +++ /dev/null @@ -1,553 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[19:0] clb.O[4:0] - clb.I[39:20] clb.O[9:5] - - - - - - - - - - - - - - - - - - - diff --git a/fpga_flow/benchmarks/List/lattice_benchmark.txt b/fpga_flow/benchmarks/List/lattice_benchmark.txt deleted file mode 100644 index 912818af7..000000000 --- a/fpga_flow/benchmarks/List/lattice_benchmark.txt +++ /dev/null @@ -1,2 +0,0 @@ -# Circuit Names, fixed routing channel width, -PID/*.v, 120 \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore deleted file mode 100644 index 7e0debc3e..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/.gitignore +++ /dev/null @@ -1,8 +0,0 @@ -# Ignore everything -* -# But descend into directories -!*/ -!.gitignore -# Recursively allow files under subtree -!/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/** -!/PID_Controller/** diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v deleted file mode 100644 index 7e9f45680..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/16x16bit_multiplier_pipelined.v +++ /dev/null @@ -1,1413 +0,0 @@ -/*16x16-bit multiplier -Author: Zhu Xu -Email: m99a1@yahoo.cn -*/ - -//Booth Encoder Array -module booth_array( -input [15:0]multiplier, -output [7:0]zero, -output [7:0]double, -output [7:0]negation -); - -booth_radix4 booth_radix4_0( -{multiplier[1:0],1'b0}, -zero[0], -double[0], -negation[0] -); - -booth_radix4 booth_radix4_1( -multiplier[3:1], -zero[1], -double[1], -negation[1] -); - -booth_radix4 booth_radix4_2( -multiplier[5:3], -zero[2], -double[2], -negation[2] -); -booth_radix4 booth_radix4_3( -multiplier[7:5], -zero[3], -double[3], -negation[3] -); - -booth_radix4 booth_radix4_4( -multiplier[9:7], -zero[4], -double[4], -negation[4] -); - -booth_radix4 booth_radix4_5( -multiplier[11:9], -zero[5], -double[5], -negation[5] -); -booth_radix4 booth_radix4_6( -multiplier[13:11], -zero[6], -double[6], -negation[6] -); - -booth_radix4 booth_radix4_7( -multiplier[15:13], -zero[7], -double[7], -negation[7] -); - -endmodule - -/*partial product generator unit -generate one 17-bit partial with inversed MSB without correction bit for negation -*/ -module partial_product_gen( -input [15:0]md, //multiplicand -input zero, -input double, -input negation, -output [16:0]pp -); - -wire [15:0]nmd; -assign nmd=negation?~md:md; - -wire [15:0]zmd; -assign zmd=zero?0:nmd; - -assign pp=double?{~zmd[15],zmd[14:0],negation}:{~zmd[15],zmd[15:0]}; - -endmodule - -module half_adder( -input A, -input B, -output S, -output carry -); -assign S=A^B; -assign carry=A&B; -endmodule - -module full_adder( -input A, -input B, -input cin, -output S, -output cout -); -wire AB; -assign AB=A&B; -wire AxorB; -assign AxorB=A^B; -assign S=AxorB^cin; -assign cout=AB|(AxorB&cin); -endmodule - -module compressor42( -input A, -input B, -input C, -input D, -input cin, -output S, -output carry, -output cout -); -wire AB; -assign AB=A&B; -wire AxorB; -assign AxorB=A^B; -wire CD; -assign CD=C&D; -wire CxorD; -assign CxorD=C^D; - -wire AxBxCxD=AxorB^CxorD; - -assign cout=AB|CD; -assign carry=(AB&CD)|(AxorB&CxorD)|((AxBxCxD)&cin); - -assign S=AxBxCxD^cin; - -endmodule - - -module multiplier_16x16bit_pipelined( -input i_clk, -input i_rst, -input i_start, -input [15:0]i_md, -input [15:0]i_mr, -output [31:0]o_product, -output o_ready -); -/////////////////////////////////////////////////////////////stage 0/////////////////////////////////////////////////// - -reg [15:0]md; -reg [15:0]mr; -reg stage_0_ready; - -always @(posedge i_clk or negedge i_rst)begin - if(!i_rst)begin - md<=0; - mr<=0; - stage_0_ready<=0; - end - else begin - if(i_start)begin - md<=i_md; - mr<=i_mr; - end - stage_0_ready<=i_start; - end - -end - -wire [7:0]zero; -wire [7:0]double; -wire [7:0]negation; - -booth_array booth_array_0( -mr, -zero, -double, -negation -); - - -//layer 0 -wire layer_0_w0[1:0]; -wire layer_0_w1; -wire layer_0_w2[2:0]; -wire layer_0_w3[1:0]; -wire layer_0_w4[3:0]; -wire layer_0_w5[2:0]; -wire layer_0_w6[4:0]; -wire layer_0_w7[3:0]; -wire layer_0_w8[5:0]; -wire layer_0_w9[4:0]; -wire layer_0_w10[6:0]; -wire layer_0_w11[5:0]; -wire layer_0_w12[7:0]; -wire layer_0_w13[6:0]; -wire layer_0_w14[8:0]; -wire layer_0_w15[7:0]; -wire layer_0_w16[8:0]; -wire layer_0_w17[7:0]; -wire layer_0_w18[6:0]; -wire layer_0_w19[6:0]; -wire layer_0_w20[5:0]; -wire layer_0_w21[5:0]; -wire layer_0_w22[4:0]; -wire layer_0_w23[4:0]; -wire layer_0_w24[3:0]; -wire layer_0_w25[3:0]; -wire layer_0_w26[2:0]; -wire layer_0_w27[2:0]; -wire layer_0_w28[1:0]; -wire layer_0_w29[1:0]; -wire layer_0_w30; -wire layer_0_w31; -partial_product_gen partial_product_gen_0( -md, -zero[0], -double[0], -negation[0], -{layer_0_w16[0],layer_0_w15[0],layer_0_w14[0],layer_0_w13[0],layer_0_w12[0],layer_0_w11[0],layer_0_w10[0],layer_0_w9[0],layer_0_w8[0],layer_0_w7[0],layer_0_w6[0],layer_0_w5[0],layer_0_w4[0],layer_0_w3[0],layer_0_w2[0],layer_0_w1,layer_0_w0[0]} -); -partial_product_gen partial_product_gen_1( -md, -zero[1], -double[1], -negation[1], -{layer_0_w18[0],layer_0_w17[0],layer_0_w16[1],layer_0_w15[1],layer_0_w14[1],layer_0_w13[1],layer_0_w12[1],layer_0_w11[1],layer_0_w10[1],layer_0_w9[1],layer_0_w8[1],layer_0_w7[1],layer_0_w6[1],layer_0_w5[1],layer_0_w4[1],layer_0_w3[1],layer_0_w2[1]} -); -partial_product_gen partial_product_gen_2( -md, -zero[2], -double[2], -negation[2], -{layer_0_w20[0],layer_0_w19[0],layer_0_w18[1],layer_0_w17[1],layer_0_w16[2],layer_0_w15[2],layer_0_w14[2],layer_0_w13[2],layer_0_w12[2],layer_0_w11[2],layer_0_w10[2],layer_0_w9[2],layer_0_w8[2],layer_0_w7[2],layer_0_w6[2],layer_0_w5[2],layer_0_w4[2]} -); -partial_product_gen partial_product_gen_3( -md, -zero[3], -double[3], -negation[3], -{layer_0_w22[0],layer_0_w21[0],layer_0_w20[1],layer_0_w19[1],layer_0_w18[2],layer_0_w17[2],layer_0_w16[3],layer_0_w15[3],layer_0_w14[3],layer_0_w13[3],layer_0_w12[3],layer_0_w11[3],layer_0_w10[3],layer_0_w9[3],layer_0_w8[3],layer_0_w7[3],layer_0_w6[3]} -); -partial_product_gen partial_product_gen_4( -md, -zero[4], -double[4], -negation[4], -{layer_0_w24[0],layer_0_w23[0],layer_0_w22[1],layer_0_w21[1],layer_0_w20[2],layer_0_w19[2],layer_0_w18[3],layer_0_w17[3],layer_0_w16[4],layer_0_w15[4],layer_0_w14[4],layer_0_w13[4],layer_0_w12[4],layer_0_w11[4],layer_0_w10[4],layer_0_w9[4],layer_0_w8[4]} -); -partial_product_gen partial_product_gen_5( -md, -zero[5], -double[5], -negation[5], -{layer_0_w26[0],layer_0_w25[0],layer_0_w24[1],layer_0_w23[1],layer_0_w22[2],layer_0_w21[2],layer_0_w20[3],layer_0_w19[3],layer_0_w18[4],layer_0_w17[4],layer_0_w16[5],layer_0_w15[5],layer_0_w14[5],layer_0_w13[5],layer_0_w12[5],layer_0_w11[5],layer_0_w10[5]} -); -partial_product_gen partial_product_gen_6( -md, -zero[6], -double[6], -negation[6], -{layer_0_w28[0],layer_0_w27[0],layer_0_w26[1],layer_0_w25[1],layer_0_w24[2],layer_0_w23[2],layer_0_w22[3],layer_0_w21[3],layer_0_w20[4],layer_0_w19[4],layer_0_w18[5],layer_0_w17[5],layer_0_w16[6],layer_0_w15[6],layer_0_w14[6],layer_0_w13[6],layer_0_w12[6]} -); -partial_product_gen partial_product_gen_7( -md, -zero[7], -double[7], -negation[7], -{layer_0_w30,layer_0_w29[0],layer_0_w28[1],layer_0_w27[1],layer_0_w26[2],layer_0_w25[2],layer_0_w24[3],layer_0_w23[3],layer_0_w22[4],layer_0_w21[4],layer_0_w20[5],layer_0_w19[5],layer_0_w18[6],layer_0_w17[6],layer_0_w16[7],layer_0_w15[7],layer_0_w14[7]} -); -//correction for negation -assign layer_0_w0[1]=negation[0]; -//sign extension -assign layer_0_w16[8]=1; -assign layer_0_w17[7]=1; -//correction for negation -assign layer_0_w2[2]=negation[1]; -//sign extension -assign layer_0_w19[6]=1; -//correction for negation -assign layer_0_w4[3]=negation[2]; -//sign extension -assign layer_0_w21[5]=1; -//correction for negation -assign layer_0_w6[4]=negation[3]; -//sign extension -assign layer_0_w23[4]=1; -//correction for negation -assign layer_0_w8[5]=negation[4]; -//sign extension -assign layer_0_w25[3]=1; -//correction for negation -assign layer_0_w10[6]=negation[5]; -//sign extension -assign layer_0_w27[2]=1; -//correction for negation -assign layer_0_w12[7]=negation[6]; -//sign extension -assign layer_0_w29[1]=1; -//correction for negation -assign layer_0_w14[8]=negation[7]; -//sign extension -assign layer_0_w31=1; - -//layer 1 -wire layer_1_w0[1:0]; -wire layer_1_w1; -wire layer_1_w2[2:0]; -wire layer_1_w3[1:0]; -wire layer_1_w4[1:0]; -wire layer_1_w5[1:0]; -wire layer_1_w6[1:0]; -wire layer_1_w7[3:0]; -wire layer_1_w8[2:0]; -wire layer_1_w9[2:0]; -wire layer_1_w10[4:0]; -wire layer_1_w11[3:0]; -wire layer_1_w12[3:0]; -wire layer_1_w13[5:0]; -wire layer_1_w14[4:0]; -wire layer_1_w15[4:0]; -wire layer_1_w16[5:0]; -wire layer_1_w17[4:0]; -wire layer_1_w18[5:0]; -wire layer_1_w19[4:0]; -wire layer_1_w20[3:0]; -wire layer_1_w21[3:0]; -wire layer_1_w22[2:0]; -wire layer_1_w23[2:0]; -wire layer_1_w24[3:0]; -wire layer_1_w25[2:0]; -wire layer_1_w26[1:0]; -wire layer_1_w27[1:0]; -wire layer_1_w28[2:0]; -wire layer_1_w29[1:0]; -wire layer_1_w30; -wire layer_1_w31; -assign layer_1_w0[0]=layer_0_w0[0]; -assign layer_1_w0[1]=layer_0_w0[1]; -assign layer_1_w1=layer_0_w1; -assign layer_1_w2[0]=layer_0_w2[0]; -assign layer_1_w2[1]=layer_0_w2[1]; -assign layer_1_w2[2]=layer_0_w2[2]; -assign layer_1_w3[0]=layer_0_w3[0]; -assign layer_1_w3[1]=layer_0_w3[1]; -full_adder layer_1_full_adder_0( -layer_0_w4[0], -layer_0_w4[1], -layer_0_w4[2], -layer_1_w4[0], -layer_1_w5[0] -); -assign layer_1_w4[1]=layer_0_w4[3]; -full_adder layer_1_full_adder_1( -layer_0_w5[0], -layer_0_w5[1], -layer_0_w5[2], -layer_1_w5[1], -layer_1_w6[0] -); -compressor42 layer_1_compressor42_0( -layer_0_w6[0], -layer_0_w6[1], -layer_0_w6[2], -layer_0_w6[3], -layer_0_w6[4], -layer_1_w6[1], -layer_1_w7[0], -layer_1_w7[1] -); -full_adder layer_1_full_adder_2( -layer_0_w7[0], -layer_0_w7[1], -layer_0_w7[2], -layer_1_w7[2], -layer_1_w8[0] -); -assign layer_1_w7[3]=layer_0_w7[3]; -compressor42 layer_1_compressor42_1( -layer_0_w8[0], -layer_0_w8[1], -layer_0_w8[2], -layer_0_w8[3], -layer_0_w8[4], -layer_1_w8[1], -layer_1_w9[0], -layer_1_w9[1] -); -assign layer_1_w8[2]=layer_0_w8[5]; -compressor42 layer_1_compressor42_2( -layer_0_w9[0], -layer_0_w9[1], -layer_0_w9[2], -layer_0_w9[3], -layer_0_w9[4], -layer_1_w9[2], -layer_1_w10[0], -layer_1_w10[1] -); -compressor42 layer_1_compressor42_3( -layer_0_w10[0], -layer_0_w10[1], -layer_0_w10[2], -layer_0_w10[3], -layer_0_w10[4], -layer_1_w10[2], -layer_1_w11[0], -layer_1_w11[1] -); -assign layer_1_w10[3]=layer_0_w10[5]; -assign layer_1_w10[4]=layer_0_w10[6]; -compressor42 layer_1_compressor42_4( -layer_0_w11[0], -layer_0_w11[1], -layer_0_w11[2], -layer_0_w11[3], -layer_0_w11[4], -layer_1_w11[2], -layer_1_w12[0], -layer_1_w12[1] -); -assign layer_1_w11[3]=layer_0_w11[5]; -compressor42 layer_1_compressor42_5( -layer_0_w12[0], -layer_0_w12[1], -layer_0_w12[2], -layer_0_w12[3], -layer_0_w12[4], -layer_1_w12[2], -layer_1_w13[0], -layer_1_w13[1] -); -full_adder layer_1_full_adder_3( -layer_0_w12[5], -layer_0_w12[6], -layer_0_w12[7], -layer_1_w12[3], -layer_1_w13[2] -); -compressor42 layer_1_compressor42_6( -layer_0_w13[0], -layer_0_w13[1], -layer_0_w13[2], -layer_0_w13[3], -layer_0_w13[4], -layer_1_w13[3], -layer_1_w14[0], -layer_1_w14[1] -); -assign layer_1_w13[4]=layer_0_w13[5]; -assign layer_1_w13[5]=layer_0_w13[6]; -compressor42 layer_1_compressor42_7( -layer_0_w14[0], -layer_0_w14[1], -layer_0_w14[2], -layer_0_w14[3], -layer_0_w14[4], -layer_1_w14[2], -layer_1_w15[0], -layer_1_w15[1] -); -full_adder layer_1_full_adder_4( -layer_0_w14[5], -layer_0_w14[6], -layer_0_w14[7], -layer_1_w14[3], -layer_1_w15[2] -); -assign layer_1_w14[4]=layer_0_w14[8]; -compressor42 layer_1_compressor42_8( -layer_0_w15[0], -layer_0_w15[1], -layer_0_w15[2], -layer_0_w15[3], -layer_0_w15[4], -layer_1_w15[3], -layer_1_w16[0], -layer_1_w16[1] -); -full_adder layer_1_full_adder_5( -layer_0_w15[5], -layer_0_w15[6], -layer_0_w15[7], -layer_1_w15[4], -layer_1_w16[2] -); -compressor42 layer_1_compressor42_9( -layer_0_w16[0], -layer_0_w16[1], -layer_0_w16[2], -layer_0_w16[3], -layer_0_w16[4], -layer_1_w16[3], -layer_1_w17[0], -layer_1_w17[1] -); -full_adder layer_1_full_adder_6( -layer_0_w16[5], -layer_0_w16[6], -layer_0_w16[7], -layer_1_w16[4], -layer_1_w17[2] -); -assign layer_1_w16[5]=layer_0_w16[8]; -compressor42 layer_1_compressor42_10( -layer_0_w17[0], -layer_0_w17[1], -layer_0_w17[2], -layer_0_w17[3], -layer_0_w17[4], -layer_1_w17[3], -layer_1_w18[0], -layer_1_w18[1] -); -full_adder layer_1_full_adder_7( -layer_0_w17[5], -layer_0_w17[6], -layer_0_w17[7], -layer_1_w17[4], -layer_1_w18[2] -); -compressor42 layer_1_compressor42_11( -layer_0_w18[0], -layer_0_w18[1], -layer_0_w18[2], -layer_0_w18[3], -layer_0_w18[4], -layer_1_w18[3], -layer_1_w19[0], -layer_1_w19[1] -); -assign layer_1_w18[4]=layer_0_w18[5]; -assign layer_1_w18[5]=layer_0_w18[6]; -compressor42 layer_1_compressor42_12( -layer_0_w19[0], -layer_0_w19[1], -layer_0_w19[2], -layer_0_w19[3], -layer_0_w19[4], -layer_1_w19[2], -layer_1_w20[0], -layer_1_w20[1] -); -assign layer_1_w19[3]=layer_0_w19[5]; -assign layer_1_w19[4]=layer_0_w19[6]; -compressor42 layer_1_compressor42_13( -layer_0_w20[0], -layer_0_w20[1], -layer_0_w20[2], -layer_0_w20[3], -layer_0_w20[4], -layer_1_w20[2], -layer_1_w21[0], -layer_1_w21[1] -); -assign layer_1_w20[3]=layer_0_w20[5]; -compressor42 layer_1_compressor42_14( -layer_0_w21[0], -layer_0_w21[1], -layer_0_w21[2], -layer_0_w21[3], -layer_0_w21[4], -layer_1_w21[2], -layer_1_w22[0], -layer_1_w22[1] -); -assign layer_1_w21[3]=layer_0_w21[5]; -compressor42 layer_1_compressor42_15( -layer_0_w22[0], -layer_0_w22[1], -layer_0_w22[2], -layer_0_w22[3], -layer_0_w22[4], -layer_1_w22[2], -layer_1_w23[0], -layer_1_w23[1] -); -compressor42 layer_1_compressor42_16( -layer_0_w23[0], -layer_0_w23[1], -layer_0_w23[2], -layer_0_w23[3], -layer_0_w23[4], -layer_1_w23[2], -layer_1_w24[0], -layer_1_w24[1] -); -full_adder layer_1_full_adder_8( -layer_0_w24[0], -layer_0_w24[1], -layer_0_w24[2], -layer_1_w24[2], -layer_1_w25[0] -); -assign layer_1_w24[3]=layer_0_w24[3]; -full_adder layer_1_full_adder_9( -layer_0_w25[0], -layer_0_w25[1], -layer_0_w25[2], -layer_1_w25[1], -layer_1_w26[0] -); -assign layer_1_w25[2]=layer_0_w25[3]; -full_adder layer_1_full_adder_10( -layer_0_w26[0], -layer_0_w26[1], -layer_0_w26[2], -layer_1_w26[1], -layer_1_w27[0] -); -full_adder layer_1_full_adder_11( -layer_0_w27[0], -layer_0_w27[1], -layer_0_w27[2], -layer_1_w27[1], -layer_1_w28[0] -); -assign layer_1_w28[1]=layer_0_w28[0]; -assign layer_1_w28[2]=layer_0_w28[1]; -assign layer_1_w29[0]=layer_0_w29[0]; -assign layer_1_w29[1]=layer_0_w29[1]; -assign layer_1_w30=layer_0_w30; -assign layer_1_w31=layer_0_w31; - -//layer 2 -wire [1:0]layer_2_w0; -wire layer_2_w1; -wire [2:0]layer_2_w2; -wire [1:0]layer_2_w3; -wire [1:0]layer_2_w4; -wire [1:0]layer_2_w5; -wire [1:0]layer_2_w6; -wire [1:0]layer_2_w7; -wire [1:0]layer_2_w8; -wire [1:0]layer_2_w9; -wire [1:0]layer_2_w10; -wire [3:0]layer_2_w11; -wire [2:0]layer_2_w12; -wire [2:0]layer_2_w13; -wire [2:0]layer_2_w14; -wire [2:0]layer_2_w15; -wire [3:0]layer_2_w16; -wire [2:0]layer_2_w17; -wire [3:0]layer_2_w18; -wire [2:0]layer_2_w19; -wire [3:0]layer_2_w20; -wire [2:0]layer_2_w21; -wire [1:0]layer_2_w22; -wire [1:0]layer_2_w23; -wire [2:0]layer_2_w24; -wire [1:0]layer_2_w25; -wire [2:0]layer_2_w26; -wire [1:0]layer_2_w27; -wire layer_2_w28; -wire [2:0]layer_2_w29; -wire layer_2_w30; -wire layer_2_w31; -assign layer_2_w0[0]=layer_1_w0[0]; -assign layer_2_w0[1]=layer_1_w0[1]; -assign layer_2_w1=layer_1_w1; -assign layer_2_w2[0]=layer_1_w2[0]; -assign layer_2_w2[1]=layer_1_w2[1]; -assign layer_2_w2[2]=layer_1_w2[2]; -assign layer_2_w3[0]=layer_1_w3[0]; -assign layer_2_w3[1]=layer_1_w3[1]; -assign layer_2_w4[0]=layer_1_w4[0]; -assign layer_2_w4[1]=layer_1_w4[1]; -assign layer_2_w5[0]=layer_1_w5[0]; -assign layer_2_w5[1]=layer_1_w5[1]; -assign layer_2_w6[0]=layer_1_w6[0]; -assign layer_2_w6[1]=layer_1_w6[1]; -full_adder layer_2_full_adder_0( -layer_1_w7[0], -layer_1_w7[1], -layer_1_w7[2], -layer_2_w7[0], -layer_2_w8[0] -); -assign layer_2_w7[1]=layer_1_w7[3]; -full_adder layer_2_full_adder_1( -layer_1_w8[0], -layer_1_w8[1], -layer_1_w8[2], -layer_2_w8[1], -layer_2_w9[0] -); -full_adder layer_2_full_adder_2( -layer_1_w9[0], -layer_1_w9[1], -layer_1_w9[2], -layer_2_w9[1], -layer_2_w10[0] -); -compressor42 layer_2_compressor42_0( -layer_1_w10[0], -layer_1_w10[1], -layer_1_w10[2], -layer_1_w10[3], -layer_1_w10[4], -layer_2_w10[1], -layer_2_w11[0], -layer_2_w11[1] -); -full_adder layer_2_full_adder_3( -layer_1_w11[0], -layer_1_w11[1], -layer_1_w11[2], -layer_2_w11[2], -layer_2_w12[0] -); -assign layer_2_w11[3]=layer_1_w11[3]; -full_adder layer_2_full_adder_4( -layer_1_w12[0], -layer_1_w12[1], -layer_1_w12[2], -layer_2_w12[1], -layer_2_w13[0] -); -assign layer_2_w12[2]=layer_1_w12[3]; -compressor42 layer_2_compressor42_1( -layer_1_w13[0], -layer_1_w13[1], -layer_1_w13[2], -layer_1_w13[3], -layer_1_w13[4], -layer_2_w13[1], -layer_2_w14[0], -layer_2_w14[1] -); -assign layer_2_w13[2]=layer_1_w13[5]; -compressor42 layer_2_compressor42_2( -layer_1_w14[0], -layer_1_w14[1], -layer_1_w14[2], -layer_1_w14[3], -layer_1_w14[4], -layer_2_w14[2], -layer_2_w15[0], -layer_2_w15[1] -); -compressor42 layer_2_compressor42_3( -layer_1_w15[0], -layer_1_w15[1], -layer_1_w15[2], -layer_1_w15[3], -layer_1_w15[4], -layer_2_w15[2], -layer_2_w16[0], -layer_2_w16[1] -); -compressor42 layer_2_compressor42_4( -layer_1_w16[0], -layer_1_w16[1], -layer_1_w16[2], -layer_1_w16[3], -layer_1_w16[4], -layer_2_w16[2], -layer_2_w17[0], -layer_2_w17[1] -); -assign layer_2_w16[3]=layer_1_w16[5]; -compressor42 layer_2_compressor42_5( -layer_1_w17[0], -layer_1_w17[1], -layer_1_w17[2], -layer_1_w17[3], -layer_1_w17[4], -layer_2_w17[2], -layer_2_w18[0], -layer_2_w18[1] -); -compressor42 layer_2_compressor42_6( -layer_1_w18[0], -layer_1_w18[1], -layer_1_w18[2], -layer_1_w18[3], -layer_1_w18[4], -layer_2_w18[2], -layer_2_w19[0], -layer_2_w19[1] -); -assign layer_2_w18[3]=layer_1_w18[5]; -compressor42 layer_2_compressor42_7( -layer_1_w19[0], -layer_1_w19[1], -layer_1_w19[2], -layer_1_w19[3], -layer_1_w19[4], -layer_2_w19[2], -layer_2_w20[0], -layer_2_w20[1] -); -full_adder layer_2_full_adder_5( -layer_1_w20[0], -layer_1_w20[1], -layer_1_w20[2], -layer_2_w20[2], -layer_2_w21[0] -); -assign layer_2_w20[3]=layer_1_w20[3]; -full_adder layer_2_full_adder_6( -layer_1_w21[0], -layer_1_w21[1], -layer_1_w21[2], -layer_2_w21[1], -layer_2_w22[0] -); -assign layer_2_w21[2]=layer_1_w21[3]; -full_adder layer_2_full_adder_7( -layer_1_w22[0], -layer_1_w22[1], -layer_1_w22[2], -layer_2_w22[1], -layer_2_w23[0] -); -full_adder layer_2_full_adder_8( -layer_1_w23[0], -layer_1_w23[1], -layer_1_w23[2], -layer_2_w23[1], -layer_2_w24[0] -); -full_adder layer_2_full_adder_9( -layer_1_w24[0], -layer_1_w24[1], -layer_1_w24[2], -layer_2_w24[1], -layer_2_w25[0] -); -assign layer_2_w24[2]=layer_1_w24[3]; -full_adder layer_2_full_adder_10( -layer_1_w25[0], -layer_1_w25[1], -layer_1_w25[2], -layer_2_w25[1], -layer_2_w26[0] -); -assign layer_2_w26[1]=layer_1_w26[0]; -assign layer_2_w26[2]=layer_1_w26[1]; -assign layer_2_w27[0]=layer_1_w27[0]; -assign layer_2_w27[1]=layer_1_w27[1]; -full_adder layer_2_full_adder_11( -layer_1_w28[0], -layer_1_w28[1], -layer_1_w28[2], -layer_2_w28, -layer_2_w29[0] -); -assign layer_2_w29[1]=layer_1_w29[0]; -assign layer_2_w29[2]=layer_1_w29[1]; -assign layer_2_w30=layer_1_w30; -assign layer_2_w31=layer_1_w31; - - -///////////////////////////////////////////////////////stage 1/////////////////////////////////////////////////////// -reg [1:0]reg_layer_2_w0; -reg reg_layer_2_w1; -reg [2:0]reg_layer_2_w2; -reg [1:0]reg_layer_2_w3; -reg [1:0]reg_layer_2_w4; -reg [1:0]reg_layer_2_w5; -reg [1:0]reg_layer_2_w6; -reg [1:0]reg_layer_2_w7; -reg [1:0]reg_layer_2_w8; -reg [1:0]reg_layer_2_w9; -reg [1:0]reg_layer_2_w10; -reg [3:0]reg_layer_2_w11; -reg [2:0]reg_layer_2_w12; -reg [2:0]reg_layer_2_w13; -reg [2:0]reg_layer_2_w14; -reg [2:0]reg_layer_2_w15; -reg [3:0]reg_layer_2_w16; -reg [2:0]reg_layer_2_w17; -reg [3:0]reg_layer_2_w18; -reg [2:0]reg_layer_2_w19; -reg [3:0]reg_layer_2_w20; -reg [2:0]reg_layer_2_w21; -reg [1:0]reg_layer_2_w22; -reg [1:0]reg_layer_2_w23; -reg [2:0]reg_layer_2_w24; -reg [1:0]reg_layer_2_w25; -reg [2:0]reg_layer_2_w26; -reg [1:0]reg_layer_2_w27; -reg reg_layer_2_w28; -reg [2:0]reg_layer_2_w29; -reg reg_layer_2_w30; -reg reg_layer_2_w31; -reg stage_1_ready; -assign o_ready=stage_1_ready; - -always @(posedge i_clk or negedge i_rst)begin - if(!i_rst)begin - stage_1_ready<=0; - reg_layer_2_w0<=0; - reg_layer_2_w1<=0; - reg_layer_2_w2<=0; - reg_layer_2_w3<=0; - reg_layer_2_w4<=0; - reg_layer_2_w5<=0; - reg_layer_2_w6<=0; - reg_layer_2_w7<=0; - reg_layer_2_w8<=0; - reg_layer_2_w9<=0; - reg_layer_2_w10<=0; - reg_layer_2_w11<=0; - reg_layer_2_w12<=0; - reg_layer_2_w13<=0; - reg_layer_2_w14<=0; - reg_layer_2_w15<=0; - reg_layer_2_w16<=0; - reg_layer_2_w17<=0; - reg_layer_2_w18<=0; - reg_layer_2_w19<=0; - reg_layer_2_w20<=0; - reg_layer_2_w21<=0; - reg_layer_2_w22<=0; - reg_layer_2_w23<=0; - reg_layer_2_w24<=0; - reg_layer_2_w25<=0; - reg_layer_2_w26<=0; - reg_layer_2_w27<=0; - reg_layer_2_w28<=0; - reg_layer_2_w29<=0; - reg_layer_2_w30<=0; - reg_layer_2_w31<=0; - end - else begin - if(stage_0_ready)begin - reg_layer_2_w0<=layer_2_w0; - reg_layer_2_w1<=layer_2_w1; - reg_layer_2_w2<=layer_2_w2; - reg_layer_2_w3<=layer_2_w3; - reg_layer_2_w4<=layer_2_w4; - reg_layer_2_w5<=layer_2_w5; - reg_layer_2_w6<=layer_2_w6; - reg_layer_2_w7<=layer_2_w7; - reg_layer_2_w8<=layer_2_w8; - reg_layer_2_w9<=layer_2_w9; - reg_layer_2_w10<=layer_2_w10; - reg_layer_2_w11<=layer_2_w11; - reg_layer_2_w12<=layer_2_w12; - reg_layer_2_w13<=layer_2_w13; - reg_layer_2_w14<=layer_2_w14; - reg_layer_2_w15<=layer_2_w15; - reg_layer_2_w16<=layer_2_w16; - reg_layer_2_w17<=layer_2_w17; - reg_layer_2_w18<=layer_2_w18; - reg_layer_2_w19<=layer_2_w19; - reg_layer_2_w20<=layer_2_w20; - reg_layer_2_w21<=layer_2_w21; - reg_layer_2_w22<=layer_2_w22; - reg_layer_2_w23<=layer_2_w23; - reg_layer_2_w24<=layer_2_w24; - reg_layer_2_w25<=layer_2_w25; - reg_layer_2_w26<=layer_2_w26; - reg_layer_2_w27<=layer_2_w27; - reg_layer_2_w28<=layer_2_w28; - reg_layer_2_w29<=layer_2_w29; - reg_layer_2_w30<=layer_2_w30; - reg_layer_2_w31<=layer_2_w31; - end - stage_1_ready<=stage_0_ready; - end -end - -//layer 3 -wire layer_3_w0[1:0]; -wire layer_3_w1; -wire layer_3_w2[2:0]; -wire layer_3_w3[1:0]; -wire layer_3_w4[1:0]; -wire layer_3_w5[1:0]; -wire layer_3_w6[1:0]; -wire layer_3_w7[1:0]; -wire layer_3_w8[1:0]; -wire layer_3_w9[1:0]; -wire layer_3_w10[1:0]; -wire layer_3_w11[1:0]; -wire layer_3_w12[1:0]; -wire layer_3_w13[1:0]; -wire layer_3_w14[1:0]; -wire layer_3_w15[1:0]; -wire layer_3_w16[2:0]; -wire layer_3_w17[1:0]; -wire layer_3_w18[2:0]; -wire layer_3_w19[1:0]; -wire layer_3_w20[2:0]; -wire layer_3_w21[1:0]; -wire layer_3_w22[2:0]; -wire layer_3_w23[1:0]; -wire layer_3_w24; -wire layer_3_w25[2:0]; -wire layer_3_w26; -wire layer_3_w27[2:0]; -wire layer_3_w28; -wire layer_3_w29; -wire layer_3_w30[1:0]; -wire layer_3_w31; -assign layer_3_w0[0]=reg_layer_2_w0[0]; -assign layer_3_w0[1]=reg_layer_2_w0[1]; -assign layer_3_w1=reg_layer_2_w1; -assign layer_3_w2[0]=reg_layer_2_w2[0]; -assign layer_3_w2[1]=reg_layer_2_w2[1]; -assign layer_3_w2[2]=reg_layer_2_w2[2]; -assign layer_3_w3[0]=reg_layer_2_w3[0]; -assign layer_3_w3[1]=reg_layer_2_w3[1]; -assign layer_3_w4[0]=reg_layer_2_w4[0]; -assign layer_3_w4[1]=reg_layer_2_w4[1]; -assign layer_3_w5[0]=reg_layer_2_w5[0]; -assign layer_3_w5[1]=reg_layer_2_w5[1]; -assign layer_3_w6[0]=reg_layer_2_w6[0]; -assign layer_3_w6[1]=reg_layer_2_w6[1]; -assign layer_3_w7[0]=reg_layer_2_w7[0]; -assign layer_3_w7[1]=reg_layer_2_w7[1]; -assign layer_3_w8[0]=reg_layer_2_w8[0]; -assign layer_3_w8[1]=reg_layer_2_w8[1]; -assign layer_3_w9[0]=reg_layer_2_w9[0]; -assign layer_3_w9[1]=reg_layer_2_w9[1]; -assign layer_3_w10[0]=reg_layer_2_w10[0]; -assign layer_3_w10[1]=reg_layer_2_w10[1]; -full_adder layer_3_full_adder_0( -reg_layer_2_w11[0], -reg_layer_2_w11[1], -reg_layer_2_w11[2], -layer_3_w11[0], -layer_3_w12[0] -); -assign layer_3_w11[1]=reg_layer_2_w11[3]; -full_adder layer_3_full_adder_1( -reg_layer_2_w12[0], -reg_layer_2_w12[1], -reg_layer_2_w12[2], -layer_3_w12[1], -layer_3_w13[0] -); -full_adder layer_3_full_adder_2( -reg_layer_2_w13[0], -reg_layer_2_w13[1], -reg_layer_2_w13[2], -layer_3_w13[1], -layer_3_w14[0] -); -full_adder layer_3_full_adder_3( -reg_layer_2_w14[0], -reg_layer_2_w14[1], -reg_layer_2_w14[2], -layer_3_w14[1], -layer_3_w15[0] -); -full_adder layer_3_full_adder_4( -reg_layer_2_w15[0], -reg_layer_2_w15[1], -reg_layer_2_w15[2], -layer_3_w15[1], -layer_3_w16[0] -); -full_adder layer_3_full_adder_5( -reg_layer_2_w16[0], -reg_layer_2_w16[1], -reg_layer_2_w16[2], -layer_3_w16[1], -layer_3_w17[0] -); -assign layer_3_w16[2]=reg_layer_2_w16[3]; -full_adder layer_3_full_adder_6( -reg_layer_2_w17[0], -reg_layer_2_w17[1], -reg_layer_2_w17[2], -layer_3_w17[1], -layer_3_w18[0] -); -full_adder layer_3_full_adder_7( -reg_layer_2_w18[0], -reg_layer_2_w18[1], -reg_layer_2_w18[2], -layer_3_w18[1], -layer_3_w19[0] -); -assign layer_3_w18[2]=reg_layer_2_w18[3]; -full_adder layer_3_full_adder_8( -reg_layer_2_w19[0], -reg_layer_2_w19[1], -reg_layer_2_w19[2], -layer_3_w19[1], -layer_3_w20[0] -); -full_adder layer_3_full_adder_9( -reg_layer_2_w20[0], -reg_layer_2_w20[1], -reg_layer_2_w20[2], -layer_3_w20[1], -layer_3_w21[0] -); -assign layer_3_w20[2]=reg_layer_2_w20[3]; -full_adder layer_3_full_adder_10( -reg_layer_2_w21[0], -reg_layer_2_w21[1], -reg_layer_2_w21[2], -layer_3_w21[1], -layer_3_w22[0] -); -assign layer_3_w22[1]=reg_layer_2_w22[0]; -assign layer_3_w22[2]=reg_layer_2_w22[1]; -assign layer_3_w23[0]=reg_layer_2_w23[0]; -assign layer_3_w23[1]=reg_layer_2_w23[1]; -full_adder layer_3_full_adder_11( -reg_layer_2_w24[0], -reg_layer_2_w24[1], -reg_layer_2_w24[2], -layer_3_w24, -layer_3_w25[0] -); -assign layer_3_w25[1]=reg_layer_2_w25[0]; -assign layer_3_w25[2]=reg_layer_2_w25[1]; -full_adder layer_3_full_adder_12( -reg_layer_2_w26[0], -reg_layer_2_w26[1], -reg_layer_2_w26[2], -layer_3_w26, -layer_3_w27[0] -); -assign layer_3_w27[1]=reg_layer_2_w27[0]; -assign layer_3_w27[2]=reg_layer_2_w27[1]; -assign layer_3_w28=reg_layer_2_w28; -full_adder layer_3_full_adder_13( -reg_layer_2_w29[0], -reg_layer_2_w29[1], -reg_layer_2_w29[2], -layer_3_w29, -layer_3_w30[0] -); -assign layer_3_w30[1]=reg_layer_2_w30; -assign layer_3_w31=reg_layer_2_w31; - -//layer 4 -wire layer_4_w0[1:0]; -wire layer_4_w1; -wire layer_4_w2; -wire layer_4_w3[1:0]; -wire layer_4_w4[1:0]; -wire layer_4_w5[1:0]; -wire layer_4_w6[1:0]; -wire layer_4_w7[1:0]; -wire layer_4_w8[1:0]; -wire layer_4_w9[1:0]; -wire layer_4_w10[1:0]; -wire layer_4_w11[1:0]; -wire layer_4_w12[1:0]; -wire layer_4_w13[1:0]; -wire layer_4_w14[1:0]; -wire layer_4_w15[1:0]; -wire layer_4_w16[1:0]; -wire layer_4_w17[1:0]; -wire layer_4_w18[1:0]; -wire layer_4_w19[1:0]; -wire layer_4_w20[1:0]; -wire layer_4_w21[1:0]; -wire layer_4_w22[1:0]; -wire layer_4_w23[1:0]; -wire layer_4_w24[1:0]; -wire layer_4_w25; -wire layer_4_w26[1:0]; -wire layer_4_w27; -wire layer_4_w28[1:0]; -wire layer_4_w29; -wire layer_4_w30[1:0]; -wire layer_4_w31; -assign layer_4_w0[0]=layer_3_w0[0]; -assign layer_4_w0[1]=layer_3_w0[1]; -assign layer_4_w1=layer_3_w1; -full_adder layer_4_full_adder_0( -layer_3_w2[0], -layer_3_w2[1], -layer_3_w2[2], -layer_4_w2, -layer_4_w3[0] -); -half_adder layer_4_half_adder_0( -layer_3_w3[0], -layer_3_w3[1], -layer_4_w3[1], -layer_4_w4[0] -); -half_adder layer_4_half_adder_1( -layer_3_w4[0], -layer_3_w4[1], -layer_4_w4[1], -layer_4_w5[0] -); -half_adder layer_4_half_adder_2( -layer_3_w5[0], -layer_3_w5[1], -layer_4_w5[1], -layer_4_w6[0] -); -half_adder layer_4_half_adder_3( -layer_3_w6[0], -layer_3_w6[1], -layer_4_w6[1], -layer_4_w7[0] -); -half_adder layer_4_half_adder_4( -layer_3_w7[0], -layer_3_w7[1], -layer_4_w7[1], -layer_4_w8[0] -); -half_adder layer_4_half_adder_5( -layer_3_w8[0], -layer_3_w8[1], -layer_4_w8[1], -layer_4_w9[0] -); -half_adder layer_4_half_adder_6( -layer_3_w9[0], -layer_3_w9[1], -layer_4_w9[1], -layer_4_w10[0] -); -half_adder layer_4_half_adder_7( -layer_3_w10[0], -layer_3_w10[1], -layer_4_w10[1], -layer_4_w11[0] -); -half_adder layer_4_half_adder_8( -layer_3_w11[0], -layer_3_w11[1], -layer_4_w11[1], -layer_4_w12[0] -); -half_adder layer_4_half_adder_9( -layer_3_w12[0], -layer_3_w12[1], -layer_4_w12[1], -layer_4_w13[0] -); -half_adder layer_4_half_adder_10( -layer_3_w13[0], -layer_3_w13[1], -layer_4_w13[1], -layer_4_w14[0] -); -half_adder layer_4_half_adder_11( -layer_3_w14[0], -layer_3_w14[1], -layer_4_w14[1], -layer_4_w15[0] -); -half_adder layer_4_half_adder_12( -layer_3_w15[0], -layer_3_w15[1], -layer_4_w15[1], -layer_4_w16[0] -); -full_adder layer_4_full_adder_1( -layer_3_w16[0], -layer_3_w16[1], -layer_3_w16[2], -layer_4_w16[1], -layer_4_w17[0] -); -half_adder layer_4_half_adder_13( -layer_3_w17[0], -layer_3_w17[1], -layer_4_w17[1], -layer_4_w18[0] -); -full_adder layer_4_full_adder_2( -layer_3_w18[0], -layer_3_w18[1], -layer_3_w18[2], -layer_4_w18[1], -layer_4_w19[0] -); -half_adder layer_4_half_adder_14( -layer_3_w19[0], -layer_3_w19[1], -layer_4_w19[1], -layer_4_w20[0] -); -full_adder layer_4_full_adder_3( -layer_3_w20[0], -layer_3_w20[1], -layer_3_w20[2], -layer_4_w20[1], -layer_4_w21[0] -); -half_adder layer_4_half_adder_15( -layer_3_w21[0], -layer_3_w21[1], -layer_4_w21[1], -layer_4_w22[0] -); -full_adder layer_4_full_adder_4( -layer_3_w22[0], -layer_3_w22[1], -layer_3_w22[2], -layer_4_w22[1], -layer_4_w23[0] -); -half_adder layer_4_half_adder_16( -layer_3_w23[0], -layer_3_w23[1], -layer_4_w23[1], -layer_4_w24[0] -); -assign layer_4_w24[1]=layer_3_w24; -full_adder layer_4_full_adder_5( -layer_3_w25[0], -layer_3_w25[1], -layer_3_w25[2], -layer_4_w25, -layer_4_w26[0] -); -assign layer_4_w26[1]=layer_3_w26; -full_adder layer_4_full_adder_6( -layer_3_w27[0], -layer_3_w27[1], -layer_3_w27[2], -layer_4_w27, -layer_4_w28[0] -); -assign layer_4_w28[1]=layer_3_w28; -assign layer_4_w29=layer_3_w29; -assign layer_4_w30[0]=layer_3_w30[0]; -assign layer_4_w30[1]=layer_3_w30[1]; -assign layer_4_w31=layer_3_w31; - -//group reduction results into 2 numbers -wire [31:0]A,B; -assign A[0]=layer_4_w0[0]; -assign B[0]=layer_4_w0[1]; -assign A[1]=layer_4_w1; -assign B[1]=0; -assign A[2]=layer_4_w2; -assign B[2]=0; -assign A[3]=layer_4_w3[0]; -assign B[3]=layer_4_w3[1]; -assign A[4]=layer_4_w4[0]; -assign B[4]=layer_4_w4[1]; -assign A[5]=layer_4_w5[0]; -assign B[5]=layer_4_w5[1]; -assign A[6]=layer_4_w6[0]; -assign B[6]=layer_4_w6[1]; -assign A[7]=layer_4_w7[0]; -assign B[7]=layer_4_w7[1]; -assign A[8]=layer_4_w8[0]; -assign B[8]=layer_4_w8[1]; -assign A[9]=layer_4_w9[0]; -assign B[9]=layer_4_w9[1]; -assign A[10]=layer_4_w10[0]; -assign B[10]=layer_4_w10[1]; -assign A[11]=layer_4_w11[0]; -assign B[11]=layer_4_w11[1]; -assign A[12]=layer_4_w12[0]; -assign B[12]=layer_4_w12[1]; -assign A[13]=layer_4_w13[0]; -assign B[13]=layer_4_w13[1]; -assign A[14]=layer_4_w14[0]; -assign B[14]=layer_4_w14[1]; -assign A[15]=layer_4_w15[0]; -assign B[15]=layer_4_w15[1]; -assign A[16]=layer_4_w16[0]; -assign B[16]=layer_4_w16[1]; -assign A[17]=layer_4_w17[0]; -assign B[17]=layer_4_w17[1]; -assign A[18]=layer_4_w18[0]; -assign B[18]=layer_4_w18[1]; -assign A[19]=layer_4_w19[0]; -assign B[19]=layer_4_w19[1]; -assign A[20]=layer_4_w20[0]; -assign B[20]=layer_4_w20[1]; -assign A[21]=layer_4_w21[0]; -assign B[21]=layer_4_w21[1]; -assign A[22]=layer_4_w22[0]; -assign B[22]=layer_4_w22[1]; -assign A[23]=layer_4_w23[0]; -assign B[23]=layer_4_w23[1]; -assign A[24]=layer_4_w24[0]; -assign B[24]=layer_4_w24[1]; -assign A[25]=layer_4_w25; -assign B[25]=0; -assign A[26]=layer_4_w26[0]; -assign B[26]=layer_4_w26[1]; -assign A[27]=layer_4_w27; -assign B[27]=0; -assign A[28]=layer_4_w28[0]; -assign B[28]=layer_4_w28[1]; -assign A[29]=layer_4_w29; -assign B[29]=0; -assign A[30]=layer_4_w30[0]; -assign B[30]=layer_4_w30[1]; -assign A[31]=layer_4_w31; -assign B[31]=0; - -wire carry; -adder_32bit adder_32bit( -A, -B, -1'b0, -o_product, -carry -); - - -endmodule diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v deleted file mode 100644 index bd68e0204..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/CLA_fixed.v +++ /dev/null @@ -1,259 +0,0 @@ -/*Carry look-ahead adder -Author: Zhu Xu -Email: m99a1@yahoo.cn -*/ - -module operator_A( -input A, -input B, -output P, -output G -); - -assign P=A^B; -assign G=A&B; - -endmodule - -module operator_B( -input P,G,P1,G1, -output Po,Go -); - -assign Po=P&P1; -assign Go=G|(P&G1); - -endmodule - -module operator_C( -input P,G,G1, -output Go -); - -assign Go=G|(P&G1); - -endmodule - - -/* 32-bit prefix-2 Han-Carlson adder -stage 0: Number of Generation=32, NP=32, NOA=32, NOB=0, NOC=0. -stage 1: NG=16, NP=15, NOA=0, NOB=15, NOC=1. -stage 2: NG=16, NP=14, NOA=0, NOB=14, NOC=1. -stage 3: NG=16, NP=12, NOA=0, NOB=12, NOC=2. -stage 4: NG=16, NP=8, NOA=0, NOB=8, NOC=4. -stage 5: NG=16, NP=0, NOA=0, NOB=0, NOC=8. -stage 6; NG=32, NP=0, NOA=0, NOB=0, NOC=15. -*/ -module adder_32bit( -input [31:0]i_a,i_b, -input i_c, -output [31:0]o_s, -output o_c -); - -//stage 0 -wire [31:0]P0,G0; -operator_A operator_A_0(i_a[0],i_b[0],P0[0],G0[0]); -operator_A operator_A_1(i_a[1],i_b[1],P0[1],G0[1]); -operator_A operator_A_2(i_a[2],i_b[2],P0[2],G0[2]); -operator_A operator_A_3(i_a[3],i_b[3],P0[3],G0[3]); -operator_A operator_A_4(i_a[4],i_b[4],P0[4],G0[4]); -operator_A operator_A_5(i_a[5],i_b[5],P0[5],G0[5]); -operator_A operator_A_6(i_a[6],i_b[6],P0[6],G0[6]); -operator_A operator_A_7(i_a[7],i_b[7],P0[7],G0[7]); -operator_A operator_A_8(i_a[8],i_b[8],P0[8],G0[8]); -operator_A operator_A_9(i_a[9],i_b[9],P0[9],G0[9]); -operator_A operator_A_10(i_a[10],i_b[10],P0[10],G0[10]); -operator_A operator_A_11(i_a[11],i_b[11],P0[11],G0[11]); -operator_A operator_A_12(i_a[12],i_b[12],P0[12],G0[12]); -operator_A operator_A_13(i_a[13],i_b[13],P0[13],G0[13]); -operator_A operator_A_14(i_a[14],i_b[14],P0[14],G0[14]); -operator_A operator_A_15(i_a[15],i_b[15],P0[15],G0[15]); -operator_A operator_A_16(i_a[16],i_b[16],P0[16],G0[16]); -operator_A operator_A_17(i_a[17],i_b[17],P0[17],G0[17]); -operator_A operator_A_18(i_a[18],i_b[18],P0[18],G0[18]); -operator_A operator_A_19(i_a[19],i_b[19],P0[19],G0[19]); -operator_A operator_A_20(i_a[20],i_b[20],P0[20],G0[20]); -operator_A operator_A_21(i_a[21],i_b[21],P0[21],G0[21]); -operator_A operator_A_22(i_a[22],i_b[22],P0[22],G0[22]); -operator_A operator_A_23(i_a[23],i_b[23],P0[23],G0[23]); -operator_A operator_A_24(i_a[24],i_b[24],P0[24],G0[24]); -operator_A operator_A_25(i_a[25],i_b[25],P0[25],G0[25]); -operator_A operator_A_26(i_a[26],i_b[26],P0[26],G0[26]); -operator_A operator_A_27(i_a[27],i_b[27],P0[27],G0[27]); -operator_A operator_A_28(i_a[28],i_b[28],P0[28],G0[28]); -operator_A operator_A_29(i_a[29],i_b[29],P0[29],G0[29]); -operator_A operator_A_30(i_a[30],i_b[30],P0[30],G0[30]); -operator_A operator_A_31(i_a[31],i_b[31],P0[31],G0[31]); - -//stage 1 -wire [15:0]G1; -wire [15:1]P1; -operator_C operator_C_stage_1_0(P0[0],G0[0],i_c,G1[0]); -operator_B operator_B_stage_1_1(P0[2],G0[2],P0[1],G0[1],P1[1],G1[1]); -operator_B operator_B_stage_1_2(P0[4],G0[4],P0[3],G0[3],P1[2],G1[2]); -operator_B operator_B_stage_1_3(P0[6],G0[6],P0[5],G0[5],P1[3],G1[3]); -operator_B operator_B_stage_1_4(P0[8],G0[8],P0[7],G0[7],P1[4],G1[4]); -operator_B operator_B_stage_1_5(P0[10],G0[10],P0[9],G0[9],P1[5],G1[5]); -operator_B operator_B_stage_1_6(P0[12],G0[12],P0[11],G0[11],P1[6],G1[6]); -operator_B operator_B_stage_1_7(P0[14],G0[14],P0[13],G0[13],P1[7],G1[7]); -operator_B operator_B_stage_1_8(P0[16],G0[16],P0[15],G0[15],P1[8],G1[8]); -operator_B operator_B_stage_1_9(P0[18],G0[18],P0[17],G0[17],P1[9],G1[9]); -operator_B operator_B_stage_1_10(P0[20],G0[20],P0[19],G0[19],P1[10],G1[10]); -operator_B operator_B_stage_1_11(P0[22],G0[22],P0[21],G0[21],P1[11],G1[11]); -operator_B operator_B_stage_1_12(P0[24],G0[24],P0[23],G0[23],P1[12],G1[12]); -operator_B operator_B_stage_1_13(P0[26],G0[26],P0[25],G0[25],P1[13],G1[13]); -operator_B operator_B_stage_1_14(P0[28],G0[28],P0[27],G0[27],P1[14],G1[14]); -operator_B operator_B_stage_1_15(P0[30],G0[30],P0[29],G0[29],P1[15],G1[15]); - - - -//stage 2 -wire [15:0]G2; -wire [15:2]P2; -assign G2[0]=G1[0]; -operator_C operator_C_stage_2_1(P1[1],G1[1],G1[0],G2[1]); -operator_B operator_B_stage_2_2(P1[2], G1[2],P1[1],G1[1],P2[2],G2[2]); -operator_B operator_B_stage_2_3(P1[3], G1[3],P1[2],G1[2],P2[3],G2[3]); -operator_B operator_B_stage_2_4(P1[4], G1[4],P1[3],G1[3],P2[4],G2[4]); -operator_B operator_B_stage_2_5(P1[5], G1[5],P1[4],G1[4],P2[5],G2[5]); -operator_B operator_B_stage_2_6(P1[6], G1[6],P1[5],G1[5],P2[6],G2[6]); -operator_B operator_B_stage_2_7(P1[7], G1[7],P1[6],G1[6],P2[7],G2[7]); -operator_B operator_B_stage_2_8(P1[8], G1[8],P1[7],G1[7],P2[8],G2[8]); -operator_B operator_B_stage_2_9(P1[9], G1[9],P1[8],G1[8],P2[9],G2[9]); -operator_B operator_B_stage_2_10(P1[10], G1[10],P1[9],G1[9],P2[10],G2[10]); -operator_B operator_B_stage_2_11(P1[11], G1[11],P1[10],G1[10],P2[11],G2[11]); -operator_B operator_B_stage_2_12(P1[12], G1[12],P1[11],G1[11],P2[12],G2[12]); -operator_B operator_B_stage_2_13(P1[13], G1[13],P1[12],G1[12],P2[13],G2[13]); -operator_B operator_B_stage_2_14(P1[14], G1[14],P1[13],G1[13],P2[14],G2[14]); -operator_B operator_B_stage_2_15(P1[15], G1[15],P1[14],G1[14],P2[15],G2[15]); - -//stage 3 -wire [15:0]G3; -wire [15:4]P3; -assign G3[0]=G2[0]; -assign G3[1]=G2[1]; -operator_C operator_C_stage_3_2(P2[2],G2[2],G2[0],G3[2]); -operator_C operator_C_stage_3_3(P2[3],G2[3],G2[1],G3[3]); -operator_B operator_B_stage_3_4(P2[4], G2[4],P2[2],G2[2],P3[4],G3[4]); -operator_B operator_B_stage_3_5(P2[5], G2[5],P2[3],G2[3],P3[5],G3[5]); -operator_B operator_B_stage_3_6(P2[6], G2[6],P2[4],G2[4],P3[6],G3[6]); -operator_B operator_B_stage_3_7(P2[7], G2[7],P2[5],G2[5],P3[7],G3[7]); -operator_B operator_B_stage_3_8(P2[8], G2[8],P2[6],G2[6],P3[8],G3[8]); -operator_B operator_B_stage_3_9(P2[9], G2[9],P2[7],G2[7],P3[9],G3[9]); -operator_B operator_B_stage_3_10(P2[10], G2[10],P2[8],G2[8],P3[10],G3[10]); -operator_B operator_B_stage_3_11(P2[11], G2[11],P2[9],G2[9],P3[11],G3[11]); -operator_B operator_B_stage_3_12(P2[12], G2[12],P2[10],G2[10],P3[12],G3[12]); -operator_B operator_B_stage_3_13(P2[13], G2[13],P2[11],G2[11],P3[13],G3[13]); -operator_B operator_B_stage_3_14(P2[14], G2[14],P2[12],G2[12],P3[14],G3[14]); -operator_B operator_B_stage_3_15(P2[15], G2[15],P2[13],G2[13],P3[15],G3[15]); - -//stage 4 -wire [15:0]G4; -wire [15:8]P4; -assign G4[0]=G3[0]; -assign G4[1]=G3[1]; -assign G4[2]=G3[2]; -assign G4[3]=G3[3]; -operator_C operator_C_stage_4_4(P3[4],G3[4],G3[0],G4[4]); -operator_C operator_C_stage_4_5(P3[5],G3[5],G3[1],G4[5]); -operator_C operator_C_stage_4_6(P3[6],G3[6],G3[2],G4[6]); -operator_C operator_C_stage_4_7(P3[7],G3[7],G3[3],G4[7]); -operator_B operator_B_stage_4_8(P3[8], G3[8],P3[4],G3[4],P4[8],G4[8]); -operator_B operator_B_stage_4_9(P3[9], G3[9],P3[5],G3[5],P4[9],G4[9]); -operator_B operator_B_stage_4_10(P3[10], G3[10],P3[6],G3[6],P4[10],G4[10]); -operator_B operator_B_stage_4_11(P3[11], G3[11],P3[7],G3[7],P4[11],G4[11]); -operator_B operator_B_stage_4_12(P3[12], G3[12],P3[8],G3[8],P4[12],G4[12]); -operator_B operator_B_stage_4_13(P3[13], G3[13],P3[9],G3[9],P4[13],G4[13]); -operator_B operator_B_stage_4_14(P3[14], G3[14],P3[10],G3[10],P4[14],G4[14]); -operator_B operator_B_stage_4_15(P3[15], G3[15],P3[11],G3[11],P4[15],G4[15]); - -//stage 5 -wire [15:0]G5; -assign G5[0]=G4[0]; -assign G5[1]=G4[1]; -assign G5[2]=G4[2]; -assign G5[3]=G4[3]; -assign G5[4]=G4[4]; -assign G5[5]=G4[5]; -assign G5[6]=G4[6]; -assign G5[7]=G4[7]; -operator_C operator_C_stage_5_8(P4[8],G4[8],G4[0],G5[8]); -operator_C operator_C_stage_5_9(P4[9],G4[9],G4[1],G5[9]); -operator_C operator_C_stage_5_10(P4[10],G4[10],G4[2],G5[10]); -operator_C operator_C_stage_5_11(P4[11],G4[11],G4[3],G5[11]); -operator_C operator_C_stage_5_12(P4[12],G4[12],G4[4],G5[12]); -operator_C operator_C_stage_5_13(P4[13],G4[13],G4[5],G5[13]); -operator_C operator_C_stage_5_14(P4[14],G4[14],G4[6],G5[14]); -operator_C operator_C_stage_5_15(P4[15],G4[15],G4[7],G5[15]); - -//stage 6 -wire [31:0]G6; -assign G6[0]=G5[0]; -assign G6[2]=G5[1]; -assign G6[4]=G5[2]; -assign G6[6]=G5[3]; -assign G6[8]=G5[4]; -assign G6[10]=G5[5]; -assign G6[12]=G5[6]; -assign G6[14]=G5[7]; -assign G6[16]=G5[8]; -assign G6[18]=G5[9]; -assign G6[20]=G5[10]; -assign G6[22]=G5[11]; -assign G6[24]=G5[12]; -assign G6[26]=G5[13]; -assign G6[28]=G5[14]; -assign G6[30]=G5[15]; -operator_C operator_C_stage_6_0(P0[1],G0[1],G5[0],G6[1]); -operator_C operator_C_stage_6_1(P0[3],G0[3],G5[1],G6[3]); -operator_C operator_C_stage_6_2(P0[5],G0[5],G5[2],G6[5]); -operator_C operator_C_stage_6_3(P0[7],G0[7],G5[3],G6[7]); -operator_C operator_C_stage_6_4(P0[9],G0[9],G5[4],G6[9]); -operator_C operator_C_stage_6_5(P0[11],G0[11],G5[5],G6[11]); -operator_C operator_C_stage_6_6(P0[13],G0[13],G5[6],G6[13]); -operator_C operator_C_stage_6_7(P0[15],G0[15],G5[7],G6[15]); -operator_C operator_C_stage_6_8(P0[17],G0[17],G5[8],G6[17]); -operator_C operator_C_stage_6_9(P0[19],G0[19],G5[9],G6[19]); -operator_C operator_C_stage_6_10(P0[21],G0[21],G5[10],G6[21]); -operator_C operator_C_stage_6_11(P0[23],G0[23],G5[11],G6[23]); -operator_C operator_C_stage_6_12(P0[25],G0[25],G5[12],G6[25]); -operator_C operator_C_stage_6_13(P0[27],G0[27],G5[13],G6[27]); -operator_C operator_C_stage_6_14(P0[29],G0[29],G5[14],G6[29]); -operator_C operator_C_stage_6_15(P0[31],G0[31],G5[15],G6[31]); - -assign o_s[0]=P0[0]^i_c; -assign o_s[1]=P0[1]^G6[0]; -assign o_s[2]=P0[2]^G6[1]; -assign o_s[3]=P0[3]^G6[2]; -assign o_s[4]=P0[4]^G6[3]; -assign o_s[5]=P0[5]^G6[4]; -assign o_s[6]=P0[6]^G6[5]; -assign o_s[7]=P0[7]^G6[6]; -assign o_s[8]=P0[8]^G6[7]; -assign o_s[9]=P0[9]^G6[8]; -assign o_s[10]=P0[10]^G6[9]; -assign o_s[11]=P0[11]^G6[10]; -assign o_s[12]=P0[12]^G6[11]; -assign o_s[13]=P0[13]^G6[12]; -assign o_s[14]=P0[14]^G6[13]; -assign o_s[15]=P0[15]^G6[14]; -assign o_s[16]=P0[16]^G6[15]; -assign o_s[17]=P0[17]^G6[16]; -assign o_s[18]=P0[18]^G6[17]; -assign o_s[19]=P0[19]^G6[18]; -assign o_s[20]=P0[20]^G6[19]; -assign o_s[21]=P0[21]^G6[20]; -assign o_s[22]=P0[22]^G6[21]; -assign o_s[23]=P0[23]^G6[22]; -assign o_s[24]=P0[24]^G6[23]; -assign o_s[25]=P0[25]^G6[24]; -assign o_s[26]=P0[26]^G6[25]; -assign o_s[27]=P0[27]^G6[26]; -assign o_s[28]=P0[28]^G6[27]; -assign o_s[29]=P0[29]^G6[28]; -assign o_s[30]=P0[30]^G6[29]; -assign o_s[31]=P0[31]^G6[30]; -assign o_c=G6[31]; - -endmodule \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v deleted file mode 100644 index 086156ddd..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID.v +++ /dev/null @@ -1,434 +0,0 @@ -/* PID controller - -sigma=Ki*e(n)+sigma -u(n)=(Kp+Kd)*e(n)+sigma+Kd*(-e(n-1)) - -Data width of Wishbone slave port can be can be toggled between 64-bit, 32-bit and 16-bit. -Address width of Wishbone slave port can be can be modified by changing parameter adr_wb_nb. - -Wishbone compliant -Work as Wishbone slave, support Classic standard SINGLE/BLOCK READ/WRITE Cycle - -registers or wires -[15:0]kp,ki,kd,sp,pv; can be both read and written -[15:0]kpd; read only -[15:0]err[0:1]; read only -[15:0]mr,md; not accessable -[31:0]p,b; not accessable -[31:0]un,sigma; read only -RS write 0 to RS will reset err[0], OF, un and sigma - - - -[4:0]of; overflow register, read only through Wishbone interface, address: 0x40 -of[0]==1 : kpd overflow -of[1]==1 : err[0] overflow -of[2]==1 : err[1] overflow -of[3]==1 : un overflow -of[4]==1 : sigma overflow -[0:15]rl; read lock, when asserted corelated reagister can not be read through Wishbone interface -[0:7]wl; write lock, when asserted corelated reagister can not be written through Wishbone interface - - - -*/ - -`include "PID_defines.v" - -module PID #( -`ifdef wb_16bit -parameter wb_nb=16, -`endif -`ifdef wb_32bit -parameter wb_nb=32, -`endif -`ifdef wb_64bit -parameter wb_nb=64, -`endif - adr_wb_nb=16, - kp_adr = 0, - ki_adr = 1, - kd_adr = 2, - sp_adr = 3, - pv_adr = 4, - kpd_adr = 5, - err_0_adr = 6, - err_1_adr = 7, - un_adr = 8, - sigma_adr = 9, - of_adr = 10, - RS_adr = 11 -)( -input i_clk, -input i_rst, //reset when high -//Wishbone Slave port -input i_wb_cyc, -input i_wb_stb, -input i_wb_we, -input [adr_wb_nb-1:0]i_wb_adr, -input [wb_nb-1:0]i_wb_data, -output o_wb_ack, -output [wb_nb-1:0]o_wb_data, - -//u(n) output -output [31:0]o_un, -output o_valid -); - - - -reg [15:0]kp,ki,kd,sp,pv; -reg wla,wlb; // write locks -wire wlRS; -assign wlRS=wla|wlb; -wire [0:7]wl={{3{wla}},{2{wlb}},3'h0}; - -reg wack; //write acknowledged - -wire [2:0]adr; // address for write -`ifdef wb_16bit -assign adr=i_wb_adr[3:1]; -`endif -`ifdef wb_32bit -assign adr=i_wb_adr[4:2]; -`endif -`ifdef wb_64bit -assign adr=i_wb_adr[5:3]; -`endif - -wire [3:0]adr_1; // address for read -`ifdef wb_32bit -assign adr_1=i_wb_adr[5:2]; -`endif -`ifdef wb_16bit -assign adr_1=i_wb_adr[4:1]; -`endif -`ifdef wb_64bit -assign adr_1=i_wb_adr[6:3]; -`endif - - -wire we; // write enable -assign we=i_wb_cyc&i_wb_we&i_wb_stb; -wire re; //read enable -assign re=i_wb_cyc&(~i_wb_we)&i_wb_stb; - -reg state_0; //state machine No.1's state register - -wire adr_check_1; // A '1' means address is within the range of adr_1 -`ifdef wb_32bit -assign adr_check_1=i_wb_adr[adr_wb_nb-1:6]==0; -`endif -`ifdef wb_16bit -assign adr_check_1=i_wb_adr[adr_wb_nb-1:5]==0; -`endif -`ifdef wb_64bit -assign adr_check_1=i_wb_adr[adr_wb_nb-1:7]==0; -`endif - -wire adr_check; // A '1' means address is within the range of adr -`ifdef wb_16bit -assign adr_check=i_wb_adr[4]==0&&adr_check_1; -`endif -`ifdef wb_32bit -assign adr_check=i_wb_adr[5]==0&&adr_check_1; -`endif -`ifdef wb_64bit -assign adr_check=i_wb_adr[6]==0&&adr_check_1; -`endif - - //state machine No.1 -reg RS; -always@(posedge i_clk or posedge i_rst) - if(i_rst)begin - state_0<=0; - wack<=0; - kp<=0; - ki<=0; - kd<=0; - sp<=0; - pv<=0; - RS<=0; - end - else begin - if(wack&&(!i_wb_stb)) wack<=0; - if(RS)RS<=0; - case(state_0) - 0: begin - if(we&&(!wack)) state_0<=1; - end - 1: begin - if(adr_check)begin - if(!wl[adr])begin - wack<=1; - state_0<=0; - case(adr) - 0: begin - kp<=i_wb_data[15:0]; - end - 1: begin - ki<=i_wb_data[15:0]; - end - 2: begin - kd<=i_wb_data[15:0]; - end - 3: begin - sp<=i_wb_data[15:0]; - end - 4: begin - pv<=i_wb_data[15:0]; - end - endcase - - end - end - else if((adr_1==RS_adr)&&(!wlRS)&&(i_wb_data==0))begin - wack<=1; - state_0<=0; - RS<=1; - end - else begin - wack<=1; - state_0<=0; - end - end - endcase - end - - - //state machine No.2 -reg [9:0]state_1; - -wire update_kpd; -assign update_kpd=wack&&(~adr[2])&&(~adr[0])&&adr_check; //adr==0||adr==2 - -wire update_esu; //update e(n), sigma and u(n) -assign update_esu=wack&&(adr==4)&&adr_check; - -reg rla; // read locks -reg rlb; - - -reg [4:0]of; -reg [15:0]kpd; -reg [15:0]err[0:1]; - -wire [15:0]mr,md; - -reg [31:0]p; -reg [31:0]a,sigma,un; - -reg cout; -wire cin; -wire [31:0]sum; -wire [31:0]product; - -reg start; //start signal for multiplier - -reg [1:0]mr_index; -reg [1:0]md_index; -assign mr= mr_index==1?kpd: - mr_index==2?kd:ki; -assign md= md_index==2?err[1]: - md_index==1?err[0]:sum[15:0]; - - -wire of_addition[0:1]; -assign of_addition[0]=(p[15]&&a[15]&&(!sum[15]))||((!p[15])&&(!a[15])&&sum[15]); -assign of_addition[1]=(p[31]&&a[31]&&(!sum[31]))||((!p[31])&&(!a[31])&&sum[31]); - -always@(posedge i_clk or posedge i_rst) - if(i_rst)begin - state_1<=12'b000000000001; - wla<=0; - wlb<=0; - rla<=0; - rlb<=0; - of<=0; - kpd<=0; - err[0]<=0; - err[1]<=0; - p<=0; - a<=0; - sigma<=0; - un<=0; - start<=0; - mr_index<=0; - md_index<=0; - cout<=0; - end - else begin - case(state_1) - 10'b0000000001: begin - if(update_kpd)begin - state_1<=10'b0000000010; - wla<=1; - rla<=1; - end - else if(update_esu)begin - state_1<=10'b0000001000; - wla<=1; - wlb<=1; - rlb<=1; - end - else if(RS)begin //start a new sequance of U(n) - un<=0; - sigma<=0; - of<=0; - err[0]<=0; - end - end - 10'b0000000010: begin - p<={{16{kp[15]}},kp}; - a<={{16{kd[15]}},kd}; - state_1<=10'b0000000100; - end - 10'b0000000100: begin - kpd<=sum[15:0]; - wla<=0; - rla<=0; - of[0]<=of_addition[0]; - state_1<=10'b0000000001; - end - 10'b0000001000: begin - p<={{16{sp[15]}},sp}; - a<={{16{~pv[15]}},~pv}; - cout<=1; - start<=1; // start calculate err0 * ki - state_1<=10'b0000010000; - end - 10'b0000010000: begin - err[0]<=sum[15:0]; - of[1]<=of_addition[0]; - of[2]<=of[1]; - p<={{16{~err[0][15]}},~err[0]}; - a<={31'b0,1'b1}; - cout<=0; - mr_index<=1; // start calculate err0 * kpd - md_index<=1; - state_1<=10'b0000100000; - end - 10'b0000100000: begin - err[1]<=sum[15:0]; - mr_index<=2; // start calculate err1 * kd - md_index<=2; - state_1<=10'b0001000000; - end - 10'b0001000000: begin - mr_index<=0; - md_index<=0; - start<=0; - p<=product; // start calculate err0*ki + sigma_last - a<=sigma; - state_1<=10'b0010000000; - end - 10'b0010000000: begin - a<=sum; // start calculate err0*kpd + sigma_recent - sigma<=sum; - of[3]<=of[4]|of_addition[1]; - of[4]<=of[4]|of_addition[1]; - p<=product; - state_1<=10'b0100000000; - end - 10'b0100000000: begin - a<=sum; // start calculate err0*kpd + sigma_recent+err1*kd - of[3]<=of[3]|of_addition[1]; - p<=product; - state_1<=10'b1000000000; - end - 10'b1000000000: begin - un<=sum; - of[3]<=of[3]|of_addition[1]; - state_1<=10'b0000000001; - wla<=0; - wlb<=0; - rlb<=0; - end - endcase - end - - -wire ready; -multiplier_16x16bit_pipelined multiplier_16x16bit_pipelined( -i_clk, -~i_rst, -start, -md, -mr, -product, -ready -); - -adder_32bit adder_32bit_0( -a, -p, -cout, -sum, -cin -); - - -wire [wb_nb-1:0]rdata[0:15]; //wishbone read data array -`ifdef wb_16bit -assign rdata[0]=kp; -assign rdata[1]=ki; -assign rdata[2]=kd; -assign rdata[3]=sp; -assign rdata[4]=pv; -assign rdata[5]=kpd; -assign rdata[6]=err[0]; -assign rdata[7]=err[1]; -assign rdata[8]=un[15:0]; -assign rdata[9]=sigma[15:0]; -assign rdata[10]={11'b0,of}; -`endif - -`ifdef wb_32bit -assign rdata[0]={{16{kp[15]}},kp}; -assign rdata[1]={{16{ki[15]}},ki}; -assign rdata[2]={{16{kd[15]}},kd}; -assign rdata[3]={{16{sp[15]}},sp}; -assign rdata[4]={{16{pv[15]}},pv}; -assign rdata[5]={{16{kpd[15]}},kpd}; -assign rdata[6]={{16{err[0][15]}},err[0]}; -assign rdata[7]={{16{err[1][15]}},err[1]}; -assign rdata[8]=un; -assign rdata[9]=sigma; -assign rdata[10]={27'b0,of}; -`endif - -`ifdef wb_64bit -assign rdata[0]={{48{kp[15]}},kp}; -assign rdata[1]={{48{ki[15]}},ki}; -assign rdata[2]={{48{kd[15]}},kd}; -assign rdata[3]={{48{sp[15]}},sp}; -assign rdata[4]={{48{pv[15]}},pv}; -assign rdata[5]={{48{kpd[15]}},kpd}; -assign rdata[6]={{48{err[0][15]}},err[0]}; -assign rdata[7]={{48{err[1][15]}},err[1]}; -assign rdata[8]={{32{un[31]}},un}; -assign rdata[9]={{32{sigma[31]}},sigma}; -assign rdata[10]={59'b0,of}; -`endif - -assign rdata[11]=0; -assign rdata[12]=0; -assign rdata[13]=0; -assign rdata[14]=0; -assign rdata[15]=0; - - -wire [0:15]rl; -assign rl={5'b0,rla,{4{rlb}},rla|rlb,5'b0}; - -wire rack; // wishbone read acknowledged -assign rack=(re&adr_check_1&(~rl[adr_1]))|(re&(~adr_check_1)); - -assign o_wb_ack=(wack|rack)&i_wb_stb; - -assign o_wb_data=adr_check_1?rdata[adr_1]:0; -assign o_un=un; -assign o_valid=~rlb; - - -endmodule \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v deleted file mode 100644 index a43f6b38d..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/PID_defines.v +++ /dev/null @@ -1,8 +0,0 @@ -//`define wb_16bit -`define wb_32bit -//`define wb_64bit - - -//`define PID_test - -//`define PID_direct_test \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v deleted file mode 100644 index f33b3d80e..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller/PID/booth.v +++ /dev/null @@ -1,37 +0,0 @@ -/*Booth Encoder -Author: Zhu Xu -Email: m99a1@yahoo.cn -*/ -module booth_radix4( -input [2:0]codes, -output zero, -output double, -output negation -); - -wire A; -assign A=codes[2]; -wire B; -assign B=codes[1]; -wire C; -assign C=codes[0]; -wire nB,nC,nA; -assign nB=~B; -assign nC=~C; -assign nA=~A; - -wire BC; -assign BC=B&C; -wire nBnC; -assign nBnC=nB&nC; -wire nBanC; -assign nBanC=nB|nC; - -assign double=(nBnC&A)|(BC&nA); -assign negation=A&nBanC; -assign zero=(A&BC)|(nA&nBnC); - - - - -endmodule \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v deleted file mode 100644 index ff94461cd..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/delay_gen_ihd_ipd_isd.v +++ /dev/null @@ -1,207 +0,0 @@ -//================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// ------------------------------------------------------------------ -// Copyright (c) 2014 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. - -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// - - -module delay_gen_ihd_ipd_isd( - input clk, - input rst, - input start_stop, - input [15:0] isd_val, - input [15:0] ipd_val, - input config_reg_done, - input symbol_shift_done, - input packet_shift_done, - input hop_shift_done, - output reg isd_delay_en, - output reg ipd_delay_en -); - -reg [15:0] isd_val_temp; -reg [15:0] ipd_val_temp; -reg [15:0] isd_count; -reg [15:0] ipd_count; -wire [20:0] max_count; -wire [20:0] max_count_pkt /* synthesis syn_multstyle = logic */; -reg clk_count,clk_count_pkt; -reg count_done,count_done_pkt; - -parameter const_fact=20; -assign max_count=isd_val_temp * const_fact; -assign max_count_pkt=ipd_val_temp * const_fact; - -//wire count_enable,count_enable_pkt; -reg count_enable,count_enable_pkt; -//wire config_done; -//assign config_done= !rst_n ? 0 : config_reg_done ? 1 : config_done; //orignal -//assign count_enable= rst ? 0 : count_done ? 0 : symbol_shift_done ? 1 : count_enable; //orignal -//assign count_enable_pkt= rst ? 0 : count_done_pkt ? 0 : (packet_shift_done || hop_shift_done) ? 1 : count_enable_pkt; - -//assign isd_delay_en=symbol_shift_done ? 1 : (isd_count==max_count-1) : - -///////**********modified 11/feb/2014*************** ///////// - always @(posedge clk or posedge rst) begin - if(rst || !start_stop) begin - count_enable=0; - end - else begin - if(count_done) - count_enable=0; - else if(symbol_shift_done) - count_enable=1; - else - count_enable=count_enable; - - end -end - -always @(posedge clk or posedge rst) begin - if(rst || !start_stop) begin - count_enable_pkt=0; - end - else begin - if(count_done_pkt) - count_enable_pkt=0; - else if(packet_shift_done || hop_shift_done) - count_enable_pkt=1; - else - count_enable_pkt=count_enable_pkt; - end -end - -/////////////////******************************////////// - - - - -///////////////////////symbol//////////////////////////////////// -always @(posedge clk or posedge rst) begin - if(rst || !start_stop) begin - isd_count<=0; - count_done<=0; - isd_delay_en<=0; - end - else begin - count_done<=0; - if(count_enable) begin - if(isd_count==max_count) begin - isd_count<=0; - count_done<=1; - isd_delay_en<=0; - end - else begin - isd_delay_en<=1; - isd_count<=isd_count+1; - end - end - else begin - isd_delay_en<=0; - isd_count<=0; - end - end -end - -always @(posedge clk or posedge rst) begin - if(rst || !start_stop) begin - isd_val_temp<=0; - clk_count<=0; - end - else begin - if(!config_reg_done) begin - isd_val_temp<=isd_val; - clk_count<=0; - end - else if(config_reg_done) begin - clk_count<=clk_count+1; - isd_val_temp<=isd_val; - end - else begin - isd_val_temp<=isd_val_temp; - end - end -end -///////////////packet////////////////////// -always @(posedge clk or posedge rst) begin - if(rst || !start_stop) begin - ipd_count<=0; - count_done_pkt<=0; - ipd_delay_en<=0; - end - else begin - count_done_pkt<=0; - if(count_enable_pkt) begin - if(ipd_count==max_count_pkt) begin - ipd_count<=0; - count_done_pkt<=1; - ipd_delay_en<=0; - end - else begin - ipd_delay_en<=1; - ipd_count<=ipd_count+1; - end - end - else begin - ipd_delay_en<=0; - ipd_count<=0; - end - end -end - -always @(posedge clk or posedge rst) begin - if(rst || !start_stop) begin - ipd_val_temp<=0; - clk_count_pkt<=0; - end -else begin - if(!config_reg_done) begin - ipd_val_temp<=ipd_val; - clk_count_pkt<=0; - end - else if(config_reg_done) begin - clk_count_pkt<=clk_count_pkt+1; - ipd_val_temp<=ipd_val; - end - else begin // if(!config_reg_done) begin - ipd_val_temp<=ipd_val_temp; - end - end -end - -endmodule diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v deleted file mode 100644 index a1ccc5fdc..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_defines.v +++ /dev/null @@ -1,369 +0,0 @@ -//================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// ------------------------------------------------------------------ -// Copyright (c) 2014 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. - -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// - - - -/*********************************************************************** - * * - * EFB REGISTER SET * - * * - ***********************************************************************/ - - -`define MICO_EFB_I2C_CR 8'h08 -`define MICO_EFB_I2C_CMDR 8'h09 -`define MICO_EFB_I2C_BLOR 8'h0a -`define MICO_EFB_I2C_BHIR 8'h0b -`define MICO_EFB_I2C_TXDR 8'h0d -`define MICO_EFB_I2C_SR 8'h0c -`define MICO_EFB_I2C_GCDR 8'h0f -`define MICO_EFB_I2C_RXDR 8'h0e -`define MICO_EFB_I2C_IRQSR 8'h06 -`define MICO_EFB_I2C_IRQENR 8'h09 - -/*********************************************************************** - * * - * EFB I2C CONTROLLER PHYSICAL DEVICE SPECIFIC INFORMATION * - * * - ***********************************************************************/ - - - -// Control Register Bit Masks -`define MICO_EFB_I2C_CR_I2CEN 8'h80 -`define MICO_EFB_I2C_CR_GCEN 8'h40 -`define MICO_EFB_I2C_CR_WKUPEN 8'h20 -// Status Register Bit Masks -`define MICO_EFB_I2C_SR_TIP 8'h80 -`define MICO_EFB_I2C_SR_BUSY 8'h40 -`define MICO_EFB_I2C_SR_RARC 8'h20 -`define MICO_EFB_I2C_SR_SRW 8'h10 -`define MICO_EFB_I2C_SR_ARBL 8'h08 -`define MICO_EFB_I2C_SR_TRRDY 8'h04 -`define MICO_EFB_I2C_SR_TROE 8'h02 -`define MICO_EFB_I2C_SR_HGC 8'h01 -// Command Register Bit Masks -`define MICO_EFB_I2C_CMDR_STA 8'h80 -`define MICO_EFB_I2C_CMDR_STO 8'h40 -`define MICO_EFB_I2C_CMDR_RD 8'h20 -`define MICO_EFB_I2C_CMDR_WR 8'h10 -`define MICO_EFB_I2C_CMDR_NACK 8'h08 -`define MICO_EFB_I2C_CMDR_CKSDIS 8'h04 - - -/*********************************************************************** - * * - * CODE SPECIFIC * - * * - ***********************************************************************/ - - `define ALL_ZERO 8'h00 - `define READ 1'b0 - `define READ 1'b0 - `define HIGH 1'b1 - `define WRITE 1'b1 - `define LOW 1'b0 - `define READ_STATUS 1'b0 - `define READ_DATA 1'b0 - -/*********************************************************************** - * * - * State Machine Variables * - * * - ***********************************************************************/ - -`define state0 8'd00 -`define state1 8'd01 -`define state2 8'd02 -`define state3 8'd03 -`define state4 8'd04 -`define state5 8'd05 -`define state6 8'd06 -`define state7 8'd07 -`define state8 8'd08 -`define state9 8'd09 -`define state10 8'd10 -`define state11 8'd11 -`define state12 8'd12 -`define state13 8'd13 -`define state14 8'd14 -`define state15 8'd15 -`define state16 8'd16 -`define state17 8'd17 -`define state18 8'd18 -`define state19 8'd19 -`define state20 8'd20 -`define state21 8'd21 -`define state22 8'd22 -`define state23 8'd23 -`define state24 8'd24 -`define state25 8'd25 -`define state26 8'd26 -`define state27 8'd27 -`define state28 8'd28 -`define state29 8'd29 -`define state30 8'd30 -`define state31 8'd31 -`define state32 8'd32 -`define state33 8'd33 -`define state34 8'd34 -`define state35 8'd35 -`define state36 8'd36 -`define state37 8'd37 -`define state38 8'd38 -`define state39 8'd39 -`define state40 8'd40 -`define state41 8'd41 -`define state42 8'd42 -`define state43 8'd43 -`define state44 8'd44 -`define state45 8'd45 -`define state46 8'd46 -`define state47 8'd47 -`define state48 8'd48 -`define state49 8'd49 -`define state50 8'd50 -`define state51 8'd51 -`define state52 8'd52 -`define state53 8'd53 -`define state54 8'd54 -`define state55 8'd55 -`define state56 8'd56 -`define state57 8'd57 -`define state58 8'd58 -`define state59 8'd59 -`define state60 8'd60 -`define state61 8'd61 -`define state62 8'd62 -`define state63 8'd63 -`define state64 8'd64 -`define state65 8'd65 -`define state66 8'd66 -`define state67 8'd67 -`define state68 8'd68 -`define state69 8'd69 -`define state70 8'd70 -`define state71 8'd71 -`define state72 8'd72 -`define state73 8'd73 -`define state74 8'd74 -`define state75 8'd75 -`define state76 8'd76 -`define state77 8'd77 -`define state78 8'd78 -`define state79 8'd79 -`define state80 8'd80 -`define state81 8'd81 -`define state82 8'd82 -`define state83 8'd83 -`define state84 8'd84 -`define state85 8'd85 -`define state86 8'd86 -`define state87 8'd87 -`define state88 8'd88 -`define state89 8'd89 -`define state90 8'd90 -`define state91 8'd91 -`define state92 8'd92 -`define state93 8'd93 -`define state94 8'd94 -`define state95 8'd95 -`define state96 8'd96 -`define state97 8'd97 -`define state98 8'd98 -`define state99 8'd99 -`define state100 8'd100 -`define state101 8'd101 -`define state102 8'd102 -`define state103 8'd103 -`define state104 8'd104 -`define state105 8'd105 -`define state106 8'd106 -`define state107 8'd107 -`define state108 8'd108 -`define state109 8'd109 -`define state110 8'd110 -`define state111 8'd111 -`define state112 8'd112 -`define state113 8'd113 -`define state114 8'd114 -`define state115 8'd115 -`define state116 8'd116 -`define state117 8'd117 -`define state118 8'd118 -`define state119 8'd119 -`define state120 8'd120 -`define state121 8'd121 -`define state122 8'd122 -`define state123 8'd123 -`define state124 8'd124 -`define state125 8'd125 -`define state126 8'd126 -`define state127 8'd127 -`define state128 8'd128 -`define state129 8'd129 -`define state130 8'd130 -`define state131 8'd131 -`define state132 8'd132 -`define state133 8'd133 -`define state134 8'd134 -`define state135 8'd135 -`define state136 8'd136 -`define state137 8'd137 -`define state138 8'd138 -`define state139 8'd139 -`define state140 8'd140 -`define state141 8'd141 -`define state142 8'd142 -`define state143 8'd143 -`define state144 8'd144 -`define state145 8'd145 -`define state146 8'd146 -`define state147 8'd147 -`define state148 8'd148 -`define state149 8'd149 -`define state150 8'd150 -`define state151 8'd151 -`define state152 8'd152 -`define state153 8'd153 -`define state154 8'd154 -`define state155 8'd155 -`define state156 8'd156 -`define state157 8'd157 -`define state158 8'd158 -`define state159 8'd159 -`define state160 8'd160 -`define state161 8'd161 -`define state162 8'd162 -`define state163 8'd163 -`define state164 8'd164 -`define state165 8'd165 -`define state166 8'd166 -`define state167 8'd167 -`define state168 8'd168 -`define state169 8'd169 -`define state170 8'd170 -`define state171 8'd171 -`define state172 8'd172 -`define state173 8'd173 -`define state174 8'd174 -`define state175 8'd175 -`define state176 8'd176 -`define state177 8'd177 -`define state178 8'd178 -`define state179 8'd179 -`define state180 8'd180 -`define state181 8'd181 -`define state182 8'd182 -`define state183 8'd183 -`define state184 8'd184 -`define state185 8'd185 -`define state186 8'd186 -`define state187 8'd187 -`define state188 8'd188 -`define state189 8'd189 -`define state190 8'd190 -`define state191 8'd191 -`define state192 8'd192 -`define state193 8'd193 -`define state194 8'd194 -`define state195 8'd195 -`define state196 8'd196 -`define state197 8'd197 -`define state198 8'd198 -`define state199 8'd199 -`define state200 8'd200 -`define state201 8'd201 -`define state202 8'd202 -`define state203 8'd203 -`define state204 8'd204 -`define state205 8'd205 -`define state206 8'd206 -`define state207 8'd207 -`define state208 8'd208 -`define state209 8'd209 -`define state210 8'd210 -`define state211 8'd211 -`define state212 8'd212 -`define state213 8'd213 -`define state214 8'd214 -`define state215 8'd215 -`define state216 8'd216 -`define state217 8'd217 -`define state218 8'd218 -`define state219 8'd219 -`define state220 8'd220 -`define state221 8'd221 -`define state222 8'd222 -`define state223 8'd223 -`define state224 8'd224 -`define state225 8'd225 -`define state226 8'd226 -`define state227 8'd227 -`define state228 8'd228 -`define state229 8'd229 -`define state230 8'd230 -`define state231 8'd231 -`define state232 8'd232 -`define state233 8'd233 -`define state234 8'd234 -`define state235 8'd235 -`define state236 8'd236 -`define state237 8'd237 -`define state238 8'd238 -`define state239 8'd239 -`define state240 8'd240 -`define state241 8'd241 -`define state242 8'd242 -`define state243 8'd243 -`define state244 8'd244 -`define state245 8'd245 -`define state246 8'd246 -`define state247 8'd247 -`define state248 8'd248 -`define state249 8'd249 -`define state250 8'd250 -`define state251 8'd251 -`define state252 8'd252 -`define state253 8'd253 -`define state254 8'd254 -`define state255 8'd255 - diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v deleted file mode 100644 index e1aac59ec..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/i2c_slave_data_fsm.v +++ /dev/null @@ -1,649 +0,0 @@ -//================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// ------------------------------------------------------------------ -// Copyright (c) 2014 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. - -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// - -`include "i2c_defines.v" -`include "i2c_new_reg.v" -`timescale 1 ns / 1 ns - - -module serialInterface (/*AUTOARG*/ - // Outputs - dataOut, regAddr, sdaOut, writeEn, readEn, i2c_start, - // Inputs - clk, dataIn, rst, scl, sdaIn - ); - input clk; - input [7:0] dataIn; - input rst; - input scl; - input sdaIn; - output [7:0] dataOut; - output [7:0] regAddr; - output sdaOut; - output writeEn; - output readEn; - output i2c_start; - - // I2C_SLAVE_INIT_ADDR: Upper Bits <9:2> can be changed. Lower bits <1:0> are fixed. - // For I2C Hard IP located in Upper Left <1:0> must be set to "01". - // For I2C Hard IP located in Upper Right <1:0> must be set to "10". - parameter I2C_SLAVE_INIT_ADDR = "0b1111100001"; //Upper Left - //parameter I2C_SLAVE_INIT_ADDR = "0b1111100010"; //Upper Right - - // BUS_ADDR74: Fixed value. SBADRI [7:4] bits also should match with this value to - // activate the IP. - // For I2C Hard IP located in Upper Left [7:4] must be set to "0001". - // For I2C Hard IP located in Upper Right [7:4] must be set to "0011". - parameter BUS_ADDR74_STRING = "0b0001"; //Upper Left - //parameter BUS_ADDR74_STRING = "0b0011"; //Upper Right - - // These are for the "OR" function with "wb_adr_i". Note that bits [7:4] are copies - // of BUS_ADDR74_STRING. - parameter BUS_ADDR74 = 8'b0001_0000; //Upper Left - //parameter BUS_ADDR74 = 8'b0011_0000; //Upper Right - - reg [7:0] regAddr; - reg writeEn; - wire [7:0] dataOut; - reg i2c_start; - - /* - * System bus interface signals - */ - reg [7:0] wb_dat_i; - reg wb_stb_i; - reg [7:0] wb_adr_i; - reg wb_we_i; - wire [7:0] wb_dat_o; - wire wb_ack_o; - /* - * Data Read and Write Register - */ - reg [7:0] temp0; - reg [7:0] temp1; - reg [7:0] temp2; - reg [7:0] temp3; - reg [7:0] n_temp0; - reg [7:0] n_temp1; - reg [7:0] n_temp2; - reg [7:0] n_temp3; - reg readEn; - - - /* - * i2c Module Instanitiation - */ - - - i2c UUT1 ( - .wb_clk_i (clk), - .wb_dat_i (wb_dat_i), - .wb_stb_i (wb_stb_i), - .wb_adr_i (wb_adr_i | BUS_ADDR74), - .wb_we_i (wb_we_i), - .wb_dat_o (wb_dat_o), - .wb_ack_o (wb_ack_o), - .i2c_irqo ( ), - .i2c_scl (scl), - .i2c_sda (sdaOut), - .i2c_sda_in (sdaIn), - .rst_i(rst) - ); - - defparam UUT1.I2C_SLAVE_INIT_ADDR = I2C_SLAVE_INIT_ADDR; - defparam UUT1.BUS_ADDR74_STRING = BUS_ADDR74_STRING; - - /* - * Signal & wire Declartion - */ - reg efb_flag; - reg n_efb_flag; - reg [7:0] n_wb_dat_i; - reg n_wb_stb_i; - reg [7:0] n_wb_adr_i; - reg n_wb_we_i; - reg [7:0] c_state; - reg [7:0] n_state; - reg n_count_en; - reg count_en; - wire invalid_command = 0; - - /* - * Output generation - */ - - assign dataOut = temp3; - - always @(posedge clk or posedge rst)begin - if (rst)begin - writeEn <= 0; - readEn <= 0; - end else begin - if(c_state == `state14)begin - writeEn <= 1'b1; - end else begin - writeEn <= 1'b0; - end - - if(c_state == `state15)begin - readEn <= 1'b1; - end else if (c_state == `state13) begin //** - if (n_temp2 & (`MICO_EFB_I2C_SR_SRW)) begin - readEn <= 1'b1; - end else begin - readEn <= 1'b0; - end - end else begin - readEn <= 1'b0; - end - end - end - - always @(posedge clk or posedge rst)begin - if (rst)begin - regAddr <= 0; - end else begin - if(c_state == `state2)begin - regAddr <= 8'd0; - end else if(c_state == `state9)begin - regAddr <= temp1; - //end else if(writeEn || readEn)begin - // regAddr <= regAddr + 1; - end - end - end - - //slave start detect - always @(posedge clk or posedge rst) begin - if (rst) begin - i2c_start <= 0; - end else begin - if (c_state == `state12) begin - i2c_start <= 0; - end else if (c_state == `state9) begin - i2c_start <= 1; - end - end - end - - /* - * Main state machine - */ - always @ (posedge clk or posedge rst) begin - if(rst) begin - wb_dat_i <= 8'h00; - wb_stb_i <= 1'b0 ; - wb_adr_i <= 8'h00; - wb_we_i <= 1'b0; - end else begin - wb_dat_i <= #1 n_wb_dat_i; - wb_stb_i <= #1 n_wb_stb_i; - wb_adr_i <= #1 n_wb_adr_i; - wb_we_i <= #1 n_wb_we_i ; - end - end - - always @ (posedge clk or posedge rst) begin - if(rst) begin - c_state <= 10'h000; - efb_flag <= 1'b0 ; - count_en <= 1'b0; - end else begin - c_state <= n_state ; - efb_flag <= n_efb_flag; - count_en <= n_count_en; - end - end - - always @ (posedge clk or posedge rst) begin - if(rst) begin - temp0 <= 8'h00 ; - temp1 <= 8'h00 ; - temp2 <= 8'h00 ; - temp3 <= 8'h00 ; - end else begin - temp0 <= n_temp0 ; - temp1 <= n_temp1 ; - temp2 <= n_temp2 ; - temp3 <= n_temp3 ; - end - end - - always @(posedge clk or posedge rst) begin - if (rst) begin - n_temp2 <= 0; - end else begin - n_temp2 <= wb_dat_o; //** - end - end - - /* - * FSM combinational block - */ - always @ ( * ) begin - n_efb_flag = 1'b0 ; - n_state = c_state ; - n_wb_dat_i = 8'h00; - n_wb_stb_i = 1'b0 ; - n_wb_adr_i = 8'h00; - n_wb_we_i = 1'b0; - n_count_en = 1'b0; - n_temp0 = temp0; - n_temp1 = temp1; - n_temp3 = temp3; - - case(c_state) - `state0: begin - n_wb_dat_i = 8'h00; - n_wb_stb_i = 1'b0 ; - n_wb_adr_i = 8'h00; - n_wb_we_i = 1'b0; - n_wb_stb_i = 1'b0 ; - n_state = `state1 ; - end - - `state1: begin // Enable I2C Interface - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - n_state = `state2; - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `MICO_EFB_I2C_CR; - n_wb_dat_i = 8'h80; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state2: begin // Clock Disable - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - n_state = `state3; - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `MICO_EFB_I2C_CMDR; - n_wb_dat_i = 8'h04; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state3: begin // Wait for not BUSY - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - if(wb_dat_o & (`MICO_EFB_I2C_SR_BUSY))begin - n_state = `state4; - end else begin - n_state = c_state; - end - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_STATUS; - n_wb_adr_i = `MICO_EFB_I2C_SR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state4: begin // Discard data 1 - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - n_temp0 = wb_dat_o; - n_state = `state5; - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_DATA; - n_wb_adr_i = `MICO_EFB_I2C_RXDR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state5: begin // Discard data 2 - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - n_temp0 = wb_dat_o; - n_state = `state6; - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_DATA; - n_wb_adr_i = `MICO_EFB_I2C_RXDR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state6: begin // Clock Enable - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - n_state = `state7; - end else begin - n_efb_flag = `HIGH; - n_wb_we_i = `WRITE; - n_wb_adr_i = `MICO_EFB_I2C_CMDR; - n_wb_dat_i = 8'h00; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state7: begin // wait for data to come - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - n_temp1 = 8'h00; - if((wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY)))begin - n_state = `state8; // Slave acknowledged - end else if (~wb_dat_o[6])begin - n_state = `state2; // Disable clock - end else begin - n_state = c_state; - end - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_STATUS; - n_wb_adr_i = `MICO_EFB_I2C_SR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state8: begin // Store i2C Command Information - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - n_temp1 = wb_dat_o; - n_state = `state9; - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_DATA; - n_wb_adr_i = `MICO_EFB_I2C_RXDR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state9: begin // Send ACK or NACK Based upon Command Receive & Wait for Stop `state 17 - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - if(invalid_command)begin // This is tied to '0' at present - n_state = `state17; - end else begin - n_state = `state12; - end - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `MICO_EFB_I2C_CMDR; - n_wb_dat_i = {4'h0,invalid_command,3'b000}; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state12: begin // Wait for TRRDY Bit - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY))begin - n_state = `state13; - end else if (~wb_dat_o[6])begin - n_state = `state2; - end else begin - n_state = c_state; - end - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_STATUS; - n_wb_adr_i = `MICO_EFB_I2C_SR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state13: begin // Check for read or write operation - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - if(wb_dat_o & (`MICO_EFB_I2C_SR_SRW))begin - n_state = `state15; //Read from slave - end else begin - n_state = `state14; //Write to slave - end - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_STATUS; - n_wb_adr_i = `MICO_EFB_I2C_SR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state14: begin // Write data - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - n_temp3 = wb_dat_o; - n_state = `state19; - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_DATA; - n_wb_adr_i = `MICO_EFB_I2C_RXDR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state15: begin // Send Data to Master - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - n_state = `state18; - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `WRITE; - n_wb_adr_i = `MICO_EFB_I2C_TXDR; - n_wb_dat_i = dataIn; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state17: begin // Wait till Stop is Send - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - if(~wb_dat_o[6])begin - n_state = `state2; - end else begin - n_state = c_state; - end - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_STATUS; - n_wb_adr_i = `MICO_EFB_I2C_SR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - `state18: begin // Wait for TxRDY flag and send data again if required - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY))begin - n_state = `state15; // Send Data - end else if (~wb_dat_o[6]) begin// If Stop go to beginning - n_state = `state2; - end else begin - n_state = c_state; - end - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_STATUS; - n_wb_adr_i = `MICO_EFB_I2C_SR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - - - `state19: begin // Wait for TRRDY bit - if (wb_ack_o && efb_flag) begin - n_wb_dat_i = `ALL_ZERO ; - n_wb_adr_i = `ALL_ZERO ; - n_wb_we_i = `LOW ; - n_wb_stb_i = `LOW ; - n_efb_flag = `LOW ; - n_count_en = `LOW ; - if(wb_dat_o & (`MICO_EFB_I2C_SR_TRRDY)) begin - n_state = `state14; - end else if (~wb_dat_o[6])begin - n_state = `state2; - end else begin - n_state = c_state; - end - end else begin - n_efb_flag = `HIGH ; - n_wb_we_i = `READ_STATUS; - n_wb_adr_i = `MICO_EFB_I2C_SR; - n_wb_dat_i = 0 ; - n_wb_stb_i = `HIGH ; - n_state = c_state; - end - end - endcase - end - - -endmodule diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v deleted file mode 100644 index 0ca379453..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/led_driver_19022014.v +++ /dev/null @@ -1,203 +0,0 @@ -//================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// ------------------------------------------------------------------ -// Copyright (c) 2014 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. - -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// - - -module led_driver ( - input sys_clk, - input rst_n, - input txn_start, - input mobeam_start_stop, - input led_polarity, - input [7:0] bar_width, - input [7:0] barcode_array, - output drive_on, - output byte_done, - output bit_done, - output oled - //output dynamic_clk); - ); - - //reg [15:0] clk_count; - - /* - always @(posedge sys_clk or negedge rst_n) - begin - if (~rst_n) - clk_count <= 16'b0; - else - if (clk_count==16'd4) - clk_count<= 0; - else - clk_count <= clk_count + 1'b1; - - end */// always @ (posedge sys_clk or negedge rst_n) - - // assign dynamic_clk = (clk_count==16'd4); - - - reg oled,drive_on; - reg oled_int; - reg [15:0] bw_count; - reg [7:0] ba_reg = 8'b10011001; - reg reload_ba_reg; - reg driver_busy; - - wire [7:0] BW; - reg [15:0] BWx10 /* synthesis syn_multstyle = logic */; - reg [2:0] bit_cnt; - reg byte_done_int; - reg txn_start_d; - /////////////////TXN_Start edge detect///////////////// - - always @(posedge sys_clk or negedge rst_n) - begin - if (~rst_n || !mobeam_start_stop) begin - txn_start_d<= 1'b0; - end - else - txn_start_d<=txn_start; - - end - assign txn_start_pos = txn_start & (~txn_start_d); - - - - -assign BW =bar_width; -//assign byte_done_mod= (&bit_cnt) & reload_ba_reg; -//assign byte_done_mod= (&bit_cnt) && (bw_count==1'b1); -assign byte_done_mod= (BWx10==16'd4)?(&bit_cnt) && (bw_count==1'b1):byte_done_int; -assign byte_done = byte_done_mod; -assign bit_done = reload_ba_reg; - // assign BWx10 = BW * 10 - 1'b1; - - always @(posedge sys_clk or negedge rst_n) - begin - if (~rst_n || !mobeam_start_stop) begin - ba_reg <= 8'd0; - BWx10<=16'd4; - byte_done_int<= 1'b0; - bit_cnt<= 3'd0; - end - else begin - if (BW==0) - BWx10<= 4; - else begin - BWx10 <= BW * 10 - 1'b1; - // BWX5 <= BW * 5 - 1'b1; //for 25% duty cycle - // BWX15 <= - end - - //if (txn_start_pos) begin - if (txn_start && bit_cnt==3'd0) begin - ba_reg <=barcode_array; - end - if (reload_ba_reg) begin - //ba_reg <= {ba_reg[0],ba_reg[7:1]}; //lsb first - ba_reg <= {ba_reg[6:0],ba_reg[7]}; //msb first - if (bit_cnt==3'd7) - byte_done_int<=1'b1; - else - byte_done_int<=1'b0; - - if (&bit_cnt) begin - //byte_done_int<=1'b1; - bit_cnt<= 3'd0; - end - else begin - // byte_done_int<= 1'b0; - bit_cnt<= bit_cnt + 1'b1; - end - - end - else - byte_done_int<= 1'b0; - end - end - - always @(posedge sys_clk or negedge rst_n) - begin - if (~rst_n || !mobeam_start_stop) - begin - oled_int <= 1'b0; - bw_count <= 16'b0; - reload_ba_reg <= 1'b0; - driver_busy<= 1'b0; - - end - else - if (txn_start) begin - // driver_busy<= 1'b1; - if (bw_count == BWx10) - begin - //oled<=ba_reg[0]; //lsb_first - oled_int<=ba_reg[7]; //msb first - bw_count<=16'b0; - reload_ba_reg <= 1'b1; - end - - else begin - oled_int<= oled_int; - bw_count<= bw_count + 1'b1; - reload_ba_reg <= 1'b0; - end - end - else - reload_ba_reg <= 1'b0; - end // always @ (posedge sys_clk or negedge rst_n) - - always @(posedge sys_clk ) begin - if (~rst_n || !mobeam_start_stop) begin - oled<=0; - end else begin - if(led_polarity)begin - oled <= oled_int; - drive_on<=oled_int; - end else begin - oled <= ~oled_int; - drive_on<=~oled_int; - end - end - - end - -endmodule // clk_gen - diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v deleted file mode 100644 index d824cda12..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_control_fsm_19022014.v +++ /dev/null @@ -1,1009 +0,0 @@ -//================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// ------------------------------------------------------------------ -// Copyright (c) 2014 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. - -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// - - -module mobeam_control_fsm( - //`ifndef SIM - input shift_done, - input bit_done, - // `endif - input sys_clk_i, - input rst_mobeam, -// input new_data_rd, -// input data_strobe, - input start_stop, - -// output reg config_reg_done, -// output reg write_to_bsr_buffer, - - //bsr memory signals - input [7:0] bsr_mem_data, - output bsr_mem_clk, - output reg [8:0] bsr_mem_addr, - output reg bsr_mem_rd_en, - - //ba memory signals - input [15:0] ba_mem_data , - output ba_mem_clk, - output reg [7:0] ba_mem_addr, - output reg ba_mem_rd_en, - - //TO LED DRIVER - output [7:0] o_byte_data, - output txn_start, -// output reg bsr_load_done, - output reg [7:0] bsr_bw -); - -`define IDLE_BSR 0 -`define LB_READ 1 -`define LB_READ_LATENCY 2 -`define LP_READ 3 -`define LP_READ_LATENCY 4 -`define BL_READ 5 -`define BL_READ_LATENCY 6 -`define NH_READ 7 -`define NH_READ_LATENCY 8 -`define NR_READ 9 -`define NR_READ_LATENCY 10 - -`define BSR_READ 11 -`define BSR_READ_LATENCY 12 -`define START_HOP 13 -//`define BEAM_START_STOP -//`define BEAM_START_STOP_LATENCY 10 - -`define IDLE_STATE 14 -`define READ_WORD 15 -`define READ_BYTE_LATENCY_1 16 -`define DELAY_STATE 17 -`define SHIFT_WORD 18 - - - -// ============================================================================== -// state assignments & defines -// ============================================================================== -parameter BSR_ADDR_WIDTH = 3 ; -parameter BSR_MEM_DEPTH = 1 << BSR_ADDR_WIDTH ; -///mobeam reg addresses//////////// -//parameter revision_code_addr=8'hEE; //EE -parameter rst_mobeam_addr=8'hF1; //ED -parameter lb_addr=8'hEA; //F0 -parameter lp_addr=8'hEB; //EF -parameter bl_addr=8'hEC; //E9 -parameter nh_addr=8'hED; //EA -parameter nr_addr=8'hEE; //EB -parameter bsr_addr=8'h80; -parameter ba_addr=8'h00; -parameter beam_start_stop_addr=8'hF0; //EC - - - -integer bsr_data_count; -reg rd_done; -reg i,i_2; - -reg [7:0] o_lb_data; -reg [7:0] o_lp_data; -reg [7:0] o_nh_data; -reg [7:0] o_nr_data; -reg [7:0] o_bl_data; -reg [7:0] o_bsr_data; -reg [4:0] ba_state; -reg [4:0] bsr_state; -reg [7:0] bsr_buffer [0:6]; -reg config_reg_done; -//reg write_to_bsr_buffer; - - -//reg start_stop; //from mobeam reg set -//wire shift_done; //from led control logic - - - - -//////////////////////////BA FSM//////////////////////////////////////////////// - - assign ba_mem_clk=sys_clk_i; - reg [7:0] byte_data; - wire bl_done; - reg [1:0]check_shift_done_count_d; - - always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam || !start_stop) begin - //check_clk_1=0; - //check_clk_2=0; - byte_data <= 8'd0; - check_shift_done_count_d<=0; - end - else begin - check_shift_done_count_d<=check_shift_done_count; - // if(ba_state!=`IDLE_STATE) begin - - if(check_shift_done_count_d==2'b01) begin - //if(check_clk_1==1) begin - byte_data<=ba_mem_data[15:8]; - //check_clk_1=0; - //end - //else - //check_clk_1=1; - end - else if(check_shift_done_count_d==2'b00) begin - //if(check_clk_2==1) begin - byte_data<=ba_mem_data[7:0]; - //check_clk_2=0; - //end - //else - //check_clk_2=1; - end - else - byte_data<=byte_data; - end - end - - - - - ////*****count shift_done's***************//// - - reg [1:0] check_shift_done_count; - reg clk_count_2,clk_count_3; - - always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam || !start_stop) begin - clk_count_2<=0; - clk_count_3<=0; - check_shift_done_count<=2'b00; - end - else begin - if(/*tx_out_en_high_dtc*/symbol_shift_done) - check_shift_done_count<=0; - else if(shift_done) begin - // if(clk_count_2==1) begin - // clk_count_2<=0; - check_shift_done_count<=check_shift_done_count + 1; - // end - // else begin - // check_shift_done_count<=check_shift_done_count; - // end - // clk_count_2<=clk_count_2 + 1; - end - else if(check_shift_done_count==2'b10) begin - // if(clk_count_3==1) begin - check_shift_done_count<=0; - // clk_count_3<=0; - // end - // else begin - // check_shift_done_count<=check_shift_done_count; - // end - // clk_count_3<=clk_count_3+1; - end - else - check_shift_done_count<=check_shift_done_count; - end - end - - /* - always @(posedge sys_clk_i or negedge rst_mobeam_n) begin - if(!rst_mobeam_n) begin - clk_count_2<=0; - clk_count_3<=0; - check_shift_done_count<=2'b00; - end - else begin - - if(shift_done) begin - if(clk_count_2==1) begin - clk_count_2<=0; - check_shift_done_count<=check_shift_done_count + 1; - end - else begin - check_shift_done_count<=check_shift_done_count; - end - clk_count_2<=clk_count_2 + 1; - end - else if(check_shift_done_count==2'b10) begin - if(clk_count_3==1) begin - check_shift_done_count<=0; - clk_count_3<=0; - end - else begin - check_shift_done_count<=check_shift_done_count; - end - clk_count_3<=clk_count_3+1; - end - else - check_shift_done_count<=check_shift_done_count; - end - end - */ - //assign check_shift_done_count= (!rst_mobeam_n) ? 3'b000 : shift_done ? (check_shift_done_count + 1) : check_shift_done_count; - - wire incr_ba_mem_addr; - reg q_tx_out_en_0,q_tx_out_en_1; - assign incr_ba_mem_addr=(check_shift_done_count==2'b10) ? 1 : 0; - //assign bl_done=(bl_byte_count_3==o_bl_data + 1) ? 1 : 0; - //assign o_byte_data=((bl_byte_count_3 >0) && !bl_done) ? byte_data : 8'bz; - //assign o_byte_data= ba_mem_rd_en ? (/*(isd_delay_en || ipd_delay_en)*/ !tx_out_en ? 8'bz : byte_data) : 0; - - assign o_byte_data= byte_data; - assign txn_start = q_tx_out_en_1; - - - //assign txn_start = tx_out_en; //orignal - - always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam || !start_stop) begin - q_tx_out_en_0<=0; - q_tx_out_en_1<=0; - end - else begin - q_tx_out_en_0<=tx_out_en; - q_tx_out_en_1<=q_tx_out_en_0; - end - end - wire tx_out_en_high_dtc; - - assign tx_out_en_high_dtc= ~q_tx_out_en_0 && tx_out_en; - -//////////////BA FSM///////////////////////////////////////////// - always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam) begin - ba_mem_addr<=0; - ba_mem_rd_en<=0; - ba_state<=`IDLE_STATE; - end - else begin - case(ba_state) - `IDLE_STATE: begin - ba_mem_addr<=0; - ba_mem_rd_en<=0; - if(/*start_stop*/ config_reg_done) - ba_state<=`READ_WORD; - else - ba_state<=`IDLE_STATE; - end - - `READ_WORD:begin - ba_mem_rd_en<=1; - if(!start_stop) - ba_state<=`IDLE_STATE; - else if(symbol_shift_done) //make address=0 when #shift_done's == o_bl_data - ba_mem_addr<=0; - else if(!tx_out_en) - ba_state<=`DELAY_STATE; - else if(incr_ba_mem_addr) begin - ba_mem_addr<=ba_mem_addr + 1; - ba_state<=`READ_BYTE_LATENCY_1; - end - else begin - ba_mem_addr<=ba_mem_addr; - ba_state<=`READ_WORD; - end - end - - `READ_BYTE_LATENCY_1:begin - if(!start_stop) - ba_state<=`IDLE_STATE; - else - ba_state<=`READ_WORD; - end - - `DELAY_STATE:begin - if(!start_stop) - ba_state<=`IDLE_STATE; - else begin - ba_mem_addr<=ba_mem_addr; - if(tx_out_en) - ba_state<=`READ_WORD; - else - ba_state<=`DELAY_STATE; - end - end - - endcase - end //else begin - end //else always -///////////////////////////////////////////////////////////////// - reg start_stop_count; - - always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam) begin - start_stop_count=0; - end - else begin - if(start_stop) - start_stop_count=1; - end - end - - -//////////////////BSR FSM/////////////////////////////////////// - - - -assign bsr_mem_clk=sys_clk_i; -reg state_count; -reg init_addr_read_done; -reg [8:0] prev_mem_rd_addr; -reg [8:0] next_mem_rd_addr; - - always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam) begin - bsr_state<=`IDLE_BSR; - i<=0; - i_2<=0; - bsr_data_count<=0; - // write_to_bsr_buffer<=0; - state_count<=0; - config_reg_done<=0; - next_mem_rd_addr<=0; - bsr_mem_addr<=0; - prev_mem_rd_addr<=0; - bsr_mem_rd_en<=1'b1; - // bsr_load_done<=0; - init_addr_read_done<=0; - rd_done<=1'b0; - o_lb_data<=0; - o_lp_data<=0; - o_nh_data<=0; - o_nr_data<=0; - o_bl_data<=0; - o_bsr_data<=0; - end - else begin - - case(bsr_state) - `IDLE_BSR:begin - i<=0; - i_2<=0; - bsr_data_count<=0; - // write_to_bsr_buffer<=0; - state_count<=0; - config_reg_done<=0; - next_mem_rd_addr<=0; - bsr_mem_addr<=0; - prev_mem_rd_addr<=0; - bsr_mem_rd_en<=1'b1; - // bsr_load_done<=0; - init_addr_read_done<=0; - rd_done<=1'b0; - if (start_stop==1) - bsr_state<=`LB_READ; - else - bsr_state<=`IDLE_BSR; - end - - - `LB_READ:begin - bsr_mem_addr<=lb_addr; - bsr_mem_rd_en<=1'b1; - bsr_state<=`LB_READ_LATENCY; - end - - `LB_READ_LATENCY:begin - state_count<=state_count + 1; - if(state_count==1) begin - o_lb_data<=bsr_mem_data; - state_count<=0; - bsr_state<=`LP_READ; - end - else - bsr_state<=`LB_READ_LATENCY; - end - - `LP_READ:begin - bsr_mem_addr<=lp_addr; - bsr_mem_rd_en<=1'b1; - bsr_state<=`LP_READ_LATENCY; - end - - `LP_READ_LATENCY:begin - state_count<=state_count + 1; - if(state_count==1) begin - o_lp_data<=bsr_mem_data; - state_count<=0; - bsr_state<=`BL_READ; - end - else - bsr_state<=`LP_READ_LATENCY; - end - - `BL_READ:begin - bsr_mem_addr<=bl_addr; - bsr_mem_rd_en<=1'b1; - bsr_state<=`BL_READ_LATENCY; - - end - - `BL_READ_LATENCY:begin - state_count<=state_count + 1; - if(state_count==1) begin - o_bl_data<=bsr_mem_data; - state_count<=0; - bsr_state<=`NH_READ; - end - else - bsr_state<=`BL_READ_LATENCY; - end - - `NH_READ:begin - bsr_mem_addr<=nh_addr; - bsr_mem_rd_en<=1'b1; - bsr_state<=`NH_READ_LATENCY; - end - - `NH_READ_LATENCY:begin - state_count<=state_count + 1; - if(state_count==1) begin - o_nh_data<=bsr_mem_data; - state_count<=0; - bsr_state<=`NR_READ; - end - else - bsr_state<=`NH_READ_LATENCY; - end - - `NR_READ:begin - bsr_mem_addr<=nr_addr; - bsr_mem_rd_en<=1'b1; - rd_done<=1'b1; - bsr_state<=`NR_READ_LATENCY; - end - - `NR_READ_LATENCY:begin - state_count<=state_count + 1; - if(state_count==1) begin - o_nr_data<=bsr_mem_data; - state_count<=0; - bsr_state<=`BSR_READ; - end - else - bsr_state<=`NR_READ_LATENCY; - end - - - `BSR_READ:begin - if (i==0) begin - i<=1'b1; - bsr_data_count<=0; - - if(init_addr_read_done==0 || nh_hop_shift_done_2) - bsr_mem_addr<=bsr_addr; - else if(hop_shift_done_3) begin //if shift_count==np*ns then next 8 bytes else - //config_reg_done<=0; - bsr_mem_addr<=next_mem_rd_addr+1; - end - else - bsr_mem_addr<=prev_mem_rd_addr; - - bsr_mem_rd_en<=1'b1; - bsr_state<=`BSR_READ_LATENCY; - end - else begin - bsr_mem_addr<=bsr_mem_addr+1; - bsr_data_count<=bsr_data_count+1; - if (bsr_data_count==6) begin //read all 8 bytes of bsr data,increament hop_count - // bsr_data_count<=0; - next_mem_rd_addr<=bsr_mem_addr; - // write_to_bsr_buffer<=0; - // bsr_load_done<=1; - config_reg_done<=1; - //bsr_state<=`BEAM_START_STOP; - bsr_state<=`START_HOP; - end - else begin - config_reg_done<=config_reg_done; - bsr_state<=`BSR_READ_LATENCY; - end - end - end - - `BSR_READ_LATENCY:begin - if(i_2==1'b0) begin /*store first address in temp register*/ - i_2<=1'b1; - prev_mem_rd_addr<=bsr_mem_addr; - end - state_count<=state_count + 1; - // write_to_bsr_buffer<=1; - if(state_count==1) begin - o_bsr_data<=bsr_mem_data; - bsr_buffer[bsr_data_count]<=bsr_mem_data; - state_count<=0; - bsr_state<=`BSR_READ; - end - else begin - bsr_state<=`BSR_READ_LATENCY; - // write_to_bsr_buffer<=0; - end - end - - `START_HOP: begin - i<=1'b0; - i_2<=1'b0; - // bsr_load_done<=0; - init_addr_read_done<=1; - if(!start_stop && start_stop_count) - bsr_state<=`IDLE_BSR; - else if(hop_shift_done) - bsr_state<=`BSR_READ; - else - bsr_state<=`START_HOP; - end - - - // `BEAM_START_STOP: begin - // i<=1'b0; - // i_2<=1'b0; - // init_addr_read_done<=1; - // bsr_load_done<=0; - // rd_done<=1'b0; - // bsr_mem_addr<=beam_start_stop_addr; - // bsr_mem_rd_en<=1'b1; - // if(hop_shift_done/*symbol_shift_done*/) - // bsr_state<=`BSR_READ; - // else - // bsr_state<=`BEAM_START_STOP_LATENCY; - // end - - // `BEAM_START_STOP_LATENCY:begin - // state_count<=state_count + 1; - // if(state_count==1) begin - // state_count<=0; - // if (bsr_mem_data==8'b00000001) begin - // start_stop<=1'b1; - // if(hop_shift_done/*symbol_shift_done*/) - // bsr_state<=`BSR_READ; - // else - // bsr_state<=`BEAM_START_STOP; - // end - // else begin - // start_stop<=1'b0; - // bsr_state<=`IDLE_BSR; - // end - // end - // else - // bsr_state<=`BEAM_START_STOP_LATENCY; - // end - - endcase - - end - end - - /////*********edge detection for config_reg_done***********//////////// - reg q_config_reg_done; - always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam) - q_config_reg_done<=0; - else - q_config_reg_done<=config_reg_done; - end - - assign config_reg_done_pos_dtc= config_reg_done && (~q_config_reg_done); - - -////**************LOGIC TO FIND PACKET AND SYMBOL COUNT*************///////// - reg [7:0] packet_count; - reg [3:0] hop_count; - reg [7:0] symbol_count; - reg [7:0] shift_done_count; - reg symbol_shift_done,symbol_shift_done_2,symbol_shift_done_3; - reg packet_shift_done; - reg hop_shift_done,hop_shift_done_2,hop_shift_done_3; - reg clk_count,clk_count_4; - reg nh_hop_shift_done,nh_hop_shift_done_2,nh_hop_shift_done_3; - - assign nh_hop_shift_done_led=nh_hop_shift_done_3; - - - always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam) begin - packet_count=0; - hop_count=0; - hop_shift_done=0; - shift_done_count=0; - symbol_count=0; - clk_count<=0; - clk_count_4<=0; - hop_shift_done_2<=0; - hop_shift_done_3<=0; - nh_hop_shift_done<=0; - nh_hop_shift_done_2<=0; - nh_hop_shift_done_3<=0; - symbol_shift_done<=0; - symbol_shift_done_2<=0; - symbol_shift_done_3<=0; - packet_shift_done=0; - end - else begin - if(start_stop) begin - hop_shift_done=0; - nh_hop_shift_done<=0; - symbol_shift_done<=0; - packet_shift_done=0; - if(shift_done) begin - //clk_count<=clk_count+1; - //if(clk_count==1'b1) begin //orignal - //clk_count<=0; - if(shift_done_count==(o_bl_data-1)) begin //bl check - shift_done_count=0; - symbol_shift_done<=1; - if(symbol_count==(bsr_ns-1)) begin //symbol_check - symbol_count=0; - packet_shift_done=1; - if(packet_count==(bsr_np-1)) begin //packet check - packet_count=0; - hop_shift_done=1; - if(hop_count==(o_nh_data-1)) begin //hop_check - hop_count=0; - nh_hop_shift_done<=1; - end - else begin - hop_count=hop_count + 1; //hop_check - end - end - else begin //packet check - packet_count=packet_count+1; - hop_shift_done=0; - end - end - else begin - symbol_count=symbol_count+1; - end - end - else - shift_done_count=shift_done_count+1; //bl check - end - else - //shift_done_count=shift_done_count+1; //orignal - shift_done_count=shift_done_count; - //end //orignal - - nh_hop_shift_done_2<=nh_hop_shift_done; - nh_hop_shift_done_3<=nh_hop_shift_done_2; - hop_shift_done_2<=hop_shift_done; - hop_shift_done_3<=hop_shift_done_2; - symbol_shift_done_2<=symbol_shift_done; - symbol_shift_done_3<=symbol_shift_done_2; - end - else begin - packet_count=0; - hop_count=0; - hop_shift_done=0; - shift_done_count=0; - symbol_count=0; - clk_count<=0; - clk_count_4<=0; - hop_shift_done_2<=0; - hop_shift_done_3<=0; - nh_hop_shift_done<=0; - nh_hop_shift_done_2<=0; - nh_hop_shift_done_3<=0; - symbol_shift_done<=0; - symbol_shift_done_2<=0; - symbol_shift_done_3<=0; - packet_shift_done=0; - end - end -end - /* - - always @(posedge sys_clk_i or negedge rst_mobeam_n) begin - if(!rst_mobeam_n) begin - packet_count=0; - hop_count=0; - hop_shift_done=0; - shift_done_count=0; - clk_count<=0; - nh_hop_shift_done=0; - end - else begin - if(start_stop) begin - hop_shift_done=0; - nh_hop_shift_done=0; - if(shift_done) begin - clk_count<=clk_count+1; - if(clk_count==1'b1) begin - clk_count<=0; - if(shift_done_count==(bsr_ns-1)) begin - shift_done_count=0; - if(packet_count==(bsr_np-1)) begin - packet_count=0; - if(hop_count==(o_nh_data-1)) begin - hop_count=0; - nh_hop_shift_done=1; - // hop_shift_done=1; - end - else begin - hop_shift_done=1; - hop_count=hop_count + 1; - end - end - else begin - packet_count=packet_count+1; - hop_shift_done=0; - end - end - else - shift_done_count=shift_done_count+1; - end - end - else - shift_done_count=shift_done_count; - end - else begin - shift_done_count=0; - packet_count=0; - hop_count=0; - hop_shift_done=0; - end - end -end -*/ -/////////*******BSR CONTROL REGSITER DATA******************//////// - -wire [7:0] bsr_bw_int; //bar width -wire [7:0] bsr_ns; //number of symbols -wire [15:0] bsr_isd; //inter symbol distance -wire [7:0] bsr_np; //number of packets -wire [15:0] bsr_ipd; //inter packet distance -//wire [55:0] control_reg; - -//assign bsr_bw = bsr_bw_int; //orignal - -always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam || !start_stop) begin - bsr_bw<= 0; - end -else - if (hop_after_txn_neg || config_reg_done_pos_dtc) //added "|| config_reg_done_pos_dtc" on 13/feb/2014 - bsr_bw <= bsr_bw_int; - //else - //bsr_bw <= bsr_bw; - end - - - - -//assign bsr_bw = (bsr_data_count==31'd7) ? (hop_after_txn_neg ? bsr_bw_int : bsr_bw) : 0 ; - - -assign bsr_bw_int=(bsr_data_count==31'd7) ? {bsr_buffer[0][7:0]} : 0; -assign bsr_ns=(bsr_data_count==31'd7) ? bsr_buffer[1][7:0] : 0; -assign bsr_isd=(bsr_data_count==31'd7) ?{bsr_buffer[3][7:0],bsr_buffer[2][7:0]} : 0; -assign bsr_np=(bsr_data_count==31'd7) ? bsr_buffer[4][7:0] : 0; -assign bsr_ipd=(bsr_data_count==31'd7) ? {bsr_buffer[6][7:0],bsr_buffer[5][7:0]}: 0; - -//assign control_reg=!rst_mobeam ? 56'bz : bsr_load_done ? {bsr_ipd,bsr_np,bsr_isd,bsr_ns,bsr_bw}:control_reg; - -//assign o_ba_mem_data=start_stop ? ba_mem_data : 16'bz; -//assign o_ba_mem_data=(ba_state==`SHIFT_WORD) ? ba_mem_data : 16'bz; - -/************************************************************************/ - - - - -/////***************FSM DECODE********************////////////// - /*AUTOASCIIENUM("bsr_state" "state_ASCII")*/ - // Beginning of automatic ASCII enum decoding - reg [111:0] state_ASCII; // Decode of bsr_state - always @(bsr_state) begin - case ({bsr_state}) - `IDLE_BSR : state_ASCII = "IDLE_BSR "; - `NH_READ : state_ASCII = "NH_READ"; - `NH_READ_LATENCY: state_ASCII = "NH_READ_LATENCY "; - `NR_READ : state_ASCII = "NR_READ "; - `NR_READ_LATENCY: state_ASCII = "NR_READ_LATENCY "; - `BL_READ : state_ASCII = "BL_READ "; - `BL_READ_LATENCY: state_ASCII = "BL_READ_LATENCY "; - `BSR_READ : state_ASCII = "BSR_READ "; - `BSR_READ_LATENCY: state_ASCII = "BSR_READ_LATENCY "; - `START_HOP : state_ASCII = "START_HOP "; - `LB_READ : state_ASCII = "LB_READ "; - `LB_READ_LATENCY: state_ASCII = "LB_READ_LATENCY "; - `LP_READ : state_ASCII = "LP_READ "; - `LP_READ_LATENCY: state_ASCII = "LP_READ_LATENCY "; - - //`BEAM_START_STOP : state_ASCII = "BEAM_START_STOP "; - //`BEAM_START_STOP_LATENCY: state_ASCII = "BEAM_START_STOP_LATENCY "; - default: state_ASCII = "%Error "; - endcase - end - // End of automatics - - /*AUTOASCIIENUM("ba_state" "state_ASCII")*/ - // Beginning of automatic ASCII enum decoding - reg [111:0] ba_state_ASCII; // Decode of ba_state - always @(ba_state) begin - case ({ba_state}) - `IDLE_STATE : ba_state_ASCII = "IDLE_STATE "; - `READ_WORD : ba_state_ASCII = "READ_WORD"; - `READ_BYTE_LATENCY_1: ba_state_ASCII = "READ_BYTE_LATENCY_1 "; - `DELAY_STATE : ba_state_ASCII = "DELAY_STATE "; - - `SHIFT_WORD : ba_state_ASCII = "SHIFT_WORD "; - default: ba_state_ASCII = "%Error "; - endcase - end - // End of automatics -////////////////********************************//////////////////// - /* -wire isd_delay_en; -wire ipd_delay_en; -wire low_isd_delay_en_dtc; -wire tx_out_en; - - -reg q1_isd_delay_en,q2_isd_delay_en; - - -always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam) begin - q1_isd_delay_en<=0; - q2_isd_delay_en<=0; - end - else begin - q1_isd_delay_en<=isd_delay_en; - q2_isd_delay_en<=q1_isd_delay_en; - end - end - */ -// assign low_isd_delay_en_dtc= q1_isd_delay_en && ~isd_delay_en ;///*&& q2_isd_delay_en*/; - -wire isd_delay_en; -wire ipd_delay_en; -wire low_isd_delay_en_dtc; - - -//assign tx_out_en= ba_mem_rd_en ? ((isd_delay_en || ipd_delay_en) ? 0 : 1) : 0; - -//assign dummy_tx_out_en= ba_mem_rd_en ? ( (isd_delay_en && ipd_delay_en) ? (ipd_delay_en ? 1 : 0) : (isd_delay_en ? 1 : 0)) : 0 ; - -//assign dummy_tx_out_en= ba_mem_rd_en ? (isd_delay_en_rise_dtc ? ((isd_delay_en_rise_dtc && ipd_delay_en_rise_dtc) ? (ipd_delay_en ? 1 : 0) : ipd_delay_en) : (isd_delay_en ? 1 : 0)) : 0 ; //(isd_delay_en ? 1 : 0)) : 0 ; - -reg q1_isd_delay_en,q1_ipd_delay_en; - -always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam || !start_stop) begin - q1_isd_delay_en<=0; - q1_ipd_delay_en<=0; - end - else begin - q1_isd_delay_en<=isd_delay_en; - q1_ipd_delay_en<=ipd_delay_en; - end -end - -reg tx_out_en; - - -always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam || !start_stop) begin - tx_out_en<=0; - end -else begin - if(ba_mem_rd_en) begin - if(isd_delay_en_rise_dtc && ipd_delay_en_rise_dtc) - tx_out_en<=0; - else if(isd_delay_en_rise_dtc) - tx_out_en<=0; - else if(isd_delay_en_fall_dtc && ipd_delay_en) // - tx_out_en<=0; - else if(ipd_delay_en_fall_dtc) - tx_out_en<=1; - else if(!isd_delay_en && !ipd_delay_en) // - tx_out_en<=1; - else - tx_out_en<=tx_out_en; - end - else - tx_out_en<=0; - end -end - -assign isd_delay_en_rise_dtc=~q1_isd_delay_en && isd_delay_en; -assign ipd_delay_en_rise_dtc=~q1_ipd_delay_en && ipd_delay_en; -assign isd_delay_en_fall_dtc=q1_isd_delay_en && ~isd_delay_en; -assign ipd_delay_en_fall_dtc=q1_ipd_delay_en && ~ipd_delay_en; -assign low_isd_delay_en_dtc= q1_isd_delay_en && ~isd_delay_en ;///*&& q2_isd_delay_en*/; - - -reg hop_after_txn,q_hop_after_txn; - -always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam || !start_stop) begin - hop_after_txn<=0; - end - else begin - if(hop_shift_done) - hop_after_txn<=1; - else if(tx_out_en && bit_done) - hop_after_txn<=0; - else - hop_after_txn<=hop_after_txn; - end -end - -always @(posedge sys_clk_i or posedge rst_mobeam) begin - if(rst_mobeam || !start_stop) begin - q_hop_after_txn<=0; - end - else - q_hop_after_txn<=hop_after_txn; -end - - assign hop_after_txn_neg= (~hop_after_txn) & q_hop_after_txn; - - -delay_gen_ihd_ipd_isd mobeam_delay_gen_inst( - .clk(sys_clk_i), - .rst(rst_mobeam), - .isd_val(bsr_isd), - .ipd_val(bsr_ipd), - .start_stop(start_stop), - .config_reg_done(config_reg_done), - .hop_shift_done(hop_shift_done), - .packet_shift_done(packet_shift_done), - .symbol_shift_done(symbol_shift_done), - .isd_delay_en(isd_delay_en), - .ipd_delay_en(ipd_delay_en) - ) ; - - /* - `ifdef SIM - reg shift_done; - initial begin - shift_done=0; - #160000 - repeat(1000) begin - #40000 - shift_done=1; - #50 - shift_done=0; - end - - end - `endif - */ -endmodule \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v deleted file mode 100644 index 5100e5fe9..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_delay_gen.v +++ /dev/null @@ -1,160 +0,0 @@ -//================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// ------------------------------------------------------------------ -// Copyright (c) 2014 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. - -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// - - -module mobeam_delay_gen( - input clk, - input rst_n, - input [15:0] isd_val, - input [15:0] ipd_val, - input config_reg_done, - input symbol_shift_done, - input packet_shift_done, - output reg isd_delay_en, - output reg ipd_delay_en -); - -reg [15:0] isd_val_temp; -reg [15:0] ipd_val_temp; -reg [15:0] isd_count; -reg [15:0] ipd_count; -wire [15:0] max_count,max_count_pkt; -reg clk_count,clk_count_pkt; -reg count_done,count_done_pkt; - -parameter const=10; -assign max_count=isd_val_temp * const; -assign max_count_pkt=ipd_val_temp * const; - -wire count_enable,count_enable_pkt; -//wire config_done; -//assign config_done= !rst_n ? 0 : config_reg_done ? 1 : config_done; -assign count_enable= !rst_n ? 0 : count_done ? 0 : symbol_shift_done ? 1 : count_enable; -assign count_enable_pkt= !rst_n ? 0 : count_done_pkt ? 0 : packet_shift_done ? 1 : count_enable_pkt; - -//assign isd_delay_en=symbol_shift_done ? 1 : (isd_count==max_count-1) : - -///////////////////////symbol//////////////////////////////////// -always @(posedge clk or negedge rst_n) begin - if(!rst_n) begin - isd_count<=0; - count_done<=0; - end - else begin - count_done<=0; - if(count_enable) begin - if(isd_count==max_count-1) begin - isd_count<=0; - count_done<=1; - isd_delay_en<=0; - end - else begin - isd_delay_en<=1; - isd_count<=isd_count+1; - end - end - else begin - isd_delay_en<=0; - isd_count<=0; - end - end -end - -always @(posedge clk or negedge rst_n) begin - if(!rst_n) begin - isd_val_temp<=0; - clk_count<=0; - end - else begin - if(clk_count) - isd_val_temp<=isd_val_temp; - else if(config_reg_done) begin - clk_count<=clk_count+1; - isd_val_temp<=isd_val; - end - else - isd_val_temp<=isd_val_temp; - end -end -///////////////packet////////////////////// -always @(posedge clk or negedge rst_n) begin - if(!rst_n) begin - ipd_count<=0; - count_done_pkt<=0; - end - else begin - count_done_pkt<=0; - if(count_enable_pkt) begin - if(ipd_count==max_count_pkt-1) begin - ipd_count<=0; - count_done_pkt<=1; - ipd_delay_en<=0; - end - else begin - ipd_delay_en<=1; - ipd_count<=ipd_count+1; - end - end - else begin - ipd_delay_en<=0; - ipd_count<=0; - end - end -end - -always @(posedge clk or negedge rst_n) begin - if(!rst_n) begin - ipd_val_temp<=0; - clk_count_pkt<=0; - end - else begin - if(clk_count_pkt) - ipd_val_temp<=ipd_val_temp; - else if(config_reg_done) begin - clk_count_pkt<=clk_count_pkt+1; - ipd_val_temp<=ipd_val; - end - else - ipd_val_temp<=ipd_val_temp; - end -end - -endmodule diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v deleted file mode 100644 index c8d1494e8..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/mobeam_i2c_reg_interface_19022014.v +++ /dev/null @@ -1,377 +0,0 @@ -//================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// ------------------------------------------------------------------ -// Copyright (c) 2014 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. - -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// - - -module mobeam_i2c_reg_interface( - rst_i, - clk_i, - //i2c slave interface signals/// - i2c_master_to_slave_data_i, - i2c_slave_to_master_data_o, - i2c_slave_data_address_i, - wr_en_i, - rd_en_i, - i2c_start_i, - //MoBeam control logic interface// - rd_revision_code, - rst_mobeam, - mobeam_start_stop, - led_polarity, - o_ba_mem_data, - i_ba_mem_addr, - i_ba_mem_rd_en, - i_ba_mem_rd_clk, - o_bsr_mem_data, - i_bsr_mem_addr, - i_bsr_mem_rd_en, - i_bsr_mem_rd_clk - // i_config_reg_done, - // o_new_data_rd, - // o_data_strobe - ); -//i2c slave interface signals/// -input [7:0] i2c_master_to_slave_data_i; -output reg [7:0]i2c_slave_to_master_data_o; -input [7:0] i2c_slave_data_address_i; -input wr_en_i; -input rd_en_i; -input i2c_start_i; -input rst_i; -input clk_i; -//mobeam control logic interface// -output [15:0] o_ba_mem_data; -input [7:0] i_ba_mem_addr; -input i_ba_mem_rd_en; -input i_ba_mem_rd_clk; -output reg rd_revision_code=0; -output reg rst_mobeam=0; -//input[7:0] i_revision_code_data; -//input rd_revision_code; -output [7:0] o_bsr_mem_data; -//output reg [15:0] mem_data_buf16; -input [8:0] i_bsr_mem_addr; -input i_bsr_mem_rd_en; -input i_bsr_mem_rd_clk; -output reg mobeam_start_stop=1'b0; -output reg led_polarity=1'b0; -//output reg o_new_data_rd=1'b0; -//output reg o_data_strobe=1'b0; -//input i_config_reg_done; - - - - - - - - -//////////////wire & reg declarations////////////////// -wire wr_en; -wire rd_en; -reg d1_wr_en_i; -reg d2_wr_en_i; -reg d1_rd_en_i; -reg d2_rd_en_i; - -parameter revision_code=8'hF1; - - - - -/////////////////////BSR and CONFIG data memory////////////// - -SB_RAM512x8 ram512x8_inst -( - .RDATA(o_bsr_mem_data),// EBR512x8_data - .RADDR(i_bsr_mem_addr),// EBR512x8_addr - .RCLK(i_bsr_mem_rd_clk), - .RCLKE(i_bsr_mem_rd_en), - .RE(i_bsr_mem_rd_en),// EBR512x8_re - .WADDR({1'b0,bsr_mem_addr_in}), - .WCLK(clk_i), - .WCLKE(1'b1),///*bsr_wr_en/*wr_en*/), - .WDATA(i2c_master_to_slave_data_i), - .WE(bsr_wr_en) ////*bsr_wr_en/*wr_en*/) -); - -defparam ram512x8_inst.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -//ICE Technology Library 66 -//Lattice Semiconductor Corporation Confidential -defparam ram512x8_inst.INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram512x8_inst.INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - -///////////////////////BA i.e. beamable data memory////////////// -SB_RAM256x16 ram256x16_inst ( -.RDATA(o_ba_mem_data), -.RADDR(i_ba_mem_addr), -.RCLK(i_ba_mem_rd_clk), -.RCLKE(i_ba_mem_rd_en), -.RE(i_ba_mem_rd_en), -.WADDR(ba_mem_addr_in_delayed_1), -.WCLK(clk_i), -.WCLKE(1'b1),///*ba_wr_en/*wr_en*/), -.WDATA(ba_mem_data_buffer), -.WE(ba_wr_en_delayed),///*wr_en*/), -.MASK(16'd0) -); -defparam ram256x16_inst.INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; -defparam ram256x16_inst.INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - -// Write valid pulse -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - d1_wr_en_i <= 0; - d2_wr_en_i <= 0; - end else begin - d1_wr_en_i <= wr_en_i; - d2_wr_en_i <= d1_wr_en_i; - end -end - -assign wr_en = d2_wr_en_i && ~d1_wr_en_i; - -// Read enable pulse -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - d1_rd_en_i <= 0; - d2_rd_en_i <= 0; - end else begin - d1_rd_en_i <= rd_en_i; - d2_rd_en_i <= d1_rd_en_i; - end -end - - -assign rd_en = ~d2_rd_en_i && d1_rd_en_i; - -reg [7:0] bsr_mem_addr_in; - -reg [7:0] ba_mem_addr_in; -reg ba_wr_en; - - -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - bsr_mem_addr_in <= 9'd0; - - end -else - if (i2c_start_i) - bsr_mem_addr_in <= i2c_slave_data_address_i; - - else if (i2c_slave_data_address_i == 8'h80) begin - if (wr_en) begin - bsr_mem_addr_in <=bsr_mem_addr_in + 1'b1; - - end - - end -end - -assign bsr_wr_en = (i2c_slave_data_address_i == 8'h00)?1'b0:wr_en; - -//MOBEAM START-STOP -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - mobeam_start_stop<=1'b0; - - end -else - if (i2c_slave_data_address_i == 8'hF0) //8'hEC - if (wr_en & (i2c_master_to_slave_data_i==8'b00000001))begin - mobeam_start_stop<=1'b1; - end - else if(wr_en & (i2c_master_to_slave_data_i==8'b00000000))begin - mobeam_start_stop<=1'b0; - end - -end - - -//MOBEAM RESET -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - rst_mobeam<=1'b0; - - end -else - if (i2c_slave_data_address_i == 8'hF1) - if (wr_en & (i2c_master_to_slave_data_i==8'b00000001))begin - rst_mobeam<=1'b1; - end - else if(wr_en & (i2c_master_to_slave_data_i==8'b00000000))begin - rst_mobeam<=1'b0; - end - -end - -//REVISION CODE -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - rd_revision_code<=1'b0; - - end -else - if (rd_en)begin - if (i2c_slave_data_address_i == 8'hF2) begin - rd_revision_code<=1'b1; - i2c_slave_to_master_data_o<=revision_code; - end - else begin - rd_revision_code<=1'b0; - i2c_slave_to_master_data_o<=0; - end - end - else - i2c_slave_to_master_data_o<=0; - -end - -//LED POLARITY -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - led_polarity<=1'b0; - - end else begin - //if (wr_en)begin - //if (i2c_slave_data_address_i == 8'hEB)begin - //if (i2c_master_to_slave_data_i==8'b00000001)begin - led_polarity<=1'b1; - //end else begin - //led_polarity<=1'b0; - //end - //end - //end - end -end - -reg ba_wr_en_delayed; -reg wr_en_cnt; -reg [7:0] ba_mem_addr_in_delayed,ba_mem_addr_in_delayed_1; -reg [7:0] data_buffer; -reg [15:0] ba_mem_data_buffer; - - -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - ba_mem_addr_in_delayed<=8'd0; - ba_mem_addr_in_delayed_1<=8'd0; - ba_wr_en_delayed<= 1'b0; - - end -else begin - ba_mem_addr_in_delayed<= ba_mem_addr_in; - ba_mem_addr_in_delayed_1<= ba_mem_addr_in_delayed; - ba_wr_en_delayed<= ba_wr_en; - -end -end - - - - - -//assign ba_mem_data_buffer = { i2c_master_to_slave_data_i,data_buffer}; -always @(posedge clk_i or posedge rst_i) begin - if (rst_i) begin - ba_mem_addr_in <= 9'd0; - ba_wr_en<= 1'b0; - wr_en_cnt<= 1'b0; - end -else - - if (i2c_slave_data_address_i == 8'h00) begin - - if (wr_en_cnt) begin - ba_mem_data_buffer <= { i2c_master_to_slave_data_i,data_buffer}; - end - - - if (wr_en) begin - wr_en_cnt<= wr_en_cnt + 1'b1; - ba_wr_en<= 1'b1; - if (~wr_en_cnt)begin - data_buffer <= i2c_master_to_slave_data_i; - end - else - ba_mem_addr_in <= ba_mem_addr_in + 1'b1; - end - else - ba_wr_en<= 1'b0; - - end - else begin - ba_mem_addr_in<=0; - ba_wr_en<= 1'b0; - wr_en_cnt<=0; - end - -end -endmodule \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v deleted file mode 100644 index f2d0b0a68..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/testpll_pll_20_25Mhz.v +++ /dev/null @@ -1,82 +0,0 @@ -//================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// ------------------------------------------------------------------ -// Copyright (c) 2014 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. - -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// - - -module testpll_pll(REFERENCECLK, - PLLOUTCORE, - PLLOUTGLOBAL, - RESET, - LOCK); - -input REFERENCECLK; -input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */ -output PLLOUTCORE; -output PLLOUTGLOBAL; -output LOCK; - -SB_PLL40_CORE testpll_pll_inst(.REFERENCECLK(REFERENCECLK), - .PLLOUTCORE(PLLOUTCORE), - .PLLOUTGLOBAL(PLLOUTGLOBAL), - .EXTFEEDBACK(), - .DYNAMICDELAY(), - .RESETB(RESET), - .BYPASS(1'b0), - .LATCHINPUTVALUE(), - .LOCK(LOCK), - .SDI(), - .SDO(), - .SCLK()); - -//\\ Fin=27, Fout=20.05; -defparam testpll_pll_inst.DIVR = 4'b0000; -defparam testpll_pll_inst.DIVF = 7'b0010111; -defparam testpll_pll_inst.DIVQ = 3'b101; -defparam testpll_pll_inst.FILTER_RANGE = 3'b011; -defparam testpll_pll_inst.FEEDBACK_PATH = "SIMPLE"; -defparam testpll_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED"; -defparam testpll_pll_inst.FDA_FEEDBACK = 4'b0000; -defparam testpll_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED"; -defparam testpll_pll_inst.FDA_RELATIVE = 4'b0000; -defparam testpll_pll_inst.SHIFTREG_DIV_MODE = 2'b00; -defparam testpll_pll_inst.PLLOUT_SELECT = "GENCLK"; -defparam testpll_pll_inst.ENABLE_ICEGATE = 1'b0; - -endmodule diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v deleted file mode 100644 index 77af4ca73..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/top_module.v +++ /dev/null @@ -1,334 +0,0 @@ -//================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// ------------------------------------------------------------------ -// Copyright (c) 2014 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. - -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// - -//`define SIM -`define i2c -//`define spi -//`define uart - - - -module top_module - // Outputs - ( o_led, - // Inouts - `ifdef i2c - io_i2c_scl, io_i2c_sda, - `endif - //spi signals - `ifdef spi - i_sck, i_csn, i_mosi,o_miso, - `endif - `ifdef uart - o_tx,i_rx, - `endif - //testpoints - drive_on, - // Inputs - i_clk - )/*synthesis syn_dspstyle=logic*/; - - //input i_rst; - - output wire o_led; - output drive_on; - input i_clk; -`ifdef i2c - inout io_i2c_scl; - inout io_i2c_sda; -`endif -`ifdef spi - input i_sck; - input i_csn; - input i_mosi; - output o_miso; -`endif -`ifdef uart - output o_tx; - input i_rx; -`endif - wire sclin_i; - wire sdain_i; - wire sdaout_i; - wire [7:0] datain_i; - wire write_en_i; - wire [7:0] dataout_i; - wire [7:0] regaddr_i; - wire read_en_i; - reg [15:0] poweron_reset_count_i = 0; //initialized for simulation - reg poweron_reset_n_i = 0; // initialized for simulation - wire rst_i; - -//mobeam control logic interface// -wire [15:0] o_ba_mem_data; -wire [7:0] i_ba_mem_addr; -wire i_ba_mem_rd_en; -wire i_ba_mem_rd_clk; -wire rd_revision_code; -wire rst_mobeam; -wire [7:0] o_bsr_mem_data; -wire [8:0] i_bsr_mem_addr; -wire i_bsr_mem_rd_en; -wire i_bsr_mem_rd_clk; -wire o_new_data_rd; -wire o_bsr_data_strobe; -wire i_config_reg_done; -//////////////////////////////// -wire clk_20mhz_g; - -testpll_pll testpll_pll_inst(.REFERENCECLK(i_clk), - .PLLOUTCORE(), - .PLLOUTGLOBAL(clk_20mhz_g), - .RESET(~rst_i/*1'b1*/), - .LOCK()); - -//selection of SPI or I2C/// -`ifdef spi -user_logic_control_reg_spidata_buf spi_mobeam_logic_interface -( -///spi Signal///// - .i_sys_clk(i_clk), - .rst(rst_i), - .i_sck(i_sck), - .i_csn(i_csn), - .i_mosi(i_mosi), - .o_miso(o_miso), -///Mobeam Control Signals/// - .rd_revision_code(rd_revision_code), - .rst_mobeam(rst_mobeam), - .led_polarity(led_polarity), - .mobeam_start_stop(mobeam_start_stop), - .o_ba_mem_data(o_ba_mem_data), - .i_ba_mem_addr(i_ba_mem_addr), - .i_ba_mem_rd_en(i_ba_mem_rd_en), - .i_ba_mem_rd_clk(i_ba_mem_rd_clk), - .o_bsr_mem_data(o_bsr_mem_data), - .i_bsr_mem_addr(i_bsr_mem_addr), - .i_bsr_mem_rd_en(i_bsr_mem_rd_en), - .i_bsr_mem_rd_clk(i_bsr_mem_rd_clk) -// .i_config_reg_done(i_config_reg_done), -// .o_new_data_rd(o_new_data_rd), -// .o_data_strobe(o_bsr_data_strobe) -); -`endif - -`ifdef i2c -user_logic_control_reg_data_buf i2c_mobeam_logic_interface -( -///i2c Signal///// - .clk(clk_20mhz_g), - .rst(rst_i), - .scl(sclin_i), - .sdaout(sdaout_i), - .sdaIn(sdain_i), -///Mobeam Control Signals/// - .rd_revision_code(rd_revision_code), - .rst_mobeam(rst_mobeam), - .led_polarity(led_polarity), - .mobeam_start_stop(mobeam_start_stop), - .o_ba_mem_data(o_ba_mem_data), - .i_ba_mem_addr(i_ba_mem_addr), - .i_ba_mem_rd_en(i_ba_mem_rd_en), - .i_ba_mem_rd_clk(i_ba_mem_rd_clk), - .o_bsr_mem_data(o_bsr_mem_data), - .i_bsr_mem_addr(i_bsr_mem_addr), - .i_bsr_mem_rd_en(i_bsr_mem_rd_en), - .i_bsr_mem_rd_clk(i_bsr_mem_rd_clk) -// .i_config_reg_done(i_config_reg_done), -// .o_new_data_rd(o_new_data_rd), -// .o_data_strobe(o_bsr_data_strobe) -); -`endif - -//-------------------------------------------------------------- - //uart module instantiation -`ifdef uart - uart_top u_inst( - .i_sys_clk (clk_20mhz_g), - .i_sys_rst (rst_i), - .i_rx (i_rx), - //outputs - .o_tx (o_tx), - .o_done (done_i), - ///Mobeam Control Signals - .rd_revision_code (rd_revision_code), - .rst_mobeam (rst_mobeam), - .led_polarity (led_polarity), - .mobeam_start_stop (mobeam_start_stop), - .o_ba_mem_data (o_ba_mem_data), - .i_ba_mem_addr (i_ba_mem_addr), - .i_ba_mem_rd_en (i_ba_mem_rd_en), - .i_ba_mem_rd_clk (i_ba_mem_rd_clk), - .o_bsr_mem_data (o_bsr_mem_data), - .i_bsr_mem_addr (i_bsr_mem_addr), - .i_bsr_mem_rd_en (i_bsr_mem_rd_en), - .i_bsr_mem_rd_clk (i_bsr_mem_rd_clk) - ); -`endif -/////////////////////////////////////////////////////// - -////MobeamControlFSM////// -mobeam_control_fsm fsm_mobeam( - .sys_clk_i(clk_20mhz_g), - ///Mobeam Control Signals/// - .start_stop(mobeam_start_stop), - .rst_mobeam(rst_mobeam|rst_i), - //bsr memory signals - .bsr_mem_data(o_bsr_mem_data), - .bsr_mem_clk(i_bsr_mem_rd_clk), - .bsr_mem_addr(i_bsr_mem_addr), - .bsr_mem_rd_en(i_bsr_mem_rd_en), - - //ba memory signals - .ba_mem_data(o_ba_mem_data), - .ba_mem_clk(i_ba_mem_rd_clk), - .ba_mem_addr(i_ba_mem_addr), - .ba_mem_rd_en(i_ba_mem_rd_en), - - //TO LED DRIVER - .o_byte_data(barcode_array), - .shift_done(byte_done), - .bit_done(bit_done), - .txn_start(txn_start), - // .bsr_load_done(), - .bsr_bw(bar_width) - -); - -wire [7:0] bar_width, barcode_array; -/////LED Driver////// -led_driver led_drive_inst ( - .sys_clk(clk_20mhz_g), - .mobeam_start_stop(mobeam_start_stop), - .led_polarity(led_polarity), - .rst_n(~rst_i|rst_mobeam), - .txn_start(txn_start), - .bar_width(bar_width), - .barcode_array(barcode_array), - .byte_done(byte_done), - .bit_done(bit_done), - .drive_on(drive_on), - .oled(o_led) - //output dynamic_clk); - ); -//////////////////////////////////////// - -//////////////////////////////////////////////// -/////oled data verification///////////////////// - `ifdef SIM - -reg [7:0] capture_oled=0; -reg [7:0] oled_check=0; -integer i=8; -integer mon; - - -initial begin - mon = $fopen("monitor.txt","w"); //file to write -end - -always @(posedge i_clk) begin -// $fwrite(mon,"%h \n",oled_check); - if(txn_start && /*rise_reload_ba_reg_dtc*/fall_reload_ba_reg_dtc) begin - //if(led_polarity) - capture_oled[i]= o_led; - //else - // capture_oled[i]= ~o_led; - end - end - - always @( negedge fall_reload_ba_reg_dtc) begin - if(i==0) begin - oled_check=capture_oled; - - i<=7; - end - else - - i<=i-1; - end - - -always @(posedge i_clk) begin - if(txn_start && byte_done) - $fwrite(mon,"%h \n",oled_check); - end - - - reg q_reload_ba_reg; -always @(posedge i_clk or posedge rst_i) begin - if(rst_i) - q_reload_ba_reg<=0; - else - q_reload_ba_reg<=led_drive_inst.reload_ba_reg; - end -assign rise_reload_ba_reg_dtc=(~q_reload_ba_reg) && led_drive_inst.reload_ba_reg; - -assign fall_reload_ba_reg_dtc=(q_reload_ba_reg) && (~led_drive_inst.reload_ba_reg); - -`endif - -//end -/////////////////////////////////////////////////////////////// -/////////////////////////////////////////////////////////////// -`ifdef i2c - assign io_i2c_sda = (sdaout_i == 1'b0) ? 1'b0 : 1'bz; - assign sdain_i = io_i2c_sda; - assign sclin_i = io_i2c_scl; -`endif - - always @(posedge i_clk)begin - if(poweron_reset_count_i == 256)begin - poweron_reset_count_i <= 256; - end else begin - poweron_reset_count_i <= poweron_reset_count_i + 1; - end - end - - always @(posedge i_clk)begin - if(poweron_reset_count_i == 256)begin - poweron_reset_n_i <= 1; - end else begin - poweron_reset_n_i <= 0; - end - end - assign rst_i = ~poweron_reset_n_i; -endmodule // i2c_slave \ No newline at end of file diff --git a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v b/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v deleted file mode 100644 index e3b434533..000000000 --- a/fpga_flow/benchmarks/Verilog/lattice_ultra_example/UG73-iCE40_Ultra_Barcode_Emulation/hardware/source/top_module/user_logic_control_reg_i2c_data_buf.v +++ /dev/null @@ -1,138 +0,0 @@ -//================================================================== -// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< -// ------------------------------------------------------------------ -// Copyright (c) 2014 by Lattice Semiconductor Corporation -// ALL RIGHTS RESERVED -// ------------------------------------------------------------------ -// -// Permission: -// -// Lattice SG Pte. Ltd. grants permission to use this code for use -// in synthesis for any Lattice programmable logic product. Other -// use of this code, including the selling or duplication of any -// portion is strictly prohibited. - -// -// Disclaimer: -// -// This VHDL or Verilog source code is intended as a design reference -// which illustrates how these types of functions can be implemented. -// It is the user's responsibility to verify their design for -// consistency and functionality through the use of formal -// verification methods. Lattice provides no warranty -// regarding the use or functionality of this code. -// -// -------------------------------------------------------------------- -// -// Lattice SG Pte. Ltd. -// 101 Thomson Road, United Square #07-02 -// Singapore 307591 -// -// -// TEL: 1-800-Lattice (USA and Canada) -// +65-6631-2000 (Singapore) -// +1-503-268-8001 (other locations) -// -// web: http://www.latticesemi.com/ -// email: techsupport@latticesemi.com -// -// -------------------------------------------------------------------- -// - - -module user_logic_control_reg_data_buf -( -///i2c signal///// - clk, - rst, - scl, - sdaout, - sdaIn, -///mobeam control signals/// - rd_revision_code, - rst_mobeam, - led_polarity, - mobeam_start_stop, - o_ba_mem_data, - i_ba_mem_addr, - i_ba_mem_rd_en, - i_ba_mem_rd_clk, - o_bsr_mem_data, - i_bsr_mem_addr, - i_bsr_mem_rd_en, - i_bsr_mem_rd_clk -); -///////i2c signals interface/////// -input clk; -input rst; -inout scl; -output sdaout; -input sdaIn; -////////////////////////////////// -//mobeam control logic interface// -output [15:0] o_ba_mem_data; -input [7:0] i_ba_mem_addr; -input i_ba_mem_rd_en; -input i_ba_mem_rd_clk; -output rd_revision_code; -output rst_mobeam; -output mobeam_start_stop; -output [7:0] o_bsr_mem_data; -input [8:0] i_bsr_mem_addr; -input i_bsr_mem_rd_en; -input i_bsr_mem_rd_clk; - -output led_polarity; - -////////////////////////////////// -///////wires and reg declarations//// -wire[7:0]dataOut; -wire[7:0]regAddr; -wire writeEn; -wire readEn; -wire i2c_start; -wire[7:0]dataIn; -/////////////////////////////////////// -serialInterface i2cslavedatafsm(/*AUTOARG*/ - // Outputs - .dataOut(dataOut), - .regAddr(regAddr), - .sdaOut(sdaout), - .writeEn(writeEn), - .readEn(readEn), - .i2c_start(i2c_start), - // Inputs - .clk(clk), - .dataIn(dataIn), - .rst(rst), - .scl(scl), - .sdaIn(sdaIn) - ); - - - /*mobeam_reg_sets*/mobeam_i2c_reg_interface mobeam_registers( - .rst_i(rst), - .clk_i(clk), - //i2c slave interface signals/// - .i2c_master_to_slave_data_i(dataOut), - .i2c_slave_to_master_data_o(dataIn), - .i2c_slave_data_address_i(regAddr), - .wr_en_i(writeEn), - .rd_en_i(readEn), - .i2c_start_i(i2c_start), - //MoBeam control logic interface// - .rd_revision_code(rd_revision_code), - .rst_mobeam(rst_mobeam), - .led_polarity(led_polarity), - .mobeam_start_stop(mobeam_start_stop), - .o_ba_mem_data(o_ba_mem_data), - .i_ba_mem_addr(i_ba_mem_addr), - .i_ba_mem_rd_en(i_ba_mem_rd_en), - .i_ba_mem_rd_clk(i_ba_mem_rd_clk), - .o_bsr_mem_data(o_bsr_mem_data), - .i_bsr_mem_addr(i_bsr_mem_addr), - .i_bsr_mem_rd_en(i_bsr_mem_rd_en), - .i_bsr_mem_rd_clk(i_bsr_mem_rd_clk) - ); - -endmodule \ No newline at end of file diff --git a/fpga_flow/configs/lattice_benchmark.conf b/fpga_flow/configs/lattice_benchmark.conf deleted file mode 100644 index 7d270f6e3..000000000 --- a/fpga_flow/configs/lattice_benchmark.conf +++ /dev/null @@ -1,31 +0,0 @@ -# Standard Configuration Example -[dir_path] -script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/ -benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/lattice_ultra_example/PID_Controller -yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys -odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe -cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit -abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc -abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc -abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc -mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1 -m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net -mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2 -vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr -rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results -ace_path = OPENFPGAPATHKEYWORD/ace2/ace - -[flow_conf] -#Flow Types standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr -flow_type = yosys_vpr -vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/winbond90/k6_N10_rram_memory_bank_SC_winbond90.xml -mpack1_abc_stdlib = Not_Required -m2net_conf = Not_Required -mpack2_arch = Not_Required -power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/winbond90nm/winbond90nm_power_properties.xml - -[csv_tags] -mpack1_tags = Global mapping efficiency: | efficiency: | occupancy wo buf: | efficiency wo buf: -mpack2_tags = BLE Number: | BLE Fill Rate: -vpr_tags = Netlist clb blocks: | Final critical path: | Total logic delay: | total net delay: | Total routing area: | Total used logic block area: | Total wirelength: | Packing took | Placement took | Routing took | Average net density: | Median net density: | Recommend no. of clock cycles: -vpr_power_tags = PB Types | Routing | Switch Box | Connection Box | Primitives | Interc Structures | lut6 | ff diff --git a/vpr7_x2p/vpr/ARCH/k6_ReRAM_Winbond.xml b/vpr7_x2p/vpr/ARCH/k6_ReRAM_Winbond.xml deleted file mode 100755 index f7cc298a6..000000000 --- a/vpr7_x2p/vpr/ARCH/k6_ReRAM_Winbond.xml +++ /dev/null @@ -1,1453 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - - 10e-12 0e-12 0e-12 - - - 10e-12 0e-12 0e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.I[19:0] clb.O[4:0] - clb.I[39:20] clb.O[9:5] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - From 4f3cb0bdf34c11a76b231c18d65d6a54e16174d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 14:29:50 -0600 Subject: [PATCH 24/84] added tileable routing chanW adaption to fixed W router --- fpga_flow/scripts/fpga_flow.pl | 2 +- vpr7_x2p/vpr/SRC/base/place_and_route.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 23cb76067..6474004a3 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1474,7 +1474,7 @@ sub run_vpr_route($ $ $ $ $ $ $ $ $) my ($chan_width_opt) = (""); if (($fix_chan_width > 0)||($fix_chan_width == 0)) { - $chan_width_opt = "-route_chan_width $fix_chan_width"; + $chan_width_opt = "--route_chan_width $fix_chan_width"; } if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) { $chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width"; diff --git a/vpr7_x2p/vpr/SRC/base/place_and_route.c b/vpr7_x2p/vpr/SRC/base/place_and_route.c index 1e2bad1f2..8c1d410a2 100644 --- a/vpr7_x2p/vpr/SRC/base/place_and_route.c +++ b/vpr7_x2p/vpr/SRC/base/place_and_route.c @@ -153,6 +153,21 @@ void place_and_route(enum e_operation operation, } /* Other constraints can be left to rr_graph to check since this is one pass routing */ + /* Xifan Tang: W estimation for tileable routing architecture */ + /* Build the segment inf vector */ + std::vector segment_vec; + for (int iseg = 0; iseg < det_routing_arch.num_segment; ++iseg) { + segment_vec.push_back(segment_inf[iseg]); + } + + if (TRUE == router_opts.use_tileable_route_chan_width) { + int adapted_W = adapt_to_tileable_route_chan_width(width_fac, segment_vec); + vpr_printf(TIO_MESSAGE_INFO, + "Adapt routing channel width (%d) to be tileable: %d\n", + width_fac, adapted_W); + width_fac = adapted_W; + } + /* Allocate the major routing structures. */ clb_opins_used_locally = alloc_route_structs(); From b79d276ea9bc83c2ce61156a60023729dfffefc8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 14:44:54 -0600 Subject: [PATCH 25/84] add profiling to fpga_x2p_setup --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index df2d52625..0cca853d8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -1310,12 +1310,19 @@ void fpga_x2p_free(t_arch* Arch) { /* Top-level function of FPGA-SPICE setup */ void fpga_x2p_setup(t_vpr_setup vpr_setup, t_arch* Arch) { + /* Timer */ + clock_t t_start; + clock_t t_end; + float run_time_sec; + int num_rename_violation = 0; int num_clocks = 0; float vpr_crit_path_delay = 0.; float vpr_clock_freq = 0.; float vpr_clock_period = 0.; + /* Start time count */ + t_start = clock(); vpr_printf(TIO_MESSAGE_INFO, "\nFPGA-SPICE Tool suites Initilization begins...\n"); @@ -1465,6 +1472,13 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup, spice_net_info_add_density_weight(vpr_setup.FPGA_SPICE_Opts.signal_density_weight); } + /* End time count */ + t_end = clock(); + + run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, "FPGA X2P setup took %g seconds\n", run_time_sec); + + return; } From 6b894640c772e97cd727ba13103ba1294407216b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 14:59:05 -0600 Subject: [PATCH 26/84] bug fixing in fpga_flow.pl --- fpga_flow/scripts/fpga_flow.pl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index d66eb2c17..833045f98 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1460,7 +1460,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) # foreach my $file (0..$#files){ # print "$files[$file]\t"; # } - 3 print "\n"; + # print "\n"; #} chdir $cwd; } From 1a1da30ae96402cdc270caf1801692d9c3935272 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 16:46:43 -0600 Subject: [PATCH 27/84] fixed a critical bug in using tileable route chan W --- vpr7_x2p/vpr/SRC/base/place_and_route.c | 33 +++++++++---------- .../rr_graph/rr_graph_builder_utils.cpp | 8 ++--- .../vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c | 12 +++---- 3 files changed, 24 insertions(+), 29 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/base/place_and_route.c b/vpr7_x2p/vpr/SRC/base/place_and_route.c index 8c1d410a2..c3351c89c 100644 --- a/vpr7_x2p/vpr/SRC/base/place_and_route.c +++ b/vpr7_x2p/vpr/SRC/base/place_and_route.c @@ -353,21 +353,12 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, low = -1; } - /* Xifan Tang: W estimation for tileable routing architecture */ /* Build the segment inf vector */ std::vector segment_vec; for (int iseg = 0; iseg < det_routing_arch.num_segment; ++iseg) { segment_vec.push_back(segment_inf[iseg]); } - if (TRUE == router_opts.use_tileable_route_chan_width) { - int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec); - vpr_printf(TIO_MESSAGE_INFO, - "Adapt routing channel width (%d) to be tileable: %d\n", - current, adapted_W); - current = adapted_W; - } - /* Constraints must be checked to not break rr_graph generator */ if (det_routing_arch.directionality == UNI_DIRECTIONAL) { if (current % 2 != 0) { @@ -390,6 +381,21 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, attempt_count = 0; while (final == -1) { + /* Xifan Tang: W estimation for tileable routing architecture */ + if (TRUE == router_opts.use_tileable_route_chan_width) { + int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec); + vpr_printf(TIO_MESSAGE_INFO, + "Adapt routing channel width (%d) to be tileable: %d\n", + current, adapted_W); + current = adapted_W; + } + /* Do a early exit when the current equals to high or low, + * This means that the current W has been tried already. We just return a final value (high) + */ + if ( (current == high) || (current == low) ) { + final = high; + break; + } vpr_printf(TIO_MESSAGE_INFO, "Using low: %d, high: %d, current: %d\n", low, high, current); fflush(stdout); @@ -509,15 +515,6 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, } } current = current + current % udsd_multiplier; - - /* Xifan Tang: W estimation for tileable routing architecture */ - if (TRUE == router_opts.use_tileable_route_chan_width) { - int adapted_W = adapt_to_tileable_route_chan_width(current, segment_vec); - vpr_printf(TIO_MESSAGE_INFO, - "Adapt routing channel width (%d) to be tileable: %d\n", - current, adapted_W); - current = adapted_W; - } } /* The binary search above occassionally does not find the minimum * diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp index d7d2fcd34..6752def9e 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/rr_graph_builder_utils.cpp @@ -625,7 +625,7 @@ void print_rr_graph_stats() { /* Get the minimum SB mux size */ int num_sb_mux = 0; - short avg_sb_mux_size = 0; + size_t avg_sb_mux_size = 0; for (int inode = 0; inode < num_rr_nodes; ++inode) { /* MUX multiplexers for SBs */ if ( (CHANX == rr_node[inode].type) @@ -640,7 +640,7 @@ void print_rr_graph_stats() { vpr_printf(TIO_MESSAGE_INFO, "Total No. of Switch Block Multiplexer size:%d\n", num_sb_mux); vpr_printf(TIO_MESSAGE_INFO, "Maximum Switch Block Multiplexer size:%d\n", max_sb_mux_size); vpr_printf(TIO_MESSAGE_INFO, "Minimum Switch Block Multiplexer size:%d\n", min_sb_mux_size); - vpr_printf(TIO_MESSAGE_INFO, "Average Switch Block Multiplexer size:%d\n", avg_sb_mux_size); + vpr_printf(TIO_MESSAGE_INFO, "Average Switch Block Multiplexer size:%lu\n", avg_sb_mux_size); vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); /* Get the maximum SB mux size */ @@ -662,7 +662,7 @@ void print_rr_graph_stats() { /* Get the minimum SB mux size */ int num_cb_mux = 0; - short avg_cb_mux_size = 0; + size_t avg_cb_mux_size = 0; for (int inode = 0; inode < num_rr_nodes; ++inode) { /* MUX multiplexers for SBs */ if (IPIN == rr_node[inode].type) { @@ -675,7 +675,7 @@ void print_rr_graph_stats() { vpr_printf(TIO_MESSAGE_INFO, "Total No. of Connection Block Multiplexer size:%d\n", num_cb_mux); vpr_printf(TIO_MESSAGE_INFO, "Maximum Connection Block Multiplexer size:%d\n", max_cb_mux_size); vpr_printf(TIO_MESSAGE_INFO, "Minimum Connection Block Multiplexer size:%d\n", min_cb_mux_size); - vpr_printf(TIO_MESSAGE_INFO, "Average Connection Block Multiplexer size:%d\n", avg_cb_mux_size); + vpr_printf(TIO_MESSAGE_INFO, "Average Connection Block Multiplexer size:%lu\n", avg_cb_mux_size); vpr_printf(TIO_MESSAGE_INFO, "------------------------------------------------\n"); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c index 0cca853d8..011eca31a 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_setup.c @@ -51,8 +51,7 @@ void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, t_spice_model* spice_models); static -void init_and_check_sram_inf(t_arch* arch, - t_det_routing_arch* routing_arch); +void init_and_check_sram_inf(t_arch* arch); static t_llist* check_and_add_one_global_port_to_llist(t_llist* old_head, @@ -378,8 +377,7 @@ void init_and_check_one_sram_inf_orgz(t_sram_inf_orgz* cur_sram_inf_orgz, } static -void init_and_check_sram_inf(t_arch* arch, - t_det_routing_arch* routing_arch) { +void init_and_check_sram_inf(t_arch* arch) { /* We have two branches: * 1. SPICE SRAM organization information * 2. Verilog SRAM organization information @@ -511,7 +509,7 @@ void init_check_arch_spice_models(t_arch* arch, } /* Step C: Find SRAM Model*/ - init_and_check_sram_inf(arch, routing_arch); + init_and_check_sram_inf(arch); /* Step D: Find the segment spice_model*/ for (i = 0; i < arch->num_segments; i++) { @@ -689,7 +687,7 @@ void rec_identify_pb_type_phy_mode(t_pb_type* cur_pb_type) { /* Identify physical mode of pb_types in each defined complex block */ static -void init_check_arch_pb_type_idle_and_phy_mode(t_arch* Arch) { +void init_check_arch_pb_type_idle_and_phy_mode() { int itype; for (itype = 0; itype < num_types; itype++) { @@ -1330,7 +1328,7 @@ void fpga_x2p_setup(t_vpr_setup vpr_setup, init_check_arch_spice_models(Arch, &(vpr_setup.RoutingArch)); /* Initialize idle mode and physical mode of each pb_type and pb_graph_node */ - init_check_arch_pb_type_idle_and_phy_mode(Arch); + init_check_arch_pb_type_idle_and_phy_mode(); /* Create and initialize a linked list for global ports */ global_ports_head = init_llist_global_ports(Arch->spice); From d64aeef5c4eff6dbb086c3a77571f5dcc6e9a97b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 16:57:34 -0600 Subject: [PATCH 28/84] add profiling to routing compact process --- .../SRC/fpga_x2p/base/fpga_x2p_unique_routing.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index 82f8eb688..45c67fa33 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1319,6 +1319,14 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, int num_segments, t_rr_indexed_data* LL_rr_indexed_data) { + /* Timer */ + clock_t t_start; + clock_t t_end; + float run_time_sec; + + /* Start time count */ + t_start = clock(); + /* Create an object */ DeviceRRGSB LL_device_rr_gsb; @@ -1394,6 +1402,12 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, } } + /* End time count */ + t_end = clock(); + + run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniqifying took %g seconds\n", run_time_sec); + return LL_device_rr_gsb; } From 5a50fa84d1f0a562c135277fc767017f577bf0ff Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 3 Jul 2019 22:57:43 -0600 Subject: [PATCH 29/84] keep updating fpga_flow.pl to use system call --- fpga_flow/scripts/fpga_flow.pl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 833045f98..cac4149ac 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1756,7 +1756,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { } # Remove previous route results if (-e $vpr_route) { - `rm $vpr_route`; + system("rm $vpr_route"); } # Keep increase min_chan_width until route success # Extract data from VPR stats @@ -1784,7 +1784,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); # Remove previous route results if (-e $vpr_route) { - `rm $vpr_route`; + system(rm $vpr_route); } # Keep increase min_chan_width until route success &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); @@ -2165,7 +2165,7 @@ sub run_mpack2_flow($ $ $ $) } # Remove previous route results - `rm $vpr_route`; + system("rm $vpr_route"); # Keep increase min_chan_width until route success # Extract data from VPR stats while (1) { @@ -2188,7 +2188,7 @@ sub run_mpack2_flow($ $ $ $) my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); # Remove previous route results if (-e $vpr_route) { - `rm $vpr_route`; + system("rm $vpr_route"); } # Keep increase min_chan_width until route success # Extract data from VPR stats @@ -3542,7 +3542,7 @@ sub gen_csv_rpt($) sub remove_designs() { if ("on" eq $opt_ptr->{remove_designs}) { - `rm -rf $conf_ptr->{dir_path}->{rpt_dir}->{val}`; + system("rm -rf $conf_ptr->{dir_path}->{rpt_dir}->{val}"); } } From c8ceb8f7d56440b9c56d06d2439b907862c8165e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2019 12:23:11 -0600 Subject: [PATCH 30/84] update fpga_flow.pl --- fpga_flow/scripts/fpga_flow.pl | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index cac4149ac..fbbd4fc70 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -12,7 +12,7 @@ use Cwd; use FileHandle; # Multi-thread support use threads; -use threads::shared; +#use threads::shared; # Date my $mydate = gmctime(); @@ -709,8 +709,6 @@ sub run_abc_fpgamap($ $ $) # Get ABC path my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_path}->{val}); - print "Entering $abc_dir\n"; - chdir $abc_dir; my ($lut_num) = $opt_ptr->{K_val}; # Before we run this blif, identify it is a combinational or sequential my ($abc_seq_optimize) = (""); @@ -738,6 +736,9 @@ sub run_abc_fpgamap($ $ $) close($ABC_CMD_FH); # # Create a local copy for the commands + # + print "Entering $abc_dir\n"; + chdir $abc_dir; system("./$abc_name -F $cmd_log > $log"); @@ -3211,7 +3212,13 @@ sub gen_csv_rpt_standard_flow($ $) # Check log/stats one by one foreach $tmp(@benchmark_names) { $tmp =~ s/\.blif$//g; - print $CSVFH "$tmp"; + + if ("on" eq $opt_ptr->{matlab_rpt}) { + print $CSVFH "{'$tmp'}"; + } else { + print $CSVFH "$tmp"; + } + print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{LUTs}"; if ("on" eq $opt_ptr->{min_route_chan_width}) { print $CSVFH ",$rpt_h{$tag}->{$tmp}->{$N_val}->{$K_val}->{min_route_chan_width}"; From 3077efa74f6fa3dd4b7b11dd50a92aec0968be92 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 4 Jul 2019 17:13:34 -0600 Subject: [PATCH 31/84] add option to compact tileable routing arch --- vpr7_x2p/libarchfpga/SRC/include/physical_types.h | 1 + vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c | 8 ++++++-- vpr7_x2p/vpr/SRC/base/SetupVPR.c | 1 + vpr7_x2p/vpr/SRC/base/place_and_route.c | 1 + vpr7_x2p/vpr/SRC/base/vpr_types.h | 1 + vpr7_x2p/vpr/SRC/ctags_vpr_src.sh | 2 +- .../device/rr_graph/tileable_rr_graph_builder.cpp | 10 +++++++--- .../SRC/device/rr_graph/tileable_rr_graph_builder.h | 1 + .../SRC/device/rr_graph/tileable_rr_graph_gsb.cpp | 12 ++++++++++-- .../vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h | 1 + vpr7_x2p/vpr/SRC/place/timing_place_lookup.c | 1 + vpr7_x2p/vpr/SRC/route/route_common.c | 1 + vpr7_x2p/vpr/SRC/route/rr_graph.c | 5 +++-- vpr7_x2p/vpr/SRC/route/rr_graph.h | 2 +- 14 files changed, 36 insertions(+), 11 deletions(-) diff --git a/vpr7_x2p/libarchfpga/SRC/include/physical_types.h b/vpr7_x2p/libarchfpga/SRC/include/physical_types.h index 6e7a064e7..24dee9ea8 100644 --- a/vpr7_x2p/libarchfpga/SRC/include/physical_types.h +++ b/vpr7_x2p/libarchfpga/SRC/include/physical_types.h @@ -936,6 +936,7 @@ struct s_arch { float R_minW_pmos; int Fs; int SubFs; + boolean wire_opposite_side; float C_ipin_cblock; float T_ipin_cblock; /* mrFPGA: Xifan TANG */ diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c index e93a05914..fde8b5472 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c @@ -23,8 +23,8 @@ ***********************************************************************/ /************************************************************************ - * Filename: rr_blocks.cpp - * Created by: Xifan Tang + * Filename: read_xml_arch_file.c + * Created by: Jason Luu * Change history: * +-------------------------------------+ * | Date | Author | Notes @@ -2200,6 +2200,10 @@ static void ProcessDevice(INOUTP ezxml_t Node, OUTP struct s_arch *arch, /* By default, the subFs is the same as the main Fs */ arch->SubFs = GetIntProperty(Cur, "sub_fs", FALSE, arch->Fs); + /* A switch to allow passing tracks wired to the same routing channels */ + arch->wire_opposite_side = GetBooleanProperty(Cur, "wire_opposite_side", FALSE, FALSE); + ezxml_set_attr(Cur, "wire_opposite_side", NULL); + FreeNode(Cur); } diff --git a/vpr7_x2p/vpr/SRC/base/SetupVPR.c b/vpr7_x2p/vpr/SRC/base/SetupVPR.c index 531951966..f120084ea 100644 --- a/vpr7_x2p/vpr/SRC/base/SetupVPR.c +++ b/vpr7_x2p/vpr/SRC/base/SetupVPR.c @@ -541,6 +541,7 @@ static void SetupRoutingArch(INP t_arch Arch, RoutingArch->R_minW_pmos = Arch.R_minW_pmos; RoutingArch->Fs = Arch.Fs; RoutingArch->sub_Fs = Arch.SubFs; + RoutingArch->wire_opposite_side = Arch.wire_opposite_side; RoutingArch->directionality = BI_DIRECTIONAL; if (Arch.Segments) RoutingArch->directionality = Arch.Segments[0].directionality; diff --git a/vpr7_x2p/vpr/SRC/base/place_and_route.c b/vpr7_x2p/vpr/SRC/base/place_and_route.c index c3351c89c..6a73f9cad 100644 --- a/vpr7_x2p/vpr/SRC/base/place_and_route.c +++ b/vpr7_x2p/vpr/SRC/base/place_and_route.c @@ -606,6 +606,7 @@ static int binary_search_place_and_route(struct s_placer_opts placer_opts, chan_width_x[0], NULL, det_routing_arch.switch_block_type, det_routing_arch.Fs, det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, + det_routing_arch.wire_opposite_side, det_routing_arch.num_segment, det_routing_arch.num_switch, segment_inf, det_routing_arch.global_route_switch, diff --git a/vpr7_x2p/vpr/SRC/base/vpr_types.h b/vpr7_x2p/vpr/SRC/base/vpr_types.h index 717be3087..412d6f6e6 100755 --- a/vpr7_x2p/vpr/SRC/base/vpr_types.h +++ b/vpr7_x2p/vpr/SRC/base/vpr_types.h @@ -810,6 +810,7 @@ struct s_det_routing_arch { int Fs; enum e_switch_block_type switch_block_type; int sub_Fs; + boolean wire_opposite_side; enum e_switch_block_type switch_block_sub_type; int num_segment; short num_switch; diff --git a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh index 030dca84f..5a37c337a 100755 --- a/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh +++ b/vpr7_x2p/vpr/SRC/ctags_vpr_src.sh @@ -1,2 +1,2 @@ rm tags -ctags -R shell_main.c main.c ./* ../../libarchfpga/include/*.[ch] ../../libarchfpga/fpga_spice_include/*.[ch] ../../libarchfpga/*.[ch] ../../pcre/SRC/*.[ch] ../../libarchfpga/SRC/include/*.[ch] +ctags -R shell_main.c main.c ./* ../../libarchfpga/SRC/include/*.[ch] ../../libarchfpga/SRC/fpga_spice_include/*.[ch] ../../libarchfpga/SRC/*.[ch] ../../pcre/SRC/*.[ch] diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp index 25fa5929a..fe521ffa0 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp @@ -780,7 +780,8 @@ void build_rr_graph_edges(t_rr_graph* rr_graph, const std::vector segment_inf, int** Fc_in, int** Fc_out, const enum e_switch_block_type sb_type, const int Fs, - const enum e_switch_block_type sb_subtype, const int subFs) { + const enum e_switch_block_type sb_subtype, const int subFs, + const bool wire_opposite_side) { /* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ build_rr_graph_edges_for_source_nodes(rr_graph, grids); @@ -807,7 +808,9 @@ void build_rr_graph_edges(t_rr_graph* rr_graph, /* adapt the switch_block_conn for the GSB nodes */ t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */ - sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, sb_type, Fs, sb_subtype, subFs, segment_inf); + sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, + sb_type, Fs, sb_subtype, subFs, wire_opposite_side, + segment_inf); /* Build edges for a GSB */ build_edges_for_one_tileable_rr_gsb(rr_graph, &rr_gsb, @@ -908,6 +911,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, INP struct s_grid_tile **L_grid, INP const int chan_width, INP const enum e_switch_block_type sb_type, INP const int Fs, INP const enum e_switch_block_type sb_subtype, INP const int subFs, + INP const boolean wire_opposite_side, INP const int num_seg_types, INP const t_segment_inf * segment_inf, INP const int num_switches, INP const int delayless_switch, @@ -1025,7 +1029,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, /* Create edges for a tileable rr_graph */ build_rr_graph_edges(&rr_graph, device_size, grids, device_chan_width, segment_infs, Fc_in, Fc_out, - sb_type, Fs, sb_subtype, subFs); + sb_type, Fs, sb_subtype, subFs, (bool)wire_opposite_side); /************************************************************************ * 6.2 Build direction connection lists diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h index 41ad7c485..1494aec13 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.h @@ -12,6 +12,7 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, INP struct s_grid_tile **L_grid, INP const int chan_width, INP const enum e_switch_block_type sb_type, INP const int Fs, INP const enum e_switch_block_type sb_subtype, INP const int subFs, + INP const boolean wire_opposite_side, INP const int num_seg_types, INP const t_segment_inf * segment_inf, INP const int num_switches, INP const int delayless_switch, diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp index 27f111091..02e7e4701 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp @@ -357,6 +357,7 @@ void build_gsb_one_group_track_to_track_map(const t_rr_graph* rr_graph, const RRGSB& rr_gsb, const enum e_switch_block_type sb_type, const int Fs, + const bool wire_opposite_side, const t_track_group from_tracks, /* [0..gsb_side][track_indices] */ const t_track_group to_tracks, /* [0..gsb_side][track_indices] */ t_track2track_map* track2track_map) { @@ -387,7 +388,11 @@ void build_gsb_one_group_track_to_track_map(const t_rr_graph* rr_graph, if (from_side == to_side) { continue; } - + /* Bypass those from_side is opposite to to_side if required */ + if ( (true == wire_opposite_side) + && (to_side_manager.get_opposite() == from_side) ) { + continue; + } /* Get other track_ids depending on the switch block pattern */ /* Find the track ids that will start at the other sides */ std::vector to_track_ids = get_switch_block_to_track_id(sb_type, Fs, from_side, inode, @@ -477,6 +482,7 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, const int Fs, const enum e_switch_block_type sb_subtype, const int subFs, + const bool wire_opposite_side, const std::vector segment_inf) { t_track2track_map track2track_map; /* [0..gsb_side][0..chan_width][track_indices] */ @@ -549,7 +555,8 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, /* For Group 1: we build connections between end_tracks and start_tracks*/ build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, sb_type, Fs, - end_tracks, start_tracks, + true, /* End tracks should always to wired to start tracks */ + end_tracks, start_tracks, &track2track_map); /* For Group 2: we build connections between end_tracks and start_tracks*/ @@ -558,6 +565,7 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, */ build_gsb_one_group_track_to_track_map(rr_graph, rr_gsb, sb_subtype, subFs, + wire_opposite_side, /* Pass tracks may not be wired to start tracks */ pass_tracks, start_tracks, &track2track_map); diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h index 5f5a4cb49..c860c3695 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.h @@ -25,6 +25,7 @@ t_track2track_map build_gsb_track_to_track_map(const t_rr_graph* rr_graph, const int Fs, const enum e_switch_block_type sb_subtype, const int subFs, + const bool wire_opposite_side, const std::vector segment_inf); RRGSB build_one_tileable_rr_gsb(const DeviceCoordinator& device_range, diff --git a/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c b/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c index b0d6bdbc9..371825e90 100755 --- a/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c +++ b/vpr7_x2p/vpr/SRC/place/timing_place_lookup.c @@ -462,6 +462,7 @@ static void alloc_routing_structs(struct s_router_opts router_opts, chan_width_x[0], NULL, det_routing_arch.switch_block_type, det_routing_arch.Fs, det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, + det_routing_arch.wire_opposite_side, det_routing_arch.num_segment, det_routing_arch.num_switch, segment_inf, det_routing_arch.global_route_switch, diff --git a/vpr7_x2p/vpr/SRC/route/route_common.c b/vpr7_x2p/vpr/SRC/route/route_common.c index 58cbfca31..ad8f2d8eb 100755 --- a/vpr7_x2p/vpr/SRC/route/route_common.c +++ b/vpr7_x2p/vpr/SRC/route/route_common.c @@ -300,6 +300,7 @@ boolean try_route(int width_fac, struct s_router_opts router_opts, chan_width_x[0], NULL, det_routing_arch.switch_block_type, det_routing_arch.Fs, det_routing_arch.switch_block_sub_type, det_routing_arch.sub_Fs, + det_routing_arch.wire_opposite_side, det_routing_arch.num_segment, det_routing_arch.num_switch, segment_inf, det_routing_arch.global_route_switch, diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph.c b/vpr7_x2p/vpr/SRC/route/rr_graph.c index d6edcf7fd..1c9c01e18 100755 --- a/vpr7_x2p/vpr/SRC/route/rr_graph.c +++ b/vpr7_x2p/vpr/SRC/route/rr_graph.c @@ -213,7 +213,8 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types, INP struct s_grid_tile **L_grid, INP int chan_width, INP struct s_chan_width_dist *chan_capacity_inf, INP enum e_switch_block_type sb_type, INP int Fs, - INP enum e_switch_block_type sb_sub_type, INP int sub_Fs, INP int num_seg_types, + INP enum e_switch_block_type sb_sub_type, INP int sub_Fs, INP boolean wire_opposite_side, + INP int num_seg_types, INP int num_switches, INP t_segment_inf * segment_inf, INP int global_route_switch, INP int delayless_switch, INP t_timing_inf timing_inf, INP int wire_to_ipin_switch, @@ -228,7 +229,7 @@ void build_rr_graph(INP t_graph_type graph_type, INP int L_num_types, L_nx, L_ny, L_grid, chan_width, sb_type, Fs, - sb_sub_type, sub_Fs, + sb_sub_type, sub_Fs, wire_opposite_side, num_seg_types, segment_inf, num_switches, delayless_switch, timing_inf, wire_to_ipin_switch, diff --git a/vpr7_x2p/vpr/SRC/route/rr_graph.h b/vpr7_x2p/vpr/SRC/route/rr_graph.h index 1a84393b7..a0dd91644 100755 --- a/vpr7_x2p/vpr/SRC/route/rr_graph.h +++ b/vpr7_x2p/vpr/SRC/route/rr_graph.h @@ -28,7 +28,7 @@ void build_rr_graph(INP t_graph_type graph_type, INP struct s_chan_width_dist *chan_capacity_inf, INP enum e_switch_block_type sb_type, INP int Fs, - INP enum e_switch_block_type sb_sub_type, INP int sub_Fs, + INP enum e_switch_block_type sb_sub_type, INP int sub_Fs, INP boolean wire_opposite_side, INP int num_seg_types, INP int num_switches, INP t_segment_inf * segment_inf, From f56adc681567b73c7826228641e089482dffc009 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 5 Jul 2019 10:20:16 -0600 Subject: [PATCH 32/84] Update documentation --- .../fpga_verilog/command_line_usage.rst | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst index 6e1fc1239..3deb835a6 100644 --- a/docs/source/fpga_verilog/command_line_usage.rst +++ b/docs/source/fpga_verilog/command_line_usage.rst @@ -8,11 +8,12 @@ FPGA-Verilog Supported Options:: --fpga_verilog --fpga_verilog_dir --fpga_verilog_include_timing - --fpga_verilog_init_sim - --fpga_verilog_print_modelsim_autodeck - --fpga_verilog_modelsim_ini_path + --fpga_verilog_include_signal_init + --fpga_verilog_print_modelsim_autodeck --fpga_verilog_print_top_testbench - --fpga_verilog_print_top_auto_testbench + --fpga_verilog_print_autocheck_top_testbench + --fpga_verilog_print_formal_verification_top_netlist + --fpga_verilog_include_icarus_simulator .. csv-table:: Commmand-line Options of FPGA-Verilog @@ -20,14 +21,15 @@ FPGA-Verilog Supported Options:: :widths: 15, 30 "--fpga_verilog", "Turn on the FPGA-Verilog." - "--fpga_verilog_dir ", "Specify the directory that all the Verilog files will be outputted to. is the destination directory." - "--fpga_verilog_include_timing", "Includes the timings found in the XML file." - "--fpga_verilog_init_sim", "Initializes the simulation for ModelSim." - "--fpga_verilog_print_modelsim_autodeck", "Generates the scripts necessary to the ModelSim simulation." - "--fpga_verilog_modelsim_ini_path ", "Gives the path for the .ini necessary to ModelSim." - "--fpga_verilog_print_top_testbench", "Print the full-chip-level testbench for the FPGA. Determines the type of autodeck." - "--fpga_verilog_print_top_auto_testbench \ - ", "Prints the testbench associated with the given benchmark. Determines the type of autodeck." + "--fpga_verilog_dir ", "Specify the directory where all the Verilog files will be outputted to. is the destination directory." + "--fpga_verilog_include_timing", "Includes the timings found in the XML architecture description file." + "--fpga_verilog_include_signal_init", "Set all nets to random value to be close of a real power-on case" + "--fpga_verilog_print_modelsim_autodeck ", "Generates the scripts necessary to the ModelSim simulation and specify the path to modelsim.ini file." + "--fpga_verilog_print_top_testbench", "Prints the full-chip-level testbench for the FPGA, which includes programming phase and operationg phase (random patterns)." + "--fpga_verilog_print_autocheck_top_testbench \ + ", "Prints a testbench stimulating the generated FPGA and the initial benchmark to compare stimuli responses, which includes programming phase and operationg phase (random patterns)" + "--fpga_verilog_print_formal_verification_top_netlist", "Prints a Verilog top file compliant with formal verification tools. With this top file the FPGA is initialy programmed. It also prints a testbench with random patterns, which can be manually or automatically check regarding previous options." + "--fpga_verilog_include_icarus_simulator", "Activates waveforms .vcd file generation and simulation timeout, which are required for Icarus Verilog simulator" .. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are: From 27dbc527a0f75911dc6980b3d6eec3fa8eac460a Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 5 Jul 2019 11:06:55 -0600 Subject: [PATCH 33/84] Update Readme --- README.md | 21 ++++++++++++------- compilation/macos_compilation.md | 4 ++-- compilation/red_hat_compilation.md | 4 ++-- compilation/ubuntu_compilation.md | 4 ++-- .../fpga_verilog/command_line_usage.rst | 2 +- 5 files changed, 20 insertions(+), 15 deletions(-) diff --git a/README.md b/README.md index 2e5089786..ed700daca 100644 --- a/README.md +++ b/README.md @@ -1,23 +1,28 @@ -# Getting Started with FPGA-SPICE +# Getting Started with OpenFPGA [![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) ## Introduction -FPGA-SPICE is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of heterogeneous architectures. +OpenFPGA is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures. ## Compilation -The different ways of compiling can be found in the **./compilation** folder. +The different ways of compiling can be found in the **./compilation** folder. -We currently implemented it for: +**Compilation steps:** +1. Create a folder named build in OpenPFGA repository (mkdir build && cd build) +2. Create Makefile in this folder using cmake (cmake ..) +3. Compile the tool and its dependencies (make) -1. Ubuntu 18.04 -2. Red Hat 7.5 -3. MacOS High Sierra 10.13.4 +*We currently implemented OpenFPGA for:* -Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions. +*1. Ubuntu 18.04* +*2. Red Hat 7.5* +*3. MacOS High Sierra 10.13.4* + +*Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.* ## Documentation OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options. diff --git a/compilation/macos_compilation.md b/compilation/macos_compilation.md index f5589b386..c5de47da7 100644 --- a/compilation/macos_compilation.md +++ b/compilation/macos_compilation.md @@ -32,9 +32,9 @@ This will show the different options that can be used. Our modifications concern A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog -`source ./go.sh` +`source ./go_fpga_verilog.sh` -This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate. +This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate. For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html). As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture. diff --git a/compilation/red_hat_compilation.md b/compilation/red_hat_compilation.md index cc45e39a8..2fc0c14fd 100644 --- a/compilation/red_hat_compilation.md +++ b/compilation/red_hat_compilation.md @@ -32,9 +32,9 @@ This will show the different options that can be used. Our modifications concern A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog -`source ./go.sh` +`source ./go_fpga_verilog.sh` -This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate. +This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate. For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html). As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture. diff --git a/compilation/ubuntu_compilation.md b/compilation/ubuntu_compilation.md index 85627de66..63bb79ca3 100644 --- a/compilation/ubuntu_compilation.md +++ b/compilation/ubuntu_compilation.md @@ -29,9 +29,9 @@ This will show the different options that can be used. Our modifications concern A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog -`source ./go.sh` +`source ./go_fpga_verilog.sh` -This script uses the enhanced version of vpr with some new options such as --fpga_spice_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate. +This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate. For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html). As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture. diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst index 6e1fc1239..29eb72b0a 100644 --- a/docs/source/fpga_verilog/command_line_usage.rst +++ b/docs/source/fpga_verilog/command_line_usage.rst @@ -20,7 +20,7 @@ FPGA-Verilog Supported Options:: :widths: 15, 30 "--fpga_verilog", "Turn on the FPGA-Verilog." - "--fpga_verilog_dir ", "Specify the directory that all the Verilog files will be outputted to. is the destination directory." + "--fpga_verilog_dir ", "Specify the directory that all the Verilog files will be outputted to is the destination directory." "--fpga_verilog_include_timing", "Includes the timings found in the XML file." "--fpga_verilog_init_sim", "Initializes the simulation for ModelSim." "--fpga_verilog_print_modelsim_autodeck", "Generates the scripts necessary to the ModelSim simulation." From 64d8e9663a40d8f0c3dbfdabbfc31080c6824aed Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2019 13:13:35 -0600 Subject: [PATCH 34/84] minor fix to satisfy Fc_in and Fc_out --- .../device/rr_graph/tileable_rr_graph_gsb.cpp | 24 +++++++++++++++---- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp index 02e7e4701..f1c497ca2 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp @@ -1062,13 +1062,13 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, assert (0 == actual_track_list.size() % 2); /* Scale Fc */ - int actual_Fc = Fc * actual_track_list.size() / chan_width; + int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */ actual_Fc = std::max(2, actual_Fc); /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in */ - size_t track_step = actual_track_list.size() / actual_Fc; + size_t track_step = std::ceil((float)actual_track_list.size() / (float)actual_Fc); /* Track step mush be a multiple of 2!!!*/ if (0 != track_step % 2) { track_step--; /* minus 1 to increase connectivity */ @@ -1078,7 +1078,9 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, /* Adapt offset to the range of actual_track_list */ size_t actual_offset = offset % actual_track_list.size(); /* rotate the track list by an offset */ - std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + if (0 < actual_offset) { + std::rotate(actual_track_list.begin(), actual_track_list.begin() + actual_offset, actual_track_list.end()); + } /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */ int track_cnt = 0; @@ -1108,6 +1110,12 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, /* Ensure the number of tracks is similar to Fc */ //printf("Fc_in=%d, track_cnt=%d\n", actual_Fc, track_cnt); assert (actual_Fc <= track_cnt); + /* Give a warning if Fc is < track_cnt */ + if (actual_Fc < track_cnt) { + vpr_printf(TIO_MESSAGE_INFO, + "Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than IPINs!\n", + ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); + } } return; @@ -1163,13 +1171,13 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, } /* Scale Fc */ - int actual_Fc = Fc * actual_track_list.size() / chan_width; + int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); /* Minimum Fc should be 1 : ensure we will drive 1 routing track */ actual_Fc = std::max(1, actual_Fc); /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in */ - size_t track_step = actual_track_list.size() / actual_Fc; + size_t track_step = std::ceil((float)actual_track_list.size() / (float)actual_Fc); /* Track step mush be a multiple of 2!!!*/ /* Make sure step should be at least 1 */ track_step = std::max(1, (int)track_step); @@ -1203,6 +1211,12 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, /* Ensure the number of tracks is similar to Fc */ //printf("Fc_out=%lu, scaled_Fc_out=%d, track_cnt=%d, actual_track_cnt=%lu/%lu\n", Fc, actual_Fc, track_cnt, actual_track_list.size(), chan_width); assert (actual_Fc <= track_cnt); + /* Give a warning if Fc is < track_cnt */ + if (actual_Fc < track_cnt) { + vpr_printf(TIO_MESSAGE_INFO, + "Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than OPINs!\n", + opin_node_id, track_cnt, actual_Fc); + } } return; From df53f6da2c6c1ec41fae328caa5b9142de779a3b Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 5 Jul 2019 13:41:34 -0600 Subject: [PATCH 35/84] Updates FPGA-Verilog command lines --- docs/source/fpga_verilog/command_line_usage.rst | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst index aa5b8f702..dfe34eaea 100644 --- a/docs/source/fpga_verilog/command_line_usage.rst +++ b/docs/source/fpga_verilog/command_line_usage.rst @@ -40,6 +40,13 @@ FPGA-Verilog Supported Options:: ", "Prints a testbench stimulating the generated FPGA and the initial benchmark to compare stimuli responses, which includes programming phase and operationg phase (random patterns)" "--fpga_verilog_print_formal_verification_top_netlist", "Prints a Verilog top file compliant with formal verification tools. With this top file the FPGA is initialy programmed. It also prints a testbench with random patterns, which can be manually or automatically check regarding previous options." "--fpga_verilog_include_icarus_simulator", "Activates waveforms .vcd file generation and simulation timeout, which are required for Icarus Verilog simulator" + "--fpga_verilog_print_input_blif_testbench", "Generates a Verilog test-bench to use with input blif file" + "--fpga_verilog_print_report_timing_tcl", "Generates tcl commands to run STA analysis with TO COMPLETE TOOL" + "--fpga_verilog_report_timing_rpt_path ", "Specifies path where report timing are written" + "--fpga_verilog_print_sdc_pnr", "Generates SDC constraints to PNR" + "--fpga_verilog_print_sdc_analysis", "Generates SDC to run timing analysis in PNR tool" + "--fpga_verilog_print_user_defined_template", "Generates a template of hierarchy modules and their port mapping" + "", "" >>>>>>> f56adc681567b73c7826228641e089482dffc009 .. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are: From c62762ce59e7cb62db5bad573c3a602e52d7fd10 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2019 13:42:22 -0600 Subject: [PATCH 36/84] bug fixing in assign ipins to tracks using Fc_in --- .../device/rr_graph/tileable_rr_graph_gsb.cpp | 21 ++++++++----------- 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp index f1c497ca2..252d929b3 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp @@ -1064,17 +1064,14 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, /* Scale Fc */ int actual_Fc = std::ceil((float)Fc * (float)actual_track_list.size() / (float)chan_width); /* Minimum Fc should be 2 : ensure we will connect to a pair of routing tracks */ - actual_Fc = std::max(2, actual_Fc); + actual_Fc = std::max(1, actual_Fc); /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in + * For uni-directional arch, all the tracks are in pair, we will divide by 2 to be normalized (Fc counts pairs) */ - size_t track_step = std::ceil((float)actual_track_list.size() / (float)actual_Fc); - /* Track step mush be a multiple of 2!!!*/ - if (0 != track_step % 2) { - track_step--; /* minus 1 to increase connectivity */ - } + size_t track_step = std::ceil((float)(actual_track_list.size() / 2) / (float)actual_Fc); /* Make sure step should be at least 2 */ - track_step = std::max(2, (int)track_step); + track_step = std::max(1, (int)track_step); /* Adapt offset to the range of actual_track_list */ size_t actual_offset = offset % actual_track_list.size(); /* rotate the track list by an offset */ @@ -1109,12 +1106,12 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, /* Ensure the number of tracks is similar to Fc */ //printf("Fc_in=%d, track_cnt=%d\n", actual_Fc, track_cnt); - assert (actual_Fc <= track_cnt); + assert (2 * actual_Fc <= track_cnt); /* Give a warning if Fc is < track_cnt */ - if (actual_Fc < track_cnt) { + if (2 * actual_Fc < track_cnt) { vpr_printf(TIO_MESSAGE_INFO, - "Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than IPINs!\n", - ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); + "IPIN Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than IPINs!\n", + ipin_node - rr_graph->rr_node, track_cnt, 2 * actual_Fc); } } @@ -1214,7 +1211,7 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, /* Give a warning if Fc is < track_cnt */ if (actual_Fc < track_cnt) { vpr_printf(TIO_MESSAGE_INFO, - "Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than OPINs!\n", + "OPIN Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than OPINs!\n", opin_node_id, track_cnt, actual_Fc); } } From 76fefdb8766f627ccbc23f5e566c7841e02c644b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 5 Jul 2019 16:23:15 -0600 Subject: [PATCH 37/84] bug fixing in Fc_in and be serious in the performance of rr_graph --- .../device/rr_graph/tileable_rr_graph_gsb.cpp | 43 +++++++++---------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp index 252d929b3..aa6fcc2aa 100755 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_gsb.cpp @@ -1067,9 +1067,8 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, actual_Fc = std::max(1, actual_Fc); /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in - * For uni-directional arch, all the tracks are in pair, we will divide by 2 to be normalized (Fc counts pairs) - */ - size_t track_step = std::ceil((float)(actual_track_list.size() / 2) / (float)actual_Fc); + */ + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); /* Make sure step should be at least 2 */ track_step = std::max(1, (int)track_step); /* Adapt offset to the range of actual_track_list */ @@ -1081,38 +1080,35 @@ void build_gsb_one_ipin_track2pin_map(const t_rr_graph* rr_graph, /* Assign tracks: since we assign 2 track per round, we increment itrack by 2* step */ int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + 2 * track_step) { /* Update pin2track map */ size_t chan_side_index = chan_side_manager.to_size_t(); size_t ipin_index = ipin_node - rr_graph->rr_node; + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); /* track_index may exceed the chan_width(), adapt it */ - size_t track_index = actual_track_list[itrack] % chan_width; + size_t track_index = actual_track_list[actual_itrack] % chan_width; (*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index); /* track_index may exceed the chan_width(), adapt it */ - track_index = (actual_track_list[itrack] + 1) % chan_width; + track_index = (actual_track_list[actual_itrack] + 1) % chan_width; (*track2ipin_map)[chan_side_index][track_index].push_back(ipin_index); track_cnt += 2; - /* Stop when we have enough Fc: this may lead to some tracks have zero drivers. - * So I comment it. And we just make sure its track_cnt >= actual_Fc - if (actual_Fc == track_cnt) { - break; - } - */ } /* Ensure the number of tracks is similar to Fc */ - //printf("Fc_in=%d, track_cnt=%d\n", actual_Fc, track_cnt); - assert (2 * actual_Fc <= track_cnt); /* Give a warning if Fc is < track_cnt */ - if (2 * actual_Fc < track_cnt) { + /* + if (actual_Fc != track_cnt) { vpr_printf(TIO_MESSAGE_INFO, - "IPIN Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than IPINs!\n", - ipin_node - rr_graph->rr_node, track_cnt, 2 * actual_Fc); + "IPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", + ipin_node - rr_graph->rr_node, track_cnt, actual_Fc); } + */ } return; @@ -1174,7 +1170,7 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, /* Compute the step between two connection from this IPIN to tracks: * step = W' / Fc', W' and Fc' are the adapted W and Fc from actual_track_list and Fc_in */ - size_t track_step = std::ceil((float)actual_track_list.size() / (float)actual_Fc); + size_t track_step = std::floor((float)actual_track_list.size() / (float)actual_Fc); /* Track step mush be a multiple of 2!!!*/ /* Make sure step should be at least 1 */ track_step = std::max(1, (int)track_step); @@ -1189,10 +1185,13 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, /* Assign tracks */ int track_cnt = 0; + /* Keep assigning until we meet the Fc requirement */ for (size_t itrack = 0; itrack < actual_track_list.size(); itrack = itrack + track_step) { /* Update pin2track map */ size_t opin_side_index = opin_side_manager.to_size_t(); - size_t track_index = actual_track_list[itrack]; + /* itrack may exceed the size of actual_track_list, adapt it */ + size_t actual_itrack = itrack % actual_track_list.size(); + size_t track_index = actual_track_list[actual_itrack]; size_t track_rr_node_index = rr_gsb.get_chan_node(chan_side, track_index) - rr_graph->rr_node; (*opin2track_map)[opin_side_index][opin_node_id].push_back(track_rr_node_index); /* update track counter */ @@ -1206,14 +1205,14 @@ void build_gsb_one_opin_pin2track_map(const t_rr_graph* rr_graph, } /* Ensure the number of tracks is similar to Fc */ - //printf("Fc_out=%lu, scaled_Fc_out=%d, track_cnt=%d, actual_track_cnt=%lu/%lu\n", Fc, actual_Fc, track_cnt, actual_track_list.size(), chan_width); - assert (actual_Fc <= track_cnt); /* Give a warning if Fc is < track_cnt */ - if (actual_Fc < track_cnt) { + /* + if (actual_Fc != track_cnt) { vpr_printf(TIO_MESSAGE_INFO, - "OPIN Node(%lu) will have a higher Fc(=%lu) than specified(=%lu)!\nThis is due to that the number of tracks is much larger than OPINs!\n", + "OPIN Node(%lu) will have a different Fc(=%lu) than specified(=%lu)!\n", opin_node_id, track_cnt, actual_Fc); } + */ } return; From ae05c553d55bbaa171531c6e2461fbbaf3b2ecee Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 8 Jul 2019 09:48:33 -0600 Subject: [PATCH 38/84] Top module done --- .../verilog/verilog_compact_netlist.c | 14 ++--- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 52 ++++++++++++------ .../SRC/fpga_x2p/verilog/verilog_pbtypes.h | 3 +- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 54 +++++++++++++++++-- .../SRC/fpga_x2p/verilog/verilog_routing.c | 4 +- .../verilog/verilog_top_netlist_utils.c | 5 +- .../verilog/verilog_top_netlist_utils.h | 3 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 24 ++++++++- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.h | 6 ++- 9 files changed, 131 insertions(+), 34 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 57be783cf..4d8471798 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -361,7 +361,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "module %s ( \n", subckt_name); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -378,7 +378,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf /* I/O PAD */ dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, 0, phy_block_type->capacity * phy_block_type->pb_type->physical_mode_num_iopads - 1, - VERILOG_PORT_INOUT); + VERILOG_PORT_INOUT, is_explicit_mapping); /* Print configuration ports */ /* Reserved configuration ports */ @@ -406,7 +406,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, 0, temp_conf_bits_msb - 1, - VERILOG_PORT_INPUT, is_explicit_mapping); // Should be modified to be VERILOG_PORT_INPUT + VERILOG_PORT_INPUT, false); // Should be modified to be VERILOG_PORT_INPUT fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -436,9 +436,9 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf /* Print all the pins */ /* Special Care for I/O grid */ if (IO_TYPE == phy_block_type) { - dump_compact_verilog_io_grid_block_subckt_pins(fp, phy_block_type, border_side, iz); + dump_compact_verilog_io_grid_block_subckt_pins(fp, phy_block_type, border_side, iz, is_explicit_mapping); } else { - dump_verilog_grid_block_subckt_pins(fp, iz, phy_block_type); + dump_verilog_grid_block_subckt_pins(fp, iz, phy_block_type, is_explicit_mapping); } /* Print configuration ports */ @@ -450,7 +450,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf fprintf(fp, "\n//---- IOPAD ----\n"); dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, temp_iopad_lsb, temp_iopad_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); /* Reserved configuration ports */ if (0 < temp_reserved_conf_bits_msb) { fprintf(fp, ",\n"); @@ -631,7 +631,7 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, iopad_verilog_model->grid_index_low[ix][iy], iopad_verilog_model->grid_index_high[ix][iy] - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); /* Print configuration ports */ /* Reserved configuration ports */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 80ed46195..a779ee550 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -370,8 +370,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, port_prefix, pb_type_port->name); } else { if ((NULL != cur_pb_type->spice_model) - && (TRUE == dump_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + && (TRUE == dump_explicit_port_map)) { fprintf(fp, ".%s(", pb_type_port->spice_model_port->lib_name); } @@ -385,8 +384,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, } fprintf(fp, "}"); if ((NULL != cur_pb_type->spice_model) - && (TRUE == dump_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + && (TRUE == dump_explicit_port_map)) { fprintf(fp, ")"); } } @@ -1733,7 +1731,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, */ fprintf(fp, "\n"); /* dump global ports */ - if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { + if(0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } /* Simplify the port prefix, make SPICE netlist readable */ @@ -1742,7 +1740,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, stamped_iopad_cnt, iopad_verilog_model->cnt - 1, - VERILOG_PORT_INOUT); + VERILOG_PORT_INOUT, is_explicit_mapping); /* Print Configuration ports */ /* sram_verilog_model->cnt should be updated because all the child pbs have been dumped * stamped_sram_cnt remains the old sram_verilog_model->cnt before all the child pbs are dumped @@ -1848,7 +1846,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, gio_inout_prefix, stamped_iopad_cnt, stamped_iopad_cnt + child_pb_num_iopads - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); /* update stamped outpad counter */ stamped_iopad_cnt += child_pb_num_iopads; /* Print configuration ports */ @@ -1889,7 +1887,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* Print interconnections, set is_idle as TRUE*/ dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name, cur_pb_graph_node, mode_index, - is_explicit_mapping); + false); /* Check each pins of pb_graph_node */ /* Check and update stamped_sram_cnt */ /* Now we only dump one Verilog for each pb_type, and instance them when num_pb > 1 @@ -2279,9 +2277,11 @@ char* verilog_get_grid_phy_block_subckt_name(int x, int y, int z, /* Print the pins of grid subblocks */ void dump_verilog_grid_block_subckt_pins(FILE* fp, int z, - t_type_ptr type_descriptor) { + t_type_ptr type_descriptor, + bool is_explicit_mapping) { int iport, ipin, side, dump_pin_cnt; int grid_pin_index, pin_height, side_pin_index; + t_port* cur_port; t_pb_graph_node* top_pb_graph_node = NULL; /* Check the file handler*/ @@ -2313,8 +2313,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->input_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_ ", convert_side_index_to_string(side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } dump_pin_cnt++; side_pin_index++; } @@ -2338,8 +2345,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->output_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_ ", convert_side_index_to_string(side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } dump_pin_cnt++; side_pin_index++; } @@ -2363,8 +2377,15 @@ void dump_verilog_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->clock_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_ ", convert_side_index_to_string(side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } dump_pin_cnt++; side_pin_index++; } @@ -2381,7 +2402,8 @@ void dump_verilog_io_grid_block_subckt_pins(FILE* fp, int x, int y, int z, - t_type_ptr type_descriptor) { + t_type_ptr type_descriptor, + bool is_explicit_mapping) { int iport, ipin, side, dump_pin_cnt; int grid_pin_index, pin_height, side_pin_index; t_pb_graph_node* top_pb_graph_node = NULL; @@ -2552,7 +2574,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "module %s ( \n", gen_verilog_one_grid_module_name(ix, iy)); fprintf(fp, "\n"); /* dump global ports */ - if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, is_explicit_mapping)) { + if (0 < dump_verilog_global_ports(fp, global_ports_head, TRUE, false)) { fprintf(fp, ",\n"); } @@ -2568,7 +2590,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, iopad_verilog_model->grid_index_low[ix][iy], iopad_verilog_model->grid_index_high[ix][iy] - 1, - VERILOG_PORT_INPUT); + VERILOG_PORT_INPUT, is_explicit_mapping); /* Print configuration ports */ /* Reserved configuration ports */ @@ -2631,9 +2653,9 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, /* Print all the pins */ /* Special Care for I/O grid */ if (IO_TYPE == grid[ix][iy].type) { - dump_verilog_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type); + dump_verilog_io_grid_block_subckt_pins(fp, ix, iy, iz, grid[ix][iy].type, is_explicit_mapping); } else { - dump_verilog_grid_block_subckt_pins(fp, iz, grid[ix][iy].type); + dump_verilog_grid_block_subckt_pins(fp, iz, grid[ix][iy].type, is_explicit_mapping); } /* Print configuration ports */ temp_reserved_conf_bits_msb = grid[ix][iy].type->pb_type->physical_mode_num_reserved_conf_bits; @@ -2645,7 +2667,7 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, temp_iopad_lsb, temp_iopad_msb - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); assert(!(0 > temp_conf_bits_msb - temp_conf_bits_lsb)); /* Reserved configuration ports */ if (0 < temp_reserved_conf_bits_msb) { diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h index 3ad43e94c..25ffcd85d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h @@ -127,7 +127,8 @@ char* get_grid_block_subckt_name(int x, void dump_verilog_grid_block_subckt_pins(FILE* fp, int z, - t_type_ptr type_descriptor); + t_type_ptr type_descriptor, + bool is_explicit_mapping); void dump_verilog_io_grid_block_subckt_pins(FILE* fp, int x, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index a735d36fb..3354a8938 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -610,7 +610,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, /* Connect inputs*/ /* Connect outputs*/ fprintf(fp, "//----- Input and output ports -----\n"); - dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, verilog_model->dump_explicit_port_map); + dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping)); fprintf(fp, "\n//----- SRAM ports -----\n"); /* check */ @@ -622,41 +622,89 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, case SPICE_SRAM_STANDALONE: break; case SPICE_SRAM_SCAN_CHAIN: + if (true == is_explicit_mapping) { + fprintf(fp, ".sram_out( "); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".sram_outb( "); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } if (0 < num_mode_sram) { fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".mode_out( "); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".mode_outb( "); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } } break; case SPICE_SRAM_MEMORY_BANK: + if (true == is_explicit_mapping) { + fprintf(fp, ".sram_out( "); + } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".sram_outb( "); + } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } if (0 < num_mode_sram) { fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".mode_out( "); + } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, - 0, VERILOG_PORT_CONKT); + 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", "); + if (true == is_explicit_mapping) { + fprintf(fp, ".mode_outb( "); + } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, - 1, VERILOG_PORT_CONKT); + 1, VERILOG_PORT_CONKT); + } + if (true == is_explicit_mapping) { + fprintf(fp, ")"); } break; default: diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index 4ff427dcf..eced18e87 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -1900,7 +1900,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr dump_verilog_routing_switch_box_unique_side_subckt_portmap(fp, rr_sb, side, seg_id, TRUE, - is_explicit_mapping); + false); /* Put down configuration port */ /* output of each configuration bit */ @@ -1926,7 +1926,7 @@ void dump_verilog_routing_switch_box_unique_side_module(t_sram_orgz_info* cur_sr dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, cur_num_sram, esti_sram_cnt - 1, - VERILOG_PORT_INPUT, is_explicit_mapping); + VERILOG_PORT_INPUT, false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 830cbf02c..3ae703e30 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -405,7 +405,7 @@ void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, iopad_verilog_model->grid_index_low[ix][iy], iopad_verilog_model->grid_index_high[ix][iy] - 1, - VERILOG_PORT_CONKT); + VERILOG_PORT_CONKT, is_explicit_mapping); /* Print configuration ports */ /* Reserved configuration ports */ @@ -1433,7 +1433,8 @@ char* compact_verilog_get_grid_phy_block_subckt_name(t_type_ptr grid_type_descri void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp, t_type_ptr grid_type_descriptor, int border_side, - int z) { + int z, + bool is_explicit_mapping) { int iport, ipin, dump_pin_cnt; int grid_pin_index, pin_height, side_pin_index; t_pb_graph_node* top_pb_graph_node = NULL; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h index 91b185e08..c57d7694f 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h @@ -52,6 +52,7 @@ char* compact_verilog_get_grid_phy_block_subckt_name(t_type_ptr grid_type_descri void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp, t_type_ptr grid_type_descriptor, int border_side, - int z) ; + int z, + bool is_explicit_mapping) ; diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index c3287e7a7..90a010607 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -2717,7 +2717,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, */ void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, char* general_port_prefix, int lsb, int msb, - enum e_dump_verilog_port_type dump_port_type) { + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping) { char* port_full_name = NULL; /* Check the file handler*/ @@ -3238,18 +3239,39 @@ void dump_verilog_mem_sram_submodule(FILE* fp, break; } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[0].prefix); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, -1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", \n"); // /* Output of Scan-chain DFF, should be connected to the output of its successor */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[1].prefix); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, 0, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", \n"); // + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + cur_sram_verilog_model->ports[2].prefix); + } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, 1, VERILOG_PORT_CONKT); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Invalid SRAM organization type!\n", diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h index 8930d8068..a66fd48f2 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.h @@ -100,7 +100,8 @@ void dump_verilog_mux_sram_one_local_outport(FILE* fp, t_spice_model* cur_mux_spice_model, int mux_size, int sram_lsb, int sram_msb, int port_type_index, - enum e_dump_verilog_port_type dump_port_type); + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping); void dump_verilog_sram_one_local_outport(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, @@ -202,7 +203,8 @@ void dump_verilog_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_model, void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, char* general_port_prefix, int lsb, int msb, - enum e_dump_verilog_port_type dump_port_type); + enum e_dump_verilog_port_type dump_port_type, + bool is_explicit_mapping); void dump_verilog_sram_config_bus_internal_wires(FILE* fp, t_sram_orgz_info* cur_sram_orgz_info, int lsb, int msb); From df0a3d23a33cfefa1857cd35708e1be727cce8e9 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Mon, 8 Jul 2019 10:23:14 -0600 Subject: [PATCH 39/84] Correction top module --- .../verilog/verilog_compact_netlist.c | 47 +++++++++++++++---- .../verilog/verilog_top_netlist_utils.c | 2 +- vpr7_x2p/vpr/regression_verilog.sh | 2 +- 3 files changed, 41 insertions(+), 10 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 4d8471798..7e1a0cd77 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -1075,16 +1075,28 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { switch (rr_chan.get_node(itrack)->direction) { case INC_DIRECTION: - fprintf(fp, "%s, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".in%d (",itrack); + } + fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, OUT_PORT)); - fprintf(fp, "\n"); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; case DEC_DIRECTION: - fprintf(fp, "%s, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".out%d (",itrack); + } + fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, IN_PORT)); - fprintf(fp, "\n"); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%u]!\n", @@ -1103,16 +1115,28 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { switch (rr_chan.get_node(itrack)->direction) { case INC_DIRECTION: - fprintf(fp, "%s, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".out%d (",itrack); + } + fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, IN_PORT)); - fprintf(fp, "\n"); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; case DEC_DIRECTION: - fprintf(fp, "%s, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".in%d (",itrack); + } + fprintf(fp, "%s", gen_verilog_routing_channel_one_pin_name(rr_chan.get_node(itrack), x, y, itrack, OUT_PORT)); - fprintf(fp, "\n"); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } + fprintf(fp, ",\n"); break; default: vpr_printf(TIO_MESSAGE_ERROR, "(File: %s [LINE%d]) Invalid direction of %s[%d][%d]_track[%u]!\n", @@ -1125,9 +1149,16 @@ void dump_compact_verilog_defined_one_channel(FILE* fp, /* output at middle point */ for (size_t itrack = 0; itrack < rr_chan.get_chan_width(); ++itrack) { + if (true == is_explicit_mapping) { + fprintf(fp, ".mid_out%d (", + itrack); + } fprintf(fp, "%s_%d__%d__midout_%lu_ ", convert_chan_type_to_string(rr_chan.get_type()), x, y, itrack); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } if (itrack < rr_chan.get_chan_width() - 1) { fprintf(fp, ","); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index 3ae703e30..f0edb1578 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -337,7 +337,7 @@ void dump_verilog_top_netlist_ports(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "\n"); dump_verilog_top_module_ports(cur_sram_orgz_info, fp, VERILOG_PORT_INPUT, - is_explicit_mapping); + false); fprintf(fp, ");\n"); diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index e19875026..8007363cf 100644 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd - # Run VPR -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis #--fpga_x2p_compact_routing_hierarchy +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path From b2717abc3eb7e2873f6055a0799f6724f6be6bf5 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 8 Jul 2019 10:30:26 -0600 Subject: [PATCH 40/84] Replace obsolete example folder and start tutorial --- examples/Examples_README.md | 77 - examples/example_1.act | 4 - examples/example_1.blif | 10 - examples/example_1.sh | 13 - examples/example_1.xml | 403 - examples/example_1_template.xml | 403 - examples/example_2.act | 4 - examples/example_2.blif | 10 - examples/example_2.sh | 13 - examples/example_2.xml | 397 - examples/example_2_template.xml | 397 - examples/figures/example_1.png | Bin 87428 -> 0 bytes examples/figures/example_2_3x3.png | Bin 152493 -> 0 bytes examples/figures/example_2_the_CLB.png | Bin 132991 -> 0 bytes .../example_1_cbx1_0_cbmux_testbench.sp | 671 - .../example_1_cbx1_1_cbmux_testbench.sp | 683 - .../example_1_cby0_1_cbmux_testbench.sp | 675 - .../example_1_cby1_1_cbmux_testbench.sp | 671 - .../cb_tb/example_1_cbx1_0_cb_testbench.sp | 268 - .../cb_tb/example_1_cbx1_1_cb_testbench.sp | 280 - .../cb_tb/example_1_cby0_1_cb_testbench.sp | 270 - .../cb_tb/example_1_cby1_1_cb_testbench.sp | 276 - .../spice_test_example_1/example_1.bitstream | 361 - .../example_1_grid1_1_grid_testbench.sp | 177 - .../example_1_grid1_1_hardlogic_testbench.sp | 130 - .../include/design_params.sp | 73 - .../include/meas_params.sp | 22 - .../include/stimulate_params.sp | 17 - .../lut_tb/example_1_grid1_1_lut_testbench.sp | 133 - .../example_1_grid1_1_pbmux_testbench.sp | 458 - .../spice_test_example_1/run_hspice_sim.sh | 64 - .../example_1_sb0_0_sbmux_testbench.sp | 1656 -- .../example_1_sb0_1_sbmux_testbench.sp | 1686 -- .../example_1_sb1_0_sbmux_testbench.sp | 1638 -- .../example_1_sb1_1_sbmux_testbench.sp | 1670 -- .../sb_tb/example_1_sb0_0_sb_testbench.sp | 399 - .../sb_tb/example_1_sb0_1_sb_testbench.sp | 409 - .../sb_tb/example_1_sb1_0_sb_testbench.sp | 381 - .../sb_tb/example_1_sb1_1_sb_testbench.sp | 393 - .../spice_test_example_1/subckt/cbx_1_0.sp | 185 - .../spice_test_example_1/subckt/cbx_1_1.sp | 185 - .../spice_test_example_1/subckt/cby_0_1.sp | 185 - .../spice_test_example_1/subckt/cby_1_1.sp | 186 - .../spice_test_example_1/subckt/chanx_1_0.sp | 45 - .../spice_test_example_1/subckt/chanx_1_1.sp | 45 - .../spice_test_example_1/subckt/chany_0_1.sp | 45 - .../spice_test_example_1/subckt/chany_1_1.sp | 45 - .../spice_test_example_1/subckt/grid_0_1.sp | 221 - .../spice_test_example_1/subckt/grid_1_0.sp | 221 - .../spice_test_example_1/subckt/grid_1_1.sp | 209 - .../spice_test_example_1/subckt/grid_1_2.sp | 223 - .../spice_test_example_1/subckt/grid_2_1.sp | 222 - .../subckt/grid_header.sp | 13 - .../subckt/inv_buf_trans_gate.sp | 76 - examples/spice_test_example_1/subckt/luts.sp | 24 - examples/spice_test_example_1/subckt/muxes.sp | 117 - .../spice_test_example_1/subckt/nmos_pmos.sp | 25 - .../subckt/routing_header.sp | 20 - .../spice_test_example_1/subckt/sb_0_0.sp | 220 - .../spice_test_example_1/subckt/sb_0_1.sp | 232 - .../spice_test_example_1/subckt/sb_1_0.sp | 220 - .../spice_test_example_1/subckt/sb_1_1.sp | 232 - examples/spice_test_example_1/subckt/wires.sp | 50 - .../top_tb/example_1_top.sp | 1300 -- .../example_2_cbx1_0_cbmux_testbench.sp | 2762 --- .../example_2_cbx1_1_cbmux_testbench.sp | 2704 --- .../example_2_cby0_1_cbmux_testbench.sp | 2702 --- .../example_2_cby1_1_cbmux_testbench.sp | 2754 --- .../cb_tb/example_2_cbx1_0_cb_testbench.sp | 1266 -- .../cb_tb/example_2_cbx1_1_cb_testbench.sp | 1182 -- .../cb_tb/example_2_cby0_1_cb_testbench.sp | 1182 -- .../cb_tb/example_2_cby1_1_cb_testbench.sp | 1200 -- .../spice_test_example_2/example_2.bitstream | 2658 --- .../example_2_grid1_1_grid_testbench.sp | 556 - .../example_2_grid1_1_hardlogic_testbench.sp | 346 - .../include/design_params.sp | 73 - .../include/meas_params.sp | 22 - .../include/stimulate_params.sp | 17 - .../lut_tb/example_2_grid1_1_lut_testbench.sp | 362 - .../example_2_grid1_1_pbmux_testbench.sp | 16912 ---------------- .../spice_test_example_2/run_hspice_sim.sh | 64 - .../example_2_sb0_0_sbmux_testbench.sp | 5410 ----- .../example_2_sb0_1_sbmux_testbench.sp | 5435 ----- .../example_2_sb1_0_sbmux_testbench.sp | 5409 ----- .../example_2_sb1_1_sbmux_testbench.sp | 5436 ----- .../sb_tb/example_2_sb0_0_sb_testbench.sp | 1161 -- .../sb_tb/example_2_sb0_1_sb_testbench.sp | 1151 -- .../sb_tb/example_2_sb1_0_sb_testbench.sp | 1109 - .../sb_tb/example_2_sb1_1_sb_testbench.sp | 1101 - .../spice_test_example_2/subckt/cbx_1_0.sp | 616 - .../spice_test_example_2/subckt/cbx_1_1.sp | 615 - .../spice_test_example_2/subckt/cby_0_1.sp | 615 - .../spice_test_example_2/subckt/cby_1_1.sp | 615 - .../spice_test_example_2/subckt/chanx_1_0.sp | 115 - .../spice_test_example_2/subckt/chanx_1_1.sp | 115 - .../spice_test_example_2/subckt/chany_0_1.sp | 115 - .../spice_test_example_2/subckt/chany_1_1.sp | 115 - .../spice_test_example_2/subckt/grid_0_1.sp | 222 - .../spice_test_example_2/subckt/grid_1_0.sp | 222 - .../spice_test_example_2/subckt/grid_1_1.sp | 5565 ----- .../spice_test_example_2/subckt/grid_1_2.sp | 222 - .../spice_test_example_2/subckt/grid_2_1.sp | 221 - .../subckt/grid_header.sp | 13 - .../subckt/inv_buf_trans_gate.sp | 76 - examples/spice_test_example_2/subckt/luts.sp | 30 - examples/spice_test_example_2/subckt/muxes.sp | 284 - .../spice_test_example_2/subckt/nmos_pmos.sp | 25 - .../subckt/routing_header.sp | 20 - .../spice_test_example_2/subckt/sb_0_0.sp | 628 - .../spice_test_example_2/subckt/sb_0_1.sp | 658 - .../spice_test_example_2/subckt/sb_1_0.sp | 658 - .../spice_test_example_2/subckt/sb_1_1.sp | 688 - examples/spice_test_example_2/subckt/wires.sp | 50 - .../top_tb/example_2_top.sp | 2663 --- .../verilog_test_example_1/example_1_top.v | 1373 -- examples/verilog_test_example_1/lb/grid_0_1.v | 694 - examples/verilog_test_example_1/lb/grid_1_0.v | 694 - examples/verilog_test_example_1/lb/grid_1_1.v | 452 - examples/verilog_test_example_1/lb/grid_1_2.v | 694 - examples/verilog_test_example_1/lb/grid_2_1.v | 694 - .../verilog_test_example_1/lb/logic_blocks.v | 16 - .../verilog_test_example_1/routing/cbx_1_0.v | 302 - .../verilog_test_example_1/routing/cbx_1_1.v | 302 - .../verilog_test_example_1/routing/cby_0_1.v | 302 - .../verilog_test_example_1/routing/cby_1_1.v | 304 - .../routing/chanx_1_0.v | 175 - .../routing/chanx_1_1.v | 175 - .../routing/chany_0_1.v | 175 - .../routing/chany_1_1.v | 175 - .../verilog_test_example_1/routing/routing.v | 23 - .../verilog_test_example_1/routing/sb_0_0.v | 627 - .../verilog_test_example_1/routing/sb_0_1.v | 634 - .../verilog_test_example_1/routing/sb_1_0.v | 627 - .../verilog_test_example_1/routing/sb_1_1.v | 634 - .../sub_module/decoders.v | 40 - .../sub_module/inv_buf_passgate.v | 45 - .../verilog_test_example_1/sub_module/luts.v | 23 - .../verilog_test_example_1/sub_module/muxes.v | 211 - .../verilog_test_example_1/sub_module/wires.v | 43 - .../verilog_test_example_2/example_2_top.v | 4970 ----- examples/verilog_test_example_2/lb/grid_0_1.v | 694 - examples/verilog_test_example_2/lb/grid_1_0.v | 694 - examples/verilog_test_example_2/lb/grid_1_1.v | 11197 ---------- examples/verilog_test_example_2/lb/grid_1_2.v | 694 - examples/verilog_test_example_2/lb/grid_2_1.v | 694 - .../verilog_test_example_2/lb/logic_blocks.v | 16 - .../verilog_test_example_2/routing/cbx_1_0.v | 948 - .../verilog_test_example_2/routing/cbx_1_1.v | 946 - .../verilog_test_example_2/routing/cby_0_1.v | 946 - .../verilog_test_example_2/routing/cby_1_1.v | 946 - .../routing/chanx_1_0.v | 525 - .../routing/chanx_1_1.v | 525 - .../routing/chany_0_1.v | 525 - .../routing/chany_1_1.v | 525 - .../verilog_test_example_2/routing/routing.v | 23 - .../verilog_test_example_2/routing/sb_0_0.v | 1955 -- .../verilog_test_example_2/routing/sb_0_1.v | 1971 -- .../verilog_test_example_2/routing/sb_1_0.v | 1971 -- .../verilog_test_example_2/routing/sb_1_1.v | 1987 -- .../sub_module/decoders.v | 40 - .../sub_module/inv_buf_passgate.v | 45 - .../verilog_test_example_2/sub_module/luts.v | 23 - .../verilog_test_example_2/sub_module/muxes.v | 387 - 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The .blif contains only an inverter. -The .xml is currently on which means that the size depends on the .blif. Since the .blif is -almost empty, only 1 CLB will be generated. - -Example_1_FPGA - -Schematic of the FPGA generated during example_1. -The CLB integrates a 4-inputs LUT, a FF and a MUX. - ---- - -**Things to understand in this example** - -Everything won't be explained in detail but few important structures (some common with the VPR project) are to be explained in order to build good architectures. - -```xml - - - ... add models such as the io pads. - - - ... all tech and spice parameters are defined here. - - ... define the Basic Elements of the architecture and the modules that cannot - be generated (i.e. the Flip-Flop) but need to be called. - - - - ... complex blocks - - ... here we define the hierarchy of the primitive blocks and interconnect them - together - - ... defines the primitive block - - - ... - - - - -``` - ---- -## Example_2 - -Example_2's goal is to introduce the slices, the interconnections which can be generated from it and the manual mode of the layout. -In this case, we generate a 3x3 FPGA with 4 slices. The LUTs are 6-inputs ones similarly to the ones used in the industry. -There is a feedback-loop from the output of the slices to the input MUXs - -Example_2_CLB - -Schematic showing the CLB generated in this example. - ---- - -**Things to understand in this example** - -```xml - - - - - - - -``` - -Example_2_FPGA - - - - diff --git a/examples/example_1.act b/examples/example_1.act deleted file mode 100644 index 19fd43010..000000000 --- a/examples/example_1.act +++ /dev/null @@ -1,4 +0,0 @@ -I0 0.478200 0.190600 -clk 0.493600 0.194000 -Q0 0.521800 0.190600 -n7 0.521800 0.099455 diff --git a/examples/example_1.blif b/examples/example_1.blif deleted file mode 100644 index eaf9b1fdb..000000000 --- a/examples/example_1.blif +++ /dev/null @@ -1,10 +0,0 @@ -# Benchmark "inverter.bench" written by ABC on Wed Nov 14 13:52:06 2018 -.model inverter.bench -.inputs I0 clk -.outputs Q0 - -.latch n7 Q0 re clk 0 - -.names I0 n7 -0 1 -.end diff --git a/examples/example_1.sh b/examples/example_1.sh deleted file mode 100755 index 924e3057f..000000000 --- a/examples/example_1.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh -# Example of how to run vpr - -# The paths need to be absolute hence we modify a keyword with PWD - -sed "s:OPENFPGAPATH:${PWD}/..:g" example_1_template.xml > example_1.xml - -# Pack, place, and route a heterogeneous FPGA -# Packing uses the AAPack algorithm -../vpr7_x2p/vpr/vpr ./example_1.xml ./example_1.blif --full_stats --nodisp --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_example_1 --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_example_1 - - - diff --git a/examples/example_1.xml b/examples/example_1.xml deleted file mode 100644 index 17b2b5884..000000000 --- a/examples/example_1.xml +++ /dev/null @@ -1,403 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/examples/example_1_template.xml b/examples/example_1_template.xml deleted file mode 100644 index c6b3a395e..000000000 --- a/examples/example_1_template.xml +++ /dev/null @@ -1,403 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/examples/example_2.act b/examples/example_2.act deleted file mode 100644 index e59326b48..000000000 --- a/examples/example_2.act +++ /dev/null @@ -1,4 +0,0 @@ -I0 0.501800 0.202600 -clk 0.488800 0.199600 -Q0 0.498200 0.202600 -n7 0.498200 0.100935 diff --git a/examples/example_2.blif b/examples/example_2.blif deleted file mode 100644 index de9f0eeb8..000000000 --- a/examples/example_2.blif +++ /dev/null @@ -1,10 +0,0 @@ -# Benchmark "example_2.bench" written by ABC on Wed Nov 14 11:42:18 2018 -.model example_2.bench -.inputs I0 clk -.outputs Q0 - -.latch n7 Q0 re clk 0 - -.names I0 n7 -0 1 -.end diff --git a/examples/example_2.sh b/examples/example_2.sh deleted file mode 100755 index f884a5081..000000000 --- a/examples/example_2.sh +++ /dev/null @@ -1,13 +0,0 @@ -#!/bin/sh -# Example of how to run vpr - - -# The paths need to be absolute hence we modify a keyword with PWD - -sed "s:OPENFPGAPATH:${PWD}/..:g" example_2_template.xml > example_2.xml - -# Pack, place, and route a heterogeneous FPGA -# Packing uses the AAPack algorithm -../vpr7_x2p/vpr/vpr ./example_2.xml ./example_2.blif --full_stats --nodisp --route_chan_width 100 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ./spice_test_example_2 --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ./verilog_test_example_2 - - diff --git a/examples/example_2.xml b/examples/example_2.xml deleted file mode 100644 index 982787f0f..000000000 --- a/examples/example_2.xml +++ /dev/null @@ -1,397 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - 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07de6be07..000000000 --- a/examples/example_2_template.xml +++ /dev/null @@ -1,397 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - 1 1 1 - 1 1 - - - - 1 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - 127e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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z3|l8^Y_8m@cJ5vvc$jkkoGfstvyR_dR_dNERl>({N4k-rq#szS?|6oW!_Jstt|)7x z80QJOTyGt&ShjN!2DB!n3T&jSITY< zD}7kdZiKyp2Ob?>jC%qu?3$x9qSa*q=MEXw@Z!c?nAI*$;l7--yKKIPUm|x(52_lC zmlp$$p$@THN(qqw++^K3D}4khzW&Y=^*D@obwZa&X<3c?L-#eC6b}a`Pa`?2Ac<+MmH;C)FjU{^&2|recS}!GpKlH zJaU2HKi=x%@X`JJP65RC);ChymXeF#ld2EtyHV3cGDHRnaX8e9elW9h{&cZx>N;*+s#}U|`xyu;ydu2PX z+o#J$!EO%qT(^m?;YgG4)LDB0HTEa4wHvK2quzRj)^|I#x%QFFD-uDd{xz9k<_~jp zKbNCucM7G=-0u&GD zXQ~DqX_|V2;cKhP`5(0NB4fgtxnGx>D=Kc5(kOf;r%`G?&QtuW&QR$>062#W!uc+YVly*`<-cY;qRHScU5-!YZ_ z9};((X~}@zM^ww3+69QWCvEpndDwLdfAsMUJ2)!jpC0Z{&OdYb*R}HBZKcgCV{Z=} zIPzRUMoJ6n_kVY9|LNgBe)XToap2%TvGKnp`qw*lF<4h{hWv@a{`Nm#B|qCM4s8?n zp8tD^F!b>hNSW%)_4d-=G1nhhlm~z;w-Qe1pid^f&in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_2level_tapbuf_size4[0] mux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->outb sram[2]->out sram[3]->out sram[3]->outb gvdd_mux_2level_tapbuf_size4[0] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****1010***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -***** Signal mux_2level_tapbuf_size4[0]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[0] gvdd_mux_2level_tapbuf_size4[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[69] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[69] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[69] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[69] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[69] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[69] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[69] param='mux_2level_tapbuf_size4[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[0]_energy_per_cycle param='mux_2level_tapbuf_size4[0]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[69] param='mux_2level_tapbuf_size4[0]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[69] param='dynamic_power_cb_mux[1][0]_rrnode[69]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[69] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_rise_cb_mux[1][0]_rrnode[69]' to='start_rise_cb_mux[1][0]_rrnode[69]+switch_rise_cb_mux[1][0]_rrnode[69]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[69] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_fall_cb_mux[1][0]_rrnode[69]' to='start_fall_cb_mux[1][0]_rrnode[69]+switch_fall_cb_mux[1][0]_rrnode[69]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_cb_mux[1][0]_rrnode[69]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][0]_rrnode[69]' -******* Normal TYPE loads ******* -Xload_inv[0]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[3] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to0] -+ param='leakage_cb_mux[1][0]_rrnode[69]' -.meas tran sum_energy_per_cycle_cb_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][0]_rrnode[69]' -Xmux_2level_tapbuf_size4[1] mux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->out sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size4[1] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****1010***** -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_2level_tapbuf_size4[1]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[1]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[1]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[1]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[1] gvdd_mux_2level_tapbuf_size4[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[48] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[48] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[48] param='mux_2level_tapbuf_size4[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[1]_energy_per_cycle param='mux_2level_tapbuf_size4[1]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[48] param='mux_2level_tapbuf_size4[1]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[48] param='dynamic_power_cb_mux[1][0]_rrnode[48]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[48] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_rise_cb_mux[1][0]_rrnode[48]' to='start_rise_cb_mux[1][0]_rrnode[48]+switch_rise_cb_mux[1][0]_rrnode[48]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[48] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_fall_cb_mux[1][0]_rrnode[48]' to='start_fall_cb_mux[1][0]_rrnode[48]+switch_fall_cb_mux[1][0]_rrnode[48]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[1][0]_rrnode[48]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[1][0]_rrnode[48]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to1] -+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[1][0]_rrnode[48]' -.meas tran sum_energy_per_cycle_cb_mux[0to1] -+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[1][0]_rrnode[48]' -Xmux_2level_tapbuf_size4[2] mux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->outb sram[10]->out sram[11]->out sram[11]->outb gvdd_mux_2level_tapbuf_size4[2] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****1010***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_2level_tapbuf_size4[2]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[2]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[2]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[2]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[2] gvdd_mux_2level_tapbuf_size4[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[50] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[50] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[50] param='mux_2level_tapbuf_size4[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[2]_energy_per_cycle param='mux_2level_tapbuf_size4[2]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[50] param='mux_2level_tapbuf_size4[2]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[50] param='dynamic_power_cb_mux[1][0]_rrnode[50]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[50] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_rise_cb_mux[1][0]_rrnode[50]' to='start_rise_cb_mux[1][0]_rrnode[50]+switch_rise_cb_mux[1][0]_rrnode[50]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[50] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_fall_cb_mux[1][0]_rrnode[50]' to='start_fall_cb_mux[1][0]_rrnode[50]+switch_fall_cb_mux[1][0]_rrnode[50]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[1][0]_rrnode[50]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[1][0]_rrnode[50]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to2] -+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[1][0]_rrnode[50]' -.meas tran sum_energy_per_cycle_cb_mux[0to2] -+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[1][0]_rrnode[50]' -Xmux_2level_tapbuf_size4[3] mux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->outb sram[14]->out sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size4[3] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****1010***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_2level_tapbuf_size4[3]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[3] gvdd_mux_2level_tapbuf_size4[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[52] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[52] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[52] param='mux_2level_tapbuf_size4[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[3]_energy_per_cycle param='mux_2level_tapbuf_size4[3]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[52] param='mux_2level_tapbuf_size4[3]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[52] param='dynamic_power_cb_mux[1][0]_rrnode[52]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[52] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_rise_cb_mux[1][0]_rrnode[52]' to='start_rise_cb_mux[1][0]_rrnode[52]+switch_rise_cb_mux[1][0]_rrnode[52]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[52] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_fall_cb_mux[1][0]_rrnode[52]' to='start_fall_cb_mux[1][0]_rrnode[52]+switch_fall_cb_mux[1][0]_rrnode[52]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[1][0]_rrnode[52]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[1][0]_rrnode[52]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to3] -+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[1][0]_rrnode[52]' -.meas tran sum_energy_per_cycle_cb_mux[0to3] -+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[1][0]_rrnode[52]' -Xmux_2level_tapbuf_size4[4] mux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb gvdd_mux_2level_tapbuf_size4[4] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****1010***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_2level_tapbuf_size4[4]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[4] gvdd_mux_2level_tapbuf_size4[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[54] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[54] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[54] param='mux_2level_tapbuf_size4[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[4]_energy_per_cycle param='mux_2level_tapbuf_size4[4]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[54] param='mux_2level_tapbuf_size4[4]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[54] param='dynamic_power_cb_mux[1][0]_rrnode[54]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[54] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_rise_cb_mux[1][0]_rrnode[54]' to='start_rise_cb_mux[1][0]_rrnode[54]+switch_rise_cb_mux[1][0]_rrnode[54]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[54] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_fall_cb_mux[1][0]_rrnode[54]' to='start_fall_cb_mux[1][0]_rrnode[54]+switch_fall_cb_mux[1][0]_rrnode[54]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[1][0]_rrnode[54]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[1][0]_rrnode[54]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to4] -+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[1][0]_rrnode[54]' -.meas tran sum_energy_per_cycle_cb_mux[0to4] -+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[1][0]_rrnode[54]' -Xmux_2level_tapbuf_size4[5] mux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->out sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->outb sram[22]->out sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size4[5] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[5], level=2, select_path_id=0. ***** -*****1010***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_2level_tapbuf_size4[5]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[5] gvdd_mux_2level_tapbuf_size4[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[56] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[56] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[56] param='mux_2level_tapbuf_size4[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[5]_energy_per_cycle param='mux_2level_tapbuf_size4[5]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[56] param='mux_2level_tapbuf_size4[5]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[56] param='dynamic_power_cb_mux[1][0]_rrnode[56]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[56] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_rise_cb_mux[1][0]_rrnode[56]' to='start_rise_cb_mux[1][0]_rrnode[56]+switch_rise_cb_mux[1][0]_rrnode[56]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[56] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_fall_cb_mux[1][0]_rrnode[56]' to='start_fall_cb_mux[1][0]_rrnode[56]+switch_fall_cb_mux[1][0]_rrnode[56]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[1][0]_rrnode[56]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[1][0]_rrnode[56]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to5] -+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[1][0]_rrnode[56]' -.meas tran sum_energy_per_cycle_cb_mux[0to5] -+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[1][0]_rrnode[56]' -Xmux_2level_tapbuf_size4[6] mux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->outb sram[26]->out sram[27]->out sram[27]->outb gvdd_mux_2level_tapbuf_size4[6] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****1010***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_2level_tapbuf_size4[6]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[6] gvdd_mux_2level_tapbuf_size4[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[58] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[58] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[58] param='mux_2level_tapbuf_size4[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[6]_energy_per_cycle param='mux_2level_tapbuf_size4[6]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[58] param='mux_2level_tapbuf_size4[6]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[58] param='dynamic_power_cb_mux[1][0]_rrnode[58]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[58] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_rise_cb_mux[1][0]_rrnode[58]' to='start_rise_cb_mux[1][0]_rrnode[58]+switch_rise_cb_mux[1][0]_rrnode[58]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[58] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_fall_cb_mux[1][0]_rrnode[58]' to='start_fall_cb_mux[1][0]_rrnode[58]+switch_fall_cb_mux[1][0]_rrnode[58]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[1][0]_rrnode[58]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[1][0]_rrnode[58]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to6] -+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[1][0]_rrnode[58]' -.meas tran sum_energy_per_cycle_cb_mux[0to6] -+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[1][0]_rrnode[58]' -Xmux_2level_tapbuf_size4[7] mux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->out sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->outb sram[30]->out sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size4[7] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****1010***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_2level_tapbuf_size4[7]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[7] gvdd_mux_2level_tapbuf_size4[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[60] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[60] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[60] param='mux_2level_tapbuf_size4[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[7]_energy_per_cycle param='mux_2level_tapbuf_size4[7]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[60] param='mux_2level_tapbuf_size4[7]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[60] param='dynamic_power_cb_mux[1][0]_rrnode[60]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[60] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_rise_cb_mux[1][0]_rrnode[60]' to='start_rise_cb_mux[1][0]_rrnode[60]+switch_rise_cb_mux[1][0]_rrnode[60]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[60] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_fall_cb_mux[1][0]_rrnode[60]' to='start_fall_cb_mux[1][0]_rrnode[60]+switch_fall_cb_mux[1][0]_rrnode[60]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[1][0]_rrnode[60]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[1][0]_rrnode[60]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to7] -+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[1][0]_rrnode[60]' -.meas tran sum_energy_per_cycle_cb_mux[0to7] -+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[1][0]_rrnode[60]' -Xmux_2level_tapbuf_size4[8] mux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->outb sram[34]->out sram[35]->out sram[35]->outb gvdd_mux_2level_tapbuf_size4[8] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****1010***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -***** Signal mux_2level_tapbuf_size4[8]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[8] gvdd_mux_2level_tapbuf_size4[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[62] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[62] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[62] param='mux_2level_tapbuf_size4[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[8]_energy_per_cycle param='mux_2level_tapbuf_size4[8]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[62] param='mux_2level_tapbuf_size4[8]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[62] param='dynamic_power_cb_mux[1][0]_rrnode[62]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[62] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_rise_cb_mux[1][0]_rrnode[62]' to='start_rise_cb_mux[1][0]_rrnode[62]+switch_rise_cb_mux[1][0]_rrnode[62]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[62] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_fall_cb_mux[1][0]_rrnode[62]' to='start_fall_cb_mux[1][0]_rrnode[62]+switch_fall_cb_mux[1][0]_rrnode[62]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[1][0]_rrnode[62]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[1][0]_rrnode[62]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to8] -+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[1][0]_rrnode[62]' -.meas tran sum_energy_per_cycle_cb_mux[0to8] -+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[1][0]_rrnode[62]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 2 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '2*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='2*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to8]' -.meas tran total_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to8]' -.meas tran total_leakage_power_cb_mux -+ param='sum_leakage_power_cb_mux[0to8]' -.meas tran total_energy_per_cycle_cb_mux -+ param='sum_energy_per_cycle_cb_mux[0to8]' -.end diff --git a/examples/spice_test_example_1/cb_mux_tb/example_1_cbx1_1_cbmux_testbench.sp b/examples/spice_test_example_1/cb_mux_tb/example_1_cbx1_1_cbmux_testbench.sp deleted file mode 100644 index 115591ec0..000000000 --- a/examples/spice_test_example_1/cb_mux_tb/example_1_cbx1_1_cbmux_testbench.sp +++ /dev/null @@ -1,683 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_2level_tapbuf_size4[0] mux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->outb sram[2]->out sram[3]->out sram[3]->outb gvdd_mux_2level_tapbuf_size4[0] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****1010***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -***** Signal mux_2level_tapbuf_size4[0]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[0] gvdd_mux_2level_tapbuf_size4[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[89] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[89] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[89] param='mux_2level_tapbuf_size4[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[0]_energy_per_cycle param='mux_2level_tapbuf_size4[0]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[89] param='mux_2level_tapbuf_size4[0]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[89] param='dynamic_power_cb_mux[1][1]_rrnode[89]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[89] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_rise_cb_mux[1][1]_rrnode[89]' to='start_rise_cb_mux[1][1]_rrnode[89]+switch_rise_cb_mux[1][1]_rrnode[89]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[89] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_fall_cb_mux[1][1]_rrnode[89]' to='start_fall_cb_mux[1][1]_rrnode[89]+switch_fall_cb_mux[1][1]_rrnode[89]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_cb_mux[1][1]_rrnode[89]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][1]_rrnode[89]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to0] -+ param='leakage_cb_mux[1][1]_rrnode[89]' -.meas tran sum_energy_per_cycle_cb_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][1]_rrnode[89]' -Xmux_2level_tapbuf_size4[1] mux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->out sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size4[1] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****1010***** -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_2level_tapbuf_size4[1]->in[0] density = 0.1906, probability=0.5218.***** -Vmux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_2level_tapbuf_size4[1]->in[1] density = 0.1906, probability=0.4782.***** -Vmux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_2level_tapbuf_size4[1]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[1]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[1] gvdd_mux_2level_tapbuf_size4[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[91] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[91] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[91] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[91] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[91] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[91] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[91] param='mux_2level_tapbuf_size4[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='clock_period' to='7*clock_period' -.meas tran mux_2level_tapbuf_size4[1]_energy_per_cycle param='mux_2level_tapbuf_size4[1]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[91] param='mux_2level_tapbuf_size4[1]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[91] param='dynamic_power_cb_mux[1][1]_rrnode[91]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[91] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_rise_cb_mux[1][1]_rrnode[91]' to='start_rise_cb_mux[1][1]_rrnode[91]+switch_rise_cb_mux[1][1]_rrnode[91]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[91] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_fall_cb_mux[1][1]_rrnode[91]' to='start_fall_cb_mux[1][1]_rrnode[91]+switch_fall_cb_mux[1][1]_rrnode[91]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[1][1]_rrnode[91]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[91]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to1] -+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[1][1]_rrnode[91]' -.meas tran sum_energy_per_cycle_cb_mux[0to1] -+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[91]' -Xmux_2level_tapbuf_size4[2] mux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->outb sram[10]->out sram[11]->out sram[11]->outb gvdd_mux_2level_tapbuf_size4[2] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****1010***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_2level_tapbuf_size4[2]->in[0] density = 0.1906, probability=0.5218.***** -Vmux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_2level_tapbuf_size4[2]->in[1] density = 0.1906, probability=0.5218.***** -Vmux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_2level_tapbuf_size4[2]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[2]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[2] gvdd_mux_2level_tapbuf_size4[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[93] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[93] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[93] param='mux_2level_tapbuf_size4[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='clock_period' to='7*clock_period' -.meas tran mux_2level_tapbuf_size4[2]_energy_per_cycle param='mux_2level_tapbuf_size4[2]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[93] param='mux_2level_tapbuf_size4[2]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[93] param='dynamic_power_cb_mux[1][1]_rrnode[93]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[93] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_rise_cb_mux[1][1]_rrnode[93]' to='start_rise_cb_mux[1][1]_rrnode[93]+switch_rise_cb_mux[1][1]_rrnode[93]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[93] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_fall_cb_mux[1][1]_rrnode[93]' to='start_fall_cb_mux[1][1]_rrnode[93]+switch_fall_cb_mux[1][1]_rrnode[93]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[1][1]_rrnode[93]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[93]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to2] -+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[1][1]_rrnode[93]' -.meas tran sum_energy_per_cycle_cb_mux[0to2] -+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[93]' -Xmux_2level_tapbuf_size4[3] mux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->outb sram[14]->out sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size4[3] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****1010***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_2level_tapbuf_size4[3]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[3] gvdd_mux_2level_tapbuf_size4[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[95] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[95] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[95] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[95] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[95] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[95] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[95] param='mux_2level_tapbuf_size4[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[3]_energy_per_cycle param='mux_2level_tapbuf_size4[3]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[95] param='mux_2level_tapbuf_size4[3]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[95] param='dynamic_power_cb_mux[1][1]_rrnode[95]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[95] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_rise_cb_mux[1][1]_rrnode[95]' to='start_rise_cb_mux[1][1]_rrnode[95]+switch_rise_cb_mux[1][1]_rrnode[95]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[95] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_fall_cb_mux[1][1]_rrnode[95]' to='start_fall_cb_mux[1][1]_rrnode[95]+switch_fall_cb_mux[1][1]_rrnode[95]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[1][1]_rrnode[95]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[95]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to3] -+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[1][1]_rrnode[95]' -.meas tran sum_energy_per_cycle_cb_mux[0to3] -+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[95]' -Xmux_2level_tapbuf_size4[4] mux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb gvdd_mux_2level_tapbuf_size4[4] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****1010***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_2level_tapbuf_size4[4]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[4] gvdd_mux_2level_tapbuf_size4[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[97] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[97] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[97] param='mux_2level_tapbuf_size4[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[4]_energy_per_cycle param='mux_2level_tapbuf_size4[4]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[97] param='mux_2level_tapbuf_size4[4]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[97] param='dynamic_power_cb_mux[1][1]_rrnode[97]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[97] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_rise_cb_mux[1][1]_rrnode[97]' to='start_rise_cb_mux[1][1]_rrnode[97]+switch_rise_cb_mux[1][1]_rrnode[97]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[97] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_fall_cb_mux[1][1]_rrnode[97]' to='start_fall_cb_mux[1][1]_rrnode[97]+switch_fall_cb_mux[1][1]_rrnode[97]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[1][1]_rrnode[97]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[97]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to4] -+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[1][1]_rrnode[97]' -.meas tran sum_energy_per_cycle_cb_mux[0to4] -+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[97]' -Xmux_2level_tapbuf_size4[5] mux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->out sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->outb sram[22]->out sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size4[5] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[5], level=2, select_path_id=0. ***** -*****1010***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_2level_tapbuf_size4[5]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[5] gvdd_mux_2level_tapbuf_size4[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[99] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[99] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[99] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[99] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[99] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[99] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[99] param='mux_2level_tapbuf_size4[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[5]_energy_per_cycle param='mux_2level_tapbuf_size4[5]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[99] param='mux_2level_tapbuf_size4[5]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[99] param='dynamic_power_cb_mux[1][1]_rrnode[99]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[99] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_rise_cb_mux[1][1]_rrnode[99]' to='start_rise_cb_mux[1][1]_rrnode[99]+switch_rise_cb_mux[1][1]_rrnode[99]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[99] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_fall_cb_mux[1][1]_rrnode[99]' to='start_fall_cb_mux[1][1]_rrnode[99]+switch_fall_cb_mux[1][1]_rrnode[99]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[1][1]_rrnode[99]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[99]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to5] -+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[1][1]_rrnode[99]' -.meas tran sum_energy_per_cycle_cb_mux[0to5] -+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[99]' -Xmux_2level_tapbuf_size4[6] mux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->outb sram[26]->out sram[27]->out sram[27]->outb gvdd_mux_2level_tapbuf_size4[6] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****1010***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_2level_tapbuf_size4[6]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[6] gvdd_mux_2level_tapbuf_size4[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[101] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[101] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[101] param='mux_2level_tapbuf_size4[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[6]_energy_per_cycle param='mux_2level_tapbuf_size4[6]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[101] param='mux_2level_tapbuf_size4[6]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[101] param='dynamic_power_cb_mux[1][1]_rrnode[101]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[101] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_rise_cb_mux[1][1]_rrnode[101]' to='start_rise_cb_mux[1][1]_rrnode[101]+switch_rise_cb_mux[1][1]_rrnode[101]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[101] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_fall_cb_mux[1][1]_rrnode[101]' to='start_fall_cb_mux[1][1]_rrnode[101]+switch_fall_cb_mux[1][1]_rrnode[101]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[1][1]_rrnode[101]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[101]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to6] -+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[1][1]_rrnode[101]' -.meas tran sum_energy_per_cycle_cb_mux[0to6] -+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[101]' -Xmux_2level_tapbuf_size4[7] mux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->out sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->outb sram[30]->out sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size4[7] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****1010***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_2level_tapbuf_size4[7]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[2] density = 0.1906, probability=0.4782.***** -Vmux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_2level_tapbuf_size4[7]->in[3] density = 0.1906, probability=0.4782.***** -Vmux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_2level_tapbuf_size4[7] gvdd_mux_2level_tapbuf_size4[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[103] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[103] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[103] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[103] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[103] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[103] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[103] param='mux_2level_tapbuf_size4[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='clock_period' to='7*clock_period' -.meas tran mux_2level_tapbuf_size4[7]_energy_per_cycle param='mux_2level_tapbuf_size4[7]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[103] param='mux_2level_tapbuf_size4[7]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[103] param='dynamic_power_cb_mux[1][1]_rrnode[103]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[103] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_rise_cb_mux[1][1]_rrnode[103]' to='start_rise_cb_mux[1][1]_rrnode[103]+switch_rise_cb_mux[1][1]_rrnode[103]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[103] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_fall_cb_mux[1][1]_rrnode[103]' to='start_fall_cb_mux[1][1]_rrnode[103]+switch_fall_cb_mux[1][1]_rrnode[103]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[1][1]_rrnode[103]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[103]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to7] -+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[1][1]_rrnode[103]' -.meas tran sum_energy_per_cycle_cb_mux[0to7] -+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[103]' -Xmux_2level_tapbuf_size4[8] mux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->outb sram[34]->out sram[35]->out sram[35]->outb gvdd_mux_2level_tapbuf_size4[8] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****1010***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -***** Signal mux_2level_tapbuf_size4[8]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[8] gvdd_mux_2level_tapbuf_size4[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[67] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[67] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[67] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[67] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[67] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[67] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[67] param='mux_2level_tapbuf_size4[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[8]_energy_per_cycle param='mux_2level_tapbuf_size4[8]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[67] param='mux_2level_tapbuf_size4[8]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[67] param='dynamic_power_cb_mux[1][1]_rrnode[67]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[67] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_rise_cb_mux[1][1]_rrnode[67]' to='start_rise_cb_mux[1][1]_rrnode[67]+switch_rise_cb_mux[1][1]_rrnode[67]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[67] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_fall_cb_mux[1][1]_rrnode[67]' to='start_fall_cb_mux[1][1]_rrnode[67]+switch_fall_cb_mux[1][1]_rrnode[67]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[1][1]_rrnode[67]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[67]' -******* Normal TYPE loads ******* -Xload_inv[0]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[3] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to8] -+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[1][1]_rrnode[67]' -.meas tran sum_energy_per_cycle_cb_mux[0to8] -+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[67]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='7*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to8]' -.meas tran total_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to8]' -.meas tran total_leakage_power_cb_mux -+ param='sum_leakage_power_cb_mux[0to8]' -.meas tran total_energy_per_cycle_cb_mux -+ param='sum_energy_per_cycle_cb_mux[0to8]' -.end diff --git a/examples/spice_test_example_1/cb_mux_tb/example_1_cby0_1_cbmux_testbench.sp b/examples/spice_test_example_1/cb_mux_tb/example_1_cby0_1_cbmux_testbench.sp deleted file mode 100644 index 71247f12e..000000000 --- a/examples/spice_test_example_1/cb_mux_tb/example_1_cby0_1_cbmux_testbench.sp +++ /dev/null @@ -1,675 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_2level_tapbuf_size4[0] mux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->out sram[0]->out sram[0]->outb sram[1]->outb sram[1]->out sram[2]->out sram[2]->outb sram[3]->outb sram[3]->out gvdd_mux_2level_tapbuf_size4[0] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[0], level=2, select_path_id=3. ***** -*****0101***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -***** Signal mux_2level_tapbuf_size4[0]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[3] density = 0.1906, probability=0.4782.***** -Vmux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_2level_tapbuf_size4[0] gvdd_mux_2level_tapbuf_size4[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[70] trig v(mux_2level_tapbuf_size4[0]->in[3]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[70] trig v(mux_2level_tapbuf_size4[0]->in[3]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[70] when v(mux_2level_tapbuf_size4[0]->in[3])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[70] trig v(mux_2level_tapbuf_size4[0]->in[3]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[70] when v(mux_2level_tapbuf_size4[0]->in[3])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[70] trig v(mux_2level_tapbuf_size4[0]->in[3]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[70] param='mux_2level_tapbuf_size4[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='clock_period' to='7*clock_period' -.meas tran mux_2level_tapbuf_size4[0]_energy_per_cycle param='mux_2level_tapbuf_size4[0]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[70] param='mux_2level_tapbuf_size4[0]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[70] param='dynamic_power_cb_mux[0][1]_rrnode[70]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[70] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_rise_cb_mux[0][1]_rrnode[70]' to='start_rise_cb_mux[0][1]_rrnode[70]+switch_rise_cb_mux[0][1]_rrnode[70]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[70] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_fall_cb_mux[0][1]_rrnode[70]' to='start_fall_cb_mux[0][1]_rrnode[70]+switch_fall_cb_mux[0][1]_rrnode[70]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_cb_mux[0][1]_rrnode[70]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_cb_mux[0][1]_rrnode[70]' -******* Normal TYPE loads ******* -Xload_inv[0]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_2level_tapbuf_size4[0]->out mux_2level_tapbuf_size4[0]->out_out[3] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to0] -+ param='leakage_cb_mux[0][1]_rrnode[70]' -.meas tran sum_energy_per_cycle_cb_mux[0to0] -+ param='energy_per_cycle_cb_mux[0][1]_rrnode[70]' -Xmux_2level_tapbuf_size4[1] mux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->out sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size4[1] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****1010***** -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_2level_tapbuf_size4[1]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[1]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[1]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[1]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[1] gvdd_mux_2level_tapbuf_size4[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[16] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[16] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[16] param='mux_2level_tapbuf_size4[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[1]_energy_per_cycle param='mux_2level_tapbuf_size4[1]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[16] param='mux_2level_tapbuf_size4[1]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[16] param='dynamic_power_cb_mux[0][1]_rrnode[16]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[16] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_rise_cb_mux[0][1]_rrnode[16]' to='start_rise_cb_mux[0][1]_rrnode[16]+switch_rise_cb_mux[0][1]_rrnode[16]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[16] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_fall_cb_mux[0][1]_rrnode[16]' to='start_fall_cb_mux[0][1]_rrnode[16]+switch_fall_cb_mux[0][1]_rrnode[16]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[0][1]_rrnode[16]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[0][1]_rrnode[16]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to1] -+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[0][1]_rrnode[16]' -.meas tran sum_energy_per_cycle_cb_mux[0to1] -+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[0][1]_rrnode[16]' -Xmux_2level_tapbuf_size4[2] mux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->outb sram[10]->out sram[11]->out sram[11]->outb gvdd_mux_2level_tapbuf_size4[2] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****1010***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_2level_tapbuf_size4[2]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[2]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[2]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[2]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[2] gvdd_mux_2level_tapbuf_size4[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[18] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[18] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[18] param='mux_2level_tapbuf_size4[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[2]_energy_per_cycle param='mux_2level_tapbuf_size4[2]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[18] param='mux_2level_tapbuf_size4[2]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[18] param='dynamic_power_cb_mux[0][1]_rrnode[18]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[18] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_rise_cb_mux[0][1]_rrnode[18]' to='start_rise_cb_mux[0][1]_rrnode[18]+switch_rise_cb_mux[0][1]_rrnode[18]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[18] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_fall_cb_mux[0][1]_rrnode[18]' to='start_fall_cb_mux[0][1]_rrnode[18]+switch_fall_cb_mux[0][1]_rrnode[18]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[0][1]_rrnode[18]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[0][1]_rrnode[18]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to2] -+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[0][1]_rrnode[18]' -.meas tran sum_energy_per_cycle_cb_mux[0to2] -+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[0][1]_rrnode[18]' -Xmux_2level_tapbuf_size4[3] mux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->outb sram[14]->out sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size4[3] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****1010***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_2level_tapbuf_size4[3]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[3] gvdd_mux_2level_tapbuf_size4[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[20] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[20] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[20] param='mux_2level_tapbuf_size4[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[3]_energy_per_cycle param='mux_2level_tapbuf_size4[3]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[20] param='mux_2level_tapbuf_size4[3]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[20] param='dynamic_power_cb_mux[0][1]_rrnode[20]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[20] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_rise_cb_mux[0][1]_rrnode[20]' to='start_rise_cb_mux[0][1]_rrnode[20]+switch_rise_cb_mux[0][1]_rrnode[20]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[20] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_fall_cb_mux[0][1]_rrnode[20]' to='start_fall_cb_mux[0][1]_rrnode[20]+switch_fall_cb_mux[0][1]_rrnode[20]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[0][1]_rrnode[20]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[0][1]_rrnode[20]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to3] -+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[0][1]_rrnode[20]' -.meas tran sum_energy_per_cycle_cb_mux[0to3] -+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[0][1]_rrnode[20]' -Xmux_2level_tapbuf_size4[4] mux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb gvdd_mux_2level_tapbuf_size4[4] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****1010***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_2level_tapbuf_size4[4]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[4] gvdd_mux_2level_tapbuf_size4[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[22] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[22] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[22] param='mux_2level_tapbuf_size4[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[4]_energy_per_cycle param='mux_2level_tapbuf_size4[4]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[22] param='mux_2level_tapbuf_size4[4]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[22] param='dynamic_power_cb_mux[0][1]_rrnode[22]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[22] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_rise_cb_mux[0][1]_rrnode[22]' to='start_rise_cb_mux[0][1]_rrnode[22]+switch_rise_cb_mux[0][1]_rrnode[22]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[22] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_fall_cb_mux[0][1]_rrnode[22]' to='start_fall_cb_mux[0][1]_rrnode[22]+switch_fall_cb_mux[0][1]_rrnode[22]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[0][1]_rrnode[22]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[0][1]_rrnode[22]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to4] -+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[0][1]_rrnode[22]' -.meas tran sum_energy_per_cycle_cb_mux[0to4] -+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[0][1]_rrnode[22]' -Xmux_2level_tapbuf_size4[5] mux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->out sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->outb sram[22]->out sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size4[5] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[5], level=2, select_path_id=0. ***** -*****1010***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_2level_tapbuf_size4[5]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[5] gvdd_mux_2level_tapbuf_size4[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[24] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[24] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[24] param='mux_2level_tapbuf_size4[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[5]_energy_per_cycle param='mux_2level_tapbuf_size4[5]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[24] param='mux_2level_tapbuf_size4[5]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[24] param='dynamic_power_cb_mux[0][1]_rrnode[24]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[24] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_rise_cb_mux[0][1]_rrnode[24]' to='start_rise_cb_mux[0][1]_rrnode[24]+switch_rise_cb_mux[0][1]_rrnode[24]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[24] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_fall_cb_mux[0][1]_rrnode[24]' to='start_fall_cb_mux[0][1]_rrnode[24]+switch_fall_cb_mux[0][1]_rrnode[24]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[0][1]_rrnode[24]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[0][1]_rrnode[24]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to5] -+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[0][1]_rrnode[24]' -.meas tran sum_energy_per_cycle_cb_mux[0to5] -+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[0][1]_rrnode[24]' -Xmux_2level_tapbuf_size4[6] mux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->outb sram[26]->out sram[27]->out sram[27]->outb gvdd_mux_2level_tapbuf_size4[6] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****1010***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_2level_tapbuf_size4[6]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[6] gvdd_mux_2level_tapbuf_size4[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[26] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[26] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[26] param='mux_2level_tapbuf_size4[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[6]_energy_per_cycle param='mux_2level_tapbuf_size4[6]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[26] param='mux_2level_tapbuf_size4[6]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[26] param='dynamic_power_cb_mux[0][1]_rrnode[26]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[26] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_rise_cb_mux[0][1]_rrnode[26]' to='start_rise_cb_mux[0][1]_rrnode[26]+switch_rise_cb_mux[0][1]_rrnode[26]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[26] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_fall_cb_mux[0][1]_rrnode[26]' to='start_fall_cb_mux[0][1]_rrnode[26]+switch_fall_cb_mux[0][1]_rrnode[26]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[0][1]_rrnode[26]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[0][1]_rrnode[26]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to6] -+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[0][1]_rrnode[26]' -.meas tran sum_energy_per_cycle_cb_mux[0to6] -+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[0][1]_rrnode[26]' -Xmux_2level_tapbuf_size4[7] mux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->out sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->outb sram[30]->out sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size4[7] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****1010***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_2level_tapbuf_size4[7]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[3] density = 0.1906, probability=0.4782.***** -Vmux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_2level_tapbuf_size4[7] gvdd_mux_2level_tapbuf_size4[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[28] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[28] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[28] param='mux_2level_tapbuf_size4[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='clock_period' to='7*clock_period' -.meas tran mux_2level_tapbuf_size4[7]_energy_per_cycle param='mux_2level_tapbuf_size4[7]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[28] param='mux_2level_tapbuf_size4[7]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[28] param='dynamic_power_cb_mux[0][1]_rrnode[28]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[28] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_rise_cb_mux[0][1]_rrnode[28]' to='start_rise_cb_mux[0][1]_rrnode[28]+switch_rise_cb_mux[0][1]_rrnode[28]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[28] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_fall_cb_mux[0][1]_rrnode[28]' to='start_fall_cb_mux[0][1]_rrnode[28]+switch_fall_cb_mux[0][1]_rrnode[28]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[0][1]_rrnode[28]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[0][1]_rrnode[28]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to7] -+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[0][1]_rrnode[28]' -.meas tran sum_energy_per_cycle_cb_mux[0to7] -+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[0][1]_rrnode[28]' -Xmux_2level_tapbuf_size4[8] mux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->outb sram[34]->out sram[35]->out sram[35]->outb gvdd_mux_2level_tapbuf_size4[8] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****1010***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -***** Signal mux_2level_tapbuf_size4[8]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[8] gvdd_mux_2level_tapbuf_size4[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[30] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[30] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[30] param='mux_2level_tapbuf_size4[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[8]_energy_per_cycle param='mux_2level_tapbuf_size4[8]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[30] param='mux_2level_tapbuf_size4[8]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[30] param='dynamic_power_cb_mux[0][1]_rrnode[30]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[30] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_rise_cb_mux[0][1]_rrnode[30]' to='start_rise_cb_mux[0][1]_rrnode[30]+switch_rise_cb_mux[0][1]_rrnode[30]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[30] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_fall_cb_mux[0][1]_rrnode[30]' to='start_fall_cb_mux[0][1]_rrnode[30]+switch_fall_cb_mux[0][1]_rrnode[30]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[0][1]_rrnode[30]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[0][1]_rrnode[30]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to8] -+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[0][1]_rrnode[30]' -.meas tran sum_energy_per_cycle_cb_mux[0to8] -+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[0][1]_rrnode[30]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='7*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to8]' -.meas tran total_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to8]' -.meas tran total_leakage_power_cb_mux -+ param='sum_leakage_power_cb_mux[0to8]' -.meas tran total_energy_per_cycle_cb_mux -+ param='sum_energy_per_cycle_cb_mux[0to8]' -.end diff --git a/examples/spice_test_example_1/cb_mux_tb/example_1_cby1_1_cbmux_testbench.sp b/examples/spice_test_example_1/cb_mux_tb/example_1_cby1_1_cbmux_testbench.sp deleted file mode 100644 index de47ee992..000000000 --- a/examples/spice_test_example_1/cb_mux_tb/example_1_cby1_1_cbmux_testbench.sp +++ /dev/null @@ -1,671 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_2level_tapbuf_size4[0] mux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->outb sram[2]->out sram[3]->out sram[3]->outb gvdd_mux_2level_tapbuf_size4[0] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****1010***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -***** Signal mux_2level_tapbuf_size4[0]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[0] mux_2level_tapbuf_size4[0]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[1] mux_2level_tapbuf_size4[0]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[2] mux_2level_tapbuf_size4[0]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[0]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[0]->in[3] mux_2level_tapbuf_size4[0]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[0] gvdd_mux_2level_tapbuf_size4[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[121] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[121] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[121] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[121] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[121] when v(mux_2level_tapbuf_size4[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[121] trig v(mux_2level_tapbuf_size4[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[121] param='mux_2level_tapbuf_size4[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[0]_energy_per_cycle param='mux_2level_tapbuf_size4[0]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[121] param='mux_2level_tapbuf_size4[0]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[121] param='dynamic_power_cb_mux[1][1]_rrnode[121]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[121] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_rise_cb_mux[1][1]_rrnode[121]' to='start_rise_cb_mux[1][1]_rrnode[121]+switch_rise_cb_mux[1][1]_rrnode[121]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[121] avg p(Vgvdd_mux_2level_tapbuf_size4[0]) from='start_fall_cb_mux[1][1]_rrnode[121]' to='start_fall_cb_mux[1][1]_rrnode[121]+switch_fall_cb_mux[1][1]_rrnode[121]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_cb_mux[1][1]_rrnode[121]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][1]_rrnode[121]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to0] -+ param='leakage_cb_mux[1][1]_rrnode[121]' -.meas tran sum_energy_per_cycle_cb_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][1]_rrnode[121]' -Xmux_2level_tapbuf_size4[1] mux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->out sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size4[1] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****1010***** -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_2level_tapbuf_size4[1]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[0] mux_2level_tapbuf_size4[1]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[1]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[1] mux_2level_tapbuf_size4[1]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[1]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[2] mux_2level_tapbuf_size4[1]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[1]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[1]->in[3] mux_2level_tapbuf_size4[1]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[1] gvdd_mux_2level_tapbuf_size4[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[123] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[123] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[123] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[123] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[123] when v(mux_2level_tapbuf_size4[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[123] trig v(mux_2level_tapbuf_size4[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[123] param='mux_2level_tapbuf_size4[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[1]_energy_per_cycle param='mux_2level_tapbuf_size4[1]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[123] param='mux_2level_tapbuf_size4[1]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[123] param='dynamic_power_cb_mux[1][1]_rrnode[123]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[123] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_rise_cb_mux[1][1]_rrnode[123]' to='start_rise_cb_mux[1][1]_rrnode[123]+switch_rise_cb_mux[1][1]_rrnode[123]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[123] avg p(Vgvdd_mux_2level_tapbuf_size4[1]) from='start_fall_cb_mux[1][1]_rrnode[123]' to='start_fall_cb_mux[1][1]_rrnode[123]+switch_fall_cb_mux[1][1]_rrnode[123]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[1][1]_rrnode[123]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[123]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to1] -+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[1][1]_rrnode[123]' -.meas tran sum_energy_per_cycle_cb_mux[0to1] -+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[123]' -Xmux_2level_tapbuf_size4[2] mux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->outb sram[10]->out sram[11]->out sram[11]->outb gvdd_mux_2level_tapbuf_size4[2] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****1010***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_2level_tapbuf_size4[2]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[0] mux_2level_tapbuf_size4[2]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[2]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[1] mux_2level_tapbuf_size4[2]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[2]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[2] mux_2level_tapbuf_size4[2]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[2]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[2]->in[3] mux_2level_tapbuf_size4[2]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[2] gvdd_mux_2level_tapbuf_size4[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[125] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[125] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[125] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[125] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[125] when v(mux_2level_tapbuf_size4[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[125] trig v(mux_2level_tapbuf_size4[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[125] param='mux_2level_tapbuf_size4[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[2]_energy_per_cycle param='mux_2level_tapbuf_size4[2]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[125] param='mux_2level_tapbuf_size4[2]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[125] param='dynamic_power_cb_mux[1][1]_rrnode[125]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[125] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_rise_cb_mux[1][1]_rrnode[125]' to='start_rise_cb_mux[1][1]_rrnode[125]+switch_rise_cb_mux[1][1]_rrnode[125]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[125] avg p(Vgvdd_mux_2level_tapbuf_size4[2]) from='start_fall_cb_mux[1][1]_rrnode[125]' to='start_fall_cb_mux[1][1]_rrnode[125]+switch_fall_cb_mux[1][1]_rrnode[125]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[1][1]_rrnode[125]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[125]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to2] -+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[1][1]_rrnode[125]' -.meas tran sum_energy_per_cycle_cb_mux[0to2] -+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[125]' -Xmux_2level_tapbuf_size4[3] mux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->outb sram[14]->out sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size4[3] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****1010***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_2level_tapbuf_size4[3]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[0] mux_2level_tapbuf_size4[3]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[1] mux_2level_tapbuf_size4[3]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[2] mux_2level_tapbuf_size4[3]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[3]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[3]->in[3] mux_2level_tapbuf_size4[3]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[3] gvdd_mux_2level_tapbuf_size4[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[127] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[127] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[127] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[127] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[127] when v(mux_2level_tapbuf_size4[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[127] trig v(mux_2level_tapbuf_size4[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[127] param='mux_2level_tapbuf_size4[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[3]_energy_per_cycle param='mux_2level_tapbuf_size4[3]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[127] param='mux_2level_tapbuf_size4[3]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[127] param='dynamic_power_cb_mux[1][1]_rrnode[127]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[127] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_rise_cb_mux[1][1]_rrnode[127]' to='start_rise_cb_mux[1][1]_rrnode[127]+switch_rise_cb_mux[1][1]_rrnode[127]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[127] avg p(Vgvdd_mux_2level_tapbuf_size4[3]) from='start_fall_cb_mux[1][1]_rrnode[127]' to='start_fall_cb_mux[1][1]_rrnode[127]+switch_fall_cb_mux[1][1]_rrnode[127]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[1][1]_rrnode[127]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[127]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to3] -+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[1][1]_rrnode[127]' -.meas tran sum_energy_per_cycle_cb_mux[0to3] -+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[127]' -Xmux_2level_tapbuf_size4[4] mux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb gvdd_mux_2level_tapbuf_size4[4] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****1010***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_2level_tapbuf_size4[4]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[0] mux_2level_tapbuf_size4[4]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[1] mux_2level_tapbuf_size4[4]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[2] mux_2level_tapbuf_size4[4]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[4]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[4]->in[3] mux_2level_tapbuf_size4[4]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[4] gvdd_mux_2level_tapbuf_size4[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[129] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[129] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[129] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[129] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[129] when v(mux_2level_tapbuf_size4[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[129] trig v(mux_2level_tapbuf_size4[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[129] param='mux_2level_tapbuf_size4[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[4]_energy_per_cycle param='mux_2level_tapbuf_size4[4]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[129] param='mux_2level_tapbuf_size4[4]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[129] param='dynamic_power_cb_mux[1][1]_rrnode[129]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[129] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_rise_cb_mux[1][1]_rrnode[129]' to='start_rise_cb_mux[1][1]_rrnode[129]+switch_rise_cb_mux[1][1]_rrnode[129]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[129] avg p(Vgvdd_mux_2level_tapbuf_size4[4]) from='start_fall_cb_mux[1][1]_rrnode[129]' to='start_fall_cb_mux[1][1]_rrnode[129]+switch_fall_cb_mux[1][1]_rrnode[129]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[1][1]_rrnode[129]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[129]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to4] -+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[1][1]_rrnode[129]' -.meas tran sum_energy_per_cycle_cb_mux[0to4] -+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[129]' -Xmux_2level_tapbuf_size4[5] mux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->out sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->outb sram[22]->out sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size4[5] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[5], level=2, select_path_id=0. ***** -*****1010***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_2level_tapbuf_size4[5]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[0] mux_2level_tapbuf_size4[5]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[1] mux_2level_tapbuf_size4[5]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[2] mux_2level_tapbuf_size4[5]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[5]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[5]->in[3] mux_2level_tapbuf_size4[5]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[5] gvdd_mux_2level_tapbuf_size4[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[131] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[131] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[131] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[131] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[131] when v(mux_2level_tapbuf_size4[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[131] trig v(mux_2level_tapbuf_size4[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[131] param='mux_2level_tapbuf_size4[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[5]_energy_per_cycle param='mux_2level_tapbuf_size4[5]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[131] param='mux_2level_tapbuf_size4[5]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[131] param='dynamic_power_cb_mux[1][1]_rrnode[131]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[131] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_rise_cb_mux[1][1]_rrnode[131]' to='start_rise_cb_mux[1][1]_rrnode[131]+switch_rise_cb_mux[1][1]_rrnode[131]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[131] avg p(Vgvdd_mux_2level_tapbuf_size4[5]) from='start_fall_cb_mux[1][1]_rrnode[131]' to='start_fall_cb_mux[1][1]_rrnode[131]+switch_fall_cb_mux[1][1]_rrnode[131]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[1][1]_rrnode[131]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[131]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to5] -+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[1][1]_rrnode[131]' -.meas tran sum_energy_per_cycle_cb_mux[0to5] -+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[131]' -Xmux_2level_tapbuf_size4[6] mux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->outb sram[26]->out sram[27]->out sram[27]->outb gvdd_mux_2level_tapbuf_size4[6] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****1010***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_2level_tapbuf_size4[6]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[0] mux_2level_tapbuf_size4[6]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[1] mux_2level_tapbuf_size4[6]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[2] mux_2level_tapbuf_size4[6]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[6]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[6]->in[3] mux_2level_tapbuf_size4[6]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[6] gvdd_mux_2level_tapbuf_size4[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[133] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[133] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[133] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[133] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[133] when v(mux_2level_tapbuf_size4[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[133] trig v(mux_2level_tapbuf_size4[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[133] param='mux_2level_tapbuf_size4[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[6]_energy_per_cycle param='mux_2level_tapbuf_size4[6]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[133] param='mux_2level_tapbuf_size4[6]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[133] param='dynamic_power_cb_mux[1][1]_rrnode[133]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[133] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_rise_cb_mux[1][1]_rrnode[133]' to='start_rise_cb_mux[1][1]_rrnode[133]+switch_rise_cb_mux[1][1]_rrnode[133]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[133] avg p(Vgvdd_mux_2level_tapbuf_size4[6]) from='start_fall_cb_mux[1][1]_rrnode[133]' to='start_fall_cb_mux[1][1]_rrnode[133]+switch_fall_cb_mux[1][1]_rrnode[133]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[1][1]_rrnode[133]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[133]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to6] -+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[1][1]_rrnode[133]' -.meas tran sum_energy_per_cycle_cb_mux[0to6] -+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[133]' -Xmux_2level_tapbuf_size4[7] mux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->out sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->outb sram[30]->out sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size4[7] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****1010***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_2level_tapbuf_size4[7]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[0] mux_2level_tapbuf_size4[7]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[1] mux_2level_tapbuf_size4[7]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[2] mux_2level_tapbuf_size4[7]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[7]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[7]->in[3] mux_2level_tapbuf_size4[7]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[7] gvdd_mux_2level_tapbuf_size4[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[135] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[135] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[135] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[135] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[135] when v(mux_2level_tapbuf_size4[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[135] trig v(mux_2level_tapbuf_size4[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[135] param='mux_2level_tapbuf_size4[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[7]_energy_per_cycle param='mux_2level_tapbuf_size4[7]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[135] param='mux_2level_tapbuf_size4[7]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[135] param='dynamic_power_cb_mux[1][1]_rrnode[135]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[135] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_rise_cb_mux[1][1]_rrnode[135]' to='start_rise_cb_mux[1][1]_rrnode[135]+switch_rise_cb_mux[1][1]_rrnode[135]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[135] avg p(Vgvdd_mux_2level_tapbuf_size4[7]) from='start_fall_cb_mux[1][1]_rrnode[135]' to='start_fall_cb_mux[1][1]_rrnode[135]+switch_fall_cb_mux[1][1]_rrnode[135]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[1][1]_rrnode[135]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[135]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to7] -+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[1][1]_rrnode[135]' -.meas tran sum_energy_per_cycle_cb_mux[0to7] -+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[135]' -Xmux_2level_tapbuf_size4[8] mux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->outb sram[34]->out sram[35]->out sram[35]->outb gvdd_mux_2level_tapbuf_size4[8] 0 mux_2level_tapbuf_size4 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****1010***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -***** Signal mux_2level_tapbuf_size4[8]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[0] mux_2level_tapbuf_size4[8]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[1] mux_2level_tapbuf_size4[8]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[2] mux_2level_tapbuf_size4[8]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size4[8]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size4[8]->in[3] mux_2level_tapbuf_size4[8]->in[3] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size4[8] gvdd_mux_2level_tapbuf_size4[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[68] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[68] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[68] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[68] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[68] when v(mux_2level_tapbuf_size4[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[68] trig v(mux_2level_tapbuf_size4[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size4[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[68] param='mux_2level_tapbuf_size4[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size4[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size4[8]_energy_per_cycle param='mux_2level_tapbuf_size4[8]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[68] param='mux_2level_tapbuf_size4[8]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[68] param='dynamic_power_cb_mux[1][1]_rrnode[68]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[68] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_rise_cb_mux[1][1]_rrnode[68]' to='start_rise_cb_mux[1][1]_rrnode[68]+switch_rise_cb_mux[1][1]_rrnode[68]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[68] avg p(Vgvdd_mux_2level_tapbuf_size4[8]) from='start_fall_cb_mux[1][1]_rrnode[68]' to='start_fall_cb_mux[1][1]_rrnode[68]+switch_fall_cb_mux[1][1]_rrnode[68]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[1][1]_rrnode[68]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[68]' -******* Normal TYPE loads ******* -Xload_inv[0]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_2level_tapbuf_size4[8]->out mux_2level_tapbuf_size4[8]->out_out[3] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to8] -+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[1][1]_rrnode[68]' -.meas tran sum_energy_per_cycle_cb_mux[0to8] -+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[68]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 2 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '2*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='2*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to8]' -.meas tran total_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to8]' -.meas tran total_leakage_power_cb_mux -+ param='sum_leakage_power_cb_mux[0to8]' -.meas tran total_energy_per_cycle_cb_mux -+ param='sum_energy_per_cycle_cb_mux[0to8]' -.end diff --git a/examples/spice_test_example_1/cb_tb/example_1_cbx1_0_cb_testbench.sp b/examples/spice_test_example_1/cb_tb/example_1_cbx1_0_cb_testbench.sp deleted file mode 100644 index 7c998e53e..000000000 --- a/examples/spice_test_example_1/cb_tb/example_1_cbx1_0_cb_testbench.sp +++ /dev/null @@ -1,268 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_cbs -****** Include subckt netlists: Connection Box X-channel [1][0] ***** -.include './spice_test_example_1/subckt/cbx_1_0.sp' -***** Call defined Connection Box[1][0] ***** -Xcbx[1][0] -+ chanx[1][0]_midout[0] -+ chanx[1][0]_midout[1] -+ chanx[1][0]_midout[2] -+ chanx[1][0]_midout[3] -+ chanx[1][0]_midout[4] -+ chanx[1][0]_midout[5] -+ chanx[1][0]_midout[6] -+ chanx[1][0]_midout[7] -+ chanx[1][0]_midout[8] -+ chanx[1][0]_midout[9] -+ chanx[1][0]_midout[10] -+ chanx[1][0]_midout[11] -+ chanx[1][0]_midout[12] -+ chanx[1][0]_midout[13] -+ chanx[1][0]_midout[14] -+ chanx[1][0]_midout[15] -+ chanx[1][0]_midout[16] -+ chanx[1][0]_midout[17] -+ chanx[1][0]_midout[18] -+ chanx[1][0]_midout[19] -+ chanx[1][0]_midout[20] -+ chanx[1][0]_midout[21] -+ chanx[1][0]_midout[22] -+ chanx[1][0]_midout[23] -+ chanx[1][0]_midout[24] -+ chanx[1][0]_midout[25] -+ chanx[1][0]_midout[26] -+ chanx[1][0]_midout[27] -+ chanx[1][0]_midout[28] -+ chanx[1][0]_midout[29] -+ grid[1][1]_pin[0][2][2] -+ grid[1][0]_pin[0][0][0] -+ grid[1][0]_pin[0][0][2] -+ grid[1][0]_pin[0][0][4] -+ grid[1][0]_pin[0][0][6] -+ grid[1][0]_pin[0][0][8] -+ grid[1][0]_pin[0][0][10] -+ grid[1][0]_pin[0][0][12] -+ grid[1][0]_pin[0][0][14] -+ gvdd_cbx[1][0] 0 cbx[1][0] -***** Signal chanx[1][0]_midout[0] density = 0, probability=0.***** -Vchanx[1][0]_midout[0] chanx[1][0]_midout[0] 0 -+ 0 -***** Signal chanx[1][0]_midout[1] density = 0, probability=0.***** -Vchanx[1][0]_midout[1] chanx[1][0]_midout[1] 0 -+ 0 -***** Signal chanx[1][0]_midout[2] density = 0, probability=0.***** -Vchanx[1][0]_midout[2] chanx[1][0]_midout[2] 0 -+ 0 -***** Signal chanx[1][0]_midout[3] density = 0, probability=0.***** -Vchanx[1][0]_midout[3] chanx[1][0]_midout[3] 0 -+ 0 -***** Signal chanx[1][0]_midout[4] density = 0, probability=0.***** -Vchanx[1][0]_midout[4] chanx[1][0]_midout[4] 0 -+ 0 -***** Signal chanx[1][0]_midout[5] density = 0, probability=0.***** -Vchanx[1][0]_midout[5] chanx[1][0]_midout[5] 0 -+ 0 -***** Signal chanx[1][0]_midout[6] density = 0, probability=0.***** -Vchanx[1][0]_midout[6] chanx[1][0]_midout[6] 0 -+ 0 -***** Signal chanx[1][0]_midout[7] density = 0, probability=0.***** -Vchanx[1][0]_midout[7] chanx[1][0]_midout[7] 0 -+ 0 -***** Signal chanx[1][0]_midout[8] density = 0, probability=0.***** -Vchanx[1][0]_midout[8] chanx[1][0]_midout[8] 0 -+ 0 -***** Signal chanx[1][0]_midout[9] density = 0, probability=0.***** -Vchanx[1][0]_midout[9] chanx[1][0]_midout[9] 0 -+ 0 -***** Signal chanx[1][0]_midout[10] density = 0, probability=0.***** -Vchanx[1][0]_midout[10] chanx[1][0]_midout[10] 0 -+ 0 -***** Signal chanx[1][0]_midout[11] density = 0, probability=0.***** -Vchanx[1][0]_midout[11] chanx[1][0]_midout[11] 0 -+ 0 -***** Signal chanx[1][0]_midout[12] density = 0, probability=0.***** -Vchanx[1][0]_midout[12] chanx[1][0]_midout[12] 0 -+ 0 -***** Signal chanx[1][0]_midout[13] density = 0, probability=0.***** -Vchanx[1][0]_midout[13] chanx[1][0]_midout[13] 0 -+ 0 -***** Signal chanx[1][0]_midout[14] density = 0, probability=0.***** -Vchanx[1][0]_midout[14] chanx[1][0]_midout[14] 0 -+ 0 -***** Signal chanx[1][0]_midout[15] density = 0, probability=0.***** -Vchanx[1][0]_midout[15] chanx[1][0]_midout[15] 0 -+ 0 -***** Signal chanx[1][0]_midout[16] density = 0, probability=0.***** -Vchanx[1][0]_midout[16] chanx[1][0]_midout[16] 0 -+ 0 -***** Signal chanx[1][0]_midout[17] density = 0, probability=0.***** -Vchanx[1][0]_midout[17] chanx[1][0]_midout[17] 0 -+ 0 -***** Signal chanx[1][0]_midout[18] density = 0, probability=0.***** -Vchanx[1][0]_midout[18] chanx[1][0]_midout[18] 0 -+ 0 -***** Signal chanx[1][0]_midout[19] density = 0, probability=0.***** -Vchanx[1][0]_midout[19] chanx[1][0]_midout[19] 0 -+ 0 -***** Signal chanx[1][0]_midout[20] density = 0, probability=0.***** -Vchanx[1][0]_midout[20] chanx[1][0]_midout[20] 0 -+ 0 -***** Signal chanx[1][0]_midout[21] density = 0, probability=0.***** -Vchanx[1][0]_midout[21] chanx[1][0]_midout[21] 0 -+ 0 -***** Signal chanx[1][0]_midout[22] density = 0, probability=0.***** -Vchanx[1][0]_midout[22] chanx[1][0]_midout[22] 0 -+ 0 -***** Signal chanx[1][0]_midout[23] density = 0, probability=0.***** -Vchanx[1][0]_midout[23] chanx[1][0]_midout[23] 0 -+ 0 -***** Signal chanx[1][0]_midout[24] density = 0, probability=0.***** -Vchanx[1][0]_midout[24] chanx[1][0]_midout[24] 0 -+ 0 -***** Signal chanx[1][0]_midout[25] density = 0, probability=0.***** -Vchanx[1][0]_midout[25] chanx[1][0]_midout[25] 0 -+ 0 -***** Signal chanx[1][0]_midout[26] density = 0, probability=0.***** -Vchanx[1][0]_midout[26] chanx[1][0]_midout[26] 0 -+ 0 -***** Signal chanx[1][0]_midout[27] density = 0, probability=0.***** -Vchanx[1][0]_midout[27] chanx[1][0]_midout[27] 0 -+ 0 -***** Signal chanx[1][0]_midout[28] density = 0, probability=0.***** -Vchanx[1][0]_midout[28] chanx[1][0]_midout[28] 0 -+ 0 -***** Signal chanx[1][0]_midout[29] density = 0, probability=0.***** -Vchanx[1][0]_midout[29] chanx[1][0]_midout[29] 0 -+ 0 -******* Normal TYPE loads ******* -Xload_inv[0]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[3] gvdd_load 0 inv size=1 -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -***** Voltage supplies ***** -***** Voltage supplies ***** -Vgvdd_cb[1][0] gvdd_cbx[1][0] 0 vsp -Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp -***** 2 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '2*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_cb avg p(Vgvdd_cb[1][0]) from=0 to='clock_period' -.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_cb avg p(Vgvdd_cb[1][0]) from='clock_period' to='2*clock_period' -.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period' -.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='2*clock_period' -.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_1/cb_tb/example_1_cbx1_1_cb_testbench.sp b/examples/spice_test_example_1/cb_tb/example_1_cbx1_1_cb_testbench.sp deleted file mode 100644 index 279ef6b1a..000000000 --- a/examples/spice_test_example_1/cb_tb/example_1_cbx1_1_cb_testbench.sp +++ /dev/null @@ -1,280 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_cbs -****** Include subckt netlists: Connection Box X-channel [1][1] ***** -.include './spice_test_example_1/subckt/cbx_1_1.sp' -***** Call defined Connection Box[1][1] ***** -Xcbx[1][1] -+ chanx[1][1]_midout[0] -+ chanx[1][1]_midout[1] -+ chanx[1][1]_midout[2] -+ chanx[1][1]_midout[3] -+ chanx[1][1]_midout[4] -+ chanx[1][1]_midout[5] -+ chanx[1][1]_midout[6] -+ chanx[1][1]_midout[7] -+ chanx[1][1]_midout[8] -+ chanx[1][1]_midout[9] -+ chanx[1][1]_midout[10] -+ chanx[1][1]_midout[11] -+ chanx[1][1]_midout[12] -+ chanx[1][1]_midout[13] -+ chanx[1][1]_midout[14] -+ chanx[1][1]_midout[15] -+ chanx[1][1]_midout[16] -+ chanx[1][1]_midout[17] -+ chanx[1][1]_midout[18] -+ chanx[1][1]_midout[19] -+ chanx[1][1]_midout[20] -+ chanx[1][1]_midout[21] -+ chanx[1][1]_midout[22] -+ chanx[1][1]_midout[23] -+ chanx[1][1]_midout[24] -+ chanx[1][1]_midout[25] -+ chanx[1][1]_midout[26] -+ chanx[1][1]_midout[27] -+ chanx[1][1]_midout[28] -+ chanx[1][1]_midout[29] -+ grid[1][2]_pin[0][2][0] -+ grid[1][2]_pin[0][2][2] -+ grid[1][2]_pin[0][2][4] -+ grid[1][2]_pin[0][2][6] -+ grid[1][2]_pin[0][2][8] -+ grid[1][2]_pin[0][2][10] -+ grid[1][2]_pin[0][2][12] -+ grid[1][2]_pin[0][2][14] -+ grid[1][1]_pin[0][0][0] -+ gvdd_cbx[1][1] 0 cbx[1][1] -***** Signal chanx[1][1]_midout[0] density = 0.1906, probability=0.5218.***** -Vchanx[1][1]_midout[0] chanx[1][1]_midout[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal chanx[1][1]_midout[1] density = 0.1906, probability=0.4782.***** -Vchanx[1][1]_midout[1] chanx[1][1]_midout[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal chanx[1][1]_midout[2] density = 0.1906, probability=0.5218.***** -Vchanx[1][1]_midout[2] chanx[1][1]_midout[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal chanx[1][1]_midout[3] density = 0.1906, probability=0.5218.***** -Vchanx[1][1]_midout[3] chanx[1][1]_midout[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal chanx[1][1]_midout[4] density = 0, probability=0.***** -Vchanx[1][1]_midout[4] chanx[1][1]_midout[4] 0 -+ 0 -***** Signal chanx[1][1]_midout[5] density = 0, probability=0.***** -Vchanx[1][1]_midout[5] chanx[1][1]_midout[5] 0 -+ 0 -***** Signal chanx[1][1]_midout[6] density = 0, probability=0.***** -Vchanx[1][1]_midout[6] chanx[1][1]_midout[6] 0 -+ 0 -***** Signal chanx[1][1]_midout[7] density = 0, probability=0.***** -Vchanx[1][1]_midout[7] chanx[1][1]_midout[7] 0 -+ 0 -***** Signal chanx[1][1]_midout[8] density = 0, probability=0.***** -Vchanx[1][1]_midout[8] chanx[1][1]_midout[8] 0 -+ 0 -***** Signal chanx[1][1]_midout[9] density = 0, probability=0.***** -Vchanx[1][1]_midout[9] chanx[1][1]_midout[9] 0 -+ 0 -***** Signal chanx[1][1]_midout[10] density = 0, probability=0.***** -Vchanx[1][1]_midout[10] chanx[1][1]_midout[10] 0 -+ 0 -***** Signal chanx[1][1]_midout[11] density = 0, probability=0.***** -Vchanx[1][1]_midout[11] chanx[1][1]_midout[11] 0 -+ 0 -***** Signal chanx[1][1]_midout[12] density = 0, probability=0.***** -Vchanx[1][1]_midout[12] chanx[1][1]_midout[12] 0 -+ 0 -***** Signal chanx[1][1]_midout[13] density = 0, probability=0.***** -Vchanx[1][1]_midout[13] chanx[1][1]_midout[13] 0 -+ 0 -***** Signal chanx[1][1]_midout[14] density = 0, probability=0.***** -Vchanx[1][1]_midout[14] chanx[1][1]_midout[14] 0 -+ 0 -***** Signal chanx[1][1]_midout[15] density = 0, probability=0.***** -Vchanx[1][1]_midout[15] chanx[1][1]_midout[15] 0 -+ 0 -***** Signal chanx[1][1]_midout[16] density = 0, probability=0.***** -Vchanx[1][1]_midout[16] chanx[1][1]_midout[16] 0 -+ 0 -***** Signal chanx[1][1]_midout[17] density = 0, probability=0.***** -Vchanx[1][1]_midout[17] chanx[1][1]_midout[17] 0 -+ 0 -***** Signal chanx[1][1]_midout[18] density = 0, probability=0.***** -Vchanx[1][1]_midout[18] chanx[1][1]_midout[18] 0 -+ 0 -***** Signal chanx[1][1]_midout[19] density = 0, probability=0.***** -Vchanx[1][1]_midout[19] chanx[1][1]_midout[19] 0 -+ 0 -***** Signal chanx[1][1]_midout[20] density = 0, probability=0.***** -Vchanx[1][1]_midout[20] chanx[1][1]_midout[20] 0 -+ 0 -***** Signal chanx[1][1]_midout[21] density = 0, probability=0.***** -Vchanx[1][1]_midout[21] chanx[1][1]_midout[21] 0 -+ 0 -***** Signal chanx[1][1]_midout[22] density = 0, probability=0.***** -Vchanx[1][1]_midout[22] chanx[1][1]_midout[22] 0 -+ 0 -***** Signal chanx[1][1]_midout[23] density = 0, probability=0.***** -Vchanx[1][1]_midout[23] chanx[1][1]_midout[23] 0 -+ 0 -***** Signal chanx[1][1]_midout[24] density = 0, probability=0.***** -Vchanx[1][1]_midout[24] chanx[1][1]_midout[24] 0 -+ 0 -***** Signal chanx[1][1]_midout[25] density = 0, probability=0.***** -Vchanx[1][1]_midout[25] chanx[1][1]_midout[25] 0 -+ 0 -***** Signal chanx[1][1]_midout[26] density = 0, probability=0.***** -Vchanx[1][1]_midout[26] chanx[1][1]_midout[26] 0 -+ 0 -***** Signal chanx[1][1]_midout[27] density = 0, probability=0.***** -Vchanx[1][1]_midout[27] chanx[1][1]_midout[27] 0 -+ 0 -***** Signal chanx[1][1]_midout[28] density = 0.1906, probability=0.4782.***** -Vchanx[1][1]_midout[28] chanx[1][1]_midout[28] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal chanx[1][1]_midout[29] density = 0.1906, probability=0.4782.***** -Vchanx[1][1]_midout[29] chanx[1][1]_midout[29] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[0]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[3] gvdd_load 0 inv size=1 -******* END loads ******* - -***** Voltage supplies ***** -***** Voltage supplies ***** -Vgvdd_cb[1][1] gvdd_cbx[1][1] 0 vsp -Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_cb avg p(Vgvdd_cb[1][1]) from=0 to='clock_period' -.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_cb avg p(Vgvdd_cb[1][1]) from='clock_period' to='7*clock_period' -.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period' -.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='7*clock_period' -.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_1/cb_tb/example_1_cby0_1_cb_testbench.sp b/examples/spice_test_example_1/cb_tb/example_1_cby0_1_cb_testbench.sp deleted file mode 100644 index 59e8ce85a..000000000 --- a/examples/spice_test_example_1/cb_tb/example_1_cby0_1_cb_testbench.sp +++ /dev/null @@ -1,270 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_cbs -****** Include subckt netlists: Connection Box Y-channel [0][1] ***** -.include './spice_test_example_1/subckt/cby_0_1.sp' -***** Call defined Connection Box[0][1] ***** -Xcby[0][1] -+ chany[0][1]_midout[0] -+ chany[0][1]_midout[1] -+ chany[0][1]_midout[2] -+ chany[0][1]_midout[3] -+ chany[0][1]_midout[4] -+ chany[0][1]_midout[5] -+ chany[0][1]_midout[6] -+ chany[0][1]_midout[7] -+ chany[0][1]_midout[8] -+ chany[0][1]_midout[9] -+ chany[0][1]_midout[10] -+ chany[0][1]_midout[11] -+ chany[0][1]_midout[12] -+ chany[0][1]_midout[13] -+ chany[0][1]_midout[14] -+ chany[0][1]_midout[15] -+ chany[0][1]_midout[16] -+ chany[0][1]_midout[17] -+ chany[0][1]_midout[18] -+ chany[0][1]_midout[19] -+ chany[0][1]_midout[20] -+ chany[0][1]_midout[21] -+ chany[0][1]_midout[22] -+ chany[0][1]_midout[23] -+ chany[0][1]_midout[24] -+ chany[0][1]_midout[25] -+ chany[0][1]_midout[26] -+ chany[0][1]_midout[27] -+ chany[0][1]_midout[28] -+ chany[0][1]_midout[29] -+ grid[1][1]_pin[0][3][3] -+ grid[0][1]_pin[0][1][0] -+ grid[0][1]_pin[0][1][2] -+ grid[0][1]_pin[0][1][4] -+ grid[0][1]_pin[0][1][6] -+ grid[0][1]_pin[0][1][8] -+ grid[0][1]_pin[0][1][10] -+ grid[0][1]_pin[0][1][12] -+ grid[0][1]_pin[0][1][14] -+ gvdd_cby[0][1] 0 cby[0][1] -***** Signal chany[0][1]_midout[0] density = 0, probability=0.***** -Vchany[0][1]_midout[0] chany[0][1]_midout[0] 0 -+ 0 -***** Signal chany[0][1]_midout[1] density = 0, probability=0.***** -Vchany[0][1]_midout[1] chany[0][1]_midout[1] 0 -+ 0 -***** Signal chany[0][1]_midout[2] density = 0, probability=0.***** -Vchany[0][1]_midout[2] chany[0][1]_midout[2] 0 -+ 0 -***** Signal chany[0][1]_midout[3] density = 0, probability=0.***** -Vchany[0][1]_midout[3] chany[0][1]_midout[3] 0 -+ 0 -***** Signal chany[0][1]_midout[4] density = 0, probability=0.***** -Vchany[0][1]_midout[4] chany[0][1]_midout[4] 0 -+ 0 -***** Signal chany[0][1]_midout[5] density = 0, probability=0.***** -Vchany[0][1]_midout[5] chany[0][1]_midout[5] 0 -+ 0 -***** Signal chany[0][1]_midout[6] density = 0, probability=0.***** -Vchany[0][1]_midout[6] chany[0][1]_midout[6] 0 -+ 0 -***** Signal chany[0][1]_midout[7] density = 0, probability=0.***** -Vchany[0][1]_midout[7] chany[0][1]_midout[7] 0 -+ 0 -***** Signal chany[0][1]_midout[8] density = 0, probability=0.***** -Vchany[0][1]_midout[8] chany[0][1]_midout[8] 0 -+ 0 -***** Signal chany[0][1]_midout[9] density = 0, probability=0.***** -Vchany[0][1]_midout[9] chany[0][1]_midout[9] 0 -+ 0 -***** Signal chany[0][1]_midout[10] density = 0, probability=0.***** -Vchany[0][1]_midout[10] chany[0][1]_midout[10] 0 -+ 0 -***** Signal chany[0][1]_midout[11] density = 0, probability=0.***** -Vchany[0][1]_midout[11] chany[0][1]_midout[11] 0 -+ 0 -***** Signal chany[0][1]_midout[12] density = 0, probability=0.***** -Vchany[0][1]_midout[12] chany[0][1]_midout[12] 0 -+ 0 -***** Signal chany[0][1]_midout[13] density = 0, probability=0.***** -Vchany[0][1]_midout[13] chany[0][1]_midout[13] 0 -+ 0 -***** Signal chany[0][1]_midout[14] density = 0, probability=0.***** -Vchany[0][1]_midout[14] chany[0][1]_midout[14] 0 -+ 0 -***** Signal chany[0][1]_midout[15] density = 0, probability=0.***** -Vchany[0][1]_midout[15] chany[0][1]_midout[15] 0 -+ 0 -***** Signal chany[0][1]_midout[16] density = 0, probability=0.***** -Vchany[0][1]_midout[16] chany[0][1]_midout[16] 0 -+ 0 -***** Signal chany[0][1]_midout[17] density = 0, probability=0.***** -Vchany[0][1]_midout[17] chany[0][1]_midout[17] 0 -+ 0 -***** Signal chany[0][1]_midout[18] density = 0, probability=0.***** -Vchany[0][1]_midout[18] chany[0][1]_midout[18] 0 -+ 0 -***** Signal chany[0][1]_midout[19] density = 0, probability=0.***** -Vchany[0][1]_midout[19] chany[0][1]_midout[19] 0 -+ 0 -***** Signal chany[0][1]_midout[20] density = 0, probability=0.***** -Vchany[0][1]_midout[20] chany[0][1]_midout[20] 0 -+ 0 -***** Signal chany[0][1]_midout[21] density = 0, probability=0.***** -Vchany[0][1]_midout[21] chany[0][1]_midout[21] 0 -+ 0 -***** Signal chany[0][1]_midout[22] density = 0, probability=0.***** -Vchany[0][1]_midout[22] chany[0][1]_midout[22] 0 -+ 0 -***** Signal chany[0][1]_midout[23] density = 0, probability=0.***** -Vchany[0][1]_midout[23] chany[0][1]_midout[23] 0 -+ 0 -***** Signal chany[0][1]_midout[24] density = 0, probability=0.***** -Vchany[0][1]_midout[24] chany[0][1]_midout[24] 0 -+ 0 -***** Signal chany[0][1]_midout[25] density = 0, probability=0.***** -Vchany[0][1]_midout[25] chany[0][1]_midout[25] 0 -+ 0 -***** Signal chany[0][1]_midout[26] density = 0, probability=0.***** -Vchany[0][1]_midout[26] chany[0][1]_midout[26] 0 -+ 0 -***** Signal chany[0][1]_midout[27] density = 0.1906, probability=0.4782.***** -Vchany[0][1]_midout[27] chany[0][1]_midout[27] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal chany[0][1]_midout[28] density = 0, probability=0.***** -Vchany[0][1]_midout[28] chany[0][1]_midout[28] 0 -+ 0 -***** Signal chany[0][1]_midout[29] density = 0, probability=0.***** -Vchany[0][1]_midout[29] chany[0][1]_midout[29] 0 -+ 0 -******* Normal TYPE loads ******* -Xload_inv[0]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[3] gvdd_load 0 inv size=1 -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -***** Voltage supplies ***** -***** Voltage supplies ***** -Vgvdd_cb[0][1] gvdd_cby[0][1] 0 vsp -Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_cb avg p(Vgvdd_cb[0][1]) from=0 to='clock_period' -.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_cb avg p(Vgvdd_cb[0][1]) from='clock_period' to='7*clock_period' -.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period' -.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='7*clock_period' -.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_1/cb_tb/example_1_cby1_1_cb_testbench.sp b/examples/spice_test_example_1/cb_tb/example_1_cby1_1_cb_testbench.sp deleted file mode 100644 index ba3936a66..000000000 --- a/examples/spice_test_example_1/cb_tb/example_1_cby1_1_cb_testbench.sp +++ /dev/null @@ -1,276 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_cbs -****** Include subckt netlists: Connection Box Y-channel [1][1] ***** -.include './spice_test_example_1/subckt/cby_1_1.sp' -***** Call defined Connection Box[1][1] ***** -Xcby[1][1] -+ chany[1][1]_midout[0] -+ chany[1][1]_midout[1] -+ chany[1][1]_midout[2] -+ chany[1][1]_midout[3] -+ chany[1][1]_midout[4] -+ chany[1][1]_midout[5] -+ chany[1][1]_midout[6] -+ chany[1][1]_midout[7] -+ chany[1][1]_midout[8] -+ chany[1][1]_midout[9] -+ chany[1][1]_midout[10] -+ chany[1][1]_midout[11] -+ chany[1][1]_midout[12] -+ chany[1][1]_midout[13] -+ chany[1][1]_midout[14] -+ chany[1][1]_midout[15] -+ chany[1][1]_midout[16] -+ chany[1][1]_midout[17] -+ chany[1][1]_midout[18] -+ chany[1][1]_midout[19] -+ chany[1][1]_midout[20] -+ chany[1][1]_midout[21] -+ chany[1][1]_midout[22] -+ chany[1][1]_midout[23] -+ chany[1][1]_midout[24] -+ chany[1][1]_midout[25] -+ chany[1][1]_midout[26] -+ chany[1][1]_midout[27] -+ chany[1][1]_midout[28] -+ chany[1][1]_midout[29] -+ grid[2][1]_pin[0][3][0] -+ grid[2][1]_pin[0][3][2] -+ grid[2][1]_pin[0][3][4] -+ grid[2][1]_pin[0][3][6] -+ grid[2][1]_pin[0][3][8] -+ grid[2][1]_pin[0][3][10] -+ grid[2][1]_pin[0][3][12] -+ grid[2][1]_pin[0][3][14] -+ grid[1][1]_pin[0][1][1] -+ grid[1][1]_pin[0][1][5] -+ gvdd_cby[1][1] 0 cby[1][1] -***** Signal chany[1][1]_midout[0] density = 0, probability=0.***** -Vchany[1][1]_midout[0] chany[1][1]_midout[0] 0 -+ 0 -***** Signal chany[1][1]_midout[1] density = 0, probability=0.***** -Vchany[1][1]_midout[1] chany[1][1]_midout[1] 0 -+ 0 -***** Signal chany[1][1]_midout[2] density = 0, probability=0.***** -Vchany[1][1]_midout[2] chany[1][1]_midout[2] 0 -+ 0 -***** Signal chany[1][1]_midout[3] density = 0, probability=0.***** -Vchany[1][1]_midout[3] chany[1][1]_midout[3] 0 -+ 0 -***** Signal chany[1][1]_midout[4] density = 0, probability=0.***** -Vchany[1][1]_midout[4] chany[1][1]_midout[4] 0 -+ 0 -***** Signal chany[1][1]_midout[5] density = 0, probability=0.***** -Vchany[1][1]_midout[5] chany[1][1]_midout[5] 0 -+ 0 -***** Signal chany[1][1]_midout[6] density = 0, probability=0.***** -Vchany[1][1]_midout[6] chany[1][1]_midout[6] 0 -+ 0 -***** Signal chany[1][1]_midout[7] density = 0, probability=0.***** -Vchany[1][1]_midout[7] chany[1][1]_midout[7] 0 -+ 0 -***** Signal chany[1][1]_midout[8] density = 0, probability=0.***** -Vchany[1][1]_midout[8] chany[1][1]_midout[8] 0 -+ 0 -***** Signal chany[1][1]_midout[9] density = 0, probability=0.***** -Vchany[1][1]_midout[9] chany[1][1]_midout[9] 0 -+ 0 -***** Signal chany[1][1]_midout[10] density = 0, probability=0.***** -Vchany[1][1]_midout[10] chany[1][1]_midout[10] 0 -+ 0 -***** Signal chany[1][1]_midout[11] density = 0, probability=0.***** -Vchany[1][1]_midout[11] chany[1][1]_midout[11] 0 -+ 0 -***** Signal chany[1][1]_midout[12] density = 0, probability=0.***** -Vchany[1][1]_midout[12] chany[1][1]_midout[12] 0 -+ 0 -***** Signal chany[1][1]_midout[13] density = 0, probability=0.***** -Vchany[1][1]_midout[13] chany[1][1]_midout[13] 0 -+ 0 -***** Signal chany[1][1]_midout[14] density = 0, probability=0.***** -Vchany[1][1]_midout[14] chany[1][1]_midout[14] 0 -+ 0 -***** Signal chany[1][1]_midout[15] density = 0, probability=0.***** -Vchany[1][1]_midout[15] chany[1][1]_midout[15] 0 -+ 0 -***** Signal chany[1][1]_midout[16] density = 0, probability=0.***** -Vchany[1][1]_midout[16] chany[1][1]_midout[16] 0 -+ 0 -***** Signal chany[1][1]_midout[17] density = 0, probability=0.***** -Vchany[1][1]_midout[17] chany[1][1]_midout[17] 0 -+ 0 -***** Signal chany[1][1]_midout[18] density = 0, probability=0.***** -Vchany[1][1]_midout[18] chany[1][1]_midout[18] 0 -+ 0 -***** Signal chany[1][1]_midout[19] density = 0, probability=0.***** -Vchany[1][1]_midout[19] chany[1][1]_midout[19] 0 -+ 0 -***** Signal chany[1][1]_midout[20] density = 0, probability=0.***** -Vchany[1][1]_midout[20] chany[1][1]_midout[20] 0 -+ 0 -***** Signal chany[1][1]_midout[21] density = 0, probability=0.***** -Vchany[1][1]_midout[21] chany[1][1]_midout[21] 0 -+ 0 -***** Signal chany[1][1]_midout[22] density = 0, probability=0.***** -Vchany[1][1]_midout[22] chany[1][1]_midout[22] 0 -+ 0 -***** Signal chany[1][1]_midout[23] density = 0, probability=0.***** -Vchany[1][1]_midout[23] chany[1][1]_midout[23] 0 -+ 0 -***** Signal chany[1][1]_midout[24] density = 0, probability=0.***** -Vchany[1][1]_midout[24] chany[1][1]_midout[24] 0 -+ 0 -***** Signal chany[1][1]_midout[25] density = 0, probability=0.***** -Vchany[1][1]_midout[25] chany[1][1]_midout[25] 0 -+ 0 -***** Signal chany[1][1]_midout[26] density = 0, probability=0.***** -Vchany[1][1]_midout[26] chany[1][1]_midout[26] 0 -+ 0 -***** Signal chany[1][1]_midout[27] density = 0, probability=0.***** -Vchany[1][1]_midout[27] chany[1][1]_midout[27] 0 -+ 0 -***** Signal chany[1][1]_midout[28] density = 0, probability=0.***** -Vchany[1][1]_midout[28] chany[1][1]_midout[28] 0 -+ 0 -***** Signal chany[1][1]_midout[29] density = 0, probability=0.***** -Vchany[1][1]_midout[29] chany[1][1]_midout[29] 0 -+ 0 -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[0]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[3] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[4]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[0] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[1] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[2] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[3] gvdd_load 0 inv size=1 -******* END loads ******* - -***** Voltage supplies ***** -***** Voltage supplies ***** -Vgvdd_cb[1][1] gvdd_cby[1][1] 0 vsp -Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp -***** 2 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '2*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_cb avg p(Vgvdd_cb[1][1]) from=0 to='clock_period' -.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_cb avg p(Vgvdd_cb[1][1]) from='clock_period' to='2*clock_period' -.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period' -.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='2*clock_period' -.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_1/example_1.bitstream b/examples/spice_test_example_1/example_1.bitstream deleted file mode 100644 index d53a57db1..000000000 --- a/examples/spice_test_example_1/example_1.bitstream +++ /dev/null @@ -1,361 +0,0 @@ -0, // Configuration bit No.: 364, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 361 -1, // Configuration bit No.: 363, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 361 -0, // Configuration bit No.: 362, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 361 -1, // Configuration bit No.: 361, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 361 -0, // Configuration bit No.: 360, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 357 -1, // Configuration bit No.: 359, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 357 -0, // Configuration bit No.: 358, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 357 -1, // Configuration bit No.: 357, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 357 -0, // Configuration bit No.: 356, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 353 -1, // Configuration bit No.: 355, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 353 -0, // Configuration bit No.: 354, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 353 -1, // Configuration bit No.: 353, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 353 -0, // Configuration bit No.: 352, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 349 -1, // Configuration bit No.: 351, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 349 -0, // Configuration bit No.: 350, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 349 -1, // Configuration bit No.: 349, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 349 -0, // Configuration bit No.: 348, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 345 -1, // Configuration bit No.: 347, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 345 -0, // Configuration bit No.: 346, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 345 -1, // Configuration bit No.: 345, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 345 -0, // Configuration bit No.: 344, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 341 -1, // Configuration bit No.: 343, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 341 -0, // Configuration bit No.: 342, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 341 -1, // Configuration bit No.: 341, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 341 -0, // Configuration bit No.: 340, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 337 -1, // Configuration bit No.: 339, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 337 -0, // Configuration bit No.: 338, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 337 -1, // Configuration bit No.: 337, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 337 -0, // Configuration bit No.: 336, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 333 -1, // Configuration bit No.: 335, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 333 -0, // Configuration bit No.: 334, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 333 -1, // Configuration bit No.: 333, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 333 -0, // Configuration bit No.: 332, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 329 -1, // Configuration bit No.: 331, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 329 -0, // Configuration bit No.: 330, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 329 -1, // Configuration bit No.: 329, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 329 -0, // Configuration bit No.: 328, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 325 -1, // Configuration bit No.: 327, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 325 -0, // Configuration bit No.: 326, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 325 -1, // Configuration bit No.: 325, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 325 -0, // Configuration bit No.: 324, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 321 -1, // Configuration bit No.: 323, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 321 -0, // Configuration bit No.: 322, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 321 -1, // Configuration bit No.: 321, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 321 -0, // Configuration bit No.: 320, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 317 -1, // Configuration bit No.: 319, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 317 -0, // Configuration bit No.: 318, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 317 -1, // Configuration bit No.: 317, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 317 -0, // Configuration bit No.: 316, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 313 -1, // Configuration bit No.: 315, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 313 -0, // Configuration bit No.: 314, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 313 -1, // Configuration bit No.: 313, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 313 -0, // Configuration bit No.: 312, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 309 -1, // Configuration bit No.: 311, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 309 -0, // Configuration bit No.: 310, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 309 -1, // Configuration bit No.: 309, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 309 -0, // Configuration bit No.: 308, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 305 -1, // Configuration bit No.: 307, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 305 -0, // Configuration bit No.: 306, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 305 -1, // Configuration bit No.: 305, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 305 -0, // Configuration bit No.: 304, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 301 -1, // Configuration bit No.: 303, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 301 -0, // Configuration bit No.: 302, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 301 -1, // Configuration bit No.: 301, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 301 -0, // Configuration bit No.: 300, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 297 -1, // Configuration bit No.: 299, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 297 -0, // Configuration bit No.: 298, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 297 -1, // Configuration bit No.: 297, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 297 -1, // Configuration bit No.: 296, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 293 -0, // Configuration bit No.: 295, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 293 -1, // Configuration bit No.: 294, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 293 -0, // Configuration bit No.: 293, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 293 -0, // Configuration bit No.: 292, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 289 -1, // Configuration bit No.: 291, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 289 -0, // Configuration bit No.: 290, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 289 -1, // Configuration bit No.: 289, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 289 -0, // Configuration bit No.: 288, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 285 -1, // Configuration bit No.: 287, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 285 -0, // Configuration bit No.: 286, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 285 -1, // Configuration bit No.: 285, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 285 -0, // Configuration bit No.: 284, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 281 -1, // Configuration bit No.: 283, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 281 -0, // Configuration bit No.: 282, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 281 -1, // Configuration bit No.: 281, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 281 -0, // Configuration bit No.: 280, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 277 -1, // Configuration bit No.: 279, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 277 -0, // Configuration bit No.: 278, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 277 -1, // Configuration bit No.: 277, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 277 -0, // Configuration bit No.: 276, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 273 -1, // Configuration bit No.: 275, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 273 -0, // Configuration bit No.: 274, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 273 -1, // Configuration bit No.: 273, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 273 -0, // Configuration bit No.: 272, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 269 -1, // Configuration bit No.: 271, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 269 -0, // Configuration bit No.: 270, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 269 -1, // Configuration bit No.: 269, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 269 -0, // Configuration bit No.: 268, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 265 -1, // Configuration bit No.: 267, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 265 -0, // Configuration bit No.: 266, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 265 -1, // Configuration bit No.: 265, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 265 -0, // Configuration bit No.: 264, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 261 -1, // Configuration bit No.: 263, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 261 -0, // Configuration bit No.: 262, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 261 -1, // Configuration bit No.: 261, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 261 -0, // Configuration bit No.: 260, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 257 -1, // Configuration bit No.: 259, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 257 -0, // Configuration bit No.: 258, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 257 -1, // Configuration bit No.: 257, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 257 -0, // Configuration bit No.: 256, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 253 -1, // Configuration bit No.: 255, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 253 -0, // Configuration bit No.: 254, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 253 -1, // Configuration bit No.: 253, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 253 -0, // Configuration bit No.: 252, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 249 -1, // Configuration bit No.: 251, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 249 -0, // Configuration bit No.: 250, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 249 -1, // Configuration bit No.: 249, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 249 -0, // Configuration bit No.: 248, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 245 -1, // Configuration bit No.: 247, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 245 -0, // Configuration bit No.: 246, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 245 -1, // Configuration bit No.: 245, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 245 -0, // Configuration bit No.: 244, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 241 -1, // Configuration bit No.: 243, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 241 -0, // Configuration bit No.: 242, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 241 -1, // Configuration bit No.: 241, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 241 -0, // Configuration bit No.: 240, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 237 -1, // Configuration bit No.: 239, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 237 -0, // Configuration bit No.: 238, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 237 -1, // Configuration bit No.: 237, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 237 -0, // Configuration bit No.: 236, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 233 -1, // Configuration bit No.: 235, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 233 -0, // Configuration bit No.: 234, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 233 -1, // Configuration bit No.: 233, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 233 -0, // Configuration bit No.: 232, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 229 -1, // Configuration bit No.: 231, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 229 -0, // Configuration bit No.: 230, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 229 -1, // Configuration bit No.: 229, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 229 -0, // Configuration bit No.: 228, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 225 -1, // Configuration bit No.: 227, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 225 -0, // Configuration bit No.: 226, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 225 -1, // Configuration bit No.: 225, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 225 -0, // Configuration bit No.: 224, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 221 -1, // Configuration bit No.: 223, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 221 -0, // Configuration bit No.: 222, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 221 -1, // Configuration bit No.: 221, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 221 -1, // Configuration bit No.: 217, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 217 -1, // Configuration bit No.: 216, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 216 -1, // Configuration bit No.: 215, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 215 -1, // Configuration bit No.: 214, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 214 -1, // Configuration bit No.: 213, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 213 -1, // Configuration bit No.: 212, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 212 -1, // Configuration bit No.: 211, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 211 -1, // Configuration bit No.: 210, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 210 -1, // Configuration bit No.: 209, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 209 -1, // Configuration bit No.: 208, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 208 -1, // Configuration bit No.: 207, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 207 -1, // Configuration bit No.: 206, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 206 -0, // Configuration bit No.: 207, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 205 -0, // Configuration bit No.: 206, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 205 -1, // Configuration bit No.: 205, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 205 -0, // Configuration bit No.: 204, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 202 -0, // Configuration bit No.: 203, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 202 -1, // Configuration bit No.: 202, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 202 -0, // Configuration bit No.: 201, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 199 -1, // Configuration bit No.: 200, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 199 -0, // Configuration bit No.: 199, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 199 -1, // Configuration bit No.: 196, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 196 -1, // Configuration bit No.: 195, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 195 -1, // Configuration bit No.: 194, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 194 -1, // Configuration bit No.: 193, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 193 -1, // Configuration bit No.: 192, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 192 -1, // Configuration bit No.: 191, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 191 -1, // Configuration bit No.: 190, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 190 -1, // Configuration bit No.: 189, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 189 -1, // Configuration bit No.: 188, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 188 -1, // Configuration bit No.: 187, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 187 -1, // Configuration bit No.: 186, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 186 -1, // Configuration bit No.: 185, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 185 -1, // Configuration bit No.: 184, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 184 -1, // Configuration bit No.: 183, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 183 -0, // Configuration bit No.: 184, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 182 -0, // Configuration bit No.: 183, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 182 -1, // Configuration bit No.: 182, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 182 -1, // Configuration bit No.: 179, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 179 -1, // Configuration bit No.: 178, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 178 -1, // Configuration bit No.: 177, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 177 -1, // Configuration bit No.: 176, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 176 -1, // Configuration bit No.: 175, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 175 -1, // Configuration bit No.: 174, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 174 -1, // Configuration bit No.: 173, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 173 -1, // Configuration bit No.: 172, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 172 -1, // Configuration bit No.: 171, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 171 -1, // Configuration bit No.: 170, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 170 -1, // Configuration bit No.: 169, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 169 -1, // Configuration bit No.: 168, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 168 -1, // Configuration bit No.: 167, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 167 -1, // Configuration bit No.: 166, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 166 -0, // Configuration bit No.: 167, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 165 -0, // Configuration bit No.: 166, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 165 -1, // Configuration bit No.: 165, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 165 -1, // Configuration bit No.: 162, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 162 -1, // Configuration bit No.: 161, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 161 -1, // Configuration bit No.: 160, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 160 -1, // Configuration bit No.: 159, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 159 -1, // Configuration bit No.: 158, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 158 -1, // Configuration bit No.: 157, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 157 -1, // Configuration bit No.: 156, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 156 -1, // Configuration bit No.: 155, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 155 -1, // Configuration bit No.: 154, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 154 -1, // Configuration bit No.: 153, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 153 -1, // Configuration bit No.: 152, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 152 -1, // Configuration bit No.: 151, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 151 -1, // Configuration bit No.: 150, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 150 -1, // Configuration bit No.: 149, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 149 -0, // Configuration bit No.: 150, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 148 -0, // Configuration bit No.: 149, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 148 -1, // Configuration bit No.: 148, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 148 -1, // Configuration bit No.: 145, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 145 -0, // Configuration bit No.: 144, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 144 -1, // Configuration bit No.: 143, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 143 -1, // Configuration bit No.: 142, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 142 -1, // Configuration bit No.: 141, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 141 -1, // Configuration bit No.: 140, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 140 -1, // Configuration bit No.: 139, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 139 -1, // Configuration bit No.: 138, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 138 -1, // Configuration bit No.: 137, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 137 -1, // Configuration bit No.: 136, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 136 -1, // Configuration bit No.: 135, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 135 -1, // Configuration bit No.: 134, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 134 -1, // Configuration bit No.: 133, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 133 -1, // Configuration bit No.: 132, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 132 -0, // Configuration bit No.: 133, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 131 -0, // Configuration bit No.: 132, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 131 -1, // Configuration bit No.: 131, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 131 -1, // Configuration bit No.: 128, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 128 -1, // Configuration bit No.: 127, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 127 -1, // Configuration bit No.: 126, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 126 -1, // Configuration bit No.: 125, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 125 -1, // Configuration bit No.: 124, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 124 -1, // Configuration bit No.: 123, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 123 -1, // Configuration bit No.: 122, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 122 -1, // Configuration bit No.: 121, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 121 -1, // Configuration bit No.: 120, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 120 -1, // Configuration bit No.: 119, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 119 -1, // Configuration bit No.: 118, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 118 -1, // Configuration bit No.: 117, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 117 -0, // Configuration bit No.: 118, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 116 -0, // Configuration bit No.: 117, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 116 -1, // Configuration bit No.: 116, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 116 -0, // Configuration bit No.: 115, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 113 -0, // Configuration bit No.: 114, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 113 -1, // Configuration bit No.: 113, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 113 -0, // Configuration bit No.: 112, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 110 -0, // Configuration bit No.: 111, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 110 -1, // Configuration bit No.: 110, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 110 -1, // Configuration bit No.: 107, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 107 -1, // Configuration bit No.: 106, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 106 -1, // Configuration bit No.: 105, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 105 -1, // Configuration bit No.: 104, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 104 -1, // Configuration bit No.: 103, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 103 -1, // Configuration bit No.: 102, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 102 -1, // Configuration bit No.: 101, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 101 -1, // Configuration bit No.: 100, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 100 -1, // Configuration bit No.: 99, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 99 -1, // Configuration bit No.: 98, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 98 -1, // Configuration bit No.: 97, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 97 -1, // Configuration bit No.: 96, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 96 -1, // Configuration bit No.: 95, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 95 -1, // Configuration bit No.: 94, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 94 -0, // Configuration bit No.: 95, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 93 -0, // Configuration bit No.: 94, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 93 -1, // Configuration bit No.: 93, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 93 -1, // Configuration bit No.: 90, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 90 -1, // Configuration bit No.: 89, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 89 -1, // Configuration bit No.: 88, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 88 -1, // Configuration bit No.: 87, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 87 -1, // Configuration bit No.: 86, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 86 -1, // Configuration bit No.: 85, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 85 -1, // Configuration bit No.: 84, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 84 -1, // Configuration bit No.: 83, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 83 -1, // Configuration bit No.: 82, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 82 -1, // Configuration bit No.: 81, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 81 -1, // Configuration bit No.: 80, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 80 -1, // Configuration bit No.: 79, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 79 -1, // Configuration bit No.: 78, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 78 -1, // Configuration bit No.: 77, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 77 -0, // Configuration bit No.: 78, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 76 -0, // Configuration bit No.: 77, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 76 -1, // Configuration bit No.: 76, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 76 -1, // Configuration bit No.: 73, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 73 -1, // Configuration bit No.: 72, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 72 -1, // Configuration bit No.: 71, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 71 -1, // Configuration bit No.: 70, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 70 -1, // Configuration bit No.: 69, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 69 -1, // Configuration bit No.: 68, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 68 -0, // Configuration bit No.: 67, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 67 -1, // Configuration bit No.: 66, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 66 -1, // Configuration bit No.: 65, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 65 -1, // Configuration bit No.: 64, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 64 -1, // Configuration bit No.: 63, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 63 -1, // Configuration bit No.: 62, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 62 -1, // Configuration bit No.: 61, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 61 -1, // Configuration bit No.: 60, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 60 -1, // Configuration bit No.: 59, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 59 -1, // Configuration bit No.: 58, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 58 -1, // Configuration bit No.: 57, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 57 -1, // Configuration bit No.: 56, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 56 -1, // Configuration bit No.: 55, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 55 -1, // Configuration bit No.: 54, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 54 -1, // Configuration bit No.: 53, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 53 -1, // Configuration bit No.: 52, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 52 -1, // Configuration bit No.: 51, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 51 -1, // Configuration bit No.: 50, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 50 -1, // Configuration bit No.: 49, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 49 -1, // Configuration bit No.: 48, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 48 -1, // Configuration bit No.: 47, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 47 -1, // Configuration bit No.: 46, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 46 -1, // Configuration bit No.: 45, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 45 -1, // Configuration bit No.: 44, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 44 -1, // Configuration bit No.: 43, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 43 -1, // Configuration bit No.: 42, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 42 -0, // Configuration bit No.: 46, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 41 -0, // Configuration bit No.: 45, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 41 -1, // Configuration bit No.: 44, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 41 -0, // Configuration bit No.: 43, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 41 -0, // Configuration bit No.: 42, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 41 -1, // Configuration bit No.: 41, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 41 -0, // Configuration bit No.: 40, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 35 -0, // Configuration bit No.: 39, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 35 -1, // Configuration bit No.: 38, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 35 -0, // Configuration bit No.: 37, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 35 -0, // Configuration bit No.: 36, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 35 -1, // Configuration bit No.: 35, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 35 -0, // Configuration bit No.: 34, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 29 -0, // Configuration bit No.: 33, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 29 -1, // Configuration bit No.: 32, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 29 -0, // Configuration bit No.: 31, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 29 -0, // Configuration bit No.: 30, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 29 -1, // Configuration bit No.: 29, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 29 -0, // Configuration bit No.: 28, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 23 -0, // Configuration bit No.: 27, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 23 -1, // Configuration bit No.: 26, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 23 -0, // Configuration bit No.: 25, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 23 -1, // Configuration bit No.: 24, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 23 -0, // Configuration bit No.: 23, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 23 -1, // Configuration bit No.: 17, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 17 -1, // Configuration bit No.: 31, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16 -0, // Configuration bit No.: 30, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16 -1, // Configuration bit No.: 29, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16 -0, // Configuration bit No.: 28, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16 -1, // Configuration bit No.: 27, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16 -0, // Configuration bit No.: 26, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16 -1, // Configuration bit No.: 25, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16 -0, // Configuration bit No.: 24, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16 -1, // Configuration bit No.: 23, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16 -0, // Configuration bit No.: 22, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16 -1, // Configuration bit No.: 21, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16 -0, // Configuration bit No.: 20, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16 -1, // Configuration bit No.: 19, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16 -0, // Configuration bit No.: 18, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16 -1, // Configuration bit No.: 17, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 16 -0, // Configuration bit No.: 16, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 16 diff --git a/examples/spice_test_example_1/grid_tb/example_1_grid1_1_grid_testbench.sp b/examples/spice_test_example_1/grid_tb/example_1_grid1_1_grid_testbench.sp deleted file mode 100644 index 2a45de2c4..000000000 --- a/examples/spice_test_example_1/grid_tb/example_1_grid1_1_grid_testbench.sp +++ /dev/null @@ -1,177 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA Grid Testbench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -****** Include subckt netlists: Look-Up Tables (LUTs) ***** -.include './spice_test_example_1/subckt/luts.sp' -****** Include subckt netlists: Grid[1][1] ***** -.include './spice_test_example_1/subckt/grid_1_1.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_local_interc gvdd_io gvdd_hardlogic -.global gvdd_sram_local_routing -.global gvdd_sram_luts -.global gvdd_sram_io -***** Global VDD ports of Look-Up Table ***** -.global -+ gvdd_lut4[0] - -***** Global VDD ports of Flip-flop ***** -.global -+ gvdd_dff[0] - -***** Global VDD ports of iopad ***** - -***** Global VDD ports of hard_logic ***** - -Xgrid[1][1] -+ grid[1][1]_pin[0][0][0] -+ grid[1][1]_pin[0][0][4] -+ grid[1][1]_pin[0][1][1] -+ grid[1][1]_pin[0][1][5] -+ grid[1][1]_pin[0][2][2] -+ grid[1][1]_pin[0][3][3] -+ gvdd 0 grid[1][1] -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -Vgvdd_local_interc gvdd_local_interc 0 vsp -Vgvdd_sram_luts gvdd_sram_luts 0 vsp -Vgvdd_sram_local_routing gvdd_sram_local_routing 0 vsp -Vgvdd_sram_io gvdd_sram_io 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** Global VDD for Hard Logics ***** -***** Global VDD for Look-Up Tables (LUTs) ***** -Vgvdd_lut4[0] gvdd_lut4[0] 0 vsp -Rgvdd_lut4[0]_huge gvdd_lut4[0] 0 'vsp/10e-15' -***** Global VDD for Flip-flops (FFs) ***** -Vgvdd_dff[0] gvdd_dff[0] 0 vsp -Rgvdd_dff[0]_huge gvdd_dff[0] 0 'vsp/10e-15' -Vgrid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0] 0 -+ 0 -Xgrid[1][1]_pin[0][0][4]_inv[0] grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][4]_inv[1] grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][4]_inv[2] grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][4]_inv[3] grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[3] gvdd_load 0 inv size=1 -Vgrid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1] 0 -+ 0 -Vgrid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5] 0 -+ 0 -Vgrid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2] 0 -+ 0 -Vgrid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.measure tran leakage_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from=0 to='clock_period' -.measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period' -.measure tran leakage_power_local_routing avg p(Vgvdd_local_interc) from=0 to='clock_period' -.measure tran leakage_power_lut4[0] avg p(Vgvdd_lut4[0]) from=0 to='clock_period' -.measure tran leakage_power_lut4[0to0] -+ param = 'leakage_power_lut4[0]' -.measure tran total_leakage_power_lut4 -+ param = 'leakage_power_lut4[0to0]' -.measure tran leakage_power_dff[0] avg p(Vgvdd_dff[0]) from=0 to='clock_period' -.measure tran leakage_power_dff[0to0] -+ param = 'leakage_power_dff[0]' -.measure tran total_leakage_power_dff -+ param = 'leakage_power_dff[0to0]' -.measure tran dynamic_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from='clock_period' to='7*clock_period' -.measure tran total_energy_per_cycle_sram_local_routing param='dynamic_power_sram_local_routing*clock_period' -.measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='7*clock_period' -.measure tran total_energy_per_cycle_sram_luts param='dynamic_power_sram_luts*clock_period' -.measure tran dynamic_power_local_interc avg p(Vgvdd_local_interc) from='clock_period' to='7*clock_period' -.measure tran total_energy_per_cycle_local_routing param='dynamic_power_local_interc*clock_period' -.measure tran dynamic_power_lut4[0] avg p(Vgvdd_lut4[0]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_lut4[0to0] -+ param = 'dynamic_power_lut4[0]' -.measure tran total_dynamic_power_lut4 -+ param = 'dynamic_power_lut4[0to0]' -.measure tran total_energy_per_cycle_lut4 -+ param = 'dynamic_power_lut4[0to0]*clock_period' -.measure tran dynamic_power_dff[0] avg p(Vgvdd_dff[0]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_dff[0to0] -+ param = 'dynamic_power_dff[0]' -.measure tran total_dynamic_power_dff -+ param = 'dynamic_power_dff[0to0]' -.measure tran total_energy_per_cycle_dff -+ param = 'dynamic_power_dff[0to0]*clock_period' -.end diff --git a/examples/spice_test_example_1/hardlogic_tb/example_1_grid1_1_hardlogic_testbench.sp b/examples/spice_test_example_1/hardlogic_tb/example_1_grid1_1_hardlogic_testbench.sp deleted file mode 100644 index cef5a37ea..000000000 --- a/examples/spice_test_example_1/hardlogic_tb/example_1_grid1_1_hardlogic_testbench.sp +++ /dev/null @@ -1,130 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA Hard Logic Testbench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_load -***** Global VDD ports of Flip-flop ***** -.global -+ gvdd_dff[0] - -***** Global VDD ports of hard_logic ***** - -***** Global VDD ports of iopad ***** - -.global gvdd_sram_io -***** Hardlogic[1]: logical_block_index[3], gvdd_index[0]***** -Xhardlogic_dff[0] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[0]->D[0] -+ hardlogic_dff[0]->Q[0] -+ gvdd_dff[0] ggnd -+ static_dff -Vhardlogic_dff[0]->D[0] hardlogic_dff[0]->D[0] 0 -+ pulse(vsp 0 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*20.1096*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '20.1096*clock_period') -Xload_inv[0]_no0 hardlogic_dff[0]->Q[0] hardlogic_dff[0]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** Global VDD for FFs ***** -Vgvdd_dff[0] gvdd_dff[0] 0 vsp -Rgvdd_dff[0]_huge gvdd_dff[0] 0 'vsp/10e-15' -***** Global VDD for Hardlogics ***** -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.measure tran leakage_power_dff[0] avg p(Vgvdd_dff[0]) from=0 to='clock_period' -.measure tran leakage_power_dff[0to0] -+ param = 'leakage_power_dff[0]' -.measure tran total_leakage_power_dff -+ param = 'leakage_power_dff[0to0]' -.measure tran dynamic_power_dff[0] avg p(Vgvdd_dff[0]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_dff[0to0] -+ param = 'dynamic_power_dff[0]' -.measure tran total_dynamic_power_dff -+ param = 'dynamic_power_dff[0to0]' -.measure tran total_energy_per_cycle_dff -+ param = 'dynamic_power_dff[0to0]*clock_period' -.end diff --git a/examples/spice_test_example_1/include/design_params.sp b/examples/spice_test_example_1/include/design_params.sp deleted file mode 100644 index eccbea2ad..000000000 --- a/examples/spice_test_example_1/include/design_params.sp +++ /dev/null @@ -1,73 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Parameters for Circuit Designs * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Technology Library ****** -.lib '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/subvt_fpga/process/tsmc40nm/toplevel.l' TOP_TT -****** Transistor Parameters ****** -.param beta=2 -.param nl=4e-08 -.param wn=1.4e-07 -.param pl=4e-08 -.param wp=1.4e-07 -.param io_nl=2.7e-07 -.param io_wn=3.2e-07 -.param io_pl=2.7e-07 -.param io_wp=3.2e-07 -.param vsp=0.9 -.param io_vsp=2.5 -***** Parameters for Circuits ***** -***** Parameters for SPICE MODEL: INVTX1 ***** -***** Parameters for SPICE MODEL: buf4 ***** -***** Parameters for SPICE MODEL: tap_buf4 ***** -***** Parameters for SPICE MODEL: TGATE ***** -***** Parameters for SPICE MODEL: chan_segment ***** -.param chan_segment_wire_param_res_val=101 -.param chan_segment_wire_param_cap_val=2.25e-14 -***** Parameters for SPICE MODEL: direct_interc ***** -.param direct_interc_wire_param_res_val=0 -.param direct_interc_wire_param_cap_val=0 -***** Parameters for SPICE MODEL: mux_1level_tapbuf ***** -.param mux_1level_tapbuf_input_buf_size=1 -.param mux_1level_tapbuf_output_buf_size=1 -.param mux_1level_tapbuf_pgl_pmos_size=2 -.param mux_1level_tapbuf_pgl_nmos_size=1 -***** Parameters for SPICE MODEL: mux_2level ***** -.param mux_2level_input_buf_size=1 -.param mux_2level_output_buf_size=1 -.param mux_2level_pgl_pmos_size=2 -.param mux_2level_pgl_nmos_size=1 -***** Parameters for SPICE MODEL: mux_2level_tapbuf ***** -.param mux_2level_tapbuf_input_buf_size=1 -.param mux_2level_tapbuf_output_buf_size=1 -.param mux_2level_tapbuf_pgl_pmos_size=2 -.param mux_2level_tapbuf_pgl_nmos_size=1 -***** Parameters for SPICE MODEL: static_dff ***** -.param static_dff_input_buf_size=1 -.param static_dff_output_buf_size=1 -.param static_dff_pgl_pmos_size=1.41483e-38 -.param static_dff_pgl_nmos_size=0 -***** Parameters for SPICE MODEL: lut4 ***** -.param lut4_input_buf_size=1 -.param lut4_output_buf_size=1 -.param lut4_pgl_pmos_size=2 -.param lut4_pgl_nmos_size=1 -***** Parameters for SPICE MODEL: sram6T ***** -.param sram6T_input_buf_size=1 -.param sram6T_output_buf_size=1 -.param sram6T_pgl_pmos_size=1.41552e-38 -.param sram6T_pgl_nmos_size=0 -***** Parameters for SPICE MODEL: sram6T_blwl ***** -.param sram6T_blwl_input_buf_size=1 -.param sram6T_blwl_output_buf_size=1 -.param sram6T_blwl_pgl_pmos_size=1.41575e-38 -.param sram6T_blwl_pgl_nmos_size=0 -***** Parameters for SPICE MODEL: iopad ***** -.param iopad_input_buf_size=1 -.param iopad_output_buf_size=1 -.param iopad_pgl_pmos_size=1.41608e-38 -.param iopad_pgl_nmos_size=0 diff --git a/examples/spice_test_example_1/include/meas_params.sp b/examples/spice_test_example_1/include/meas_params.sp deleted file mode 100644 index 2c7879d02..000000000 --- a/examples/spice_test_example_1/include/meas_params.sp +++ /dev/null @@ -1,22 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Parameters for measurement * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Parameters For Slew Measurement ***** -***** Rising Edge ***** -.param slew_upper_thres_pct_rise=0.95 -.param slew_lower_thres_pct_rise=0.05 -***** Falling Edge ***** -.param slew_upper_thres_pct_fall=0.05 -.param slew_lower_thres_pct_fall=0.95 -***** Parameters For Delay Measurement ***** -***** Rising Edge ***** -.param input_thres_pct_rise=0.5 -.param output_thres_pct_rise=0.5 -***** Falling Edge ***** -.param input_thres_pct_fall=0.5 -.param output_thres_pct_fall=0.5 diff --git a/examples/spice_test_example_1/include/stimulate_params.sp b/examples/spice_test_example_1/include/stimulate_params.sp deleted file mode 100644 index c3a8951eb..000000000 --- a/examples/spice_test_example_1/include/stimulate_params.sp +++ /dev/null @@ -1,17 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Parameters for Stimulations * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Frequency ***** -.param clock_period=4.68274e-10 -***** Parameters For Input Stimulations ***** -.param input_slew_pct_rise='2.5e-11/clock_period' -.param input_slew_pct_fall='2.5e-11/clock_period' -***** Parameters For Clock Stimulations ***** -***** Slew ***** -.param clock_slew_pct_rise='2e-11/clock_period' -.param clock_slew_pct_fall='2e-11/clock_period' diff --git a/examples/spice_test_example_1/lut_tb/example_1_grid1_1_lut_testbench.sp b/examples/spice_test_example_1/lut_tb/example_1_grid1_1_lut_testbench.sp deleted file mode 100644 index 00cb6ec8f..000000000 --- a/examples/spice_test_example_1/lut_tb/example_1_grid1_1_lut_testbench.sp +++ /dev/null @@ -1,133 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA LUT Testbench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -****** Include subckt netlists: Look-Up Tables (LUTs) ***** -.include './spice_test_example_1/subckt/luts.sp' -****** Include subckt netlists: Grid[1][1] ***** -.include './spice_test_example_1/subckt/grid_1_1.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_luts -.global gvdd_load -***** Global VDD ports of Look-Up Table ***** -.global -+ gvdd_lut4[0] - -***** LUT[0]: logical_block_index[4], gvdd_index[0]***** -Xlut[0] lut[0]->in[0] lut[0]->in[1] lut[0]->in[2] lut[0]->in[3] lut[0]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_lut4[0] -Vlut[0]->in[0] lut[0]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vlut[0]->in[1] lut[0]->in[1] 0 -+ 0 -Vlut[0]->in[2] lut[0]->in[2] 0 -+ 0 -Vlut[0]->in[3] lut[0]->in[3] 0 -+ 0 -Xload_inv[0]_no0 lut[0]->out lut[0]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 lut[0]->out lut[0]->out_out[1] gvdd_load 0 inv size=1 -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for LUTs SRAMs ***** -Vgvdd_sram_luts gvdd_sram_luts 0 vsp -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** Global VDD for Look-Up Tables (LUTs) ***** -Vgvdd_lut4[0] gvdd_lut4[0] 0 vsp -Rgvdd_lut4[0]_huge gvdd_lut4[0] 0 'vsp/10e-15' -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period' -.measure tran leakage_power_lut4[0] avg p(Vgvdd_lut4[0]) from=0 to='clock_period' -.measure tran leakage_power_lut4[0to0] -+ param = 'leakage_power_lut4[0]' -.measure tran total_leakage_power_lut4 -+ param = 'leakage_power_lut4[0to0]' -.measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='7*clock_period' -.measure tran energy_per_cycle_sram_luts param='dynamic_power_sram_luts*clock_period' -.measure tran dynamic_power_lut4[0] avg p(Vgvdd_lut4[0]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_lut4[0to0] -+ param = 'dynamic_power_lut4[0]' -.measure tran total_dynamic_power_lut4 -+ param = 'dynamic_power_lut4[0to0]' -.measure tran total_energy_per_cycle_lut4 -+ param = 'dynamic_power_lut4[0to0]*clock_period' -.end diff --git a/examples/spice_test_example_1/pb_mux_tb/example_1_grid1_1_pbmux_testbench.sp b/examples/spice_test_example_1/pb_mux_tb/example_1_grid1_1_pbmux_testbench.sp deleted file mode 100644 index dfed45400..000000000 --- a/examples/spice_test_example_1/pb_mux_tb/example_1_grid1_1_pbmux_testbench.sp +++ /dev/null @@ -1,458 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_2level_size5[0] mux_2level_size5[0]->in[0] mux_2level_size5[0]->in[1] mux_2level_size5[0]->in[2] mux_2level_size5[0]->in[3] mux_2level_size5[0]->in[4] mux_2level_size5[0]->out sram[0]->out sram[0]->outb sram[1]->outb sram[1]->out sram[2]->out sram[2]->outb sram[3]->outb sram[3]->out sram[4]->out sram[4]->outb sram[5]->out sram[5]->outb gvdd_mux_2level_size5[0] 0 mux_2level_size5 -***** SRAM bits for MUX[0], level=2, select_path_id=3. ***** -*****010100***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -***** Signal mux_2level_size5[0]->in[0] density = 0, probability=0.***** -Vmux_2level_size5[0]->in[0] mux_2level_size5[0]->in[0] 0 -+ 0 -***** Signal mux_2level_size5[0]->in[1] density = 0, probability=0.***** -Vmux_2level_size5[0]->in[1] mux_2level_size5[0]->in[1] 0 -+ 0 -***** Signal mux_2level_size5[0]->in[2] density = 0, probability=0.***** -Vmux_2level_size5[0]->in[2] mux_2level_size5[0]->in[2] 0 -+ 0 -***** Signal mux_2level_size5[0]->in[3] density = 0.1906, probability=0.4782.***** -Vmux_2level_size5[0]->in[3] mux_2level_size5[0]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_2level_size5[0]->in[4] density = 0.1906, probability=0.5218.***** -Vmux_2level_size5[0]->in[4] mux_2level_size5[0]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_2level_size5[0] gvdd_mux_2level_size5[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar trig v(mux_2level_size5[0]->in[3]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size5[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar trig v(mux_2level_size5[0]->in[3]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size5[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar when v(mux_2level_size5[0]->in[3])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar trig v(mux_2level_size5[0]->in[3]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size5[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar when v(mux_2level_size5[0]->in[3])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar trig v(mux_2level_size5[0]->in[3]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size5[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size5[0]_leakage_power avg p(Vgvdd_mux_2level_size5[0]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar param='mux_2level_size5[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size5[0]_dynamic_power avg p(Vgvdd_mux_2level_size5[0]) from='clock_period' to='7*clock_period' -.meas tran mux_2level_size5[0]_energy_per_cycle param='mux_2level_size5[0]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar param='mux_2level_size5[0]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar avg p(Vgvdd_mux_2level_size5[0]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar avg p(Vgvdd_mux_2level_size5[0]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar' -Xload_inv[0]_no0 mux_2level_size5[0]->out mux_2level_size5[0]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to0] -+ param='leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to0] -+ param='energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[0]_crossbar' -Xmux_2level_size5[1] mux_2level_size5[1]->in[0] mux_2level_size5[1]->in[1] mux_2level_size5[1]->in[2] mux_2level_size5[1]->in[3] mux_2level_size5[1]->in[4] mux_2level_size5[1]->out sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb sram[8]->out sram[8]->outb sram[9]->outb sram[9]->out sram[10]->out sram[10]->outb sram[11]->out sram[11]->outb gvdd_mux_2level_size5[1] 0 mux_2level_size5 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****100100***** -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_2level_size5[1]->in[0] density = 0, probability=0.***** -Vmux_2level_size5[1]->in[0] mux_2level_size5[1]->in[0] 0 -+ 0 -***** Signal mux_2level_size5[1]->in[1] density = 0, probability=0.***** -Vmux_2level_size5[1]->in[1] mux_2level_size5[1]->in[1] 0 -+ 0 -***** Signal mux_2level_size5[1]->in[2] density = 0, probability=0.***** -Vmux_2level_size5[1]->in[2] mux_2level_size5[1]->in[2] 0 -+ 0 -***** Signal mux_2level_size5[1]->in[3] density = 0.1906, probability=0.4782.***** -Vmux_2level_size5[1]->in[3] mux_2level_size5[1]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_2level_size5[1]->in[4] density = 0.1906, probability=0.5218.***** -Vmux_2level_size5[1]->in[4] mux_2level_size5[1]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_2level_size5[1] gvdd_mux_2level_size5[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar trig v(mux_2level_size5[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size5[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar trig v(mux_2level_size5[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size5[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar when v(mux_2level_size5[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar trig v(mux_2level_size5[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size5[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar when v(mux_2level_size5[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar trig v(mux_2level_size5[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size5[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size5[1]_leakage_power avg p(Vgvdd_mux_2level_size5[1]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar param='mux_2level_size5[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size5[1]_dynamic_power avg p(Vgvdd_mux_2level_size5[1]) from='clock_period' to='7*clock_period' -.meas tran mux_2level_size5[1]_energy_per_cycle param='mux_2level_size5[1]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar param='mux_2level_size5[1]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar avg p(Vgvdd_mux_2level_size5[1]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar avg p(Vgvdd_mux_2level_size5[1]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar' -Xload_inv[1]_no0 mux_2level_size5[1]->out mux_2level_size5[1]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to1] -+ param='sum_leakage_power_pb_mux[0to0]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to1] -+ param='sum_energy_per_cycle_pb_mux[0to0]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[1]_crossbar' -Xmux_2level_size5[2] mux_2level_size5[2]->in[0] mux_2level_size5[2]->in[1] mux_2level_size5[2]->in[2] mux_2level_size5[2]->in[3] mux_2level_size5[2]->in[4] mux_2level_size5[2]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->out sram[14]->outb sram[15]->outb sram[15]->out sram[16]->out sram[16]->outb sram[17]->out sram[17]->outb gvdd_mux_2level_size5[2] 0 mux_2level_size5 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****100100***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -***** Signal mux_2level_size5[2]->in[0] density = 0, probability=0.***** -Vmux_2level_size5[2]->in[0] mux_2level_size5[2]->in[0] 0 -+ 0 -***** Signal mux_2level_size5[2]->in[1] density = 0, probability=0.***** -Vmux_2level_size5[2]->in[1] mux_2level_size5[2]->in[1] 0 -+ 0 -***** Signal mux_2level_size5[2]->in[2] density = 0, probability=0.***** -Vmux_2level_size5[2]->in[2] mux_2level_size5[2]->in[2] 0 -+ 0 -***** Signal mux_2level_size5[2]->in[3] density = 0.1906, probability=0.4782.***** -Vmux_2level_size5[2]->in[3] mux_2level_size5[2]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_2level_size5[2]->in[4] density = 0.1906, probability=0.5218.***** -Vmux_2level_size5[2]->in[4] mux_2level_size5[2]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_2level_size5[2] gvdd_mux_2level_size5[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar trig v(mux_2level_size5[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size5[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar trig v(mux_2level_size5[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size5[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar when v(mux_2level_size5[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar trig v(mux_2level_size5[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size5[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar when v(mux_2level_size5[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar trig v(mux_2level_size5[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size5[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size5[2]_leakage_power avg p(Vgvdd_mux_2level_size5[2]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar param='mux_2level_size5[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size5[2]_dynamic_power avg p(Vgvdd_mux_2level_size5[2]) from='clock_period' to='7*clock_period' -.meas tran mux_2level_size5[2]_energy_per_cycle param='mux_2level_size5[2]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar param='mux_2level_size5[2]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar avg p(Vgvdd_mux_2level_size5[2]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar avg p(Vgvdd_mux_2level_size5[2]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar' -Xload_inv[2]_no0 mux_2level_size5[2]->out mux_2level_size5[2]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to2] -+ param='sum_leakage_power_pb_mux[0to1]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to2] -+ param='sum_energy_per_cycle_pb_mux[0to1]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[2]_crossbar' -Xmux_2level_size5[3] mux_2level_size5[3]->in[0] mux_2level_size5[3]->in[1] mux_2level_size5[3]->in[2] mux_2level_size5[3]->in[3] mux_2level_size5[3]->in[4] mux_2level_size5[3]->out sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb sram[20]->out sram[20]->outb sram[21]->outb sram[21]->out sram[22]->out sram[22]->outb sram[23]->out sram[23]->outb gvdd_mux_2level_size5[3] 0 mux_2level_size5 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****100100***** -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_2level_size5[3]->in[0] density = 0, probability=0.***** -Vmux_2level_size5[3]->in[0] mux_2level_size5[3]->in[0] 0 -+ 0 -***** Signal mux_2level_size5[3]->in[1] density = 0, probability=0.***** -Vmux_2level_size5[3]->in[1] mux_2level_size5[3]->in[1] 0 -+ 0 -***** Signal mux_2level_size5[3]->in[2] density = 0, probability=0.***** -Vmux_2level_size5[3]->in[2] mux_2level_size5[3]->in[2] 0 -+ 0 -***** Signal mux_2level_size5[3]->in[3] density = 0.1906, probability=0.4782.***** -Vmux_2level_size5[3]->in[3] mux_2level_size5[3]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_2level_size5[3]->in[4] density = 0.1906, probability=0.5218.***** -Vmux_2level_size5[3]->in[4] mux_2level_size5[3]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_2level_size5[3] gvdd_mux_2level_size5[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar trig v(mux_2level_size5[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size5[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar trig v(mux_2level_size5[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size5[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar when v(mux_2level_size5[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar trig v(mux_2level_size5[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size5[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar when v(mux_2level_size5[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar trig v(mux_2level_size5[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size5[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size5[3]_leakage_power avg p(Vgvdd_mux_2level_size5[3]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar param='mux_2level_size5[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size5[3]_dynamic_power avg p(Vgvdd_mux_2level_size5[3]) from='clock_period' to='7*clock_period' -.meas tran mux_2level_size5[3]_energy_per_cycle param='mux_2level_size5[3]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar param='mux_2level_size5[3]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar avg p(Vgvdd_mux_2level_size5[3]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar avg p(Vgvdd_mux_2level_size5[3]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar' -Xload_inv[3]_no0 mux_2level_size5[3]->out mux_2level_size5[3]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to3] -+ param='sum_leakage_power_pb_mux[0to2]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to3] -+ param='sum_energy_per_cycle_pb_mux[0to2]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_in[3]_crossbar' -Xmux_1level_tapbuf_size2[4] mux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->out sram[24]->outb sram[24]->out gvdd_mux_1level_tapbuf_size2[4] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****1***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -***** Signal mux_1level_tapbuf_size2[4]->in[0] density = 0.1906, probability=0.5218.***** -Vmux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_1level_tapbuf_size2[4]->in[1] density = 0.099455, probability=0.5218.***** -Vmux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->in[1] 0 -+ pulse(vsp 0 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*20.1096*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '20.1096*clock_period') -Vgvdd_mux_1level_tapbuf_size2[4] gvdd_mux_1level_tapbuf_size2[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 param='mux_1level_tapbuf_size2[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size2[4]_energy_per_cycle param='mux_1level_tapbuf_size2[4]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 param='mux_1level_tapbuf_size2[4]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1' -Xload_inv[4]_no0 mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 mux_1level_tapbuf_size2[4]->out load_inv[8]_out gvdd_load 0 inv size=1 -Xload_inv[9]_no0 mux_1level_tapbuf_size2[4]->out load_inv[9]_out gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_1level_tapbuf_size2[4]->out load_inv[10]_out gvdd_load 0 inv size=1 -Xload_inv[11]_no0 mux_1level_tapbuf_size2[4]->out load_inv[11]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to4] -+ param='sum_leakage_power_pb_mux[0to3]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to4] -+ param='sum_energy_per_cycle_pb_mux[0to3]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_out[0]_mux1' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='7*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to4]' -.meas tran total_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to4]' -.meas tran total_leakage_power_pb_mux -+ param='sum_leakage_power_pb_mux[0to4]' -.meas tran total_energy_per_cycle_pb_mux -+ param='sum_energy_per_cycle_pb_mux[0to4]' -.end diff --git a/examples/spice_test_example_1/run_hspice_sim.sh b/examples/spice_test_example_1/run_hspice_sim.sh deleted file mode 100644 index 7c9755d57..000000000 --- a/examples/spice_test_example_1/run_hspice_sim.sh +++ /dev/null @@ -1,64 +0,0 @@ -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 0 Finish, 21 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/top_tb/example_1_top.sp -o ./spice_test_example_1/results/example_1_top.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 1 Finish, 20 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/grid_tb/example_1_grid1_1_grid_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_grid_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 2 Finish, 19 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/hardlogic_tb/example_1_grid1_1_hardlogic_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_hardlogic_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 3 Finish, 18 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/lut_tb/example_1_grid1_1_lut_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_lut_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 4 Finish, 17 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb1_1_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_1_sb_testbench.lis -echo Number of clock cycles in simulation: 2 -echo Simulation progress: 5 Finish, 16 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb1_0_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_0_sb_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 6 Finish, 15 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb0_1_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_1_sb_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 7 Finish, 14 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/sb_tb/example_1_sb0_0_sb_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_0_sb_testbench.lis -echo Number of clock cycles in simulation: 2 -echo Simulation progress: 8 Finish, 13 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cby1_1_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cby1_1_cb_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 9 Finish, 12 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cby0_1_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cby0_1_cb_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 10 Finish, 11 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cbx1_1_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_1_cb_testbench.lis -echo Number of clock cycles in simulation: 2 -echo Simulation progress: 11 Finish, 10 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/cb_tb/example_1_cbx1_0_cb_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_0_cb_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 12 Finish, 9 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb1_1_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_1_sbmux_testbench.lis -echo Number of clock cycles in simulation: 2 -echo Simulation progress: 13 Finish, 8 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb1_0_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb1_0_sbmux_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 14 Finish, 7 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb0_1_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_1_sbmux_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 15 Finish, 6 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/sb_mux_tb/example_1_sb0_0_sbmux_testbench.sp -o ./spice_test_example_1/results/example_1_sb0_0_sbmux_testbench.lis -echo Number of clock cycles in simulation: 2 -echo Simulation progress: 16 Finish, 5 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cby1_1_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cby1_1_cbmux_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 17 Finish, 4 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cby0_1_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cby0_1_cbmux_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 18 Finish, 3 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cbx1_1_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_1_cbmux_testbench.lis -echo Number of clock cycles in simulation: 2 -echo Simulation progress: 19 Finish, 2 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/cb_mux_tb/example_1_cbx1_0_cbmux_testbench.sp -o ./spice_test_example_1/results/example_1_cbx1_0_cbmux_testbench.lis -echo Number of clock cycles in simulation: 7 -echo Simulation progress: 20 Finish, 1 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_1/pb_mux_tb/example_1_grid1_1_pbmux_testbench.sp -o ./spice_test_example_1/results/example_1_grid1_1_pbmux_testbench.lis -echo Simulation progress: 21 Finish, 0 to go, total 21 diff --git a/examples/spice_test_example_1/sb_mux_tb/example_1_sb0_0_sbmux_testbench.sp b/examples/spice_test_example_1/sb_mux_tb/example_1_sb0_0_sbmux_testbench.sp deleted file mode 100644 index 449f04cef..000000000 --- a/examples/spice_test_example_1/sb_mux_tb/example_1_sb0_0_sbmux_testbench.sp +++ /dev/null @@ -1,1656 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_1level_tapbuf_size3[0] mux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb gvdd_mux_1level_tapbuf_size3[0] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[0], level=1, select_path_id=0. ***** -*****100***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -***** Signal mux_1level_tapbuf_size3[0]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[0] gvdd_mux_1level_tapbuf_size3[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[197] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[197] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[197] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[197] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[197] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[197] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[197] param='mux_1level_tapbuf_size3[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[0]_energy_per_cycle param='mux_1level_tapbuf_size3[0]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[197] param='mux_1level_tapbuf_size3[0]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[197] param='dynamic_power_sb_mux[0][0]_rrnode[197]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[197] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_rise_sb_mux[0][0]_rrnode[197]' to='start_rise_sb_mux[0][0]_rrnode[197]+switch_rise_sb_mux[0][0]_rrnode[197]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[197] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_fall_sb_mux[0][0]_rrnode[197]' to='start_fall_sb_mux[0][0]_rrnode[197]+switch_fall_sb_mux[0][0]_rrnode[197]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_sb_mux[0][0]_rrnode[197]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_sb_mux[0][0]_rrnode[197]' -***** Load for rr_node[197] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=0, type=5 ***** -Xchan_mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to0] -+ param='leakage_sb_mux[0][0]_rrnode[197]' -.meas tran sum_energy_per_cycle_sb_mux[0to0] -+ param='energy_per_cycle_sb_mux[0][0]_rrnode[197]' -Xmux_1level_tapbuf_size2[1] mux_1level_tapbuf_size2[1]->in[0] mux_1level_tapbuf_size2[1]->in[1] mux_1level_tapbuf_size2[1]->out sram[3]->outb sram[3]->out gvdd_mux_1level_tapbuf_size2[1] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[1], level=1, select_path_id=0. ***** -*****1***** -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -***** Signal mux_1level_tapbuf_size2[1]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[1]->in[0] mux_1level_tapbuf_size2[1]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[1]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[1]->in[1] mux_1level_tapbuf_size2[1]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[1] gvdd_mux_1level_tapbuf_size2[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[199] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[199] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[199] when v(mux_1level_tapbuf_size2[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[199] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[199] when v(mux_1level_tapbuf_size2[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[199] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[1]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[199] param='mux_1level_tapbuf_size2[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[1]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[1]_energy_per_cycle param='mux_1level_tapbuf_size2[1]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[199] param='mux_1level_tapbuf_size2[1]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[199] param='dynamic_power_sb_mux[0][0]_rrnode[199]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[199] avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='start_rise_sb_mux[0][0]_rrnode[199]' to='start_rise_sb_mux[0][0]_rrnode[199]+switch_rise_sb_mux[0][0]_rrnode[199]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[199] avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='start_fall_sb_mux[0][0]_rrnode[199]' to='start_fall_sb_mux[0][0]_rrnode[199]+switch_fall_sb_mux[0][0]_rrnode[199]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_sb_mux[0][0]_rrnode[199]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_sb_mux[0][0]_rrnode[199]' -***** Load for rr_node[199] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=2, type=5 ***** -Xchan_mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to1] -+ param='sum_leakage_power_sb_mux[0to0]+leakage_sb_mux[0][0]_rrnode[199]' -.meas tran sum_energy_per_cycle_sb_mux[0to1] -+ param='sum_energy_per_cycle_sb_mux[0to0]+energy_per_cycle_sb_mux[0][0]_rrnode[199]' -Xmux_1level_tapbuf_size2[2] mux_1level_tapbuf_size2[2]->in[0] mux_1level_tapbuf_size2[2]->in[1] mux_1level_tapbuf_size2[2]->out sram[4]->outb sram[4]->out gvdd_mux_1level_tapbuf_size2[2] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[2], level=1, select_path_id=0. ***** -*****1***** -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -***** Signal mux_1level_tapbuf_size2[2]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[2]->in[0] mux_1level_tapbuf_size2[2]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[2]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[2]->in[1] mux_1level_tapbuf_size2[2]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[2] gvdd_mux_1level_tapbuf_size2[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[201] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[201] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[201] when v(mux_1level_tapbuf_size2[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[201] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[201] when v(mux_1level_tapbuf_size2[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[201] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[2]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[201] param='mux_1level_tapbuf_size2[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[2]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[2]_energy_per_cycle param='mux_1level_tapbuf_size2[2]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[201] param='mux_1level_tapbuf_size2[2]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[201] param='dynamic_power_sb_mux[0][0]_rrnode[201]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[201] avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='start_rise_sb_mux[0][0]_rrnode[201]' to='start_rise_sb_mux[0][0]_rrnode[201]+switch_rise_sb_mux[0][0]_rrnode[201]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[201] avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='start_fall_sb_mux[0][0]_rrnode[201]' to='start_fall_sb_mux[0][0]_rrnode[201]+switch_fall_sb_mux[0][0]_rrnode[201]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_sb_mux[0][0]_rrnode[201]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_sb_mux[0][0]_rrnode[201]' -***** Load for rr_node[201] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=4, type=5 ***** -Xchan_mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[4]_no0 mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to2] -+ param='sum_leakage_power_sb_mux[0to1]+leakage_sb_mux[0][0]_rrnode[201]' -.meas tran sum_energy_per_cycle_sb_mux[0to2] -+ param='sum_energy_per_cycle_sb_mux[0to1]+energy_per_cycle_sb_mux[0][0]_rrnode[201]' -Xmux_1level_tapbuf_size2[3] mux_1level_tapbuf_size2[3]->in[0] mux_1level_tapbuf_size2[3]->in[1] mux_1level_tapbuf_size2[3]->out sram[5]->outb sram[5]->out gvdd_mux_1level_tapbuf_size2[3] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[3], level=1, select_path_id=0. ***** -*****1***** -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -***** Signal mux_1level_tapbuf_size2[3]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[3]->in[0] mux_1level_tapbuf_size2[3]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[3]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[3]->in[1] mux_1level_tapbuf_size2[3]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[3] gvdd_mux_1level_tapbuf_size2[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[203] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[203] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[203] when v(mux_1level_tapbuf_size2[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[203] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[203] when v(mux_1level_tapbuf_size2[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[203] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[3]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[203] param='mux_1level_tapbuf_size2[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[3]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[3]_energy_per_cycle param='mux_1level_tapbuf_size2[3]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[203] param='mux_1level_tapbuf_size2[3]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[203] param='dynamic_power_sb_mux[0][0]_rrnode[203]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[203] avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='start_rise_sb_mux[0][0]_rrnode[203]' to='start_rise_sb_mux[0][0]_rrnode[203]+switch_rise_sb_mux[0][0]_rrnode[203]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[203] avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='start_fall_sb_mux[0][0]_rrnode[203]' to='start_fall_sb_mux[0][0]_rrnode[203]+switch_fall_sb_mux[0][0]_rrnode[203]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_sb_mux[0][0]_rrnode[203]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_sb_mux[0][0]_rrnode[203]' -***** Load for rr_node[203] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=6, type=5 ***** -Xchan_mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[6]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to3] -+ param='sum_leakage_power_sb_mux[0to2]+leakage_sb_mux[0][0]_rrnode[203]' -.meas tran sum_energy_per_cycle_sb_mux[0to3] -+ param='sum_energy_per_cycle_sb_mux[0to2]+energy_per_cycle_sb_mux[0][0]_rrnode[203]' -Xmux_1level_tapbuf_size2[4] mux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->out sram[6]->outb sram[6]->out gvdd_mux_1level_tapbuf_size2[4] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****1***** -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -***** Signal mux_1level_tapbuf_size2[4]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[4]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[4] gvdd_mux_1level_tapbuf_size2[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[205] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[205] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[205] when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[205] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[205] when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[205] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[205] param='mux_1level_tapbuf_size2[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[4]_energy_per_cycle param='mux_1level_tapbuf_size2[4]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[205] param='mux_1level_tapbuf_size2[4]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[205] param='dynamic_power_sb_mux[0][0]_rrnode[205]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[205] avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_rise_sb_mux[0][0]_rrnode[205]' to='start_rise_sb_mux[0][0]_rrnode[205]+switch_rise_sb_mux[0][0]_rrnode[205]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[205] avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_fall_sb_mux[0][0]_rrnode[205]' to='start_fall_sb_mux[0][0]_rrnode[205]+switch_fall_sb_mux[0][0]_rrnode[205]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_sb_mux[0][0]_rrnode[205]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_sb_mux[0][0]_rrnode[205]' -***** Load for rr_node[205] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=8, type=5 ***** -Xchan_mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[9]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to4] -+ param='sum_leakage_power_sb_mux[0to3]+leakage_sb_mux[0][0]_rrnode[205]' -.meas tran sum_energy_per_cycle_sb_mux[0to4] -+ param='sum_energy_per_cycle_sb_mux[0to3]+energy_per_cycle_sb_mux[0][0]_rrnode[205]' -Xmux_1level_tapbuf_size2[5] mux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->out sram[7]->outb sram[7]->out gvdd_mux_1level_tapbuf_size2[5] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[5], level=1, select_path_id=0. ***** -*****1***** -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_1level_tapbuf_size2[5]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[5]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[5] gvdd_mux_1level_tapbuf_size2[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[207] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[207] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[207] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[207] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[207] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[207] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[207] param='mux_1level_tapbuf_size2[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[5]_energy_per_cycle param='mux_1level_tapbuf_size2[5]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[207] param='mux_1level_tapbuf_size2[5]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[207] param='dynamic_power_sb_mux[0][0]_rrnode[207]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[207] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_rise_sb_mux[0][0]_rrnode[207]' to='start_rise_sb_mux[0][0]_rrnode[207]+switch_rise_sb_mux[0][0]_rrnode[207]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[207] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_fall_sb_mux[0][0]_rrnode[207]' to='start_fall_sb_mux[0][0]_rrnode[207]+switch_fall_sb_mux[0][0]_rrnode[207]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_sb_mux[0][0]_rrnode[207]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_sb_mux[0][0]_rrnode[207]' -***** Load for rr_node[207] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=10, type=5 ***** -Xchan_mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[11]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to5] -+ param='sum_leakage_power_sb_mux[0to4]+leakage_sb_mux[0][0]_rrnode[207]' -.meas tran sum_energy_per_cycle_sb_mux[0to5] -+ param='sum_energy_per_cycle_sb_mux[0to4]+energy_per_cycle_sb_mux[0][0]_rrnode[207]' -Xmux_1level_tapbuf_size2[6] mux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->out sram[8]->outb sram[8]->out gvdd_mux_1level_tapbuf_size2[6] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[6], level=1, select_path_id=0. ***** -*****1***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -***** Signal mux_1level_tapbuf_size2[6]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[6]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[6] gvdd_mux_1level_tapbuf_size2[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[209] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[209] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[209] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[209] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[209] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[209] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[209] param='mux_1level_tapbuf_size2[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[6]_energy_per_cycle param='mux_1level_tapbuf_size2[6]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[209] param='mux_1level_tapbuf_size2[6]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[209] param='dynamic_power_sb_mux[0][0]_rrnode[209]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[209] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_rise_sb_mux[0][0]_rrnode[209]' to='start_rise_sb_mux[0][0]_rrnode[209]+switch_rise_sb_mux[0][0]_rrnode[209]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[209] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_fall_sb_mux[0][0]_rrnode[209]' to='start_fall_sb_mux[0][0]_rrnode[209]+switch_fall_sb_mux[0][0]_rrnode[209]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_sb_mux[0][0]_rrnode[209]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_sb_mux[0][0]_rrnode[209]' -***** Load for rr_node[209] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=12, type=5 ***** -Xchan_mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[14]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to6] -+ param='sum_leakage_power_sb_mux[0to5]+leakage_sb_mux[0][0]_rrnode[209]' -.meas tran sum_energy_per_cycle_sb_mux[0to6] -+ param='sum_energy_per_cycle_sb_mux[0to5]+energy_per_cycle_sb_mux[0][0]_rrnode[209]' -Xmux_1level_tapbuf_size2[7] mux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->out sram[9]->outb sram[9]->out gvdd_mux_1level_tapbuf_size2[7] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[7], level=1, select_path_id=0. ***** -*****1***** -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -***** Signal mux_1level_tapbuf_size2[7]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[7]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[7] gvdd_mux_1level_tapbuf_size2[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[211] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[211] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[211] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[211] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[211] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[211] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[211] param='mux_1level_tapbuf_size2[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[7]_energy_per_cycle param='mux_1level_tapbuf_size2[7]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[211] param='mux_1level_tapbuf_size2[7]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[211] param='dynamic_power_sb_mux[0][0]_rrnode[211]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[211] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_rise_sb_mux[0][0]_rrnode[211]' to='start_rise_sb_mux[0][0]_rrnode[211]+switch_rise_sb_mux[0][0]_rrnode[211]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[211] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_fall_sb_mux[0][0]_rrnode[211]' to='start_fall_sb_mux[0][0]_rrnode[211]+switch_fall_sb_mux[0][0]_rrnode[211]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_sb_mux[0][0]_rrnode[211]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_sb_mux[0][0]_rrnode[211]' -***** Load for rr_node[211] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=14, type=5 ***** -Xchan_mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[16]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to7] -+ param='sum_leakage_power_sb_mux[0to6]+leakage_sb_mux[0][0]_rrnode[211]' -.meas tran sum_energy_per_cycle_sb_mux[0to7] -+ param='sum_energy_per_cycle_sb_mux[0to6]+energy_per_cycle_sb_mux[0][0]_rrnode[211]' -Xmux_1level_tapbuf_size2[8] mux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->out sram[10]->outb sram[10]->out gvdd_mux_1level_tapbuf_size2[8] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[8], level=1, select_path_id=0. ***** -*****1***** -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -***** Signal mux_1level_tapbuf_size2[8]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[8]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[8] gvdd_mux_1level_tapbuf_size2[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[213] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[213] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[213] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[213] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[213] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[213] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[213] param='mux_1level_tapbuf_size2[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[8]_energy_per_cycle param='mux_1level_tapbuf_size2[8]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[213] param='mux_1level_tapbuf_size2[8]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[213] param='dynamic_power_sb_mux[0][0]_rrnode[213]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[213] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_rise_sb_mux[0][0]_rrnode[213]' to='start_rise_sb_mux[0][0]_rrnode[213]+switch_rise_sb_mux[0][0]_rrnode[213]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[213] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_fall_sb_mux[0][0]_rrnode[213]' to='start_fall_sb_mux[0][0]_rrnode[213]+switch_fall_sb_mux[0][0]_rrnode[213]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_sb_mux[0][0]_rrnode[213]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_sb_mux[0][0]_rrnode[213]' -***** Load for rr_node[213] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=16, type=5 ***** -Xchan_mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[18]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to8] -+ param='sum_leakage_power_sb_mux[0to7]+leakage_sb_mux[0][0]_rrnode[213]' -.meas tran sum_energy_per_cycle_sb_mux[0to8] -+ param='sum_energy_per_cycle_sb_mux[0to7]+energy_per_cycle_sb_mux[0][0]_rrnode[213]' -Xmux_1level_tapbuf_size2[9] mux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->out sram[11]->outb sram[11]->out gvdd_mux_1level_tapbuf_size2[9] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[9], level=1, select_path_id=0. ***** -*****1***** -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_1level_tapbuf_size2[9]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[9]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[9] gvdd_mux_1level_tapbuf_size2[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[215] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[215] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[215] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[215] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[215] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[215] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[215] param='mux_1level_tapbuf_size2[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[9]_energy_per_cycle param='mux_1level_tapbuf_size2[9]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[215] param='mux_1level_tapbuf_size2[9]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[215] param='dynamic_power_sb_mux[0][0]_rrnode[215]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[215] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_rise_sb_mux[0][0]_rrnode[215]' to='start_rise_sb_mux[0][0]_rrnode[215]+switch_rise_sb_mux[0][0]_rrnode[215]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[215] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_fall_sb_mux[0][0]_rrnode[215]' to='start_fall_sb_mux[0][0]_rrnode[215]+switch_fall_sb_mux[0][0]_rrnode[215]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_sb_mux[0][0]_rrnode[215]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_sb_mux[0][0]_rrnode[215]' -***** Load for rr_node[215] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=18, type=5 ***** -Xchan_mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[20]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to9] -+ param='sum_leakage_power_sb_mux[0to8]+leakage_sb_mux[0][0]_rrnode[215]' -.meas tran sum_energy_per_cycle_sb_mux[0to9] -+ param='sum_energy_per_cycle_sb_mux[0to8]+energy_per_cycle_sb_mux[0][0]_rrnode[215]' -Xmux_1level_tapbuf_size2[10] mux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->out sram[12]->outb sram[12]->out gvdd_mux_1level_tapbuf_size2[10] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[10], level=1, select_path_id=0. ***** -*****1***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -***** Signal mux_1level_tapbuf_size2[10]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[10]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[10] gvdd_mux_1level_tapbuf_size2[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[217] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[217] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[217] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[217] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[217] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[217] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[217] param='mux_1level_tapbuf_size2[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[10]_energy_per_cycle param='mux_1level_tapbuf_size2[10]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[217] param='mux_1level_tapbuf_size2[10]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[217] param='dynamic_power_sb_mux[0][0]_rrnode[217]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[217] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_rise_sb_mux[0][0]_rrnode[217]' to='start_rise_sb_mux[0][0]_rrnode[217]+switch_rise_sb_mux[0][0]_rrnode[217]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[217] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_fall_sb_mux[0][0]_rrnode[217]' to='start_fall_sb_mux[0][0]_rrnode[217]+switch_fall_sb_mux[0][0]_rrnode[217]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_sb_mux[0][0]_rrnode[217]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_sb_mux[0][0]_rrnode[217]' -***** Load for rr_node[217] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=20, type=5 ***** -Xchan_mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[22]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to10] -+ param='sum_leakage_power_sb_mux[0to9]+leakage_sb_mux[0][0]_rrnode[217]' -.meas tran sum_energy_per_cycle_sb_mux[0to10] -+ param='sum_energy_per_cycle_sb_mux[0to9]+energy_per_cycle_sb_mux[0][0]_rrnode[217]' -Xmux_1level_tapbuf_size2[11] mux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->out sram[13]->outb sram[13]->out gvdd_mux_1level_tapbuf_size2[11] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[11], level=1, select_path_id=0. ***** -*****1***** -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -***** Signal mux_1level_tapbuf_size2[11]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[11]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[11] gvdd_mux_1level_tapbuf_size2[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[219] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[219] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[219] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[219] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[219] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[219] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[219] param='mux_1level_tapbuf_size2[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[11]_energy_per_cycle param='mux_1level_tapbuf_size2[11]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[219] param='mux_1level_tapbuf_size2[11]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[219] param='dynamic_power_sb_mux[0][0]_rrnode[219]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[219] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_rise_sb_mux[0][0]_rrnode[219]' to='start_rise_sb_mux[0][0]_rrnode[219]+switch_rise_sb_mux[0][0]_rrnode[219]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[219] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_fall_sb_mux[0][0]_rrnode[219]' to='start_fall_sb_mux[0][0]_rrnode[219]+switch_fall_sb_mux[0][0]_rrnode[219]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_sb_mux[0][0]_rrnode[219]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_sb_mux[0][0]_rrnode[219]' -***** Load for rr_node[219] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=22, type=5 ***** -Xchan_mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[24]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to11] -+ param='sum_leakage_power_sb_mux[0to10]+leakage_sb_mux[0][0]_rrnode[219]' -.meas tran sum_energy_per_cycle_sb_mux[0to11] -+ param='sum_energy_per_cycle_sb_mux[0to10]+energy_per_cycle_sb_mux[0][0]_rrnode[219]' -Xmux_1level_tapbuf_size2[12] mux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->out sram[14]->outb sram[14]->out gvdd_mux_1level_tapbuf_size2[12] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[12], level=1, select_path_id=0. ***** -*****1***** -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -***** Signal mux_1level_tapbuf_size2[12]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[12]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[12] gvdd_mux_1level_tapbuf_size2[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[221] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[221] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[221] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[221] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[221] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[221] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[221] param='mux_1level_tapbuf_size2[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[12]_energy_per_cycle param='mux_1level_tapbuf_size2[12]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[221] param='mux_1level_tapbuf_size2[12]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[221] param='dynamic_power_sb_mux[0][0]_rrnode[221]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[221] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_rise_sb_mux[0][0]_rrnode[221]' to='start_rise_sb_mux[0][0]_rrnode[221]+switch_rise_sb_mux[0][0]_rrnode[221]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[221] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_fall_sb_mux[0][0]_rrnode[221]' to='start_fall_sb_mux[0][0]_rrnode[221]+switch_fall_sb_mux[0][0]_rrnode[221]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_sb_mux[0][0]_rrnode[221]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_sb_mux[0][0]_rrnode[221]' -***** Load for rr_node[221] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=24, type=5 ***** -Xchan_mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[26]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to12] -+ param='sum_leakage_power_sb_mux[0to11]+leakage_sb_mux[0][0]_rrnode[221]' -.meas tran sum_energy_per_cycle_sb_mux[0to12] -+ param='sum_energy_per_cycle_sb_mux[0to11]+energy_per_cycle_sb_mux[0][0]_rrnode[221]' -Xmux_1level_tapbuf_size2[13] mux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->out sram[15]->outb sram[15]->out gvdd_mux_1level_tapbuf_size2[13] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[13], level=1, select_path_id=0. ***** -*****1***** -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_1level_tapbuf_size2[13]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[13]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[13] gvdd_mux_1level_tapbuf_size2[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[223] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[223] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[223] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[223] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[223] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[223] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[223] param='mux_1level_tapbuf_size2[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[13]_energy_per_cycle param='mux_1level_tapbuf_size2[13]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[223] param='mux_1level_tapbuf_size2[13]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[223] param='dynamic_power_sb_mux[0][0]_rrnode[223]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[223] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_rise_sb_mux[0][0]_rrnode[223]' to='start_rise_sb_mux[0][0]_rrnode[223]+switch_rise_sb_mux[0][0]_rrnode[223]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[223] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_fall_sb_mux[0][0]_rrnode[223]' to='start_fall_sb_mux[0][0]_rrnode[223]+switch_fall_sb_mux[0][0]_rrnode[223]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_sb_mux[0][0]_rrnode[223]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_sb_mux[0][0]_rrnode[223]' -***** Load for rr_node[223] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=26, type=5 ***** -Xchan_mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[28]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to13] -+ param='sum_leakage_power_sb_mux[0to12]+leakage_sb_mux[0][0]_rrnode[223]' -.meas tran sum_energy_per_cycle_sb_mux[0to13] -+ param='sum_energy_per_cycle_sb_mux[0to12]+energy_per_cycle_sb_mux[0][0]_rrnode[223]' -Xmux_1level_tapbuf_size2[14] mux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->out sram[16]->outb sram[16]->out gvdd_mux_1level_tapbuf_size2[14] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[14], level=1, select_path_id=0. ***** -*****1***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -***** Signal mux_1level_tapbuf_size2[14]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[14]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[14] gvdd_mux_1level_tapbuf_size2[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[225] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[225] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[225] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[225] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[225] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[225] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[225] param='mux_1level_tapbuf_size2[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[14]_energy_per_cycle param='mux_1level_tapbuf_size2[14]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[225] param='mux_1level_tapbuf_size2[14]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[225] param='dynamic_power_sb_mux[0][0]_rrnode[225]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[225] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_rise_sb_mux[0][0]_rrnode[225]' to='start_rise_sb_mux[0][0]_rrnode[225]+switch_rise_sb_mux[0][0]_rrnode[225]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[225] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_fall_sb_mux[0][0]_rrnode[225]' to='start_fall_sb_mux[0][0]_rrnode[225]+switch_fall_sb_mux[0][0]_rrnode[225]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_sb_mux[0][0]_rrnode[225]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_sb_mux[0][0]_rrnode[225]' -***** Load for rr_node[225] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=28, type=5 ***** -Xchan_mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[31]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to14] -+ param='sum_leakage_power_sb_mux[0to13]+leakage_sb_mux[0][0]_rrnode[225]' -.meas tran sum_energy_per_cycle_sb_mux[0to14] -+ param='sum_energy_per_cycle_sb_mux[0to13]+energy_per_cycle_sb_mux[0][0]_rrnode[225]' -Xmux_1level_tapbuf_size3[15] mux_1level_tapbuf_size3[15]->in[0] mux_1level_tapbuf_size3[15]->in[1] mux_1level_tapbuf_size3[15]->in[2] mux_1level_tapbuf_size3[15]->out sram[17]->outb sram[17]->out sram[18]->out sram[18]->outb sram[19]->out sram[19]->outb gvdd_mux_1level_tapbuf_size3[15] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[15], level=1, select_path_id=0. ***** -*****100***** -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_1level_tapbuf_size3[15]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[15]->in[0] mux_1level_tapbuf_size3[15]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[15]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[15]->in[1] mux_1level_tapbuf_size3[15]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[15]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[15]->in[2] mux_1level_tapbuf_size3[15]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[15] gvdd_mux_1level_tapbuf_size3[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[137] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[137] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[137] when v(mux_1level_tapbuf_size3[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[137] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[137] when v(mux_1level_tapbuf_size3[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[137] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[15]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[137] param='mux_1level_tapbuf_size3[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[15]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[15]_energy_per_cycle param='mux_1level_tapbuf_size3[15]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[137] param='mux_1level_tapbuf_size3[15]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[137] param='dynamic_power_sb_mux[0][0]_rrnode[137]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[137] avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='start_rise_sb_mux[0][0]_rrnode[137]' to='start_rise_sb_mux[0][0]_rrnode[137]+switch_rise_sb_mux[0][0]_rrnode[137]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[137] avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='start_fall_sb_mux[0][0]_rrnode[137]' to='start_fall_sb_mux[0][0]_rrnode[137]+switch_fall_sb_mux[0][0]_rrnode[137]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_sb_mux[0][0]_rrnode[137]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_sb_mux[0][0]_rrnode[137]' -***** Load for rr_node[137] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=0, type=4 ***** -Xchan_mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[33]_no0 mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to15] -+ param='sum_leakage_power_sb_mux[0to14]+leakage_sb_mux[0][0]_rrnode[137]' -.meas tran sum_energy_per_cycle_sb_mux[0to15] -+ param='sum_energy_per_cycle_sb_mux[0to14]+energy_per_cycle_sb_mux[0][0]_rrnode[137]' -Xmux_1level_tapbuf_size2[16] mux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->out sram[20]->outb sram[20]->out gvdd_mux_1level_tapbuf_size2[16] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[16], level=1, select_path_id=0. ***** -*****1***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -***** Signal mux_1level_tapbuf_size2[16]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[16]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[16] gvdd_mux_1level_tapbuf_size2[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[139] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[139] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[139] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[139] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[139] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[139] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[139] param='mux_1level_tapbuf_size2[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[16]_energy_per_cycle param='mux_1level_tapbuf_size2[16]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[139] param='mux_1level_tapbuf_size2[16]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[139] param='dynamic_power_sb_mux[0][0]_rrnode[139]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[139] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_rise_sb_mux[0][0]_rrnode[139]' to='start_rise_sb_mux[0][0]_rrnode[139]+switch_rise_sb_mux[0][0]_rrnode[139]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[139] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_fall_sb_mux[0][0]_rrnode[139]' to='start_fall_sb_mux[0][0]_rrnode[139]+switch_fall_sb_mux[0][0]_rrnode[139]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_sb_mux[0][0]_rrnode[139]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_sb_mux[0][0]_rrnode[139]' -***** Load for rr_node[139] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=2, type=4 ***** -Xchan_mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[36]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to16] -+ param='sum_leakage_power_sb_mux[0to15]+leakage_sb_mux[0][0]_rrnode[139]' -.meas tran sum_energy_per_cycle_sb_mux[0to16] -+ param='sum_energy_per_cycle_sb_mux[0to15]+energy_per_cycle_sb_mux[0][0]_rrnode[139]' -Xmux_1level_tapbuf_size2[17] mux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->out sram[21]->outb sram[21]->out gvdd_mux_1level_tapbuf_size2[17] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[17], level=1, select_path_id=0. ***** -*****1***** -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -***** Signal mux_1level_tapbuf_size2[17]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[17]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[17] gvdd_mux_1level_tapbuf_size2[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[141] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[141] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[141] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[141] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[141] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[141] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[141] param='mux_1level_tapbuf_size2[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[17]_energy_per_cycle param='mux_1level_tapbuf_size2[17]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[141] param='mux_1level_tapbuf_size2[17]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[141] param='dynamic_power_sb_mux[0][0]_rrnode[141]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[141] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_rise_sb_mux[0][0]_rrnode[141]' to='start_rise_sb_mux[0][0]_rrnode[141]+switch_rise_sb_mux[0][0]_rrnode[141]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[141] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_fall_sb_mux[0][0]_rrnode[141]' to='start_fall_sb_mux[0][0]_rrnode[141]+switch_fall_sb_mux[0][0]_rrnode[141]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_sb_mux[0][0]_rrnode[141]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_sb_mux[0][0]_rrnode[141]' -***** Load for rr_node[141] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=4, type=4 ***** -Xchan_mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[38]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to17] -+ param='sum_leakage_power_sb_mux[0to16]+leakage_sb_mux[0][0]_rrnode[141]' -.meas tran sum_energy_per_cycle_sb_mux[0to17] -+ param='sum_energy_per_cycle_sb_mux[0to16]+energy_per_cycle_sb_mux[0][0]_rrnode[141]' -Xmux_1level_tapbuf_size2[18] mux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->out sram[22]->outb sram[22]->out gvdd_mux_1level_tapbuf_size2[18] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[18], level=1, select_path_id=0. ***** -*****1***** -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -***** Signal mux_1level_tapbuf_size2[18]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[18]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[18] gvdd_mux_1level_tapbuf_size2[18] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[143] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[143] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[143] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[143] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[143] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[143] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[143] param='mux_1level_tapbuf_size2[18]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[18]_energy_per_cycle param='mux_1level_tapbuf_size2[18]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[143] param='mux_1level_tapbuf_size2[18]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[143] param='dynamic_power_sb_mux[0][0]_rrnode[143]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[143] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_rise_sb_mux[0][0]_rrnode[143]' to='start_rise_sb_mux[0][0]_rrnode[143]+switch_rise_sb_mux[0][0]_rrnode[143]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[143] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_fall_sb_mux[0][0]_rrnode[143]' to='start_fall_sb_mux[0][0]_rrnode[143]+switch_fall_sb_mux[0][0]_rrnode[143]' -.meas tran sum_leakage_power_mux[0to18] -+ param='sum_leakage_power_mux[0to17]+leakage_sb_mux[0][0]_rrnode[143]' -.meas tran sum_energy_per_cycle_mux[0to18] -+ param='sum_energy_per_cycle_mux[0to17]+energy_per_cycle_sb_mux[0][0]_rrnode[143]' -***** Load for rr_node[143] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=6, type=4 ***** -Xchan_mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[40]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to18] -+ param='sum_leakage_power_sb_mux[0to17]+leakage_sb_mux[0][0]_rrnode[143]' -.meas tran sum_energy_per_cycle_sb_mux[0to18] -+ param='sum_energy_per_cycle_sb_mux[0to17]+energy_per_cycle_sb_mux[0][0]_rrnode[143]' -Xmux_1level_tapbuf_size2[19] mux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->out sram[23]->outb sram[23]->out gvdd_mux_1level_tapbuf_size2[19] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[19], level=1, select_path_id=0. ***** -*****1***** -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_1level_tapbuf_size2[19]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[19]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[19] gvdd_mux_1level_tapbuf_size2[19] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[145] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[145] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[145] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[145] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[145] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[145] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[145] param='mux_1level_tapbuf_size2[19]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[19]_energy_per_cycle param='mux_1level_tapbuf_size2[19]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[145] param='mux_1level_tapbuf_size2[19]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[145] param='dynamic_power_sb_mux[0][0]_rrnode[145]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[145] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_rise_sb_mux[0][0]_rrnode[145]' to='start_rise_sb_mux[0][0]_rrnode[145]+switch_rise_sb_mux[0][0]_rrnode[145]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[145] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_fall_sb_mux[0][0]_rrnode[145]' to='start_fall_sb_mux[0][0]_rrnode[145]+switch_fall_sb_mux[0][0]_rrnode[145]' -.meas tran sum_leakage_power_mux[0to19] -+ param='sum_leakage_power_mux[0to18]+leakage_sb_mux[0][0]_rrnode[145]' -.meas tran sum_energy_per_cycle_mux[0to19] -+ param='sum_energy_per_cycle_mux[0to18]+energy_per_cycle_sb_mux[0][0]_rrnode[145]' -***** Load for rr_node[145] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=8, type=4 ***** -Xchan_mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[43]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to19] -+ param='sum_leakage_power_sb_mux[0to18]+leakage_sb_mux[0][0]_rrnode[145]' -.meas tran sum_energy_per_cycle_sb_mux[0to19] -+ param='sum_energy_per_cycle_sb_mux[0to18]+energy_per_cycle_sb_mux[0][0]_rrnode[145]' -Xmux_1level_tapbuf_size2[20] mux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->out sram[24]->outb sram[24]->out gvdd_mux_1level_tapbuf_size2[20] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[20], level=1, select_path_id=0. ***** -*****1***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -***** Signal mux_1level_tapbuf_size2[20]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[20]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[20] gvdd_mux_1level_tapbuf_size2[20] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[147] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[147] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[147] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[147] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[147] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[147] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[147] param='mux_1level_tapbuf_size2[20]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[20]_energy_per_cycle param='mux_1level_tapbuf_size2[20]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[147] param='mux_1level_tapbuf_size2[20]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[147] param='dynamic_power_sb_mux[0][0]_rrnode[147]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[147] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_rise_sb_mux[0][0]_rrnode[147]' to='start_rise_sb_mux[0][0]_rrnode[147]+switch_rise_sb_mux[0][0]_rrnode[147]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[147] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_fall_sb_mux[0][0]_rrnode[147]' to='start_fall_sb_mux[0][0]_rrnode[147]+switch_fall_sb_mux[0][0]_rrnode[147]' -.meas tran sum_leakage_power_mux[0to20] -+ param='sum_leakage_power_mux[0to19]+leakage_sb_mux[0][0]_rrnode[147]' -.meas tran sum_energy_per_cycle_mux[0to20] -+ param='sum_energy_per_cycle_mux[0to19]+energy_per_cycle_sb_mux[0][0]_rrnode[147]' -***** Load for rr_node[147] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=10, type=4 ***** -Xchan_mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[45]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to20] -+ param='sum_leakage_power_sb_mux[0to19]+leakage_sb_mux[0][0]_rrnode[147]' -.meas tran sum_energy_per_cycle_sb_mux[0to20] -+ param='sum_energy_per_cycle_sb_mux[0to19]+energy_per_cycle_sb_mux[0][0]_rrnode[147]' -Xmux_1level_tapbuf_size2[21] mux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->out sram[25]->outb sram[25]->out gvdd_mux_1level_tapbuf_size2[21] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[21], level=1, select_path_id=0. ***** -*****1***** -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -***** Signal mux_1level_tapbuf_size2[21]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[21]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[21] gvdd_mux_1level_tapbuf_size2[21] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[149] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[149] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[149] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[149] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[149] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[149] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[149] param='mux_1level_tapbuf_size2[21]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[21]_energy_per_cycle param='mux_1level_tapbuf_size2[21]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[149] param='mux_1level_tapbuf_size2[21]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[149] param='dynamic_power_sb_mux[0][0]_rrnode[149]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[149] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_rise_sb_mux[0][0]_rrnode[149]' to='start_rise_sb_mux[0][0]_rrnode[149]+switch_rise_sb_mux[0][0]_rrnode[149]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[149] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_fall_sb_mux[0][0]_rrnode[149]' to='start_fall_sb_mux[0][0]_rrnode[149]+switch_fall_sb_mux[0][0]_rrnode[149]' -.meas tran sum_leakage_power_mux[0to21] -+ param='sum_leakage_power_mux[0to20]+leakage_sb_mux[0][0]_rrnode[149]' -.meas tran sum_energy_per_cycle_mux[0to21] -+ param='sum_energy_per_cycle_mux[0to20]+energy_per_cycle_sb_mux[0][0]_rrnode[149]' -***** Load for rr_node[149] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=12, type=4 ***** -Xchan_mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[47]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to21] -+ param='sum_leakage_power_sb_mux[0to20]+leakage_sb_mux[0][0]_rrnode[149]' -.meas tran sum_energy_per_cycle_sb_mux[0to21] -+ param='sum_energy_per_cycle_sb_mux[0to20]+energy_per_cycle_sb_mux[0][0]_rrnode[149]' -Xmux_1level_tapbuf_size2[22] mux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->out sram[26]->outb sram[26]->out gvdd_mux_1level_tapbuf_size2[22] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[22], level=1, select_path_id=0. ***** -*****1***** -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -***** Signal mux_1level_tapbuf_size2[22]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[22]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[22] gvdd_mux_1level_tapbuf_size2[22] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[151] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[151] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[151] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[151] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[151] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[151] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[151] param='mux_1level_tapbuf_size2[22]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[22]_energy_per_cycle param='mux_1level_tapbuf_size2[22]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[151] param='mux_1level_tapbuf_size2[22]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[151] param='dynamic_power_sb_mux[0][0]_rrnode[151]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[151] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_rise_sb_mux[0][0]_rrnode[151]' to='start_rise_sb_mux[0][0]_rrnode[151]+switch_rise_sb_mux[0][0]_rrnode[151]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[151] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_fall_sb_mux[0][0]_rrnode[151]' to='start_fall_sb_mux[0][0]_rrnode[151]+switch_fall_sb_mux[0][0]_rrnode[151]' -.meas tran sum_leakage_power_mux[0to22] -+ param='sum_leakage_power_mux[0to21]+leakage_sb_mux[0][0]_rrnode[151]' -.meas tran sum_energy_per_cycle_mux[0to22] -+ param='sum_energy_per_cycle_mux[0to21]+energy_per_cycle_sb_mux[0][0]_rrnode[151]' -***** Load for rr_node[151] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=14, type=4 ***** -Xchan_mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[49]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to22] -+ param='sum_leakage_power_sb_mux[0to21]+leakage_sb_mux[0][0]_rrnode[151]' -.meas tran sum_energy_per_cycle_sb_mux[0to22] -+ param='sum_energy_per_cycle_sb_mux[0to21]+energy_per_cycle_sb_mux[0][0]_rrnode[151]' -Xmux_1level_tapbuf_size2[23] mux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->out sram[27]->outb sram[27]->out gvdd_mux_1level_tapbuf_size2[23] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[23], level=1, select_path_id=0. ***** -*****1***** -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_1level_tapbuf_size2[23]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[23]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[23] gvdd_mux_1level_tapbuf_size2[23] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[153] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[153] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[153] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[153] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[153] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[153] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[153] param='mux_1level_tapbuf_size2[23]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[23]_energy_per_cycle param='mux_1level_tapbuf_size2[23]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[153] param='mux_1level_tapbuf_size2[23]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[153] param='dynamic_power_sb_mux[0][0]_rrnode[153]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[153] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_rise_sb_mux[0][0]_rrnode[153]' to='start_rise_sb_mux[0][0]_rrnode[153]+switch_rise_sb_mux[0][0]_rrnode[153]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[153] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_fall_sb_mux[0][0]_rrnode[153]' to='start_fall_sb_mux[0][0]_rrnode[153]+switch_fall_sb_mux[0][0]_rrnode[153]' -.meas tran sum_leakage_power_mux[0to23] -+ param='sum_leakage_power_mux[0to22]+leakage_sb_mux[0][0]_rrnode[153]' -.meas tran sum_energy_per_cycle_mux[0to23] -+ param='sum_energy_per_cycle_mux[0to22]+energy_per_cycle_sb_mux[0][0]_rrnode[153]' -***** Load for rr_node[153] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=16, type=4 ***** -Xchan_mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[51]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to23] -+ param='sum_leakage_power_sb_mux[0to22]+leakage_sb_mux[0][0]_rrnode[153]' -.meas tran sum_energy_per_cycle_sb_mux[0to23] -+ param='sum_energy_per_cycle_sb_mux[0to22]+energy_per_cycle_sb_mux[0][0]_rrnode[153]' -Xmux_1level_tapbuf_size2[24] mux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->out sram[28]->outb sram[28]->out gvdd_mux_1level_tapbuf_size2[24] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[24], level=1, select_path_id=0. ***** -*****1***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -***** Signal mux_1level_tapbuf_size2[24]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[24]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[24] gvdd_mux_1level_tapbuf_size2[24] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[155] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[155] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[155] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[155] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[155] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[155] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[155] param='mux_1level_tapbuf_size2[24]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[24]_energy_per_cycle param='mux_1level_tapbuf_size2[24]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[155] param='mux_1level_tapbuf_size2[24]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[155] param='dynamic_power_sb_mux[0][0]_rrnode[155]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[155] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_rise_sb_mux[0][0]_rrnode[155]' to='start_rise_sb_mux[0][0]_rrnode[155]+switch_rise_sb_mux[0][0]_rrnode[155]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[155] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_fall_sb_mux[0][0]_rrnode[155]' to='start_fall_sb_mux[0][0]_rrnode[155]+switch_fall_sb_mux[0][0]_rrnode[155]' -.meas tran sum_leakage_power_mux[0to24] -+ param='sum_leakage_power_mux[0to23]+leakage_sb_mux[0][0]_rrnode[155]' -.meas tran sum_energy_per_cycle_mux[0to24] -+ param='sum_energy_per_cycle_mux[0to23]+energy_per_cycle_sb_mux[0][0]_rrnode[155]' -***** Load for rr_node[155] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=18, type=4 ***** -Xchan_mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[53]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to24] -+ param='sum_leakage_power_sb_mux[0to23]+leakage_sb_mux[0][0]_rrnode[155]' -.meas tran sum_energy_per_cycle_sb_mux[0to24] -+ param='sum_energy_per_cycle_sb_mux[0to23]+energy_per_cycle_sb_mux[0][0]_rrnode[155]' -Xmux_1level_tapbuf_size2[25] mux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->out sram[29]->outb sram[29]->out gvdd_mux_1level_tapbuf_size2[25] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[25], level=1, select_path_id=0. ***** -*****1***** -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -***** Signal mux_1level_tapbuf_size2[25]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[25]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[25] gvdd_mux_1level_tapbuf_size2[25] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[157] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[157] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[157] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[157] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[157] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[157] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[157] param='mux_1level_tapbuf_size2[25]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[25]_energy_per_cycle param='mux_1level_tapbuf_size2[25]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[157] param='mux_1level_tapbuf_size2[25]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[157] param='dynamic_power_sb_mux[0][0]_rrnode[157]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[157] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_rise_sb_mux[0][0]_rrnode[157]' to='start_rise_sb_mux[0][0]_rrnode[157]+switch_rise_sb_mux[0][0]_rrnode[157]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[157] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_fall_sb_mux[0][0]_rrnode[157]' to='start_fall_sb_mux[0][0]_rrnode[157]+switch_fall_sb_mux[0][0]_rrnode[157]' -.meas tran sum_leakage_power_mux[0to25] -+ param='sum_leakage_power_mux[0to24]+leakage_sb_mux[0][0]_rrnode[157]' -.meas tran sum_energy_per_cycle_mux[0to25] -+ param='sum_energy_per_cycle_mux[0to24]+energy_per_cycle_sb_mux[0][0]_rrnode[157]' -***** Load for rr_node[157] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=20, type=4 ***** -Xchan_mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[55]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to25] -+ param='sum_leakage_power_sb_mux[0to24]+leakage_sb_mux[0][0]_rrnode[157]' -.meas tran sum_energy_per_cycle_sb_mux[0to25] -+ param='sum_energy_per_cycle_sb_mux[0to24]+energy_per_cycle_sb_mux[0][0]_rrnode[157]' -Xmux_1level_tapbuf_size2[26] mux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->out sram[30]->outb sram[30]->out gvdd_mux_1level_tapbuf_size2[26] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[26], level=1, select_path_id=0. ***** -*****1***** -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -***** Signal mux_1level_tapbuf_size2[26]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[26]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[26] gvdd_mux_1level_tapbuf_size2[26] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[159] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[159] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[159] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[159] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[159] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[159] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[159] param='mux_1level_tapbuf_size2[26]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[26]_energy_per_cycle param='mux_1level_tapbuf_size2[26]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[159] param='mux_1level_tapbuf_size2[26]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[159] param='dynamic_power_sb_mux[0][0]_rrnode[159]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[159] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_rise_sb_mux[0][0]_rrnode[159]' to='start_rise_sb_mux[0][0]_rrnode[159]+switch_rise_sb_mux[0][0]_rrnode[159]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[159] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_fall_sb_mux[0][0]_rrnode[159]' to='start_fall_sb_mux[0][0]_rrnode[159]+switch_fall_sb_mux[0][0]_rrnode[159]' -.meas tran sum_leakage_power_mux[0to26] -+ param='sum_leakage_power_mux[0to25]+leakage_sb_mux[0][0]_rrnode[159]' -.meas tran sum_energy_per_cycle_mux[0to26] -+ param='sum_energy_per_cycle_mux[0to25]+energy_per_cycle_sb_mux[0][0]_rrnode[159]' -***** Load for rr_node[159] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=22, type=4 ***** -Xchan_mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[57]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to26] -+ param='sum_leakage_power_sb_mux[0to25]+leakage_sb_mux[0][0]_rrnode[159]' -.meas tran sum_energy_per_cycle_sb_mux[0to26] -+ param='sum_energy_per_cycle_sb_mux[0to25]+energy_per_cycle_sb_mux[0][0]_rrnode[159]' -Xmux_1level_tapbuf_size2[27] mux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->out sram[31]->outb sram[31]->out gvdd_mux_1level_tapbuf_size2[27] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[27], level=1, select_path_id=0. ***** -*****1***** -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_1level_tapbuf_size2[27]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[27]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[27] gvdd_mux_1level_tapbuf_size2[27] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[161] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[161] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[161] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[161] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[161] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[161] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[161] param='mux_1level_tapbuf_size2[27]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[27]_energy_per_cycle param='mux_1level_tapbuf_size2[27]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[161] param='mux_1level_tapbuf_size2[27]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[161] param='dynamic_power_sb_mux[0][0]_rrnode[161]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[161] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_rise_sb_mux[0][0]_rrnode[161]' to='start_rise_sb_mux[0][0]_rrnode[161]+switch_rise_sb_mux[0][0]_rrnode[161]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[161] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_fall_sb_mux[0][0]_rrnode[161]' to='start_fall_sb_mux[0][0]_rrnode[161]+switch_fall_sb_mux[0][0]_rrnode[161]' -.meas tran sum_leakage_power_mux[0to27] -+ param='sum_leakage_power_mux[0to26]+leakage_sb_mux[0][0]_rrnode[161]' -.meas tran sum_energy_per_cycle_mux[0to27] -+ param='sum_energy_per_cycle_mux[0to26]+energy_per_cycle_sb_mux[0][0]_rrnode[161]' -***** Load for rr_node[161] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=24, type=4 ***** -Xchan_mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[60]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to27] -+ param='sum_leakage_power_sb_mux[0to26]+leakage_sb_mux[0][0]_rrnode[161]' -.meas tran sum_energy_per_cycle_sb_mux[0to27] -+ param='sum_energy_per_cycle_sb_mux[0to26]+energy_per_cycle_sb_mux[0][0]_rrnode[161]' -Xmux_1level_tapbuf_size2[28] mux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->out sram[32]->outb sram[32]->out gvdd_mux_1level_tapbuf_size2[28] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[28], level=1, select_path_id=0. ***** -*****1***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -***** Signal mux_1level_tapbuf_size2[28]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[28]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[28] gvdd_mux_1level_tapbuf_size2[28] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[163] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[163] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[163] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[163] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[163] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[163] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[163] param='mux_1level_tapbuf_size2[28]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[28]_energy_per_cycle param='mux_1level_tapbuf_size2[28]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[163] param='mux_1level_tapbuf_size2[28]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[163] param='dynamic_power_sb_mux[0][0]_rrnode[163]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[163] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_rise_sb_mux[0][0]_rrnode[163]' to='start_rise_sb_mux[0][0]_rrnode[163]+switch_rise_sb_mux[0][0]_rrnode[163]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[163] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_fall_sb_mux[0][0]_rrnode[163]' to='start_fall_sb_mux[0][0]_rrnode[163]+switch_fall_sb_mux[0][0]_rrnode[163]' -.meas tran sum_leakage_power_mux[0to28] -+ param='sum_leakage_power_mux[0to27]+leakage_sb_mux[0][0]_rrnode[163]' -.meas tran sum_energy_per_cycle_mux[0to28] -+ param='sum_energy_per_cycle_mux[0to27]+energy_per_cycle_sb_mux[0][0]_rrnode[163]' -***** Load for rr_node[163] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=26, type=4 ***** -Xchan_mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[62]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to28] -+ param='sum_leakage_power_sb_mux[0to27]+leakage_sb_mux[0][0]_rrnode[163]' -.meas tran sum_energy_per_cycle_sb_mux[0to28] -+ param='sum_energy_per_cycle_sb_mux[0to27]+energy_per_cycle_sb_mux[0][0]_rrnode[163]' -Xmux_1level_tapbuf_size2[29] mux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->out sram[33]->outb sram[33]->out gvdd_mux_1level_tapbuf_size2[29] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[29], level=1, select_path_id=0. ***** -*****1***** -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -***** Signal mux_1level_tapbuf_size2[29]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[29]->in[1] density = 0.1906, probability=0.4782.***** -Vmux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_1level_tapbuf_size2[29] gvdd_mux_1level_tapbuf_size2[29] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[165] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[165] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[165] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[165] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[165] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[165] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[165] param='mux_1level_tapbuf_size2[29]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size2[29]_energy_per_cycle param='mux_1level_tapbuf_size2[29]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[165] param='mux_1level_tapbuf_size2[29]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[165] param='dynamic_power_sb_mux[0][0]_rrnode[165]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[165] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_rise_sb_mux[0][0]_rrnode[165]' to='start_rise_sb_mux[0][0]_rrnode[165]+switch_rise_sb_mux[0][0]_rrnode[165]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[165] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_fall_sb_mux[0][0]_rrnode[165]' to='start_fall_sb_mux[0][0]_rrnode[165]+switch_fall_sb_mux[0][0]_rrnode[165]' -.meas tran sum_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to28]+leakage_sb_mux[0][0]_rrnode[165]' -.meas tran sum_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to28]+energy_per_cycle_sb_mux[0][0]_rrnode[165]' -***** Load for rr_node[165] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=28, type=4 ***** -Xchan_mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[64]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to29] -+ param='sum_leakage_power_sb_mux[0to28]+leakage_sb_mux[0][0]_rrnode[165]' -.meas tran sum_energy_per_cycle_sb_mux[0to29] -+ param='sum_energy_per_cycle_sb_mux[0to28]+energy_per_cycle_sb_mux[0][0]_rrnode[165]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='7*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to29]' -.meas tran total_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to29]' -.meas tran total_leakage_power_sb_mux -+ param='sum_leakage_power_sb_mux[0to29]' -.meas tran total_energy_per_cycle_sb_mux -+ param='sum_energy_per_cycle_sb_mux[0to29]' -.end diff --git a/examples/spice_test_example_1/sb_mux_tb/example_1_sb0_1_sbmux_testbench.sp b/examples/spice_test_example_1/sb_mux_tb/example_1_sb0_1_sbmux_testbench.sp deleted file mode 100644 index 70a586e9d..000000000 --- a/examples/spice_test_example_1/sb_mux_tb/example_1_sb0_1_sbmux_testbench.sp +++ /dev/null @@ -1,1686 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_1level_tapbuf_size3[0] mux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb gvdd_mux_1level_tapbuf_size3[0] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[0], level=1, select_path_id=0. ***** -*****100***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -***** Signal mux_1level_tapbuf_size3[0]->in[0] density = 0.1906, probability=0.5218.***** -Vmux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_1level_tapbuf_size3[0]->in[1] density = 0.1906, probability=0.4782.***** -Vmux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_1level_tapbuf_size3[0]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[0] gvdd_mux_1level_tapbuf_size3[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[167] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[167] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[167] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[167] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[167] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[167] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[167] param='mux_1level_tapbuf_size3[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size3[0]_energy_per_cycle param='mux_1level_tapbuf_size3[0]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[167] param='mux_1level_tapbuf_size3[0]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[167] param='dynamic_power_sb_mux[0][1]_rrnode[167]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[167] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_rise_sb_mux[0][1]_rrnode[167]' to='start_rise_sb_mux[0][1]_rrnode[167]+switch_rise_sb_mux[0][1]_rrnode[167]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[167] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_fall_sb_mux[0][1]_rrnode[167]' to='start_fall_sb_mux[0][1]_rrnode[167]+switch_fall_sb_mux[0][1]_rrnode[167]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_sb_mux[0][1]_rrnode[167]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_sb_mux[0][1]_rrnode[167]' -***** Load for rr_node[167] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=0, type=4 ***** -Xchan_mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to0] -+ param='leakage_sb_mux[0][1]_rrnode[167]' -.meas tran sum_energy_per_cycle_sb_mux[0to0] -+ param='energy_per_cycle_sb_mux[0][1]_rrnode[167]' -Xmux_1level_tapbuf_size3[1] mux_1level_tapbuf_size3[1]->in[0] mux_1level_tapbuf_size3[1]->in[1] mux_1level_tapbuf_size3[1]->in[2] mux_1level_tapbuf_size3[1]->out sram[3]->outb sram[3]->out sram[4]->out sram[4]->outb sram[5]->out sram[5]->outb gvdd_mux_1level_tapbuf_size3[1] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[1], level=1, select_path_id=0. ***** -*****100***** -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -***** Signal mux_1level_tapbuf_size3[1]->in[0] density = 0.1906, probability=0.5218.***** -Vmux_1level_tapbuf_size3[1]->in[0] mux_1level_tapbuf_size3[1]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_1level_tapbuf_size3[1]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[1] mux_1level_tapbuf_size3[1]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[1]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[2] mux_1level_tapbuf_size3[1]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[1] gvdd_mux_1level_tapbuf_size3[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[169] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[169] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[169] when v(mux_1level_tapbuf_size3[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[169] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[169] when v(mux_1level_tapbuf_size3[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[169] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[1]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[169] param='mux_1level_tapbuf_size3[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[1]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size3[1]_energy_per_cycle param='mux_1level_tapbuf_size3[1]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[169] param='mux_1level_tapbuf_size3[1]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[169] param='dynamic_power_sb_mux[0][1]_rrnode[169]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[169] avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='start_rise_sb_mux[0][1]_rrnode[169]' to='start_rise_sb_mux[0][1]_rrnode[169]+switch_rise_sb_mux[0][1]_rrnode[169]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[169] avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='start_fall_sb_mux[0][1]_rrnode[169]' to='start_fall_sb_mux[0][1]_rrnode[169]+switch_fall_sb_mux[0][1]_rrnode[169]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_sb_mux[0][1]_rrnode[169]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_sb_mux[0][1]_rrnode[169]' -***** Load for rr_node[169] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=2, type=4 ***** -Xchan_mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to1] -+ param='sum_leakage_power_sb_mux[0to0]+leakage_sb_mux[0][1]_rrnode[169]' -.meas tran sum_energy_per_cycle_sb_mux[0to1] -+ param='sum_energy_per_cycle_sb_mux[0to0]+energy_per_cycle_sb_mux[0][1]_rrnode[169]' -Xmux_1level_tapbuf_size3[2] mux_1level_tapbuf_size3[2]->in[0] mux_1level_tapbuf_size3[2]->in[1] mux_1level_tapbuf_size3[2]->in[2] mux_1level_tapbuf_size3[2]->out sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb sram[8]->out sram[8]->outb gvdd_mux_1level_tapbuf_size3[2] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[2], level=1, select_path_id=0. ***** -*****100***** -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -***** Signal mux_1level_tapbuf_size3[2]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[0] mux_1level_tapbuf_size3[2]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[2]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[1] mux_1level_tapbuf_size3[2]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[2]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[2] mux_1level_tapbuf_size3[2]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[2] gvdd_mux_1level_tapbuf_size3[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[171] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[171] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[171] when v(mux_1level_tapbuf_size3[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[171] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[171] when v(mux_1level_tapbuf_size3[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[171] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[2]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[171] param='mux_1level_tapbuf_size3[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[2]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[2]_energy_per_cycle param='mux_1level_tapbuf_size3[2]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[171] param='mux_1level_tapbuf_size3[2]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[171] param='dynamic_power_sb_mux[0][1]_rrnode[171]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[171] avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='start_rise_sb_mux[0][1]_rrnode[171]' to='start_rise_sb_mux[0][1]_rrnode[171]+switch_rise_sb_mux[0][1]_rrnode[171]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[171] avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='start_fall_sb_mux[0][1]_rrnode[171]' to='start_fall_sb_mux[0][1]_rrnode[171]+switch_fall_sb_mux[0][1]_rrnode[171]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_sb_mux[0][1]_rrnode[171]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_sb_mux[0][1]_rrnode[171]' -***** Load for rr_node[171] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=4, type=4 ***** -Xchan_mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[4]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to2] -+ param='sum_leakage_power_sb_mux[0to1]+leakage_sb_mux[0][1]_rrnode[171]' -.meas tran sum_energy_per_cycle_sb_mux[0to2] -+ param='sum_energy_per_cycle_sb_mux[0to1]+energy_per_cycle_sb_mux[0][1]_rrnode[171]' -Xmux_1level_tapbuf_size2[3] mux_1level_tapbuf_size2[3]->in[0] mux_1level_tapbuf_size2[3]->in[1] mux_1level_tapbuf_size2[3]->out sram[9]->outb sram[9]->out gvdd_mux_1level_tapbuf_size2[3] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[3], level=1, select_path_id=0. ***** -*****1***** -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -***** Signal mux_1level_tapbuf_size2[3]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[3]->in[0] mux_1level_tapbuf_size2[3]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[3]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[3]->in[1] mux_1level_tapbuf_size2[3]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[3] gvdd_mux_1level_tapbuf_size2[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[173] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[173] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[173] when v(mux_1level_tapbuf_size2[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[173] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[173] when v(mux_1level_tapbuf_size2[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[173] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[3]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[173] param='mux_1level_tapbuf_size2[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[3]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[3]_energy_per_cycle param='mux_1level_tapbuf_size2[3]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[173] param='mux_1level_tapbuf_size2[3]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[173] param='dynamic_power_sb_mux[0][1]_rrnode[173]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[173] avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='start_rise_sb_mux[0][1]_rrnode[173]' to='start_rise_sb_mux[0][1]_rrnode[173]+switch_rise_sb_mux[0][1]_rrnode[173]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[173] avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='start_fall_sb_mux[0][1]_rrnode[173]' to='start_fall_sb_mux[0][1]_rrnode[173]+switch_fall_sb_mux[0][1]_rrnode[173]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_sb_mux[0][1]_rrnode[173]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_sb_mux[0][1]_rrnode[173]' -***** Load for rr_node[173] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=6, type=4 ***** -Xchan_mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[6]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to3] -+ param='sum_leakage_power_sb_mux[0to2]+leakage_sb_mux[0][1]_rrnode[173]' -.meas tran sum_energy_per_cycle_sb_mux[0to3] -+ param='sum_energy_per_cycle_sb_mux[0to2]+energy_per_cycle_sb_mux[0][1]_rrnode[173]' -Xmux_1level_tapbuf_size2[4] mux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->out sram[10]->outb sram[10]->out gvdd_mux_1level_tapbuf_size2[4] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****1***** -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -***** Signal mux_1level_tapbuf_size2[4]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[4]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[4] gvdd_mux_1level_tapbuf_size2[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[175] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[175] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[175] when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[175] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[175] when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[175] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[175] param='mux_1level_tapbuf_size2[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[4]_energy_per_cycle param='mux_1level_tapbuf_size2[4]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[175] param='mux_1level_tapbuf_size2[4]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[175] param='dynamic_power_sb_mux[0][1]_rrnode[175]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[175] avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_rise_sb_mux[0][1]_rrnode[175]' to='start_rise_sb_mux[0][1]_rrnode[175]+switch_rise_sb_mux[0][1]_rrnode[175]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[175] avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_fall_sb_mux[0][1]_rrnode[175]' to='start_fall_sb_mux[0][1]_rrnode[175]+switch_fall_sb_mux[0][1]_rrnode[175]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_sb_mux[0][1]_rrnode[175]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_sb_mux[0][1]_rrnode[175]' -***** Load for rr_node[175] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=8, type=4 ***** -Xchan_mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[9]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to4] -+ param='sum_leakage_power_sb_mux[0to3]+leakage_sb_mux[0][1]_rrnode[175]' -.meas tran sum_energy_per_cycle_sb_mux[0to4] -+ param='sum_energy_per_cycle_sb_mux[0to3]+energy_per_cycle_sb_mux[0][1]_rrnode[175]' -Xmux_1level_tapbuf_size2[5] mux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->out sram[11]->outb sram[11]->out gvdd_mux_1level_tapbuf_size2[5] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[5], level=1, select_path_id=0. ***** -*****1***** -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_1level_tapbuf_size2[5]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[5]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[5] gvdd_mux_1level_tapbuf_size2[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[177] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[177] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[177] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[177] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[177] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[177] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[177] param='mux_1level_tapbuf_size2[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[5]_energy_per_cycle param='mux_1level_tapbuf_size2[5]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[177] param='mux_1level_tapbuf_size2[5]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[177] param='dynamic_power_sb_mux[0][1]_rrnode[177]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[177] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_rise_sb_mux[0][1]_rrnode[177]' to='start_rise_sb_mux[0][1]_rrnode[177]+switch_rise_sb_mux[0][1]_rrnode[177]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[177] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_fall_sb_mux[0][1]_rrnode[177]' to='start_fall_sb_mux[0][1]_rrnode[177]+switch_fall_sb_mux[0][1]_rrnode[177]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_sb_mux[0][1]_rrnode[177]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_sb_mux[0][1]_rrnode[177]' -***** Load for rr_node[177] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=10, type=4 ***** -Xchan_mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[11]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to5] -+ param='sum_leakage_power_sb_mux[0to4]+leakage_sb_mux[0][1]_rrnode[177]' -.meas tran sum_energy_per_cycle_sb_mux[0to5] -+ param='sum_energy_per_cycle_sb_mux[0to4]+energy_per_cycle_sb_mux[0][1]_rrnode[177]' -Xmux_1level_tapbuf_size2[6] mux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->out sram[12]->outb sram[12]->out gvdd_mux_1level_tapbuf_size2[6] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[6], level=1, select_path_id=0. ***** -*****1***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -***** Signal mux_1level_tapbuf_size2[6]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[6]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[6] gvdd_mux_1level_tapbuf_size2[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[179] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[179] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[179] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[179] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[179] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[179] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[179] param='mux_1level_tapbuf_size2[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[6]_energy_per_cycle param='mux_1level_tapbuf_size2[6]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[179] param='mux_1level_tapbuf_size2[6]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[179] param='dynamic_power_sb_mux[0][1]_rrnode[179]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[179] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_rise_sb_mux[0][1]_rrnode[179]' to='start_rise_sb_mux[0][1]_rrnode[179]+switch_rise_sb_mux[0][1]_rrnode[179]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[179] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_fall_sb_mux[0][1]_rrnode[179]' to='start_fall_sb_mux[0][1]_rrnode[179]+switch_fall_sb_mux[0][1]_rrnode[179]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_sb_mux[0][1]_rrnode[179]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_sb_mux[0][1]_rrnode[179]' -***** Load for rr_node[179] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=12, type=4 ***** -Xchan_mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[13]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to6] -+ param='sum_leakage_power_sb_mux[0to5]+leakage_sb_mux[0][1]_rrnode[179]' -.meas tran sum_energy_per_cycle_sb_mux[0to6] -+ param='sum_energy_per_cycle_sb_mux[0to5]+energy_per_cycle_sb_mux[0][1]_rrnode[179]' -Xmux_1level_tapbuf_size2[7] mux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->out sram[13]->outb sram[13]->out gvdd_mux_1level_tapbuf_size2[7] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[7], level=1, select_path_id=0. ***** -*****1***** -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -***** Signal mux_1level_tapbuf_size2[7]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[7]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[7] gvdd_mux_1level_tapbuf_size2[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[181] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[181] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[181] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[181] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[181] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[181] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[181] param='mux_1level_tapbuf_size2[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[7]_energy_per_cycle param='mux_1level_tapbuf_size2[7]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[181] param='mux_1level_tapbuf_size2[7]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[181] param='dynamic_power_sb_mux[0][1]_rrnode[181]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[181] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_rise_sb_mux[0][1]_rrnode[181]' to='start_rise_sb_mux[0][1]_rrnode[181]+switch_rise_sb_mux[0][1]_rrnode[181]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[181] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_fall_sb_mux[0][1]_rrnode[181]' to='start_fall_sb_mux[0][1]_rrnode[181]+switch_fall_sb_mux[0][1]_rrnode[181]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_sb_mux[0][1]_rrnode[181]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_sb_mux[0][1]_rrnode[181]' -***** Load for rr_node[181] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=14, type=4 ***** -Xchan_mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[17]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to7] -+ param='sum_leakage_power_sb_mux[0to6]+leakage_sb_mux[0][1]_rrnode[181]' -.meas tran sum_energy_per_cycle_sb_mux[0to7] -+ param='sum_energy_per_cycle_sb_mux[0to6]+energy_per_cycle_sb_mux[0][1]_rrnode[181]' -Xmux_1level_tapbuf_size2[8] mux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->out sram[14]->outb sram[14]->out gvdd_mux_1level_tapbuf_size2[8] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[8], level=1, select_path_id=0. ***** -*****1***** -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -***** Signal mux_1level_tapbuf_size2[8]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[8]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[8] gvdd_mux_1level_tapbuf_size2[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[183] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[183] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[183] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[183] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[183] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[183] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[183] param='mux_1level_tapbuf_size2[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[8]_energy_per_cycle param='mux_1level_tapbuf_size2[8]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[183] param='mux_1level_tapbuf_size2[8]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[183] param='dynamic_power_sb_mux[0][1]_rrnode[183]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[183] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_rise_sb_mux[0][1]_rrnode[183]' to='start_rise_sb_mux[0][1]_rrnode[183]+switch_rise_sb_mux[0][1]_rrnode[183]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[183] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_fall_sb_mux[0][1]_rrnode[183]' to='start_fall_sb_mux[0][1]_rrnode[183]+switch_fall_sb_mux[0][1]_rrnode[183]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_sb_mux[0][1]_rrnode[183]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_sb_mux[0][1]_rrnode[183]' -***** Load for rr_node[183] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=16, type=4 ***** -Xchan_mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[19]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to8] -+ param='sum_leakage_power_sb_mux[0to7]+leakage_sb_mux[0][1]_rrnode[183]' -.meas tran sum_energy_per_cycle_sb_mux[0to8] -+ param='sum_energy_per_cycle_sb_mux[0to7]+energy_per_cycle_sb_mux[0][1]_rrnode[183]' -Xmux_1level_tapbuf_size2[9] mux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->out sram[15]->outb sram[15]->out gvdd_mux_1level_tapbuf_size2[9] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[9], level=1, select_path_id=0. ***** -*****1***** -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_1level_tapbuf_size2[9]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[9]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[9] gvdd_mux_1level_tapbuf_size2[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[185] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[185] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[185] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[185] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[185] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[185] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[185] param='mux_1level_tapbuf_size2[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[9]_energy_per_cycle param='mux_1level_tapbuf_size2[9]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[185] param='mux_1level_tapbuf_size2[9]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[185] param='dynamic_power_sb_mux[0][1]_rrnode[185]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[185] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_rise_sb_mux[0][1]_rrnode[185]' to='start_rise_sb_mux[0][1]_rrnode[185]+switch_rise_sb_mux[0][1]_rrnode[185]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[185] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_fall_sb_mux[0][1]_rrnode[185]' to='start_fall_sb_mux[0][1]_rrnode[185]+switch_fall_sb_mux[0][1]_rrnode[185]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_sb_mux[0][1]_rrnode[185]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_sb_mux[0][1]_rrnode[185]' -***** Load for rr_node[185] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=18, type=4 ***** -Xchan_mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[21]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to9] -+ param='sum_leakage_power_sb_mux[0to8]+leakage_sb_mux[0][1]_rrnode[185]' -.meas tran sum_energy_per_cycle_sb_mux[0to9] -+ param='sum_energy_per_cycle_sb_mux[0to8]+energy_per_cycle_sb_mux[0][1]_rrnode[185]' -Xmux_1level_tapbuf_size2[10] mux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->out sram[16]->outb sram[16]->out gvdd_mux_1level_tapbuf_size2[10] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[10], level=1, select_path_id=0. ***** -*****1***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -***** Signal mux_1level_tapbuf_size2[10]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[10]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[10] gvdd_mux_1level_tapbuf_size2[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[187] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[187] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[187] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[187] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[187] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[187] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[187] param='mux_1level_tapbuf_size2[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[10]_energy_per_cycle param='mux_1level_tapbuf_size2[10]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[187] param='mux_1level_tapbuf_size2[10]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[187] param='dynamic_power_sb_mux[0][1]_rrnode[187]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[187] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_rise_sb_mux[0][1]_rrnode[187]' to='start_rise_sb_mux[0][1]_rrnode[187]+switch_rise_sb_mux[0][1]_rrnode[187]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[187] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_fall_sb_mux[0][1]_rrnode[187]' to='start_fall_sb_mux[0][1]_rrnode[187]+switch_fall_sb_mux[0][1]_rrnode[187]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_sb_mux[0][1]_rrnode[187]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_sb_mux[0][1]_rrnode[187]' -***** Load for rr_node[187] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=20, type=4 ***** -Xchan_mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[23]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to10] -+ param='sum_leakage_power_sb_mux[0to9]+leakage_sb_mux[0][1]_rrnode[187]' -.meas tran sum_energy_per_cycle_sb_mux[0to10] -+ param='sum_energy_per_cycle_sb_mux[0to9]+energy_per_cycle_sb_mux[0][1]_rrnode[187]' -Xmux_1level_tapbuf_size2[11] mux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->out sram[17]->outb sram[17]->out gvdd_mux_1level_tapbuf_size2[11] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[11], level=1, select_path_id=0. ***** -*****1***** -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -***** Signal mux_1level_tapbuf_size2[11]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[11]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[11] gvdd_mux_1level_tapbuf_size2[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[189] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[189] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[189] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[189] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[189] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[189] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[189] param='mux_1level_tapbuf_size2[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[11]_energy_per_cycle param='mux_1level_tapbuf_size2[11]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[189] param='mux_1level_tapbuf_size2[11]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[189] param='dynamic_power_sb_mux[0][1]_rrnode[189]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[189] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_rise_sb_mux[0][1]_rrnode[189]' to='start_rise_sb_mux[0][1]_rrnode[189]+switch_rise_sb_mux[0][1]_rrnode[189]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[189] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_fall_sb_mux[0][1]_rrnode[189]' to='start_fall_sb_mux[0][1]_rrnode[189]+switch_fall_sb_mux[0][1]_rrnode[189]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_sb_mux[0][1]_rrnode[189]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_sb_mux[0][1]_rrnode[189]' -***** Load for rr_node[189] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=22, type=4 ***** -Xchan_mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[25]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to11] -+ param='sum_leakage_power_sb_mux[0to10]+leakage_sb_mux[0][1]_rrnode[189]' -.meas tran sum_energy_per_cycle_sb_mux[0to11] -+ param='sum_energy_per_cycle_sb_mux[0to10]+energy_per_cycle_sb_mux[0][1]_rrnode[189]' -Xmux_1level_tapbuf_size2[12] mux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->out sram[18]->outb sram[18]->out gvdd_mux_1level_tapbuf_size2[12] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[12], level=1, select_path_id=0. ***** -*****1***** -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -***** Signal mux_1level_tapbuf_size2[12]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[12]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[12] gvdd_mux_1level_tapbuf_size2[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[191] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[191] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[191] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[191] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[191] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[191] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[191] param='mux_1level_tapbuf_size2[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[12]_energy_per_cycle param='mux_1level_tapbuf_size2[12]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[191] param='mux_1level_tapbuf_size2[12]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[191] param='dynamic_power_sb_mux[0][1]_rrnode[191]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[191] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_rise_sb_mux[0][1]_rrnode[191]' to='start_rise_sb_mux[0][1]_rrnode[191]+switch_rise_sb_mux[0][1]_rrnode[191]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[191] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_fall_sb_mux[0][1]_rrnode[191]' to='start_fall_sb_mux[0][1]_rrnode[191]+switch_fall_sb_mux[0][1]_rrnode[191]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_sb_mux[0][1]_rrnode[191]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_sb_mux[0][1]_rrnode[191]' -***** Load for rr_node[191] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=24, type=4 ***** -Xchan_mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[27]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to12] -+ param='sum_leakage_power_sb_mux[0to11]+leakage_sb_mux[0][1]_rrnode[191]' -.meas tran sum_energy_per_cycle_sb_mux[0to12] -+ param='sum_energy_per_cycle_sb_mux[0to11]+energy_per_cycle_sb_mux[0][1]_rrnode[191]' -Xmux_1level_tapbuf_size2[13] mux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->out sram[19]->outb sram[19]->out gvdd_mux_1level_tapbuf_size2[13] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[13], level=1, select_path_id=0. ***** -*****1***** -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_1level_tapbuf_size2[13]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[13]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[13] gvdd_mux_1level_tapbuf_size2[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[193] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[193] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[193] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[193] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[193] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[193] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[193] param='mux_1level_tapbuf_size2[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[13]_energy_per_cycle param='mux_1level_tapbuf_size2[13]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[193] param='mux_1level_tapbuf_size2[13]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[193] param='dynamic_power_sb_mux[0][1]_rrnode[193]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[193] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_rise_sb_mux[0][1]_rrnode[193]' to='start_rise_sb_mux[0][1]_rrnode[193]+switch_rise_sb_mux[0][1]_rrnode[193]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[193] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_fall_sb_mux[0][1]_rrnode[193]' to='start_fall_sb_mux[0][1]_rrnode[193]+switch_fall_sb_mux[0][1]_rrnode[193]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_sb_mux[0][1]_rrnode[193]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_sb_mux[0][1]_rrnode[193]' -***** Load for rr_node[193] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=26, type=4 ***** -Xchan_mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[29]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to13] -+ param='sum_leakage_power_sb_mux[0to12]+leakage_sb_mux[0][1]_rrnode[193]' -.meas tran sum_energy_per_cycle_sb_mux[0to13] -+ param='sum_energy_per_cycle_sb_mux[0to12]+energy_per_cycle_sb_mux[0][1]_rrnode[193]' -Xmux_1level_tapbuf_size2[14] mux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->out sram[20]->outb sram[20]->out gvdd_mux_1level_tapbuf_size2[14] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[14], level=1, select_path_id=0. ***** -*****1***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -***** Signal mux_1level_tapbuf_size2[14]->in[0] density = 0.1906, probability=0.4782.***** -Vmux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_1level_tapbuf_size2[14]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[14] gvdd_mux_1level_tapbuf_size2[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[195] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[195] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[195] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[195] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[195] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[195] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[195] param='mux_1level_tapbuf_size2[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size2[14]_energy_per_cycle param='mux_1level_tapbuf_size2[14]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[195] param='mux_1level_tapbuf_size2[14]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[195] param='dynamic_power_sb_mux[0][1]_rrnode[195]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[195] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_rise_sb_mux[0][1]_rrnode[195]' to='start_rise_sb_mux[0][1]_rrnode[195]+switch_rise_sb_mux[0][1]_rrnode[195]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[195] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_fall_sb_mux[0][1]_rrnode[195]' to='start_fall_sb_mux[0][1]_rrnode[195]+switch_fall_sb_mux[0][1]_rrnode[195]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_sb_mux[0][1]_rrnode[195]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_sb_mux[0][1]_rrnode[195]' -***** Load for rr_node[195] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=28, type=4 ***** -Xchan_mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[31]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to14] -+ param='sum_leakage_power_sb_mux[0to13]+leakage_sb_mux[0][1]_rrnode[195]' -.meas tran sum_energy_per_cycle_sb_mux[0to14] -+ param='sum_energy_per_cycle_sb_mux[0to13]+energy_per_cycle_sb_mux[0][1]_rrnode[195]' -Xmux_1level_tapbuf_size3[15] mux_1level_tapbuf_size3[15]->in[0] mux_1level_tapbuf_size3[15]->in[1] mux_1level_tapbuf_size3[15]->in[2] mux_1level_tapbuf_size3[15]->out sram[21]->outb sram[21]->out sram[22]->out sram[22]->outb sram[23]->out sram[23]->outb gvdd_mux_1level_tapbuf_size3[15] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[15], level=1, select_path_id=0. ***** -*****100***** -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_1level_tapbuf_size3[15]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[15]->in[0] mux_1level_tapbuf_size3[15]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[15]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[15]->in[1] mux_1level_tapbuf_size3[15]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[15]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[15]->in[2] mux_1level_tapbuf_size3[15]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[15] gvdd_mux_1level_tapbuf_size3[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[198] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[198] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[198] when v(mux_1level_tapbuf_size3[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[198] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[198] when v(mux_1level_tapbuf_size3[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[198] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[15]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[198] param='mux_1level_tapbuf_size3[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[15]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[15]_energy_per_cycle param='mux_1level_tapbuf_size3[15]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[198] param='mux_1level_tapbuf_size3[15]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[198] param='dynamic_power_sb_mux[0][1]_rrnode[198]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[198] avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='start_rise_sb_mux[0][1]_rrnode[198]' to='start_rise_sb_mux[0][1]_rrnode[198]+switch_rise_sb_mux[0][1]_rrnode[198]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[198] avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='start_fall_sb_mux[0][1]_rrnode[198]' to='start_fall_sb_mux[0][1]_rrnode[198]+switch_fall_sb_mux[0][1]_rrnode[198]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_sb_mux[0][1]_rrnode[198]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_sb_mux[0][1]_rrnode[198]' -***** Load for rr_node[198] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=1, type=5 ***** -Xchan_mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[33]_no0 mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to15] -+ param='sum_leakage_power_sb_mux[0to14]+leakage_sb_mux[0][1]_rrnode[198]' -.meas tran sum_energy_per_cycle_sb_mux[0to15] -+ param='sum_energy_per_cycle_sb_mux[0to14]+energy_per_cycle_sb_mux[0][1]_rrnode[198]' -Xmux_1level_tapbuf_size2[16] mux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->out sram[24]->outb sram[24]->out gvdd_mux_1level_tapbuf_size2[16] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[16], level=1, select_path_id=0. ***** -*****1***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -***** Signal mux_1level_tapbuf_size2[16]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[16]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[16] gvdd_mux_1level_tapbuf_size2[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[200] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[200] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[200] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[200] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[200] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[200] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[200] param='mux_1level_tapbuf_size2[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[16]_energy_per_cycle param='mux_1level_tapbuf_size2[16]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[200] param='mux_1level_tapbuf_size2[16]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[200] param='dynamic_power_sb_mux[0][1]_rrnode[200]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[200] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_rise_sb_mux[0][1]_rrnode[200]' to='start_rise_sb_mux[0][1]_rrnode[200]+switch_rise_sb_mux[0][1]_rrnode[200]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[200] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_fall_sb_mux[0][1]_rrnode[200]' to='start_fall_sb_mux[0][1]_rrnode[200]+switch_fall_sb_mux[0][1]_rrnode[200]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_sb_mux[0][1]_rrnode[200]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_sb_mux[0][1]_rrnode[200]' -***** Load for rr_node[200] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=3, type=5 ***** -Xchan_mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[35]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to16] -+ param='sum_leakage_power_sb_mux[0to15]+leakage_sb_mux[0][1]_rrnode[200]' -.meas tran sum_energy_per_cycle_sb_mux[0to16] -+ param='sum_energy_per_cycle_sb_mux[0to15]+energy_per_cycle_sb_mux[0][1]_rrnode[200]' -Xmux_1level_tapbuf_size2[17] mux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->out sram[25]->outb sram[25]->out gvdd_mux_1level_tapbuf_size2[17] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[17], level=1, select_path_id=0. ***** -*****1***** -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -***** Signal mux_1level_tapbuf_size2[17]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[17]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[17] gvdd_mux_1level_tapbuf_size2[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[202] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[202] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[202] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[202] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[202] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[202] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[202] param='mux_1level_tapbuf_size2[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[17]_energy_per_cycle param='mux_1level_tapbuf_size2[17]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[202] param='mux_1level_tapbuf_size2[17]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[202] param='dynamic_power_sb_mux[0][1]_rrnode[202]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[202] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_rise_sb_mux[0][1]_rrnode[202]' to='start_rise_sb_mux[0][1]_rrnode[202]+switch_rise_sb_mux[0][1]_rrnode[202]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[202] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_fall_sb_mux[0][1]_rrnode[202]' to='start_fall_sb_mux[0][1]_rrnode[202]+switch_fall_sb_mux[0][1]_rrnode[202]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_sb_mux[0][1]_rrnode[202]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_sb_mux[0][1]_rrnode[202]' -***** Load for rr_node[202] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=5, type=5 ***** -Xchan_mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[37]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to17] -+ param='sum_leakage_power_sb_mux[0to16]+leakage_sb_mux[0][1]_rrnode[202]' -.meas tran sum_energy_per_cycle_sb_mux[0to17] -+ param='sum_energy_per_cycle_sb_mux[0to16]+energy_per_cycle_sb_mux[0][1]_rrnode[202]' -Xmux_1level_tapbuf_size2[18] mux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->out sram[26]->outb sram[26]->out gvdd_mux_1level_tapbuf_size2[18] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[18], level=1, select_path_id=0. ***** -*****1***** -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -***** Signal mux_1level_tapbuf_size2[18]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[18]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[18] gvdd_mux_1level_tapbuf_size2[18] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[204] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[204] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[204] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[204] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[204] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[204] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[204] param='mux_1level_tapbuf_size2[18]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[18]_energy_per_cycle param='mux_1level_tapbuf_size2[18]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[204] param='mux_1level_tapbuf_size2[18]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[204] param='dynamic_power_sb_mux[0][1]_rrnode[204]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[204] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_rise_sb_mux[0][1]_rrnode[204]' to='start_rise_sb_mux[0][1]_rrnode[204]+switch_rise_sb_mux[0][1]_rrnode[204]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[204] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_fall_sb_mux[0][1]_rrnode[204]' to='start_fall_sb_mux[0][1]_rrnode[204]+switch_fall_sb_mux[0][1]_rrnode[204]' -.meas tran sum_leakage_power_mux[0to18] -+ param='sum_leakage_power_mux[0to17]+leakage_sb_mux[0][1]_rrnode[204]' -.meas tran sum_energy_per_cycle_mux[0to18] -+ param='sum_energy_per_cycle_mux[0to17]+energy_per_cycle_sb_mux[0][1]_rrnode[204]' -***** Load for rr_node[204] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=7, type=5 ***** -Xchan_mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[39]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to18] -+ param='sum_leakage_power_sb_mux[0to17]+leakage_sb_mux[0][1]_rrnode[204]' -.meas tran sum_energy_per_cycle_sb_mux[0to18] -+ param='sum_energy_per_cycle_sb_mux[0to17]+energy_per_cycle_sb_mux[0][1]_rrnode[204]' -Xmux_1level_tapbuf_size2[19] mux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->out sram[27]->outb sram[27]->out gvdd_mux_1level_tapbuf_size2[19] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[19], level=1, select_path_id=0. ***** -*****1***** -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_1level_tapbuf_size2[19]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[19]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[19] gvdd_mux_1level_tapbuf_size2[19] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[206] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[206] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[206] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[206] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[206] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[206] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[206] param='mux_1level_tapbuf_size2[19]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[19]_energy_per_cycle param='mux_1level_tapbuf_size2[19]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[206] param='mux_1level_tapbuf_size2[19]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[206] param='dynamic_power_sb_mux[0][1]_rrnode[206]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[206] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_rise_sb_mux[0][1]_rrnode[206]' to='start_rise_sb_mux[0][1]_rrnode[206]+switch_rise_sb_mux[0][1]_rrnode[206]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[206] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_fall_sb_mux[0][1]_rrnode[206]' to='start_fall_sb_mux[0][1]_rrnode[206]+switch_fall_sb_mux[0][1]_rrnode[206]' -.meas tran sum_leakage_power_mux[0to19] -+ param='sum_leakage_power_mux[0to18]+leakage_sb_mux[0][1]_rrnode[206]' -.meas tran sum_energy_per_cycle_mux[0to19] -+ param='sum_energy_per_cycle_mux[0to18]+energy_per_cycle_sb_mux[0][1]_rrnode[206]' -***** Load for rr_node[206] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=9, type=5 ***** -Xchan_mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[42]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to19] -+ param='sum_leakage_power_sb_mux[0to18]+leakage_sb_mux[0][1]_rrnode[206]' -.meas tran sum_energy_per_cycle_sb_mux[0to19] -+ param='sum_energy_per_cycle_sb_mux[0to18]+energy_per_cycle_sb_mux[0][1]_rrnode[206]' -Xmux_1level_tapbuf_size2[20] mux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->out sram[28]->outb sram[28]->out gvdd_mux_1level_tapbuf_size2[20] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[20], level=1, select_path_id=0. ***** -*****1***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -***** Signal mux_1level_tapbuf_size2[20]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[20]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[20] gvdd_mux_1level_tapbuf_size2[20] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[208] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[208] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[208] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[208] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[208] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[208] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[208] param='mux_1level_tapbuf_size2[20]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[20]_energy_per_cycle param='mux_1level_tapbuf_size2[20]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[208] param='mux_1level_tapbuf_size2[20]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[208] param='dynamic_power_sb_mux[0][1]_rrnode[208]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[208] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_rise_sb_mux[0][1]_rrnode[208]' to='start_rise_sb_mux[0][1]_rrnode[208]+switch_rise_sb_mux[0][1]_rrnode[208]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[208] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_fall_sb_mux[0][1]_rrnode[208]' to='start_fall_sb_mux[0][1]_rrnode[208]+switch_fall_sb_mux[0][1]_rrnode[208]' -.meas tran sum_leakage_power_mux[0to20] -+ param='sum_leakage_power_mux[0to19]+leakage_sb_mux[0][1]_rrnode[208]' -.meas tran sum_energy_per_cycle_mux[0to20] -+ param='sum_energy_per_cycle_mux[0to19]+energy_per_cycle_sb_mux[0][1]_rrnode[208]' -***** Load for rr_node[208] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=11, type=5 ***** -Xchan_mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[44]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to20] -+ param='sum_leakage_power_sb_mux[0to19]+leakage_sb_mux[0][1]_rrnode[208]' -.meas tran sum_energy_per_cycle_sb_mux[0to20] -+ param='sum_energy_per_cycle_sb_mux[0to19]+energy_per_cycle_sb_mux[0][1]_rrnode[208]' -Xmux_1level_tapbuf_size2[21] mux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->out sram[29]->outb sram[29]->out gvdd_mux_1level_tapbuf_size2[21] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[21], level=1, select_path_id=0. ***** -*****1***** -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -***** Signal mux_1level_tapbuf_size2[21]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[21]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[21] gvdd_mux_1level_tapbuf_size2[21] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[210] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[210] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[210] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[210] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[210] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[210] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[210] param='mux_1level_tapbuf_size2[21]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[21]_energy_per_cycle param='mux_1level_tapbuf_size2[21]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[210] param='mux_1level_tapbuf_size2[21]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[210] param='dynamic_power_sb_mux[0][1]_rrnode[210]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[210] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_rise_sb_mux[0][1]_rrnode[210]' to='start_rise_sb_mux[0][1]_rrnode[210]+switch_rise_sb_mux[0][1]_rrnode[210]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[210] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_fall_sb_mux[0][1]_rrnode[210]' to='start_fall_sb_mux[0][1]_rrnode[210]+switch_fall_sb_mux[0][1]_rrnode[210]' -.meas tran sum_leakage_power_mux[0to21] -+ param='sum_leakage_power_mux[0to20]+leakage_sb_mux[0][1]_rrnode[210]' -.meas tran sum_energy_per_cycle_mux[0to21] -+ param='sum_energy_per_cycle_mux[0to20]+energy_per_cycle_sb_mux[0][1]_rrnode[210]' -***** Load for rr_node[210] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=13, type=5 ***** -Xchan_mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[47]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to21] -+ param='sum_leakage_power_sb_mux[0to20]+leakage_sb_mux[0][1]_rrnode[210]' -.meas tran sum_energy_per_cycle_sb_mux[0to21] -+ param='sum_energy_per_cycle_sb_mux[0to20]+energy_per_cycle_sb_mux[0][1]_rrnode[210]' -Xmux_1level_tapbuf_size2[22] mux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->out sram[30]->outb sram[30]->out gvdd_mux_1level_tapbuf_size2[22] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[22], level=1, select_path_id=0. ***** -*****1***** -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -***** Signal mux_1level_tapbuf_size2[22]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[22]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[22] gvdd_mux_1level_tapbuf_size2[22] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[212] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[212] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[212] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[212] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[212] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[212] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[212] param='mux_1level_tapbuf_size2[22]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[22]_energy_per_cycle param='mux_1level_tapbuf_size2[22]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[212] param='mux_1level_tapbuf_size2[22]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[212] param='dynamic_power_sb_mux[0][1]_rrnode[212]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[212] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_rise_sb_mux[0][1]_rrnode[212]' to='start_rise_sb_mux[0][1]_rrnode[212]+switch_rise_sb_mux[0][1]_rrnode[212]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[212] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_fall_sb_mux[0][1]_rrnode[212]' to='start_fall_sb_mux[0][1]_rrnode[212]+switch_fall_sb_mux[0][1]_rrnode[212]' -.meas tran sum_leakage_power_mux[0to22] -+ param='sum_leakage_power_mux[0to21]+leakage_sb_mux[0][1]_rrnode[212]' -.meas tran sum_energy_per_cycle_mux[0to22] -+ param='sum_energy_per_cycle_mux[0to21]+energy_per_cycle_sb_mux[0][1]_rrnode[212]' -***** Load for rr_node[212] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=15, type=5 ***** -Xchan_mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[49]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to22] -+ param='sum_leakage_power_sb_mux[0to21]+leakage_sb_mux[0][1]_rrnode[212]' -.meas tran sum_energy_per_cycle_sb_mux[0to22] -+ param='sum_energy_per_cycle_sb_mux[0to21]+energy_per_cycle_sb_mux[0][1]_rrnode[212]' -Xmux_1level_tapbuf_size2[23] mux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->out sram[31]->outb sram[31]->out gvdd_mux_1level_tapbuf_size2[23] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[23], level=1, select_path_id=0. ***** -*****1***** -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_1level_tapbuf_size2[23]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[23]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[23] gvdd_mux_1level_tapbuf_size2[23] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[214] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[214] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[214] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[214] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[214] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[214] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[214] param='mux_1level_tapbuf_size2[23]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[23]_energy_per_cycle param='mux_1level_tapbuf_size2[23]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[214] param='mux_1level_tapbuf_size2[23]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[214] param='dynamic_power_sb_mux[0][1]_rrnode[214]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[214] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_rise_sb_mux[0][1]_rrnode[214]' to='start_rise_sb_mux[0][1]_rrnode[214]+switch_rise_sb_mux[0][1]_rrnode[214]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[214] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_fall_sb_mux[0][1]_rrnode[214]' to='start_fall_sb_mux[0][1]_rrnode[214]+switch_fall_sb_mux[0][1]_rrnode[214]' -.meas tran sum_leakage_power_mux[0to23] -+ param='sum_leakage_power_mux[0to22]+leakage_sb_mux[0][1]_rrnode[214]' -.meas tran sum_energy_per_cycle_mux[0to23] -+ param='sum_energy_per_cycle_mux[0to22]+energy_per_cycle_sb_mux[0][1]_rrnode[214]' -***** Load for rr_node[214] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=17, type=5 ***** -Xchan_mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[51]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to23] -+ param='sum_leakage_power_sb_mux[0to22]+leakage_sb_mux[0][1]_rrnode[214]' -.meas tran sum_energy_per_cycle_sb_mux[0to23] -+ param='sum_energy_per_cycle_sb_mux[0to22]+energy_per_cycle_sb_mux[0][1]_rrnode[214]' -Xmux_1level_tapbuf_size2[24] mux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->out sram[32]->outb sram[32]->out gvdd_mux_1level_tapbuf_size2[24] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[24], level=1, select_path_id=0. ***** -*****1***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -***** Signal mux_1level_tapbuf_size2[24]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[24]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[24] gvdd_mux_1level_tapbuf_size2[24] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[216] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[216] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[216] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[216] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[216] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[216] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[216] param='mux_1level_tapbuf_size2[24]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[24]_energy_per_cycle param='mux_1level_tapbuf_size2[24]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[216] param='mux_1level_tapbuf_size2[24]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[216] param='dynamic_power_sb_mux[0][1]_rrnode[216]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[216] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_rise_sb_mux[0][1]_rrnode[216]' to='start_rise_sb_mux[0][1]_rrnode[216]+switch_rise_sb_mux[0][1]_rrnode[216]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[216] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_fall_sb_mux[0][1]_rrnode[216]' to='start_fall_sb_mux[0][1]_rrnode[216]+switch_fall_sb_mux[0][1]_rrnode[216]' -.meas tran sum_leakage_power_mux[0to24] -+ param='sum_leakage_power_mux[0to23]+leakage_sb_mux[0][1]_rrnode[216]' -.meas tran sum_energy_per_cycle_mux[0to24] -+ param='sum_energy_per_cycle_mux[0to23]+energy_per_cycle_sb_mux[0][1]_rrnode[216]' -***** Load for rr_node[216] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=19, type=5 ***** -Xchan_mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[53]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to24] -+ param='sum_leakage_power_sb_mux[0to23]+leakage_sb_mux[0][1]_rrnode[216]' -.meas tran sum_energy_per_cycle_sb_mux[0to24] -+ param='sum_energy_per_cycle_sb_mux[0to23]+energy_per_cycle_sb_mux[0][1]_rrnode[216]' -Xmux_1level_tapbuf_size2[25] mux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->out sram[33]->outb sram[33]->out gvdd_mux_1level_tapbuf_size2[25] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[25], level=1, select_path_id=0. ***** -*****1***** -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -***** Signal mux_1level_tapbuf_size2[25]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[25]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[25] gvdd_mux_1level_tapbuf_size2[25] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[218] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[218] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[218] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[218] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[218] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[218] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[218] param='mux_1level_tapbuf_size2[25]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[25]_energy_per_cycle param='mux_1level_tapbuf_size2[25]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[218] param='mux_1level_tapbuf_size2[25]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[218] param='dynamic_power_sb_mux[0][1]_rrnode[218]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[218] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_rise_sb_mux[0][1]_rrnode[218]' to='start_rise_sb_mux[0][1]_rrnode[218]+switch_rise_sb_mux[0][1]_rrnode[218]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[218] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_fall_sb_mux[0][1]_rrnode[218]' to='start_fall_sb_mux[0][1]_rrnode[218]+switch_fall_sb_mux[0][1]_rrnode[218]' -.meas tran sum_leakage_power_mux[0to25] -+ param='sum_leakage_power_mux[0to24]+leakage_sb_mux[0][1]_rrnode[218]' -.meas tran sum_energy_per_cycle_mux[0to25] -+ param='sum_energy_per_cycle_mux[0to24]+energy_per_cycle_sb_mux[0][1]_rrnode[218]' -***** Load for rr_node[218] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=21, type=5 ***** -Xchan_mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[55]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to25] -+ param='sum_leakage_power_sb_mux[0to24]+leakage_sb_mux[0][1]_rrnode[218]' -.meas tran sum_energy_per_cycle_sb_mux[0to25] -+ param='sum_energy_per_cycle_sb_mux[0to24]+energy_per_cycle_sb_mux[0][1]_rrnode[218]' -Xmux_1level_tapbuf_size2[26] mux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->out sram[34]->outb sram[34]->out gvdd_mux_1level_tapbuf_size2[26] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[26], level=1, select_path_id=0. ***** -*****1***** -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -***** Signal mux_1level_tapbuf_size2[26]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[26]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[26] gvdd_mux_1level_tapbuf_size2[26] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[220] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[220] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[220] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[220] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[220] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[220] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[220] param='mux_1level_tapbuf_size2[26]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[26]_energy_per_cycle param='mux_1level_tapbuf_size2[26]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[220] param='mux_1level_tapbuf_size2[26]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[220] param='dynamic_power_sb_mux[0][1]_rrnode[220]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[220] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_rise_sb_mux[0][1]_rrnode[220]' to='start_rise_sb_mux[0][1]_rrnode[220]+switch_rise_sb_mux[0][1]_rrnode[220]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[220] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_fall_sb_mux[0][1]_rrnode[220]' to='start_fall_sb_mux[0][1]_rrnode[220]+switch_fall_sb_mux[0][1]_rrnode[220]' -.meas tran sum_leakage_power_mux[0to26] -+ param='sum_leakage_power_mux[0to25]+leakage_sb_mux[0][1]_rrnode[220]' -.meas tran sum_energy_per_cycle_mux[0to26] -+ param='sum_energy_per_cycle_mux[0to25]+energy_per_cycle_sb_mux[0][1]_rrnode[220]' -***** Load for rr_node[220] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=23, type=5 ***** -Xchan_mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[57]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to26] -+ param='sum_leakage_power_sb_mux[0to25]+leakage_sb_mux[0][1]_rrnode[220]' -.meas tran sum_energy_per_cycle_sb_mux[0to26] -+ param='sum_energy_per_cycle_sb_mux[0to25]+energy_per_cycle_sb_mux[0][1]_rrnode[220]' -Xmux_1level_tapbuf_size2[27] mux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->out sram[35]->outb sram[35]->out gvdd_mux_1level_tapbuf_size2[27] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[27], level=1, select_path_id=0. ***** -*****1***** -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -***** Signal mux_1level_tapbuf_size2[27]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[27]->in[1] density = 0.1906, probability=0.5218.***** -Vmux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_1level_tapbuf_size2[27] gvdd_mux_1level_tapbuf_size2[27] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[222] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[222] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[222] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[222] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[222] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[222] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[222] param='mux_1level_tapbuf_size2[27]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size2[27]_energy_per_cycle param='mux_1level_tapbuf_size2[27]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[222] param='mux_1level_tapbuf_size2[27]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[222] param='dynamic_power_sb_mux[0][1]_rrnode[222]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[222] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_rise_sb_mux[0][1]_rrnode[222]' to='start_rise_sb_mux[0][1]_rrnode[222]+switch_rise_sb_mux[0][1]_rrnode[222]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[222] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_fall_sb_mux[0][1]_rrnode[222]' to='start_fall_sb_mux[0][1]_rrnode[222]+switch_fall_sb_mux[0][1]_rrnode[222]' -.meas tran sum_leakage_power_mux[0to27] -+ param='sum_leakage_power_mux[0to26]+leakage_sb_mux[0][1]_rrnode[222]' -.meas tran sum_energy_per_cycle_mux[0to27] -+ param='sum_energy_per_cycle_mux[0to26]+energy_per_cycle_sb_mux[0][1]_rrnode[222]' -***** Load for rr_node[222] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=25, type=5 ***** -Xchan_mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[59]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[60]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to27] -+ param='sum_leakage_power_sb_mux[0to26]+leakage_sb_mux[0][1]_rrnode[222]' -.meas tran sum_energy_per_cycle_sb_mux[0to27] -+ param='sum_energy_per_cycle_sb_mux[0to26]+energy_per_cycle_sb_mux[0][1]_rrnode[222]' -Xmux_1level_tapbuf_size2[28] mux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->out sram[36]->out sram[36]->outb gvdd_mux_1level_tapbuf_size2[28] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[28], level=1, select_path_id=1. ***** -*****0***** -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -***** Signal mux_1level_tapbuf_size2[28]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[28]->in[1] density = 0.1906, probability=0.4782.***** -Vmux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_1level_tapbuf_size2[28] gvdd_mux_1level_tapbuf_size2[28] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[224] trig v(mux_1level_tapbuf_size2[28]->in[1]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[224] trig v(mux_1level_tapbuf_size2[28]->in[1]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[224] when v(mux_1level_tapbuf_size2[28]->in[1])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[224] trig v(mux_1level_tapbuf_size2[28]->in[1]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[224] when v(mux_1level_tapbuf_size2[28]->in[1])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[224] trig v(mux_1level_tapbuf_size2[28]->in[1]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[224] param='mux_1level_tapbuf_size2[28]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size2[28]_energy_per_cycle param='mux_1level_tapbuf_size2[28]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[224] param='mux_1level_tapbuf_size2[28]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[224] param='dynamic_power_sb_mux[0][1]_rrnode[224]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[224] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_rise_sb_mux[0][1]_rrnode[224]' to='start_rise_sb_mux[0][1]_rrnode[224]+switch_rise_sb_mux[0][1]_rrnode[224]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[224] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_fall_sb_mux[0][1]_rrnode[224]' to='start_fall_sb_mux[0][1]_rrnode[224]+switch_fall_sb_mux[0][1]_rrnode[224]' -.meas tran sum_leakage_power_mux[0to28] -+ param='sum_leakage_power_mux[0to27]+leakage_sb_mux[0][1]_rrnode[224]' -.meas tran sum_energy_per_cycle_mux[0to28] -+ param='sum_energy_per_cycle_mux[0to27]+energy_per_cycle_sb_mux[0][1]_rrnode[224]' -***** Load for rr_node[224] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=27, type=5 ***** -Xchan_mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[61]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to28] -+ param='sum_leakage_power_sb_mux[0to27]+leakage_sb_mux[0][1]_rrnode[224]' -.meas tran sum_energy_per_cycle_sb_mux[0to28] -+ param='sum_energy_per_cycle_sb_mux[0to27]+energy_per_cycle_sb_mux[0][1]_rrnode[224]' -Xmux_1level_tapbuf_size2[29] mux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->out sram[37]->outb sram[37]->out gvdd_mux_1level_tapbuf_size2[29] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[29], level=1, select_path_id=0. ***** -*****1***** -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -***** Signal mux_1level_tapbuf_size2[29]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[29]->in[1] density = 0.1906, probability=0.4782.***** -Vmux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_1level_tapbuf_size2[29] gvdd_mux_1level_tapbuf_size2[29] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[226] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[226] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[226] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[226] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[226] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[226] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[226] param='mux_1level_tapbuf_size2[29]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size2[29]_energy_per_cycle param='mux_1level_tapbuf_size2[29]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[226] param='mux_1level_tapbuf_size2[29]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[226] param='dynamic_power_sb_mux[0][1]_rrnode[226]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[226] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_rise_sb_mux[0][1]_rrnode[226]' to='start_rise_sb_mux[0][1]_rrnode[226]+switch_rise_sb_mux[0][1]_rrnode[226]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[226] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_fall_sb_mux[0][1]_rrnode[226]' to='start_fall_sb_mux[0][1]_rrnode[226]+switch_fall_sb_mux[0][1]_rrnode[226]' -.meas tran sum_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to28]+leakage_sb_mux[0][1]_rrnode[226]' -.meas tran sum_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to28]+energy_per_cycle_sb_mux[0][1]_rrnode[226]' -***** Load for rr_node[226] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=29, type=5 ***** -Xchan_mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[64]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to29] -+ param='sum_leakage_power_sb_mux[0to28]+leakage_sb_mux[0][1]_rrnode[226]' -.meas tran sum_energy_per_cycle_sb_mux[0to29] -+ param='sum_energy_per_cycle_sb_mux[0to28]+energy_per_cycle_sb_mux[0][1]_rrnode[226]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='7*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to29]' -.meas tran total_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to29]' -.meas tran total_leakage_power_sb_mux -+ param='sum_leakage_power_sb_mux[0to29]' -.meas tran total_energy_per_cycle_sb_mux -+ param='sum_energy_per_cycle_sb_mux[0to29]' -.end diff --git a/examples/spice_test_example_1/sb_mux_tb/example_1_sb1_0_sbmux_testbench.sp b/examples/spice_test_example_1/sb_mux_tb/example_1_sb1_0_sbmux_testbench.sp deleted file mode 100644 index af8fb64ca..000000000 --- a/examples/spice_test_example_1/sb_mux_tb/example_1_sb1_0_sbmux_testbench.sp +++ /dev/null @@ -1,1638 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_1level_tapbuf_size3[0] mux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb gvdd_mux_1level_tapbuf_size3[0] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[0], level=1, select_path_id=0. ***** -*****100***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -***** Signal mux_1level_tapbuf_size3[0]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[0] gvdd_mux_1level_tapbuf_size3[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[227] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[227] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[227] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[227] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[227] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[227] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[227] param='mux_1level_tapbuf_size3[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[0]_energy_per_cycle param='mux_1level_tapbuf_size3[0]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[227] param='mux_1level_tapbuf_size3[0]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[227] param='dynamic_power_sb_mux[1][0]_rrnode[227]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[227] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_rise_sb_mux[1][0]_rrnode[227]' to='start_rise_sb_mux[1][0]_rrnode[227]+switch_rise_sb_mux[1][0]_rrnode[227]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[227] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_fall_sb_mux[1][0]_rrnode[227]' to='start_fall_sb_mux[1][0]_rrnode[227]+switch_fall_sb_mux[1][0]_rrnode[227]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_sb_mux[1][0]_rrnode[227]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_sb_mux[1][0]_rrnode[227]' -***** Load for rr_node[227] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=0, type=5 ***** -Xchan_mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to0] -+ param='leakage_sb_mux[1][0]_rrnode[227]' -.meas tran sum_energy_per_cycle_sb_mux[0to0] -+ param='energy_per_cycle_sb_mux[1][0]_rrnode[227]' -Xmux_1level_tapbuf_size2[1] mux_1level_tapbuf_size2[1]->in[0] mux_1level_tapbuf_size2[1]->in[1] mux_1level_tapbuf_size2[1]->out sram[3]->outb sram[3]->out gvdd_mux_1level_tapbuf_size2[1] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[1], level=1, select_path_id=0. ***** -*****1***** -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -***** Signal mux_1level_tapbuf_size2[1]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[1]->in[0] mux_1level_tapbuf_size2[1]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[1]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[1]->in[1] mux_1level_tapbuf_size2[1]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[1] gvdd_mux_1level_tapbuf_size2[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[229] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[229] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[229] when v(mux_1level_tapbuf_size2[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[229] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[229] when v(mux_1level_tapbuf_size2[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[229] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[1]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[229] param='mux_1level_tapbuf_size2[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[1]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[1]_energy_per_cycle param='mux_1level_tapbuf_size2[1]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[229] param='mux_1level_tapbuf_size2[1]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[229] param='dynamic_power_sb_mux[1][0]_rrnode[229]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[229] avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='start_rise_sb_mux[1][0]_rrnode[229]' to='start_rise_sb_mux[1][0]_rrnode[229]+switch_rise_sb_mux[1][0]_rrnode[229]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[229] avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='start_fall_sb_mux[1][0]_rrnode[229]' to='start_fall_sb_mux[1][0]_rrnode[229]+switch_fall_sb_mux[1][0]_rrnode[229]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_sb_mux[1][0]_rrnode[229]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_sb_mux[1][0]_rrnode[229]' -***** Load for rr_node[229] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=2, type=5 ***** -Xchan_mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to1] -+ param='sum_leakage_power_sb_mux[0to0]+leakage_sb_mux[1][0]_rrnode[229]' -.meas tran sum_energy_per_cycle_sb_mux[0to1] -+ param='sum_energy_per_cycle_sb_mux[0to0]+energy_per_cycle_sb_mux[1][0]_rrnode[229]' -Xmux_1level_tapbuf_size2[2] mux_1level_tapbuf_size2[2]->in[0] mux_1level_tapbuf_size2[2]->in[1] mux_1level_tapbuf_size2[2]->out sram[4]->outb sram[4]->out gvdd_mux_1level_tapbuf_size2[2] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[2], level=1, select_path_id=0. ***** -*****1***** -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -***** Signal mux_1level_tapbuf_size2[2]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[2]->in[0] mux_1level_tapbuf_size2[2]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[2]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[2]->in[1] mux_1level_tapbuf_size2[2]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[2] gvdd_mux_1level_tapbuf_size2[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[231] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[231] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[231] when v(mux_1level_tapbuf_size2[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[231] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[231] when v(mux_1level_tapbuf_size2[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[231] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[2]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[231] param='mux_1level_tapbuf_size2[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[2]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[2]_energy_per_cycle param='mux_1level_tapbuf_size2[2]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[231] param='mux_1level_tapbuf_size2[2]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[231] param='dynamic_power_sb_mux[1][0]_rrnode[231]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[231] avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='start_rise_sb_mux[1][0]_rrnode[231]' to='start_rise_sb_mux[1][0]_rrnode[231]+switch_rise_sb_mux[1][0]_rrnode[231]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[231] avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='start_fall_sb_mux[1][0]_rrnode[231]' to='start_fall_sb_mux[1][0]_rrnode[231]+switch_fall_sb_mux[1][0]_rrnode[231]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_sb_mux[1][0]_rrnode[231]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_sb_mux[1][0]_rrnode[231]' -***** Load for rr_node[231] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=4, type=5 ***** -Xchan_mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[3]_no0 mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to2] -+ param='sum_leakage_power_sb_mux[0to1]+leakage_sb_mux[1][0]_rrnode[231]' -.meas tran sum_energy_per_cycle_sb_mux[0to2] -+ param='sum_energy_per_cycle_sb_mux[0to1]+energy_per_cycle_sb_mux[1][0]_rrnode[231]' -Xmux_1level_tapbuf_size2[3] mux_1level_tapbuf_size2[3]->in[0] mux_1level_tapbuf_size2[3]->in[1] mux_1level_tapbuf_size2[3]->out sram[5]->outb sram[5]->out gvdd_mux_1level_tapbuf_size2[3] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[3], level=1, select_path_id=0. ***** -*****1***** -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -***** Signal mux_1level_tapbuf_size2[3]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[3]->in[0] mux_1level_tapbuf_size2[3]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[3]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[3]->in[1] mux_1level_tapbuf_size2[3]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[3] gvdd_mux_1level_tapbuf_size2[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[233] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[233] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[233] when v(mux_1level_tapbuf_size2[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[233] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[233] when v(mux_1level_tapbuf_size2[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[233] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[3]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[233] param='mux_1level_tapbuf_size2[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[3]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[3]_energy_per_cycle param='mux_1level_tapbuf_size2[3]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[233] param='mux_1level_tapbuf_size2[3]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[233] param='dynamic_power_sb_mux[1][0]_rrnode[233]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[233] avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='start_rise_sb_mux[1][0]_rrnode[233]' to='start_rise_sb_mux[1][0]_rrnode[233]+switch_rise_sb_mux[1][0]_rrnode[233]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[233] avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='start_fall_sb_mux[1][0]_rrnode[233]' to='start_fall_sb_mux[1][0]_rrnode[233]+switch_fall_sb_mux[1][0]_rrnode[233]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_sb_mux[1][0]_rrnode[233]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_sb_mux[1][0]_rrnode[233]' -***** Load for rr_node[233] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=6, type=5 ***** -Xchan_mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[4]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to3] -+ param='sum_leakage_power_sb_mux[0to2]+leakage_sb_mux[1][0]_rrnode[233]' -.meas tran sum_energy_per_cycle_sb_mux[0to3] -+ param='sum_energy_per_cycle_sb_mux[0to2]+energy_per_cycle_sb_mux[1][0]_rrnode[233]' -Xmux_1level_tapbuf_size2[4] mux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->out sram[6]->outb sram[6]->out gvdd_mux_1level_tapbuf_size2[4] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****1***** -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -***** Signal mux_1level_tapbuf_size2[4]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[4]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[4] gvdd_mux_1level_tapbuf_size2[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[235] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[235] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[235] when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[235] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[235] when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[235] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[235] param='mux_1level_tapbuf_size2[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[4]_energy_per_cycle param='mux_1level_tapbuf_size2[4]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[235] param='mux_1level_tapbuf_size2[4]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[235] param='dynamic_power_sb_mux[1][0]_rrnode[235]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[235] avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_rise_sb_mux[1][0]_rrnode[235]' to='start_rise_sb_mux[1][0]_rrnode[235]+switch_rise_sb_mux[1][0]_rrnode[235]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[235] avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_fall_sb_mux[1][0]_rrnode[235]' to='start_fall_sb_mux[1][0]_rrnode[235]+switch_fall_sb_mux[1][0]_rrnode[235]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_sb_mux[1][0]_rrnode[235]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_sb_mux[1][0]_rrnode[235]' -***** Load for rr_node[235] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=8, type=5 ***** -Xchan_mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[5]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to4] -+ param='sum_leakage_power_sb_mux[0to3]+leakage_sb_mux[1][0]_rrnode[235]' -.meas tran sum_energy_per_cycle_sb_mux[0to4] -+ param='sum_energy_per_cycle_sb_mux[0to3]+energy_per_cycle_sb_mux[1][0]_rrnode[235]' -Xmux_1level_tapbuf_size2[5] mux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->out sram[7]->outb sram[7]->out gvdd_mux_1level_tapbuf_size2[5] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[5], level=1, select_path_id=0. ***** -*****1***** -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_1level_tapbuf_size2[5]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[5]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[5] gvdd_mux_1level_tapbuf_size2[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[237] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[237] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[237] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[237] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[237] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[237] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[237] param='mux_1level_tapbuf_size2[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[5]_energy_per_cycle param='mux_1level_tapbuf_size2[5]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[237] param='mux_1level_tapbuf_size2[5]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[237] param='dynamic_power_sb_mux[1][0]_rrnode[237]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[237] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_rise_sb_mux[1][0]_rrnode[237]' to='start_rise_sb_mux[1][0]_rrnode[237]+switch_rise_sb_mux[1][0]_rrnode[237]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[237] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_fall_sb_mux[1][0]_rrnode[237]' to='start_fall_sb_mux[1][0]_rrnode[237]+switch_fall_sb_mux[1][0]_rrnode[237]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_sb_mux[1][0]_rrnode[237]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_sb_mux[1][0]_rrnode[237]' -***** Load for rr_node[237] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=10, type=5 ***** -Xchan_mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[6]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to5] -+ param='sum_leakage_power_sb_mux[0to4]+leakage_sb_mux[1][0]_rrnode[237]' -.meas tran sum_energy_per_cycle_sb_mux[0to5] -+ param='sum_energy_per_cycle_sb_mux[0to4]+energy_per_cycle_sb_mux[1][0]_rrnode[237]' -Xmux_1level_tapbuf_size2[6] mux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->out sram[8]->outb sram[8]->out gvdd_mux_1level_tapbuf_size2[6] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[6], level=1, select_path_id=0. ***** -*****1***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -***** Signal mux_1level_tapbuf_size2[6]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[6]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[6] gvdd_mux_1level_tapbuf_size2[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[239] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[239] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[239] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[239] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[239] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[239] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[239] param='mux_1level_tapbuf_size2[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[6]_energy_per_cycle param='mux_1level_tapbuf_size2[6]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[239] param='mux_1level_tapbuf_size2[6]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[239] param='dynamic_power_sb_mux[1][0]_rrnode[239]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[239] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_rise_sb_mux[1][0]_rrnode[239]' to='start_rise_sb_mux[1][0]_rrnode[239]+switch_rise_sb_mux[1][0]_rrnode[239]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[239] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_fall_sb_mux[1][0]_rrnode[239]' to='start_fall_sb_mux[1][0]_rrnode[239]+switch_fall_sb_mux[1][0]_rrnode[239]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_sb_mux[1][0]_rrnode[239]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_sb_mux[1][0]_rrnode[239]' -***** Load for rr_node[239] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=12, type=5 ***** -Xchan_mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[7]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to6] -+ param='sum_leakage_power_sb_mux[0to5]+leakage_sb_mux[1][0]_rrnode[239]' -.meas tran sum_energy_per_cycle_sb_mux[0to6] -+ param='sum_energy_per_cycle_sb_mux[0to5]+energy_per_cycle_sb_mux[1][0]_rrnode[239]' -Xmux_1level_tapbuf_size2[7] mux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->out sram[9]->outb sram[9]->out gvdd_mux_1level_tapbuf_size2[7] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[7], level=1, select_path_id=0. ***** -*****1***** -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -***** Signal mux_1level_tapbuf_size2[7]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[7]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[7] gvdd_mux_1level_tapbuf_size2[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[241] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[241] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[241] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[241] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[241] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[241] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[241] param='mux_1level_tapbuf_size2[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[7]_energy_per_cycle param='mux_1level_tapbuf_size2[7]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[241] param='mux_1level_tapbuf_size2[7]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[241] param='dynamic_power_sb_mux[1][0]_rrnode[241]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[241] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_rise_sb_mux[1][0]_rrnode[241]' to='start_rise_sb_mux[1][0]_rrnode[241]+switch_rise_sb_mux[1][0]_rrnode[241]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[241] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_fall_sb_mux[1][0]_rrnode[241]' to='start_fall_sb_mux[1][0]_rrnode[241]+switch_fall_sb_mux[1][0]_rrnode[241]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_sb_mux[1][0]_rrnode[241]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_sb_mux[1][0]_rrnode[241]' -***** Load for rr_node[241] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=14, type=5 ***** -Xchan_mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[8]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to7] -+ param='sum_leakage_power_sb_mux[0to6]+leakage_sb_mux[1][0]_rrnode[241]' -.meas tran sum_energy_per_cycle_sb_mux[0to7] -+ param='sum_energy_per_cycle_sb_mux[0to6]+energy_per_cycle_sb_mux[1][0]_rrnode[241]' -Xmux_1level_tapbuf_size2[8] mux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->out sram[10]->outb sram[10]->out gvdd_mux_1level_tapbuf_size2[8] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[8], level=1, select_path_id=0. ***** -*****1***** -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -***** Signal mux_1level_tapbuf_size2[8]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[8]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[8] gvdd_mux_1level_tapbuf_size2[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[243] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[243] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[243] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[243] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[243] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[243] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[243] param='mux_1level_tapbuf_size2[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[8]_energy_per_cycle param='mux_1level_tapbuf_size2[8]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[243] param='mux_1level_tapbuf_size2[8]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[243] param='dynamic_power_sb_mux[1][0]_rrnode[243]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[243] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_rise_sb_mux[1][0]_rrnode[243]' to='start_rise_sb_mux[1][0]_rrnode[243]+switch_rise_sb_mux[1][0]_rrnode[243]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[243] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_fall_sb_mux[1][0]_rrnode[243]' to='start_fall_sb_mux[1][0]_rrnode[243]+switch_fall_sb_mux[1][0]_rrnode[243]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_sb_mux[1][0]_rrnode[243]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_sb_mux[1][0]_rrnode[243]' -***** Load for rr_node[243] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=16, type=5 ***** -Xchan_mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[9]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to8] -+ param='sum_leakage_power_sb_mux[0to7]+leakage_sb_mux[1][0]_rrnode[243]' -.meas tran sum_energy_per_cycle_sb_mux[0to8] -+ param='sum_energy_per_cycle_sb_mux[0to7]+energy_per_cycle_sb_mux[1][0]_rrnode[243]' -Xmux_1level_tapbuf_size2[9] mux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->out sram[11]->outb sram[11]->out gvdd_mux_1level_tapbuf_size2[9] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[9], level=1, select_path_id=0. ***** -*****1***** -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_1level_tapbuf_size2[9]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[9]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[9] gvdd_mux_1level_tapbuf_size2[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[245] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[245] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[245] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[245] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[245] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[245] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[245] param='mux_1level_tapbuf_size2[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[9]_energy_per_cycle param='mux_1level_tapbuf_size2[9]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[245] param='mux_1level_tapbuf_size2[9]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[245] param='dynamic_power_sb_mux[1][0]_rrnode[245]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[245] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_rise_sb_mux[1][0]_rrnode[245]' to='start_rise_sb_mux[1][0]_rrnode[245]+switch_rise_sb_mux[1][0]_rrnode[245]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[245] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_fall_sb_mux[1][0]_rrnode[245]' to='start_fall_sb_mux[1][0]_rrnode[245]+switch_fall_sb_mux[1][0]_rrnode[245]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_sb_mux[1][0]_rrnode[245]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_sb_mux[1][0]_rrnode[245]' -***** Load for rr_node[245] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=18, type=5 ***** -Xchan_mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[11]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to9] -+ param='sum_leakage_power_sb_mux[0to8]+leakage_sb_mux[1][0]_rrnode[245]' -.meas tran sum_energy_per_cycle_sb_mux[0to9] -+ param='sum_energy_per_cycle_sb_mux[0to8]+energy_per_cycle_sb_mux[1][0]_rrnode[245]' -Xmux_1level_tapbuf_size2[10] mux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->out sram[12]->outb sram[12]->out gvdd_mux_1level_tapbuf_size2[10] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[10], level=1, select_path_id=0. ***** -*****1***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -***** Signal mux_1level_tapbuf_size2[10]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[10]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[10] gvdd_mux_1level_tapbuf_size2[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[247] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[247] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[247] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[247] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[247] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[247] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[247] param='mux_1level_tapbuf_size2[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[10]_energy_per_cycle param='mux_1level_tapbuf_size2[10]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[247] param='mux_1level_tapbuf_size2[10]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[247] param='dynamic_power_sb_mux[1][0]_rrnode[247]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[247] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_rise_sb_mux[1][0]_rrnode[247]' to='start_rise_sb_mux[1][0]_rrnode[247]+switch_rise_sb_mux[1][0]_rrnode[247]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[247] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_fall_sb_mux[1][0]_rrnode[247]' to='start_fall_sb_mux[1][0]_rrnode[247]+switch_fall_sb_mux[1][0]_rrnode[247]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_sb_mux[1][0]_rrnode[247]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_sb_mux[1][0]_rrnode[247]' -***** Load for rr_node[247] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=20, type=5 ***** -Xchan_mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[12]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to10] -+ param='sum_leakage_power_sb_mux[0to9]+leakage_sb_mux[1][0]_rrnode[247]' -.meas tran sum_energy_per_cycle_sb_mux[0to10] -+ param='sum_energy_per_cycle_sb_mux[0to9]+energy_per_cycle_sb_mux[1][0]_rrnode[247]' -Xmux_1level_tapbuf_size2[11] mux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->out sram[13]->outb sram[13]->out gvdd_mux_1level_tapbuf_size2[11] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[11], level=1, select_path_id=0. ***** -*****1***** -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -***** Signal mux_1level_tapbuf_size2[11]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[11]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[11] gvdd_mux_1level_tapbuf_size2[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[249] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[249] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[249] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[249] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[249] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[249] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[249] param='mux_1level_tapbuf_size2[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[11]_energy_per_cycle param='mux_1level_tapbuf_size2[11]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[249] param='mux_1level_tapbuf_size2[11]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[249] param='dynamic_power_sb_mux[1][0]_rrnode[249]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[249] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_rise_sb_mux[1][0]_rrnode[249]' to='start_rise_sb_mux[1][0]_rrnode[249]+switch_rise_sb_mux[1][0]_rrnode[249]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[249] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_fall_sb_mux[1][0]_rrnode[249]' to='start_fall_sb_mux[1][0]_rrnode[249]+switch_fall_sb_mux[1][0]_rrnode[249]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_sb_mux[1][0]_rrnode[249]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_sb_mux[1][0]_rrnode[249]' -***** Load for rr_node[249] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=22, type=5 ***** -Xchan_mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[13]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to11] -+ param='sum_leakage_power_sb_mux[0to10]+leakage_sb_mux[1][0]_rrnode[249]' -.meas tran sum_energy_per_cycle_sb_mux[0to11] -+ param='sum_energy_per_cycle_sb_mux[0to10]+energy_per_cycle_sb_mux[1][0]_rrnode[249]' -Xmux_1level_tapbuf_size2[12] mux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->out sram[14]->outb sram[14]->out gvdd_mux_1level_tapbuf_size2[12] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[12], level=1, select_path_id=0. ***** -*****1***** -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -***** Signal mux_1level_tapbuf_size2[12]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[12]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[12] gvdd_mux_1level_tapbuf_size2[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[251] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[251] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[251] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[251] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[251] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[251] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[251] param='mux_1level_tapbuf_size2[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[12]_energy_per_cycle param='mux_1level_tapbuf_size2[12]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[251] param='mux_1level_tapbuf_size2[12]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[251] param='dynamic_power_sb_mux[1][0]_rrnode[251]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[251] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_rise_sb_mux[1][0]_rrnode[251]' to='start_rise_sb_mux[1][0]_rrnode[251]+switch_rise_sb_mux[1][0]_rrnode[251]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[251] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_fall_sb_mux[1][0]_rrnode[251]' to='start_fall_sb_mux[1][0]_rrnode[251]+switch_fall_sb_mux[1][0]_rrnode[251]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_sb_mux[1][0]_rrnode[251]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_sb_mux[1][0]_rrnode[251]' -***** Load for rr_node[251] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=24, type=5 ***** -Xchan_mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[14]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to12] -+ param='sum_leakage_power_sb_mux[0to11]+leakage_sb_mux[1][0]_rrnode[251]' -.meas tran sum_energy_per_cycle_sb_mux[0to12] -+ param='sum_energy_per_cycle_sb_mux[0to11]+energy_per_cycle_sb_mux[1][0]_rrnode[251]' -Xmux_1level_tapbuf_size2[13] mux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->out sram[15]->outb sram[15]->out gvdd_mux_1level_tapbuf_size2[13] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[13], level=1, select_path_id=0. ***** -*****1***** -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_1level_tapbuf_size2[13]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[13]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[13] gvdd_mux_1level_tapbuf_size2[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[253] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[253] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[253] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[253] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[253] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[253] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[253] param='mux_1level_tapbuf_size2[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[13]_energy_per_cycle param='mux_1level_tapbuf_size2[13]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[253] param='mux_1level_tapbuf_size2[13]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[253] param='dynamic_power_sb_mux[1][0]_rrnode[253]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[253] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_rise_sb_mux[1][0]_rrnode[253]' to='start_rise_sb_mux[1][0]_rrnode[253]+switch_rise_sb_mux[1][0]_rrnode[253]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[253] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_fall_sb_mux[1][0]_rrnode[253]' to='start_fall_sb_mux[1][0]_rrnode[253]+switch_fall_sb_mux[1][0]_rrnode[253]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_sb_mux[1][0]_rrnode[253]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_sb_mux[1][0]_rrnode[253]' -***** Load for rr_node[253] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=26, type=5 ***** -Xchan_mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[15]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to13] -+ param='sum_leakage_power_sb_mux[0to12]+leakage_sb_mux[1][0]_rrnode[253]' -.meas tran sum_energy_per_cycle_sb_mux[0to13] -+ param='sum_energy_per_cycle_sb_mux[0to12]+energy_per_cycle_sb_mux[1][0]_rrnode[253]' -Xmux_1level_tapbuf_size2[14] mux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->out sram[16]->outb sram[16]->out gvdd_mux_1level_tapbuf_size2[14] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[14], level=1, select_path_id=0. ***** -*****1***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -***** Signal mux_1level_tapbuf_size2[14]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[14]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[14] gvdd_mux_1level_tapbuf_size2[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[255] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[255] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[255] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[255] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[255] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[255] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[255] param='mux_1level_tapbuf_size2[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[14]_energy_per_cycle param='mux_1level_tapbuf_size2[14]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[255] param='mux_1level_tapbuf_size2[14]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[255] param='dynamic_power_sb_mux[1][0]_rrnode[255]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[255] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_rise_sb_mux[1][0]_rrnode[255]' to='start_rise_sb_mux[1][0]_rrnode[255]+switch_rise_sb_mux[1][0]_rrnode[255]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[255] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_fall_sb_mux[1][0]_rrnode[255]' to='start_fall_sb_mux[1][0]_rrnode[255]+switch_fall_sb_mux[1][0]_rrnode[255]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_sb_mux[1][0]_rrnode[255]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_sb_mux[1][0]_rrnode[255]' -***** Load for rr_node[255] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=28, type=5 ***** -Xchan_mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[16]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to14] -+ param='sum_leakage_power_sb_mux[0to13]+leakage_sb_mux[1][0]_rrnode[255]' -.meas tran sum_energy_per_cycle_sb_mux[0to14] -+ param='sum_energy_per_cycle_sb_mux[0to13]+energy_per_cycle_sb_mux[1][0]_rrnode[255]' -Xmux_1level_tapbuf_size3[15] mux_1level_tapbuf_size3[15]->in[0] mux_1level_tapbuf_size3[15]->in[1] mux_1level_tapbuf_size3[15]->in[2] mux_1level_tapbuf_size3[15]->out sram[17]->outb sram[17]->out sram[18]->out sram[18]->outb sram[19]->out sram[19]->outb gvdd_mux_1level_tapbuf_size3[15] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[15], level=1, select_path_id=0. ***** -*****100***** -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_1level_tapbuf_size3[15]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[15]->in[0] mux_1level_tapbuf_size3[15]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[15]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[15]->in[1] mux_1level_tapbuf_size3[15]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[15]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[15]->in[2] mux_1level_tapbuf_size3[15]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[15] gvdd_mux_1level_tapbuf_size3[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[138] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[138] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[138] when v(mux_1level_tapbuf_size3[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[138] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[138] when v(mux_1level_tapbuf_size3[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[138] trig v(mux_1level_tapbuf_size3[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[15]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[138] param='mux_1level_tapbuf_size3[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[15]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[15]_energy_per_cycle param='mux_1level_tapbuf_size3[15]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[138] param='mux_1level_tapbuf_size3[15]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[138] param='dynamic_power_sb_mux[1][0]_rrnode[138]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[138] avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='start_rise_sb_mux[1][0]_rrnode[138]' to='start_rise_sb_mux[1][0]_rrnode[138]+switch_rise_sb_mux[1][0]_rrnode[138]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[138] avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='start_fall_sb_mux[1][0]_rrnode[138]' to='start_fall_sb_mux[1][0]_rrnode[138]+switch_fall_sb_mux[1][0]_rrnode[138]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_sb_mux[1][0]_rrnode[138]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_sb_mux[1][0]_rrnode[138]' -***** Load for rr_node[138] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=1, type=4 ***** -Xchan_mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[17]_no0 mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to15] -+ param='sum_leakage_power_sb_mux[0to14]+leakage_sb_mux[1][0]_rrnode[138]' -.meas tran sum_energy_per_cycle_sb_mux[0to15] -+ param='sum_energy_per_cycle_sb_mux[0to14]+energy_per_cycle_sb_mux[1][0]_rrnode[138]' -Xmux_1level_tapbuf_size2[16] mux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->out sram[20]->outb sram[20]->out gvdd_mux_1level_tapbuf_size2[16] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[16], level=1, select_path_id=0. ***** -*****1***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -***** Signal mux_1level_tapbuf_size2[16]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[16]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[16] gvdd_mux_1level_tapbuf_size2[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[140] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[140] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[140] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[140] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[140] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[140] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[140] param='mux_1level_tapbuf_size2[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[16]_energy_per_cycle param='mux_1level_tapbuf_size2[16]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[140] param='mux_1level_tapbuf_size2[16]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[140] param='dynamic_power_sb_mux[1][0]_rrnode[140]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[140] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_rise_sb_mux[1][0]_rrnode[140]' to='start_rise_sb_mux[1][0]_rrnode[140]+switch_rise_sb_mux[1][0]_rrnode[140]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[140] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_fall_sb_mux[1][0]_rrnode[140]' to='start_fall_sb_mux[1][0]_rrnode[140]+switch_fall_sb_mux[1][0]_rrnode[140]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_sb_mux[1][0]_rrnode[140]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_sb_mux[1][0]_rrnode[140]' -***** Load for rr_node[140] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=3, type=4 ***** -Xchan_mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[20]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to16] -+ param='sum_leakage_power_sb_mux[0to15]+leakage_sb_mux[1][0]_rrnode[140]' -.meas tran sum_energy_per_cycle_sb_mux[0to16] -+ param='sum_energy_per_cycle_sb_mux[0to15]+energy_per_cycle_sb_mux[1][0]_rrnode[140]' -Xmux_1level_tapbuf_size2[17] mux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->out sram[21]->outb sram[21]->out gvdd_mux_1level_tapbuf_size2[17] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[17], level=1, select_path_id=0. ***** -*****1***** -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -***** Signal mux_1level_tapbuf_size2[17]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[17]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[17] gvdd_mux_1level_tapbuf_size2[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[142] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[142] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[142] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[142] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[142] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[142] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[142] param='mux_1level_tapbuf_size2[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[17]_energy_per_cycle param='mux_1level_tapbuf_size2[17]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[142] param='mux_1level_tapbuf_size2[17]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[142] param='dynamic_power_sb_mux[1][0]_rrnode[142]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[142] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_rise_sb_mux[1][0]_rrnode[142]' to='start_rise_sb_mux[1][0]_rrnode[142]+switch_rise_sb_mux[1][0]_rrnode[142]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[142] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_fall_sb_mux[1][0]_rrnode[142]' to='start_fall_sb_mux[1][0]_rrnode[142]+switch_fall_sb_mux[1][0]_rrnode[142]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_sb_mux[1][0]_rrnode[142]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_sb_mux[1][0]_rrnode[142]' -***** Load for rr_node[142] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=5, type=4 ***** -Xchan_mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[22]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to17] -+ param='sum_leakage_power_sb_mux[0to16]+leakage_sb_mux[1][0]_rrnode[142]' -.meas tran sum_energy_per_cycle_sb_mux[0to17] -+ param='sum_energy_per_cycle_sb_mux[0to16]+energy_per_cycle_sb_mux[1][0]_rrnode[142]' -Xmux_1level_tapbuf_size2[18] mux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->out sram[22]->outb sram[22]->out gvdd_mux_1level_tapbuf_size2[18] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[18], level=1, select_path_id=0. ***** -*****1***** -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -***** Signal mux_1level_tapbuf_size2[18]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[18]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[18] gvdd_mux_1level_tapbuf_size2[18] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[144] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[144] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[144] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[144] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[144] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[144] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[144] param='mux_1level_tapbuf_size2[18]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[18]_energy_per_cycle param='mux_1level_tapbuf_size2[18]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[144] param='mux_1level_tapbuf_size2[18]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[144] param='dynamic_power_sb_mux[1][0]_rrnode[144]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[144] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_rise_sb_mux[1][0]_rrnode[144]' to='start_rise_sb_mux[1][0]_rrnode[144]+switch_rise_sb_mux[1][0]_rrnode[144]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[144] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_fall_sb_mux[1][0]_rrnode[144]' to='start_fall_sb_mux[1][0]_rrnode[144]+switch_fall_sb_mux[1][0]_rrnode[144]' -.meas tran sum_leakage_power_mux[0to18] -+ param='sum_leakage_power_mux[0to17]+leakage_sb_mux[1][0]_rrnode[144]' -.meas tran sum_energy_per_cycle_mux[0to18] -+ param='sum_energy_per_cycle_mux[0to17]+energy_per_cycle_sb_mux[1][0]_rrnode[144]' -***** Load for rr_node[144] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=7, type=4 ***** -Xchan_mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[24]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to18] -+ param='sum_leakage_power_sb_mux[0to17]+leakage_sb_mux[1][0]_rrnode[144]' -.meas tran sum_energy_per_cycle_sb_mux[0to18] -+ param='sum_energy_per_cycle_sb_mux[0to17]+energy_per_cycle_sb_mux[1][0]_rrnode[144]' -Xmux_1level_tapbuf_size2[19] mux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->out sram[23]->outb sram[23]->out gvdd_mux_1level_tapbuf_size2[19] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[19], level=1, select_path_id=0. ***** -*****1***** -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_1level_tapbuf_size2[19]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[19]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[19] gvdd_mux_1level_tapbuf_size2[19] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[146] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[146] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[146] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[146] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[146] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[146] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[146] param='mux_1level_tapbuf_size2[19]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[19]_energy_per_cycle param='mux_1level_tapbuf_size2[19]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[146] param='mux_1level_tapbuf_size2[19]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[146] param='dynamic_power_sb_mux[1][0]_rrnode[146]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[146] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_rise_sb_mux[1][0]_rrnode[146]' to='start_rise_sb_mux[1][0]_rrnode[146]+switch_rise_sb_mux[1][0]_rrnode[146]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[146] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_fall_sb_mux[1][0]_rrnode[146]' to='start_fall_sb_mux[1][0]_rrnode[146]+switch_fall_sb_mux[1][0]_rrnode[146]' -.meas tran sum_leakage_power_mux[0to19] -+ param='sum_leakage_power_mux[0to18]+leakage_sb_mux[1][0]_rrnode[146]' -.meas tran sum_energy_per_cycle_mux[0to19] -+ param='sum_energy_per_cycle_mux[0to18]+energy_per_cycle_sb_mux[1][0]_rrnode[146]' -***** Load for rr_node[146] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=9, type=4 ***** -Xchan_mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[27]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to19] -+ param='sum_leakage_power_sb_mux[0to18]+leakage_sb_mux[1][0]_rrnode[146]' -.meas tran sum_energy_per_cycle_sb_mux[0to19] -+ param='sum_energy_per_cycle_sb_mux[0to18]+energy_per_cycle_sb_mux[1][0]_rrnode[146]' -Xmux_1level_tapbuf_size2[20] mux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->out sram[24]->outb sram[24]->out gvdd_mux_1level_tapbuf_size2[20] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[20], level=1, select_path_id=0. ***** -*****1***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -***** Signal mux_1level_tapbuf_size2[20]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[20]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[20] gvdd_mux_1level_tapbuf_size2[20] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[148] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[148] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[148] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[148] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[148] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[148] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[148] param='mux_1level_tapbuf_size2[20]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[20]_energy_per_cycle param='mux_1level_tapbuf_size2[20]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[148] param='mux_1level_tapbuf_size2[20]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[148] param='dynamic_power_sb_mux[1][0]_rrnode[148]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[148] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_rise_sb_mux[1][0]_rrnode[148]' to='start_rise_sb_mux[1][0]_rrnode[148]+switch_rise_sb_mux[1][0]_rrnode[148]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[148] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_fall_sb_mux[1][0]_rrnode[148]' to='start_fall_sb_mux[1][0]_rrnode[148]+switch_fall_sb_mux[1][0]_rrnode[148]' -.meas tran sum_leakage_power_mux[0to20] -+ param='sum_leakage_power_mux[0to19]+leakage_sb_mux[1][0]_rrnode[148]' -.meas tran sum_energy_per_cycle_mux[0to20] -+ param='sum_energy_per_cycle_mux[0to19]+energy_per_cycle_sb_mux[1][0]_rrnode[148]' -***** Load for rr_node[148] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=11, type=4 ***** -Xchan_mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[29]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to20] -+ param='sum_leakage_power_sb_mux[0to19]+leakage_sb_mux[1][0]_rrnode[148]' -.meas tran sum_energy_per_cycle_sb_mux[0to20] -+ param='sum_energy_per_cycle_sb_mux[0to19]+energy_per_cycle_sb_mux[1][0]_rrnode[148]' -Xmux_1level_tapbuf_size2[21] mux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->out sram[25]->outb sram[25]->out gvdd_mux_1level_tapbuf_size2[21] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[21], level=1, select_path_id=0. ***** -*****1***** -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -***** Signal mux_1level_tapbuf_size2[21]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[21]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[21] gvdd_mux_1level_tapbuf_size2[21] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[150] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[150] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[150] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[150] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[150] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[150] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[150] param='mux_1level_tapbuf_size2[21]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[21]_energy_per_cycle param='mux_1level_tapbuf_size2[21]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[150] param='mux_1level_tapbuf_size2[21]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[150] param='dynamic_power_sb_mux[1][0]_rrnode[150]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[150] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_rise_sb_mux[1][0]_rrnode[150]' to='start_rise_sb_mux[1][0]_rrnode[150]+switch_rise_sb_mux[1][0]_rrnode[150]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[150] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_fall_sb_mux[1][0]_rrnode[150]' to='start_fall_sb_mux[1][0]_rrnode[150]+switch_fall_sb_mux[1][0]_rrnode[150]' -.meas tran sum_leakage_power_mux[0to21] -+ param='sum_leakage_power_mux[0to20]+leakage_sb_mux[1][0]_rrnode[150]' -.meas tran sum_energy_per_cycle_mux[0to21] -+ param='sum_energy_per_cycle_mux[0to20]+energy_per_cycle_sb_mux[1][0]_rrnode[150]' -***** Load for rr_node[150] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=13, type=4 ***** -Xchan_mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[31]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to21] -+ param='sum_leakage_power_sb_mux[0to20]+leakage_sb_mux[1][0]_rrnode[150]' -.meas tran sum_energy_per_cycle_sb_mux[0to21] -+ param='sum_energy_per_cycle_sb_mux[0to20]+energy_per_cycle_sb_mux[1][0]_rrnode[150]' -Xmux_1level_tapbuf_size2[22] mux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->out sram[26]->outb sram[26]->out gvdd_mux_1level_tapbuf_size2[22] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[22], level=1, select_path_id=0. ***** -*****1***** -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -***** Signal mux_1level_tapbuf_size2[22]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[22]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[22] gvdd_mux_1level_tapbuf_size2[22] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[152] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[152] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[152] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[152] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[152] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[152] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[152] param='mux_1level_tapbuf_size2[22]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[22]_energy_per_cycle param='mux_1level_tapbuf_size2[22]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[152] param='mux_1level_tapbuf_size2[22]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[152] param='dynamic_power_sb_mux[1][0]_rrnode[152]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[152] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_rise_sb_mux[1][0]_rrnode[152]' to='start_rise_sb_mux[1][0]_rrnode[152]+switch_rise_sb_mux[1][0]_rrnode[152]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[152] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_fall_sb_mux[1][0]_rrnode[152]' to='start_fall_sb_mux[1][0]_rrnode[152]+switch_fall_sb_mux[1][0]_rrnode[152]' -.meas tran sum_leakage_power_mux[0to22] -+ param='sum_leakage_power_mux[0to21]+leakage_sb_mux[1][0]_rrnode[152]' -.meas tran sum_energy_per_cycle_mux[0to22] -+ param='sum_energy_per_cycle_mux[0to21]+energy_per_cycle_sb_mux[1][0]_rrnode[152]' -***** Load for rr_node[152] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=15, type=4 ***** -Xchan_mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[33]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to22] -+ param='sum_leakage_power_sb_mux[0to21]+leakage_sb_mux[1][0]_rrnode[152]' -.meas tran sum_energy_per_cycle_sb_mux[0to22] -+ param='sum_energy_per_cycle_sb_mux[0to21]+energy_per_cycle_sb_mux[1][0]_rrnode[152]' -Xmux_1level_tapbuf_size2[23] mux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->out sram[27]->outb sram[27]->out gvdd_mux_1level_tapbuf_size2[23] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[23], level=1, select_path_id=0. ***** -*****1***** -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_1level_tapbuf_size2[23]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[23]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[23] gvdd_mux_1level_tapbuf_size2[23] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[154] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[154] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[154] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[154] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[154] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[154] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[154] param='mux_1level_tapbuf_size2[23]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[23]_energy_per_cycle param='mux_1level_tapbuf_size2[23]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[154] param='mux_1level_tapbuf_size2[23]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[154] param='dynamic_power_sb_mux[1][0]_rrnode[154]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[154] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_rise_sb_mux[1][0]_rrnode[154]' to='start_rise_sb_mux[1][0]_rrnode[154]+switch_rise_sb_mux[1][0]_rrnode[154]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[154] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_fall_sb_mux[1][0]_rrnode[154]' to='start_fall_sb_mux[1][0]_rrnode[154]+switch_fall_sb_mux[1][0]_rrnode[154]' -.meas tran sum_leakage_power_mux[0to23] -+ param='sum_leakage_power_mux[0to22]+leakage_sb_mux[1][0]_rrnode[154]' -.meas tran sum_energy_per_cycle_mux[0to23] -+ param='sum_energy_per_cycle_mux[0to22]+energy_per_cycle_sb_mux[1][0]_rrnode[154]' -***** Load for rr_node[154] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=17, type=4 ***** -Xchan_mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[35]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to23] -+ param='sum_leakage_power_sb_mux[0to22]+leakage_sb_mux[1][0]_rrnode[154]' -.meas tran sum_energy_per_cycle_sb_mux[0to23] -+ param='sum_energy_per_cycle_sb_mux[0to22]+energy_per_cycle_sb_mux[1][0]_rrnode[154]' -Xmux_1level_tapbuf_size2[24] mux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->out sram[28]->outb sram[28]->out gvdd_mux_1level_tapbuf_size2[24] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[24], level=1, select_path_id=0. ***** -*****1***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -***** Signal mux_1level_tapbuf_size2[24]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[24]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[24] gvdd_mux_1level_tapbuf_size2[24] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[156] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[156] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[156] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[156] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[156] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[156] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[156] param='mux_1level_tapbuf_size2[24]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[24]_energy_per_cycle param='mux_1level_tapbuf_size2[24]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[156] param='mux_1level_tapbuf_size2[24]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[156] param='dynamic_power_sb_mux[1][0]_rrnode[156]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[156] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_rise_sb_mux[1][0]_rrnode[156]' to='start_rise_sb_mux[1][0]_rrnode[156]+switch_rise_sb_mux[1][0]_rrnode[156]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[156] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_fall_sb_mux[1][0]_rrnode[156]' to='start_fall_sb_mux[1][0]_rrnode[156]+switch_fall_sb_mux[1][0]_rrnode[156]' -.meas tran sum_leakage_power_mux[0to24] -+ param='sum_leakage_power_mux[0to23]+leakage_sb_mux[1][0]_rrnode[156]' -.meas tran sum_energy_per_cycle_mux[0to24] -+ param='sum_energy_per_cycle_mux[0to23]+energy_per_cycle_sb_mux[1][0]_rrnode[156]' -***** Load for rr_node[156] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=19, type=4 ***** -Xchan_mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[37]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to24] -+ param='sum_leakage_power_sb_mux[0to23]+leakage_sb_mux[1][0]_rrnode[156]' -.meas tran sum_energy_per_cycle_sb_mux[0to24] -+ param='sum_energy_per_cycle_sb_mux[0to23]+energy_per_cycle_sb_mux[1][0]_rrnode[156]' -Xmux_1level_tapbuf_size2[25] mux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->out sram[29]->outb sram[29]->out gvdd_mux_1level_tapbuf_size2[25] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[25], level=1, select_path_id=0. ***** -*****1***** -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -***** Signal mux_1level_tapbuf_size2[25]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[25]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[25] gvdd_mux_1level_tapbuf_size2[25] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[158] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[158] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[158] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[158] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[158] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[158] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[158] param='mux_1level_tapbuf_size2[25]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[25]_energy_per_cycle param='mux_1level_tapbuf_size2[25]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[158] param='mux_1level_tapbuf_size2[25]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[158] param='dynamic_power_sb_mux[1][0]_rrnode[158]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[158] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_rise_sb_mux[1][0]_rrnode[158]' to='start_rise_sb_mux[1][0]_rrnode[158]+switch_rise_sb_mux[1][0]_rrnode[158]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[158] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_fall_sb_mux[1][0]_rrnode[158]' to='start_fall_sb_mux[1][0]_rrnode[158]+switch_fall_sb_mux[1][0]_rrnode[158]' -.meas tran sum_leakage_power_mux[0to25] -+ param='sum_leakage_power_mux[0to24]+leakage_sb_mux[1][0]_rrnode[158]' -.meas tran sum_energy_per_cycle_mux[0to25] -+ param='sum_energy_per_cycle_mux[0to24]+energy_per_cycle_sb_mux[1][0]_rrnode[158]' -***** Load for rr_node[158] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=21, type=4 ***** -Xchan_mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[39]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to25] -+ param='sum_leakage_power_sb_mux[0to24]+leakage_sb_mux[1][0]_rrnode[158]' -.meas tran sum_energy_per_cycle_sb_mux[0to25] -+ param='sum_energy_per_cycle_sb_mux[0to24]+energy_per_cycle_sb_mux[1][0]_rrnode[158]' -Xmux_1level_tapbuf_size2[26] mux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->out sram[30]->outb sram[30]->out gvdd_mux_1level_tapbuf_size2[26] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[26], level=1, select_path_id=0. ***** -*****1***** -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -***** Signal mux_1level_tapbuf_size2[26]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[26]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[26] gvdd_mux_1level_tapbuf_size2[26] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[160] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[160] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[160] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[160] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[160] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[160] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[160] param='mux_1level_tapbuf_size2[26]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[26]_energy_per_cycle param='mux_1level_tapbuf_size2[26]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[160] param='mux_1level_tapbuf_size2[26]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[160] param='dynamic_power_sb_mux[1][0]_rrnode[160]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[160] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_rise_sb_mux[1][0]_rrnode[160]' to='start_rise_sb_mux[1][0]_rrnode[160]+switch_rise_sb_mux[1][0]_rrnode[160]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[160] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_fall_sb_mux[1][0]_rrnode[160]' to='start_fall_sb_mux[1][0]_rrnode[160]+switch_fall_sb_mux[1][0]_rrnode[160]' -.meas tran sum_leakage_power_mux[0to26] -+ param='sum_leakage_power_mux[0to25]+leakage_sb_mux[1][0]_rrnode[160]' -.meas tran sum_energy_per_cycle_mux[0to26] -+ param='sum_energy_per_cycle_mux[0to25]+energy_per_cycle_sb_mux[1][0]_rrnode[160]' -***** Load for rr_node[160] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=23, type=4 ***** -Xchan_mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[41]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to26] -+ param='sum_leakage_power_sb_mux[0to25]+leakage_sb_mux[1][0]_rrnode[160]' -.meas tran sum_energy_per_cycle_sb_mux[0to26] -+ param='sum_energy_per_cycle_sb_mux[0to25]+energy_per_cycle_sb_mux[1][0]_rrnode[160]' -Xmux_1level_tapbuf_size2[27] mux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->out sram[31]->outb sram[31]->out gvdd_mux_1level_tapbuf_size2[27] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[27], level=1, select_path_id=0. ***** -*****1***** -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_1level_tapbuf_size2[27]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[27]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[27] gvdd_mux_1level_tapbuf_size2[27] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[162] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[162] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[162] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[162] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[162] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[162] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[162] param='mux_1level_tapbuf_size2[27]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[27]_energy_per_cycle param='mux_1level_tapbuf_size2[27]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[162] param='mux_1level_tapbuf_size2[27]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[162] param='dynamic_power_sb_mux[1][0]_rrnode[162]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[162] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_rise_sb_mux[1][0]_rrnode[162]' to='start_rise_sb_mux[1][0]_rrnode[162]+switch_rise_sb_mux[1][0]_rrnode[162]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[162] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_fall_sb_mux[1][0]_rrnode[162]' to='start_fall_sb_mux[1][0]_rrnode[162]+switch_fall_sb_mux[1][0]_rrnode[162]' -.meas tran sum_leakage_power_mux[0to27] -+ param='sum_leakage_power_mux[0to26]+leakage_sb_mux[1][0]_rrnode[162]' -.meas tran sum_energy_per_cycle_mux[0to27] -+ param='sum_energy_per_cycle_mux[0to26]+energy_per_cycle_sb_mux[1][0]_rrnode[162]' -***** Load for rr_node[162] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=25, type=4 ***** -Xchan_mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[44]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to27] -+ param='sum_leakage_power_sb_mux[0to26]+leakage_sb_mux[1][0]_rrnode[162]' -.meas tran sum_energy_per_cycle_sb_mux[0to27] -+ param='sum_energy_per_cycle_sb_mux[0to26]+energy_per_cycle_sb_mux[1][0]_rrnode[162]' -Xmux_1level_tapbuf_size2[28] mux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->out sram[32]->outb sram[32]->out gvdd_mux_1level_tapbuf_size2[28] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[28], level=1, select_path_id=0. ***** -*****1***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -***** Signal mux_1level_tapbuf_size2[28]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[28]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[28] gvdd_mux_1level_tapbuf_size2[28] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[164] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[164] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[164] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[164] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[164] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[164] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[164] param='mux_1level_tapbuf_size2[28]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[28]_energy_per_cycle param='mux_1level_tapbuf_size2[28]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[164] param='mux_1level_tapbuf_size2[28]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[164] param='dynamic_power_sb_mux[1][0]_rrnode[164]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[164] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_rise_sb_mux[1][0]_rrnode[164]' to='start_rise_sb_mux[1][0]_rrnode[164]+switch_rise_sb_mux[1][0]_rrnode[164]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[164] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_fall_sb_mux[1][0]_rrnode[164]' to='start_fall_sb_mux[1][0]_rrnode[164]+switch_fall_sb_mux[1][0]_rrnode[164]' -.meas tran sum_leakage_power_mux[0to28] -+ param='sum_leakage_power_mux[0to27]+leakage_sb_mux[1][0]_rrnode[164]' -.meas tran sum_energy_per_cycle_mux[0to28] -+ param='sum_energy_per_cycle_mux[0to27]+energy_per_cycle_sb_mux[1][0]_rrnode[164]' -***** Load for rr_node[164] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=27, type=4 ***** -Xchan_mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[46]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to28] -+ param='sum_leakage_power_sb_mux[0to27]+leakage_sb_mux[1][0]_rrnode[164]' -.meas tran sum_energy_per_cycle_sb_mux[0to28] -+ param='sum_energy_per_cycle_sb_mux[0to27]+energy_per_cycle_sb_mux[1][0]_rrnode[164]' -Xmux_1level_tapbuf_size2[29] mux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->out sram[33]->outb sram[33]->out gvdd_mux_1level_tapbuf_size2[29] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[29], level=1, select_path_id=0. ***** -*****1***** -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -***** Signal mux_1level_tapbuf_size2[29]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[29]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[29] gvdd_mux_1level_tapbuf_size2[29] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[166] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[166] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[166] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[166] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[166] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[166] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[166] param='mux_1level_tapbuf_size2[29]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[29]_energy_per_cycle param='mux_1level_tapbuf_size2[29]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[166] param='mux_1level_tapbuf_size2[29]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[166] param='dynamic_power_sb_mux[1][0]_rrnode[166]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[166] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_rise_sb_mux[1][0]_rrnode[166]' to='start_rise_sb_mux[1][0]_rrnode[166]+switch_rise_sb_mux[1][0]_rrnode[166]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[166] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_fall_sb_mux[1][0]_rrnode[166]' to='start_fall_sb_mux[1][0]_rrnode[166]+switch_fall_sb_mux[1][0]_rrnode[166]' -.meas tran sum_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to28]+leakage_sb_mux[1][0]_rrnode[166]' -.meas tran sum_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to28]+energy_per_cycle_sb_mux[1][0]_rrnode[166]' -***** Load for rr_node[166] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=29, type=4 ***** -Xchan_mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[48]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to29] -+ param='sum_leakage_power_sb_mux[0to28]+leakage_sb_mux[1][0]_rrnode[166]' -.meas tran sum_energy_per_cycle_sb_mux[0to29] -+ param='sum_energy_per_cycle_sb_mux[0to28]+energy_per_cycle_sb_mux[1][0]_rrnode[166]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 2 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '2*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='2*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to29]' -.meas tran total_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to29]' -.meas tran total_leakage_power_sb_mux -+ param='sum_leakage_power_sb_mux[0to29]' -.meas tran total_energy_per_cycle_sb_mux -+ param='sum_energy_per_cycle_sb_mux[0to29]' -.end diff --git a/examples/spice_test_example_1/sb_mux_tb/example_1_sb1_1_sbmux_testbench.sp b/examples/spice_test_example_1/sb_mux_tb/example_1_sb1_1_sbmux_testbench.sp deleted file mode 100644 index 849ca57b9..000000000 --- a/examples/spice_test_example_1/sb_mux_tb/example_1_sb1_1_sbmux_testbench.sp +++ /dev/null @@ -1,1670 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_1level_tapbuf_size3[0] mux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb gvdd_mux_1level_tapbuf_size3[0] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[0], level=1, select_path_id=0. ***** -*****100***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -***** Signal mux_1level_tapbuf_size3[0]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[2] density = 0.1906, probability=0.5218.***** -Vmux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_1level_tapbuf_size3[0] gvdd_mux_1level_tapbuf_size3[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[228] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[228] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[228] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[228] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[228] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[228] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[228] param='mux_1level_tapbuf_size3[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size3[0]_energy_per_cycle param='mux_1level_tapbuf_size3[0]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[228] param='mux_1level_tapbuf_size3[0]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[228] param='dynamic_power_sb_mux[1][1]_rrnode[228]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[228] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_rise_sb_mux[1][1]_rrnode[228]' to='start_rise_sb_mux[1][1]_rrnode[228]+switch_rise_sb_mux[1][1]_rrnode[228]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[228] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_fall_sb_mux[1][1]_rrnode[228]' to='start_fall_sb_mux[1][1]_rrnode[228]+switch_fall_sb_mux[1][1]_rrnode[228]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_sb_mux[1][1]_rrnode[228]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_sb_mux[1][1]_rrnode[228]' -***** Load for rr_node[228] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=1, type=5 ***** -Xchan_mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to0] -+ param='leakage_sb_mux[1][1]_rrnode[228]' -.meas tran sum_energy_per_cycle_sb_mux[0to0] -+ param='energy_per_cycle_sb_mux[1][1]_rrnode[228]' -Xmux_1level_tapbuf_size2[1] mux_1level_tapbuf_size2[1]->in[0] mux_1level_tapbuf_size2[1]->in[1] mux_1level_tapbuf_size2[1]->out sram[3]->outb sram[3]->out gvdd_mux_1level_tapbuf_size2[1] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[1], level=1, select_path_id=0. ***** -*****1***** -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -***** Signal mux_1level_tapbuf_size2[1]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[1]->in[0] mux_1level_tapbuf_size2[1]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[1]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[1]->in[1] mux_1level_tapbuf_size2[1]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[1] gvdd_mux_1level_tapbuf_size2[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[230] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[230] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[230] when v(mux_1level_tapbuf_size2[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[230] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[230] when v(mux_1level_tapbuf_size2[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[230] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[1]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[230] param='mux_1level_tapbuf_size2[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[1]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[1]_energy_per_cycle param='mux_1level_tapbuf_size2[1]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[230] param='mux_1level_tapbuf_size2[1]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[230] param='dynamic_power_sb_mux[1][1]_rrnode[230]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[230] avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='start_rise_sb_mux[1][1]_rrnode[230]' to='start_rise_sb_mux[1][1]_rrnode[230]+switch_rise_sb_mux[1][1]_rrnode[230]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[230] avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='start_fall_sb_mux[1][1]_rrnode[230]' to='start_fall_sb_mux[1][1]_rrnode[230]+switch_fall_sb_mux[1][1]_rrnode[230]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_sb_mux[1][1]_rrnode[230]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_sb_mux[1][1]_rrnode[230]' -***** Load for rr_node[230] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=3, type=5 ***** -Xchan_mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to1] -+ param='sum_leakage_power_sb_mux[0to0]+leakage_sb_mux[1][1]_rrnode[230]' -.meas tran sum_energy_per_cycle_sb_mux[0to1] -+ param='sum_energy_per_cycle_sb_mux[0to0]+energy_per_cycle_sb_mux[1][1]_rrnode[230]' -Xmux_1level_tapbuf_size2[2] mux_1level_tapbuf_size2[2]->in[0] mux_1level_tapbuf_size2[2]->in[1] mux_1level_tapbuf_size2[2]->out sram[4]->outb sram[4]->out gvdd_mux_1level_tapbuf_size2[2] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[2], level=1, select_path_id=0. ***** -*****1***** -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -***** Signal mux_1level_tapbuf_size2[2]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[2]->in[0] mux_1level_tapbuf_size2[2]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[2]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[2]->in[1] mux_1level_tapbuf_size2[2]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[2] gvdd_mux_1level_tapbuf_size2[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[232] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[232] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[232] when v(mux_1level_tapbuf_size2[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[232] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[232] when v(mux_1level_tapbuf_size2[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[232] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[2]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[232] param='mux_1level_tapbuf_size2[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[2]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[2]_energy_per_cycle param='mux_1level_tapbuf_size2[2]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[232] param='mux_1level_tapbuf_size2[2]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[232] param='dynamic_power_sb_mux[1][1]_rrnode[232]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[232] avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='start_rise_sb_mux[1][1]_rrnode[232]' to='start_rise_sb_mux[1][1]_rrnode[232]+switch_rise_sb_mux[1][1]_rrnode[232]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[232] avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='start_fall_sb_mux[1][1]_rrnode[232]' to='start_fall_sb_mux[1][1]_rrnode[232]+switch_fall_sb_mux[1][1]_rrnode[232]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_sb_mux[1][1]_rrnode[232]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_sb_mux[1][1]_rrnode[232]' -***** Load for rr_node[232] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=5, type=5 ***** -Xchan_mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[3]_no0 mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to2] -+ param='sum_leakage_power_sb_mux[0to1]+leakage_sb_mux[1][1]_rrnode[232]' -.meas tran sum_energy_per_cycle_sb_mux[0to2] -+ param='sum_energy_per_cycle_sb_mux[0to1]+energy_per_cycle_sb_mux[1][1]_rrnode[232]' -Xmux_1level_tapbuf_size2[3] mux_1level_tapbuf_size2[3]->in[0] mux_1level_tapbuf_size2[3]->in[1] mux_1level_tapbuf_size2[3]->out sram[5]->outb sram[5]->out gvdd_mux_1level_tapbuf_size2[3] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[3], level=1, select_path_id=0. ***** -*****1***** -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -***** Signal mux_1level_tapbuf_size2[3]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[3]->in[0] mux_1level_tapbuf_size2[3]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[3]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[3]->in[1] mux_1level_tapbuf_size2[3]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[3] gvdd_mux_1level_tapbuf_size2[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[234] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[234] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[234] when v(mux_1level_tapbuf_size2[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[234] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[234] when v(mux_1level_tapbuf_size2[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[234] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[3]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[234] param='mux_1level_tapbuf_size2[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[3]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[3]_energy_per_cycle param='mux_1level_tapbuf_size2[3]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[234] param='mux_1level_tapbuf_size2[3]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[234] param='dynamic_power_sb_mux[1][1]_rrnode[234]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[234] avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='start_rise_sb_mux[1][1]_rrnode[234]' to='start_rise_sb_mux[1][1]_rrnode[234]+switch_rise_sb_mux[1][1]_rrnode[234]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[234] avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='start_fall_sb_mux[1][1]_rrnode[234]' to='start_fall_sb_mux[1][1]_rrnode[234]+switch_fall_sb_mux[1][1]_rrnode[234]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_sb_mux[1][1]_rrnode[234]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_sb_mux[1][1]_rrnode[234]' -***** Load for rr_node[234] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=7, type=5 ***** -Xchan_mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[4]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to3] -+ param='sum_leakage_power_sb_mux[0to2]+leakage_sb_mux[1][1]_rrnode[234]' -.meas tran sum_energy_per_cycle_sb_mux[0to3] -+ param='sum_energy_per_cycle_sb_mux[0to2]+energy_per_cycle_sb_mux[1][1]_rrnode[234]' -Xmux_1level_tapbuf_size2[4] mux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->out sram[6]->outb sram[6]->out gvdd_mux_1level_tapbuf_size2[4] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****1***** -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -***** Signal mux_1level_tapbuf_size2[4]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[4]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[4] gvdd_mux_1level_tapbuf_size2[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[236] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[236] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[236] when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[236] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[236] when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[236] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[236] param='mux_1level_tapbuf_size2[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[4]_energy_per_cycle param='mux_1level_tapbuf_size2[4]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[236] param='mux_1level_tapbuf_size2[4]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[236] param='dynamic_power_sb_mux[1][1]_rrnode[236]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[236] avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_rise_sb_mux[1][1]_rrnode[236]' to='start_rise_sb_mux[1][1]_rrnode[236]+switch_rise_sb_mux[1][1]_rrnode[236]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[236] avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_fall_sb_mux[1][1]_rrnode[236]' to='start_fall_sb_mux[1][1]_rrnode[236]+switch_fall_sb_mux[1][1]_rrnode[236]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_sb_mux[1][1]_rrnode[236]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_sb_mux[1][1]_rrnode[236]' -***** Load for rr_node[236] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=9, type=5 ***** -Xchan_mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[5]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to4] -+ param='sum_leakage_power_sb_mux[0to3]+leakage_sb_mux[1][1]_rrnode[236]' -.meas tran sum_energy_per_cycle_sb_mux[0to4] -+ param='sum_energy_per_cycle_sb_mux[0to3]+energy_per_cycle_sb_mux[1][1]_rrnode[236]' -Xmux_1level_tapbuf_size2[5] mux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->out sram[7]->outb sram[7]->out gvdd_mux_1level_tapbuf_size2[5] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[5], level=1, select_path_id=0. ***** -*****1***** -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_1level_tapbuf_size2[5]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[5]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[5] gvdd_mux_1level_tapbuf_size2[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[238] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[238] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[238] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[238] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[238] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[238] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[238] param='mux_1level_tapbuf_size2[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[5]_energy_per_cycle param='mux_1level_tapbuf_size2[5]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[238] param='mux_1level_tapbuf_size2[5]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[238] param='dynamic_power_sb_mux[1][1]_rrnode[238]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[238] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_rise_sb_mux[1][1]_rrnode[238]' to='start_rise_sb_mux[1][1]_rrnode[238]+switch_rise_sb_mux[1][1]_rrnode[238]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[238] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_fall_sb_mux[1][1]_rrnode[238]' to='start_fall_sb_mux[1][1]_rrnode[238]+switch_fall_sb_mux[1][1]_rrnode[238]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_sb_mux[1][1]_rrnode[238]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_sb_mux[1][1]_rrnode[238]' -***** Load for rr_node[238] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=11, type=5 ***** -Xchan_mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[6]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to5] -+ param='sum_leakage_power_sb_mux[0to4]+leakage_sb_mux[1][1]_rrnode[238]' -.meas tran sum_energy_per_cycle_sb_mux[0to5] -+ param='sum_energy_per_cycle_sb_mux[0to4]+energy_per_cycle_sb_mux[1][1]_rrnode[238]' -Xmux_1level_tapbuf_size2[6] mux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->out sram[8]->outb sram[8]->out gvdd_mux_1level_tapbuf_size2[6] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[6], level=1, select_path_id=0. ***** -*****1***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -***** Signal mux_1level_tapbuf_size2[6]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[6]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[6] gvdd_mux_1level_tapbuf_size2[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[240] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[240] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[240] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[240] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[240] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[240] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[240] param='mux_1level_tapbuf_size2[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[6]_energy_per_cycle param='mux_1level_tapbuf_size2[6]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[240] param='mux_1level_tapbuf_size2[6]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[240] param='dynamic_power_sb_mux[1][1]_rrnode[240]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[240] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_rise_sb_mux[1][1]_rrnode[240]' to='start_rise_sb_mux[1][1]_rrnode[240]+switch_rise_sb_mux[1][1]_rrnode[240]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[240] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_fall_sb_mux[1][1]_rrnode[240]' to='start_fall_sb_mux[1][1]_rrnode[240]+switch_fall_sb_mux[1][1]_rrnode[240]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_sb_mux[1][1]_rrnode[240]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_sb_mux[1][1]_rrnode[240]' -***** Load for rr_node[240] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=13, type=5 ***** -Xchan_mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[7]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to6] -+ param='sum_leakage_power_sb_mux[0to5]+leakage_sb_mux[1][1]_rrnode[240]' -.meas tran sum_energy_per_cycle_sb_mux[0to6] -+ param='sum_energy_per_cycle_sb_mux[0to5]+energy_per_cycle_sb_mux[1][1]_rrnode[240]' -Xmux_1level_tapbuf_size2[7] mux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->out sram[9]->outb sram[9]->out gvdd_mux_1level_tapbuf_size2[7] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[7], level=1, select_path_id=0. ***** -*****1***** -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -***** Signal mux_1level_tapbuf_size2[7]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[7]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[7] gvdd_mux_1level_tapbuf_size2[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[242] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[242] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[242] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[242] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[242] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[242] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[242] param='mux_1level_tapbuf_size2[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[7]_energy_per_cycle param='mux_1level_tapbuf_size2[7]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[242] param='mux_1level_tapbuf_size2[7]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[242] param='dynamic_power_sb_mux[1][1]_rrnode[242]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[242] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_rise_sb_mux[1][1]_rrnode[242]' to='start_rise_sb_mux[1][1]_rrnode[242]+switch_rise_sb_mux[1][1]_rrnode[242]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[242] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_fall_sb_mux[1][1]_rrnode[242]' to='start_fall_sb_mux[1][1]_rrnode[242]+switch_fall_sb_mux[1][1]_rrnode[242]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_sb_mux[1][1]_rrnode[242]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_sb_mux[1][1]_rrnode[242]' -***** Load for rr_node[242] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=15, type=5 ***** -Xchan_mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[8]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to7] -+ param='sum_leakage_power_sb_mux[0to6]+leakage_sb_mux[1][1]_rrnode[242]' -.meas tran sum_energy_per_cycle_sb_mux[0to7] -+ param='sum_energy_per_cycle_sb_mux[0to6]+energy_per_cycle_sb_mux[1][1]_rrnode[242]' -Xmux_1level_tapbuf_size2[8] mux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->out sram[10]->outb sram[10]->out gvdd_mux_1level_tapbuf_size2[8] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[8], level=1, select_path_id=0. ***** -*****1***** -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -***** Signal mux_1level_tapbuf_size2[8]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[8]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[8] gvdd_mux_1level_tapbuf_size2[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[244] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[244] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[244] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[244] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[244] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[244] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[244] param='mux_1level_tapbuf_size2[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[8]_energy_per_cycle param='mux_1level_tapbuf_size2[8]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[244] param='mux_1level_tapbuf_size2[8]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[244] param='dynamic_power_sb_mux[1][1]_rrnode[244]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[244] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_rise_sb_mux[1][1]_rrnode[244]' to='start_rise_sb_mux[1][1]_rrnode[244]+switch_rise_sb_mux[1][1]_rrnode[244]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[244] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_fall_sb_mux[1][1]_rrnode[244]' to='start_fall_sb_mux[1][1]_rrnode[244]+switch_fall_sb_mux[1][1]_rrnode[244]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_sb_mux[1][1]_rrnode[244]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_sb_mux[1][1]_rrnode[244]' -***** Load for rr_node[244] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=17, type=5 ***** -Xchan_mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[9]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to8] -+ param='sum_leakage_power_sb_mux[0to7]+leakage_sb_mux[1][1]_rrnode[244]' -.meas tran sum_energy_per_cycle_sb_mux[0to8] -+ param='sum_energy_per_cycle_sb_mux[0to7]+energy_per_cycle_sb_mux[1][1]_rrnode[244]' -Xmux_1level_tapbuf_size2[9] mux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->out sram[11]->outb sram[11]->out gvdd_mux_1level_tapbuf_size2[9] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[9], level=1, select_path_id=0. ***** -*****1***** -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_1level_tapbuf_size2[9]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[9]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[9] gvdd_mux_1level_tapbuf_size2[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[246] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[246] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[246] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[246] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[246] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[246] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[246] param='mux_1level_tapbuf_size2[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[9]_energy_per_cycle param='mux_1level_tapbuf_size2[9]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[246] param='mux_1level_tapbuf_size2[9]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[246] param='dynamic_power_sb_mux[1][1]_rrnode[246]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[246] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_rise_sb_mux[1][1]_rrnode[246]' to='start_rise_sb_mux[1][1]_rrnode[246]+switch_rise_sb_mux[1][1]_rrnode[246]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[246] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_fall_sb_mux[1][1]_rrnode[246]' to='start_fall_sb_mux[1][1]_rrnode[246]+switch_fall_sb_mux[1][1]_rrnode[246]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_sb_mux[1][1]_rrnode[246]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_sb_mux[1][1]_rrnode[246]' -***** Load for rr_node[246] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=19, type=5 ***** -Xchan_mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[11]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to9] -+ param='sum_leakage_power_sb_mux[0to8]+leakage_sb_mux[1][1]_rrnode[246]' -.meas tran sum_energy_per_cycle_sb_mux[0to9] -+ param='sum_energy_per_cycle_sb_mux[0to8]+energy_per_cycle_sb_mux[1][1]_rrnode[246]' -Xmux_1level_tapbuf_size2[10] mux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->out sram[12]->outb sram[12]->out gvdd_mux_1level_tapbuf_size2[10] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[10], level=1, select_path_id=0. ***** -*****1***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -***** Signal mux_1level_tapbuf_size2[10]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[10]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[10] gvdd_mux_1level_tapbuf_size2[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[248] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[248] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[248] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[248] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[248] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[248] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[248] param='mux_1level_tapbuf_size2[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[10]_energy_per_cycle param='mux_1level_tapbuf_size2[10]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[248] param='mux_1level_tapbuf_size2[10]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[248] param='dynamic_power_sb_mux[1][1]_rrnode[248]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[248] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_rise_sb_mux[1][1]_rrnode[248]' to='start_rise_sb_mux[1][1]_rrnode[248]+switch_rise_sb_mux[1][1]_rrnode[248]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[248] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_fall_sb_mux[1][1]_rrnode[248]' to='start_fall_sb_mux[1][1]_rrnode[248]+switch_fall_sb_mux[1][1]_rrnode[248]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_sb_mux[1][1]_rrnode[248]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_sb_mux[1][1]_rrnode[248]' -***** Load for rr_node[248] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=21, type=5 ***** -Xchan_mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[12]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to10] -+ param='sum_leakage_power_sb_mux[0to9]+leakage_sb_mux[1][1]_rrnode[248]' -.meas tran sum_energy_per_cycle_sb_mux[0to10] -+ param='sum_energy_per_cycle_sb_mux[0to9]+energy_per_cycle_sb_mux[1][1]_rrnode[248]' -Xmux_1level_tapbuf_size2[11] mux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->out sram[13]->outb sram[13]->out gvdd_mux_1level_tapbuf_size2[11] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[11], level=1, select_path_id=0. ***** -*****1***** -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -***** Signal mux_1level_tapbuf_size2[11]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[11]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[11] gvdd_mux_1level_tapbuf_size2[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[250] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[250] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[250] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[250] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[250] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[250] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[250] param='mux_1level_tapbuf_size2[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[11]_energy_per_cycle param='mux_1level_tapbuf_size2[11]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[250] param='mux_1level_tapbuf_size2[11]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[250] param='dynamic_power_sb_mux[1][1]_rrnode[250]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[250] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_rise_sb_mux[1][1]_rrnode[250]' to='start_rise_sb_mux[1][1]_rrnode[250]+switch_rise_sb_mux[1][1]_rrnode[250]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[250] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_fall_sb_mux[1][1]_rrnode[250]' to='start_fall_sb_mux[1][1]_rrnode[250]+switch_fall_sb_mux[1][1]_rrnode[250]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_sb_mux[1][1]_rrnode[250]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_sb_mux[1][1]_rrnode[250]' -***** Load for rr_node[250] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=23, type=5 ***** -Xchan_mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[13]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to11] -+ param='sum_leakage_power_sb_mux[0to10]+leakage_sb_mux[1][1]_rrnode[250]' -.meas tran sum_energy_per_cycle_sb_mux[0to11] -+ param='sum_energy_per_cycle_sb_mux[0to10]+energy_per_cycle_sb_mux[1][1]_rrnode[250]' -Xmux_1level_tapbuf_size2[12] mux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->out sram[14]->outb sram[14]->out gvdd_mux_1level_tapbuf_size2[12] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[12], level=1, select_path_id=0. ***** -*****1***** -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -***** Signal mux_1level_tapbuf_size2[12]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[12]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[12] gvdd_mux_1level_tapbuf_size2[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[252] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[252] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[252] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[252] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[252] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[252] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[252] param='mux_1level_tapbuf_size2[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[12]_energy_per_cycle param='mux_1level_tapbuf_size2[12]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[252] param='mux_1level_tapbuf_size2[12]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[252] param='dynamic_power_sb_mux[1][1]_rrnode[252]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[252] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_rise_sb_mux[1][1]_rrnode[252]' to='start_rise_sb_mux[1][1]_rrnode[252]+switch_rise_sb_mux[1][1]_rrnode[252]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[252] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_fall_sb_mux[1][1]_rrnode[252]' to='start_fall_sb_mux[1][1]_rrnode[252]+switch_fall_sb_mux[1][1]_rrnode[252]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_sb_mux[1][1]_rrnode[252]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_sb_mux[1][1]_rrnode[252]' -***** Load for rr_node[252] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=25, type=5 ***** -Xchan_mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[14]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to12] -+ param='sum_leakage_power_sb_mux[0to11]+leakage_sb_mux[1][1]_rrnode[252]' -.meas tran sum_energy_per_cycle_sb_mux[0to12] -+ param='sum_energy_per_cycle_sb_mux[0to11]+energy_per_cycle_sb_mux[1][1]_rrnode[252]' -Xmux_1level_tapbuf_size2[13] mux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->out sram[15]->outb sram[15]->out gvdd_mux_1level_tapbuf_size2[13] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[13], level=1, select_path_id=0. ***** -*****1***** -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_1level_tapbuf_size2[13]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[13]->in[1] density = 0.1906, probability=0.4782.***** -Vmux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_1level_tapbuf_size2[13] gvdd_mux_1level_tapbuf_size2[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[254] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[254] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[254] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[254] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[254] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[254] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[254] param='mux_1level_tapbuf_size2[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size2[13]_energy_per_cycle param='mux_1level_tapbuf_size2[13]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[254] param='mux_1level_tapbuf_size2[13]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[254] param='dynamic_power_sb_mux[1][1]_rrnode[254]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[254] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_rise_sb_mux[1][1]_rrnode[254]' to='start_rise_sb_mux[1][1]_rrnode[254]+switch_rise_sb_mux[1][1]_rrnode[254]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[254] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_fall_sb_mux[1][1]_rrnode[254]' to='start_fall_sb_mux[1][1]_rrnode[254]+switch_fall_sb_mux[1][1]_rrnode[254]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_sb_mux[1][1]_rrnode[254]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_sb_mux[1][1]_rrnode[254]' -***** Load for rr_node[254] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=27, type=5 ***** -Xchan_mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[15]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to13] -+ param='sum_leakage_power_sb_mux[0to12]+leakage_sb_mux[1][1]_rrnode[254]' -.meas tran sum_energy_per_cycle_sb_mux[0to13] -+ param='sum_energy_per_cycle_sb_mux[0to12]+energy_per_cycle_sb_mux[1][1]_rrnode[254]' -Xmux_1level_tapbuf_size2[14] mux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->out sram[16]->outb sram[16]->out gvdd_mux_1level_tapbuf_size2[14] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[14], level=1, select_path_id=0. ***** -*****1***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -***** Signal mux_1level_tapbuf_size2[14]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[14]->in[1] density = 0.1906, probability=0.5218.***** -Vmux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgvdd_mux_1level_tapbuf_size2[14] gvdd_mux_1level_tapbuf_size2[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[256] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[256] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[256] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[256] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[256] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[256] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[256] param='mux_1level_tapbuf_size2[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size2[14]_energy_per_cycle param='mux_1level_tapbuf_size2[14]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[256] param='mux_1level_tapbuf_size2[14]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[256] param='dynamic_power_sb_mux[1][1]_rrnode[256]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[256] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_rise_sb_mux[1][1]_rrnode[256]' to='start_rise_sb_mux[1][1]_rrnode[256]+switch_rise_sb_mux[1][1]_rrnode[256]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[256] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_fall_sb_mux[1][1]_rrnode[256]' to='start_fall_sb_mux[1][1]_rrnode[256]+switch_fall_sb_mux[1][1]_rrnode[256]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_sb_mux[1][1]_rrnode[256]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_sb_mux[1][1]_rrnode[256]' -***** Load for rr_node[256] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=29, type=5 ***** -Xchan_mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[16]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to14] -+ param='sum_leakage_power_sb_mux[0to13]+leakage_sb_mux[1][1]_rrnode[256]' -.meas tran sum_energy_per_cycle_sb_mux[0to14] -+ param='sum_energy_per_cycle_sb_mux[0to13]+energy_per_cycle_sb_mux[1][1]_rrnode[256]' -Xmux_1level_tapbuf_size3[15] mux_1level_tapbuf_size3[15]->in[0] mux_1level_tapbuf_size3[15]->in[1] mux_1level_tapbuf_size3[15]->in[2] mux_1level_tapbuf_size3[15]->out sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb gvdd_mux_1level_tapbuf_size3[15] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[15], level=1, select_path_id=1. ***** -*****010***** -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_1level_tapbuf_size3[15]->in[0] density = 0.1906, probability=0.5218.***** -Vmux_1level_tapbuf_size3[15]->in[0] mux_1level_tapbuf_size3[15]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_1level_tapbuf_size3[15]->in[1] density = 0.1906, probability=0.4782.***** -Vmux_1level_tapbuf_size3[15]->in[1] mux_1level_tapbuf_size3[15]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_1level_tapbuf_size3[15]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[15]->in[2] mux_1level_tapbuf_size3[15]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[15] gvdd_mux_1level_tapbuf_size3[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[168] trig v(mux_1level_tapbuf_size3[15]->in[1]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[168] trig v(mux_1level_tapbuf_size3[15]->in[1]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[168] when v(mux_1level_tapbuf_size3[15]->in[1])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[168] trig v(mux_1level_tapbuf_size3[15]->in[1]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[168] when v(mux_1level_tapbuf_size3[15]->in[1])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[168] trig v(mux_1level_tapbuf_size3[15]->in[1]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[15]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[168] param='mux_1level_tapbuf_size3[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[15]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size3[15]_energy_per_cycle param='mux_1level_tapbuf_size3[15]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[168] param='mux_1level_tapbuf_size3[15]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[168] param='dynamic_power_sb_mux[1][1]_rrnode[168]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[168] avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='start_rise_sb_mux[1][1]_rrnode[168]' to='start_rise_sb_mux[1][1]_rrnode[168]+switch_rise_sb_mux[1][1]_rrnode[168]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[168] avg p(Vgvdd_mux_1level_tapbuf_size3[15]) from='start_fall_sb_mux[1][1]_rrnode[168]' to='start_fall_sb_mux[1][1]_rrnode[168]+switch_fall_sb_mux[1][1]_rrnode[168]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_sb_mux[1][1]_rrnode[168]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_sb_mux[1][1]_rrnode[168]' -***** Load for rr_node[168] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=1, type=4 ***** -Xchan_mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[17]_no0 mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out mux_1level_tapbuf_size3[15]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[15]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to15] -+ param='sum_leakage_power_sb_mux[0to14]+leakage_sb_mux[1][1]_rrnode[168]' -.meas tran sum_energy_per_cycle_sb_mux[0to15] -+ param='sum_energy_per_cycle_sb_mux[0to14]+energy_per_cycle_sb_mux[1][1]_rrnode[168]' -Xmux_1level_tapbuf_size3[16] mux_1level_tapbuf_size3[16]->in[0] mux_1level_tapbuf_size3[16]->in[1] mux_1level_tapbuf_size3[16]->in[2] mux_1level_tapbuf_size3[16]->out sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->out sram[22]->outb gvdd_mux_1level_tapbuf_size3[16] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[16], level=1, select_path_id=0. ***** -*****100***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -***** Signal mux_1level_tapbuf_size3[16]->in[0] density = 0.1906, probability=0.5218.***** -Vmux_1level_tapbuf_size3[16]->in[0] mux_1level_tapbuf_size3[16]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_1level_tapbuf_size3[16]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[16]->in[1] mux_1level_tapbuf_size3[16]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[16]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[16]->in[2] mux_1level_tapbuf_size3[16]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[16] gvdd_mux_1level_tapbuf_size3[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[170] trig v(mux_1level_tapbuf_size3[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[170] trig v(mux_1level_tapbuf_size3[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[170] when v(mux_1level_tapbuf_size3[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[170] trig v(mux_1level_tapbuf_size3[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[170] when v(mux_1level_tapbuf_size3[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[170] trig v(mux_1level_tapbuf_size3[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[16]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[16]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[170] param='mux_1level_tapbuf_size3[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[16]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[16]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size3[16]_energy_per_cycle param='mux_1level_tapbuf_size3[16]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[170] param='mux_1level_tapbuf_size3[16]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[170] param='dynamic_power_sb_mux[1][1]_rrnode[170]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[170] avg p(Vgvdd_mux_1level_tapbuf_size3[16]) from='start_rise_sb_mux[1][1]_rrnode[170]' to='start_rise_sb_mux[1][1]_rrnode[170]+switch_rise_sb_mux[1][1]_rrnode[170]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[170] avg p(Vgvdd_mux_1level_tapbuf_size3[16]) from='start_fall_sb_mux[1][1]_rrnode[170]' to='start_fall_sb_mux[1][1]_rrnode[170]+switch_fall_sb_mux[1][1]_rrnode[170]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_sb_mux[1][1]_rrnode[170]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_sb_mux[1][1]_rrnode[170]' -***** Load for rr_node[170] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=3, type=4 ***** -Xchan_mux_1level_tapbuf_size3[16]->out_loadlvl[0]_out mux_1level_tapbuf_size3[16]->out mux_1level_tapbuf_size3[16]->out_loadlvl[0]_out mux_1level_tapbuf_size3[16]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[19]_no0 mux_1level_tapbuf_size3[16]->out_loadlvl[0]_out mux_1level_tapbuf_size3[16]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 mux_1level_tapbuf_size3[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[16]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to16] -+ param='sum_leakage_power_sb_mux[0to15]+leakage_sb_mux[1][1]_rrnode[170]' -.meas tran sum_energy_per_cycle_sb_mux[0to16] -+ param='sum_energy_per_cycle_sb_mux[0to15]+energy_per_cycle_sb_mux[1][1]_rrnode[170]' -Xmux_1level_tapbuf_size3[17] mux_1level_tapbuf_size3[17]->in[0] mux_1level_tapbuf_size3[17]->in[1] mux_1level_tapbuf_size3[17]->in[2] mux_1level_tapbuf_size3[17]->out sram[23]->outb sram[23]->out sram[24]->out sram[24]->outb sram[25]->out sram[25]->outb gvdd_mux_1level_tapbuf_size3[17] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[17], level=1, select_path_id=0. ***** -*****100***** -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -***** Signal mux_1level_tapbuf_size3[17]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[17]->in[0] mux_1level_tapbuf_size3[17]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[17]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[17]->in[1] mux_1level_tapbuf_size3[17]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[17]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[17]->in[2] mux_1level_tapbuf_size3[17]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[17] gvdd_mux_1level_tapbuf_size3[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[172] trig v(mux_1level_tapbuf_size3[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[172] trig v(mux_1level_tapbuf_size3[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[172] when v(mux_1level_tapbuf_size3[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[172] trig v(mux_1level_tapbuf_size3[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[172] when v(mux_1level_tapbuf_size3[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[172] trig v(mux_1level_tapbuf_size3[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[17]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[17]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[172] param='mux_1level_tapbuf_size3[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[17]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[17]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[17]_energy_per_cycle param='mux_1level_tapbuf_size3[17]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[172] param='mux_1level_tapbuf_size3[17]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[172] param='dynamic_power_sb_mux[1][1]_rrnode[172]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[172] avg p(Vgvdd_mux_1level_tapbuf_size3[17]) from='start_rise_sb_mux[1][1]_rrnode[172]' to='start_rise_sb_mux[1][1]_rrnode[172]+switch_rise_sb_mux[1][1]_rrnode[172]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[172] avg p(Vgvdd_mux_1level_tapbuf_size3[17]) from='start_fall_sb_mux[1][1]_rrnode[172]' to='start_fall_sb_mux[1][1]_rrnode[172]+switch_fall_sb_mux[1][1]_rrnode[172]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_sb_mux[1][1]_rrnode[172]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_sb_mux[1][1]_rrnode[172]' -***** Load for rr_node[172] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=5, type=4 ***** -Xchan_mux_1level_tapbuf_size3[17]->out_loadlvl[0]_out mux_1level_tapbuf_size3[17]->out mux_1level_tapbuf_size3[17]->out_loadlvl[0]_out mux_1level_tapbuf_size3[17]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[21]_no0 mux_1level_tapbuf_size3[17]->out_loadlvl[0]_out mux_1level_tapbuf_size3[17]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 mux_1level_tapbuf_size3[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[17]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to17] -+ param='sum_leakage_power_sb_mux[0to16]+leakage_sb_mux[1][1]_rrnode[172]' -.meas tran sum_energy_per_cycle_sb_mux[0to17] -+ param='sum_energy_per_cycle_sb_mux[0to16]+energy_per_cycle_sb_mux[1][1]_rrnode[172]' -Xmux_1level_tapbuf_size2[18] mux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->out sram[26]->outb sram[26]->out gvdd_mux_1level_tapbuf_size2[18] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[18], level=1, select_path_id=0. ***** -*****1***** -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -***** Signal mux_1level_tapbuf_size2[18]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[18]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[18] gvdd_mux_1level_tapbuf_size2[18] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[174] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[174] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[174] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[174] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[174] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[174] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[174] param='mux_1level_tapbuf_size2[18]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[18]_energy_per_cycle param='mux_1level_tapbuf_size2[18]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[174] param='mux_1level_tapbuf_size2[18]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[174] param='dynamic_power_sb_mux[1][1]_rrnode[174]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[174] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_rise_sb_mux[1][1]_rrnode[174]' to='start_rise_sb_mux[1][1]_rrnode[174]+switch_rise_sb_mux[1][1]_rrnode[174]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[174] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_fall_sb_mux[1][1]_rrnode[174]' to='start_fall_sb_mux[1][1]_rrnode[174]+switch_fall_sb_mux[1][1]_rrnode[174]' -.meas tran sum_leakage_power_mux[0to18] -+ param='sum_leakage_power_mux[0to17]+leakage_sb_mux[1][1]_rrnode[174]' -.meas tran sum_energy_per_cycle_mux[0to18] -+ param='sum_energy_per_cycle_mux[0to17]+energy_per_cycle_sb_mux[1][1]_rrnode[174]' -***** Load for rr_node[174] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=7, type=4 ***** -Xchan_mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[23]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to18] -+ param='sum_leakage_power_sb_mux[0to17]+leakage_sb_mux[1][1]_rrnode[174]' -.meas tran sum_energy_per_cycle_sb_mux[0to18] -+ param='sum_energy_per_cycle_sb_mux[0to17]+energy_per_cycle_sb_mux[1][1]_rrnode[174]' -Xmux_1level_tapbuf_size2[19] mux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->out sram[27]->outb sram[27]->out gvdd_mux_1level_tapbuf_size2[19] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[19], level=1, select_path_id=0. ***** -*****1***** -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_1level_tapbuf_size2[19]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[19]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[19] gvdd_mux_1level_tapbuf_size2[19] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[176] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[176] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[176] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[176] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[176] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[176] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[176] param='mux_1level_tapbuf_size2[19]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[19]_energy_per_cycle param='mux_1level_tapbuf_size2[19]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[176] param='mux_1level_tapbuf_size2[19]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[176] param='dynamic_power_sb_mux[1][1]_rrnode[176]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[176] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_rise_sb_mux[1][1]_rrnode[176]' to='start_rise_sb_mux[1][1]_rrnode[176]+switch_rise_sb_mux[1][1]_rrnode[176]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[176] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_fall_sb_mux[1][1]_rrnode[176]' to='start_fall_sb_mux[1][1]_rrnode[176]+switch_fall_sb_mux[1][1]_rrnode[176]' -.meas tran sum_leakage_power_mux[0to19] -+ param='sum_leakage_power_mux[0to18]+leakage_sb_mux[1][1]_rrnode[176]' -.meas tran sum_energy_per_cycle_mux[0to19] -+ param='sum_energy_per_cycle_mux[0to18]+energy_per_cycle_sb_mux[1][1]_rrnode[176]' -***** Load for rr_node[176] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=9, type=4 ***** -Xchan_mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[26]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to19] -+ param='sum_leakage_power_sb_mux[0to18]+leakage_sb_mux[1][1]_rrnode[176]' -.meas tran sum_energy_per_cycle_sb_mux[0to19] -+ param='sum_energy_per_cycle_sb_mux[0to18]+energy_per_cycle_sb_mux[1][1]_rrnode[176]' -Xmux_1level_tapbuf_size2[20] mux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->out sram[28]->outb sram[28]->out gvdd_mux_1level_tapbuf_size2[20] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[20], level=1, select_path_id=0. ***** -*****1***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -***** Signal mux_1level_tapbuf_size2[20]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[20]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[20] gvdd_mux_1level_tapbuf_size2[20] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[178] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[178] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[178] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[178] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[178] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[178] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[178] param='mux_1level_tapbuf_size2[20]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[20]_energy_per_cycle param='mux_1level_tapbuf_size2[20]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[178] param='mux_1level_tapbuf_size2[20]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[178] param='dynamic_power_sb_mux[1][1]_rrnode[178]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[178] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_rise_sb_mux[1][1]_rrnode[178]' to='start_rise_sb_mux[1][1]_rrnode[178]+switch_rise_sb_mux[1][1]_rrnode[178]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[178] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_fall_sb_mux[1][1]_rrnode[178]' to='start_fall_sb_mux[1][1]_rrnode[178]+switch_fall_sb_mux[1][1]_rrnode[178]' -.meas tran sum_leakage_power_mux[0to20] -+ param='sum_leakage_power_mux[0to19]+leakage_sb_mux[1][1]_rrnode[178]' -.meas tran sum_energy_per_cycle_mux[0to20] -+ param='sum_energy_per_cycle_mux[0to19]+energy_per_cycle_sb_mux[1][1]_rrnode[178]' -***** Load for rr_node[178] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=11, type=4 ***** -Xchan_mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[28]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to20] -+ param='sum_leakage_power_sb_mux[0to19]+leakage_sb_mux[1][1]_rrnode[178]' -.meas tran sum_energy_per_cycle_sb_mux[0to20] -+ param='sum_energy_per_cycle_sb_mux[0to19]+energy_per_cycle_sb_mux[1][1]_rrnode[178]' -Xmux_1level_tapbuf_size2[21] mux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->out sram[29]->outb sram[29]->out gvdd_mux_1level_tapbuf_size2[21] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[21], level=1, select_path_id=0. ***** -*****1***** -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -***** Signal mux_1level_tapbuf_size2[21]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[21]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[21] gvdd_mux_1level_tapbuf_size2[21] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[180] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[180] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[180] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[180] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[180] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[180] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[180] param='mux_1level_tapbuf_size2[21]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[21]_energy_per_cycle param='mux_1level_tapbuf_size2[21]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[180] param='mux_1level_tapbuf_size2[21]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[180] param='dynamic_power_sb_mux[1][1]_rrnode[180]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[180] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_rise_sb_mux[1][1]_rrnode[180]' to='start_rise_sb_mux[1][1]_rrnode[180]+switch_rise_sb_mux[1][1]_rrnode[180]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[180] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_fall_sb_mux[1][1]_rrnode[180]' to='start_fall_sb_mux[1][1]_rrnode[180]+switch_fall_sb_mux[1][1]_rrnode[180]' -.meas tran sum_leakage_power_mux[0to21] -+ param='sum_leakage_power_mux[0to20]+leakage_sb_mux[1][1]_rrnode[180]' -.meas tran sum_energy_per_cycle_mux[0to21] -+ param='sum_energy_per_cycle_mux[0to20]+energy_per_cycle_sb_mux[1][1]_rrnode[180]' -***** Load for rr_node[180] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=13, type=4 ***** -Xchan_mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[30]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[31]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to21] -+ param='sum_leakage_power_sb_mux[0to20]+leakage_sb_mux[1][1]_rrnode[180]' -.meas tran sum_energy_per_cycle_sb_mux[0to21] -+ param='sum_energy_per_cycle_sb_mux[0to20]+energy_per_cycle_sb_mux[1][1]_rrnode[180]' -Xmux_1level_tapbuf_size2[22] mux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->out sram[30]->outb sram[30]->out gvdd_mux_1level_tapbuf_size2[22] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[22], level=1, select_path_id=0. ***** -*****1***** -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -***** Signal mux_1level_tapbuf_size2[22]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[22]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[22] gvdd_mux_1level_tapbuf_size2[22] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[182] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[182] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[182] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[182] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[182] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[182] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[182] param='mux_1level_tapbuf_size2[22]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[22]_energy_per_cycle param='mux_1level_tapbuf_size2[22]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[182] param='mux_1level_tapbuf_size2[22]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[182] param='dynamic_power_sb_mux[1][1]_rrnode[182]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[182] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_rise_sb_mux[1][1]_rrnode[182]' to='start_rise_sb_mux[1][1]_rrnode[182]+switch_rise_sb_mux[1][1]_rrnode[182]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[182] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_fall_sb_mux[1][1]_rrnode[182]' to='start_fall_sb_mux[1][1]_rrnode[182]+switch_fall_sb_mux[1][1]_rrnode[182]' -.meas tran sum_leakage_power_mux[0to22] -+ param='sum_leakage_power_mux[0to21]+leakage_sb_mux[1][1]_rrnode[182]' -.meas tran sum_energy_per_cycle_mux[0to22] -+ param='sum_energy_per_cycle_mux[0to21]+energy_per_cycle_sb_mux[1][1]_rrnode[182]' -***** Load for rr_node[182] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=15, type=4 ***** -Xchan_mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[34]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to22] -+ param='sum_leakage_power_sb_mux[0to21]+leakage_sb_mux[1][1]_rrnode[182]' -.meas tran sum_energy_per_cycle_sb_mux[0to22] -+ param='sum_energy_per_cycle_sb_mux[0to21]+energy_per_cycle_sb_mux[1][1]_rrnode[182]' -Xmux_1level_tapbuf_size2[23] mux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->out sram[31]->outb sram[31]->out gvdd_mux_1level_tapbuf_size2[23] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[23], level=1, select_path_id=0. ***** -*****1***** -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_1level_tapbuf_size2[23]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[23]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[23] gvdd_mux_1level_tapbuf_size2[23] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[184] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[184] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[184] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[184] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[184] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[184] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[184] param='mux_1level_tapbuf_size2[23]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[23]_energy_per_cycle param='mux_1level_tapbuf_size2[23]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[184] param='mux_1level_tapbuf_size2[23]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[184] param='dynamic_power_sb_mux[1][1]_rrnode[184]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[184] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_rise_sb_mux[1][1]_rrnode[184]' to='start_rise_sb_mux[1][1]_rrnode[184]+switch_rise_sb_mux[1][1]_rrnode[184]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[184] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_fall_sb_mux[1][1]_rrnode[184]' to='start_fall_sb_mux[1][1]_rrnode[184]+switch_fall_sb_mux[1][1]_rrnode[184]' -.meas tran sum_leakage_power_mux[0to23] -+ param='sum_leakage_power_mux[0to22]+leakage_sb_mux[1][1]_rrnode[184]' -.meas tran sum_energy_per_cycle_mux[0to23] -+ param='sum_energy_per_cycle_mux[0to22]+energy_per_cycle_sb_mux[1][1]_rrnode[184]' -***** Load for rr_node[184] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=17, type=4 ***** -Xchan_mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[36]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to23] -+ param='sum_leakage_power_sb_mux[0to22]+leakage_sb_mux[1][1]_rrnode[184]' -.meas tran sum_energy_per_cycle_sb_mux[0to23] -+ param='sum_energy_per_cycle_sb_mux[0to22]+energy_per_cycle_sb_mux[1][1]_rrnode[184]' -Xmux_1level_tapbuf_size2[24] mux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->out sram[32]->outb sram[32]->out gvdd_mux_1level_tapbuf_size2[24] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[24], level=1, select_path_id=0. ***** -*****1***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -***** Signal mux_1level_tapbuf_size2[24]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[24]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[24] gvdd_mux_1level_tapbuf_size2[24] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[186] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[186] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[186] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[186] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[186] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[186] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[186] param='mux_1level_tapbuf_size2[24]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[24]_energy_per_cycle param='mux_1level_tapbuf_size2[24]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[186] param='mux_1level_tapbuf_size2[24]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[186] param='dynamic_power_sb_mux[1][1]_rrnode[186]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[186] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_rise_sb_mux[1][1]_rrnode[186]' to='start_rise_sb_mux[1][1]_rrnode[186]+switch_rise_sb_mux[1][1]_rrnode[186]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[186] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_fall_sb_mux[1][1]_rrnode[186]' to='start_fall_sb_mux[1][1]_rrnode[186]+switch_fall_sb_mux[1][1]_rrnode[186]' -.meas tran sum_leakage_power_mux[0to24] -+ param='sum_leakage_power_mux[0to23]+leakage_sb_mux[1][1]_rrnode[186]' -.meas tran sum_energy_per_cycle_mux[0to24] -+ param='sum_energy_per_cycle_mux[0to23]+energy_per_cycle_sb_mux[1][1]_rrnode[186]' -***** Load for rr_node[186] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=19, type=4 ***** -Xchan_mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[38]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to24] -+ param='sum_leakage_power_sb_mux[0to23]+leakage_sb_mux[1][1]_rrnode[186]' -.meas tran sum_energy_per_cycle_sb_mux[0to24] -+ param='sum_energy_per_cycle_sb_mux[0to23]+energy_per_cycle_sb_mux[1][1]_rrnode[186]' -Xmux_1level_tapbuf_size2[25] mux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->out sram[33]->outb sram[33]->out gvdd_mux_1level_tapbuf_size2[25] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[25], level=1, select_path_id=0. ***** -*****1***** -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -***** Signal mux_1level_tapbuf_size2[25]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[25]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[25] gvdd_mux_1level_tapbuf_size2[25] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[188] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[188] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[188] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[188] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[188] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[188] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[188] param='mux_1level_tapbuf_size2[25]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[25]_energy_per_cycle param='mux_1level_tapbuf_size2[25]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[188] param='mux_1level_tapbuf_size2[25]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[188] param='dynamic_power_sb_mux[1][1]_rrnode[188]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[188] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_rise_sb_mux[1][1]_rrnode[188]' to='start_rise_sb_mux[1][1]_rrnode[188]+switch_rise_sb_mux[1][1]_rrnode[188]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[188] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_fall_sb_mux[1][1]_rrnode[188]' to='start_fall_sb_mux[1][1]_rrnode[188]+switch_fall_sb_mux[1][1]_rrnode[188]' -.meas tran sum_leakage_power_mux[0to25] -+ param='sum_leakage_power_mux[0to24]+leakage_sb_mux[1][1]_rrnode[188]' -.meas tran sum_energy_per_cycle_mux[0to25] -+ param='sum_energy_per_cycle_mux[0to24]+energy_per_cycle_sb_mux[1][1]_rrnode[188]' -***** Load for rr_node[188] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=21, type=4 ***** -Xchan_mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[40]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to25] -+ param='sum_leakage_power_sb_mux[0to24]+leakage_sb_mux[1][1]_rrnode[188]' -.meas tran sum_energy_per_cycle_sb_mux[0to25] -+ param='sum_energy_per_cycle_sb_mux[0to24]+energy_per_cycle_sb_mux[1][1]_rrnode[188]' -Xmux_1level_tapbuf_size2[26] mux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->out sram[34]->outb sram[34]->out gvdd_mux_1level_tapbuf_size2[26] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[26], level=1, select_path_id=0. ***** -*****1***** -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -***** Signal mux_1level_tapbuf_size2[26]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[26]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[26] gvdd_mux_1level_tapbuf_size2[26] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[190] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[190] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[190] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[190] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[190] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[190] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[190] param='mux_1level_tapbuf_size2[26]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[26]_energy_per_cycle param='mux_1level_tapbuf_size2[26]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[190] param='mux_1level_tapbuf_size2[26]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[190] param='dynamic_power_sb_mux[1][1]_rrnode[190]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[190] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_rise_sb_mux[1][1]_rrnode[190]' to='start_rise_sb_mux[1][1]_rrnode[190]+switch_rise_sb_mux[1][1]_rrnode[190]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[190] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_fall_sb_mux[1][1]_rrnode[190]' to='start_fall_sb_mux[1][1]_rrnode[190]+switch_fall_sb_mux[1][1]_rrnode[190]' -.meas tran sum_leakage_power_mux[0to26] -+ param='sum_leakage_power_mux[0to25]+leakage_sb_mux[1][1]_rrnode[190]' -.meas tran sum_energy_per_cycle_mux[0to26] -+ param='sum_energy_per_cycle_mux[0to25]+energy_per_cycle_sb_mux[1][1]_rrnode[190]' -***** Load for rr_node[190] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=23, type=4 ***** -Xchan_mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[42]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to26] -+ param='sum_leakage_power_sb_mux[0to25]+leakage_sb_mux[1][1]_rrnode[190]' -.meas tran sum_energy_per_cycle_sb_mux[0to26] -+ param='sum_energy_per_cycle_sb_mux[0to25]+energy_per_cycle_sb_mux[1][1]_rrnode[190]' -Xmux_1level_tapbuf_size2[27] mux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->out sram[35]->outb sram[35]->out gvdd_mux_1level_tapbuf_size2[27] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[27], level=1, select_path_id=0. ***** -*****1***** -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -***** Signal mux_1level_tapbuf_size2[27]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[27]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[27] gvdd_mux_1level_tapbuf_size2[27] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[192] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[192] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[192] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[192] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[192] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[192] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[192] param='mux_1level_tapbuf_size2[27]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[27]_energy_per_cycle param='mux_1level_tapbuf_size2[27]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[192] param='mux_1level_tapbuf_size2[27]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[192] param='dynamic_power_sb_mux[1][1]_rrnode[192]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[192] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_rise_sb_mux[1][1]_rrnode[192]' to='start_rise_sb_mux[1][1]_rrnode[192]+switch_rise_sb_mux[1][1]_rrnode[192]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[192] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_fall_sb_mux[1][1]_rrnode[192]' to='start_fall_sb_mux[1][1]_rrnode[192]+switch_fall_sb_mux[1][1]_rrnode[192]' -.meas tran sum_leakage_power_mux[0to27] -+ param='sum_leakage_power_mux[0to26]+leakage_sb_mux[1][1]_rrnode[192]' -.meas tran sum_energy_per_cycle_mux[0to27] -+ param='sum_energy_per_cycle_mux[0to26]+energy_per_cycle_sb_mux[1][1]_rrnode[192]' -***** Load for rr_node[192] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=25, type=4 ***** -Xchan_mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[44]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to27] -+ param='sum_leakage_power_sb_mux[0to26]+leakage_sb_mux[1][1]_rrnode[192]' -.meas tran sum_energy_per_cycle_sb_mux[0to27] -+ param='sum_energy_per_cycle_sb_mux[0to26]+energy_per_cycle_sb_mux[1][1]_rrnode[192]' -Xmux_1level_tapbuf_size2[28] mux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->out sram[36]->outb sram[36]->out gvdd_mux_1level_tapbuf_size2[28] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[28], level=1, select_path_id=0. ***** -*****1***** -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -***** Signal mux_1level_tapbuf_size2[28]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[28]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[28] gvdd_mux_1level_tapbuf_size2[28] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[194] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[194] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[194] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[194] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[194] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[194] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[194] param='mux_1level_tapbuf_size2[28]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[28]_energy_per_cycle param='mux_1level_tapbuf_size2[28]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[194] param='mux_1level_tapbuf_size2[28]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[194] param='dynamic_power_sb_mux[1][1]_rrnode[194]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[194] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_rise_sb_mux[1][1]_rrnode[194]' to='start_rise_sb_mux[1][1]_rrnode[194]+switch_rise_sb_mux[1][1]_rrnode[194]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[194] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_fall_sb_mux[1][1]_rrnode[194]' to='start_fall_sb_mux[1][1]_rrnode[194]+switch_fall_sb_mux[1][1]_rrnode[194]' -.meas tran sum_leakage_power_mux[0to28] -+ param='sum_leakage_power_mux[0to27]+leakage_sb_mux[1][1]_rrnode[194]' -.meas tran sum_energy_per_cycle_mux[0to28] -+ param='sum_energy_per_cycle_mux[0to27]+energy_per_cycle_sb_mux[1][1]_rrnode[194]' -***** Load for rr_node[194] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=27, type=4 ***** -Xchan_mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[46]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to28] -+ param='sum_leakage_power_sb_mux[0to27]+leakage_sb_mux[1][1]_rrnode[194]' -.meas tran sum_energy_per_cycle_sb_mux[0to28] -+ param='sum_energy_per_cycle_sb_mux[0to27]+energy_per_cycle_sb_mux[1][1]_rrnode[194]' -Xmux_1level_tapbuf_size2[29] mux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->out sram[37]->outb sram[37]->out gvdd_mux_1level_tapbuf_size2[29] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[29], level=1, select_path_id=0. ***** -*****1***** -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -***** Signal mux_1level_tapbuf_size2[29]->in[0] density = 0.1906, probability=0.4782.***** -Vmux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -***** Signal mux_1level_tapbuf_size2[29]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[29] gvdd_mux_1level_tapbuf_size2[29] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[196] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[196] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[196] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[196] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[196] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[196] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[196] param='mux_1level_tapbuf_size2[29]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='clock_period' to='7*clock_period' -.meas tran mux_1level_tapbuf_size2[29]_energy_per_cycle param='mux_1level_tapbuf_size2[29]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[196] param='mux_1level_tapbuf_size2[29]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[196] param='dynamic_power_sb_mux[1][1]_rrnode[196]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[196] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_rise_sb_mux[1][1]_rrnode[196]' to='start_rise_sb_mux[1][1]_rrnode[196]+switch_rise_sb_mux[1][1]_rrnode[196]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[196] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_fall_sb_mux[1][1]_rrnode[196]' to='start_fall_sb_mux[1][1]_rrnode[196]+switch_fall_sb_mux[1][1]_rrnode[196]' -.meas tran sum_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to28]+leakage_sb_mux[1][1]_rrnode[196]' -.meas tran sum_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to28]+energy_per_cycle_sb_mux[1][1]_rrnode[196]' -***** Load for rr_node[196] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=29, type=4 ***** -Xchan_mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[48]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to29] -+ param='sum_leakage_power_sb_mux[0to28]+leakage_sb_mux[1][1]_rrnode[196]' -.meas tran sum_energy_per_cycle_sb_mux[0to29] -+ param='sum_energy_per_cycle_sb_mux[0to28]+energy_per_cycle_sb_mux[1][1]_rrnode[196]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='7*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to29]' -.meas tran total_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to29]' -.meas tran total_leakage_power_sb_mux -+ param='sum_leakage_power_sb_mux[0to29]' -.meas tran total_energy_per_cycle_sb_mux -+ param='sum_energy_per_cycle_sb_mux[0to29]' -.end diff --git a/examples/spice_test_example_1/sb_tb/example_1_sb0_0_sb_testbench.sp b/examples/spice_test_example_1/sb_tb/example_1_sb0_0_sb_testbench.sp deleted file mode 100644 index ec57014ef..000000000 --- a/examples/spice_test_example_1/sb_tb/example_1_sb0_0_sb_testbench.sp +++ /dev/null @@ -1,399 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_sbs -****** Include subckt netlists: Switch Block[0][0] ***** -.include './spice_test_example_1/subckt/sb_0_0.sp' -***** Call defined Switch Box[0][0] ***** -Xsb[0][0] -+ chany[0][1]_out[0] chany[0][1]_in[1] chany[0][1]_out[2] chany[0][1]_in[3] chany[0][1]_out[4] chany[0][1]_in[5] chany[0][1]_out[6] chany[0][1]_in[7] chany[0][1]_out[8] chany[0][1]_in[9] chany[0][1]_out[10] chany[0][1]_in[11] chany[0][1]_out[12] chany[0][1]_in[13] chany[0][1]_out[14] chany[0][1]_in[15] chany[0][1]_out[16] chany[0][1]_in[17] chany[0][1]_out[18] chany[0][1]_in[19] chany[0][1]_out[20] chany[0][1]_in[21] chany[0][1]_out[22] chany[0][1]_in[23] chany[0][1]_out[24] chany[0][1]_in[25] chany[0][1]_out[26] chany[0][1]_in[27] chany[0][1]_out[28] chany[0][1]_in[29] -+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] -+ chanx[1][0]_out[0] chanx[1][0]_in[1] chanx[1][0]_out[2] chanx[1][0]_in[3] chanx[1][0]_out[4] chanx[1][0]_in[5] chanx[1][0]_out[6] chanx[1][0]_in[7] chanx[1][0]_out[8] chanx[1][0]_in[9] chanx[1][0]_out[10] chanx[1][0]_in[11] chanx[1][0]_out[12] chanx[1][0]_in[13] chanx[1][0]_out[14] chanx[1][0]_in[15] chanx[1][0]_out[16] chanx[1][0]_in[17] chanx[1][0]_out[18] chanx[1][0]_in[19] chanx[1][0]_out[20] chanx[1][0]_in[21] chanx[1][0]_out[22] chanx[1][0]_in[23] chanx[1][0]_out[24] chanx[1][0]_in[25] chanx[1][0]_out[26] chanx[1][0]_in[27] chanx[1][0]_out[28] chanx[1][0]_in[29] -+ grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ -+ -+ -+ -+ gvdd_sb[0][0] 0 sb[0][0] -**** Load for rr_node[197] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=0, type=5 ***** -Xchan_chany[0][1]_out[0]_loadlvl[0]_out chany[0][1]_out[0] chany[0][1]_out[0]_loadlvl[0]_out chany[0][1]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 chany[0][1]_out[0]_loadlvl[0]_out chany[0][1]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 chany[0][1]_out[0]_loadlvl[0]_midout chany[0][1]_out[0]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[1] density = 0, probability=0.***** -Vchany[0][1]_in[1] chany[0][1]_in[1] 0 -+ 0 -**** Load for rr_node[199] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=2, type=5 ***** -Xchan_chany[0][1]_out[2]_loadlvl[0]_out chany[0][1]_out[2] chany[0][1]_out[2]_loadlvl[0]_out chany[0][1]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 chany[0][1]_out[2]_loadlvl[0]_out chany[0][1]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 chany[0][1]_out[2]_loadlvl[0]_midout chany[0][1]_out[2]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[3] density = 0, probability=0.***** -Vchany[0][1]_in[3] chany[0][1]_in[3] 0 -+ 0 -**** Load for rr_node[201] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=4, type=5 ***** -Xchan_chany[0][1]_out[4]_loadlvl[0]_out chany[0][1]_out[4] chany[0][1]_out[4]_loadlvl[0]_out chany[0][1]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[4]_no0 chany[0][1]_out[4]_loadlvl[0]_out chany[0][1]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 chany[0][1]_out[4]_loadlvl[0]_midout chany[0][1]_out[4]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[5] density = 0, probability=0.***** -Vchany[0][1]_in[5] chany[0][1]_in[5] 0 -+ 0 -**** Load for rr_node[203] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=6, type=5 ***** -Xchan_chany[0][1]_out[6]_loadlvl[0]_out chany[0][1]_out[6] chany[0][1]_out[6]_loadlvl[0]_out chany[0][1]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[6]_no0 chany[0][1]_out[6]_loadlvl[0]_out chany[0][1]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 chany[0][1]_out[6]_loadlvl[0]_midout chany[0][1]_out[6]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 chany[0][1]_out[6]_loadlvl[0]_midout chany[0][1]_out[6]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[7] density = 0, probability=0.***** -Vchany[0][1]_in[7] chany[0][1]_in[7] 0 -+ 0 -**** Load for rr_node[205] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=8, type=5 ***** -Xchan_chany[0][1]_out[8]_loadlvl[0]_out chany[0][1]_out[8] chany[0][1]_out[8]_loadlvl[0]_out chany[0][1]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[9]_no0 chany[0][1]_out[8]_loadlvl[0]_out chany[0][1]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 chany[0][1]_out[8]_loadlvl[0]_midout chany[0][1]_out[8]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[9] density = 0, probability=0.***** -Vchany[0][1]_in[9] chany[0][1]_in[9] 0 -+ 0 -**** Load for rr_node[207] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=10, type=5 ***** -Xchan_chany[0][1]_out[10]_loadlvl[0]_out chany[0][1]_out[10] chany[0][1]_out[10]_loadlvl[0]_out chany[0][1]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[11]_no0 chany[0][1]_out[10]_loadlvl[0]_out chany[0][1]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 chany[0][1]_out[10]_loadlvl[0]_midout chany[0][1]_out[10]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 chany[0][1]_out[10]_loadlvl[0]_midout chany[0][1]_out[10]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[11] density = 0, probability=0.***** -Vchany[0][1]_in[11] chany[0][1]_in[11] 0 -+ 0 -**** Load for rr_node[209] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=12, type=5 ***** -Xchan_chany[0][1]_out[12]_loadlvl[0]_out chany[0][1]_out[12] chany[0][1]_out[12]_loadlvl[0]_out chany[0][1]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[14]_no0 chany[0][1]_out[12]_loadlvl[0]_out chany[0][1]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 chany[0][1]_out[12]_loadlvl[0]_midout chany[0][1]_out[12]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[13] density = 0, probability=0.***** -Vchany[0][1]_in[13] chany[0][1]_in[13] 0 -+ 0 -**** Load for rr_node[211] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=14, type=5 ***** -Xchan_chany[0][1]_out[14]_loadlvl[0]_out chany[0][1]_out[14] chany[0][1]_out[14]_loadlvl[0]_out chany[0][1]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[16]_no0 chany[0][1]_out[14]_loadlvl[0]_out chany[0][1]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 chany[0][1]_out[14]_loadlvl[0]_midout chany[0][1]_out[14]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[15] density = 0, probability=0.***** -Vchany[0][1]_in[15] chany[0][1]_in[15] 0 -+ 0 -**** Load for rr_node[213] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=16, type=5 ***** -Xchan_chany[0][1]_out[16]_loadlvl[0]_out chany[0][1]_out[16] chany[0][1]_out[16]_loadlvl[0]_out chany[0][1]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[18]_no0 chany[0][1]_out[16]_loadlvl[0]_out chany[0][1]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 chany[0][1]_out[16]_loadlvl[0]_midout chany[0][1]_out[16]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[17] density = 0, probability=0.***** -Vchany[0][1]_in[17] chany[0][1]_in[17] 0 -+ 0 -**** Load for rr_node[215] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=18, type=5 ***** -Xchan_chany[0][1]_out[18]_loadlvl[0]_out chany[0][1]_out[18] chany[0][1]_out[18]_loadlvl[0]_out chany[0][1]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[20]_no0 chany[0][1]_out[18]_loadlvl[0]_out chany[0][1]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 chany[0][1]_out[18]_loadlvl[0]_midout chany[0][1]_out[18]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[19] density = 0, probability=0.***** -Vchany[0][1]_in[19] chany[0][1]_in[19] 0 -+ 0 -**** Load for rr_node[217] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=20, type=5 ***** -Xchan_chany[0][1]_out[20]_loadlvl[0]_out chany[0][1]_out[20] chany[0][1]_out[20]_loadlvl[0]_out chany[0][1]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[22]_no0 chany[0][1]_out[20]_loadlvl[0]_out chany[0][1]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 chany[0][1]_out[20]_loadlvl[0]_midout chany[0][1]_out[20]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[21] density = 0, probability=0.***** -Vchany[0][1]_in[21] chany[0][1]_in[21] 0 -+ 0 -**** Load for rr_node[219] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=22, type=5 ***** -Xchan_chany[0][1]_out[22]_loadlvl[0]_out chany[0][1]_out[22] chany[0][1]_out[22]_loadlvl[0]_out chany[0][1]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[24]_no0 chany[0][1]_out[22]_loadlvl[0]_out chany[0][1]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 chany[0][1]_out[22]_loadlvl[0]_midout chany[0][1]_out[22]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[23] density = 0, probability=0.***** -Vchany[0][1]_in[23] chany[0][1]_in[23] 0 -+ 0 -**** Load for rr_node[221] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=24, type=5 ***** -Xchan_chany[0][1]_out[24]_loadlvl[0]_out chany[0][1]_out[24] chany[0][1]_out[24]_loadlvl[0]_out chany[0][1]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[26]_no0 chany[0][1]_out[24]_loadlvl[0]_out chany[0][1]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 chany[0][1]_out[24]_loadlvl[0]_midout chany[0][1]_out[24]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[25] density = 0, probability=0.***** -Vchany[0][1]_in[25] chany[0][1]_in[25] 0 -+ 0 -**** Load for rr_node[223] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=26, type=5 ***** -Xchan_chany[0][1]_out[26]_loadlvl[0]_out chany[0][1]_out[26] chany[0][1]_out[26]_loadlvl[0]_out chany[0][1]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[28]_no0 chany[0][1]_out[26]_loadlvl[0]_out chany[0][1]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 chany[0][1]_out[26]_loadlvl[0]_midout chany[0][1]_out[26]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 chany[0][1]_out[26]_loadlvl[0]_midout chany[0][1]_out[26]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[27] density = 0.1906, probability=0.4782.***** -Vchany[0][1]_in[27] chany[0][1]_in[27] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -**** Load for rr_node[225] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=28, type=5 ***** -Xchan_chany[0][1]_out[28]_loadlvl[0]_out chany[0][1]_out[28] chany[0][1]_out[28]_loadlvl[0]_out chany[0][1]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[31]_no0 chany[0][1]_out[28]_loadlvl[0]_out chany[0][1]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 chany[0][1]_out[28]_loadlvl[0]_midout chany[0][1]_out[28]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[29] density = 0, probability=0.***** -Vchany[0][1]_in[29] chany[0][1]_in[29] 0 -+ 0 -Vgrid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][1] 0 -+ 0 -Vgrid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][3] 0 -+ 0 -Vgrid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][5] 0 -+ 0 -Vgrid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][7] 0 -+ 0 -Vgrid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][9] 0 -+ 0 -Vgrid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][11] 0 -+ 0 -Vgrid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][13] 0 -+ 0 -Vgrid[0][1]_pin[0][1][15] grid[0][1]_pin[0][1][15] 0 -+ 0 - -**** Load for rr_node[137] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=0, type=4 ***** -Xchan_chanx[1][0]_out[0]_loadlvl[0]_out chanx[1][0]_out[0] chanx[1][0]_out[0]_loadlvl[0]_out chanx[1][0]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[33]_no0 chanx[1][0]_out[0]_loadlvl[0]_out chanx[1][0]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 chanx[1][0]_out[0]_loadlvl[0]_midout chanx[1][0]_out[0]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 chanx[1][0]_out[0]_loadlvl[0]_midout chanx[1][0]_out[0]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[1] density = 0, probability=0.***** -Vchanx[1][0]_in[1] chanx[1][0]_in[1] 0 -+ 0 -**** Load for rr_node[139] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=2, type=4 ***** -Xchan_chanx[1][0]_out[2]_loadlvl[0]_out chanx[1][0]_out[2] chanx[1][0]_out[2]_loadlvl[0]_out chanx[1][0]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[36]_no0 chanx[1][0]_out[2]_loadlvl[0]_out chanx[1][0]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 chanx[1][0]_out[2]_loadlvl[0]_midout chanx[1][0]_out[2]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[3] density = 0, probability=0.***** -Vchanx[1][0]_in[3] chanx[1][0]_in[3] 0 -+ 0 -**** Load for rr_node[141] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=4, type=4 ***** -Xchan_chanx[1][0]_out[4]_loadlvl[0]_out chanx[1][0]_out[4] chanx[1][0]_out[4]_loadlvl[0]_out chanx[1][0]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[38]_no0 chanx[1][0]_out[4]_loadlvl[0]_out chanx[1][0]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 chanx[1][0]_out[4]_loadlvl[0]_midout chanx[1][0]_out[4]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[5] density = 0, probability=0.***** -Vchanx[1][0]_in[5] chanx[1][0]_in[5] 0 -+ 0 -**** Load for rr_node[143] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=6, type=4 ***** -Xchan_chanx[1][0]_out[6]_loadlvl[0]_out chanx[1][0]_out[6] chanx[1][0]_out[6]_loadlvl[0]_out chanx[1][0]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[40]_no0 chanx[1][0]_out[6]_loadlvl[0]_out chanx[1][0]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 chanx[1][0]_out[6]_loadlvl[0]_midout chanx[1][0]_out[6]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 chanx[1][0]_out[6]_loadlvl[0]_midout chanx[1][0]_out[6]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[7] density = 0, probability=0.***** -Vchanx[1][0]_in[7] chanx[1][0]_in[7] 0 -+ 0 -**** Load for rr_node[145] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=8, type=4 ***** -Xchan_chanx[1][0]_out[8]_loadlvl[0]_out chanx[1][0]_out[8] chanx[1][0]_out[8]_loadlvl[0]_out chanx[1][0]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[43]_no0 chanx[1][0]_out[8]_loadlvl[0]_out chanx[1][0]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 chanx[1][0]_out[8]_loadlvl[0]_midout chanx[1][0]_out[8]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[9] density = 0, probability=0.***** -Vchanx[1][0]_in[9] chanx[1][0]_in[9] 0 -+ 0 -**** Load for rr_node[147] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=10, type=4 ***** -Xchan_chanx[1][0]_out[10]_loadlvl[0]_out chanx[1][0]_out[10] chanx[1][0]_out[10]_loadlvl[0]_out chanx[1][0]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[45]_no0 chanx[1][0]_out[10]_loadlvl[0]_out chanx[1][0]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 chanx[1][0]_out[10]_loadlvl[0]_midout chanx[1][0]_out[10]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[11] density = 0, probability=0.***** -Vchanx[1][0]_in[11] chanx[1][0]_in[11] 0 -+ 0 -**** Load for rr_node[149] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=12, type=4 ***** -Xchan_chanx[1][0]_out[12]_loadlvl[0]_out chanx[1][0]_out[12] chanx[1][0]_out[12]_loadlvl[0]_out chanx[1][0]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[47]_no0 chanx[1][0]_out[12]_loadlvl[0]_out chanx[1][0]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 chanx[1][0]_out[12]_loadlvl[0]_midout chanx[1][0]_out[12]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[13] density = 0, probability=0.***** -Vchanx[1][0]_in[13] chanx[1][0]_in[13] 0 -+ 0 -**** Load for rr_node[151] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=14, type=4 ***** -Xchan_chanx[1][0]_out[14]_loadlvl[0]_out chanx[1][0]_out[14] chanx[1][0]_out[14]_loadlvl[0]_out chanx[1][0]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[49]_no0 chanx[1][0]_out[14]_loadlvl[0]_out chanx[1][0]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 chanx[1][0]_out[14]_loadlvl[0]_midout chanx[1][0]_out[14]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[15] density = 0, probability=0.***** -Vchanx[1][0]_in[15] chanx[1][0]_in[15] 0 -+ 0 -**** Load for rr_node[153] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=16, type=4 ***** -Xchan_chanx[1][0]_out[16]_loadlvl[0]_out chanx[1][0]_out[16] chanx[1][0]_out[16]_loadlvl[0]_out chanx[1][0]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[51]_no0 chanx[1][0]_out[16]_loadlvl[0]_out chanx[1][0]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 chanx[1][0]_out[16]_loadlvl[0]_midout chanx[1][0]_out[16]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[17] density = 0, probability=0.***** -Vchanx[1][0]_in[17] chanx[1][0]_in[17] 0 -+ 0 -**** Load for rr_node[155] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=18, type=4 ***** -Xchan_chanx[1][0]_out[18]_loadlvl[0]_out chanx[1][0]_out[18] chanx[1][0]_out[18]_loadlvl[0]_out chanx[1][0]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[53]_no0 chanx[1][0]_out[18]_loadlvl[0]_out chanx[1][0]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 chanx[1][0]_out[18]_loadlvl[0]_midout chanx[1][0]_out[18]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[19] density = 0, probability=0.***** -Vchanx[1][0]_in[19] chanx[1][0]_in[19] 0 -+ 0 -**** Load for rr_node[157] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=20, type=4 ***** -Xchan_chanx[1][0]_out[20]_loadlvl[0]_out chanx[1][0]_out[20] chanx[1][0]_out[20]_loadlvl[0]_out chanx[1][0]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[55]_no0 chanx[1][0]_out[20]_loadlvl[0]_out chanx[1][0]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 chanx[1][0]_out[20]_loadlvl[0]_midout chanx[1][0]_out[20]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[21] density = 0, probability=0.***** -Vchanx[1][0]_in[21] chanx[1][0]_in[21] 0 -+ 0 -**** Load for rr_node[159] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=22, type=4 ***** -Xchan_chanx[1][0]_out[22]_loadlvl[0]_out chanx[1][0]_out[22] chanx[1][0]_out[22]_loadlvl[0]_out chanx[1][0]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[57]_no0 chanx[1][0]_out[22]_loadlvl[0]_out chanx[1][0]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 chanx[1][0]_out[22]_loadlvl[0]_midout chanx[1][0]_out[22]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 chanx[1][0]_out[22]_loadlvl[0]_midout chanx[1][0]_out[22]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[23] density = 0, probability=0.***** -Vchanx[1][0]_in[23] chanx[1][0]_in[23] 0 -+ 0 -**** Load for rr_node[161] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=24, type=4 ***** -Xchan_chanx[1][0]_out[24]_loadlvl[0]_out chanx[1][0]_out[24] chanx[1][0]_out[24]_loadlvl[0]_out chanx[1][0]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[60]_no0 chanx[1][0]_out[24]_loadlvl[0]_out chanx[1][0]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 chanx[1][0]_out[24]_loadlvl[0]_midout chanx[1][0]_out[24]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[25] density = 0, probability=0.***** -Vchanx[1][0]_in[25] chanx[1][0]_in[25] 0 -+ 0 -**** Load for rr_node[163] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=26, type=4 ***** -Xchan_chanx[1][0]_out[26]_loadlvl[0]_out chanx[1][0]_out[26] chanx[1][0]_out[26]_loadlvl[0]_out chanx[1][0]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[62]_no0 chanx[1][0]_out[26]_loadlvl[0]_out chanx[1][0]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 chanx[1][0]_out[26]_loadlvl[0]_midout chanx[1][0]_out[26]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[27] density = 0, probability=0.***** -Vchanx[1][0]_in[27] chanx[1][0]_in[27] 0 -+ 0 -**** Load for rr_node[165] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=28, type=4 ***** -Xchan_chanx[1][0]_out[28]_loadlvl[0]_out chanx[1][0]_out[28] chanx[1][0]_out[28]_loadlvl[0]_out chanx[1][0]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[64]_no0 chanx[1][0]_out[28]_loadlvl[0]_out chanx[1][0]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 chanx[1][0]_out[28]_loadlvl[0]_midout chanx[1][0]_out[28]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[29] density = 0, probability=0.***** -Vchanx[1][0]_in[29] chanx[1][0]_in[29] 0 -+ 0 -Vgrid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][1] 0 -+ 0 -Vgrid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][3] 0 -+ 0 -Vgrid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][5] 0 -+ 0 -Vgrid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][7] 0 -+ 0 -Vgrid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][9] 0 -+ 0 -Vgrid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][11] 0 -+ 0 -Vgrid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][13] 0 -+ 0 -Vgrid[1][0]_pin[0][0][15] grid[1][0]_pin[0][0][15] 0 -+ 0 - - - -***** Voltage supplies ***** -Vgvdd_sb[0][0] gvdd_sb[0][0] 0 vsp -Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_sb avg p(Vgvdd_sb[0][0]) from=0 to='clock_period' -.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_sb avg p(Vgvdd_sb[0][0]) from='clock_period' to='7*clock_period' -.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period' -.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='7*clock_period' -.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_1/sb_tb/example_1_sb0_1_sb_testbench.sp b/examples/spice_test_example_1/sb_tb/example_1_sb0_1_sb_testbench.sp deleted file mode 100644 index 36ec8022c..000000000 --- a/examples/spice_test_example_1/sb_tb/example_1_sb0_1_sb_testbench.sp +++ /dev/null @@ -1,409 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_sbs -****** Include subckt netlists: Switch Block[0][1] ***** -.include './spice_test_example_1/subckt/sb_0_1.sp' -***** Call defined Switch Box[0][1] ***** -Xsb[0][1] -+ -+ -+ chanx[1][1]_out[0] chanx[1][1]_in[1] chanx[1][1]_out[2] chanx[1][1]_in[3] chanx[1][1]_out[4] chanx[1][1]_in[5] chanx[1][1]_out[6] chanx[1][1]_in[7] chanx[1][1]_out[8] chanx[1][1]_in[9] chanx[1][1]_out[10] chanx[1][1]_in[11] chanx[1][1]_out[12] chanx[1][1]_in[13] chanx[1][1]_out[14] chanx[1][1]_in[15] chanx[1][1]_out[16] chanx[1][1]_in[17] chanx[1][1]_out[18] chanx[1][1]_in[19] chanx[1][1]_out[20] chanx[1][1]_in[21] chanx[1][1]_out[22] chanx[1][1]_in[23] chanx[1][1]_out[24] chanx[1][1]_in[25] chanx[1][1]_out[26] chanx[1][1]_in[27] chanx[1][1]_out[28] chanx[1][1]_in[29] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][4] -+ chany[0][1]_in[0] chany[0][1]_out[1] chany[0][1]_in[2] chany[0][1]_out[3] chany[0][1]_in[4] chany[0][1]_out[5] chany[0][1]_in[6] chany[0][1]_out[7] chany[0][1]_in[8] chany[0][1]_out[9] chany[0][1]_in[10] chany[0][1]_out[11] chany[0][1]_in[12] chany[0][1]_out[13] chany[0][1]_in[14] chany[0][1]_out[15] chany[0][1]_in[16] chany[0][1]_out[17] chany[0][1]_in[18] chany[0][1]_out[19] chany[0][1]_in[20] chany[0][1]_out[21] chany[0][1]_in[22] chany[0][1]_out[23] chany[0][1]_in[24] chany[0][1]_out[25] chany[0][1]_in[26] chany[0][1]_out[27] chany[0][1]_in[28] chany[0][1]_out[29] -+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] -+ -+ -+ gvdd_sb[0][1] 0 sb[0][1] - -**** Load for rr_node[167] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=0, type=4 ***** -Xchan_chanx[1][1]_out[0]_loadlvl[0]_out chanx[1][1]_out[0] chanx[1][1]_out[0]_loadlvl[0]_out chanx[1][1]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 chanx[1][1]_out[0]_loadlvl[0]_out chanx[1][1]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 chanx[1][1]_out[0]_loadlvl[0]_midout chanx[1][1]_out[0]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[1] density = 0.1906, probability=0.4782.***** -Vchanx[1][1]_in[1] chanx[1][1]_in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -**** Load for rr_node[169] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=2, type=4 ***** -Xchan_chanx[1][1]_out[2]_loadlvl[0]_out chanx[1][1]_out[2] chanx[1][1]_out[2]_loadlvl[0]_out chanx[1][1]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 chanx[1][1]_out[2]_loadlvl[0]_out chanx[1][1]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 chanx[1][1]_out[2]_loadlvl[0]_midout chanx[1][1]_out[2]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[3] density = 0.1906, probability=0.5218.***** -Vchanx[1][1]_in[3] chanx[1][1]_in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -**** Load for rr_node[171] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=4, type=4 ***** -Xchan_chanx[1][1]_out[4]_loadlvl[0]_out chanx[1][1]_out[4] chanx[1][1]_out[4]_loadlvl[0]_out chanx[1][1]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[4]_no0 chanx[1][1]_out[4]_loadlvl[0]_out chanx[1][1]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 chanx[1][1]_out[4]_loadlvl[0]_midout chanx[1][1]_out[4]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[5] density = 0, probability=0.***** -Vchanx[1][1]_in[5] chanx[1][1]_in[5] 0 -+ 0 -**** Load for rr_node[173] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=6, type=4 ***** -Xchan_chanx[1][1]_out[6]_loadlvl[0]_out chanx[1][1]_out[6] chanx[1][1]_out[6]_loadlvl[0]_out chanx[1][1]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[6]_no0 chanx[1][1]_out[6]_loadlvl[0]_out chanx[1][1]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 chanx[1][1]_out[6]_loadlvl[0]_midout chanx[1][1]_out[6]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 chanx[1][1]_out[6]_loadlvl[0]_midout chanx[1][1]_out[6]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[7] density = 0, probability=0.***** -Vchanx[1][1]_in[7] chanx[1][1]_in[7] 0 -+ 0 -**** Load for rr_node[175] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=8, type=4 ***** -Xchan_chanx[1][1]_out[8]_loadlvl[0]_out chanx[1][1]_out[8] chanx[1][1]_out[8]_loadlvl[0]_out chanx[1][1]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[9]_no0 chanx[1][1]_out[8]_loadlvl[0]_out chanx[1][1]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 chanx[1][1]_out[8]_loadlvl[0]_midout chanx[1][1]_out[8]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[9] density = 0, probability=0.***** -Vchanx[1][1]_in[9] chanx[1][1]_in[9] 0 -+ 0 -**** Load for rr_node[177] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=10, type=4 ***** -Xchan_chanx[1][1]_out[10]_loadlvl[0]_out chanx[1][1]_out[10] chanx[1][1]_out[10]_loadlvl[0]_out chanx[1][1]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[11]_no0 chanx[1][1]_out[10]_loadlvl[0]_out chanx[1][1]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 chanx[1][1]_out[10]_loadlvl[0]_midout chanx[1][1]_out[10]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[11] density = 0, probability=0.***** -Vchanx[1][1]_in[11] chanx[1][1]_in[11] 0 -+ 0 -**** Load for rr_node[179] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=12, type=4 ***** -Xchan_chanx[1][1]_out[12]_loadlvl[0]_out chanx[1][1]_out[12] chanx[1][1]_out[12]_loadlvl[0]_out chanx[1][1]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[13]_no0 chanx[1][1]_out[12]_loadlvl[0]_out chanx[1][1]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 chanx[1][1]_out[12]_loadlvl[0]_midout chanx[1][1]_out[12]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 chanx[1][1]_out[12]_loadlvl[0]_midout chanx[1][1]_out[12]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 chanx[1][1]_out[12]_loadlvl[0]_midout chanx[1][1]_out[12]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[13] density = 0, probability=0.***** -Vchanx[1][1]_in[13] chanx[1][1]_in[13] 0 -+ 0 -**** Load for rr_node[181] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=14, type=4 ***** -Xchan_chanx[1][1]_out[14]_loadlvl[0]_out chanx[1][1]_out[14] chanx[1][1]_out[14]_loadlvl[0]_out chanx[1][1]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[17]_no0 chanx[1][1]_out[14]_loadlvl[0]_out chanx[1][1]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 chanx[1][1]_out[14]_loadlvl[0]_midout chanx[1][1]_out[14]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[15] density = 0, probability=0.***** -Vchanx[1][1]_in[15] chanx[1][1]_in[15] 0 -+ 0 -**** Load for rr_node[183] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=16, type=4 ***** -Xchan_chanx[1][1]_out[16]_loadlvl[0]_out chanx[1][1]_out[16] chanx[1][1]_out[16]_loadlvl[0]_out chanx[1][1]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[19]_no0 chanx[1][1]_out[16]_loadlvl[0]_out chanx[1][1]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 chanx[1][1]_out[16]_loadlvl[0]_midout chanx[1][1]_out[16]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[17] density = 0, probability=0.***** -Vchanx[1][1]_in[17] chanx[1][1]_in[17] 0 -+ 0 -**** Load for rr_node[185] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=18, type=4 ***** -Xchan_chanx[1][1]_out[18]_loadlvl[0]_out chanx[1][1]_out[18] chanx[1][1]_out[18]_loadlvl[0]_out chanx[1][1]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[21]_no0 chanx[1][1]_out[18]_loadlvl[0]_out chanx[1][1]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 chanx[1][1]_out[18]_loadlvl[0]_midout chanx[1][1]_out[18]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[19] density = 0, probability=0.***** -Vchanx[1][1]_in[19] chanx[1][1]_in[19] 0 -+ 0 -**** Load for rr_node[187] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=20, type=4 ***** -Xchan_chanx[1][1]_out[20]_loadlvl[0]_out chanx[1][1]_out[20] chanx[1][1]_out[20]_loadlvl[0]_out chanx[1][1]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[23]_no0 chanx[1][1]_out[20]_loadlvl[0]_out chanx[1][1]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 chanx[1][1]_out[20]_loadlvl[0]_midout chanx[1][1]_out[20]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[21] density = 0, probability=0.***** -Vchanx[1][1]_in[21] chanx[1][1]_in[21] 0 -+ 0 -**** Load for rr_node[189] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=22, type=4 ***** -Xchan_chanx[1][1]_out[22]_loadlvl[0]_out chanx[1][1]_out[22] chanx[1][1]_out[22]_loadlvl[0]_out chanx[1][1]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[25]_no0 chanx[1][1]_out[22]_loadlvl[0]_out chanx[1][1]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 chanx[1][1]_out[22]_loadlvl[0]_midout chanx[1][1]_out[22]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[23] density = 0, probability=0.***** -Vchanx[1][1]_in[23] chanx[1][1]_in[23] 0 -+ 0 -**** Load for rr_node[191] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=24, type=4 ***** -Xchan_chanx[1][1]_out[24]_loadlvl[0]_out chanx[1][1]_out[24] chanx[1][1]_out[24]_loadlvl[0]_out chanx[1][1]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[27]_no0 chanx[1][1]_out[24]_loadlvl[0]_out chanx[1][1]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 chanx[1][1]_out[24]_loadlvl[0]_midout chanx[1][1]_out[24]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[25] density = 0, probability=0.***** -Vchanx[1][1]_in[25] chanx[1][1]_in[25] 0 -+ 0 -**** Load for rr_node[193] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=26, type=4 ***** -Xchan_chanx[1][1]_out[26]_loadlvl[0]_out chanx[1][1]_out[26] chanx[1][1]_out[26]_loadlvl[0]_out chanx[1][1]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[29]_no0 chanx[1][1]_out[26]_loadlvl[0]_out chanx[1][1]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 chanx[1][1]_out[26]_loadlvl[0]_midout chanx[1][1]_out[26]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[27] density = 0, probability=0.***** -Vchanx[1][1]_in[27] chanx[1][1]_in[27] 0 -+ 0 -**** Load for rr_node[195] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=28, type=4 ***** -Xchan_chanx[1][1]_out[28]_loadlvl[0]_out chanx[1][1]_out[28] chanx[1][1]_out[28]_loadlvl[0]_out chanx[1][1]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[31]_no0 chanx[1][1]_out[28]_loadlvl[0]_out chanx[1][1]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 chanx[1][1]_out[28]_loadlvl[0]_midout chanx[1][1]_out[28]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[29] density = 0.1906, probability=0.4782.***** -Vchanx[1][1]_in[29] chanx[1][1]_in[29] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgrid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][1] 0 -+ 0 -Vgrid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][3] 0 -+ 0 -Vgrid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][5] 0 -+ 0 -Vgrid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][7] 0 -+ 0 -Vgrid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][9] 0 -+ 0 -Vgrid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][11] 0 -+ 0 -Vgrid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][13] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgrid[1][2]_pin[0][2][15] grid[1][2]_pin[0][2][15] 0 -+ 0 -Vgrid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') - -***** Signal chany[0][1]_in[0] density = 0, probability=0.***** -Vchany[0][1]_in[0] chany[0][1]_in[0] 0 -+ 0 -**** Load for rr_node[198] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=1, type=5 ***** -Xchan_chany[0][1]_out[1]_loadlvl[0]_out chany[0][1]_out[1] chany[0][1]_out[1]_loadlvl[0]_out chany[0][1]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[33]_no0 chany[0][1]_out[1]_loadlvl[0]_out chany[0][1]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 chany[0][1]_out[1]_loadlvl[0]_midout chany[0][1]_out[1]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[2] density = 0, probability=0.***** -Vchany[0][1]_in[2] chany[0][1]_in[2] 0 -+ 0 -**** Load for rr_node[200] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=3, type=5 ***** -Xchan_chany[0][1]_out[3]_loadlvl[0]_out chany[0][1]_out[3] chany[0][1]_out[3]_loadlvl[0]_out chany[0][1]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[35]_no0 chany[0][1]_out[3]_loadlvl[0]_out chany[0][1]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 chany[0][1]_out[3]_loadlvl[0]_midout chany[0][1]_out[3]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[4] density = 0, probability=0.***** -Vchany[0][1]_in[4] chany[0][1]_in[4] 0 -+ 0 -**** Load for rr_node[202] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=5, type=5 ***** -Xchan_chany[0][1]_out[5]_loadlvl[0]_out chany[0][1]_out[5] chany[0][1]_out[5]_loadlvl[0]_out chany[0][1]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[37]_no0 chany[0][1]_out[5]_loadlvl[0]_out chany[0][1]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 chany[0][1]_out[5]_loadlvl[0]_midout chany[0][1]_out[5]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[6] density = 0, probability=0.***** -Vchany[0][1]_in[6] chany[0][1]_in[6] 0 -+ 0 -**** Load for rr_node[204] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=7, type=5 ***** -Xchan_chany[0][1]_out[7]_loadlvl[0]_out chany[0][1]_out[7] chany[0][1]_out[7]_loadlvl[0]_out chany[0][1]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[39]_no0 chany[0][1]_out[7]_loadlvl[0]_out chany[0][1]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 chany[0][1]_out[7]_loadlvl[0]_midout chany[0][1]_out[7]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 chany[0][1]_out[7]_loadlvl[0]_midout chany[0][1]_out[7]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[8] density = 0, probability=0.***** -Vchany[0][1]_in[8] chany[0][1]_in[8] 0 -+ 0 -**** Load for rr_node[206] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=9, type=5 ***** -Xchan_chany[0][1]_out[9]_loadlvl[0]_out chany[0][1]_out[9] chany[0][1]_out[9]_loadlvl[0]_out chany[0][1]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[42]_no0 chany[0][1]_out[9]_loadlvl[0]_out chany[0][1]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 chany[0][1]_out[9]_loadlvl[0]_midout chany[0][1]_out[9]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[10] density = 0, probability=0.***** -Vchany[0][1]_in[10] chany[0][1]_in[10] 0 -+ 0 -**** Load for rr_node[208] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=11, type=5 ***** -Xchan_chany[0][1]_out[11]_loadlvl[0]_out chany[0][1]_out[11] chany[0][1]_out[11]_loadlvl[0]_out chany[0][1]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[44]_no0 chany[0][1]_out[11]_loadlvl[0]_out chany[0][1]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 chany[0][1]_out[11]_loadlvl[0]_midout chany[0][1]_out[11]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 chany[0][1]_out[11]_loadlvl[0]_midout chany[0][1]_out[11]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[12] density = 0, probability=0.***** -Vchany[0][1]_in[12] chany[0][1]_in[12] 0 -+ 0 -**** Load for rr_node[210] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=13, type=5 ***** -Xchan_chany[0][1]_out[13]_loadlvl[0]_out chany[0][1]_out[13] chany[0][1]_out[13]_loadlvl[0]_out chany[0][1]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[47]_no0 chany[0][1]_out[13]_loadlvl[0]_out chany[0][1]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 chany[0][1]_out[13]_loadlvl[0]_midout chany[0][1]_out[13]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[14] density = 0, probability=0.***** -Vchany[0][1]_in[14] chany[0][1]_in[14] 0 -+ 0 -**** Load for rr_node[212] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=15, type=5 ***** -Xchan_chany[0][1]_out[15]_loadlvl[0]_out chany[0][1]_out[15] chany[0][1]_out[15]_loadlvl[0]_out chany[0][1]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[49]_no0 chany[0][1]_out[15]_loadlvl[0]_out chany[0][1]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 chany[0][1]_out[15]_loadlvl[0]_midout chany[0][1]_out[15]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[16] density = 0, probability=0.***** -Vchany[0][1]_in[16] chany[0][1]_in[16] 0 -+ 0 -**** Load for rr_node[214] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=17, type=5 ***** -Xchan_chany[0][1]_out[17]_loadlvl[0]_out chany[0][1]_out[17] chany[0][1]_out[17]_loadlvl[0]_out chany[0][1]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[51]_no0 chany[0][1]_out[17]_loadlvl[0]_out chany[0][1]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 chany[0][1]_out[17]_loadlvl[0]_midout chany[0][1]_out[17]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[18] density = 0, probability=0.***** -Vchany[0][1]_in[18] chany[0][1]_in[18] 0 -+ 0 -**** Load for rr_node[216] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=19, type=5 ***** -Xchan_chany[0][1]_out[19]_loadlvl[0]_out chany[0][1]_out[19] chany[0][1]_out[19]_loadlvl[0]_out chany[0][1]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[53]_no0 chany[0][1]_out[19]_loadlvl[0]_out chany[0][1]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 chany[0][1]_out[19]_loadlvl[0]_midout chany[0][1]_out[19]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[20] density = 0, probability=0.***** -Vchany[0][1]_in[20] chany[0][1]_in[20] 0 -+ 0 -**** Load for rr_node[218] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=21, type=5 ***** -Xchan_chany[0][1]_out[21]_loadlvl[0]_out chany[0][1]_out[21] chany[0][1]_out[21]_loadlvl[0]_out chany[0][1]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[55]_no0 chany[0][1]_out[21]_loadlvl[0]_out chany[0][1]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 chany[0][1]_out[21]_loadlvl[0]_midout chany[0][1]_out[21]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[22] density = 0, probability=0.***** -Vchany[0][1]_in[22] chany[0][1]_in[22] 0 -+ 0 -**** Load for rr_node[220] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=23, type=5 ***** -Xchan_chany[0][1]_out[23]_loadlvl[0]_out chany[0][1]_out[23] chany[0][1]_out[23]_loadlvl[0]_out chany[0][1]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[57]_no0 chany[0][1]_out[23]_loadlvl[0]_out chany[0][1]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 chany[0][1]_out[23]_loadlvl[0]_midout chany[0][1]_out[23]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[24] density = 0, probability=0.***** -Vchany[0][1]_in[24] chany[0][1]_in[24] 0 -+ 0 -**** Load for rr_node[222] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=25, type=5 ***** -Xchan_chany[0][1]_out[25]_loadlvl[0]_out chany[0][1]_out[25] chany[0][1]_out[25]_loadlvl[0]_out chany[0][1]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[59]_no0 chany[0][1]_out[25]_loadlvl[0]_out chany[0][1]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[60]_no0 chany[0][1]_out[25]_loadlvl[0]_midout chany[0][1]_out[25]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[26] density = 0, probability=0.***** -Vchany[0][1]_in[26] chany[0][1]_in[26] 0 -+ 0 -**** Load for rr_node[224] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=27, type=5 ***** -Xchan_chany[0][1]_out[27]_loadlvl[0]_out chany[0][1]_out[27] chany[0][1]_out[27]_loadlvl[0]_out chany[0][1]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[61]_no0 chany[0][1]_out[27]_loadlvl[0]_out chany[0][1]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 chany[0][1]_out[27]_loadlvl[0]_midout chany[0][1]_out[27]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 chany[0][1]_out[27]_loadlvl[0]_midout chany[0][1]_out[27]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[28] density = 0, probability=0.***** -Vchany[0][1]_in[28] chany[0][1]_in[28] 0 -+ 0 -**** Load for rr_node[226] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=29, type=5 ***** -Xchan_chany[0][1]_out[29]_loadlvl[0]_out chany[0][1]_out[29] chany[0][1]_out[29]_loadlvl[0]_out chany[0][1]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[64]_no0 chany[0][1]_out[29]_loadlvl[0]_out chany[0][1]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 chany[0][1]_out[29]_loadlvl[0]_midout chany[0][1]_out[29]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Vgrid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][1] 0 -+ 0 -Vgrid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][3] 0 -+ 0 -Vgrid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][5] 0 -+ 0 -Vgrid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][7] 0 -+ 0 -Vgrid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][9] 0 -+ 0 -Vgrid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][11] 0 -+ 0 -Vgrid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][13] 0 -+ 0 -Vgrid[0][1]_pin[0][1][15] grid[0][1]_pin[0][1][15] 0 -+ 0 - - -***** Voltage supplies ***** -Vgvdd_sb[0][1] gvdd_sb[0][1] 0 vsp -Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_sb avg p(Vgvdd_sb[0][1]) from=0 to='clock_period' -.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_sb avg p(Vgvdd_sb[0][1]) from='clock_period' to='7*clock_period' -.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period' -.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='7*clock_period' -.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_1/sb_tb/example_1_sb1_0_sb_testbench.sp b/examples/spice_test_example_1/sb_tb/example_1_sb1_0_sb_testbench.sp deleted file mode 100644 index 7b5fcf95b..000000000 --- a/examples/spice_test_example_1/sb_tb/example_1_sb1_0_sb_testbench.sp +++ /dev/null @@ -1,381 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_sbs -****** Include subckt netlists: Switch Block[1][0] ***** -.include './spice_test_example_1/subckt/sb_1_0.sp' -***** Call defined Switch Box[1][0] ***** -Xsb[1][0] -+ chany[1][1]_out[0] chany[1][1]_in[1] chany[1][1]_out[2] chany[1][1]_in[3] chany[1][1]_out[4] chany[1][1]_in[5] chany[1][1]_out[6] chany[1][1]_in[7] chany[1][1]_out[8] chany[1][1]_in[9] chany[1][1]_out[10] chany[1][1]_in[11] chany[1][1]_out[12] chany[1][1]_in[13] chany[1][1]_out[14] chany[1][1]_in[15] chany[1][1]_out[16] chany[1][1]_in[17] chany[1][1]_out[18] chany[1][1]_in[19] chany[1][1]_out[20] chany[1][1]_in[21] chany[1][1]_out[22] chany[1][1]_in[23] chany[1][1]_out[24] chany[1][1]_in[25] chany[1][1]_out[26] chany[1][1]_in[27] chany[1][1]_out[28] chany[1][1]_in[29] -+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] -+ -+ -+ -+ -+ chanx[1][0]_in[0] chanx[1][0]_out[1] chanx[1][0]_in[2] chanx[1][0]_out[3] chanx[1][0]_in[4] chanx[1][0]_out[5] chanx[1][0]_in[6] chanx[1][0]_out[7] chanx[1][0]_in[8] chanx[1][0]_out[9] chanx[1][0]_in[10] chanx[1][0]_out[11] chanx[1][0]_in[12] chanx[1][0]_out[13] chanx[1][0]_in[14] chanx[1][0]_out[15] chanx[1][0]_in[16] chanx[1][0]_out[17] chanx[1][0]_in[18] chanx[1][0]_out[19] chanx[1][0]_in[20] chanx[1][0]_out[21] chanx[1][0]_in[22] chanx[1][0]_out[23] chanx[1][0]_in[24] chanx[1][0]_out[25] chanx[1][0]_in[26] chanx[1][0]_out[27] chanx[1][0]_in[28] chanx[1][0]_out[29] -+ grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ gvdd_sb[1][0] 0 sb[1][0] -**** Load for rr_node[227] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=0, type=5 ***** -Xchan_chany[1][1]_out[0]_loadlvl[0]_out chany[1][1]_out[0] chany[1][1]_out[0]_loadlvl[0]_out chany[1][1]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 chany[1][1]_out[0]_loadlvl[0]_out chany[1][1]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 chany[1][1]_out[0]_loadlvl[0]_midout chany[1][1]_out[0]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[1] density = 0, probability=0.***** -Vchany[1][1]_in[1] chany[1][1]_in[1] 0 -+ 0 -**** Load for rr_node[229] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=2, type=5 ***** -Xchan_chany[1][1]_out[2]_loadlvl[0]_out chany[1][1]_out[2] chany[1][1]_out[2]_loadlvl[0]_out chany[1][1]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 chany[1][1]_out[2]_loadlvl[0]_out chany[1][1]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[3] density = 0, probability=0.***** -Vchany[1][1]_in[3] chany[1][1]_in[3] 0 -+ 0 -**** Load for rr_node[231] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=4, type=5 ***** -Xchan_chany[1][1]_out[4]_loadlvl[0]_out chany[1][1]_out[4] chany[1][1]_out[4]_loadlvl[0]_out chany[1][1]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[3]_no0 chany[1][1]_out[4]_loadlvl[0]_out chany[1][1]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[5] density = 0, probability=0.***** -Vchany[1][1]_in[5] chany[1][1]_in[5] 0 -+ 0 -**** Load for rr_node[233] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=6, type=5 ***** -Xchan_chany[1][1]_out[6]_loadlvl[0]_out chany[1][1]_out[6] chany[1][1]_out[6]_loadlvl[0]_out chany[1][1]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[4]_no0 chany[1][1]_out[6]_loadlvl[0]_out chany[1][1]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[7] density = 0, probability=0.***** -Vchany[1][1]_in[7] chany[1][1]_in[7] 0 -+ 0 -**** Load for rr_node[235] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=8, type=5 ***** -Xchan_chany[1][1]_out[8]_loadlvl[0]_out chany[1][1]_out[8] chany[1][1]_out[8]_loadlvl[0]_out chany[1][1]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[5]_no0 chany[1][1]_out[8]_loadlvl[0]_out chany[1][1]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[9] density = 0, probability=0.***** -Vchany[1][1]_in[9] chany[1][1]_in[9] 0 -+ 0 -**** Load for rr_node[237] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=10, type=5 ***** -Xchan_chany[1][1]_out[10]_loadlvl[0]_out chany[1][1]_out[10] chany[1][1]_out[10]_loadlvl[0]_out chany[1][1]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[6]_no0 chany[1][1]_out[10]_loadlvl[0]_out chany[1][1]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[11] density = 0, probability=0.***** -Vchany[1][1]_in[11] chany[1][1]_in[11] 0 -+ 0 -**** Load for rr_node[239] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=12, type=5 ***** -Xchan_chany[1][1]_out[12]_loadlvl[0]_out chany[1][1]_out[12] chany[1][1]_out[12]_loadlvl[0]_out chany[1][1]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[7]_no0 chany[1][1]_out[12]_loadlvl[0]_out chany[1][1]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[13] density = 0, probability=0.***** -Vchany[1][1]_in[13] chany[1][1]_in[13] 0 -+ 0 -**** Load for rr_node[241] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=14, type=5 ***** -Xchan_chany[1][1]_out[14]_loadlvl[0]_out chany[1][1]_out[14] chany[1][1]_out[14]_loadlvl[0]_out chany[1][1]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[8]_no0 chany[1][1]_out[14]_loadlvl[0]_out chany[1][1]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[15] density = 0, probability=0.***** -Vchany[1][1]_in[15] chany[1][1]_in[15] 0 -+ 0 -**** Load for rr_node[243] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=16, type=5 ***** -Xchan_chany[1][1]_out[16]_loadlvl[0]_out chany[1][1]_out[16] chany[1][1]_out[16]_loadlvl[0]_out chany[1][1]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[9]_no0 chany[1][1]_out[16]_loadlvl[0]_out chany[1][1]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 chany[1][1]_out[16]_loadlvl[0]_midout chany[1][1]_out[16]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[17] density = 0, probability=0.***** -Vchany[1][1]_in[17] chany[1][1]_in[17] 0 -+ 0 -**** Load for rr_node[245] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=18, type=5 ***** -Xchan_chany[1][1]_out[18]_loadlvl[0]_out chany[1][1]_out[18] chany[1][1]_out[18]_loadlvl[0]_out chany[1][1]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[11]_no0 chany[1][1]_out[18]_loadlvl[0]_out chany[1][1]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[19] density = 0, probability=0.***** -Vchany[1][1]_in[19] chany[1][1]_in[19] 0 -+ 0 -**** Load for rr_node[247] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=20, type=5 ***** -Xchan_chany[1][1]_out[20]_loadlvl[0]_out chany[1][1]_out[20] chany[1][1]_out[20]_loadlvl[0]_out chany[1][1]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[12]_no0 chany[1][1]_out[20]_loadlvl[0]_out chany[1][1]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[21] density = 0, probability=0.***** -Vchany[1][1]_in[21] chany[1][1]_in[21] 0 -+ 0 -**** Load for rr_node[249] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=22, type=5 ***** -Xchan_chany[1][1]_out[22]_loadlvl[0]_out chany[1][1]_out[22] chany[1][1]_out[22]_loadlvl[0]_out chany[1][1]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[13]_no0 chany[1][1]_out[22]_loadlvl[0]_out chany[1][1]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[23] density = 0, probability=0.***** -Vchany[1][1]_in[23] chany[1][1]_in[23] 0 -+ 0 -**** Load for rr_node[251] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=24, type=5 ***** -Xchan_chany[1][1]_out[24]_loadlvl[0]_out chany[1][1]_out[24] chany[1][1]_out[24]_loadlvl[0]_out chany[1][1]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[14]_no0 chany[1][1]_out[24]_loadlvl[0]_out chany[1][1]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[25] density = 0, probability=0.***** -Vchany[1][1]_in[25] chany[1][1]_in[25] 0 -+ 0 -**** Load for rr_node[253] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=26, type=5 ***** -Xchan_chany[1][1]_out[26]_loadlvl[0]_out chany[1][1]_out[26] chany[1][1]_out[26]_loadlvl[0]_out chany[1][1]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[15]_no0 chany[1][1]_out[26]_loadlvl[0]_out chany[1][1]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[27] density = 0, probability=0.***** -Vchany[1][1]_in[27] chany[1][1]_in[27] 0 -+ 0 -**** Load for rr_node[255] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=28, type=5 ***** -Xchan_chany[1][1]_out[28]_loadlvl[0]_out chany[1][1]_out[28] chany[1][1]_out[28]_loadlvl[0]_out chany[1][1]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[16]_no0 chany[1][1]_out[28]_loadlvl[0]_out chany[1][1]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[29] density = 0, probability=0.***** -Vchany[1][1]_in[29] chany[1][1]_in[29] 0 -+ 0 -Vgrid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][1] 0 -+ 0 -Vgrid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][3] 0 -+ 0 -Vgrid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][5] 0 -+ 0 -Vgrid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][7] 0 -+ 0 -Vgrid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][9] 0 -+ 0 -Vgrid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][11] 0 -+ 0 -Vgrid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][13] 0 -+ 0 -Vgrid[2][1]_pin[0][3][15] grid[2][1]_pin[0][3][15] 0 -+ 0 - - - -***** Signal chanx[1][0]_in[0] density = 0, probability=0.***** -Vchanx[1][0]_in[0] chanx[1][0]_in[0] 0 -+ 0 -**** Load for rr_node[138] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=1, type=4 ***** -Xchan_chanx[1][0]_out[1]_loadlvl[0]_out chanx[1][0]_out[1] chanx[1][0]_out[1]_loadlvl[0]_out chanx[1][0]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[17]_no0 chanx[1][0]_out[1]_loadlvl[0]_out chanx[1][0]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 chanx[1][0]_out[1]_loadlvl[0]_midout chanx[1][0]_out[1]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 chanx[1][0]_out[1]_loadlvl[0]_midout chanx[1][0]_out[1]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[2] density = 0, probability=0.***** -Vchanx[1][0]_in[2] chanx[1][0]_in[2] 0 -+ 0 -**** Load for rr_node[140] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=3, type=4 ***** -Xchan_chanx[1][0]_out[3]_loadlvl[0]_out chanx[1][0]_out[3] chanx[1][0]_out[3]_loadlvl[0]_out chanx[1][0]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[20]_no0 chanx[1][0]_out[3]_loadlvl[0]_out chanx[1][0]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 chanx[1][0]_out[3]_loadlvl[0]_midout chanx[1][0]_out[3]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[4] density = 0, probability=0.***** -Vchanx[1][0]_in[4] chanx[1][0]_in[4] 0 -+ 0 -**** Load for rr_node[142] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=5, type=4 ***** -Xchan_chanx[1][0]_out[5]_loadlvl[0]_out chanx[1][0]_out[5] chanx[1][0]_out[5]_loadlvl[0]_out chanx[1][0]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[22]_no0 chanx[1][0]_out[5]_loadlvl[0]_out chanx[1][0]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 chanx[1][0]_out[5]_loadlvl[0]_midout chanx[1][0]_out[5]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[6] density = 0, probability=0.***** -Vchanx[1][0]_in[6] chanx[1][0]_in[6] 0 -+ 0 -**** Load for rr_node[144] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=7, type=4 ***** -Xchan_chanx[1][0]_out[7]_loadlvl[0]_out chanx[1][0]_out[7] chanx[1][0]_out[7]_loadlvl[0]_out chanx[1][0]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[24]_no0 chanx[1][0]_out[7]_loadlvl[0]_out chanx[1][0]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 chanx[1][0]_out[7]_loadlvl[0]_midout chanx[1][0]_out[7]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 chanx[1][0]_out[7]_loadlvl[0]_midout chanx[1][0]_out[7]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[8] density = 0, probability=0.***** -Vchanx[1][0]_in[8] chanx[1][0]_in[8] 0 -+ 0 -**** Load for rr_node[146] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=9, type=4 ***** -Xchan_chanx[1][0]_out[9]_loadlvl[0]_out chanx[1][0]_out[9] chanx[1][0]_out[9]_loadlvl[0]_out chanx[1][0]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[27]_no0 chanx[1][0]_out[9]_loadlvl[0]_out chanx[1][0]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 chanx[1][0]_out[9]_loadlvl[0]_midout chanx[1][0]_out[9]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[10] density = 0, probability=0.***** -Vchanx[1][0]_in[10] chanx[1][0]_in[10] 0 -+ 0 -**** Load for rr_node[148] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=11, type=4 ***** -Xchan_chanx[1][0]_out[11]_loadlvl[0]_out chanx[1][0]_out[11] chanx[1][0]_out[11]_loadlvl[0]_out chanx[1][0]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[29]_no0 chanx[1][0]_out[11]_loadlvl[0]_out chanx[1][0]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 chanx[1][0]_out[11]_loadlvl[0]_midout chanx[1][0]_out[11]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[12] density = 0, probability=0.***** -Vchanx[1][0]_in[12] chanx[1][0]_in[12] 0 -+ 0 -**** Load for rr_node[150] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=13, type=4 ***** -Xchan_chanx[1][0]_out[13]_loadlvl[0]_out chanx[1][0]_out[13] chanx[1][0]_out[13]_loadlvl[0]_out chanx[1][0]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[31]_no0 chanx[1][0]_out[13]_loadlvl[0]_out chanx[1][0]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 chanx[1][0]_out[13]_loadlvl[0]_midout chanx[1][0]_out[13]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[14] density = 0, probability=0.***** -Vchanx[1][0]_in[14] chanx[1][0]_in[14] 0 -+ 0 -**** Load for rr_node[152] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=15, type=4 ***** -Xchan_chanx[1][0]_out[15]_loadlvl[0]_out chanx[1][0]_out[15] chanx[1][0]_out[15]_loadlvl[0]_out chanx[1][0]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[33]_no0 chanx[1][0]_out[15]_loadlvl[0]_out chanx[1][0]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 chanx[1][0]_out[15]_loadlvl[0]_midout chanx[1][0]_out[15]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[16] density = 0, probability=0.***** -Vchanx[1][0]_in[16] chanx[1][0]_in[16] 0 -+ 0 -**** Load for rr_node[154] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=17, type=4 ***** -Xchan_chanx[1][0]_out[17]_loadlvl[0]_out chanx[1][0]_out[17] chanx[1][0]_out[17]_loadlvl[0]_out chanx[1][0]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[35]_no0 chanx[1][0]_out[17]_loadlvl[0]_out chanx[1][0]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 chanx[1][0]_out[17]_loadlvl[0]_midout chanx[1][0]_out[17]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[18] density = 0, probability=0.***** -Vchanx[1][0]_in[18] chanx[1][0]_in[18] 0 -+ 0 -**** Load for rr_node[156] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=19, type=4 ***** -Xchan_chanx[1][0]_out[19]_loadlvl[0]_out chanx[1][0]_out[19] chanx[1][0]_out[19]_loadlvl[0]_out chanx[1][0]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[37]_no0 chanx[1][0]_out[19]_loadlvl[0]_out chanx[1][0]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 chanx[1][0]_out[19]_loadlvl[0]_midout chanx[1][0]_out[19]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[20] density = 0, probability=0.***** -Vchanx[1][0]_in[20] chanx[1][0]_in[20] 0 -+ 0 -**** Load for rr_node[158] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=21, type=4 ***** -Xchan_chanx[1][0]_out[21]_loadlvl[0]_out chanx[1][0]_out[21] chanx[1][0]_out[21]_loadlvl[0]_out chanx[1][0]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[39]_no0 chanx[1][0]_out[21]_loadlvl[0]_out chanx[1][0]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 chanx[1][0]_out[21]_loadlvl[0]_midout chanx[1][0]_out[21]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[22] density = 0, probability=0.***** -Vchanx[1][0]_in[22] chanx[1][0]_in[22] 0 -+ 0 -**** Load for rr_node[160] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=23, type=4 ***** -Xchan_chanx[1][0]_out[23]_loadlvl[0]_out chanx[1][0]_out[23] chanx[1][0]_out[23]_loadlvl[0]_out chanx[1][0]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[41]_no0 chanx[1][0]_out[23]_loadlvl[0]_out chanx[1][0]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 chanx[1][0]_out[23]_loadlvl[0]_midout chanx[1][0]_out[23]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 chanx[1][0]_out[23]_loadlvl[0]_midout chanx[1][0]_out[23]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[24] density = 0, probability=0.***** -Vchanx[1][0]_in[24] chanx[1][0]_in[24] 0 -+ 0 -**** Load for rr_node[162] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=25, type=4 ***** -Xchan_chanx[1][0]_out[25]_loadlvl[0]_out chanx[1][0]_out[25] chanx[1][0]_out[25]_loadlvl[0]_out chanx[1][0]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[44]_no0 chanx[1][0]_out[25]_loadlvl[0]_out chanx[1][0]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 chanx[1][0]_out[25]_loadlvl[0]_midout chanx[1][0]_out[25]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[26] density = 0, probability=0.***** -Vchanx[1][0]_in[26] chanx[1][0]_in[26] 0 -+ 0 -**** Load for rr_node[164] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=27, type=4 ***** -Xchan_chanx[1][0]_out[27]_loadlvl[0]_out chanx[1][0]_out[27] chanx[1][0]_out[27]_loadlvl[0]_out chanx[1][0]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[46]_no0 chanx[1][0]_out[27]_loadlvl[0]_out chanx[1][0]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 chanx[1][0]_out[27]_loadlvl[0]_midout chanx[1][0]_out[27]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[28] density = 0, probability=0.***** -Vchanx[1][0]_in[28] chanx[1][0]_in[28] 0 -+ 0 -**** Load for rr_node[166] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=29, type=4 ***** -Xchan_chanx[1][0]_out[29]_loadlvl[0]_out chanx[1][0]_out[29] chanx[1][0]_out[29]_loadlvl[0]_out chanx[1][0]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[48]_no0 chanx[1][0]_out[29]_loadlvl[0]_out chanx[1][0]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 chanx[1][0]_out[29]_loadlvl[0]_midout chanx[1][0]_out[29]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Vgrid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][1] 0 -+ 0 -Vgrid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][3] 0 -+ 0 -Vgrid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][5] 0 -+ 0 -Vgrid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][7] 0 -+ 0 -Vgrid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][9] 0 -+ 0 -Vgrid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][11] 0 -+ 0 -Vgrid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][13] 0 -+ 0 -Vgrid[1][0]_pin[0][0][15] grid[1][0]_pin[0][0][15] 0 -+ 0 - -***** Voltage supplies ***** -Vgvdd_sb[1][0] gvdd_sb[1][0] 0 vsp -Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp -***** 2 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '2*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_sb avg p(Vgvdd_sb[1][0]) from=0 to='clock_period' -.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_sb avg p(Vgvdd_sb[1][0]) from='clock_period' to='2*clock_period' -.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period' -.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='2*clock_period' -.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_1/sb_tb/example_1_sb1_1_sb_testbench.sp b/examples/spice_test_example_1/sb_tb/example_1_sb1_1_sb_testbench.sp deleted file mode 100644 index dd24e09b2..000000000 --- a/examples/spice_test_example_1/sb_tb/example_1_sb1_1_sb_testbench.sp +++ /dev/null @@ -1,393 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_sbs -****** Include subckt netlists: Switch Block[1][1] ***** -.include './spice_test_example_1/subckt/sb_1_1.sp' -***** Call defined Switch Box[1][1] ***** -Xsb[1][1] -+ -+ -+ -+ -+ chany[1][1]_in[0] chany[1][1]_out[1] chany[1][1]_in[2] chany[1][1]_out[3] chany[1][1]_in[4] chany[1][1]_out[5] chany[1][1]_in[6] chany[1][1]_out[7] chany[1][1]_in[8] chany[1][1]_out[9] chany[1][1]_in[10] chany[1][1]_out[11] chany[1][1]_in[12] chany[1][1]_out[13] chany[1][1]_in[14] chany[1][1]_out[15] chany[1][1]_in[16] chany[1][1]_out[17] chany[1][1]_in[18] chany[1][1]_out[19] chany[1][1]_in[20] chany[1][1]_out[21] chany[1][1]_in[22] chany[1][1]_out[23] chany[1][1]_in[24] chany[1][1]_out[25] chany[1][1]_in[26] chany[1][1]_out[27] chany[1][1]_in[28] chany[1][1]_out[29] -+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] -+ chanx[1][1]_in[0] chanx[1][1]_out[1] chanx[1][1]_in[2] chanx[1][1]_out[3] chanx[1][1]_in[4] chanx[1][1]_out[5] chanx[1][1]_in[6] chanx[1][1]_out[7] chanx[1][1]_in[8] chanx[1][1]_out[9] chanx[1][1]_in[10] chanx[1][1]_out[11] chanx[1][1]_in[12] chanx[1][1]_out[13] chanx[1][1]_in[14] chanx[1][1]_out[15] chanx[1][1]_in[16] chanx[1][1]_out[17] chanx[1][1]_in[18] chanx[1][1]_out[19] chanx[1][1]_in[20] chanx[1][1]_out[21] chanx[1][1]_in[22] chanx[1][1]_out[23] chanx[1][1]_in[24] chanx[1][1]_out[25] chanx[1][1]_in[26] chanx[1][1]_out[27] chanx[1][1]_in[28] chanx[1][1]_out[29] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][4] -+ gvdd_sb[1][1] 0 sb[1][1] - - -***** Signal chany[1][1]_in[0] density = 0, probability=0.***** -Vchany[1][1]_in[0] chany[1][1]_in[0] 0 -+ 0 -**** Load for rr_node[228] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=1, type=5 ***** -Xchan_chany[1][1]_out[1]_loadlvl[0]_out chany[1][1]_out[1] chany[1][1]_out[1]_loadlvl[0]_out chany[1][1]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 chany[1][1]_out[1]_loadlvl[0]_out chany[1][1]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 chany[1][1]_out[1]_loadlvl[0]_midout chany[1][1]_out[1]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[2] density = 0, probability=0.***** -Vchany[1][1]_in[2] chany[1][1]_in[2] 0 -+ 0 -**** Load for rr_node[230] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=3, type=5 ***** -Xchan_chany[1][1]_out[3]_loadlvl[0]_out chany[1][1]_out[3] chany[1][1]_out[3]_loadlvl[0]_out chany[1][1]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 chany[1][1]_out[3]_loadlvl[0]_out chany[1][1]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[4] density = 0, probability=0.***** -Vchany[1][1]_in[4] chany[1][1]_in[4] 0 -+ 0 -**** Load for rr_node[232] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=5, type=5 ***** -Xchan_chany[1][1]_out[5]_loadlvl[0]_out chany[1][1]_out[5] chany[1][1]_out[5]_loadlvl[0]_out chany[1][1]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[3]_no0 chany[1][1]_out[5]_loadlvl[0]_out chany[1][1]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[6] density = 0, probability=0.***** -Vchany[1][1]_in[6] chany[1][1]_in[6] 0 -+ 0 -**** Load for rr_node[234] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=7, type=5 ***** -Xchan_chany[1][1]_out[7]_loadlvl[0]_out chany[1][1]_out[7] chany[1][1]_out[7]_loadlvl[0]_out chany[1][1]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[4]_no0 chany[1][1]_out[7]_loadlvl[0]_out chany[1][1]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[8] density = 0, probability=0.***** -Vchany[1][1]_in[8] chany[1][1]_in[8] 0 -+ 0 -**** Load for rr_node[236] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=9, type=5 ***** -Xchan_chany[1][1]_out[9]_loadlvl[0]_out chany[1][1]_out[9] chany[1][1]_out[9]_loadlvl[0]_out chany[1][1]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[5]_no0 chany[1][1]_out[9]_loadlvl[0]_out chany[1][1]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[10] density = 0, probability=0.***** -Vchany[1][1]_in[10] chany[1][1]_in[10] 0 -+ 0 -**** Load for rr_node[238] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=11, type=5 ***** -Xchan_chany[1][1]_out[11]_loadlvl[0]_out chany[1][1]_out[11] chany[1][1]_out[11]_loadlvl[0]_out chany[1][1]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[6]_no0 chany[1][1]_out[11]_loadlvl[0]_out chany[1][1]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[12] density = 0, probability=0.***** -Vchany[1][1]_in[12] chany[1][1]_in[12] 0 -+ 0 -**** Load for rr_node[240] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=13, type=5 ***** -Xchan_chany[1][1]_out[13]_loadlvl[0]_out chany[1][1]_out[13] chany[1][1]_out[13]_loadlvl[0]_out chany[1][1]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[7]_no0 chany[1][1]_out[13]_loadlvl[0]_out chany[1][1]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[14] density = 0, probability=0.***** -Vchany[1][1]_in[14] chany[1][1]_in[14] 0 -+ 0 -**** Load for rr_node[242] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=15, type=5 ***** -Xchan_chany[1][1]_out[15]_loadlvl[0]_out chany[1][1]_out[15] chany[1][1]_out[15]_loadlvl[0]_out chany[1][1]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[8]_no0 chany[1][1]_out[15]_loadlvl[0]_out chany[1][1]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[16] density = 0, probability=0.***** -Vchany[1][1]_in[16] chany[1][1]_in[16] 0 -+ 0 -**** Load for rr_node[244] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=17, type=5 ***** -Xchan_chany[1][1]_out[17]_loadlvl[0]_out chany[1][1]_out[17] chany[1][1]_out[17]_loadlvl[0]_out chany[1][1]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[9]_no0 chany[1][1]_out[17]_loadlvl[0]_out chany[1][1]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 chany[1][1]_out[17]_loadlvl[0]_midout chany[1][1]_out[17]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[18] density = 0, probability=0.***** -Vchany[1][1]_in[18] chany[1][1]_in[18] 0 -+ 0 -**** Load for rr_node[246] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=19, type=5 ***** -Xchan_chany[1][1]_out[19]_loadlvl[0]_out chany[1][1]_out[19] chany[1][1]_out[19]_loadlvl[0]_out chany[1][1]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[11]_no0 chany[1][1]_out[19]_loadlvl[0]_out chany[1][1]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[20] density = 0, probability=0.***** -Vchany[1][1]_in[20] chany[1][1]_in[20] 0 -+ 0 -**** Load for rr_node[248] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=21, type=5 ***** -Xchan_chany[1][1]_out[21]_loadlvl[0]_out chany[1][1]_out[21] chany[1][1]_out[21]_loadlvl[0]_out chany[1][1]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[12]_no0 chany[1][1]_out[21]_loadlvl[0]_out chany[1][1]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[22] density = 0, probability=0.***** -Vchany[1][1]_in[22] chany[1][1]_in[22] 0 -+ 0 -**** Load for rr_node[250] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=23, type=5 ***** -Xchan_chany[1][1]_out[23]_loadlvl[0]_out chany[1][1]_out[23] chany[1][1]_out[23]_loadlvl[0]_out chany[1][1]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[13]_no0 chany[1][1]_out[23]_loadlvl[0]_out chany[1][1]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[24] density = 0, probability=0.***** -Vchany[1][1]_in[24] chany[1][1]_in[24] 0 -+ 0 -**** Load for rr_node[252] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=25, type=5 ***** -Xchan_chany[1][1]_out[25]_loadlvl[0]_out chany[1][1]_out[25] chany[1][1]_out[25]_loadlvl[0]_out chany[1][1]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[14]_no0 chany[1][1]_out[25]_loadlvl[0]_out chany[1][1]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[26] density = 0, probability=0.***** -Vchany[1][1]_in[26] chany[1][1]_in[26] 0 -+ 0 -**** Load for rr_node[254] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=27, type=5 ***** -Xchan_chany[1][1]_out[27]_loadlvl[0]_out chany[1][1]_out[27] chany[1][1]_out[27]_loadlvl[0]_out chany[1][1]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[15]_no0 chany[1][1]_out[27]_loadlvl[0]_out chany[1][1]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[28] density = 0, probability=0.***** -Vchany[1][1]_in[28] chany[1][1]_in[28] 0 -+ 0 -**** Load for rr_node[256] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=29, type=5 ***** -Xchan_chany[1][1]_out[29]_loadlvl[0]_out chany[1][1]_out[29] chany[1][1]_out[29]_loadlvl[0]_out chany[1][1]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[16]_no0 chany[1][1]_out[29]_loadlvl[0]_out chany[1][1]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Vgrid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][1] 0 -+ 0 -Vgrid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][3] 0 -+ 0 -Vgrid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][5] 0 -+ 0 -Vgrid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][7] 0 -+ 0 -Vgrid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][9] 0 -+ 0 -Vgrid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][11] 0 -+ 0 -Vgrid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][13] 0 -+ 0 -Vgrid[2][1]_pin[0][3][15] grid[2][1]_pin[0][3][15] 0 -+ 0 - -***** Signal chanx[1][1]_in[0] density = 0.1906, probability=0.5218.***** -Vchanx[1][1]_in[0] chanx[1][1]_in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -**** Load for rr_node[168] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=1, type=4 ***** -Xchan_chanx[1][1]_out[1]_loadlvl[0]_out chanx[1][1]_out[1] chanx[1][1]_out[1]_loadlvl[0]_out chanx[1][1]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[17]_no0 chanx[1][1]_out[1]_loadlvl[0]_out chanx[1][1]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 chanx[1][1]_out[1]_loadlvl[0]_midout chanx[1][1]_out[1]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[2] density = 0.1906, probability=0.5218.***** -Vchanx[1][1]_in[2] chanx[1][1]_in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -**** Load for rr_node[170] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=3, type=4 ***** -Xchan_chanx[1][1]_out[3]_loadlvl[0]_out chanx[1][1]_out[3] chanx[1][1]_out[3]_loadlvl[0]_out chanx[1][1]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[19]_no0 chanx[1][1]_out[3]_loadlvl[0]_out chanx[1][1]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 chanx[1][1]_out[3]_loadlvl[0]_midout chanx[1][1]_out[3]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[4] density = 0, probability=0.***** -Vchanx[1][1]_in[4] chanx[1][1]_in[4] 0 -+ 0 -**** Load for rr_node[172] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=5, type=4 ***** -Xchan_chanx[1][1]_out[5]_loadlvl[0]_out chanx[1][1]_out[5] chanx[1][1]_out[5]_loadlvl[0]_out chanx[1][1]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[21]_no0 chanx[1][1]_out[5]_loadlvl[0]_out chanx[1][1]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 chanx[1][1]_out[5]_loadlvl[0]_midout chanx[1][1]_out[5]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[6] density = 0, probability=0.***** -Vchanx[1][1]_in[6] chanx[1][1]_in[6] 0 -+ 0 -**** Load for rr_node[174] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=7, type=4 ***** -Xchan_chanx[1][1]_out[7]_loadlvl[0]_out chanx[1][1]_out[7] chanx[1][1]_out[7]_loadlvl[0]_out chanx[1][1]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[23]_no0 chanx[1][1]_out[7]_loadlvl[0]_out chanx[1][1]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 chanx[1][1]_out[7]_loadlvl[0]_midout chanx[1][1]_out[7]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 chanx[1][1]_out[7]_loadlvl[0]_midout chanx[1][1]_out[7]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[8] density = 0, probability=0.***** -Vchanx[1][1]_in[8] chanx[1][1]_in[8] 0 -+ 0 -**** Load for rr_node[176] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=9, type=4 ***** -Xchan_chanx[1][1]_out[9]_loadlvl[0]_out chanx[1][1]_out[9] chanx[1][1]_out[9]_loadlvl[0]_out chanx[1][1]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[26]_no0 chanx[1][1]_out[9]_loadlvl[0]_out chanx[1][1]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 chanx[1][1]_out[9]_loadlvl[0]_midout chanx[1][1]_out[9]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[10] density = 0, probability=0.***** -Vchanx[1][1]_in[10] chanx[1][1]_in[10] 0 -+ 0 -**** Load for rr_node[178] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=11, type=4 ***** -Xchan_chanx[1][1]_out[11]_loadlvl[0]_out chanx[1][1]_out[11] chanx[1][1]_out[11]_loadlvl[0]_out chanx[1][1]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[28]_no0 chanx[1][1]_out[11]_loadlvl[0]_out chanx[1][1]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 chanx[1][1]_out[11]_loadlvl[0]_midout chanx[1][1]_out[11]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[12] density = 0, probability=0.***** -Vchanx[1][1]_in[12] chanx[1][1]_in[12] 0 -+ 0 -**** Load for rr_node[180] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=13, type=4 ***** -Xchan_chanx[1][1]_out[13]_loadlvl[0]_out chanx[1][1]_out[13] chanx[1][1]_out[13]_loadlvl[0]_out chanx[1][1]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[30]_no0 chanx[1][1]_out[13]_loadlvl[0]_out chanx[1][1]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[31]_no0 chanx[1][1]_out[13]_loadlvl[0]_midout chanx[1][1]_out[13]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 chanx[1][1]_out[13]_loadlvl[0]_midout chanx[1][1]_out[13]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 chanx[1][1]_out[13]_loadlvl[0]_midout chanx[1][1]_out[13]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[14] density = 0, probability=0.***** -Vchanx[1][1]_in[14] chanx[1][1]_in[14] 0 -+ 0 -**** Load for rr_node[182] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=15, type=4 ***** -Xchan_chanx[1][1]_out[15]_loadlvl[0]_out chanx[1][1]_out[15] chanx[1][1]_out[15]_loadlvl[0]_out chanx[1][1]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[34]_no0 chanx[1][1]_out[15]_loadlvl[0]_out chanx[1][1]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 chanx[1][1]_out[15]_loadlvl[0]_midout chanx[1][1]_out[15]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[16] density = 0, probability=0.***** -Vchanx[1][1]_in[16] chanx[1][1]_in[16] 0 -+ 0 -**** Load for rr_node[184] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=17, type=4 ***** -Xchan_chanx[1][1]_out[17]_loadlvl[0]_out chanx[1][1]_out[17] chanx[1][1]_out[17]_loadlvl[0]_out chanx[1][1]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[36]_no0 chanx[1][1]_out[17]_loadlvl[0]_out chanx[1][1]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 chanx[1][1]_out[17]_loadlvl[0]_midout chanx[1][1]_out[17]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[18] density = 0, probability=0.***** -Vchanx[1][1]_in[18] chanx[1][1]_in[18] 0 -+ 0 -**** Load for rr_node[186] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=19, type=4 ***** -Xchan_chanx[1][1]_out[19]_loadlvl[0]_out chanx[1][1]_out[19] chanx[1][1]_out[19]_loadlvl[0]_out chanx[1][1]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[38]_no0 chanx[1][1]_out[19]_loadlvl[0]_out chanx[1][1]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 chanx[1][1]_out[19]_loadlvl[0]_midout chanx[1][1]_out[19]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[20] density = 0, probability=0.***** -Vchanx[1][1]_in[20] chanx[1][1]_in[20] 0 -+ 0 -**** Load for rr_node[188] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=21, type=4 ***** -Xchan_chanx[1][1]_out[21]_loadlvl[0]_out chanx[1][1]_out[21] chanx[1][1]_out[21]_loadlvl[0]_out chanx[1][1]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[40]_no0 chanx[1][1]_out[21]_loadlvl[0]_out chanx[1][1]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 chanx[1][1]_out[21]_loadlvl[0]_midout chanx[1][1]_out[21]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[22] density = 0, probability=0.***** -Vchanx[1][1]_in[22] chanx[1][1]_in[22] 0 -+ 0 -**** Load for rr_node[190] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=23, type=4 ***** -Xchan_chanx[1][1]_out[23]_loadlvl[0]_out chanx[1][1]_out[23] chanx[1][1]_out[23]_loadlvl[0]_out chanx[1][1]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[42]_no0 chanx[1][1]_out[23]_loadlvl[0]_out chanx[1][1]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 chanx[1][1]_out[23]_loadlvl[0]_midout chanx[1][1]_out[23]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[24] density = 0, probability=0.***** -Vchanx[1][1]_in[24] chanx[1][1]_in[24] 0 -+ 0 -**** Load for rr_node[192] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=25, type=4 ***** -Xchan_chanx[1][1]_out[25]_loadlvl[0]_out chanx[1][1]_out[25] chanx[1][1]_out[25]_loadlvl[0]_out chanx[1][1]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[44]_no0 chanx[1][1]_out[25]_loadlvl[0]_out chanx[1][1]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 chanx[1][1]_out[25]_loadlvl[0]_midout chanx[1][1]_out[25]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[26] density = 0, probability=0.***** -Vchanx[1][1]_in[26] chanx[1][1]_in[26] 0 -+ 0 -**** Load for rr_node[194] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=27, type=4 ***** -Xchan_chanx[1][1]_out[27]_loadlvl[0]_out chanx[1][1]_out[27] chanx[1][1]_out[27]_loadlvl[0]_out chanx[1][1]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[46]_no0 chanx[1][1]_out[27]_loadlvl[0]_out chanx[1][1]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 chanx[1][1]_out[27]_loadlvl[0]_midout chanx[1][1]_out[27]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[28] density = 0.1906, probability=0.4782.***** -Vchanx[1][1]_in[28] chanx[1][1]_in[28] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -**** Load for rr_node[196] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=29, type=4 ***** -Xchan_chanx[1][1]_out[29]_loadlvl[0]_out chanx[1][1]_out[29] chanx[1][1]_out[29]_loadlvl[0]_out chanx[1][1]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[48]_no0 chanx[1][1]_out[29]_loadlvl[0]_out chanx[1][1]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 chanx[1][1]_out[29]_loadlvl[0]_midout chanx[1][1]_out[29]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Vgrid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][1] 0 -+ 0 -Vgrid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][3] 0 -+ 0 -Vgrid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][5] 0 -+ 0 -Vgrid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][7] 0 -+ 0 -Vgrid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][9] 0 -+ 0 -Vgrid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][11] 0 -+ 0 -Vgrid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][13] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgrid[1][2]_pin[0][2][15] grid[1][2]_pin[0][2][15] 0 -+ 0 -Vgrid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5218*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') - -***** Voltage supplies ***** -Vgvdd_sb[1][1] gvdd_sb[1][1] 0 vsp -Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_sb avg p(Vgvdd_sb[1][1]) from=0 to='clock_period' -.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_sb avg p(Vgvdd_sb[1][1]) from='clock_period' to='7*clock_period' -.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period' -.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='7*clock_period' -.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_1/subckt/cbx_1_0.sp b/examples/spice_test_example_1/subckt/cbx_1_0.sp deleted file mode 100644 index 2902a59a1..000000000 --- a/examples/spice_test_example_1/subckt/cbx_1_0.sp +++ /dev/null @@ -1,185 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Connection Block X-channel [1][0] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -.subckt cbx[1][0] -+ chanx[1][0]_midout[0] -+ chanx[1][0]_midout[1] -+ chanx[1][0]_midout[2] -+ chanx[1][0]_midout[3] -+ chanx[1][0]_midout[4] -+ chanx[1][0]_midout[5] -+ chanx[1][0]_midout[6] -+ chanx[1][0]_midout[7] -+ chanx[1][0]_midout[8] -+ chanx[1][0]_midout[9] -+ chanx[1][0]_midout[10] -+ chanx[1][0]_midout[11] -+ chanx[1][0]_midout[12] -+ chanx[1][0]_midout[13] -+ chanx[1][0]_midout[14] -+ chanx[1][0]_midout[15] -+ chanx[1][0]_midout[16] -+ chanx[1][0]_midout[17] -+ chanx[1][0]_midout[18] -+ chanx[1][0]_midout[19] -+ chanx[1][0]_midout[20] -+ chanx[1][0]_midout[21] -+ chanx[1][0]_midout[22] -+ chanx[1][0]_midout[23] -+ chanx[1][0]_midout[24] -+ chanx[1][0]_midout[25] -+ chanx[1][0]_midout[26] -+ chanx[1][0]_midout[27] -+ chanx[1][0]_midout[28] -+ chanx[1][0]_midout[29] -+ grid[1][1]_pin[0][2][2] -+ grid[1][0]_pin[0][0][0] -+ grid[1][0]_pin[0][0][2] -+ grid[1][0]_pin[0][0][4] -+ grid[1][0]_pin[0][0][6] -+ grid[1][0]_pin[0][0][8] -+ grid[1][0]_pin[0][0][10] -+ grid[1][0]_pin[0][0][12] -+ grid[1][0]_pin[0][0][14] -+ svdd sgnd -Xmux_2level_tapbuf_size4[0] chanx[1][0]_midout[6] chanx[1][0]_midout[7] chanx[1][0]_midout[22] chanx[1][0]_midout[23] grid[1][1]_pin[0][2][2] sram[217]->outb sram[217]->out sram[218]->out sram[218]->outb sram[219]->outb sram[219]->out sram[220]->out sram[220]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****1010***** -Xsram[217] sram->in sram[217]->out sram[217]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[217]->out) 0 -.nodeset V(sram[217]->outb) vsp -Xsram[218] sram->in sram[218]->out sram[218]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[218]->out) 0 -.nodeset V(sram[218]->outb) vsp -Xsram[219] sram->in sram[219]->out sram[219]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[219]->out) 0 -.nodeset V(sram[219]->outb) vsp -Xsram[220] sram->in sram[220]->out sram[220]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[220]->out) 0 -.nodeset V(sram[220]->outb) vsp -Xmux_2level_tapbuf_size4[1] chanx[1][0]_midout[0] chanx[1][0]_midout[1] chanx[1][0]_midout[14] chanx[1][0]_midout[15] grid[1][0]_pin[0][0][0] sram[221]->outb sram[221]->out sram[222]->out sram[222]->outb sram[223]->outb sram[223]->out sram[224]->out sram[224]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****1010***** -Xsram[221] sram->in sram[221]->out sram[221]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[221]->out) 0 -.nodeset V(sram[221]->outb) vsp -Xsram[222] sram->in sram[222]->out sram[222]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[222]->out) 0 -.nodeset V(sram[222]->outb) vsp -Xsram[223] sram->in sram[223]->out sram[223]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[223]->out) 0 -.nodeset V(sram[223]->outb) vsp -Xsram[224] sram->in sram[224]->out sram[224]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[224]->out) 0 -.nodeset V(sram[224]->outb) vsp -Xmux_2level_tapbuf_size4[2] chanx[1][0]_midout[0] chanx[1][0]_midout[1] chanx[1][0]_midout[16] chanx[1][0]_midout[17] grid[1][0]_pin[0][0][2] sram[225]->outb sram[225]->out sram[226]->out sram[226]->outb sram[227]->outb sram[227]->out sram[228]->out sram[228]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****1010***** -Xsram[225] sram->in sram[225]->out sram[225]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[225]->out) 0 -.nodeset V(sram[225]->outb) vsp -Xsram[226] sram->in sram[226]->out sram[226]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[226]->out) 0 -.nodeset V(sram[226]->outb) vsp -Xsram[227] sram->in sram[227]->out sram[227]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[227]->out) 0 -.nodeset V(sram[227]->outb) vsp -Xsram[228] sram->in sram[228]->out sram[228]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[228]->out) 0 -.nodeset V(sram[228]->outb) vsp -Xmux_2level_tapbuf_size4[3] chanx[1][0]_midout[2] chanx[1][0]_midout[3] chanx[1][0]_midout[18] chanx[1][0]_midout[19] grid[1][0]_pin[0][0][4] sram[229]->outb sram[229]->out sram[230]->out sram[230]->outb sram[231]->outb sram[231]->out sram[232]->out sram[232]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****1010***** -Xsram[229] sram->in sram[229]->out sram[229]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[229]->out) 0 -.nodeset V(sram[229]->outb) vsp -Xsram[230] sram->in sram[230]->out sram[230]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[230]->out) 0 -.nodeset V(sram[230]->outb) vsp -Xsram[231] sram->in sram[231]->out sram[231]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[231]->out) 0 -.nodeset V(sram[231]->outb) vsp -Xsram[232] sram->in sram[232]->out sram[232]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[232]->out) 0 -.nodeset V(sram[232]->outb) vsp -Xmux_2level_tapbuf_size4[4] chanx[1][0]_midout[4] chanx[1][0]_midout[5] chanx[1][0]_midout[20] chanx[1][0]_midout[21] grid[1][0]_pin[0][0][6] sram[233]->outb sram[233]->out sram[234]->out sram[234]->outb sram[235]->outb sram[235]->out sram[236]->out sram[236]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****1010***** -Xsram[233] sram->in sram[233]->out sram[233]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[233]->out) 0 -.nodeset V(sram[233]->outb) vsp -Xsram[234] sram->in sram[234]->out sram[234]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[234]->out) 0 -.nodeset V(sram[234]->outb) vsp -Xsram[235] sram->in sram[235]->out sram[235]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[235]->out) 0 -.nodeset V(sram[235]->outb) vsp -Xsram[236] sram->in sram[236]->out sram[236]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[236]->out) 0 -.nodeset V(sram[236]->outb) vsp -Xmux_2level_tapbuf_size4[5] chanx[1][0]_midout[6] chanx[1][0]_midout[7] chanx[1][0]_midout[22] chanx[1][0]_midout[23] grid[1][0]_pin[0][0][8] sram[237]->outb sram[237]->out sram[238]->out sram[238]->outb sram[239]->outb sram[239]->out sram[240]->out sram[240]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[5], level=2, select_path_id=0. ***** -*****1010***** -Xsram[237] sram->in sram[237]->out sram[237]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[237]->out) 0 -.nodeset V(sram[237]->outb) vsp -Xsram[238] sram->in sram[238]->out sram[238]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[238]->out) 0 -.nodeset V(sram[238]->outb) vsp -Xsram[239] sram->in sram[239]->out sram[239]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[239]->out) 0 -.nodeset V(sram[239]->outb) vsp -Xsram[240] sram->in sram[240]->out sram[240]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[240]->out) 0 -.nodeset V(sram[240]->outb) vsp -Xmux_2level_tapbuf_size4[6] chanx[1][0]_midout[8] chanx[1][0]_midout[9] chanx[1][0]_midout[24] chanx[1][0]_midout[25] grid[1][0]_pin[0][0][10] sram[241]->outb sram[241]->out sram[242]->out sram[242]->outb sram[243]->outb sram[243]->out sram[244]->out sram[244]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****1010***** -Xsram[241] sram->in sram[241]->out sram[241]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[241]->out) 0 -.nodeset V(sram[241]->outb) vsp -Xsram[242] sram->in sram[242]->out sram[242]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[242]->out) 0 -.nodeset V(sram[242]->outb) vsp -Xsram[243] sram->in sram[243]->out sram[243]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[243]->out) 0 -.nodeset V(sram[243]->outb) vsp -Xsram[244] sram->in sram[244]->out sram[244]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[244]->out) 0 -.nodeset V(sram[244]->outb) vsp -Xmux_2level_tapbuf_size4[7] chanx[1][0]_midout[10] chanx[1][0]_midout[11] chanx[1][0]_midout[26] chanx[1][0]_midout[27] grid[1][0]_pin[0][0][12] sram[245]->outb sram[245]->out sram[246]->out sram[246]->outb sram[247]->outb sram[247]->out sram[248]->out sram[248]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****1010***** -Xsram[245] sram->in sram[245]->out sram[245]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[245]->out) 0 -.nodeset V(sram[245]->outb) vsp -Xsram[246] sram->in sram[246]->out sram[246]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[246]->out) 0 -.nodeset V(sram[246]->outb) vsp -Xsram[247] sram->in sram[247]->out sram[247]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[247]->out) 0 -.nodeset V(sram[247]->outb) vsp -Xsram[248] sram->in sram[248]->out sram[248]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[248]->out) 0 -.nodeset V(sram[248]->outb) vsp -Xmux_2level_tapbuf_size4[8] chanx[1][0]_midout[12] chanx[1][0]_midout[13] chanx[1][0]_midout[28] chanx[1][0]_midout[29] grid[1][0]_pin[0][0][14] sram[249]->outb sram[249]->out sram[250]->out sram[250]->outb sram[251]->outb sram[251]->out sram[252]->out sram[252]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****1010***** -Xsram[249] sram->in sram[249]->out sram[249]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[249]->out) 0 -.nodeset V(sram[249]->outb) vsp -Xsram[250] sram->in sram[250]->out sram[250]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[250]->out) 0 -.nodeset V(sram[250]->outb) vsp -Xsram[251] sram->in sram[251]->out sram[251]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[251]->out) 0 -.nodeset V(sram[251]->outb) vsp -Xsram[252] sram->in sram[252]->out sram[252]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[252]->out) 0 -.nodeset V(sram[252]->outb) vsp -.eom diff --git a/examples/spice_test_example_1/subckt/cbx_1_1.sp b/examples/spice_test_example_1/subckt/cbx_1_1.sp deleted file mode 100644 index d11ede211..000000000 --- a/examples/spice_test_example_1/subckt/cbx_1_1.sp +++ /dev/null @@ -1,185 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Connection Block X-channel [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -.subckt cbx[1][1] -+ chanx[1][1]_midout[0] -+ chanx[1][1]_midout[1] -+ chanx[1][1]_midout[2] -+ chanx[1][1]_midout[3] -+ chanx[1][1]_midout[4] -+ chanx[1][1]_midout[5] -+ chanx[1][1]_midout[6] -+ chanx[1][1]_midout[7] -+ chanx[1][1]_midout[8] -+ chanx[1][1]_midout[9] -+ chanx[1][1]_midout[10] -+ chanx[1][1]_midout[11] -+ chanx[1][1]_midout[12] -+ chanx[1][1]_midout[13] -+ chanx[1][1]_midout[14] -+ chanx[1][1]_midout[15] -+ chanx[1][1]_midout[16] -+ chanx[1][1]_midout[17] -+ chanx[1][1]_midout[18] -+ chanx[1][1]_midout[19] -+ chanx[1][1]_midout[20] -+ chanx[1][1]_midout[21] -+ chanx[1][1]_midout[22] -+ chanx[1][1]_midout[23] -+ chanx[1][1]_midout[24] -+ chanx[1][1]_midout[25] -+ chanx[1][1]_midout[26] -+ chanx[1][1]_midout[27] -+ chanx[1][1]_midout[28] -+ chanx[1][1]_midout[29] -+ grid[1][2]_pin[0][2][0] -+ grid[1][2]_pin[0][2][2] -+ grid[1][2]_pin[0][2][4] -+ grid[1][2]_pin[0][2][6] -+ grid[1][2]_pin[0][2][8] -+ grid[1][2]_pin[0][2][10] -+ grid[1][2]_pin[0][2][12] -+ grid[1][2]_pin[0][2][14] -+ grid[1][1]_pin[0][0][0] -+ svdd sgnd -Xmux_2level_tapbuf_size4[9] chanx[1][1]_midout[6] chanx[1][1]_midout[7] chanx[1][1]_midout[12] chanx[1][1]_midout[13] grid[1][2]_pin[0][2][0] sram[253]->outb sram[253]->out sram[254]->out sram[254]->outb sram[255]->outb sram[255]->out sram[256]->out sram[256]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[9], level=2, select_path_id=0. ***** -*****1010***** -Xsram[253] sram->in sram[253]->out sram[253]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[253]->out) 0 -.nodeset V(sram[253]->outb) vsp -Xsram[254] sram->in sram[254]->out sram[254]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[254]->out) 0 -.nodeset V(sram[254]->outb) vsp -Xsram[255] sram->in sram[255]->out sram[255]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[255]->out) 0 -.nodeset V(sram[255]->outb) vsp -Xsram[256] sram->in sram[256]->out sram[256]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[256]->out) 0 -.nodeset V(sram[256]->outb) vsp -Xmux_2level_tapbuf_size4[10] chanx[1][1]_midout[0] chanx[1][1]_midout[1] chanx[1][1]_midout[18] chanx[1][1]_midout[19] grid[1][2]_pin[0][2][2] sram[257]->outb sram[257]->out sram[258]->out sram[258]->outb sram[259]->outb sram[259]->out sram[260]->out sram[260]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[10], level=2, select_path_id=0. ***** -*****1010***** -Xsram[257] sram->in sram[257]->out sram[257]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[257]->out) 0 -.nodeset V(sram[257]->outb) vsp -Xsram[258] sram->in sram[258]->out sram[258]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[258]->out) 0 -.nodeset V(sram[258]->outb) vsp -Xsram[259] sram->in sram[259]->out sram[259]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[259]->out) 0 -.nodeset V(sram[259]->outb) vsp -Xsram[260] sram->in sram[260]->out sram[260]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[260]->out) 0 -.nodeset V(sram[260]->outb) vsp -Xmux_2level_tapbuf_size4[11] chanx[1][1]_midout[2] chanx[1][1]_midout[3] chanx[1][1]_midout[16] chanx[1][1]_midout[17] grid[1][2]_pin[0][2][4] sram[261]->outb sram[261]->out sram[262]->out sram[262]->outb sram[263]->outb sram[263]->out sram[264]->out sram[264]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[11], level=2, select_path_id=0. ***** -*****1010***** -Xsram[261] sram->in sram[261]->out sram[261]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[261]->out) 0 -.nodeset V(sram[261]->outb) vsp -Xsram[262] sram->in sram[262]->out sram[262]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[262]->out) 0 -.nodeset V(sram[262]->outb) vsp -Xsram[263] sram->in sram[263]->out sram[263]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[263]->out) 0 -.nodeset V(sram[263]->outb) vsp -Xsram[264] sram->in sram[264]->out sram[264]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[264]->out) 0 -.nodeset V(sram[264]->outb) vsp -Xmux_2level_tapbuf_size4[12] chanx[1][1]_midout[4] chanx[1][1]_midout[5] chanx[1][1]_midout[20] chanx[1][1]_midout[21] grid[1][2]_pin[0][2][6] sram[265]->outb sram[265]->out sram[266]->out sram[266]->outb sram[267]->outb sram[267]->out sram[268]->out sram[268]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[12], level=2, select_path_id=0. ***** -*****1010***** -Xsram[265] sram->in sram[265]->out sram[265]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[265]->out) 0 -.nodeset V(sram[265]->outb) vsp -Xsram[266] sram->in sram[266]->out sram[266]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[266]->out) 0 -.nodeset V(sram[266]->outb) vsp -Xsram[267] sram->in sram[267]->out sram[267]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[267]->out) 0 -.nodeset V(sram[267]->outb) vsp -Xsram[268] sram->in sram[268]->out sram[268]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[268]->out) 0 -.nodeset V(sram[268]->outb) vsp -Xmux_2level_tapbuf_size4[13] chanx[1][1]_midout[10] chanx[1][1]_midout[11] chanx[1][1]_midout[22] chanx[1][1]_midout[23] grid[1][2]_pin[0][2][8] sram[269]->outb sram[269]->out sram[270]->out sram[270]->outb sram[271]->outb sram[271]->out sram[272]->out sram[272]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[13], level=2, select_path_id=0. ***** -*****1010***** -Xsram[269] sram->in sram[269]->out sram[269]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[269]->out) 0 -.nodeset V(sram[269]->outb) vsp -Xsram[270] sram->in sram[270]->out sram[270]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[270]->out) 0 -.nodeset V(sram[270]->outb) vsp -Xsram[271] sram->in sram[271]->out sram[271]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[271]->out) 0 -.nodeset V(sram[271]->outb) vsp -Xsram[272] sram->in sram[272]->out sram[272]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[272]->out) 0 -.nodeset V(sram[272]->outb) vsp -Xmux_2level_tapbuf_size4[14] chanx[1][1]_midout[8] chanx[1][1]_midout[9] chanx[1][1]_midout[24] chanx[1][1]_midout[25] grid[1][2]_pin[0][2][10] sram[273]->outb sram[273]->out sram[274]->out sram[274]->outb sram[275]->outb sram[275]->out sram[276]->out sram[276]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[14], level=2, select_path_id=0. ***** -*****1010***** -Xsram[273] sram->in sram[273]->out sram[273]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[273]->out) 0 -.nodeset V(sram[273]->outb) vsp -Xsram[274] sram->in sram[274]->out sram[274]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[274]->out) 0 -.nodeset V(sram[274]->outb) vsp -Xsram[275] sram->in sram[275]->out sram[275]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[275]->out) 0 -.nodeset V(sram[275]->outb) vsp -Xsram[276] sram->in sram[276]->out sram[276]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[276]->out) 0 -.nodeset V(sram[276]->outb) vsp -Xmux_2level_tapbuf_size4[15] chanx[1][1]_midout[14] chanx[1][1]_midout[15] chanx[1][1]_midout[26] chanx[1][1]_midout[27] grid[1][2]_pin[0][2][12] sram[277]->outb sram[277]->out sram[278]->out sram[278]->outb sram[279]->outb sram[279]->out sram[280]->out sram[280]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[15], level=2, select_path_id=0. ***** -*****1010***** -Xsram[277] sram->in sram[277]->out sram[277]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[277]->out) 0 -.nodeset V(sram[277]->outb) vsp -Xsram[278] sram->in sram[278]->out sram[278]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[278]->out) 0 -.nodeset V(sram[278]->outb) vsp -Xsram[279] sram->in sram[279]->out sram[279]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[279]->out) 0 -.nodeset V(sram[279]->outb) vsp -Xsram[280] sram->in sram[280]->out sram[280]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[280]->out) 0 -.nodeset V(sram[280]->outb) vsp -Xmux_2level_tapbuf_size4[16] chanx[1][1]_midout[12] chanx[1][1]_midout[13] chanx[1][1]_midout[28] chanx[1][1]_midout[29] grid[1][2]_pin[0][2][14] sram[281]->outb sram[281]->out sram[282]->out sram[282]->outb sram[283]->outb sram[283]->out sram[284]->out sram[284]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[16], level=2, select_path_id=0. ***** -*****1010***** -Xsram[281] sram->in sram[281]->out sram[281]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[281]->out) 0 -.nodeset V(sram[281]->outb) vsp -Xsram[282] sram->in sram[282]->out sram[282]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[282]->out) 0 -.nodeset V(sram[282]->outb) vsp -Xsram[283] sram->in sram[283]->out sram[283]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[283]->out) 0 -.nodeset V(sram[283]->outb) vsp -Xsram[284] sram->in sram[284]->out sram[284]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[284]->out) 0 -.nodeset V(sram[284]->outb) vsp -Xmux_2level_tapbuf_size4[17] chanx[1][1]_midout[6] chanx[1][1]_midout[7] chanx[1][1]_midout[12] chanx[1][1]_midout[13] grid[1][1]_pin[0][0][0] sram[285]->outb sram[285]->out sram[286]->out sram[286]->outb sram[287]->outb sram[287]->out sram[288]->out sram[288]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[17], level=2, select_path_id=0. ***** -*****1010***** -Xsram[285] sram->in sram[285]->out sram[285]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[285]->out) 0 -.nodeset V(sram[285]->outb) vsp -Xsram[286] sram->in sram[286]->out sram[286]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[286]->out) 0 -.nodeset V(sram[286]->outb) vsp -Xsram[287] sram->in sram[287]->out sram[287]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[287]->out) 0 -.nodeset V(sram[287]->outb) vsp -Xsram[288] sram->in sram[288]->out sram[288]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[288]->out) 0 -.nodeset V(sram[288]->outb) vsp -.eom diff --git a/examples/spice_test_example_1/subckt/cby_0_1.sp b/examples/spice_test_example_1/subckt/cby_0_1.sp deleted file mode 100644 index 0cc68a295..000000000 --- a/examples/spice_test_example_1/subckt/cby_0_1.sp +++ /dev/null @@ -1,185 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Connection Block Y-channel [0][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -.subckt cby[0][1] -+ chany[0][1]_midout[0] -+ chany[0][1]_midout[1] -+ chany[0][1]_midout[2] -+ chany[0][1]_midout[3] -+ chany[0][1]_midout[4] -+ chany[0][1]_midout[5] -+ chany[0][1]_midout[6] -+ chany[0][1]_midout[7] -+ chany[0][1]_midout[8] -+ chany[0][1]_midout[9] -+ chany[0][1]_midout[10] -+ chany[0][1]_midout[11] -+ chany[0][1]_midout[12] -+ chany[0][1]_midout[13] -+ chany[0][1]_midout[14] -+ chany[0][1]_midout[15] -+ chany[0][1]_midout[16] -+ chany[0][1]_midout[17] -+ chany[0][1]_midout[18] -+ chany[0][1]_midout[19] -+ chany[0][1]_midout[20] -+ chany[0][1]_midout[21] -+ chany[0][1]_midout[22] -+ chany[0][1]_midout[23] -+ chany[0][1]_midout[24] -+ chany[0][1]_midout[25] -+ chany[0][1]_midout[26] -+ chany[0][1]_midout[27] -+ chany[0][1]_midout[28] -+ chany[0][1]_midout[29] -+ grid[1][1]_pin[0][3][3] -+ grid[0][1]_pin[0][1][0] -+ grid[0][1]_pin[0][1][2] -+ grid[0][1]_pin[0][1][4] -+ grid[0][1]_pin[0][1][6] -+ grid[0][1]_pin[0][1][8] -+ grid[0][1]_pin[0][1][10] -+ grid[0][1]_pin[0][1][12] -+ grid[0][1]_pin[0][1][14] -+ svdd sgnd -Xmux_2level_tapbuf_size4[18] chany[0][1]_midout[10] chany[0][1]_midout[11] chany[0][1]_midout[26] chany[0][1]_midout[27] grid[1][1]_pin[0][3][3] sram[289]->out sram[289]->outb sram[290]->outb sram[290]->out sram[291]->out sram[291]->outb sram[292]->outb sram[292]->out svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[18], level=2, select_path_id=3. ***** -*****0101***** -Xsram[289] sram->in sram[289]->out sram[289]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[289]->out) 0 -.nodeset V(sram[289]->outb) vsp -Xsram[290] sram->in sram[290]->out sram[290]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[290]->out) 0 -.nodeset V(sram[290]->outb) vsp -Xsram[291] sram->in sram[291]->out sram[291]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[291]->out) 0 -.nodeset V(sram[291]->outb) vsp -Xsram[292] sram->in sram[292]->out sram[292]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[292]->out) 0 -.nodeset V(sram[292]->outb) vsp -Xmux_2level_tapbuf_size4[19] chany[0][1]_midout[0] chany[0][1]_midout[1] chany[0][1]_midout[14] chany[0][1]_midout[15] grid[0][1]_pin[0][1][0] sram[293]->outb sram[293]->out sram[294]->out sram[294]->outb sram[295]->outb sram[295]->out sram[296]->out sram[296]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[19], level=2, select_path_id=0. ***** -*****1010***** -Xsram[293] sram->in sram[293]->out sram[293]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[293]->out) 0 -.nodeset V(sram[293]->outb) vsp -Xsram[294] sram->in sram[294]->out sram[294]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[294]->out) 0 -.nodeset V(sram[294]->outb) vsp -Xsram[295] sram->in sram[295]->out sram[295]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[295]->out) 0 -.nodeset V(sram[295]->outb) vsp -Xsram[296] sram->in sram[296]->out sram[296]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[296]->out) 0 -.nodeset V(sram[296]->outb) vsp -Xmux_2level_tapbuf_size4[20] chany[0][1]_midout[2] chany[0][1]_midout[3] chany[0][1]_midout[16] chany[0][1]_midout[17] grid[0][1]_pin[0][1][2] sram[297]->outb sram[297]->out sram[298]->out sram[298]->outb sram[299]->outb sram[299]->out sram[300]->out sram[300]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[20], level=2, select_path_id=0. ***** -*****1010***** -Xsram[297] sram->in sram[297]->out sram[297]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[297]->out) 0 -.nodeset V(sram[297]->outb) vsp -Xsram[298] sram->in sram[298]->out sram[298]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[298]->out) 0 -.nodeset V(sram[298]->outb) vsp -Xsram[299] sram->in sram[299]->out sram[299]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[299]->out) 0 -.nodeset V(sram[299]->outb) vsp -Xsram[300] sram->in sram[300]->out sram[300]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[300]->out) 0 -.nodeset V(sram[300]->outb) vsp -Xmux_2level_tapbuf_size4[21] chany[0][1]_midout[4] chany[0][1]_midout[5] chany[0][1]_midout[18] chany[0][1]_midout[19] grid[0][1]_pin[0][1][4] sram[301]->outb sram[301]->out sram[302]->out sram[302]->outb sram[303]->outb sram[303]->out sram[304]->out sram[304]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[21], level=2, select_path_id=0. ***** -*****1010***** -Xsram[301] sram->in sram[301]->out sram[301]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[301]->out) 0 -.nodeset V(sram[301]->outb) vsp -Xsram[302] sram->in sram[302]->out sram[302]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[302]->out) 0 -.nodeset V(sram[302]->outb) vsp -Xsram[303] sram->in sram[303]->out sram[303]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[303]->out) 0 -.nodeset V(sram[303]->outb) vsp -Xsram[304] sram->in sram[304]->out sram[304]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[304]->out) 0 -.nodeset V(sram[304]->outb) vsp -Xmux_2level_tapbuf_size4[22] chany[0][1]_midout[6] chany[0][1]_midout[7] chany[0][1]_midout[20] chany[0][1]_midout[21] grid[0][1]_pin[0][1][6] sram[305]->outb sram[305]->out sram[306]->out sram[306]->outb sram[307]->outb sram[307]->out sram[308]->out sram[308]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[22], level=2, select_path_id=0. ***** -*****1010***** -Xsram[305] sram->in sram[305]->out sram[305]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[305]->out) 0 -.nodeset V(sram[305]->outb) vsp -Xsram[306] sram->in sram[306]->out sram[306]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[306]->out) 0 -.nodeset V(sram[306]->outb) vsp -Xsram[307] sram->in sram[307]->out sram[307]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[307]->out) 0 -.nodeset V(sram[307]->outb) vsp -Xsram[308] sram->in sram[308]->out sram[308]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[308]->out) 0 -.nodeset V(sram[308]->outb) vsp -Xmux_2level_tapbuf_size4[23] chany[0][1]_midout[6] chany[0][1]_midout[7] chany[0][1]_midout[22] chany[0][1]_midout[23] grid[0][1]_pin[0][1][8] sram[309]->outb sram[309]->out sram[310]->out sram[310]->outb sram[311]->outb sram[311]->out sram[312]->out sram[312]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[23], level=2, select_path_id=0. ***** -*****1010***** -Xsram[309] sram->in sram[309]->out sram[309]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[309]->out) 0 -.nodeset V(sram[309]->outb) vsp -Xsram[310] sram->in sram[310]->out sram[310]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[310]->out) 0 -.nodeset V(sram[310]->outb) vsp -Xsram[311] sram->in sram[311]->out sram[311]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[311]->out) 0 -.nodeset V(sram[311]->outb) vsp -Xsram[312] sram->in sram[312]->out sram[312]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[312]->out) 0 -.nodeset V(sram[312]->outb) vsp -Xmux_2level_tapbuf_size4[24] chany[0][1]_midout[8] chany[0][1]_midout[9] chany[0][1]_midout[24] chany[0][1]_midout[25] grid[0][1]_pin[0][1][10] sram[313]->outb sram[313]->out sram[314]->out sram[314]->outb sram[315]->outb sram[315]->out sram[316]->out sram[316]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[24], level=2, select_path_id=0. ***** -*****1010***** -Xsram[313] sram->in sram[313]->out sram[313]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[313]->out) 0 -.nodeset V(sram[313]->outb) vsp -Xsram[314] sram->in sram[314]->out sram[314]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[314]->out) 0 -.nodeset V(sram[314]->outb) vsp -Xsram[315] sram->in sram[315]->out sram[315]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[315]->out) 0 -.nodeset V(sram[315]->outb) vsp -Xsram[316] sram->in sram[316]->out sram[316]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[316]->out) 0 -.nodeset V(sram[316]->outb) vsp -Xmux_2level_tapbuf_size4[25] chany[0][1]_midout[10] chany[0][1]_midout[11] chany[0][1]_midout[26] chany[0][1]_midout[27] grid[0][1]_pin[0][1][12] sram[317]->outb sram[317]->out sram[318]->out sram[318]->outb sram[319]->outb sram[319]->out sram[320]->out sram[320]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[25], level=2, select_path_id=0. ***** -*****1010***** -Xsram[317] sram->in sram[317]->out sram[317]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[317]->out) 0 -.nodeset V(sram[317]->outb) vsp -Xsram[318] sram->in sram[318]->out sram[318]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[318]->out) 0 -.nodeset V(sram[318]->outb) vsp -Xsram[319] sram->in sram[319]->out sram[319]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[319]->out) 0 -.nodeset V(sram[319]->outb) vsp -Xsram[320] sram->in sram[320]->out sram[320]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[320]->out) 0 -.nodeset V(sram[320]->outb) vsp -Xmux_2level_tapbuf_size4[26] chany[0][1]_midout[12] chany[0][1]_midout[13] chany[0][1]_midout[28] chany[0][1]_midout[29] grid[0][1]_pin[0][1][14] sram[321]->outb sram[321]->out sram[322]->out sram[322]->outb sram[323]->outb sram[323]->out sram[324]->out sram[324]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[26], level=2, select_path_id=0. ***** -*****1010***** -Xsram[321] sram->in sram[321]->out sram[321]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[321]->out) 0 -.nodeset V(sram[321]->outb) vsp -Xsram[322] sram->in sram[322]->out sram[322]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[322]->out) 0 -.nodeset V(sram[322]->outb) vsp -Xsram[323] sram->in sram[323]->out sram[323]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[323]->out) 0 -.nodeset V(sram[323]->outb) vsp -Xsram[324] sram->in sram[324]->out sram[324]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[324]->out) 0 -.nodeset V(sram[324]->outb) vsp -.eom diff --git a/examples/spice_test_example_1/subckt/cby_1_1.sp b/examples/spice_test_example_1/subckt/cby_1_1.sp deleted file mode 100644 index f582f1524..000000000 --- a/examples/spice_test_example_1/subckt/cby_1_1.sp +++ /dev/null @@ -1,186 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Connection Block Y-channel [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -.subckt cby[1][1] -+ chany[1][1]_midout[0] -+ chany[1][1]_midout[1] -+ chany[1][1]_midout[2] -+ chany[1][1]_midout[3] -+ chany[1][1]_midout[4] -+ chany[1][1]_midout[5] -+ chany[1][1]_midout[6] -+ chany[1][1]_midout[7] -+ chany[1][1]_midout[8] -+ chany[1][1]_midout[9] -+ chany[1][1]_midout[10] -+ chany[1][1]_midout[11] -+ chany[1][1]_midout[12] -+ chany[1][1]_midout[13] -+ chany[1][1]_midout[14] -+ chany[1][1]_midout[15] -+ chany[1][1]_midout[16] -+ chany[1][1]_midout[17] -+ chany[1][1]_midout[18] -+ chany[1][1]_midout[19] -+ chany[1][1]_midout[20] -+ chany[1][1]_midout[21] -+ chany[1][1]_midout[22] -+ chany[1][1]_midout[23] -+ chany[1][1]_midout[24] -+ chany[1][1]_midout[25] -+ chany[1][1]_midout[26] -+ chany[1][1]_midout[27] -+ chany[1][1]_midout[28] -+ chany[1][1]_midout[29] -+ grid[2][1]_pin[0][3][0] -+ grid[2][1]_pin[0][3][2] -+ grid[2][1]_pin[0][3][4] -+ grid[2][1]_pin[0][3][6] -+ grid[2][1]_pin[0][3][8] -+ grid[2][1]_pin[0][3][10] -+ grid[2][1]_pin[0][3][12] -+ grid[2][1]_pin[0][3][14] -+ grid[1][1]_pin[0][1][1] -+ grid[1][1]_pin[0][1][5] -+ svdd sgnd -Xmux_2level_tapbuf_size4[27] chany[1][1]_midout[6] chany[1][1]_midout[7] chany[1][1]_midout[18] chany[1][1]_midout[19] grid[2][1]_pin[0][3][0] sram[325]->outb sram[325]->out sram[326]->out sram[326]->outb sram[327]->outb sram[327]->out sram[328]->out sram[328]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[27], level=2, select_path_id=0. ***** -*****1010***** -Xsram[325] sram->in sram[325]->out sram[325]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[325]->out) 0 -.nodeset V(sram[325]->outb) vsp -Xsram[326] sram->in sram[326]->out sram[326]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[326]->out) 0 -.nodeset V(sram[326]->outb) vsp -Xsram[327] sram->in sram[327]->out sram[327]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[327]->out) 0 -.nodeset V(sram[327]->outb) vsp -Xsram[328] sram->in sram[328]->out sram[328]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[328]->out) 0 -.nodeset V(sram[328]->outb) vsp -Xmux_2level_tapbuf_size4[28] chany[1][1]_midout[0] chany[1][1]_midout[1] chany[1][1]_midout[16] chany[1][1]_midout[17] grid[2][1]_pin[0][3][2] sram[329]->outb sram[329]->out sram[330]->out sram[330]->outb sram[331]->outb sram[331]->out sram[332]->out sram[332]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[28], level=2, select_path_id=0. ***** -*****1010***** -Xsram[329] sram->in sram[329]->out sram[329]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[329]->out) 0 -.nodeset V(sram[329]->outb) vsp -Xsram[330] sram->in sram[330]->out sram[330]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[330]->out) 0 -.nodeset V(sram[330]->outb) vsp -Xsram[331] sram->in sram[331]->out sram[331]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[331]->out) 0 -.nodeset V(sram[331]->outb) vsp -Xsram[332] sram->in sram[332]->out sram[332]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[332]->out) 0 -.nodeset V(sram[332]->outb) vsp -Xmux_2level_tapbuf_size4[29] chany[1][1]_midout[2] chany[1][1]_midout[3] chany[1][1]_midout[20] chany[1][1]_midout[21] grid[2][1]_pin[0][3][4] sram[333]->outb sram[333]->out sram[334]->out sram[334]->outb sram[335]->outb sram[335]->out sram[336]->out sram[336]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[29], level=2, select_path_id=0. ***** -*****1010***** -Xsram[333] sram->in sram[333]->out sram[333]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[333]->out) 0 -.nodeset V(sram[333]->outb) vsp -Xsram[334] sram->in sram[334]->out sram[334]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[334]->out) 0 -.nodeset V(sram[334]->outb) vsp -Xsram[335] sram->in sram[335]->out sram[335]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[335]->out) 0 -.nodeset V(sram[335]->outb) vsp -Xsram[336] sram->in sram[336]->out sram[336]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[336]->out) 0 -.nodeset V(sram[336]->outb) vsp -Xmux_2level_tapbuf_size4[30] chany[1][1]_midout[4] chany[1][1]_midout[5] chany[1][1]_midout[22] chany[1][1]_midout[23] grid[2][1]_pin[0][3][6] sram[337]->outb sram[337]->out sram[338]->out sram[338]->outb sram[339]->outb sram[339]->out sram[340]->out sram[340]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[30], level=2, select_path_id=0. ***** -*****1010***** -Xsram[337] sram->in sram[337]->out sram[337]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[337]->out) 0 -.nodeset V(sram[337]->outb) vsp -Xsram[338] sram->in sram[338]->out sram[338]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[338]->out) 0 -.nodeset V(sram[338]->outb) vsp -Xsram[339] sram->in sram[339]->out sram[339]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[339]->out) 0 -.nodeset V(sram[339]->outb) vsp -Xsram[340] sram->in sram[340]->out sram[340]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[340]->out) 0 -.nodeset V(sram[340]->outb) vsp -Xmux_2level_tapbuf_size4[31] chany[1][1]_midout[10] chany[1][1]_midout[11] chany[1][1]_midout[22] chany[1][1]_midout[23] grid[2][1]_pin[0][3][8] sram[341]->outb sram[341]->out sram[342]->out sram[342]->outb sram[343]->outb sram[343]->out sram[344]->out sram[344]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[31], level=2, select_path_id=0. ***** -*****1010***** -Xsram[341] sram->in sram[341]->out sram[341]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[341]->out) 0 -.nodeset V(sram[341]->outb) vsp -Xsram[342] sram->in sram[342]->out sram[342]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[342]->out) 0 -.nodeset V(sram[342]->outb) vsp -Xsram[343] sram->in sram[343]->out sram[343]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[343]->out) 0 -.nodeset V(sram[343]->outb) vsp -Xsram[344] sram->in sram[344]->out sram[344]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[344]->out) 0 -.nodeset V(sram[344]->outb) vsp -Xmux_2level_tapbuf_size4[32] chany[1][1]_midout[8] chany[1][1]_midout[9] chany[1][1]_midout[24] chany[1][1]_midout[25] grid[2][1]_pin[0][3][10] sram[345]->outb sram[345]->out sram[346]->out sram[346]->outb sram[347]->outb sram[347]->out sram[348]->out sram[348]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[32], level=2, select_path_id=0. ***** -*****1010***** -Xsram[345] sram->in sram[345]->out sram[345]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[345]->out) 0 -.nodeset V(sram[345]->outb) vsp -Xsram[346] sram->in sram[346]->out sram[346]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[346]->out) 0 -.nodeset V(sram[346]->outb) vsp -Xsram[347] sram->in sram[347]->out sram[347]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[347]->out) 0 -.nodeset V(sram[347]->outb) vsp -Xsram[348] sram->in sram[348]->out sram[348]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[348]->out) 0 -.nodeset V(sram[348]->outb) vsp -Xmux_2level_tapbuf_size4[33] chany[1][1]_midout[14] chany[1][1]_midout[15] chany[1][1]_midout[26] chany[1][1]_midout[27] grid[2][1]_pin[0][3][12] sram[349]->outb sram[349]->out sram[350]->out sram[350]->outb sram[351]->outb sram[351]->out sram[352]->out sram[352]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[33], level=2, select_path_id=0. ***** -*****1010***** -Xsram[349] sram->in sram[349]->out sram[349]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[349]->out) 0 -.nodeset V(sram[349]->outb) vsp -Xsram[350] sram->in sram[350]->out sram[350]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[350]->out) 0 -.nodeset V(sram[350]->outb) vsp -Xsram[351] sram->in sram[351]->out sram[351]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[351]->out) 0 -.nodeset V(sram[351]->outb) vsp -Xsram[352] sram->in sram[352]->out sram[352]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[352]->out) 0 -.nodeset V(sram[352]->outb) vsp -Xmux_2level_tapbuf_size4[34] chany[1][1]_midout[12] chany[1][1]_midout[13] chany[1][1]_midout[28] chany[1][1]_midout[29] grid[2][1]_pin[0][3][14] sram[353]->outb sram[353]->out sram[354]->out sram[354]->outb sram[355]->outb sram[355]->out sram[356]->out sram[356]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[34], level=2, select_path_id=0. ***** -*****1010***** -Xsram[353] sram->in sram[353]->out sram[353]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[353]->out) 0 -.nodeset V(sram[353]->outb) vsp -Xsram[354] sram->in sram[354]->out sram[354]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[354]->out) 0 -.nodeset V(sram[354]->outb) vsp -Xsram[355] sram->in sram[355]->out sram[355]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[355]->out) 0 -.nodeset V(sram[355]->outb) vsp -Xsram[356] sram->in sram[356]->out sram[356]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[356]->out) 0 -.nodeset V(sram[356]->outb) vsp -Xmux_2level_tapbuf_size4[35] chany[1][1]_midout[0] chany[1][1]_midout[1] chany[1][1]_midout[16] chany[1][1]_midout[17] grid[1][1]_pin[0][1][1] sram[357]->outb sram[357]->out sram[358]->out sram[358]->outb sram[359]->outb sram[359]->out sram[360]->out sram[360]->outb svdd sgnd mux_2level_tapbuf_size4 -***** SRAM bits for MUX[35], level=2, select_path_id=0. ***** -*****1010***** -Xsram[357] sram->in sram[357]->out sram[357]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[357]->out) 0 -.nodeset V(sram[357]->outb) vsp -Xsram[358] sram->in sram[358]->out sram[358]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[358]->out) 0 -.nodeset V(sram[358]->outb) vsp -Xsram[359] sram->in sram[359]->out sram[359]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[359]->out) 0 -.nodeset V(sram[359]->outb) vsp -Xsram[360] sram->in sram[360]->out sram[360]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[360]->out) 0 -.nodeset V(sram[360]->outb) vsp -.eom diff --git a/examples/spice_test_example_1/subckt/chanx_1_0.sp b/examples/spice_test_example_1/subckt/chanx_1_0.sp deleted file mode 100644 index 241155fbf..000000000 --- a/examples/spice_test_example_1/subckt/chanx_1_0.sp +++ /dev/null @@ -1,45 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Channel X-direction [1][0] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Subckt for Channel X [1][0] ***** -.subckt chanx[1][0] -+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29 -+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29 -+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29 -+ svdd sgnd -Xtrack_seg[0] in0 out0 mid_out0 svdd sgnd chan_segment_seg0 -Xtrack_seg[1] in1 out1 mid_out1 svdd sgnd chan_segment_seg0 -Xtrack_seg[2] in2 out2 mid_out2 svdd sgnd chan_segment_seg0 -Xtrack_seg[3] in3 out3 mid_out3 svdd sgnd chan_segment_seg0 -Xtrack_seg[4] in4 out4 mid_out4 svdd sgnd chan_segment_seg0 -Xtrack_seg[5] in5 out5 mid_out5 svdd sgnd chan_segment_seg0 -Xtrack_seg[6] in6 out6 mid_out6 svdd sgnd chan_segment_seg0 -Xtrack_seg[7] in7 out7 mid_out7 svdd sgnd chan_segment_seg0 -Xtrack_seg[8] in8 out8 mid_out8 svdd sgnd chan_segment_seg0 -Xtrack_seg[9] in9 out9 mid_out9 svdd sgnd chan_segment_seg0 -Xtrack_seg[10] in10 out10 mid_out10 svdd sgnd chan_segment_seg0 -Xtrack_seg[11] in11 out11 mid_out11 svdd sgnd chan_segment_seg0 -Xtrack_seg[12] in12 out12 mid_out12 svdd sgnd chan_segment_seg1 -Xtrack_seg[13] in13 out13 mid_out13 svdd sgnd chan_segment_seg1 -Xtrack_seg[14] in14 out14 mid_out14 svdd sgnd chan_segment_seg1 -Xtrack_seg[15] in15 out15 mid_out15 svdd sgnd chan_segment_seg1 -Xtrack_seg[16] in16 out16 mid_out16 svdd sgnd chan_segment_seg1 -Xtrack_seg[17] in17 out17 mid_out17 svdd sgnd chan_segment_seg1 -Xtrack_seg[18] in18 out18 mid_out18 svdd sgnd chan_segment_seg1 -Xtrack_seg[19] in19 out19 mid_out19 svdd sgnd chan_segment_seg1 -Xtrack_seg[20] in20 out20 mid_out20 svdd sgnd chan_segment_seg1 -Xtrack_seg[21] in21 out21 mid_out21 svdd sgnd chan_segment_seg1 -Xtrack_seg[22] in22 out22 mid_out22 svdd sgnd chan_segment_seg2 -Xtrack_seg[23] in23 out23 mid_out23 svdd sgnd chan_segment_seg2 -Xtrack_seg[24] in24 out24 mid_out24 svdd sgnd chan_segment_seg2 -Xtrack_seg[25] in25 out25 mid_out25 svdd sgnd chan_segment_seg2 -Xtrack_seg[26] in26 out26 mid_out26 svdd sgnd chan_segment_seg2 -Xtrack_seg[27] in27 out27 mid_out27 svdd sgnd chan_segment_seg2 -Xtrack_seg[28] in28 out28 mid_out28 svdd sgnd chan_segment_seg2 -Xtrack_seg[29] in29 out29 mid_out29 svdd sgnd chan_segment_seg2 -.eom diff --git a/examples/spice_test_example_1/subckt/chanx_1_1.sp b/examples/spice_test_example_1/subckt/chanx_1_1.sp deleted file mode 100644 index 80de89439..000000000 --- a/examples/spice_test_example_1/subckt/chanx_1_1.sp +++ /dev/null @@ -1,45 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Channel X-direction [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Subckt for Channel X [1][1] ***** -.subckt chanx[1][1] -+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29 -+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29 -+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29 -+ svdd sgnd -Xtrack_seg[30] in0 out0 mid_out0 svdd sgnd chan_segment_seg0 -Xtrack_seg[31] in1 out1 mid_out1 svdd sgnd chan_segment_seg0 -Xtrack_seg[32] in2 out2 mid_out2 svdd sgnd chan_segment_seg0 -Xtrack_seg[33] in3 out3 mid_out3 svdd sgnd chan_segment_seg0 -Xtrack_seg[34] in4 out4 mid_out4 svdd sgnd chan_segment_seg0 -Xtrack_seg[35] in5 out5 mid_out5 svdd sgnd chan_segment_seg0 -Xtrack_seg[36] in6 out6 mid_out6 svdd sgnd chan_segment_seg0 -Xtrack_seg[37] in7 out7 mid_out7 svdd sgnd chan_segment_seg0 -Xtrack_seg[38] in8 out8 mid_out8 svdd sgnd chan_segment_seg0 -Xtrack_seg[39] in9 out9 mid_out9 svdd sgnd chan_segment_seg0 -Xtrack_seg[40] in10 out10 mid_out10 svdd sgnd chan_segment_seg0 -Xtrack_seg[41] in11 out11 mid_out11 svdd sgnd chan_segment_seg0 -Xtrack_seg[42] in12 out12 mid_out12 svdd sgnd chan_segment_seg1 -Xtrack_seg[43] in13 out13 mid_out13 svdd sgnd chan_segment_seg1 -Xtrack_seg[44] in14 out14 mid_out14 svdd sgnd chan_segment_seg1 -Xtrack_seg[45] in15 out15 mid_out15 svdd sgnd chan_segment_seg1 -Xtrack_seg[46] in16 out16 mid_out16 svdd sgnd chan_segment_seg1 -Xtrack_seg[47] in17 out17 mid_out17 svdd sgnd chan_segment_seg1 -Xtrack_seg[48] in18 out18 mid_out18 svdd sgnd chan_segment_seg1 -Xtrack_seg[49] in19 out19 mid_out19 svdd sgnd chan_segment_seg1 -Xtrack_seg[50] in20 out20 mid_out20 svdd sgnd chan_segment_seg1 -Xtrack_seg[51] in21 out21 mid_out21 svdd sgnd chan_segment_seg1 -Xtrack_seg[52] in22 out22 mid_out22 svdd sgnd chan_segment_seg2 -Xtrack_seg[53] in23 out23 mid_out23 svdd sgnd chan_segment_seg2 -Xtrack_seg[54] in24 out24 mid_out24 svdd sgnd chan_segment_seg2 -Xtrack_seg[55] in25 out25 mid_out25 svdd sgnd chan_segment_seg2 -Xtrack_seg[56] in26 out26 mid_out26 svdd sgnd chan_segment_seg2 -Xtrack_seg[57] in27 out27 mid_out27 svdd sgnd chan_segment_seg2 -Xtrack_seg[58] in28 out28 mid_out28 svdd sgnd chan_segment_seg2 -Xtrack_seg[59] in29 out29 mid_out29 svdd sgnd chan_segment_seg2 -.eom diff --git a/examples/spice_test_example_1/subckt/chany_0_1.sp b/examples/spice_test_example_1/subckt/chany_0_1.sp deleted file mode 100644 index 757fd5698..000000000 --- a/examples/spice_test_example_1/subckt/chany_0_1.sp +++ /dev/null @@ -1,45 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Channel Y-direction [0][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Subckt for Channel Y [0][1] ***** -.subckt chany[0][1] -+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29 -+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29 -+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29 -+ svdd sgnd -Xtrack_seg[60] in0 out0 mid_out0 svdd sgnd chan_segment_seg0 -Xtrack_seg[61] in1 out1 mid_out1 svdd sgnd chan_segment_seg0 -Xtrack_seg[62] in2 out2 mid_out2 svdd sgnd chan_segment_seg0 -Xtrack_seg[63] in3 out3 mid_out3 svdd sgnd chan_segment_seg0 -Xtrack_seg[64] in4 out4 mid_out4 svdd sgnd chan_segment_seg0 -Xtrack_seg[65] in5 out5 mid_out5 svdd sgnd chan_segment_seg0 -Xtrack_seg[66] in6 out6 mid_out6 svdd sgnd chan_segment_seg0 -Xtrack_seg[67] in7 out7 mid_out7 svdd sgnd chan_segment_seg0 -Xtrack_seg[68] in8 out8 mid_out8 svdd sgnd chan_segment_seg0 -Xtrack_seg[69] in9 out9 mid_out9 svdd sgnd chan_segment_seg0 -Xtrack_seg[70] in10 out10 mid_out10 svdd sgnd chan_segment_seg0 -Xtrack_seg[71] in11 out11 mid_out11 svdd sgnd chan_segment_seg0 -Xtrack_seg[72] in12 out12 mid_out12 svdd sgnd chan_segment_seg1 -Xtrack_seg[73] in13 out13 mid_out13 svdd sgnd chan_segment_seg1 -Xtrack_seg[74] in14 out14 mid_out14 svdd sgnd chan_segment_seg1 -Xtrack_seg[75] in15 out15 mid_out15 svdd sgnd chan_segment_seg1 -Xtrack_seg[76] in16 out16 mid_out16 svdd sgnd chan_segment_seg1 -Xtrack_seg[77] in17 out17 mid_out17 svdd sgnd chan_segment_seg1 -Xtrack_seg[78] in18 out18 mid_out18 svdd sgnd chan_segment_seg1 -Xtrack_seg[79] in19 out19 mid_out19 svdd sgnd chan_segment_seg1 -Xtrack_seg[80] in20 out20 mid_out20 svdd sgnd chan_segment_seg1 -Xtrack_seg[81] in21 out21 mid_out21 svdd sgnd chan_segment_seg1 -Xtrack_seg[82] in22 out22 mid_out22 svdd sgnd chan_segment_seg2 -Xtrack_seg[83] in23 out23 mid_out23 svdd sgnd chan_segment_seg2 -Xtrack_seg[84] in24 out24 mid_out24 svdd sgnd chan_segment_seg2 -Xtrack_seg[85] in25 out25 mid_out25 svdd sgnd chan_segment_seg2 -Xtrack_seg[86] in26 out26 mid_out26 svdd sgnd chan_segment_seg2 -Xtrack_seg[87] in27 out27 mid_out27 svdd sgnd chan_segment_seg2 -Xtrack_seg[88] in28 out28 mid_out28 svdd sgnd chan_segment_seg2 -Xtrack_seg[89] in29 out29 mid_out29 svdd sgnd chan_segment_seg2 -.eom diff --git a/examples/spice_test_example_1/subckt/chany_1_1.sp b/examples/spice_test_example_1/subckt/chany_1_1.sp deleted file mode 100644 index 3708ff9a0..000000000 --- a/examples/spice_test_example_1/subckt/chany_1_1.sp +++ /dev/null @@ -1,45 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Channel Y-direction [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Subckt for Channel Y [1][1] ***** -.subckt chany[1][1] -+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29 -+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29 -+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29 -+ svdd sgnd -Xtrack_seg[90] in0 out0 mid_out0 svdd sgnd chan_segment_seg0 -Xtrack_seg[91] in1 out1 mid_out1 svdd sgnd chan_segment_seg0 -Xtrack_seg[92] in2 out2 mid_out2 svdd sgnd chan_segment_seg0 -Xtrack_seg[93] in3 out3 mid_out3 svdd sgnd chan_segment_seg0 -Xtrack_seg[94] in4 out4 mid_out4 svdd sgnd chan_segment_seg0 -Xtrack_seg[95] in5 out5 mid_out5 svdd sgnd chan_segment_seg0 -Xtrack_seg[96] in6 out6 mid_out6 svdd sgnd chan_segment_seg0 -Xtrack_seg[97] in7 out7 mid_out7 svdd sgnd chan_segment_seg0 -Xtrack_seg[98] in8 out8 mid_out8 svdd sgnd chan_segment_seg0 -Xtrack_seg[99] in9 out9 mid_out9 svdd sgnd chan_segment_seg0 -Xtrack_seg[100] in10 out10 mid_out10 svdd sgnd chan_segment_seg0 -Xtrack_seg[101] in11 out11 mid_out11 svdd sgnd chan_segment_seg0 -Xtrack_seg[102] in12 out12 mid_out12 svdd sgnd chan_segment_seg1 -Xtrack_seg[103] in13 out13 mid_out13 svdd sgnd chan_segment_seg1 -Xtrack_seg[104] in14 out14 mid_out14 svdd sgnd chan_segment_seg1 -Xtrack_seg[105] in15 out15 mid_out15 svdd sgnd chan_segment_seg1 -Xtrack_seg[106] in16 out16 mid_out16 svdd sgnd chan_segment_seg1 -Xtrack_seg[107] in17 out17 mid_out17 svdd sgnd chan_segment_seg1 -Xtrack_seg[108] in18 out18 mid_out18 svdd sgnd chan_segment_seg1 -Xtrack_seg[109] in19 out19 mid_out19 svdd sgnd chan_segment_seg1 -Xtrack_seg[110] in20 out20 mid_out20 svdd sgnd chan_segment_seg1 -Xtrack_seg[111] in21 out21 mid_out21 svdd sgnd chan_segment_seg1 -Xtrack_seg[112] in22 out22 mid_out22 svdd sgnd chan_segment_seg2 -Xtrack_seg[113] in23 out23 mid_out23 svdd sgnd chan_segment_seg2 -Xtrack_seg[114] in24 out24 mid_out24 svdd sgnd chan_segment_seg2 -Xtrack_seg[115] in25 out25 mid_out25 svdd sgnd chan_segment_seg2 -Xtrack_seg[116] in26 out26 mid_out26 svdd sgnd chan_segment_seg2 -Xtrack_seg[117] in27 out27 mid_out27 svdd sgnd chan_segment_seg2 -Xtrack_seg[118] in28 out28 mid_out28 svdd sgnd chan_segment_seg2 -Xtrack_seg[119] in29 out29 mid_out29 svdd sgnd chan_segment_seg2 -.eom diff --git a/examples/spice_test_example_1/subckt/grid_0_1.sp b/examples/spice_test_example_1/subckt/grid_0_1.sp deleted file mode 100644 index 3039b5688..000000000 --- a/examples/spice_test_example_1/subckt/grid_0_1.sp +++ /dev/null @@ -1,221 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Phyiscal Logic Block [0][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Grid[0][1] type_descriptor: io[0] ***** -.subckt grid[0][1]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[0] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[0] sram[41]->outb sram[41]->out gvdd_iopad[0] sgnd iopad -***** SRAM bits for IOPAD[0] ***** -*****1***** -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -.eom -.subckt grid[0][1]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[0]_mode[io_phy]_iopad[0] -Xdirect_interc[14] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[15] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[1] ***** -.subckt grid[0][1]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[1] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[1] sram[42]->outb sram[42]->out gvdd_iopad[1] sgnd iopad -***** SRAM bits for IOPAD[1] ***** -*****1***** -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -.eom -.subckt grid[0][1]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[1]_mode[io_phy]_iopad[0] -Xdirect_interc[16] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[17] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[2] ***** -.subckt grid[0][1]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[2] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[2] sram[43]->outb sram[43]->out gvdd_iopad[2] sgnd iopad -***** SRAM bits for IOPAD[2] ***** -*****1***** -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -.eom -.subckt grid[0][1]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[2]_mode[io_phy]_iopad[0] -Xdirect_interc[18] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[19] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[3] ***** -.subckt grid[0][1]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[3] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[3] sram[44]->outb sram[44]->out gvdd_iopad[3] sgnd iopad -***** SRAM bits for IOPAD[3] ***** -*****1***** -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -.eom -.subckt grid[0][1]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[3]_mode[io_phy]_iopad[0] -Xdirect_interc[20] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[21] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[4] ***** -.subckt grid[0][1]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[4] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[4] sram[45]->outb sram[45]->out gvdd_iopad[4] sgnd iopad -***** SRAM bits for IOPAD[4] ***** -*****1***** -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -.eom -.subckt grid[0][1]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[4]_mode[io_phy]_iopad[0] -Xdirect_interc[22] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[23] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[5] ***** -.subckt grid[0][1]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[5] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[5] sram[46]->outb sram[46]->out gvdd_iopad[5] sgnd iopad -***** SRAM bits for IOPAD[5] ***** -*****1***** -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -.eom -.subckt grid[0][1]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[5]_mode[io_phy]_iopad[0] -Xdirect_interc[24] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[25] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[6] ***** -.subckt grid[0][1]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[6] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[6] sram[47]->outb sram[47]->out gvdd_iopad[6] sgnd iopad -***** SRAM bits for IOPAD[6] ***** -*****1***** -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -.eom -.subckt grid[0][1]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[6]_mode[io_phy]_iopad[0] -Xdirect_interc[26] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[27] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[7] ***** -.subckt grid[0][1]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[7] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[7] sram[48]->outb sram[48]->out gvdd_iopad[7] sgnd iopad -***** SRAM bits for IOPAD[7] ***** -*****1***** -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -.eom -.subckt grid[0][1]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[7]_mode[io_phy]_iopad[0] -Xdirect_interc[28] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[29] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1], Capactity: 8 ***** -***** Top Protocol ***** -.subckt grid[0][1] -+ right_height[0]_pin[0] -+ right_height[0]_pin[1] -+ right_height[0]_pin[2] -+ right_height[0]_pin[3] -+ right_height[0]_pin[4] -+ right_height[0]_pin[5] -+ right_height[0]_pin[6] -+ right_height[0]_pin[7] -+ right_height[0]_pin[8] -+ right_height[0]_pin[9] -+ right_height[0]_pin[10] -+ right_height[0]_pin[11] -+ right_height[0]_pin[12] -+ right_height[0]_pin[13] -+ right_height[0]_pin[14] -+ right_height[0]_pin[15] -+ svdd sgnd -Xgrid[0][1][0] -+ right_height[0]_pin[0] -+ right_height[0]_pin[1] -+ svdd sgnd grid[0][1]_io[0]_mode[io_phy] -Xgrid[0][1][1] -+ right_height[0]_pin[2] -+ right_height[0]_pin[3] -+ svdd sgnd grid[0][1]_io[1]_mode[io_phy] -Xgrid[0][1][2] -+ right_height[0]_pin[4] -+ right_height[0]_pin[5] -+ svdd sgnd grid[0][1]_io[2]_mode[io_phy] -Xgrid[0][1][3] -+ right_height[0]_pin[6] -+ right_height[0]_pin[7] -+ svdd sgnd grid[0][1]_io[3]_mode[io_phy] -Xgrid[0][1][4] -+ right_height[0]_pin[8] -+ right_height[0]_pin[9] -+ svdd sgnd grid[0][1]_io[4]_mode[io_phy] -Xgrid[0][1][5] -+ right_height[0]_pin[10] -+ right_height[0]_pin[11] -+ svdd sgnd grid[0][1]_io[5]_mode[io_phy] -Xgrid[0][1][6] -+ right_height[0]_pin[12] -+ right_height[0]_pin[13] -+ svdd sgnd grid[0][1]_io[6]_mode[io_phy] -Xgrid[0][1][7] -+ right_height[0]_pin[14] -+ right_height[0]_pin[15] -+ svdd sgnd grid[0][1]_io[7]_mode[io_phy] -.eom diff --git a/examples/spice_test_example_1/subckt/grid_1_0.sp b/examples/spice_test_example_1/subckt/grid_1_0.sp deleted file mode 100644 index 8785a307b..000000000 --- a/examples/spice_test_example_1/subckt/grid_1_0.sp +++ /dev/null @@ -1,221 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Phyiscal Logic Block [1][0] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Grid[1][0] type_descriptor: io[0] ***** -.subckt grid[1][0]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[16] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[16] sram[57]->outb sram[57]->out gvdd_iopad[16] sgnd iopad -***** SRAM bits for IOPAD[16] ***** -*****1***** -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -.eom -.subckt grid[1][0]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[0]_mode[io_phy]_iopad[0] -Xdirect_interc[46] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[47] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[1] ***** -.subckt grid[1][0]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[17] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[17] sram[58]->outb sram[58]->out gvdd_iopad[17] sgnd iopad -***** SRAM bits for IOPAD[17] ***** -*****1***** -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -.eom -.subckt grid[1][0]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[1]_mode[io_phy]_iopad[0] -Xdirect_interc[48] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[49] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[2] ***** -.subckt grid[1][0]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[18] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[18] sram[59]->outb sram[59]->out gvdd_iopad[18] sgnd iopad -***** SRAM bits for IOPAD[18] ***** -*****1***** -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -.eom -.subckt grid[1][0]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[2]_mode[io_phy]_iopad[0] -Xdirect_interc[50] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[51] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[3] ***** -.subckt grid[1][0]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[19] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[19] sram[60]->outb sram[60]->out gvdd_iopad[19] sgnd iopad -***** SRAM bits for IOPAD[19] ***** -*****1***** -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -.eom -.subckt grid[1][0]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[3]_mode[io_phy]_iopad[0] -Xdirect_interc[52] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[53] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[4] ***** -.subckt grid[1][0]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[20] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[20] sram[61]->outb sram[61]->out gvdd_iopad[20] sgnd iopad -***** SRAM bits for IOPAD[20] ***** -*****1***** -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -.eom -.subckt grid[1][0]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[4]_mode[io_phy]_iopad[0] -Xdirect_interc[54] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[55] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[5] ***** -.subckt grid[1][0]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[21] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[21] sram[62]->outb sram[62]->out gvdd_iopad[21] sgnd iopad -***** SRAM bits for IOPAD[21] ***** -*****1***** -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -.eom -.subckt grid[1][0]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[5]_mode[io_phy]_iopad[0] -Xdirect_interc[56] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[57] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[6] ***** -.subckt grid[1][0]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[22] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[22] sram[63]->outb sram[63]->out gvdd_iopad[22] sgnd iopad -***** SRAM bits for IOPAD[22] ***** -*****1***** -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -.eom -.subckt grid[1][0]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[6]_mode[io_phy]_iopad[0] -Xdirect_interc[58] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[59] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[7] ***** -.subckt grid[1][0]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[23] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[23] sram[64]->outb sram[64]->out gvdd_iopad[23] sgnd iopad -***** SRAM bits for IOPAD[23] ***** -*****1***** -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -.eom -.subckt grid[1][0]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[7]_mode[io_phy]_iopad[0] -Xdirect_interc[60] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[61] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0], Capactity: 8 ***** -***** Top Protocol ***** -.subckt grid[1][0] -+ top_height[0]_pin[0] -+ top_height[0]_pin[1] -+ top_height[0]_pin[2] -+ top_height[0]_pin[3] -+ top_height[0]_pin[4] -+ top_height[0]_pin[5] -+ top_height[0]_pin[6] -+ top_height[0]_pin[7] -+ top_height[0]_pin[8] -+ top_height[0]_pin[9] -+ top_height[0]_pin[10] -+ top_height[0]_pin[11] -+ top_height[0]_pin[12] -+ top_height[0]_pin[13] -+ top_height[0]_pin[14] -+ top_height[0]_pin[15] -+ svdd sgnd -Xgrid[1][0][0] -+ top_height[0]_pin[0] -+ top_height[0]_pin[1] -+ svdd sgnd grid[1][0]_io[0]_mode[io_phy] -Xgrid[1][0][1] -+ top_height[0]_pin[2] -+ top_height[0]_pin[3] -+ svdd sgnd grid[1][0]_io[1]_mode[io_phy] -Xgrid[1][0][2] -+ top_height[0]_pin[4] -+ top_height[0]_pin[5] -+ svdd sgnd grid[1][0]_io[2]_mode[io_phy] -Xgrid[1][0][3] -+ top_height[0]_pin[6] -+ top_height[0]_pin[7] -+ svdd sgnd grid[1][0]_io[3]_mode[io_phy] -Xgrid[1][0][4] -+ top_height[0]_pin[8] -+ top_height[0]_pin[9] -+ svdd sgnd grid[1][0]_io[4]_mode[io_phy] -Xgrid[1][0][5] -+ top_height[0]_pin[10] -+ top_height[0]_pin[11] -+ svdd sgnd grid[1][0]_io[5]_mode[io_phy] -Xgrid[1][0][6] -+ top_height[0]_pin[12] -+ top_height[0]_pin[13] -+ svdd sgnd grid[1][0]_io[6]_mode[io_phy] -Xgrid[1][0][7] -+ top_height[0]_pin[14] -+ top_height[0]_pin[15] -+ svdd sgnd grid[1][0]_io[7]_mode[io_phy] -.eom diff --git a/examples/spice_test_example_1/subckt/grid_1_1.sp b/examples/spice_test_example_1/subckt/grid_1_1.sp deleted file mode 100644 index adbefc770..000000000 --- a/examples/spice_test_example_1/subckt/grid_1_1.sp +++ /dev/null @@ -1,209 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Logic Block [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Grid[1][1] type_descriptor: clb[0] ***** -***** Logical block mapped to this LUT: n7 ***** -.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_lut4[0] lut4[0]->in[0] lut4[0]->in[1] lut4[0]->in[2] lut4[0]->in[3] lut4[0]->out[0] svdd sgnd -***** Truth Table for LUT[0], size=4. ***** -* 0--- 1 * -***** SRAM bits for LUT[0], size=4, num_sram=16. ***** -*****0101010101010101***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -Xlut4[0] lut4[0]->in[0] lut4[0]->in[1] lut4[0]->in[2] lut4[0]->in[3] lut4[0]->out[0] sram[0]->out sram[1]->outb sram[2]->out sram[3]->outb sram[4]->out sram[5]->outb sram[6]->out sram[7]->outb sram[8]->out sram[9]->outb sram[10]->out sram[11]->outb sram[12]->out sram[13]->outb sram[14]->out sram[15]->outb gvdd_lut4[0] sgnd lut4 -.eom -***** Logical block mapped to this FF: Q0 ***** -.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[0] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[0] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4] mode[ble4]->in[0] mode[ble4]->in[1] mode[ble4]->in[2] mode[ble4]->in[3] mode[ble4]->out[0] mode[ble4]->clk[0] svdd sgnd -Xlut4[0] lut4[0]->in[0] lut4[0]->in[1] lut4[0]->in[2] lut4[0]->in[3] lut4[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_lut4[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4]_ff[0] -Xmux_1level_tapbuf_size2[0] ff[0]->Q[0] lut4[0]->out[0] mode[ble4]->out[0] sram[16]->outb sram[16]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[0], level=1, select_path_id=0. ***** -*****1***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xdirect_interc[0] mode[ble4]->in[0] lut4[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[1] mode[ble4]->in[1] lut4[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[2] mode[ble4]->in[2] lut4[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[3] mode[ble4]->in[3] lut4[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[4] lut4[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[5] mode[ble4]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4] mode[n1_lut4]->in[0] mode[n1_lut4]->in[1] mode[n1_lut4]->in[2] mode[n1_lut4]->in[3] mode[n1_lut4]->out[0] mode[n1_lut4]->clk[0] svdd sgnd -Xble4[0] ble4[0]->in[0] ble4[0]->in[1] ble4[0]->in[2] ble4[0]->in[3] ble4[0]->out[0] ble4[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4]_ble4[0]_mode[ble4] -Xdirect_interc[6] ble4[0]->out[0] mode[n1_lut4]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[7] mode[n1_lut4]->in[0] ble4[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[8] mode[n1_lut4]->in[1] ble4[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[9] mode[n1_lut4]->in[2] ble4[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[10] mode[n1_lut4]->in[3] ble4[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[11] mode[n1_lut4]->clk[0] ble4[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->O[0] mode[clb]->clk[0] svdd sgnd -Xfle[0] fle[0]->in[0] fle[0]->in[1] fle[0]->in[2] fle[0]->in[3] fle[0]->out[0] fle[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut4] -Xdirect_interc[12] fle[0]->out[0] mode[clb]->O[0] gvdd_local_interc sgnd direct_interc -Xmux_2level_size5[0] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] fle[0]->out[0] fle[0]->in[0] sram[17]->out sram[17]->outb sram[18]->outb sram[18]->out sram[19]->out sram[19]->outb sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->out sram[22]->outb gvdd_local_interc sgnd mux_2level_size5 -***** SRAM bits for MUX[0], level=2, select_path_id=3. ***** -*****010100***** -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xmux_2level_size5[1] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] fle[0]->out[0] fle[0]->in[1] sram[23]->outb sram[23]->out sram[24]->out sram[24]->outb sram[25]->out sram[25]->outb sram[26]->outb sram[26]->out sram[27]->out sram[27]->outb sram[28]->out sram[28]->outb gvdd_local_interc sgnd mux_2level_size5 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****100100***** -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xmux_2level_size5[2] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] fle[0]->out[0] fle[0]->in[2] sram[29]->outb sram[29]->out sram[30]->out sram[30]->outb sram[31]->out sram[31]->outb sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->out sram[34]->outb gvdd_local_interc sgnd mux_2level_size5 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****100100***** -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xmux_2level_size5[3] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] fle[0]->out[0] fle[0]->in[3] sram[35]->outb sram[35]->out sram[36]->out sram[36]->outb sram[37]->out sram[37]->outb sram[38]->outb sram[38]->out sram[39]->out sram[39]->outb sram[40]->out sram[40]->outb gvdd_local_interc sgnd mux_2level_size5 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****100100***** -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -Xdirect_interc[13] mode[clb]->clk[0] fle[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][1], Capactity: 1 ***** -***** Top Protocol ***** -.subckt grid[1][1] -+ top_height[0]_pin[0] -+ top_height[0]_pin[4] -+ right_height[0]_pin[1] -+ right_height[0]_pin[5] -+ bottom_height[0]_pin[2] -+ left_height[0]_pin[3] -+ svdd sgnd -Xgrid[1][1][0] -+ top_height[0]_pin[0] -+ right_height[0]_pin[1] -+ bottom_height[0]_pin[2] -+ left_height[0]_pin[3] -+ top_height[0]_pin[4] -+ right_height[0]_pin[5] -+ svdd sgnd grid[1][1]_clb[0]_mode[clb] -.eom diff --git a/examples/spice_test_example_1/subckt/grid_1_2.sp b/examples/spice_test_example_1/subckt/grid_1_2.sp deleted file mode 100644 index 8d0038a15..000000000 --- a/examples/spice_test_example_1/subckt/grid_1_2.sp +++ /dev/null @@ -1,223 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Phyiscal Logic Block [1][2] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Grid[1][2] type_descriptor: io[0] ***** -.subckt grid[1][2]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[24] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[24] sram[65]->outb sram[65]->out gvdd_iopad[24] sgnd iopad -***** SRAM bits for IOPAD[24] ***** -*****1***** -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -.eom -.subckt grid[1][2]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[0]_mode[io_phy]_iopad[0] -Xdirect_interc[62] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[63] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[1] ***** -***** Logical block mapped to this IO: out_Q0 ***** -.subckt grid[1][2]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[25] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[25] sram[66]->out sram[66]->outb gvdd_iopad[25] sgnd iopad -***** SRAM bits for IOPAD[25] ***** -*****0***** -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -.eom -.subckt grid[1][2]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[1]_mode[io_phy]_iopad[0] -Xdirect_interc[64] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[65] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[2] ***** -.subckt grid[1][2]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[26] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[26] sram[67]->outb sram[67]->out gvdd_iopad[26] sgnd iopad -***** SRAM bits for IOPAD[26] ***** -*****1***** -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -.eom -.subckt grid[1][2]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[2]_mode[io_phy]_iopad[0] -Xdirect_interc[66] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[67] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[3] ***** -.subckt grid[1][2]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[27] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[27] sram[68]->outb sram[68]->out gvdd_iopad[27] sgnd iopad -***** SRAM bits for IOPAD[27] ***** -*****1***** -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -.eom -.subckt grid[1][2]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[3]_mode[io_phy]_iopad[0] -Xdirect_interc[68] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[69] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[4] ***** -.subckt grid[1][2]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[28] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[28] sram[69]->outb sram[69]->out gvdd_iopad[28] sgnd iopad -***** SRAM bits for IOPAD[28] ***** -*****1***** -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -.eom -.subckt grid[1][2]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[4]_mode[io_phy]_iopad[0] -Xdirect_interc[70] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[71] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[5] ***** -.subckt grid[1][2]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[29] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[29] sram[70]->outb sram[70]->out gvdd_iopad[29] sgnd iopad -***** SRAM bits for IOPAD[29] ***** -*****1***** -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -.eom -.subckt grid[1][2]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[5]_mode[io_phy]_iopad[0] -Xdirect_interc[72] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[73] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[6] ***** -***** Logical block mapped to this IO: I0 ***** -.subckt grid[1][2]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[30] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[30] sram[71]->outb sram[71]->out gvdd_iopad[30] sgnd iopad -***** SRAM bits for IOPAD[30] ***** -*****1***** -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -.eom -.subckt grid[1][2]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[6]_mode[io_phy]_iopad[0] -Xdirect_interc[74] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[75] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[7] ***** -.subckt grid[1][2]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[31] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[31] sram[72]->outb sram[72]->out gvdd_iopad[31] sgnd iopad -***** SRAM bits for IOPAD[31] ***** -*****1***** -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -.eom -.subckt grid[1][2]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[7]_mode[io_phy]_iopad[0] -Xdirect_interc[76] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[77] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2], Capactity: 8 ***** -***** Top Protocol ***** -.subckt grid[1][2] -+ bottom_height[0]_pin[0] -+ bottom_height[0]_pin[1] -+ bottom_height[0]_pin[2] -+ bottom_height[0]_pin[3] -+ bottom_height[0]_pin[4] -+ bottom_height[0]_pin[5] -+ bottom_height[0]_pin[6] -+ bottom_height[0]_pin[7] -+ bottom_height[0]_pin[8] -+ bottom_height[0]_pin[9] -+ bottom_height[0]_pin[10] -+ bottom_height[0]_pin[11] -+ bottom_height[0]_pin[12] -+ bottom_height[0]_pin[13] -+ bottom_height[0]_pin[14] -+ bottom_height[0]_pin[15] -+ svdd sgnd -Xgrid[1][2][0] -+ bottom_height[0]_pin[0] -+ bottom_height[0]_pin[1] -+ svdd sgnd grid[1][2]_io[0]_mode[io_phy] -Xgrid[1][2][1] -+ bottom_height[0]_pin[2] -+ bottom_height[0]_pin[3] -+ svdd sgnd grid[1][2]_io[1]_mode[io_phy] -Xgrid[1][2][2] -+ bottom_height[0]_pin[4] -+ bottom_height[0]_pin[5] -+ svdd sgnd grid[1][2]_io[2]_mode[io_phy] -Xgrid[1][2][3] -+ bottom_height[0]_pin[6] -+ bottom_height[0]_pin[7] -+ svdd sgnd grid[1][2]_io[3]_mode[io_phy] -Xgrid[1][2][4] -+ bottom_height[0]_pin[8] -+ bottom_height[0]_pin[9] -+ svdd sgnd grid[1][2]_io[4]_mode[io_phy] -Xgrid[1][2][5] -+ bottom_height[0]_pin[10] -+ bottom_height[0]_pin[11] -+ svdd sgnd grid[1][2]_io[5]_mode[io_phy] -Xgrid[1][2][6] -+ bottom_height[0]_pin[12] -+ bottom_height[0]_pin[13] -+ svdd sgnd grid[1][2]_io[6]_mode[io_phy] -Xgrid[1][2][7] -+ bottom_height[0]_pin[14] -+ bottom_height[0]_pin[15] -+ svdd sgnd grid[1][2]_io[7]_mode[io_phy] -.eom diff --git a/examples/spice_test_example_1/subckt/grid_2_1.sp b/examples/spice_test_example_1/subckt/grid_2_1.sp deleted file mode 100644 index 29b267a44..000000000 --- a/examples/spice_test_example_1/subckt/grid_2_1.sp +++ /dev/null @@ -1,222 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Phyiscal Logic Block [2][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Grid[2][1] type_descriptor: io[0] ***** -.subckt grid[2][1]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[8] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[8] sram[49]->outb sram[49]->out gvdd_iopad[8] sgnd iopad -***** SRAM bits for IOPAD[8] ***** -*****1***** -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -.eom -.subckt grid[2][1]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[0]_mode[io_phy]_iopad[0] -Xdirect_interc[30] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[31] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[1] ***** -.subckt grid[2][1]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[9] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[9] sram[50]->outb sram[50]->out gvdd_iopad[9] sgnd iopad -***** SRAM bits for IOPAD[9] ***** -*****1***** -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -.eom -.subckt grid[2][1]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[1]_mode[io_phy]_iopad[0] -Xdirect_interc[32] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[33] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[2] ***** -.subckt grid[2][1]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[10] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[10] sram[51]->outb sram[51]->out gvdd_iopad[10] sgnd iopad -***** SRAM bits for IOPAD[10] ***** -*****1***** -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -.eom -.subckt grid[2][1]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[2]_mode[io_phy]_iopad[0] -Xdirect_interc[34] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[35] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[3] ***** -.subckt grid[2][1]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[11] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[11] sram[52]->outb sram[52]->out gvdd_iopad[11] sgnd iopad -***** SRAM bits for IOPAD[11] ***** -*****1***** -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -.eom -.subckt grid[2][1]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[3]_mode[io_phy]_iopad[0] -Xdirect_interc[36] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[37] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[4] ***** -.subckt grid[2][1]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[12] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[12] sram[53]->outb sram[53]->out gvdd_iopad[12] sgnd iopad -***** SRAM bits for IOPAD[12] ***** -*****1***** -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -.eom -.subckt grid[2][1]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[4]_mode[io_phy]_iopad[0] -Xdirect_interc[38] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[39] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[5] ***** -.subckt grid[2][1]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[13] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[13] sram[54]->outb sram[54]->out gvdd_iopad[13] sgnd iopad -***** SRAM bits for IOPAD[13] ***** -*****1***** -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -.eom -.subckt grid[2][1]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[5]_mode[io_phy]_iopad[0] -Xdirect_interc[40] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[41] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[6] ***** -.subckt grid[2][1]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[14] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[14] sram[55]->outb sram[55]->out gvdd_iopad[14] sgnd iopad -***** SRAM bits for IOPAD[14] ***** -*****1***** -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -.eom -.subckt grid[2][1]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[6]_mode[io_phy]_iopad[0] -Xdirect_interc[42] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[43] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[7] ***** -***** Logical block mapped to this IO: clk ***** -.subckt grid[2][1]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[15] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[15] sram[56]->outb sram[56]->out gvdd_iopad[15] sgnd iopad -***** SRAM bits for IOPAD[15] ***** -*****1***** -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -.eom -.subckt grid[2][1]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[7]_mode[io_phy]_iopad[0] -Xdirect_interc[44] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[45] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1], Capactity: 8 ***** -***** Top Protocol ***** -.subckt grid[2][1] -+ left_height[0]_pin[0] -+ left_height[0]_pin[1] -+ left_height[0]_pin[2] -+ left_height[0]_pin[3] -+ left_height[0]_pin[4] -+ left_height[0]_pin[5] -+ left_height[0]_pin[6] -+ left_height[0]_pin[7] -+ left_height[0]_pin[8] -+ left_height[0]_pin[9] -+ left_height[0]_pin[10] -+ left_height[0]_pin[11] -+ left_height[0]_pin[12] -+ left_height[0]_pin[13] -+ left_height[0]_pin[14] -+ left_height[0]_pin[15] -+ svdd sgnd -Xgrid[2][1][0] -+ left_height[0]_pin[0] -+ left_height[0]_pin[1] -+ svdd sgnd grid[2][1]_io[0]_mode[io_phy] -Xgrid[2][1][1] -+ left_height[0]_pin[2] -+ left_height[0]_pin[3] -+ svdd sgnd grid[2][1]_io[1]_mode[io_phy] -Xgrid[2][1][2] -+ left_height[0]_pin[4] -+ left_height[0]_pin[5] -+ svdd sgnd grid[2][1]_io[2]_mode[io_phy] -Xgrid[2][1][3] -+ left_height[0]_pin[6] -+ left_height[0]_pin[7] -+ svdd sgnd grid[2][1]_io[3]_mode[io_phy] -Xgrid[2][1][4] -+ left_height[0]_pin[8] -+ left_height[0]_pin[9] -+ svdd sgnd grid[2][1]_io[4]_mode[io_phy] -Xgrid[2][1][5] -+ left_height[0]_pin[10] -+ left_height[0]_pin[11] -+ svdd sgnd grid[2][1]_io[5]_mode[io_phy] -Xgrid[2][1][6] -+ left_height[0]_pin[12] -+ left_height[0]_pin[13] -+ svdd sgnd grid[2][1]_io[6]_mode[io_phy] -Xgrid[2][1][7] -+ left_height[0]_pin[14] -+ left_height[0]_pin[15] -+ svdd sgnd grid[2][1]_io[7]_mode[io_phy] -.eom diff --git a/examples/spice_test_example_1/subckt/grid_header.sp b/examples/spice_test_example_1/subckt/grid_header.sp deleted file mode 100644 index c84bbca94..000000000 --- a/examples/spice_test_example_1/subckt/grid_header.sp +++ /dev/null @@ -1,13 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Header file * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -.include './spice_test_example_1/subckt/grid_1_2.sp' -.include './spice_test_example_1/subckt/grid_1_0.sp' -.include './spice_test_example_1/subckt/grid_2_1.sp' -.include './spice_test_example_1/subckt/grid_0_1.sp' -.include './spice_test_example_1/subckt/grid_1_1.sp' diff --git a/examples/spice_test_example_1/subckt/inv_buf_trans_gate.sp b/examples/spice_test_example_1/subckt/inv_buf_trans_gate.sp deleted file mode 100644 index fc5acafda..000000000 --- a/examples/spice_test_example_1/subckt/inv_buf_trans_gate.sp +++ /dev/null @@ -1,76 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Inverter, Buffer, Trans. Gate * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -* Inverter -.subckt inv in out svdd sgnd size=1 -Xn0_inv out in sgnd sgnd vpr_nmos L=nl W='size*wn' -Xp0_inv out in svdd svdd vpr_pmos L=pl W='size*beta*wp' -.eom inv - -* Powergated Inverter -.subckt pg_inv en enb in out svdd sgnd size=1 pg_size=1 -Xn0_inv out in sgnd_pg sgnd vpr_nmos L=nl W='size*wn' -Xp0_inv out in svdd_pg svdd vpr_pmos L=pl W='size*beta*wp' -Xn0_inv_pg sgnd_pg en sgnd sgnd vpr_nmos L=nl W='pg_size*wn' -Xp0_inv_pg svdd_pg enb svdd svdd vpr_pmos L=pl W='pg_size*beta*wp' -.eom inv - -* Buffer -.subckt buf in out svdd sgnd size=2 base_size=1 -Xinv0 in mid svdd sgnd inv base_size='base_size' -Xinv1 mid out svdd sgnd inv size='size*base_size' -.eom buf - -* Power-gated Buffer -.subckt pg_buf en enb in out svdd sgnd size=2 pg_size=2 -Xinv0 en enb in mid svdd sgnd pg_inv size=1 pg_size=1 -Xinv1 en enb mid out svdd sgnd pg_inv size=size pg_size=size -.eom buf - -* Transmission Gate (Complementary Pass Transistor) -.subckt cpt in out sel sel_inv svdd sgnd nmos_size=1 pmos_size=1 -Xn0_cpt in sel out sgnd vpr_nmos L=nl W='nmos_size*wn' -Xp0_cpt in sel_inv out svdd vpr_pmos L=pl W='pmos_size*wp' -.eom cpt - -.subckt tapbuf_level2_f4 in out svdd sgnd -Rinv_in in in_lvl0 0 -Xinv_lvl0_no0 in_lvl0 in_lvl1 svdd sgnd inv -Xinv_lvl1_no0 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no1 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no2 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no3 in_lvl1 in_lvl2 svdd sgnd inv -Rinv_out in_lvl2 out 0 -.eom - -.subckt tapbuf_level3_f4 in out svdd sgnd -Rinv_in in in_lvl0 0 -Xinv_lvl0_no0 in_lvl0 in_lvl1 svdd sgnd inv -Xinv_lvl1_no0 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no1 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no2 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no3 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl2_no0 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no1 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no2 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no3 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no4 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no5 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no6 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no7 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no8 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no9 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no10 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no11 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no12 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no13 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no14 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no15 in_lvl2 in_lvl3 svdd sgnd inv -Rinv_out in_lvl3 out 0 -.eom - diff --git a/examples/spice_test_example_1/subckt/luts.sp b/examples/spice_test_example_1/subckt/luts.sp deleted file mode 100644 index 8ad3254e6..000000000 --- a/examples/spice_test_example_1/subckt/luts.sp +++ /dev/null @@ -1,24 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: LUTs * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Auto-generated LUT info: spice_model_name = lut4, size = 4 ***** -.subckt lut4 in0 in1 in2 in3 out sram0 sram1 sram2 sram3 sram4 sram5 sram6 sram7 sram8 sram9 sram10 sram11 sram12 sram13 sram14 sram15 svdd sgnd -Xinv0_in0_no0 in0 lut_mux_in0_inv svdd sgnd inv size='4' -Xbuf4_in0 in0 lut_mux_in0 svdd sgnd tapbuf_level2_f4 - -Xinv0_in1_no0 in1 lut_mux_in1_inv svdd sgnd inv size='4' -Xbuf4_in1 in1 lut_mux_in1 svdd sgnd tapbuf_level2_f4 - -Xinv0_in2_no0 in2 lut_mux_in2_inv svdd sgnd inv size='4' -Xbuf4_in2 in2 lut_mux_in2 svdd sgnd tapbuf_level2_f4 - -Xinv0_in3_no0 in3 lut_mux_in3_inv svdd sgnd inv size='4' -Xbuf4_in3 in3 lut_mux_in3 svdd sgnd tapbuf_level2_f4 - -Xlut_mux sram0 sram1 sram2 sram3 sram4 sram5 sram6 sram7 sram8 sram9 sram10 sram11 sram12 sram13 sram14 sram15 out lut_mux_in0 lut_mux_in0_inv lut_mux_in1 lut_mux_in1_inv lut_mux_in2 lut_mux_in2_inv lut_mux_in3 lut_mux_in3_inv svdd sgnd lut4_mux_size16 -.eom diff --git a/examples/spice_test_example_1/subckt/muxes.sp b/examples/spice_test_example_1/subckt/muxes.sp deleted file mode 100644 index feaa27918..000000000 --- a/examples/spice_test_example_1/subckt/muxes.sp +++ /dev/null @@ -1,117 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: MUXes used in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -.subckt mux_2level_tapbuf_size4_basis in0 in1 out sel0 sel_inv0 sel1 sel_inv1 svdd sgnd -Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_2level_tapbuf_pgl_nmos_size' pmos_size='mux_2level_tapbuf_pgl_pmos_size' -Xcpt_1 in1 out sel1 sel_inv1 svdd sgnd cpt nmos_size='mux_2level_tapbuf_pgl_nmos_size' pmos_size='mux_2level_tapbuf_pgl_pmos_size' -.eom - -***** CMOS MUX info: spice_model_name=mux_2level_tapbuf, size=4, structure: multi-level ***** -.subckt mux_2level_tapbuf_size4 in0 in1 in2 in3 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 svdd sgnd -Xmux_basis_no0 mux2_l2_in0 mux2_l2_in1 mux2_l1_in0 sram2 sram_inv2 sram3 sram_inv3 svdd sgnd mux_2level_tapbuf_size4_basis -Xmux_basis_no1 mux2_l2_in2 mux2_l2_in3 mux2_l1_in1 sram2 sram_inv2 sram3 sram_inv3 svdd sgnd mux_2level_tapbuf_size4_basis -Xmux_basis_no2 mux2_l1_in0 mux2_l1_in1 mux2_l0_in0 sram0 sram_inv0 sram1 sram_inv1 svdd sgnd mux_2level_tapbuf_size4_basis -Xinv0 in0 mux2_l2_in0 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv1 in1 mux2_l2_in1 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv2 in2 mux2_l2_in2 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv3 in3 mux2_l2_in3 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xbuf_out mux2_l0_in0 out svdd sgnd tapbuf_level3_f4 -.eom -***** END CMOS MUX info: spice_model_name=mux_2level_tapbuf, size=4 ***** - -.subckt lut4_size16_basis in0 in1 out sel0 sel_inv0 svdd sgnd -Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='lut4_pgl_nmos_size' pmos_size='lut4_pgl_pmos_size' -Xcpt_1 in1 out sel_inv0 sel0 svdd sgnd cpt nmos_size='lut4_pgl_nmos_size' pmos_size='lut4_pgl_pmos_size' -.eom - -***** CMOS MUX info: spice_model_name= lut4_MUX, size=16 ***** -.subckt lut4_mux_size16 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 in15 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 svdd sgnd -Xmux_basis_no0 mux2_l4_in0 mux2_l4_in1 mux2_l3_in0 sram0 sram_inv0 svdd sgnd lut4_size16_basis -Xmux_basis_no1 mux2_l4_in2 mux2_l4_in3 mux2_l3_in1 sram0 sram_inv0 svdd sgnd lut4_size16_basis -Xmux_basis_no2 mux2_l4_in4 mux2_l4_in5 mux2_l3_in2 sram0 sram_inv0 svdd sgnd lut4_size16_basis -Xmux_basis_no3 mux2_l4_in6 mux2_l4_in7 mux2_l3_in3 sram0 sram_inv0 svdd sgnd lut4_size16_basis -Xmux_basis_no4 mux2_l4_in8 mux2_l4_in9 mux2_l3_in4 sram0 sram_inv0 svdd sgnd lut4_size16_basis -Xmux_basis_no5 mux2_l4_in10 mux2_l4_in11 mux2_l3_in5 sram0 sram_inv0 svdd sgnd lut4_size16_basis -Xmux_basis_no6 mux2_l4_in12 mux2_l4_in13 mux2_l3_in6 sram0 sram_inv0 svdd sgnd lut4_size16_basis -Xmux_basis_no7 mux2_l4_in14 mux2_l4_in15 mux2_l3_in7 sram0 sram_inv0 svdd sgnd lut4_size16_basis -Xmux_basis_no8 mux2_l3_in0 mux2_l3_in1 mux2_l2_in0 sram1 sram_inv1 svdd sgnd lut4_size16_basis -Xmux_basis_no9 mux2_l3_in2 mux2_l3_in3 mux2_l2_in1 sram1 sram_inv1 svdd sgnd lut4_size16_basis -Xmux_basis_no10 mux2_l3_in4 mux2_l3_in5 mux2_l2_in2 sram1 sram_inv1 svdd sgnd lut4_size16_basis -Xmux_basis_no11 mux2_l3_in6 mux2_l3_in7 mux2_l2_in3 sram1 sram_inv1 svdd sgnd lut4_size16_basis -Xmux_basis_no12 mux2_l2_in0 mux2_l2_in1 mux2_l1_in0 sram2 sram_inv2 svdd sgnd lut4_size16_basis -Xmux_basis_no13 mux2_l2_in2 mux2_l2_in3 mux2_l1_in1 sram2 sram_inv2 svdd sgnd lut4_size16_basis -Xmux_basis_no14 mux2_l1_in0 mux2_l1_in1 mux2_l0_in0 sram3 sram_inv3 svdd sgnd lut4_size16_basis -Xinv0 in0 mux2_l4_in0 svdd sgnd inv size='lut4_input_buf_size' -Xinv1 in1 mux2_l4_in1 svdd sgnd inv size='lut4_input_buf_size' -Xinv2 in2 mux2_l4_in2 svdd sgnd inv size='lut4_input_buf_size' -Xinv3 in3 mux2_l4_in3 svdd sgnd inv size='lut4_input_buf_size' -Xinv4 in4 mux2_l4_in4 svdd sgnd inv size='lut4_input_buf_size' -Xinv5 in5 mux2_l4_in5 svdd sgnd inv size='lut4_input_buf_size' -Xinv6 in6 mux2_l4_in6 svdd sgnd inv size='lut4_input_buf_size' -Xinv7 in7 mux2_l4_in7 svdd sgnd inv size='lut4_input_buf_size' -Xinv8 in8 mux2_l4_in8 svdd sgnd inv size='lut4_input_buf_size' -Xinv9 in9 mux2_l4_in9 svdd sgnd inv size='lut4_input_buf_size' -Xinv10 in10 mux2_l4_in10 svdd sgnd inv size='lut4_input_buf_size' -Xinv11 in11 mux2_l4_in11 svdd sgnd inv size='lut4_input_buf_size' -Xinv12 in12 mux2_l4_in12 svdd sgnd inv size='lut4_input_buf_size' -Xinv13 in13 mux2_l4_in13 svdd sgnd inv size='lut4_input_buf_size' -Xinv14 in14 mux2_l4_in14 svdd sgnd inv size='lut4_input_buf_size' -Xinv15 in15 mux2_l4_in15 svdd sgnd inv size='lut4_input_buf_size' -Xinv_out mux2_l0_in0 out svdd sgnd inv size='lut4_output_buf_size' -.eom -***** END CMOS MUX info: spice_model_name=lut4, size=16 ***** - -.subckt mux_2level_size5_basis in0 in1 in2 out sel0 sel_inv0 sel1 sel_inv1 sel2 sel_inv2 svdd sgnd -Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -Xcpt_1 in1 out sel1 sel_inv1 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -Xcpt_2 in2 out sel2 sel_inv2 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -.eom - -***** CMOS MUX info: spice_model_name=mux_2level, size=5, structure: multi-level ***** -.subckt mux_2level_size5 in0 in1 in2 in3 in4 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 sram4 sram_inv4 sram5 sram_inv5 svdd sgnd -Xmux_basis_no0 mux2_l2_in0 mux2_l2_in1 mux2_l2_in2 mux2_l1_in0 sram3 sram_inv3 sram4 sram_inv4 sram5 sram_inv5 svdd sgnd mux_2level_size5_basis -Xmux_basis_no1 mux2_l1_in0 mux2_l1_in1 mux2_l1_in2 mux2_l0_in0 sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 svdd sgnd mux_2level_size5_basis -Xinv0 in0 mux2_l2_in0 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv1 in1 mux2_l2_in1 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv2 in2 mux2_l2_in2 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv3 in3 mux2_l1_in1 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv4 in4 mux2_l1_in2 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv_out mux2_l0_in0 out svdd sgnd inv size='mux_2level_output_buf_size' -.eom -***** END CMOS MUX info: spice_model_name=mux_2level, size=5 ***** - -.subckt mux_1level_tapbuf_size2_basis in0 in1 out sel0 sel_inv0 svdd sgnd -Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size' -Xcpt_1 in1 out sel_inv0 sel0 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size' -.eom - -***** CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=2, structure: one-level ***** -.subckt mux_1level_tapbuf_size2 in0 in1 out sram0 sram_inv0 svdd sgnd -Xmux_basis_no0 mux2_l1_in0 mux2_l1_in1 mux2_l0_in0 sram0 sram_inv0 svdd sgnd mux_1level_tapbuf_size2_basis -Xinv0 in0 mux2_l1_in0 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size' -Xinv1 in1 mux2_l1_in1 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size' -Xbuf_out mux2_l0_in0 out svdd sgnd tapbuf_level3_f4 -.eom -***** END CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=2 ***** - -.subckt mux_1level_tapbuf_size3_basis in0 in1 in2 out sel0 sel_inv0 sel1 sel_inv1 sel2 sel_inv2 svdd sgnd -Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size' -Xcpt_1 in1 out sel1 sel_inv1 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size' -Xcpt_2 in2 out sel2 sel_inv2 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size' -.eom - -***** CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=3, structure: one-level ***** -.subckt mux_1level_tapbuf_size3 in0 in1 in2 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 svdd sgnd -Xmux_basis_no0 mux2_l1_in0 mux2_l1_in1 mux2_l1_in2 mux2_l0_in0 sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 svdd sgnd mux_1level_tapbuf_size3_basis -Xinv0 in0 mux2_l1_in0 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size' -Xinv1 in1 mux2_l1_in1 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size' -Xinv2 in2 mux2_l1_in2 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size' -Xbuf_out mux2_l0_in0 out svdd sgnd tapbuf_level3_f4 -.eom -***** END CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=3 ***** - diff --git a/examples/spice_test_example_1/subckt/nmos_pmos.sp b/examples/spice_test_example_1/subckt/nmos_pmos.sp deleted file mode 100644 index c07c80b1a..000000000 --- a/examples/spice_test_example_1/subckt/nmos_pmos.sp +++ /dev/null @@ -1,25 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Standard and I/O NMOS and PMOS * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -* Standard NMOS -.subckt vpr_nmos drain gate source bulk L=nl W=wn -M1 drain gate source bulk nch L=L W=W -.eom vpr_nmos - -* Standard PMOS -.subckt vpr_pmos drain gate source bulk L=pl W=wp -M1 drain gate source bulk pch L=L W=W -.eom vpr_pmos -* I/O NMOS -.subckt vpr_io_nmos drain gate source bulk L=io_nl W=io_wn -M1 drain gate source bulk nch_25 L=L W=W -.eom vpr_io_nmos -* I/O PMOS -.subckt vpr_io_pmos drain gate source bulk L=io_pl W=io_wp -M1 drain gate source bulk pch_25 L=L W=W -.eom vpr_io_pmos diff --git a/examples/spice_test_example_1/subckt/routing_header.sp b/examples/spice_test_example_1/subckt/routing_header.sp deleted file mode 100644 index 2c98afb3e..000000000 --- a/examples/spice_test_example_1/subckt/routing_header.sp +++ /dev/null @@ -1,20 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Header file * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -.include './spice_test_example_1/subckt/cby_1_1.sp' -.include './spice_test_example_1/subckt/cby_0_1.sp' -.include './spice_test_example_1/subckt/cbx_1_1.sp' -.include './spice_test_example_1/subckt/cbx_1_0.sp' -.include './spice_test_example_1/subckt/sb_1_1.sp' -.include './spice_test_example_1/subckt/sb_1_0.sp' -.include './spice_test_example_1/subckt/sb_0_1.sp' -.include './spice_test_example_1/subckt/sb_0_0.sp' -.include './spice_test_example_1/subckt/chany_1_1.sp' -.include './spice_test_example_1/subckt/chany_0_1.sp' -.include './spice_test_example_1/subckt/chanx_1_1.sp' -.include './spice_test_example_1/subckt/chanx_1_0.sp' diff --git a/examples/spice_test_example_1/subckt/sb_0_0.sp b/examples/spice_test_example_1/subckt/sb_0_0.sp deleted file mode 100644 index 13b02a8e8..000000000 --- a/examples/spice_test_example_1/subckt/sb_0_0.sp +++ /dev/null @@ -1,220 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Switch Block [0][0] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Switch Box[0][0] Sub-Circuit ***** -.subckt sb[0][0] -***** Inputs/outputs of top side ***** -+ chany[0][1]_out[0] chany[0][1]_in[1] chany[0][1]_out[2] chany[0][1]_in[3] chany[0][1]_out[4] chany[0][1]_in[5] chany[0][1]_out[6] chany[0][1]_in[7] chany[0][1]_out[8] chany[0][1]_in[9] chany[0][1]_out[10] chany[0][1]_in[11] chany[0][1]_out[12] chany[0][1]_in[13] chany[0][1]_out[14] chany[0][1]_in[15] chany[0][1]_out[16] chany[0][1]_in[17] chany[0][1]_out[18] chany[0][1]_in[19] chany[0][1]_out[20] chany[0][1]_in[21] chany[0][1]_out[22] chany[0][1]_in[23] chany[0][1]_out[24] chany[0][1]_in[25] chany[0][1]_out[26] chany[0][1]_in[27] chany[0][1]_out[28] chany[0][1]_in[29] -+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] -+ ***** Inputs/outputs of right side ***** -+ chanx[1][0]_out[0] chanx[1][0]_in[1] chanx[1][0]_out[2] chanx[1][0]_in[3] chanx[1][0]_out[4] chanx[1][0]_in[5] chanx[1][0]_out[6] chanx[1][0]_in[7] chanx[1][0]_out[8] chanx[1][0]_in[9] chanx[1][0]_out[10] chanx[1][0]_in[11] chanx[1][0]_out[12] chanx[1][0]_in[13] chanx[1][0]_out[14] chanx[1][0]_in[15] chanx[1][0]_out[16] chanx[1][0]_in[17] chanx[1][0]_out[18] chanx[1][0]_in[19] chanx[1][0]_out[20] chanx[1][0]_in[21] chanx[1][0]_out[22] chanx[1][0]_in[23] chanx[1][0]_out[24] chanx[1][0]_in[25] chanx[1][0]_out[26] chanx[1][0]_in[27] chanx[1][0]_out[28] chanx[1][0]_in[29] -+ grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ ***** Inputs/outputs of bottom side ***** -+ -+ -+ ***** Inputs/outputs of left side ***** -+ -+ -+ svdd sgnd -***** top side Multiplexers ***** -Xmux_1level_tapbuf_size3[1] grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][15] chanx[1][0]_in[3] chany[0][1]_out[0] sram[73]->outb sram[73]->out sram[74]->out sram[74]->outb sram[75]->out sram[75]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[1], level=1, select_path_id=0. ***** -*****100***** -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -Xmux_1level_tapbuf_size2[2] grid[0][1]_pin[0][1][1] chanx[1][0]_in[5] chany[0][1]_out[2] sram[76]->outb sram[76]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[2], level=1, select_path_id=0. ***** -*****1***** -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -Xmux_1level_tapbuf_size2[3] grid[0][1]_pin[0][1][3] chanx[1][0]_in[7] chany[0][1]_out[4] sram[77]->outb sram[77]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[3], level=1, select_path_id=0. ***** -*****1***** -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -Xmux_1level_tapbuf_size2[4] grid[0][1]_pin[0][1][3] chanx[1][0]_in[9] chany[0][1]_out[6] sram[78]->outb sram[78]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****1***** -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -Xmux_1level_tapbuf_size2[5] grid[0][1]_pin[0][1][5] chanx[1][0]_in[11] chany[0][1]_out[8] sram[79]->outb sram[79]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[5], level=1, select_path_id=0. ***** -*****1***** -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -Xmux_1level_tapbuf_size2[6] grid[0][1]_pin[0][1][5] chanx[1][0]_in[13] chany[0][1]_out[10] sram[80]->outb sram[80]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[6], level=1, select_path_id=0. ***** -*****1***** -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -Xmux_1level_tapbuf_size2[7] grid[0][1]_pin[0][1][7] chanx[1][0]_in[15] chany[0][1]_out[12] sram[81]->outb sram[81]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[7], level=1, select_path_id=0. ***** -*****1***** -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -Xmux_1level_tapbuf_size2[8] grid[0][1]_pin[0][1][7] chanx[1][0]_in[17] chany[0][1]_out[14] sram[82]->outb sram[82]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[8], level=1, select_path_id=0. ***** -*****1***** -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -Xmux_1level_tapbuf_size2[9] grid[0][1]_pin[0][1][9] chanx[1][0]_in[19] chany[0][1]_out[16] sram[83]->outb sram[83]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[9], level=1, select_path_id=0. ***** -*****1***** -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -Xmux_1level_tapbuf_size2[10] grid[0][1]_pin[0][1][9] chanx[1][0]_in[21] chany[0][1]_out[18] sram[84]->outb sram[84]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[10], level=1, select_path_id=0. ***** -*****1***** -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -Xmux_1level_tapbuf_size2[11] grid[0][1]_pin[0][1][11] chanx[1][0]_in[23] chany[0][1]_out[20] sram[85]->outb sram[85]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[11], level=1, select_path_id=0. ***** -*****1***** -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -Xmux_1level_tapbuf_size2[12] grid[0][1]_pin[0][1][11] chanx[1][0]_in[25] chany[0][1]_out[22] sram[86]->outb sram[86]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[12], level=1, select_path_id=0. ***** -*****1***** -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -Xmux_1level_tapbuf_size2[13] grid[0][1]_pin[0][1][13] chanx[1][0]_in[27] chany[0][1]_out[24] sram[87]->outb sram[87]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[13], level=1, select_path_id=0. ***** -*****1***** -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -Xmux_1level_tapbuf_size2[14] grid[0][1]_pin[0][1][13] chanx[1][0]_in[29] chany[0][1]_out[26] sram[88]->outb sram[88]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[14], level=1, select_path_id=0. ***** -*****1***** -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -Xmux_1level_tapbuf_size2[15] grid[0][1]_pin[0][1][15] chanx[1][0]_in[1] chany[0][1]_out[28] sram[89]->outb sram[89]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[15], level=1, select_path_id=0. ***** -*****1***** -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -***** right side Multiplexers ***** -Xmux_1level_tapbuf_size3[16] grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][15] chany[0][1]_in[29] chanx[1][0]_out[0] sram[90]->outb sram[90]->out sram[91]->out sram[91]->outb sram[92]->out sram[92]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[16], level=1, select_path_id=0. ***** -*****100***** -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -Xmux_1level_tapbuf_size2[17] grid[1][0]_pin[0][0][1] chany[0][1]_in[1] chanx[1][0]_out[2] sram[93]->outb sram[93]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[17], level=1, select_path_id=0. ***** -*****1***** -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -Xmux_1level_tapbuf_size2[18] grid[1][0]_pin[0][0][3] chany[0][1]_in[3] chanx[1][0]_out[4] sram[94]->outb sram[94]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[18], level=1, select_path_id=0. ***** -*****1***** -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -Xmux_1level_tapbuf_size2[19] grid[1][0]_pin[0][0][3] chany[0][1]_in[5] chanx[1][0]_out[6] sram[95]->outb sram[95]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[19], level=1, select_path_id=0. ***** -*****1***** -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -Xmux_1level_tapbuf_size2[20] grid[1][0]_pin[0][0][5] chany[0][1]_in[7] chanx[1][0]_out[8] sram[96]->outb sram[96]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[20], level=1, select_path_id=0. ***** -*****1***** -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -Xmux_1level_tapbuf_size2[21] grid[1][0]_pin[0][0][5] chany[0][1]_in[9] chanx[1][0]_out[10] sram[97]->outb sram[97]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[21], level=1, select_path_id=0. ***** -*****1***** -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -Xmux_1level_tapbuf_size2[22] grid[1][0]_pin[0][0][7] chany[0][1]_in[11] chanx[1][0]_out[12] sram[98]->outb sram[98]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[22], level=1, select_path_id=0. ***** -*****1***** -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -Xmux_1level_tapbuf_size2[23] grid[1][0]_pin[0][0][7] chany[0][1]_in[13] chanx[1][0]_out[14] sram[99]->outb sram[99]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[23], level=1, select_path_id=0. ***** -*****1***** -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -Xmux_1level_tapbuf_size2[24] grid[1][0]_pin[0][0][9] chany[0][1]_in[15] chanx[1][0]_out[16] sram[100]->outb sram[100]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[24], level=1, select_path_id=0. ***** -*****1***** -Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[100]->out) 0 -.nodeset V(sram[100]->outb) vsp -Xmux_1level_tapbuf_size2[25] grid[1][0]_pin[0][0][9] chany[0][1]_in[17] chanx[1][0]_out[18] sram[101]->outb sram[101]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[25], level=1, select_path_id=0. ***** -*****1***** -Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[101]->out) 0 -.nodeset V(sram[101]->outb) vsp -Xmux_1level_tapbuf_size2[26] grid[1][0]_pin[0][0][11] chany[0][1]_in[19] chanx[1][0]_out[20] sram[102]->outb sram[102]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[26], level=1, select_path_id=0. ***** -*****1***** -Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[102]->out) 0 -.nodeset V(sram[102]->outb) vsp -Xmux_1level_tapbuf_size2[27] grid[1][0]_pin[0][0][11] chany[0][1]_in[21] chanx[1][0]_out[22] sram[103]->outb sram[103]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[27], level=1, select_path_id=0. ***** -*****1***** -Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[103]->out) 0 -.nodeset V(sram[103]->outb) vsp -Xmux_1level_tapbuf_size2[28] grid[1][0]_pin[0][0][13] chany[0][1]_in[23] chanx[1][0]_out[24] sram[104]->outb sram[104]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[28], level=1, select_path_id=0. ***** -*****1***** -Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[104]->out) 0 -.nodeset V(sram[104]->outb) vsp -Xmux_1level_tapbuf_size2[29] grid[1][0]_pin[0][0][13] chany[0][1]_in[25] chanx[1][0]_out[26] sram[105]->outb sram[105]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[29], level=1, select_path_id=0. ***** -*****1***** -Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[105]->out) 0 -.nodeset V(sram[105]->outb) vsp -Xmux_1level_tapbuf_size2[30] grid[1][0]_pin[0][0][15] chany[0][1]_in[27] chanx[1][0]_out[28] sram[106]->outb sram[106]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[30], level=1, select_path_id=0. ***** -*****1***** -Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[106]->out) 0 -.nodeset V(sram[106]->outb) vsp -***** bottom side Multiplexers ***** -***** left side Multiplexers ***** -.eom diff --git a/examples/spice_test_example_1/subckt/sb_0_1.sp b/examples/spice_test_example_1/subckt/sb_0_1.sp deleted file mode 100644 index b59696244..000000000 --- a/examples/spice_test_example_1/subckt/sb_0_1.sp +++ /dev/null @@ -1,232 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Switch Block [0][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Switch Box[0][1] Sub-Circuit ***** -.subckt sb[0][1] -***** Inputs/outputs of top side ***** -+ -+ -+ ***** Inputs/outputs of right side ***** -+ chanx[1][1]_out[0] chanx[1][1]_in[1] chanx[1][1]_out[2] chanx[1][1]_in[3] chanx[1][1]_out[4] chanx[1][1]_in[5] chanx[1][1]_out[6] chanx[1][1]_in[7] chanx[1][1]_out[8] chanx[1][1]_in[9] chanx[1][1]_out[10] chanx[1][1]_in[11] chanx[1][1]_out[12] chanx[1][1]_in[13] chanx[1][1]_out[14] chanx[1][1]_in[15] chanx[1][1]_out[16] chanx[1][1]_in[17] chanx[1][1]_out[18] chanx[1][1]_in[19] chanx[1][1]_out[20] chanx[1][1]_in[21] chanx[1][1]_out[22] chanx[1][1]_in[23] chanx[1][1]_out[24] chanx[1][1]_in[25] chanx[1][1]_out[26] chanx[1][1]_in[27] chanx[1][1]_out[28] chanx[1][1]_in[29] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][4] -+ ***** Inputs/outputs of bottom side ***** -+ chany[0][1]_in[0] chany[0][1]_out[1] chany[0][1]_in[2] chany[0][1]_out[3] chany[0][1]_in[4] chany[0][1]_out[5] chany[0][1]_in[6] chany[0][1]_out[7] chany[0][1]_in[8] chany[0][1]_out[9] chany[0][1]_in[10] chany[0][1]_out[11] chany[0][1]_in[12] chany[0][1]_out[13] chany[0][1]_in[14] chany[0][1]_out[15] chany[0][1]_in[16] chany[0][1]_out[17] chany[0][1]_in[18] chany[0][1]_out[19] chany[0][1]_in[20] chany[0][1]_out[21] chany[0][1]_in[22] chany[0][1]_out[23] chany[0][1]_in[24] chany[0][1]_out[25] chany[0][1]_in[26] chany[0][1]_out[27] chany[0][1]_in[28] chany[0][1]_out[29] -+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] -+ ***** Inputs/outputs of left side ***** -+ -+ -+ svdd sgnd -***** top side Multiplexers ***** -***** right side Multiplexers ***** -Xmux_1level_tapbuf_size3[31] grid[1][1]_pin[0][0][4] grid[1][2]_pin[0][2][13] chany[0][1]_in[26] chanx[1][1]_out[0] sram[107]->outb sram[107]->out sram[108]->out sram[108]->outb sram[109]->out sram[109]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[31], level=1, select_path_id=0. ***** -*****100***** -Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[107]->out) 0 -.nodeset V(sram[107]->outb) vsp -Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[108]->out) 0 -.nodeset V(sram[108]->outb) vsp -Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[109]->out) 0 -.nodeset V(sram[109]->outb) vsp -Xmux_1level_tapbuf_size3[32] grid[1][1]_pin[0][0][4] grid[1][2]_pin[0][2][15] chany[0][1]_in[24] chanx[1][1]_out[2] sram[110]->outb sram[110]->out sram[111]->out sram[111]->outb sram[112]->out sram[112]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[32], level=1, select_path_id=0. ***** -*****100***** -Xsram[110] sram->in sram[110]->out sram[110]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[110]->out) 0 -.nodeset V(sram[110]->outb) vsp -Xsram[111] sram->in sram[111]->out sram[111]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[111]->out) 0 -.nodeset V(sram[111]->outb) vsp -Xsram[112] sram->in sram[112]->out sram[112]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[112]->out) 0 -.nodeset V(sram[112]->outb) vsp -Xmux_1level_tapbuf_size3[33] grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][15] chany[0][1]_in[22] chanx[1][1]_out[4] sram[113]->outb sram[113]->out sram[114]->out sram[114]->outb sram[115]->out sram[115]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[33], level=1, select_path_id=0. ***** -*****100***** -Xsram[113] sram->in sram[113]->out sram[113]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[113]->out) 0 -.nodeset V(sram[113]->outb) vsp -Xsram[114] sram->in sram[114]->out sram[114]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[114]->out) 0 -.nodeset V(sram[114]->outb) vsp -Xsram[115] sram->in sram[115]->out sram[115]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[115]->out) 0 -.nodeset V(sram[115]->outb) vsp -Xmux_1level_tapbuf_size2[34] grid[1][2]_pin[0][2][1] chany[0][1]_in[20] chanx[1][1]_out[6] sram[116]->outb sram[116]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[34], level=1, select_path_id=0. ***** -*****1***** -Xsram[116] sram->in sram[116]->out sram[116]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[116]->out) 0 -.nodeset V(sram[116]->outb) vsp -Xmux_1level_tapbuf_size2[35] grid[1][2]_pin[0][2][3] chany[0][1]_in[18] chanx[1][1]_out[8] sram[117]->outb sram[117]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[35], level=1, select_path_id=0. ***** -*****1***** -Xsram[117] sram->in sram[117]->out sram[117]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[117]->out) 0 -.nodeset V(sram[117]->outb) vsp -Xmux_1level_tapbuf_size2[36] grid[1][2]_pin[0][2][3] chany[0][1]_in[16] chanx[1][1]_out[10] sram[118]->outb sram[118]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[36], level=1, select_path_id=0. ***** -*****1***** -Xsram[118] sram->in sram[118]->out sram[118]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[118]->out) 0 -.nodeset V(sram[118]->outb) vsp -Xmux_1level_tapbuf_size2[37] grid[1][2]_pin[0][2][5] chany[0][1]_in[14] chanx[1][1]_out[12] sram[119]->outb sram[119]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[37], level=1, select_path_id=0. ***** -*****1***** -Xsram[119] sram->in sram[119]->out sram[119]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[119]->out) 0 -.nodeset V(sram[119]->outb) vsp -Xmux_1level_tapbuf_size2[38] grid[1][2]_pin[0][2][5] chany[0][1]_in[12] chanx[1][1]_out[14] sram[120]->outb sram[120]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[38], level=1, select_path_id=0. ***** -*****1***** -Xsram[120] sram->in sram[120]->out sram[120]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[120]->out) 0 -.nodeset V(sram[120]->outb) vsp -Xmux_1level_tapbuf_size2[39] grid[1][2]_pin[0][2][7] chany[0][1]_in[10] chanx[1][1]_out[16] sram[121]->outb sram[121]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[39], level=1, select_path_id=0. ***** -*****1***** -Xsram[121] sram->in sram[121]->out sram[121]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[121]->out) 0 -.nodeset V(sram[121]->outb) vsp -Xmux_1level_tapbuf_size2[40] grid[1][2]_pin[0][2][7] chany[0][1]_in[8] chanx[1][1]_out[18] sram[122]->outb sram[122]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[40], level=1, select_path_id=0. ***** -*****1***** -Xsram[122] sram->in sram[122]->out sram[122]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[122]->out) 0 -.nodeset V(sram[122]->outb) vsp -Xmux_1level_tapbuf_size2[41] grid[1][2]_pin[0][2][9] chany[0][1]_in[6] chanx[1][1]_out[20] sram[123]->outb sram[123]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[41], level=1, select_path_id=0. ***** -*****1***** -Xsram[123] sram->in sram[123]->out sram[123]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[123]->out) 0 -.nodeset V(sram[123]->outb) vsp -Xmux_1level_tapbuf_size2[42] grid[1][2]_pin[0][2][9] chany[0][1]_in[4] chanx[1][1]_out[22] sram[124]->outb sram[124]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[42], level=1, select_path_id=0. ***** -*****1***** -Xsram[124] sram->in sram[124]->out sram[124]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[124]->out) 0 -.nodeset V(sram[124]->outb) vsp -Xmux_1level_tapbuf_size2[43] grid[1][2]_pin[0][2][11] chany[0][1]_in[2] chanx[1][1]_out[24] sram[125]->outb sram[125]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[43], level=1, select_path_id=0. ***** -*****1***** -Xsram[125] sram->in sram[125]->out sram[125]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[125]->out) 0 -.nodeset V(sram[125]->outb) vsp -Xmux_1level_tapbuf_size2[44] grid[1][2]_pin[0][2][11] chany[0][1]_in[0] chanx[1][1]_out[26] sram[126]->outb sram[126]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[44], level=1, select_path_id=0. ***** -*****1***** -Xsram[126] sram->in sram[126]->out sram[126]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[126]->out) 0 -.nodeset V(sram[126]->outb) vsp -Xmux_1level_tapbuf_size2[45] grid[1][2]_pin[0][2][13] chany[0][1]_in[28] chanx[1][1]_out[28] sram[127]->outb sram[127]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[45], level=1, select_path_id=0. ***** -*****1***** -Xsram[127] sram->in sram[127]->out sram[127]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[127]->out) 0 -.nodeset V(sram[127]->outb) vsp -***** bottom side Multiplexers ***** -Xmux_1level_tapbuf_size3[46] grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][15] chanx[1][1]_in[27] chany[0][1]_out[1] sram[128]->outb sram[128]->out sram[129]->out sram[129]->outb sram[130]->out sram[130]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[46], level=1, select_path_id=0. ***** -*****100***** -Xsram[128] sram->in sram[128]->out sram[128]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[128]->out) 0 -.nodeset V(sram[128]->outb) vsp -Xsram[129] sram->in sram[129]->out sram[129]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[129]->out) 0 -.nodeset V(sram[129]->outb) vsp -Xsram[130] sram->in sram[130]->out sram[130]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[130]->out) 0 -.nodeset V(sram[130]->outb) vsp -Xmux_1level_tapbuf_size2[47] grid[0][1]_pin[0][1][1] chanx[1][1]_in[25] chany[0][1]_out[3] sram[131]->outb sram[131]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[47], level=1, select_path_id=0. ***** -*****1***** -Xsram[131] sram->in sram[131]->out sram[131]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[131]->out) 0 -.nodeset V(sram[131]->outb) vsp -Xmux_1level_tapbuf_size2[48] grid[0][1]_pin[0][1][3] chanx[1][1]_in[23] chany[0][1]_out[5] sram[132]->outb sram[132]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[48], level=1, select_path_id=0. ***** -*****1***** -Xsram[132] sram->in sram[132]->out sram[132]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[132]->out) 0 -.nodeset V(sram[132]->outb) vsp -Xmux_1level_tapbuf_size2[49] grid[0][1]_pin[0][1][3] chanx[1][1]_in[21] chany[0][1]_out[7] sram[133]->outb sram[133]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[49], level=1, select_path_id=0. ***** -*****1***** -Xsram[133] sram->in sram[133]->out sram[133]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[133]->out) 0 -.nodeset V(sram[133]->outb) vsp -Xmux_1level_tapbuf_size2[50] grid[0][1]_pin[0][1][5] chanx[1][1]_in[19] chany[0][1]_out[9] sram[134]->outb sram[134]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[50], level=1, select_path_id=0. ***** -*****1***** -Xsram[134] sram->in sram[134]->out sram[134]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[134]->out) 0 -.nodeset V(sram[134]->outb) vsp -Xmux_1level_tapbuf_size2[51] grid[0][1]_pin[0][1][5] chanx[1][1]_in[17] chany[0][1]_out[11] sram[135]->outb sram[135]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[51], level=1, select_path_id=0. ***** -*****1***** -Xsram[135] sram->in sram[135]->out sram[135]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[135]->out) 0 -.nodeset V(sram[135]->outb) vsp -Xmux_1level_tapbuf_size2[52] grid[0][1]_pin[0][1][7] chanx[1][1]_in[15] chany[0][1]_out[13] sram[136]->outb sram[136]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[52], level=1, select_path_id=0. ***** -*****1***** -Xsram[136] sram->in sram[136]->out sram[136]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[136]->out) 0 -.nodeset V(sram[136]->outb) vsp -Xmux_1level_tapbuf_size2[53] grid[0][1]_pin[0][1][7] chanx[1][1]_in[13] chany[0][1]_out[15] sram[137]->outb sram[137]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[53], level=1, select_path_id=0. ***** -*****1***** -Xsram[137] sram->in sram[137]->out sram[137]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[137]->out) 0 -.nodeset V(sram[137]->outb) vsp -Xmux_1level_tapbuf_size2[54] grid[0][1]_pin[0][1][9] chanx[1][1]_in[11] chany[0][1]_out[17] sram[138]->outb sram[138]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[54], level=1, select_path_id=0. ***** -*****1***** -Xsram[138] sram->in sram[138]->out sram[138]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[138]->out) 0 -.nodeset V(sram[138]->outb) vsp -Xmux_1level_tapbuf_size2[55] grid[0][1]_pin[0][1][9] chanx[1][1]_in[9] chany[0][1]_out[19] sram[139]->outb sram[139]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[55], level=1, select_path_id=0. ***** -*****1***** -Xsram[139] sram->in sram[139]->out sram[139]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[139]->out) 0 -.nodeset V(sram[139]->outb) vsp -Xmux_1level_tapbuf_size2[56] grid[0][1]_pin[0][1][11] chanx[1][1]_in[7] chany[0][1]_out[21] sram[140]->outb sram[140]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[56], level=1, select_path_id=0. ***** -*****1***** -Xsram[140] sram->in sram[140]->out sram[140]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[140]->out) 0 -.nodeset V(sram[140]->outb) vsp -Xmux_1level_tapbuf_size2[57] grid[0][1]_pin[0][1][11] chanx[1][1]_in[5] chany[0][1]_out[23] sram[141]->outb sram[141]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[57], level=1, select_path_id=0. ***** -*****1***** -Xsram[141] sram->in sram[141]->out sram[141]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[141]->out) 0 -.nodeset V(sram[141]->outb) vsp -Xmux_1level_tapbuf_size2[58] grid[0][1]_pin[0][1][13] chanx[1][1]_in[3] chany[0][1]_out[25] sram[142]->outb sram[142]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[58], level=1, select_path_id=0. ***** -*****1***** -Xsram[142] sram->in sram[142]->out sram[142]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[142]->out) 0 -.nodeset V(sram[142]->outb) vsp -Xmux_1level_tapbuf_size2[59] grid[0][1]_pin[0][1][13] chanx[1][1]_in[1] chany[0][1]_out[27] sram[143]->out sram[143]->outb svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[59], level=1, select_path_id=1. ***** -*****0***** -Xsram[143] sram->in sram[143]->out sram[143]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[143]->out) 0 -.nodeset V(sram[143]->outb) vsp -Xmux_1level_tapbuf_size2[60] grid[0][1]_pin[0][1][15] chanx[1][1]_in[29] chany[0][1]_out[29] sram[144]->outb sram[144]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[60], level=1, select_path_id=0. ***** -*****1***** -Xsram[144] sram->in sram[144]->out sram[144]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[144]->out) 0 -.nodeset V(sram[144]->outb) vsp -***** left side Multiplexers ***** -.eom diff --git a/examples/spice_test_example_1/subckt/sb_1_0.sp b/examples/spice_test_example_1/subckt/sb_1_0.sp deleted file mode 100644 index 07d8a8f4b..000000000 --- a/examples/spice_test_example_1/subckt/sb_1_0.sp +++ /dev/null @@ -1,220 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Switch Block [1][0] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Switch Box[1][0] Sub-Circuit ***** -.subckt sb[1][0] -***** Inputs/outputs of top side ***** -+ chany[1][1]_out[0] chany[1][1]_in[1] chany[1][1]_out[2] chany[1][1]_in[3] chany[1][1]_out[4] chany[1][1]_in[5] chany[1][1]_out[6] chany[1][1]_in[7] chany[1][1]_out[8] chany[1][1]_in[9] chany[1][1]_out[10] chany[1][1]_in[11] chany[1][1]_out[12] chany[1][1]_in[13] chany[1][1]_out[14] chany[1][1]_in[15] chany[1][1]_out[16] chany[1][1]_in[17] chany[1][1]_out[18] chany[1][1]_in[19] chany[1][1]_out[20] chany[1][1]_in[21] chany[1][1]_out[22] chany[1][1]_in[23] chany[1][1]_out[24] chany[1][1]_in[25] chany[1][1]_out[26] chany[1][1]_in[27] chany[1][1]_out[28] chany[1][1]_in[29] -+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] -+ ***** Inputs/outputs of right side ***** -+ -+ -+ ***** Inputs/outputs of bottom side ***** -+ -+ -+ ***** Inputs/outputs of left side ***** -+ chanx[1][0]_in[0] chanx[1][0]_out[1] chanx[1][0]_in[2] chanx[1][0]_out[3] chanx[1][0]_in[4] chanx[1][0]_out[5] chanx[1][0]_in[6] chanx[1][0]_out[7] chanx[1][0]_in[8] chanx[1][0]_out[9] chanx[1][0]_in[10] chanx[1][0]_out[11] chanx[1][0]_in[12] chanx[1][0]_out[13] chanx[1][0]_in[14] chanx[1][0]_out[15] chanx[1][0]_in[16] chanx[1][0]_out[17] chanx[1][0]_in[18] chanx[1][0]_out[19] chanx[1][0]_in[20] chanx[1][0]_out[21] chanx[1][0]_in[22] chanx[1][0]_out[23] chanx[1][0]_in[24] chanx[1][0]_out[25] chanx[1][0]_in[26] chanx[1][0]_out[27] chanx[1][0]_in[28] chanx[1][0]_out[29] -+ grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ svdd sgnd -***** top side Multiplexers ***** -Xmux_1level_tapbuf_size3[61] grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][15] chanx[1][0]_in[0] chany[1][1]_out[0] sram[145]->outb sram[145]->out sram[146]->out sram[146]->outb sram[147]->out sram[147]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[61], level=1, select_path_id=0. ***** -*****100***** -Xsram[145] sram->in sram[145]->out sram[145]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[145]->out) 0 -.nodeset V(sram[145]->outb) vsp -Xsram[146] sram->in sram[146]->out sram[146]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[146]->out) 0 -.nodeset V(sram[146]->outb) vsp -Xsram[147] sram->in sram[147]->out sram[147]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[147]->out) 0 -.nodeset V(sram[147]->outb) vsp -Xmux_1level_tapbuf_size2[62] grid[2][1]_pin[0][3][1] chanx[1][0]_in[28] chany[1][1]_out[2] sram[148]->outb sram[148]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[62], level=1, select_path_id=0. ***** -*****1***** -Xsram[148] sram->in sram[148]->out sram[148]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[148]->out) 0 -.nodeset V(sram[148]->outb) vsp -Xmux_1level_tapbuf_size2[63] grid[2][1]_pin[0][3][3] chanx[1][0]_in[26] chany[1][1]_out[4] sram[149]->outb sram[149]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[63], level=1, select_path_id=0. ***** -*****1***** -Xsram[149] sram->in sram[149]->out sram[149]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[149]->out) 0 -.nodeset V(sram[149]->outb) vsp -Xmux_1level_tapbuf_size2[64] grid[2][1]_pin[0][3][3] chanx[1][0]_in[24] chany[1][1]_out[6] sram[150]->outb sram[150]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[64], level=1, select_path_id=0. ***** -*****1***** -Xsram[150] sram->in sram[150]->out sram[150]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[150]->out) 0 -.nodeset V(sram[150]->outb) vsp -Xmux_1level_tapbuf_size2[65] grid[2][1]_pin[0][3][5] chanx[1][0]_in[22] chany[1][1]_out[8] sram[151]->outb sram[151]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[65], level=1, select_path_id=0. ***** -*****1***** -Xsram[151] sram->in sram[151]->out sram[151]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[151]->out) 0 -.nodeset V(sram[151]->outb) vsp -Xmux_1level_tapbuf_size2[66] grid[2][1]_pin[0][3][5] chanx[1][0]_in[20] chany[1][1]_out[10] sram[152]->outb sram[152]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[66], level=1, select_path_id=0. ***** -*****1***** -Xsram[152] sram->in sram[152]->out sram[152]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[152]->out) 0 -.nodeset V(sram[152]->outb) vsp -Xmux_1level_tapbuf_size2[67] grid[2][1]_pin[0][3][7] chanx[1][0]_in[18] chany[1][1]_out[12] sram[153]->outb sram[153]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[67], level=1, select_path_id=0. ***** -*****1***** -Xsram[153] sram->in sram[153]->out sram[153]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[153]->out) 0 -.nodeset V(sram[153]->outb) vsp -Xmux_1level_tapbuf_size2[68] grid[2][1]_pin[0][3][7] chanx[1][0]_in[16] chany[1][1]_out[14] sram[154]->outb sram[154]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[68], level=1, select_path_id=0. ***** -*****1***** -Xsram[154] sram->in sram[154]->out sram[154]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[154]->out) 0 -.nodeset V(sram[154]->outb) vsp -Xmux_1level_tapbuf_size2[69] grid[2][1]_pin[0][3][9] chanx[1][0]_in[14] chany[1][1]_out[16] sram[155]->outb sram[155]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[69], level=1, select_path_id=0. ***** -*****1***** -Xsram[155] sram->in sram[155]->out sram[155]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[155]->out) 0 -.nodeset V(sram[155]->outb) vsp -Xmux_1level_tapbuf_size2[70] grid[2][1]_pin[0][3][9] chanx[1][0]_in[12] chany[1][1]_out[18] sram[156]->outb sram[156]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[70], level=1, select_path_id=0. ***** -*****1***** -Xsram[156] sram->in sram[156]->out sram[156]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[156]->out) 0 -.nodeset V(sram[156]->outb) vsp -Xmux_1level_tapbuf_size2[71] grid[2][1]_pin[0][3][11] chanx[1][0]_in[10] chany[1][1]_out[20] sram[157]->outb sram[157]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[71], level=1, select_path_id=0. ***** -*****1***** -Xsram[157] sram->in sram[157]->out sram[157]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[157]->out) 0 -.nodeset V(sram[157]->outb) vsp -Xmux_1level_tapbuf_size2[72] grid[2][1]_pin[0][3][11] chanx[1][0]_in[8] chany[1][1]_out[22] sram[158]->outb sram[158]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[72], level=1, select_path_id=0. ***** -*****1***** -Xsram[158] sram->in sram[158]->out sram[158]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[158]->out) 0 -.nodeset V(sram[158]->outb) vsp -Xmux_1level_tapbuf_size2[73] grid[2][1]_pin[0][3][13] chanx[1][0]_in[6] chany[1][1]_out[24] sram[159]->outb sram[159]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[73], level=1, select_path_id=0. ***** -*****1***** -Xsram[159] sram->in sram[159]->out sram[159]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[159]->out) 0 -.nodeset V(sram[159]->outb) vsp -Xmux_1level_tapbuf_size2[74] grid[2][1]_pin[0][3][13] chanx[1][0]_in[4] chany[1][1]_out[26] sram[160]->outb sram[160]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[74], level=1, select_path_id=0. ***** -*****1***** -Xsram[160] sram->in sram[160]->out sram[160]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[160]->out) 0 -.nodeset V(sram[160]->outb) vsp -Xmux_1level_tapbuf_size2[75] grid[2][1]_pin[0][3][15] chanx[1][0]_in[2] chany[1][1]_out[28] sram[161]->outb sram[161]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[75], level=1, select_path_id=0. ***** -*****1***** -Xsram[161] sram->in sram[161]->out sram[161]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[161]->out) 0 -.nodeset V(sram[161]->outb) vsp -***** right side Multiplexers ***** -***** bottom side Multiplexers ***** -***** left side Multiplexers ***** -Xmux_1level_tapbuf_size3[76] grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][15] chany[1][1]_in[1] chanx[1][0]_out[1] sram[162]->outb sram[162]->out sram[163]->out sram[163]->outb sram[164]->out sram[164]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[76], level=1, select_path_id=0. ***** -*****100***** -Xsram[162] sram->in sram[162]->out sram[162]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[162]->out) 0 -.nodeset V(sram[162]->outb) vsp -Xsram[163] sram->in sram[163]->out sram[163]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[163]->out) 0 -.nodeset V(sram[163]->outb) vsp -Xsram[164] sram->in sram[164]->out sram[164]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[164]->out) 0 -.nodeset V(sram[164]->outb) vsp -Xmux_1level_tapbuf_size2[77] grid[1][0]_pin[0][0][1] chany[1][1]_in[29] chanx[1][0]_out[3] sram[165]->outb sram[165]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[77], level=1, select_path_id=0. ***** -*****1***** -Xsram[165] sram->in sram[165]->out sram[165]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[165]->out) 0 -.nodeset V(sram[165]->outb) vsp -Xmux_1level_tapbuf_size2[78] grid[1][0]_pin[0][0][3] chany[1][1]_in[27] chanx[1][0]_out[5] sram[166]->outb sram[166]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[78], level=1, select_path_id=0. ***** -*****1***** -Xsram[166] sram->in sram[166]->out sram[166]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[166]->out) 0 -.nodeset V(sram[166]->outb) vsp -Xmux_1level_tapbuf_size2[79] grid[1][0]_pin[0][0][3] chany[1][1]_in[25] chanx[1][0]_out[7] sram[167]->outb sram[167]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[79], level=1, select_path_id=0. ***** -*****1***** -Xsram[167] sram->in sram[167]->out sram[167]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[167]->out) 0 -.nodeset V(sram[167]->outb) vsp -Xmux_1level_tapbuf_size2[80] grid[1][0]_pin[0][0][5] chany[1][1]_in[23] chanx[1][0]_out[9] sram[168]->outb sram[168]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[80], level=1, select_path_id=0. ***** -*****1***** -Xsram[168] sram->in sram[168]->out sram[168]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[168]->out) 0 -.nodeset V(sram[168]->outb) vsp -Xmux_1level_tapbuf_size2[81] grid[1][0]_pin[0][0][5] chany[1][1]_in[21] chanx[1][0]_out[11] sram[169]->outb sram[169]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[81], level=1, select_path_id=0. ***** -*****1***** -Xsram[169] sram->in sram[169]->out sram[169]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[169]->out) 0 -.nodeset V(sram[169]->outb) vsp -Xmux_1level_tapbuf_size2[82] grid[1][0]_pin[0][0][7] chany[1][1]_in[19] chanx[1][0]_out[13] sram[170]->outb sram[170]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[82], level=1, select_path_id=0. ***** -*****1***** -Xsram[170] sram->in sram[170]->out sram[170]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[170]->out) 0 -.nodeset V(sram[170]->outb) vsp -Xmux_1level_tapbuf_size2[83] grid[1][0]_pin[0][0][7] chany[1][1]_in[17] chanx[1][0]_out[15] sram[171]->outb sram[171]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[83], level=1, select_path_id=0. ***** -*****1***** -Xsram[171] sram->in sram[171]->out sram[171]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[171]->out) 0 -.nodeset V(sram[171]->outb) vsp -Xmux_1level_tapbuf_size2[84] grid[1][0]_pin[0][0][9] chany[1][1]_in[15] chanx[1][0]_out[17] sram[172]->outb sram[172]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[84], level=1, select_path_id=0. ***** -*****1***** -Xsram[172] sram->in sram[172]->out sram[172]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[172]->out) 0 -.nodeset V(sram[172]->outb) vsp -Xmux_1level_tapbuf_size2[85] grid[1][0]_pin[0][0][9] chany[1][1]_in[13] chanx[1][0]_out[19] sram[173]->outb sram[173]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[85], level=1, select_path_id=0. ***** -*****1***** -Xsram[173] sram->in sram[173]->out sram[173]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[173]->out) 0 -.nodeset V(sram[173]->outb) vsp -Xmux_1level_tapbuf_size2[86] grid[1][0]_pin[0][0][11] chany[1][1]_in[11] chanx[1][0]_out[21] sram[174]->outb sram[174]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[86], level=1, select_path_id=0. ***** -*****1***** -Xsram[174] sram->in sram[174]->out sram[174]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[174]->out) 0 -.nodeset V(sram[174]->outb) vsp -Xmux_1level_tapbuf_size2[87] grid[1][0]_pin[0][0][11] chany[1][1]_in[9] chanx[1][0]_out[23] sram[175]->outb sram[175]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[87], level=1, select_path_id=0. ***** -*****1***** -Xsram[175] sram->in sram[175]->out sram[175]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[175]->out) 0 -.nodeset V(sram[175]->outb) vsp -Xmux_1level_tapbuf_size2[88] grid[1][0]_pin[0][0][13] chany[1][1]_in[7] chanx[1][0]_out[25] sram[176]->outb sram[176]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[88], level=1, select_path_id=0. ***** -*****1***** -Xsram[176] sram->in sram[176]->out sram[176]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[176]->out) 0 -.nodeset V(sram[176]->outb) vsp -Xmux_1level_tapbuf_size2[89] grid[1][0]_pin[0][0][13] chany[1][1]_in[5] chanx[1][0]_out[27] sram[177]->outb sram[177]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[89], level=1, select_path_id=0. ***** -*****1***** -Xsram[177] sram->in sram[177]->out sram[177]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[177]->out) 0 -.nodeset V(sram[177]->outb) vsp -Xmux_1level_tapbuf_size2[90] grid[1][0]_pin[0][0][15] chany[1][1]_in[3] chanx[1][0]_out[29] sram[178]->outb sram[178]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[90], level=1, select_path_id=0. ***** -*****1***** -Xsram[178] sram->in sram[178]->out sram[178]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[178]->out) 0 -.nodeset V(sram[178]->outb) vsp -.eom diff --git a/examples/spice_test_example_1/subckt/sb_1_1.sp b/examples/spice_test_example_1/subckt/sb_1_1.sp deleted file mode 100644 index 7a4d362a3..000000000 --- a/examples/spice_test_example_1/subckt/sb_1_1.sp +++ /dev/null @@ -1,232 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Switch Block [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -***** Switch Box[1][1] Sub-Circuit ***** -.subckt sb[1][1] -***** Inputs/outputs of top side ***** -+ -+ -+ ***** Inputs/outputs of right side ***** -+ -+ -+ ***** Inputs/outputs of bottom side ***** -+ chany[1][1]_in[0] chany[1][1]_out[1] chany[1][1]_in[2] chany[1][1]_out[3] chany[1][1]_in[4] chany[1][1]_out[5] chany[1][1]_in[6] chany[1][1]_out[7] chany[1][1]_in[8] chany[1][1]_out[9] chany[1][1]_in[10] chany[1][1]_out[11] chany[1][1]_in[12] chany[1][1]_out[13] chany[1][1]_in[14] chany[1][1]_out[15] chany[1][1]_in[16] chany[1][1]_out[17] chany[1][1]_in[18] chany[1][1]_out[19] chany[1][1]_in[20] chany[1][1]_out[21] chany[1][1]_in[22] chany[1][1]_out[23] chany[1][1]_in[24] chany[1][1]_out[25] chany[1][1]_in[26] chany[1][1]_out[27] chany[1][1]_in[28] chany[1][1]_out[29] -+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] -+ ***** Inputs/outputs of left side ***** -+ chanx[1][1]_in[0] chanx[1][1]_out[1] chanx[1][1]_in[2] chanx[1][1]_out[3] chanx[1][1]_in[4] chanx[1][1]_out[5] chanx[1][1]_in[6] chanx[1][1]_out[7] chanx[1][1]_in[8] chanx[1][1]_out[9] chanx[1][1]_in[10] chanx[1][1]_out[11] chanx[1][1]_in[12] chanx[1][1]_out[13] chanx[1][1]_in[14] chanx[1][1]_out[15] chanx[1][1]_in[16] chanx[1][1]_out[17] chanx[1][1]_in[18] chanx[1][1]_out[19] chanx[1][1]_in[20] chanx[1][1]_out[21] chanx[1][1]_in[22] chanx[1][1]_out[23] chanx[1][1]_in[24] chanx[1][1]_out[25] chanx[1][1]_in[26] chanx[1][1]_out[27] chanx[1][1]_in[28] chanx[1][1]_out[29] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][4] -+ svdd sgnd -***** top side Multiplexers ***** -***** right side Multiplexers ***** -***** bottom side Multiplexers ***** -Xmux_1level_tapbuf_size3[91] grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][15] chanx[1][1]_in[2] chany[1][1]_out[1] sram[179]->outb sram[179]->out sram[180]->out sram[180]->outb sram[181]->out sram[181]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[91], level=1, select_path_id=0. ***** -*****100***** -Xsram[179] sram->in sram[179]->out sram[179]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[179]->out) 0 -.nodeset V(sram[179]->outb) vsp -Xsram[180] sram->in sram[180]->out sram[180]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[180]->out) 0 -.nodeset V(sram[180]->outb) vsp -Xsram[181] sram->in sram[181]->out sram[181]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[181]->out) 0 -.nodeset V(sram[181]->outb) vsp -Xmux_1level_tapbuf_size2[92] grid[2][1]_pin[0][3][1] chanx[1][1]_in[4] chany[1][1]_out[3] sram[182]->outb sram[182]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[92], level=1, select_path_id=0. ***** -*****1***** -Xsram[182] sram->in sram[182]->out sram[182]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[182]->out) 0 -.nodeset V(sram[182]->outb) vsp -Xmux_1level_tapbuf_size2[93] grid[2][1]_pin[0][3][3] chanx[1][1]_in[6] chany[1][1]_out[5] sram[183]->outb sram[183]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[93], level=1, select_path_id=0. ***** -*****1***** -Xsram[183] sram->in sram[183]->out sram[183]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[183]->out) 0 -.nodeset V(sram[183]->outb) vsp -Xmux_1level_tapbuf_size2[94] grid[2][1]_pin[0][3][3] chanx[1][1]_in[8] chany[1][1]_out[7] sram[184]->outb sram[184]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[94], level=1, select_path_id=0. ***** -*****1***** -Xsram[184] sram->in sram[184]->out sram[184]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[184]->out) 0 -.nodeset V(sram[184]->outb) vsp -Xmux_1level_tapbuf_size2[95] grid[2][1]_pin[0][3][5] chanx[1][1]_in[10] chany[1][1]_out[9] sram[185]->outb sram[185]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[95], level=1, select_path_id=0. ***** -*****1***** -Xsram[185] sram->in sram[185]->out sram[185]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[185]->out) 0 -.nodeset V(sram[185]->outb) vsp -Xmux_1level_tapbuf_size2[96] grid[2][1]_pin[0][3][5] chanx[1][1]_in[12] chany[1][1]_out[11] sram[186]->outb sram[186]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[96], level=1, select_path_id=0. ***** -*****1***** -Xsram[186] sram->in sram[186]->out sram[186]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[186]->out) 0 -.nodeset V(sram[186]->outb) vsp -Xmux_1level_tapbuf_size2[97] grid[2][1]_pin[0][3][7] chanx[1][1]_in[14] chany[1][1]_out[13] sram[187]->outb sram[187]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[97], level=1, select_path_id=0. ***** -*****1***** -Xsram[187] sram->in sram[187]->out sram[187]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[187]->out) 0 -.nodeset V(sram[187]->outb) vsp -Xmux_1level_tapbuf_size2[98] grid[2][1]_pin[0][3][7] chanx[1][1]_in[16] chany[1][1]_out[15] sram[188]->outb sram[188]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[98], level=1, select_path_id=0. ***** -*****1***** -Xsram[188] sram->in sram[188]->out sram[188]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[188]->out) 0 -.nodeset V(sram[188]->outb) vsp -Xmux_1level_tapbuf_size2[99] grid[2][1]_pin[0][3][9] chanx[1][1]_in[18] chany[1][1]_out[17] sram[189]->outb sram[189]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[99], level=1, select_path_id=0. ***** -*****1***** -Xsram[189] sram->in sram[189]->out sram[189]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[189]->out) 0 -.nodeset V(sram[189]->outb) vsp -Xmux_1level_tapbuf_size2[100] grid[2][1]_pin[0][3][9] chanx[1][1]_in[20] chany[1][1]_out[19] sram[190]->outb sram[190]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[100], level=1, select_path_id=0. ***** -*****1***** -Xsram[190] sram->in sram[190]->out sram[190]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[190]->out) 0 -.nodeset V(sram[190]->outb) vsp -Xmux_1level_tapbuf_size2[101] grid[2][1]_pin[0][3][11] chanx[1][1]_in[22] chany[1][1]_out[21] sram[191]->outb sram[191]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[101], level=1, select_path_id=0. ***** -*****1***** -Xsram[191] sram->in sram[191]->out sram[191]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[191]->out) 0 -.nodeset V(sram[191]->outb) vsp -Xmux_1level_tapbuf_size2[102] grid[2][1]_pin[0][3][11] chanx[1][1]_in[24] chany[1][1]_out[23] sram[192]->outb sram[192]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[102], level=1, select_path_id=0. ***** -*****1***** -Xsram[192] sram->in sram[192]->out sram[192]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[192]->out) 0 -.nodeset V(sram[192]->outb) vsp -Xmux_1level_tapbuf_size2[103] grid[2][1]_pin[0][3][13] chanx[1][1]_in[26] chany[1][1]_out[25] sram[193]->outb sram[193]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[103], level=1, select_path_id=0. ***** -*****1***** -Xsram[193] sram->in sram[193]->out sram[193]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[193]->out) 0 -.nodeset V(sram[193]->outb) vsp -Xmux_1level_tapbuf_size2[104] grid[2][1]_pin[0][3][13] chanx[1][1]_in[28] chany[1][1]_out[27] sram[194]->outb sram[194]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[104], level=1, select_path_id=0. ***** -*****1***** -Xsram[194] sram->in sram[194]->out sram[194]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[194]->out) 0 -.nodeset V(sram[194]->outb) vsp -Xmux_1level_tapbuf_size2[105] grid[2][1]_pin[0][3][15] chanx[1][1]_in[0] chany[1][1]_out[29] sram[195]->outb sram[195]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[105], level=1, select_path_id=0. ***** -*****1***** -Xsram[195] sram->in sram[195]->out sram[195]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[195]->out) 0 -.nodeset V(sram[195]->outb) vsp -***** left side Multiplexers ***** -Xmux_1level_tapbuf_size3[106] grid[1][1]_pin[0][0][4] grid[1][2]_pin[0][2][13] chany[1][1]_in[28] chanx[1][1]_out[1] sram[196]->out sram[196]->outb sram[197]->outb sram[197]->out sram[198]->out sram[198]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[106], level=1, select_path_id=1. ***** -*****010***** -Xsram[196] sram->in sram[196]->out sram[196]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[196]->out) 0 -.nodeset V(sram[196]->outb) vsp -Xsram[197] sram->in sram[197]->out sram[197]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[197]->out) 0 -.nodeset V(sram[197]->outb) vsp -Xsram[198] sram->in sram[198]->out sram[198]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[198]->out) 0 -.nodeset V(sram[198]->outb) vsp -Xmux_1level_tapbuf_size3[107] grid[1][1]_pin[0][0][4] grid[1][2]_pin[0][2][15] chany[1][1]_in[0] chanx[1][1]_out[3] sram[199]->outb sram[199]->out sram[200]->out sram[200]->outb sram[201]->out sram[201]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[107], level=1, select_path_id=0. ***** -*****100***** -Xsram[199] sram->in sram[199]->out sram[199]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[199]->out) 0 -.nodeset V(sram[199]->outb) vsp -Xsram[200] sram->in sram[200]->out sram[200]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[200]->out) 0 -.nodeset V(sram[200]->outb) vsp -Xsram[201] sram->in sram[201]->out sram[201]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[201]->out) 0 -.nodeset V(sram[201]->outb) vsp -Xmux_1level_tapbuf_size3[108] grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][15] chany[1][1]_in[2] chanx[1][1]_out[5] sram[202]->outb sram[202]->out sram[203]->out sram[203]->outb sram[204]->out sram[204]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[108], level=1, select_path_id=0. ***** -*****100***** -Xsram[202] sram->in sram[202]->out sram[202]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[202]->out) 0 -.nodeset V(sram[202]->outb) vsp -Xsram[203] sram->in sram[203]->out sram[203]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[203]->out) 0 -.nodeset V(sram[203]->outb) vsp -Xsram[204] sram->in sram[204]->out sram[204]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[204]->out) 0 -.nodeset V(sram[204]->outb) vsp -Xmux_1level_tapbuf_size2[109] grid[1][2]_pin[0][2][1] chany[1][1]_in[4] chanx[1][1]_out[7] sram[205]->outb sram[205]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[109], level=1, select_path_id=0. ***** -*****1***** -Xsram[205] sram->in sram[205]->out sram[205]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[205]->out) 0 -.nodeset V(sram[205]->outb) vsp -Xmux_1level_tapbuf_size2[110] grid[1][2]_pin[0][2][3] chany[1][1]_in[6] chanx[1][1]_out[9] sram[206]->outb sram[206]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[110], level=1, select_path_id=0. ***** -*****1***** -Xsram[206] sram->in sram[206]->out sram[206]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[206]->out) 0 -.nodeset V(sram[206]->outb) vsp -Xmux_1level_tapbuf_size2[111] grid[1][2]_pin[0][2][3] chany[1][1]_in[8] chanx[1][1]_out[11] sram[207]->outb sram[207]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[111], level=1, select_path_id=0. ***** -*****1***** -Xsram[207] sram->in sram[207]->out sram[207]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[207]->out) 0 -.nodeset V(sram[207]->outb) vsp -Xmux_1level_tapbuf_size2[112] grid[1][2]_pin[0][2][5] chany[1][1]_in[10] chanx[1][1]_out[13] sram[208]->outb sram[208]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[112], level=1, select_path_id=0. ***** -*****1***** -Xsram[208] sram->in sram[208]->out sram[208]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[208]->out) 0 -.nodeset V(sram[208]->outb) vsp -Xmux_1level_tapbuf_size2[113] grid[1][2]_pin[0][2][5] chany[1][1]_in[12] chanx[1][1]_out[15] sram[209]->outb sram[209]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[113], level=1, select_path_id=0. ***** -*****1***** -Xsram[209] sram->in sram[209]->out sram[209]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[209]->out) 0 -.nodeset V(sram[209]->outb) vsp -Xmux_1level_tapbuf_size2[114] grid[1][2]_pin[0][2][7] chany[1][1]_in[14] chanx[1][1]_out[17] sram[210]->outb sram[210]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[114], level=1, select_path_id=0. ***** -*****1***** -Xsram[210] sram->in sram[210]->out sram[210]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[210]->out) 0 -.nodeset V(sram[210]->outb) vsp -Xmux_1level_tapbuf_size2[115] grid[1][2]_pin[0][2][7] chany[1][1]_in[16] chanx[1][1]_out[19] sram[211]->outb sram[211]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[115], level=1, select_path_id=0. ***** -*****1***** -Xsram[211] sram->in sram[211]->out sram[211]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[211]->out) 0 -.nodeset V(sram[211]->outb) vsp -Xmux_1level_tapbuf_size2[116] grid[1][2]_pin[0][2][9] chany[1][1]_in[18] chanx[1][1]_out[21] sram[212]->outb sram[212]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[116], level=1, select_path_id=0. ***** -*****1***** -Xsram[212] sram->in sram[212]->out sram[212]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[212]->out) 0 -.nodeset V(sram[212]->outb) vsp -Xmux_1level_tapbuf_size2[117] grid[1][2]_pin[0][2][9] chany[1][1]_in[20] chanx[1][1]_out[23] sram[213]->outb sram[213]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[117], level=1, select_path_id=0. ***** -*****1***** -Xsram[213] sram->in sram[213]->out sram[213]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[213]->out) 0 -.nodeset V(sram[213]->outb) vsp -Xmux_1level_tapbuf_size2[118] grid[1][2]_pin[0][2][11] chany[1][1]_in[22] chanx[1][1]_out[25] sram[214]->outb sram[214]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[118], level=1, select_path_id=0. ***** -*****1***** -Xsram[214] sram->in sram[214]->out sram[214]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[214]->out) 0 -.nodeset V(sram[214]->outb) vsp -Xmux_1level_tapbuf_size2[119] grid[1][2]_pin[0][2][11] chany[1][1]_in[24] chanx[1][1]_out[27] sram[215]->outb sram[215]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[119], level=1, select_path_id=0. ***** -*****1***** -Xsram[215] sram->in sram[215]->out sram[215]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[215]->out) 0 -.nodeset V(sram[215]->outb) vsp -Xmux_1level_tapbuf_size2[120] grid[1][2]_pin[0][2][13] chany[1][1]_in[26] chanx[1][1]_out[29] sram[216]->outb sram[216]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[120], level=1, select_path_id=0. ***** -*****1***** -Xsram[216] sram->in sram[216]->out sram[216]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[216]->out) 0 -.nodeset V(sram[216]->outb) vsp -.eom diff --git a/examples/spice_test_example_1/subckt/wires.sp b/examples/spice_test_example_1/subckt/wires.sp deleted file mode 100644 index c3c1067aa..000000000 --- a/examples/spice_test_example_1/subckt/wires.sp +++ /dev/null @@ -1,50 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Wires * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -* Wire, spice_model_name=direct_interc -.subckt direct_interc in out svdd sgnd -Rshortcut in out 0 -.eom - -* Wire models for segments in routing -* Wire, spice_model_name=chan_segment -.subckt chan_segment_seg0 in out mid_out svdd sgnd -Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2' -Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2' -Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2' -Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2' -* Connect the output of middle point -Vmid_out_ckt pie_wire_in0_inter mid_out 0 -Rin in pie_wire_in0 0 -Rout pie_wire_in1 out 0 -.eom - -* Wire, spice_model_name=chan_segment -.subckt chan_segment_seg1 in out mid_out svdd sgnd -Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2' -Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2' -Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2' -Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2' -* Connect the output of middle point -Vmid_out_ckt pie_wire_in0_inter mid_out 0 -Rin in pie_wire_in0 0 -Rout pie_wire_in1 out 0 -.eom - -* Wire, spice_model_name=chan_segment -.subckt chan_segment_seg2 in out mid_out svdd sgnd -Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2' -Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2' -Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2' -Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2' -* Connect the output of middle point -Vmid_out_ckt pie_wire_in0_inter mid_out 0 -Rin in pie_wire_in0 0 -Rout pie_wire_in1 out 0 -.eom - diff --git a/examples/spice_test_example_1/top_tb/example_1_top.sp b/examples/spice_test_example_1/top_tb/example_1_top.sp deleted file mode 100644 index 5e37c9bbb..000000000 --- a/examples/spice_test_example_1/top_tb/example_1_top.sp +++ /dev/null @@ -1,1300 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Netlist for Design: example_1 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:04 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_1/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_1/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_1/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_1/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_1/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_1/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_1/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -****** Include subckt netlists: Look-Up Tables (LUTs) ***** -.include './spice_test_example_1/subckt/luts.sp' -****** Include subckt netlists: Logic Blocks ***** -.include './spice_test_example_1/subckt/grid_header.sp' -****** Include subckt netlists: Routing structures (Switch Boxes, Channels, Connection Boxes) ***** -.include './spice_test_example_1/subckt/routing_header.sp' -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_local_interc gvdd_io gvdd_hardlogic -.global gvdd_sram_local_routing -.global gvdd_sram_luts -.global gvdd_sram_cbs -.global gvdd_sram_sbs -.global gvdd_sram_io -***** Global VDD ports of Look-Up Table ***** -.global -+ gvdd_lut4[0] - -***** Global VDD ports of Flip-flop ***** -.global -+ gvdd_dff[0] - -***** Global VDD ports of iopad ***** -.global -+ gvdd_iopad[0] -+ gvdd_iopad[1] -+ gvdd_iopad[2] -+ gvdd_iopad[3] -+ gvdd_iopad[4] -+ gvdd_iopad[5] -+ gvdd_iopad[6] -+ gvdd_iopad[7] -+ gvdd_iopad[8] -+ gvdd_iopad[9] -+ gvdd_iopad[10] -+ gvdd_iopad[11] -+ gvdd_iopad[12] -+ gvdd_iopad[13] -+ gvdd_iopad[14] -+ gvdd_iopad[15] -+ gvdd_iopad[16] -+ gvdd_iopad[17] -+ gvdd_iopad[18] -+ gvdd_iopad[19] -+ gvdd_iopad[20] -+ gvdd_iopad[21] -+ gvdd_iopad[22] -+ gvdd_iopad[23] -+ gvdd_iopad[24] -+ gvdd_iopad[25] -+ gvdd_iopad[26] -+ gvdd_iopad[27] -+ gvdd_iopad[28] -+ gvdd_iopad[29] -+ gvdd_iopad[30] -+ gvdd_iopad[31] - -***** Global VDD ports of hard_logic ***** -.global - -***** Global Vdds for Switch Boxes ***** -.global gvdd_sb[0][0] gvdd_sb[0][1] gvdd_sb[1][0] gvdd_sb[1][1] -***** Global Vdds for Connection Blocks - X channels ***** -.global gvdd_cbx[1][0] gvdd_cbx[1][1] -***** Global Vdds for Connection Blocks - Y channels ***** -.global gvdd_cby[0][1] gvdd_cby[1][1] -***** Global input/output ports of I/O Pads ***** -.global -+ gfpga_pad_iopad[0] -+ gfpga_pad_iopad[1] -+ gfpga_pad_iopad[2] -+ gfpga_pad_iopad[3] -+ gfpga_pad_iopad[4] -+ gfpga_pad_iopad[5] -+ gfpga_pad_iopad[6] -+ gfpga_pad_iopad[7] -+ gfpga_pad_iopad[8] -+ gfpga_pad_iopad[9] -+ gfpga_pad_iopad[10] -+ gfpga_pad_iopad[11] -+ gfpga_pad_iopad[12] -+ gfpga_pad_iopad[13] -+ gfpga_pad_iopad[14] -+ gfpga_pad_iopad[15] -+ gfpga_pad_iopad[16] -+ gfpga_pad_iopad[17] -+ gfpga_pad_iopad[18] -+ gfpga_pad_iopad[19] -+ gfpga_pad_iopad[20] -+ gfpga_pad_iopad[21] -+ gfpga_pad_iopad[22] -+ gfpga_pad_iopad[23] -+ gfpga_pad_iopad[24] -+ gfpga_pad_iopad[25] -+ gfpga_pad_iopad[26] -+ gfpga_pad_iopad[27] -+ gfpga_pad_iopad[28] -+ gfpga_pad_iopad[29] -+ gfpga_pad_iopad[30] -+ gfpga_pad_iopad[31] - -***** Link Blif Benchmark inputs to FPGA IOPADs ***** -***** Blif Benchmark inout I0 is mapped to FPGA IOPAD gfpga_pad_[30] ***** -RI0_gfpga_pad_[30] I0_gfpga_pad_[30] gfpga_pad_iopad[30] 0 -***** Blif Benchmark inout clk is mapped to FPGA IOPAD gfpga_pad_[15] ***** -Rclk_gfpga_pad_[15] clk_gfpga_pad_[15] gfpga_pad_iopad[15] 0 -***** Blif Benchmark inout out_Q0 is mapped to FPGA IOPAD gfpga_pad_[25] ***** -Rout_Q0_gfpga_pad_[25] out_Q0_gfpga_pad_[25] gfpga_pad_iopad[25] 0 -.temp 25 -.option fast -Xgrid[1][1] -+ grid[1][1]_pin[0][0][0] -+ grid[1][1]_pin[0][0][4] -+ grid[1][1]_pin[0][1][1] -+ grid[1][1]_pin[0][1][5] -+ grid[1][1]_pin[0][2][2] -+ grid[1][1]_pin[0][3][3] -+ gvdd 0 grid[1][1] -Xgrid[0][1] -+ grid[0][1]_pin[0][1][0] -+ grid[0][1]_pin[0][1][1] -+ grid[0][1]_pin[0][1][2] -+ grid[0][1]_pin[0][1][3] -+ grid[0][1]_pin[0][1][4] -+ grid[0][1]_pin[0][1][5] -+ grid[0][1]_pin[0][1][6] -+ grid[0][1]_pin[0][1][7] -+ grid[0][1]_pin[0][1][8] -+ grid[0][1]_pin[0][1][9] -+ grid[0][1]_pin[0][1][10] -+ grid[0][1]_pin[0][1][11] -+ grid[0][1]_pin[0][1][12] -+ grid[0][1]_pin[0][1][13] -+ grid[0][1]_pin[0][1][14] -+ grid[0][1]_pin[0][1][15] -+ gvdd_io 0 grid[0][1] -Xgrid[2][1] -+ grid[2][1]_pin[0][3][0] -+ grid[2][1]_pin[0][3][1] -+ grid[2][1]_pin[0][3][2] -+ grid[2][1]_pin[0][3][3] -+ grid[2][1]_pin[0][3][4] -+ grid[2][1]_pin[0][3][5] -+ grid[2][1]_pin[0][3][6] -+ grid[2][1]_pin[0][3][7] -+ grid[2][1]_pin[0][3][8] -+ grid[2][1]_pin[0][3][9] -+ grid[2][1]_pin[0][3][10] -+ grid[2][1]_pin[0][3][11] -+ grid[2][1]_pin[0][3][12] -+ grid[2][1]_pin[0][3][13] -+ grid[2][1]_pin[0][3][14] -+ grid[2][1]_pin[0][3][15] -+ gvdd_io 0 grid[2][1] -Xgrid[1][0] -+ grid[1][0]_pin[0][0][0] -+ grid[1][0]_pin[0][0][1] -+ grid[1][0]_pin[0][0][2] -+ grid[1][0]_pin[0][0][3] -+ grid[1][0]_pin[0][0][4] -+ grid[1][0]_pin[0][0][5] -+ grid[1][0]_pin[0][0][6] -+ grid[1][0]_pin[0][0][7] -+ grid[1][0]_pin[0][0][8] -+ grid[1][0]_pin[0][0][9] -+ grid[1][0]_pin[0][0][10] -+ grid[1][0]_pin[0][0][11] -+ grid[1][0]_pin[0][0][12] -+ grid[1][0]_pin[0][0][13] -+ grid[1][0]_pin[0][0][14] -+ grid[1][0]_pin[0][0][15] -+ gvdd_io 0 grid[1][0] -Xgrid[1][2] -+ grid[1][2]_pin[0][2][0] -+ grid[1][2]_pin[0][2][1] -+ grid[1][2]_pin[0][2][2] -+ grid[1][2]_pin[0][2][3] -+ grid[1][2]_pin[0][2][4] -+ grid[1][2]_pin[0][2][5] -+ grid[1][2]_pin[0][2][6] -+ grid[1][2]_pin[0][2][7] -+ grid[1][2]_pin[0][2][8] -+ grid[1][2]_pin[0][2][9] -+ grid[1][2]_pin[0][2][10] -+ grid[1][2]_pin[0][2][11] -+ grid[1][2]_pin[0][2][12] -+ grid[1][2]_pin[0][2][13] -+ grid[1][2]_pin[0][2][14] -+ grid[1][2]_pin[0][2][15] -+ gvdd_io 0 grid[1][2] -Rdangling_grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5] 0 0 -.nodeset V(grid[1][1]_pin[0][1][5]) 0 -Xchanx[1][0] -+ chanx[1][0]_out[0] -+ chanx[1][0]_in[1] -+ chanx[1][0]_out[2] -+ chanx[1][0]_in[3] -+ chanx[1][0]_out[4] -+ chanx[1][0]_in[5] -+ chanx[1][0]_out[6] -+ chanx[1][0]_in[7] -+ chanx[1][0]_out[8] -+ chanx[1][0]_in[9] -+ chanx[1][0]_out[10] -+ chanx[1][0]_in[11] -+ chanx[1][0]_out[12] -+ chanx[1][0]_in[13] -+ chanx[1][0]_out[14] -+ chanx[1][0]_in[15] -+ chanx[1][0]_out[16] -+ chanx[1][0]_in[17] -+ chanx[1][0]_out[18] -+ chanx[1][0]_in[19] -+ chanx[1][0]_out[20] -+ chanx[1][0]_in[21] -+ chanx[1][0]_out[22] -+ chanx[1][0]_in[23] -+ chanx[1][0]_out[24] -+ chanx[1][0]_in[25] -+ chanx[1][0]_out[26] -+ chanx[1][0]_in[27] -+ chanx[1][0]_out[28] -+ chanx[1][0]_in[29] -+ chanx[1][0]_in[0] -+ chanx[1][0]_out[1] -+ chanx[1][0]_in[2] -+ chanx[1][0]_out[3] -+ chanx[1][0]_in[4] -+ chanx[1][0]_out[5] -+ chanx[1][0]_in[6] -+ chanx[1][0]_out[7] -+ chanx[1][0]_in[8] -+ chanx[1][0]_out[9] -+ chanx[1][0]_in[10] -+ chanx[1][0]_out[11] -+ chanx[1][0]_in[12] -+ chanx[1][0]_out[13] -+ chanx[1][0]_in[14] -+ chanx[1][0]_out[15] -+ chanx[1][0]_in[16] -+ chanx[1][0]_out[17] -+ chanx[1][0]_in[18] -+ chanx[1][0]_out[19] -+ chanx[1][0]_in[20] -+ chanx[1][0]_out[21] -+ chanx[1][0]_in[22] -+ chanx[1][0]_out[23] -+ chanx[1][0]_in[24] -+ chanx[1][0]_out[25] -+ chanx[1][0]_in[26] -+ chanx[1][0]_out[27] -+ chanx[1][0]_in[28] -+ chanx[1][0]_out[29] -+ chanx[1][0]_midout[0] -+ chanx[1][0]_midout[1] -+ chanx[1][0]_midout[2] -+ chanx[1][0]_midout[3] -+ chanx[1][0]_midout[4] -+ chanx[1][0]_midout[5] -+ chanx[1][0]_midout[6] -+ chanx[1][0]_midout[7] -+ chanx[1][0]_midout[8] -+ chanx[1][0]_midout[9] -+ chanx[1][0]_midout[10] -+ chanx[1][0]_midout[11] -+ chanx[1][0]_midout[12] -+ chanx[1][0]_midout[13] -+ chanx[1][0]_midout[14] -+ chanx[1][0]_midout[15] -+ chanx[1][0]_midout[16] -+ chanx[1][0]_midout[17] -+ chanx[1][0]_midout[18] -+ chanx[1][0]_midout[19] -+ chanx[1][0]_midout[20] -+ chanx[1][0]_midout[21] -+ chanx[1][0]_midout[22] -+ chanx[1][0]_midout[23] -+ chanx[1][0]_midout[24] -+ chanx[1][0]_midout[25] -+ chanx[1][0]_midout[26] -+ chanx[1][0]_midout[27] -+ chanx[1][0]_midout[28] -+ chanx[1][0]_midout[29] -+ gvdd 0 chanx[1][0] -Xchanx[1][1] -+ chanx[1][1]_out[0] -+ chanx[1][1]_in[1] -+ chanx[1][1]_out[2] -+ chanx[1][1]_in[3] -+ chanx[1][1]_out[4] -+ chanx[1][1]_in[5] -+ chanx[1][1]_out[6] -+ chanx[1][1]_in[7] -+ chanx[1][1]_out[8] -+ chanx[1][1]_in[9] -+ chanx[1][1]_out[10] -+ chanx[1][1]_in[11] -+ chanx[1][1]_out[12] -+ chanx[1][1]_in[13] -+ chanx[1][1]_out[14] -+ chanx[1][1]_in[15] -+ chanx[1][1]_out[16] -+ chanx[1][1]_in[17] -+ chanx[1][1]_out[18] -+ chanx[1][1]_in[19] -+ chanx[1][1]_out[20] -+ chanx[1][1]_in[21] -+ chanx[1][1]_out[22] -+ chanx[1][1]_in[23] -+ chanx[1][1]_out[24] -+ chanx[1][1]_in[25] -+ chanx[1][1]_out[26] -+ chanx[1][1]_in[27] -+ chanx[1][1]_out[28] -+ chanx[1][1]_in[29] -+ chanx[1][1]_in[0] -+ chanx[1][1]_out[1] -+ chanx[1][1]_in[2] -+ chanx[1][1]_out[3] -+ chanx[1][1]_in[4] -+ chanx[1][1]_out[5] -+ chanx[1][1]_in[6] -+ chanx[1][1]_out[7] -+ chanx[1][1]_in[8] -+ chanx[1][1]_out[9] -+ chanx[1][1]_in[10] -+ chanx[1][1]_out[11] -+ chanx[1][1]_in[12] -+ chanx[1][1]_out[13] -+ chanx[1][1]_in[14] -+ chanx[1][1]_out[15] -+ chanx[1][1]_in[16] -+ chanx[1][1]_out[17] -+ chanx[1][1]_in[18] -+ chanx[1][1]_out[19] -+ chanx[1][1]_in[20] -+ chanx[1][1]_out[21] -+ chanx[1][1]_in[22] -+ chanx[1][1]_out[23] -+ chanx[1][1]_in[24] -+ chanx[1][1]_out[25] -+ chanx[1][1]_in[26] -+ chanx[1][1]_out[27] -+ chanx[1][1]_in[28] -+ chanx[1][1]_out[29] -+ chanx[1][1]_midout[0] -+ chanx[1][1]_midout[1] -+ chanx[1][1]_midout[2] -+ chanx[1][1]_midout[3] -+ chanx[1][1]_midout[4] -+ chanx[1][1]_midout[5] -+ chanx[1][1]_midout[6] -+ chanx[1][1]_midout[7] -+ chanx[1][1]_midout[8] -+ chanx[1][1]_midout[9] -+ chanx[1][1]_midout[10] -+ chanx[1][1]_midout[11] -+ chanx[1][1]_midout[12] -+ chanx[1][1]_midout[13] -+ chanx[1][1]_midout[14] -+ chanx[1][1]_midout[15] -+ chanx[1][1]_midout[16] -+ chanx[1][1]_midout[17] -+ chanx[1][1]_midout[18] -+ chanx[1][1]_midout[19] -+ chanx[1][1]_midout[20] -+ chanx[1][1]_midout[21] -+ chanx[1][1]_midout[22] -+ chanx[1][1]_midout[23] -+ chanx[1][1]_midout[24] -+ chanx[1][1]_midout[25] -+ chanx[1][1]_midout[26] -+ chanx[1][1]_midout[27] -+ chanx[1][1]_midout[28] -+ chanx[1][1]_midout[29] -+ gvdd 0 chanx[1][1] -Xchany[0][1] -+ chany[0][1]_out[0] -+ chany[0][1]_in[1] -+ chany[0][1]_out[2] -+ chany[0][1]_in[3] -+ chany[0][1]_out[4] -+ chany[0][1]_in[5] -+ chany[0][1]_out[6] -+ chany[0][1]_in[7] -+ chany[0][1]_out[8] -+ chany[0][1]_in[9] -+ chany[0][1]_out[10] -+ chany[0][1]_in[11] -+ chany[0][1]_out[12] -+ chany[0][1]_in[13] -+ chany[0][1]_out[14] -+ chany[0][1]_in[15] -+ chany[0][1]_out[16] -+ chany[0][1]_in[17] -+ chany[0][1]_out[18] -+ chany[0][1]_in[19] -+ chany[0][1]_out[20] -+ chany[0][1]_in[21] -+ chany[0][1]_out[22] -+ chany[0][1]_in[23] -+ chany[0][1]_out[24] -+ chany[0][1]_in[25] -+ chany[0][1]_out[26] -+ chany[0][1]_in[27] -+ chany[0][1]_out[28] -+ chany[0][1]_in[29] -+ chany[0][1]_in[0] -+ chany[0][1]_out[1] -+ chany[0][1]_in[2] -+ chany[0][1]_out[3] -+ chany[0][1]_in[4] -+ chany[0][1]_out[5] -+ chany[0][1]_in[6] -+ chany[0][1]_out[7] -+ chany[0][1]_in[8] -+ chany[0][1]_out[9] -+ chany[0][1]_in[10] -+ chany[0][1]_out[11] -+ chany[0][1]_in[12] -+ chany[0][1]_out[13] -+ chany[0][1]_in[14] -+ chany[0][1]_out[15] -+ chany[0][1]_in[16] -+ chany[0][1]_out[17] -+ chany[0][1]_in[18] -+ chany[0][1]_out[19] -+ chany[0][1]_in[20] -+ chany[0][1]_out[21] -+ chany[0][1]_in[22] -+ chany[0][1]_out[23] -+ chany[0][1]_in[24] -+ chany[0][1]_out[25] -+ chany[0][1]_in[26] -+ chany[0][1]_out[27] -+ chany[0][1]_in[28] -+ chany[0][1]_out[29] -+ chany[0][1]_midout[0] -+ chany[0][1]_midout[1] -+ chany[0][1]_midout[2] -+ chany[0][1]_midout[3] -+ chany[0][1]_midout[4] -+ chany[0][1]_midout[5] -+ chany[0][1]_midout[6] -+ chany[0][1]_midout[7] -+ chany[0][1]_midout[8] -+ chany[0][1]_midout[9] -+ chany[0][1]_midout[10] -+ chany[0][1]_midout[11] -+ chany[0][1]_midout[12] -+ chany[0][1]_midout[13] -+ chany[0][1]_midout[14] -+ chany[0][1]_midout[15] -+ chany[0][1]_midout[16] -+ chany[0][1]_midout[17] -+ chany[0][1]_midout[18] -+ chany[0][1]_midout[19] -+ chany[0][1]_midout[20] -+ chany[0][1]_midout[21] -+ chany[0][1]_midout[22] -+ chany[0][1]_midout[23] -+ chany[0][1]_midout[24] -+ chany[0][1]_midout[25] -+ chany[0][1]_midout[26] -+ chany[0][1]_midout[27] -+ chany[0][1]_midout[28] -+ chany[0][1]_midout[29] -+ gvdd 0 chany[0][1] -Xchany[1][1] -+ chany[1][1]_out[0] -+ chany[1][1]_in[1] -+ chany[1][1]_out[2] -+ chany[1][1]_in[3] -+ chany[1][1]_out[4] -+ chany[1][1]_in[5] -+ chany[1][1]_out[6] -+ chany[1][1]_in[7] -+ chany[1][1]_out[8] -+ chany[1][1]_in[9] -+ chany[1][1]_out[10] -+ chany[1][1]_in[11] -+ chany[1][1]_out[12] -+ chany[1][1]_in[13] -+ chany[1][1]_out[14] -+ chany[1][1]_in[15] -+ chany[1][1]_out[16] -+ chany[1][1]_in[17] -+ chany[1][1]_out[18] -+ chany[1][1]_in[19] -+ chany[1][1]_out[20] -+ chany[1][1]_in[21] -+ chany[1][1]_out[22] -+ chany[1][1]_in[23] -+ chany[1][1]_out[24] -+ chany[1][1]_in[25] -+ chany[1][1]_out[26] -+ chany[1][1]_in[27] -+ chany[1][1]_out[28] -+ chany[1][1]_in[29] -+ chany[1][1]_in[0] -+ chany[1][1]_out[1] -+ chany[1][1]_in[2] -+ chany[1][1]_out[3] -+ chany[1][1]_in[4] -+ chany[1][1]_out[5] -+ chany[1][1]_in[6] -+ chany[1][1]_out[7] -+ chany[1][1]_in[8] -+ chany[1][1]_out[9] -+ chany[1][1]_in[10] -+ chany[1][1]_out[11] -+ chany[1][1]_in[12] -+ chany[1][1]_out[13] -+ chany[1][1]_in[14] -+ chany[1][1]_out[15] -+ chany[1][1]_in[16] -+ chany[1][1]_out[17] -+ chany[1][1]_in[18] -+ chany[1][1]_out[19] -+ chany[1][1]_in[20] -+ chany[1][1]_out[21] -+ chany[1][1]_in[22] -+ chany[1][1]_out[23] -+ chany[1][1]_in[24] -+ chany[1][1]_out[25] -+ chany[1][1]_in[26] -+ chany[1][1]_out[27] -+ chany[1][1]_in[28] -+ chany[1][1]_out[29] -+ chany[1][1]_midout[0] -+ chany[1][1]_midout[1] -+ chany[1][1]_midout[2] -+ chany[1][1]_midout[3] -+ chany[1][1]_midout[4] -+ chany[1][1]_midout[5] -+ chany[1][1]_midout[6] -+ chany[1][1]_midout[7] -+ chany[1][1]_midout[8] -+ chany[1][1]_midout[9] -+ chany[1][1]_midout[10] -+ chany[1][1]_midout[11] -+ chany[1][1]_midout[12] -+ chany[1][1]_midout[13] -+ chany[1][1]_midout[14] -+ chany[1][1]_midout[15] -+ chany[1][1]_midout[16] -+ chany[1][1]_midout[17] -+ chany[1][1]_midout[18] -+ chany[1][1]_midout[19] -+ chany[1][1]_midout[20] -+ chany[1][1]_midout[21] -+ chany[1][1]_midout[22] -+ chany[1][1]_midout[23] -+ chany[1][1]_midout[24] -+ chany[1][1]_midout[25] -+ chany[1][1]_midout[26] -+ chany[1][1]_midout[27] -+ chany[1][1]_midout[28] -+ chany[1][1]_midout[29] -+ gvdd 0 chany[1][1] -Xcbx[1][0] -+ chanx[1][0]_midout[0] -+ chanx[1][0]_midout[1] -+ chanx[1][0]_midout[2] -+ chanx[1][0]_midout[3] -+ chanx[1][0]_midout[4] -+ chanx[1][0]_midout[5] -+ chanx[1][0]_midout[6] -+ chanx[1][0]_midout[7] -+ chanx[1][0]_midout[8] -+ chanx[1][0]_midout[9] -+ chanx[1][0]_midout[10] -+ chanx[1][0]_midout[11] -+ chanx[1][0]_midout[12] -+ chanx[1][0]_midout[13] -+ chanx[1][0]_midout[14] -+ chanx[1][0]_midout[15] -+ chanx[1][0]_midout[16] -+ chanx[1][0]_midout[17] -+ chanx[1][0]_midout[18] -+ chanx[1][0]_midout[19] -+ chanx[1][0]_midout[20] -+ chanx[1][0]_midout[21] -+ chanx[1][0]_midout[22] -+ chanx[1][0]_midout[23] -+ chanx[1][0]_midout[24] -+ chanx[1][0]_midout[25] -+ chanx[1][0]_midout[26] -+ chanx[1][0]_midout[27] -+ chanx[1][0]_midout[28] -+ chanx[1][0]_midout[29] -+ grid[1][1]_pin[0][2][2] -+ grid[1][0]_pin[0][0][0] -+ grid[1][0]_pin[0][0][2] -+ grid[1][0]_pin[0][0][4] -+ grid[1][0]_pin[0][0][6] -+ grid[1][0]_pin[0][0][8] -+ grid[1][0]_pin[0][0][10] -+ grid[1][0]_pin[0][0][12] -+ grid[1][0]_pin[0][0][14] -+ gvdd_cbx[1][0] 0 cbx[1][0] -Xcbx[1][1] -+ chanx[1][1]_midout[0] -+ chanx[1][1]_midout[1] -+ chanx[1][1]_midout[2] -+ chanx[1][1]_midout[3] -+ chanx[1][1]_midout[4] -+ chanx[1][1]_midout[5] -+ chanx[1][1]_midout[6] -+ chanx[1][1]_midout[7] -+ chanx[1][1]_midout[8] -+ chanx[1][1]_midout[9] -+ chanx[1][1]_midout[10] -+ chanx[1][1]_midout[11] -+ chanx[1][1]_midout[12] -+ chanx[1][1]_midout[13] -+ chanx[1][1]_midout[14] -+ chanx[1][1]_midout[15] -+ chanx[1][1]_midout[16] -+ chanx[1][1]_midout[17] -+ chanx[1][1]_midout[18] -+ chanx[1][1]_midout[19] -+ chanx[1][1]_midout[20] -+ chanx[1][1]_midout[21] -+ chanx[1][1]_midout[22] -+ chanx[1][1]_midout[23] -+ chanx[1][1]_midout[24] -+ chanx[1][1]_midout[25] -+ chanx[1][1]_midout[26] -+ chanx[1][1]_midout[27] -+ chanx[1][1]_midout[28] -+ chanx[1][1]_midout[29] -+ grid[1][2]_pin[0][2][0] -+ grid[1][2]_pin[0][2][2] -+ grid[1][2]_pin[0][2][4] -+ grid[1][2]_pin[0][2][6] -+ grid[1][2]_pin[0][2][8] -+ grid[1][2]_pin[0][2][10] -+ grid[1][2]_pin[0][2][12] -+ grid[1][2]_pin[0][2][14] -+ grid[1][1]_pin[0][0][0] -+ gvdd_cbx[1][1] 0 cbx[1][1] -Xcby[0][1] -+ chany[0][1]_midout[0] -+ chany[0][1]_midout[1] -+ chany[0][1]_midout[2] -+ chany[0][1]_midout[3] -+ chany[0][1]_midout[4] -+ chany[0][1]_midout[5] -+ chany[0][1]_midout[6] -+ chany[0][1]_midout[7] -+ chany[0][1]_midout[8] -+ chany[0][1]_midout[9] -+ chany[0][1]_midout[10] -+ chany[0][1]_midout[11] -+ chany[0][1]_midout[12] -+ chany[0][1]_midout[13] -+ chany[0][1]_midout[14] -+ chany[0][1]_midout[15] -+ chany[0][1]_midout[16] -+ chany[0][1]_midout[17] -+ chany[0][1]_midout[18] -+ chany[0][1]_midout[19] -+ chany[0][1]_midout[20] -+ chany[0][1]_midout[21] -+ chany[0][1]_midout[22] -+ chany[0][1]_midout[23] -+ chany[0][1]_midout[24] -+ chany[0][1]_midout[25] -+ chany[0][1]_midout[26] -+ chany[0][1]_midout[27] -+ chany[0][1]_midout[28] -+ chany[0][1]_midout[29] -+ grid[1][1]_pin[0][3][3] -+ grid[0][1]_pin[0][1][0] -+ grid[0][1]_pin[0][1][2] -+ grid[0][1]_pin[0][1][4] -+ grid[0][1]_pin[0][1][6] -+ grid[0][1]_pin[0][1][8] -+ grid[0][1]_pin[0][1][10] -+ grid[0][1]_pin[0][1][12] -+ grid[0][1]_pin[0][1][14] -+ gvdd_cby[0][1] 0 cby[0][1] -Xcby[1][1] -+ chany[1][1]_midout[0] -+ chany[1][1]_midout[1] -+ chany[1][1]_midout[2] -+ chany[1][1]_midout[3] -+ chany[1][1]_midout[4] -+ chany[1][1]_midout[5] -+ chany[1][1]_midout[6] -+ chany[1][1]_midout[7] -+ chany[1][1]_midout[8] -+ chany[1][1]_midout[9] -+ chany[1][1]_midout[10] -+ chany[1][1]_midout[11] -+ chany[1][1]_midout[12] -+ chany[1][1]_midout[13] -+ chany[1][1]_midout[14] -+ chany[1][1]_midout[15] -+ chany[1][1]_midout[16] -+ chany[1][1]_midout[17] -+ chany[1][1]_midout[18] -+ chany[1][1]_midout[19] -+ chany[1][1]_midout[20] -+ chany[1][1]_midout[21] -+ chany[1][1]_midout[22] -+ chany[1][1]_midout[23] -+ chany[1][1]_midout[24] -+ chany[1][1]_midout[25] -+ chany[1][1]_midout[26] -+ chany[1][1]_midout[27] -+ chany[1][1]_midout[28] -+ chany[1][1]_midout[29] -+ grid[2][1]_pin[0][3][0] -+ grid[2][1]_pin[0][3][2] -+ grid[2][1]_pin[0][3][4] -+ grid[2][1]_pin[0][3][6] -+ grid[2][1]_pin[0][3][8] -+ grid[2][1]_pin[0][3][10] -+ grid[2][1]_pin[0][3][12] -+ grid[2][1]_pin[0][3][14] -+ grid[1][1]_pin[0][1][1] -+ grid[1][1]_pin[0][1][5] -+ gvdd_cby[1][1] 0 cby[1][1] -Xsb[0][0] -+ chany[0][1]_out[0] chany[0][1]_in[1] chany[0][1]_out[2] chany[0][1]_in[3] chany[0][1]_out[4] chany[0][1]_in[5] chany[0][1]_out[6] chany[0][1]_in[7] chany[0][1]_out[8] chany[0][1]_in[9] chany[0][1]_out[10] chany[0][1]_in[11] chany[0][1]_out[12] chany[0][1]_in[13] chany[0][1]_out[14] chany[0][1]_in[15] chany[0][1]_out[16] chany[0][1]_in[17] chany[0][1]_out[18] chany[0][1]_in[19] chany[0][1]_out[20] chany[0][1]_in[21] chany[0][1]_out[22] chany[0][1]_in[23] chany[0][1]_out[24] chany[0][1]_in[25] chany[0][1]_out[26] chany[0][1]_in[27] chany[0][1]_out[28] chany[0][1]_in[29] -+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] -+ chanx[1][0]_out[0] chanx[1][0]_in[1] chanx[1][0]_out[2] chanx[1][0]_in[3] chanx[1][0]_out[4] chanx[1][0]_in[5] chanx[1][0]_out[6] chanx[1][0]_in[7] chanx[1][0]_out[8] chanx[1][0]_in[9] chanx[1][0]_out[10] chanx[1][0]_in[11] chanx[1][0]_out[12] chanx[1][0]_in[13] chanx[1][0]_out[14] chanx[1][0]_in[15] chanx[1][0]_out[16] chanx[1][0]_in[17] chanx[1][0]_out[18] chanx[1][0]_in[19] chanx[1][0]_out[20] chanx[1][0]_in[21] chanx[1][0]_out[22] chanx[1][0]_in[23] chanx[1][0]_out[24] chanx[1][0]_in[25] chanx[1][0]_out[26] chanx[1][0]_in[27] chanx[1][0]_out[28] chanx[1][0]_in[29] -+ grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ -+ -+ -+ -+ gvdd_sb[0][0] 0 sb[0][0] -Xsb[0][1] -+ -+ -+ chanx[1][1]_out[0] chanx[1][1]_in[1] chanx[1][1]_out[2] chanx[1][1]_in[3] chanx[1][1]_out[4] chanx[1][1]_in[5] chanx[1][1]_out[6] chanx[1][1]_in[7] chanx[1][1]_out[8] chanx[1][1]_in[9] chanx[1][1]_out[10] chanx[1][1]_in[11] chanx[1][1]_out[12] chanx[1][1]_in[13] chanx[1][1]_out[14] chanx[1][1]_in[15] chanx[1][1]_out[16] chanx[1][1]_in[17] chanx[1][1]_out[18] chanx[1][1]_in[19] chanx[1][1]_out[20] chanx[1][1]_in[21] chanx[1][1]_out[22] chanx[1][1]_in[23] chanx[1][1]_out[24] chanx[1][1]_in[25] chanx[1][1]_out[26] chanx[1][1]_in[27] chanx[1][1]_out[28] chanx[1][1]_in[29] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][4] -+ chany[0][1]_in[0] chany[0][1]_out[1] chany[0][1]_in[2] chany[0][1]_out[3] chany[0][1]_in[4] chany[0][1]_out[5] chany[0][1]_in[6] chany[0][1]_out[7] chany[0][1]_in[8] chany[0][1]_out[9] chany[0][1]_in[10] chany[0][1]_out[11] chany[0][1]_in[12] chany[0][1]_out[13] chany[0][1]_in[14] chany[0][1]_out[15] chany[0][1]_in[16] chany[0][1]_out[17] chany[0][1]_in[18] chany[0][1]_out[19] chany[0][1]_in[20] chany[0][1]_out[21] chany[0][1]_in[22] chany[0][1]_out[23] chany[0][1]_in[24] chany[0][1]_out[25] chany[0][1]_in[26] chany[0][1]_out[27] chany[0][1]_in[28] chany[0][1]_out[29] -+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] -+ -+ -+ gvdd_sb[0][1] 0 sb[0][1] -Xsb[1][0] -+ chany[1][1]_out[0] chany[1][1]_in[1] chany[1][1]_out[2] chany[1][1]_in[3] chany[1][1]_out[4] chany[1][1]_in[5] chany[1][1]_out[6] chany[1][1]_in[7] chany[1][1]_out[8] chany[1][1]_in[9] chany[1][1]_out[10] chany[1][1]_in[11] chany[1][1]_out[12] chany[1][1]_in[13] chany[1][1]_out[14] chany[1][1]_in[15] chany[1][1]_out[16] chany[1][1]_in[17] chany[1][1]_out[18] chany[1][1]_in[19] chany[1][1]_out[20] chany[1][1]_in[21] chany[1][1]_out[22] chany[1][1]_in[23] chany[1][1]_out[24] chany[1][1]_in[25] chany[1][1]_out[26] chany[1][1]_in[27] chany[1][1]_out[28] chany[1][1]_in[29] -+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] -+ -+ -+ -+ -+ chanx[1][0]_in[0] chanx[1][0]_out[1] chanx[1][0]_in[2] chanx[1][0]_out[3] chanx[1][0]_in[4] chanx[1][0]_out[5] chanx[1][0]_in[6] chanx[1][0]_out[7] chanx[1][0]_in[8] chanx[1][0]_out[9] chanx[1][0]_in[10] chanx[1][0]_out[11] chanx[1][0]_in[12] chanx[1][0]_out[13] chanx[1][0]_in[14] chanx[1][0]_out[15] chanx[1][0]_in[16] chanx[1][0]_out[17] chanx[1][0]_in[18] chanx[1][0]_out[19] chanx[1][0]_in[20] chanx[1][0]_out[21] chanx[1][0]_in[22] chanx[1][0]_out[23] chanx[1][0]_in[24] chanx[1][0]_out[25] chanx[1][0]_in[26] chanx[1][0]_out[27] chanx[1][0]_in[28] chanx[1][0]_out[29] -+ grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ gvdd_sb[1][0] 0 sb[1][0] -Xsb[1][1] -+ -+ -+ -+ -+ chany[1][1]_in[0] chany[1][1]_out[1] chany[1][1]_in[2] chany[1][1]_out[3] chany[1][1]_in[4] chany[1][1]_out[5] chany[1][1]_in[6] chany[1][1]_out[7] chany[1][1]_in[8] chany[1][1]_out[9] chany[1][1]_in[10] chany[1][1]_out[11] chany[1][1]_in[12] chany[1][1]_out[13] chany[1][1]_in[14] chany[1][1]_out[15] chany[1][1]_in[16] chany[1][1]_out[17] chany[1][1]_in[18] chany[1][1]_out[19] chany[1][1]_in[20] chany[1][1]_out[21] chany[1][1]_in[22] chany[1][1]_out[23] chany[1][1]_in[24] chany[1][1]_out[25] chany[1][1]_in[26] chany[1][1]_out[27] chany[1][1]_in[28] chany[1][1]_out[29] -+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] -+ chanx[1][1]_in[0] chanx[1][1]_out[1] chanx[1][1]_in[2] chanx[1][1]_out[3] chanx[1][1]_in[4] chanx[1][1]_out[5] chanx[1][1]_in[6] chanx[1][1]_out[7] chanx[1][1]_in[8] chanx[1][1]_out[9] chanx[1][1]_in[10] chanx[1][1]_out[11] chanx[1][1]_in[12] chanx[1][1]_out[13] chanx[1][1]_in[14] chanx[1][1]_out[15] chanx[1][1]_in[16] chanx[1][1]_out[17] chanx[1][1]_in[18] chanx[1][1]_out[19] chanx[1][1]_in[20] chanx[1][1]_out[21] chanx[1][1]_in[22] chanx[1][1]_out[23] chanx[1][1]_in[24] chanx[1][1]_out[25] chanx[1][1]_in[26] chanx[1][1]_out[27] chanx[1][1]_in[28] chanx[1][1]_out[29] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][4] -+ gvdd_sb[1][1] 0 sb[1][1] -***** BEGIN CLB to CLB Direct Connections ***** -***** END CLB to CLB Direct Connections ***** -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for I/O pads ***** -Vgvdd_io gvdd_io 0 vsp -***** Global VDD for I/O pads SRAMs ***** -Vgvdd_sram_io gvdd_sram_io 0 vsp -***** Global VDD for Local Interconnection ***** -Vgvdd_local_interc gvdd_local_interc 0 vsp -***** Global VDD for CLB to CLB direct connection ***** -Vgvdd_direct_interc gvdd_direct_interc 0 vsp -***** Global VDD for local routing SRAMs ***** -Vgvdd_sram_local_routing gvdd_sram_local_routing 0 vsp -***** Global VDD for LUTs SRAMs ***** -Vgvdd_sram_luts gvdd_sram_luts 0 vsp -***** Global VDD for Connection Boxes SRAMs ***** -Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp -***** Global VDD for Switch Boxes SRAMs ***** -Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp -***** Global VDD for Hard Logics ***** -***** Global VDD for Look-Up Tables (LUTs) ***** -Vgvdd_lut4[0] gvdd_lut4[0] 0 vsp -Rgvdd_lut4[0]_huge gvdd_lut4[0] 0 'vsp/10e-15' -***** Global VDD for Flip-flops (FFs) ***** -Vgvdd_dff[0] gvdd_dff[0] 0 vsp -Rgvdd_dff[0]_huge gvdd_dff[0] 0 'vsp/10e-15' -***** Global VDD for Flip-flops (FFs) ***** -Vgvdd_iopad[0] gvdd_iopad[0] 0 vsp -Rgvdd_iopad[0]_huge gvdd_iopad[0] 0 'vsp/10e-15' -Vgvdd_iopad[1] gvdd_iopad[1] 0 vsp -Rgvdd_iopad[1]_huge gvdd_iopad[1] 0 'vsp/10e-15' -Vgvdd_iopad[2] gvdd_iopad[2] 0 vsp -Rgvdd_iopad[2]_huge gvdd_iopad[2] 0 'vsp/10e-15' -Vgvdd_iopad[3] gvdd_iopad[3] 0 vsp -Rgvdd_iopad[3]_huge gvdd_iopad[3] 0 'vsp/10e-15' -Vgvdd_iopad[4] gvdd_iopad[4] 0 vsp -Rgvdd_iopad[4]_huge gvdd_iopad[4] 0 'vsp/10e-15' -Vgvdd_iopad[5] gvdd_iopad[5] 0 vsp -Rgvdd_iopad[5]_huge gvdd_iopad[5] 0 'vsp/10e-15' -Vgvdd_iopad[6] gvdd_iopad[6] 0 vsp -Rgvdd_iopad[6]_huge gvdd_iopad[6] 0 'vsp/10e-15' -Vgvdd_iopad[7] gvdd_iopad[7] 0 vsp -Rgvdd_iopad[7]_huge gvdd_iopad[7] 0 'vsp/10e-15' -Vgvdd_iopad[8] gvdd_iopad[8] 0 vsp -Rgvdd_iopad[8]_huge gvdd_iopad[8] 0 'vsp/10e-15' -Vgvdd_iopad[9] gvdd_iopad[9] 0 vsp -Rgvdd_iopad[9]_huge gvdd_iopad[9] 0 'vsp/10e-15' -Vgvdd_iopad[10] gvdd_iopad[10] 0 vsp -Rgvdd_iopad[10]_huge gvdd_iopad[10] 0 'vsp/10e-15' -Vgvdd_iopad[11] gvdd_iopad[11] 0 vsp -Rgvdd_iopad[11]_huge gvdd_iopad[11] 0 'vsp/10e-15' -Vgvdd_iopad[12] gvdd_iopad[12] 0 vsp -Rgvdd_iopad[12]_huge gvdd_iopad[12] 0 'vsp/10e-15' -Vgvdd_iopad[13] gvdd_iopad[13] 0 vsp -Rgvdd_iopad[13]_huge gvdd_iopad[13] 0 'vsp/10e-15' -Vgvdd_iopad[14] gvdd_iopad[14] 0 vsp -Rgvdd_iopad[14]_huge gvdd_iopad[14] 0 'vsp/10e-15' -Vgvdd_iopad[15] gvdd_iopad[15] 0 vsp -Rgvdd_iopad[15]_huge gvdd_iopad[15] 0 'vsp/10e-15' -Vgvdd_iopad[16] gvdd_iopad[16] 0 vsp -Rgvdd_iopad[16]_huge gvdd_iopad[16] 0 'vsp/10e-15' -Vgvdd_iopad[17] gvdd_iopad[17] 0 vsp -Rgvdd_iopad[17]_huge gvdd_iopad[17] 0 'vsp/10e-15' -Vgvdd_iopad[18] gvdd_iopad[18] 0 vsp -Rgvdd_iopad[18]_huge gvdd_iopad[18] 0 'vsp/10e-15' -Vgvdd_iopad[19] gvdd_iopad[19] 0 vsp -Rgvdd_iopad[19]_huge gvdd_iopad[19] 0 'vsp/10e-15' -Vgvdd_iopad[20] gvdd_iopad[20] 0 vsp -Rgvdd_iopad[20]_huge gvdd_iopad[20] 0 'vsp/10e-15' -Vgvdd_iopad[21] gvdd_iopad[21] 0 vsp -Rgvdd_iopad[21]_huge gvdd_iopad[21] 0 'vsp/10e-15' -Vgvdd_iopad[22] gvdd_iopad[22] 0 vsp -Rgvdd_iopad[22]_huge gvdd_iopad[22] 0 'vsp/10e-15' -Vgvdd_iopad[23] gvdd_iopad[23] 0 vsp -Rgvdd_iopad[23]_huge gvdd_iopad[23] 0 'vsp/10e-15' -Vgvdd_iopad[24] gvdd_iopad[24] 0 vsp -Rgvdd_iopad[24]_huge gvdd_iopad[24] 0 'vsp/10e-15' -Vgvdd_iopad[25] gvdd_iopad[25] 0 vsp -Rgvdd_iopad[25]_huge gvdd_iopad[25] 0 'vsp/10e-15' -Vgvdd_iopad[26] gvdd_iopad[26] 0 vsp -Rgvdd_iopad[26]_huge gvdd_iopad[26] 0 'vsp/10e-15' -Vgvdd_iopad[27] gvdd_iopad[27] 0 vsp -Rgvdd_iopad[27]_huge gvdd_iopad[27] 0 'vsp/10e-15' -Vgvdd_iopad[28] gvdd_iopad[28] 0 vsp -Rgvdd_iopad[28]_huge gvdd_iopad[28] 0 'vsp/10e-15' -Vgvdd_iopad[29] gvdd_iopad[29] 0 vsp -Rgvdd_iopad[29]_huge gvdd_iopad[29] 0 'vsp/10e-15' -Vgvdd_iopad[30] gvdd_iopad[30] 0 vsp -Rgvdd_iopad[30]_huge gvdd_iopad[30] 0 'vsp/10e-15' -Vgvdd_iopad[31] gvdd_iopad[31] 0 vsp -Rgvdd_iopad[31]_huge gvdd_iopad[31] 0 'vsp/10e-15' -***** Global VDD for Switch Boxes(SBs) ***** -Vgvdd_sb[0][0] gvdd_sb[0][0] 0 vsp -Vgvdd_sb[0][1] gvdd_sb[0][1] 0 vsp -Vgvdd_sb[1][0] gvdd_sb[1][0] 0 vsp -Vgvdd_sb[1][1] gvdd_sb[1][1] 0 vsp -***** Global VDD for Connection Boxes(CBs) ***** -Vgvdd_cbx[1][0] gvdd_cbx[1][0] 0 vsp -Vgvdd_cbx[1][1] gvdd_cbx[1][1] 0 vsp -Vgvdd_cby[0][1] gvdd_cby[0][1] 0 vsp -Vgvdd_cby[1][1] gvdd_cby[1][1] 0 vsp -Vgfpga_pad_iopad[0] gfpga_pad_iopad[0] 0 0 -Vgfpga_pad_iopad[1] gfpga_pad_iopad[1] 0 0 -Vgfpga_pad_iopad[2] gfpga_pad_iopad[2] 0 0 -Vgfpga_pad_iopad[3] gfpga_pad_iopad[3] 0 0 -Vgfpga_pad_iopad[4] gfpga_pad_iopad[4] 0 0 -Vgfpga_pad_iopad[5] gfpga_pad_iopad[5] 0 0 -Vgfpga_pad_iopad[6] gfpga_pad_iopad[6] 0 0 -Vgfpga_pad_iopad[7] gfpga_pad_iopad[7] 0 0 -Vgfpga_pad_iopad[8] gfpga_pad_iopad[8] 0 0 -Vgfpga_pad_iopad[9] gfpga_pad_iopad[9] 0 0 -Vgfpga_pad_iopad[10] gfpga_pad_iopad[10] 0 0 -Vgfpga_pad_iopad[11] gfpga_pad_iopad[11] 0 0 -Vgfpga_pad_iopad[12] gfpga_pad_iopad[12] 0 0 -Vgfpga_pad_iopad[13] gfpga_pad_iopad[13] 0 0 -Vgfpga_pad_iopad[14] gfpga_pad_iopad[14] 0 0 -Vgfpga_pad_iopad[15] gfpga_pad_iopad[15] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4936*10.3093*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.3093*clock_period') -Vgfpga_pad_iopad[16] gfpga_pad_iopad[16] 0 0 -Vgfpga_pad_iopad[17] gfpga_pad_iopad[17] 0 0 -Vgfpga_pad_iopad[18] gfpga_pad_iopad[18] 0 0 -Vgfpga_pad_iopad[19] gfpga_pad_iopad[19] 0 0 -Vgfpga_pad_iopad[20] gfpga_pad_iopad[20] 0 0 -Vgfpga_pad_iopad[21] gfpga_pad_iopad[21] 0 0 -Vgfpga_pad_iopad[22] gfpga_pad_iopad[22] 0 0 -Vgfpga_pad_iopad[23] gfpga_pad_iopad[23] 0 0 -Vgfpga_pad_iopad[24] gfpga_pad_iopad[24] 0 0 -Vgfpga_pad_iopad[26] gfpga_pad_iopad[26] 0 0 -Vgfpga_pad_iopad[27] gfpga_pad_iopad[27] 0 0 -Vgfpga_pad_iopad[28] gfpga_pad_iopad[28] 0 0 -Vgfpga_pad_iopad[29] gfpga_pad_iopad[29] 0 0 -Vgfpga_pad_iopad[30] gfpga_pad_iopad[30] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4782*10.4932*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.4932*clock_period') -Vgfpga_pad_iopad[31] gfpga_pad_iopad[31] 0 0 -***** 7 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '7*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.measure tran leakage_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from=0 to='clock_period' -.measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period' -.measure tran leakage_power_sram_cbs avg p(Vgvdd_sram_cbs) from=0 to='clock_period' -.measure tran leakage_power_sram_sbs avg p(Vgvdd_sram_sbs) from=0 to='clock_period' -.measure tran leakage_power_io avg p(Vgvdd_io) from=0 to='clock_period' -.measure tran leakage_power_local_interc avg p(Vgvdd_local_interc) from=0 to='clock_period' -.measure tran leakage_power_direct_interc avg p(Vgvdd_direct_interc) from=0 to='clock_period' -.measure tran leakage_power_lut4[0] avg p(Vgvdd_lut4[0]) from=0 to='clock_period' -.measure tran leakage_power_lut4[0to0] -+ param = 'leakage_power_lut4[0]' -.measure tran total_leakage_power_lut4 -+ param = 'leakage_power_lut4[0to0]' -.measure tran leakage_power_dff[0] avg p(Vgvdd_dff[0]) from=0 to='clock_period' -.measure tran leakage_power_dff[0to0] -+ param = 'leakage_power_dff[0]' -.measure tran total_leakage_power_dff -+ param = 'leakage_power_dff[0to0]' -.measure tran leakage_power_iopad[0] avg p(Vgvdd_iopad[0]) from=0 to='clock_period' -.measure tran leakage_power_iopad[1] avg p(Vgvdd_iopad[1]) from=0 to='clock_period' -.measure tran leakage_power_iopad[2] avg p(Vgvdd_iopad[2]) from=0 to='clock_period' -.measure tran leakage_power_iopad[3] avg p(Vgvdd_iopad[3]) from=0 to='clock_period' -.measure tran leakage_power_iopad[4] avg p(Vgvdd_iopad[4]) from=0 to='clock_period' -.measure tran leakage_power_iopad[5] avg p(Vgvdd_iopad[5]) from=0 to='clock_period' -.measure tran leakage_power_iopad[6] avg p(Vgvdd_iopad[6]) from=0 to='clock_period' -.measure tran leakage_power_iopad[7] avg p(Vgvdd_iopad[7]) from=0 to='clock_period' -.measure tran leakage_power_iopad[8] avg p(Vgvdd_iopad[8]) from=0 to='clock_period' -.measure tran leakage_power_iopad[9] avg p(Vgvdd_iopad[9]) from=0 to='clock_period' -.measure tran leakage_power_iopad[10] avg p(Vgvdd_iopad[10]) from=0 to='clock_period' -.measure tran leakage_power_iopad[11] avg p(Vgvdd_iopad[11]) from=0 to='clock_period' -.measure tran leakage_power_iopad[12] avg p(Vgvdd_iopad[12]) from=0 to='clock_period' -.measure tran leakage_power_iopad[13] avg p(Vgvdd_iopad[13]) from=0 to='clock_period' -.measure tran leakage_power_iopad[14] avg p(Vgvdd_iopad[14]) from=0 to='clock_period' -.measure tran leakage_power_iopad[15] avg p(Vgvdd_iopad[15]) from=0 to='clock_period' -.measure tran leakage_power_iopad[16] avg p(Vgvdd_iopad[16]) from=0 to='clock_period' -.measure tran leakage_power_iopad[17] avg p(Vgvdd_iopad[17]) from=0 to='clock_period' -.measure tran leakage_power_iopad[18] avg p(Vgvdd_iopad[18]) from=0 to='clock_period' -.measure tran leakage_power_iopad[19] avg p(Vgvdd_iopad[19]) from=0 to='clock_period' -.measure tran leakage_power_iopad[20] avg p(Vgvdd_iopad[20]) from=0 to='clock_period' -.measure tran leakage_power_iopad[21] avg p(Vgvdd_iopad[21]) from=0 to='clock_period' -.measure tran leakage_power_iopad[22] avg p(Vgvdd_iopad[22]) from=0 to='clock_period' -.measure tran leakage_power_iopad[23] avg p(Vgvdd_iopad[23]) from=0 to='clock_period' -.measure tran leakage_power_iopad[24] avg p(Vgvdd_iopad[24]) from=0 to='clock_period' -.measure tran leakage_power_iopad[25] avg p(Vgvdd_iopad[25]) from=0 to='clock_period' -.measure tran leakage_power_iopad[26] avg p(Vgvdd_iopad[26]) from=0 to='clock_period' -.measure tran leakage_power_iopad[27] avg p(Vgvdd_iopad[27]) from=0 to='clock_period' -.measure tran leakage_power_iopad[28] avg p(Vgvdd_iopad[28]) from=0 to='clock_period' -.measure tran leakage_power_iopad[29] avg p(Vgvdd_iopad[29]) from=0 to='clock_period' -.measure tran leakage_power_iopad[30] avg p(Vgvdd_iopad[30]) from=0 to='clock_period' -.measure tran leakage_power_iopad[31] avg p(Vgvdd_iopad[31]) from=0 to='clock_period' -.measure tran leakage_power_iopad[0to0] -+ param = 'leakage_power_iopad[0]' -.measure tran leakage_power_iopad[0to1] -+ param = 'leakage_power_iopad[1]+leakage_power_iopad[0to0]' -.measure tran leakage_power_iopad[0to2] -+ param = 'leakage_power_iopad[2]+leakage_power_iopad[0to1]' -.measure tran leakage_power_iopad[0to3] -+ param = 'leakage_power_iopad[3]+leakage_power_iopad[0to2]' -.measure tran leakage_power_iopad[0to4] -+ param = 'leakage_power_iopad[4]+leakage_power_iopad[0to3]' -.measure tran leakage_power_iopad[0to5] -+ param = 'leakage_power_iopad[5]+leakage_power_iopad[0to4]' -.measure tran leakage_power_iopad[0to6] -+ param = 'leakage_power_iopad[6]+leakage_power_iopad[0to5]' -.measure tran leakage_power_iopad[0to7] -+ param = 'leakage_power_iopad[7]+leakage_power_iopad[0to6]' -.measure tran leakage_power_iopad[0to8] -+ param = 'leakage_power_iopad[8]+leakage_power_iopad[0to7]' -.measure tran leakage_power_iopad[0to9] -+ param = 'leakage_power_iopad[9]+leakage_power_iopad[0to8]' -.measure tran leakage_power_iopad[0to10] -+ param = 'leakage_power_iopad[10]+leakage_power_iopad[0to9]' -.measure tran leakage_power_iopad[0to11] -+ param = 'leakage_power_iopad[11]+leakage_power_iopad[0to10]' -.measure tran leakage_power_iopad[0to12] -+ param = 'leakage_power_iopad[12]+leakage_power_iopad[0to11]' -.measure tran leakage_power_iopad[0to13] -+ param = 'leakage_power_iopad[13]+leakage_power_iopad[0to12]' -.measure tran leakage_power_iopad[0to14] -+ param = 'leakage_power_iopad[14]+leakage_power_iopad[0to13]' -.measure tran leakage_power_iopad[0to15] -+ param = 'leakage_power_iopad[15]+leakage_power_iopad[0to14]' -.measure tran leakage_power_iopad[0to16] -+ param = 'leakage_power_iopad[16]+leakage_power_iopad[0to15]' -.measure tran leakage_power_iopad[0to17] -+ param = 'leakage_power_iopad[17]+leakage_power_iopad[0to16]' -.measure tran leakage_power_iopad[0to18] -+ param = 'leakage_power_iopad[18]+leakage_power_iopad[0to17]' -.measure tran leakage_power_iopad[0to19] -+ param = 'leakage_power_iopad[19]+leakage_power_iopad[0to18]' -.measure tran leakage_power_iopad[0to20] -+ param = 'leakage_power_iopad[20]+leakage_power_iopad[0to19]' -.measure tran leakage_power_iopad[0to21] -+ param = 'leakage_power_iopad[21]+leakage_power_iopad[0to20]' -.measure tran leakage_power_iopad[0to22] -+ param = 'leakage_power_iopad[22]+leakage_power_iopad[0to21]' -.measure tran leakage_power_iopad[0to23] -+ param = 'leakage_power_iopad[23]+leakage_power_iopad[0to22]' -.measure tran leakage_power_iopad[0to24] -+ param = 'leakage_power_iopad[24]+leakage_power_iopad[0to23]' -.measure tran leakage_power_iopad[0to25] -+ param = 'leakage_power_iopad[25]+leakage_power_iopad[0to24]' -.measure tran leakage_power_iopad[0to26] -+ param = 'leakage_power_iopad[26]+leakage_power_iopad[0to25]' -.measure tran leakage_power_iopad[0to27] -+ param = 'leakage_power_iopad[27]+leakage_power_iopad[0to26]' -.measure tran leakage_power_iopad[0to28] -+ param = 'leakage_power_iopad[28]+leakage_power_iopad[0to27]' -.measure tran leakage_power_iopad[0to29] -+ param = 'leakage_power_iopad[29]+leakage_power_iopad[0to28]' -.measure tran leakage_power_iopad[0to30] -+ param = 'leakage_power_iopad[30]+leakage_power_iopad[0to29]' -.measure tran leakage_power_iopad[0to31] -+ param = 'leakage_power_iopad[31]+leakage_power_iopad[0to30]' -.measure tran total_leakage_power_iopad -+ param = 'leakage_power_iopad[0to31]' -***** Measure Leakage Power for Connection Boxes(CBs) ***** -.measure tran leakage_power_cbx[1][0] avg p(Vgvdd_cbx[1][0]) from=0 to='clock_period' -.measure tran leakage_power_cbx[1][1] avg p(Vgvdd_cbx[1][1]) from=0 to='clock_period' -.measure tran leakage_power_cby[0][1] avg p(Vgvdd_cby[0][1]) from=0 to='clock_period' -.measure tran leakage_power_cby[1][1] avg p(Vgvdd_cby[1][1]) from=0 to='clock_period' -***** Measure Total Leakage Power for Connection Boxes(CBs) ***** -.measure tran leakage_power_cbx[1to1][0to0] -+ param='leakage_power_cbx[1][0]' -.measure tran leakage_power_cbx[1to1][0to1] -+ param='leakage_power_cbx[1][1]+leakage_power_cbx[1to1][0to0]' -.measure tran leakage_power_cby[0to0][1to1] -+ param='leakage_power_cby[0][1]' -.measure tran leakage_power_cby[0to1][1to1] -+ param='leakage_power_cby[1][1]+leakage_power_cby[0to0][1to1]' -.measure tran leakage_power_cbs -+ param='leakage_power_cbx[1to1][0to1]+leakage_power_cby[0to1][1to1]' -***** Measure Leakage Power for Switch Boxes(SBs) ***** -.measure tran leakage_power_sb[0][0] avg p(Vgvdd_sb[0][0]) from=0 to='clock_period' -.measure tran leakage_power_sb[0][1] avg p(Vgvdd_sb[0][1]) from=0 to='clock_period' -.measure tran leakage_power_sb[1][0] avg p(Vgvdd_sb[1][0]) from=0 to='clock_period' -.measure tran leakage_power_sb[1][1] avg p(Vgvdd_sb[1][1]) from=0 to='clock_period' -***** Measure Total Leakage Power for Switch Boxes(SBs) ***** -.measure tran leakage_power_sb[0to0][0to0] -+ param='leakage_power_sb[0][0]' -.measure tran leakage_power_sb[0to0][0to1] -+ param='leakage_power_sb[0][1]+leakage_power_sb[0to0][0to0]' -.measure tran leakage_power_sb[0to1][0to0] -+ param='leakage_power_sb[1][0]+leakage_power_sb[0to0][0to1]' -.measure tran leakage_power_sb[0to1][0to1] -+ param='leakage_power_sb[1][1]+leakage_power_sb[0to1][0to0]' -.measure tran leakage_power_sbs -+ param='leakage_power_sb[0to1][0to1]' -.measure tran dynamic_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from='clock_period' to='7*clock_period' -.measure tran energy_per_cycle_sram_local_routing - + param='dynamic_power_sram_local_routing*clock_period' -.measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='7*clock_period' -.measure tran energy_per_cycle_sram_luts - + param='dynamic_power_sram_luts*clock_period' -.measure tran dynamic_power_sram_cbs avg p(Vgvdd_sram_cbs) from='clock_period' to='7*clock_period' -.measure tran energy_per_cycle_sram_cbs - + param='dynamic_power_sram_cbs*clock_period' -.measure tran dynamic_power_sram_sbs avg p(Vgvdd_sram_sbs) from='clock_period' to='7*clock_period' -.measure tran energy_per_cycle_sram_sbs - + param='dynamic_power_sram_sbs*clock_period' -.measure tran dynamic_power_iopad[0] avg p(Vgvdd_iopad[0]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[1] avg p(Vgvdd_iopad[1]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[2] avg p(Vgvdd_iopad[2]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[3] avg p(Vgvdd_iopad[3]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[4] avg p(Vgvdd_iopad[4]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[5] avg p(Vgvdd_iopad[5]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[6] avg p(Vgvdd_iopad[6]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[7] avg p(Vgvdd_iopad[7]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[8] avg p(Vgvdd_iopad[8]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[9] avg p(Vgvdd_iopad[9]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[10] avg p(Vgvdd_iopad[10]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[11] avg p(Vgvdd_iopad[11]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[12] avg p(Vgvdd_iopad[12]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[13] avg p(Vgvdd_iopad[13]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[14] avg p(Vgvdd_iopad[14]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[15] avg p(Vgvdd_iopad[15]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[16] avg p(Vgvdd_iopad[16]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[17] avg p(Vgvdd_iopad[17]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[18] avg p(Vgvdd_iopad[18]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[19] avg p(Vgvdd_iopad[19]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[20] avg p(Vgvdd_iopad[20]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[21] avg p(Vgvdd_iopad[21]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[22] avg p(Vgvdd_iopad[22]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[23] avg p(Vgvdd_iopad[23]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[24] avg p(Vgvdd_iopad[24]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[25] avg p(Vgvdd_iopad[25]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[26] avg p(Vgvdd_iopad[26]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[27] avg p(Vgvdd_iopad[27]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[28] avg p(Vgvdd_iopad[28]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[29] avg p(Vgvdd_iopad[29]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[30] avg p(Vgvdd_iopad[30]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[31] avg p(Vgvdd_iopad[31]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_iopad[0to0] -+ param = 'dynamic_power_iopad[0]' -.measure tran dynamic_power_iopad[0to1] -+ param = 'dynamic_power_iopad[1]+dynamic_power_iopad[0to0]' -.measure tran dynamic_power_iopad[0to2] -+ param = 'dynamic_power_iopad[2]+dynamic_power_iopad[0to1]' -.measure tran dynamic_power_iopad[0to3] -+ param = 'dynamic_power_iopad[3]+dynamic_power_iopad[0to2]' -.measure tran dynamic_power_iopad[0to4] -+ param = 'dynamic_power_iopad[4]+dynamic_power_iopad[0to3]' -.measure tran dynamic_power_iopad[0to5] -+ param = 'dynamic_power_iopad[5]+dynamic_power_iopad[0to4]' -.measure tran dynamic_power_iopad[0to6] -+ param = 'dynamic_power_iopad[6]+dynamic_power_iopad[0to5]' -.measure tran dynamic_power_iopad[0to7] -+ param = 'dynamic_power_iopad[7]+dynamic_power_iopad[0to6]' -.measure tran dynamic_power_iopad[0to8] -+ param = 'dynamic_power_iopad[8]+dynamic_power_iopad[0to7]' -.measure tran dynamic_power_iopad[0to9] -+ param = 'dynamic_power_iopad[9]+dynamic_power_iopad[0to8]' -.measure tran dynamic_power_iopad[0to10] -+ param = 'dynamic_power_iopad[10]+dynamic_power_iopad[0to9]' -.measure tran dynamic_power_iopad[0to11] -+ param = 'dynamic_power_iopad[11]+dynamic_power_iopad[0to10]' -.measure tran dynamic_power_iopad[0to12] -+ param = 'dynamic_power_iopad[12]+dynamic_power_iopad[0to11]' -.measure tran dynamic_power_iopad[0to13] -+ param = 'dynamic_power_iopad[13]+dynamic_power_iopad[0to12]' -.measure tran dynamic_power_iopad[0to14] -+ param = 'dynamic_power_iopad[14]+dynamic_power_iopad[0to13]' -.measure tran dynamic_power_iopad[0to15] -+ param = 'dynamic_power_iopad[15]+dynamic_power_iopad[0to14]' -.measure tran dynamic_power_iopad[0to16] -+ param = 'dynamic_power_iopad[16]+dynamic_power_iopad[0to15]' -.measure tran dynamic_power_iopad[0to17] -+ param = 'dynamic_power_iopad[17]+dynamic_power_iopad[0to16]' -.measure tran dynamic_power_iopad[0to18] -+ param = 'dynamic_power_iopad[18]+dynamic_power_iopad[0to17]' -.measure tran dynamic_power_iopad[0to19] -+ param = 'dynamic_power_iopad[19]+dynamic_power_iopad[0to18]' -.measure tran dynamic_power_iopad[0to20] -+ param = 'dynamic_power_iopad[20]+dynamic_power_iopad[0to19]' -.measure tran dynamic_power_iopad[0to21] -+ param = 'dynamic_power_iopad[21]+dynamic_power_iopad[0to20]' -.measure tran dynamic_power_iopad[0to22] -+ param = 'dynamic_power_iopad[22]+dynamic_power_iopad[0to21]' -.measure tran dynamic_power_iopad[0to23] -+ param = 'dynamic_power_iopad[23]+dynamic_power_iopad[0to22]' -.measure tran dynamic_power_iopad[0to24] -+ param = 'dynamic_power_iopad[24]+dynamic_power_iopad[0to23]' -.measure tran dynamic_power_iopad[0to25] -+ param = 'dynamic_power_iopad[25]+dynamic_power_iopad[0to24]' -.measure tran dynamic_power_iopad[0to26] -+ param = 'dynamic_power_iopad[26]+dynamic_power_iopad[0to25]' -.measure tran dynamic_power_iopad[0to27] -+ param = 'dynamic_power_iopad[27]+dynamic_power_iopad[0to26]' -.measure tran dynamic_power_iopad[0to28] -+ param = 'dynamic_power_iopad[28]+dynamic_power_iopad[0to27]' -.measure tran dynamic_power_iopad[0to29] -+ param = 'dynamic_power_iopad[29]+dynamic_power_iopad[0to28]' -.measure tran dynamic_power_iopad[0to30] -+ param = 'dynamic_power_iopad[30]+dynamic_power_iopad[0to29]' -.measure tran dynamic_power_iopad[0to31] -+ param = 'dynamic_power_iopad[31]+dynamic_power_iopad[0to30]' -.measure tran total_dynamic_power_iopad -+ param = 'dynamic_power_iopad[0to31]' -.measure tran total_energy_per_cycle_iopad -+ param = 'dynamic_power_iopad[0to31]*clock_period' -.measure tran dynamic_power_local_interc avg p(Vgvdd_local_interc) from='clock_period' to='7*clock_period' -.measure tran energy_per_cycle_local_routing - + param='dynamic_power_local_interc*clock_period' -.measure tran dynamic_power_direct_interc avg p(Vgvdd_direct_interc) from='clock_period' to='7*clock_period' -.measure tran energy_per_cycle_direct_interc - + param='dynamic_power_direct_interc*clock_period' -.measure tran dynamic_power_lut4[0] avg p(Vgvdd_lut4[0]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_lut4[0to0] -+ param = 'dynamic_power_lut4[0]' -.measure tran total_dynamic_power_lut4 -+ param = 'dynamic_power_lut4[0to0]' -.measure tran total_energy_per_cycle_lut4 -+ param = 'dynamic_power_lut4[0to0]*clock_period' -.measure tran dynamic_power_dff[0] avg p(Vgvdd_dff[0]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_dff[0to0] -+ param = 'dynamic_power_dff[0]' -.measure tran total_dynamic_power_dff -+ param = 'dynamic_power_dff[0to0]' -.measure tran total_energy_per_cycle_dff -+ param = 'dynamic_power_dff[0to0]*clock_period' -***** Measure Dynamic Power for Connection Boxes(CBs) ***** -.measure tran dynamic_power_cbx[1][0] avg p(Vgvdd_cbx[1][0]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_cbx[1][1] avg p(Vgvdd_cbx[1][1]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_cby[0][1] avg p(Vgvdd_cby[0][1]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_cby[1][1] avg p(Vgvdd_cby[1][1]) from='clock_period' to='7*clock_period' -***** Measure Total Dynamic Power for Connection Boxes(CBs) ***** -.measure tran dynamic_power_cbx[1to1][0to0] -+ param='dynamic_power_cbx[1][0]' -.measure tran dynamic_power_cbx[1to1][0to1] -+ param='dynamic_power_cbx[1][1]+dynamic_power_cbx[1to1][0to0]' -.measure tran dynamic_power_cby[0to0][1to1] -+ param='dynamic_power_cby[0][1]' -.measure tran dynamic_power_cby[0to1][1to1] -+ param='dynamic_power_cby[1][1]+dynamic_power_cby[0to0][1to1]' -.measure tran dynamic_power_cbs -+ param='dynamic_power_cbx[1to1][0to1]+dynamic_power_cby[0to1][1to1]' -.measure tran energy_per_cycle_cbs - + param='dynamic_power_cbs*clock_period' -***** Measure Dynamic Power for Switch Boxes(SBs) ***** -.measure tran dynamic_power_sb[0][0] avg p(Vgvdd_sb[0][0]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_sb[0][1] avg p(Vgvdd_sb[0][1]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_sb[1][0] avg p(Vgvdd_sb[1][0]) from='clock_period' to='7*clock_period' -.measure tran dynamic_power_sb[1][1] avg p(Vgvdd_sb[1][1]) from='clock_period' to='7*clock_period' -***** Measure Total Dynamic Power for Switch Boxes(SBs) ***** -.measure tran dynamic_power_sb[0to0][0to0] -+ param='dynamic_power_sb[0][0]' -.measure tran dynamic_power_sb[0to0][0to1] -+ param='dynamic_power_sb[0][1]+dynamic_power_sb[0to0][0to0]' -.measure tran dynamic_power_sb[0to1][0to0] -+ param='dynamic_power_sb[1][0]+dynamic_power_sb[0to0][0to1]' -.measure tran dynamic_power_sb[0to1][0to1] -+ param='dynamic_power_sb[1][1]+dynamic_power_sb[0to1][0to0]' -.measure tran dynamic_power_sbs -+ param='dynamic_power_sb[0to1][0to1]' -.measure tran energy_per_cycle_sbs - + param='dynamic_power_sbs*clock_period' -.end diff --git a/examples/spice_test_example_2/cb_mux_tb/example_2_cbx1_0_cbmux_testbench.sp b/examples/spice_test_example_2/cb_mux_tb/example_2_cbx1_0_cbmux_testbench.sp deleted file mode 100644 index 4741f8414..000000000 --- a/examples/spice_test_example_2/cb_mux_tb/example_2_cbx1_0_cbmux_testbench.sp +++ /dev/null @@ -1,2762 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_2level_tapbuf_size16[0] mux_2level_tapbuf_size16[0]->in[0] mux_2level_tapbuf_size16[0]->in[1] mux_2level_tapbuf_size16[0]->in[2] mux_2level_tapbuf_size16[0]->in[3] mux_2level_tapbuf_size16[0]->in[4] mux_2level_tapbuf_size16[0]->in[5] mux_2level_tapbuf_size16[0]->in[6] mux_2level_tapbuf_size16[0]->in[7] mux_2level_tapbuf_size16[0]->in[8] mux_2level_tapbuf_size16[0]->in[9] mux_2level_tapbuf_size16[0]->in[10] mux_2level_tapbuf_size16[0]->in[11] mux_2level_tapbuf_size16[0]->in[12] mux_2level_tapbuf_size16[0]->in[13] mux_2level_tapbuf_size16[0]->in[14] mux_2level_tapbuf_size16[0]->in[15] mux_2level_tapbuf_size16[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb sram[3]->out sram[3]->outb sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->out sram[6]->outb sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size16[0] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_2level_tapbuf_size16[0]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[0] mux_2level_tapbuf_size16[0]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[1] mux_2level_tapbuf_size16[0]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[0]->in[2] mux_2level_tapbuf_size16[0]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[0]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[0]->in[3] mux_2level_tapbuf_size16[0]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[0]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[4] mux_2level_tapbuf_size16[0]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[5] mux_2level_tapbuf_size16[0]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[6] mux_2level_tapbuf_size16[0]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[7] mux_2level_tapbuf_size16[0]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[8] mux_2level_tapbuf_size16[0]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[9] mux_2level_tapbuf_size16[0]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[10] mux_2level_tapbuf_size16[0]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[11] mux_2level_tapbuf_size16[0]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[12] mux_2level_tapbuf_size16[0]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[13] mux_2level_tapbuf_size16[0]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[14] mux_2level_tapbuf_size16[0]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[15] mux_2level_tapbuf_size16[0]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[0] gvdd_mux_2level_tapbuf_size16[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[78] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[78] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[78] when v(mux_2level_tapbuf_size16[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[78] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[78] when v(mux_2level_tapbuf_size16[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[78] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[78] param='mux_2level_tapbuf_size16[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[0]_energy_per_cycle param='mux_2level_tapbuf_size16[0]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[78] param='mux_2level_tapbuf_size16[0]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[78] param='dynamic_power_cb_mux[1][0]_rrnode[78]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[78] avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='start_rise_cb_mux[1][0]_rrnode[78]' to='start_rise_cb_mux[1][0]_rrnode[78]+switch_rise_cb_mux[1][0]_rrnode[78]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[78] avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='start_fall_cb_mux[1][0]_rrnode[78]' to='start_fall_cb_mux[1][0]_rrnode[78]+switch_fall_cb_mux[1][0]_rrnode[78]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_cb_mux[1][0]_rrnode[78]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][0]_rrnode[78]' -******* Normal TYPE loads ******* -Xload_inv[0]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[31]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to0] -+ param='leakage_cb_mux[1][0]_rrnode[78]' -.meas tran sum_energy_per_cycle_cb_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][0]_rrnode[78]' -Xmux_2level_tapbuf_size16[1] mux_2level_tapbuf_size16[1]->in[0] mux_2level_tapbuf_size16[1]->in[1] mux_2level_tapbuf_size16[1]->in[2] mux_2level_tapbuf_size16[1]->in[3] mux_2level_tapbuf_size16[1]->in[4] mux_2level_tapbuf_size16[1]->in[5] mux_2level_tapbuf_size16[1]->in[6] mux_2level_tapbuf_size16[1]->in[7] mux_2level_tapbuf_size16[1]->in[8] mux_2level_tapbuf_size16[1]->in[9] mux_2level_tapbuf_size16[1]->in[10] mux_2level_tapbuf_size16[1]->in[11] mux_2level_tapbuf_size16[1]->in[12] mux_2level_tapbuf_size16[1]->in[13] mux_2level_tapbuf_size16[1]->in[14] mux_2level_tapbuf_size16[1]->in[15] mux_2level_tapbuf_size16[1]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->out sram[10]->outb sram[11]->out sram[11]->outb sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->out sram[14]->outb sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size16[1] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_2level_tapbuf_size16[1]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[0] mux_2level_tapbuf_size16[1]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[1] mux_2level_tapbuf_size16[1]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[1]->in[2] mux_2level_tapbuf_size16[1]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[1]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[1]->in[3] mux_2level_tapbuf_size16[1]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[1]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[4] mux_2level_tapbuf_size16[1]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[5] mux_2level_tapbuf_size16[1]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[6] mux_2level_tapbuf_size16[1]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[7] mux_2level_tapbuf_size16[1]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[8] mux_2level_tapbuf_size16[1]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[9] mux_2level_tapbuf_size16[1]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[10] mux_2level_tapbuf_size16[1]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[11] mux_2level_tapbuf_size16[1]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[12] mux_2level_tapbuf_size16[1]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[13] mux_2level_tapbuf_size16[1]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[14] mux_2level_tapbuf_size16[1]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[15] mux_2level_tapbuf_size16[1]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[1] gvdd_mux_2level_tapbuf_size16[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[82] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[82] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[82] when v(mux_2level_tapbuf_size16[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[82] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[82] when v(mux_2level_tapbuf_size16[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[82] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[82] param='mux_2level_tapbuf_size16[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[1]_energy_per_cycle param='mux_2level_tapbuf_size16[1]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[82] param='mux_2level_tapbuf_size16[1]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[82] param='dynamic_power_cb_mux[1][0]_rrnode[82]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[82] avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='start_rise_cb_mux[1][0]_rrnode[82]' to='start_rise_cb_mux[1][0]_rrnode[82]+switch_rise_cb_mux[1][0]_rrnode[82]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[82] avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='start_fall_cb_mux[1][0]_rrnode[82]' to='start_fall_cb_mux[1][0]_rrnode[82]+switch_fall_cb_mux[1][0]_rrnode[82]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[1][0]_rrnode[82]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[1][0]_rrnode[82]' -******* Normal TYPE loads ******* -Xload_inv[60]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[78]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[109]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[112]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to1] -+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[1][0]_rrnode[82]' -.meas tran sum_energy_per_cycle_cb_mux[0to1] -+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[1][0]_rrnode[82]' -Xmux_2level_tapbuf_size16[2] mux_2level_tapbuf_size16[2]->in[0] mux_2level_tapbuf_size16[2]->in[1] mux_2level_tapbuf_size16[2]->in[2] mux_2level_tapbuf_size16[2]->in[3] mux_2level_tapbuf_size16[2]->in[4] mux_2level_tapbuf_size16[2]->in[5] mux_2level_tapbuf_size16[2]->in[6] mux_2level_tapbuf_size16[2]->in[7] mux_2level_tapbuf_size16[2]->in[8] mux_2level_tapbuf_size16[2]->in[9] mux_2level_tapbuf_size16[2]->in[10] mux_2level_tapbuf_size16[2]->in[11] mux_2level_tapbuf_size16[2]->in[12] mux_2level_tapbuf_size16[2]->in[13] mux_2level_tapbuf_size16[2]->in[14] mux_2level_tapbuf_size16[2]->in[15] mux_2level_tapbuf_size16[2]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->out sram[18]->outb sram[19]->out sram[19]->outb sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->out sram[22]->outb sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size16[2] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_2level_tapbuf_size16[2]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[0] mux_2level_tapbuf_size16[2]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[1] mux_2level_tapbuf_size16[2]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[2]->in[2] mux_2level_tapbuf_size16[2]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[2]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[2]->in[3] mux_2level_tapbuf_size16[2]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[2]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[4] mux_2level_tapbuf_size16[2]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[5] mux_2level_tapbuf_size16[2]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[6] mux_2level_tapbuf_size16[2]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[7] mux_2level_tapbuf_size16[2]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[8] mux_2level_tapbuf_size16[2]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[9] mux_2level_tapbuf_size16[2]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[10] mux_2level_tapbuf_size16[2]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[11] mux_2level_tapbuf_size16[2]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[12] mux_2level_tapbuf_size16[2]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[13] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[2]->in[13] mux_2level_tapbuf_size16[2]->in[13] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[2]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[14] mux_2level_tapbuf_size16[2]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[15] mux_2level_tapbuf_size16[2]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[2] gvdd_mux_2level_tapbuf_size16[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[86] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[86] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[86] when v(mux_2level_tapbuf_size16[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[86] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[86] when v(mux_2level_tapbuf_size16[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[86] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[86] param='mux_2level_tapbuf_size16[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[2]_energy_per_cycle param='mux_2level_tapbuf_size16[2]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[86] param='mux_2level_tapbuf_size16[2]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[86] param='dynamic_power_cb_mux[1][0]_rrnode[86]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[86] avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='start_rise_cb_mux[1][0]_rrnode[86]' to='start_rise_cb_mux[1][0]_rrnode[86]+switch_rise_cb_mux[1][0]_rrnode[86]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[86] avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='start_fall_cb_mux[1][0]_rrnode[86]' to='start_fall_cb_mux[1][0]_rrnode[86]+switch_fall_cb_mux[1][0]_rrnode[86]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[1][0]_rrnode[86]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[1][0]_rrnode[86]' -******* Normal TYPE loads ******* -Xload_inv[120]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[125]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[128]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[130]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to2] -+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[1][0]_rrnode[86]' -.meas tran sum_energy_per_cycle_cb_mux[0to2] -+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[1][0]_rrnode[86]' -Xmux_2level_tapbuf_size16[3] mux_2level_tapbuf_size16[3]->in[0] mux_2level_tapbuf_size16[3]->in[1] mux_2level_tapbuf_size16[3]->in[2] mux_2level_tapbuf_size16[3]->in[3] mux_2level_tapbuf_size16[3]->in[4] mux_2level_tapbuf_size16[3]->in[5] mux_2level_tapbuf_size16[3]->in[6] mux_2level_tapbuf_size16[3]->in[7] mux_2level_tapbuf_size16[3]->in[8] mux_2level_tapbuf_size16[3]->in[9] mux_2level_tapbuf_size16[3]->in[10] mux_2level_tapbuf_size16[3]->in[11] mux_2level_tapbuf_size16[3]->in[12] mux_2level_tapbuf_size16[3]->in[13] mux_2level_tapbuf_size16[3]->in[14] mux_2level_tapbuf_size16[3]->in[15] mux_2level_tapbuf_size16[3]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->out sram[26]->outb sram[27]->out sram[27]->outb sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->out sram[30]->outb sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size16[3] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_2level_tapbuf_size16[3]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[0] mux_2level_tapbuf_size16[3]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[1] mux_2level_tapbuf_size16[3]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[3]->in[2] mux_2level_tapbuf_size16[3]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[3]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[3]->in[3] mux_2level_tapbuf_size16[3]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[3]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[4] mux_2level_tapbuf_size16[3]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[5] mux_2level_tapbuf_size16[3]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[6] mux_2level_tapbuf_size16[3]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[7] mux_2level_tapbuf_size16[3]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[8] mux_2level_tapbuf_size16[3]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[9] mux_2level_tapbuf_size16[3]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[10] mux_2level_tapbuf_size16[3]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[11] mux_2level_tapbuf_size16[3]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[12] mux_2level_tapbuf_size16[3]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[13] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[3]->in[13] mux_2level_tapbuf_size16[3]->in[13] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[3]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[14] mux_2level_tapbuf_size16[3]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[15] mux_2level_tapbuf_size16[3]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[3] gvdd_mux_2level_tapbuf_size16[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[90] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[90] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[90] when v(mux_2level_tapbuf_size16[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[90] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[90] when v(mux_2level_tapbuf_size16[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[90] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[90] param='mux_2level_tapbuf_size16[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[3]_energy_per_cycle param='mux_2level_tapbuf_size16[3]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[90] param='mux_2level_tapbuf_size16[3]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[90] param='dynamic_power_cb_mux[1][0]_rrnode[90]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[90] avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='start_rise_cb_mux[1][0]_rrnode[90]' to='start_rise_cb_mux[1][0]_rrnode[90]+switch_rise_cb_mux[1][0]_rrnode[90]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[90] avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='start_fall_cb_mux[1][0]_rrnode[90]' to='start_fall_cb_mux[1][0]_rrnode[90]+switch_fall_cb_mux[1][0]_rrnode[90]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[1][0]_rrnode[90]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[1][0]_rrnode[90]' -******* Normal TYPE loads ******* -Xload_inv[180]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to3] -+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[1][0]_rrnode[90]' -.meas tran sum_energy_per_cycle_cb_mux[0to3] -+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[1][0]_rrnode[90]' -Xmux_2level_tapbuf_size16[4] mux_2level_tapbuf_size16[4]->in[0] mux_2level_tapbuf_size16[4]->in[1] mux_2level_tapbuf_size16[4]->in[2] mux_2level_tapbuf_size16[4]->in[3] mux_2level_tapbuf_size16[4]->in[4] mux_2level_tapbuf_size16[4]->in[5] mux_2level_tapbuf_size16[4]->in[6] mux_2level_tapbuf_size16[4]->in[7] mux_2level_tapbuf_size16[4]->in[8] mux_2level_tapbuf_size16[4]->in[9] mux_2level_tapbuf_size16[4]->in[10] mux_2level_tapbuf_size16[4]->in[11] mux_2level_tapbuf_size16[4]->in[12] mux_2level_tapbuf_size16[4]->in[13] mux_2level_tapbuf_size16[4]->in[14] mux_2level_tapbuf_size16[4]->in[15] mux_2level_tapbuf_size16[4]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->out sram[34]->outb sram[35]->out sram[35]->outb sram[36]->outb sram[36]->out sram[37]->out sram[37]->outb sram[38]->out sram[38]->outb sram[39]->out sram[39]->outb gvdd_mux_2level_tapbuf_size16[4] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -***** Signal mux_2level_tapbuf_size16[4]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[0] mux_2level_tapbuf_size16[4]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[1] mux_2level_tapbuf_size16[4]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[4]->in[2] mux_2level_tapbuf_size16[4]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[4]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[4]->in[3] mux_2level_tapbuf_size16[4]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[4]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[4] mux_2level_tapbuf_size16[4]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[5] mux_2level_tapbuf_size16[4]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[6] mux_2level_tapbuf_size16[4]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[7] mux_2level_tapbuf_size16[4]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[8] mux_2level_tapbuf_size16[4]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[9] mux_2level_tapbuf_size16[4]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[10] mux_2level_tapbuf_size16[4]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[11] mux_2level_tapbuf_size16[4]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[12] mux_2level_tapbuf_size16[4]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[13] mux_2level_tapbuf_size16[4]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[14] mux_2level_tapbuf_size16[4]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[15] mux_2level_tapbuf_size16[4]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[4] gvdd_mux_2level_tapbuf_size16[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[94] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[94] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[94] when v(mux_2level_tapbuf_size16[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[94] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[94] when v(mux_2level_tapbuf_size16[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[94] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[94] param='mux_2level_tapbuf_size16[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[4]_energy_per_cycle param='mux_2level_tapbuf_size16[4]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[94] param='mux_2level_tapbuf_size16[4]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[94] param='dynamic_power_cb_mux[1][0]_rrnode[94]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[94] avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='start_rise_cb_mux[1][0]_rrnode[94]' to='start_rise_cb_mux[1][0]_rrnode[94]+switch_rise_cb_mux[1][0]_rrnode[94]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[94] avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='start_fall_cb_mux[1][0]_rrnode[94]' to='start_fall_cb_mux[1][0]_rrnode[94]+switch_fall_cb_mux[1][0]_rrnode[94]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[1][0]_rrnode[94]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[1][0]_rrnode[94]' -******* Normal TYPE loads ******* -Xload_inv[240]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to4] -+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[1][0]_rrnode[94]' -.meas tran sum_energy_per_cycle_cb_mux[0to4] -+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[1][0]_rrnode[94]' -Xmux_2level_tapbuf_size16[5] mux_2level_tapbuf_size16[5]->in[0] mux_2level_tapbuf_size16[5]->in[1] mux_2level_tapbuf_size16[5]->in[2] mux_2level_tapbuf_size16[5]->in[3] mux_2level_tapbuf_size16[5]->in[4] mux_2level_tapbuf_size16[5]->in[5] mux_2level_tapbuf_size16[5]->in[6] mux_2level_tapbuf_size16[5]->in[7] mux_2level_tapbuf_size16[5]->in[8] mux_2level_tapbuf_size16[5]->in[9] mux_2level_tapbuf_size16[5]->in[10] mux_2level_tapbuf_size16[5]->in[11] mux_2level_tapbuf_size16[5]->in[12] mux_2level_tapbuf_size16[5]->in[13] mux_2level_tapbuf_size16[5]->in[14] mux_2level_tapbuf_size16[5]->in[15] mux_2level_tapbuf_size16[5]->out sram[40]->outb sram[40]->out sram[41]->out sram[41]->outb sram[42]->out sram[42]->outb sram[43]->out sram[43]->outb sram[44]->out sram[44]->outb sram[45]->out sram[45]->outb sram[46]->out sram[46]->outb sram[47]->outb sram[47]->out gvdd_mux_2level_tapbuf_size16[5] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[5], level=2, select_path_id=3. ***** -*****10000001***** -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -***** Signal mux_2level_tapbuf_size16[5]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[0] mux_2level_tapbuf_size16[5]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[1] mux_2level_tapbuf_size16[5]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[5]->in[2] mux_2level_tapbuf_size16[5]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[5]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[5]->in[3] mux_2level_tapbuf_size16[5]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[5]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[4] mux_2level_tapbuf_size16[5]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[5] mux_2level_tapbuf_size16[5]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[6] mux_2level_tapbuf_size16[5]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[7] mux_2level_tapbuf_size16[5]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[8] mux_2level_tapbuf_size16[5]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[9] mux_2level_tapbuf_size16[5]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[10] mux_2level_tapbuf_size16[5]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[11] mux_2level_tapbuf_size16[5]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[12] mux_2level_tapbuf_size16[5]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[13] mux_2level_tapbuf_size16[5]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[14] mux_2level_tapbuf_size16[5]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[15] mux_2level_tapbuf_size16[5]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[5] gvdd_mux_2level_tapbuf_size16[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[98] trig v(mux_2level_tapbuf_size16[5]->in[3]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[98] trig v(mux_2level_tapbuf_size16[5]->in[3]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[98] when v(mux_2level_tapbuf_size16[5]->in[3])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[98] trig v(mux_2level_tapbuf_size16[5]->in[3]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[98] when v(mux_2level_tapbuf_size16[5]->in[3])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[98] trig v(mux_2level_tapbuf_size16[5]->in[3]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[98] param='mux_2level_tapbuf_size16[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[5]_energy_per_cycle param='mux_2level_tapbuf_size16[5]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[98] param='mux_2level_tapbuf_size16[5]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[98] param='dynamic_power_cb_mux[1][0]_rrnode[98]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[98] avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='start_rise_cb_mux[1][0]_rrnode[98]' to='start_rise_cb_mux[1][0]_rrnode[98]+switch_rise_cb_mux[1][0]_rrnode[98]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[98] avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='start_fall_cb_mux[1][0]_rrnode[98]' to='start_fall_cb_mux[1][0]_rrnode[98]+switch_fall_cb_mux[1][0]_rrnode[98]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[1][0]_rrnode[98]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[1][0]_rrnode[98]' -******* Normal TYPE loads ******* -Xload_inv[300]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[326]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[330]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[333]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[335]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[338]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[342]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[345]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[357]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to5] -+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[1][0]_rrnode[98]' -.meas tran sum_energy_per_cycle_cb_mux[0to5] -+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[1][0]_rrnode[98]' -Xmux_2level_tapbuf_size16[6] mux_2level_tapbuf_size16[6]->in[0] mux_2level_tapbuf_size16[6]->in[1] mux_2level_tapbuf_size16[6]->in[2] mux_2level_tapbuf_size16[6]->in[3] mux_2level_tapbuf_size16[6]->in[4] mux_2level_tapbuf_size16[6]->in[5] mux_2level_tapbuf_size16[6]->in[6] mux_2level_tapbuf_size16[6]->in[7] mux_2level_tapbuf_size16[6]->in[8] mux_2level_tapbuf_size16[6]->in[9] mux_2level_tapbuf_size16[6]->in[10] mux_2level_tapbuf_size16[6]->in[11] mux_2level_tapbuf_size16[6]->in[12] mux_2level_tapbuf_size16[6]->in[13] mux_2level_tapbuf_size16[6]->in[14] mux_2level_tapbuf_size16[6]->in[15] mux_2level_tapbuf_size16[6]->out sram[48]->outb sram[48]->out sram[49]->out sram[49]->outb sram[50]->out sram[50]->outb sram[51]->out sram[51]->outb sram[52]->outb sram[52]->out sram[53]->out sram[53]->outb sram[54]->out sram[54]->outb sram[55]->out sram[55]->outb gvdd_mux_2level_tapbuf_size16[6] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -***** Signal mux_2level_tapbuf_size16[6]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[0] mux_2level_tapbuf_size16[6]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[1] mux_2level_tapbuf_size16[6]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[2] mux_2level_tapbuf_size16[6]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[3] mux_2level_tapbuf_size16[6]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[4] mux_2level_tapbuf_size16[6]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[5] mux_2level_tapbuf_size16[6]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[6] mux_2level_tapbuf_size16[6]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[7] mux_2level_tapbuf_size16[6]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[8] mux_2level_tapbuf_size16[6]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[9] mux_2level_tapbuf_size16[6]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[10] mux_2level_tapbuf_size16[6]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[11] mux_2level_tapbuf_size16[6]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[12] mux_2level_tapbuf_size16[6]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[13] mux_2level_tapbuf_size16[6]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[14] mux_2level_tapbuf_size16[6]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[15] mux_2level_tapbuf_size16[6]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[6] gvdd_mux_2level_tapbuf_size16[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[102] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[102] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[102] when v(mux_2level_tapbuf_size16[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[102] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[102] when v(mux_2level_tapbuf_size16[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[102] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[102] param='mux_2level_tapbuf_size16[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[6]_energy_per_cycle param='mux_2level_tapbuf_size16[6]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[102] param='mux_2level_tapbuf_size16[6]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[102] param='dynamic_power_cb_mux[1][0]_rrnode[102]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[102] avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='start_rise_cb_mux[1][0]_rrnode[102]' to='start_rise_cb_mux[1][0]_rrnode[102]+switch_rise_cb_mux[1][0]_rrnode[102]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[102] avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='start_fall_cb_mux[1][0]_rrnode[102]' to='start_fall_cb_mux[1][0]_rrnode[102]+switch_fall_cb_mux[1][0]_rrnode[102]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[1][0]_rrnode[102]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[1][0]_rrnode[102]' -******* Normal TYPE loads ******* -Xload_inv[360]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[365]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[369]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[381]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[384]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[388]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[389]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[390]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[391]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[392]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[393]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[394]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[395]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[396]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[397]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[398]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[399]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[400]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[401]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[402]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[403]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[404]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[405]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[406]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[407]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[408]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[409]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[410]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[411]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[412]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[413]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[414]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[415]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[416]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[417]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[418]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[419]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to6] -+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[1][0]_rrnode[102]' -.meas tran sum_energy_per_cycle_cb_mux[0to6] -+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[1][0]_rrnode[102]' -Xmux_2level_tapbuf_size16[7] mux_2level_tapbuf_size16[7]->in[0] mux_2level_tapbuf_size16[7]->in[1] mux_2level_tapbuf_size16[7]->in[2] mux_2level_tapbuf_size16[7]->in[3] mux_2level_tapbuf_size16[7]->in[4] mux_2level_tapbuf_size16[7]->in[5] mux_2level_tapbuf_size16[7]->in[6] mux_2level_tapbuf_size16[7]->in[7] mux_2level_tapbuf_size16[7]->in[8] mux_2level_tapbuf_size16[7]->in[9] mux_2level_tapbuf_size16[7]->in[10] mux_2level_tapbuf_size16[7]->in[11] mux_2level_tapbuf_size16[7]->in[12] mux_2level_tapbuf_size16[7]->in[13] mux_2level_tapbuf_size16[7]->in[14] mux_2level_tapbuf_size16[7]->in[15] mux_2level_tapbuf_size16[7]->out sram[56]->outb sram[56]->out sram[57]->out sram[57]->outb sram[58]->out sram[58]->outb sram[59]->out sram[59]->outb sram[60]->outb sram[60]->out sram[61]->out sram[61]->outb sram[62]->out sram[62]->outb sram[63]->out sram[63]->outb gvdd_mux_2level_tapbuf_size16[7] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -***** Signal mux_2level_tapbuf_size16[7]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[0] mux_2level_tapbuf_size16[7]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[1] mux_2level_tapbuf_size16[7]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[2] mux_2level_tapbuf_size16[7]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[3] mux_2level_tapbuf_size16[7]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[4] mux_2level_tapbuf_size16[7]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[5] mux_2level_tapbuf_size16[7]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[6] mux_2level_tapbuf_size16[7]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[7] mux_2level_tapbuf_size16[7]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[8] mux_2level_tapbuf_size16[7]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[9] mux_2level_tapbuf_size16[7]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[10] mux_2level_tapbuf_size16[7]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[11] mux_2level_tapbuf_size16[7]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[12] mux_2level_tapbuf_size16[7]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[13] mux_2level_tapbuf_size16[7]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[14] mux_2level_tapbuf_size16[7]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[15] mux_2level_tapbuf_size16[7]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[7] gvdd_mux_2level_tapbuf_size16[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[106] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[106] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[106] when v(mux_2level_tapbuf_size16[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[106] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[106] when v(mux_2level_tapbuf_size16[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[106] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[106] param='mux_2level_tapbuf_size16[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[7]_energy_per_cycle param='mux_2level_tapbuf_size16[7]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[106] param='mux_2level_tapbuf_size16[7]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[106] param='dynamic_power_cb_mux[1][0]_rrnode[106]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[106] avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='start_rise_cb_mux[1][0]_rrnode[106]' to='start_rise_cb_mux[1][0]_rrnode[106]+switch_rise_cb_mux[1][0]_rrnode[106]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[106] avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='start_fall_cb_mux[1][0]_rrnode[106]' to='start_fall_cb_mux[1][0]_rrnode[106]+switch_fall_cb_mux[1][0]_rrnode[106]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[1][0]_rrnode[106]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[1][0]_rrnode[106]' -******* Normal TYPE loads ******* -Xload_inv[420]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[421]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[422]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[423]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[424]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[425]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[426]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[427]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[428]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[429]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[430]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[431]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[432]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[433]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[434]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[435]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[436]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[437]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[438]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[439]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[440]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[441]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[442]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[443]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[444]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[445]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[446]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[447]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[448]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[449]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[450]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[451]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[452]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[453]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[454]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[455]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[456]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[457]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[458]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[459]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[460]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[461]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[462]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[463]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[464]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[465]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[466]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[467]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[468]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[469]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[470]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[471]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[472]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[473]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[474]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[475]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[476]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[477]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[478]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[479]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to7] -+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[1][0]_rrnode[106]' -.meas tran sum_energy_per_cycle_cb_mux[0to7] -+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[1][0]_rrnode[106]' -Xmux_2level_tapbuf_size16[8] mux_2level_tapbuf_size16[8]->in[0] mux_2level_tapbuf_size16[8]->in[1] mux_2level_tapbuf_size16[8]->in[2] mux_2level_tapbuf_size16[8]->in[3] mux_2level_tapbuf_size16[8]->in[4] mux_2level_tapbuf_size16[8]->in[5] mux_2level_tapbuf_size16[8]->in[6] mux_2level_tapbuf_size16[8]->in[7] mux_2level_tapbuf_size16[8]->in[8] mux_2level_tapbuf_size16[8]->in[9] mux_2level_tapbuf_size16[8]->in[10] mux_2level_tapbuf_size16[8]->in[11] mux_2level_tapbuf_size16[8]->in[12] mux_2level_tapbuf_size16[8]->in[13] mux_2level_tapbuf_size16[8]->in[14] mux_2level_tapbuf_size16[8]->in[15] mux_2level_tapbuf_size16[8]->out sram[64]->outb sram[64]->out sram[65]->out sram[65]->outb sram[66]->out sram[66]->outb sram[67]->out sram[67]->outb sram[68]->outb sram[68]->out sram[69]->out sram[69]->outb sram[70]->out sram[70]->outb sram[71]->out sram[71]->outb gvdd_mux_2level_tapbuf_size16[8] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -***** Signal mux_2level_tapbuf_size16[8]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[8]->in[0] mux_2level_tapbuf_size16[8]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[8]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[8]->in[1] mux_2level_tapbuf_size16[8]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[8]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[2] mux_2level_tapbuf_size16[8]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[3] mux_2level_tapbuf_size16[8]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[4] mux_2level_tapbuf_size16[8]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[5] mux_2level_tapbuf_size16[8]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[6] mux_2level_tapbuf_size16[8]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[7] mux_2level_tapbuf_size16[8]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[8] mux_2level_tapbuf_size16[8]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[9] mux_2level_tapbuf_size16[8]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[10] mux_2level_tapbuf_size16[8]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[11] mux_2level_tapbuf_size16[8]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[12] mux_2level_tapbuf_size16[8]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[13] mux_2level_tapbuf_size16[8]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[14] mux_2level_tapbuf_size16[8]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[15] mux_2level_tapbuf_size16[8]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[8] gvdd_mux_2level_tapbuf_size16[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[110] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[110] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[110] when v(mux_2level_tapbuf_size16[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[110] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[110] when v(mux_2level_tapbuf_size16[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[110] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[110] param='mux_2level_tapbuf_size16[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[8]_energy_per_cycle param='mux_2level_tapbuf_size16[8]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[110] param='mux_2level_tapbuf_size16[8]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[110] param='dynamic_power_cb_mux[1][0]_rrnode[110]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[110] avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='start_rise_cb_mux[1][0]_rrnode[110]' to='start_rise_cb_mux[1][0]_rrnode[110]+switch_rise_cb_mux[1][0]_rrnode[110]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[110] avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='start_fall_cb_mux[1][0]_rrnode[110]' to='start_fall_cb_mux[1][0]_rrnode[110]+switch_fall_cb_mux[1][0]_rrnode[110]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[1][0]_rrnode[110]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[1][0]_rrnode[110]' -******* Normal TYPE loads ******* -Xload_inv[480]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[481]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[482]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[483]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[484]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[485]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[486]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[487]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[488]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[489]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[490]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[491]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[492]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[493]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[494]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[495]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[496]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[497]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[498]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[499]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[500]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[501]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[502]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[503]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[504]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[505]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[506]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[507]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[508]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[509]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[510]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[511]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[512]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[513]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[514]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[515]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[516]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[517]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[518]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[519]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[520]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[521]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[522]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[523]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[524]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[525]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[526]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[527]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[528]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[529]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[530]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[531]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[532]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[533]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[534]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[535]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[536]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[537]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[538]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[539]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to8] -+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[1][0]_rrnode[110]' -.meas tran sum_energy_per_cycle_cb_mux[0to8] -+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[1][0]_rrnode[110]' -Xmux_2level_tapbuf_size16[9] mux_2level_tapbuf_size16[9]->in[0] mux_2level_tapbuf_size16[9]->in[1] mux_2level_tapbuf_size16[9]->in[2] mux_2level_tapbuf_size16[9]->in[3] mux_2level_tapbuf_size16[9]->in[4] mux_2level_tapbuf_size16[9]->in[5] mux_2level_tapbuf_size16[9]->in[6] mux_2level_tapbuf_size16[9]->in[7] mux_2level_tapbuf_size16[9]->in[8] mux_2level_tapbuf_size16[9]->in[9] mux_2level_tapbuf_size16[9]->in[10] mux_2level_tapbuf_size16[9]->in[11] mux_2level_tapbuf_size16[9]->in[12] mux_2level_tapbuf_size16[9]->in[13] mux_2level_tapbuf_size16[9]->in[14] mux_2level_tapbuf_size16[9]->in[15] mux_2level_tapbuf_size16[9]->out sram[72]->outb sram[72]->out sram[73]->out sram[73]->outb sram[74]->out sram[74]->outb sram[75]->out sram[75]->outb sram[76]->outb sram[76]->out sram[77]->out sram[77]->outb sram[78]->out sram[78]->outb sram[79]->out sram[79]->outb gvdd_mux_2level_tapbuf_size16[9] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[9], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -***** Signal mux_2level_tapbuf_size16[9]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[9]->in[0] mux_2level_tapbuf_size16[9]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[9]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[9]->in[1] mux_2level_tapbuf_size16[9]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[9]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[2] mux_2level_tapbuf_size16[9]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[3] mux_2level_tapbuf_size16[9]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[4] mux_2level_tapbuf_size16[9]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[5] mux_2level_tapbuf_size16[9]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[6] mux_2level_tapbuf_size16[9]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[7] mux_2level_tapbuf_size16[9]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[8] mux_2level_tapbuf_size16[9]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[9] mux_2level_tapbuf_size16[9]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[10] mux_2level_tapbuf_size16[9]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[11] mux_2level_tapbuf_size16[9]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[12] mux_2level_tapbuf_size16[9]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[13] mux_2level_tapbuf_size16[9]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[14] mux_2level_tapbuf_size16[9]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[15] mux_2level_tapbuf_size16[9]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[9] gvdd_mux_2level_tapbuf_size16[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[114] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[114] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[114] when v(mux_2level_tapbuf_size16[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[114] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[114] when v(mux_2level_tapbuf_size16[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[114] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[9]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[114] param='mux_2level_tapbuf_size16[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[9]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[9]_energy_per_cycle param='mux_2level_tapbuf_size16[9]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[114] param='mux_2level_tapbuf_size16[9]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[114] param='dynamic_power_cb_mux[1][0]_rrnode[114]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[114] avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='start_rise_cb_mux[1][0]_rrnode[114]' to='start_rise_cb_mux[1][0]_rrnode[114]+switch_rise_cb_mux[1][0]_rrnode[114]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[114] avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='start_fall_cb_mux[1][0]_rrnode[114]' to='start_fall_cb_mux[1][0]_rrnode[114]+switch_fall_cb_mux[1][0]_rrnode[114]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_cb_mux[1][0]_rrnode[114]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_cb_mux[1][0]_rrnode[114]' -******* Normal TYPE loads ******* -Xload_inv[540]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[541]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[542]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[543]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[544]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[545]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[546]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[547]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[548]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[549]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[550]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[551]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[552]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[553]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[554]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[555]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[556]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[557]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[558]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[559]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[560]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[561]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[562]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[563]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[564]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[565]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[566]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[567]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[568]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[569]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[570]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[571]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[572]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[573]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[574]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[575]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[576]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[577]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[578]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[579]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[580]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[581]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[582]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[583]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[584]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[585]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[586]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[587]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[588]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[589]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[590]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[591]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[592]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[593]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[594]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[595]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[596]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[597]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[598]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[599]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to9] -+ param='sum_leakage_power_cb_mux[0to8]+leakage_cb_mux[1][0]_rrnode[114]' -.meas tran sum_energy_per_cycle_cb_mux[0to9] -+ param='sum_energy_per_cycle_cb_mux[0to8]+energy_per_cycle_cb_mux[1][0]_rrnode[114]' -Xmux_2level_tapbuf_size16[10] mux_2level_tapbuf_size16[10]->in[0] mux_2level_tapbuf_size16[10]->in[1] mux_2level_tapbuf_size16[10]->in[2] mux_2level_tapbuf_size16[10]->in[3] mux_2level_tapbuf_size16[10]->in[4] mux_2level_tapbuf_size16[10]->in[5] mux_2level_tapbuf_size16[10]->in[6] mux_2level_tapbuf_size16[10]->in[7] mux_2level_tapbuf_size16[10]->in[8] mux_2level_tapbuf_size16[10]->in[9] mux_2level_tapbuf_size16[10]->in[10] mux_2level_tapbuf_size16[10]->in[11] mux_2level_tapbuf_size16[10]->in[12] mux_2level_tapbuf_size16[10]->in[13] mux_2level_tapbuf_size16[10]->in[14] mux_2level_tapbuf_size16[10]->in[15] mux_2level_tapbuf_size16[10]->out sram[80]->outb sram[80]->out sram[81]->out sram[81]->outb sram[82]->out sram[82]->outb sram[83]->out sram[83]->outb sram[84]->outb sram[84]->out sram[85]->out sram[85]->outb sram[86]->out sram[86]->outb sram[87]->out sram[87]->outb gvdd_mux_2level_tapbuf_size16[10] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[10], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -***** Signal mux_2level_tapbuf_size16[10]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[0] mux_2level_tapbuf_size16[10]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[1] mux_2level_tapbuf_size16[10]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[10]->in[2] mux_2level_tapbuf_size16[10]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[10]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[10]->in[3] mux_2level_tapbuf_size16[10]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[10]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[4] mux_2level_tapbuf_size16[10]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[5] mux_2level_tapbuf_size16[10]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[6] mux_2level_tapbuf_size16[10]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[7] mux_2level_tapbuf_size16[10]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[8] mux_2level_tapbuf_size16[10]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[9] mux_2level_tapbuf_size16[10]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[10] mux_2level_tapbuf_size16[10]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[11] mux_2level_tapbuf_size16[10]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[12] mux_2level_tapbuf_size16[10]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[13] mux_2level_tapbuf_size16[10]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[14] mux_2level_tapbuf_size16[10]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[15] mux_2level_tapbuf_size16[10]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[10] gvdd_mux_2level_tapbuf_size16[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[48] when v(mux_2level_tapbuf_size16[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[48] when v(mux_2level_tapbuf_size16[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[48] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[10]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[48] param='mux_2level_tapbuf_size16[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[10]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[10]_energy_per_cycle param='mux_2level_tapbuf_size16[10]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[48] param='mux_2level_tapbuf_size16[10]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[48] param='dynamic_power_cb_mux[1][0]_rrnode[48]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[48] avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='start_rise_cb_mux[1][0]_rrnode[48]' to='start_rise_cb_mux[1][0]_rrnode[48]+switch_rise_cb_mux[1][0]_rrnode[48]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[48] avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='start_fall_cb_mux[1][0]_rrnode[48]' to='start_fall_cb_mux[1][0]_rrnode[48]+switch_fall_cb_mux[1][0]_rrnode[48]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_cb_mux[1][0]_rrnode[48]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_cb_mux[1][0]_rrnode[48]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to10] -+ param='sum_leakage_power_cb_mux[0to9]+leakage_cb_mux[1][0]_rrnode[48]' -.meas tran sum_energy_per_cycle_cb_mux[0to10] -+ param='sum_energy_per_cycle_cb_mux[0to9]+energy_per_cycle_cb_mux[1][0]_rrnode[48]' -Xmux_2level_tapbuf_size16[11] mux_2level_tapbuf_size16[11]->in[0] mux_2level_tapbuf_size16[11]->in[1] mux_2level_tapbuf_size16[11]->in[2] mux_2level_tapbuf_size16[11]->in[3] mux_2level_tapbuf_size16[11]->in[4] mux_2level_tapbuf_size16[11]->in[5] mux_2level_tapbuf_size16[11]->in[6] mux_2level_tapbuf_size16[11]->in[7] mux_2level_tapbuf_size16[11]->in[8] mux_2level_tapbuf_size16[11]->in[9] mux_2level_tapbuf_size16[11]->in[10] mux_2level_tapbuf_size16[11]->in[11] mux_2level_tapbuf_size16[11]->in[12] mux_2level_tapbuf_size16[11]->in[13] mux_2level_tapbuf_size16[11]->in[14] mux_2level_tapbuf_size16[11]->in[15] mux_2level_tapbuf_size16[11]->out sram[88]->outb sram[88]->out sram[89]->out sram[89]->outb sram[90]->out sram[90]->outb sram[91]->out sram[91]->outb sram[92]->outb sram[92]->out sram[93]->out sram[93]->outb sram[94]->out sram[94]->outb sram[95]->out sram[95]->outb gvdd_mux_2level_tapbuf_size16[11] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[11], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -***** Signal mux_2level_tapbuf_size16[11]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[0] mux_2level_tapbuf_size16[11]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[1] mux_2level_tapbuf_size16[11]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[11]->in[2] mux_2level_tapbuf_size16[11]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[11]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[11]->in[3] mux_2level_tapbuf_size16[11]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[11]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[4] mux_2level_tapbuf_size16[11]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[5] mux_2level_tapbuf_size16[11]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[6] mux_2level_tapbuf_size16[11]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[7] mux_2level_tapbuf_size16[11]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[8] mux_2level_tapbuf_size16[11]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[9] mux_2level_tapbuf_size16[11]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[10] mux_2level_tapbuf_size16[11]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[11] mux_2level_tapbuf_size16[11]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[12] mux_2level_tapbuf_size16[11]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[13] mux_2level_tapbuf_size16[11]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[14] mux_2level_tapbuf_size16[11]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[15] mux_2level_tapbuf_size16[11]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[11] gvdd_mux_2level_tapbuf_size16[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[50] when v(mux_2level_tapbuf_size16[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[50] when v(mux_2level_tapbuf_size16[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[50] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[11]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[50] param='mux_2level_tapbuf_size16[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[11]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[11]_energy_per_cycle param='mux_2level_tapbuf_size16[11]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[50] param='mux_2level_tapbuf_size16[11]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[50] param='dynamic_power_cb_mux[1][0]_rrnode[50]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[50] avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='start_rise_cb_mux[1][0]_rrnode[50]' to='start_rise_cb_mux[1][0]_rrnode[50]+switch_rise_cb_mux[1][0]_rrnode[50]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[50] avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='start_fall_cb_mux[1][0]_rrnode[50]' to='start_fall_cb_mux[1][0]_rrnode[50]+switch_fall_cb_mux[1][0]_rrnode[50]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_cb_mux[1][0]_rrnode[50]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_cb_mux[1][0]_rrnode[50]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to11] -+ param='sum_leakage_power_cb_mux[0to10]+leakage_cb_mux[1][0]_rrnode[50]' -.meas tran sum_energy_per_cycle_cb_mux[0to11] -+ param='sum_energy_per_cycle_cb_mux[0to10]+energy_per_cycle_cb_mux[1][0]_rrnode[50]' -Xmux_2level_tapbuf_size16[12] mux_2level_tapbuf_size16[12]->in[0] mux_2level_tapbuf_size16[12]->in[1] mux_2level_tapbuf_size16[12]->in[2] mux_2level_tapbuf_size16[12]->in[3] mux_2level_tapbuf_size16[12]->in[4] mux_2level_tapbuf_size16[12]->in[5] mux_2level_tapbuf_size16[12]->in[6] mux_2level_tapbuf_size16[12]->in[7] mux_2level_tapbuf_size16[12]->in[8] mux_2level_tapbuf_size16[12]->in[9] mux_2level_tapbuf_size16[12]->in[10] mux_2level_tapbuf_size16[12]->in[11] mux_2level_tapbuf_size16[12]->in[12] mux_2level_tapbuf_size16[12]->in[13] mux_2level_tapbuf_size16[12]->in[14] mux_2level_tapbuf_size16[12]->in[15] mux_2level_tapbuf_size16[12]->out sram[96]->outb sram[96]->out sram[97]->out sram[97]->outb sram[98]->out sram[98]->outb sram[99]->out sram[99]->outb sram[100]->outb sram[100]->out sram[101]->out sram[101]->outb sram[102]->out sram[102]->outb sram[103]->out sram[103]->outb gvdd_mux_2level_tapbuf_size16[12] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[12], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[100]->out) 0 -.nodeset V(sram[100]->outb) vsp -Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[101]->out) 0 -.nodeset V(sram[101]->outb) vsp -Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[102]->out) 0 -.nodeset V(sram[102]->outb) vsp -Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[103]->out) 0 -.nodeset V(sram[103]->outb) vsp -***** Signal mux_2level_tapbuf_size16[12]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[0] mux_2level_tapbuf_size16[12]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[1] mux_2level_tapbuf_size16[12]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[12]->in[2] mux_2level_tapbuf_size16[12]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[12]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[12]->in[3] mux_2level_tapbuf_size16[12]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[12]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[4] mux_2level_tapbuf_size16[12]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[5] mux_2level_tapbuf_size16[12]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[6] mux_2level_tapbuf_size16[12]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[7] mux_2level_tapbuf_size16[12]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[8] mux_2level_tapbuf_size16[12]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[9] mux_2level_tapbuf_size16[12]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[10] mux_2level_tapbuf_size16[12]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[11] mux_2level_tapbuf_size16[12]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[12] mux_2level_tapbuf_size16[12]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[13] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[12]->in[13] mux_2level_tapbuf_size16[12]->in[13] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[12]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[14] mux_2level_tapbuf_size16[12]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[15] mux_2level_tapbuf_size16[12]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[12] gvdd_mux_2level_tapbuf_size16[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[52] when v(mux_2level_tapbuf_size16[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[52] when v(mux_2level_tapbuf_size16[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[52] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[12]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[52] param='mux_2level_tapbuf_size16[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[12]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[12]_energy_per_cycle param='mux_2level_tapbuf_size16[12]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[52] param='mux_2level_tapbuf_size16[12]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[52] param='dynamic_power_cb_mux[1][0]_rrnode[52]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[52] avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='start_rise_cb_mux[1][0]_rrnode[52]' to='start_rise_cb_mux[1][0]_rrnode[52]+switch_rise_cb_mux[1][0]_rrnode[52]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[52] avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='start_fall_cb_mux[1][0]_rrnode[52]' to='start_fall_cb_mux[1][0]_rrnode[52]+switch_fall_cb_mux[1][0]_rrnode[52]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_cb_mux[1][0]_rrnode[52]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_cb_mux[1][0]_rrnode[52]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to12] -+ param='sum_leakage_power_cb_mux[0to11]+leakage_cb_mux[1][0]_rrnode[52]' -.meas tran sum_energy_per_cycle_cb_mux[0to12] -+ param='sum_energy_per_cycle_cb_mux[0to11]+energy_per_cycle_cb_mux[1][0]_rrnode[52]' -Xmux_2level_tapbuf_size16[13] mux_2level_tapbuf_size16[13]->in[0] mux_2level_tapbuf_size16[13]->in[1] mux_2level_tapbuf_size16[13]->in[2] mux_2level_tapbuf_size16[13]->in[3] mux_2level_tapbuf_size16[13]->in[4] mux_2level_tapbuf_size16[13]->in[5] mux_2level_tapbuf_size16[13]->in[6] mux_2level_tapbuf_size16[13]->in[7] mux_2level_tapbuf_size16[13]->in[8] mux_2level_tapbuf_size16[13]->in[9] mux_2level_tapbuf_size16[13]->in[10] mux_2level_tapbuf_size16[13]->in[11] mux_2level_tapbuf_size16[13]->in[12] mux_2level_tapbuf_size16[13]->in[13] mux_2level_tapbuf_size16[13]->in[14] mux_2level_tapbuf_size16[13]->in[15] mux_2level_tapbuf_size16[13]->out sram[104]->outb sram[104]->out sram[105]->out sram[105]->outb sram[106]->out sram[106]->outb sram[107]->out sram[107]->outb sram[108]->outb sram[108]->out sram[109]->out sram[109]->outb sram[110]->out sram[110]->outb sram[111]->out sram[111]->outb gvdd_mux_2level_tapbuf_size16[13] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[13], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[104]->out) 0 -.nodeset V(sram[104]->outb) vsp -Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[105]->out) 0 -.nodeset V(sram[105]->outb) vsp -Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[106]->out) 0 -.nodeset V(sram[106]->outb) vsp -Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[107]->out) 0 -.nodeset V(sram[107]->outb) vsp -Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[108]->out) 0 -.nodeset V(sram[108]->outb) vsp -Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[109]->out) 0 -.nodeset V(sram[109]->outb) vsp -Xsram[110] sram->in sram[110]->out sram[110]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[110]->out) 0 -.nodeset V(sram[110]->outb) vsp -Xsram[111] sram->in sram[111]->out sram[111]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[111]->out) 0 -.nodeset V(sram[111]->outb) vsp -***** Signal mux_2level_tapbuf_size16[13]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[0] mux_2level_tapbuf_size16[13]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[1] mux_2level_tapbuf_size16[13]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[13]->in[2] mux_2level_tapbuf_size16[13]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[13]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[13]->in[3] mux_2level_tapbuf_size16[13]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[13]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[4] mux_2level_tapbuf_size16[13]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[5] mux_2level_tapbuf_size16[13]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[6] mux_2level_tapbuf_size16[13]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[7] mux_2level_tapbuf_size16[13]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[8] mux_2level_tapbuf_size16[13]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[9] mux_2level_tapbuf_size16[13]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[10] mux_2level_tapbuf_size16[13]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[11] mux_2level_tapbuf_size16[13]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[12] mux_2level_tapbuf_size16[13]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[13] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[13]->in[13] mux_2level_tapbuf_size16[13]->in[13] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[13]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[14] mux_2level_tapbuf_size16[13]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[15] mux_2level_tapbuf_size16[13]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[13] gvdd_mux_2level_tapbuf_size16[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[54] when v(mux_2level_tapbuf_size16[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[54] when v(mux_2level_tapbuf_size16[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[54] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[13]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[54] param='mux_2level_tapbuf_size16[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[13]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[13]_energy_per_cycle param='mux_2level_tapbuf_size16[13]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[54] param='mux_2level_tapbuf_size16[13]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[54] param='dynamic_power_cb_mux[1][0]_rrnode[54]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[54] avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='start_rise_cb_mux[1][0]_rrnode[54]' to='start_rise_cb_mux[1][0]_rrnode[54]+switch_rise_cb_mux[1][0]_rrnode[54]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[54] avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='start_fall_cb_mux[1][0]_rrnode[54]' to='start_fall_cb_mux[1][0]_rrnode[54]+switch_fall_cb_mux[1][0]_rrnode[54]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_cb_mux[1][0]_rrnode[54]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_cb_mux[1][0]_rrnode[54]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to13] -+ param='sum_leakage_power_cb_mux[0to12]+leakage_cb_mux[1][0]_rrnode[54]' -.meas tran sum_energy_per_cycle_cb_mux[0to13] -+ param='sum_energy_per_cycle_cb_mux[0to12]+energy_per_cycle_cb_mux[1][0]_rrnode[54]' -Xmux_2level_tapbuf_size16[14] mux_2level_tapbuf_size16[14]->in[0] mux_2level_tapbuf_size16[14]->in[1] mux_2level_tapbuf_size16[14]->in[2] mux_2level_tapbuf_size16[14]->in[3] mux_2level_tapbuf_size16[14]->in[4] mux_2level_tapbuf_size16[14]->in[5] mux_2level_tapbuf_size16[14]->in[6] mux_2level_tapbuf_size16[14]->in[7] mux_2level_tapbuf_size16[14]->in[8] mux_2level_tapbuf_size16[14]->in[9] mux_2level_tapbuf_size16[14]->in[10] mux_2level_tapbuf_size16[14]->in[11] mux_2level_tapbuf_size16[14]->in[12] mux_2level_tapbuf_size16[14]->in[13] mux_2level_tapbuf_size16[14]->in[14] mux_2level_tapbuf_size16[14]->in[15] mux_2level_tapbuf_size16[14]->out sram[112]->outb sram[112]->out sram[113]->out sram[113]->outb sram[114]->out sram[114]->outb sram[115]->out sram[115]->outb sram[116]->outb sram[116]->out sram[117]->out sram[117]->outb sram[118]->out sram[118]->outb sram[119]->out sram[119]->outb gvdd_mux_2level_tapbuf_size16[14] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[14], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[112] sram->in sram[112]->out sram[112]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[112]->out) 0 -.nodeset V(sram[112]->outb) vsp -Xsram[113] sram->in sram[113]->out sram[113]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[113]->out) 0 -.nodeset V(sram[113]->outb) vsp -Xsram[114] sram->in sram[114]->out sram[114]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[114]->out) 0 -.nodeset V(sram[114]->outb) vsp -Xsram[115] sram->in sram[115]->out sram[115]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[115]->out) 0 -.nodeset V(sram[115]->outb) vsp -Xsram[116] sram->in sram[116]->out sram[116]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[116]->out) 0 -.nodeset V(sram[116]->outb) vsp -Xsram[117] sram->in sram[117]->out sram[117]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[117]->out) 0 -.nodeset V(sram[117]->outb) vsp -Xsram[118] sram->in sram[118]->out sram[118]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[118]->out) 0 -.nodeset V(sram[118]->outb) vsp -Xsram[119] sram->in sram[119]->out sram[119]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[119]->out) 0 -.nodeset V(sram[119]->outb) vsp -***** Signal mux_2level_tapbuf_size16[14]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[0] mux_2level_tapbuf_size16[14]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[1] mux_2level_tapbuf_size16[14]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[2] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[14]->in[2] mux_2level_tapbuf_size16[14]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[14]->in[3] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[14]->in[3] mux_2level_tapbuf_size16[14]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[14]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[4] mux_2level_tapbuf_size16[14]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[5] mux_2level_tapbuf_size16[14]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[6] mux_2level_tapbuf_size16[14]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[7] mux_2level_tapbuf_size16[14]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[8] mux_2level_tapbuf_size16[14]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[9] mux_2level_tapbuf_size16[14]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[10] mux_2level_tapbuf_size16[14]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[11] mux_2level_tapbuf_size16[14]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[12] mux_2level_tapbuf_size16[14]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[13] mux_2level_tapbuf_size16[14]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[14] mux_2level_tapbuf_size16[14]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[15] mux_2level_tapbuf_size16[14]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[14] gvdd_mux_2level_tapbuf_size16[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[56] when v(mux_2level_tapbuf_size16[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[56] when v(mux_2level_tapbuf_size16[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[56] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[14]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[56] param='mux_2level_tapbuf_size16[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[14]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[14]_energy_per_cycle param='mux_2level_tapbuf_size16[14]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[56] param='mux_2level_tapbuf_size16[14]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[56] param='dynamic_power_cb_mux[1][0]_rrnode[56]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[56] avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='start_rise_cb_mux[1][0]_rrnode[56]' to='start_rise_cb_mux[1][0]_rrnode[56]+switch_rise_cb_mux[1][0]_rrnode[56]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[56] avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='start_fall_cb_mux[1][0]_rrnode[56]' to='start_fall_cb_mux[1][0]_rrnode[56]+switch_fall_cb_mux[1][0]_rrnode[56]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_cb_mux[1][0]_rrnode[56]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_cb_mux[1][0]_rrnode[56]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to14] -+ param='sum_leakage_power_cb_mux[0to13]+leakage_cb_mux[1][0]_rrnode[56]' -.meas tran sum_energy_per_cycle_cb_mux[0to14] -+ param='sum_energy_per_cycle_cb_mux[0to13]+energy_per_cycle_cb_mux[1][0]_rrnode[56]' -Xmux_2level_tapbuf_size16[15] mux_2level_tapbuf_size16[15]->in[0] mux_2level_tapbuf_size16[15]->in[1] mux_2level_tapbuf_size16[15]->in[2] mux_2level_tapbuf_size16[15]->in[3] mux_2level_tapbuf_size16[15]->in[4] mux_2level_tapbuf_size16[15]->in[5] mux_2level_tapbuf_size16[15]->in[6] mux_2level_tapbuf_size16[15]->in[7] mux_2level_tapbuf_size16[15]->in[8] mux_2level_tapbuf_size16[15]->in[9] mux_2level_tapbuf_size16[15]->in[10] mux_2level_tapbuf_size16[15]->in[11] mux_2level_tapbuf_size16[15]->in[12] mux_2level_tapbuf_size16[15]->in[13] mux_2level_tapbuf_size16[15]->in[14] mux_2level_tapbuf_size16[15]->in[15] mux_2level_tapbuf_size16[15]->out sram[120]->outb sram[120]->out sram[121]->out sram[121]->outb sram[122]->out sram[122]->outb sram[123]->out sram[123]->outb sram[124]->outb sram[124]->out sram[125]->out sram[125]->outb sram[126]->out sram[126]->outb sram[127]->out sram[127]->outb gvdd_mux_2level_tapbuf_size16[15] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[15], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[120] sram->in sram[120]->out sram[120]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[120]->out) 0 -.nodeset V(sram[120]->outb) vsp -Xsram[121] sram->in sram[121]->out sram[121]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[121]->out) 0 -.nodeset V(sram[121]->outb) vsp -Xsram[122] sram->in sram[122]->out sram[122]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[122]->out) 0 -.nodeset V(sram[122]->outb) vsp -Xsram[123] sram->in sram[123]->out sram[123]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[123]->out) 0 -.nodeset V(sram[123]->outb) vsp -Xsram[124] sram->in sram[124]->out sram[124]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[124]->out) 0 -.nodeset V(sram[124]->outb) vsp -Xsram[125] sram->in sram[125]->out sram[125]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[125]->out) 0 -.nodeset V(sram[125]->outb) vsp -Xsram[126] sram->in sram[126]->out sram[126]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[126]->out) 0 -.nodeset V(sram[126]->outb) vsp -Xsram[127] sram->in sram[127]->out sram[127]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[127]->out) 0 -.nodeset V(sram[127]->outb) vsp -***** Signal mux_2level_tapbuf_size16[15]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[0] mux_2level_tapbuf_size16[15]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[1] mux_2level_tapbuf_size16[15]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[2] mux_2level_tapbuf_size16[15]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[3] mux_2level_tapbuf_size16[15]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[4] mux_2level_tapbuf_size16[15]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[5] mux_2level_tapbuf_size16[15]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[6] mux_2level_tapbuf_size16[15]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[7] mux_2level_tapbuf_size16[15]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[8] mux_2level_tapbuf_size16[15]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[9] mux_2level_tapbuf_size16[15]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[10] mux_2level_tapbuf_size16[15]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[11] mux_2level_tapbuf_size16[15]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[12] mux_2level_tapbuf_size16[15]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[13] mux_2level_tapbuf_size16[15]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[14] mux_2level_tapbuf_size16[15]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[15] mux_2level_tapbuf_size16[15]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[15] gvdd_mux_2level_tapbuf_size16[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[58] when v(mux_2level_tapbuf_size16[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[58] when v(mux_2level_tapbuf_size16[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[58] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[15]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[58] param='mux_2level_tapbuf_size16[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[15]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[15]_energy_per_cycle param='mux_2level_tapbuf_size16[15]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[58] param='mux_2level_tapbuf_size16[15]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[58] param='dynamic_power_cb_mux[1][0]_rrnode[58]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[58] avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='start_rise_cb_mux[1][0]_rrnode[58]' to='start_rise_cb_mux[1][0]_rrnode[58]+switch_rise_cb_mux[1][0]_rrnode[58]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[58] avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='start_fall_cb_mux[1][0]_rrnode[58]' to='start_fall_cb_mux[1][0]_rrnode[58]+switch_fall_cb_mux[1][0]_rrnode[58]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_cb_mux[1][0]_rrnode[58]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_cb_mux[1][0]_rrnode[58]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to15] -+ param='sum_leakage_power_cb_mux[0to14]+leakage_cb_mux[1][0]_rrnode[58]' -.meas tran sum_energy_per_cycle_cb_mux[0to15] -+ param='sum_energy_per_cycle_cb_mux[0to14]+energy_per_cycle_cb_mux[1][0]_rrnode[58]' -Xmux_2level_tapbuf_size16[16] mux_2level_tapbuf_size16[16]->in[0] mux_2level_tapbuf_size16[16]->in[1] mux_2level_tapbuf_size16[16]->in[2] mux_2level_tapbuf_size16[16]->in[3] mux_2level_tapbuf_size16[16]->in[4] mux_2level_tapbuf_size16[16]->in[5] mux_2level_tapbuf_size16[16]->in[6] mux_2level_tapbuf_size16[16]->in[7] mux_2level_tapbuf_size16[16]->in[8] mux_2level_tapbuf_size16[16]->in[9] mux_2level_tapbuf_size16[16]->in[10] mux_2level_tapbuf_size16[16]->in[11] mux_2level_tapbuf_size16[16]->in[12] mux_2level_tapbuf_size16[16]->in[13] mux_2level_tapbuf_size16[16]->in[14] mux_2level_tapbuf_size16[16]->in[15] mux_2level_tapbuf_size16[16]->out sram[128]->outb sram[128]->out sram[129]->out sram[129]->outb sram[130]->out sram[130]->outb sram[131]->out sram[131]->outb sram[132]->outb sram[132]->out sram[133]->out sram[133]->outb sram[134]->out sram[134]->outb sram[135]->out sram[135]->outb gvdd_mux_2level_tapbuf_size16[16] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[16], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[128] sram->in sram[128]->out sram[128]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[128]->out) 0 -.nodeset V(sram[128]->outb) vsp -Xsram[129] sram->in sram[129]->out sram[129]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[129]->out) 0 -.nodeset V(sram[129]->outb) vsp -Xsram[130] sram->in sram[130]->out sram[130]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[130]->out) 0 -.nodeset V(sram[130]->outb) vsp -Xsram[131] sram->in sram[131]->out sram[131]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[131]->out) 0 -.nodeset V(sram[131]->outb) vsp -Xsram[132] sram->in sram[132]->out sram[132]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[132]->out) 0 -.nodeset V(sram[132]->outb) vsp -Xsram[133] sram->in sram[133]->out sram[133]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[133]->out) 0 -.nodeset V(sram[133]->outb) vsp -Xsram[134] sram->in sram[134]->out sram[134]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[134]->out) 0 -.nodeset V(sram[134]->outb) vsp -Xsram[135] sram->in sram[135]->out sram[135]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[135]->out) 0 -.nodeset V(sram[135]->outb) vsp -***** Signal mux_2level_tapbuf_size16[16]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[0] mux_2level_tapbuf_size16[16]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[1] mux_2level_tapbuf_size16[16]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[2] mux_2level_tapbuf_size16[16]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[3] mux_2level_tapbuf_size16[16]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[4] mux_2level_tapbuf_size16[16]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[5] mux_2level_tapbuf_size16[16]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[6] mux_2level_tapbuf_size16[16]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[7] mux_2level_tapbuf_size16[16]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[8] mux_2level_tapbuf_size16[16]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[9] mux_2level_tapbuf_size16[16]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[10] mux_2level_tapbuf_size16[16]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[11] mux_2level_tapbuf_size16[16]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[12] mux_2level_tapbuf_size16[16]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[13] mux_2level_tapbuf_size16[16]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[14] mux_2level_tapbuf_size16[16]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[15] mux_2level_tapbuf_size16[16]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[16] gvdd_mux_2level_tapbuf_size16[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[60] when v(mux_2level_tapbuf_size16[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[60] when v(mux_2level_tapbuf_size16[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[60] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[16]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[60] param='mux_2level_tapbuf_size16[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[16]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[16]_energy_per_cycle param='mux_2level_tapbuf_size16[16]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[60] param='mux_2level_tapbuf_size16[16]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[60] param='dynamic_power_cb_mux[1][0]_rrnode[60]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[60] avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='start_rise_cb_mux[1][0]_rrnode[60]' to='start_rise_cb_mux[1][0]_rrnode[60]+switch_rise_cb_mux[1][0]_rrnode[60]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[60] avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='start_fall_cb_mux[1][0]_rrnode[60]' to='start_fall_cb_mux[1][0]_rrnode[60]+switch_fall_cb_mux[1][0]_rrnode[60]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_cb_mux[1][0]_rrnode[60]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_cb_mux[1][0]_rrnode[60]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to16] -+ param='sum_leakage_power_cb_mux[0to15]+leakage_cb_mux[1][0]_rrnode[60]' -.meas tran sum_energy_per_cycle_cb_mux[0to16] -+ param='sum_energy_per_cycle_cb_mux[0to15]+energy_per_cycle_cb_mux[1][0]_rrnode[60]' -Xmux_2level_tapbuf_size16[17] mux_2level_tapbuf_size16[17]->in[0] mux_2level_tapbuf_size16[17]->in[1] mux_2level_tapbuf_size16[17]->in[2] mux_2level_tapbuf_size16[17]->in[3] mux_2level_tapbuf_size16[17]->in[4] mux_2level_tapbuf_size16[17]->in[5] mux_2level_tapbuf_size16[17]->in[6] mux_2level_tapbuf_size16[17]->in[7] mux_2level_tapbuf_size16[17]->in[8] mux_2level_tapbuf_size16[17]->in[9] mux_2level_tapbuf_size16[17]->in[10] mux_2level_tapbuf_size16[17]->in[11] mux_2level_tapbuf_size16[17]->in[12] mux_2level_tapbuf_size16[17]->in[13] mux_2level_tapbuf_size16[17]->in[14] mux_2level_tapbuf_size16[17]->in[15] mux_2level_tapbuf_size16[17]->out sram[136]->outb sram[136]->out sram[137]->out sram[137]->outb sram[138]->out sram[138]->outb sram[139]->out sram[139]->outb sram[140]->outb sram[140]->out sram[141]->out sram[141]->outb sram[142]->out sram[142]->outb sram[143]->out sram[143]->outb gvdd_mux_2level_tapbuf_size16[17] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[17], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[136] sram->in sram[136]->out sram[136]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[136]->out) 0 -.nodeset V(sram[136]->outb) vsp -Xsram[137] sram->in sram[137]->out sram[137]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[137]->out) 0 -.nodeset V(sram[137]->outb) vsp -Xsram[138] sram->in sram[138]->out sram[138]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[138]->out) 0 -.nodeset V(sram[138]->outb) vsp -Xsram[139] sram->in sram[139]->out sram[139]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[139]->out) 0 -.nodeset V(sram[139]->outb) vsp -Xsram[140] sram->in sram[140]->out sram[140]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[140]->out) 0 -.nodeset V(sram[140]->outb) vsp -Xsram[141] sram->in sram[141]->out sram[141]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[141]->out) 0 -.nodeset V(sram[141]->outb) vsp -Xsram[142] sram->in sram[142]->out sram[142]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[142]->out) 0 -.nodeset V(sram[142]->outb) vsp -Xsram[143] sram->in sram[143]->out sram[143]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[143]->out) 0 -.nodeset V(sram[143]->outb) vsp -***** Signal mux_2level_tapbuf_size16[17]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[17]->in[0] mux_2level_tapbuf_size16[17]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[17]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_2level_tapbuf_size16[17]->in[1] mux_2level_tapbuf_size16[17]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[17]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[2] mux_2level_tapbuf_size16[17]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[3] mux_2level_tapbuf_size16[17]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[4] mux_2level_tapbuf_size16[17]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[5] mux_2level_tapbuf_size16[17]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[6] mux_2level_tapbuf_size16[17]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[7] mux_2level_tapbuf_size16[17]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[8] mux_2level_tapbuf_size16[17]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[9] mux_2level_tapbuf_size16[17]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[10] mux_2level_tapbuf_size16[17]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[11] mux_2level_tapbuf_size16[17]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[12] mux_2level_tapbuf_size16[17]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[13] mux_2level_tapbuf_size16[17]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[14] mux_2level_tapbuf_size16[17]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[15] mux_2level_tapbuf_size16[17]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[17] gvdd_mux_2level_tapbuf_size16[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][0]_rrnode[62] when v(mux_2level_tapbuf_size16[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][0]_rrnode[62] when v(mux_2level_tapbuf_size16[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][0]_rrnode[62] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[17]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][0]_rrnode[62] param='mux_2level_tapbuf_size16[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[17]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[17]_energy_per_cycle param='mux_2level_tapbuf_size16[17]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][0]_rrnode[62] param='mux_2level_tapbuf_size16[17]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][0]_rrnode[62] param='dynamic_power_cb_mux[1][0]_rrnode[62]*clock_period' -.meas tran dynamic_rise_cb_mux[1][0]_rrnode[62] avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='start_rise_cb_mux[1][0]_rrnode[62]' to='start_rise_cb_mux[1][0]_rrnode[62]+switch_rise_cb_mux[1][0]_rrnode[62]' -.meas tran dynamic_fall_cb_mux[1][0]_rrnode[62] avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='start_fall_cb_mux[1][0]_rrnode[62]' to='start_fall_cb_mux[1][0]_rrnode[62]+switch_fall_cb_mux[1][0]_rrnode[62]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_cb_mux[1][0]_rrnode[62]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_cb_mux[1][0]_rrnode[62]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to17] -+ param='sum_leakage_power_cb_mux[0to16]+leakage_cb_mux[1][0]_rrnode[62]' -.meas tran sum_energy_per_cycle_cb_mux[0to17] -+ param='sum_energy_per_cycle_cb_mux[0to16]+energy_per_cycle_cb_mux[1][0]_rrnode[62]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='6*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to17]' -.meas tran total_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to17]' -.meas tran total_leakage_power_cb_mux -+ param='sum_leakage_power_cb_mux[0to17]' -.meas tran total_energy_per_cycle_cb_mux -+ param='sum_energy_per_cycle_cb_mux[0to17]' -.end diff --git a/examples/spice_test_example_2/cb_mux_tb/example_2_cbx1_1_cbmux_testbench.sp b/examples/spice_test_example_2/cb_mux_tb/example_2_cbx1_1_cbmux_testbench.sp deleted file mode 100644 index 5ea0da82a..000000000 --- a/examples/spice_test_example_2/cb_mux_tb/example_2_cbx1_1_cbmux_testbench.sp +++ /dev/null @@ -1,2704 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_2level_tapbuf_size16[0] mux_2level_tapbuf_size16[0]->in[0] mux_2level_tapbuf_size16[0]->in[1] mux_2level_tapbuf_size16[0]->in[2] mux_2level_tapbuf_size16[0]->in[3] mux_2level_tapbuf_size16[0]->in[4] mux_2level_tapbuf_size16[0]->in[5] mux_2level_tapbuf_size16[0]->in[6] mux_2level_tapbuf_size16[0]->in[7] mux_2level_tapbuf_size16[0]->in[8] mux_2level_tapbuf_size16[0]->in[9] mux_2level_tapbuf_size16[0]->in[10] mux_2level_tapbuf_size16[0]->in[11] mux_2level_tapbuf_size16[0]->in[12] mux_2level_tapbuf_size16[0]->in[13] mux_2level_tapbuf_size16[0]->in[14] mux_2level_tapbuf_size16[0]->in[15] mux_2level_tapbuf_size16[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb sram[3]->out sram[3]->outb sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->out sram[6]->outb sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size16[0] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_2level_tapbuf_size16[0]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[0] mux_2level_tapbuf_size16[0]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[1] mux_2level_tapbuf_size16[0]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[2] mux_2level_tapbuf_size16[0]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[3] mux_2level_tapbuf_size16[0]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[4] mux_2level_tapbuf_size16[0]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[5] mux_2level_tapbuf_size16[0]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[6] mux_2level_tapbuf_size16[0]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[7] mux_2level_tapbuf_size16[0]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[8] mux_2level_tapbuf_size16[0]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[9] mux_2level_tapbuf_size16[0]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[10] mux_2level_tapbuf_size16[0]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[11] mux_2level_tapbuf_size16[0]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[12] mux_2level_tapbuf_size16[0]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[13] mux_2level_tapbuf_size16[0]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[14] mux_2level_tapbuf_size16[0]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[15] mux_2level_tapbuf_size16[0]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[0] gvdd_mux_2level_tapbuf_size16[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[143] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[143] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[143] when v(mux_2level_tapbuf_size16[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[143] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[143] when v(mux_2level_tapbuf_size16[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[143] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[143] param='mux_2level_tapbuf_size16[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[0]_energy_per_cycle param='mux_2level_tapbuf_size16[0]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[143] param='mux_2level_tapbuf_size16[0]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[143] param='dynamic_power_cb_mux[1][1]_rrnode[143]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[143] avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='start_rise_cb_mux[1][1]_rrnode[143]' to='start_rise_cb_mux[1][1]_rrnode[143]+switch_rise_cb_mux[1][1]_rrnode[143]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[143] avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='start_fall_cb_mux[1][1]_rrnode[143]' to='start_fall_cb_mux[1][1]_rrnode[143]+switch_fall_cb_mux[1][1]_rrnode[143]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_cb_mux[1][1]_rrnode[143]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][1]_rrnode[143]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to0] -+ param='leakage_cb_mux[1][1]_rrnode[143]' -.meas tran sum_energy_per_cycle_cb_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][1]_rrnode[143]' -Xmux_2level_tapbuf_size16[1] mux_2level_tapbuf_size16[1]->in[0] mux_2level_tapbuf_size16[1]->in[1] mux_2level_tapbuf_size16[1]->in[2] mux_2level_tapbuf_size16[1]->in[3] mux_2level_tapbuf_size16[1]->in[4] mux_2level_tapbuf_size16[1]->in[5] mux_2level_tapbuf_size16[1]->in[6] mux_2level_tapbuf_size16[1]->in[7] mux_2level_tapbuf_size16[1]->in[8] mux_2level_tapbuf_size16[1]->in[9] mux_2level_tapbuf_size16[1]->in[10] mux_2level_tapbuf_size16[1]->in[11] mux_2level_tapbuf_size16[1]->in[12] mux_2level_tapbuf_size16[1]->in[13] mux_2level_tapbuf_size16[1]->in[14] mux_2level_tapbuf_size16[1]->in[15] mux_2level_tapbuf_size16[1]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->out sram[10]->outb sram[11]->out sram[11]->outb sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->out sram[14]->outb sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size16[1] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_2level_tapbuf_size16[1]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[0] mux_2level_tapbuf_size16[1]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[1] mux_2level_tapbuf_size16[1]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[2] mux_2level_tapbuf_size16[1]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[3] mux_2level_tapbuf_size16[1]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[4] mux_2level_tapbuf_size16[1]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[5] mux_2level_tapbuf_size16[1]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[6] mux_2level_tapbuf_size16[1]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[7] mux_2level_tapbuf_size16[1]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[8] mux_2level_tapbuf_size16[1]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[9] mux_2level_tapbuf_size16[1]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[10] mux_2level_tapbuf_size16[1]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[11] mux_2level_tapbuf_size16[1]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[12] mux_2level_tapbuf_size16[1]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[13] mux_2level_tapbuf_size16[1]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[14] mux_2level_tapbuf_size16[1]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[15] mux_2level_tapbuf_size16[1]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[1] gvdd_mux_2level_tapbuf_size16[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[145] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[145] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[145] when v(mux_2level_tapbuf_size16[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[145] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[145] when v(mux_2level_tapbuf_size16[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[145] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[145] param='mux_2level_tapbuf_size16[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[1]_energy_per_cycle param='mux_2level_tapbuf_size16[1]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[145] param='mux_2level_tapbuf_size16[1]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[145] param='dynamic_power_cb_mux[1][1]_rrnode[145]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[145] avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='start_rise_cb_mux[1][1]_rrnode[145]' to='start_rise_cb_mux[1][1]_rrnode[145]+switch_rise_cb_mux[1][1]_rrnode[145]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[145] avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='start_fall_cb_mux[1][1]_rrnode[145]' to='start_fall_cb_mux[1][1]_rrnode[145]+switch_fall_cb_mux[1][1]_rrnode[145]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[1][1]_rrnode[145]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[145]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to1] -+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[1][1]_rrnode[145]' -.meas tran sum_energy_per_cycle_cb_mux[0to1] -+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[145]' -Xmux_2level_tapbuf_size16[2] mux_2level_tapbuf_size16[2]->in[0] mux_2level_tapbuf_size16[2]->in[1] mux_2level_tapbuf_size16[2]->in[2] mux_2level_tapbuf_size16[2]->in[3] mux_2level_tapbuf_size16[2]->in[4] mux_2level_tapbuf_size16[2]->in[5] mux_2level_tapbuf_size16[2]->in[6] mux_2level_tapbuf_size16[2]->in[7] mux_2level_tapbuf_size16[2]->in[8] mux_2level_tapbuf_size16[2]->in[9] mux_2level_tapbuf_size16[2]->in[10] mux_2level_tapbuf_size16[2]->in[11] mux_2level_tapbuf_size16[2]->in[12] mux_2level_tapbuf_size16[2]->in[13] mux_2level_tapbuf_size16[2]->in[14] mux_2level_tapbuf_size16[2]->in[15] mux_2level_tapbuf_size16[2]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->out sram[18]->outb sram[19]->out sram[19]->outb sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->out sram[22]->outb sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size16[2] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_2level_tapbuf_size16[2]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[0] mux_2level_tapbuf_size16[2]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[1] mux_2level_tapbuf_size16[2]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[2] mux_2level_tapbuf_size16[2]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[3] mux_2level_tapbuf_size16[2]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[4] mux_2level_tapbuf_size16[2]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[5] mux_2level_tapbuf_size16[2]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[6] mux_2level_tapbuf_size16[2]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[7] mux_2level_tapbuf_size16[2]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[8] mux_2level_tapbuf_size16[2]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[9] mux_2level_tapbuf_size16[2]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[10] mux_2level_tapbuf_size16[2]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[11] mux_2level_tapbuf_size16[2]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[12] mux_2level_tapbuf_size16[2]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[13] mux_2level_tapbuf_size16[2]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[14] mux_2level_tapbuf_size16[2]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[15] mux_2level_tapbuf_size16[2]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[2] gvdd_mux_2level_tapbuf_size16[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[147] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[147] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[147] when v(mux_2level_tapbuf_size16[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[147] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[147] when v(mux_2level_tapbuf_size16[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[147] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[147] param='mux_2level_tapbuf_size16[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[2]_energy_per_cycle param='mux_2level_tapbuf_size16[2]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[147] param='mux_2level_tapbuf_size16[2]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[147] param='dynamic_power_cb_mux[1][1]_rrnode[147]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[147] avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='start_rise_cb_mux[1][1]_rrnode[147]' to='start_rise_cb_mux[1][1]_rrnode[147]+switch_rise_cb_mux[1][1]_rrnode[147]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[147] avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='start_fall_cb_mux[1][1]_rrnode[147]' to='start_fall_cb_mux[1][1]_rrnode[147]+switch_fall_cb_mux[1][1]_rrnode[147]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[1][1]_rrnode[147]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[147]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to2] -+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[1][1]_rrnode[147]' -.meas tran sum_energy_per_cycle_cb_mux[0to2] -+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[147]' -Xmux_2level_tapbuf_size16[3] mux_2level_tapbuf_size16[3]->in[0] mux_2level_tapbuf_size16[3]->in[1] mux_2level_tapbuf_size16[3]->in[2] mux_2level_tapbuf_size16[3]->in[3] mux_2level_tapbuf_size16[3]->in[4] mux_2level_tapbuf_size16[3]->in[5] mux_2level_tapbuf_size16[3]->in[6] mux_2level_tapbuf_size16[3]->in[7] mux_2level_tapbuf_size16[3]->in[8] mux_2level_tapbuf_size16[3]->in[9] mux_2level_tapbuf_size16[3]->in[10] mux_2level_tapbuf_size16[3]->in[11] mux_2level_tapbuf_size16[3]->in[12] mux_2level_tapbuf_size16[3]->in[13] mux_2level_tapbuf_size16[3]->in[14] mux_2level_tapbuf_size16[3]->in[15] mux_2level_tapbuf_size16[3]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->out sram[26]->outb sram[27]->out sram[27]->outb sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->out sram[30]->outb sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size16[3] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_2level_tapbuf_size16[3]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[0] mux_2level_tapbuf_size16[3]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[1] mux_2level_tapbuf_size16[3]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[2] mux_2level_tapbuf_size16[3]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[3] mux_2level_tapbuf_size16[3]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[4] mux_2level_tapbuf_size16[3]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[5] mux_2level_tapbuf_size16[3]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[6] mux_2level_tapbuf_size16[3]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[7] mux_2level_tapbuf_size16[3]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[8] mux_2level_tapbuf_size16[3]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[9] mux_2level_tapbuf_size16[3]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[10] mux_2level_tapbuf_size16[3]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[11] mux_2level_tapbuf_size16[3]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[12] mux_2level_tapbuf_size16[3]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[13] mux_2level_tapbuf_size16[3]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[14] mux_2level_tapbuf_size16[3]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[15] mux_2level_tapbuf_size16[3]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[3] gvdd_mux_2level_tapbuf_size16[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[149] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[149] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[149] when v(mux_2level_tapbuf_size16[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[149] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[149] when v(mux_2level_tapbuf_size16[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[149] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[149] param='mux_2level_tapbuf_size16[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[3]_energy_per_cycle param='mux_2level_tapbuf_size16[3]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[149] param='mux_2level_tapbuf_size16[3]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[149] param='dynamic_power_cb_mux[1][1]_rrnode[149]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[149] avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='start_rise_cb_mux[1][1]_rrnode[149]' to='start_rise_cb_mux[1][1]_rrnode[149]+switch_rise_cb_mux[1][1]_rrnode[149]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[149] avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='start_fall_cb_mux[1][1]_rrnode[149]' to='start_fall_cb_mux[1][1]_rrnode[149]+switch_fall_cb_mux[1][1]_rrnode[149]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[1][1]_rrnode[149]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[149]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to3] -+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[1][1]_rrnode[149]' -.meas tran sum_energy_per_cycle_cb_mux[0to3] -+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[149]' -Xmux_2level_tapbuf_size16[4] mux_2level_tapbuf_size16[4]->in[0] mux_2level_tapbuf_size16[4]->in[1] mux_2level_tapbuf_size16[4]->in[2] mux_2level_tapbuf_size16[4]->in[3] mux_2level_tapbuf_size16[4]->in[4] mux_2level_tapbuf_size16[4]->in[5] mux_2level_tapbuf_size16[4]->in[6] mux_2level_tapbuf_size16[4]->in[7] mux_2level_tapbuf_size16[4]->in[8] mux_2level_tapbuf_size16[4]->in[9] mux_2level_tapbuf_size16[4]->in[10] mux_2level_tapbuf_size16[4]->in[11] mux_2level_tapbuf_size16[4]->in[12] mux_2level_tapbuf_size16[4]->in[13] mux_2level_tapbuf_size16[4]->in[14] mux_2level_tapbuf_size16[4]->in[15] mux_2level_tapbuf_size16[4]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->out sram[34]->outb sram[35]->out sram[35]->outb sram[36]->outb sram[36]->out sram[37]->out sram[37]->outb sram[38]->out sram[38]->outb sram[39]->out sram[39]->outb gvdd_mux_2level_tapbuf_size16[4] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -***** Signal mux_2level_tapbuf_size16[4]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[0] mux_2level_tapbuf_size16[4]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[1] mux_2level_tapbuf_size16[4]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[2] mux_2level_tapbuf_size16[4]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[3] mux_2level_tapbuf_size16[4]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[4] mux_2level_tapbuf_size16[4]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[5] mux_2level_tapbuf_size16[4]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[6] mux_2level_tapbuf_size16[4]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[7] mux_2level_tapbuf_size16[4]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[8] mux_2level_tapbuf_size16[4]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[9] mux_2level_tapbuf_size16[4]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[10] mux_2level_tapbuf_size16[4]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[11] mux_2level_tapbuf_size16[4]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[12] mux_2level_tapbuf_size16[4]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[13] mux_2level_tapbuf_size16[4]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[14] mux_2level_tapbuf_size16[4]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[15] mux_2level_tapbuf_size16[4]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[4] gvdd_mux_2level_tapbuf_size16[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[151] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[151] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[151] when v(mux_2level_tapbuf_size16[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[151] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[151] when v(mux_2level_tapbuf_size16[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[151] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[151] param='mux_2level_tapbuf_size16[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[4]_energy_per_cycle param='mux_2level_tapbuf_size16[4]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[151] param='mux_2level_tapbuf_size16[4]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[151] param='dynamic_power_cb_mux[1][1]_rrnode[151]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[151] avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='start_rise_cb_mux[1][1]_rrnode[151]' to='start_rise_cb_mux[1][1]_rrnode[151]+switch_rise_cb_mux[1][1]_rrnode[151]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[151] avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='start_fall_cb_mux[1][1]_rrnode[151]' to='start_fall_cb_mux[1][1]_rrnode[151]+switch_fall_cb_mux[1][1]_rrnode[151]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[1][1]_rrnode[151]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[151]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to4] -+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[1][1]_rrnode[151]' -.meas tran sum_energy_per_cycle_cb_mux[0to4] -+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[151]' -Xmux_2level_tapbuf_size16[5] mux_2level_tapbuf_size16[5]->in[0] mux_2level_tapbuf_size16[5]->in[1] mux_2level_tapbuf_size16[5]->in[2] mux_2level_tapbuf_size16[5]->in[3] mux_2level_tapbuf_size16[5]->in[4] mux_2level_tapbuf_size16[5]->in[5] mux_2level_tapbuf_size16[5]->in[6] mux_2level_tapbuf_size16[5]->in[7] mux_2level_tapbuf_size16[5]->in[8] mux_2level_tapbuf_size16[5]->in[9] mux_2level_tapbuf_size16[5]->in[10] mux_2level_tapbuf_size16[5]->in[11] mux_2level_tapbuf_size16[5]->in[12] mux_2level_tapbuf_size16[5]->in[13] mux_2level_tapbuf_size16[5]->in[14] mux_2level_tapbuf_size16[5]->in[15] mux_2level_tapbuf_size16[5]->out sram[40]->outb sram[40]->out sram[41]->out sram[41]->outb sram[42]->out sram[42]->outb sram[43]->out sram[43]->outb sram[44]->outb sram[44]->out sram[45]->out sram[45]->outb sram[46]->out sram[46]->outb sram[47]->out sram[47]->outb gvdd_mux_2level_tapbuf_size16[5] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[5], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -***** Signal mux_2level_tapbuf_size16[5]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[0] mux_2level_tapbuf_size16[5]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[1] mux_2level_tapbuf_size16[5]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[2] mux_2level_tapbuf_size16[5]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[3] mux_2level_tapbuf_size16[5]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[4] mux_2level_tapbuf_size16[5]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[5] mux_2level_tapbuf_size16[5]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[6] mux_2level_tapbuf_size16[5]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[7] mux_2level_tapbuf_size16[5]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[8] mux_2level_tapbuf_size16[5]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[9] mux_2level_tapbuf_size16[5]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[10] mux_2level_tapbuf_size16[5]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[11] mux_2level_tapbuf_size16[5]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[12] mux_2level_tapbuf_size16[5]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[13] mux_2level_tapbuf_size16[5]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[14] mux_2level_tapbuf_size16[5]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[15] mux_2level_tapbuf_size16[5]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[5] gvdd_mux_2level_tapbuf_size16[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[153] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[153] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[153] when v(mux_2level_tapbuf_size16[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[153] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[153] when v(mux_2level_tapbuf_size16[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[153] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[153] param='mux_2level_tapbuf_size16[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[5]_energy_per_cycle param='mux_2level_tapbuf_size16[5]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[153] param='mux_2level_tapbuf_size16[5]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[153] param='dynamic_power_cb_mux[1][1]_rrnode[153]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[153] avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='start_rise_cb_mux[1][1]_rrnode[153]' to='start_rise_cb_mux[1][1]_rrnode[153]+switch_rise_cb_mux[1][1]_rrnode[153]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[153] avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='start_fall_cb_mux[1][1]_rrnode[153]' to='start_fall_cb_mux[1][1]_rrnode[153]+switch_fall_cb_mux[1][1]_rrnode[153]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[1][1]_rrnode[153]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[153]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to5] -+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[1][1]_rrnode[153]' -.meas tran sum_energy_per_cycle_cb_mux[0to5] -+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[153]' -Xmux_2level_tapbuf_size16[6] mux_2level_tapbuf_size16[6]->in[0] mux_2level_tapbuf_size16[6]->in[1] mux_2level_tapbuf_size16[6]->in[2] mux_2level_tapbuf_size16[6]->in[3] mux_2level_tapbuf_size16[6]->in[4] mux_2level_tapbuf_size16[6]->in[5] mux_2level_tapbuf_size16[6]->in[6] mux_2level_tapbuf_size16[6]->in[7] mux_2level_tapbuf_size16[6]->in[8] mux_2level_tapbuf_size16[6]->in[9] mux_2level_tapbuf_size16[6]->in[10] mux_2level_tapbuf_size16[6]->in[11] mux_2level_tapbuf_size16[6]->in[12] mux_2level_tapbuf_size16[6]->in[13] mux_2level_tapbuf_size16[6]->in[14] mux_2level_tapbuf_size16[6]->in[15] mux_2level_tapbuf_size16[6]->out sram[48]->outb sram[48]->out sram[49]->out sram[49]->outb sram[50]->out sram[50]->outb sram[51]->out sram[51]->outb sram[52]->out sram[52]->outb sram[53]->out sram[53]->outb sram[54]->outb sram[54]->out sram[55]->out sram[55]->outb gvdd_mux_2level_tapbuf_size16[6] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[6], level=2, select_path_id=2. ***** -*****10000010***** -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -***** Signal mux_2level_tapbuf_size16[6]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[0] mux_2level_tapbuf_size16[6]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[1] mux_2level_tapbuf_size16[6]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[2] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[6]->in[2] mux_2level_tapbuf_size16[6]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[6]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[3] mux_2level_tapbuf_size16[6]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[4] mux_2level_tapbuf_size16[6]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[5] mux_2level_tapbuf_size16[6]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[6] mux_2level_tapbuf_size16[6]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[7] mux_2level_tapbuf_size16[6]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[8] mux_2level_tapbuf_size16[6]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[9] mux_2level_tapbuf_size16[6]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[10] mux_2level_tapbuf_size16[6]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[11] mux_2level_tapbuf_size16[6]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[12] mux_2level_tapbuf_size16[6]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[13] mux_2level_tapbuf_size16[6]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[14] mux_2level_tapbuf_size16[6]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[15] mux_2level_tapbuf_size16[6]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[6] gvdd_mux_2level_tapbuf_size16[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[155] trig v(mux_2level_tapbuf_size16[6]->in[2]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[155] trig v(mux_2level_tapbuf_size16[6]->in[2]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[155] when v(mux_2level_tapbuf_size16[6]->in[2])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[155] trig v(mux_2level_tapbuf_size16[6]->in[2]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[155] when v(mux_2level_tapbuf_size16[6]->in[2])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[155] trig v(mux_2level_tapbuf_size16[6]->in[2]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[155] param='mux_2level_tapbuf_size16[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[6]_energy_per_cycle param='mux_2level_tapbuf_size16[6]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[155] param='mux_2level_tapbuf_size16[6]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[155] param='dynamic_power_cb_mux[1][1]_rrnode[155]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[155] avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='start_rise_cb_mux[1][1]_rrnode[155]' to='start_rise_cb_mux[1][1]_rrnode[155]+switch_rise_cb_mux[1][1]_rrnode[155]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[155] avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='start_fall_cb_mux[1][1]_rrnode[155]' to='start_fall_cb_mux[1][1]_rrnode[155]+switch_fall_cb_mux[1][1]_rrnode[155]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[1][1]_rrnode[155]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[155]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to6] -+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[1][1]_rrnode[155]' -.meas tran sum_energy_per_cycle_cb_mux[0to6] -+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[155]' -Xmux_2level_tapbuf_size16[7] mux_2level_tapbuf_size16[7]->in[0] mux_2level_tapbuf_size16[7]->in[1] mux_2level_tapbuf_size16[7]->in[2] mux_2level_tapbuf_size16[7]->in[3] mux_2level_tapbuf_size16[7]->in[4] mux_2level_tapbuf_size16[7]->in[5] mux_2level_tapbuf_size16[7]->in[6] mux_2level_tapbuf_size16[7]->in[7] mux_2level_tapbuf_size16[7]->in[8] mux_2level_tapbuf_size16[7]->in[9] mux_2level_tapbuf_size16[7]->in[10] mux_2level_tapbuf_size16[7]->in[11] mux_2level_tapbuf_size16[7]->in[12] mux_2level_tapbuf_size16[7]->in[13] mux_2level_tapbuf_size16[7]->in[14] mux_2level_tapbuf_size16[7]->in[15] mux_2level_tapbuf_size16[7]->out sram[56]->outb sram[56]->out sram[57]->out sram[57]->outb sram[58]->out sram[58]->outb sram[59]->out sram[59]->outb sram[60]->outb sram[60]->out sram[61]->out sram[61]->outb sram[62]->out sram[62]->outb sram[63]->out sram[63]->outb gvdd_mux_2level_tapbuf_size16[7] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -***** Signal mux_2level_tapbuf_size16[7]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[0] mux_2level_tapbuf_size16[7]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[1] mux_2level_tapbuf_size16[7]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[2] mux_2level_tapbuf_size16[7]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[3] mux_2level_tapbuf_size16[7]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[4] mux_2level_tapbuf_size16[7]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[5] mux_2level_tapbuf_size16[7]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[6] mux_2level_tapbuf_size16[7]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[7] mux_2level_tapbuf_size16[7]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[8] mux_2level_tapbuf_size16[7]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[9] mux_2level_tapbuf_size16[7]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[10] mux_2level_tapbuf_size16[7]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[11] mux_2level_tapbuf_size16[7]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[12] mux_2level_tapbuf_size16[7]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[13] mux_2level_tapbuf_size16[7]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[14] mux_2level_tapbuf_size16[7]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[15] mux_2level_tapbuf_size16[7]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[7] gvdd_mux_2level_tapbuf_size16[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[157] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[157] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[157] when v(mux_2level_tapbuf_size16[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[157] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[157] when v(mux_2level_tapbuf_size16[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[157] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[157] param='mux_2level_tapbuf_size16[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[7]_energy_per_cycle param='mux_2level_tapbuf_size16[7]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[157] param='mux_2level_tapbuf_size16[7]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[157] param='dynamic_power_cb_mux[1][1]_rrnode[157]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[157] avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='start_rise_cb_mux[1][1]_rrnode[157]' to='start_rise_cb_mux[1][1]_rrnode[157]+switch_rise_cb_mux[1][1]_rrnode[157]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[157] avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='start_fall_cb_mux[1][1]_rrnode[157]' to='start_fall_cb_mux[1][1]_rrnode[157]+switch_fall_cb_mux[1][1]_rrnode[157]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[1][1]_rrnode[157]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[157]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to7] -+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[1][1]_rrnode[157]' -.meas tran sum_energy_per_cycle_cb_mux[0to7] -+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[157]' -Xmux_2level_tapbuf_size16[8] mux_2level_tapbuf_size16[8]->in[0] mux_2level_tapbuf_size16[8]->in[1] mux_2level_tapbuf_size16[8]->in[2] mux_2level_tapbuf_size16[8]->in[3] mux_2level_tapbuf_size16[8]->in[4] mux_2level_tapbuf_size16[8]->in[5] mux_2level_tapbuf_size16[8]->in[6] mux_2level_tapbuf_size16[8]->in[7] mux_2level_tapbuf_size16[8]->in[8] mux_2level_tapbuf_size16[8]->in[9] mux_2level_tapbuf_size16[8]->in[10] mux_2level_tapbuf_size16[8]->in[11] mux_2level_tapbuf_size16[8]->in[12] mux_2level_tapbuf_size16[8]->in[13] mux_2level_tapbuf_size16[8]->in[14] mux_2level_tapbuf_size16[8]->in[15] mux_2level_tapbuf_size16[8]->out sram[64]->outb sram[64]->out sram[65]->out sram[65]->outb sram[66]->out sram[66]->outb sram[67]->out sram[67]->outb sram[68]->outb sram[68]->out sram[69]->out sram[69]->outb sram[70]->out sram[70]->outb sram[71]->out sram[71]->outb gvdd_mux_2level_tapbuf_size16[8] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -***** Signal mux_2level_tapbuf_size16[8]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[0] mux_2level_tapbuf_size16[8]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[1] mux_2level_tapbuf_size16[8]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[2] mux_2level_tapbuf_size16[8]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[3] mux_2level_tapbuf_size16[8]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[4] mux_2level_tapbuf_size16[8]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[5] mux_2level_tapbuf_size16[8]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[6] mux_2level_tapbuf_size16[8]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[7] mux_2level_tapbuf_size16[8]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[8] mux_2level_tapbuf_size16[8]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[9] mux_2level_tapbuf_size16[8]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[10] mux_2level_tapbuf_size16[8]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[11] mux_2level_tapbuf_size16[8]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[12] mux_2level_tapbuf_size16[8]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[13] mux_2level_tapbuf_size16[8]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[14] mux_2level_tapbuf_size16[8]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[15] mux_2level_tapbuf_size16[8]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[8] gvdd_mux_2level_tapbuf_size16[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[76] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[76] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[76] when v(mux_2level_tapbuf_size16[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[76] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[76] when v(mux_2level_tapbuf_size16[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[76] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[76] param='mux_2level_tapbuf_size16[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[8]_energy_per_cycle param='mux_2level_tapbuf_size16[8]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[76] param='mux_2level_tapbuf_size16[8]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[76] param='dynamic_power_cb_mux[1][1]_rrnode[76]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[76] avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='start_rise_cb_mux[1][1]_rrnode[76]' to='start_rise_cb_mux[1][1]_rrnode[76]+switch_rise_cb_mux[1][1]_rrnode[76]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[76] avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='start_fall_cb_mux[1][1]_rrnode[76]' to='start_fall_cb_mux[1][1]_rrnode[76]+switch_fall_cb_mux[1][1]_rrnode[76]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[1][1]_rrnode[76]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[76]' -******* Normal TYPE loads ******* -Xload_inv[0]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[31]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to8] -+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[1][1]_rrnode[76]' -.meas tran sum_energy_per_cycle_cb_mux[0to8] -+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[76]' -Xmux_2level_tapbuf_size16[9] mux_2level_tapbuf_size16[9]->in[0] mux_2level_tapbuf_size16[9]->in[1] mux_2level_tapbuf_size16[9]->in[2] mux_2level_tapbuf_size16[9]->in[3] mux_2level_tapbuf_size16[9]->in[4] mux_2level_tapbuf_size16[9]->in[5] mux_2level_tapbuf_size16[9]->in[6] mux_2level_tapbuf_size16[9]->in[7] mux_2level_tapbuf_size16[9]->in[8] mux_2level_tapbuf_size16[9]->in[9] mux_2level_tapbuf_size16[9]->in[10] mux_2level_tapbuf_size16[9]->in[11] mux_2level_tapbuf_size16[9]->in[12] mux_2level_tapbuf_size16[9]->in[13] mux_2level_tapbuf_size16[9]->in[14] mux_2level_tapbuf_size16[9]->in[15] mux_2level_tapbuf_size16[9]->out sram[72]->outb sram[72]->out sram[73]->out sram[73]->outb sram[74]->out sram[74]->outb sram[75]->out sram[75]->outb sram[76]->outb sram[76]->out sram[77]->out sram[77]->outb sram[78]->out sram[78]->outb sram[79]->out sram[79]->outb gvdd_mux_2level_tapbuf_size16[9] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[9], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -***** Signal mux_2level_tapbuf_size16[9]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[0] mux_2level_tapbuf_size16[9]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[1] mux_2level_tapbuf_size16[9]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[2] mux_2level_tapbuf_size16[9]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[3] mux_2level_tapbuf_size16[9]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[4] mux_2level_tapbuf_size16[9]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[5] mux_2level_tapbuf_size16[9]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[6] mux_2level_tapbuf_size16[9]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[7] mux_2level_tapbuf_size16[9]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[8] mux_2level_tapbuf_size16[9]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[9] mux_2level_tapbuf_size16[9]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[10] mux_2level_tapbuf_size16[9]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[11] mux_2level_tapbuf_size16[9]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[12] mux_2level_tapbuf_size16[9]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[13] mux_2level_tapbuf_size16[9]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[14] mux_2level_tapbuf_size16[9]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[15] mux_2level_tapbuf_size16[9]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[9] gvdd_mux_2level_tapbuf_size16[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[80] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[80] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[80] when v(mux_2level_tapbuf_size16[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[80] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[80] when v(mux_2level_tapbuf_size16[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[80] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[9]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[80] param='mux_2level_tapbuf_size16[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[9]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[9]_energy_per_cycle param='mux_2level_tapbuf_size16[9]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[80] param='mux_2level_tapbuf_size16[9]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[80] param='dynamic_power_cb_mux[1][1]_rrnode[80]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[80] avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='start_rise_cb_mux[1][1]_rrnode[80]' to='start_rise_cb_mux[1][1]_rrnode[80]+switch_rise_cb_mux[1][1]_rrnode[80]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[80] avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='start_fall_cb_mux[1][1]_rrnode[80]' to='start_fall_cb_mux[1][1]_rrnode[80]+switch_fall_cb_mux[1][1]_rrnode[80]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_cb_mux[1][1]_rrnode[80]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_cb_mux[1][1]_rrnode[80]' -******* Normal TYPE loads ******* -Xload_inv[60]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[78]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[109]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[112]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to9] -+ param='sum_leakage_power_cb_mux[0to8]+leakage_cb_mux[1][1]_rrnode[80]' -.meas tran sum_energy_per_cycle_cb_mux[0to9] -+ param='sum_energy_per_cycle_cb_mux[0to8]+energy_per_cycle_cb_mux[1][1]_rrnode[80]' -Xmux_2level_tapbuf_size16[10] mux_2level_tapbuf_size16[10]->in[0] mux_2level_tapbuf_size16[10]->in[1] mux_2level_tapbuf_size16[10]->in[2] mux_2level_tapbuf_size16[10]->in[3] mux_2level_tapbuf_size16[10]->in[4] mux_2level_tapbuf_size16[10]->in[5] mux_2level_tapbuf_size16[10]->in[6] mux_2level_tapbuf_size16[10]->in[7] mux_2level_tapbuf_size16[10]->in[8] mux_2level_tapbuf_size16[10]->in[9] mux_2level_tapbuf_size16[10]->in[10] mux_2level_tapbuf_size16[10]->in[11] mux_2level_tapbuf_size16[10]->in[12] mux_2level_tapbuf_size16[10]->in[13] mux_2level_tapbuf_size16[10]->in[14] mux_2level_tapbuf_size16[10]->in[15] mux_2level_tapbuf_size16[10]->out sram[80]->outb sram[80]->out sram[81]->out sram[81]->outb sram[82]->out sram[82]->outb sram[83]->out sram[83]->outb sram[84]->outb sram[84]->out sram[85]->out sram[85]->outb sram[86]->out sram[86]->outb sram[87]->out sram[87]->outb gvdd_mux_2level_tapbuf_size16[10] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[10], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -***** Signal mux_2level_tapbuf_size16[10]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[0] mux_2level_tapbuf_size16[10]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[1] mux_2level_tapbuf_size16[10]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[2] mux_2level_tapbuf_size16[10]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[3] mux_2level_tapbuf_size16[10]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[4] mux_2level_tapbuf_size16[10]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[5] mux_2level_tapbuf_size16[10]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[6] mux_2level_tapbuf_size16[10]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[7] mux_2level_tapbuf_size16[10]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[8] mux_2level_tapbuf_size16[10]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[9] mux_2level_tapbuf_size16[10]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[10] mux_2level_tapbuf_size16[10]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[11] mux_2level_tapbuf_size16[10]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[12] mux_2level_tapbuf_size16[10]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[13] mux_2level_tapbuf_size16[10]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[14] mux_2level_tapbuf_size16[10]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[15] mux_2level_tapbuf_size16[10]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[10] gvdd_mux_2level_tapbuf_size16[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[84] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[84] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[84] when v(mux_2level_tapbuf_size16[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[84] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[84] when v(mux_2level_tapbuf_size16[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[84] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[10]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[84] param='mux_2level_tapbuf_size16[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[10]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[10]_energy_per_cycle param='mux_2level_tapbuf_size16[10]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[84] param='mux_2level_tapbuf_size16[10]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[84] param='dynamic_power_cb_mux[1][1]_rrnode[84]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[84] avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='start_rise_cb_mux[1][1]_rrnode[84]' to='start_rise_cb_mux[1][1]_rrnode[84]+switch_rise_cb_mux[1][1]_rrnode[84]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[84] avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='start_fall_cb_mux[1][1]_rrnode[84]' to='start_fall_cb_mux[1][1]_rrnode[84]+switch_fall_cb_mux[1][1]_rrnode[84]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_cb_mux[1][1]_rrnode[84]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_cb_mux[1][1]_rrnode[84]' -******* Normal TYPE loads ******* -Xload_inv[120]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[125]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[128]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[130]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to10] -+ param='sum_leakage_power_cb_mux[0to9]+leakage_cb_mux[1][1]_rrnode[84]' -.meas tran sum_energy_per_cycle_cb_mux[0to10] -+ param='sum_energy_per_cycle_cb_mux[0to9]+energy_per_cycle_cb_mux[1][1]_rrnode[84]' -Xmux_2level_tapbuf_size16[11] mux_2level_tapbuf_size16[11]->in[0] mux_2level_tapbuf_size16[11]->in[1] mux_2level_tapbuf_size16[11]->in[2] mux_2level_tapbuf_size16[11]->in[3] mux_2level_tapbuf_size16[11]->in[4] mux_2level_tapbuf_size16[11]->in[5] mux_2level_tapbuf_size16[11]->in[6] mux_2level_tapbuf_size16[11]->in[7] mux_2level_tapbuf_size16[11]->in[8] mux_2level_tapbuf_size16[11]->in[9] mux_2level_tapbuf_size16[11]->in[10] mux_2level_tapbuf_size16[11]->in[11] mux_2level_tapbuf_size16[11]->in[12] mux_2level_tapbuf_size16[11]->in[13] mux_2level_tapbuf_size16[11]->in[14] mux_2level_tapbuf_size16[11]->in[15] mux_2level_tapbuf_size16[11]->out sram[88]->outb sram[88]->out sram[89]->out sram[89]->outb sram[90]->out sram[90]->outb sram[91]->out sram[91]->outb sram[92]->outb sram[92]->out sram[93]->out sram[93]->outb sram[94]->out sram[94]->outb sram[95]->out sram[95]->outb gvdd_mux_2level_tapbuf_size16[11] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[11], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -***** Signal mux_2level_tapbuf_size16[11]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[0] mux_2level_tapbuf_size16[11]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[1] mux_2level_tapbuf_size16[11]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[2] mux_2level_tapbuf_size16[11]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[3] mux_2level_tapbuf_size16[11]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[4] mux_2level_tapbuf_size16[11]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[5] mux_2level_tapbuf_size16[11]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[6] mux_2level_tapbuf_size16[11]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[7] mux_2level_tapbuf_size16[11]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[8] mux_2level_tapbuf_size16[11]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[9] mux_2level_tapbuf_size16[11]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[10] mux_2level_tapbuf_size16[11]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[11] mux_2level_tapbuf_size16[11]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[12] mux_2level_tapbuf_size16[11]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[13] mux_2level_tapbuf_size16[11]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[14] mux_2level_tapbuf_size16[11]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[15] mux_2level_tapbuf_size16[11]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[11] gvdd_mux_2level_tapbuf_size16[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[88] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[88] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[88] when v(mux_2level_tapbuf_size16[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[88] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[88] when v(mux_2level_tapbuf_size16[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[88] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[11]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[88] param='mux_2level_tapbuf_size16[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[11]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[11]_energy_per_cycle param='mux_2level_tapbuf_size16[11]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[88] param='mux_2level_tapbuf_size16[11]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[88] param='dynamic_power_cb_mux[1][1]_rrnode[88]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[88] avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='start_rise_cb_mux[1][1]_rrnode[88]' to='start_rise_cb_mux[1][1]_rrnode[88]+switch_rise_cb_mux[1][1]_rrnode[88]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[88] avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='start_fall_cb_mux[1][1]_rrnode[88]' to='start_fall_cb_mux[1][1]_rrnode[88]+switch_fall_cb_mux[1][1]_rrnode[88]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_cb_mux[1][1]_rrnode[88]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_cb_mux[1][1]_rrnode[88]' -******* Normal TYPE loads ******* -Xload_inv[180]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to11] -+ param='sum_leakage_power_cb_mux[0to10]+leakage_cb_mux[1][1]_rrnode[88]' -.meas tran sum_energy_per_cycle_cb_mux[0to11] -+ param='sum_energy_per_cycle_cb_mux[0to10]+energy_per_cycle_cb_mux[1][1]_rrnode[88]' -Xmux_2level_tapbuf_size16[12] mux_2level_tapbuf_size16[12]->in[0] mux_2level_tapbuf_size16[12]->in[1] mux_2level_tapbuf_size16[12]->in[2] mux_2level_tapbuf_size16[12]->in[3] mux_2level_tapbuf_size16[12]->in[4] mux_2level_tapbuf_size16[12]->in[5] mux_2level_tapbuf_size16[12]->in[6] mux_2level_tapbuf_size16[12]->in[7] mux_2level_tapbuf_size16[12]->in[8] mux_2level_tapbuf_size16[12]->in[9] mux_2level_tapbuf_size16[12]->in[10] mux_2level_tapbuf_size16[12]->in[11] mux_2level_tapbuf_size16[12]->in[12] mux_2level_tapbuf_size16[12]->in[13] mux_2level_tapbuf_size16[12]->in[14] mux_2level_tapbuf_size16[12]->in[15] mux_2level_tapbuf_size16[12]->out sram[96]->outb sram[96]->out sram[97]->out sram[97]->outb sram[98]->out sram[98]->outb sram[99]->out sram[99]->outb sram[100]->outb sram[100]->out sram[101]->out sram[101]->outb sram[102]->out sram[102]->outb sram[103]->out sram[103]->outb gvdd_mux_2level_tapbuf_size16[12] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[12], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[100]->out) 0 -.nodeset V(sram[100]->outb) vsp -Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[101]->out) 0 -.nodeset V(sram[101]->outb) vsp -Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[102]->out) 0 -.nodeset V(sram[102]->outb) vsp -Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[103]->out) 0 -.nodeset V(sram[103]->outb) vsp -***** Signal mux_2level_tapbuf_size16[12]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[0] mux_2level_tapbuf_size16[12]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[1] mux_2level_tapbuf_size16[12]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[2] mux_2level_tapbuf_size16[12]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[3] mux_2level_tapbuf_size16[12]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[4] mux_2level_tapbuf_size16[12]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[5] mux_2level_tapbuf_size16[12]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[6] mux_2level_tapbuf_size16[12]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[7] mux_2level_tapbuf_size16[12]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[8] mux_2level_tapbuf_size16[12]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[9] mux_2level_tapbuf_size16[12]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[10] mux_2level_tapbuf_size16[12]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[11] mux_2level_tapbuf_size16[12]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[12] mux_2level_tapbuf_size16[12]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[13] mux_2level_tapbuf_size16[12]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[14] mux_2level_tapbuf_size16[12]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[15] mux_2level_tapbuf_size16[12]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[12] gvdd_mux_2level_tapbuf_size16[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[92] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[92] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[92] when v(mux_2level_tapbuf_size16[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[92] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[92] when v(mux_2level_tapbuf_size16[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[92] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[12]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[92] param='mux_2level_tapbuf_size16[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[12]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[12]_energy_per_cycle param='mux_2level_tapbuf_size16[12]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[92] param='mux_2level_tapbuf_size16[12]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[92] param='dynamic_power_cb_mux[1][1]_rrnode[92]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[92] avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='start_rise_cb_mux[1][1]_rrnode[92]' to='start_rise_cb_mux[1][1]_rrnode[92]+switch_rise_cb_mux[1][1]_rrnode[92]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[92] avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='start_fall_cb_mux[1][1]_rrnode[92]' to='start_fall_cb_mux[1][1]_rrnode[92]+switch_fall_cb_mux[1][1]_rrnode[92]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_cb_mux[1][1]_rrnode[92]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_cb_mux[1][1]_rrnode[92]' -******* Normal TYPE loads ******* -Xload_inv[240]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to12] -+ param='sum_leakage_power_cb_mux[0to11]+leakage_cb_mux[1][1]_rrnode[92]' -.meas tran sum_energy_per_cycle_cb_mux[0to12] -+ param='sum_energy_per_cycle_cb_mux[0to11]+energy_per_cycle_cb_mux[1][1]_rrnode[92]' -Xmux_2level_tapbuf_size16[13] mux_2level_tapbuf_size16[13]->in[0] mux_2level_tapbuf_size16[13]->in[1] mux_2level_tapbuf_size16[13]->in[2] mux_2level_tapbuf_size16[13]->in[3] mux_2level_tapbuf_size16[13]->in[4] mux_2level_tapbuf_size16[13]->in[5] mux_2level_tapbuf_size16[13]->in[6] mux_2level_tapbuf_size16[13]->in[7] mux_2level_tapbuf_size16[13]->in[8] mux_2level_tapbuf_size16[13]->in[9] mux_2level_tapbuf_size16[13]->in[10] mux_2level_tapbuf_size16[13]->in[11] mux_2level_tapbuf_size16[13]->in[12] mux_2level_tapbuf_size16[13]->in[13] mux_2level_tapbuf_size16[13]->in[14] mux_2level_tapbuf_size16[13]->in[15] mux_2level_tapbuf_size16[13]->out sram[104]->outb sram[104]->out sram[105]->out sram[105]->outb sram[106]->out sram[106]->outb sram[107]->out sram[107]->outb sram[108]->outb sram[108]->out sram[109]->out sram[109]->outb sram[110]->out sram[110]->outb sram[111]->out sram[111]->outb gvdd_mux_2level_tapbuf_size16[13] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[13], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[104]->out) 0 -.nodeset V(sram[104]->outb) vsp -Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[105]->out) 0 -.nodeset V(sram[105]->outb) vsp -Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[106]->out) 0 -.nodeset V(sram[106]->outb) vsp -Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[107]->out) 0 -.nodeset V(sram[107]->outb) vsp -Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[108]->out) 0 -.nodeset V(sram[108]->outb) vsp -Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[109]->out) 0 -.nodeset V(sram[109]->outb) vsp -Xsram[110] sram->in sram[110]->out sram[110]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[110]->out) 0 -.nodeset V(sram[110]->outb) vsp -Xsram[111] sram->in sram[111]->out sram[111]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[111]->out) 0 -.nodeset V(sram[111]->outb) vsp -***** Signal mux_2level_tapbuf_size16[13]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[0] mux_2level_tapbuf_size16[13]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[1] mux_2level_tapbuf_size16[13]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[2] mux_2level_tapbuf_size16[13]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[3] mux_2level_tapbuf_size16[13]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[4] mux_2level_tapbuf_size16[13]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[5] mux_2level_tapbuf_size16[13]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[6] mux_2level_tapbuf_size16[13]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[7] mux_2level_tapbuf_size16[13]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[8] mux_2level_tapbuf_size16[13]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[9] mux_2level_tapbuf_size16[13]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[10] mux_2level_tapbuf_size16[13]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[11] mux_2level_tapbuf_size16[13]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[12] mux_2level_tapbuf_size16[13]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[13] mux_2level_tapbuf_size16[13]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[14] mux_2level_tapbuf_size16[13]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[15] mux_2level_tapbuf_size16[13]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[13] gvdd_mux_2level_tapbuf_size16[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[96] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[96] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[96] when v(mux_2level_tapbuf_size16[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[96] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[96] when v(mux_2level_tapbuf_size16[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[96] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[13]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[96] param='mux_2level_tapbuf_size16[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[13]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[13]_energy_per_cycle param='mux_2level_tapbuf_size16[13]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[96] param='mux_2level_tapbuf_size16[13]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[96] param='dynamic_power_cb_mux[1][1]_rrnode[96]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[96] avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='start_rise_cb_mux[1][1]_rrnode[96]' to='start_rise_cb_mux[1][1]_rrnode[96]+switch_rise_cb_mux[1][1]_rrnode[96]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[96] avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='start_fall_cb_mux[1][1]_rrnode[96]' to='start_fall_cb_mux[1][1]_rrnode[96]+switch_fall_cb_mux[1][1]_rrnode[96]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_cb_mux[1][1]_rrnode[96]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_cb_mux[1][1]_rrnode[96]' -******* Normal TYPE loads ******* -Xload_inv[300]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[326]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[330]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[333]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[335]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[338]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[342]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[345]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[357]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to13] -+ param='sum_leakage_power_cb_mux[0to12]+leakage_cb_mux[1][1]_rrnode[96]' -.meas tran sum_energy_per_cycle_cb_mux[0to13] -+ param='sum_energy_per_cycle_cb_mux[0to12]+energy_per_cycle_cb_mux[1][1]_rrnode[96]' -Xmux_2level_tapbuf_size16[14] mux_2level_tapbuf_size16[14]->in[0] mux_2level_tapbuf_size16[14]->in[1] mux_2level_tapbuf_size16[14]->in[2] mux_2level_tapbuf_size16[14]->in[3] mux_2level_tapbuf_size16[14]->in[4] mux_2level_tapbuf_size16[14]->in[5] mux_2level_tapbuf_size16[14]->in[6] mux_2level_tapbuf_size16[14]->in[7] mux_2level_tapbuf_size16[14]->in[8] mux_2level_tapbuf_size16[14]->in[9] mux_2level_tapbuf_size16[14]->in[10] mux_2level_tapbuf_size16[14]->in[11] mux_2level_tapbuf_size16[14]->in[12] mux_2level_tapbuf_size16[14]->in[13] mux_2level_tapbuf_size16[14]->in[14] mux_2level_tapbuf_size16[14]->in[15] mux_2level_tapbuf_size16[14]->out sram[112]->outb sram[112]->out sram[113]->out sram[113]->outb sram[114]->out sram[114]->outb sram[115]->out sram[115]->outb sram[116]->outb sram[116]->out sram[117]->out sram[117]->outb sram[118]->out sram[118]->outb sram[119]->out sram[119]->outb gvdd_mux_2level_tapbuf_size16[14] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[14], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[112] sram->in sram[112]->out sram[112]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[112]->out) 0 -.nodeset V(sram[112]->outb) vsp -Xsram[113] sram->in sram[113]->out sram[113]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[113]->out) 0 -.nodeset V(sram[113]->outb) vsp -Xsram[114] sram->in sram[114]->out sram[114]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[114]->out) 0 -.nodeset V(sram[114]->outb) vsp -Xsram[115] sram->in sram[115]->out sram[115]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[115]->out) 0 -.nodeset V(sram[115]->outb) vsp -Xsram[116] sram->in sram[116]->out sram[116]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[116]->out) 0 -.nodeset V(sram[116]->outb) vsp -Xsram[117] sram->in sram[117]->out sram[117]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[117]->out) 0 -.nodeset V(sram[117]->outb) vsp -Xsram[118] sram->in sram[118]->out sram[118]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[118]->out) 0 -.nodeset V(sram[118]->outb) vsp -Xsram[119] sram->in sram[119]->out sram[119]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[119]->out) 0 -.nodeset V(sram[119]->outb) vsp -***** Signal mux_2level_tapbuf_size16[14]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[0] mux_2level_tapbuf_size16[14]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[1] mux_2level_tapbuf_size16[14]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[2] mux_2level_tapbuf_size16[14]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[3] mux_2level_tapbuf_size16[14]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[4] mux_2level_tapbuf_size16[14]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[5] mux_2level_tapbuf_size16[14]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[6] mux_2level_tapbuf_size16[14]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[7] mux_2level_tapbuf_size16[14]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[8] mux_2level_tapbuf_size16[14]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[9] mux_2level_tapbuf_size16[14]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[10] mux_2level_tapbuf_size16[14]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[11] mux_2level_tapbuf_size16[14]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[12] mux_2level_tapbuf_size16[14]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[13] mux_2level_tapbuf_size16[14]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[14] mux_2level_tapbuf_size16[14]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[15] mux_2level_tapbuf_size16[14]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[14] gvdd_mux_2level_tapbuf_size16[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[100] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[100] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[100] when v(mux_2level_tapbuf_size16[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[100] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[100] when v(mux_2level_tapbuf_size16[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[100] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[14]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[100] param='mux_2level_tapbuf_size16[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[14]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[14]_energy_per_cycle param='mux_2level_tapbuf_size16[14]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[100] param='mux_2level_tapbuf_size16[14]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[100] param='dynamic_power_cb_mux[1][1]_rrnode[100]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[100] avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='start_rise_cb_mux[1][1]_rrnode[100]' to='start_rise_cb_mux[1][1]_rrnode[100]+switch_rise_cb_mux[1][1]_rrnode[100]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[100] avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='start_fall_cb_mux[1][1]_rrnode[100]' to='start_fall_cb_mux[1][1]_rrnode[100]+switch_fall_cb_mux[1][1]_rrnode[100]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_cb_mux[1][1]_rrnode[100]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_cb_mux[1][1]_rrnode[100]' -******* Normal TYPE loads ******* -Xload_inv[360]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[365]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[369]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[381]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[384]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[388]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[389]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[390]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[391]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[392]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[393]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[394]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[395]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[396]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[397]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[398]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[399]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[400]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[401]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[402]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[403]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[404]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[405]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[406]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[407]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[408]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[409]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[410]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[411]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[412]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[413]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[414]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[415]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[416]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[417]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[418]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[419]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to14] -+ param='sum_leakage_power_cb_mux[0to13]+leakage_cb_mux[1][1]_rrnode[100]' -.meas tran sum_energy_per_cycle_cb_mux[0to14] -+ param='sum_energy_per_cycle_cb_mux[0to13]+energy_per_cycle_cb_mux[1][1]_rrnode[100]' -Xmux_2level_tapbuf_size16[15] mux_2level_tapbuf_size16[15]->in[0] mux_2level_tapbuf_size16[15]->in[1] mux_2level_tapbuf_size16[15]->in[2] mux_2level_tapbuf_size16[15]->in[3] mux_2level_tapbuf_size16[15]->in[4] mux_2level_tapbuf_size16[15]->in[5] mux_2level_tapbuf_size16[15]->in[6] mux_2level_tapbuf_size16[15]->in[7] mux_2level_tapbuf_size16[15]->in[8] mux_2level_tapbuf_size16[15]->in[9] mux_2level_tapbuf_size16[15]->in[10] mux_2level_tapbuf_size16[15]->in[11] mux_2level_tapbuf_size16[15]->in[12] mux_2level_tapbuf_size16[15]->in[13] mux_2level_tapbuf_size16[15]->in[14] mux_2level_tapbuf_size16[15]->in[15] mux_2level_tapbuf_size16[15]->out sram[120]->outb sram[120]->out sram[121]->out sram[121]->outb sram[122]->out sram[122]->outb sram[123]->out sram[123]->outb sram[124]->outb sram[124]->out sram[125]->out sram[125]->outb sram[126]->out sram[126]->outb sram[127]->out sram[127]->outb gvdd_mux_2level_tapbuf_size16[15] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[15], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[120] sram->in sram[120]->out sram[120]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[120]->out) 0 -.nodeset V(sram[120]->outb) vsp -Xsram[121] sram->in sram[121]->out sram[121]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[121]->out) 0 -.nodeset V(sram[121]->outb) vsp -Xsram[122] sram->in sram[122]->out sram[122]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[122]->out) 0 -.nodeset V(sram[122]->outb) vsp -Xsram[123] sram->in sram[123]->out sram[123]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[123]->out) 0 -.nodeset V(sram[123]->outb) vsp -Xsram[124] sram->in sram[124]->out sram[124]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[124]->out) 0 -.nodeset V(sram[124]->outb) vsp -Xsram[125] sram->in sram[125]->out sram[125]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[125]->out) 0 -.nodeset V(sram[125]->outb) vsp -Xsram[126] sram->in sram[126]->out sram[126]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[126]->out) 0 -.nodeset V(sram[126]->outb) vsp -Xsram[127] sram->in sram[127]->out sram[127]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[127]->out) 0 -.nodeset V(sram[127]->outb) vsp -***** Signal mux_2level_tapbuf_size16[15]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[0] mux_2level_tapbuf_size16[15]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[1] mux_2level_tapbuf_size16[15]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[2] mux_2level_tapbuf_size16[15]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[3] mux_2level_tapbuf_size16[15]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[4] mux_2level_tapbuf_size16[15]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[5] mux_2level_tapbuf_size16[15]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[6] mux_2level_tapbuf_size16[15]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[7] mux_2level_tapbuf_size16[15]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[8] mux_2level_tapbuf_size16[15]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[9] mux_2level_tapbuf_size16[15]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[10] mux_2level_tapbuf_size16[15]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[11] mux_2level_tapbuf_size16[15]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[12] mux_2level_tapbuf_size16[15]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[13] mux_2level_tapbuf_size16[15]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[14] mux_2level_tapbuf_size16[15]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[15] mux_2level_tapbuf_size16[15]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[15] gvdd_mux_2level_tapbuf_size16[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[104] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[104] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[104] when v(mux_2level_tapbuf_size16[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[104] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[104] when v(mux_2level_tapbuf_size16[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[104] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[15]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[104] param='mux_2level_tapbuf_size16[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[15]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[15]_energy_per_cycle param='mux_2level_tapbuf_size16[15]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[104] param='mux_2level_tapbuf_size16[15]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[104] param='dynamic_power_cb_mux[1][1]_rrnode[104]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[104] avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='start_rise_cb_mux[1][1]_rrnode[104]' to='start_rise_cb_mux[1][1]_rrnode[104]+switch_rise_cb_mux[1][1]_rrnode[104]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[104] avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='start_fall_cb_mux[1][1]_rrnode[104]' to='start_fall_cb_mux[1][1]_rrnode[104]+switch_fall_cb_mux[1][1]_rrnode[104]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_cb_mux[1][1]_rrnode[104]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_cb_mux[1][1]_rrnode[104]' -******* Normal TYPE loads ******* -Xload_inv[420]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[421]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[422]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[423]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[424]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[425]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[426]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[427]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[428]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[429]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[430]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[431]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[432]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[433]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[434]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[435]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[436]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[437]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[438]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[439]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[440]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[441]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[442]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[443]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[444]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[445]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[446]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[447]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[448]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[449]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[450]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[451]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[452]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[453]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[454]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[455]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[456]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[457]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[458]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[459]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[460]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[461]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[462]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[463]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[464]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[465]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[466]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[467]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[468]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[469]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[470]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[471]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[472]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[473]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[474]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[475]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[476]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[477]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[478]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[479]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to15] -+ param='sum_leakage_power_cb_mux[0to14]+leakage_cb_mux[1][1]_rrnode[104]' -.meas tran sum_energy_per_cycle_cb_mux[0to15] -+ param='sum_energy_per_cycle_cb_mux[0to14]+energy_per_cycle_cb_mux[1][1]_rrnode[104]' -Xmux_2level_tapbuf_size16[16] mux_2level_tapbuf_size16[16]->in[0] mux_2level_tapbuf_size16[16]->in[1] mux_2level_tapbuf_size16[16]->in[2] mux_2level_tapbuf_size16[16]->in[3] mux_2level_tapbuf_size16[16]->in[4] mux_2level_tapbuf_size16[16]->in[5] mux_2level_tapbuf_size16[16]->in[6] mux_2level_tapbuf_size16[16]->in[7] mux_2level_tapbuf_size16[16]->in[8] mux_2level_tapbuf_size16[16]->in[9] mux_2level_tapbuf_size16[16]->in[10] mux_2level_tapbuf_size16[16]->in[11] mux_2level_tapbuf_size16[16]->in[12] mux_2level_tapbuf_size16[16]->in[13] mux_2level_tapbuf_size16[16]->in[14] mux_2level_tapbuf_size16[16]->in[15] mux_2level_tapbuf_size16[16]->out sram[128]->outb sram[128]->out sram[129]->out sram[129]->outb sram[130]->out sram[130]->outb sram[131]->out sram[131]->outb sram[132]->outb sram[132]->out sram[133]->out sram[133]->outb sram[134]->out sram[134]->outb sram[135]->out sram[135]->outb gvdd_mux_2level_tapbuf_size16[16] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[16], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[128] sram->in sram[128]->out sram[128]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[128]->out) 0 -.nodeset V(sram[128]->outb) vsp -Xsram[129] sram->in sram[129]->out sram[129]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[129]->out) 0 -.nodeset V(sram[129]->outb) vsp -Xsram[130] sram->in sram[130]->out sram[130]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[130]->out) 0 -.nodeset V(sram[130]->outb) vsp -Xsram[131] sram->in sram[131]->out sram[131]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[131]->out) 0 -.nodeset V(sram[131]->outb) vsp -Xsram[132] sram->in sram[132]->out sram[132]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[132]->out) 0 -.nodeset V(sram[132]->outb) vsp -Xsram[133] sram->in sram[133]->out sram[133]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[133]->out) 0 -.nodeset V(sram[133]->outb) vsp -Xsram[134] sram->in sram[134]->out sram[134]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[134]->out) 0 -.nodeset V(sram[134]->outb) vsp -Xsram[135] sram->in sram[135]->out sram[135]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[135]->out) 0 -.nodeset V(sram[135]->outb) vsp -***** Signal mux_2level_tapbuf_size16[16]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[0] mux_2level_tapbuf_size16[16]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[1] mux_2level_tapbuf_size16[16]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[2] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[16]->in[2] mux_2level_tapbuf_size16[16]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[16]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[3] mux_2level_tapbuf_size16[16]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[4] mux_2level_tapbuf_size16[16]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[5] mux_2level_tapbuf_size16[16]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[6] mux_2level_tapbuf_size16[16]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[7] mux_2level_tapbuf_size16[16]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[8] mux_2level_tapbuf_size16[16]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[9] mux_2level_tapbuf_size16[16]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[10] mux_2level_tapbuf_size16[16]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[11] mux_2level_tapbuf_size16[16]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[12] mux_2level_tapbuf_size16[16]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[13] mux_2level_tapbuf_size16[16]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[14] mux_2level_tapbuf_size16[16]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[15] mux_2level_tapbuf_size16[16]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[16] gvdd_mux_2level_tapbuf_size16[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[108] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[108] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[108] when v(mux_2level_tapbuf_size16[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[108] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[108] when v(mux_2level_tapbuf_size16[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[108] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[16]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[108] param='mux_2level_tapbuf_size16[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[16]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[16]_energy_per_cycle param='mux_2level_tapbuf_size16[16]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[108] param='mux_2level_tapbuf_size16[16]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[108] param='dynamic_power_cb_mux[1][1]_rrnode[108]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[108] avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='start_rise_cb_mux[1][1]_rrnode[108]' to='start_rise_cb_mux[1][1]_rrnode[108]+switch_rise_cb_mux[1][1]_rrnode[108]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[108] avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='start_fall_cb_mux[1][1]_rrnode[108]' to='start_fall_cb_mux[1][1]_rrnode[108]+switch_fall_cb_mux[1][1]_rrnode[108]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_cb_mux[1][1]_rrnode[108]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_cb_mux[1][1]_rrnode[108]' -******* Normal TYPE loads ******* -Xload_inv[480]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[481]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[482]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[483]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[484]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[485]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[486]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[487]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[488]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[489]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[490]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[491]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[492]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[493]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[494]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[495]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[496]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[497]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[498]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[499]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[500]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[501]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[502]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[503]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[504]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[505]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[506]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[507]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[508]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[509]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[510]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[511]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[512]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[513]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[514]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[515]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[516]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[517]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[518]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[519]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[520]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[521]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[522]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[523]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[524]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[525]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[526]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[527]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[528]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[529]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[530]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[531]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[532]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[533]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[534]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[535]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[536]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[537]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[538]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[539]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to16] -+ param='sum_leakage_power_cb_mux[0to15]+leakage_cb_mux[1][1]_rrnode[108]' -.meas tran sum_energy_per_cycle_cb_mux[0to16] -+ param='sum_energy_per_cycle_cb_mux[0to15]+energy_per_cycle_cb_mux[1][1]_rrnode[108]' -Xmux_2level_tapbuf_size16[17] mux_2level_tapbuf_size16[17]->in[0] mux_2level_tapbuf_size16[17]->in[1] mux_2level_tapbuf_size16[17]->in[2] mux_2level_tapbuf_size16[17]->in[3] mux_2level_tapbuf_size16[17]->in[4] mux_2level_tapbuf_size16[17]->in[5] mux_2level_tapbuf_size16[17]->in[6] mux_2level_tapbuf_size16[17]->in[7] mux_2level_tapbuf_size16[17]->in[8] mux_2level_tapbuf_size16[17]->in[9] mux_2level_tapbuf_size16[17]->in[10] mux_2level_tapbuf_size16[17]->in[11] mux_2level_tapbuf_size16[17]->in[12] mux_2level_tapbuf_size16[17]->in[13] mux_2level_tapbuf_size16[17]->in[14] mux_2level_tapbuf_size16[17]->in[15] mux_2level_tapbuf_size16[17]->out sram[136]->outb sram[136]->out sram[137]->out sram[137]->outb sram[138]->out sram[138]->outb sram[139]->out sram[139]->outb sram[140]->outb sram[140]->out sram[141]->out sram[141]->outb sram[142]->out sram[142]->outb sram[143]->out sram[143]->outb gvdd_mux_2level_tapbuf_size16[17] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[17], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[136] sram->in sram[136]->out sram[136]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[136]->out) 0 -.nodeset V(sram[136]->outb) vsp -Xsram[137] sram->in sram[137]->out sram[137]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[137]->out) 0 -.nodeset V(sram[137]->outb) vsp -Xsram[138] sram->in sram[138]->out sram[138]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[138]->out) 0 -.nodeset V(sram[138]->outb) vsp -Xsram[139] sram->in sram[139]->out sram[139]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[139]->out) 0 -.nodeset V(sram[139]->outb) vsp -Xsram[140] sram->in sram[140]->out sram[140]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[140]->out) 0 -.nodeset V(sram[140]->outb) vsp -Xsram[141] sram->in sram[141]->out sram[141]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[141]->out) 0 -.nodeset V(sram[141]->outb) vsp -Xsram[142] sram->in sram[142]->out sram[142]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[142]->out) 0 -.nodeset V(sram[142]->outb) vsp -Xsram[143] sram->in sram[143]->out sram[143]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[143]->out) 0 -.nodeset V(sram[143]->outb) vsp -***** Signal mux_2level_tapbuf_size16[17]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[0] mux_2level_tapbuf_size16[17]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[1] mux_2level_tapbuf_size16[17]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[2] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[17]->in[2] mux_2level_tapbuf_size16[17]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[17]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[3] mux_2level_tapbuf_size16[17]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[4] mux_2level_tapbuf_size16[17]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[5] mux_2level_tapbuf_size16[17]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[6] mux_2level_tapbuf_size16[17]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[7] mux_2level_tapbuf_size16[17]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[8] mux_2level_tapbuf_size16[17]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[9] mux_2level_tapbuf_size16[17]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[10] mux_2level_tapbuf_size16[17]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[11] mux_2level_tapbuf_size16[17]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[12] mux_2level_tapbuf_size16[17]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[13] mux_2level_tapbuf_size16[17]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[14] mux_2level_tapbuf_size16[17]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[15] mux_2level_tapbuf_size16[17]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[17] gvdd_mux_2level_tapbuf_size16[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[112] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[112] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[112] when v(mux_2level_tapbuf_size16[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[112] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[112] when v(mux_2level_tapbuf_size16[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[112] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[17]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[112] param='mux_2level_tapbuf_size16[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[17]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[17]_energy_per_cycle param='mux_2level_tapbuf_size16[17]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[112] param='mux_2level_tapbuf_size16[17]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[112] param='dynamic_power_cb_mux[1][1]_rrnode[112]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[112] avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='start_rise_cb_mux[1][1]_rrnode[112]' to='start_rise_cb_mux[1][1]_rrnode[112]+switch_rise_cb_mux[1][1]_rrnode[112]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[112] avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='start_fall_cb_mux[1][1]_rrnode[112]' to='start_fall_cb_mux[1][1]_rrnode[112]+switch_fall_cb_mux[1][1]_rrnode[112]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_cb_mux[1][1]_rrnode[112]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_cb_mux[1][1]_rrnode[112]' -******* Normal TYPE loads ******* -Xload_inv[540]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[541]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[542]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[543]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[544]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[545]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[546]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[547]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[548]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[549]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[550]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[551]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[552]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[553]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[554]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[555]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[556]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[557]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[558]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[559]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[560]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[561]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[562]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[563]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[564]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[565]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[566]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[567]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[568]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[569]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[570]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[571]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[572]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[573]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[574]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[575]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[576]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[577]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[578]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[579]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[580]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[581]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[582]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[583]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[584]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[585]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[586]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[587]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[588]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[589]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[590]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[591]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[592]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[593]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[594]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[595]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[596]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[597]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[598]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[599]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to17] -+ param='sum_leakage_power_cb_mux[0to16]+leakage_cb_mux[1][1]_rrnode[112]' -.meas tran sum_energy_per_cycle_cb_mux[0to17] -+ param='sum_energy_per_cycle_cb_mux[0to16]+energy_per_cycle_cb_mux[1][1]_rrnode[112]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='6*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to17]' -.meas tran total_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to17]' -.meas tran total_leakage_power_cb_mux -+ param='sum_leakage_power_cb_mux[0to17]' -.meas tran total_energy_per_cycle_cb_mux -+ param='sum_energy_per_cycle_cb_mux[0to17]' -.end diff --git a/examples/spice_test_example_2/cb_mux_tb/example_2_cby0_1_cbmux_testbench.sp b/examples/spice_test_example_2/cb_mux_tb/example_2_cby0_1_cbmux_testbench.sp deleted file mode 100644 index c2bd347ed..000000000 --- a/examples/spice_test_example_2/cb_mux_tb/example_2_cby0_1_cbmux_testbench.sp +++ /dev/null @@ -1,2702 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_2level_tapbuf_size16[0] mux_2level_tapbuf_size16[0]->in[0] mux_2level_tapbuf_size16[0]->in[1] mux_2level_tapbuf_size16[0]->in[2] mux_2level_tapbuf_size16[0]->in[3] mux_2level_tapbuf_size16[0]->in[4] mux_2level_tapbuf_size16[0]->in[5] mux_2level_tapbuf_size16[0]->in[6] mux_2level_tapbuf_size16[0]->in[7] mux_2level_tapbuf_size16[0]->in[8] mux_2level_tapbuf_size16[0]->in[9] mux_2level_tapbuf_size16[0]->in[10] mux_2level_tapbuf_size16[0]->in[11] mux_2level_tapbuf_size16[0]->in[12] mux_2level_tapbuf_size16[0]->in[13] mux_2level_tapbuf_size16[0]->in[14] mux_2level_tapbuf_size16[0]->in[15] mux_2level_tapbuf_size16[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb sram[3]->out sram[3]->outb sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->out sram[6]->outb sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size16[0] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_2level_tapbuf_size16[0]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[0] mux_2level_tapbuf_size16[0]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[1] mux_2level_tapbuf_size16[0]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[2] mux_2level_tapbuf_size16[0]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[3] mux_2level_tapbuf_size16[0]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[4] mux_2level_tapbuf_size16[0]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[5] mux_2level_tapbuf_size16[0]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[6] mux_2level_tapbuf_size16[0]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[7] mux_2level_tapbuf_size16[0]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[8] mux_2level_tapbuf_size16[0]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[9] mux_2level_tapbuf_size16[0]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[10] mux_2level_tapbuf_size16[0]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[11] mux_2level_tapbuf_size16[0]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[12] mux_2level_tapbuf_size16[0]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[13] mux_2level_tapbuf_size16[0]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[14] mux_2level_tapbuf_size16[0]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[15] mux_2level_tapbuf_size16[0]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[0] gvdd_mux_2level_tapbuf_size16[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[79] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[79] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[79] when v(mux_2level_tapbuf_size16[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[79] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[79] when v(mux_2level_tapbuf_size16[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[79] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[79] param='mux_2level_tapbuf_size16[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[0]_energy_per_cycle param='mux_2level_tapbuf_size16[0]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[79] param='mux_2level_tapbuf_size16[0]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[79] param='dynamic_power_cb_mux[0][1]_rrnode[79]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[79] avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='start_rise_cb_mux[0][1]_rrnode[79]' to='start_rise_cb_mux[0][1]_rrnode[79]+switch_rise_cb_mux[0][1]_rrnode[79]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[79] avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='start_fall_cb_mux[0][1]_rrnode[79]' to='start_fall_cb_mux[0][1]_rrnode[79]+switch_fall_cb_mux[0][1]_rrnode[79]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_cb_mux[0][1]_rrnode[79]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_cb_mux[0][1]_rrnode[79]' -******* Normal TYPE loads ******* -Xload_inv[0]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[31]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 mux_2level_tapbuf_size16[0]->out mux_2level_tapbuf_size16[0]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to0] -+ param='leakage_cb_mux[0][1]_rrnode[79]' -.meas tran sum_energy_per_cycle_cb_mux[0to0] -+ param='energy_per_cycle_cb_mux[0][1]_rrnode[79]' -Xmux_2level_tapbuf_size16[1] mux_2level_tapbuf_size16[1]->in[0] mux_2level_tapbuf_size16[1]->in[1] mux_2level_tapbuf_size16[1]->in[2] mux_2level_tapbuf_size16[1]->in[3] mux_2level_tapbuf_size16[1]->in[4] mux_2level_tapbuf_size16[1]->in[5] mux_2level_tapbuf_size16[1]->in[6] mux_2level_tapbuf_size16[1]->in[7] mux_2level_tapbuf_size16[1]->in[8] mux_2level_tapbuf_size16[1]->in[9] mux_2level_tapbuf_size16[1]->in[10] mux_2level_tapbuf_size16[1]->in[11] mux_2level_tapbuf_size16[1]->in[12] mux_2level_tapbuf_size16[1]->in[13] mux_2level_tapbuf_size16[1]->in[14] mux_2level_tapbuf_size16[1]->in[15] mux_2level_tapbuf_size16[1]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->out sram[10]->outb sram[11]->out sram[11]->outb sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->out sram[14]->outb sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size16[1] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_2level_tapbuf_size16[1]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[0] mux_2level_tapbuf_size16[1]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[1] mux_2level_tapbuf_size16[1]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[2] mux_2level_tapbuf_size16[1]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[3] mux_2level_tapbuf_size16[1]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[4] mux_2level_tapbuf_size16[1]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[5] mux_2level_tapbuf_size16[1]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[6] mux_2level_tapbuf_size16[1]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[7] mux_2level_tapbuf_size16[1]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[8] mux_2level_tapbuf_size16[1]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[9] mux_2level_tapbuf_size16[1]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[10] mux_2level_tapbuf_size16[1]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[11] mux_2level_tapbuf_size16[1]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[12] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[1]->in[12] mux_2level_tapbuf_size16[1]->in[12] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[1]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[13] mux_2level_tapbuf_size16[1]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[14] mux_2level_tapbuf_size16[1]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[15] mux_2level_tapbuf_size16[1]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[1] gvdd_mux_2level_tapbuf_size16[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[83] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[83] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[83] when v(mux_2level_tapbuf_size16[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[83] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[83] when v(mux_2level_tapbuf_size16[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[83] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[83] param='mux_2level_tapbuf_size16[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[1]_energy_per_cycle param='mux_2level_tapbuf_size16[1]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[83] param='mux_2level_tapbuf_size16[1]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[83] param='dynamic_power_cb_mux[0][1]_rrnode[83]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[83] avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='start_rise_cb_mux[0][1]_rrnode[83]' to='start_rise_cb_mux[0][1]_rrnode[83]+switch_rise_cb_mux[0][1]_rrnode[83]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[83] avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='start_fall_cb_mux[0][1]_rrnode[83]' to='start_fall_cb_mux[0][1]_rrnode[83]+switch_fall_cb_mux[0][1]_rrnode[83]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[0][1]_rrnode[83]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[0][1]_rrnode[83]' -******* Normal TYPE loads ******* -Xload_inv[60]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[78]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[109]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[112]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 mux_2level_tapbuf_size16[1]->out mux_2level_tapbuf_size16[1]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to1] -+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[0][1]_rrnode[83]' -.meas tran sum_energy_per_cycle_cb_mux[0to1] -+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[0][1]_rrnode[83]' -Xmux_2level_tapbuf_size16[2] mux_2level_tapbuf_size16[2]->in[0] mux_2level_tapbuf_size16[2]->in[1] mux_2level_tapbuf_size16[2]->in[2] mux_2level_tapbuf_size16[2]->in[3] mux_2level_tapbuf_size16[2]->in[4] mux_2level_tapbuf_size16[2]->in[5] mux_2level_tapbuf_size16[2]->in[6] mux_2level_tapbuf_size16[2]->in[7] mux_2level_tapbuf_size16[2]->in[8] mux_2level_tapbuf_size16[2]->in[9] mux_2level_tapbuf_size16[2]->in[10] mux_2level_tapbuf_size16[2]->in[11] mux_2level_tapbuf_size16[2]->in[12] mux_2level_tapbuf_size16[2]->in[13] mux_2level_tapbuf_size16[2]->in[14] mux_2level_tapbuf_size16[2]->in[15] mux_2level_tapbuf_size16[2]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->out sram[18]->outb sram[19]->out sram[19]->outb sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->out sram[22]->outb sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size16[2] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_2level_tapbuf_size16[2]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[0] mux_2level_tapbuf_size16[2]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[1] mux_2level_tapbuf_size16[2]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[2] mux_2level_tapbuf_size16[2]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[3] mux_2level_tapbuf_size16[2]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[4] mux_2level_tapbuf_size16[2]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[5] mux_2level_tapbuf_size16[2]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[6] mux_2level_tapbuf_size16[2]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[7] mux_2level_tapbuf_size16[2]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[8] mux_2level_tapbuf_size16[2]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[9] mux_2level_tapbuf_size16[2]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[10] mux_2level_tapbuf_size16[2]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[11] mux_2level_tapbuf_size16[2]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[12] mux_2level_tapbuf_size16[2]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[13] mux_2level_tapbuf_size16[2]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[14] mux_2level_tapbuf_size16[2]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[15] mux_2level_tapbuf_size16[2]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[2] gvdd_mux_2level_tapbuf_size16[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[87] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[87] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[87] when v(mux_2level_tapbuf_size16[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[87] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[87] when v(mux_2level_tapbuf_size16[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[87] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[87] param='mux_2level_tapbuf_size16[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[2]_energy_per_cycle param='mux_2level_tapbuf_size16[2]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[87] param='mux_2level_tapbuf_size16[2]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[87] param='dynamic_power_cb_mux[0][1]_rrnode[87]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[87] avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='start_rise_cb_mux[0][1]_rrnode[87]' to='start_rise_cb_mux[0][1]_rrnode[87]+switch_rise_cb_mux[0][1]_rrnode[87]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[87] avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='start_fall_cb_mux[0][1]_rrnode[87]' to='start_fall_cb_mux[0][1]_rrnode[87]+switch_fall_cb_mux[0][1]_rrnode[87]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[0][1]_rrnode[87]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[0][1]_rrnode[87]' -******* Normal TYPE loads ******* -Xload_inv[120]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[125]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[128]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[130]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 mux_2level_tapbuf_size16[2]->out mux_2level_tapbuf_size16[2]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to2] -+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[0][1]_rrnode[87]' -.meas tran sum_energy_per_cycle_cb_mux[0to2] -+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[0][1]_rrnode[87]' -Xmux_2level_tapbuf_size16[3] mux_2level_tapbuf_size16[3]->in[0] mux_2level_tapbuf_size16[3]->in[1] mux_2level_tapbuf_size16[3]->in[2] mux_2level_tapbuf_size16[3]->in[3] mux_2level_tapbuf_size16[3]->in[4] mux_2level_tapbuf_size16[3]->in[5] mux_2level_tapbuf_size16[3]->in[6] mux_2level_tapbuf_size16[3]->in[7] mux_2level_tapbuf_size16[3]->in[8] mux_2level_tapbuf_size16[3]->in[9] mux_2level_tapbuf_size16[3]->in[10] mux_2level_tapbuf_size16[3]->in[11] mux_2level_tapbuf_size16[3]->in[12] mux_2level_tapbuf_size16[3]->in[13] mux_2level_tapbuf_size16[3]->in[14] mux_2level_tapbuf_size16[3]->in[15] mux_2level_tapbuf_size16[3]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->out sram[26]->outb sram[27]->out sram[27]->outb sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->out sram[30]->outb sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size16[3] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_2level_tapbuf_size16[3]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[0] mux_2level_tapbuf_size16[3]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[1] mux_2level_tapbuf_size16[3]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[2] mux_2level_tapbuf_size16[3]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[3] mux_2level_tapbuf_size16[3]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[4] mux_2level_tapbuf_size16[3]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[5] mux_2level_tapbuf_size16[3]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[6] mux_2level_tapbuf_size16[3]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[7] mux_2level_tapbuf_size16[3]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[8] mux_2level_tapbuf_size16[3]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[9] mux_2level_tapbuf_size16[3]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[10] mux_2level_tapbuf_size16[3]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[11] mux_2level_tapbuf_size16[3]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[12] mux_2level_tapbuf_size16[3]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[13] mux_2level_tapbuf_size16[3]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[14] mux_2level_tapbuf_size16[3]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[15] mux_2level_tapbuf_size16[3]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[3] gvdd_mux_2level_tapbuf_size16[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[91] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[91] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[91] when v(mux_2level_tapbuf_size16[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[91] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[91] when v(mux_2level_tapbuf_size16[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[91] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[91] param='mux_2level_tapbuf_size16[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[3]_energy_per_cycle param='mux_2level_tapbuf_size16[3]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[91] param='mux_2level_tapbuf_size16[3]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[91] param='dynamic_power_cb_mux[0][1]_rrnode[91]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[91] avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='start_rise_cb_mux[0][1]_rrnode[91]' to='start_rise_cb_mux[0][1]_rrnode[91]+switch_rise_cb_mux[0][1]_rrnode[91]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[91] avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='start_fall_cb_mux[0][1]_rrnode[91]' to='start_fall_cb_mux[0][1]_rrnode[91]+switch_fall_cb_mux[0][1]_rrnode[91]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[0][1]_rrnode[91]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[0][1]_rrnode[91]' -******* Normal TYPE loads ******* -Xload_inv[180]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 mux_2level_tapbuf_size16[3]->out mux_2level_tapbuf_size16[3]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to3] -+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[0][1]_rrnode[91]' -.meas tran sum_energy_per_cycle_cb_mux[0to3] -+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[0][1]_rrnode[91]' -Xmux_2level_tapbuf_size16[4] mux_2level_tapbuf_size16[4]->in[0] mux_2level_tapbuf_size16[4]->in[1] mux_2level_tapbuf_size16[4]->in[2] mux_2level_tapbuf_size16[4]->in[3] mux_2level_tapbuf_size16[4]->in[4] mux_2level_tapbuf_size16[4]->in[5] mux_2level_tapbuf_size16[4]->in[6] mux_2level_tapbuf_size16[4]->in[7] mux_2level_tapbuf_size16[4]->in[8] mux_2level_tapbuf_size16[4]->in[9] mux_2level_tapbuf_size16[4]->in[10] mux_2level_tapbuf_size16[4]->in[11] mux_2level_tapbuf_size16[4]->in[12] mux_2level_tapbuf_size16[4]->in[13] mux_2level_tapbuf_size16[4]->in[14] mux_2level_tapbuf_size16[4]->in[15] mux_2level_tapbuf_size16[4]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->out sram[34]->outb sram[35]->out sram[35]->outb sram[36]->outb sram[36]->out sram[37]->out sram[37]->outb sram[38]->out sram[38]->outb sram[39]->out sram[39]->outb gvdd_mux_2level_tapbuf_size16[4] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -***** Signal mux_2level_tapbuf_size16[4]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[0] mux_2level_tapbuf_size16[4]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[1] mux_2level_tapbuf_size16[4]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[2] mux_2level_tapbuf_size16[4]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[3] mux_2level_tapbuf_size16[4]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[4] mux_2level_tapbuf_size16[4]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[5] mux_2level_tapbuf_size16[4]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[6] mux_2level_tapbuf_size16[4]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[7] mux_2level_tapbuf_size16[4]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[8] mux_2level_tapbuf_size16[4]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[9] mux_2level_tapbuf_size16[4]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[10] mux_2level_tapbuf_size16[4]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[11] mux_2level_tapbuf_size16[4]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[12] mux_2level_tapbuf_size16[4]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[13] mux_2level_tapbuf_size16[4]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[14] mux_2level_tapbuf_size16[4]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[15] mux_2level_tapbuf_size16[4]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[4] gvdd_mux_2level_tapbuf_size16[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[95] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[95] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[95] when v(mux_2level_tapbuf_size16[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[95] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[95] when v(mux_2level_tapbuf_size16[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[95] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[95] param='mux_2level_tapbuf_size16[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[4]_energy_per_cycle param='mux_2level_tapbuf_size16[4]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[95] param='mux_2level_tapbuf_size16[4]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[95] param='dynamic_power_cb_mux[0][1]_rrnode[95]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[95] avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='start_rise_cb_mux[0][1]_rrnode[95]' to='start_rise_cb_mux[0][1]_rrnode[95]+switch_rise_cb_mux[0][1]_rrnode[95]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[95] avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='start_fall_cb_mux[0][1]_rrnode[95]' to='start_fall_cb_mux[0][1]_rrnode[95]+switch_fall_cb_mux[0][1]_rrnode[95]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[0][1]_rrnode[95]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[0][1]_rrnode[95]' -******* Normal TYPE loads ******* -Xload_inv[240]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 mux_2level_tapbuf_size16[4]->out mux_2level_tapbuf_size16[4]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to4] -+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[0][1]_rrnode[95]' -.meas tran sum_energy_per_cycle_cb_mux[0to4] -+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[0][1]_rrnode[95]' -Xmux_2level_tapbuf_size16[5] mux_2level_tapbuf_size16[5]->in[0] mux_2level_tapbuf_size16[5]->in[1] mux_2level_tapbuf_size16[5]->in[2] mux_2level_tapbuf_size16[5]->in[3] mux_2level_tapbuf_size16[5]->in[4] mux_2level_tapbuf_size16[5]->in[5] mux_2level_tapbuf_size16[5]->in[6] mux_2level_tapbuf_size16[5]->in[7] mux_2level_tapbuf_size16[5]->in[8] mux_2level_tapbuf_size16[5]->in[9] mux_2level_tapbuf_size16[5]->in[10] mux_2level_tapbuf_size16[5]->in[11] mux_2level_tapbuf_size16[5]->in[12] mux_2level_tapbuf_size16[5]->in[13] mux_2level_tapbuf_size16[5]->in[14] mux_2level_tapbuf_size16[5]->in[15] mux_2level_tapbuf_size16[5]->out sram[40]->outb sram[40]->out sram[41]->out sram[41]->outb sram[42]->out sram[42]->outb sram[43]->out sram[43]->outb sram[44]->outb sram[44]->out sram[45]->out sram[45]->outb sram[46]->out sram[46]->outb sram[47]->out sram[47]->outb gvdd_mux_2level_tapbuf_size16[5] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[5], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -***** Signal mux_2level_tapbuf_size16[5]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[0] mux_2level_tapbuf_size16[5]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[1] mux_2level_tapbuf_size16[5]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[2] mux_2level_tapbuf_size16[5]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[3] mux_2level_tapbuf_size16[5]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[4] mux_2level_tapbuf_size16[5]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[5] mux_2level_tapbuf_size16[5]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[6] mux_2level_tapbuf_size16[5]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[7] mux_2level_tapbuf_size16[5]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[8] mux_2level_tapbuf_size16[5]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[9] mux_2level_tapbuf_size16[5]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[10] mux_2level_tapbuf_size16[5]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[11] mux_2level_tapbuf_size16[5]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[12] mux_2level_tapbuf_size16[5]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[13] mux_2level_tapbuf_size16[5]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[14] mux_2level_tapbuf_size16[5]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[15] mux_2level_tapbuf_size16[5]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[5] gvdd_mux_2level_tapbuf_size16[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[99] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[99] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[99] when v(mux_2level_tapbuf_size16[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[99] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[99] when v(mux_2level_tapbuf_size16[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[99] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[99] param='mux_2level_tapbuf_size16[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[5]_energy_per_cycle param='mux_2level_tapbuf_size16[5]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[99] param='mux_2level_tapbuf_size16[5]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[99] param='dynamic_power_cb_mux[0][1]_rrnode[99]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[99] avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='start_rise_cb_mux[0][1]_rrnode[99]' to='start_rise_cb_mux[0][1]_rrnode[99]+switch_rise_cb_mux[0][1]_rrnode[99]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[99] avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='start_fall_cb_mux[0][1]_rrnode[99]' to='start_fall_cb_mux[0][1]_rrnode[99]+switch_fall_cb_mux[0][1]_rrnode[99]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[0][1]_rrnode[99]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[0][1]_rrnode[99]' -******* Normal TYPE loads ******* -Xload_inv[300]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[326]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[330]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[333]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[335]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[338]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[342]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[345]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[357]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 mux_2level_tapbuf_size16[5]->out mux_2level_tapbuf_size16[5]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to5] -+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[0][1]_rrnode[99]' -.meas tran sum_energy_per_cycle_cb_mux[0to5] -+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[0][1]_rrnode[99]' -Xmux_2level_tapbuf_size16[6] mux_2level_tapbuf_size16[6]->in[0] mux_2level_tapbuf_size16[6]->in[1] mux_2level_tapbuf_size16[6]->in[2] mux_2level_tapbuf_size16[6]->in[3] mux_2level_tapbuf_size16[6]->in[4] mux_2level_tapbuf_size16[6]->in[5] mux_2level_tapbuf_size16[6]->in[6] mux_2level_tapbuf_size16[6]->in[7] mux_2level_tapbuf_size16[6]->in[8] mux_2level_tapbuf_size16[6]->in[9] mux_2level_tapbuf_size16[6]->in[10] mux_2level_tapbuf_size16[6]->in[11] mux_2level_tapbuf_size16[6]->in[12] mux_2level_tapbuf_size16[6]->in[13] mux_2level_tapbuf_size16[6]->in[14] mux_2level_tapbuf_size16[6]->in[15] mux_2level_tapbuf_size16[6]->out sram[48]->outb sram[48]->out sram[49]->out sram[49]->outb sram[50]->out sram[50]->outb sram[51]->out sram[51]->outb sram[52]->outb sram[52]->out sram[53]->out sram[53]->outb sram[54]->out sram[54]->outb sram[55]->out sram[55]->outb gvdd_mux_2level_tapbuf_size16[6] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -***** Signal mux_2level_tapbuf_size16[6]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[0] mux_2level_tapbuf_size16[6]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[1] mux_2level_tapbuf_size16[6]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[2] mux_2level_tapbuf_size16[6]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[3] mux_2level_tapbuf_size16[6]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[4] mux_2level_tapbuf_size16[6]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[5] mux_2level_tapbuf_size16[6]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[6] mux_2level_tapbuf_size16[6]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[7] mux_2level_tapbuf_size16[6]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[8] mux_2level_tapbuf_size16[6]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[9] mux_2level_tapbuf_size16[6]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[10] mux_2level_tapbuf_size16[6]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[11] mux_2level_tapbuf_size16[6]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[12] mux_2level_tapbuf_size16[6]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[13] mux_2level_tapbuf_size16[6]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[14] mux_2level_tapbuf_size16[6]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[15] mux_2level_tapbuf_size16[6]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[6] gvdd_mux_2level_tapbuf_size16[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[103] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[103] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[103] when v(mux_2level_tapbuf_size16[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[103] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[103] when v(mux_2level_tapbuf_size16[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[103] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[103] param='mux_2level_tapbuf_size16[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[6]_energy_per_cycle param='mux_2level_tapbuf_size16[6]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[103] param='mux_2level_tapbuf_size16[6]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[103] param='dynamic_power_cb_mux[0][1]_rrnode[103]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[103] avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='start_rise_cb_mux[0][1]_rrnode[103]' to='start_rise_cb_mux[0][1]_rrnode[103]+switch_rise_cb_mux[0][1]_rrnode[103]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[103] avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='start_fall_cb_mux[0][1]_rrnode[103]' to='start_fall_cb_mux[0][1]_rrnode[103]+switch_fall_cb_mux[0][1]_rrnode[103]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[0][1]_rrnode[103]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[0][1]_rrnode[103]' -******* Normal TYPE loads ******* -Xload_inv[360]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[365]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[369]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[381]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[384]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[388]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[389]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[390]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[391]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[392]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[393]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[394]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[395]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[396]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[397]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[398]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[399]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[400]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[401]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[402]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[403]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[404]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[405]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[406]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[407]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[408]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[409]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[410]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[411]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[412]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[413]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[414]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[415]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[416]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[417]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[418]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[419]_no0 mux_2level_tapbuf_size16[6]->out mux_2level_tapbuf_size16[6]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to6] -+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[0][1]_rrnode[103]' -.meas tran sum_energy_per_cycle_cb_mux[0to6] -+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[0][1]_rrnode[103]' -Xmux_2level_tapbuf_size16[7] mux_2level_tapbuf_size16[7]->in[0] mux_2level_tapbuf_size16[7]->in[1] mux_2level_tapbuf_size16[7]->in[2] mux_2level_tapbuf_size16[7]->in[3] mux_2level_tapbuf_size16[7]->in[4] mux_2level_tapbuf_size16[7]->in[5] mux_2level_tapbuf_size16[7]->in[6] mux_2level_tapbuf_size16[7]->in[7] mux_2level_tapbuf_size16[7]->in[8] mux_2level_tapbuf_size16[7]->in[9] mux_2level_tapbuf_size16[7]->in[10] mux_2level_tapbuf_size16[7]->in[11] mux_2level_tapbuf_size16[7]->in[12] mux_2level_tapbuf_size16[7]->in[13] mux_2level_tapbuf_size16[7]->in[14] mux_2level_tapbuf_size16[7]->in[15] mux_2level_tapbuf_size16[7]->out sram[56]->outb sram[56]->out sram[57]->out sram[57]->outb sram[58]->out sram[58]->outb sram[59]->out sram[59]->outb sram[60]->outb sram[60]->out sram[61]->out sram[61]->outb sram[62]->out sram[62]->outb sram[63]->out sram[63]->outb gvdd_mux_2level_tapbuf_size16[7] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -***** Signal mux_2level_tapbuf_size16[7]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[0] mux_2level_tapbuf_size16[7]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[1] mux_2level_tapbuf_size16[7]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[2] mux_2level_tapbuf_size16[7]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[3] mux_2level_tapbuf_size16[7]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[4] mux_2level_tapbuf_size16[7]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[5] mux_2level_tapbuf_size16[7]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[6] mux_2level_tapbuf_size16[7]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[7] mux_2level_tapbuf_size16[7]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[8] mux_2level_tapbuf_size16[7]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[9] mux_2level_tapbuf_size16[7]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[10] mux_2level_tapbuf_size16[7]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[11] mux_2level_tapbuf_size16[7]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[12] mux_2level_tapbuf_size16[7]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[13] mux_2level_tapbuf_size16[7]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[14] mux_2level_tapbuf_size16[7]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[15] mux_2level_tapbuf_size16[7]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[7] gvdd_mux_2level_tapbuf_size16[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[107] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[107] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[107] when v(mux_2level_tapbuf_size16[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[107] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[107] when v(mux_2level_tapbuf_size16[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[107] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[107] param='mux_2level_tapbuf_size16[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[7]_energy_per_cycle param='mux_2level_tapbuf_size16[7]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[107] param='mux_2level_tapbuf_size16[7]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[107] param='dynamic_power_cb_mux[0][1]_rrnode[107]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[107] avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='start_rise_cb_mux[0][1]_rrnode[107]' to='start_rise_cb_mux[0][1]_rrnode[107]+switch_rise_cb_mux[0][1]_rrnode[107]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[107] avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='start_fall_cb_mux[0][1]_rrnode[107]' to='start_fall_cb_mux[0][1]_rrnode[107]+switch_fall_cb_mux[0][1]_rrnode[107]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[0][1]_rrnode[107]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[0][1]_rrnode[107]' -******* Normal TYPE loads ******* -Xload_inv[420]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[421]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[422]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[423]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[424]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[425]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[426]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[427]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[428]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[429]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[430]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[431]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[432]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[433]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[434]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[435]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[436]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[437]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[438]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[439]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[440]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[441]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[442]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[443]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[444]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[445]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[446]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[447]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[448]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[449]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[450]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[451]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[452]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[453]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[454]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[455]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[456]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[457]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[458]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[459]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[460]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[461]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[462]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[463]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[464]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[465]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[466]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[467]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[468]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[469]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[470]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[471]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[472]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[473]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[474]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[475]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[476]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[477]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[478]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[479]_no0 mux_2level_tapbuf_size16[7]->out mux_2level_tapbuf_size16[7]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to7] -+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[0][1]_rrnode[107]' -.meas tran sum_energy_per_cycle_cb_mux[0to7] -+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[0][1]_rrnode[107]' -Xmux_2level_tapbuf_size16[8] mux_2level_tapbuf_size16[8]->in[0] mux_2level_tapbuf_size16[8]->in[1] mux_2level_tapbuf_size16[8]->in[2] mux_2level_tapbuf_size16[8]->in[3] mux_2level_tapbuf_size16[8]->in[4] mux_2level_tapbuf_size16[8]->in[5] mux_2level_tapbuf_size16[8]->in[6] mux_2level_tapbuf_size16[8]->in[7] mux_2level_tapbuf_size16[8]->in[8] mux_2level_tapbuf_size16[8]->in[9] mux_2level_tapbuf_size16[8]->in[10] mux_2level_tapbuf_size16[8]->in[11] mux_2level_tapbuf_size16[8]->in[12] mux_2level_tapbuf_size16[8]->in[13] mux_2level_tapbuf_size16[8]->in[14] mux_2level_tapbuf_size16[8]->in[15] mux_2level_tapbuf_size16[8]->out sram[64]->outb sram[64]->out sram[65]->out sram[65]->outb sram[66]->out sram[66]->outb sram[67]->out sram[67]->outb sram[68]->outb sram[68]->out sram[69]->out sram[69]->outb sram[70]->out sram[70]->outb sram[71]->out sram[71]->outb gvdd_mux_2level_tapbuf_size16[8] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -***** Signal mux_2level_tapbuf_size16[8]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[0] mux_2level_tapbuf_size16[8]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[1] mux_2level_tapbuf_size16[8]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[2] mux_2level_tapbuf_size16[8]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[3] mux_2level_tapbuf_size16[8]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[4] mux_2level_tapbuf_size16[8]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[5] mux_2level_tapbuf_size16[8]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[6] mux_2level_tapbuf_size16[8]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[7] mux_2level_tapbuf_size16[8]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[8] mux_2level_tapbuf_size16[8]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[9] mux_2level_tapbuf_size16[8]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[10] mux_2level_tapbuf_size16[8]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[11] mux_2level_tapbuf_size16[8]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[12] mux_2level_tapbuf_size16[8]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[13] mux_2level_tapbuf_size16[8]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[14] mux_2level_tapbuf_size16[8]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[15] mux_2level_tapbuf_size16[8]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[8] gvdd_mux_2level_tapbuf_size16[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[111] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[111] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[111] when v(mux_2level_tapbuf_size16[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[111] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[111] when v(mux_2level_tapbuf_size16[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[111] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[111] param='mux_2level_tapbuf_size16[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[8]_energy_per_cycle param='mux_2level_tapbuf_size16[8]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[111] param='mux_2level_tapbuf_size16[8]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[111] param='dynamic_power_cb_mux[0][1]_rrnode[111]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[111] avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='start_rise_cb_mux[0][1]_rrnode[111]' to='start_rise_cb_mux[0][1]_rrnode[111]+switch_rise_cb_mux[0][1]_rrnode[111]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[111] avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='start_fall_cb_mux[0][1]_rrnode[111]' to='start_fall_cb_mux[0][1]_rrnode[111]+switch_fall_cb_mux[0][1]_rrnode[111]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[0][1]_rrnode[111]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[0][1]_rrnode[111]' -******* Normal TYPE loads ******* -Xload_inv[480]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[481]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[482]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[483]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[484]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[485]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[486]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[487]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[488]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[489]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[490]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[491]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[492]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[493]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[494]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[495]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[496]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[497]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[498]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[499]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[500]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[501]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[502]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[503]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[504]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[505]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[506]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[507]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[508]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[509]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[510]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[511]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[512]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[513]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[514]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[515]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[516]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[517]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[518]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[519]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[520]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[521]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[522]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[523]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[524]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[525]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[526]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[527]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[528]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[529]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[530]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[531]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[532]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[533]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[534]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[535]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[536]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[537]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[538]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[539]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to8] -+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[0][1]_rrnode[111]' -.meas tran sum_energy_per_cycle_cb_mux[0to8] -+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[0][1]_rrnode[111]' -Xmux_2level_tapbuf_size16[9] mux_2level_tapbuf_size16[9]->in[0] mux_2level_tapbuf_size16[9]->in[1] mux_2level_tapbuf_size16[9]->in[2] mux_2level_tapbuf_size16[9]->in[3] mux_2level_tapbuf_size16[9]->in[4] mux_2level_tapbuf_size16[9]->in[5] mux_2level_tapbuf_size16[9]->in[6] mux_2level_tapbuf_size16[9]->in[7] mux_2level_tapbuf_size16[9]->in[8] mux_2level_tapbuf_size16[9]->in[9] mux_2level_tapbuf_size16[9]->in[10] mux_2level_tapbuf_size16[9]->in[11] mux_2level_tapbuf_size16[9]->in[12] mux_2level_tapbuf_size16[9]->in[13] mux_2level_tapbuf_size16[9]->in[14] mux_2level_tapbuf_size16[9]->in[15] mux_2level_tapbuf_size16[9]->out sram[72]->outb sram[72]->out sram[73]->out sram[73]->outb sram[74]->out sram[74]->outb sram[75]->out sram[75]->outb sram[76]->outb sram[76]->out sram[77]->out sram[77]->outb sram[78]->out sram[78]->outb sram[79]->out sram[79]->outb gvdd_mux_2level_tapbuf_size16[9] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[9], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -***** Signal mux_2level_tapbuf_size16[9]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[0] mux_2level_tapbuf_size16[9]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[1] mux_2level_tapbuf_size16[9]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[2] mux_2level_tapbuf_size16[9]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[3] mux_2level_tapbuf_size16[9]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[4] mux_2level_tapbuf_size16[9]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[5] mux_2level_tapbuf_size16[9]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[6] mux_2level_tapbuf_size16[9]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[7] mux_2level_tapbuf_size16[9]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[8] mux_2level_tapbuf_size16[9]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[9] mux_2level_tapbuf_size16[9]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[10] mux_2level_tapbuf_size16[9]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[11] mux_2level_tapbuf_size16[9]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[12] mux_2level_tapbuf_size16[9]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[13] mux_2level_tapbuf_size16[9]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[14] mux_2level_tapbuf_size16[9]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[15] mux_2level_tapbuf_size16[9]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[9] gvdd_mux_2level_tapbuf_size16[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[115] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[115] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[115] when v(mux_2level_tapbuf_size16[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[115] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[115] when v(mux_2level_tapbuf_size16[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[115] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[9]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[115] param='mux_2level_tapbuf_size16[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[9]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[9]_energy_per_cycle param='mux_2level_tapbuf_size16[9]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[115] param='mux_2level_tapbuf_size16[9]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[115] param='dynamic_power_cb_mux[0][1]_rrnode[115]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[115] avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='start_rise_cb_mux[0][1]_rrnode[115]' to='start_rise_cb_mux[0][1]_rrnode[115]+switch_rise_cb_mux[0][1]_rrnode[115]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[115] avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='start_fall_cb_mux[0][1]_rrnode[115]' to='start_fall_cb_mux[0][1]_rrnode[115]+switch_fall_cb_mux[0][1]_rrnode[115]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_cb_mux[0][1]_rrnode[115]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_cb_mux[0][1]_rrnode[115]' -******* Normal TYPE loads ******* -Xload_inv[540]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[541]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[542]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[543]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[544]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[545]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[546]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[547]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[548]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[549]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[550]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[551]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[552]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[553]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[554]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[555]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[556]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[557]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[558]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[559]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[560]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[561]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[562]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[563]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[564]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[565]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[566]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[567]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[568]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[569]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[570]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[571]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[572]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[573]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[574]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[575]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[576]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[577]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[578]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[579]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[580]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[581]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[582]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[583]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[584]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[585]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[586]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[587]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[588]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[589]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[590]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[591]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[592]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[593]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[594]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[595]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[596]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[597]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[598]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[599]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to9] -+ param='sum_leakage_power_cb_mux[0to8]+leakage_cb_mux[0][1]_rrnode[115]' -.meas tran sum_energy_per_cycle_cb_mux[0to9] -+ param='sum_energy_per_cycle_cb_mux[0to8]+energy_per_cycle_cb_mux[0][1]_rrnode[115]' -Xmux_2level_tapbuf_size16[10] mux_2level_tapbuf_size16[10]->in[0] mux_2level_tapbuf_size16[10]->in[1] mux_2level_tapbuf_size16[10]->in[2] mux_2level_tapbuf_size16[10]->in[3] mux_2level_tapbuf_size16[10]->in[4] mux_2level_tapbuf_size16[10]->in[5] mux_2level_tapbuf_size16[10]->in[6] mux_2level_tapbuf_size16[10]->in[7] mux_2level_tapbuf_size16[10]->in[8] mux_2level_tapbuf_size16[10]->in[9] mux_2level_tapbuf_size16[10]->in[10] mux_2level_tapbuf_size16[10]->in[11] mux_2level_tapbuf_size16[10]->in[12] mux_2level_tapbuf_size16[10]->in[13] mux_2level_tapbuf_size16[10]->in[14] mux_2level_tapbuf_size16[10]->in[15] mux_2level_tapbuf_size16[10]->out sram[80]->outb sram[80]->out sram[81]->out sram[81]->outb sram[82]->out sram[82]->outb sram[83]->out sram[83]->outb sram[84]->outb sram[84]->out sram[85]->out sram[85]->outb sram[86]->out sram[86]->outb sram[87]->out sram[87]->outb gvdd_mux_2level_tapbuf_size16[10] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[10], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -***** Signal mux_2level_tapbuf_size16[10]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[0] mux_2level_tapbuf_size16[10]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[1] mux_2level_tapbuf_size16[10]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[2] mux_2level_tapbuf_size16[10]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[3] mux_2level_tapbuf_size16[10]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[4] mux_2level_tapbuf_size16[10]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[5] mux_2level_tapbuf_size16[10]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[6] mux_2level_tapbuf_size16[10]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[7] mux_2level_tapbuf_size16[10]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[8] mux_2level_tapbuf_size16[10]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[9] mux_2level_tapbuf_size16[10]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[10] mux_2level_tapbuf_size16[10]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[11] mux_2level_tapbuf_size16[10]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[12] mux_2level_tapbuf_size16[10]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[13] mux_2level_tapbuf_size16[10]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[14] mux_2level_tapbuf_size16[10]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[15] mux_2level_tapbuf_size16[10]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[10] gvdd_mux_2level_tapbuf_size16[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[16] when v(mux_2level_tapbuf_size16[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[16] when v(mux_2level_tapbuf_size16[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[16] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[10]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[16] param='mux_2level_tapbuf_size16[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[10]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[10]_energy_per_cycle param='mux_2level_tapbuf_size16[10]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[16] param='mux_2level_tapbuf_size16[10]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[16] param='dynamic_power_cb_mux[0][1]_rrnode[16]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[16] avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='start_rise_cb_mux[0][1]_rrnode[16]' to='start_rise_cb_mux[0][1]_rrnode[16]+switch_rise_cb_mux[0][1]_rrnode[16]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[16] avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='start_fall_cb_mux[0][1]_rrnode[16]' to='start_fall_cb_mux[0][1]_rrnode[16]+switch_fall_cb_mux[0][1]_rrnode[16]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_cb_mux[0][1]_rrnode[16]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_cb_mux[0][1]_rrnode[16]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to10] -+ param='sum_leakage_power_cb_mux[0to9]+leakage_cb_mux[0][1]_rrnode[16]' -.meas tran sum_energy_per_cycle_cb_mux[0to10] -+ param='sum_energy_per_cycle_cb_mux[0to9]+energy_per_cycle_cb_mux[0][1]_rrnode[16]' -Xmux_2level_tapbuf_size16[11] mux_2level_tapbuf_size16[11]->in[0] mux_2level_tapbuf_size16[11]->in[1] mux_2level_tapbuf_size16[11]->in[2] mux_2level_tapbuf_size16[11]->in[3] mux_2level_tapbuf_size16[11]->in[4] mux_2level_tapbuf_size16[11]->in[5] mux_2level_tapbuf_size16[11]->in[6] mux_2level_tapbuf_size16[11]->in[7] mux_2level_tapbuf_size16[11]->in[8] mux_2level_tapbuf_size16[11]->in[9] mux_2level_tapbuf_size16[11]->in[10] mux_2level_tapbuf_size16[11]->in[11] mux_2level_tapbuf_size16[11]->in[12] mux_2level_tapbuf_size16[11]->in[13] mux_2level_tapbuf_size16[11]->in[14] mux_2level_tapbuf_size16[11]->in[15] mux_2level_tapbuf_size16[11]->out sram[88]->outb sram[88]->out sram[89]->out sram[89]->outb sram[90]->out sram[90]->outb sram[91]->out sram[91]->outb sram[92]->outb sram[92]->out sram[93]->out sram[93]->outb sram[94]->out sram[94]->outb sram[95]->out sram[95]->outb gvdd_mux_2level_tapbuf_size16[11] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[11], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -***** Signal mux_2level_tapbuf_size16[11]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[0] mux_2level_tapbuf_size16[11]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[1] mux_2level_tapbuf_size16[11]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[2] mux_2level_tapbuf_size16[11]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[3] mux_2level_tapbuf_size16[11]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[4] mux_2level_tapbuf_size16[11]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[5] mux_2level_tapbuf_size16[11]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[6] mux_2level_tapbuf_size16[11]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[7] mux_2level_tapbuf_size16[11]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[8] mux_2level_tapbuf_size16[11]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[9] mux_2level_tapbuf_size16[11]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[10] mux_2level_tapbuf_size16[11]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[11] mux_2level_tapbuf_size16[11]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[12] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[11]->in[12] mux_2level_tapbuf_size16[11]->in[12] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[11]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[13] mux_2level_tapbuf_size16[11]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[14] mux_2level_tapbuf_size16[11]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[15] mux_2level_tapbuf_size16[11]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[11] gvdd_mux_2level_tapbuf_size16[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[18] when v(mux_2level_tapbuf_size16[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[18] when v(mux_2level_tapbuf_size16[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[18] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[11]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[18] param='mux_2level_tapbuf_size16[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[11]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[11]_energy_per_cycle param='mux_2level_tapbuf_size16[11]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[18] param='mux_2level_tapbuf_size16[11]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[18] param='dynamic_power_cb_mux[0][1]_rrnode[18]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[18] avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='start_rise_cb_mux[0][1]_rrnode[18]' to='start_rise_cb_mux[0][1]_rrnode[18]+switch_rise_cb_mux[0][1]_rrnode[18]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[18] avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='start_fall_cb_mux[0][1]_rrnode[18]' to='start_fall_cb_mux[0][1]_rrnode[18]+switch_fall_cb_mux[0][1]_rrnode[18]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_cb_mux[0][1]_rrnode[18]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_cb_mux[0][1]_rrnode[18]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to11] -+ param='sum_leakage_power_cb_mux[0to10]+leakage_cb_mux[0][1]_rrnode[18]' -.meas tran sum_energy_per_cycle_cb_mux[0to11] -+ param='sum_energy_per_cycle_cb_mux[0to10]+energy_per_cycle_cb_mux[0][1]_rrnode[18]' -Xmux_2level_tapbuf_size16[12] mux_2level_tapbuf_size16[12]->in[0] mux_2level_tapbuf_size16[12]->in[1] mux_2level_tapbuf_size16[12]->in[2] mux_2level_tapbuf_size16[12]->in[3] mux_2level_tapbuf_size16[12]->in[4] mux_2level_tapbuf_size16[12]->in[5] mux_2level_tapbuf_size16[12]->in[6] mux_2level_tapbuf_size16[12]->in[7] mux_2level_tapbuf_size16[12]->in[8] mux_2level_tapbuf_size16[12]->in[9] mux_2level_tapbuf_size16[12]->in[10] mux_2level_tapbuf_size16[12]->in[11] mux_2level_tapbuf_size16[12]->in[12] mux_2level_tapbuf_size16[12]->in[13] mux_2level_tapbuf_size16[12]->in[14] mux_2level_tapbuf_size16[12]->in[15] mux_2level_tapbuf_size16[12]->out sram[96]->outb sram[96]->out sram[97]->out sram[97]->outb sram[98]->out sram[98]->outb sram[99]->out sram[99]->outb sram[100]->outb sram[100]->out sram[101]->out sram[101]->outb sram[102]->out sram[102]->outb sram[103]->out sram[103]->outb gvdd_mux_2level_tapbuf_size16[12] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[12], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[100]->out) 0 -.nodeset V(sram[100]->outb) vsp -Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[101]->out) 0 -.nodeset V(sram[101]->outb) vsp -Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[102]->out) 0 -.nodeset V(sram[102]->outb) vsp -Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[103]->out) 0 -.nodeset V(sram[103]->outb) vsp -***** Signal mux_2level_tapbuf_size16[12]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[0] mux_2level_tapbuf_size16[12]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[1] mux_2level_tapbuf_size16[12]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[2] mux_2level_tapbuf_size16[12]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[3] mux_2level_tapbuf_size16[12]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[4] mux_2level_tapbuf_size16[12]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[5] mux_2level_tapbuf_size16[12]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[6] mux_2level_tapbuf_size16[12]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[7] mux_2level_tapbuf_size16[12]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[8] mux_2level_tapbuf_size16[12]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[9] mux_2level_tapbuf_size16[12]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[10] mux_2level_tapbuf_size16[12]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[11] mux_2level_tapbuf_size16[12]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[12] mux_2level_tapbuf_size16[12]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[13] mux_2level_tapbuf_size16[12]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[14] mux_2level_tapbuf_size16[12]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[15] mux_2level_tapbuf_size16[12]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[12] gvdd_mux_2level_tapbuf_size16[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[20] when v(mux_2level_tapbuf_size16[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[20] when v(mux_2level_tapbuf_size16[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[20] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[12]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[20] param='mux_2level_tapbuf_size16[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[12]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[12]_energy_per_cycle param='mux_2level_tapbuf_size16[12]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[20] param='mux_2level_tapbuf_size16[12]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[20] param='dynamic_power_cb_mux[0][1]_rrnode[20]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[20] avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='start_rise_cb_mux[0][1]_rrnode[20]' to='start_rise_cb_mux[0][1]_rrnode[20]+switch_rise_cb_mux[0][1]_rrnode[20]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[20] avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='start_fall_cb_mux[0][1]_rrnode[20]' to='start_fall_cb_mux[0][1]_rrnode[20]+switch_fall_cb_mux[0][1]_rrnode[20]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_cb_mux[0][1]_rrnode[20]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_cb_mux[0][1]_rrnode[20]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to12] -+ param='sum_leakage_power_cb_mux[0to11]+leakage_cb_mux[0][1]_rrnode[20]' -.meas tran sum_energy_per_cycle_cb_mux[0to12] -+ param='sum_energy_per_cycle_cb_mux[0to11]+energy_per_cycle_cb_mux[0][1]_rrnode[20]' -Xmux_2level_tapbuf_size16[13] mux_2level_tapbuf_size16[13]->in[0] mux_2level_tapbuf_size16[13]->in[1] mux_2level_tapbuf_size16[13]->in[2] mux_2level_tapbuf_size16[13]->in[3] mux_2level_tapbuf_size16[13]->in[4] mux_2level_tapbuf_size16[13]->in[5] mux_2level_tapbuf_size16[13]->in[6] mux_2level_tapbuf_size16[13]->in[7] mux_2level_tapbuf_size16[13]->in[8] mux_2level_tapbuf_size16[13]->in[9] mux_2level_tapbuf_size16[13]->in[10] mux_2level_tapbuf_size16[13]->in[11] mux_2level_tapbuf_size16[13]->in[12] mux_2level_tapbuf_size16[13]->in[13] mux_2level_tapbuf_size16[13]->in[14] mux_2level_tapbuf_size16[13]->in[15] mux_2level_tapbuf_size16[13]->out sram[104]->outb sram[104]->out sram[105]->out sram[105]->outb sram[106]->out sram[106]->outb sram[107]->out sram[107]->outb sram[108]->outb sram[108]->out sram[109]->out sram[109]->outb sram[110]->out sram[110]->outb sram[111]->out sram[111]->outb gvdd_mux_2level_tapbuf_size16[13] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[13], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[104]->out) 0 -.nodeset V(sram[104]->outb) vsp -Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[105]->out) 0 -.nodeset V(sram[105]->outb) vsp -Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[106]->out) 0 -.nodeset V(sram[106]->outb) vsp -Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[107]->out) 0 -.nodeset V(sram[107]->outb) vsp -Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[108]->out) 0 -.nodeset V(sram[108]->outb) vsp -Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[109]->out) 0 -.nodeset V(sram[109]->outb) vsp -Xsram[110] sram->in sram[110]->out sram[110]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[110]->out) 0 -.nodeset V(sram[110]->outb) vsp -Xsram[111] sram->in sram[111]->out sram[111]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[111]->out) 0 -.nodeset V(sram[111]->outb) vsp -***** Signal mux_2level_tapbuf_size16[13]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[0] mux_2level_tapbuf_size16[13]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[1] mux_2level_tapbuf_size16[13]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[2] mux_2level_tapbuf_size16[13]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[3] mux_2level_tapbuf_size16[13]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[4] mux_2level_tapbuf_size16[13]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[5] mux_2level_tapbuf_size16[13]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[6] mux_2level_tapbuf_size16[13]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[7] mux_2level_tapbuf_size16[13]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[8] mux_2level_tapbuf_size16[13]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[9] mux_2level_tapbuf_size16[13]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[10] mux_2level_tapbuf_size16[13]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[11] mux_2level_tapbuf_size16[13]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[12] mux_2level_tapbuf_size16[13]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[13] mux_2level_tapbuf_size16[13]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[14] mux_2level_tapbuf_size16[13]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[15] mux_2level_tapbuf_size16[13]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[13] gvdd_mux_2level_tapbuf_size16[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[22] when v(mux_2level_tapbuf_size16[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[22] when v(mux_2level_tapbuf_size16[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[22] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[13]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[22] param='mux_2level_tapbuf_size16[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[13]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[13]_energy_per_cycle param='mux_2level_tapbuf_size16[13]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[22] param='mux_2level_tapbuf_size16[13]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[22] param='dynamic_power_cb_mux[0][1]_rrnode[22]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[22] avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='start_rise_cb_mux[0][1]_rrnode[22]' to='start_rise_cb_mux[0][1]_rrnode[22]+switch_rise_cb_mux[0][1]_rrnode[22]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[22] avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='start_fall_cb_mux[0][1]_rrnode[22]' to='start_fall_cb_mux[0][1]_rrnode[22]+switch_fall_cb_mux[0][1]_rrnode[22]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_cb_mux[0][1]_rrnode[22]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_cb_mux[0][1]_rrnode[22]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to13] -+ param='sum_leakage_power_cb_mux[0to12]+leakage_cb_mux[0][1]_rrnode[22]' -.meas tran sum_energy_per_cycle_cb_mux[0to13] -+ param='sum_energy_per_cycle_cb_mux[0to12]+energy_per_cycle_cb_mux[0][1]_rrnode[22]' -Xmux_2level_tapbuf_size16[14] mux_2level_tapbuf_size16[14]->in[0] mux_2level_tapbuf_size16[14]->in[1] mux_2level_tapbuf_size16[14]->in[2] mux_2level_tapbuf_size16[14]->in[3] mux_2level_tapbuf_size16[14]->in[4] mux_2level_tapbuf_size16[14]->in[5] mux_2level_tapbuf_size16[14]->in[6] mux_2level_tapbuf_size16[14]->in[7] mux_2level_tapbuf_size16[14]->in[8] mux_2level_tapbuf_size16[14]->in[9] mux_2level_tapbuf_size16[14]->in[10] mux_2level_tapbuf_size16[14]->in[11] mux_2level_tapbuf_size16[14]->in[12] mux_2level_tapbuf_size16[14]->in[13] mux_2level_tapbuf_size16[14]->in[14] mux_2level_tapbuf_size16[14]->in[15] mux_2level_tapbuf_size16[14]->out sram[112]->outb sram[112]->out sram[113]->out sram[113]->outb sram[114]->out sram[114]->outb sram[115]->out sram[115]->outb sram[116]->outb sram[116]->out sram[117]->out sram[117]->outb sram[118]->out sram[118]->outb sram[119]->out sram[119]->outb gvdd_mux_2level_tapbuf_size16[14] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[14], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[112] sram->in sram[112]->out sram[112]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[112]->out) 0 -.nodeset V(sram[112]->outb) vsp -Xsram[113] sram->in sram[113]->out sram[113]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[113]->out) 0 -.nodeset V(sram[113]->outb) vsp -Xsram[114] sram->in sram[114]->out sram[114]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[114]->out) 0 -.nodeset V(sram[114]->outb) vsp -Xsram[115] sram->in sram[115]->out sram[115]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[115]->out) 0 -.nodeset V(sram[115]->outb) vsp -Xsram[116] sram->in sram[116]->out sram[116]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[116]->out) 0 -.nodeset V(sram[116]->outb) vsp -Xsram[117] sram->in sram[117]->out sram[117]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[117]->out) 0 -.nodeset V(sram[117]->outb) vsp -Xsram[118] sram->in sram[118]->out sram[118]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[118]->out) 0 -.nodeset V(sram[118]->outb) vsp -Xsram[119] sram->in sram[119]->out sram[119]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[119]->out) 0 -.nodeset V(sram[119]->outb) vsp -***** Signal mux_2level_tapbuf_size16[14]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[0] mux_2level_tapbuf_size16[14]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[1] mux_2level_tapbuf_size16[14]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[2] mux_2level_tapbuf_size16[14]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[3] mux_2level_tapbuf_size16[14]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[4] mux_2level_tapbuf_size16[14]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[5] mux_2level_tapbuf_size16[14]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[6] mux_2level_tapbuf_size16[14]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[7] mux_2level_tapbuf_size16[14]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[8] mux_2level_tapbuf_size16[14]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[9] mux_2level_tapbuf_size16[14]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[10] mux_2level_tapbuf_size16[14]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[11] mux_2level_tapbuf_size16[14]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[12] mux_2level_tapbuf_size16[14]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[13] mux_2level_tapbuf_size16[14]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[14] mux_2level_tapbuf_size16[14]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[15] mux_2level_tapbuf_size16[14]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[14] gvdd_mux_2level_tapbuf_size16[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[24] when v(mux_2level_tapbuf_size16[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[24] when v(mux_2level_tapbuf_size16[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[24] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[14]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[24] param='mux_2level_tapbuf_size16[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[14]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[14]_energy_per_cycle param='mux_2level_tapbuf_size16[14]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[24] param='mux_2level_tapbuf_size16[14]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[24] param='dynamic_power_cb_mux[0][1]_rrnode[24]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[24] avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='start_rise_cb_mux[0][1]_rrnode[24]' to='start_rise_cb_mux[0][1]_rrnode[24]+switch_rise_cb_mux[0][1]_rrnode[24]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[24] avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='start_fall_cb_mux[0][1]_rrnode[24]' to='start_fall_cb_mux[0][1]_rrnode[24]+switch_fall_cb_mux[0][1]_rrnode[24]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_cb_mux[0][1]_rrnode[24]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_cb_mux[0][1]_rrnode[24]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to14] -+ param='sum_leakage_power_cb_mux[0to13]+leakage_cb_mux[0][1]_rrnode[24]' -.meas tran sum_energy_per_cycle_cb_mux[0to14] -+ param='sum_energy_per_cycle_cb_mux[0to13]+energy_per_cycle_cb_mux[0][1]_rrnode[24]' -Xmux_2level_tapbuf_size16[15] mux_2level_tapbuf_size16[15]->in[0] mux_2level_tapbuf_size16[15]->in[1] mux_2level_tapbuf_size16[15]->in[2] mux_2level_tapbuf_size16[15]->in[3] mux_2level_tapbuf_size16[15]->in[4] mux_2level_tapbuf_size16[15]->in[5] mux_2level_tapbuf_size16[15]->in[6] mux_2level_tapbuf_size16[15]->in[7] mux_2level_tapbuf_size16[15]->in[8] mux_2level_tapbuf_size16[15]->in[9] mux_2level_tapbuf_size16[15]->in[10] mux_2level_tapbuf_size16[15]->in[11] mux_2level_tapbuf_size16[15]->in[12] mux_2level_tapbuf_size16[15]->in[13] mux_2level_tapbuf_size16[15]->in[14] mux_2level_tapbuf_size16[15]->in[15] mux_2level_tapbuf_size16[15]->out sram[120]->outb sram[120]->out sram[121]->out sram[121]->outb sram[122]->out sram[122]->outb sram[123]->out sram[123]->outb sram[124]->outb sram[124]->out sram[125]->out sram[125]->outb sram[126]->out sram[126]->outb sram[127]->out sram[127]->outb gvdd_mux_2level_tapbuf_size16[15] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[15], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[120] sram->in sram[120]->out sram[120]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[120]->out) 0 -.nodeset V(sram[120]->outb) vsp -Xsram[121] sram->in sram[121]->out sram[121]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[121]->out) 0 -.nodeset V(sram[121]->outb) vsp -Xsram[122] sram->in sram[122]->out sram[122]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[122]->out) 0 -.nodeset V(sram[122]->outb) vsp -Xsram[123] sram->in sram[123]->out sram[123]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[123]->out) 0 -.nodeset V(sram[123]->outb) vsp -Xsram[124] sram->in sram[124]->out sram[124]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[124]->out) 0 -.nodeset V(sram[124]->outb) vsp -Xsram[125] sram->in sram[125]->out sram[125]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[125]->out) 0 -.nodeset V(sram[125]->outb) vsp -Xsram[126] sram->in sram[126]->out sram[126]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[126]->out) 0 -.nodeset V(sram[126]->outb) vsp -Xsram[127] sram->in sram[127]->out sram[127]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[127]->out) 0 -.nodeset V(sram[127]->outb) vsp -***** Signal mux_2level_tapbuf_size16[15]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[0] mux_2level_tapbuf_size16[15]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[1] mux_2level_tapbuf_size16[15]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[2] mux_2level_tapbuf_size16[15]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[3] mux_2level_tapbuf_size16[15]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[4] mux_2level_tapbuf_size16[15]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[5] mux_2level_tapbuf_size16[15]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[6] mux_2level_tapbuf_size16[15]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[7] mux_2level_tapbuf_size16[15]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[8] mux_2level_tapbuf_size16[15]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[9] mux_2level_tapbuf_size16[15]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[10] mux_2level_tapbuf_size16[15]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[11] mux_2level_tapbuf_size16[15]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[12] mux_2level_tapbuf_size16[15]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[13] mux_2level_tapbuf_size16[15]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[14] mux_2level_tapbuf_size16[15]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[15] mux_2level_tapbuf_size16[15]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[15] gvdd_mux_2level_tapbuf_size16[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[26] when v(mux_2level_tapbuf_size16[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[26] when v(mux_2level_tapbuf_size16[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[26] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[15]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[26] param='mux_2level_tapbuf_size16[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[15]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[15]_energy_per_cycle param='mux_2level_tapbuf_size16[15]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[26] param='mux_2level_tapbuf_size16[15]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[26] param='dynamic_power_cb_mux[0][1]_rrnode[26]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[26] avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='start_rise_cb_mux[0][1]_rrnode[26]' to='start_rise_cb_mux[0][1]_rrnode[26]+switch_rise_cb_mux[0][1]_rrnode[26]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[26] avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='start_fall_cb_mux[0][1]_rrnode[26]' to='start_fall_cb_mux[0][1]_rrnode[26]+switch_fall_cb_mux[0][1]_rrnode[26]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_cb_mux[0][1]_rrnode[26]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_cb_mux[0][1]_rrnode[26]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to15] -+ param='sum_leakage_power_cb_mux[0to14]+leakage_cb_mux[0][1]_rrnode[26]' -.meas tran sum_energy_per_cycle_cb_mux[0to15] -+ param='sum_energy_per_cycle_cb_mux[0to14]+energy_per_cycle_cb_mux[0][1]_rrnode[26]' -Xmux_2level_tapbuf_size16[16] mux_2level_tapbuf_size16[16]->in[0] mux_2level_tapbuf_size16[16]->in[1] mux_2level_tapbuf_size16[16]->in[2] mux_2level_tapbuf_size16[16]->in[3] mux_2level_tapbuf_size16[16]->in[4] mux_2level_tapbuf_size16[16]->in[5] mux_2level_tapbuf_size16[16]->in[6] mux_2level_tapbuf_size16[16]->in[7] mux_2level_tapbuf_size16[16]->in[8] mux_2level_tapbuf_size16[16]->in[9] mux_2level_tapbuf_size16[16]->in[10] mux_2level_tapbuf_size16[16]->in[11] mux_2level_tapbuf_size16[16]->in[12] mux_2level_tapbuf_size16[16]->in[13] mux_2level_tapbuf_size16[16]->in[14] mux_2level_tapbuf_size16[16]->in[15] mux_2level_tapbuf_size16[16]->out sram[128]->outb sram[128]->out sram[129]->out sram[129]->outb sram[130]->out sram[130]->outb sram[131]->out sram[131]->outb sram[132]->outb sram[132]->out sram[133]->out sram[133]->outb sram[134]->out sram[134]->outb sram[135]->out sram[135]->outb gvdd_mux_2level_tapbuf_size16[16] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[16], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[128] sram->in sram[128]->out sram[128]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[128]->out) 0 -.nodeset V(sram[128]->outb) vsp -Xsram[129] sram->in sram[129]->out sram[129]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[129]->out) 0 -.nodeset V(sram[129]->outb) vsp -Xsram[130] sram->in sram[130]->out sram[130]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[130]->out) 0 -.nodeset V(sram[130]->outb) vsp -Xsram[131] sram->in sram[131]->out sram[131]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[131]->out) 0 -.nodeset V(sram[131]->outb) vsp -Xsram[132] sram->in sram[132]->out sram[132]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[132]->out) 0 -.nodeset V(sram[132]->outb) vsp -Xsram[133] sram->in sram[133]->out sram[133]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[133]->out) 0 -.nodeset V(sram[133]->outb) vsp -Xsram[134] sram->in sram[134]->out sram[134]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[134]->out) 0 -.nodeset V(sram[134]->outb) vsp -Xsram[135] sram->in sram[135]->out sram[135]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[135]->out) 0 -.nodeset V(sram[135]->outb) vsp -***** Signal mux_2level_tapbuf_size16[16]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[0] mux_2level_tapbuf_size16[16]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[1] mux_2level_tapbuf_size16[16]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[2] mux_2level_tapbuf_size16[16]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[3] mux_2level_tapbuf_size16[16]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[4] mux_2level_tapbuf_size16[16]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[5] mux_2level_tapbuf_size16[16]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[6] mux_2level_tapbuf_size16[16]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[7] mux_2level_tapbuf_size16[16]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[8] mux_2level_tapbuf_size16[16]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[9] mux_2level_tapbuf_size16[16]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[10] mux_2level_tapbuf_size16[16]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[11] mux_2level_tapbuf_size16[16]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[12] mux_2level_tapbuf_size16[16]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[13] mux_2level_tapbuf_size16[16]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[14] mux_2level_tapbuf_size16[16]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[15] mux_2level_tapbuf_size16[16]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[16] gvdd_mux_2level_tapbuf_size16[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[28] when v(mux_2level_tapbuf_size16[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[28] when v(mux_2level_tapbuf_size16[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[28] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[16]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[28] param='mux_2level_tapbuf_size16[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[16]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[16]_energy_per_cycle param='mux_2level_tapbuf_size16[16]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[28] param='mux_2level_tapbuf_size16[16]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[28] param='dynamic_power_cb_mux[0][1]_rrnode[28]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[28] avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='start_rise_cb_mux[0][1]_rrnode[28]' to='start_rise_cb_mux[0][1]_rrnode[28]+switch_rise_cb_mux[0][1]_rrnode[28]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[28] avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='start_fall_cb_mux[0][1]_rrnode[28]' to='start_fall_cb_mux[0][1]_rrnode[28]+switch_fall_cb_mux[0][1]_rrnode[28]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_cb_mux[0][1]_rrnode[28]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_cb_mux[0][1]_rrnode[28]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to16] -+ param='sum_leakage_power_cb_mux[0to15]+leakage_cb_mux[0][1]_rrnode[28]' -.meas tran sum_energy_per_cycle_cb_mux[0to16] -+ param='sum_energy_per_cycle_cb_mux[0to15]+energy_per_cycle_cb_mux[0][1]_rrnode[28]' -Xmux_2level_tapbuf_size16[17] mux_2level_tapbuf_size16[17]->in[0] mux_2level_tapbuf_size16[17]->in[1] mux_2level_tapbuf_size16[17]->in[2] mux_2level_tapbuf_size16[17]->in[3] mux_2level_tapbuf_size16[17]->in[4] mux_2level_tapbuf_size16[17]->in[5] mux_2level_tapbuf_size16[17]->in[6] mux_2level_tapbuf_size16[17]->in[7] mux_2level_tapbuf_size16[17]->in[8] mux_2level_tapbuf_size16[17]->in[9] mux_2level_tapbuf_size16[17]->in[10] mux_2level_tapbuf_size16[17]->in[11] mux_2level_tapbuf_size16[17]->in[12] mux_2level_tapbuf_size16[17]->in[13] mux_2level_tapbuf_size16[17]->in[14] mux_2level_tapbuf_size16[17]->in[15] mux_2level_tapbuf_size16[17]->out sram[136]->outb sram[136]->out sram[137]->out sram[137]->outb sram[138]->out sram[138]->outb sram[139]->out sram[139]->outb sram[140]->outb sram[140]->out sram[141]->out sram[141]->outb sram[142]->out sram[142]->outb sram[143]->out sram[143]->outb gvdd_mux_2level_tapbuf_size16[17] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[17], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[136] sram->in sram[136]->out sram[136]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[136]->out) 0 -.nodeset V(sram[136]->outb) vsp -Xsram[137] sram->in sram[137]->out sram[137]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[137]->out) 0 -.nodeset V(sram[137]->outb) vsp -Xsram[138] sram->in sram[138]->out sram[138]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[138]->out) 0 -.nodeset V(sram[138]->outb) vsp -Xsram[139] sram->in sram[139]->out sram[139]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[139]->out) 0 -.nodeset V(sram[139]->outb) vsp -Xsram[140] sram->in sram[140]->out sram[140]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[140]->out) 0 -.nodeset V(sram[140]->outb) vsp -Xsram[141] sram->in sram[141]->out sram[141]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[141]->out) 0 -.nodeset V(sram[141]->outb) vsp -Xsram[142] sram->in sram[142]->out sram[142]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[142]->out) 0 -.nodeset V(sram[142]->outb) vsp -Xsram[143] sram->in sram[143]->out sram[143]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[143]->out) 0 -.nodeset V(sram[143]->outb) vsp -***** Signal mux_2level_tapbuf_size16[17]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[0] mux_2level_tapbuf_size16[17]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[1] mux_2level_tapbuf_size16[17]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[2] mux_2level_tapbuf_size16[17]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[3] mux_2level_tapbuf_size16[17]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[4] mux_2level_tapbuf_size16[17]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[5] mux_2level_tapbuf_size16[17]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[6] mux_2level_tapbuf_size16[17]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[7] mux_2level_tapbuf_size16[17]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[8] mux_2level_tapbuf_size16[17]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[9] mux_2level_tapbuf_size16[17]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[10] mux_2level_tapbuf_size16[17]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[11] mux_2level_tapbuf_size16[17]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[12] mux_2level_tapbuf_size16[17]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[13] mux_2level_tapbuf_size16[17]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[14] mux_2level_tapbuf_size16[17]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[15] mux_2level_tapbuf_size16[17]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[17] gvdd_mux_2level_tapbuf_size16[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[0][1]_rrnode[30] when v(mux_2level_tapbuf_size16[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[0][1]_rrnode[30] when v(mux_2level_tapbuf_size16[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[0][1]_rrnode[30] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[17]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from=0 to='clock_period' -.meas tran leakage_cb_mux[0][1]_rrnode[30] param='mux_2level_tapbuf_size16[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[17]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[17]_energy_per_cycle param='mux_2level_tapbuf_size16[17]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[0][1]_rrnode[30] param='mux_2level_tapbuf_size16[17]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[0][1]_rrnode[30] param='dynamic_power_cb_mux[0][1]_rrnode[30]*clock_period' -.meas tran dynamic_rise_cb_mux[0][1]_rrnode[30] avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='start_rise_cb_mux[0][1]_rrnode[30]' to='start_rise_cb_mux[0][1]_rrnode[30]+switch_rise_cb_mux[0][1]_rrnode[30]' -.meas tran dynamic_fall_cb_mux[0][1]_rrnode[30] avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='start_fall_cb_mux[0][1]_rrnode[30]' to='start_fall_cb_mux[0][1]_rrnode[30]+switch_fall_cb_mux[0][1]_rrnode[30]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_cb_mux[0][1]_rrnode[30]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_cb_mux[0][1]_rrnode[30]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to17] -+ param='sum_leakage_power_cb_mux[0to16]+leakage_cb_mux[0][1]_rrnode[30]' -.meas tran sum_energy_per_cycle_cb_mux[0to17] -+ param='sum_energy_per_cycle_cb_mux[0to16]+energy_per_cycle_cb_mux[0][1]_rrnode[30]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='6*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to17]' -.meas tran total_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to17]' -.meas tran total_leakage_power_cb_mux -+ param='sum_leakage_power_cb_mux[0to17]' -.meas tran total_energy_per_cycle_cb_mux -+ param='sum_energy_per_cycle_cb_mux[0to17]' -.end diff --git a/examples/spice_test_example_2/cb_mux_tb/example_2_cby1_1_cbmux_testbench.sp b/examples/spice_test_example_2/cb_mux_tb/example_2_cby1_1_cbmux_testbench.sp deleted file mode 100644 index 4e702e177..000000000 --- a/examples/spice_test_example_2/cb_mux_tb/example_2_cby1_1_cbmux_testbench.sp +++ /dev/null @@ -1,2754 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_2level_tapbuf_size16[0] mux_2level_tapbuf_size16[0]->in[0] mux_2level_tapbuf_size16[0]->in[1] mux_2level_tapbuf_size16[0]->in[2] mux_2level_tapbuf_size16[0]->in[3] mux_2level_tapbuf_size16[0]->in[4] mux_2level_tapbuf_size16[0]->in[5] mux_2level_tapbuf_size16[0]->in[6] mux_2level_tapbuf_size16[0]->in[7] mux_2level_tapbuf_size16[0]->in[8] mux_2level_tapbuf_size16[0]->in[9] mux_2level_tapbuf_size16[0]->in[10] mux_2level_tapbuf_size16[0]->in[11] mux_2level_tapbuf_size16[0]->in[12] mux_2level_tapbuf_size16[0]->in[13] mux_2level_tapbuf_size16[0]->in[14] mux_2level_tapbuf_size16[0]->in[15] mux_2level_tapbuf_size16[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb sram[3]->out sram[3]->outb sram[4]->outb sram[4]->out sram[5]->out sram[5]->outb sram[6]->out sram[6]->outb sram[7]->out sram[7]->outb gvdd_mux_2level_tapbuf_size16[0] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_2level_tapbuf_size16[0]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[0] mux_2level_tapbuf_size16[0]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[1] mux_2level_tapbuf_size16[0]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[2] mux_2level_tapbuf_size16[0]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[3] mux_2level_tapbuf_size16[0]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[4] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[0]->in[4] mux_2level_tapbuf_size16[0]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[0]->in[5] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[0]->in[5] mux_2level_tapbuf_size16[0]->in[5] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[0]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[6] mux_2level_tapbuf_size16[0]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[7] mux_2level_tapbuf_size16[0]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[8] mux_2level_tapbuf_size16[0]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[9] mux_2level_tapbuf_size16[0]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[10] mux_2level_tapbuf_size16[0]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[11] mux_2level_tapbuf_size16[0]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[12] mux_2level_tapbuf_size16[0]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[13] mux_2level_tapbuf_size16[0]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[14] mux_2level_tapbuf_size16[0]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[0]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[0]->in[15] mux_2level_tapbuf_size16[0]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[0] gvdd_mux_2level_tapbuf_size16[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[175] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[175] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[175] when v(mux_2level_tapbuf_size16[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[175] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[175] when v(mux_2level_tapbuf_size16[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[175] trig v(mux_2level_tapbuf_size16[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[0]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[175] param='mux_2level_tapbuf_size16[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[0]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[0]_energy_per_cycle param='mux_2level_tapbuf_size16[0]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[175] param='mux_2level_tapbuf_size16[0]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[175] param='dynamic_power_cb_mux[1][1]_rrnode[175]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[175] avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='start_rise_cb_mux[1][1]_rrnode[175]' to='start_rise_cb_mux[1][1]_rrnode[175]+switch_rise_cb_mux[1][1]_rrnode[175]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[175] avg p(Vgvdd_mux_2level_tapbuf_size16[0]) from='start_fall_cb_mux[1][1]_rrnode[175]' to='start_fall_cb_mux[1][1]_rrnode[175]+switch_fall_cb_mux[1][1]_rrnode[175]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_cb_mux[1][1]_rrnode[175]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][1]_rrnode[175]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to0] -+ param='leakage_cb_mux[1][1]_rrnode[175]' -.meas tran sum_energy_per_cycle_cb_mux[0to0] -+ param='energy_per_cycle_cb_mux[1][1]_rrnode[175]' -Xmux_2level_tapbuf_size16[1] mux_2level_tapbuf_size16[1]->in[0] mux_2level_tapbuf_size16[1]->in[1] mux_2level_tapbuf_size16[1]->in[2] mux_2level_tapbuf_size16[1]->in[3] mux_2level_tapbuf_size16[1]->in[4] mux_2level_tapbuf_size16[1]->in[5] mux_2level_tapbuf_size16[1]->in[6] mux_2level_tapbuf_size16[1]->in[7] mux_2level_tapbuf_size16[1]->in[8] mux_2level_tapbuf_size16[1]->in[9] mux_2level_tapbuf_size16[1]->in[10] mux_2level_tapbuf_size16[1]->in[11] mux_2level_tapbuf_size16[1]->in[12] mux_2level_tapbuf_size16[1]->in[13] mux_2level_tapbuf_size16[1]->in[14] mux_2level_tapbuf_size16[1]->in[15] mux_2level_tapbuf_size16[1]->out sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->out sram[10]->outb sram[11]->out sram[11]->outb sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->out sram[14]->outb sram[15]->out sram[15]->outb gvdd_mux_2level_tapbuf_size16[1] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_2level_tapbuf_size16[1]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[0] mux_2level_tapbuf_size16[1]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[1] mux_2level_tapbuf_size16[1]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[2] mux_2level_tapbuf_size16[1]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[3] mux_2level_tapbuf_size16[1]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[4] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[1]->in[4] mux_2level_tapbuf_size16[1]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[1]->in[5] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[1]->in[5] mux_2level_tapbuf_size16[1]->in[5] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[1]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[6] mux_2level_tapbuf_size16[1]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[7] mux_2level_tapbuf_size16[1]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[8] mux_2level_tapbuf_size16[1]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[9] mux_2level_tapbuf_size16[1]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[10] mux_2level_tapbuf_size16[1]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[11] mux_2level_tapbuf_size16[1]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[12] mux_2level_tapbuf_size16[1]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[13] mux_2level_tapbuf_size16[1]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[14] mux_2level_tapbuf_size16[1]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[1]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[1]->in[15] mux_2level_tapbuf_size16[1]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[1] gvdd_mux_2level_tapbuf_size16[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[177] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[177] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[177] when v(mux_2level_tapbuf_size16[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[177] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[177] when v(mux_2level_tapbuf_size16[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[177] trig v(mux_2level_tapbuf_size16[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[1]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[177] param='mux_2level_tapbuf_size16[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[1]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[1]_energy_per_cycle param='mux_2level_tapbuf_size16[1]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[177] param='mux_2level_tapbuf_size16[1]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[177] param='dynamic_power_cb_mux[1][1]_rrnode[177]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[177] avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='start_rise_cb_mux[1][1]_rrnode[177]' to='start_rise_cb_mux[1][1]_rrnode[177]+switch_rise_cb_mux[1][1]_rrnode[177]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[177] avg p(Vgvdd_mux_2level_tapbuf_size16[1]) from='start_fall_cb_mux[1][1]_rrnode[177]' to='start_fall_cb_mux[1][1]_rrnode[177]+switch_fall_cb_mux[1][1]_rrnode[177]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_cb_mux[1][1]_rrnode[177]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[177]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to1] -+ param='sum_leakage_power_cb_mux[0to0]+leakage_cb_mux[1][1]_rrnode[177]' -.meas tran sum_energy_per_cycle_cb_mux[0to1] -+ param='sum_energy_per_cycle_cb_mux[0to0]+energy_per_cycle_cb_mux[1][1]_rrnode[177]' -Xmux_2level_tapbuf_size16[2] mux_2level_tapbuf_size16[2]->in[0] mux_2level_tapbuf_size16[2]->in[1] mux_2level_tapbuf_size16[2]->in[2] mux_2level_tapbuf_size16[2]->in[3] mux_2level_tapbuf_size16[2]->in[4] mux_2level_tapbuf_size16[2]->in[5] mux_2level_tapbuf_size16[2]->in[6] mux_2level_tapbuf_size16[2]->in[7] mux_2level_tapbuf_size16[2]->in[8] mux_2level_tapbuf_size16[2]->in[9] mux_2level_tapbuf_size16[2]->in[10] mux_2level_tapbuf_size16[2]->in[11] mux_2level_tapbuf_size16[2]->in[12] mux_2level_tapbuf_size16[2]->in[13] mux_2level_tapbuf_size16[2]->in[14] mux_2level_tapbuf_size16[2]->in[15] mux_2level_tapbuf_size16[2]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->out sram[18]->outb sram[19]->out sram[19]->outb sram[20]->outb sram[20]->out sram[21]->out sram[21]->outb sram[22]->out sram[22]->outb sram[23]->out sram[23]->outb gvdd_mux_2level_tapbuf_size16[2] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_2level_tapbuf_size16[2]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[0] mux_2level_tapbuf_size16[2]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[1] mux_2level_tapbuf_size16[2]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[2] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[2]->in[2] mux_2level_tapbuf_size16[2]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[2]->in[3] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[2]->in[3] mux_2level_tapbuf_size16[2]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[2]->in[4] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[2]->in[4] mux_2level_tapbuf_size16[2]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[2]->in[5] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[2]->in[5] mux_2level_tapbuf_size16[2]->in[5] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[2]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[6] mux_2level_tapbuf_size16[2]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[7] mux_2level_tapbuf_size16[2]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[8] mux_2level_tapbuf_size16[2]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[9] mux_2level_tapbuf_size16[2]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[10] mux_2level_tapbuf_size16[2]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[11] mux_2level_tapbuf_size16[2]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[12] mux_2level_tapbuf_size16[2]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[13] mux_2level_tapbuf_size16[2]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[14] mux_2level_tapbuf_size16[2]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[2]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[2]->in[15] mux_2level_tapbuf_size16[2]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[2] gvdd_mux_2level_tapbuf_size16[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[179] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[179] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[179] when v(mux_2level_tapbuf_size16[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[179] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[179] when v(mux_2level_tapbuf_size16[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[179] trig v(mux_2level_tapbuf_size16[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[2]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[179] param='mux_2level_tapbuf_size16[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[2]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[2]_energy_per_cycle param='mux_2level_tapbuf_size16[2]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[179] param='mux_2level_tapbuf_size16[2]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[179] param='dynamic_power_cb_mux[1][1]_rrnode[179]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[179] avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='start_rise_cb_mux[1][1]_rrnode[179]' to='start_rise_cb_mux[1][1]_rrnode[179]+switch_rise_cb_mux[1][1]_rrnode[179]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[179] avg p(Vgvdd_mux_2level_tapbuf_size16[2]) from='start_fall_cb_mux[1][1]_rrnode[179]' to='start_fall_cb_mux[1][1]_rrnode[179]+switch_fall_cb_mux[1][1]_rrnode[179]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_cb_mux[1][1]_rrnode[179]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[179]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to2] -+ param='sum_leakage_power_cb_mux[0to1]+leakage_cb_mux[1][1]_rrnode[179]' -.meas tran sum_energy_per_cycle_cb_mux[0to2] -+ param='sum_energy_per_cycle_cb_mux[0to1]+energy_per_cycle_cb_mux[1][1]_rrnode[179]' -Xmux_2level_tapbuf_size16[3] mux_2level_tapbuf_size16[3]->in[0] mux_2level_tapbuf_size16[3]->in[1] mux_2level_tapbuf_size16[3]->in[2] mux_2level_tapbuf_size16[3]->in[3] mux_2level_tapbuf_size16[3]->in[4] mux_2level_tapbuf_size16[3]->in[5] mux_2level_tapbuf_size16[3]->in[6] mux_2level_tapbuf_size16[3]->in[7] mux_2level_tapbuf_size16[3]->in[8] mux_2level_tapbuf_size16[3]->in[9] mux_2level_tapbuf_size16[3]->in[10] mux_2level_tapbuf_size16[3]->in[11] mux_2level_tapbuf_size16[3]->in[12] mux_2level_tapbuf_size16[3]->in[13] mux_2level_tapbuf_size16[3]->in[14] mux_2level_tapbuf_size16[3]->in[15] mux_2level_tapbuf_size16[3]->out sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->out sram[26]->outb sram[27]->out sram[27]->outb sram[28]->outb sram[28]->out sram[29]->out sram[29]->outb sram[30]->out sram[30]->outb sram[31]->out sram[31]->outb gvdd_mux_2level_tapbuf_size16[3] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_2level_tapbuf_size16[3]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[0] mux_2level_tapbuf_size16[3]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[1] mux_2level_tapbuf_size16[3]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[2] mux_2level_tapbuf_size16[3]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[3] mux_2level_tapbuf_size16[3]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[4] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[3]->in[4] mux_2level_tapbuf_size16[3]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[3]->in[5] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[3]->in[5] mux_2level_tapbuf_size16[3]->in[5] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[3]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[6] mux_2level_tapbuf_size16[3]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[7] mux_2level_tapbuf_size16[3]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[8] mux_2level_tapbuf_size16[3]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[9] mux_2level_tapbuf_size16[3]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[10] mux_2level_tapbuf_size16[3]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[11] mux_2level_tapbuf_size16[3]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[12] mux_2level_tapbuf_size16[3]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[13] mux_2level_tapbuf_size16[3]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[14] mux_2level_tapbuf_size16[3]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[3]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[3]->in[15] mux_2level_tapbuf_size16[3]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[3] gvdd_mux_2level_tapbuf_size16[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[181] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[181] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[181] when v(mux_2level_tapbuf_size16[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[181] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[181] when v(mux_2level_tapbuf_size16[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[181] trig v(mux_2level_tapbuf_size16[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[3]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[181] param='mux_2level_tapbuf_size16[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[3]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[3]_energy_per_cycle param='mux_2level_tapbuf_size16[3]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[181] param='mux_2level_tapbuf_size16[3]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[181] param='dynamic_power_cb_mux[1][1]_rrnode[181]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[181] avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='start_rise_cb_mux[1][1]_rrnode[181]' to='start_rise_cb_mux[1][1]_rrnode[181]+switch_rise_cb_mux[1][1]_rrnode[181]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[181] avg p(Vgvdd_mux_2level_tapbuf_size16[3]) from='start_fall_cb_mux[1][1]_rrnode[181]' to='start_fall_cb_mux[1][1]_rrnode[181]+switch_fall_cb_mux[1][1]_rrnode[181]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_cb_mux[1][1]_rrnode[181]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[181]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to3] -+ param='sum_leakage_power_cb_mux[0to2]+leakage_cb_mux[1][1]_rrnode[181]' -.meas tran sum_energy_per_cycle_cb_mux[0to3] -+ param='sum_energy_per_cycle_cb_mux[0to2]+energy_per_cycle_cb_mux[1][1]_rrnode[181]' -Xmux_2level_tapbuf_size16[4] mux_2level_tapbuf_size16[4]->in[0] mux_2level_tapbuf_size16[4]->in[1] mux_2level_tapbuf_size16[4]->in[2] mux_2level_tapbuf_size16[4]->in[3] mux_2level_tapbuf_size16[4]->in[4] mux_2level_tapbuf_size16[4]->in[5] mux_2level_tapbuf_size16[4]->in[6] mux_2level_tapbuf_size16[4]->in[7] mux_2level_tapbuf_size16[4]->in[8] mux_2level_tapbuf_size16[4]->in[9] mux_2level_tapbuf_size16[4]->in[10] mux_2level_tapbuf_size16[4]->in[11] mux_2level_tapbuf_size16[4]->in[12] mux_2level_tapbuf_size16[4]->in[13] mux_2level_tapbuf_size16[4]->in[14] mux_2level_tapbuf_size16[4]->in[15] mux_2level_tapbuf_size16[4]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->out sram[34]->outb sram[35]->out sram[35]->outb sram[36]->outb sram[36]->out sram[37]->out sram[37]->outb sram[38]->out sram[38]->outb sram[39]->out sram[39]->outb gvdd_mux_2level_tapbuf_size16[4] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -***** Signal mux_2level_tapbuf_size16[4]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[0] mux_2level_tapbuf_size16[4]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[1] mux_2level_tapbuf_size16[4]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[2] mux_2level_tapbuf_size16[4]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[3] mux_2level_tapbuf_size16[4]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[4] mux_2level_tapbuf_size16[4]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[5] mux_2level_tapbuf_size16[4]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[6] mux_2level_tapbuf_size16[4]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[7] mux_2level_tapbuf_size16[4]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[8] mux_2level_tapbuf_size16[4]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[9] mux_2level_tapbuf_size16[4]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[10] mux_2level_tapbuf_size16[4]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[11] mux_2level_tapbuf_size16[4]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[12] mux_2level_tapbuf_size16[4]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[13] mux_2level_tapbuf_size16[4]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[14] mux_2level_tapbuf_size16[4]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[4]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[4]->in[15] mux_2level_tapbuf_size16[4]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[4] gvdd_mux_2level_tapbuf_size16[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[183] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[183] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[183] when v(mux_2level_tapbuf_size16[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[183] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[183] when v(mux_2level_tapbuf_size16[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[183] trig v(mux_2level_tapbuf_size16[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[4]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[183] param='mux_2level_tapbuf_size16[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[4]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[4]_energy_per_cycle param='mux_2level_tapbuf_size16[4]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[183] param='mux_2level_tapbuf_size16[4]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[183] param='dynamic_power_cb_mux[1][1]_rrnode[183]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[183] avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='start_rise_cb_mux[1][1]_rrnode[183]' to='start_rise_cb_mux[1][1]_rrnode[183]+switch_rise_cb_mux[1][1]_rrnode[183]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[183] avg p(Vgvdd_mux_2level_tapbuf_size16[4]) from='start_fall_cb_mux[1][1]_rrnode[183]' to='start_fall_cb_mux[1][1]_rrnode[183]+switch_fall_cb_mux[1][1]_rrnode[183]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_cb_mux[1][1]_rrnode[183]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[183]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to4] -+ param='sum_leakage_power_cb_mux[0to3]+leakage_cb_mux[1][1]_rrnode[183]' -.meas tran sum_energy_per_cycle_cb_mux[0to4] -+ param='sum_energy_per_cycle_cb_mux[0to3]+energy_per_cycle_cb_mux[1][1]_rrnode[183]' -Xmux_2level_tapbuf_size16[5] mux_2level_tapbuf_size16[5]->in[0] mux_2level_tapbuf_size16[5]->in[1] mux_2level_tapbuf_size16[5]->in[2] mux_2level_tapbuf_size16[5]->in[3] mux_2level_tapbuf_size16[5]->in[4] mux_2level_tapbuf_size16[5]->in[5] mux_2level_tapbuf_size16[5]->in[6] mux_2level_tapbuf_size16[5]->in[7] mux_2level_tapbuf_size16[5]->in[8] mux_2level_tapbuf_size16[5]->in[9] mux_2level_tapbuf_size16[5]->in[10] mux_2level_tapbuf_size16[5]->in[11] mux_2level_tapbuf_size16[5]->in[12] mux_2level_tapbuf_size16[5]->in[13] mux_2level_tapbuf_size16[5]->in[14] mux_2level_tapbuf_size16[5]->in[15] mux_2level_tapbuf_size16[5]->out sram[40]->outb sram[40]->out sram[41]->out sram[41]->outb sram[42]->out sram[42]->outb sram[43]->out sram[43]->outb sram[44]->outb sram[44]->out sram[45]->out sram[45]->outb sram[46]->out sram[46]->outb sram[47]->out sram[47]->outb gvdd_mux_2level_tapbuf_size16[5] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[5], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -***** Signal mux_2level_tapbuf_size16[5]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[0] mux_2level_tapbuf_size16[5]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[1] mux_2level_tapbuf_size16[5]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[2] mux_2level_tapbuf_size16[5]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[3] mux_2level_tapbuf_size16[5]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[4] mux_2level_tapbuf_size16[5]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[5] mux_2level_tapbuf_size16[5]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[6] mux_2level_tapbuf_size16[5]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[7] mux_2level_tapbuf_size16[5]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[8] mux_2level_tapbuf_size16[5]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[9] mux_2level_tapbuf_size16[5]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[10] mux_2level_tapbuf_size16[5]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[11] mux_2level_tapbuf_size16[5]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[12] mux_2level_tapbuf_size16[5]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[13] mux_2level_tapbuf_size16[5]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[14] mux_2level_tapbuf_size16[5]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[5]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[5]->in[15] mux_2level_tapbuf_size16[5]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[5] gvdd_mux_2level_tapbuf_size16[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[185] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[185] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[185] when v(mux_2level_tapbuf_size16[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[185] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[185] when v(mux_2level_tapbuf_size16[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[185] trig v(mux_2level_tapbuf_size16[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[5]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[185] param='mux_2level_tapbuf_size16[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[5]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[5]_energy_per_cycle param='mux_2level_tapbuf_size16[5]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[185] param='mux_2level_tapbuf_size16[5]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[185] param='dynamic_power_cb_mux[1][1]_rrnode[185]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[185] avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='start_rise_cb_mux[1][1]_rrnode[185]' to='start_rise_cb_mux[1][1]_rrnode[185]+switch_rise_cb_mux[1][1]_rrnode[185]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[185] avg p(Vgvdd_mux_2level_tapbuf_size16[5]) from='start_fall_cb_mux[1][1]_rrnode[185]' to='start_fall_cb_mux[1][1]_rrnode[185]+switch_fall_cb_mux[1][1]_rrnode[185]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_cb_mux[1][1]_rrnode[185]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[185]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to5] -+ param='sum_leakage_power_cb_mux[0to4]+leakage_cb_mux[1][1]_rrnode[185]' -.meas tran sum_energy_per_cycle_cb_mux[0to5] -+ param='sum_energy_per_cycle_cb_mux[0to4]+energy_per_cycle_cb_mux[1][1]_rrnode[185]' -Xmux_2level_tapbuf_size16[6] mux_2level_tapbuf_size16[6]->in[0] mux_2level_tapbuf_size16[6]->in[1] mux_2level_tapbuf_size16[6]->in[2] mux_2level_tapbuf_size16[6]->in[3] mux_2level_tapbuf_size16[6]->in[4] mux_2level_tapbuf_size16[6]->in[5] mux_2level_tapbuf_size16[6]->in[6] mux_2level_tapbuf_size16[6]->in[7] mux_2level_tapbuf_size16[6]->in[8] mux_2level_tapbuf_size16[6]->in[9] mux_2level_tapbuf_size16[6]->in[10] mux_2level_tapbuf_size16[6]->in[11] mux_2level_tapbuf_size16[6]->in[12] mux_2level_tapbuf_size16[6]->in[13] mux_2level_tapbuf_size16[6]->in[14] mux_2level_tapbuf_size16[6]->in[15] mux_2level_tapbuf_size16[6]->out sram[48]->outb sram[48]->out sram[49]->out sram[49]->outb sram[50]->out sram[50]->outb sram[51]->out sram[51]->outb sram[52]->outb sram[52]->out sram[53]->out sram[53]->outb sram[54]->out sram[54]->outb sram[55]->out sram[55]->outb gvdd_mux_2level_tapbuf_size16[6] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -***** Signal mux_2level_tapbuf_size16[6]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[0] mux_2level_tapbuf_size16[6]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[1] mux_2level_tapbuf_size16[6]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[2] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[6]->in[2] mux_2level_tapbuf_size16[6]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[6]->in[3] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[6]->in[3] mux_2level_tapbuf_size16[6]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[6]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[4] mux_2level_tapbuf_size16[6]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[5] mux_2level_tapbuf_size16[6]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[6] mux_2level_tapbuf_size16[6]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[7] mux_2level_tapbuf_size16[6]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[8] mux_2level_tapbuf_size16[6]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[9] mux_2level_tapbuf_size16[6]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[10] mux_2level_tapbuf_size16[6]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[11] mux_2level_tapbuf_size16[6]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[12] mux_2level_tapbuf_size16[6]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[13] mux_2level_tapbuf_size16[6]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[14] mux_2level_tapbuf_size16[6]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[6]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[6]->in[15] mux_2level_tapbuf_size16[6]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[6] gvdd_mux_2level_tapbuf_size16[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[187] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[187] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[187] when v(mux_2level_tapbuf_size16[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[187] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[187] when v(mux_2level_tapbuf_size16[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[187] trig v(mux_2level_tapbuf_size16[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[6]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[187] param='mux_2level_tapbuf_size16[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[6]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[6]_energy_per_cycle param='mux_2level_tapbuf_size16[6]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[187] param='mux_2level_tapbuf_size16[6]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[187] param='dynamic_power_cb_mux[1][1]_rrnode[187]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[187] avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='start_rise_cb_mux[1][1]_rrnode[187]' to='start_rise_cb_mux[1][1]_rrnode[187]+switch_rise_cb_mux[1][1]_rrnode[187]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[187] avg p(Vgvdd_mux_2level_tapbuf_size16[6]) from='start_fall_cb_mux[1][1]_rrnode[187]' to='start_fall_cb_mux[1][1]_rrnode[187]+switch_fall_cb_mux[1][1]_rrnode[187]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_cb_mux[1][1]_rrnode[187]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[187]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to6] -+ param='sum_leakage_power_cb_mux[0to5]+leakage_cb_mux[1][1]_rrnode[187]' -.meas tran sum_energy_per_cycle_cb_mux[0to6] -+ param='sum_energy_per_cycle_cb_mux[0to5]+energy_per_cycle_cb_mux[1][1]_rrnode[187]' -Xmux_2level_tapbuf_size16[7] mux_2level_tapbuf_size16[7]->in[0] mux_2level_tapbuf_size16[7]->in[1] mux_2level_tapbuf_size16[7]->in[2] mux_2level_tapbuf_size16[7]->in[3] mux_2level_tapbuf_size16[7]->in[4] mux_2level_tapbuf_size16[7]->in[5] mux_2level_tapbuf_size16[7]->in[6] mux_2level_tapbuf_size16[7]->in[7] mux_2level_tapbuf_size16[7]->in[8] mux_2level_tapbuf_size16[7]->in[9] mux_2level_tapbuf_size16[7]->in[10] mux_2level_tapbuf_size16[7]->in[11] mux_2level_tapbuf_size16[7]->in[12] mux_2level_tapbuf_size16[7]->in[13] mux_2level_tapbuf_size16[7]->in[14] mux_2level_tapbuf_size16[7]->in[15] mux_2level_tapbuf_size16[7]->out sram[56]->outb sram[56]->out sram[57]->out sram[57]->outb sram[58]->out sram[58]->outb sram[59]->out sram[59]->outb sram[60]->outb sram[60]->out sram[61]->out sram[61]->outb sram[62]->out sram[62]->outb sram[63]->out sram[63]->outb gvdd_mux_2level_tapbuf_size16[7] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -***** Signal mux_2level_tapbuf_size16[7]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[0] mux_2level_tapbuf_size16[7]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[1] mux_2level_tapbuf_size16[7]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[2] mux_2level_tapbuf_size16[7]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[3] mux_2level_tapbuf_size16[7]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[4] mux_2level_tapbuf_size16[7]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[5] mux_2level_tapbuf_size16[7]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[6] mux_2level_tapbuf_size16[7]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[7] mux_2level_tapbuf_size16[7]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[8] mux_2level_tapbuf_size16[7]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[9] mux_2level_tapbuf_size16[7]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[10] mux_2level_tapbuf_size16[7]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[11] mux_2level_tapbuf_size16[7]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[12] mux_2level_tapbuf_size16[7]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[13] mux_2level_tapbuf_size16[7]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[14] mux_2level_tapbuf_size16[7]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[7]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[7]->in[15] mux_2level_tapbuf_size16[7]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[7] gvdd_mux_2level_tapbuf_size16[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[189] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[189] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[189] when v(mux_2level_tapbuf_size16[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[189] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[189] when v(mux_2level_tapbuf_size16[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[189] trig v(mux_2level_tapbuf_size16[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[7]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[189] param='mux_2level_tapbuf_size16[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[7]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[7]_energy_per_cycle param='mux_2level_tapbuf_size16[7]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[189] param='mux_2level_tapbuf_size16[7]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[189] param='dynamic_power_cb_mux[1][1]_rrnode[189]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[189] avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='start_rise_cb_mux[1][1]_rrnode[189]' to='start_rise_cb_mux[1][1]_rrnode[189]+switch_rise_cb_mux[1][1]_rrnode[189]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[189] avg p(Vgvdd_mux_2level_tapbuf_size16[7]) from='start_fall_cb_mux[1][1]_rrnode[189]' to='start_fall_cb_mux[1][1]_rrnode[189]+switch_fall_cb_mux[1][1]_rrnode[189]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_cb_mux[1][1]_rrnode[189]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[189]' -******* IO_TYPE loads ******* -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to7] -+ param='sum_leakage_power_cb_mux[0to6]+leakage_cb_mux[1][1]_rrnode[189]' -.meas tran sum_energy_per_cycle_cb_mux[0to7] -+ param='sum_energy_per_cycle_cb_mux[0to6]+energy_per_cycle_cb_mux[1][1]_rrnode[189]' -Xmux_2level_tapbuf_size16[8] mux_2level_tapbuf_size16[8]->in[0] mux_2level_tapbuf_size16[8]->in[1] mux_2level_tapbuf_size16[8]->in[2] mux_2level_tapbuf_size16[8]->in[3] mux_2level_tapbuf_size16[8]->in[4] mux_2level_tapbuf_size16[8]->in[5] mux_2level_tapbuf_size16[8]->in[6] mux_2level_tapbuf_size16[8]->in[7] mux_2level_tapbuf_size16[8]->in[8] mux_2level_tapbuf_size16[8]->in[9] mux_2level_tapbuf_size16[8]->in[10] mux_2level_tapbuf_size16[8]->in[11] mux_2level_tapbuf_size16[8]->in[12] mux_2level_tapbuf_size16[8]->in[13] mux_2level_tapbuf_size16[8]->in[14] mux_2level_tapbuf_size16[8]->in[15] mux_2level_tapbuf_size16[8]->out sram[64]->outb sram[64]->out sram[65]->out sram[65]->outb sram[66]->out sram[66]->outb sram[67]->out sram[67]->outb sram[68]->outb sram[68]->out sram[69]->out sram[69]->outb sram[70]->out sram[70]->outb sram[71]->out sram[71]->outb gvdd_mux_2level_tapbuf_size16[8] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -***** Signal mux_2level_tapbuf_size16[8]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[0] mux_2level_tapbuf_size16[8]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[1] mux_2level_tapbuf_size16[8]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[2] mux_2level_tapbuf_size16[8]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[3] mux_2level_tapbuf_size16[8]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[4] mux_2level_tapbuf_size16[8]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[5] mux_2level_tapbuf_size16[8]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[6] mux_2level_tapbuf_size16[8]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[7] mux_2level_tapbuf_size16[8]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[8] mux_2level_tapbuf_size16[8]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[9] mux_2level_tapbuf_size16[8]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[10] mux_2level_tapbuf_size16[8]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[11] mux_2level_tapbuf_size16[8]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[12] mux_2level_tapbuf_size16[8]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[13] mux_2level_tapbuf_size16[8]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[14] mux_2level_tapbuf_size16[8]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[8]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[8]->in[15] mux_2level_tapbuf_size16[8]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[8] gvdd_mux_2level_tapbuf_size16[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[77] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[77] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[77] when v(mux_2level_tapbuf_size16[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[77] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[77] when v(mux_2level_tapbuf_size16[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[77] trig v(mux_2level_tapbuf_size16[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[8]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[77] param='mux_2level_tapbuf_size16[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[8]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[8]_energy_per_cycle param='mux_2level_tapbuf_size16[8]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[77] param='mux_2level_tapbuf_size16[8]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[77] param='dynamic_power_cb_mux[1][1]_rrnode[77]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[77] avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='start_rise_cb_mux[1][1]_rrnode[77]' to='start_rise_cb_mux[1][1]_rrnode[77]+switch_rise_cb_mux[1][1]_rrnode[77]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[77] avg p(Vgvdd_mux_2level_tapbuf_size16[8]) from='start_fall_cb_mux[1][1]_rrnode[77]' to='start_fall_cb_mux[1][1]_rrnode[77]+switch_fall_cb_mux[1][1]_rrnode[77]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_cb_mux[1][1]_rrnode[77]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[77]' -******* Normal TYPE loads ******* -Xload_inv[0]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[31]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 mux_2level_tapbuf_size16[8]->out mux_2level_tapbuf_size16[8]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to8] -+ param='sum_leakage_power_cb_mux[0to7]+leakage_cb_mux[1][1]_rrnode[77]' -.meas tran sum_energy_per_cycle_cb_mux[0to8] -+ param='sum_energy_per_cycle_cb_mux[0to7]+energy_per_cycle_cb_mux[1][1]_rrnode[77]' -Xmux_2level_tapbuf_size16[9] mux_2level_tapbuf_size16[9]->in[0] mux_2level_tapbuf_size16[9]->in[1] mux_2level_tapbuf_size16[9]->in[2] mux_2level_tapbuf_size16[9]->in[3] mux_2level_tapbuf_size16[9]->in[4] mux_2level_tapbuf_size16[9]->in[5] mux_2level_tapbuf_size16[9]->in[6] mux_2level_tapbuf_size16[9]->in[7] mux_2level_tapbuf_size16[9]->in[8] mux_2level_tapbuf_size16[9]->in[9] mux_2level_tapbuf_size16[9]->in[10] mux_2level_tapbuf_size16[9]->in[11] mux_2level_tapbuf_size16[9]->in[12] mux_2level_tapbuf_size16[9]->in[13] mux_2level_tapbuf_size16[9]->in[14] mux_2level_tapbuf_size16[9]->in[15] mux_2level_tapbuf_size16[9]->out sram[72]->outb sram[72]->out sram[73]->out sram[73]->outb sram[74]->out sram[74]->outb sram[75]->out sram[75]->outb sram[76]->outb sram[76]->out sram[77]->out sram[77]->outb sram[78]->out sram[78]->outb sram[79]->out sram[79]->outb gvdd_mux_2level_tapbuf_size16[9] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[9], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -***** Signal mux_2level_tapbuf_size16[9]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[0] mux_2level_tapbuf_size16[9]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[1] mux_2level_tapbuf_size16[9]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[2] mux_2level_tapbuf_size16[9]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[3] mux_2level_tapbuf_size16[9]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[4] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[9]->in[4] mux_2level_tapbuf_size16[9]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[9]->in[5] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[9]->in[5] mux_2level_tapbuf_size16[9]->in[5] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[9]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[6] mux_2level_tapbuf_size16[9]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[7] mux_2level_tapbuf_size16[9]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[8] mux_2level_tapbuf_size16[9]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[9] mux_2level_tapbuf_size16[9]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[10] mux_2level_tapbuf_size16[9]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[11] mux_2level_tapbuf_size16[9]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[12] mux_2level_tapbuf_size16[9]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[13] mux_2level_tapbuf_size16[9]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[14] mux_2level_tapbuf_size16[9]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[9]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[9]->in[15] mux_2level_tapbuf_size16[9]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[9] gvdd_mux_2level_tapbuf_size16[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[81] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[81] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[81] when v(mux_2level_tapbuf_size16[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[81] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[81] when v(mux_2level_tapbuf_size16[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[81] trig v(mux_2level_tapbuf_size16[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[9]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[81] param='mux_2level_tapbuf_size16[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[9]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[9]_energy_per_cycle param='mux_2level_tapbuf_size16[9]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[81] param='mux_2level_tapbuf_size16[9]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[81] param='dynamic_power_cb_mux[1][1]_rrnode[81]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[81] avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='start_rise_cb_mux[1][1]_rrnode[81]' to='start_rise_cb_mux[1][1]_rrnode[81]+switch_rise_cb_mux[1][1]_rrnode[81]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[81] avg p(Vgvdd_mux_2level_tapbuf_size16[9]) from='start_fall_cb_mux[1][1]_rrnode[81]' to='start_fall_cb_mux[1][1]_rrnode[81]+switch_fall_cb_mux[1][1]_rrnode[81]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_cb_mux[1][1]_rrnode[81]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_cb_mux[1][1]_rrnode[81]' -******* Normal TYPE loads ******* -Xload_inv[60]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[78]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[109]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[112]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 mux_2level_tapbuf_size16[9]->out mux_2level_tapbuf_size16[9]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to9] -+ param='sum_leakage_power_cb_mux[0to8]+leakage_cb_mux[1][1]_rrnode[81]' -.meas tran sum_energy_per_cycle_cb_mux[0to9] -+ param='sum_energy_per_cycle_cb_mux[0to8]+energy_per_cycle_cb_mux[1][1]_rrnode[81]' -Xmux_2level_tapbuf_size16[10] mux_2level_tapbuf_size16[10]->in[0] mux_2level_tapbuf_size16[10]->in[1] mux_2level_tapbuf_size16[10]->in[2] mux_2level_tapbuf_size16[10]->in[3] mux_2level_tapbuf_size16[10]->in[4] mux_2level_tapbuf_size16[10]->in[5] mux_2level_tapbuf_size16[10]->in[6] mux_2level_tapbuf_size16[10]->in[7] mux_2level_tapbuf_size16[10]->in[8] mux_2level_tapbuf_size16[10]->in[9] mux_2level_tapbuf_size16[10]->in[10] mux_2level_tapbuf_size16[10]->in[11] mux_2level_tapbuf_size16[10]->in[12] mux_2level_tapbuf_size16[10]->in[13] mux_2level_tapbuf_size16[10]->in[14] mux_2level_tapbuf_size16[10]->in[15] mux_2level_tapbuf_size16[10]->out sram[80]->outb sram[80]->out sram[81]->out sram[81]->outb sram[82]->out sram[82]->outb sram[83]->out sram[83]->outb sram[84]->outb sram[84]->out sram[85]->out sram[85]->outb sram[86]->out sram[86]->outb sram[87]->out sram[87]->outb gvdd_mux_2level_tapbuf_size16[10] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[10], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -***** Signal mux_2level_tapbuf_size16[10]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[0] mux_2level_tapbuf_size16[10]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[1] mux_2level_tapbuf_size16[10]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[2] mux_2level_tapbuf_size16[10]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[3] mux_2level_tapbuf_size16[10]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[4] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[10]->in[4] mux_2level_tapbuf_size16[10]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[10]->in[5] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[10]->in[5] mux_2level_tapbuf_size16[10]->in[5] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[10]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[6] mux_2level_tapbuf_size16[10]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[7] mux_2level_tapbuf_size16[10]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[8] mux_2level_tapbuf_size16[10]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[9] mux_2level_tapbuf_size16[10]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[10] mux_2level_tapbuf_size16[10]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[11] mux_2level_tapbuf_size16[10]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[12] mux_2level_tapbuf_size16[10]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[13] mux_2level_tapbuf_size16[10]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[14] mux_2level_tapbuf_size16[10]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[10]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[10]->in[15] mux_2level_tapbuf_size16[10]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[10] gvdd_mux_2level_tapbuf_size16[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[85] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[85] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[85] when v(mux_2level_tapbuf_size16[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[85] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[85] when v(mux_2level_tapbuf_size16[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[85] trig v(mux_2level_tapbuf_size16[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[10]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[85] param='mux_2level_tapbuf_size16[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[10]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[10]_energy_per_cycle param='mux_2level_tapbuf_size16[10]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[85] param='mux_2level_tapbuf_size16[10]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[85] param='dynamic_power_cb_mux[1][1]_rrnode[85]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[85] avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='start_rise_cb_mux[1][1]_rrnode[85]' to='start_rise_cb_mux[1][1]_rrnode[85]+switch_rise_cb_mux[1][1]_rrnode[85]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[85] avg p(Vgvdd_mux_2level_tapbuf_size16[10]) from='start_fall_cb_mux[1][1]_rrnode[85]' to='start_fall_cb_mux[1][1]_rrnode[85]+switch_fall_cb_mux[1][1]_rrnode[85]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_cb_mux[1][1]_rrnode[85]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_cb_mux[1][1]_rrnode[85]' -******* Normal TYPE loads ******* -Xload_inv[120]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[125]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[128]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[130]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 mux_2level_tapbuf_size16[10]->out mux_2level_tapbuf_size16[10]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to10] -+ param='sum_leakage_power_cb_mux[0to9]+leakage_cb_mux[1][1]_rrnode[85]' -.meas tran sum_energy_per_cycle_cb_mux[0to10] -+ param='sum_energy_per_cycle_cb_mux[0to9]+energy_per_cycle_cb_mux[1][1]_rrnode[85]' -Xmux_2level_tapbuf_size16[11] mux_2level_tapbuf_size16[11]->in[0] mux_2level_tapbuf_size16[11]->in[1] mux_2level_tapbuf_size16[11]->in[2] mux_2level_tapbuf_size16[11]->in[3] mux_2level_tapbuf_size16[11]->in[4] mux_2level_tapbuf_size16[11]->in[5] mux_2level_tapbuf_size16[11]->in[6] mux_2level_tapbuf_size16[11]->in[7] mux_2level_tapbuf_size16[11]->in[8] mux_2level_tapbuf_size16[11]->in[9] mux_2level_tapbuf_size16[11]->in[10] mux_2level_tapbuf_size16[11]->in[11] mux_2level_tapbuf_size16[11]->in[12] mux_2level_tapbuf_size16[11]->in[13] mux_2level_tapbuf_size16[11]->in[14] mux_2level_tapbuf_size16[11]->in[15] mux_2level_tapbuf_size16[11]->out sram[88]->outb sram[88]->out sram[89]->out sram[89]->outb sram[90]->out sram[90]->outb sram[91]->out sram[91]->outb sram[92]->outb sram[92]->out sram[93]->out sram[93]->outb sram[94]->out sram[94]->outb sram[95]->out sram[95]->outb gvdd_mux_2level_tapbuf_size16[11] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[11], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -***** Signal mux_2level_tapbuf_size16[11]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[0] mux_2level_tapbuf_size16[11]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[1] mux_2level_tapbuf_size16[11]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[2] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[11]->in[2] mux_2level_tapbuf_size16[11]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[11]->in[3] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[11]->in[3] mux_2level_tapbuf_size16[11]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[11]->in[4] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[11]->in[4] mux_2level_tapbuf_size16[11]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[11]->in[5] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[11]->in[5] mux_2level_tapbuf_size16[11]->in[5] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[11]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[6] mux_2level_tapbuf_size16[11]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[7] mux_2level_tapbuf_size16[11]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[8] mux_2level_tapbuf_size16[11]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[9] mux_2level_tapbuf_size16[11]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[10] mux_2level_tapbuf_size16[11]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[11] mux_2level_tapbuf_size16[11]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[12] mux_2level_tapbuf_size16[11]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[13] mux_2level_tapbuf_size16[11]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[14] mux_2level_tapbuf_size16[11]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[11]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[11]->in[15] mux_2level_tapbuf_size16[11]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[11] gvdd_mux_2level_tapbuf_size16[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[89] when v(mux_2level_tapbuf_size16[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[89] when v(mux_2level_tapbuf_size16[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[89] trig v(mux_2level_tapbuf_size16[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[11]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[89] param='mux_2level_tapbuf_size16[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[11]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[11]_energy_per_cycle param='mux_2level_tapbuf_size16[11]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[89] param='mux_2level_tapbuf_size16[11]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[89] param='dynamic_power_cb_mux[1][1]_rrnode[89]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[89] avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='start_rise_cb_mux[1][1]_rrnode[89]' to='start_rise_cb_mux[1][1]_rrnode[89]+switch_rise_cb_mux[1][1]_rrnode[89]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[89] avg p(Vgvdd_mux_2level_tapbuf_size16[11]) from='start_fall_cb_mux[1][1]_rrnode[89]' to='start_fall_cb_mux[1][1]_rrnode[89]+switch_fall_cb_mux[1][1]_rrnode[89]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_cb_mux[1][1]_rrnode[89]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_cb_mux[1][1]_rrnode[89]' -******* Normal TYPE loads ******* -Xload_inv[180]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 mux_2level_tapbuf_size16[11]->out mux_2level_tapbuf_size16[11]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to11] -+ param='sum_leakage_power_cb_mux[0to10]+leakage_cb_mux[1][1]_rrnode[89]' -.meas tran sum_energy_per_cycle_cb_mux[0to11] -+ param='sum_energy_per_cycle_cb_mux[0to10]+energy_per_cycle_cb_mux[1][1]_rrnode[89]' -Xmux_2level_tapbuf_size16[12] mux_2level_tapbuf_size16[12]->in[0] mux_2level_tapbuf_size16[12]->in[1] mux_2level_tapbuf_size16[12]->in[2] mux_2level_tapbuf_size16[12]->in[3] mux_2level_tapbuf_size16[12]->in[4] mux_2level_tapbuf_size16[12]->in[5] mux_2level_tapbuf_size16[12]->in[6] mux_2level_tapbuf_size16[12]->in[7] mux_2level_tapbuf_size16[12]->in[8] mux_2level_tapbuf_size16[12]->in[9] mux_2level_tapbuf_size16[12]->in[10] mux_2level_tapbuf_size16[12]->in[11] mux_2level_tapbuf_size16[12]->in[12] mux_2level_tapbuf_size16[12]->in[13] mux_2level_tapbuf_size16[12]->in[14] mux_2level_tapbuf_size16[12]->in[15] mux_2level_tapbuf_size16[12]->out sram[96]->outb sram[96]->out sram[97]->out sram[97]->outb sram[98]->out sram[98]->outb sram[99]->out sram[99]->outb sram[100]->outb sram[100]->out sram[101]->out sram[101]->outb sram[102]->out sram[102]->outb sram[103]->out sram[103]->outb gvdd_mux_2level_tapbuf_size16[12] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[12], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[100]->out) 0 -.nodeset V(sram[100]->outb) vsp -Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[101]->out) 0 -.nodeset V(sram[101]->outb) vsp -Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[102]->out) 0 -.nodeset V(sram[102]->outb) vsp -Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[103]->out) 0 -.nodeset V(sram[103]->outb) vsp -***** Signal mux_2level_tapbuf_size16[12]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[0] mux_2level_tapbuf_size16[12]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[1] mux_2level_tapbuf_size16[12]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[2] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[12]->in[2] mux_2level_tapbuf_size16[12]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[12]->in[3] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[12]->in[3] mux_2level_tapbuf_size16[12]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[12]->in[4] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[12]->in[4] mux_2level_tapbuf_size16[12]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[12]->in[5] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[12]->in[5] mux_2level_tapbuf_size16[12]->in[5] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[12]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[6] mux_2level_tapbuf_size16[12]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[7] mux_2level_tapbuf_size16[12]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[8] mux_2level_tapbuf_size16[12]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[9] mux_2level_tapbuf_size16[12]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[10] mux_2level_tapbuf_size16[12]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[11] mux_2level_tapbuf_size16[12]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[12] mux_2level_tapbuf_size16[12]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[13] mux_2level_tapbuf_size16[12]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[14] mux_2level_tapbuf_size16[12]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[12]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[12]->in[15] mux_2level_tapbuf_size16[12]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[12] gvdd_mux_2level_tapbuf_size16[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[93] when v(mux_2level_tapbuf_size16[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[93] when v(mux_2level_tapbuf_size16[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[93] trig v(mux_2level_tapbuf_size16[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[12]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[93] param='mux_2level_tapbuf_size16[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[12]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[12]_energy_per_cycle param='mux_2level_tapbuf_size16[12]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[93] param='mux_2level_tapbuf_size16[12]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[93] param='dynamic_power_cb_mux[1][1]_rrnode[93]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[93] avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='start_rise_cb_mux[1][1]_rrnode[93]' to='start_rise_cb_mux[1][1]_rrnode[93]+switch_rise_cb_mux[1][1]_rrnode[93]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[93] avg p(Vgvdd_mux_2level_tapbuf_size16[12]) from='start_fall_cb_mux[1][1]_rrnode[93]' to='start_fall_cb_mux[1][1]_rrnode[93]+switch_fall_cb_mux[1][1]_rrnode[93]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_cb_mux[1][1]_rrnode[93]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_cb_mux[1][1]_rrnode[93]' -******* Normal TYPE loads ******* -Xload_inv[240]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 mux_2level_tapbuf_size16[12]->out mux_2level_tapbuf_size16[12]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to12] -+ param='sum_leakage_power_cb_mux[0to11]+leakage_cb_mux[1][1]_rrnode[93]' -.meas tran sum_energy_per_cycle_cb_mux[0to12] -+ param='sum_energy_per_cycle_cb_mux[0to11]+energy_per_cycle_cb_mux[1][1]_rrnode[93]' -Xmux_2level_tapbuf_size16[13] mux_2level_tapbuf_size16[13]->in[0] mux_2level_tapbuf_size16[13]->in[1] mux_2level_tapbuf_size16[13]->in[2] mux_2level_tapbuf_size16[13]->in[3] mux_2level_tapbuf_size16[13]->in[4] mux_2level_tapbuf_size16[13]->in[5] mux_2level_tapbuf_size16[13]->in[6] mux_2level_tapbuf_size16[13]->in[7] mux_2level_tapbuf_size16[13]->in[8] mux_2level_tapbuf_size16[13]->in[9] mux_2level_tapbuf_size16[13]->in[10] mux_2level_tapbuf_size16[13]->in[11] mux_2level_tapbuf_size16[13]->in[12] mux_2level_tapbuf_size16[13]->in[13] mux_2level_tapbuf_size16[13]->in[14] mux_2level_tapbuf_size16[13]->in[15] mux_2level_tapbuf_size16[13]->out sram[104]->outb sram[104]->out sram[105]->out sram[105]->outb sram[106]->out sram[106]->outb sram[107]->out sram[107]->outb sram[108]->outb sram[108]->out sram[109]->out sram[109]->outb sram[110]->out sram[110]->outb sram[111]->out sram[111]->outb gvdd_mux_2level_tapbuf_size16[13] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[13], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[104]->out) 0 -.nodeset V(sram[104]->outb) vsp -Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[105]->out) 0 -.nodeset V(sram[105]->outb) vsp -Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[106]->out) 0 -.nodeset V(sram[106]->outb) vsp -Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[107]->out) 0 -.nodeset V(sram[107]->outb) vsp -Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[108]->out) 0 -.nodeset V(sram[108]->outb) vsp -Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[109]->out) 0 -.nodeset V(sram[109]->outb) vsp -Xsram[110] sram->in sram[110]->out sram[110]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[110]->out) 0 -.nodeset V(sram[110]->outb) vsp -Xsram[111] sram->in sram[111]->out sram[111]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[111]->out) 0 -.nodeset V(sram[111]->outb) vsp -***** Signal mux_2level_tapbuf_size16[13]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[0] mux_2level_tapbuf_size16[13]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[1] mux_2level_tapbuf_size16[13]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[2] mux_2level_tapbuf_size16[13]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[3] mux_2level_tapbuf_size16[13]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[4] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[13]->in[4] mux_2level_tapbuf_size16[13]->in[4] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[13]->in[5] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[13]->in[5] mux_2level_tapbuf_size16[13]->in[5] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[13]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[6] mux_2level_tapbuf_size16[13]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[7] mux_2level_tapbuf_size16[13]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[8] mux_2level_tapbuf_size16[13]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[9] mux_2level_tapbuf_size16[13]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[10] mux_2level_tapbuf_size16[13]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[11] mux_2level_tapbuf_size16[13]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[12] mux_2level_tapbuf_size16[13]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[13] mux_2level_tapbuf_size16[13]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[14] mux_2level_tapbuf_size16[13]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[13]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[13]->in[15] mux_2level_tapbuf_size16[13]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[13] gvdd_mux_2level_tapbuf_size16[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[97] when v(mux_2level_tapbuf_size16[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[97] when v(mux_2level_tapbuf_size16[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[97] trig v(mux_2level_tapbuf_size16[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[13]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[97] param='mux_2level_tapbuf_size16[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[13]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[13]_energy_per_cycle param='mux_2level_tapbuf_size16[13]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[97] param='mux_2level_tapbuf_size16[13]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[97] param='dynamic_power_cb_mux[1][1]_rrnode[97]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[97] avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='start_rise_cb_mux[1][1]_rrnode[97]' to='start_rise_cb_mux[1][1]_rrnode[97]+switch_rise_cb_mux[1][1]_rrnode[97]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[97] avg p(Vgvdd_mux_2level_tapbuf_size16[13]) from='start_fall_cb_mux[1][1]_rrnode[97]' to='start_fall_cb_mux[1][1]_rrnode[97]+switch_fall_cb_mux[1][1]_rrnode[97]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_cb_mux[1][1]_rrnode[97]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_cb_mux[1][1]_rrnode[97]' -******* Normal TYPE loads ******* -Xload_inv[300]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[326]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[330]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[333]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[335]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[338]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[342]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[345]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[357]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 mux_2level_tapbuf_size16[13]->out mux_2level_tapbuf_size16[13]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to13] -+ param='sum_leakage_power_cb_mux[0to12]+leakage_cb_mux[1][1]_rrnode[97]' -.meas tran sum_energy_per_cycle_cb_mux[0to13] -+ param='sum_energy_per_cycle_cb_mux[0to12]+energy_per_cycle_cb_mux[1][1]_rrnode[97]' -Xmux_2level_tapbuf_size16[14] mux_2level_tapbuf_size16[14]->in[0] mux_2level_tapbuf_size16[14]->in[1] mux_2level_tapbuf_size16[14]->in[2] mux_2level_tapbuf_size16[14]->in[3] mux_2level_tapbuf_size16[14]->in[4] mux_2level_tapbuf_size16[14]->in[5] mux_2level_tapbuf_size16[14]->in[6] mux_2level_tapbuf_size16[14]->in[7] mux_2level_tapbuf_size16[14]->in[8] mux_2level_tapbuf_size16[14]->in[9] mux_2level_tapbuf_size16[14]->in[10] mux_2level_tapbuf_size16[14]->in[11] mux_2level_tapbuf_size16[14]->in[12] mux_2level_tapbuf_size16[14]->in[13] mux_2level_tapbuf_size16[14]->in[14] mux_2level_tapbuf_size16[14]->in[15] mux_2level_tapbuf_size16[14]->out sram[112]->outb sram[112]->out sram[113]->out sram[113]->outb sram[114]->out sram[114]->outb sram[115]->out sram[115]->outb sram[116]->outb sram[116]->out sram[117]->out sram[117]->outb sram[118]->out sram[118]->outb sram[119]->out sram[119]->outb gvdd_mux_2level_tapbuf_size16[14] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[14], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[112] sram->in sram[112]->out sram[112]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[112]->out) 0 -.nodeset V(sram[112]->outb) vsp -Xsram[113] sram->in sram[113]->out sram[113]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[113]->out) 0 -.nodeset V(sram[113]->outb) vsp -Xsram[114] sram->in sram[114]->out sram[114]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[114]->out) 0 -.nodeset V(sram[114]->outb) vsp -Xsram[115] sram->in sram[115]->out sram[115]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[115]->out) 0 -.nodeset V(sram[115]->outb) vsp -Xsram[116] sram->in sram[116]->out sram[116]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[116]->out) 0 -.nodeset V(sram[116]->outb) vsp -Xsram[117] sram->in sram[117]->out sram[117]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[117]->out) 0 -.nodeset V(sram[117]->outb) vsp -Xsram[118] sram->in sram[118]->out sram[118]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[118]->out) 0 -.nodeset V(sram[118]->outb) vsp -Xsram[119] sram->in sram[119]->out sram[119]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[119]->out) 0 -.nodeset V(sram[119]->outb) vsp -***** Signal mux_2level_tapbuf_size16[14]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[0] mux_2level_tapbuf_size16[14]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[1] mux_2level_tapbuf_size16[14]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[2] mux_2level_tapbuf_size16[14]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[3] mux_2level_tapbuf_size16[14]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[4] mux_2level_tapbuf_size16[14]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[5] mux_2level_tapbuf_size16[14]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[6] mux_2level_tapbuf_size16[14]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[7] mux_2level_tapbuf_size16[14]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[8] mux_2level_tapbuf_size16[14]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[9] mux_2level_tapbuf_size16[14]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[10] mux_2level_tapbuf_size16[14]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[11] mux_2level_tapbuf_size16[14]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[12] mux_2level_tapbuf_size16[14]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[13] mux_2level_tapbuf_size16[14]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[14] mux_2level_tapbuf_size16[14]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[14]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[14]->in[15] mux_2level_tapbuf_size16[14]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[14] gvdd_mux_2level_tapbuf_size16[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[101] when v(mux_2level_tapbuf_size16[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[101] when v(mux_2level_tapbuf_size16[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[101] trig v(mux_2level_tapbuf_size16[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[14]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[101] param='mux_2level_tapbuf_size16[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[14]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[14]_energy_per_cycle param='mux_2level_tapbuf_size16[14]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[101] param='mux_2level_tapbuf_size16[14]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[101] param='dynamic_power_cb_mux[1][1]_rrnode[101]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[101] avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='start_rise_cb_mux[1][1]_rrnode[101]' to='start_rise_cb_mux[1][1]_rrnode[101]+switch_rise_cb_mux[1][1]_rrnode[101]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[101] avg p(Vgvdd_mux_2level_tapbuf_size16[14]) from='start_fall_cb_mux[1][1]_rrnode[101]' to='start_fall_cb_mux[1][1]_rrnode[101]+switch_fall_cb_mux[1][1]_rrnode[101]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_cb_mux[1][1]_rrnode[101]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_cb_mux[1][1]_rrnode[101]' -******* Normal TYPE loads ******* -Xload_inv[360]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[365]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[369]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[381]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[384]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[388]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[389]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[390]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[391]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[392]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[393]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[394]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[395]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[396]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[397]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[398]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[399]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[400]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[401]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[402]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[403]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[404]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[405]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[406]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[407]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[408]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[409]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[410]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[411]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[412]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[413]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[414]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[415]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[416]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[417]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[418]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[419]_no0 mux_2level_tapbuf_size16[14]->out mux_2level_tapbuf_size16[14]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to14] -+ param='sum_leakage_power_cb_mux[0to13]+leakage_cb_mux[1][1]_rrnode[101]' -.meas tran sum_energy_per_cycle_cb_mux[0to14] -+ param='sum_energy_per_cycle_cb_mux[0to13]+energy_per_cycle_cb_mux[1][1]_rrnode[101]' -Xmux_2level_tapbuf_size16[15] mux_2level_tapbuf_size16[15]->in[0] mux_2level_tapbuf_size16[15]->in[1] mux_2level_tapbuf_size16[15]->in[2] mux_2level_tapbuf_size16[15]->in[3] mux_2level_tapbuf_size16[15]->in[4] mux_2level_tapbuf_size16[15]->in[5] mux_2level_tapbuf_size16[15]->in[6] mux_2level_tapbuf_size16[15]->in[7] mux_2level_tapbuf_size16[15]->in[8] mux_2level_tapbuf_size16[15]->in[9] mux_2level_tapbuf_size16[15]->in[10] mux_2level_tapbuf_size16[15]->in[11] mux_2level_tapbuf_size16[15]->in[12] mux_2level_tapbuf_size16[15]->in[13] mux_2level_tapbuf_size16[15]->in[14] mux_2level_tapbuf_size16[15]->in[15] mux_2level_tapbuf_size16[15]->out sram[120]->outb sram[120]->out sram[121]->out sram[121]->outb sram[122]->out sram[122]->outb sram[123]->out sram[123]->outb sram[124]->outb sram[124]->out sram[125]->out sram[125]->outb sram[126]->out sram[126]->outb sram[127]->out sram[127]->outb gvdd_mux_2level_tapbuf_size16[15] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[15], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[120] sram->in sram[120]->out sram[120]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[120]->out) 0 -.nodeset V(sram[120]->outb) vsp -Xsram[121] sram->in sram[121]->out sram[121]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[121]->out) 0 -.nodeset V(sram[121]->outb) vsp -Xsram[122] sram->in sram[122]->out sram[122]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[122]->out) 0 -.nodeset V(sram[122]->outb) vsp -Xsram[123] sram->in sram[123]->out sram[123]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[123]->out) 0 -.nodeset V(sram[123]->outb) vsp -Xsram[124] sram->in sram[124]->out sram[124]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[124]->out) 0 -.nodeset V(sram[124]->outb) vsp -Xsram[125] sram->in sram[125]->out sram[125]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[125]->out) 0 -.nodeset V(sram[125]->outb) vsp -Xsram[126] sram->in sram[126]->out sram[126]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[126]->out) 0 -.nodeset V(sram[126]->outb) vsp -Xsram[127] sram->in sram[127]->out sram[127]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[127]->out) 0 -.nodeset V(sram[127]->outb) vsp -***** Signal mux_2level_tapbuf_size16[15]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[0] mux_2level_tapbuf_size16[15]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[1] mux_2level_tapbuf_size16[15]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[2] mux_2level_tapbuf_size16[15]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[3] mux_2level_tapbuf_size16[15]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[4] mux_2level_tapbuf_size16[15]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[5] mux_2level_tapbuf_size16[15]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[6] mux_2level_tapbuf_size16[15]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[7] mux_2level_tapbuf_size16[15]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[8] mux_2level_tapbuf_size16[15]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[9] mux_2level_tapbuf_size16[15]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[10] mux_2level_tapbuf_size16[15]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[11] mux_2level_tapbuf_size16[15]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[12] mux_2level_tapbuf_size16[15]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[13] mux_2level_tapbuf_size16[15]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[14] mux_2level_tapbuf_size16[15]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[15]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[15]->in[15] mux_2level_tapbuf_size16[15]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[15] gvdd_mux_2level_tapbuf_size16[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[105] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[105] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[105] when v(mux_2level_tapbuf_size16[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[105] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[105] when v(mux_2level_tapbuf_size16[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[105] trig v(mux_2level_tapbuf_size16[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[15]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[105] param='mux_2level_tapbuf_size16[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[15]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[15]_energy_per_cycle param='mux_2level_tapbuf_size16[15]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[105] param='mux_2level_tapbuf_size16[15]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[105] param='dynamic_power_cb_mux[1][1]_rrnode[105]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[105] avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='start_rise_cb_mux[1][1]_rrnode[105]' to='start_rise_cb_mux[1][1]_rrnode[105]+switch_rise_cb_mux[1][1]_rrnode[105]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[105] avg p(Vgvdd_mux_2level_tapbuf_size16[15]) from='start_fall_cb_mux[1][1]_rrnode[105]' to='start_fall_cb_mux[1][1]_rrnode[105]+switch_fall_cb_mux[1][1]_rrnode[105]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_cb_mux[1][1]_rrnode[105]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_cb_mux[1][1]_rrnode[105]' -******* Normal TYPE loads ******* -Xload_inv[420]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[421]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[422]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[423]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[424]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[425]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[426]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[427]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[428]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[429]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[430]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[431]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[432]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[433]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[434]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[435]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[436]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[437]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[438]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[439]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[440]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[441]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[442]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[443]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[444]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[445]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[446]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[447]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[448]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[449]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[450]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[451]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[452]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[453]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[454]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[455]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[456]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[457]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[458]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[459]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[460]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[461]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[462]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[463]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[464]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[465]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[466]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[467]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[468]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[469]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[470]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[471]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[472]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[473]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[474]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[475]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[476]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[477]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[478]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[479]_no0 mux_2level_tapbuf_size16[15]->out mux_2level_tapbuf_size16[15]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to15] -+ param='sum_leakage_power_cb_mux[0to14]+leakage_cb_mux[1][1]_rrnode[105]' -.meas tran sum_energy_per_cycle_cb_mux[0to15] -+ param='sum_energy_per_cycle_cb_mux[0to14]+energy_per_cycle_cb_mux[1][1]_rrnode[105]' -Xmux_2level_tapbuf_size16[16] mux_2level_tapbuf_size16[16]->in[0] mux_2level_tapbuf_size16[16]->in[1] mux_2level_tapbuf_size16[16]->in[2] mux_2level_tapbuf_size16[16]->in[3] mux_2level_tapbuf_size16[16]->in[4] mux_2level_tapbuf_size16[16]->in[5] mux_2level_tapbuf_size16[16]->in[6] mux_2level_tapbuf_size16[16]->in[7] mux_2level_tapbuf_size16[16]->in[8] mux_2level_tapbuf_size16[16]->in[9] mux_2level_tapbuf_size16[16]->in[10] mux_2level_tapbuf_size16[16]->in[11] mux_2level_tapbuf_size16[16]->in[12] mux_2level_tapbuf_size16[16]->in[13] mux_2level_tapbuf_size16[16]->in[14] mux_2level_tapbuf_size16[16]->in[15] mux_2level_tapbuf_size16[16]->out sram[128]->outb sram[128]->out sram[129]->out sram[129]->outb sram[130]->out sram[130]->outb sram[131]->out sram[131]->outb sram[132]->outb sram[132]->out sram[133]->out sram[133]->outb sram[134]->out sram[134]->outb sram[135]->out sram[135]->outb gvdd_mux_2level_tapbuf_size16[16] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[16], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[128] sram->in sram[128]->out sram[128]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[128]->out) 0 -.nodeset V(sram[128]->outb) vsp -Xsram[129] sram->in sram[129]->out sram[129]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[129]->out) 0 -.nodeset V(sram[129]->outb) vsp -Xsram[130] sram->in sram[130]->out sram[130]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[130]->out) 0 -.nodeset V(sram[130]->outb) vsp -Xsram[131] sram->in sram[131]->out sram[131]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[131]->out) 0 -.nodeset V(sram[131]->outb) vsp -Xsram[132] sram->in sram[132]->out sram[132]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[132]->out) 0 -.nodeset V(sram[132]->outb) vsp -Xsram[133] sram->in sram[133]->out sram[133]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[133]->out) 0 -.nodeset V(sram[133]->outb) vsp -Xsram[134] sram->in sram[134]->out sram[134]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[134]->out) 0 -.nodeset V(sram[134]->outb) vsp -Xsram[135] sram->in sram[135]->out sram[135]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[135]->out) 0 -.nodeset V(sram[135]->outb) vsp -***** Signal mux_2level_tapbuf_size16[16]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[0] mux_2level_tapbuf_size16[16]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[1] mux_2level_tapbuf_size16[16]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[2] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[16]->in[2] mux_2level_tapbuf_size16[16]->in[2] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[16]->in[3] density = 0.2026, probability=0.4982.***** -Vmux_2level_tapbuf_size16[16]->in[3] mux_2level_tapbuf_size16[16]->in[3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_tapbuf_size16[16]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[4] mux_2level_tapbuf_size16[16]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[5] mux_2level_tapbuf_size16[16]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[6] mux_2level_tapbuf_size16[16]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[7] mux_2level_tapbuf_size16[16]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[8] mux_2level_tapbuf_size16[16]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[9] mux_2level_tapbuf_size16[16]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[10] mux_2level_tapbuf_size16[16]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[11] mux_2level_tapbuf_size16[16]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[12] mux_2level_tapbuf_size16[16]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[13] mux_2level_tapbuf_size16[16]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[14] mux_2level_tapbuf_size16[16]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[16]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[16]->in[15] mux_2level_tapbuf_size16[16]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[16] gvdd_mux_2level_tapbuf_size16[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[109] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[109] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[109] when v(mux_2level_tapbuf_size16[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[109] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[109] when v(mux_2level_tapbuf_size16[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[109] trig v(mux_2level_tapbuf_size16[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[16]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[109] param='mux_2level_tapbuf_size16[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[16]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_tapbuf_size16[16]_energy_per_cycle param='mux_2level_tapbuf_size16[16]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[109] param='mux_2level_tapbuf_size16[16]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[109] param='dynamic_power_cb_mux[1][1]_rrnode[109]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[109] avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='start_rise_cb_mux[1][1]_rrnode[109]' to='start_rise_cb_mux[1][1]_rrnode[109]+switch_rise_cb_mux[1][1]_rrnode[109]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[109] avg p(Vgvdd_mux_2level_tapbuf_size16[16]) from='start_fall_cb_mux[1][1]_rrnode[109]' to='start_fall_cb_mux[1][1]_rrnode[109]+switch_fall_cb_mux[1][1]_rrnode[109]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_cb_mux[1][1]_rrnode[109]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_cb_mux[1][1]_rrnode[109]' -******* Normal TYPE loads ******* -Xload_inv[480]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[481]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[482]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[483]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[484]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[485]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[486]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[487]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[488]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[489]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[490]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[491]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[492]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[493]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[494]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[495]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[496]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[497]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[498]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[499]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[500]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[501]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[502]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[503]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[504]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[505]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[506]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[507]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[508]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[509]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[510]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[511]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[512]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[513]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[514]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[515]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[516]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[517]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[518]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[519]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[520]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[521]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[522]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[523]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[524]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[525]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[526]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[527]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[528]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[529]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[530]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[531]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[532]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[533]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[534]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[535]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[536]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[537]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[538]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[539]_no0 mux_2level_tapbuf_size16[16]->out mux_2level_tapbuf_size16[16]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to16] -+ param='sum_leakage_power_cb_mux[0to15]+leakage_cb_mux[1][1]_rrnode[109]' -.meas tran sum_energy_per_cycle_cb_mux[0to16] -+ param='sum_energy_per_cycle_cb_mux[0to15]+energy_per_cycle_cb_mux[1][1]_rrnode[109]' -Xmux_2level_tapbuf_size16[17] mux_2level_tapbuf_size16[17]->in[0] mux_2level_tapbuf_size16[17]->in[1] mux_2level_tapbuf_size16[17]->in[2] mux_2level_tapbuf_size16[17]->in[3] mux_2level_tapbuf_size16[17]->in[4] mux_2level_tapbuf_size16[17]->in[5] mux_2level_tapbuf_size16[17]->in[6] mux_2level_tapbuf_size16[17]->in[7] mux_2level_tapbuf_size16[17]->in[8] mux_2level_tapbuf_size16[17]->in[9] mux_2level_tapbuf_size16[17]->in[10] mux_2level_tapbuf_size16[17]->in[11] mux_2level_tapbuf_size16[17]->in[12] mux_2level_tapbuf_size16[17]->in[13] mux_2level_tapbuf_size16[17]->in[14] mux_2level_tapbuf_size16[17]->in[15] mux_2level_tapbuf_size16[17]->out sram[136]->outb sram[136]->out sram[137]->out sram[137]->outb sram[138]->out sram[138]->outb sram[139]->out sram[139]->outb sram[140]->outb sram[140]->out sram[141]->out sram[141]->outb sram[142]->out sram[142]->outb sram[143]->out sram[143]->outb gvdd_mux_2level_tapbuf_size16[17] 0 mux_2level_tapbuf_size16 -***** SRAM bits for MUX[17], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[136] sram->in sram[136]->out sram[136]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[136]->out) 0 -.nodeset V(sram[136]->outb) vsp -Xsram[137] sram->in sram[137]->out sram[137]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[137]->out) 0 -.nodeset V(sram[137]->outb) vsp -Xsram[138] sram->in sram[138]->out sram[138]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[138]->out) 0 -.nodeset V(sram[138]->outb) vsp -Xsram[139] sram->in sram[139]->out sram[139]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[139]->out) 0 -.nodeset V(sram[139]->outb) vsp -Xsram[140] sram->in sram[140]->out sram[140]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[140]->out) 0 -.nodeset V(sram[140]->outb) vsp -Xsram[141] sram->in sram[141]->out sram[141]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[141]->out) 0 -.nodeset V(sram[141]->outb) vsp -Xsram[142] sram->in sram[142]->out sram[142]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[142]->out) 0 -.nodeset V(sram[142]->outb) vsp -Xsram[143] sram->in sram[143]->out sram[143]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[143]->out) 0 -.nodeset V(sram[143]->outb) vsp -***** Signal mux_2level_tapbuf_size16[17]->in[0] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[0] mux_2level_tapbuf_size16[17]->in[0] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[1] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[1] mux_2level_tapbuf_size16[17]->in[1] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[2] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[2] mux_2level_tapbuf_size16[17]->in[2] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[3] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[3] mux_2level_tapbuf_size16[17]->in[3] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[4] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[4] mux_2level_tapbuf_size16[17]->in[4] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[5] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[5] mux_2level_tapbuf_size16[17]->in[5] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[6] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[6] mux_2level_tapbuf_size16[17]->in[6] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[7] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[7] mux_2level_tapbuf_size16[17]->in[7] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[8] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[8] mux_2level_tapbuf_size16[17]->in[8] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[9] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[9] mux_2level_tapbuf_size16[17]->in[9] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[10] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[10] mux_2level_tapbuf_size16[17]->in[10] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[11] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[11] mux_2level_tapbuf_size16[17]->in[11] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[12] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[12] mux_2level_tapbuf_size16[17]->in[12] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[13] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[13] mux_2level_tapbuf_size16[17]->in[13] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[14] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[14] mux_2level_tapbuf_size16[17]->in[14] 0 -+ 0 -***** Signal mux_2level_tapbuf_size16[17]->in[15] density = 0, probability=0.***** -Vmux_2level_tapbuf_size16[17]->in[15] mux_2level_tapbuf_size16[17]->in[15] 0 -+ 0 -Vgvdd_mux_2level_tapbuf_size16[17] gvdd_mux_2level_tapbuf_size16[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_cb_mux[1][1]_rrnode[113] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_cb_mux[1][1]_rrnode[113] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_cb_mux[1][1]_rrnode[113] when v(mux_2level_tapbuf_size16[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_cb_mux[1][1]_rrnode[113] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_cb_mux[1][1]_rrnode[113] when v(mux_2level_tapbuf_size16[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_cb_mux[1][1]_rrnode[113] trig v(mux_2level_tapbuf_size16[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_tapbuf_size16[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[17]_leakage_power avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from=0 to='clock_period' -.meas tran leakage_cb_mux[1][1]_rrnode[113] param='mux_2level_tapbuf_size16[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_tapbuf_size16[17]_dynamic_power avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='clock_period' to='2*clock_period' -.meas tran mux_2level_tapbuf_size16[17]_energy_per_cycle param='mux_2level_tapbuf_size16[17]_dynamic_power*clock_period' -.meas tran dynamic_power_cb_mux[1][1]_rrnode[113] param='mux_2level_tapbuf_size16[17]_dynamic_power' -.meas tran energy_per_cycle_cb_mux[1][1]_rrnode[113] param='dynamic_power_cb_mux[1][1]_rrnode[113]*clock_period' -.meas tran dynamic_rise_cb_mux[1][1]_rrnode[113] avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='start_rise_cb_mux[1][1]_rrnode[113]' to='start_rise_cb_mux[1][1]_rrnode[113]+switch_rise_cb_mux[1][1]_rrnode[113]' -.meas tran dynamic_fall_cb_mux[1][1]_rrnode[113] avg p(Vgvdd_mux_2level_tapbuf_size16[17]) from='start_fall_cb_mux[1][1]_rrnode[113]' to='start_fall_cb_mux[1][1]_rrnode[113]+switch_fall_cb_mux[1][1]_rrnode[113]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_cb_mux[1][1]_rrnode[113]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_cb_mux[1][1]_rrnode[113]' -******* Normal TYPE loads ******* -Xload_inv[540]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[541]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[542]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[543]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[544]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[545]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[546]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[547]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[548]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[549]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[550]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[551]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[552]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[553]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[554]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[555]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[556]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[557]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[558]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[559]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[560]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[561]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[562]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[563]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[564]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[565]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[566]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[567]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[568]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[569]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[570]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[571]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[572]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[573]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[574]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[575]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[576]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[577]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[578]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[579]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[580]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[581]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[582]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[583]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[584]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[585]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[586]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[587]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[588]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[589]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[590]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[591]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[592]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[593]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[594]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[595]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[596]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[597]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[598]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[599]_no0 mux_2level_tapbuf_size16[17]->out mux_2level_tapbuf_size16[17]->out_out[59] gvdd_load 0 inv size=1 -******* END loads ******* -.meas tran sum_leakage_power_cb_mux[0to17] -+ param='sum_leakage_power_cb_mux[0to16]+leakage_cb_mux[1][1]_rrnode[113]' -.meas tran sum_energy_per_cycle_cb_mux[0to17] -+ param='sum_energy_per_cycle_cb_mux[0to16]+energy_per_cycle_cb_mux[1][1]_rrnode[113]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='6*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to17]' -.meas tran total_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to17]' -.meas tran total_leakage_power_cb_mux -+ param='sum_leakage_power_cb_mux[0to17]' -.meas tran total_energy_per_cycle_cb_mux -+ param='sum_energy_per_cycle_cb_mux[0to17]' -.end diff --git a/examples/spice_test_example_2/cb_tb/example_2_cbx1_0_cb_testbench.sp b/examples/spice_test_example_2/cb_tb/example_2_cbx1_0_cb_testbench.sp deleted file mode 100644 index 84b87b831..000000000 --- a/examples/spice_test_example_2/cb_tb/example_2_cbx1_0_cb_testbench.sp +++ /dev/null @@ -1,1266 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_cbs -****** Include subckt netlists: Connection Box X-channel [1][0] ***** -.include './spice_test_example_2/subckt/cbx_1_0.sp' -***** Call defined Connection Box[1][0] ***** -Xcbx[1][0] -+ chanx[1][0]_midout[0] -+ chanx[1][0]_midout[1] -+ chanx[1][0]_midout[2] -+ chanx[1][0]_midout[3] -+ chanx[1][0]_midout[4] -+ chanx[1][0]_midout[5] -+ chanx[1][0]_midout[6] -+ chanx[1][0]_midout[7] -+ chanx[1][0]_midout[8] -+ chanx[1][0]_midout[9] -+ chanx[1][0]_midout[10] -+ chanx[1][0]_midout[11] -+ chanx[1][0]_midout[12] -+ chanx[1][0]_midout[13] -+ chanx[1][0]_midout[14] -+ chanx[1][0]_midout[15] -+ chanx[1][0]_midout[16] -+ chanx[1][0]_midout[17] -+ chanx[1][0]_midout[18] -+ chanx[1][0]_midout[19] -+ chanx[1][0]_midout[20] -+ chanx[1][0]_midout[21] -+ chanx[1][0]_midout[22] -+ chanx[1][0]_midout[23] -+ chanx[1][0]_midout[24] -+ chanx[1][0]_midout[25] -+ chanx[1][0]_midout[26] -+ chanx[1][0]_midout[27] -+ chanx[1][0]_midout[28] -+ chanx[1][0]_midout[29] -+ chanx[1][0]_midout[30] -+ chanx[1][0]_midout[31] -+ chanx[1][0]_midout[32] -+ chanx[1][0]_midout[33] -+ chanx[1][0]_midout[34] -+ chanx[1][0]_midout[35] -+ chanx[1][0]_midout[36] -+ chanx[1][0]_midout[37] -+ chanx[1][0]_midout[38] -+ chanx[1][0]_midout[39] -+ chanx[1][0]_midout[40] -+ chanx[1][0]_midout[41] -+ chanx[1][0]_midout[42] -+ chanx[1][0]_midout[43] -+ chanx[1][0]_midout[44] -+ chanx[1][0]_midout[45] -+ chanx[1][0]_midout[46] -+ chanx[1][0]_midout[47] -+ chanx[1][0]_midout[48] -+ chanx[1][0]_midout[49] -+ chanx[1][0]_midout[50] -+ chanx[1][0]_midout[51] -+ chanx[1][0]_midout[52] -+ chanx[1][0]_midout[53] -+ chanx[1][0]_midout[54] -+ chanx[1][0]_midout[55] -+ chanx[1][0]_midout[56] -+ chanx[1][0]_midout[57] -+ chanx[1][0]_midout[58] -+ chanx[1][0]_midout[59] -+ chanx[1][0]_midout[60] -+ chanx[1][0]_midout[61] -+ chanx[1][0]_midout[62] -+ chanx[1][0]_midout[63] -+ chanx[1][0]_midout[64] -+ chanx[1][0]_midout[65] -+ chanx[1][0]_midout[66] -+ chanx[1][0]_midout[67] -+ chanx[1][0]_midout[68] -+ chanx[1][0]_midout[69] -+ chanx[1][0]_midout[70] -+ chanx[1][0]_midout[71] -+ chanx[1][0]_midout[72] -+ chanx[1][0]_midout[73] -+ chanx[1][0]_midout[74] -+ chanx[1][0]_midout[75] -+ chanx[1][0]_midout[76] -+ chanx[1][0]_midout[77] -+ chanx[1][0]_midout[78] -+ chanx[1][0]_midout[79] -+ chanx[1][0]_midout[80] -+ chanx[1][0]_midout[81] -+ chanx[1][0]_midout[82] -+ chanx[1][0]_midout[83] -+ chanx[1][0]_midout[84] -+ chanx[1][0]_midout[85] -+ chanx[1][0]_midout[86] -+ chanx[1][0]_midout[87] -+ chanx[1][0]_midout[88] -+ chanx[1][0]_midout[89] -+ chanx[1][0]_midout[90] -+ chanx[1][0]_midout[91] -+ chanx[1][0]_midout[92] -+ chanx[1][0]_midout[93] -+ chanx[1][0]_midout[94] -+ chanx[1][0]_midout[95] -+ chanx[1][0]_midout[96] -+ chanx[1][0]_midout[97] -+ chanx[1][0]_midout[98] -+ chanx[1][0]_midout[99] -+ grid[1][1]_pin[0][2][2] -+ grid[1][1]_pin[0][2][6] -+ grid[1][1]_pin[0][2][10] -+ grid[1][1]_pin[0][2][14] -+ grid[1][1]_pin[0][2][18] -+ grid[1][1]_pin[0][2][22] -+ grid[1][1]_pin[0][2][26] -+ grid[1][1]_pin[0][2][30] -+ grid[1][1]_pin[0][2][34] -+ grid[1][1]_pin[0][2][38] -+ grid[1][1]_pin[0][2][50] -+ grid[1][0]_pin[0][0][0] -+ grid[1][0]_pin[0][0][2] -+ grid[1][0]_pin[0][0][4] -+ grid[1][0]_pin[0][0][6] -+ grid[1][0]_pin[0][0][8] -+ grid[1][0]_pin[0][0][10] -+ grid[1][0]_pin[0][0][12] -+ grid[1][0]_pin[0][0][14] -+ gvdd_cbx[1][0] 0 cbx[1][0] -***** Signal chanx[1][0]_midout[0] density = 0, probability=0.***** -Vchanx[1][0]_midout[0] chanx[1][0]_midout[0] 0 -+ 0 -***** Signal chanx[1][0]_midout[1] density = 0, probability=0.***** -Vchanx[1][0]_midout[1] chanx[1][0]_midout[1] 0 -+ 0 -***** Signal chanx[1][0]_midout[2] density = 0, probability=0.***** -Vchanx[1][0]_midout[2] chanx[1][0]_midout[2] 0 -+ 0 -***** Signal chanx[1][0]_midout[3] density = 0, probability=0.***** -Vchanx[1][0]_midout[3] chanx[1][0]_midout[3] 0 -+ 0 -***** Signal chanx[1][0]_midout[4] density = 0, probability=0.***** -Vchanx[1][0]_midout[4] chanx[1][0]_midout[4] 0 -+ 0 -***** Signal chanx[1][0]_midout[5] density = 0, probability=0.***** -Vchanx[1][0]_midout[5] chanx[1][0]_midout[5] 0 -+ 0 -***** Signal chanx[1][0]_midout[6] density = 0, probability=0.***** -Vchanx[1][0]_midout[6] chanx[1][0]_midout[6] 0 -+ 0 -***** Signal chanx[1][0]_midout[7] density = 0, probability=0.***** -Vchanx[1][0]_midout[7] chanx[1][0]_midout[7] 0 -+ 0 -***** Signal chanx[1][0]_midout[8] density = 0, probability=0.***** -Vchanx[1][0]_midout[8] chanx[1][0]_midout[8] 0 -+ 0 -***** Signal chanx[1][0]_midout[9] density = 0, probability=0.***** -Vchanx[1][0]_midout[9] chanx[1][0]_midout[9] 0 -+ 0 -***** Signal chanx[1][0]_midout[10] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_midout[10] chanx[1][0]_midout[10] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[11] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_midout[11] chanx[1][0]_midout[11] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[12] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_midout[12] chanx[1][0]_midout[12] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[13] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_midout[13] chanx[1][0]_midout[13] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[14] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_midout[14] chanx[1][0]_midout[14] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[15] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_midout[15] chanx[1][0]_midout[15] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[16] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_midout[16] chanx[1][0]_midout[16] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[17] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_midout[17] chanx[1][0]_midout[17] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[18] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_midout[18] chanx[1][0]_midout[18] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[19] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_midout[19] chanx[1][0]_midout[19] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[20] density = 0, probability=0.***** -Vchanx[1][0]_midout[20] chanx[1][0]_midout[20] 0 -+ 0 -***** Signal chanx[1][0]_midout[21] density = 0, probability=0.***** -Vchanx[1][0]_midout[21] chanx[1][0]_midout[21] 0 -+ 0 -***** Signal chanx[1][0]_midout[22] density = 0, probability=0.***** -Vchanx[1][0]_midout[22] chanx[1][0]_midout[22] 0 -+ 0 -***** Signal chanx[1][0]_midout[23] density = 0, probability=0.***** -Vchanx[1][0]_midout[23] chanx[1][0]_midout[23] 0 -+ 0 -***** Signal chanx[1][0]_midout[24] density = 0, probability=0.***** -Vchanx[1][0]_midout[24] chanx[1][0]_midout[24] 0 -+ 0 -***** Signal chanx[1][0]_midout[25] density = 0, probability=0.***** -Vchanx[1][0]_midout[25] chanx[1][0]_midout[25] 0 -+ 0 -***** Signal chanx[1][0]_midout[26] density = 0, probability=0.***** -Vchanx[1][0]_midout[26] chanx[1][0]_midout[26] 0 -+ 0 -***** Signal chanx[1][0]_midout[27] density = 0, probability=0.***** -Vchanx[1][0]_midout[27] chanx[1][0]_midout[27] 0 -+ 0 -***** Signal chanx[1][0]_midout[28] density = 0, probability=0.***** -Vchanx[1][0]_midout[28] chanx[1][0]_midout[28] 0 -+ 0 -***** Signal chanx[1][0]_midout[29] density = 0, probability=0.***** -Vchanx[1][0]_midout[29] chanx[1][0]_midout[29] 0 -+ 0 -***** Signal chanx[1][0]_midout[30] density = 0, probability=0.***** -Vchanx[1][0]_midout[30] chanx[1][0]_midout[30] 0 -+ 0 -***** Signal chanx[1][0]_midout[31] density = 0, probability=0.***** -Vchanx[1][0]_midout[31] chanx[1][0]_midout[31] 0 -+ 0 -***** Signal chanx[1][0]_midout[32] density = 0, probability=0.***** -Vchanx[1][0]_midout[32] chanx[1][0]_midout[32] 0 -+ 0 -***** Signal chanx[1][0]_midout[33] density = 0, probability=0.***** -Vchanx[1][0]_midout[33] chanx[1][0]_midout[33] 0 -+ 0 -***** Signal chanx[1][0]_midout[34] density = 0, probability=0.***** -Vchanx[1][0]_midout[34] chanx[1][0]_midout[34] 0 -+ 0 -***** Signal chanx[1][0]_midout[35] density = 0, probability=0.***** -Vchanx[1][0]_midout[35] chanx[1][0]_midout[35] 0 -+ 0 -***** Signal chanx[1][0]_midout[36] density = 0, probability=0.***** -Vchanx[1][0]_midout[36] chanx[1][0]_midout[36] 0 -+ 0 -***** Signal chanx[1][0]_midout[37] density = 0, probability=0.***** -Vchanx[1][0]_midout[37] chanx[1][0]_midout[37] 0 -+ 0 -***** Signal chanx[1][0]_midout[38] density = 0, probability=0.***** -Vchanx[1][0]_midout[38] chanx[1][0]_midout[38] 0 -+ 0 -***** Signal chanx[1][0]_midout[39] density = 0, probability=0.***** -Vchanx[1][0]_midout[39] chanx[1][0]_midout[39] 0 -+ 0 -***** Signal chanx[1][0]_midout[40] density = 0, probability=0.***** -Vchanx[1][0]_midout[40] chanx[1][0]_midout[40] 0 -+ 0 -***** Signal chanx[1][0]_midout[41] density = 0, probability=0.***** -Vchanx[1][0]_midout[41] chanx[1][0]_midout[41] 0 -+ 0 -***** Signal chanx[1][0]_midout[42] density = 0, probability=0.***** -Vchanx[1][0]_midout[42] chanx[1][0]_midout[42] 0 -+ 0 -***** Signal chanx[1][0]_midout[43] density = 0, probability=0.***** -Vchanx[1][0]_midout[43] chanx[1][0]_midout[43] 0 -+ 0 -***** Signal chanx[1][0]_midout[44] density = 0, probability=0.***** -Vchanx[1][0]_midout[44] chanx[1][0]_midout[44] 0 -+ 0 -***** Signal chanx[1][0]_midout[45] density = 0, probability=0.***** -Vchanx[1][0]_midout[45] chanx[1][0]_midout[45] 0 -+ 0 -***** Signal chanx[1][0]_midout[46] density = 0, probability=0.***** -Vchanx[1][0]_midout[46] chanx[1][0]_midout[46] 0 -+ 0 -***** Signal chanx[1][0]_midout[47] density = 0, probability=0.***** -Vchanx[1][0]_midout[47] chanx[1][0]_midout[47] 0 -+ 0 -***** Signal chanx[1][0]_midout[48] density = 0, probability=0.***** -Vchanx[1][0]_midout[48] chanx[1][0]_midout[48] 0 -+ 0 -***** Signal chanx[1][0]_midout[49] density = 0, probability=0.***** -Vchanx[1][0]_midout[49] chanx[1][0]_midout[49] 0 -+ 0 -***** Signal chanx[1][0]_midout[50] density = 0, probability=0.***** -Vchanx[1][0]_midout[50] chanx[1][0]_midout[50] 0 -+ 0 -***** Signal chanx[1][0]_midout[51] density = 0, probability=0.***** -Vchanx[1][0]_midout[51] chanx[1][0]_midout[51] 0 -+ 0 -***** Signal chanx[1][0]_midout[52] density = 0, probability=0.***** -Vchanx[1][0]_midout[52] chanx[1][0]_midout[52] 0 -+ 0 -***** Signal chanx[1][0]_midout[53] density = 0, probability=0.***** -Vchanx[1][0]_midout[53] chanx[1][0]_midout[53] 0 -+ 0 -***** Signal chanx[1][0]_midout[54] density = 0, probability=0.***** -Vchanx[1][0]_midout[54] chanx[1][0]_midout[54] 0 -+ 0 -***** Signal chanx[1][0]_midout[55] density = 0, probability=0.***** -Vchanx[1][0]_midout[55] chanx[1][0]_midout[55] 0 -+ 0 -***** Signal chanx[1][0]_midout[56] density = 0, probability=0.***** -Vchanx[1][0]_midout[56] chanx[1][0]_midout[56] 0 -+ 0 -***** Signal chanx[1][0]_midout[57] density = 0, probability=0.***** -Vchanx[1][0]_midout[57] chanx[1][0]_midout[57] 0 -+ 0 -***** Signal chanx[1][0]_midout[58] density = 0, probability=0.***** -Vchanx[1][0]_midout[58] chanx[1][0]_midout[58] 0 -+ 0 -***** Signal chanx[1][0]_midout[59] density = 0, probability=0.***** -Vchanx[1][0]_midout[59] chanx[1][0]_midout[59] 0 -+ 0 -***** Signal chanx[1][0]_midout[60] density = 0, probability=0.***** -Vchanx[1][0]_midout[60] chanx[1][0]_midout[60] 0 -+ 0 -***** Signal chanx[1][0]_midout[61] density = 0, probability=0.***** -Vchanx[1][0]_midout[61] chanx[1][0]_midout[61] 0 -+ 0 -***** Signal chanx[1][0]_midout[62] density = 0, probability=0.***** -Vchanx[1][0]_midout[62] chanx[1][0]_midout[62] 0 -+ 0 -***** Signal chanx[1][0]_midout[63] density = 0, probability=0.***** -Vchanx[1][0]_midout[63] chanx[1][0]_midout[63] 0 -+ 0 -***** Signal chanx[1][0]_midout[64] density = 0, probability=0.***** -Vchanx[1][0]_midout[64] chanx[1][0]_midout[64] 0 -+ 0 -***** Signal chanx[1][0]_midout[65] density = 0, probability=0.***** -Vchanx[1][0]_midout[65] chanx[1][0]_midout[65] 0 -+ 0 -***** Signal chanx[1][0]_midout[66] density = 0, probability=0.***** -Vchanx[1][0]_midout[66] chanx[1][0]_midout[66] 0 -+ 0 -***** Signal chanx[1][0]_midout[67] density = 0, probability=0.***** -Vchanx[1][0]_midout[67] chanx[1][0]_midout[67] 0 -+ 0 -***** Signal chanx[1][0]_midout[68] density = 0, probability=0.***** -Vchanx[1][0]_midout[68] chanx[1][0]_midout[68] 0 -+ 0 -***** Signal chanx[1][0]_midout[69] density = 0, probability=0.***** -Vchanx[1][0]_midout[69] chanx[1][0]_midout[69] 0 -+ 0 -***** Signal chanx[1][0]_midout[70] density = 0, probability=0.***** -Vchanx[1][0]_midout[70] chanx[1][0]_midout[70] 0 -+ 0 -***** Signal chanx[1][0]_midout[71] density = 0, probability=0.***** -Vchanx[1][0]_midout[71] chanx[1][0]_midout[71] 0 -+ 0 -***** Signal chanx[1][0]_midout[72] density = 0, probability=0.***** -Vchanx[1][0]_midout[72] chanx[1][0]_midout[72] 0 -+ 0 -***** Signal chanx[1][0]_midout[73] density = 0, probability=0.***** -Vchanx[1][0]_midout[73] chanx[1][0]_midout[73] 0 -+ 0 -***** Signal chanx[1][0]_midout[74] density = 0, probability=0.***** -Vchanx[1][0]_midout[74] chanx[1][0]_midout[74] 0 -+ 0 -***** Signal chanx[1][0]_midout[75] density = 0, probability=0.***** -Vchanx[1][0]_midout[75] chanx[1][0]_midout[75] 0 -+ 0 -***** Signal chanx[1][0]_midout[76] density = 0, probability=0.***** -Vchanx[1][0]_midout[76] chanx[1][0]_midout[76] 0 -+ 0 -***** Signal chanx[1][0]_midout[77] density = 0, probability=0.***** -Vchanx[1][0]_midout[77] chanx[1][0]_midout[77] 0 -+ 0 -***** Signal chanx[1][0]_midout[78] density = 0, probability=0.***** -Vchanx[1][0]_midout[78] chanx[1][0]_midout[78] 0 -+ 0 -***** Signal chanx[1][0]_midout[79] density = 0.2026, probability=0.4982.***** -Vchanx[1][0]_midout[79] chanx[1][0]_midout[79] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][0]_midout[80] density = 0, probability=0.***** -Vchanx[1][0]_midout[80] chanx[1][0]_midout[80] 0 -+ 0 -***** Signal chanx[1][0]_midout[81] density = 0, probability=0.***** -Vchanx[1][0]_midout[81] chanx[1][0]_midout[81] 0 -+ 0 -***** Signal chanx[1][0]_midout[82] density = 0, probability=0.***** -Vchanx[1][0]_midout[82] chanx[1][0]_midout[82] 0 -+ 0 -***** Signal chanx[1][0]_midout[83] density = 0, probability=0.***** -Vchanx[1][0]_midout[83] chanx[1][0]_midout[83] 0 -+ 0 -***** Signal chanx[1][0]_midout[84] density = 0, probability=0.***** -Vchanx[1][0]_midout[84] chanx[1][0]_midout[84] 0 -+ 0 -***** Signal chanx[1][0]_midout[85] density = 0, probability=0.***** -Vchanx[1][0]_midout[85] chanx[1][0]_midout[85] 0 -+ 0 -***** Signal chanx[1][0]_midout[86] density = 0, probability=0.***** -Vchanx[1][0]_midout[86] chanx[1][0]_midout[86] 0 -+ 0 -***** Signal chanx[1][0]_midout[87] density = 0, probability=0.***** -Vchanx[1][0]_midout[87] chanx[1][0]_midout[87] 0 -+ 0 -***** Signal chanx[1][0]_midout[88] density = 0, probability=0.***** -Vchanx[1][0]_midout[88] chanx[1][0]_midout[88] 0 -+ 0 -***** Signal chanx[1][0]_midout[89] density = 0, probability=0.***** -Vchanx[1][0]_midout[89] chanx[1][0]_midout[89] 0 -+ 0 -***** Signal chanx[1][0]_midout[90] density = 0, probability=0.***** -Vchanx[1][0]_midout[90] chanx[1][0]_midout[90] 0 -+ 0 -***** Signal chanx[1][0]_midout[91] density = 0, probability=0.***** -Vchanx[1][0]_midout[91] chanx[1][0]_midout[91] 0 -+ 0 -***** Signal chanx[1][0]_midout[92] density = 0, probability=0.***** -Vchanx[1][0]_midout[92] chanx[1][0]_midout[92] 0 -+ 0 -***** Signal chanx[1][0]_midout[93] density = 0, probability=0.***** -Vchanx[1][0]_midout[93] chanx[1][0]_midout[93] 0 -+ 0 -***** Signal chanx[1][0]_midout[94] density = 0, probability=0.***** -Vchanx[1][0]_midout[94] chanx[1][0]_midout[94] 0 -+ 0 -***** Signal chanx[1][0]_midout[95] density = 0, probability=0.***** -Vchanx[1][0]_midout[95] chanx[1][0]_midout[95] 0 -+ 0 -***** Signal chanx[1][0]_midout[96] density = 0, probability=0.***** -Vchanx[1][0]_midout[96] chanx[1][0]_midout[96] 0 -+ 0 -***** Signal chanx[1][0]_midout[97] density = 0, probability=0.***** -Vchanx[1][0]_midout[97] chanx[1][0]_midout[97] 0 -+ 0 -***** Signal chanx[1][0]_midout[98] density = 0, probability=0.***** -Vchanx[1][0]_midout[98] chanx[1][0]_midout[98] 0 -+ 0 -***** Signal chanx[1][0]_midout[99] density = 0, probability=0.***** -Vchanx[1][0]_midout[99] chanx[1][0]_midout[99] 0 -+ 0 -******* Normal TYPE loads ******* -Xload_inv[0]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[4] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[5] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[6] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[7] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[8] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[9] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[10] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[11] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[12] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[13] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[14] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[15] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[16] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[17] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[18] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[19] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[20] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[21] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[22] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[23] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[24] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[25] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[26] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[27] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[28] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[29] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[30] gvdd_load 0 inv size=1 -Xload_inv[31]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[31] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[32] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[33] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[34] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[35] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[36] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[37] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[38] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[39] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[40] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[41] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[42] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[43] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[44] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[45] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[46] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[47] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[48] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[49] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[50] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[51] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[52] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[53] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[54] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[55] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[56] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[57] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[58] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 grid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[60]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[1] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[2] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[3] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[4] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[5] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[6] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[7] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[8] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[9] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[10] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[11] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[12] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[13] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[14] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[15] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[16] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[17] gvdd_load 0 inv size=1 -Xload_inv[78]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[18] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[19] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[20] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[21] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[22] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[23] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[24] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[25] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[26] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[27] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[28] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[29] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[30] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[31] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[32] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[33] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[34] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[35] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[36] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[37] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[38] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[39] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[40] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[41] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[42] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[43] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[44] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[45] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[46] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[47] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[48] gvdd_load 0 inv size=1 -Xload_inv[109]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[49] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[50] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[51] gvdd_load 0 inv size=1 -Xload_inv[112]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[52] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[53] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[54] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[55] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[56] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[57] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[58] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 grid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[120]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[3] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[4] gvdd_load 0 inv size=1 -Xload_inv[125]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[5] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[6] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[7] gvdd_load 0 inv size=1 -Xload_inv[128]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[8] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[9] gvdd_load 0 inv size=1 -Xload_inv[130]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[10] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[11] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[12] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[13] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[14] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[15] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[16] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[17] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[18] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[19] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[20] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[21] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[22] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[23] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[24] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[25] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[26] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[27] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[28] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[29] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[30] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[31] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[32] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[33] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[34] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[35] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[36] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[37] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[38] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[39] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[40] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[41] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[42] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[43] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[44] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[45] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[46] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[47] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[48] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[49] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[50] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[51] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[52] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[53] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[54] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[55] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[56] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[57] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[58] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 grid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[180]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[0] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[1] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[2] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[3] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[4] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[5] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[6] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[7] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[8] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[9] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[10] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[11] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[12] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[13] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[14] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[15] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[16] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[17] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[18] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[19] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[20] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[21] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[22] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[23] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[24] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[25] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[26] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[27] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[28] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[29] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[30] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[31] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[32] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[33] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[34] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[35] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[36] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[37] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[38] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[39] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[40] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[41] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[42] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[43] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[44] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[45] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[46] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[47] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[48] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[49] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[50] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[51] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[52] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[53] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[54] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[55] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[56] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[57] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[58] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 grid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[240]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[0] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[1] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[2] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[3] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[4] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[5] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[6] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[7] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[8] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[9] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[10] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[11] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[12] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[13] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[14] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[15] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[16] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[17] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[18] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[19] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[20] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[21] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[22] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[23] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[24] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[25] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[26] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[27] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[28] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[29] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[30] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[31] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[32] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[33] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[34] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[35] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[36] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[37] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[38] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[39] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[40] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[41] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[42] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[43] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[44] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[45] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[46] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[47] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[48] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[49] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[50] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[51] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[52] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[53] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[54] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[55] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[56] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[57] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[58] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 grid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[300]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[0] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[1] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[2] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[3] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[4] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[5] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[6] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[7] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[8] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[9] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[10] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[11] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[12] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[13] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[14] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[15] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[16] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[17] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[18] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[19] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[20] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[21] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[22] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[23] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[24] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[25] gvdd_load 0 inv size=1 -Xload_inv[326]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[26] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[27] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[28] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[29] gvdd_load 0 inv size=1 -Xload_inv[330]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[30] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[31] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[32] gvdd_load 0 inv size=1 -Xload_inv[333]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[33] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[34] gvdd_load 0 inv size=1 -Xload_inv[335]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[35] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[36] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[37] gvdd_load 0 inv size=1 -Xload_inv[338]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[38] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[39] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[40] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[41] gvdd_load 0 inv size=1 -Xload_inv[342]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[42] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[43] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[44] gvdd_load 0 inv size=1 -Xload_inv[345]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[45] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[46] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[47] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[48] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[49] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[50] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[51] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[52] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[53] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[54] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[55] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[56] gvdd_load 0 inv size=1 -Xload_inv[357]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[57] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[58] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 grid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[360]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[0] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[1] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[2] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[3] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[4] gvdd_load 0 inv size=1 -Xload_inv[365]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[5] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[6] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[7] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[8] gvdd_load 0 inv size=1 -Xload_inv[369]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[9] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[10] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[11] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[12] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[13] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[14] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[15] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[16] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[17] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[18] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[19] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[20] gvdd_load 0 inv size=1 -Xload_inv[381]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[21] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[22] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[23] gvdd_load 0 inv size=1 -Xload_inv[384]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[24] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[25] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[26] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[27] gvdd_load 0 inv size=1 -Xload_inv[388]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[28] gvdd_load 0 inv size=1 -Xload_inv[389]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[29] gvdd_load 0 inv size=1 -Xload_inv[390]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[30] gvdd_load 0 inv size=1 -Xload_inv[391]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[31] gvdd_load 0 inv size=1 -Xload_inv[392]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[32] gvdd_load 0 inv size=1 -Xload_inv[393]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[33] gvdd_load 0 inv size=1 -Xload_inv[394]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[34] gvdd_load 0 inv size=1 -Xload_inv[395]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[35] gvdd_load 0 inv size=1 -Xload_inv[396]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[36] gvdd_load 0 inv size=1 -Xload_inv[397]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[37] gvdd_load 0 inv size=1 -Xload_inv[398]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[38] gvdd_load 0 inv size=1 -Xload_inv[399]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[39] gvdd_load 0 inv size=1 -Xload_inv[400]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[40] gvdd_load 0 inv size=1 -Xload_inv[401]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[41] gvdd_load 0 inv size=1 -Xload_inv[402]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[42] gvdd_load 0 inv size=1 -Xload_inv[403]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[43] gvdd_load 0 inv size=1 -Xload_inv[404]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[44] gvdd_load 0 inv size=1 -Xload_inv[405]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[45] gvdd_load 0 inv size=1 -Xload_inv[406]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[46] gvdd_load 0 inv size=1 -Xload_inv[407]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[47] gvdd_load 0 inv size=1 -Xload_inv[408]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[48] gvdd_load 0 inv size=1 -Xload_inv[409]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[49] gvdd_load 0 inv size=1 -Xload_inv[410]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[50] gvdd_load 0 inv size=1 -Xload_inv[411]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[51] gvdd_load 0 inv size=1 -Xload_inv[412]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[52] gvdd_load 0 inv size=1 -Xload_inv[413]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[53] gvdd_load 0 inv size=1 -Xload_inv[414]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[54] gvdd_load 0 inv size=1 -Xload_inv[415]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[55] gvdd_load 0 inv size=1 -Xload_inv[416]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[56] gvdd_load 0 inv size=1 -Xload_inv[417]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[57] gvdd_load 0 inv size=1 -Xload_inv[418]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[58] gvdd_load 0 inv size=1 -Xload_inv[419]_no0 grid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[420]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[0] gvdd_load 0 inv size=1 -Xload_inv[421]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[1] gvdd_load 0 inv size=1 -Xload_inv[422]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[2] gvdd_load 0 inv size=1 -Xload_inv[423]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[3] gvdd_load 0 inv size=1 -Xload_inv[424]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[4] gvdd_load 0 inv size=1 -Xload_inv[425]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[5] gvdd_load 0 inv size=1 -Xload_inv[426]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[6] gvdd_load 0 inv size=1 -Xload_inv[427]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[7] gvdd_load 0 inv size=1 -Xload_inv[428]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[8] gvdd_load 0 inv size=1 -Xload_inv[429]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[9] gvdd_load 0 inv size=1 -Xload_inv[430]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[10] gvdd_load 0 inv size=1 -Xload_inv[431]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[11] gvdd_load 0 inv size=1 -Xload_inv[432]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[12] gvdd_load 0 inv size=1 -Xload_inv[433]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[13] gvdd_load 0 inv size=1 -Xload_inv[434]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[14] gvdd_load 0 inv size=1 -Xload_inv[435]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[15] gvdd_load 0 inv size=1 -Xload_inv[436]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[16] gvdd_load 0 inv size=1 -Xload_inv[437]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[17] gvdd_load 0 inv size=1 -Xload_inv[438]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[18] gvdd_load 0 inv size=1 -Xload_inv[439]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[19] gvdd_load 0 inv size=1 -Xload_inv[440]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[20] gvdd_load 0 inv size=1 -Xload_inv[441]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[21] gvdd_load 0 inv size=1 -Xload_inv[442]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[22] gvdd_load 0 inv size=1 -Xload_inv[443]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[23] gvdd_load 0 inv size=1 -Xload_inv[444]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[24] gvdd_load 0 inv size=1 -Xload_inv[445]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[25] gvdd_load 0 inv size=1 -Xload_inv[446]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[26] gvdd_load 0 inv size=1 -Xload_inv[447]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[27] gvdd_load 0 inv size=1 -Xload_inv[448]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[28] gvdd_load 0 inv size=1 -Xload_inv[449]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[29] gvdd_load 0 inv size=1 -Xload_inv[450]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[30] gvdd_load 0 inv size=1 -Xload_inv[451]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[31] gvdd_load 0 inv size=1 -Xload_inv[452]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[32] gvdd_load 0 inv size=1 -Xload_inv[453]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[33] gvdd_load 0 inv size=1 -Xload_inv[454]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[34] gvdd_load 0 inv size=1 -Xload_inv[455]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[35] gvdd_load 0 inv size=1 -Xload_inv[456]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[36] gvdd_load 0 inv size=1 -Xload_inv[457]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[37] gvdd_load 0 inv size=1 -Xload_inv[458]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[38] gvdd_load 0 inv size=1 -Xload_inv[459]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[39] gvdd_load 0 inv size=1 -Xload_inv[460]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[40] gvdd_load 0 inv size=1 -Xload_inv[461]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[41] gvdd_load 0 inv size=1 -Xload_inv[462]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[42] gvdd_load 0 inv size=1 -Xload_inv[463]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[43] gvdd_load 0 inv size=1 -Xload_inv[464]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[44] gvdd_load 0 inv size=1 -Xload_inv[465]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[45] gvdd_load 0 inv size=1 -Xload_inv[466]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[46] gvdd_load 0 inv size=1 -Xload_inv[467]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[47] gvdd_load 0 inv size=1 -Xload_inv[468]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[48] gvdd_load 0 inv size=1 -Xload_inv[469]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[49] gvdd_load 0 inv size=1 -Xload_inv[470]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[50] gvdd_load 0 inv size=1 -Xload_inv[471]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[51] gvdd_load 0 inv size=1 -Xload_inv[472]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[52] gvdd_load 0 inv size=1 -Xload_inv[473]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[53] gvdd_load 0 inv size=1 -Xload_inv[474]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[54] gvdd_load 0 inv size=1 -Xload_inv[475]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[55] gvdd_load 0 inv size=1 -Xload_inv[476]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[56] gvdd_load 0 inv size=1 -Xload_inv[477]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[57] gvdd_load 0 inv size=1 -Xload_inv[478]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[58] gvdd_load 0 inv size=1 -Xload_inv[479]_no0 grid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[480]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[0] gvdd_load 0 inv size=1 -Xload_inv[481]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[1] gvdd_load 0 inv size=1 -Xload_inv[482]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[2] gvdd_load 0 inv size=1 -Xload_inv[483]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[3] gvdd_load 0 inv size=1 -Xload_inv[484]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[4] gvdd_load 0 inv size=1 -Xload_inv[485]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[5] gvdd_load 0 inv size=1 -Xload_inv[486]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[6] gvdd_load 0 inv size=1 -Xload_inv[487]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[7] gvdd_load 0 inv size=1 -Xload_inv[488]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[8] gvdd_load 0 inv size=1 -Xload_inv[489]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[9] gvdd_load 0 inv size=1 -Xload_inv[490]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[10] gvdd_load 0 inv size=1 -Xload_inv[491]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[11] gvdd_load 0 inv size=1 -Xload_inv[492]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[12] gvdd_load 0 inv size=1 -Xload_inv[493]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[13] gvdd_load 0 inv size=1 -Xload_inv[494]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[14] gvdd_load 0 inv size=1 -Xload_inv[495]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[15] gvdd_load 0 inv size=1 -Xload_inv[496]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[16] gvdd_load 0 inv size=1 -Xload_inv[497]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[17] gvdd_load 0 inv size=1 -Xload_inv[498]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[18] gvdd_load 0 inv size=1 -Xload_inv[499]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[19] gvdd_load 0 inv size=1 -Xload_inv[500]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[20] gvdd_load 0 inv size=1 -Xload_inv[501]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[21] gvdd_load 0 inv size=1 -Xload_inv[502]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[22] gvdd_load 0 inv size=1 -Xload_inv[503]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[23] gvdd_load 0 inv size=1 -Xload_inv[504]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[24] gvdd_load 0 inv size=1 -Xload_inv[505]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[25] gvdd_load 0 inv size=1 -Xload_inv[506]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[26] gvdd_load 0 inv size=1 -Xload_inv[507]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[27] gvdd_load 0 inv size=1 -Xload_inv[508]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[28] gvdd_load 0 inv size=1 -Xload_inv[509]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[29] gvdd_load 0 inv size=1 -Xload_inv[510]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[30] gvdd_load 0 inv size=1 -Xload_inv[511]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[31] gvdd_load 0 inv size=1 -Xload_inv[512]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[32] gvdd_load 0 inv size=1 -Xload_inv[513]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[33] gvdd_load 0 inv size=1 -Xload_inv[514]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[34] gvdd_load 0 inv size=1 -Xload_inv[515]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[35] gvdd_load 0 inv size=1 -Xload_inv[516]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[36] gvdd_load 0 inv size=1 -Xload_inv[517]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[37] gvdd_load 0 inv size=1 -Xload_inv[518]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[38] gvdd_load 0 inv size=1 -Xload_inv[519]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[39] gvdd_load 0 inv size=1 -Xload_inv[520]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[40] gvdd_load 0 inv size=1 -Xload_inv[521]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[41] gvdd_load 0 inv size=1 -Xload_inv[522]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[42] gvdd_load 0 inv size=1 -Xload_inv[523]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[43] gvdd_load 0 inv size=1 -Xload_inv[524]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[44] gvdd_load 0 inv size=1 -Xload_inv[525]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[45] gvdd_load 0 inv size=1 -Xload_inv[526]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[46] gvdd_load 0 inv size=1 -Xload_inv[527]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[47] gvdd_load 0 inv size=1 -Xload_inv[528]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[48] gvdd_load 0 inv size=1 -Xload_inv[529]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[49] gvdd_load 0 inv size=1 -Xload_inv[530]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[50] gvdd_load 0 inv size=1 -Xload_inv[531]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[51] gvdd_load 0 inv size=1 -Xload_inv[532]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[52] gvdd_load 0 inv size=1 -Xload_inv[533]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[53] gvdd_load 0 inv size=1 -Xload_inv[534]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[54] gvdd_load 0 inv size=1 -Xload_inv[535]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[55] gvdd_load 0 inv size=1 -Xload_inv[536]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[56] gvdd_load 0 inv size=1 -Xload_inv[537]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[57] gvdd_load 0 inv size=1 -Xload_inv[538]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[58] gvdd_load 0 inv size=1 -Xload_inv[539]_no0 grid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[540]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[0] gvdd_load 0 inv size=1 -Xload_inv[541]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[1] gvdd_load 0 inv size=1 -Xload_inv[542]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[2] gvdd_load 0 inv size=1 -Xload_inv[543]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[3] gvdd_load 0 inv size=1 -Xload_inv[544]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[4] gvdd_load 0 inv size=1 -Xload_inv[545]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[5] gvdd_load 0 inv size=1 -Xload_inv[546]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[6] gvdd_load 0 inv size=1 -Xload_inv[547]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[7] gvdd_load 0 inv size=1 -Xload_inv[548]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[8] gvdd_load 0 inv size=1 -Xload_inv[549]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[9] gvdd_load 0 inv size=1 -Xload_inv[550]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[10] gvdd_load 0 inv size=1 -Xload_inv[551]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[11] gvdd_load 0 inv size=1 -Xload_inv[552]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[12] gvdd_load 0 inv size=1 -Xload_inv[553]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[13] gvdd_load 0 inv size=1 -Xload_inv[554]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[14] gvdd_load 0 inv size=1 -Xload_inv[555]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[15] gvdd_load 0 inv size=1 -Xload_inv[556]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[16] gvdd_load 0 inv size=1 -Xload_inv[557]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[17] gvdd_load 0 inv size=1 -Xload_inv[558]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[18] gvdd_load 0 inv size=1 -Xload_inv[559]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[19] gvdd_load 0 inv size=1 -Xload_inv[560]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[20] gvdd_load 0 inv size=1 -Xload_inv[561]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[21] gvdd_load 0 inv size=1 -Xload_inv[562]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[22] gvdd_load 0 inv size=1 -Xload_inv[563]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[23] gvdd_load 0 inv size=1 -Xload_inv[564]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[24] gvdd_load 0 inv size=1 -Xload_inv[565]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[25] gvdd_load 0 inv size=1 -Xload_inv[566]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[26] gvdd_load 0 inv size=1 -Xload_inv[567]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[27] gvdd_load 0 inv size=1 -Xload_inv[568]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[28] gvdd_load 0 inv size=1 -Xload_inv[569]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[29] gvdd_load 0 inv size=1 -Xload_inv[570]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[30] gvdd_load 0 inv size=1 -Xload_inv[571]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[31] gvdd_load 0 inv size=1 -Xload_inv[572]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[32] gvdd_load 0 inv size=1 -Xload_inv[573]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[33] gvdd_load 0 inv size=1 -Xload_inv[574]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[34] gvdd_load 0 inv size=1 -Xload_inv[575]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[35] gvdd_load 0 inv size=1 -Xload_inv[576]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[36] gvdd_load 0 inv size=1 -Xload_inv[577]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[37] gvdd_load 0 inv size=1 -Xload_inv[578]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[38] gvdd_load 0 inv size=1 -Xload_inv[579]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[39] gvdd_load 0 inv size=1 -Xload_inv[580]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[40] gvdd_load 0 inv size=1 -Xload_inv[581]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[41] gvdd_load 0 inv size=1 -Xload_inv[582]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[42] gvdd_load 0 inv size=1 -Xload_inv[583]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[43] gvdd_load 0 inv size=1 -Xload_inv[584]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[44] gvdd_load 0 inv size=1 -Xload_inv[585]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[45] gvdd_load 0 inv size=1 -Xload_inv[586]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[46] gvdd_load 0 inv size=1 -Xload_inv[587]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[47] gvdd_load 0 inv size=1 -Xload_inv[588]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[48] gvdd_load 0 inv size=1 -Xload_inv[589]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[49] gvdd_load 0 inv size=1 -Xload_inv[590]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[50] gvdd_load 0 inv size=1 -Xload_inv[591]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[51] gvdd_load 0 inv size=1 -Xload_inv[592]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[52] gvdd_load 0 inv size=1 -Xload_inv[593]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[53] gvdd_load 0 inv size=1 -Xload_inv[594]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[54] gvdd_load 0 inv size=1 -Xload_inv[595]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[55] gvdd_load 0 inv size=1 -Xload_inv[596]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[56] gvdd_load 0 inv size=1 -Xload_inv[597]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[57] gvdd_load 0 inv size=1 -Xload_inv[598]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[58] gvdd_load 0 inv size=1 -Xload_inv[599]_no0 grid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[600]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[0] gvdd_load 0 inv size=1 -Xload_inv[601]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[1] gvdd_load 0 inv size=1 -Xload_inv[602]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[2] gvdd_load 0 inv size=1 -Xload_inv[603]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[3] gvdd_load 0 inv size=1 -Xload_inv[604]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[4] gvdd_load 0 inv size=1 -Xload_inv[605]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[5] gvdd_load 0 inv size=1 -Xload_inv[606]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[6] gvdd_load 0 inv size=1 -Xload_inv[607]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[7] gvdd_load 0 inv size=1 -Xload_inv[608]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[8] gvdd_load 0 inv size=1 -Xload_inv[609]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[9] gvdd_load 0 inv size=1 -Xload_inv[610]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[10] gvdd_load 0 inv size=1 -Xload_inv[611]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[11] gvdd_load 0 inv size=1 -Xload_inv[612]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[12] gvdd_load 0 inv size=1 -Xload_inv[613]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[13] gvdd_load 0 inv size=1 -Xload_inv[614]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[14] gvdd_load 0 inv size=1 -Xload_inv[615]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[15] gvdd_load 0 inv size=1 -Xload_inv[616]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[16] gvdd_load 0 inv size=1 -Xload_inv[617]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[17] gvdd_load 0 inv size=1 -Xload_inv[618]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[18] gvdd_load 0 inv size=1 -Xload_inv[619]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[19] gvdd_load 0 inv size=1 -Xload_inv[620]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[20] gvdd_load 0 inv size=1 -Xload_inv[621]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[21] gvdd_load 0 inv size=1 -Xload_inv[622]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[22] gvdd_load 0 inv size=1 -Xload_inv[623]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[23] gvdd_load 0 inv size=1 -Xload_inv[624]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[24] gvdd_load 0 inv size=1 -Xload_inv[625]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[25] gvdd_load 0 inv size=1 -Xload_inv[626]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[26] gvdd_load 0 inv size=1 -Xload_inv[627]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[27] gvdd_load 0 inv size=1 -Xload_inv[628]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[28] gvdd_load 0 inv size=1 -Xload_inv[629]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[29] gvdd_load 0 inv size=1 -Xload_inv[630]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[30] gvdd_load 0 inv size=1 -Xload_inv[631]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[31] gvdd_load 0 inv size=1 -Xload_inv[632]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[32] gvdd_load 0 inv size=1 -Xload_inv[633]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[33] gvdd_load 0 inv size=1 -Xload_inv[634]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[34] gvdd_load 0 inv size=1 -Xload_inv[635]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[35] gvdd_load 0 inv size=1 -Xload_inv[636]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[36] gvdd_load 0 inv size=1 -Xload_inv[637]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[37] gvdd_load 0 inv size=1 -Xload_inv[638]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[38] gvdd_load 0 inv size=1 -Xload_inv[639]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[39] gvdd_load 0 inv size=1 -Xload_inv[640]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[40] gvdd_load 0 inv size=1 -Xload_inv[641]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[41] gvdd_load 0 inv size=1 -Xload_inv[642]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[42] gvdd_load 0 inv size=1 -Xload_inv[643]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[43] gvdd_load 0 inv size=1 -Xload_inv[644]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[44] gvdd_load 0 inv size=1 -Xload_inv[645]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[45] gvdd_load 0 inv size=1 -Xload_inv[646]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[46] gvdd_load 0 inv size=1 -Xload_inv[647]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[47] gvdd_load 0 inv size=1 -Xload_inv[648]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[48] gvdd_load 0 inv size=1 -Xload_inv[649]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[49] gvdd_load 0 inv size=1 -Xload_inv[650]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[50] gvdd_load 0 inv size=1 -Xload_inv[651]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[51] gvdd_load 0 inv size=1 -Xload_inv[652]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[52] gvdd_load 0 inv size=1 -Xload_inv[653]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[53] gvdd_load 0 inv size=1 -Xload_inv[654]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[54] gvdd_load 0 inv size=1 -Xload_inv[655]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[55] gvdd_load 0 inv size=1 -Xload_inv[656]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[56] gvdd_load 0 inv size=1 -Xload_inv[657]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[57] gvdd_load 0 inv size=1 -Xload_inv[658]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[58] gvdd_load 0 inv size=1 -Xload_inv[659]_no0 grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -***** Voltage supplies ***** -***** Voltage supplies ***** -Vgvdd_cb[1][0] gvdd_cbx[1][0] 0 vsp -Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_cb avg p(Vgvdd_cb[1][0]) from=0 to='clock_period' -.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_cb avg p(Vgvdd_cb[1][0]) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period' -.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_2/cb_tb/example_2_cbx1_1_cb_testbench.sp b/examples/spice_test_example_2/cb_tb/example_2_cbx1_1_cb_testbench.sp deleted file mode 100644 index 45bbf707e..000000000 --- a/examples/spice_test_example_2/cb_tb/example_2_cbx1_1_cb_testbench.sp +++ /dev/null @@ -1,1182 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_cbs -****** Include subckt netlists: Connection Box X-channel [1][1] ***** -.include './spice_test_example_2/subckt/cbx_1_1.sp' -***** Call defined Connection Box[1][1] ***** -Xcbx[1][1] -+ chanx[1][1]_midout[0] -+ chanx[1][1]_midout[1] -+ chanx[1][1]_midout[2] -+ chanx[1][1]_midout[3] -+ chanx[1][1]_midout[4] -+ chanx[1][1]_midout[5] -+ chanx[1][1]_midout[6] -+ chanx[1][1]_midout[7] -+ chanx[1][1]_midout[8] -+ chanx[1][1]_midout[9] -+ chanx[1][1]_midout[10] -+ chanx[1][1]_midout[11] -+ chanx[1][1]_midout[12] -+ chanx[1][1]_midout[13] -+ chanx[1][1]_midout[14] -+ chanx[1][1]_midout[15] -+ chanx[1][1]_midout[16] -+ chanx[1][1]_midout[17] -+ chanx[1][1]_midout[18] -+ chanx[1][1]_midout[19] -+ chanx[1][1]_midout[20] -+ chanx[1][1]_midout[21] -+ chanx[1][1]_midout[22] -+ chanx[1][1]_midout[23] -+ chanx[1][1]_midout[24] -+ chanx[1][1]_midout[25] -+ chanx[1][1]_midout[26] -+ chanx[1][1]_midout[27] -+ chanx[1][1]_midout[28] -+ chanx[1][1]_midout[29] -+ chanx[1][1]_midout[30] -+ chanx[1][1]_midout[31] -+ chanx[1][1]_midout[32] -+ chanx[1][1]_midout[33] -+ chanx[1][1]_midout[34] -+ chanx[1][1]_midout[35] -+ chanx[1][1]_midout[36] -+ chanx[1][1]_midout[37] -+ chanx[1][1]_midout[38] -+ chanx[1][1]_midout[39] -+ chanx[1][1]_midout[40] -+ chanx[1][1]_midout[41] -+ chanx[1][1]_midout[42] -+ chanx[1][1]_midout[43] -+ chanx[1][1]_midout[44] -+ chanx[1][1]_midout[45] -+ chanx[1][1]_midout[46] -+ chanx[1][1]_midout[47] -+ chanx[1][1]_midout[48] -+ chanx[1][1]_midout[49] -+ chanx[1][1]_midout[50] -+ chanx[1][1]_midout[51] -+ chanx[1][1]_midout[52] -+ chanx[1][1]_midout[53] -+ chanx[1][1]_midout[54] -+ chanx[1][1]_midout[55] -+ chanx[1][1]_midout[56] -+ chanx[1][1]_midout[57] -+ chanx[1][1]_midout[58] -+ chanx[1][1]_midout[59] -+ chanx[1][1]_midout[60] -+ chanx[1][1]_midout[61] -+ chanx[1][1]_midout[62] -+ chanx[1][1]_midout[63] -+ chanx[1][1]_midout[64] -+ chanx[1][1]_midout[65] -+ chanx[1][1]_midout[66] -+ chanx[1][1]_midout[67] -+ chanx[1][1]_midout[68] -+ chanx[1][1]_midout[69] -+ chanx[1][1]_midout[70] -+ chanx[1][1]_midout[71] -+ chanx[1][1]_midout[72] -+ chanx[1][1]_midout[73] -+ chanx[1][1]_midout[74] -+ chanx[1][1]_midout[75] -+ chanx[1][1]_midout[76] -+ chanx[1][1]_midout[77] -+ chanx[1][1]_midout[78] -+ chanx[1][1]_midout[79] -+ chanx[1][1]_midout[80] -+ chanx[1][1]_midout[81] -+ chanx[1][1]_midout[82] -+ chanx[1][1]_midout[83] -+ chanx[1][1]_midout[84] -+ chanx[1][1]_midout[85] -+ chanx[1][1]_midout[86] -+ chanx[1][1]_midout[87] -+ chanx[1][1]_midout[88] -+ chanx[1][1]_midout[89] -+ chanx[1][1]_midout[90] -+ chanx[1][1]_midout[91] -+ chanx[1][1]_midout[92] -+ chanx[1][1]_midout[93] -+ chanx[1][1]_midout[94] -+ chanx[1][1]_midout[95] -+ chanx[1][1]_midout[96] -+ chanx[1][1]_midout[97] -+ chanx[1][1]_midout[98] -+ chanx[1][1]_midout[99] -+ grid[1][2]_pin[0][2][0] -+ grid[1][2]_pin[0][2][2] -+ grid[1][2]_pin[0][2][4] -+ grid[1][2]_pin[0][2][6] -+ grid[1][2]_pin[0][2][8] -+ grid[1][2]_pin[0][2][10] -+ grid[1][2]_pin[0][2][12] -+ grid[1][2]_pin[0][2][14] -+ grid[1][1]_pin[0][0][0] -+ grid[1][1]_pin[0][0][4] -+ grid[1][1]_pin[0][0][8] -+ grid[1][1]_pin[0][0][12] -+ grid[1][1]_pin[0][0][16] -+ grid[1][1]_pin[0][0][20] -+ grid[1][1]_pin[0][0][24] -+ grid[1][1]_pin[0][0][28] -+ grid[1][1]_pin[0][0][32] -+ grid[1][1]_pin[0][0][36] -+ gvdd_cbx[1][1] 0 cbx[1][1] -***** Signal chanx[1][1]_midout[0] density = 0, probability=0.***** -Vchanx[1][1]_midout[0] chanx[1][1]_midout[0] 0 -+ 0 -***** Signal chanx[1][1]_midout[1] density = 0, probability=0.***** -Vchanx[1][1]_midout[1] chanx[1][1]_midout[1] 0 -+ 0 -***** Signal chanx[1][1]_midout[2] density = 0, probability=0.***** -Vchanx[1][1]_midout[2] chanx[1][1]_midout[2] 0 -+ 0 -***** Signal chanx[1][1]_midout[3] density = 0, probability=0.***** -Vchanx[1][1]_midout[3] chanx[1][1]_midout[3] 0 -+ 0 -***** Signal chanx[1][1]_midout[4] density = 0, probability=0.***** -Vchanx[1][1]_midout[4] chanx[1][1]_midout[4] 0 -+ 0 -***** Signal chanx[1][1]_midout[5] density = 0, probability=0.***** -Vchanx[1][1]_midout[5] chanx[1][1]_midout[5] 0 -+ 0 -***** Signal chanx[1][1]_midout[6] density = 0, probability=0.***** -Vchanx[1][1]_midout[6] chanx[1][1]_midout[6] 0 -+ 0 -***** Signal chanx[1][1]_midout[7] density = 0, probability=0.***** -Vchanx[1][1]_midout[7] chanx[1][1]_midout[7] 0 -+ 0 -***** Signal chanx[1][1]_midout[8] density = 0, probability=0.***** -Vchanx[1][1]_midout[8] chanx[1][1]_midout[8] 0 -+ 0 -***** Signal chanx[1][1]_midout[9] density = 0, probability=0.***** -Vchanx[1][1]_midout[9] chanx[1][1]_midout[9] 0 -+ 0 -***** Signal chanx[1][1]_midout[10] density = 0, probability=0.***** -Vchanx[1][1]_midout[10] chanx[1][1]_midout[10] 0 -+ 0 -***** Signal chanx[1][1]_midout[11] density = 0, probability=0.***** -Vchanx[1][1]_midout[11] chanx[1][1]_midout[11] 0 -+ 0 -***** Signal chanx[1][1]_midout[12] density = 0, probability=0.***** -Vchanx[1][1]_midout[12] chanx[1][1]_midout[12] 0 -+ 0 -***** Signal chanx[1][1]_midout[13] density = 0, probability=0.***** -Vchanx[1][1]_midout[13] chanx[1][1]_midout[13] 0 -+ 0 -***** Signal chanx[1][1]_midout[14] density = 0, probability=0.***** -Vchanx[1][1]_midout[14] chanx[1][1]_midout[14] 0 -+ 0 -***** Signal chanx[1][1]_midout[15] density = 0, probability=0.***** -Vchanx[1][1]_midout[15] chanx[1][1]_midout[15] 0 -+ 0 -***** Signal chanx[1][1]_midout[16] density = 0, probability=0.***** -Vchanx[1][1]_midout[16] chanx[1][1]_midout[16] 0 -+ 0 -***** Signal chanx[1][1]_midout[17] density = 0, probability=0.***** -Vchanx[1][1]_midout[17] chanx[1][1]_midout[17] 0 -+ 0 -***** Signal chanx[1][1]_midout[18] density = 0, probability=0.***** -Vchanx[1][1]_midout[18] chanx[1][1]_midout[18] 0 -+ 0 -***** Signal chanx[1][1]_midout[19] density = 0, probability=0.***** -Vchanx[1][1]_midout[19] chanx[1][1]_midout[19] 0 -+ 0 -***** Signal chanx[1][1]_midout[20] density = 0.2026, probability=0.4982.***** -Vchanx[1][1]_midout[20] chanx[1][1]_midout[20] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chanx[1][1]_midout[21] density = 0, probability=0.***** -Vchanx[1][1]_midout[21] chanx[1][1]_midout[21] 0 -+ 0 -***** Signal chanx[1][1]_midout[22] density = 0, probability=0.***** -Vchanx[1][1]_midout[22] chanx[1][1]_midout[22] 0 -+ 0 -***** Signal chanx[1][1]_midout[23] density = 0, probability=0.***** -Vchanx[1][1]_midout[23] chanx[1][1]_midout[23] 0 -+ 0 -***** Signal chanx[1][1]_midout[24] density = 0, probability=0.***** -Vchanx[1][1]_midout[24] chanx[1][1]_midout[24] 0 -+ 0 -***** Signal chanx[1][1]_midout[25] density = 0, probability=0.***** -Vchanx[1][1]_midout[25] chanx[1][1]_midout[25] 0 -+ 0 -***** Signal chanx[1][1]_midout[26] density = 0, probability=0.***** -Vchanx[1][1]_midout[26] chanx[1][1]_midout[26] 0 -+ 0 -***** Signal chanx[1][1]_midout[27] density = 0, probability=0.***** -Vchanx[1][1]_midout[27] chanx[1][1]_midout[27] 0 -+ 0 -***** Signal chanx[1][1]_midout[28] density = 0, probability=0.***** -Vchanx[1][1]_midout[28] chanx[1][1]_midout[28] 0 -+ 0 -***** Signal chanx[1][1]_midout[29] density = 0, probability=0.***** -Vchanx[1][1]_midout[29] chanx[1][1]_midout[29] 0 -+ 0 -***** Signal chanx[1][1]_midout[30] density = 0, probability=0.***** -Vchanx[1][1]_midout[30] chanx[1][1]_midout[30] 0 -+ 0 -***** Signal chanx[1][1]_midout[31] density = 0, probability=0.***** -Vchanx[1][1]_midout[31] chanx[1][1]_midout[31] 0 -+ 0 -***** Signal chanx[1][1]_midout[32] density = 0, probability=0.***** -Vchanx[1][1]_midout[32] chanx[1][1]_midout[32] 0 -+ 0 -***** Signal chanx[1][1]_midout[33] density = 0, probability=0.***** -Vchanx[1][1]_midout[33] chanx[1][1]_midout[33] 0 -+ 0 -***** Signal chanx[1][1]_midout[34] density = 0, probability=0.***** -Vchanx[1][1]_midout[34] chanx[1][1]_midout[34] 0 -+ 0 -***** Signal chanx[1][1]_midout[35] density = 0, probability=0.***** -Vchanx[1][1]_midout[35] chanx[1][1]_midout[35] 0 -+ 0 -***** Signal chanx[1][1]_midout[36] density = 0, probability=0.***** -Vchanx[1][1]_midout[36] chanx[1][1]_midout[36] 0 -+ 0 -***** Signal chanx[1][1]_midout[37] density = 0, probability=0.***** -Vchanx[1][1]_midout[37] chanx[1][1]_midout[37] 0 -+ 0 -***** Signal chanx[1][1]_midout[38] density = 0, probability=0.***** -Vchanx[1][1]_midout[38] chanx[1][1]_midout[38] 0 -+ 0 -***** Signal chanx[1][1]_midout[39] density = 0, probability=0.***** -Vchanx[1][1]_midout[39] chanx[1][1]_midout[39] 0 -+ 0 -***** Signal chanx[1][1]_midout[40] density = 0, probability=0.***** -Vchanx[1][1]_midout[40] chanx[1][1]_midout[40] 0 -+ 0 -***** Signal chanx[1][1]_midout[41] density = 0, probability=0.***** -Vchanx[1][1]_midout[41] chanx[1][1]_midout[41] 0 -+ 0 -***** Signal chanx[1][1]_midout[42] density = 0, probability=0.***** -Vchanx[1][1]_midout[42] chanx[1][1]_midout[42] 0 -+ 0 -***** Signal chanx[1][1]_midout[43] density = 0, probability=0.***** -Vchanx[1][1]_midout[43] chanx[1][1]_midout[43] 0 -+ 0 -***** Signal chanx[1][1]_midout[44] density = 0, probability=0.***** -Vchanx[1][1]_midout[44] chanx[1][1]_midout[44] 0 -+ 0 -***** Signal chanx[1][1]_midout[45] density = 0, probability=0.***** -Vchanx[1][1]_midout[45] chanx[1][1]_midout[45] 0 -+ 0 -***** Signal chanx[1][1]_midout[46] density = 0, probability=0.***** -Vchanx[1][1]_midout[46] chanx[1][1]_midout[46] 0 -+ 0 -***** Signal chanx[1][1]_midout[47] density = 0, probability=0.***** -Vchanx[1][1]_midout[47] chanx[1][1]_midout[47] 0 -+ 0 -***** Signal chanx[1][1]_midout[48] density = 0, probability=0.***** -Vchanx[1][1]_midout[48] chanx[1][1]_midout[48] 0 -+ 0 -***** Signal chanx[1][1]_midout[49] density = 0, probability=0.***** -Vchanx[1][1]_midout[49] chanx[1][1]_midout[49] 0 -+ 0 -***** Signal chanx[1][1]_midout[50] density = 0, probability=0.***** -Vchanx[1][1]_midout[50] chanx[1][1]_midout[50] 0 -+ 0 -***** Signal chanx[1][1]_midout[51] density = 0, probability=0.***** -Vchanx[1][1]_midout[51] chanx[1][1]_midout[51] 0 -+ 0 -***** Signal chanx[1][1]_midout[52] density = 0, probability=0.***** -Vchanx[1][1]_midout[52] chanx[1][1]_midout[52] 0 -+ 0 -***** Signal chanx[1][1]_midout[53] density = 0, probability=0.***** -Vchanx[1][1]_midout[53] chanx[1][1]_midout[53] 0 -+ 0 -***** Signal chanx[1][1]_midout[54] density = 0, probability=0.***** -Vchanx[1][1]_midout[54] chanx[1][1]_midout[54] 0 -+ 0 -***** Signal chanx[1][1]_midout[55] density = 0, probability=0.***** -Vchanx[1][1]_midout[55] chanx[1][1]_midout[55] 0 -+ 0 -***** Signal chanx[1][1]_midout[56] density = 0, probability=0.***** -Vchanx[1][1]_midout[56] chanx[1][1]_midout[56] 0 -+ 0 -***** Signal chanx[1][1]_midout[57] density = 0, probability=0.***** -Vchanx[1][1]_midout[57] chanx[1][1]_midout[57] 0 -+ 0 -***** Signal chanx[1][1]_midout[58] density = 0, probability=0.***** -Vchanx[1][1]_midout[58] chanx[1][1]_midout[58] 0 -+ 0 -***** Signal chanx[1][1]_midout[59] density = 0, probability=0.***** -Vchanx[1][1]_midout[59] chanx[1][1]_midout[59] 0 -+ 0 -***** Signal chanx[1][1]_midout[60] density = 0, probability=0.***** -Vchanx[1][1]_midout[60] chanx[1][1]_midout[60] 0 -+ 0 -***** Signal chanx[1][1]_midout[61] density = 0, probability=0.***** -Vchanx[1][1]_midout[61] chanx[1][1]_midout[61] 0 -+ 0 -***** Signal chanx[1][1]_midout[62] density = 0, probability=0.***** -Vchanx[1][1]_midout[62] chanx[1][1]_midout[62] 0 -+ 0 -***** Signal chanx[1][1]_midout[63] density = 0, probability=0.***** -Vchanx[1][1]_midout[63] chanx[1][1]_midout[63] 0 -+ 0 -***** Signal chanx[1][1]_midout[64] density = 0, probability=0.***** -Vchanx[1][1]_midout[64] chanx[1][1]_midout[64] 0 -+ 0 -***** Signal chanx[1][1]_midout[65] density = 0, probability=0.***** -Vchanx[1][1]_midout[65] chanx[1][1]_midout[65] 0 -+ 0 -***** Signal chanx[1][1]_midout[66] density = 0, probability=0.***** -Vchanx[1][1]_midout[66] chanx[1][1]_midout[66] 0 -+ 0 -***** Signal chanx[1][1]_midout[67] density = 0, probability=0.***** -Vchanx[1][1]_midout[67] chanx[1][1]_midout[67] 0 -+ 0 -***** Signal chanx[1][1]_midout[68] density = 0, probability=0.***** -Vchanx[1][1]_midout[68] chanx[1][1]_midout[68] 0 -+ 0 -***** Signal chanx[1][1]_midout[69] density = 0, probability=0.***** -Vchanx[1][1]_midout[69] chanx[1][1]_midout[69] 0 -+ 0 -***** Signal chanx[1][1]_midout[70] density = 0, probability=0.***** -Vchanx[1][1]_midout[70] chanx[1][1]_midout[70] 0 -+ 0 -***** Signal chanx[1][1]_midout[71] density = 0, probability=0.***** -Vchanx[1][1]_midout[71] chanx[1][1]_midout[71] 0 -+ 0 -***** Signal chanx[1][1]_midout[72] density = 0, probability=0.***** -Vchanx[1][1]_midout[72] chanx[1][1]_midout[72] 0 -+ 0 -***** Signal chanx[1][1]_midout[73] density = 0, probability=0.***** -Vchanx[1][1]_midout[73] chanx[1][1]_midout[73] 0 -+ 0 -***** Signal chanx[1][1]_midout[74] density = 0, probability=0.***** -Vchanx[1][1]_midout[74] chanx[1][1]_midout[74] 0 -+ 0 -***** Signal chanx[1][1]_midout[75] density = 0, probability=0.***** -Vchanx[1][1]_midout[75] chanx[1][1]_midout[75] 0 -+ 0 -***** Signal chanx[1][1]_midout[76] density = 0, probability=0.***** -Vchanx[1][1]_midout[76] chanx[1][1]_midout[76] 0 -+ 0 -***** Signal chanx[1][1]_midout[77] density = 0, probability=0.***** -Vchanx[1][1]_midout[77] chanx[1][1]_midout[77] 0 -+ 0 -***** Signal chanx[1][1]_midout[78] density = 0, probability=0.***** -Vchanx[1][1]_midout[78] chanx[1][1]_midout[78] 0 -+ 0 -***** Signal chanx[1][1]_midout[79] density = 0, probability=0.***** -Vchanx[1][1]_midout[79] chanx[1][1]_midout[79] 0 -+ 0 -***** Signal chanx[1][1]_midout[80] density = 0, probability=0.***** -Vchanx[1][1]_midout[80] chanx[1][1]_midout[80] 0 -+ 0 -***** Signal chanx[1][1]_midout[81] density = 0, probability=0.***** -Vchanx[1][1]_midout[81] chanx[1][1]_midout[81] 0 -+ 0 -***** Signal chanx[1][1]_midout[82] density = 0, probability=0.***** -Vchanx[1][1]_midout[82] chanx[1][1]_midout[82] 0 -+ 0 -***** Signal chanx[1][1]_midout[83] density = 0, probability=0.***** -Vchanx[1][1]_midout[83] chanx[1][1]_midout[83] 0 -+ 0 -***** Signal chanx[1][1]_midout[84] density = 0, probability=0.***** -Vchanx[1][1]_midout[84] chanx[1][1]_midout[84] 0 -+ 0 -***** Signal chanx[1][1]_midout[85] density = 0, probability=0.***** -Vchanx[1][1]_midout[85] chanx[1][1]_midout[85] 0 -+ 0 -***** Signal chanx[1][1]_midout[86] density = 0, probability=0.***** -Vchanx[1][1]_midout[86] chanx[1][1]_midout[86] 0 -+ 0 -***** Signal chanx[1][1]_midout[87] density = 0, probability=0.***** -Vchanx[1][1]_midout[87] chanx[1][1]_midout[87] 0 -+ 0 -***** Signal chanx[1][1]_midout[88] density = 0, probability=0.***** -Vchanx[1][1]_midout[88] chanx[1][1]_midout[88] 0 -+ 0 -***** Signal chanx[1][1]_midout[89] density = 0, probability=0.***** -Vchanx[1][1]_midout[89] chanx[1][1]_midout[89] 0 -+ 0 -***** Signal chanx[1][1]_midout[90] density = 0, probability=0.***** -Vchanx[1][1]_midout[90] chanx[1][1]_midout[90] 0 -+ 0 -***** Signal chanx[1][1]_midout[91] density = 0, probability=0.***** -Vchanx[1][1]_midout[91] chanx[1][1]_midout[91] 0 -+ 0 -***** Signal chanx[1][1]_midout[92] density = 0, probability=0.***** -Vchanx[1][1]_midout[92] chanx[1][1]_midout[92] 0 -+ 0 -***** Signal chanx[1][1]_midout[93] density = 0, probability=0.***** -Vchanx[1][1]_midout[93] chanx[1][1]_midout[93] 0 -+ 0 -***** Signal chanx[1][1]_midout[94] density = 0, probability=0.***** -Vchanx[1][1]_midout[94] chanx[1][1]_midout[94] 0 -+ 0 -***** Signal chanx[1][1]_midout[95] density = 0, probability=0.***** -Vchanx[1][1]_midout[95] chanx[1][1]_midout[95] 0 -+ 0 -***** Signal chanx[1][1]_midout[96] density = 0, probability=0.***** -Vchanx[1][1]_midout[96] chanx[1][1]_midout[96] 0 -+ 0 -***** Signal chanx[1][1]_midout[97] density = 0, probability=0.***** -Vchanx[1][1]_midout[97] chanx[1][1]_midout[97] 0 -+ 0 -***** Signal chanx[1][1]_midout[98] density = 0, probability=0.***** -Vchanx[1][1]_midout[98] chanx[1][1]_midout[98] 0 -+ 0 -***** Signal chanx[1][1]_midout[99] density = 0, probability=0.***** -Vchanx[1][1]_midout[99] chanx[1][1]_midout[99] 0 -+ 0 -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[0]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[4] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[5] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[6] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[7] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[8] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[9] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[10] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[11] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[12] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[13] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[14] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[15] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[16] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[17] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[18] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[19] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[20] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[21] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[22] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[23] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[24] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[25] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[26] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[27] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[28] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[29] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[30] gvdd_load 0 inv size=1 -Xload_inv[31]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[31] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[32] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[33] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[34] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[35] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[36] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[37] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[38] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[39] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[40] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[41] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[42] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[43] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[44] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[45] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[46] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[47] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[48] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[49] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[50] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[51] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[52] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[53] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[54] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[55] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[56] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[57] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[58] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 grid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[60]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[1] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[2] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[3] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[4] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[5] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[6] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[7] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[8] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[9] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[10] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[11] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[12] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[13] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[14] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[15] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[16] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[17] gvdd_load 0 inv size=1 -Xload_inv[78]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[18] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[19] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[20] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[21] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[22] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[23] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[24] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[25] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[26] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[27] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[28] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[29] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[30] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[31] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[32] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[33] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[34] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[35] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[36] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[37] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[38] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[39] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[40] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[41] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[42] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[43] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[44] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[45] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[46] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[47] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[48] gvdd_load 0 inv size=1 -Xload_inv[109]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[49] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[50] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[51] gvdd_load 0 inv size=1 -Xload_inv[112]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[52] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[53] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[54] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[55] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[56] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[57] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[58] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 grid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[120]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[3] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[4] gvdd_load 0 inv size=1 -Xload_inv[125]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[5] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[6] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[7] gvdd_load 0 inv size=1 -Xload_inv[128]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[8] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[9] gvdd_load 0 inv size=1 -Xload_inv[130]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[10] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[11] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[12] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[13] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[14] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[15] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[16] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[17] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[18] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[19] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[20] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[21] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[22] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[23] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[24] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[25] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[26] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[27] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[28] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[29] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[30] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[31] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[32] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[33] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[34] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[35] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[36] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[37] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[38] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[39] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[40] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[41] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[42] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[43] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[44] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[45] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[46] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[47] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[48] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[49] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[50] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[51] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[52] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[53] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[54] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[55] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[56] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[57] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[58] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 grid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[180]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[0] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[1] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[2] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[3] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[4] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[5] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[6] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[7] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[8] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[9] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[10] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[11] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[12] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[13] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[14] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[15] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[16] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[17] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[18] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[19] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[20] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[21] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[22] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[23] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[24] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[25] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[26] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[27] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[28] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[29] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[30] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[31] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[32] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[33] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[34] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[35] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[36] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[37] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[38] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[39] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[40] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[41] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[42] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[43] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[44] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[45] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[46] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[47] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[48] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[49] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[50] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[51] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[52] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[53] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[54] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[55] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[56] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[57] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[58] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 grid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[240]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[0] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[1] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[2] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[3] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[4] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[5] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[6] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[7] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[8] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[9] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[10] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[11] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[12] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[13] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[14] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[15] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[16] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[17] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[18] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[19] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[20] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[21] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[22] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[23] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[24] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[25] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[26] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[27] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[28] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[29] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[30] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[31] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[32] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[33] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[34] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[35] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[36] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[37] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[38] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[39] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[40] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[41] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[42] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[43] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[44] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[45] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[46] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[47] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[48] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[49] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[50] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[51] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[52] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[53] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[54] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[55] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[56] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[57] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[58] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 grid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[300]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[0] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[1] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[2] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[3] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[4] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[5] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[6] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[7] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[8] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[9] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[10] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[11] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[12] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[13] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[14] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[15] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[16] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[17] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[18] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[19] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[20] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[21] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[22] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[23] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[24] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[25] gvdd_load 0 inv size=1 -Xload_inv[326]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[26] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[27] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[28] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[29] gvdd_load 0 inv size=1 -Xload_inv[330]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[30] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[31] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[32] gvdd_load 0 inv size=1 -Xload_inv[333]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[33] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[34] gvdd_load 0 inv size=1 -Xload_inv[335]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[35] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[36] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[37] gvdd_load 0 inv size=1 -Xload_inv[338]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[38] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[39] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[40] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[41] gvdd_load 0 inv size=1 -Xload_inv[342]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[42] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[43] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[44] gvdd_load 0 inv size=1 -Xload_inv[345]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[45] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[46] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[47] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[48] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[49] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[50] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[51] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[52] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[53] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[54] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[55] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[56] gvdd_load 0 inv size=1 -Xload_inv[357]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[57] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[58] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 grid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[360]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[0] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[1] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[2] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[3] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[4] gvdd_load 0 inv size=1 -Xload_inv[365]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[5] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[6] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[7] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[8] gvdd_load 0 inv size=1 -Xload_inv[369]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[9] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[10] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[11] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[12] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[13] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[14] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[15] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[16] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[17] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[18] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[19] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[20] gvdd_load 0 inv size=1 -Xload_inv[381]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[21] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[22] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[23] gvdd_load 0 inv size=1 -Xload_inv[384]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[24] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[25] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[26] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[27] gvdd_load 0 inv size=1 -Xload_inv[388]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[28] gvdd_load 0 inv size=1 -Xload_inv[389]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[29] gvdd_load 0 inv size=1 -Xload_inv[390]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[30] gvdd_load 0 inv size=1 -Xload_inv[391]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[31] gvdd_load 0 inv size=1 -Xload_inv[392]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[32] gvdd_load 0 inv size=1 -Xload_inv[393]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[33] gvdd_load 0 inv size=1 -Xload_inv[394]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[34] gvdd_load 0 inv size=1 -Xload_inv[395]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[35] gvdd_load 0 inv size=1 -Xload_inv[396]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[36] gvdd_load 0 inv size=1 -Xload_inv[397]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[37] gvdd_load 0 inv size=1 -Xload_inv[398]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[38] gvdd_load 0 inv size=1 -Xload_inv[399]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[39] gvdd_load 0 inv size=1 -Xload_inv[400]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[40] gvdd_load 0 inv size=1 -Xload_inv[401]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[41] gvdd_load 0 inv size=1 -Xload_inv[402]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[42] gvdd_load 0 inv size=1 -Xload_inv[403]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[43] gvdd_load 0 inv size=1 -Xload_inv[404]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[44] gvdd_load 0 inv size=1 -Xload_inv[405]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[45] gvdd_load 0 inv size=1 -Xload_inv[406]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[46] gvdd_load 0 inv size=1 -Xload_inv[407]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[47] gvdd_load 0 inv size=1 -Xload_inv[408]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[48] gvdd_load 0 inv size=1 -Xload_inv[409]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[49] gvdd_load 0 inv size=1 -Xload_inv[410]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[50] gvdd_load 0 inv size=1 -Xload_inv[411]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[51] gvdd_load 0 inv size=1 -Xload_inv[412]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[52] gvdd_load 0 inv size=1 -Xload_inv[413]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[53] gvdd_load 0 inv size=1 -Xload_inv[414]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[54] gvdd_load 0 inv size=1 -Xload_inv[415]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[55] gvdd_load 0 inv size=1 -Xload_inv[416]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[56] gvdd_load 0 inv size=1 -Xload_inv[417]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[57] gvdd_load 0 inv size=1 -Xload_inv[418]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[58] gvdd_load 0 inv size=1 -Xload_inv[419]_no0 grid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[420]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[0] gvdd_load 0 inv size=1 -Xload_inv[421]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[1] gvdd_load 0 inv size=1 -Xload_inv[422]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[2] gvdd_load 0 inv size=1 -Xload_inv[423]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[3] gvdd_load 0 inv size=1 -Xload_inv[424]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[4] gvdd_load 0 inv size=1 -Xload_inv[425]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[5] gvdd_load 0 inv size=1 -Xload_inv[426]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[6] gvdd_load 0 inv size=1 -Xload_inv[427]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[7] gvdd_load 0 inv size=1 -Xload_inv[428]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[8] gvdd_load 0 inv size=1 -Xload_inv[429]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[9] gvdd_load 0 inv size=1 -Xload_inv[430]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[10] gvdd_load 0 inv size=1 -Xload_inv[431]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[11] gvdd_load 0 inv size=1 -Xload_inv[432]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[12] gvdd_load 0 inv size=1 -Xload_inv[433]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[13] gvdd_load 0 inv size=1 -Xload_inv[434]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[14] gvdd_load 0 inv size=1 -Xload_inv[435]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[15] gvdd_load 0 inv size=1 -Xload_inv[436]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[16] gvdd_load 0 inv size=1 -Xload_inv[437]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[17] gvdd_load 0 inv size=1 -Xload_inv[438]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[18] gvdd_load 0 inv size=1 -Xload_inv[439]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[19] gvdd_load 0 inv size=1 -Xload_inv[440]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[20] gvdd_load 0 inv size=1 -Xload_inv[441]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[21] gvdd_load 0 inv size=1 -Xload_inv[442]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[22] gvdd_load 0 inv size=1 -Xload_inv[443]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[23] gvdd_load 0 inv size=1 -Xload_inv[444]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[24] gvdd_load 0 inv size=1 -Xload_inv[445]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[25] gvdd_load 0 inv size=1 -Xload_inv[446]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[26] gvdd_load 0 inv size=1 -Xload_inv[447]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[27] gvdd_load 0 inv size=1 -Xload_inv[448]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[28] gvdd_load 0 inv size=1 -Xload_inv[449]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[29] gvdd_load 0 inv size=1 -Xload_inv[450]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[30] gvdd_load 0 inv size=1 -Xload_inv[451]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[31] gvdd_load 0 inv size=1 -Xload_inv[452]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[32] gvdd_load 0 inv size=1 -Xload_inv[453]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[33] gvdd_load 0 inv size=1 -Xload_inv[454]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[34] gvdd_load 0 inv size=1 -Xload_inv[455]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[35] gvdd_load 0 inv size=1 -Xload_inv[456]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[36] gvdd_load 0 inv size=1 -Xload_inv[457]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[37] gvdd_load 0 inv size=1 -Xload_inv[458]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[38] gvdd_load 0 inv size=1 -Xload_inv[459]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[39] gvdd_load 0 inv size=1 -Xload_inv[460]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[40] gvdd_load 0 inv size=1 -Xload_inv[461]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[41] gvdd_load 0 inv size=1 -Xload_inv[462]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[42] gvdd_load 0 inv size=1 -Xload_inv[463]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[43] gvdd_load 0 inv size=1 -Xload_inv[464]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[44] gvdd_load 0 inv size=1 -Xload_inv[465]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[45] gvdd_load 0 inv size=1 -Xload_inv[466]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[46] gvdd_load 0 inv size=1 -Xload_inv[467]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[47] gvdd_load 0 inv size=1 -Xload_inv[468]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[48] gvdd_load 0 inv size=1 -Xload_inv[469]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[49] gvdd_load 0 inv size=1 -Xload_inv[470]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[50] gvdd_load 0 inv size=1 -Xload_inv[471]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[51] gvdd_load 0 inv size=1 -Xload_inv[472]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[52] gvdd_load 0 inv size=1 -Xload_inv[473]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[53] gvdd_load 0 inv size=1 -Xload_inv[474]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[54] gvdd_load 0 inv size=1 -Xload_inv[475]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[55] gvdd_load 0 inv size=1 -Xload_inv[476]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[56] gvdd_load 0 inv size=1 -Xload_inv[477]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[57] gvdd_load 0 inv size=1 -Xload_inv[478]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[58] gvdd_load 0 inv size=1 -Xload_inv[479]_no0 grid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[480]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[0] gvdd_load 0 inv size=1 -Xload_inv[481]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[1] gvdd_load 0 inv size=1 -Xload_inv[482]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[2] gvdd_load 0 inv size=1 -Xload_inv[483]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[3] gvdd_load 0 inv size=1 -Xload_inv[484]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[4] gvdd_load 0 inv size=1 -Xload_inv[485]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[5] gvdd_load 0 inv size=1 -Xload_inv[486]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[6] gvdd_load 0 inv size=1 -Xload_inv[487]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[7] gvdd_load 0 inv size=1 -Xload_inv[488]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[8] gvdd_load 0 inv size=1 -Xload_inv[489]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[9] gvdd_load 0 inv size=1 -Xload_inv[490]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[10] gvdd_load 0 inv size=1 -Xload_inv[491]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[11] gvdd_load 0 inv size=1 -Xload_inv[492]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[12] gvdd_load 0 inv size=1 -Xload_inv[493]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[13] gvdd_load 0 inv size=1 -Xload_inv[494]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[14] gvdd_load 0 inv size=1 -Xload_inv[495]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[15] gvdd_load 0 inv size=1 -Xload_inv[496]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[16] gvdd_load 0 inv size=1 -Xload_inv[497]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[17] gvdd_load 0 inv size=1 -Xload_inv[498]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[18] gvdd_load 0 inv size=1 -Xload_inv[499]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[19] gvdd_load 0 inv size=1 -Xload_inv[500]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[20] gvdd_load 0 inv size=1 -Xload_inv[501]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[21] gvdd_load 0 inv size=1 -Xload_inv[502]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[22] gvdd_load 0 inv size=1 -Xload_inv[503]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[23] gvdd_load 0 inv size=1 -Xload_inv[504]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[24] gvdd_load 0 inv size=1 -Xload_inv[505]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[25] gvdd_load 0 inv size=1 -Xload_inv[506]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[26] gvdd_load 0 inv size=1 -Xload_inv[507]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[27] gvdd_load 0 inv size=1 -Xload_inv[508]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[28] gvdd_load 0 inv size=1 -Xload_inv[509]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[29] gvdd_load 0 inv size=1 -Xload_inv[510]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[30] gvdd_load 0 inv size=1 -Xload_inv[511]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[31] gvdd_load 0 inv size=1 -Xload_inv[512]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[32] gvdd_load 0 inv size=1 -Xload_inv[513]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[33] gvdd_load 0 inv size=1 -Xload_inv[514]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[34] gvdd_load 0 inv size=1 -Xload_inv[515]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[35] gvdd_load 0 inv size=1 -Xload_inv[516]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[36] gvdd_load 0 inv size=1 -Xload_inv[517]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[37] gvdd_load 0 inv size=1 -Xload_inv[518]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[38] gvdd_load 0 inv size=1 -Xload_inv[519]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[39] gvdd_load 0 inv size=1 -Xload_inv[520]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[40] gvdd_load 0 inv size=1 -Xload_inv[521]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[41] gvdd_load 0 inv size=1 -Xload_inv[522]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[42] gvdd_load 0 inv size=1 -Xload_inv[523]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[43] gvdd_load 0 inv size=1 -Xload_inv[524]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[44] gvdd_load 0 inv size=1 -Xload_inv[525]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[45] gvdd_load 0 inv size=1 -Xload_inv[526]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[46] gvdd_load 0 inv size=1 -Xload_inv[527]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[47] gvdd_load 0 inv size=1 -Xload_inv[528]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[48] gvdd_load 0 inv size=1 -Xload_inv[529]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[49] gvdd_load 0 inv size=1 -Xload_inv[530]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[50] gvdd_load 0 inv size=1 -Xload_inv[531]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[51] gvdd_load 0 inv size=1 -Xload_inv[532]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[52] gvdd_load 0 inv size=1 -Xload_inv[533]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[53] gvdd_load 0 inv size=1 -Xload_inv[534]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[54] gvdd_load 0 inv size=1 -Xload_inv[535]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[55] gvdd_load 0 inv size=1 -Xload_inv[536]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[56] gvdd_load 0 inv size=1 -Xload_inv[537]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[57] gvdd_load 0 inv size=1 -Xload_inv[538]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[58] gvdd_load 0 inv size=1 -Xload_inv[539]_no0 grid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[540]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[0] gvdd_load 0 inv size=1 -Xload_inv[541]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[1] gvdd_load 0 inv size=1 -Xload_inv[542]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[2] gvdd_load 0 inv size=1 -Xload_inv[543]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[3] gvdd_load 0 inv size=1 -Xload_inv[544]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[4] gvdd_load 0 inv size=1 -Xload_inv[545]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[5] gvdd_load 0 inv size=1 -Xload_inv[546]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[6] gvdd_load 0 inv size=1 -Xload_inv[547]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[7] gvdd_load 0 inv size=1 -Xload_inv[548]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[8] gvdd_load 0 inv size=1 -Xload_inv[549]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[9] gvdd_load 0 inv size=1 -Xload_inv[550]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[10] gvdd_load 0 inv size=1 -Xload_inv[551]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[11] gvdd_load 0 inv size=1 -Xload_inv[552]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[12] gvdd_load 0 inv size=1 -Xload_inv[553]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[13] gvdd_load 0 inv size=1 -Xload_inv[554]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[14] gvdd_load 0 inv size=1 -Xload_inv[555]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[15] gvdd_load 0 inv size=1 -Xload_inv[556]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[16] gvdd_load 0 inv size=1 -Xload_inv[557]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[17] gvdd_load 0 inv size=1 -Xload_inv[558]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[18] gvdd_load 0 inv size=1 -Xload_inv[559]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[19] gvdd_load 0 inv size=1 -Xload_inv[560]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[20] gvdd_load 0 inv size=1 -Xload_inv[561]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[21] gvdd_load 0 inv size=1 -Xload_inv[562]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[22] gvdd_load 0 inv size=1 -Xload_inv[563]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[23] gvdd_load 0 inv size=1 -Xload_inv[564]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[24] gvdd_load 0 inv size=1 -Xload_inv[565]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[25] gvdd_load 0 inv size=1 -Xload_inv[566]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[26] gvdd_load 0 inv size=1 -Xload_inv[567]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[27] gvdd_load 0 inv size=1 -Xload_inv[568]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[28] gvdd_load 0 inv size=1 -Xload_inv[569]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[29] gvdd_load 0 inv size=1 -Xload_inv[570]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[30] gvdd_load 0 inv size=1 -Xload_inv[571]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[31] gvdd_load 0 inv size=1 -Xload_inv[572]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[32] gvdd_load 0 inv size=1 -Xload_inv[573]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[33] gvdd_load 0 inv size=1 -Xload_inv[574]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[34] gvdd_load 0 inv size=1 -Xload_inv[575]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[35] gvdd_load 0 inv size=1 -Xload_inv[576]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[36] gvdd_load 0 inv size=1 -Xload_inv[577]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[37] gvdd_load 0 inv size=1 -Xload_inv[578]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[38] gvdd_load 0 inv size=1 -Xload_inv[579]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[39] gvdd_load 0 inv size=1 -Xload_inv[580]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[40] gvdd_load 0 inv size=1 -Xload_inv[581]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[41] gvdd_load 0 inv size=1 -Xload_inv[582]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[42] gvdd_load 0 inv size=1 -Xload_inv[583]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[43] gvdd_load 0 inv size=1 -Xload_inv[584]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[44] gvdd_load 0 inv size=1 -Xload_inv[585]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[45] gvdd_load 0 inv size=1 -Xload_inv[586]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[46] gvdd_load 0 inv size=1 -Xload_inv[587]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[47] gvdd_load 0 inv size=1 -Xload_inv[588]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[48] gvdd_load 0 inv size=1 -Xload_inv[589]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[49] gvdd_load 0 inv size=1 -Xload_inv[590]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[50] gvdd_load 0 inv size=1 -Xload_inv[591]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[51] gvdd_load 0 inv size=1 -Xload_inv[592]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[52] gvdd_load 0 inv size=1 -Xload_inv[593]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[53] gvdd_load 0 inv size=1 -Xload_inv[594]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[54] gvdd_load 0 inv size=1 -Xload_inv[595]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[55] gvdd_load 0 inv size=1 -Xload_inv[596]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[56] gvdd_load 0 inv size=1 -Xload_inv[597]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[57] gvdd_load 0 inv size=1 -Xload_inv[598]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[58] gvdd_load 0 inv size=1 -Xload_inv[599]_no0 grid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -***** Voltage supplies ***** -***** Voltage supplies ***** -Vgvdd_cb[1][1] gvdd_cbx[1][1] 0 vsp -Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_cb avg p(Vgvdd_cb[1][1]) from=0 to='clock_period' -.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_cb avg p(Vgvdd_cb[1][1]) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period' -.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_2/cb_tb/example_2_cby0_1_cb_testbench.sp b/examples/spice_test_example_2/cb_tb/example_2_cby0_1_cb_testbench.sp deleted file mode 100644 index 51ac06385..000000000 --- a/examples/spice_test_example_2/cb_tb/example_2_cby0_1_cb_testbench.sp +++ /dev/null @@ -1,1182 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_cbs -****** Include subckt netlists: Connection Box Y-channel [0][1] ***** -.include './spice_test_example_2/subckt/cby_0_1.sp' -***** Call defined Connection Box[0][1] ***** -Xcby[0][1] -+ chany[0][1]_midout[0] -+ chany[0][1]_midout[1] -+ chany[0][1]_midout[2] -+ chany[0][1]_midout[3] -+ chany[0][1]_midout[4] -+ chany[0][1]_midout[5] -+ chany[0][1]_midout[6] -+ chany[0][1]_midout[7] -+ chany[0][1]_midout[8] -+ chany[0][1]_midout[9] -+ chany[0][1]_midout[10] -+ chany[0][1]_midout[11] -+ chany[0][1]_midout[12] -+ chany[0][1]_midout[13] -+ chany[0][1]_midout[14] -+ chany[0][1]_midout[15] -+ chany[0][1]_midout[16] -+ chany[0][1]_midout[17] -+ chany[0][1]_midout[18] -+ chany[0][1]_midout[19] -+ chany[0][1]_midout[20] -+ chany[0][1]_midout[21] -+ chany[0][1]_midout[22] -+ chany[0][1]_midout[23] -+ chany[0][1]_midout[24] -+ chany[0][1]_midout[25] -+ chany[0][1]_midout[26] -+ chany[0][1]_midout[27] -+ chany[0][1]_midout[28] -+ chany[0][1]_midout[29] -+ chany[0][1]_midout[30] -+ chany[0][1]_midout[31] -+ chany[0][1]_midout[32] -+ chany[0][1]_midout[33] -+ chany[0][1]_midout[34] -+ chany[0][1]_midout[35] -+ chany[0][1]_midout[36] -+ chany[0][1]_midout[37] -+ chany[0][1]_midout[38] -+ chany[0][1]_midout[39] -+ chany[0][1]_midout[40] -+ chany[0][1]_midout[41] -+ chany[0][1]_midout[42] -+ chany[0][1]_midout[43] -+ chany[0][1]_midout[44] -+ chany[0][1]_midout[45] -+ chany[0][1]_midout[46] -+ chany[0][1]_midout[47] -+ chany[0][1]_midout[48] -+ chany[0][1]_midout[49] -+ chany[0][1]_midout[50] -+ chany[0][1]_midout[51] -+ chany[0][1]_midout[52] -+ chany[0][1]_midout[53] -+ chany[0][1]_midout[54] -+ chany[0][1]_midout[55] -+ chany[0][1]_midout[56] -+ chany[0][1]_midout[57] -+ chany[0][1]_midout[58] -+ chany[0][1]_midout[59] -+ chany[0][1]_midout[60] -+ chany[0][1]_midout[61] -+ chany[0][1]_midout[62] -+ chany[0][1]_midout[63] -+ chany[0][1]_midout[64] -+ chany[0][1]_midout[65] -+ chany[0][1]_midout[66] -+ chany[0][1]_midout[67] -+ chany[0][1]_midout[68] -+ chany[0][1]_midout[69] -+ chany[0][1]_midout[70] -+ chany[0][1]_midout[71] -+ chany[0][1]_midout[72] -+ chany[0][1]_midout[73] -+ chany[0][1]_midout[74] -+ chany[0][1]_midout[75] -+ chany[0][1]_midout[76] -+ chany[0][1]_midout[77] -+ chany[0][1]_midout[78] -+ chany[0][1]_midout[79] -+ chany[0][1]_midout[80] -+ chany[0][1]_midout[81] -+ chany[0][1]_midout[82] -+ chany[0][1]_midout[83] -+ chany[0][1]_midout[84] -+ chany[0][1]_midout[85] -+ chany[0][1]_midout[86] -+ chany[0][1]_midout[87] -+ chany[0][1]_midout[88] -+ chany[0][1]_midout[89] -+ chany[0][1]_midout[90] -+ chany[0][1]_midout[91] -+ chany[0][1]_midout[92] -+ chany[0][1]_midout[93] -+ chany[0][1]_midout[94] -+ chany[0][1]_midout[95] -+ chany[0][1]_midout[96] -+ chany[0][1]_midout[97] -+ chany[0][1]_midout[98] -+ chany[0][1]_midout[99] -+ grid[1][1]_pin[0][3][3] -+ grid[1][1]_pin[0][3][7] -+ grid[1][1]_pin[0][3][11] -+ grid[1][1]_pin[0][3][15] -+ grid[1][1]_pin[0][3][19] -+ grid[1][1]_pin[0][3][23] -+ grid[1][1]_pin[0][3][27] -+ grid[1][1]_pin[0][3][31] -+ grid[1][1]_pin[0][3][35] -+ grid[1][1]_pin[0][3][39] -+ grid[0][1]_pin[0][1][0] -+ grid[0][1]_pin[0][1][2] -+ grid[0][1]_pin[0][1][4] -+ grid[0][1]_pin[0][1][6] -+ grid[0][1]_pin[0][1][8] -+ grid[0][1]_pin[0][1][10] -+ grid[0][1]_pin[0][1][12] -+ grid[0][1]_pin[0][1][14] -+ gvdd_cby[0][1] 0 cby[0][1] -***** Signal chany[0][1]_midout[0] density = 0, probability=0.***** -Vchany[0][1]_midout[0] chany[0][1]_midout[0] 0 -+ 0 -***** Signal chany[0][1]_midout[1] density = 0, probability=0.***** -Vchany[0][1]_midout[1] chany[0][1]_midout[1] 0 -+ 0 -***** Signal chany[0][1]_midout[2] density = 0, probability=0.***** -Vchany[0][1]_midout[2] chany[0][1]_midout[2] 0 -+ 0 -***** Signal chany[0][1]_midout[3] density = 0, probability=0.***** -Vchany[0][1]_midout[3] chany[0][1]_midout[3] 0 -+ 0 -***** Signal chany[0][1]_midout[4] density = 0, probability=0.***** -Vchany[0][1]_midout[4] chany[0][1]_midout[4] 0 -+ 0 -***** Signal chany[0][1]_midout[5] density = 0, probability=0.***** -Vchany[0][1]_midout[5] chany[0][1]_midout[5] 0 -+ 0 -***** Signal chany[0][1]_midout[6] density = 0, probability=0.***** -Vchany[0][1]_midout[6] chany[0][1]_midout[6] 0 -+ 0 -***** Signal chany[0][1]_midout[7] density = 0, probability=0.***** -Vchany[0][1]_midout[7] chany[0][1]_midout[7] 0 -+ 0 -***** Signal chany[0][1]_midout[8] density = 0, probability=0.***** -Vchany[0][1]_midout[8] chany[0][1]_midout[8] 0 -+ 0 -***** Signal chany[0][1]_midout[9] density = 0, probability=0.***** -Vchany[0][1]_midout[9] chany[0][1]_midout[9] 0 -+ 0 -***** Signal chany[0][1]_midout[10] density = 0, probability=0.***** -Vchany[0][1]_midout[10] chany[0][1]_midout[10] 0 -+ 0 -***** Signal chany[0][1]_midout[11] density = 0, probability=0.***** -Vchany[0][1]_midout[11] chany[0][1]_midout[11] 0 -+ 0 -***** Signal chany[0][1]_midout[12] density = 0, probability=0.***** -Vchany[0][1]_midout[12] chany[0][1]_midout[12] 0 -+ 0 -***** Signal chany[0][1]_midout[13] density = 0, probability=0.***** -Vchany[0][1]_midout[13] chany[0][1]_midout[13] 0 -+ 0 -***** Signal chany[0][1]_midout[14] density = 0, probability=0.***** -Vchany[0][1]_midout[14] chany[0][1]_midout[14] 0 -+ 0 -***** Signal chany[0][1]_midout[15] density = 0, probability=0.***** -Vchany[0][1]_midout[15] chany[0][1]_midout[15] 0 -+ 0 -***** Signal chany[0][1]_midout[16] density = 0, probability=0.***** -Vchany[0][1]_midout[16] chany[0][1]_midout[16] 0 -+ 0 -***** Signal chany[0][1]_midout[17] density = 0, probability=0.***** -Vchany[0][1]_midout[17] chany[0][1]_midout[17] 0 -+ 0 -***** Signal chany[0][1]_midout[18] density = 0, probability=0.***** -Vchany[0][1]_midout[18] chany[0][1]_midout[18] 0 -+ 0 -***** Signal chany[0][1]_midout[19] density = 0, probability=0.***** -Vchany[0][1]_midout[19] chany[0][1]_midout[19] 0 -+ 0 -***** Signal chany[0][1]_midout[20] density = 0, probability=0.***** -Vchany[0][1]_midout[20] chany[0][1]_midout[20] 0 -+ 0 -***** Signal chany[0][1]_midout[21] density = 0, probability=0.***** -Vchany[0][1]_midout[21] chany[0][1]_midout[21] 0 -+ 0 -***** Signal chany[0][1]_midout[22] density = 0, probability=0.***** -Vchany[0][1]_midout[22] chany[0][1]_midout[22] 0 -+ 0 -***** Signal chany[0][1]_midout[23] density = 0, probability=0.***** -Vchany[0][1]_midout[23] chany[0][1]_midout[23] 0 -+ 0 -***** Signal chany[0][1]_midout[24] density = 0, probability=0.***** -Vchany[0][1]_midout[24] chany[0][1]_midout[24] 0 -+ 0 -***** Signal chany[0][1]_midout[25] density = 0, probability=0.***** -Vchany[0][1]_midout[25] chany[0][1]_midout[25] 0 -+ 0 -***** Signal chany[0][1]_midout[26] density = 0, probability=0.***** -Vchany[0][1]_midout[26] chany[0][1]_midout[26] 0 -+ 0 -***** Signal chany[0][1]_midout[27] density = 0, probability=0.***** -Vchany[0][1]_midout[27] chany[0][1]_midout[27] 0 -+ 0 -***** Signal chany[0][1]_midout[28] density = 0, probability=0.***** -Vchany[0][1]_midout[28] chany[0][1]_midout[28] 0 -+ 0 -***** Signal chany[0][1]_midout[29] density = 0, probability=0.***** -Vchany[0][1]_midout[29] chany[0][1]_midout[29] 0 -+ 0 -***** Signal chany[0][1]_midout[30] density = 0, probability=0.***** -Vchany[0][1]_midout[30] chany[0][1]_midout[30] 0 -+ 0 -***** Signal chany[0][1]_midout[31] density = 0, probability=0.***** -Vchany[0][1]_midout[31] chany[0][1]_midout[31] 0 -+ 0 -***** Signal chany[0][1]_midout[32] density = 0, probability=0.***** -Vchany[0][1]_midout[32] chany[0][1]_midout[32] 0 -+ 0 -***** Signal chany[0][1]_midout[33] density = 0, probability=0.***** -Vchany[0][1]_midout[33] chany[0][1]_midout[33] 0 -+ 0 -***** Signal chany[0][1]_midout[34] density = 0, probability=0.***** -Vchany[0][1]_midout[34] chany[0][1]_midout[34] 0 -+ 0 -***** Signal chany[0][1]_midout[35] density = 0, probability=0.***** -Vchany[0][1]_midout[35] chany[0][1]_midout[35] 0 -+ 0 -***** Signal chany[0][1]_midout[36] density = 0, probability=0.***** -Vchany[0][1]_midout[36] chany[0][1]_midout[36] 0 -+ 0 -***** Signal chany[0][1]_midout[37] density = 0, probability=0.***** -Vchany[0][1]_midout[37] chany[0][1]_midout[37] 0 -+ 0 -***** Signal chany[0][1]_midout[38] density = 0, probability=0.***** -Vchany[0][1]_midout[38] chany[0][1]_midout[38] 0 -+ 0 -***** Signal chany[0][1]_midout[39] density = 0, probability=0.***** -Vchany[0][1]_midout[39] chany[0][1]_midout[39] 0 -+ 0 -***** Signal chany[0][1]_midout[40] density = 0, probability=0.***** -Vchany[0][1]_midout[40] chany[0][1]_midout[40] 0 -+ 0 -***** Signal chany[0][1]_midout[41] density = 0, probability=0.***** -Vchany[0][1]_midout[41] chany[0][1]_midout[41] 0 -+ 0 -***** Signal chany[0][1]_midout[42] density = 0, probability=0.***** -Vchany[0][1]_midout[42] chany[0][1]_midout[42] 0 -+ 0 -***** Signal chany[0][1]_midout[43] density = 0, probability=0.***** -Vchany[0][1]_midout[43] chany[0][1]_midout[43] 0 -+ 0 -***** Signal chany[0][1]_midout[44] density = 0, probability=0.***** -Vchany[0][1]_midout[44] chany[0][1]_midout[44] 0 -+ 0 -***** Signal chany[0][1]_midout[45] density = 0, probability=0.***** -Vchany[0][1]_midout[45] chany[0][1]_midout[45] 0 -+ 0 -***** Signal chany[0][1]_midout[46] density = 0, probability=0.***** -Vchany[0][1]_midout[46] chany[0][1]_midout[46] 0 -+ 0 -***** Signal chany[0][1]_midout[47] density = 0, probability=0.***** -Vchany[0][1]_midout[47] chany[0][1]_midout[47] 0 -+ 0 -***** Signal chany[0][1]_midout[48] density = 0, probability=0.***** -Vchany[0][1]_midout[48] chany[0][1]_midout[48] 0 -+ 0 -***** Signal chany[0][1]_midout[49] density = 0, probability=0.***** -Vchany[0][1]_midout[49] chany[0][1]_midout[49] 0 -+ 0 -***** Signal chany[0][1]_midout[50] density = 0, probability=0.***** -Vchany[0][1]_midout[50] chany[0][1]_midout[50] 0 -+ 0 -***** Signal chany[0][1]_midout[51] density = 0, probability=0.***** -Vchany[0][1]_midout[51] chany[0][1]_midout[51] 0 -+ 0 -***** Signal chany[0][1]_midout[52] density = 0, probability=0.***** -Vchany[0][1]_midout[52] chany[0][1]_midout[52] 0 -+ 0 -***** Signal chany[0][1]_midout[53] density = 0, probability=0.***** -Vchany[0][1]_midout[53] chany[0][1]_midout[53] 0 -+ 0 -***** Signal chany[0][1]_midout[54] density = 0, probability=0.***** -Vchany[0][1]_midout[54] chany[0][1]_midout[54] 0 -+ 0 -***** Signal chany[0][1]_midout[55] density = 0, probability=0.***** -Vchany[0][1]_midout[55] chany[0][1]_midout[55] 0 -+ 0 -***** Signal chany[0][1]_midout[56] density = 0, probability=0.***** -Vchany[0][1]_midout[56] chany[0][1]_midout[56] 0 -+ 0 -***** Signal chany[0][1]_midout[57] density = 0, probability=0.***** -Vchany[0][1]_midout[57] chany[0][1]_midout[57] 0 -+ 0 -***** Signal chany[0][1]_midout[58] density = 0, probability=0.***** -Vchany[0][1]_midout[58] chany[0][1]_midout[58] 0 -+ 0 -***** Signal chany[0][1]_midout[59] density = 0, probability=0.***** -Vchany[0][1]_midout[59] chany[0][1]_midout[59] 0 -+ 0 -***** Signal chany[0][1]_midout[60] density = 0, probability=0.***** -Vchany[0][1]_midout[60] chany[0][1]_midout[60] 0 -+ 0 -***** Signal chany[0][1]_midout[61] density = 0, probability=0.***** -Vchany[0][1]_midout[61] chany[0][1]_midout[61] 0 -+ 0 -***** Signal chany[0][1]_midout[62] density = 0, probability=0.***** -Vchany[0][1]_midout[62] chany[0][1]_midout[62] 0 -+ 0 -***** Signal chany[0][1]_midout[63] density = 0, probability=0.***** -Vchany[0][1]_midout[63] chany[0][1]_midout[63] 0 -+ 0 -***** Signal chany[0][1]_midout[64] density = 0, probability=0.***** -Vchany[0][1]_midout[64] chany[0][1]_midout[64] 0 -+ 0 -***** Signal chany[0][1]_midout[65] density = 0, probability=0.***** -Vchany[0][1]_midout[65] chany[0][1]_midout[65] 0 -+ 0 -***** Signal chany[0][1]_midout[66] density = 0, probability=0.***** -Vchany[0][1]_midout[66] chany[0][1]_midout[66] 0 -+ 0 -***** Signal chany[0][1]_midout[67] density = 0, probability=0.***** -Vchany[0][1]_midout[67] chany[0][1]_midout[67] 0 -+ 0 -***** Signal chany[0][1]_midout[68] density = 0, probability=0.***** -Vchany[0][1]_midout[68] chany[0][1]_midout[68] 0 -+ 0 -***** Signal chany[0][1]_midout[69] density = 0, probability=0.***** -Vchany[0][1]_midout[69] chany[0][1]_midout[69] 0 -+ 0 -***** Signal chany[0][1]_midout[70] density = 0, probability=0.***** -Vchany[0][1]_midout[70] chany[0][1]_midout[70] 0 -+ 0 -***** Signal chany[0][1]_midout[71] density = 0, probability=0.***** -Vchany[0][1]_midout[71] chany[0][1]_midout[71] 0 -+ 0 -***** Signal chany[0][1]_midout[72] density = 0, probability=0.***** -Vchany[0][1]_midout[72] chany[0][1]_midout[72] 0 -+ 0 -***** Signal chany[0][1]_midout[73] density = 0, probability=0.***** -Vchany[0][1]_midout[73] chany[0][1]_midout[73] 0 -+ 0 -***** Signal chany[0][1]_midout[74] density = 0, probability=0.***** -Vchany[0][1]_midout[74] chany[0][1]_midout[74] 0 -+ 0 -***** Signal chany[0][1]_midout[75] density = 0, probability=0.***** -Vchany[0][1]_midout[75] chany[0][1]_midout[75] 0 -+ 0 -***** Signal chany[0][1]_midout[76] density = 0.2026, probability=0.4982.***** -Vchany[0][1]_midout[76] chany[0][1]_midout[76] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[0][1]_midout[77] density = 0, probability=0.***** -Vchany[0][1]_midout[77] chany[0][1]_midout[77] 0 -+ 0 -***** Signal chany[0][1]_midout[78] density = 0, probability=0.***** -Vchany[0][1]_midout[78] chany[0][1]_midout[78] 0 -+ 0 -***** Signal chany[0][1]_midout[79] density = 0, probability=0.***** -Vchany[0][1]_midout[79] chany[0][1]_midout[79] 0 -+ 0 -***** Signal chany[0][1]_midout[80] density = 0, probability=0.***** -Vchany[0][1]_midout[80] chany[0][1]_midout[80] 0 -+ 0 -***** Signal chany[0][1]_midout[81] density = 0, probability=0.***** -Vchany[0][1]_midout[81] chany[0][1]_midout[81] 0 -+ 0 -***** Signal chany[0][1]_midout[82] density = 0, probability=0.***** -Vchany[0][1]_midout[82] chany[0][1]_midout[82] 0 -+ 0 -***** Signal chany[0][1]_midout[83] density = 0, probability=0.***** -Vchany[0][1]_midout[83] chany[0][1]_midout[83] 0 -+ 0 -***** Signal chany[0][1]_midout[84] density = 0, probability=0.***** -Vchany[0][1]_midout[84] chany[0][1]_midout[84] 0 -+ 0 -***** Signal chany[0][1]_midout[85] density = 0, probability=0.***** -Vchany[0][1]_midout[85] chany[0][1]_midout[85] 0 -+ 0 -***** Signal chany[0][1]_midout[86] density = 0, probability=0.***** -Vchany[0][1]_midout[86] chany[0][1]_midout[86] 0 -+ 0 -***** Signal chany[0][1]_midout[87] density = 0, probability=0.***** -Vchany[0][1]_midout[87] chany[0][1]_midout[87] 0 -+ 0 -***** Signal chany[0][1]_midout[88] density = 0, probability=0.***** -Vchany[0][1]_midout[88] chany[0][1]_midout[88] 0 -+ 0 -***** Signal chany[0][1]_midout[89] density = 0, probability=0.***** -Vchany[0][1]_midout[89] chany[0][1]_midout[89] 0 -+ 0 -***** Signal chany[0][1]_midout[90] density = 0, probability=0.***** -Vchany[0][1]_midout[90] chany[0][1]_midout[90] 0 -+ 0 -***** Signal chany[0][1]_midout[91] density = 0, probability=0.***** -Vchany[0][1]_midout[91] chany[0][1]_midout[91] 0 -+ 0 -***** Signal chany[0][1]_midout[92] density = 0, probability=0.***** -Vchany[0][1]_midout[92] chany[0][1]_midout[92] 0 -+ 0 -***** Signal chany[0][1]_midout[93] density = 0, probability=0.***** -Vchany[0][1]_midout[93] chany[0][1]_midout[93] 0 -+ 0 -***** Signal chany[0][1]_midout[94] density = 0, probability=0.***** -Vchany[0][1]_midout[94] chany[0][1]_midout[94] 0 -+ 0 -***** Signal chany[0][1]_midout[95] density = 0, probability=0.***** -Vchany[0][1]_midout[95] chany[0][1]_midout[95] 0 -+ 0 -***** Signal chany[0][1]_midout[96] density = 0, probability=0.***** -Vchany[0][1]_midout[96] chany[0][1]_midout[96] 0 -+ 0 -***** Signal chany[0][1]_midout[97] density = 0, probability=0.***** -Vchany[0][1]_midout[97] chany[0][1]_midout[97] 0 -+ 0 -***** Signal chany[0][1]_midout[98] density = 0, probability=0.***** -Vchany[0][1]_midout[98] chany[0][1]_midout[98] 0 -+ 0 -***** Signal chany[0][1]_midout[99] density = 0, probability=0.***** -Vchany[0][1]_midout[99] chany[0][1]_midout[99] 0 -+ 0 -******* Normal TYPE loads ******* -Xload_inv[0]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[4] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[5] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[6] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[7] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[8] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[9] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[10] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[11] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[12] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[13] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[14] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[15] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[16] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[17] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[18] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[19] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[20] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[21] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[22] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[23] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[24] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[25] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[26] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[27] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[28] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[29] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[30] gvdd_load 0 inv size=1 -Xload_inv[31]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[31] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[32] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[33] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[34] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[35] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[36] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[37] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[38] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[39] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[40] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[41] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[42] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[43] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[44] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[45] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[46] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[47] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[48] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[49] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[50] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[51] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[52] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[53] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[54] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[55] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[56] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[57] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[58] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 grid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[60]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[1] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[2] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[3] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[4] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[5] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[6] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[7] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[8] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[9] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[10] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[11] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[12] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[13] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[14] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[15] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[16] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[17] gvdd_load 0 inv size=1 -Xload_inv[78]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[18] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[19] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[20] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[21] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[22] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[23] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[24] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[25] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[26] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[27] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[28] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[29] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[30] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[31] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[32] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[33] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[34] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[35] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[36] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[37] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[38] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[39] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[40] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[41] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[42] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[43] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[44] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[45] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[46] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[47] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[48] gvdd_load 0 inv size=1 -Xload_inv[109]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[49] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[50] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[51] gvdd_load 0 inv size=1 -Xload_inv[112]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[52] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[53] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[54] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[55] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[56] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[57] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[58] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 grid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[120]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[3] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[4] gvdd_load 0 inv size=1 -Xload_inv[125]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[5] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[6] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[7] gvdd_load 0 inv size=1 -Xload_inv[128]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[8] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[9] gvdd_load 0 inv size=1 -Xload_inv[130]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[10] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[11] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[12] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[13] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[14] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[15] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[16] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[17] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[18] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[19] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[20] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[21] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[22] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[23] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[24] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[25] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[26] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[27] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[28] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[29] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[30] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[31] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[32] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[33] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[34] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[35] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[36] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[37] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[38] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[39] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[40] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[41] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[42] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[43] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[44] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[45] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[46] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[47] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[48] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[49] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[50] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[51] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[52] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[53] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[54] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[55] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[56] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[57] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[58] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 grid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[180]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[0] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[1] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[2] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[3] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[4] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[5] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[6] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[7] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[8] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[9] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[10] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[11] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[12] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[13] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[14] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[15] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[16] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[17] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[18] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[19] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[20] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[21] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[22] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[23] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[24] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[25] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[26] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[27] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[28] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[29] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[30] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[31] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[32] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[33] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[34] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[35] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[36] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[37] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[38] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[39] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[40] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[41] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[42] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[43] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[44] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[45] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[46] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[47] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[48] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[49] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[50] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[51] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[52] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[53] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[54] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[55] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[56] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[57] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[58] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 grid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[240]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[0] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[1] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[2] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[3] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[4] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[5] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[6] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[7] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[8] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[9] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[10] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[11] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[12] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[13] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[14] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[15] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[16] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[17] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[18] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[19] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[20] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[21] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[22] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[23] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[24] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[25] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[26] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[27] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[28] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[29] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[30] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[31] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[32] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[33] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[34] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[35] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[36] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[37] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[38] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[39] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[40] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[41] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[42] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[43] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[44] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[45] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[46] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[47] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[48] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[49] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[50] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[51] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[52] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[53] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[54] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[55] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[56] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[57] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[58] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 grid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[300]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[0] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[1] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[2] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[3] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[4] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[5] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[6] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[7] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[8] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[9] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[10] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[11] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[12] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[13] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[14] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[15] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[16] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[17] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[18] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[19] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[20] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[21] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[22] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[23] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[24] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[25] gvdd_load 0 inv size=1 -Xload_inv[326]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[26] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[27] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[28] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[29] gvdd_load 0 inv size=1 -Xload_inv[330]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[30] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[31] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[32] gvdd_load 0 inv size=1 -Xload_inv[333]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[33] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[34] gvdd_load 0 inv size=1 -Xload_inv[335]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[35] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[36] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[37] gvdd_load 0 inv size=1 -Xload_inv[338]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[38] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[39] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[40] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[41] gvdd_load 0 inv size=1 -Xload_inv[342]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[42] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[43] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[44] gvdd_load 0 inv size=1 -Xload_inv[345]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[45] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[46] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[47] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[48] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[49] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[50] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[51] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[52] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[53] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[54] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[55] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[56] gvdd_load 0 inv size=1 -Xload_inv[357]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[57] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[58] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 grid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[360]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[0] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[1] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[2] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[3] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[4] gvdd_load 0 inv size=1 -Xload_inv[365]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[5] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[6] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[7] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[8] gvdd_load 0 inv size=1 -Xload_inv[369]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[9] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[10] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[11] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[12] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[13] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[14] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[15] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[16] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[17] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[18] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[19] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[20] gvdd_load 0 inv size=1 -Xload_inv[381]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[21] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[22] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[23] gvdd_load 0 inv size=1 -Xload_inv[384]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[24] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[25] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[26] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[27] gvdd_load 0 inv size=1 -Xload_inv[388]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[28] gvdd_load 0 inv size=1 -Xload_inv[389]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[29] gvdd_load 0 inv size=1 -Xload_inv[390]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[30] gvdd_load 0 inv size=1 -Xload_inv[391]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[31] gvdd_load 0 inv size=1 -Xload_inv[392]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[32] gvdd_load 0 inv size=1 -Xload_inv[393]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[33] gvdd_load 0 inv size=1 -Xload_inv[394]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[34] gvdd_load 0 inv size=1 -Xload_inv[395]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[35] gvdd_load 0 inv size=1 -Xload_inv[396]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[36] gvdd_load 0 inv size=1 -Xload_inv[397]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[37] gvdd_load 0 inv size=1 -Xload_inv[398]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[38] gvdd_load 0 inv size=1 -Xload_inv[399]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[39] gvdd_load 0 inv size=1 -Xload_inv[400]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[40] gvdd_load 0 inv size=1 -Xload_inv[401]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[41] gvdd_load 0 inv size=1 -Xload_inv[402]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[42] gvdd_load 0 inv size=1 -Xload_inv[403]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[43] gvdd_load 0 inv size=1 -Xload_inv[404]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[44] gvdd_load 0 inv size=1 -Xload_inv[405]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[45] gvdd_load 0 inv size=1 -Xload_inv[406]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[46] gvdd_load 0 inv size=1 -Xload_inv[407]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[47] gvdd_load 0 inv size=1 -Xload_inv[408]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[48] gvdd_load 0 inv size=1 -Xload_inv[409]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[49] gvdd_load 0 inv size=1 -Xload_inv[410]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[50] gvdd_load 0 inv size=1 -Xload_inv[411]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[51] gvdd_load 0 inv size=1 -Xload_inv[412]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[52] gvdd_load 0 inv size=1 -Xload_inv[413]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[53] gvdd_load 0 inv size=1 -Xload_inv[414]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[54] gvdd_load 0 inv size=1 -Xload_inv[415]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[55] gvdd_load 0 inv size=1 -Xload_inv[416]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[56] gvdd_load 0 inv size=1 -Xload_inv[417]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[57] gvdd_load 0 inv size=1 -Xload_inv[418]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[58] gvdd_load 0 inv size=1 -Xload_inv[419]_no0 grid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[420]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[0] gvdd_load 0 inv size=1 -Xload_inv[421]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[1] gvdd_load 0 inv size=1 -Xload_inv[422]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[2] gvdd_load 0 inv size=1 -Xload_inv[423]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[3] gvdd_load 0 inv size=1 -Xload_inv[424]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[4] gvdd_load 0 inv size=1 -Xload_inv[425]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[5] gvdd_load 0 inv size=1 -Xload_inv[426]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[6] gvdd_load 0 inv size=1 -Xload_inv[427]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[7] gvdd_load 0 inv size=1 -Xload_inv[428]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[8] gvdd_load 0 inv size=1 -Xload_inv[429]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[9] gvdd_load 0 inv size=1 -Xload_inv[430]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[10] gvdd_load 0 inv size=1 -Xload_inv[431]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[11] gvdd_load 0 inv size=1 -Xload_inv[432]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[12] gvdd_load 0 inv size=1 -Xload_inv[433]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[13] gvdd_load 0 inv size=1 -Xload_inv[434]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[14] gvdd_load 0 inv size=1 -Xload_inv[435]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[15] gvdd_load 0 inv size=1 -Xload_inv[436]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[16] gvdd_load 0 inv size=1 -Xload_inv[437]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[17] gvdd_load 0 inv size=1 -Xload_inv[438]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[18] gvdd_load 0 inv size=1 -Xload_inv[439]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[19] gvdd_load 0 inv size=1 -Xload_inv[440]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[20] gvdd_load 0 inv size=1 -Xload_inv[441]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[21] gvdd_load 0 inv size=1 -Xload_inv[442]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[22] gvdd_load 0 inv size=1 -Xload_inv[443]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[23] gvdd_load 0 inv size=1 -Xload_inv[444]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[24] gvdd_load 0 inv size=1 -Xload_inv[445]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[25] gvdd_load 0 inv size=1 -Xload_inv[446]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[26] gvdd_load 0 inv size=1 -Xload_inv[447]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[27] gvdd_load 0 inv size=1 -Xload_inv[448]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[28] gvdd_load 0 inv size=1 -Xload_inv[449]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[29] gvdd_load 0 inv size=1 -Xload_inv[450]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[30] gvdd_load 0 inv size=1 -Xload_inv[451]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[31] gvdd_load 0 inv size=1 -Xload_inv[452]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[32] gvdd_load 0 inv size=1 -Xload_inv[453]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[33] gvdd_load 0 inv size=1 -Xload_inv[454]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[34] gvdd_load 0 inv size=1 -Xload_inv[455]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[35] gvdd_load 0 inv size=1 -Xload_inv[456]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[36] gvdd_load 0 inv size=1 -Xload_inv[457]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[37] gvdd_load 0 inv size=1 -Xload_inv[458]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[38] gvdd_load 0 inv size=1 -Xload_inv[459]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[39] gvdd_load 0 inv size=1 -Xload_inv[460]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[40] gvdd_load 0 inv size=1 -Xload_inv[461]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[41] gvdd_load 0 inv size=1 -Xload_inv[462]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[42] gvdd_load 0 inv size=1 -Xload_inv[463]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[43] gvdd_load 0 inv size=1 -Xload_inv[464]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[44] gvdd_load 0 inv size=1 -Xload_inv[465]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[45] gvdd_load 0 inv size=1 -Xload_inv[466]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[46] gvdd_load 0 inv size=1 -Xload_inv[467]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[47] gvdd_load 0 inv size=1 -Xload_inv[468]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[48] gvdd_load 0 inv size=1 -Xload_inv[469]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[49] gvdd_load 0 inv size=1 -Xload_inv[470]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[50] gvdd_load 0 inv size=1 -Xload_inv[471]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[51] gvdd_load 0 inv size=1 -Xload_inv[472]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[52] gvdd_load 0 inv size=1 -Xload_inv[473]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[53] gvdd_load 0 inv size=1 -Xload_inv[474]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[54] gvdd_load 0 inv size=1 -Xload_inv[475]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[55] gvdd_load 0 inv size=1 -Xload_inv[476]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[56] gvdd_load 0 inv size=1 -Xload_inv[477]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[57] gvdd_load 0 inv size=1 -Xload_inv[478]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[58] gvdd_load 0 inv size=1 -Xload_inv[479]_no0 grid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[480]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[0] gvdd_load 0 inv size=1 -Xload_inv[481]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[1] gvdd_load 0 inv size=1 -Xload_inv[482]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[2] gvdd_load 0 inv size=1 -Xload_inv[483]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[3] gvdd_load 0 inv size=1 -Xload_inv[484]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[4] gvdd_load 0 inv size=1 -Xload_inv[485]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[5] gvdd_load 0 inv size=1 -Xload_inv[486]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[6] gvdd_load 0 inv size=1 -Xload_inv[487]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[7] gvdd_load 0 inv size=1 -Xload_inv[488]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[8] gvdd_load 0 inv size=1 -Xload_inv[489]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[9] gvdd_load 0 inv size=1 -Xload_inv[490]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[10] gvdd_load 0 inv size=1 -Xload_inv[491]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[11] gvdd_load 0 inv size=1 -Xload_inv[492]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[12] gvdd_load 0 inv size=1 -Xload_inv[493]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[13] gvdd_load 0 inv size=1 -Xload_inv[494]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[14] gvdd_load 0 inv size=1 -Xload_inv[495]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[15] gvdd_load 0 inv size=1 -Xload_inv[496]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[16] gvdd_load 0 inv size=1 -Xload_inv[497]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[17] gvdd_load 0 inv size=1 -Xload_inv[498]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[18] gvdd_load 0 inv size=1 -Xload_inv[499]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[19] gvdd_load 0 inv size=1 -Xload_inv[500]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[20] gvdd_load 0 inv size=1 -Xload_inv[501]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[21] gvdd_load 0 inv size=1 -Xload_inv[502]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[22] gvdd_load 0 inv size=1 -Xload_inv[503]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[23] gvdd_load 0 inv size=1 -Xload_inv[504]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[24] gvdd_load 0 inv size=1 -Xload_inv[505]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[25] gvdd_load 0 inv size=1 -Xload_inv[506]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[26] gvdd_load 0 inv size=1 -Xload_inv[507]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[27] gvdd_load 0 inv size=1 -Xload_inv[508]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[28] gvdd_load 0 inv size=1 -Xload_inv[509]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[29] gvdd_load 0 inv size=1 -Xload_inv[510]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[30] gvdd_load 0 inv size=1 -Xload_inv[511]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[31] gvdd_load 0 inv size=1 -Xload_inv[512]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[32] gvdd_load 0 inv size=1 -Xload_inv[513]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[33] gvdd_load 0 inv size=1 -Xload_inv[514]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[34] gvdd_load 0 inv size=1 -Xload_inv[515]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[35] gvdd_load 0 inv size=1 -Xload_inv[516]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[36] gvdd_load 0 inv size=1 -Xload_inv[517]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[37] gvdd_load 0 inv size=1 -Xload_inv[518]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[38] gvdd_load 0 inv size=1 -Xload_inv[519]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[39] gvdd_load 0 inv size=1 -Xload_inv[520]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[40] gvdd_load 0 inv size=1 -Xload_inv[521]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[41] gvdd_load 0 inv size=1 -Xload_inv[522]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[42] gvdd_load 0 inv size=1 -Xload_inv[523]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[43] gvdd_load 0 inv size=1 -Xload_inv[524]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[44] gvdd_load 0 inv size=1 -Xload_inv[525]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[45] gvdd_load 0 inv size=1 -Xload_inv[526]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[46] gvdd_load 0 inv size=1 -Xload_inv[527]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[47] gvdd_load 0 inv size=1 -Xload_inv[528]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[48] gvdd_load 0 inv size=1 -Xload_inv[529]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[49] gvdd_load 0 inv size=1 -Xload_inv[530]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[50] gvdd_load 0 inv size=1 -Xload_inv[531]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[51] gvdd_load 0 inv size=1 -Xload_inv[532]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[52] gvdd_load 0 inv size=1 -Xload_inv[533]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[53] gvdd_load 0 inv size=1 -Xload_inv[534]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[54] gvdd_load 0 inv size=1 -Xload_inv[535]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[55] gvdd_load 0 inv size=1 -Xload_inv[536]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[56] gvdd_load 0 inv size=1 -Xload_inv[537]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[57] gvdd_load 0 inv size=1 -Xload_inv[538]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[58] gvdd_load 0 inv size=1 -Xload_inv[539]_no0 grid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[540]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[0] gvdd_load 0 inv size=1 -Xload_inv[541]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[1] gvdd_load 0 inv size=1 -Xload_inv[542]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[2] gvdd_load 0 inv size=1 -Xload_inv[543]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[3] gvdd_load 0 inv size=1 -Xload_inv[544]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[4] gvdd_load 0 inv size=1 -Xload_inv[545]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[5] gvdd_load 0 inv size=1 -Xload_inv[546]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[6] gvdd_load 0 inv size=1 -Xload_inv[547]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[7] gvdd_load 0 inv size=1 -Xload_inv[548]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[8] gvdd_load 0 inv size=1 -Xload_inv[549]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[9] gvdd_load 0 inv size=1 -Xload_inv[550]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[10] gvdd_load 0 inv size=1 -Xload_inv[551]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[11] gvdd_load 0 inv size=1 -Xload_inv[552]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[12] gvdd_load 0 inv size=1 -Xload_inv[553]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[13] gvdd_load 0 inv size=1 -Xload_inv[554]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[14] gvdd_load 0 inv size=1 -Xload_inv[555]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[15] gvdd_load 0 inv size=1 -Xload_inv[556]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[16] gvdd_load 0 inv size=1 -Xload_inv[557]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[17] gvdd_load 0 inv size=1 -Xload_inv[558]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[18] gvdd_load 0 inv size=1 -Xload_inv[559]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[19] gvdd_load 0 inv size=1 -Xload_inv[560]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[20] gvdd_load 0 inv size=1 -Xload_inv[561]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[21] gvdd_load 0 inv size=1 -Xload_inv[562]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[22] gvdd_load 0 inv size=1 -Xload_inv[563]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[23] gvdd_load 0 inv size=1 -Xload_inv[564]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[24] gvdd_load 0 inv size=1 -Xload_inv[565]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[25] gvdd_load 0 inv size=1 -Xload_inv[566]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[26] gvdd_load 0 inv size=1 -Xload_inv[567]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[27] gvdd_load 0 inv size=1 -Xload_inv[568]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[28] gvdd_load 0 inv size=1 -Xload_inv[569]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[29] gvdd_load 0 inv size=1 -Xload_inv[570]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[30] gvdd_load 0 inv size=1 -Xload_inv[571]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[31] gvdd_load 0 inv size=1 -Xload_inv[572]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[32] gvdd_load 0 inv size=1 -Xload_inv[573]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[33] gvdd_load 0 inv size=1 -Xload_inv[574]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[34] gvdd_load 0 inv size=1 -Xload_inv[575]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[35] gvdd_load 0 inv size=1 -Xload_inv[576]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[36] gvdd_load 0 inv size=1 -Xload_inv[577]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[37] gvdd_load 0 inv size=1 -Xload_inv[578]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[38] gvdd_load 0 inv size=1 -Xload_inv[579]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[39] gvdd_load 0 inv size=1 -Xload_inv[580]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[40] gvdd_load 0 inv size=1 -Xload_inv[581]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[41] gvdd_load 0 inv size=1 -Xload_inv[582]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[42] gvdd_load 0 inv size=1 -Xload_inv[583]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[43] gvdd_load 0 inv size=1 -Xload_inv[584]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[44] gvdd_load 0 inv size=1 -Xload_inv[585]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[45] gvdd_load 0 inv size=1 -Xload_inv[586]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[46] gvdd_load 0 inv size=1 -Xload_inv[587]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[47] gvdd_load 0 inv size=1 -Xload_inv[588]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[48] gvdd_load 0 inv size=1 -Xload_inv[589]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[49] gvdd_load 0 inv size=1 -Xload_inv[590]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[50] gvdd_load 0 inv size=1 -Xload_inv[591]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[51] gvdd_load 0 inv size=1 -Xload_inv[592]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[52] gvdd_load 0 inv size=1 -Xload_inv[593]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[53] gvdd_load 0 inv size=1 -Xload_inv[594]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[54] gvdd_load 0 inv size=1 -Xload_inv[595]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[55] gvdd_load 0 inv size=1 -Xload_inv[596]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[56] gvdd_load 0 inv size=1 -Xload_inv[597]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[57] gvdd_load 0 inv size=1 -Xload_inv[598]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[58] gvdd_load 0 inv size=1 -Xload_inv[599]_no0 grid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -***** Voltage supplies ***** -***** Voltage supplies ***** -Vgvdd_cb[0][1] gvdd_cby[0][1] 0 vsp -Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_cb avg p(Vgvdd_cb[0][1]) from=0 to='clock_period' -.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_cb avg p(Vgvdd_cb[0][1]) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period' -.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_2/cb_tb/example_2_cby1_1_cb_testbench.sp b/examples/spice_test_example_2/cb_tb/example_2_cby1_1_cb_testbench.sp deleted file mode 100644 index 0845d3932..000000000 --- a/examples/spice_test_example_2/cb_tb/example_2_cby1_1_cb_testbench.sp +++ /dev/null @@ -1,1200 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Connection Box Testbench Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_cbs -****** Include subckt netlists: Connection Box Y-channel [1][1] ***** -.include './spice_test_example_2/subckt/cby_1_1.sp' -***** Call defined Connection Box[1][1] ***** -Xcby[1][1] -+ chany[1][1]_midout[0] -+ chany[1][1]_midout[1] -+ chany[1][1]_midout[2] -+ chany[1][1]_midout[3] -+ chany[1][1]_midout[4] -+ chany[1][1]_midout[5] -+ chany[1][1]_midout[6] -+ chany[1][1]_midout[7] -+ chany[1][1]_midout[8] -+ chany[1][1]_midout[9] -+ chany[1][1]_midout[10] -+ chany[1][1]_midout[11] -+ chany[1][1]_midout[12] -+ chany[1][1]_midout[13] -+ chany[1][1]_midout[14] -+ chany[1][1]_midout[15] -+ chany[1][1]_midout[16] -+ chany[1][1]_midout[17] -+ chany[1][1]_midout[18] -+ chany[1][1]_midout[19] -+ chany[1][1]_midout[20] -+ chany[1][1]_midout[21] -+ chany[1][1]_midout[22] -+ chany[1][1]_midout[23] -+ chany[1][1]_midout[24] -+ chany[1][1]_midout[25] -+ chany[1][1]_midout[26] -+ chany[1][1]_midout[27] -+ chany[1][1]_midout[28] -+ chany[1][1]_midout[29] -+ chany[1][1]_midout[30] -+ chany[1][1]_midout[31] -+ chany[1][1]_midout[32] -+ chany[1][1]_midout[33] -+ chany[1][1]_midout[34] -+ chany[1][1]_midout[35] -+ chany[1][1]_midout[36] -+ chany[1][1]_midout[37] -+ chany[1][1]_midout[38] -+ chany[1][1]_midout[39] -+ chany[1][1]_midout[40] -+ chany[1][1]_midout[41] -+ chany[1][1]_midout[42] -+ chany[1][1]_midout[43] -+ chany[1][1]_midout[44] -+ chany[1][1]_midout[45] -+ chany[1][1]_midout[46] -+ chany[1][1]_midout[47] -+ chany[1][1]_midout[48] -+ chany[1][1]_midout[49] -+ chany[1][1]_midout[50] -+ chany[1][1]_midout[51] -+ chany[1][1]_midout[52] -+ chany[1][1]_midout[53] -+ chany[1][1]_midout[54] -+ chany[1][1]_midout[55] -+ chany[1][1]_midout[56] -+ chany[1][1]_midout[57] -+ chany[1][1]_midout[58] -+ chany[1][1]_midout[59] -+ chany[1][1]_midout[60] -+ chany[1][1]_midout[61] -+ chany[1][1]_midout[62] -+ chany[1][1]_midout[63] -+ chany[1][1]_midout[64] -+ chany[1][1]_midout[65] -+ chany[1][1]_midout[66] -+ chany[1][1]_midout[67] -+ chany[1][1]_midout[68] -+ chany[1][1]_midout[69] -+ chany[1][1]_midout[70] -+ chany[1][1]_midout[71] -+ chany[1][1]_midout[72] -+ chany[1][1]_midout[73] -+ chany[1][1]_midout[74] -+ chany[1][1]_midout[75] -+ chany[1][1]_midout[76] -+ chany[1][1]_midout[77] -+ chany[1][1]_midout[78] -+ chany[1][1]_midout[79] -+ chany[1][1]_midout[80] -+ chany[1][1]_midout[81] -+ chany[1][1]_midout[82] -+ chany[1][1]_midout[83] -+ chany[1][1]_midout[84] -+ chany[1][1]_midout[85] -+ chany[1][1]_midout[86] -+ chany[1][1]_midout[87] -+ chany[1][1]_midout[88] -+ chany[1][1]_midout[89] -+ chany[1][1]_midout[90] -+ chany[1][1]_midout[91] -+ chany[1][1]_midout[92] -+ chany[1][1]_midout[93] -+ chany[1][1]_midout[94] -+ chany[1][1]_midout[95] -+ chany[1][1]_midout[96] -+ chany[1][1]_midout[97] -+ chany[1][1]_midout[98] -+ chany[1][1]_midout[99] -+ grid[2][1]_pin[0][3][0] -+ grid[2][1]_pin[0][3][2] -+ grid[2][1]_pin[0][3][4] -+ grid[2][1]_pin[0][3][6] -+ grid[2][1]_pin[0][3][8] -+ grid[2][1]_pin[0][3][10] -+ grid[2][1]_pin[0][3][12] -+ grid[2][1]_pin[0][3][14] -+ grid[1][1]_pin[0][1][1] -+ grid[1][1]_pin[0][1][5] -+ grid[1][1]_pin[0][1][9] -+ grid[1][1]_pin[0][1][13] -+ grid[1][1]_pin[0][1][17] -+ grid[1][1]_pin[0][1][21] -+ grid[1][1]_pin[0][1][25] -+ grid[1][1]_pin[0][1][29] -+ grid[1][1]_pin[0][1][33] -+ grid[1][1]_pin[0][1][37] -+ gvdd_cby[1][1] 0 cby[1][1] -***** Signal chany[1][1]_midout[0] density = 0, probability=0.***** -Vchany[1][1]_midout[0] chany[1][1]_midout[0] 0 -+ 0 -***** Signal chany[1][1]_midout[1] density = 0, probability=0.***** -Vchany[1][1]_midout[1] chany[1][1]_midout[1] 0 -+ 0 -***** Signal chany[1][1]_midout[2] density = 0, probability=0.***** -Vchany[1][1]_midout[2] chany[1][1]_midout[2] 0 -+ 0 -***** Signal chany[1][1]_midout[3] density = 0, probability=0.***** -Vchany[1][1]_midout[3] chany[1][1]_midout[3] 0 -+ 0 -***** Signal chany[1][1]_midout[4] density = 0, probability=0.***** -Vchany[1][1]_midout[4] chany[1][1]_midout[4] 0 -+ 0 -***** Signal chany[1][1]_midout[5] density = 0, probability=0.***** -Vchany[1][1]_midout[5] chany[1][1]_midout[5] 0 -+ 0 -***** Signal chany[1][1]_midout[6] density = 0, probability=0.***** -Vchany[1][1]_midout[6] chany[1][1]_midout[6] 0 -+ 0 -***** Signal chany[1][1]_midout[7] density = 0, probability=0.***** -Vchany[1][1]_midout[7] chany[1][1]_midout[7] 0 -+ 0 -***** Signal chany[1][1]_midout[8] density = 0, probability=0.***** -Vchany[1][1]_midout[8] chany[1][1]_midout[8] 0 -+ 0 -***** Signal chany[1][1]_midout[9] density = 0, probability=0.***** -Vchany[1][1]_midout[9] chany[1][1]_midout[9] 0 -+ 0 -***** Signal chany[1][1]_midout[10] density = 0, probability=0.***** -Vchany[1][1]_midout[10] chany[1][1]_midout[10] 0 -+ 0 -***** Signal chany[1][1]_midout[11] density = 0, probability=0.***** -Vchany[1][1]_midout[11] chany[1][1]_midout[11] 0 -+ 0 -***** Signal chany[1][1]_midout[12] density = 0, probability=0.***** -Vchany[1][1]_midout[12] chany[1][1]_midout[12] 0 -+ 0 -***** Signal chany[1][1]_midout[13] density = 0, probability=0.***** -Vchany[1][1]_midout[13] chany[1][1]_midout[13] 0 -+ 0 -***** Signal chany[1][1]_midout[14] density = 0, probability=0.***** -Vchany[1][1]_midout[14] chany[1][1]_midout[14] 0 -+ 0 -***** Signal chany[1][1]_midout[15] density = 0, probability=0.***** -Vchany[1][1]_midout[15] chany[1][1]_midout[15] 0 -+ 0 -***** Signal chany[1][1]_midout[16] density = 0, probability=0.***** -Vchany[1][1]_midout[16] chany[1][1]_midout[16] 0 -+ 0 -***** Signal chany[1][1]_midout[17] density = 0, probability=0.***** -Vchany[1][1]_midout[17] chany[1][1]_midout[17] 0 -+ 0 -***** Signal chany[1][1]_midout[18] density = 0, probability=0.***** -Vchany[1][1]_midout[18] chany[1][1]_midout[18] 0 -+ 0 -***** Signal chany[1][1]_midout[19] density = 0, probability=0.***** -Vchany[1][1]_midout[19] chany[1][1]_midout[19] 0 -+ 0 -***** Signal chany[1][1]_midout[20] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_midout[20] chany[1][1]_midout[20] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[1][1]_midout[21] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_midout[21] chany[1][1]_midout[21] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[1][1]_midout[22] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_midout[22] chany[1][1]_midout[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[1][1]_midout[23] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_midout[23] chany[1][1]_midout[23] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[1][1]_midout[24] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_midout[24] chany[1][1]_midout[24] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[1][1]_midout[25] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_midout[25] chany[1][1]_midout[25] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[1][1]_midout[26] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_midout[26] chany[1][1]_midout[26] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[1][1]_midout[27] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_midout[27] chany[1][1]_midout[27] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[1][1]_midout[28] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_midout[28] chany[1][1]_midout[28] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[1][1]_midout[29] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_midout[29] chany[1][1]_midout[29] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal chany[1][1]_midout[30] density = 0, probability=0.***** -Vchany[1][1]_midout[30] chany[1][1]_midout[30] 0 -+ 0 -***** Signal chany[1][1]_midout[31] density = 0, probability=0.***** -Vchany[1][1]_midout[31] chany[1][1]_midout[31] 0 -+ 0 -***** Signal chany[1][1]_midout[32] density = 0, probability=0.***** -Vchany[1][1]_midout[32] chany[1][1]_midout[32] 0 -+ 0 -***** Signal chany[1][1]_midout[33] density = 0, probability=0.***** -Vchany[1][1]_midout[33] chany[1][1]_midout[33] 0 -+ 0 -***** Signal chany[1][1]_midout[34] density = 0, probability=0.***** -Vchany[1][1]_midout[34] chany[1][1]_midout[34] 0 -+ 0 -***** Signal chany[1][1]_midout[35] density = 0, probability=0.***** -Vchany[1][1]_midout[35] chany[1][1]_midout[35] 0 -+ 0 -***** Signal chany[1][1]_midout[36] density = 0, probability=0.***** -Vchany[1][1]_midout[36] chany[1][1]_midout[36] 0 -+ 0 -***** Signal chany[1][1]_midout[37] density = 0, probability=0.***** -Vchany[1][1]_midout[37] chany[1][1]_midout[37] 0 -+ 0 -***** Signal chany[1][1]_midout[38] density = 0, probability=0.***** -Vchany[1][1]_midout[38] chany[1][1]_midout[38] 0 -+ 0 -***** Signal chany[1][1]_midout[39] density = 0, probability=0.***** -Vchany[1][1]_midout[39] chany[1][1]_midout[39] 0 -+ 0 -***** Signal chany[1][1]_midout[40] density = 0, probability=0.***** -Vchany[1][1]_midout[40] chany[1][1]_midout[40] 0 -+ 0 -***** Signal chany[1][1]_midout[41] density = 0, probability=0.***** -Vchany[1][1]_midout[41] chany[1][1]_midout[41] 0 -+ 0 -***** Signal chany[1][1]_midout[42] density = 0, probability=0.***** -Vchany[1][1]_midout[42] chany[1][1]_midout[42] 0 -+ 0 -***** Signal chany[1][1]_midout[43] density = 0, probability=0.***** -Vchany[1][1]_midout[43] chany[1][1]_midout[43] 0 -+ 0 -***** Signal chany[1][1]_midout[44] density = 0, probability=0.***** -Vchany[1][1]_midout[44] chany[1][1]_midout[44] 0 -+ 0 -***** Signal chany[1][1]_midout[45] density = 0, probability=0.***** -Vchany[1][1]_midout[45] chany[1][1]_midout[45] 0 -+ 0 -***** Signal chany[1][1]_midout[46] density = 0, probability=0.***** -Vchany[1][1]_midout[46] chany[1][1]_midout[46] 0 -+ 0 -***** Signal chany[1][1]_midout[47] density = 0, probability=0.***** -Vchany[1][1]_midout[47] chany[1][1]_midout[47] 0 -+ 0 -***** Signal chany[1][1]_midout[48] density = 0, probability=0.***** -Vchany[1][1]_midout[48] chany[1][1]_midout[48] 0 -+ 0 -***** Signal chany[1][1]_midout[49] density = 0, probability=0.***** -Vchany[1][1]_midout[49] chany[1][1]_midout[49] 0 -+ 0 -***** Signal chany[1][1]_midout[50] density = 0, probability=0.***** -Vchany[1][1]_midout[50] chany[1][1]_midout[50] 0 -+ 0 -***** Signal chany[1][1]_midout[51] density = 0, probability=0.***** -Vchany[1][1]_midout[51] chany[1][1]_midout[51] 0 -+ 0 -***** Signal chany[1][1]_midout[52] density = 0, probability=0.***** -Vchany[1][1]_midout[52] chany[1][1]_midout[52] 0 -+ 0 -***** Signal chany[1][1]_midout[53] density = 0, probability=0.***** -Vchany[1][1]_midout[53] chany[1][1]_midout[53] 0 -+ 0 -***** Signal chany[1][1]_midout[54] density = 0, probability=0.***** -Vchany[1][1]_midout[54] chany[1][1]_midout[54] 0 -+ 0 -***** Signal chany[1][1]_midout[55] density = 0, probability=0.***** -Vchany[1][1]_midout[55] chany[1][1]_midout[55] 0 -+ 0 -***** Signal chany[1][1]_midout[56] density = 0, probability=0.***** -Vchany[1][1]_midout[56] chany[1][1]_midout[56] 0 -+ 0 -***** Signal chany[1][1]_midout[57] density = 0, probability=0.***** -Vchany[1][1]_midout[57] chany[1][1]_midout[57] 0 -+ 0 -***** Signal chany[1][1]_midout[58] density = 0, probability=0.***** -Vchany[1][1]_midout[58] chany[1][1]_midout[58] 0 -+ 0 -***** Signal chany[1][1]_midout[59] density = 0, probability=0.***** -Vchany[1][1]_midout[59] chany[1][1]_midout[59] 0 -+ 0 -***** Signal chany[1][1]_midout[60] density = 0, probability=0.***** -Vchany[1][1]_midout[60] chany[1][1]_midout[60] 0 -+ 0 -***** Signal chany[1][1]_midout[61] density = 0, probability=0.***** -Vchany[1][1]_midout[61] chany[1][1]_midout[61] 0 -+ 0 -***** Signal chany[1][1]_midout[62] density = 0, probability=0.***** -Vchany[1][1]_midout[62] chany[1][1]_midout[62] 0 -+ 0 -***** Signal chany[1][1]_midout[63] density = 0, probability=0.***** -Vchany[1][1]_midout[63] chany[1][1]_midout[63] 0 -+ 0 -***** Signal chany[1][1]_midout[64] density = 0, probability=0.***** -Vchany[1][1]_midout[64] chany[1][1]_midout[64] 0 -+ 0 -***** Signal chany[1][1]_midout[65] density = 0, probability=0.***** -Vchany[1][1]_midout[65] chany[1][1]_midout[65] 0 -+ 0 -***** Signal chany[1][1]_midout[66] density = 0, probability=0.***** -Vchany[1][1]_midout[66] chany[1][1]_midout[66] 0 -+ 0 -***** Signal chany[1][1]_midout[67] density = 0, probability=0.***** -Vchany[1][1]_midout[67] chany[1][1]_midout[67] 0 -+ 0 -***** Signal chany[1][1]_midout[68] density = 0, probability=0.***** -Vchany[1][1]_midout[68] chany[1][1]_midout[68] 0 -+ 0 -***** Signal chany[1][1]_midout[69] density = 0, probability=0.***** -Vchany[1][1]_midout[69] chany[1][1]_midout[69] 0 -+ 0 -***** Signal chany[1][1]_midout[70] density = 0, probability=0.***** -Vchany[1][1]_midout[70] chany[1][1]_midout[70] 0 -+ 0 -***** Signal chany[1][1]_midout[71] density = 0, probability=0.***** -Vchany[1][1]_midout[71] chany[1][1]_midout[71] 0 -+ 0 -***** Signal chany[1][1]_midout[72] density = 0, probability=0.***** -Vchany[1][1]_midout[72] chany[1][1]_midout[72] 0 -+ 0 -***** Signal chany[1][1]_midout[73] density = 0, probability=0.***** -Vchany[1][1]_midout[73] chany[1][1]_midout[73] 0 -+ 0 -***** Signal chany[1][1]_midout[74] density = 0, probability=0.***** -Vchany[1][1]_midout[74] chany[1][1]_midout[74] 0 -+ 0 -***** Signal chany[1][1]_midout[75] density = 0, probability=0.***** -Vchany[1][1]_midout[75] chany[1][1]_midout[75] 0 -+ 0 -***** Signal chany[1][1]_midout[76] density = 0, probability=0.***** -Vchany[1][1]_midout[76] chany[1][1]_midout[76] 0 -+ 0 -***** Signal chany[1][1]_midout[77] density = 0, probability=0.***** -Vchany[1][1]_midout[77] chany[1][1]_midout[77] 0 -+ 0 -***** Signal chany[1][1]_midout[78] density = 0, probability=0.***** -Vchany[1][1]_midout[78] chany[1][1]_midout[78] 0 -+ 0 -***** Signal chany[1][1]_midout[79] density = 0, probability=0.***** -Vchany[1][1]_midout[79] chany[1][1]_midout[79] 0 -+ 0 -***** Signal chany[1][1]_midout[80] density = 0, probability=0.***** -Vchany[1][1]_midout[80] chany[1][1]_midout[80] 0 -+ 0 -***** Signal chany[1][1]_midout[81] density = 0, probability=0.***** -Vchany[1][1]_midout[81] chany[1][1]_midout[81] 0 -+ 0 -***** Signal chany[1][1]_midout[82] density = 0, probability=0.***** -Vchany[1][1]_midout[82] chany[1][1]_midout[82] 0 -+ 0 -***** Signal chany[1][1]_midout[83] density = 0, probability=0.***** -Vchany[1][1]_midout[83] chany[1][1]_midout[83] 0 -+ 0 -***** Signal chany[1][1]_midout[84] density = 0, probability=0.***** -Vchany[1][1]_midout[84] chany[1][1]_midout[84] 0 -+ 0 -***** Signal chany[1][1]_midout[85] density = 0, probability=0.***** -Vchany[1][1]_midout[85] chany[1][1]_midout[85] 0 -+ 0 -***** Signal chany[1][1]_midout[86] density = 0, probability=0.***** -Vchany[1][1]_midout[86] chany[1][1]_midout[86] 0 -+ 0 -***** Signal chany[1][1]_midout[87] density = 0, probability=0.***** -Vchany[1][1]_midout[87] chany[1][1]_midout[87] 0 -+ 0 -***** Signal chany[1][1]_midout[88] density = 0, probability=0.***** -Vchany[1][1]_midout[88] chany[1][1]_midout[88] 0 -+ 0 -***** Signal chany[1][1]_midout[89] density = 0, probability=0.***** -Vchany[1][1]_midout[89] chany[1][1]_midout[89] 0 -+ 0 -***** Signal chany[1][1]_midout[90] density = 0, probability=0.***** -Vchany[1][1]_midout[90] chany[1][1]_midout[90] 0 -+ 0 -***** Signal chany[1][1]_midout[91] density = 0, probability=0.***** -Vchany[1][1]_midout[91] chany[1][1]_midout[91] 0 -+ 0 -***** Signal chany[1][1]_midout[92] density = 0, probability=0.***** -Vchany[1][1]_midout[92] chany[1][1]_midout[92] 0 -+ 0 -***** Signal chany[1][1]_midout[93] density = 0, probability=0.***** -Vchany[1][1]_midout[93] chany[1][1]_midout[93] 0 -+ 0 -***** Signal chany[1][1]_midout[94] density = 0, probability=0.***** -Vchany[1][1]_midout[94] chany[1][1]_midout[94] 0 -+ 0 -***** Signal chany[1][1]_midout[95] density = 0, probability=0.***** -Vchany[1][1]_midout[95] chany[1][1]_midout[95] 0 -+ 0 -***** Signal chany[1][1]_midout[96] density = 0, probability=0.***** -Vchany[1][1]_midout[96] chany[1][1]_midout[96] 0 -+ 0 -***** Signal chany[1][1]_midout[97] density = 0, probability=0.***** -Vchany[1][1]_midout[97] chany[1][1]_midout[97] 0 -+ 0 -***** Signal chany[1][1]_midout[98] density = 0, probability=0.***** -Vchany[1][1]_midout[98] chany[1][1]_midout[98] 0 -+ 0 -***** Signal chany[1][1]_midout[99] density = 0, probability=0.***** -Vchany[1][1]_midout[99] chany[1][1]_midout[99] 0 -+ 0 -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* IO_TYPE loads ******* -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[0]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[4] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[5] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[6] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[7] gvdd_load 0 inv size=1 -Xload_inv[8]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[8] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[9] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[10] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[11] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[12] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[13] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[14] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[15] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[16] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[17] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[18] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[19] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[20] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[21] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[22] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[23] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[24] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[25] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[26] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[27] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[28] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[29] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[30] gvdd_load 0 inv size=1 -Xload_inv[31]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[31] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[32] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[33] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[34] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[35] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[36] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[37] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[38] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[39] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[40] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[41] gvdd_load 0 inv size=1 -Xload_inv[42]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[42] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[43] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[44] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[45] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[46] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[47] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[48] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[49] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[50] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[51] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[52] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[53] gvdd_load 0 inv size=1 -Xload_inv[54]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[54] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[55] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[56] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[57] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[58] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 grid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[60]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[1] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[2] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[3] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[4] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[5] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[6] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[7] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[8] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[9] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[10] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[11] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[12] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[13] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[14] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[15] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[16] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[17] gvdd_load 0 inv size=1 -Xload_inv[78]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[18] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[19] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[20] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[21] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[22] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[23] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[24] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[25] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[26] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[27] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[28] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[29] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[30] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[31] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[32] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[33] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[34] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[35] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[36] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[37] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[38] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[39] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[40] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[41] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[42] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[43] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[44] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[45] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[46] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[47] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[48] gvdd_load 0 inv size=1 -Xload_inv[109]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[49] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[50] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[51] gvdd_load 0 inv size=1 -Xload_inv[112]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[52] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[53] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[54] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[55] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[56] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[57] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[58] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 grid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[120]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[3] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[4] gvdd_load 0 inv size=1 -Xload_inv[125]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[5] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[6] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[7] gvdd_load 0 inv size=1 -Xload_inv[128]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[8] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[9] gvdd_load 0 inv size=1 -Xload_inv[130]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[10] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[11] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[12] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[13] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[14] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[15] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[16] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[17] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[18] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[19] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[20] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[21] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[22] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[23] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[24] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[25] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[26] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[27] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[28] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[29] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[30] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[31] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[32] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[33] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[34] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[35] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[36] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[37] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[38] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[39] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[40] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[41] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[42] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[43] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[44] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[45] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[46] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[47] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[48] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[49] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[50] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[51] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[52] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[53] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[54] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[55] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[56] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[57] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[58] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 grid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[180]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[0] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[1] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[2] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[3] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[4] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[5] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[6] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[7] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[8] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[9] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[10] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[11] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[12] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[13] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[14] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[15] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[16] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[17] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[18] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[19] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[20] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[21] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[22] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[23] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[24] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[25] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[26] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[27] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[28] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[29] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[30] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[31] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[32] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[33] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[34] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[35] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[36] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[37] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[38] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[39] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[40] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[41] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[42] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[43] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[44] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[45] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[46] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[47] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[48] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[49] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[50] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[51] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[52] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[53] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[54] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[55] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[56] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[57] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[58] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 grid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[240]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[0] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[1] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[2] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[3] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[4] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[5] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[6] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[7] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[8] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[9] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[10] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[11] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[12] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[13] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[14] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[15] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[16] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[17] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[18] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[19] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[20] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[21] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[22] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[23] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[24] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[25] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[26] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[27] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[28] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[29] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[30] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[31] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[32] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[33] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[34] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[35] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[36] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[37] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[38] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[39] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[40] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[41] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[42] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[43] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[44] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[45] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[46] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[47] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[48] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[49] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[50] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[51] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[52] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[53] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[54] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[55] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[56] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[57] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[58] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 grid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[300]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[0] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[1] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[2] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[3] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[4] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[5] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[6] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[7] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[8] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[9] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[10] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[11] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[12] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[13] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[14] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[15] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[16] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[17] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[18] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[19] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[20] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[21] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[22] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[23] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[24] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[25] gvdd_load 0 inv size=1 -Xload_inv[326]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[26] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[27] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[28] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[29] gvdd_load 0 inv size=1 -Xload_inv[330]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[30] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[31] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[32] gvdd_load 0 inv size=1 -Xload_inv[333]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[33] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[34] gvdd_load 0 inv size=1 -Xload_inv[335]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[35] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[36] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[37] gvdd_load 0 inv size=1 -Xload_inv[338]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[38] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[39] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[40] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[41] gvdd_load 0 inv size=1 -Xload_inv[342]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[42] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[43] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[44] gvdd_load 0 inv size=1 -Xload_inv[345]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[45] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[46] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[47] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[48] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[49] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[50] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[51] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[52] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[53] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[54] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[55] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[56] gvdd_load 0 inv size=1 -Xload_inv[357]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[57] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[58] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 grid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[360]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[0] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[1] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[2] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[3] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[4] gvdd_load 0 inv size=1 -Xload_inv[365]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[5] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[6] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[7] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[8] gvdd_load 0 inv size=1 -Xload_inv[369]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[9] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[10] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[11] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[12] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[13] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[14] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[15] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[16] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[17] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[18] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[19] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[20] gvdd_load 0 inv size=1 -Xload_inv[381]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[21] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[22] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[23] gvdd_load 0 inv size=1 -Xload_inv[384]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[24] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[25] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[26] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[27] gvdd_load 0 inv size=1 -Xload_inv[388]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[28] gvdd_load 0 inv size=1 -Xload_inv[389]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[29] gvdd_load 0 inv size=1 -Xload_inv[390]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[30] gvdd_load 0 inv size=1 -Xload_inv[391]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[31] gvdd_load 0 inv size=1 -Xload_inv[392]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[32] gvdd_load 0 inv size=1 -Xload_inv[393]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[33] gvdd_load 0 inv size=1 -Xload_inv[394]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[34] gvdd_load 0 inv size=1 -Xload_inv[395]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[35] gvdd_load 0 inv size=1 -Xload_inv[396]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[36] gvdd_load 0 inv size=1 -Xload_inv[397]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[37] gvdd_load 0 inv size=1 -Xload_inv[398]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[38] gvdd_load 0 inv size=1 -Xload_inv[399]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[39] gvdd_load 0 inv size=1 -Xload_inv[400]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[40] gvdd_load 0 inv size=1 -Xload_inv[401]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[41] gvdd_load 0 inv size=1 -Xload_inv[402]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[42] gvdd_load 0 inv size=1 -Xload_inv[403]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[43] gvdd_load 0 inv size=1 -Xload_inv[404]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[44] gvdd_load 0 inv size=1 -Xload_inv[405]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[45] gvdd_load 0 inv size=1 -Xload_inv[406]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[46] gvdd_load 0 inv size=1 -Xload_inv[407]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[47] gvdd_load 0 inv size=1 -Xload_inv[408]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[48] gvdd_load 0 inv size=1 -Xload_inv[409]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[49] gvdd_load 0 inv size=1 -Xload_inv[410]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[50] gvdd_load 0 inv size=1 -Xload_inv[411]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[51] gvdd_load 0 inv size=1 -Xload_inv[412]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[52] gvdd_load 0 inv size=1 -Xload_inv[413]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[53] gvdd_load 0 inv size=1 -Xload_inv[414]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[54] gvdd_load 0 inv size=1 -Xload_inv[415]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[55] gvdd_load 0 inv size=1 -Xload_inv[416]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[56] gvdd_load 0 inv size=1 -Xload_inv[417]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[57] gvdd_load 0 inv size=1 -Xload_inv[418]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[58] gvdd_load 0 inv size=1 -Xload_inv[419]_no0 grid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[420]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[0] gvdd_load 0 inv size=1 -Xload_inv[421]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[1] gvdd_load 0 inv size=1 -Xload_inv[422]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[2] gvdd_load 0 inv size=1 -Xload_inv[423]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[3] gvdd_load 0 inv size=1 -Xload_inv[424]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[4] gvdd_load 0 inv size=1 -Xload_inv[425]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[5] gvdd_load 0 inv size=1 -Xload_inv[426]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[6] gvdd_load 0 inv size=1 -Xload_inv[427]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[7] gvdd_load 0 inv size=1 -Xload_inv[428]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[8] gvdd_load 0 inv size=1 -Xload_inv[429]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[9] gvdd_load 0 inv size=1 -Xload_inv[430]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[10] gvdd_load 0 inv size=1 -Xload_inv[431]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[11] gvdd_load 0 inv size=1 -Xload_inv[432]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[12] gvdd_load 0 inv size=1 -Xload_inv[433]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[13] gvdd_load 0 inv size=1 -Xload_inv[434]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[14] gvdd_load 0 inv size=1 -Xload_inv[435]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[15] gvdd_load 0 inv size=1 -Xload_inv[436]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[16] gvdd_load 0 inv size=1 -Xload_inv[437]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[17] gvdd_load 0 inv size=1 -Xload_inv[438]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[18] gvdd_load 0 inv size=1 -Xload_inv[439]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[19] gvdd_load 0 inv size=1 -Xload_inv[440]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[20] gvdd_load 0 inv size=1 -Xload_inv[441]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[21] gvdd_load 0 inv size=1 -Xload_inv[442]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[22] gvdd_load 0 inv size=1 -Xload_inv[443]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[23] gvdd_load 0 inv size=1 -Xload_inv[444]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[24] gvdd_load 0 inv size=1 -Xload_inv[445]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[25] gvdd_load 0 inv size=1 -Xload_inv[446]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[26] gvdd_load 0 inv size=1 -Xload_inv[447]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[27] gvdd_load 0 inv size=1 -Xload_inv[448]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[28] gvdd_load 0 inv size=1 -Xload_inv[449]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[29] gvdd_load 0 inv size=1 -Xload_inv[450]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[30] gvdd_load 0 inv size=1 -Xload_inv[451]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[31] gvdd_load 0 inv size=1 -Xload_inv[452]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[32] gvdd_load 0 inv size=1 -Xload_inv[453]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[33] gvdd_load 0 inv size=1 -Xload_inv[454]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[34] gvdd_load 0 inv size=1 -Xload_inv[455]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[35] gvdd_load 0 inv size=1 -Xload_inv[456]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[36] gvdd_load 0 inv size=1 -Xload_inv[457]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[37] gvdd_load 0 inv size=1 -Xload_inv[458]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[38] gvdd_load 0 inv size=1 -Xload_inv[459]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[39] gvdd_load 0 inv size=1 -Xload_inv[460]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[40] gvdd_load 0 inv size=1 -Xload_inv[461]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[41] gvdd_load 0 inv size=1 -Xload_inv[462]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[42] gvdd_load 0 inv size=1 -Xload_inv[463]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[43] gvdd_load 0 inv size=1 -Xload_inv[464]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[44] gvdd_load 0 inv size=1 -Xload_inv[465]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[45] gvdd_load 0 inv size=1 -Xload_inv[466]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[46] gvdd_load 0 inv size=1 -Xload_inv[467]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[47] gvdd_load 0 inv size=1 -Xload_inv[468]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[48] gvdd_load 0 inv size=1 -Xload_inv[469]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[49] gvdd_load 0 inv size=1 -Xload_inv[470]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[50] gvdd_load 0 inv size=1 -Xload_inv[471]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[51] gvdd_load 0 inv size=1 -Xload_inv[472]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[52] gvdd_load 0 inv size=1 -Xload_inv[473]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[53] gvdd_load 0 inv size=1 -Xload_inv[474]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[54] gvdd_load 0 inv size=1 -Xload_inv[475]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[55] gvdd_load 0 inv size=1 -Xload_inv[476]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[56] gvdd_load 0 inv size=1 -Xload_inv[477]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[57] gvdd_load 0 inv size=1 -Xload_inv[478]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[58] gvdd_load 0 inv size=1 -Xload_inv[479]_no0 grid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[480]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[0] gvdd_load 0 inv size=1 -Xload_inv[481]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[1] gvdd_load 0 inv size=1 -Xload_inv[482]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[2] gvdd_load 0 inv size=1 -Xload_inv[483]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[3] gvdd_load 0 inv size=1 -Xload_inv[484]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[4] gvdd_load 0 inv size=1 -Xload_inv[485]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[5] gvdd_load 0 inv size=1 -Xload_inv[486]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[6] gvdd_load 0 inv size=1 -Xload_inv[487]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[7] gvdd_load 0 inv size=1 -Xload_inv[488]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[8] gvdd_load 0 inv size=1 -Xload_inv[489]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[9] gvdd_load 0 inv size=1 -Xload_inv[490]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[10] gvdd_load 0 inv size=1 -Xload_inv[491]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[11] gvdd_load 0 inv size=1 -Xload_inv[492]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[12] gvdd_load 0 inv size=1 -Xload_inv[493]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[13] gvdd_load 0 inv size=1 -Xload_inv[494]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[14] gvdd_load 0 inv size=1 -Xload_inv[495]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[15] gvdd_load 0 inv size=1 -Xload_inv[496]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[16] gvdd_load 0 inv size=1 -Xload_inv[497]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[17] gvdd_load 0 inv size=1 -Xload_inv[498]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[18] gvdd_load 0 inv size=1 -Xload_inv[499]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[19] gvdd_load 0 inv size=1 -Xload_inv[500]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[20] gvdd_load 0 inv size=1 -Xload_inv[501]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[21] gvdd_load 0 inv size=1 -Xload_inv[502]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[22] gvdd_load 0 inv size=1 -Xload_inv[503]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[23] gvdd_load 0 inv size=1 -Xload_inv[504]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[24] gvdd_load 0 inv size=1 -Xload_inv[505]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[25] gvdd_load 0 inv size=1 -Xload_inv[506]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[26] gvdd_load 0 inv size=1 -Xload_inv[507]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[27] gvdd_load 0 inv size=1 -Xload_inv[508]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[28] gvdd_load 0 inv size=1 -Xload_inv[509]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[29] gvdd_load 0 inv size=1 -Xload_inv[510]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[30] gvdd_load 0 inv size=1 -Xload_inv[511]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[31] gvdd_load 0 inv size=1 -Xload_inv[512]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[32] gvdd_load 0 inv size=1 -Xload_inv[513]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[33] gvdd_load 0 inv size=1 -Xload_inv[514]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[34] gvdd_load 0 inv size=1 -Xload_inv[515]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[35] gvdd_load 0 inv size=1 -Xload_inv[516]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[36] gvdd_load 0 inv size=1 -Xload_inv[517]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[37] gvdd_load 0 inv size=1 -Xload_inv[518]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[38] gvdd_load 0 inv size=1 -Xload_inv[519]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[39] gvdd_load 0 inv size=1 -Xload_inv[520]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[40] gvdd_load 0 inv size=1 -Xload_inv[521]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[41] gvdd_load 0 inv size=1 -Xload_inv[522]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[42] gvdd_load 0 inv size=1 -Xload_inv[523]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[43] gvdd_load 0 inv size=1 -Xload_inv[524]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[44] gvdd_load 0 inv size=1 -Xload_inv[525]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[45] gvdd_load 0 inv size=1 -Xload_inv[526]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[46] gvdd_load 0 inv size=1 -Xload_inv[527]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[47] gvdd_load 0 inv size=1 -Xload_inv[528]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[48] gvdd_load 0 inv size=1 -Xload_inv[529]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[49] gvdd_load 0 inv size=1 -Xload_inv[530]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[50] gvdd_load 0 inv size=1 -Xload_inv[531]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[51] gvdd_load 0 inv size=1 -Xload_inv[532]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[52] gvdd_load 0 inv size=1 -Xload_inv[533]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[53] gvdd_load 0 inv size=1 -Xload_inv[534]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[54] gvdd_load 0 inv size=1 -Xload_inv[535]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[55] gvdd_load 0 inv size=1 -Xload_inv[536]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[56] gvdd_load 0 inv size=1 -Xload_inv[537]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[57] gvdd_load 0 inv size=1 -Xload_inv[538]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[58] gvdd_load 0 inv size=1 -Xload_inv[539]_no0 grid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -******* Normal TYPE loads ******* -Xload_inv[540]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[0] gvdd_load 0 inv size=1 -Xload_inv[541]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[1] gvdd_load 0 inv size=1 -Xload_inv[542]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[2] gvdd_load 0 inv size=1 -Xload_inv[543]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[3] gvdd_load 0 inv size=1 -Xload_inv[544]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[4] gvdd_load 0 inv size=1 -Xload_inv[545]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[5] gvdd_load 0 inv size=1 -Xload_inv[546]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[6] gvdd_load 0 inv size=1 -Xload_inv[547]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[7] gvdd_load 0 inv size=1 -Xload_inv[548]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[8] gvdd_load 0 inv size=1 -Xload_inv[549]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[9] gvdd_load 0 inv size=1 -Xload_inv[550]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[10] gvdd_load 0 inv size=1 -Xload_inv[551]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[11] gvdd_load 0 inv size=1 -Xload_inv[552]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[12] gvdd_load 0 inv size=1 -Xload_inv[553]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[13] gvdd_load 0 inv size=1 -Xload_inv[554]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[14] gvdd_load 0 inv size=1 -Xload_inv[555]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[15] gvdd_load 0 inv size=1 -Xload_inv[556]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[16] gvdd_load 0 inv size=1 -Xload_inv[557]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[17] gvdd_load 0 inv size=1 -Xload_inv[558]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[18] gvdd_load 0 inv size=1 -Xload_inv[559]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[19] gvdd_load 0 inv size=1 -Xload_inv[560]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[20] gvdd_load 0 inv size=1 -Xload_inv[561]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[21] gvdd_load 0 inv size=1 -Xload_inv[562]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[22] gvdd_load 0 inv size=1 -Xload_inv[563]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[23] gvdd_load 0 inv size=1 -Xload_inv[564]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[24] gvdd_load 0 inv size=1 -Xload_inv[565]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[25] gvdd_load 0 inv size=1 -Xload_inv[566]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[26] gvdd_load 0 inv size=1 -Xload_inv[567]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[27] gvdd_load 0 inv size=1 -Xload_inv[568]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[28] gvdd_load 0 inv size=1 -Xload_inv[569]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[29] gvdd_load 0 inv size=1 -Xload_inv[570]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[30] gvdd_load 0 inv size=1 -Xload_inv[571]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[31] gvdd_load 0 inv size=1 -Xload_inv[572]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[32] gvdd_load 0 inv size=1 -Xload_inv[573]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[33] gvdd_load 0 inv size=1 -Xload_inv[574]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[34] gvdd_load 0 inv size=1 -Xload_inv[575]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[35] gvdd_load 0 inv size=1 -Xload_inv[576]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[36] gvdd_load 0 inv size=1 -Xload_inv[577]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[37] gvdd_load 0 inv size=1 -Xload_inv[578]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[38] gvdd_load 0 inv size=1 -Xload_inv[579]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[39] gvdd_load 0 inv size=1 -Xload_inv[580]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[40] gvdd_load 0 inv size=1 -Xload_inv[581]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[41] gvdd_load 0 inv size=1 -Xload_inv[582]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[42] gvdd_load 0 inv size=1 -Xload_inv[583]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[43] gvdd_load 0 inv size=1 -Xload_inv[584]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[44] gvdd_load 0 inv size=1 -Xload_inv[585]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[45] gvdd_load 0 inv size=1 -Xload_inv[586]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[46] gvdd_load 0 inv size=1 -Xload_inv[587]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[47] gvdd_load 0 inv size=1 -Xload_inv[588]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[48] gvdd_load 0 inv size=1 -Xload_inv[589]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[49] gvdd_load 0 inv size=1 -Xload_inv[590]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[50] gvdd_load 0 inv size=1 -Xload_inv[591]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[51] gvdd_load 0 inv size=1 -Xload_inv[592]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[52] gvdd_load 0 inv size=1 -Xload_inv[593]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[53] gvdd_load 0 inv size=1 -Xload_inv[594]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[54] gvdd_load 0 inv size=1 -Xload_inv[595]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[55] gvdd_load 0 inv size=1 -Xload_inv[596]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[56] gvdd_load 0 inv size=1 -Xload_inv[597]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[57] gvdd_load 0 inv size=1 -Xload_inv[598]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[58] gvdd_load 0 inv size=1 -Xload_inv[599]_no0 grid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37]_out[59] gvdd_load 0 inv size=1 -******* END loads ******* - -***** Voltage supplies ***** -***** Voltage supplies ***** -Vgvdd_cb[1][1] gvdd_cby[1][1] 0 vsp -Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_cb avg p(Vgvdd_cb[1][1]) from=0 to='clock_period' -.meas tran leakage_power_sram_cb avg p(Vgvdd_sram_cbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_cb avg p(Vgvdd_cb[1][1]) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_cb param='dynamic_power_cb*clock_period' -.meas tran dynamic_power_sram_cb avg p(Vgvdd_sram_cbs) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sram_cb param='dynamic_power_sram_cb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_2/example_2.bitstream b/examples/spice_test_example_2/example_2.bitstream deleted file mode 100644 index c2374dc01..000000000 --- a/examples/spice_test_example_2/example_2.bitstream +++ /dev/null @@ -1,2658 +0,0 @@ -0, // Configuration bit No.: 2665, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2658 -0, // Configuration bit No.: 2664, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2658 -0, // Configuration bit No.: 2663, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2658 -1, // Configuration bit No.: 2662, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2658 -0, // Configuration bit No.: 2661, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2658 -0, // Configuration bit No.: 2660, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2658 -0, // Configuration bit No.: 2659, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2658 -1, // Configuration bit No.: 2658, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2658 -0, // Configuration bit No.: 2657, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2650 -0, // Configuration bit No.: 2656, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2650 -0, // Configuration bit No.: 2655, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2650 -1, // Configuration bit No.: 2654, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2650 -0, // Configuration bit No.: 2653, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2650 -0, // Configuration bit No.: 2652, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2650 -0, // Configuration bit No.: 2651, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2650 -1, // Configuration bit No.: 2650, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2650 -0, // Configuration bit No.: 2649, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2642 -0, // Configuration bit No.: 2648, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2642 -0, // Configuration bit No.: 2647, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2642 -1, // Configuration bit No.: 2646, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2642 -0, // Configuration bit No.: 2645, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2642 -0, // Configuration bit No.: 2644, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2642 -0, // Configuration bit No.: 2643, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2642 -1, // Configuration bit No.: 2642, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2642 -0, // Configuration bit No.: 2641, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2634 -0, // Configuration bit No.: 2640, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2634 -0, // Configuration bit No.: 2639, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2634 -1, // Configuration bit No.: 2638, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2634 -0, // Configuration bit No.: 2637, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2634 -0, // Configuration bit No.: 2636, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2634 -0, // Configuration bit No.: 2635, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2634 -1, // Configuration bit No.: 2634, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2634 -0, // Configuration bit No.: 2633, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2626 -0, // Configuration bit No.: 2632, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2626 -0, // Configuration bit No.: 2631, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2626 -1, // Configuration bit No.: 2630, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2626 -0, // Configuration bit No.: 2629, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2626 -0, // Configuration bit No.: 2628, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2626 -0, // Configuration bit No.: 2627, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2626 -1, // Configuration bit No.: 2626, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2626 -0, // Configuration bit No.: 2625, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2618 -0, // Configuration bit No.: 2624, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2618 -0, // Configuration bit No.: 2623, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2618 -1, // Configuration bit No.: 2622, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2618 -0, // Configuration bit No.: 2621, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2618 -0, // Configuration bit No.: 2620, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2618 -0, // Configuration bit No.: 2619, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2618 -1, // Configuration bit No.: 2618, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2618 -0, // Configuration bit No.: 2617, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2610 -0, // Configuration bit No.: 2616, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2610 -0, // Configuration bit No.: 2615, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2610 -1, // Configuration bit No.: 2614, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2610 -0, // Configuration bit No.: 2613, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2610 -0, // Configuration bit No.: 2612, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2610 -0, // Configuration bit No.: 2611, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2610 -1, // Configuration bit No.: 2610, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2610 -0, // Configuration bit No.: 2609, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2602 -0, // Configuration bit No.: 2608, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2602 -0, // Configuration bit No.: 2607, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2602 -1, // Configuration bit No.: 2606, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2602 -0, // Configuration bit No.: 2605, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2602 -0, // Configuration bit No.: 2604, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2602 -0, // Configuration bit No.: 2603, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2602 -1, // Configuration bit No.: 2602, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2602 -0, // Configuration bit No.: 2601, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2594 -0, // Configuration bit No.: 2600, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2594 -0, // Configuration bit No.: 2599, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2594 -1, // Configuration bit No.: 2598, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2594 -0, // Configuration bit No.: 2597, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2594 -0, // Configuration bit No.: 2596, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2594 -0, // Configuration bit No.: 2595, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2594 -1, // Configuration bit No.: 2594, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2594 -0, // Configuration bit No.: 2593, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2586 -0, // Configuration bit No.: 2592, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2586 -0, // Configuration bit No.: 2591, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2586 -1, // Configuration bit No.: 2590, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2586 -0, // Configuration bit No.: 2589, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2586 -0, // Configuration bit No.: 2588, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2586 -0, // Configuration bit No.: 2587, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2586 -1, // Configuration bit No.: 2586, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2586 -0, // Configuration bit No.: 2585, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2578 -0, // Configuration bit No.: 2584, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2578 -0, // Configuration bit No.: 2583, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2578 -1, // Configuration bit No.: 2582, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2578 -0, // Configuration bit No.: 2581, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2578 -0, // Configuration bit No.: 2580, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2578 -0, // Configuration bit No.: 2579, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2578 -1, // Configuration bit No.: 2578, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2578 -0, // Configuration bit No.: 2577, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2570 -0, // Configuration bit No.: 2576, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2570 -0, // Configuration bit No.: 2575, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2570 -1, // Configuration bit No.: 2574, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2570 -0, // Configuration bit No.: 2573, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2570 -0, // Configuration bit No.: 2572, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2570 -0, // Configuration bit No.: 2571, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2570 -1, // Configuration bit No.: 2570, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2570 -0, // Configuration bit No.: 2569, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2562 -0, // Configuration bit No.: 2568, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2562 -0, // Configuration bit No.: 2567, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2562 -1, // Configuration bit No.: 2566, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2562 -0, // Configuration bit No.: 2565, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2562 -0, // Configuration bit No.: 2564, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2562 -0, // Configuration bit No.: 2563, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2562 -1, // Configuration bit No.: 2562, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2562 -0, // Configuration bit No.: 2561, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2554 -0, // Configuration bit No.: 2560, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2554 -0, // Configuration bit No.: 2559, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2554 -1, // Configuration bit No.: 2558, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2554 -0, // Configuration bit No.: 2557, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2554 -0, // Configuration bit No.: 2556, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2554 -0, // Configuration bit No.: 2555, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2554 -1, // Configuration bit No.: 2554, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2554 -0, // Configuration bit No.: 2553, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2546 -0, // Configuration bit No.: 2552, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2546 -0, // Configuration bit No.: 2551, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2546 -1, // Configuration bit No.: 2550, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2546 -0, // Configuration bit No.: 2549, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2546 -0, // Configuration bit No.: 2548, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2546 -0, // Configuration bit No.: 2547, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2546 -1, // Configuration bit No.: 2546, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2546 -0, // Configuration bit No.: 2545, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2538 -0, // Configuration bit No.: 2544, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2538 -0, // Configuration bit No.: 2543, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2538 -1, // Configuration bit No.: 2542, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2538 -0, // Configuration bit No.: 2541, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2538 -0, // Configuration bit No.: 2540, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2538 -0, // Configuration bit No.: 2539, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2538 -1, // Configuration bit No.: 2538, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2538 -0, // Configuration bit No.: 2537, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2530 -0, // Configuration bit No.: 2536, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2530 -0, // Configuration bit No.: 2535, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2530 -1, // Configuration bit No.: 2534, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2530 -0, // Configuration bit No.: 2533, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2530 -0, // Configuration bit No.: 2532, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2530 -0, // Configuration bit No.: 2531, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2530 -1, // Configuration bit No.: 2530, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2530 -0, // Configuration bit No.: 2529, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2522 -0, // Configuration bit No.: 2528, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2522 -0, // Configuration bit No.: 2527, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2522 -1, // Configuration bit No.: 2526, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2522 -0, // Configuration bit No.: 2525, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2522 -0, // Configuration bit No.: 2524, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2522 -0, // Configuration bit No.: 2523, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2522 -1, // Configuration bit No.: 2522, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2522 -0, // Configuration bit No.: 2521, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2514 -0, // Configuration bit No.: 2520, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2514 -0, // Configuration bit No.: 2519, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2514 -1, // Configuration bit No.: 2518, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2514 -0, // Configuration bit No.: 2517, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2514 -0, // Configuration bit No.: 2516, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2514 -0, // Configuration bit No.: 2515, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2514 -1, // Configuration bit No.: 2514, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2514 -0, // Configuration bit No.: 2513, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2506 -0, // Configuration bit No.: 2512, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2506 -0, // Configuration bit No.: 2511, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2506 -1, // Configuration bit No.: 2510, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2506 -0, // Configuration bit No.: 2509, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2506 -0, // Configuration bit No.: 2508, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2506 -0, // Configuration bit No.: 2507, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2506 -1, // Configuration bit No.: 2506, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2506 -0, // Configuration bit No.: 2505, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2498 -0, // Configuration bit No.: 2504, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2498 -0, // Configuration bit No.: 2503, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2498 -1, // Configuration bit No.: 2502, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2498 -0, // Configuration bit No.: 2501, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2498 -0, // Configuration bit No.: 2500, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2498 -0, // Configuration bit No.: 2499, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2498 -1, // Configuration bit No.: 2498, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2498 -0, // Configuration bit No.: 2497, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2490 -0, // Configuration bit No.: 2496, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2490 -0, // Configuration bit No.: 2495, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2490 -1, // Configuration bit No.: 2494, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2490 -0, // Configuration bit No.: 2493, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2490 -0, // Configuration bit No.: 2492, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2490 -0, // Configuration bit No.: 2491, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2490 -1, // Configuration bit No.: 2490, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2490 -0, // Configuration bit No.: 2489, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2482 -0, // Configuration bit No.: 2488, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2482 -0, // Configuration bit No.: 2487, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2482 -1, // Configuration bit No.: 2486, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2482 -0, // Configuration bit No.: 2485, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2482 -0, // Configuration bit No.: 2484, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2482 -0, // Configuration bit No.: 2483, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2482 -1, // Configuration bit No.: 2482, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2482 -0, // Configuration bit No.: 2481, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2474 -0, // Configuration bit No.: 2480, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2474 -0, // Configuration bit No.: 2479, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2474 -1, // Configuration bit No.: 2478, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2474 -0, // Configuration bit No.: 2477, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2474 -0, // Configuration bit No.: 2476, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2474 -0, // Configuration bit No.: 2475, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2474 -1, // Configuration bit No.: 2474, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2474 -0, // Configuration bit No.: 2473, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2466 -0, // Configuration bit No.: 2472, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2466 -0, // Configuration bit No.: 2471, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2466 -1, // Configuration bit No.: 2470, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2466 -0, // Configuration bit No.: 2469, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2466 -0, // Configuration bit No.: 2468, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2466 -0, // Configuration bit No.: 2467, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2466 -1, // Configuration bit No.: 2466, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2466 -0, // Configuration bit No.: 2465, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2458 -0, // Configuration bit No.: 2464, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2458 -0, // Configuration bit No.: 2463, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2458 -1, // Configuration bit No.: 2462, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2458 -0, // Configuration bit No.: 2461, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2458 -0, // Configuration bit No.: 2460, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2458 -0, // Configuration bit No.: 2459, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2458 -1, // Configuration bit No.: 2458, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2458 -0, // Configuration bit No.: 2457, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2450 -0, // Configuration bit No.: 2456, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2450 -0, // Configuration bit No.: 2455, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2450 -1, // Configuration bit No.: 2454, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2450 -0, // Configuration bit No.: 2453, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2450 -0, // Configuration bit No.: 2452, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2450 -0, // Configuration bit No.: 2451, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2450 -1, // Configuration bit No.: 2450, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2450 -0, // Configuration bit No.: 2449, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2442 -0, // Configuration bit No.: 2448, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2442 -0, // Configuration bit No.: 2447, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2442 -1, // Configuration bit No.: 2446, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2442 -0, // Configuration bit No.: 2445, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2442 -0, // Configuration bit No.: 2444, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2442 -0, // Configuration bit No.: 2443, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2442 -1, // Configuration bit No.: 2442, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2442 -0, // Configuration bit No.: 2441, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2434 -0, // Configuration bit No.: 2440, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2434 -0, // Configuration bit No.: 2439, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2434 -1, // Configuration bit No.: 2438, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2434 -0, // Configuration bit No.: 2437, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2434 -0, // Configuration bit No.: 2436, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2434 -0, // Configuration bit No.: 2435, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2434 -1, // Configuration bit No.: 2434, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2434 -0, // Configuration bit No.: 2433, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2426 -0, // Configuration bit No.: 2432, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2426 -0, // Configuration bit No.: 2431, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2426 -1, // Configuration bit No.: 2430, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2426 -0, // Configuration bit No.: 2429, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2426 -0, // Configuration bit No.: 2428, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2426 -0, // Configuration bit No.: 2427, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2426 -1, // Configuration bit No.: 2426, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2426 -0, // Configuration bit No.: 2425, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2418 -0, // Configuration bit No.: 2424, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2418 -0, // Configuration bit No.: 2423, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2418 -1, // Configuration bit No.: 2422, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2418 -0, // Configuration bit No.: 2421, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2418 -0, // Configuration bit No.: 2420, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2418 -0, // Configuration bit No.: 2419, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2418 -1, // Configuration bit No.: 2418, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2418 -0, // Configuration bit No.: 2417, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2410 -0, // Configuration bit No.: 2416, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2410 -0, // Configuration bit No.: 2415, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2410 -1, // Configuration bit No.: 2414, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2410 -0, // Configuration bit No.: 2413, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2410 -0, // Configuration bit No.: 2412, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2410 -0, // Configuration bit No.: 2411, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2410 -1, // Configuration bit No.: 2410, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2410 -0, // Configuration bit No.: 2409, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2402 -0, // Configuration bit No.: 2408, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2402 -0, // Configuration bit No.: 2407, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2402 -1, // Configuration bit No.: 2406, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2402 -0, // Configuration bit No.: 2405, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2402 -0, // Configuration bit No.: 2404, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2402 -0, // Configuration bit No.: 2403, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2402 -1, // Configuration bit No.: 2402, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2402 -0, // Configuration bit No.: 2401, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2394 -0, // Configuration bit No.: 2400, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2394 -0, // Configuration bit No.: 2399, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2394 -1, // Configuration bit No.: 2398, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2394 -0, // Configuration bit No.: 2397, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2394 -0, // Configuration bit No.: 2396, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2394 -0, // Configuration bit No.: 2395, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2394 -1, // Configuration bit No.: 2394, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2394 -0, // Configuration bit No.: 2393, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2386 -0, // Configuration bit No.: 2392, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2386 -0, // Configuration bit No.: 2391, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2386 -1, // Configuration bit No.: 2390, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2386 -0, // Configuration bit No.: 2389, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2386 -0, // Configuration bit No.: 2388, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2386 -0, // Configuration bit No.: 2387, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2386 -1, // Configuration bit No.: 2386, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2386 -0, // Configuration bit No.: 2385, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2378 -0, // Configuration bit No.: 2384, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2378 -0, // Configuration bit No.: 2383, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2378 -1, // Configuration bit No.: 2382, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2378 -0, // Configuration bit No.: 2381, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2378 -0, // Configuration bit No.: 2380, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2378 -0, // Configuration bit No.: 2379, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2378 -1, // Configuration bit No.: 2378, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2378 -0, // Configuration bit No.: 2377, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2370 -0, // Configuration bit No.: 2376, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2370 -0, // Configuration bit No.: 2375, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2370 -1, // Configuration bit No.: 2374, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2370 -0, // Configuration bit No.: 2373, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2370 -0, // Configuration bit No.: 2372, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2370 -0, // Configuration bit No.: 2371, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2370 -1, // Configuration bit No.: 2370, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2370 -0, // Configuration bit No.: 2369, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2362 -0, // Configuration bit No.: 2368, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2362 -0, // Configuration bit No.: 2367, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2362 -1, // Configuration bit No.: 2366, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2362 -0, // Configuration bit No.: 2365, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2362 -0, // Configuration bit No.: 2364, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2362 -0, // Configuration bit No.: 2363, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2362 -1, // Configuration bit No.: 2362, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2362 -0, // Configuration bit No.: 2361, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2354 -0, // Configuration bit No.: 2360, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2354 -0, // Configuration bit No.: 2359, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2354 -1, // Configuration bit No.: 2358, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2354 -0, // Configuration bit No.: 2357, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2354 -0, // Configuration bit No.: 2356, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2354 -0, // Configuration bit No.: 2355, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2354 -1, // Configuration bit No.: 2354, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2354 -0, // Configuration bit No.: 2353, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2346 -0, // Configuration bit No.: 2352, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2346 -0, // Configuration bit No.: 2351, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2346 -1, // Configuration bit No.: 2350, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2346 -0, // Configuration bit No.: 2349, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2346 -0, // Configuration bit No.: 2348, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2346 -0, // Configuration bit No.: 2347, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2346 -1, // Configuration bit No.: 2346, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2346 -0, // Configuration bit No.: 2345, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2338 -0, // Configuration bit No.: 2344, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2338 -0, // Configuration bit No.: 2343, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2338 -1, // Configuration bit No.: 2342, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2338 -0, // Configuration bit No.: 2341, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2338 -0, // Configuration bit No.: 2340, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2338 -0, // Configuration bit No.: 2339, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2338 -1, // Configuration bit No.: 2338, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2338 -0, // Configuration bit No.: 2337, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2330 -0, // Configuration bit No.: 2336, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2330 -0, // Configuration bit No.: 2335, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2330 -1, // Configuration bit No.: 2334, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2330 -0, // Configuration bit No.: 2333, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2330 -0, // Configuration bit No.: 2332, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2330 -0, // Configuration bit No.: 2331, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2330 -1, // Configuration bit No.: 2330, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2330 -0, // Configuration bit No.: 2329, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2322 -0, // Configuration bit No.: 2328, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2322 -0, // Configuration bit No.: 2327, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2322 -1, // Configuration bit No.: 2326, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2322 -0, // Configuration bit No.: 2325, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2322 -0, // Configuration bit No.: 2324, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2322 -0, // Configuration bit No.: 2323, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2322 -1, // Configuration bit No.: 2322, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2322 -0, // Configuration bit No.: 2321, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2314 -0, // Configuration bit No.: 2320, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2314 -0, // Configuration bit No.: 2319, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2314 -1, // Configuration bit No.: 2318, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2314 -0, // Configuration bit No.: 2317, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2314 -0, // Configuration bit No.: 2316, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2314 -0, // Configuration bit No.: 2315, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2314 -1, // Configuration bit No.: 2314, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2314 -0, // Configuration bit No.: 2313, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2306 -0, // Configuration bit No.: 2312, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2306 -0, // Configuration bit No.: 2311, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2306 -1, // Configuration bit No.: 2310, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2306 -0, // Configuration bit No.: 2309, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2306 -0, // Configuration bit No.: 2308, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2306 -0, // Configuration bit No.: 2307, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2306 -1, // Configuration bit No.: 2306, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2306 -0, // Configuration bit No.: 2305, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2298 -0, // Configuration bit No.: 2304, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2298 -0, // Configuration bit No.: 2303, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2298 -1, // Configuration bit No.: 2302, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2298 -0, // Configuration bit No.: 2301, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2298 -0, // Configuration bit No.: 2300, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2298 -0, // Configuration bit No.: 2299, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2298 -1, // Configuration bit No.: 2298, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2298 -0, // Configuration bit No.: 2297, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2290 -0, // Configuration bit No.: 2296, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2290 -0, // Configuration bit No.: 2295, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2290 -1, // Configuration bit No.: 2294, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2290 -0, // Configuration bit No.: 2293, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2290 -0, // Configuration bit No.: 2292, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2290 -0, // Configuration bit No.: 2291, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2290 -1, // Configuration bit No.: 2290, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2290 -0, // Configuration bit No.: 2289, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2282 -1, // Configuration bit No.: 2288, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2282 -0, // Configuration bit No.: 2287, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2282 -0, // Configuration bit No.: 2286, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2282 -0, // Configuration bit No.: 2285, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2282 -0, // Configuration bit No.: 2284, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2282 -0, // Configuration bit No.: 2283, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2282 -1, // Configuration bit No.: 2282, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2282 -0, // Configuration bit No.: 2281, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2274 -0, // Configuration bit No.: 2280, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2274 -0, // Configuration bit No.: 2279, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2274 -1, // Configuration bit No.: 2278, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2274 -0, // Configuration bit No.: 2277, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2274 -0, // Configuration bit No.: 2276, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2274 -0, // Configuration bit No.: 2275, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2274 -1, // Configuration bit No.: 2274, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2274 -0, // Configuration bit No.: 2273, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2266 -0, // Configuration bit No.: 2272, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2266 -0, // Configuration bit No.: 2271, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2266 -1, // Configuration bit No.: 2270, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2266 -0, // Configuration bit No.: 2269, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2266 -0, // Configuration bit No.: 2268, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2266 -0, // Configuration bit No.: 2267, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2266 -1, // Configuration bit No.: 2266, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2266 -0, // Configuration bit No.: 2265, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2258 -0, // Configuration bit No.: 2264, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2258 -0, // Configuration bit No.: 2263, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2258 -1, // Configuration bit No.: 2262, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2258 -0, // Configuration bit No.: 2261, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2258 -0, // Configuration bit No.: 2260, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2258 -0, // Configuration bit No.: 2259, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2258 -1, // Configuration bit No.: 2258, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2258 -0, // Configuration bit No.: 2257, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2250 -0, // Configuration bit No.: 2256, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2250 -0, // Configuration bit No.: 2255, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2250 -1, // Configuration bit No.: 2254, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2250 -0, // Configuration bit No.: 2253, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2250 -0, // Configuration bit No.: 2252, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2250 -0, // Configuration bit No.: 2251, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2250 -1, // Configuration bit No.: 2250, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2250 -0, // Configuration bit No.: 2249, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2242 -0, // Configuration bit No.: 2248, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2242 -0, // Configuration bit No.: 2247, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2242 -1, // Configuration bit No.: 2246, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2242 -0, // Configuration bit No.: 2245, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2242 -0, // Configuration bit No.: 2244, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2242 -0, // Configuration bit No.: 2243, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2242 -1, // Configuration bit No.: 2242, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2242 -0, // Configuration bit No.: 2241, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2234 -0, // Configuration bit No.: 2240, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2234 -0, // Configuration bit No.: 2239, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2234 -1, // Configuration bit No.: 2238, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2234 -0, // Configuration bit No.: 2237, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2234 -0, // Configuration bit No.: 2236, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2234 -0, // Configuration bit No.: 2235, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2234 -1, // Configuration bit No.: 2234, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2234 -0, // Configuration bit No.: 2233, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2226 -0, // Configuration bit No.: 2232, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2226 -0, // Configuration bit No.: 2231, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2226 -1, // Configuration bit No.: 2230, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2226 -0, // Configuration bit No.: 2229, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2226 -0, // Configuration bit No.: 2228, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2226 -0, // Configuration bit No.: 2227, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2226 -1, // Configuration bit No.: 2226, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2226 -0, // Configuration bit No.: 2225, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2218 -0, // Configuration bit No.: 2224, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2218 -0, // Configuration bit No.: 2223, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2218 -1, // Configuration bit No.: 2222, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2218 -0, // Configuration bit No.: 2221, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2218 -0, // Configuration bit No.: 2220, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2218 -0, // Configuration bit No.: 2219, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2218 -1, // Configuration bit No.: 2218, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2218 -0, // Configuration bit No.: 2217, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2210 -0, // Configuration bit No.: 2216, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2210 -0, // Configuration bit No.: 2215, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2210 -1, // Configuration bit No.: 2214, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2210 -0, // Configuration bit No.: 2213, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2210 -0, // Configuration bit No.: 2212, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2210 -0, // Configuration bit No.: 2211, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2210 -1, // Configuration bit No.: 2210, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2210 -0, // Configuration bit No.: 2209, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2202 -0, // Configuration bit No.: 2208, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2202 -0, // Configuration bit No.: 2207, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2202 -1, // Configuration bit No.: 2206, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2202 -0, // Configuration bit No.: 2205, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2202 -0, // Configuration bit No.: 2204, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2202 -0, // Configuration bit No.: 2203, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2202 -1, // Configuration bit No.: 2202, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2202 -0, // Configuration bit No.: 2201, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2194 -0, // Configuration bit No.: 2200, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2194 -0, // Configuration bit No.: 2199, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2194 -1, // Configuration bit No.: 2198, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2194 -0, // Configuration bit No.: 2197, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2194 -0, // Configuration bit No.: 2196, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2194 -0, // Configuration bit No.: 2195, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2194 -1, // Configuration bit No.: 2194, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2194 -0, // Configuration bit No.: 2193, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2186 -0, // Configuration bit No.: 2192, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2186 -0, // Configuration bit No.: 2191, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2186 -1, // Configuration bit No.: 2190, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2186 -0, // Configuration bit No.: 2189, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2186 -0, // Configuration bit No.: 2188, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2186 -0, // Configuration bit No.: 2187, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2186 -1, // Configuration bit No.: 2186, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2186 -0, // Configuration bit No.: 2185, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2178 -0, // Configuration bit No.: 2184, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2178 -0, // Configuration bit No.: 2183, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2178 -1, // Configuration bit No.: 2182, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2178 -0, // Configuration bit No.: 2181, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2178 -0, // Configuration bit No.: 2180, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2178 -0, // Configuration bit No.: 2179, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2178 -1, // Configuration bit No.: 2178, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2178 -0, // Configuration bit No.: 2177, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2170 -0, // Configuration bit No.: 2176, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2170 -0, // Configuration bit No.: 2175, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2170 -1, // Configuration bit No.: 2174, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2170 -0, // Configuration bit No.: 2173, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2170 -0, // Configuration bit No.: 2172, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2170 -0, // Configuration bit No.: 2171, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2170 -1, // Configuration bit No.: 2170, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2170 -0, // Configuration bit No.: 2169, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2162 -0, // Configuration bit No.: 2168, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2162 -0, // Configuration bit No.: 2167, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2162 -1, // Configuration bit No.: 2166, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2162 -0, // Configuration bit No.: 2165, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2162 -0, // Configuration bit No.: 2164, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2162 -0, // Configuration bit No.: 2163, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2162 -1, // Configuration bit No.: 2162, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2162 -0, // Configuration bit No.: 2161, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2154 -0, // Configuration bit No.: 2160, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2154 -0, // Configuration bit No.: 2159, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2154 -1, // Configuration bit No.: 2158, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2154 -0, // Configuration bit No.: 2157, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2154 -0, // Configuration bit No.: 2156, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2154 -0, // Configuration bit No.: 2155, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2154 -1, // Configuration bit No.: 2154, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2154 -0, // Configuration bit No.: 2153, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2146 -0, // Configuration bit No.: 2152, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2146 -0, // Configuration bit No.: 2151, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2146 -1, // Configuration bit No.: 2150, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2146 -0, // Configuration bit No.: 2149, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2146 -0, // Configuration bit No.: 2148, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2146 -0, // Configuration bit No.: 2147, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2146 -1, // Configuration bit No.: 2146, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2146 -0, // Configuration bit No.: 2145, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2138 -0, // Configuration bit No.: 2144, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2138 -0, // Configuration bit No.: 2143, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2138 -1, // Configuration bit No.: 2142, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2138 -0, // Configuration bit No.: 2141, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2138 -0, // Configuration bit No.: 2140, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2138 -0, // Configuration bit No.: 2139, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2138 -1, // Configuration bit No.: 2138, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2138 -1, // Configuration bit No.: 2137, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2130 -0, // Configuration bit No.: 2136, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2130 -0, // Configuration bit No.: 2135, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2130 -0, // Configuration bit No.: 2134, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2130 -0, // Configuration bit No.: 2133, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2130 -0, // Configuration bit No.: 2132, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2130 -0, // Configuration bit No.: 2131, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2130 -1, // Configuration bit No.: 2130, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2130 -0, // Configuration bit No.: 2129, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2122 -0, // Configuration bit No.: 2128, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2122 -0, // Configuration bit No.: 2127, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2122 -1, // Configuration bit No.: 2126, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2122 -0, // Configuration bit No.: 2125, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2122 -0, // Configuration bit No.: 2124, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2122 -0, // Configuration bit No.: 2123, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2122 -1, // Configuration bit No.: 2122, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2122 -0, // Configuration bit No.: 2121, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2114 -0, // Configuration bit No.: 2120, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2114 -0, // Configuration bit No.: 2119, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2114 -1, // Configuration bit No.: 2118, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2114 -0, // Configuration bit No.: 2117, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2114 -0, // Configuration bit No.: 2116, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2114 -0, // Configuration bit No.: 2115, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2114 -1, // Configuration bit No.: 2114, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2114 -0, // Configuration bit No.: 2113, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2106 -0, // Configuration bit No.: 2112, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2106 -0, // Configuration bit No.: 2111, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2106 -1, // Configuration bit No.: 2110, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2106 -0, // Configuration bit No.: 2109, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2106 -0, // Configuration bit No.: 2108, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2106 -0, // Configuration bit No.: 2107, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2106 -1, // Configuration bit No.: 2106, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2106 -0, // Configuration bit No.: 2105, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2098 -0, // Configuration bit No.: 2104, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2098 -0, // Configuration bit No.: 2103, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2098 -1, // Configuration bit No.: 2102, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2098 -0, // Configuration bit No.: 2101, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2098 -0, // Configuration bit No.: 2100, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2098 -0, // Configuration bit No.: 2099, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2098 -1, // Configuration bit No.: 2098, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2098 -0, // Configuration bit No.: 2097, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2090 -0, // Configuration bit No.: 2096, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2090 -0, // Configuration bit No.: 2095, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2090 -1, // Configuration bit No.: 2094, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2090 -0, // Configuration bit No.: 2093, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2090 -0, // Configuration bit No.: 2092, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2090 -0, // Configuration bit No.: 2091, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2090 -1, // Configuration bit No.: 2090, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2090 -1, // Configuration bit No.: 2082, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2082 -1, // Configuration bit No.: 2081, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2081 -1, // Configuration bit No.: 2080, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2080 -1, // Configuration bit No.: 2079, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2079 -1, // Configuration bit No.: 2078, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2078 -1, // Configuration bit No.: 2077, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2077 -1, // Configuration bit No.: 2076, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2076 -1, // Configuration bit No.: 2075, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2075 -1, // Configuration bit No.: 2074, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2074 -1, // Configuration bit No.: 2073, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2073 -1, // Configuration bit No.: 2072, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2072 -1, // Configuration bit No.: 2071, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2071 -1, // Configuration bit No.: 2070, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2070 -1, // Configuration bit No.: 2069, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2069 -1, // Configuration bit No.: 2068, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2068 -1, // Configuration bit No.: 2067, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2067 -1, // Configuration bit No.: 2066, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2066 -1, // Configuration bit No.: 2065, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2065 -1, // Configuration bit No.: 2064, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2064 -1, // Configuration bit No.: 2063, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2063 -1, // Configuration bit No.: 2062, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2062 -1, // Configuration bit No.: 2061, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2061 -1, // Configuration bit No.: 2060, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2060 -1, // Configuration bit No.: 2059, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2059 -1, // Configuration bit No.: 2058, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2058 -1, // Configuration bit No.: 2057, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2057 -1, // Configuration bit No.: 2056, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2056 -1, // Configuration bit No.: 2055, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2055 -1, // Configuration bit No.: 2054, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2054 -1, // Configuration bit No.: 2053, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2053 -1, // Configuration bit No.: 2052, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2052 -1, // Configuration bit No.: 2051, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2051 -1, // Configuration bit No.: 2050, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2050 -1, // Configuration bit No.: 2049, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2049 -1, // Configuration bit No.: 2048, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2048 -1, // Configuration bit No.: 2047, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2047 -1, // Configuration bit No.: 2046, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2046 -1, // Configuration bit No.: 2045, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2045 -1, // Configuration bit No.: 2044, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2044 -1, // Configuration bit No.: 2043, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2043 -1, // Configuration bit No.: 2042, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2042 -1, // Configuration bit No.: 2041, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2041 -1, // Configuration bit No.: 2040, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2040 -1, // Configuration bit No.: 2039, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2039 -1, // Configuration bit No.: 2038, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2038 -0, // Configuration bit No.: 2039, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2037 -0, // Configuration bit No.: 2038, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2037 -1, // Configuration bit No.: 2037, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2037 -0, // Configuration bit No.: 2036, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2034 -0, // Configuration bit No.: 2035, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2034 -1, // Configuration bit No.: 2034, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2034 -0, // Configuration bit No.: 2033, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2031 -0, // Configuration bit No.: 2032, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2031 -1, // Configuration bit No.: 2031, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2031 -0, // Configuration bit No.: 2030, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2028 -0, // Configuration bit No.: 2029, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2028 -1, // Configuration bit No.: 2028, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2028 -0, // Configuration bit No.: 2027, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2025 -0, // Configuration bit No.: 2026, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 2025 -1, // Configuration bit No.: 2025, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2025 -1, // Configuration bit No.: 2022, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2022 -1, // Configuration bit No.: 2021, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2021 -1, // Configuration bit No.: 2020, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2020 -1, // Configuration bit No.: 2019, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2019 -1, // Configuration bit No.: 2018, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2018 -1, // Configuration bit No.: 2017, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2017 -1, // Configuration bit No.: 2016, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2016 -1, // Configuration bit No.: 2015, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2015 -1, // Configuration bit No.: 2014, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2014 -1, // Configuration bit No.: 2013, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2013 -1, // Configuration bit No.: 2012, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2012 -1, // Configuration bit No.: 2011, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2011 -1, // Configuration bit No.: 2010, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2010 -1, // Configuration bit No.: 2009, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2009 -1, // Configuration bit No.: 2008, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2008 -1, // Configuration bit No.: 2007, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2007 -1, // Configuration bit No.: 2006, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2006 -1, // Configuration bit No.: 2005, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2005 -1, // Configuration bit No.: 2004, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2004 -1, // Configuration bit No.: 2003, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2003 -1, // Configuration bit No.: 2002, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2002 -1, // Configuration bit No.: 2001, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2001 -1, // Configuration bit No.: 2000, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 2000 -1, // Configuration bit No.: 1999, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1999 -1, // Configuration bit No.: 1998, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1998 -1, // Configuration bit No.: 1997, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1997 -1, // Configuration bit No.: 1996, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1996 -1, // Configuration bit No.: 1995, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1995 -1, // Configuration bit No.: 1994, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1994 -1, // Configuration bit No.: 1993, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1993 -1, // Configuration bit No.: 1992, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1992 -1, // Configuration bit No.: 1991, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1991 -1, // Configuration bit No.: 1990, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1990 -1, // Configuration bit No.: 1989, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1989 -1, // Configuration bit No.: 1988, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1988 -1, // Configuration bit No.: 1987, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1987 -1, // Configuration bit No.: 1986, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1986 -1, // Configuration bit No.: 1985, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1985 -1, // Configuration bit No.: 1984, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1984 -1, // Configuration bit No.: 1983, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1983 -1, // Configuration bit No.: 1982, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1982 -1, // Configuration bit No.: 1981, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1981 -1, // Configuration bit No.: 1980, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1980 -1, // Configuration bit No.: 1979, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1979 -1, // Configuration bit No.: 1978, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1978 -0, // Configuration bit No.: 1979, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1977 -0, // Configuration bit No.: 1978, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1977 -1, // Configuration bit No.: 1977, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1977 -0, // Configuration bit No.: 1976, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1974 -0, // Configuration bit No.: 1975, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1974 -1, // Configuration bit No.: 1974, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1974 -0, // Configuration bit No.: 1973, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1971 -0, // Configuration bit No.: 1972, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1971 -1, // Configuration bit No.: 1971, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1971 -0, // Configuration bit No.: 1970, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1968 -0, // Configuration bit No.: 1969, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1968 -1, // Configuration bit No.: 1968, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1968 -0, // Configuration bit No.: 1967, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1965 -0, // Configuration bit No.: 1966, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1965 -1, // Configuration bit No.: 1965, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1965 -1, // Configuration bit No.: 1962, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1962 -1, // Configuration bit No.: 1961, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1961 -1, // Configuration bit No.: 1960, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1960 -1, // Configuration bit No.: 1959, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1959 -1, // Configuration bit No.: 1958, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1958 -1, // Configuration bit No.: 1957, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1957 -1, // Configuration bit No.: 1956, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1956 -1, // Configuration bit No.: 1955, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1955 -1, // Configuration bit No.: 1954, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1954 -1, // Configuration bit No.: 1953, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1953 -0, // Configuration bit No.: 1952, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1952 -1, // Configuration bit No.: 1951, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1951 -1, // Configuration bit No.: 1950, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1950 -1, // Configuration bit No.: 1949, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1949 -1, // Configuration bit No.: 1948, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1948 -1, // Configuration bit No.: 1947, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1947 -1, // Configuration bit No.: 1946, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1946 -1, // Configuration bit No.: 1945, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1945 -1, // Configuration bit No.: 1944, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1944 -1, // Configuration bit No.: 1943, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1943 -1, // Configuration bit No.: 1942, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1942 -1, // Configuration bit No.: 1941, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1941 -1, // Configuration bit No.: 1940, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1940 -1, // Configuration bit No.: 1939, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1939 -1, // Configuration bit No.: 1938, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1938 -1, // Configuration bit No.: 1937, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1937 -1, // Configuration bit No.: 1936, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1936 -1, // Configuration bit No.: 1935, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1935 -1, // Configuration bit No.: 1934, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1934 -1, // Configuration bit No.: 1933, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1933 -1, // Configuration bit No.: 1932, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1932 -1, // Configuration bit No.: 1931, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1931 -1, // Configuration bit No.: 1930, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1930 -1, // Configuration bit No.: 1929, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1929 -1, // Configuration bit No.: 1928, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1928 -1, // Configuration bit No.: 1927, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1927 -1, // Configuration bit No.: 1926, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1926 -1, // Configuration bit No.: 1925, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1925 -1, // Configuration bit No.: 1924, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1924 -1, // Configuration bit No.: 1923, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1923 -1, // Configuration bit No.: 1922, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1922 -1, // Configuration bit No.: 1921, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1921 -1, // Configuration bit No.: 1920, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1920 -1, // Configuration bit No.: 1919, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1919 -1, // Configuration bit No.: 1918, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1918 -1, // Configuration bit No.: 1917, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1917 -1, // Configuration bit No.: 1916, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1916 -1, // Configuration bit No.: 1915, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1915 -1, // Configuration bit No.: 1914, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1914 -1, // Configuration bit No.: 1913, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1913 -1, // Configuration bit No.: 1912, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1912 -1, // Configuration bit No.: 1911, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1911 -1, // Configuration bit No.: 1910, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1910 -1, // Configuration bit No.: 1909, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1909 -1, // Configuration bit No.: 1908, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1908 -1, // Configuration bit No.: 1907, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1907 -1, // Configuration bit No.: 1906, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1906 -1, // Configuration bit No.: 1905, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1905 -1, // Configuration bit No.: 1904, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1904 -1, // Configuration bit No.: 1903, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1903 -1, // Configuration bit No.: 1902, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1902 -1, // Configuration bit No.: 1901, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1901 -1, // Configuration bit No.: 1900, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1900 -1, // Configuration bit No.: 1899, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1899 -1, // Configuration bit No.: 1898, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1898 -1, // Configuration bit No.: 1897, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1897 -1, // Configuration bit No.: 1896, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1896 -1, // Configuration bit No.: 1895, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1895 -1, // Configuration bit No.: 1894, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1894 -1, // Configuration bit No.: 1893, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1893 -1, // Configuration bit No.: 1892, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1892 -1, // Configuration bit No.: 1891, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1891 -1, // Configuration bit No.: 1890, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1890 -1, // Configuration bit No.: 1889, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1889 -1, // Configuration bit No.: 1888, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1888 -1, // Configuration bit No.: 1887, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1887 -1, // Configuration bit No.: 1886, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1886 -1, // Configuration bit No.: 1885, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1885 -1, // Configuration bit No.: 1884, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1884 -1, // Configuration bit No.: 1883, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1883 -1, // Configuration bit No.: 1882, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1882 -1, // Configuration bit No.: 1881, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1881 -1, // Configuration bit No.: 1880, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1880 -1, // Configuration bit No.: 1879, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1879 -1, // Configuration bit No.: 1878, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1878 -1, // Configuration bit No.: 1877, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1877 -1, // Configuration bit No.: 1876, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1876 -1, // Configuration bit No.: 1875, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1875 -1, // Configuration bit No.: 1874, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1874 -1, // Configuration bit No.: 1873, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1873 -1, // Configuration bit No.: 1872, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1872 -1, // Configuration bit No.: 1871, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1871 -1, // Configuration bit No.: 1870, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1870 -1, // Configuration bit No.: 1869, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1869 -1, // Configuration bit No.: 1868, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1868 -0, // Configuration bit No.: 1869, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1867 -0, // Configuration bit No.: 1868, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1867 -1, // Configuration bit No.: 1867, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1867 -0, // Configuration bit No.: 1866, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1864 -0, // Configuration bit No.: 1865, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1864 -1, // Configuration bit No.: 1864, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1864 -0, // Configuration bit No.: 1863, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1861 -0, // Configuration bit No.: 1862, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1861 -1, // Configuration bit No.: 1861, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1861 -0, // Configuration bit No.: 1860, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1858 -0, // Configuration bit No.: 1859, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1858 -1, // Configuration bit No.: 1858, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1858 -0, // Configuration bit No.: 1857, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1855 -0, // Configuration bit No.: 1856, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1855 -1, // Configuration bit No.: 1855, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1855 -1, // Configuration bit No.: 1852, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1852 -1, // Configuration bit No.: 1851, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1851 -1, // Configuration bit No.: 1850, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1850 -1, // Configuration bit No.: 1849, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1849 -1, // Configuration bit No.: 1848, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1848 -1, // Configuration bit No.: 1847, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1847 -1, // Configuration bit No.: 1846, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1846 -1, // Configuration bit No.: 1845, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1845 -1, // Configuration bit No.: 1844, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1844 -1, // Configuration bit No.: 1843, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1843 -1, // Configuration bit No.: 1842, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1842 -1, // Configuration bit No.: 1841, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1841 -1, // Configuration bit No.: 1840, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1840 -1, // Configuration bit No.: 1839, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1839 -1, // Configuration bit No.: 1838, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1838 -1, // Configuration bit No.: 1837, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1837 -1, // Configuration bit No.: 1836, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1836 -1, // Configuration bit No.: 1835, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1835 -1, // Configuration bit No.: 1834, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1834 -1, // Configuration bit No.: 1833, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1833 -1, // Configuration bit No.: 1832, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1832 -1, // Configuration bit No.: 1831, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1831 -1, // Configuration bit No.: 1830, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1830 -1, // Configuration bit No.: 1829, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1829 -1, // Configuration bit No.: 1828, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1828 -1, // Configuration bit No.: 1827, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1827 -1, // Configuration bit No.: 1826, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1826 -1, // Configuration bit No.: 1825, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1825 -1, // Configuration bit No.: 1824, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1824 -1, // Configuration bit No.: 1823, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1823 -1, // Configuration bit No.: 1822, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1822 -1, // Configuration bit No.: 1821, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1821 -1, // Configuration bit No.: 1820, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1820 -1, // Configuration bit No.: 1819, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1819 -1, // Configuration bit No.: 1818, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1818 -1, // Configuration bit No.: 1817, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1817 -1, // Configuration bit No.: 1816, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1816 -1, // Configuration bit No.: 1815, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1815 -1, // Configuration bit No.: 1814, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1814 -1, // Configuration bit No.: 1813, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1813 -1, // Configuration bit No.: 1812, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1812 -1, // Configuration bit No.: 1811, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1811 -1, // Configuration bit No.: 1810, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1810 -1, // Configuration bit No.: 1809, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1809 -1, // Configuration bit No.: 1808, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1808 -1, // Configuration bit No.: 1807, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1807 -1, // Configuration bit No.: 1806, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1806 -1, // Configuration bit No.: 1805, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1805 -1, // Configuration bit No.: 1804, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1804 -1, // Configuration bit No.: 1803, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1803 -1, // Configuration bit No.: 1802, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1802 -1, // Configuration bit No.: 1801, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1801 -1, // Configuration bit No.: 1800, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1800 -1, // Configuration bit No.: 1799, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1799 -1, // Configuration bit No.: 1798, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1798 -1, // Configuration bit No.: 1797, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1797 -1, // Configuration bit No.: 1796, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1796 -1, // Configuration bit No.: 1795, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1795 -1, // Configuration bit No.: 1794, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1794 -1, // Configuration bit No.: 1793, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1793 -1, // Configuration bit No.: 1792, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1792 -1, // Configuration bit No.: 1791, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1791 -1, // Configuration bit No.: 1790, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1790 -1, // Configuration bit No.: 1789, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1789 -1, // Configuration bit No.: 1788, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1788 -1, // Configuration bit No.: 1787, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1787 -1, // Configuration bit No.: 1786, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1786 -1, // Configuration bit No.: 1785, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1785 -1, // Configuration bit No.: 1784, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1784 -1, // Configuration bit No.: 1783, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1783 -1, // Configuration bit No.: 1782, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1782 -1, // Configuration bit No.: 1781, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1781 -1, // Configuration bit No.: 1780, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1780 -1, // Configuration bit No.: 1779, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1779 -1, // Configuration bit No.: 1778, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1778 -1, // Configuration bit No.: 1777, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1777 -1, // Configuration bit No.: 1776, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1776 -1, // Configuration bit No.: 1775, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1775 -1, // Configuration bit No.: 1774, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1774 -1, // Configuration bit No.: 1773, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1773 -1, // Configuration bit No.: 1772, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1772 -1, // Configuration bit No.: 1771, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1771 -1, // Configuration bit No.: 1770, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1770 -1, // Configuration bit No.: 1769, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1769 -1, // Configuration bit No.: 1768, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1768 -1, // Configuration bit No.: 1767, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1767 -1, // Configuration bit No.: 1766, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1766 -1, // Configuration bit No.: 1765, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1765 -1, // Configuration bit No.: 1764, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1764 -0, // Configuration bit No.: 1763, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1763 -1, // Configuration bit No.: 1762, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1762 -1, // Configuration bit No.: 1761, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1761 -1, // Configuration bit No.: 1760, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1760 -1, // Configuration bit No.: 1759, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1759 -1, // Configuration bit No.: 1758, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1758 -0, // Configuration bit No.: 1759, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1757 -0, // Configuration bit No.: 1758, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1757 -1, // Configuration bit No.: 1757, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1757 -0, // Configuration bit No.: 1756, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1754 -0, // Configuration bit No.: 1755, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1754 -1, // Configuration bit No.: 1754, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1754 -0, // Configuration bit No.: 1753, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1751 -0, // Configuration bit No.: 1752, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1751 -1, // Configuration bit No.: 1751, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1751 -0, // Configuration bit No.: 1750, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1748 -0, // Configuration bit No.: 1749, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1748 -1, // Configuration bit No.: 1748, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1748 -0, // Configuration bit No.: 1747, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1745 -0, // Configuration bit No.: 1746, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1745 -1, // Configuration bit No.: 1745, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1745 -1, // Configuration bit No.: 1742, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1742 -1, // Configuration bit No.: 1741, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1741 -1, // Configuration bit No.: 1740, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1740 -1, // Configuration bit No.: 1739, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1739 -1, // Configuration bit No.: 1738, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1738 -1, // Configuration bit No.: 1737, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1737 -1, // Configuration bit No.: 1736, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1736 -1, // Configuration bit No.: 1735, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1735 -1, // Configuration bit No.: 1734, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1734 -1, // Configuration bit No.: 1733, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1733 -1, // Configuration bit No.: 1732, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1732 -1, // Configuration bit No.: 1731, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1731 -1, // Configuration bit No.: 1730, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1730 -1, // Configuration bit No.: 1729, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1729 -1, // Configuration bit No.: 1728, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1728 -1, // Configuration bit No.: 1727, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1727 -1, // Configuration bit No.: 1726, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1726 -1, // Configuration bit No.: 1725, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1725 -1, // Configuration bit No.: 1724, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1724 -1, // Configuration bit No.: 1723, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1723 -1, // Configuration bit No.: 1722, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1722 -1, // Configuration bit No.: 1721, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1721 -1, // Configuration bit No.: 1720, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1720 -1, // Configuration bit No.: 1719, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1719 -1, // Configuration bit No.: 1718, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1718 -1, // Configuration bit No.: 1717, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1717 -1, // Configuration bit No.: 1716, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1716 -1, // Configuration bit No.: 1715, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1715 -1, // Configuration bit No.: 1714, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1714 -1, // Configuration bit No.: 1713, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1713 -1, // Configuration bit No.: 1712, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1712 -1, // Configuration bit No.: 1711, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1711 -1, // Configuration bit No.: 1710, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1710 -1, // Configuration bit No.: 1709, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1709 -1, // Configuration bit No.: 1708, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1708 -1, // Configuration bit No.: 1707, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1707 -1, // Configuration bit No.: 1706, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1706 -1, // Configuration bit No.: 1705, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1705 -1, // Configuration bit No.: 1704, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1704 -1, // Configuration bit No.: 1703, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1703 -1, // Configuration bit No.: 1702, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1702 -1, // Configuration bit No.: 1701, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1701 -1, // Configuration bit No.: 1700, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1700 -1, // Configuration bit No.: 1699, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1699 -1, // Configuration bit No.: 1698, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1698 -1, // Configuration bit No.: 1697, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1697 -1, // Configuration bit No.: 1696, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1696 -1, // Configuration bit No.: 1695, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1695 -1, // Configuration bit No.: 1694, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1694 -1, // Configuration bit No.: 1693, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1693 -1, // Configuration bit No.: 1692, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1692 -1, // Configuration bit No.: 1691, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1691 -1, // Configuration bit No.: 1690, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1690 -1, // Configuration bit No.: 1689, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1689 -1, // Configuration bit No.: 1688, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1688 -1, // Configuration bit No.: 1687, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1687 -1, // Configuration bit No.: 1686, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1686 -1, // Configuration bit No.: 1685, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1685 -1, // Configuration bit No.: 1684, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1684 -1, // Configuration bit No.: 1683, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1683 -1, // Configuration bit No.: 1682, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1682 -0, // Configuration bit No.: 1681, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1681 -1, // Configuration bit No.: 1680, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1680 -1, // Configuration bit No.: 1679, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1679 -1, // Configuration bit No.: 1678, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1678 -1, // Configuration bit No.: 1677, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1677 -1, // Configuration bit No.: 1676, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1676 -1, // Configuration bit No.: 1675, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1675 -1, // Configuration bit No.: 1674, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1674 -1, // Configuration bit No.: 1673, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1673 -1, // Configuration bit No.: 1672, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1672 -1, // Configuration bit No.: 1671, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1671 -1, // Configuration bit No.: 1670, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1670 -1, // Configuration bit No.: 1669, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1669 -1, // Configuration bit No.: 1668, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1668 -1, // Configuration bit No.: 1667, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1667 -1, // Configuration bit No.: 1666, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1666 -1, // Configuration bit No.: 1665, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1665 -1, // Configuration bit No.: 1664, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1664 -1, // Configuration bit No.: 1663, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1663 -1, // Configuration bit No.: 1662, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1662 -1, // Configuration bit No.: 1661, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1661 -1, // Configuration bit No.: 1660, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1660 -1, // Configuration bit No.: 1659, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1659 -1, // Configuration bit No.: 1658, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1658 -1, // Configuration bit No.: 1657, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1657 -1, // Configuration bit No.: 1656, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1656 -1, // Configuration bit No.: 1655, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1655 -1, // Configuration bit No.: 1654, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1654 -1, // Configuration bit No.: 1653, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1653 -1, // Configuration bit No.: 1652, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1652 -1, // Configuration bit No.: 1651, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1651 -1, // Configuration bit No.: 1650, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1650 -1, // Configuration bit No.: 1649, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1649 -1, // Configuration bit No.: 1648, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1648 -1, // Configuration bit No.: 1647, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1647 -1, // Configuration bit No.: 1646, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1646 -1, // Configuration bit No.: 1645, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1645 -1, // Configuration bit No.: 1644, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1644 -1, // Configuration bit No.: 1643, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1643 -1, // Configuration bit No.: 1642, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1642 -0, // Configuration bit No.: 1641, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1641 -1, // Configuration bit No.: 1640, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1640 -1, // Configuration bit No.: 1639, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1639 -1, // Configuration bit No.: 1638, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1638 -1, // Configuration bit No.: 1637, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1637 -1, // Configuration bit No.: 1636, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1636 -1, // Configuration bit No.: 1635, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1635 -1, // Configuration bit No.: 1634, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1634 -1, // Configuration bit No.: 1633, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1633 -1, // Configuration bit No.: 1632, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1632 -1, // Configuration bit No.: 1631, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1631 -1, // Configuration bit No.: 1630, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1630 -1, // Configuration bit No.: 1629, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1629 -1, // Configuration bit No.: 1628, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1628 -1, // Configuration bit No.: 1627, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1627 -1, // Configuration bit No.: 1626, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1626 -1, // Configuration bit No.: 1625, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1625 -1, // Configuration bit No.: 1624, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1624 -1, // Configuration bit No.: 1623, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1623 -1, // Configuration bit No.: 1622, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1622 -1, // Configuration bit No.: 1621, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1621 -1, // Configuration bit No.: 1620, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1620 -1, // Configuration bit No.: 1619, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1619 -1, // Configuration bit No.: 1618, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1618 -1, // Configuration bit No.: 1617, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1617 -1, // Configuration bit No.: 1616, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1616 -1, // Configuration bit No.: 1615, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1615 -1, // Configuration bit No.: 1614, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1614 -1, // Configuration bit No.: 1613, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1613 -1, // Configuration bit No.: 1612, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1612 -1, // Configuration bit No.: 1611, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1611 -0, // Configuration bit No.: 1625, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1624, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1623, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1622, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1621, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1620, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1619, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -1, // Configuration bit No.: 1618, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1617, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1616, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1615, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1614, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1613, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1612, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1611, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1610 -1, // Configuration bit No.: 1610, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1610 -0, // Configuration bit No.: 1609, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1608, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1607, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1606, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1605, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1604, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1603, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -1, // Configuration bit No.: 1602, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1601, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1600, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1599, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1598, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1597, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1596, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1595, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1594 -1, // Configuration bit No.: 1594, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1594 -0, // Configuration bit No.: 1593, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1592, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1591, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1590, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1589, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1588, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1587, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -1, // Configuration bit No.: 1586, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1585, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1584, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1583, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1582, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1581, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1580, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1579, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1578 -1, // Configuration bit No.: 1578, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1578 -0, // Configuration bit No.: 1577, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1576, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1575, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1574, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1573, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1572, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1571, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -1, // Configuration bit No.: 1570, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1569, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1568, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1567, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1566, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1565, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1564, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1563, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1562 -1, // Configuration bit No.: 1562, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1562 -0, // Configuration bit No.: 1561, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1560, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1559, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1558, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1557, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1556, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1555, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -1, // Configuration bit No.: 1554, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1553, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1552, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1551, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1550, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1549, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1548, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1547, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1546 -1, // Configuration bit No.: 1546, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1546 -0, // Configuration bit No.: 1545, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -1, // Configuration bit No.: 1544, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1543, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1542, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1541, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1540, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1539, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1538, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1537, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1536, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1535, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1534, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1533, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -1, // Configuration bit No.: 1532, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1531, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1530, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1530 -0, // Configuration bit No.: 1529, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1528, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1527, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1526, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1525, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1524, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1523, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -1, // Configuration bit No.: 1522, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1521, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1520, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1519, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1518, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1517, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1516, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1515, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1514 -1, // Configuration bit No.: 1514, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1514 -0, // Configuration bit No.: 1513, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1512, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1511, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1510, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1509, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1508, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1507, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -1, // Configuration bit No.: 1506, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1505, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1504, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1503, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1502, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1501, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1500, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1499, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1498 -1, // Configuration bit No.: 1498, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1498 -0, // Configuration bit No.: 1497, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1496, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1495, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1494, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1493, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1492, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1491, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -1, // Configuration bit No.: 1490, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1489, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1488, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1487, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1486, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1485, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1484, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1483, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1482 -1, // Configuration bit No.: 1482, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1482 -0, // Configuration bit No.: 1481, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1480, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1479, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1478, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1477, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1476, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1475, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -1, // Configuration bit No.: 1474, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1473, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1472, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1471, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1470, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1469, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1468, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1467, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1466 -1, // Configuration bit No.: 1466, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1466 -0, // Configuration bit No.: 1465, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1464, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1463, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1462, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1461, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1460, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1459, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -1, // Configuration bit No.: 1458, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1457, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1456, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1455, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1454, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1453, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1452, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1451, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1450 -1, // Configuration bit No.: 1450, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1450 -0, // Configuration bit No.: 1449, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1448, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1447, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1446, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1445, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1444, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1443, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -1, // Configuration bit No.: 1442, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1441, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1440, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1439, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1438, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1437, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1436, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1435, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1434 -1, // Configuration bit No.: 1434, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1434 -0, // Configuration bit No.: 1433, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1432, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1431, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1430, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1429, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1428, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1427, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -1, // Configuration bit No.: 1426, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1425, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1424, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1423, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1422, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1421, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1420, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1419, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1418 -1, // Configuration bit No.: 1418, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1418 -0, // Configuration bit No.: 1417, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1416, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1415, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1414, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1413, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1412, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1411, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -1, // Configuration bit No.: 1410, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1409, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1408, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1407, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1406, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1405, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1404, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1403, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1402 -1, // Configuration bit No.: 1402, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1402 -0, // Configuration bit No.: 1401, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1400, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1399, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1398, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1397, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1396, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1395, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -1, // Configuration bit No.: 1394, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1393, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1392, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1391, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1390, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1389, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1388, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1387, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1386 -1, // Configuration bit No.: 1386, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1386 -0, // Configuration bit No.: 1385, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1384, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1383, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1382, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1381, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1380, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1379, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -1, // Configuration bit No.: 1378, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1377, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1376, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1375, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1374, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1373, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1372, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1371, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1370 -1, // Configuration bit No.: 1370, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1370 -0, // Configuration bit No.: 1369, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1368, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1367, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1366, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1365, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1364, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1363, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -1, // Configuration bit No.: 1362, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1361, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1360, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1359, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1358, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1357, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1356, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1355, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1354 -1, // Configuration bit No.: 1354, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1354 -0, // Configuration bit No.: 1353, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1352, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1351, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1350, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1349, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1348, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1347, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -1, // Configuration bit No.: 1346, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1345, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1344, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1343, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1342, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1341, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1340, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1339, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1338 -1, // Configuration bit No.: 1338, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1338 -0, // Configuration bit No.: 1337, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1336, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1335, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1334, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1333, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1332, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1331, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -1, // Configuration bit No.: 1330, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1329, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1328, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1327, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1326, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1325, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1324, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1323, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1322 -1, // Configuration bit No.: 1322, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1322 -0, // Configuration bit No.: 1321, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1320, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1319, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1318, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1317, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1316, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1315, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -1, // Configuration bit No.: 1314, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1313, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1312, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1311, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1310, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1309, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1308, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1307, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1306 -1, // Configuration bit No.: 1306, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1306 -0, // Configuration bit No.: 1305, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1304, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1303, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1302, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1301, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1300, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1299, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -1, // Configuration bit No.: 1298, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1297, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1296, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1295, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1294, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1293, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1292, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1291, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1290 -1, // Configuration bit No.: 1290, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1290 -0, // Configuration bit No.: 1289, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1288, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1287, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1286, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1285, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1284, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1283, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -1, // Configuration bit No.: 1282, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1281, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1280, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1279, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1278, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1277, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1276, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1275, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1274 -1, // Configuration bit No.: 1274, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1274 -0, // Configuration bit No.: 1273, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1272, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1271, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1270, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1269, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1268, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1267, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -1, // Configuration bit No.: 1266, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1265, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1264, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1263, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1262, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1261, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1260, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1259, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1258 -1, // Configuration bit No.: 1258, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1258 -0, // Configuration bit No.: 1257, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1256, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1255, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1254, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1253, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1252, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1251, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -1, // Configuration bit No.: 1250, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1249, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1248, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1247, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1246, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1245, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1244, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1243, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1242 -1, // Configuration bit No.: 1242, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1242 -0, // Configuration bit No.: 1241, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1240, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1239, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1238, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1237, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1236, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1235, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -1, // Configuration bit No.: 1234, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1233, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1232, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1231, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1230, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1229, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1228, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1227, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1226 -1, // Configuration bit No.: 1226, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1226 -0, // Configuration bit No.: 1225, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1224, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1223, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1222, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1221, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1220, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1219, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -1, // Configuration bit No.: 1218, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1217, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1216, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1215, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1214, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1213, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1212, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1211, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1210 -1, // Configuration bit No.: 1210, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1210 -0, // Configuration bit No.: 1209, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1208, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1207, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1206, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1205, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1204, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1203, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -1, // Configuration bit No.: 1202, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1201, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1200, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1199, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1198, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1197, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1196, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1195, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1194 -1, // Configuration bit No.: 1194, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1194 -0, // Configuration bit No.: 1193, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1192, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1191, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1190, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1189, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1188, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1187, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -1, // Configuration bit No.: 1186, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1185, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1184, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1183, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1182, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1181, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1180, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1179, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1178 -1, // Configuration bit No.: 1178, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1178 -0, // Configuration bit No.: 1177, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1176, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1175, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1174, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1173, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1172, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1171, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -1, // Configuration bit No.: 1170, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1169, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1168, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1167, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1166, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1165, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1164, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1163, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1162 -1, // Configuration bit No.: 1162, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1162 -0, // Configuration bit No.: 1161, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1160, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1159, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1158, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1157, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1156, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1155, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -1, // Configuration bit No.: 1154, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1153, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1152, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1151, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1150, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1149, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1148, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1147, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1146 -1, // Configuration bit No.: 1146, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1146 -0, // Configuration bit No.: 1145, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1144, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1143, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1142, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1141, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1140, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1139, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -1, // Configuration bit No.: 1138, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1137, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1136, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1135, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1134, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1133, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1132, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1131, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1130 -1, // Configuration bit No.: 1130, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1130 -0, // Configuration bit No.: 1129, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1128, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1127, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1126, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1125, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1124, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1123, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -1, // Configuration bit No.: 1122, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1121, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1120, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1119, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1118, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1117, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1116, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1115, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1114 -1, // Configuration bit No.: 1114, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1114 -0, // Configuration bit No.: 1113, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1112, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1111, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1110, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1109, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1108, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1107, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -1, // Configuration bit No.: 1106, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1105, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1104, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1103, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1102, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1101, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1100, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1099, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1098 -1, // Configuration bit No.: 1098, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1098 -0, // Configuration bit No.: 1097, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1096, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1095, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1094, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1093, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1092, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1091, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -1, // Configuration bit No.: 1090, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1089, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1088, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1087, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1086, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1085, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1084, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1083, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1082 -1, // Configuration bit No.: 1082, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1082 -0, // Configuration bit No.: 1081, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1080, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1079, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1078, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1077, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1076, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1075, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -1, // Configuration bit No.: 1074, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1073, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1072, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1071, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1070, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1069, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1068, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1067, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1066 -1, // Configuration bit No.: 1066, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1066 -0, // Configuration bit No.: 1065, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1064, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1063, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1062, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1061, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1060, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1059, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -1, // Configuration bit No.: 1058, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1057, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1056, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1055, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1054, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1053, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1052, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1051, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1050 -1, // Configuration bit No.: 1050, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1050 -0, // Configuration bit No.: 1049, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1048, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1047, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1046, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1045, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1044, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1043, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -1, // Configuration bit No.: 1042, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1041, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1040, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1039, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1038, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1037, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1036, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1035, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1034 -1, // Configuration bit No.: 1034, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1034 -0, // Configuration bit No.: 1033, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1032, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1031, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1030, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1029, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1028, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1027, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -1, // Configuration bit No.: 1026, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1025, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1024, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1023, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1022, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1021, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1020, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1019, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1018 -1, // Configuration bit No.: 1018, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1018 -0, // Configuration bit No.: 1017, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1016, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1015, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1014, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1013, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1012, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1011, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -1, // Configuration bit No.: 1010, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1009, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1008, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1007, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1006, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1005, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1004, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1003, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 1002 -1, // Configuration bit No.: 1002, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 1002 -0, // Configuration bit No.: 1001, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 1000, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 999, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 998, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 997, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 996, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 995, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -1, // Configuration bit No.: 994, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 993, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 992, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 991, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 990, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 989, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 988, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 987, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 986 -1, // Configuration bit No.: 986, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 986 -0, // Configuration bit No.: 985, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 984, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 983, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 982, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 981, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 980, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 979, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -1, // Configuration bit No.: 978, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 977, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 976, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 975, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 974, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 973, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 972, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 971, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 970 -1, // Configuration bit No.: 970, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 970 -0, // Configuration bit No.: 969, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 968, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 967, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 966, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 965, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 964, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 963, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -1, // Configuration bit No.: 962, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 961, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 960, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 959, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 958, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 957, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 956, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 955, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 954 -1, // Configuration bit No.: 954, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 954 -0, // Configuration bit No.: 953, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 952, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 951, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 950, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 949, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 948, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 947, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -1, // Configuration bit No.: 946, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 945, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 944, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 943, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 942, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 941, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 940, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 939, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 938 -1, // Configuration bit No.: 938, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 938 -0, // Configuration bit No.: 937, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 936, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 935, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 934, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 933, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 932, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 931, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -1, // Configuration bit No.: 930, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 929, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 928, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 927, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 926, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 925, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 924, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 923, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 922 -1, // Configuration bit No.: 922, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 922 -0, // Configuration bit No.: 921, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 920, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 919, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 918, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 917, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 916, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 915, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -1, // Configuration bit No.: 914, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 913, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 912, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 911, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 910, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 909, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 908, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 907, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 906 -1, // Configuration bit No.: 906, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 906 -0, // Configuration bit No.: 905, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 904, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 903, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 902, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 901, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 900, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 899, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -1, // Configuration bit No.: 898, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 897, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 896, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 895, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 894, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 893, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 892, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 891, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 890 -1, // Configuration bit No.: 890, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 890 -0, // Configuration bit No.: 889, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 888, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 887, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 886, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 885, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 884, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 883, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -1, // Configuration bit No.: 882, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 881, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 880, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 879, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 878, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 877, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 876, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 875, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 874 -1, // Configuration bit No.: 874, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 874 -0, // Configuration bit No.: 873, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 872, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 871, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 870, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 869, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 868, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 867, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -1, // Configuration bit No.: 866, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 865, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 864, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 863, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 862, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 861, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 860, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 859, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 858 -1, // Configuration bit No.: 858, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 858 -0, // Configuration bit No.: 857, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 856, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 855, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 854, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 853, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 852, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 851, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -1, // Configuration bit No.: 850, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 849, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 848, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 847, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 846, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 845, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 844, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 843, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 842 -1, // Configuration bit No.: 842, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 842 -0, // Configuration bit No.: 841, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 840, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 839, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 838, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 837, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 836, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 835, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -1, // Configuration bit No.: 834, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 833, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 832, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 831, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 830, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 829, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 828, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 827, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 826 -1, // Configuration bit No.: 826, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 826 -0, // Configuration bit No.: 825, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 824, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 823, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 822, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 821, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 820, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 819, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -1, // Configuration bit No.: 818, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 817, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 816, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 815, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 814, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 813, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 812, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 811, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 810 -1, // Configuration bit No.: 810, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 810 -0, // Configuration bit No.: 809, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 808, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 807, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 806, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 805, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 804, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 803, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -1, // Configuration bit No.: 802, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 801, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 800, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 799, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 798, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 797, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 796, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 795, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 794 -1, // Configuration bit No.: 794, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 794 -0, // Configuration bit No.: 793, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 792, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 791, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 790, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 789, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 788, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 787, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -1, // Configuration bit No.: 786, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 785, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 784, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 783, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 782, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 781, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 780, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 779, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 778 -1, // Configuration bit No.: 778, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 778 -0, // Configuration bit No.: 777, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 776, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 775, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 774, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 773, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 772, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 771, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -1, // Configuration bit No.: 770, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 769, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 768, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 767, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 766, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 765, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 764, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 763, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 762 -1, // Configuration bit No.: 762, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 762 -0, // Configuration bit No.: 761, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 760, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 759, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 758, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 757, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 756, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 755, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -1, // Configuration bit No.: 754, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 753, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 752, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 751, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 750, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 749, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 748, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 747, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 746 -1, // Configuration bit No.: 746, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 746 -0, // Configuration bit No.: 745, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 744, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 743, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 742, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 741, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 740, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 739, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -1, // Configuration bit No.: 738, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 737, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 736, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 735, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 734, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 733, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 732, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 731, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 730 -1, // Configuration bit No.: 730, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 730 -0, // Configuration bit No.: 729, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 728, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 727, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 726, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 725, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 724, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 723, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -1, // Configuration bit No.: 722, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 721, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 720, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 719, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 718, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 717, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 716, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 715, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 714 -1, // Configuration bit No.: 714, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 714 -0, // Configuration bit No.: 713, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 712, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 711, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 710, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 709, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 708, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 707, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -1, // Configuration bit No.: 706, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 705, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 704, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 703, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 702, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 701, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 700, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 699, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 698 -1, // Configuration bit No.: 698, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 698 -0, // Configuration bit No.: 697, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 696, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 695, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 694, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 693, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 692, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 691, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -1, // Configuration bit No.: 690, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 689, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 688, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 687, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 686, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 685, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 684, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 683, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 682 -1, // Configuration bit No.: 682, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 682 -0, // Configuration bit No.: 681, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 680, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 679, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 678, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 677, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 676, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 675, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -1, // Configuration bit No.: 674, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 673, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 672, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 671, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 670, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 669, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 668, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -0, // Configuration bit No.: 667, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 666 -1, // Configuration bit No.: 666, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 666 -1, // Configuration bit No.: 650, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 650 -1, // Configuration bit No.: 712, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 711, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 710, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 709, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 708, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 707, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 706, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 705, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 704, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 703, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 702, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 701, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 700, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 699, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 698, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 697, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 696, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 695, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 694, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 693, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 692, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 691, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 690, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 689, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 688, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 687, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 686, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 685, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 684, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 683, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 682, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 681, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 680, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 679, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 678, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 677, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 676, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 675, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 674, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 673, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 672, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 671, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 670, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 669, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 668, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 667, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 666, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 665, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 664, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 663, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 662, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 661, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 660, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 659, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 658, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 657, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 656, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 655, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 654, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 653, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 652, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 651, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 650, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 649 -0, // Configuration bit No.: 649, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 649 -1, // Configuration bit No.: 585, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 585 -0, // Configuration bit No.: 647, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 646, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 645, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 644, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 643, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 642, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 641, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 640, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 639, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 638, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 637, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 636, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 635, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 634, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 633, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 632, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 631, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 630, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 629, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 628, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 627, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 626, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 625, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 624, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 623, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 622, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 621, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 620, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 619, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 618, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 617, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 616, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 615, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 614, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 613, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 612, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 611, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 610, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 609, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 608, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 607, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 606, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 605, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 604, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 603, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 602, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 601, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 600, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 599, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 598, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 597, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 596, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 595, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 594, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 593, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 592, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 591, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 590, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 589, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 588, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 587, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 586, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 585, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -0, // Configuration bit No.: 584, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 584 -1, // Configuration bit No.: 520, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 520 -0, // Configuration bit No.: 582, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 581, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 580, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 579, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 578, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 577, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 576, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 575, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 574, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 573, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 572, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 571, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 570, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 569, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 568, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 567, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 566, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 565, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 564, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 563, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 562, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 561, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 560, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 559, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 558, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 557, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 556, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 555, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 554, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 553, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 552, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 551, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 550, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 549, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 548, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 547, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 546, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 545, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 544, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 543, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 542, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 541, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 540, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 539, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 538, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 537, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 536, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 535, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 534, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 533, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 532, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 531, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 530, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 529, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 528, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 527, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 526, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 525, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 524, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 523, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 522, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 521, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 520, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -0, // Configuration bit No.: 519, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 519 -1, // Configuration bit No.: 455, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 455 -0, // Configuration bit No.: 517, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 516, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 515, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 514, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 513, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 512, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 511, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 510, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 509, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 508, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 507, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 506, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 505, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 504, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 503, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 502, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 501, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 500, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 499, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 498, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 497, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 496, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 495, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 494, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 493, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 492, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 491, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 490, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 489, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 488, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 487, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 486, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 485, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 484, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 483, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 482, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 481, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 480, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 479, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 478, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 477, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 476, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 475, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 474, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 473, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 472, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 471, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 470, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 469, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 468, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 467, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 466, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 465, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 464, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 463, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 462, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 461, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 460, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 459, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 458, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 457, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 456, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 455, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -0, // Configuration bit No.: 454, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 454 -1, // Configuration bit No.: 390, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 390 -0, // Configuration bit No.: 452, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 451, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 450, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 449, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 448, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 447, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 446, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 445, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 444, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 443, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 442, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 441, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 440, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 439, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 438, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 437, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 436, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 435, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 434, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 433, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 432, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 431, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 430, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 429, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 428, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 427, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 426, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 425, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 424, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 423, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 422, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 421, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 420, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 419, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 418, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 417, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 416, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 415, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 414, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 413, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 412, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 411, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 410, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 409, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 408, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 407, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 406, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 405, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 404, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 403, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 402, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 401, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 400, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 399, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 398, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 397, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 396, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 395, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 394, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 393, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 392, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 391, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 390, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -0, // Configuration bit No.: 389, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 389 -1, // Configuration bit No.: 325, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 325 -0, // Configuration bit No.: 387, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 386, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 385, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 384, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 383, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 382, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 381, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 380, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 379, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 378, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 377, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 376, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 375, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 374, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 373, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 372, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 371, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 370, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 369, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 368, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 367, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 366, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 365, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 364, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 363, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 362, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 361, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 360, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 359, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 358, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 357, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 356, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 355, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 354, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 353, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 352, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 351, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 350, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 349, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 348, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 347, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 346, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 345, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 344, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 343, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 342, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 341, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 340, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 339, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 338, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 337, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 336, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 335, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 334, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 333, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 332, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 331, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 330, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 329, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 328, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 327, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 326, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 325, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -0, // Configuration bit No.: 324, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 324 -1, // Configuration bit No.: 260, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 260 -0, // Configuration bit No.: 322, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 321, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 320, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 319, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 318, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 317, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 316, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 315, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 314, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 313, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 312, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 311, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 310, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 309, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 308, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 307, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 306, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 305, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 304, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 303, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 302, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 301, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 300, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 299, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 298, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 297, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 296, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 295, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 294, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 293, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 292, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 291, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 290, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 289, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 288, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 287, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 286, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 285, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 284, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 283, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 282, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 281, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 280, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 279, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 278, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 277, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 276, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 275, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 274, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 273, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 272, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 271, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 270, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 269, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 268, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 267, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 266, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 265, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 264, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 263, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 262, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 261, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 260, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -0, // Configuration bit No.: 259, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 259 -1, // Configuration bit No.: 195, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 195 -0, // Configuration bit No.: 257, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 256, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 255, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 254, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 253, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 252, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 251, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 250, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 249, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 248, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 247, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 246, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 245, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 244, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 243, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 242, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 241, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 240, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 239, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 238, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 237, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 236, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 235, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 234, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 233, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 232, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 231, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 230, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 229, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 228, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 227, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 226, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 225, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 224, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 223, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 222, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 221, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 220, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 219, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 218, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 217, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 216, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 215, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 214, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 213, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 212, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 211, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 210, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 209, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 208, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 207, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 206, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 205, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 204, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 203, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 202, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 201, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 200, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 199, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 198, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 197, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 196, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 195, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -0, // Configuration bit No.: 194, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 194 -1, // Configuration bit No.: 130, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 130 -0, // Configuration bit No.: 192, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 191, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 190, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 189, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 188, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 187, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 186, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 185, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 184, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 183, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 182, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 181, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 180, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 179, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 178, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 177, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 176, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 175, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 174, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 173, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 172, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 171, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 170, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 169, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 168, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 167, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 166, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 165, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 164, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 163, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 162, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 161, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 160, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 159, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 158, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 157, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 156, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 155, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 154, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 153, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 152, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 151, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 150, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 149, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 148, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 147, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 146, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 145, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 144, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 143, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 142, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 141, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 140, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 139, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 138, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 137, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 136, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 135, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 134, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 133, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 132, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 131, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 130, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -0, // Configuration bit No.: 129, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 129 -1, // Configuration bit No.: 65, SRAM value: 1, SPICE model name: sram6T, SPICE model index: 65 -0, // Configuration bit No.: 127, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 126, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 125, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 124, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 123, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 122, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 121, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 120, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 119, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 118, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 117, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 116, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 115, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 114, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 113, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 112, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 111, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 110, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 109, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 108, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 107, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 106, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 105, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 104, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 103, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 102, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 101, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 100, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 99, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 98, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 97, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 96, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 95, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 94, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 93, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 92, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 91, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 90, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 89, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 88, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 87, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 86, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 85, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 84, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 83, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 82, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 81, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 80, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 79, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 78, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 77, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 76, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 75, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 74, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 73, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 72, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 71, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 70, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 69, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 68, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 67, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 66, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 65, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 -0, // Configuration bit No.: 64, SRAM value: 0, SPICE model name: sram6T, SPICE model index: 64 diff --git a/examples/spice_test_example_2/grid_tb/example_2_grid1_1_grid_testbench.sp b/examples/spice_test_example_2/grid_tb/example_2_grid1_1_grid_testbench.sp deleted file mode 100644 index af9b5aa06..000000000 --- a/examples/spice_test_example_2/grid_tb/example_2_grid1_1_grid_testbench.sp +++ /dev/null @@ -1,556 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA Grid Testbench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:09 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -****** Include subckt netlists: Look-Up Tables (LUTs) ***** -.include './spice_test_example_2/subckt/luts.sp' -****** Include subckt netlists: Grid[1][1] ***** -.include './spice_test_example_2/subckt/grid_1_1.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_local_interc gvdd_io gvdd_hardlogic -.global gvdd_sram_local_routing -.global gvdd_sram_luts -.global gvdd_sram_io -***** Global VDD ports of Look-Up Table ***** -.global -+ gvdd_lut6[0] -+ gvdd_lut6[1] -+ gvdd_lut6[2] -+ gvdd_lut6[3] -+ gvdd_lut6[4] -+ gvdd_lut6[5] -+ gvdd_lut6[6] -+ gvdd_lut6[7] -+ gvdd_lut6[8] -+ gvdd_lut6[9] - -***** Global VDD ports of Flip-flop ***** -.global -+ gvdd_dff[0] -+ gvdd_dff[1] -+ gvdd_dff[2] -+ gvdd_dff[3] -+ gvdd_dff[4] -+ gvdd_dff[5] -+ gvdd_dff[6] -+ gvdd_dff[7] -+ gvdd_dff[8] -+ gvdd_dff[9] - -***** Global VDD ports of iopad ***** - -***** Global VDD ports of hard_logic ***** - -Xgrid[1][1] -+ grid[1][1]_pin[0][0][0] -+ grid[1][1]_pin[0][0][4] -+ grid[1][1]_pin[0][0][8] -+ grid[1][1]_pin[0][0][12] -+ grid[1][1]_pin[0][0][16] -+ grid[1][1]_pin[0][0][20] -+ grid[1][1]_pin[0][0][24] -+ grid[1][1]_pin[0][0][28] -+ grid[1][1]_pin[0][0][32] -+ grid[1][1]_pin[0][0][36] -+ grid[1][1]_pin[0][0][40] -+ grid[1][1]_pin[0][0][44] -+ grid[1][1]_pin[0][0][48] -+ grid[1][1]_pin[0][1][1] -+ grid[1][1]_pin[0][1][5] -+ grid[1][1]_pin[0][1][9] -+ grid[1][1]_pin[0][1][13] -+ grid[1][1]_pin[0][1][17] -+ grid[1][1]_pin[0][1][21] -+ grid[1][1]_pin[0][1][25] -+ grid[1][1]_pin[0][1][29] -+ grid[1][1]_pin[0][1][33] -+ grid[1][1]_pin[0][1][37] -+ grid[1][1]_pin[0][1][41] -+ grid[1][1]_pin[0][1][45] -+ grid[1][1]_pin[0][1][49] -+ grid[1][1]_pin[0][2][2] -+ grid[1][1]_pin[0][2][6] -+ grid[1][1]_pin[0][2][10] -+ grid[1][1]_pin[0][2][14] -+ grid[1][1]_pin[0][2][18] -+ grid[1][1]_pin[0][2][22] -+ grid[1][1]_pin[0][2][26] -+ grid[1][1]_pin[0][2][30] -+ grid[1][1]_pin[0][2][34] -+ grid[1][1]_pin[0][2][38] -+ grid[1][1]_pin[0][2][42] -+ grid[1][1]_pin[0][2][46] -+ grid[1][1]_pin[0][2][50] -+ grid[1][1]_pin[0][3][3] -+ grid[1][1]_pin[0][3][7] -+ grid[1][1]_pin[0][3][11] -+ grid[1][1]_pin[0][3][15] -+ grid[1][1]_pin[0][3][19] -+ grid[1][1]_pin[0][3][23] -+ grid[1][1]_pin[0][3][27] -+ grid[1][1]_pin[0][3][31] -+ grid[1][1]_pin[0][3][35] -+ grid[1][1]_pin[0][3][39] -+ grid[1][1]_pin[0][3][43] -+ grid[1][1]_pin[0][3][47] -+ gvdd 0 grid[1][1] -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -Vgvdd_local_interc gvdd_local_interc 0 vsp -Vgvdd_sram_luts gvdd_sram_luts 0 vsp -Vgvdd_sram_local_routing gvdd_sram_local_routing 0 vsp -Vgvdd_sram_io gvdd_sram_io 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** Global VDD for Hard Logics ***** -***** Global VDD for Look-Up Tables (LUTs) ***** -Vgvdd_lut6[0] gvdd_lut6[0] 0 vsp -Rgvdd_lut6[0]_huge gvdd_lut6[0] 0 'vsp/10e-15' -Vgvdd_lut6[1] gvdd_lut6[1] 0 vsp -Rgvdd_lut6[1]_huge gvdd_lut6[1] 0 'vsp/10e-15' -Vgvdd_lut6[2] gvdd_lut6[2] 0 vsp -Rgvdd_lut6[2]_huge gvdd_lut6[2] 0 'vsp/10e-15' -Vgvdd_lut6[3] gvdd_lut6[3] 0 vsp -Rgvdd_lut6[3]_huge gvdd_lut6[3] 0 'vsp/10e-15' -Vgvdd_lut6[4] gvdd_lut6[4] 0 vsp -Rgvdd_lut6[4]_huge gvdd_lut6[4] 0 'vsp/10e-15' -Vgvdd_lut6[5] gvdd_lut6[5] 0 vsp -Rgvdd_lut6[5]_huge gvdd_lut6[5] 0 'vsp/10e-15' -Vgvdd_lut6[6] gvdd_lut6[6] 0 vsp -Rgvdd_lut6[6]_huge gvdd_lut6[6] 0 'vsp/10e-15' -Vgvdd_lut6[7] gvdd_lut6[7] 0 vsp -Rgvdd_lut6[7]_huge gvdd_lut6[7] 0 'vsp/10e-15' -Vgvdd_lut6[8] gvdd_lut6[8] 0 vsp -Rgvdd_lut6[8]_huge gvdd_lut6[8] 0 'vsp/10e-15' -Vgvdd_lut6[9] gvdd_lut6[9] 0 vsp -Rgvdd_lut6[9]_huge gvdd_lut6[9] 0 'vsp/10e-15' -***** Global VDD for Flip-flops (FFs) ***** -Vgvdd_dff[0] gvdd_dff[0] 0 vsp -Rgvdd_dff[0]_huge gvdd_dff[0] 0 'vsp/10e-15' -Vgvdd_dff[1] gvdd_dff[1] 0 vsp -Rgvdd_dff[1]_huge gvdd_dff[1] 0 'vsp/10e-15' -Vgvdd_dff[2] gvdd_dff[2] 0 vsp -Rgvdd_dff[2]_huge gvdd_dff[2] 0 'vsp/10e-15' -Vgvdd_dff[3] gvdd_dff[3] 0 vsp -Rgvdd_dff[3]_huge gvdd_dff[3] 0 'vsp/10e-15' -Vgvdd_dff[4] gvdd_dff[4] 0 vsp -Rgvdd_dff[4]_huge gvdd_dff[4] 0 'vsp/10e-15' -Vgvdd_dff[5] gvdd_dff[5] 0 vsp -Rgvdd_dff[5]_huge gvdd_dff[5] 0 'vsp/10e-15' -Vgvdd_dff[6] gvdd_dff[6] 0 vsp -Rgvdd_dff[6]_huge gvdd_dff[6] 0 'vsp/10e-15' -Vgvdd_dff[7] gvdd_dff[7] 0 vsp -Rgvdd_dff[7]_huge gvdd_dff[7] 0 'vsp/10e-15' -Vgvdd_dff[8] gvdd_dff[8] 0 vsp -Rgvdd_dff[8]_huge gvdd_dff[8] 0 'vsp/10e-15' -Vgvdd_dff[9] gvdd_dff[9] 0 vsp -Rgvdd_dff[9]_huge gvdd_dff[9] 0 'vsp/10e-15' -Vgrid[1][1]_pin[0][0][0] grid[1][1]_pin[0][0][0] 0 -+ 0 -Vgrid[1][1]_pin[0][0][4] grid[1][1]_pin[0][0][4] 0 -+ 0 -Vgrid[1][1]_pin[0][0][8] grid[1][1]_pin[0][0][8] 0 -+ 0 -Vgrid[1][1]_pin[0][0][12] grid[1][1]_pin[0][0][12] 0 -+ 0 -Vgrid[1][1]_pin[0][0][16] grid[1][1]_pin[0][0][16] 0 -+ 0 -Vgrid[1][1]_pin[0][0][20] grid[1][1]_pin[0][0][20] 0 -+ 0 -Vgrid[1][1]_pin[0][0][24] grid[1][1]_pin[0][0][24] 0 -+ 0 -Vgrid[1][1]_pin[0][0][28] grid[1][1]_pin[0][0][28] 0 -+ 0 -Vgrid[1][1]_pin[0][0][32] grid[1][1]_pin[0][0][32] 0 -+ 0 -Vgrid[1][1]_pin[0][0][36] grid[1][1]_pin[0][0][36] 0 -+ 0 -Xgrid[1][1]_pin[0][0][40]_inv[0] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][40]_inv[1] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][40]_inv[2] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][40]_inv[3] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40]_out[3] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][40]_inv[4] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40]_out[4] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][40]_inv[5] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40]_out[5] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][40]_inv[6] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40]_out[6] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][40]_inv[7] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40]_out[7] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][40]_inv[8] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40]_out[8] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][40]_inv[9] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40]_out[9] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][44]_inv[0] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][44]_inv[1] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][44]_inv[2] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][44]_inv[3] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44]_out[3] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][44]_inv[4] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44]_out[4] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][44]_inv[5] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44]_out[5] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][44]_inv[6] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44]_out[6] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][44]_inv[7] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44]_out[7] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][44]_inv[8] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44]_out[8] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][44]_inv[9] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44]_out[9] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][48]_inv[0] grid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][48]_inv[1] grid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][48]_inv[2] grid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][48]_inv[3] grid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48]_out[3] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][48]_inv[4] grid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48]_out[4] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][48]_inv[5] grid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48]_out[5] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][48]_inv[6] grid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48]_out[6] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][48]_inv[7] grid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48]_out[7] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][48]_inv[8] grid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48]_out[8] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][0][48]_inv[9] grid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48]_out[9] gvdd_load 0 inv size=1 -Vgrid[1][1]_pin[0][1][1] grid[1][1]_pin[0][1][1] 0 -+ 0 -Vgrid[1][1]_pin[0][1][5] grid[1][1]_pin[0][1][5] 0 -+ 0 -Vgrid[1][1]_pin[0][1][9] grid[1][1]_pin[0][1][9] 0 -+ 0 -Vgrid[1][1]_pin[0][1][13] grid[1][1]_pin[0][1][13] 0 -+ 0 -Vgrid[1][1]_pin[0][1][17] grid[1][1]_pin[0][1][17] 0 -+ 0 -Vgrid[1][1]_pin[0][1][21] grid[1][1]_pin[0][1][21] 0 -+ 0 -Vgrid[1][1]_pin[0][1][25] grid[1][1]_pin[0][1][25] 0 -+ 0 -Vgrid[1][1]_pin[0][1][29] grid[1][1]_pin[0][1][29] 0 -+ 0 -Vgrid[1][1]_pin[0][1][33] grid[1][1]_pin[0][1][33] 0 -+ 0 -Vgrid[1][1]_pin[0][1][37] grid[1][1]_pin[0][1][37] 0 -+ 0 -Xgrid[1][1]_pin[0][1][41]_inv[0] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][41]_inv[1] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][41]_inv[2] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][41]_inv[3] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41]_out[3] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][41]_inv[4] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41]_out[4] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][41]_inv[5] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41]_out[5] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][41]_inv[6] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41]_out[6] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][41]_inv[7] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41]_out[7] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][41]_inv[8] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41]_out[8] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][41]_inv[9] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41]_out[9] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][45]_inv[0] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][45]_inv[1] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][45]_inv[2] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][45]_inv[3] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45]_out[3] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][45]_inv[4] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45]_out[4] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][45]_inv[5] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45]_out[5] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][45]_inv[6] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45]_out[6] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][45]_inv[7] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45]_out[7] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][45]_inv[8] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45]_out[8] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][45]_inv[9] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45]_out[9] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][49]_inv[0] grid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][49]_inv[1] grid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][49]_inv[2] grid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][49]_inv[3] grid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49]_out[3] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][49]_inv[4] grid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49]_out[4] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][49]_inv[5] grid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49]_out[5] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][49]_inv[6] grid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49]_out[6] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][49]_inv[7] grid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49]_out[7] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][49]_inv[8] grid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49]_out[8] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][1][49]_inv[9] grid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49]_out[9] gvdd_load 0 inv size=1 -Vgrid[1][1]_pin[0][2][2] grid[1][1]_pin[0][2][2] 0 -+ 0 -Vgrid[1][1]_pin[0][2][6] grid[1][1]_pin[0][2][6] 0 -+ 0 -Vgrid[1][1]_pin[0][2][10] grid[1][1]_pin[0][2][10] 0 -+ 0 -Vgrid[1][1]_pin[0][2][14] grid[1][1]_pin[0][2][14] 0 -+ 0 -Vgrid[1][1]_pin[0][2][18] grid[1][1]_pin[0][2][18] 0 -+ 0 -Vgrid[1][1]_pin[0][2][22] grid[1][1]_pin[0][2][22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgrid[1][1]_pin[0][2][26] grid[1][1]_pin[0][2][26] 0 -+ 0 -Vgrid[1][1]_pin[0][2][30] grid[1][1]_pin[0][2][30] 0 -+ 0 -Vgrid[1][1]_pin[0][2][34] grid[1][1]_pin[0][2][34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgrid[1][1]_pin[0][2][38] grid[1][1]_pin[0][2][38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Xgrid[1][1]_pin[0][2][42]_inv[0] grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][42]_inv[1] grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][42]_inv[2] grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][42]_inv[3] grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42]_out[3] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][42]_inv[4] grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42]_out[4] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][42]_inv[5] grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42]_out[5] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][42]_inv[6] grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42]_out[6] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][42]_inv[7] grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42]_out[7] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][42]_inv[8] grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42]_out[8] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][42]_inv[9] grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42]_out[9] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][46]_inv[0] grid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][46]_inv[1] grid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][46]_inv[2] grid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][46]_inv[3] grid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46]_out[3] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][46]_inv[4] grid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46]_out[4] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][46]_inv[5] grid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46]_out[5] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][46]_inv[6] grid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46]_out[6] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][46]_inv[7] grid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46]_out[7] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][46]_inv[8] grid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46]_out[8] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][2][46]_inv[9] grid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46]_out[9] gvdd_load 0 inv size=1 -Vgrid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50] 0 -+ 0 -Vgrid[1][1]_pin[0][3][3] grid[1][1]_pin[0][3][3] 0 -+ 0 -Vgrid[1][1]_pin[0][3][7] grid[1][1]_pin[0][3][7] 0 -+ 0 -Vgrid[1][1]_pin[0][3][11] grid[1][1]_pin[0][3][11] 0 -+ 0 -Vgrid[1][1]_pin[0][3][15] grid[1][1]_pin[0][3][15] 0 -+ 0 -Vgrid[1][1]_pin[0][3][19] grid[1][1]_pin[0][3][19] 0 -+ 0 -Vgrid[1][1]_pin[0][3][23] grid[1][1]_pin[0][3][23] 0 -+ 0 -Vgrid[1][1]_pin[0][3][27] grid[1][1]_pin[0][3][27] 0 -+ 0 -Vgrid[1][1]_pin[0][3][31] grid[1][1]_pin[0][3][31] 0 -+ 0 -Vgrid[1][1]_pin[0][3][35] grid[1][1]_pin[0][3][35] 0 -+ 0 -Vgrid[1][1]_pin[0][3][39] grid[1][1]_pin[0][3][39] 0 -+ 0 -Xgrid[1][1]_pin[0][3][43]_inv[0] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][43]_inv[1] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][43]_inv[2] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][43]_inv[3] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43]_out[3] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][43]_inv[4] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43]_out[4] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][43]_inv[5] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43]_out[5] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][43]_inv[6] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43]_out[6] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][43]_inv[7] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43]_out[7] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][43]_inv[8] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43]_out[8] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][43]_inv[9] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43]_out[9] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][47]_inv[0] grid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47]_out[0] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][47]_inv[1] grid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47]_out[1] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][47]_inv[2] grid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47]_out[2] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][47]_inv[3] grid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47]_out[3] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][47]_inv[4] grid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47]_out[4] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][47]_inv[5] grid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47]_out[5] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][47]_inv[6] grid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47]_out[6] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][47]_inv[7] grid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47]_out[7] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][47]_inv[8] grid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47]_out[8] gvdd_load 0 inv size=1 -Xgrid[1][1]_pin[0][3][47]_inv[9] grid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47]_out[9] gvdd_load 0 inv size=1 -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.measure tran leakage_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from=0 to='clock_period' -.measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period' -.measure tran leakage_power_local_routing avg p(Vgvdd_local_interc) from=0 to='clock_period' -.measure tran leakage_power_lut6[0] avg p(Vgvdd_lut6[0]) from=0 to='clock_period' -.measure tran leakage_power_lut6[1] avg p(Vgvdd_lut6[1]) from=0 to='clock_period' -.measure tran leakage_power_lut6[2] avg p(Vgvdd_lut6[2]) from=0 to='clock_period' -.measure tran leakage_power_lut6[3] avg p(Vgvdd_lut6[3]) from=0 to='clock_period' -.measure tran leakage_power_lut6[4] avg p(Vgvdd_lut6[4]) from=0 to='clock_period' -.measure tran leakage_power_lut6[5] avg p(Vgvdd_lut6[5]) from=0 to='clock_period' -.measure tran leakage_power_lut6[6] avg p(Vgvdd_lut6[6]) from=0 to='clock_period' -.measure tran leakage_power_lut6[7] avg p(Vgvdd_lut6[7]) from=0 to='clock_period' -.measure tran leakage_power_lut6[8] avg p(Vgvdd_lut6[8]) from=0 to='clock_period' -.measure tran leakage_power_lut6[9] avg p(Vgvdd_lut6[9]) from=0 to='clock_period' -.measure tran leakage_power_lut6[0to0] -+ param = 'leakage_power_lut6[0]' -.measure tran leakage_power_lut6[0to1] -+ param = 'leakage_power_lut6[1]+leakage_power_lut6[0to0]' -.measure tran leakage_power_lut6[0to2] -+ param = 'leakage_power_lut6[2]+leakage_power_lut6[0to1]' -.measure tran leakage_power_lut6[0to3] -+ param = 'leakage_power_lut6[3]+leakage_power_lut6[0to2]' -.measure tran leakage_power_lut6[0to4] -+ param = 'leakage_power_lut6[4]+leakage_power_lut6[0to3]' -.measure tran leakage_power_lut6[0to5] -+ param = 'leakage_power_lut6[5]+leakage_power_lut6[0to4]' -.measure tran leakage_power_lut6[0to6] -+ param = 'leakage_power_lut6[6]+leakage_power_lut6[0to5]' -.measure tran leakage_power_lut6[0to7] -+ param = 'leakage_power_lut6[7]+leakage_power_lut6[0to6]' -.measure tran leakage_power_lut6[0to8] -+ param = 'leakage_power_lut6[8]+leakage_power_lut6[0to7]' -.measure tran leakage_power_lut6[0to9] -+ param = 'leakage_power_lut6[9]+leakage_power_lut6[0to8]' -.measure tran total_leakage_power_lut6 -+ param = 'leakage_power_lut6[0to9]' -.measure tran leakage_power_dff[0] avg p(Vgvdd_dff[0]) from=0 to='clock_period' -.measure tran leakage_power_dff[1] avg p(Vgvdd_dff[1]) from=0 to='clock_period' -.measure tran leakage_power_dff[2] avg p(Vgvdd_dff[2]) from=0 to='clock_period' -.measure tran leakage_power_dff[3] avg p(Vgvdd_dff[3]) from=0 to='clock_period' -.measure tran leakage_power_dff[4] avg p(Vgvdd_dff[4]) from=0 to='clock_period' -.measure tran leakage_power_dff[5] avg p(Vgvdd_dff[5]) from=0 to='clock_period' -.measure tran leakage_power_dff[6] avg p(Vgvdd_dff[6]) from=0 to='clock_period' -.measure tran leakage_power_dff[7] avg p(Vgvdd_dff[7]) from=0 to='clock_period' -.measure tran leakage_power_dff[8] avg p(Vgvdd_dff[8]) from=0 to='clock_period' -.measure tran leakage_power_dff[9] avg p(Vgvdd_dff[9]) from=0 to='clock_period' -.measure tran leakage_power_dff[0to0] -+ param = 'leakage_power_dff[0]' -.measure tran leakage_power_dff[0to1] -+ param = 'leakage_power_dff[1]+leakage_power_dff[0to0]' -.measure tran leakage_power_dff[0to2] -+ param = 'leakage_power_dff[2]+leakage_power_dff[0to1]' -.measure tran leakage_power_dff[0to3] -+ param = 'leakage_power_dff[3]+leakage_power_dff[0to2]' -.measure tran leakage_power_dff[0to4] -+ param = 'leakage_power_dff[4]+leakage_power_dff[0to3]' -.measure tran leakage_power_dff[0to5] -+ param = 'leakage_power_dff[5]+leakage_power_dff[0to4]' -.measure tran leakage_power_dff[0to6] -+ param = 'leakage_power_dff[6]+leakage_power_dff[0to5]' -.measure tran leakage_power_dff[0to7] -+ param = 'leakage_power_dff[7]+leakage_power_dff[0to6]' -.measure tran leakage_power_dff[0to8] -+ param = 'leakage_power_dff[8]+leakage_power_dff[0to7]' -.measure tran leakage_power_dff[0to9] -+ param = 'leakage_power_dff[9]+leakage_power_dff[0to8]' -.measure tran total_leakage_power_dff -+ param = 'leakage_power_dff[0to9]' -.measure tran dynamic_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from='clock_period' to='6*clock_period' -.measure tran total_energy_per_cycle_sram_local_routing param='dynamic_power_sram_local_routing*clock_period' -.measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='6*clock_period' -.measure tran total_energy_per_cycle_sram_luts param='dynamic_power_sram_luts*clock_period' -.measure tran dynamic_power_local_interc avg p(Vgvdd_local_interc) from='clock_period' to='6*clock_period' -.measure tran total_energy_per_cycle_local_routing param='dynamic_power_local_interc*clock_period' -.measure tran dynamic_power_lut6[0] avg p(Vgvdd_lut6[0]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[1] avg p(Vgvdd_lut6[1]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[2] avg p(Vgvdd_lut6[2]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[3] avg p(Vgvdd_lut6[3]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[4] avg p(Vgvdd_lut6[4]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[5] avg p(Vgvdd_lut6[5]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[6] avg p(Vgvdd_lut6[6]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[7] avg p(Vgvdd_lut6[7]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[8] avg p(Vgvdd_lut6[8]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[9] avg p(Vgvdd_lut6[9]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[0to0] -+ param = 'dynamic_power_lut6[0]' -.measure tran dynamic_power_lut6[0to1] -+ param = 'dynamic_power_lut6[1]+dynamic_power_lut6[0to0]' -.measure tran dynamic_power_lut6[0to2] -+ param = 'dynamic_power_lut6[2]+dynamic_power_lut6[0to1]' -.measure tran dynamic_power_lut6[0to3] -+ param = 'dynamic_power_lut6[3]+dynamic_power_lut6[0to2]' -.measure tran dynamic_power_lut6[0to4] -+ param = 'dynamic_power_lut6[4]+dynamic_power_lut6[0to3]' -.measure tran dynamic_power_lut6[0to5] -+ param = 'dynamic_power_lut6[5]+dynamic_power_lut6[0to4]' -.measure tran dynamic_power_lut6[0to6] -+ param = 'dynamic_power_lut6[6]+dynamic_power_lut6[0to5]' -.measure tran dynamic_power_lut6[0to7] -+ param = 'dynamic_power_lut6[7]+dynamic_power_lut6[0to6]' -.measure tran dynamic_power_lut6[0to8] -+ param = 'dynamic_power_lut6[8]+dynamic_power_lut6[0to7]' -.measure tran dynamic_power_lut6[0to9] -+ param = 'dynamic_power_lut6[9]+dynamic_power_lut6[0to8]' -.measure tran total_dynamic_power_lut6 -+ param = 'dynamic_power_lut6[0to9]' -.measure tran total_energy_per_cycle_lut6 -+ param = 'dynamic_power_lut6[0to9]*clock_period' -.measure tran dynamic_power_dff[0] avg p(Vgvdd_dff[0]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[1] avg p(Vgvdd_dff[1]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[2] avg p(Vgvdd_dff[2]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[3] avg p(Vgvdd_dff[3]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[4] avg p(Vgvdd_dff[4]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[5] avg p(Vgvdd_dff[5]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[6] avg p(Vgvdd_dff[6]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[7] avg p(Vgvdd_dff[7]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[8] avg p(Vgvdd_dff[8]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[9] avg p(Vgvdd_dff[9]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[0to0] -+ param = 'dynamic_power_dff[0]' -.measure tran dynamic_power_dff[0to1] -+ param = 'dynamic_power_dff[1]+dynamic_power_dff[0to0]' -.measure tran dynamic_power_dff[0to2] -+ param = 'dynamic_power_dff[2]+dynamic_power_dff[0to1]' -.measure tran dynamic_power_dff[0to3] -+ param = 'dynamic_power_dff[3]+dynamic_power_dff[0to2]' -.measure tran dynamic_power_dff[0to4] -+ param = 'dynamic_power_dff[4]+dynamic_power_dff[0to3]' -.measure tran dynamic_power_dff[0to5] -+ param = 'dynamic_power_dff[5]+dynamic_power_dff[0to4]' -.measure tran dynamic_power_dff[0to6] -+ param = 'dynamic_power_dff[6]+dynamic_power_dff[0to5]' -.measure tran dynamic_power_dff[0to7] -+ param = 'dynamic_power_dff[7]+dynamic_power_dff[0to6]' -.measure tran dynamic_power_dff[0to8] -+ param = 'dynamic_power_dff[8]+dynamic_power_dff[0to7]' -.measure tran dynamic_power_dff[0to9] -+ param = 'dynamic_power_dff[9]+dynamic_power_dff[0to8]' -.measure tran total_dynamic_power_dff -+ param = 'dynamic_power_dff[0to9]' -.measure tran total_energy_per_cycle_dff -+ param = 'dynamic_power_dff[0to9]*clock_period' -.end diff --git a/examples/spice_test_example_2/hardlogic_tb/example_2_grid1_1_hardlogic_testbench.sp b/examples/spice_test_example_2/hardlogic_tb/example_2_grid1_1_hardlogic_testbench.sp deleted file mode 100644 index c95c0d4dd..000000000 --- a/examples/spice_test_example_2/hardlogic_tb/example_2_grid1_1_hardlogic_testbench.sp +++ /dev/null @@ -1,346 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA Hard Logic Testbench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:09 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_load -***** Global VDD ports of Flip-flop ***** -.global -+ gvdd_dff[0] -+ gvdd_dff[1] -+ gvdd_dff[2] -+ gvdd_dff[3] -+ gvdd_dff[4] -+ gvdd_dff[5] -+ gvdd_dff[6] -+ gvdd_dff[7] -+ gvdd_dff[8] -+ gvdd_dff[9] - -***** Global VDD ports of hard_logic ***** - -***** Global VDD ports of iopad ***** - -.global gvdd_sram_io -***** Hardlogic[10]: logical_block_index[-1], gvdd_index[-1]***** -Xhardlogic_dff[0] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[0]->D[0] -+ hardlogic_dff[0]->Q[0] -+ gvdd_dff[0] ggnd -+ static_dff -Vhardlogic_dff[0]->D[0] hardlogic_dff[0]->D[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Xload_inv[0]_no0 hardlogic_dff[0]->Q[0] hardlogic_dff[0]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Hardlogic[10]: logical_block_index[-1], gvdd_index[-1]***** -Xhardlogic_dff[1] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[1]->D[0] -+ hardlogic_dff[1]->Q[0] -+ gvdd_dff[1] ggnd -+ static_dff -Vhardlogic_dff[1]->D[0] hardlogic_dff[1]->D[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Xload_inv[1]_no0 hardlogic_dff[1]->Q[0] hardlogic_dff[1]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Hardlogic[10]: logical_block_index[-1], gvdd_index[-1]***** -Xhardlogic_dff[2] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[2]->D[0] -+ hardlogic_dff[2]->Q[0] -+ gvdd_dff[2] ggnd -+ static_dff -Vhardlogic_dff[2]->D[0] hardlogic_dff[2]->D[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Xload_inv[2]_no0 hardlogic_dff[2]->Q[0] hardlogic_dff[2]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Hardlogic[10]: logical_block_index[-1], gvdd_index[-1]***** -Xhardlogic_dff[3] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[3]->D[0] -+ hardlogic_dff[3]->Q[0] -+ gvdd_dff[3] ggnd -+ static_dff -Vhardlogic_dff[3]->D[0] hardlogic_dff[3]->D[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Xload_inv[3]_no0 hardlogic_dff[3]->Q[0] hardlogic_dff[3]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Hardlogic[10]: logical_block_index[-1], gvdd_index[-1]***** -Xhardlogic_dff[4] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[4]->D[0] -+ hardlogic_dff[4]->Q[0] -+ gvdd_dff[4] ggnd -+ static_dff -Vhardlogic_dff[4]->D[0] hardlogic_dff[4]->D[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Xload_inv[4]_no0 hardlogic_dff[4]->Q[0] hardlogic_dff[4]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Hardlogic[10]: logical_block_index[-1], gvdd_index[-1]***** -Xhardlogic_dff[5] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[5]->D[0] -+ hardlogic_dff[5]->Q[0] -+ gvdd_dff[5] ggnd -+ static_dff -Vhardlogic_dff[5]->D[0] hardlogic_dff[5]->D[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Xload_inv[5]_no0 hardlogic_dff[5]->Q[0] hardlogic_dff[5]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Hardlogic[10]: logical_block_index[-1], gvdd_index[-1]***** -Xhardlogic_dff[6] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[6]->D[0] -+ hardlogic_dff[6]->Q[0] -+ gvdd_dff[6] ggnd -+ static_dff -Vhardlogic_dff[6]->D[0] hardlogic_dff[6]->D[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Xload_inv[6]_no0 hardlogic_dff[6]->Q[0] hardlogic_dff[6]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Hardlogic[10]: logical_block_index[-1], gvdd_index[-1]***** -Xhardlogic_dff[7] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[7]->D[0] -+ hardlogic_dff[7]->Q[0] -+ gvdd_dff[7] ggnd -+ static_dff -Vhardlogic_dff[7]->D[0] hardlogic_dff[7]->D[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Xload_inv[7]_no0 hardlogic_dff[7]->Q[0] hardlogic_dff[7]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Hardlogic[10]: logical_block_index[-1], gvdd_index[-1]***** -Xhardlogic_dff[8] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[8]->D[0] -+ hardlogic_dff[8]->Q[0] -+ gvdd_dff[8] ggnd -+ static_dff -Vhardlogic_dff[8]->D[0] hardlogic_dff[8]->D[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Xload_inv[8]_no0 hardlogic_dff[8]->Q[0] hardlogic_dff[8]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Hardlogic[10]: logical_block_index[3], gvdd_index[9]***** -Xhardlogic_dff[9] - -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ hardlogic_dff[9]->D[0] -+ hardlogic_dff[9]->Q[0] -+ gvdd_dff[9] ggnd -+ static_dff -Vhardlogic_dff[9]->D[0] hardlogic_dff[9]->D[0] 0 -+ pulse(vsp 0 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*19.8147*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '19.8147*clock_period') -Xload_inv[9]_no0 hardlogic_dff[9]->Q[0] hardlogic_dff[9]->Q[0]_out[0] gvdd_load 0 inv size=1 -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** Global VDD for FFs ***** -Vgvdd_dff[0] gvdd_dff[0] 0 vsp -Rgvdd_dff[0]_huge gvdd_dff[0] 0 'vsp/10e-15' -Vgvdd_dff[1] gvdd_dff[1] 0 vsp -Rgvdd_dff[1]_huge gvdd_dff[1] 0 'vsp/10e-15' -Vgvdd_dff[2] gvdd_dff[2] 0 vsp -Rgvdd_dff[2]_huge gvdd_dff[2] 0 'vsp/10e-15' -Vgvdd_dff[3] gvdd_dff[3] 0 vsp -Rgvdd_dff[3]_huge gvdd_dff[3] 0 'vsp/10e-15' -Vgvdd_dff[4] gvdd_dff[4] 0 vsp -Rgvdd_dff[4]_huge gvdd_dff[4] 0 'vsp/10e-15' -Vgvdd_dff[5] gvdd_dff[5] 0 vsp -Rgvdd_dff[5]_huge gvdd_dff[5] 0 'vsp/10e-15' -Vgvdd_dff[6] gvdd_dff[6] 0 vsp -Rgvdd_dff[6]_huge gvdd_dff[6] 0 'vsp/10e-15' -Vgvdd_dff[7] gvdd_dff[7] 0 vsp -Rgvdd_dff[7]_huge gvdd_dff[7] 0 'vsp/10e-15' -Vgvdd_dff[8] gvdd_dff[8] 0 vsp -Rgvdd_dff[8]_huge gvdd_dff[8] 0 'vsp/10e-15' -Vgvdd_dff[9] gvdd_dff[9] 0 vsp -Rgvdd_dff[9]_huge gvdd_dff[9] 0 'vsp/10e-15' -***** Global VDD for Hardlogics ***** -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.measure tran leakage_power_dff[0] avg p(Vgvdd_dff[0]) from=0 to='clock_period' -.measure tran leakage_power_dff[1] avg p(Vgvdd_dff[1]) from=0 to='clock_period' -.measure tran leakage_power_dff[2] avg p(Vgvdd_dff[2]) from=0 to='clock_period' -.measure tran leakage_power_dff[3] avg p(Vgvdd_dff[3]) from=0 to='clock_period' -.measure tran leakage_power_dff[4] avg p(Vgvdd_dff[4]) from=0 to='clock_period' -.measure tran leakage_power_dff[5] avg p(Vgvdd_dff[5]) from=0 to='clock_period' -.measure tran leakage_power_dff[6] avg p(Vgvdd_dff[6]) from=0 to='clock_period' -.measure tran leakage_power_dff[7] avg p(Vgvdd_dff[7]) from=0 to='clock_period' -.measure tran leakage_power_dff[8] avg p(Vgvdd_dff[8]) from=0 to='clock_period' -.measure tran leakage_power_dff[9] avg p(Vgvdd_dff[9]) from=0 to='clock_period' -.measure tran leakage_power_dff[0to0] -+ param = 'leakage_power_dff[0]' -.measure tran leakage_power_dff[0to1] -+ param = 'leakage_power_dff[1]+leakage_power_dff[0to0]' -.measure tran leakage_power_dff[0to2] -+ param = 'leakage_power_dff[2]+leakage_power_dff[0to1]' -.measure tran leakage_power_dff[0to3] -+ param = 'leakage_power_dff[3]+leakage_power_dff[0to2]' -.measure tran leakage_power_dff[0to4] -+ param = 'leakage_power_dff[4]+leakage_power_dff[0to3]' -.measure tran leakage_power_dff[0to5] -+ param = 'leakage_power_dff[5]+leakage_power_dff[0to4]' -.measure tran leakage_power_dff[0to6] -+ param = 'leakage_power_dff[6]+leakage_power_dff[0to5]' -.measure tran leakage_power_dff[0to7] -+ param = 'leakage_power_dff[7]+leakage_power_dff[0to6]' -.measure tran leakage_power_dff[0to8] -+ param = 'leakage_power_dff[8]+leakage_power_dff[0to7]' -.measure tran leakage_power_dff[0to9] -+ param = 'leakage_power_dff[9]+leakage_power_dff[0to8]' -.measure tran total_leakage_power_dff -+ param = 'leakage_power_dff[0to9]' -.measure tran dynamic_power_dff[0] avg p(Vgvdd_dff[0]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[1] avg p(Vgvdd_dff[1]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[2] avg p(Vgvdd_dff[2]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[3] avg p(Vgvdd_dff[3]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[4] avg p(Vgvdd_dff[4]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[5] avg p(Vgvdd_dff[5]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[6] avg p(Vgvdd_dff[6]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[7] avg p(Vgvdd_dff[7]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[8] avg p(Vgvdd_dff[8]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[9] avg p(Vgvdd_dff[9]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[0to0] -+ param = 'dynamic_power_dff[0]' -.measure tran dynamic_power_dff[0to1] -+ param = 'dynamic_power_dff[1]+dynamic_power_dff[0to0]' -.measure tran dynamic_power_dff[0to2] -+ param = 'dynamic_power_dff[2]+dynamic_power_dff[0to1]' -.measure tran dynamic_power_dff[0to3] -+ param = 'dynamic_power_dff[3]+dynamic_power_dff[0to2]' -.measure tran dynamic_power_dff[0to4] -+ param = 'dynamic_power_dff[4]+dynamic_power_dff[0to3]' -.measure tran dynamic_power_dff[0to5] -+ param = 'dynamic_power_dff[5]+dynamic_power_dff[0to4]' -.measure tran dynamic_power_dff[0to6] -+ param = 'dynamic_power_dff[6]+dynamic_power_dff[0to5]' -.measure tran dynamic_power_dff[0to7] -+ param = 'dynamic_power_dff[7]+dynamic_power_dff[0to6]' -.measure tran dynamic_power_dff[0to8] -+ param = 'dynamic_power_dff[8]+dynamic_power_dff[0to7]' -.measure tran dynamic_power_dff[0to9] -+ param = 'dynamic_power_dff[9]+dynamic_power_dff[0to8]' -.measure tran total_dynamic_power_dff -+ param = 'dynamic_power_dff[0to9]' -.measure tran total_energy_per_cycle_dff -+ param = 'dynamic_power_dff[0to9]*clock_period' -.end diff --git a/examples/spice_test_example_2/include/design_params.sp b/examples/spice_test_example_2/include/design_params.sp deleted file mode 100644 index 030c9824e..000000000 --- a/examples/spice_test_example_2/include/design_params.sp +++ /dev/null @@ -1,73 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Parameters for Circuit Designs * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Technology Library ****** -.lib '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/subvt_fpga/process/tsmc40nm/toplevel.l' TOP_TT -****** Transistor Parameters ****** -.param beta=2 -.param nl=4e-08 -.param wn=1.4e-07 -.param pl=4e-08 -.param wp=1.4e-07 -.param io_nl=2.7e-07 -.param io_wn=3.2e-07 -.param io_pl=2.7e-07 -.param io_wp=3.2e-07 -.param vsp=0.9 -.param io_vsp=2.5 -***** Parameters for Circuits ***** -***** Parameters for SPICE MODEL: INVTX1 ***** -***** Parameters for SPICE MODEL: buf4 ***** -***** Parameters for SPICE MODEL: tap_buf4 ***** -***** Parameters for SPICE MODEL: TGATE ***** -***** Parameters for SPICE MODEL: chan_segment ***** -.param chan_segment_wire_param_res_val=101 -.param chan_segment_wire_param_cap_val=2.25e-14 -***** Parameters for SPICE MODEL: direct_interc ***** -.param direct_interc_wire_param_res_val=0 -.param direct_interc_wire_param_cap_val=0 -***** Parameters for SPICE MODEL: mux_1level_tapbuf ***** -.param mux_1level_tapbuf_input_buf_size=1 -.param mux_1level_tapbuf_output_buf_size=1 -.param mux_1level_tapbuf_pgl_pmos_size=2 -.param mux_1level_tapbuf_pgl_nmos_size=1 -***** Parameters for SPICE MODEL: mux_2level ***** -.param mux_2level_input_buf_size=1 -.param mux_2level_output_buf_size=1 -.param mux_2level_pgl_pmos_size=2 -.param mux_2level_pgl_nmos_size=1 -***** Parameters for SPICE MODEL: mux_2level_tapbuf ***** -.param mux_2level_tapbuf_input_buf_size=1 -.param mux_2level_tapbuf_output_buf_size=1 -.param mux_2level_tapbuf_pgl_pmos_size=2 -.param mux_2level_tapbuf_pgl_nmos_size=1 -***** Parameters for SPICE MODEL: static_dff ***** -.param static_dff_input_buf_size=1 -.param static_dff_output_buf_size=1 -.param static_dff_pgl_pmos_size=2.22937e-38 -.param static_dff_pgl_nmos_size=0 -***** Parameters for SPICE MODEL: lut6 ***** -.param lut6_input_buf_size=1 -.param lut6_output_buf_size=1 -.param lut6_pgl_pmos_size=2 -.param lut6_pgl_nmos_size=1 -***** Parameters for SPICE MODEL: sram6T ***** -.param sram6T_input_buf_size=1 -.param sram6T_output_buf_size=1 -.param sram6T_pgl_pmos_size=2.22995e-38 -.param sram6T_pgl_nmos_size=0 -***** Parameters for SPICE MODEL: sram6T_blwl ***** -.param sram6T_blwl_input_buf_size=1 -.param sram6T_blwl_output_buf_size=1 -.param sram6T_blwl_pgl_pmos_size=2.23018e-38 -.param sram6T_blwl_pgl_nmos_size=0 -***** Parameters for SPICE MODEL: iopad ***** -.param iopad_input_buf_size=1 -.param iopad_output_buf_size=1 -.param iopad_pgl_pmos_size=2.23051e-38 -.param iopad_pgl_nmos_size=0 diff --git a/examples/spice_test_example_2/include/meas_params.sp b/examples/spice_test_example_2/include/meas_params.sp deleted file mode 100644 index 786299c13..000000000 --- a/examples/spice_test_example_2/include/meas_params.sp +++ /dev/null @@ -1,22 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Parameters for measurement * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Parameters For Slew Measurement ***** -***** Rising Edge ***** -.param slew_upper_thres_pct_rise=0.95 -.param slew_lower_thres_pct_rise=0.05 -***** Falling Edge ***** -.param slew_upper_thres_pct_fall=0.05 -.param slew_lower_thres_pct_fall=0.95 -***** Parameters For Delay Measurement ***** -***** Rising Edge ***** -.param input_thres_pct_rise=0.5 -.param output_thres_pct_rise=0.5 -***** Falling Edge ***** -.param input_thres_pct_fall=0.5 -.param output_thres_pct_fall=0.5 diff --git a/examples/spice_test_example_2/include/stimulate_params.sp b/examples/spice_test_example_2/include/stimulate_params.sp deleted file mode 100644 index 2d70a54e5..000000000 --- a/examples/spice_test_example_2/include/stimulate_params.sp +++ /dev/null @@ -1,17 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Parameters for Stimulations * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Frequency ***** -.param clock_period=4.10047e-10 -***** Parameters For Input Stimulations ***** -.param input_slew_pct_rise='2.5e-11/clock_period' -.param input_slew_pct_fall='2.5e-11/clock_period' -***** Parameters For Clock Stimulations ***** -***** Slew ***** -.param clock_slew_pct_rise='2e-11/clock_period' -.param clock_slew_pct_fall='2e-11/clock_period' diff --git a/examples/spice_test_example_2/lut_tb/example_2_grid1_1_lut_testbench.sp b/examples/spice_test_example_2/lut_tb/example_2_grid1_1_lut_testbench.sp deleted file mode 100644 index d1a3ef08c..000000000 --- a/examples/spice_test_example_2/lut_tb/example_2_grid1_1_lut_testbench.sp +++ /dev/null @@ -1,362 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA LUT Testbench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:09 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -****** Include subckt netlists: Look-Up Tables (LUTs) ***** -.include './spice_test_example_2/subckt/luts.sp' -****** Include subckt netlists: Grid[1][1] ***** -.include './spice_test_example_2/subckt/grid_1_1.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_luts -.global gvdd_load -***** Global VDD ports of Look-Up Table ***** -.global -+ gvdd_lut6[0] -+ gvdd_lut6[1] -+ gvdd_lut6[2] -+ gvdd_lut6[3] -+ gvdd_lut6[4] -+ gvdd_lut6[5] -+ gvdd_lut6[6] -+ gvdd_lut6[7] -+ gvdd_lut6[8] -+ gvdd_lut6[9] - -***** LUT[0]: logical_block_index[-1], gvdd_index[-1]***** -Xlut[0] lut[0]->in[0] lut[0]->in[1] lut[0]->in[2] lut[0]->in[3] lut[0]->in[4] lut[0]->in[5] lut[0]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Vlut[0]->in[0] lut[0]->in[0] 0 -+ 0 -Vlut[0]->in[1] lut[0]->in[1] 0 -+ 0 -Vlut[0]->in[2] lut[0]->in[2] 0 -+ 0 -Vlut[0]->in[3] lut[0]->in[3] 0 -+ 0 -Vlut[0]->in[4] lut[0]->in[4] 0 -+ 0 -Vlut[0]->in[5] lut[0]->in[5] 0 -+ 0 -Xload_inv[0]_no0 lut[0]->out lut[0]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 lut[0]->out lut[0]->out_out[1] gvdd_load 0 inv size=1 -***** LUT[1]: logical_block_index[-1], gvdd_index[-1]***** -Xlut[1] lut[1]->in[0] lut[1]->in[1] lut[1]->in[2] lut[1]->in[3] lut[1]->in[4] lut[1]->in[5] lut[1]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[1]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Vlut[1]->in[0] lut[1]->in[0] 0 -+ 0 -Vlut[1]->in[1] lut[1]->in[1] 0 -+ 0 -Vlut[1]->in[2] lut[1]->in[2] 0 -+ 0 -Vlut[1]->in[3] lut[1]->in[3] 0 -+ 0 -Vlut[1]->in[4] lut[1]->in[4] 0 -+ 0 -Vlut[1]->in[5] lut[1]->in[5] 0 -+ 0 -Xload_inv[2]_no0 lut[1]->out lut[1]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 lut[1]->out lut[1]->out_out[1] gvdd_load 0 inv size=1 -***** LUT[2]: logical_block_index[-1], gvdd_index[-1]***** -Xlut[2] lut[2]->in[0] lut[2]->in[1] lut[2]->in[2] lut[2]->in[3] lut[2]->in[4] lut[2]->in[5] lut[2]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[2]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Vlut[2]->in[0] lut[2]->in[0] 0 -+ 0 -Vlut[2]->in[1] lut[2]->in[1] 0 -+ 0 -Vlut[2]->in[2] lut[2]->in[2] 0 -+ 0 -Vlut[2]->in[3] lut[2]->in[3] 0 -+ 0 -Vlut[2]->in[4] lut[2]->in[4] 0 -+ 0 -Vlut[2]->in[5] lut[2]->in[5] 0 -+ 0 -Xload_inv[4]_no0 lut[2]->out lut[2]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 lut[2]->out lut[2]->out_out[1] gvdd_load 0 inv size=1 -***** LUT[3]: logical_block_index[-1], gvdd_index[-1]***** -Xlut[3] lut[3]->in[0] lut[3]->in[1] lut[3]->in[2] lut[3]->in[3] lut[3]->in[4] lut[3]->in[5] lut[3]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[3]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Vlut[3]->in[0] lut[3]->in[0] 0 -+ 0 -Vlut[3]->in[1] lut[3]->in[1] 0 -+ 0 -Vlut[3]->in[2] lut[3]->in[2] 0 -+ 0 -Vlut[3]->in[3] lut[3]->in[3] 0 -+ 0 -Vlut[3]->in[4] lut[3]->in[4] 0 -+ 0 -Vlut[3]->in[5] lut[3]->in[5] 0 -+ 0 -Xload_inv[6]_no0 lut[3]->out lut[3]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 lut[3]->out lut[3]->out_out[1] gvdd_load 0 inv size=1 -***** LUT[4]: logical_block_index[-1], gvdd_index[-1]***** -Xlut[4] lut[4]->in[0] lut[4]->in[1] lut[4]->in[2] lut[4]->in[3] lut[4]->in[4] lut[4]->in[5] lut[4]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[4]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Vlut[4]->in[0] lut[4]->in[0] 0 -+ 0 -Vlut[4]->in[1] lut[4]->in[1] 0 -+ 0 -Vlut[4]->in[2] lut[4]->in[2] 0 -+ 0 -Vlut[4]->in[3] lut[4]->in[3] 0 -+ 0 -Vlut[4]->in[4] lut[4]->in[4] 0 -+ 0 -Vlut[4]->in[5] lut[4]->in[5] 0 -+ 0 -Xload_inv[8]_no0 lut[4]->out lut[4]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 lut[4]->out lut[4]->out_out[1] gvdd_load 0 inv size=1 -***** LUT[5]: logical_block_index[-1], gvdd_index[-1]***** -Xlut[5] lut[5]->in[0] lut[5]->in[1] lut[5]->in[2] lut[5]->in[3] lut[5]->in[4] lut[5]->in[5] lut[5]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[5]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Vlut[5]->in[0] lut[5]->in[0] 0 -+ 0 -Vlut[5]->in[1] lut[5]->in[1] 0 -+ 0 -Vlut[5]->in[2] lut[5]->in[2] 0 -+ 0 -Vlut[5]->in[3] lut[5]->in[3] 0 -+ 0 -Vlut[5]->in[4] lut[5]->in[4] 0 -+ 0 -Vlut[5]->in[5] lut[5]->in[5] 0 -+ 0 -Xload_inv[10]_no0 lut[5]->out lut[5]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 lut[5]->out lut[5]->out_out[1] gvdd_load 0 inv size=1 -***** LUT[6]: logical_block_index[-1], gvdd_index[-1]***** -Xlut[6] lut[6]->in[0] lut[6]->in[1] lut[6]->in[2] lut[6]->in[3] lut[6]->in[4] lut[6]->in[5] lut[6]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[6]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Vlut[6]->in[0] lut[6]->in[0] 0 -+ 0 -Vlut[6]->in[1] lut[6]->in[1] 0 -+ 0 -Vlut[6]->in[2] lut[6]->in[2] 0 -+ 0 -Vlut[6]->in[3] lut[6]->in[3] 0 -+ 0 -Vlut[6]->in[4] lut[6]->in[4] 0 -+ 0 -Vlut[6]->in[5] lut[6]->in[5] 0 -+ 0 -Xload_inv[12]_no0 lut[6]->out lut[6]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 lut[6]->out lut[6]->out_out[1] gvdd_load 0 inv size=1 -***** LUT[7]: logical_block_index[-1], gvdd_index[-1]***** -Xlut[7] lut[7]->in[0] lut[7]->in[1] lut[7]->in[2] lut[7]->in[3] lut[7]->in[4] lut[7]->in[5] lut[7]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[7]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Vlut[7]->in[0] lut[7]->in[0] 0 -+ 0 -Vlut[7]->in[1] lut[7]->in[1] 0 -+ 0 -Vlut[7]->in[2] lut[7]->in[2] 0 -+ 0 -Vlut[7]->in[3] lut[7]->in[3] 0 -+ 0 -Vlut[7]->in[4] lut[7]->in[4] 0 -+ 0 -Vlut[7]->in[5] lut[7]->in[5] 0 -+ 0 -Xload_inv[14]_no0 lut[7]->out lut[7]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 lut[7]->out lut[7]->out_out[1] gvdd_load 0 inv size=1 -***** LUT[8]: logical_block_index[-1], gvdd_index[-1]***** -Xlut[8] lut[8]->in[0] lut[8]->in[1] lut[8]->in[2] lut[8]->in[3] lut[8]->in[4] lut[8]->in[5] lut[8]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[8]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Vlut[8]->in[0] lut[8]->in[0] 0 -+ 0 -Vlut[8]->in[1] lut[8]->in[1] 0 -+ 0 -Vlut[8]->in[2] lut[8]->in[2] 0 -+ 0 -Vlut[8]->in[3] lut[8]->in[3] 0 -+ 0 -Vlut[8]->in[4] lut[8]->in[4] 0 -+ 0 -Vlut[8]->in[5] lut[8]->in[5] 0 -+ 0 -Xload_inv[16]_no0 lut[8]->out lut[8]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 lut[8]->out lut[8]->out_out[1] gvdd_load 0 inv size=1 -***** LUT[9]: logical_block_index[4], gvdd_index[9]***** -Xlut[9] lut[9]->in[0] lut[9]->in[1] lut[9]->in[2] lut[9]->in[3] lut[9]->in[4] lut[9]->in[5] lut[9]->out gvdd 0 grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Vlut[9]->in[0] lut[9]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vlut[9]->in[1] lut[9]->in[1] 0 -+ 0 -Vlut[9]->in[2] lut[9]->in[2] 0 -+ 0 -Vlut[9]->in[3] lut[9]->in[3] 0 -+ 0 -Vlut[9]->in[4] lut[9]->in[4] 0 -+ 0 -Vlut[9]->in[5] lut[9]->in[5] 0 -+ 0 -Xload_inv[18]_no0 lut[9]->out lut[9]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 lut[9]->out lut[9]->out_out[1] gvdd_load 0 inv size=1 -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for LUTs SRAMs ***** -Vgvdd_sram_luts gvdd_sram_luts 0 vsp -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** Global VDD for Look-Up Tables (LUTs) ***** -Vgvdd_lut6[0] gvdd_lut6[0] 0 vsp -Rgvdd_lut6[0]_huge gvdd_lut6[0] 0 'vsp/10e-15' -Vgvdd_lut6[1] gvdd_lut6[1] 0 vsp -Rgvdd_lut6[1]_huge gvdd_lut6[1] 0 'vsp/10e-15' -Vgvdd_lut6[2] gvdd_lut6[2] 0 vsp -Rgvdd_lut6[2]_huge gvdd_lut6[2] 0 'vsp/10e-15' -Vgvdd_lut6[3] gvdd_lut6[3] 0 vsp -Rgvdd_lut6[3]_huge gvdd_lut6[3] 0 'vsp/10e-15' -Vgvdd_lut6[4] gvdd_lut6[4] 0 vsp -Rgvdd_lut6[4]_huge gvdd_lut6[4] 0 'vsp/10e-15' -Vgvdd_lut6[5] gvdd_lut6[5] 0 vsp -Rgvdd_lut6[5]_huge gvdd_lut6[5] 0 'vsp/10e-15' -Vgvdd_lut6[6] gvdd_lut6[6] 0 vsp -Rgvdd_lut6[6]_huge gvdd_lut6[6] 0 'vsp/10e-15' -Vgvdd_lut6[7] gvdd_lut6[7] 0 vsp -Rgvdd_lut6[7]_huge gvdd_lut6[7] 0 'vsp/10e-15' -Vgvdd_lut6[8] gvdd_lut6[8] 0 vsp -Rgvdd_lut6[8]_huge gvdd_lut6[8] 0 'vsp/10e-15' -Vgvdd_lut6[9] gvdd_lut6[9] 0 vsp -Rgvdd_lut6[9]_huge gvdd_lut6[9] 0 'vsp/10e-15' -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period' -.measure tran leakage_power_lut6[0] avg p(Vgvdd_lut6[0]) from=0 to='clock_period' -.measure tran leakage_power_lut6[1] avg p(Vgvdd_lut6[1]) from=0 to='clock_period' -.measure tran leakage_power_lut6[2] avg p(Vgvdd_lut6[2]) from=0 to='clock_period' -.measure tran leakage_power_lut6[3] avg p(Vgvdd_lut6[3]) from=0 to='clock_period' -.measure tran leakage_power_lut6[4] avg p(Vgvdd_lut6[4]) from=0 to='clock_period' -.measure tran leakage_power_lut6[5] avg p(Vgvdd_lut6[5]) from=0 to='clock_period' -.measure tran leakage_power_lut6[6] avg p(Vgvdd_lut6[6]) from=0 to='clock_period' -.measure tran leakage_power_lut6[7] avg p(Vgvdd_lut6[7]) from=0 to='clock_period' -.measure tran leakage_power_lut6[8] avg p(Vgvdd_lut6[8]) from=0 to='clock_period' -.measure tran leakage_power_lut6[9] avg p(Vgvdd_lut6[9]) from=0 to='clock_period' -.measure tran leakage_power_lut6[0to0] -+ param = 'leakage_power_lut6[0]' -.measure tran leakage_power_lut6[0to1] -+ param = 'leakage_power_lut6[1]+leakage_power_lut6[0to0]' -.measure tran leakage_power_lut6[0to2] -+ param = 'leakage_power_lut6[2]+leakage_power_lut6[0to1]' -.measure tran leakage_power_lut6[0to3] -+ param = 'leakage_power_lut6[3]+leakage_power_lut6[0to2]' -.measure tran leakage_power_lut6[0to4] -+ param = 'leakage_power_lut6[4]+leakage_power_lut6[0to3]' -.measure tran leakage_power_lut6[0to5] -+ param = 'leakage_power_lut6[5]+leakage_power_lut6[0to4]' -.measure tran leakage_power_lut6[0to6] -+ param = 'leakage_power_lut6[6]+leakage_power_lut6[0to5]' -.measure tran leakage_power_lut6[0to7] -+ param = 'leakage_power_lut6[7]+leakage_power_lut6[0to6]' -.measure tran leakage_power_lut6[0to8] -+ param = 'leakage_power_lut6[8]+leakage_power_lut6[0to7]' -.measure tran leakage_power_lut6[0to9] -+ param = 'leakage_power_lut6[9]+leakage_power_lut6[0to8]' -.measure tran total_leakage_power_lut6 -+ param = 'leakage_power_lut6[0to9]' -.measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='6*clock_period' -.measure tran energy_per_cycle_sram_luts param='dynamic_power_sram_luts*clock_period' -.measure tran dynamic_power_lut6[0] avg p(Vgvdd_lut6[0]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[1] avg p(Vgvdd_lut6[1]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[2] avg p(Vgvdd_lut6[2]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[3] avg p(Vgvdd_lut6[3]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[4] avg p(Vgvdd_lut6[4]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[5] avg p(Vgvdd_lut6[5]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[6] avg p(Vgvdd_lut6[6]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[7] avg p(Vgvdd_lut6[7]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[8] avg p(Vgvdd_lut6[8]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[9] avg p(Vgvdd_lut6[9]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[0to0] -+ param = 'dynamic_power_lut6[0]' -.measure tran dynamic_power_lut6[0to1] -+ param = 'dynamic_power_lut6[1]+dynamic_power_lut6[0to0]' -.measure tran dynamic_power_lut6[0to2] -+ param = 'dynamic_power_lut6[2]+dynamic_power_lut6[0to1]' -.measure tran dynamic_power_lut6[0to3] -+ param = 'dynamic_power_lut6[3]+dynamic_power_lut6[0to2]' -.measure tran dynamic_power_lut6[0to4] -+ param = 'dynamic_power_lut6[4]+dynamic_power_lut6[0to3]' -.measure tran dynamic_power_lut6[0to5] -+ param = 'dynamic_power_lut6[5]+dynamic_power_lut6[0to4]' -.measure tran dynamic_power_lut6[0to6] -+ param = 'dynamic_power_lut6[6]+dynamic_power_lut6[0to5]' -.measure tran dynamic_power_lut6[0to7] -+ param = 'dynamic_power_lut6[7]+dynamic_power_lut6[0to6]' -.measure tran dynamic_power_lut6[0to8] -+ param = 'dynamic_power_lut6[8]+dynamic_power_lut6[0to7]' -.measure tran dynamic_power_lut6[0to9] -+ param = 'dynamic_power_lut6[9]+dynamic_power_lut6[0to8]' -.measure tran total_dynamic_power_lut6 -+ param = 'dynamic_power_lut6[0to9]' -.measure tran total_energy_per_cycle_lut6 -+ param = 'dynamic_power_lut6[0to9]*clock_period' -.end diff --git a/examples/spice_test_example_2/pb_mux_tb/example_2_grid1_1_pbmux_testbench.sp b/examples/spice_test_example_2/pb_mux_tb/example_2_grid1_1_pbmux_testbench.sp deleted file mode 100644 index e2f699b48..000000000 --- a/examples/spice_test_example_2/pb_mux_tb/example_2_grid1_1_pbmux_testbench.sp +++ /dev/null @@ -1,16912 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_2level_size50[0] mux_2level_size50[0]->in[0] mux_2level_size50[0]->in[1] mux_2level_size50[0]->in[2] mux_2level_size50[0]->in[3] mux_2level_size50[0]->in[4] mux_2level_size50[0]->in[5] mux_2level_size50[0]->in[6] mux_2level_size50[0]->in[7] mux_2level_size50[0]->in[8] mux_2level_size50[0]->in[9] mux_2level_size50[0]->in[10] mux_2level_size50[0]->in[11] mux_2level_size50[0]->in[12] mux_2level_size50[0]->in[13] mux_2level_size50[0]->in[14] mux_2level_size50[0]->in[15] mux_2level_size50[0]->in[16] mux_2level_size50[0]->in[17] mux_2level_size50[0]->in[18] mux_2level_size50[0]->in[19] mux_2level_size50[0]->in[20] mux_2level_size50[0]->in[21] mux_2level_size50[0]->in[22] mux_2level_size50[0]->in[23] mux_2level_size50[0]->in[24] mux_2level_size50[0]->in[25] mux_2level_size50[0]->in[26] mux_2level_size50[0]->in[27] mux_2level_size50[0]->in[28] mux_2level_size50[0]->in[29] mux_2level_size50[0]->in[30] mux_2level_size50[0]->in[31] mux_2level_size50[0]->in[32] mux_2level_size50[0]->in[33] mux_2level_size50[0]->in[34] mux_2level_size50[0]->in[35] mux_2level_size50[0]->in[36] mux_2level_size50[0]->in[37] mux_2level_size50[0]->in[38] mux_2level_size50[0]->in[39] mux_2level_size50[0]->in[40] mux_2level_size50[0]->in[41] mux_2level_size50[0]->in[42] mux_2level_size50[0]->in[43] mux_2level_size50[0]->in[44] mux_2level_size50[0]->in[45] mux_2level_size50[0]->in[46] mux_2level_size50[0]->in[47] mux_2level_size50[0]->in[48] mux_2level_size50[0]->in[49] mux_2level_size50[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb sram[3]->out sram[3]->outb sram[4]->out sram[4]->outb sram[5]->out sram[5]->outb sram[6]->out sram[6]->outb sram[7]->out sram[7]->outb sram[8]->outb sram[8]->out sram[9]->out sram[9]->outb sram[10]->out sram[10]->outb sram[11]->out sram[11]->outb sram[12]->out sram[12]->outb sram[13]->out sram[13]->outb sram[14]->out sram[14]->outb sram[15]->out sram[15]->outb gvdd_mux_2level_size50[0] 0 mux_2level_size50 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_2level_size50[0]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[0] mux_2level_size50[0]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[1] mux_2level_size50[0]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[2] mux_2level_size50[0]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[3] mux_2level_size50[0]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[4] mux_2level_size50[0]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[5] mux_2level_size50[0]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[6] mux_2level_size50[0]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[7] mux_2level_size50[0]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[8] mux_2level_size50[0]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[9] mux_2level_size50[0]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[10] mux_2level_size50[0]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[11] mux_2level_size50[0]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[12] mux_2level_size50[0]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[13] mux_2level_size50[0]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[14] mux_2level_size50[0]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[15] mux_2level_size50[0]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[16] mux_2level_size50[0]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[17] mux_2level_size50[0]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[18] mux_2level_size50[0]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[19] mux_2level_size50[0]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[20] mux_2level_size50[0]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[21] mux_2level_size50[0]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[22] mux_2level_size50[0]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[23] mux_2level_size50[0]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[24] mux_2level_size50[0]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[25] mux_2level_size50[0]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[26] mux_2level_size50[0]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[27] mux_2level_size50[0]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[28] mux_2level_size50[0]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[29] mux_2level_size50[0]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[30] mux_2level_size50[0]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[31] mux_2level_size50[0]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[32] mux_2level_size50[0]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[33] mux_2level_size50[0]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[34] mux_2level_size50[0]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[35] mux_2level_size50[0]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[36] mux_2level_size50[0]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[37] mux_2level_size50[0]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[38] mux_2level_size50[0]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[0]->in[39] mux_2level_size50[0]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[0]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[40] mux_2level_size50[0]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[41] mux_2level_size50[0]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[42] mux_2level_size50[0]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[43] mux_2level_size50[0]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[44] mux_2level_size50[0]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[45] mux_2level_size50[0]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[46] mux_2level_size50[0]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[47] mux_2level_size50[0]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[48] mux_2level_size50[0]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[0]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[0]->in[49] mux_2level_size50[0]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[0] gvdd_mux_2level_size50[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[0]_in[0]_crossbar trig v(mux_2level_size50[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[0]_in[0]_crossbar trig v(mux_2level_size50[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[0]_in[0]_crossbar when v(mux_2level_size50[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[0]_in[0]_crossbar trig v(mux_2level_size50[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[0]_in[0]_crossbar when v(mux_2level_size50[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[0]_in[0]_crossbar trig v(mux_2level_size50[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[0]_leakage_power avg p(Vgvdd_mux_2level_size50[0]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[0]_in[0]_crossbar param='mux_2level_size50[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[0]_dynamic_power avg p(Vgvdd_mux_2level_size50[0]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[0]_energy_per_cycle param='mux_2level_size50[0]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[0]_in[0]_crossbar param='mux_2level_size50[0]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[0]_in[0]_crossbar param='dynamic_power_idle_mux50[0]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[0]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[0]) from='start_rise_idle_mux50[0]_in[0]_crossbar' to='start_rise_idle_mux50[0]_in[0]_crossbar+switch_rise_idle_mux50[0]_in[0]_crossbar' -.meas tran dynamic_fall_idle_mux50[0]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[0]) from='start_fall_idle_mux50[0]_in[0]_crossbar' to='start_fall_idle_mux50[0]_in[0]_crossbar+switch_fall_idle_mux50[0]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_idle_mux50[0]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_idle_mux50[0]_in[0]_crossbar' -Xload_inv[0]_no0 mux_2level_size50[0]->out mux_2level_size50[0]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to0] -+ param='leakage_idle_mux50[0]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to0] -+ param='energy_per_cycle_idle_mux50[0]_in[0]_crossbar' -Xmux_2level_size50[1] mux_2level_size50[1]->in[0] mux_2level_size50[1]->in[1] mux_2level_size50[1]->in[2] mux_2level_size50[1]->in[3] mux_2level_size50[1]->in[4] mux_2level_size50[1]->in[5] mux_2level_size50[1]->in[6] mux_2level_size50[1]->in[7] mux_2level_size50[1]->in[8] mux_2level_size50[1]->in[9] mux_2level_size50[1]->in[10] mux_2level_size50[1]->in[11] mux_2level_size50[1]->in[12] mux_2level_size50[1]->in[13] mux_2level_size50[1]->in[14] mux_2level_size50[1]->in[15] mux_2level_size50[1]->in[16] mux_2level_size50[1]->in[17] mux_2level_size50[1]->in[18] mux_2level_size50[1]->in[19] mux_2level_size50[1]->in[20] mux_2level_size50[1]->in[21] mux_2level_size50[1]->in[22] mux_2level_size50[1]->in[23] mux_2level_size50[1]->in[24] mux_2level_size50[1]->in[25] mux_2level_size50[1]->in[26] mux_2level_size50[1]->in[27] mux_2level_size50[1]->in[28] mux_2level_size50[1]->in[29] mux_2level_size50[1]->in[30] mux_2level_size50[1]->in[31] mux_2level_size50[1]->in[32] mux_2level_size50[1]->in[33] mux_2level_size50[1]->in[34] mux_2level_size50[1]->in[35] mux_2level_size50[1]->in[36] mux_2level_size50[1]->in[37] mux_2level_size50[1]->in[38] mux_2level_size50[1]->in[39] mux_2level_size50[1]->in[40] mux_2level_size50[1]->in[41] mux_2level_size50[1]->in[42] mux_2level_size50[1]->in[43] mux_2level_size50[1]->in[44] mux_2level_size50[1]->in[45] mux_2level_size50[1]->in[46] mux_2level_size50[1]->in[47] mux_2level_size50[1]->in[48] mux_2level_size50[1]->in[49] mux_2level_size50[1]->out sram[16]->outb sram[16]->out sram[17]->out sram[17]->outb sram[18]->out sram[18]->outb sram[19]->out sram[19]->outb sram[20]->out sram[20]->outb sram[21]->out sram[21]->outb sram[22]->out sram[22]->outb sram[23]->out sram[23]->outb sram[24]->outb sram[24]->out sram[25]->out sram[25]->outb sram[26]->out sram[26]->outb sram[27]->out sram[27]->outb sram[28]->out sram[28]->outb sram[29]->out sram[29]->outb sram[30]->out sram[30]->outb sram[31]->out sram[31]->outb gvdd_mux_2level_size50[1] 0 mux_2level_size50 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_2level_size50[1]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[0] mux_2level_size50[1]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[1] mux_2level_size50[1]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[2] mux_2level_size50[1]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[3] mux_2level_size50[1]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[4] mux_2level_size50[1]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[5] mux_2level_size50[1]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[6] mux_2level_size50[1]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[7] mux_2level_size50[1]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[8] mux_2level_size50[1]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[9] mux_2level_size50[1]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[10] mux_2level_size50[1]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[11] mux_2level_size50[1]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[12] mux_2level_size50[1]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[13] mux_2level_size50[1]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[14] mux_2level_size50[1]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[15] mux_2level_size50[1]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[16] mux_2level_size50[1]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[17] mux_2level_size50[1]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[18] mux_2level_size50[1]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[19] mux_2level_size50[1]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[20] mux_2level_size50[1]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[21] mux_2level_size50[1]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[22] mux_2level_size50[1]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[23] mux_2level_size50[1]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[24] mux_2level_size50[1]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[25] mux_2level_size50[1]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[26] mux_2level_size50[1]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[27] mux_2level_size50[1]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[28] mux_2level_size50[1]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[29] mux_2level_size50[1]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[30] mux_2level_size50[1]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[31] mux_2level_size50[1]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[32] mux_2level_size50[1]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[33] mux_2level_size50[1]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[34] mux_2level_size50[1]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[35] mux_2level_size50[1]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[36] mux_2level_size50[1]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[37] mux_2level_size50[1]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[38] mux_2level_size50[1]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[1]->in[39] mux_2level_size50[1]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[1]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[40] mux_2level_size50[1]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[41] mux_2level_size50[1]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[42] mux_2level_size50[1]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[43] mux_2level_size50[1]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[44] mux_2level_size50[1]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[45] mux_2level_size50[1]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[46] mux_2level_size50[1]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[47] mux_2level_size50[1]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[48] mux_2level_size50[1]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[1]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[1]->in[49] mux_2level_size50[1]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[1] gvdd_mux_2level_size50[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[1]_in[1]_crossbar trig v(mux_2level_size50[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[1]_in[1]_crossbar trig v(mux_2level_size50[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[1]_in[1]_crossbar when v(mux_2level_size50[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[1]_in[1]_crossbar trig v(mux_2level_size50[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[1]_in[1]_crossbar when v(mux_2level_size50[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[1]_in[1]_crossbar trig v(mux_2level_size50[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[1]_leakage_power avg p(Vgvdd_mux_2level_size50[1]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[1]_in[1]_crossbar param='mux_2level_size50[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[1]_dynamic_power avg p(Vgvdd_mux_2level_size50[1]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[1]_energy_per_cycle param='mux_2level_size50[1]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[1]_in[1]_crossbar param='mux_2level_size50[1]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[1]_in[1]_crossbar param='dynamic_power_idle_mux50[1]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[1]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[1]) from='start_rise_idle_mux50[1]_in[1]_crossbar' to='start_rise_idle_mux50[1]_in[1]_crossbar+switch_rise_idle_mux50[1]_in[1]_crossbar' -.meas tran dynamic_fall_idle_mux50[1]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[1]) from='start_fall_idle_mux50[1]_in[1]_crossbar' to='start_fall_idle_mux50[1]_in[1]_crossbar+switch_fall_idle_mux50[1]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_idle_mux50[1]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_idle_mux50[1]_in[1]_crossbar' -Xload_inv[1]_no0 mux_2level_size50[1]->out mux_2level_size50[1]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to1] -+ param='sum_leakage_power_pb_mux[0to0]+leakage_idle_mux50[1]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to1] -+ param='sum_energy_per_cycle_pb_mux[0to0]+energy_per_cycle_idle_mux50[1]_in[1]_crossbar' -Xmux_2level_size50[2] mux_2level_size50[2]->in[0] mux_2level_size50[2]->in[1] mux_2level_size50[2]->in[2] mux_2level_size50[2]->in[3] mux_2level_size50[2]->in[4] mux_2level_size50[2]->in[5] mux_2level_size50[2]->in[6] mux_2level_size50[2]->in[7] mux_2level_size50[2]->in[8] mux_2level_size50[2]->in[9] mux_2level_size50[2]->in[10] mux_2level_size50[2]->in[11] mux_2level_size50[2]->in[12] mux_2level_size50[2]->in[13] mux_2level_size50[2]->in[14] mux_2level_size50[2]->in[15] mux_2level_size50[2]->in[16] mux_2level_size50[2]->in[17] mux_2level_size50[2]->in[18] mux_2level_size50[2]->in[19] mux_2level_size50[2]->in[20] mux_2level_size50[2]->in[21] mux_2level_size50[2]->in[22] mux_2level_size50[2]->in[23] mux_2level_size50[2]->in[24] mux_2level_size50[2]->in[25] mux_2level_size50[2]->in[26] mux_2level_size50[2]->in[27] mux_2level_size50[2]->in[28] mux_2level_size50[2]->in[29] mux_2level_size50[2]->in[30] mux_2level_size50[2]->in[31] mux_2level_size50[2]->in[32] mux_2level_size50[2]->in[33] mux_2level_size50[2]->in[34] mux_2level_size50[2]->in[35] mux_2level_size50[2]->in[36] mux_2level_size50[2]->in[37] mux_2level_size50[2]->in[38] mux_2level_size50[2]->in[39] mux_2level_size50[2]->in[40] mux_2level_size50[2]->in[41] mux_2level_size50[2]->in[42] mux_2level_size50[2]->in[43] mux_2level_size50[2]->in[44] mux_2level_size50[2]->in[45] mux_2level_size50[2]->in[46] mux_2level_size50[2]->in[47] mux_2level_size50[2]->in[48] mux_2level_size50[2]->in[49] mux_2level_size50[2]->out sram[32]->outb sram[32]->out sram[33]->out sram[33]->outb sram[34]->out sram[34]->outb sram[35]->out sram[35]->outb sram[36]->out sram[36]->outb sram[37]->out sram[37]->outb sram[38]->out sram[38]->outb sram[39]->out sram[39]->outb sram[40]->outb sram[40]->out sram[41]->out sram[41]->outb sram[42]->out sram[42]->outb sram[43]->out sram[43]->outb sram[44]->out sram[44]->outb sram[45]->out sram[45]->outb sram[46]->out sram[46]->outb sram[47]->out sram[47]->outb gvdd_mux_2level_size50[2] 0 mux_2level_size50 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -***** Signal mux_2level_size50[2]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[0] mux_2level_size50[2]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[1] mux_2level_size50[2]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[2] mux_2level_size50[2]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[3] mux_2level_size50[2]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[4] mux_2level_size50[2]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[5] mux_2level_size50[2]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[6] mux_2level_size50[2]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[7] mux_2level_size50[2]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[8] mux_2level_size50[2]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[9] mux_2level_size50[2]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[10] mux_2level_size50[2]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[11] mux_2level_size50[2]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[12] mux_2level_size50[2]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[13] mux_2level_size50[2]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[14] mux_2level_size50[2]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[15] mux_2level_size50[2]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[16] mux_2level_size50[2]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[17] mux_2level_size50[2]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[18] mux_2level_size50[2]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[19] mux_2level_size50[2]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[20] mux_2level_size50[2]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[21] mux_2level_size50[2]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[22] mux_2level_size50[2]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[23] mux_2level_size50[2]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[24] mux_2level_size50[2]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[25] mux_2level_size50[2]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[26] mux_2level_size50[2]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[27] mux_2level_size50[2]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[28] mux_2level_size50[2]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[29] mux_2level_size50[2]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[30] mux_2level_size50[2]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[31] mux_2level_size50[2]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[32] mux_2level_size50[2]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[33] mux_2level_size50[2]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[34] mux_2level_size50[2]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[35] mux_2level_size50[2]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[36] mux_2level_size50[2]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[37] mux_2level_size50[2]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[38] mux_2level_size50[2]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[2]->in[39] mux_2level_size50[2]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[2]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[40] mux_2level_size50[2]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[41] mux_2level_size50[2]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[42] mux_2level_size50[2]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[43] mux_2level_size50[2]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[44] mux_2level_size50[2]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[45] mux_2level_size50[2]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[46] mux_2level_size50[2]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[47] mux_2level_size50[2]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[48] mux_2level_size50[2]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[2]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[2]->in[49] mux_2level_size50[2]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[2] gvdd_mux_2level_size50[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[2]_in[2]_crossbar trig v(mux_2level_size50[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[2]_in[2]_crossbar trig v(mux_2level_size50[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[2]_in[2]_crossbar when v(mux_2level_size50[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[2]_in[2]_crossbar trig v(mux_2level_size50[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[2]_in[2]_crossbar when v(mux_2level_size50[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[2]_in[2]_crossbar trig v(mux_2level_size50[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[2]_leakage_power avg p(Vgvdd_mux_2level_size50[2]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[2]_in[2]_crossbar param='mux_2level_size50[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[2]_dynamic_power avg p(Vgvdd_mux_2level_size50[2]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[2]_energy_per_cycle param='mux_2level_size50[2]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[2]_in[2]_crossbar param='mux_2level_size50[2]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[2]_in[2]_crossbar param='dynamic_power_idle_mux50[2]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[2]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[2]) from='start_rise_idle_mux50[2]_in[2]_crossbar' to='start_rise_idle_mux50[2]_in[2]_crossbar+switch_rise_idle_mux50[2]_in[2]_crossbar' -.meas tran dynamic_fall_idle_mux50[2]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[2]) from='start_fall_idle_mux50[2]_in[2]_crossbar' to='start_fall_idle_mux50[2]_in[2]_crossbar+switch_fall_idle_mux50[2]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_idle_mux50[2]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_idle_mux50[2]_in[2]_crossbar' -Xload_inv[2]_no0 mux_2level_size50[2]->out mux_2level_size50[2]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to2] -+ param='sum_leakage_power_pb_mux[0to1]+leakage_idle_mux50[2]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to2] -+ param='sum_energy_per_cycle_pb_mux[0to1]+energy_per_cycle_idle_mux50[2]_in[2]_crossbar' -Xmux_2level_size50[3] mux_2level_size50[3]->in[0] mux_2level_size50[3]->in[1] mux_2level_size50[3]->in[2] mux_2level_size50[3]->in[3] mux_2level_size50[3]->in[4] mux_2level_size50[3]->in[5] mux_2level_size50[3]->in[6] mux_2level_size50[3]->in[7] mux_2level_size50[3]->in[8] mux_2level_size50[3]->in[9] mux_2level_size50[3]->in[10] mux_2level_size50[3]->in[11] mux_2level_size50[3]->in[12] mux_2level_size50[3]->in[13] mux_2level_size50[3]->in[14] mux_2level_size50[3]->in[15] mux_2level_size50[3]->in[16] mux_2level_size50[3]->in[17] mux_2level_size50[3]->in[18] mux_2level_size50[3]->in[19] mux_2level_size50[3]->in[20] mux_2level_size50[3]->in[21] mux_2level_size50[3]->in[22] mux_2level_size50[3]->in[23] mux_2level_size50[3]->in[24] mux_2level_size50[3]->in[25] mux_2level_size50[3]->in[26] mux_2level_size50[3]->in[27] mux_2level_size50[3]->in[28] mux_2level_size50[3]->in[29] mux_2level_size50[3]->in[30] mux_2level_size50[3]->in[31] mux_2level_size50[3]->in[32] mux_2level_size50[3]->in[33] mux_2level_size50[3]->in[34] mux_2level_size50[3]->in[35] mux_2level_size50[3]->in[36] mux_2level_size50[3]->in[37] mux_2level_size50[3]->in[38] mux_2level_size50[3]->in[39] mux_2level_size50[3]->in[40] mux_2level_size50[3]->in[41] mux_2level_size50[3]->in[42] mux_2level_size50[3]->in[43] mux_2level_size50[3]->in[44] mux_2level_size50[3]->in[45] mux_2level_size50[3]->in[46] mux_2level_size50[3]->in[47] mux_2level_size50[3]->in[48] mux_2level_size50[3]->in[49] mux_2level_size50[3]->out sram[48]->outb sram[48]->out sram[49]->out sram[49]->outb sram[50]->out sram[50]->outb sram[51]->out sram[51]->outb sram[52]->out sram[52]->outb sram[53]->out sram[53]->outb sram[54]->out sram[54]->outb sram[55]->out sram[55]->outb sram[56]->outb sram[56]->out sram[57]->out sram[57]->outb sram[58]->out sram[58]->outb sram[59]->out sram[59]->outb sram[60]->out sram[60]->outb sram[61]->out sram[61]->outb sram[62]->out sram[62]->outb sram[63]->out sram[63]->outb gvdd_mux_2level_size50[3] 0 mux_2level_size50 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -***** Signal mux_2level_size50[3]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[0] mux_2level_size50[3]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[1] mux_2level_size50[3]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[2] mux_2level_size50[3]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[3] mux_2level_size50[3]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[4] mux_2level_size50[3]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[5] mux_2level_size50[3]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[6] mux_2level_size50[3]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[7] mux_2level_size50[3]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[8] mux_2level_size50[3]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[9] mux_2level_size50[3]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[10] mux_2level_size50[3]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[11] mux_2level_size50[3]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[12] mux_2level_size50[3]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[13] mux_2level_size50[3]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[14] mux_2level_size50[3]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[15] mux_2level_size50[3]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[16] mux_2level_size50[3]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[17] mux_2level_size50[3]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[18] mux_2level_size50[3]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[19] mux_2level_size50[3]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[20] mux_2level_size50[3]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[21] mux_2level_size50[3]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[22] mux_2level_size50[3]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[23] mux_2level_size50[3]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[24] mux_2level_size50[3]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[25] mux_2level_size50[3]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[26] mux_2level_size50[3]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[27] mux_2level_size50[3]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[28] mux_2level_size50[3]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[29] mux_2level_size50[3]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[30] mux_2level_size50[3]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[31] mux_2level_size50[3]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[32] mux_2level_size50[3]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[33] mux_2level_size50[3]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[34] mux_2level_size50[3]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[35] mux_2level_size50[3]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[36] mux_2level_size50[3]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[37] mux_2level_size50[3]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[38] mux_2level_size50[3]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[3]->in[39] mux_2level_size50[3]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[3]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[40] mux_2level_size50[3]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[41] mux_2level_size50[3]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[42] mux_2level_size50[3]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[43] mux_2level_size50[3]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[44] mux_2level_size50[3]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[45] mux_2level_size50[3]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[46] mux_2level_size50[3]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[47] mux_2level_size50[3]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[48] mux_2level_size50[3]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[3]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[3]->in[49] mux_2level_size50[3]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[3] gvdd_mux_2level_size50[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[3]_in[3]_crossbar trig v(mux_2level_size50[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[3]_in[3]_crossbar trig v(mux_2level_size50[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[3]_in[3]_crossbar when v(mux_2level_size50[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[3]_in[3]_crossbar trig v(mux_2level_size50[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[3]_in[3]_crossbar when v(mux_2level_size50[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[3]_in[3]_crossbar trig v(mux_2level_size50[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[3]_leakage_power avg p(Vgvdd_mux_2level_size50[3]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[3]_in[3]_crossbar param='mux_2level_size50[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[3]_dynamic_power avg p(Vgvdd_mux_2level_size50[3]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[3]_energy_per_cycle param='mux_2level_size50[3]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[3]_in[3]_crossbar param='mux_2level_size50[3]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[3]_in[3]_crossbar param='dynamic_power_idle_mux50[3]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[3]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[3]) from='start_rise_idle_mux50[3]_in[3]_crossbar' to='start_rise_idle_mux50[3]_in[3]_crossbar+switch_rise_idle_mux50[3]_in[3]_crossbar' -.meas tran dynamic_fall_idle_mux50[3]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[3]) from='start_fall_idle_mux50[3]_in[3]_crossbar' to='start_fall_idle_mux50[3]_in[3]_crossbar+switch_fall_idle_mux50[3]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_idle_mux50[3]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_idle_mux50[3]_in[3]_crossbar' -Xload_inv[3]_no0 mux_2level_size50[3]->out mux_2level_size50[3]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to3] -+ param='sum_leakage_power_pb_mux[0to2]+leakage_idle_mux50[3]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to3] -+ param='sum_energy_per_cycle_pb_mux[0to2]+energy_per_cycle_idle_mux50[3]_in[3]_crossbar' -Xmux_2level_size50[4] mux_2level_size50[4]->in[0] mux_2level_size50[4]->in[1] mux_2level_size50[4]->in[2] mux_2level_size50[4]->in[3] mux_2level_size50[4]->in[4] mux_2level_size50[4]->in[5] mux_2level_size50[4]->in[6] mux_2level_size50[4]->in[7] mux_2level_size50[4]->in[8] mux_2level_size50[4]->in[9] mux_2level_size50[4]->in[10] mux_2level_size50[4]->in[11] mux_2level_size50[4]->in[12] mux_2level_size50[4]->in[13] mux_2level_size50[4]->in[14] mux_2level_size50[4]->in[15] mux_2level_size50[4]->in[16] mux_2level_size50[4]->in[17] mux_2level_size50[4]->in[18] mux_2level_size50[4]->in[19] mux_2level_size50[4]->in[20] mux_2level_size50[4]->in[21] mux_2level_size50[4]->in[22] mux_2level_size50[4]->in[23] mux_2level_size50[4]->in[24] mux_2level_size50[4]->in[25] mux_2level_size50[4]->in[26] mux_2level_size50[4]->in[27] mux_2level_size50[4]->in[28] mux_2level_size50[4]->in[29] mux_2level_size50[4]->in[30] mux_2level_size50[4]->in[31] mux_2level_size50[4]->in[32] mux_2level_size50[4]->in[33] mux_2level_size50[4]->in[34] mux_2level_size50[4]->in[35] mux_2level_size50[4]->in[36] mux_2level_size50[4]->in[37] mux_2level_size50[4]->in[38] mux_2level_size50[4]->in[39] mux_2level_size50[4]->in[40] mux_2level_size50[4]->in[41] mux_2level_size50[4]->in[42] mux_2level_size50[4]->in[43] mux_2level_size50[4]->in[44] mux_2level_size50[4]->in[45] mux_2level_size50[4]->in[46] mux_2level_size50[4]->in[47] mux_2level_size50[4]->in[48] mux_2level_size50[4]->in[49] mux_2level_size50[4]->out sram[64]->outb sram[64]->out sram[65]->out sram[65]->outb sram[66]->out sram[66]->outb sram[67]->out sram[67]->outb sram[68]->out sram[68]->outb sram[69]->out sram[69]->outb sram[70]->out sram[70]->outb sram[71]->out sram[71]->outb sram[72]->outb sram[72]->out sram[73]->out sram[73]->outb sram[74]->out sram[74]->outb sram[75]->out sram[75]->outb sram[76]->out sram[76]->outb sram[77]->out sram[77]->outb sram[78]->out sram[78]->outb sram[79]->out sram[79]->outb gvdd_mux_2level_size50[4] 0 mux_2level_size50 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -***** Signal mux_2level_size50[4]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[0] mux_2level_size50[4]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[1] mux_2level_size50[4]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[2] mux_2level_size50[4]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[3] mux_2level_size50[4]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[4] mux_2level_size50[4]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[5] mux_2level_size50[4]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[6] mux_2level_size50[4]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[7] mux_2level_size50[4]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[8] mux_2level_size50[4]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[9] mux_2level_size50[4]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[10] mux_2level_size50[4]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[11] mux_2level_size50[4]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[12] mux_2level_size50[4]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[13] mux_2level_size50[4]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[14] mux_2level_size50[4]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[15] mux_2level_size50[4]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[16] mux_2level_size50[4]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[17] mux_2level_size50[4]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[18] mux_2level_size50[4]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[19] mux_2level_size50[4]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[20] mux_2level_size50[4]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[21] mux_2level_size50[4]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[22] mux_2level_size50[4]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[23] mux_2level_size50[4]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[24] mux_2level_size50[4]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[25] mux_2level_size50[4]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[26] mux_2level_size50[4]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[27] mux_2level_size50[4]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[28] mux_2level_size50[4]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[29] mux_2level_size50[4]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[30] mux_2level_size50[4]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[31] mux_2level_size50[4]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[32] mux_2level_size50[4]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[33] mux_2level_size50[4]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[34] mux_2level_size50[4]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[35] mux_2level_size50[4]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[36] mux_2level_size50[4]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[37] mux_2level_size50[4]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[38] mux_2level_size50[4]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[4]->in[39] mux_2level_size50[4]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[4]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[40] mux_2level_size50[4]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[41] mux_2level_size50[4]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[42] mux_2level_size50[4]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[43] mux_2level_size50[4]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[44] mux_2level_size50[4]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[45] mux_2level_size50[4]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[46] mux_2level_size50[4]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[47] mux_2level_size50[4]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[48] mux_2level_size50[4]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[4]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[4]->in[49] mux_2level_size50[4]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[4] gvdd_mux_2level_size50[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[4]_in[4]_crossbar trig v(mux_2level_size50[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[4]_in[4]_crossbar trig v(mux_2level_size50[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[4]_in[4]_crossbar when v(mux_2level_size50[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[4]_in[4]_crossbar trig v(mux_2level_size50[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[4]_in[4]_crossbar when v(mux_2level_size50[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[4]_in[4]_crossbar trig v(mux_2level_size50[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[4]_leakage_power avg p(Vgvdd_mux_2level_size50[4]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[4]_in[4]_crossbar param='mux_2level_size50[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[4]_dynamic_power avg p(Vgvdd_mux_2level_size50[4]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[4]_energy_per_cycle param='mux_2level_size50[4]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[4]_in[4]_crossbar param='mux_2level_size50[4]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[4]_in[4]_crossbar param='dynamic_power_idle_mux50[4]_in[4]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[4]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[4]) from='start_rise_idle_mux50[4]_in[4]_crossbar' to='start_rise_idle_mux50[4]_in[4]_crossbar+switch_rise_idle_mux50[4]_in[4]_crossbar' -.meas tran dynamic_fall_idle_mux50[4]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[4]) from='start_fall_idle_mux50[4]_in[4]_crossbar' to='start_fall_idle_mux50[4]_in[4]_crossbar+switch_fall_idle_mux50[4]_in[4]_crossbar' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_idle_mux50[4]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_idle_mux50[4]_in[4]_crossbar' -Xload_inv[4]_no0 mux_2level_size50[4]->out mux_2level_size50[4]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to4] -+ param='sum_leakage_power_pb_mux[0to3]+leakage_idle_mux50[4]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to4] -+ param='sum_energy_per_cycle_pb_mux[0to3]+energy_per_cycle_idle_mux50[4]_in[4]_crossbar' -Xmux_2level_size50[5] mux_2level_size50[5]->in[0] mux_2level_size50[5]->in[1] mux_2level_size50[5]->in[2] mux_2level_size50[5]->in[3] mux_2level_size50[5]->in[4] mux_2level_size50[5]->in[5] mux_2level_size50[5]->in[6] mux_2level_size50[5]->in[7] mux_2level_size50[5]->in[8] mux_2level_size50[5]->in[9] mux_2level_size50[5]->in[10] mux_2level_size50[5]->in[11] mux_2level_size50[5]->in[12] mux_2level_size50[5]->in[13] mux_2level_size50[5]->in[14] mux_2level_size50[5]->in[15] mux_2level_size50[5]->in[16] mux_2level_size50[5]->in[17] mux_2level_size50[5]->in[18] mux_2level_size50[5]->in[19] mux_2level_size50[5]->in[20] mux_2level_size50[5]->in[21] mux_2level_size50[5]->in[22] mux_2level_size50[5]->in[23] mux_2level_size50[5]->in[24] mux_2level_size50[5]->in[25] mux_2level_size50[5]->in[26] mux_2level_size50[5]->in[27] mux_2level_size50[5]->in[28] mux_2level_size50[5]->in[29] mux_2level_size50[5]->in[30] mux_2level_size50[5]->in[31] mux_2level_size50[5]->in[32] mux_2level_size50[5]->in[33] mux_2level_size50[5]->in[34] mux_2level_size50[5]->in[35] mux_2level_size50[5]->in[36] mux_2level_size50[5]->in[37] mux_2level_size50[5]->in[38] mux_2level_size50[5]->in[39] mux_2level_size50[5]->in[40] mux_2level_size50[5]->in[41] mux_2level_size50[5]->in[42] mux_2level_size50[5]->in[43] mux_2level_size50[5]->in[44] mux_2level_size50[5]->in[45] mux_2level_size50[5]->in[46] mux_2level_size50[5]->in[47] mux_2level_size50[5]->in[48] mux_2level_size50[5]->in[49] mux_2level_size50[5]->out sram[80]->outb sram[80]->out sram[81]->out sram[81]->outb sram[82]->out sram[82]->outb sram[83]->out sram[83]->outb sram[84]->out sram[84]->outb sram[85]->out sram[85]->outb sram[86]->out sram[86]->outb sram[87]->out sram[87]->outb sram[88]->outb sram[88]->out sram[89]->out sram[89]->outb sram[90]->out sram[90]->outb sram[91]->out sram[91]->outb sram[92]->out sram[92]->outb sram[93]->out sram[93]->outb sram[94]->out sram[94]->outb sram[95]->out sram[95]->outb gvdd_mux_2level_size50[5] 0 mux_2level_size50 -***** SRAM bits for MUX[5], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -***** Signal mux_2level_size50[5]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[0] mux_2level_size50[5]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[1] mux_2level_size50[5]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[2] mux_2level_size50[5]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[3] mux_2level_size50[5]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[4] mux_2level_size50[5]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[5] mux_2level_size50[5]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[6] mux_2level_size50[5]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[7] mux_2level_size50[5]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[8] mux_2level_size50[5]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[9] mux_2level_size50[5]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[10] mux_2level_size50[5]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[11] mux_2level_size50[5]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[12] mux_2level_size50[5]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[13] mux_2level_size50[5]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[14] mux_2level_size50[5]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[15] mux_2level_size50[5]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[16] mux_2level_size50[5]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[17] mux_2level_size50[5]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[18] mux_2level_size50[5]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[19] mux_2level_size50[5]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[20] mux_2level_size50[5]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[21] mux_2level_size50[5]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[22] mux_2level_size50[5]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[23] mux_2level_size50[5]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[24] mux_2level_size50[5]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[25] mux_2level_size50[5]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[26] mux_2level_size50[5]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[27] mux_2level_size50[5]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[28] mux_2level_size50[5]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[29] mux_2level_size50[5]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[30] mux_2level_size50[5]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[31] mux_2level_size50[5]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[32] mux_2level_size50[5]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[33] mux_2level_size50[5]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[34] mux_2level_size50[5]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[35] mux_2level_size50[5]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[36] mux_2level_size50[5]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[37] mux_2level_size50[5]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[38] mux_2level_size50[5]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[5]->in[39] mux_2level_size50[5]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[5]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[40] mux_2level_size50[5]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[41] mux_2level_size50[5]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[42] mux_2level_size50[5]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[43] mux_2level_size50[5]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[44] mux_2level_size50[5]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[45] mux_2level_size50[5]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[46] mux_2level_size50[5]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[47] mux_2level_size50[5]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[48] mux_2level_size50[5]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[5]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[5]->in[49] mux_2level_size50[5]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[5] gvdd_mux_2level_size50[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[5]_in[5]_crossbar trig v(mux_2level_size50[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[5]_in[5]_crossbar trig v(mux_2level_size50[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[5]_in[5]_crossbar when v(mux_2level_size50[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[5]_in[5]_crossbar trig v(mux_2level_size50[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[5]_in[5]_crossbar when v(mux_2level_size50[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[5]_in[5]_crossbar trig v(mux_2level_size50[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[5]_leakage_power avg p(Vgvdd_mux_2level_size50[5]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[5]_in[5]_crossbar param='mux_2level_size50[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[5]_dynamic_power avg p(Vgvdd_mux_2level_size50[5]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[5]_energy_per_cycle param='mux_2level_size50[5]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[5]_in[5]_crossbar param='mux_2level_size50[5]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[5]_in[5]_crossbar param='dynamic_power_idle_mux50[5]_in[5]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[5]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[5]) from='start_rise_idle_mux50[5]_in[5]_crossbar' to='start_rise_idle_mux50[5]_in[5]_crossbar+switch_rise_idle_mux50[5]_in[5]_crossbar' -.meas tran dynamic_fall_idle_mux50[5]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[5]) from='start_fall_idle_mux50[5]_in[5]_crossbar' to='start_fall_idle_mux50[5]_in[5]_crossbar+switch_fall_idle_mux50[5]_in[5]_crossbar' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_idle_mux50[5]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_idle_mux50[5]_in[5]_crossbar' -Xload_inv[5]_no0 mux_2level_size50[5]->out mux_2level_size50[5]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to5] -+ param='sum_leakage_power_pb_mux[0to4]+leakage_idle_mux50[5]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to5] -+ param='sum_energy_per_cycle_pb_mux[0to4]+energy_per_cycle_idle_mux50[5]_in[5]_crossbar' -Xmux_2level_size50[6] mux_2level_size50[6]->in[0] mux_2level_size50[6]->in[1] mux_2level_size50[6]->in[2] mux_2level_size50[6]->in[3] mux_2level_size50[6]->in[4] mux_2level_size50[6]->in[5] mux_2level_size50[6]->in[6] mux_2level_size50[6]->in[7] mux_2level_size50[6]->in[8] mux_2level_size50[6]->in[9] mux_2level_size50[6]->in[10] mux_2level_size50[6]->in[11] mux_2level_size50[6]->in[12] mux_2level_size50[6]->in[13] mux_2level_size50[6]->in[14] mux_2level_size50[6]->in[15] mux_2level_size50[6]->in[16] mux_2level_size50[6]->in[17] mux_2level_size50[6]->in[18] mux_2level_size50[6]->in[19] mux_2level_size50[6]->in[20] mux_2level_size50[6]->in[21] mux_2level_size50[6]->in[22] mux_2level_size50[6]->in[23] mux_2level_size50[6]->in[24] mux_2level_size50[6]->in[25] mux_2level_size50[6]->in[26] mux_2level_size50[6]->in[27] mux_2level_size50[6]->in[28] mux_2level_size50[6]->in[29] mux_2level_size50[6]->in[30] mux_2level_size50[6]->in[31] mux_2level_size50[6]->in[32] mux_2level_size50[6]->in[33] mux_2level_size50[6]->in[34] mux_2level_size50[6]->in[35] mux_2level_size50[6]->in[36] mux_2level_size50[6]->in[37] mux_2level_size50[6]->in[38] mux_2level_size50[6]->in[39] mux_2level_size50[6]->in[40] mux_2level_size50[6]->in[41] mux_2level_size50[6]->in[42] mux_2level_size50[6]->in[43] mux_2level_size50[6]->in[44] mux_2level_size50[6]->in[45] mux_2level_size50[6]->in[46] mux_2level_size50[6]->in[47] mux_2level_size50[6]->in[48] mux_2level_size50[6]->in[49] mux_2level_size50[6]->out sram[96]->outb sram[96]->out sram[97]->out sram[97]->outb sram[98]->out sram[98]->outb sram[99]->out sram[99]->outb sram[100]->out sram[100]->outb sram[101]->out sram[101]->outb sram[102]->out sram[102]->outb sram[103]->out sram[103]->outb sram[104]->outb sram[104]->out sram[105]->out sram[105]->outb sram[106]->out sram[106]->outb sram[107]->out sram[107]->outb sram[108]->out sram[108]->outb sram[109]->out sram[109]->outb sram[110]->out sram[110]->outb sram[111]->out sram[111]->outb gvdd_mux_2level_size50[6] 0 mux_2level_size50 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[100]->out) 0 -.nodeset V(sram[100]->outb) vsp -Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[101]->out) 0 -.nodeset V(sram[101]->outb) vsp -Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[102]->out) 0 -.nodeset V(sram[102]->outb) vsp -Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[103]->out) 0 -.nodeset V(sram[103]->outb) vsp -Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[104]->out) 0 -.nodeset V(sram[104]->outb) vsp -Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[105]->out) 0 -.nodeset V(sram[105]->outb) vsp -Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[106]->out) 0 -.nodeset V(sram[106]->outb) vsp -Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[107]->out) 0 -.nodeset V(sram[107]->outb) vsp -Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[108]->out) 0 -.nodeset V(sram[108]->outb) vsp -Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[109]->out) 0 -.nodeset V(sram[109]->outb) vsp -Xsram[110] sram->in sram[110]->out sram[110]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[110]->out) 0 -.nodeset V(sram[110]->outb) vsp -Xsram[111] sram->in sram[111]->out sram[111]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[111]->out) 0 -.nodeset V(sram[111]->outb) vsp -***** Signal mux_2level_size50[6]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[0] mux_2level_size50[6]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[1] mux_2level_size50[6]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[2] mux_2level_size50[6]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[3] mux_2level_size50[6]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[4] mux_2level_size50[6]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[5] mux_2level_size50[6]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[6] mux_2level_size50[6]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[7] mux_2level_size50[6]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[8] mux_2level_size50[6]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[9] mux_2level_size50[6]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[10] mux_2level_size50[6]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[11] mux_2level_size50[6]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[12] mux_2level_size50[6]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[13] mux_2level_size50[6]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[14] mux_2level_size50[6]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[15] mux_2level_size50[6]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[16] mux_2level_size50[6]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[17] mux_2level_size50[6]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[18] mux_2level_size50[6]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[19] mux_2level_size50[6]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[20] mux_2level_size50[6]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[21] mux_2level_size50[6]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[22] mux_2level_size50[6]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[23] mux_2level_size50[6]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[24] mux_2level_size50[6]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[25] mux_2level_size50[6]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[26] mux_2level_size50[6]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[27] mux_2level_size50[6]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[28] mux_2level_size50[6]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[29] mux_2level_size50[6]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[30] mux_2level_size50[6]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[31] mux_2level_size50[6]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[32] mux_2level_size50[6]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[33] mux_2level_size50[6]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[34] mux_2level_size50[6]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[35] mux_2level_size50[6]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[36] mux_2level_size50[6]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[37] mux_2level_size50[6]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[38] mux_2level_size50[6]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[6]->in[39] mux_2level_size50[6]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[6]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[40] mux_2level_size50[6]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[41] mux_2level_size50[6]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[42] mux_2level_size50[6]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[43] mux_2level_size50[6]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[44] mux_2level_size50[6]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[45] mux_2level_size50[6]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[46] mux_2level_size50[6]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[47] mux_2level_size50[6]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[48] mux_2level_size50[6]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[6]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[6]->in[49] mux_2level_size50[6]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[6] gvdd_mux_2level_size50[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[6]_in[0]_crossbar trig v(mux_2level_size50[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[6]_in[0]_crossbar trig v(mux_2level_size50[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[6]_in[0]_crossbar when v(mux_2level_size50[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[6]_in[0]_crossbar trig v(mux_2level_size50[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[6]_in[0]_crossbar when v(mux_2level_size50[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[6]_in[0]_crossbar trig v(mux_2level_size50[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[6]_leakage_power avg p(Vgvdd_mux_2level_size50[6]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[6]_in[0]_crossbar param='mux_2level_size50[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[6]_dynamic_power avg p(Vgvdd_mux_2level_size50[6]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[6]_energy_per_cycle param='mux_2level_size50[6]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[6]_in[0]_crossbar param='mux_2level_size50[6]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[6]_in[0]_crossbar param='dynamic_power_idle_mux50[6]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[6]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[6]) from='start_rise_idle_mux50[6]_in[0]_crossbar' to='start_rise_idle_mux50[6]_in[0]_crossbar+switch_rise_idle_mux50[6]_in[0]_crossbar' -.meas tran dynamic_fall_idle_mux50[6]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[6]) from='start_fall_idle_mux50[6]_in[0]_crossbar' to='start_fall_idle_mux50[6]_in[0]_crossbar+switch_fall_idle_mux50[6]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_idle_mux50[6]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_idle_mux50[6]_in[0]_crossbar' -Xload_inv[6]_no0 mux_2level_size50[6]->out mux_2level_size50[6]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to6] -+ param='sum_leakage_power_pb_mux[0to5]+leakage_idle_mux50[6]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to6] -+ param='sum_energy_per_cycle_pb_mux[0to5]+energy_per_cycle_idle_mux50[6]_in[0]_crossbar' -Xmux_2level_size50[7] mux_2level_size50[7]->in[0] mux_2level_size50[7]->in[1] mux_2level_size50[7]->in[2] mux_2level_size50[7]->in[3] mux_2level_size50[7]->in[4] mux_2level_size50[7]->in[5] mux_2level_size50[7]->in[6] mux_2level_size50[7]->in[7] mux_2level_size50[7]->in[8] mux_2level_size50[7]->in[9] mux_2level_size50[7]->in[10] mux_2level_size50[7]->in[11] mux_2level_size50[7]->in[12] mux_2level_size50[7]->in[13] mux_2level_size50[7]->in[14] mux_2level_size50[7]->in[15] mux_2level_size50[7]->in[16] mux_2level_size50[7]->in[17] mux_2level_size50[7]->in[18] mux_2level_size50[7]->in[19] mux_2level_size50[7]->in[20] mux_2level_size50[7]->in[21] mux_2level_size50[7]->in[22] mux_2level_size50[7]->in[23] mux_2level_size50[7]->in[24] mux_2level_size50[7]->in[25] mux_2level_size50[7]->in[26] mux_2level_size50[7]->in[27] mux_2level_size50[7]->in[28] mux_2level_size50[7]->in[29] mux_2level_size50[7]->in[30] mux_2level_size50[7]->in[31] mux_2level_size50[7]->in[32] mux_2level_size50[7]->in[33] mux_2level_size50[7]->in[34] mux_2level_size50[7]->in[35] mux_2level_size50[7]->in[36] mux_2level_size50[7]->in[37] mux_2level_size50[7]->in[38] mux_2level_size50[7]->in[39] mux_2level_size50[7]->in[40] mux_2level_size50[7]->in[41] mux_2level_size50[7]->in[42] mux_2level_size50[7]->in[43] mux_2level_size50[7]->in[44] mux_2level_size50[7]->in[45] mux_2level_size50[7]->in[46] mux_2level_size50[7]->in[47] mux_2level_size50[7]->in[48] mux_2level_size50[7]->in[49] mux_2level_size50[7]->out sram[112]->outb sram[112]->out sram[113]->out sram[113]->outb sram[114]->out sram[114]->outb sram[115]->out sram[115]->outb sram[116]->out sram[116]->outb sram[117]->out sram[117]->outb sram[118]->out sram[118]->outb sram[119]->out sram[119]->outb sram[120]->outb sram[120]->out sram[121]->out sram[121]->outb sram[122]->out sram[122]->outb sram[123]->out sram[123]->outb sram[124]->out sram[124]->outb sram[125]->out sram[125]->outb sram[126]->out sram[126]->outb sram[127]->out sram[127]->outb gvdd_mux_2level_size50[7] 0 mux_2level_size50 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[112] sram->in sram[112]->out sram[112]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[112]->out) 0 -.nodeset V(sram[112]->outb) vsp -Xsram[113] sram->in sram[113]->out sram[113]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[113]->out) 0 -.nodeset V(sram[113]->outb) vsp -Xsram[114] sram->in sram[114]->out sram[114]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[114]->out) 0 -.nodeset V(sram[114]->outb) vsp -Xsram[115] sram->in sram[115]->out sram[115]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[115]->out) 0 -.nodeset V(sram[115]->outb) vsp -Xsram[116] sram->in sram[116]->out sram[116]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[116]->out) 0 -.nodeset V(sram[116]->outb) vsp -Xsram[117] sram->in sram[117]->out sram[117]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[117]->out) 0 -.nodeset V(sram[117]->outb) vsp -Xsram[118] sram->in sram[118]->out sram[118]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[118]->out) 0 -.nodeset V(sram[118]->outb) vsp -Xsram[119] sram->in sram[119]->out sram[119]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[119]->out) 0 -.nodeset V(sram[119]->outb) vsp -Xsram[120] sram->in sram[120]->out sram[120]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[120]->out) 0 -.nodeset V(sram[120]->outb) vsp -Xsram[121] sram->in sram[121]->out sram[121]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[121]->out) 0 -.nodeset V(sram[121]->outb) vsp -Xsram[122] sram->in sram[122]->out sram[122]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[122]->out) 0 -.nodeset V(sram[122]->outb) vsp -Xsram[123] sram->in sram[123]->out sram[123]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[123]->out) 0 -.nodeset V(sram[123]->outb) vsp -Xsram[124] sram->in sram[124]->out sram[124]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[124]->out) 0 -.nodeset V(sram[124]->outb) vsp -Xsram[125] sram->in sram[125]->out sram[125]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[125]->out) 0 -.nodeset V(sram[125]->outb) vsp -Xsram[126] sram->in sram[126]->out sram[126]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[126]->out) 0 -.nodeset V(sram[126]->outb) vsp -Xsram[127] sram->in sram[127]->out sram[127]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[127]->out) 0 -.nodeset V(sram[127]->outb) vsp -***** Signal mux_2level_size50[7]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[0] mux_2level_size50[7]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[1] mux_2level_size50[7]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[2] mux_2level_size50[7]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[3] mux_2level_size50[7]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[4] mux_2level_size50[7]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[5] mux_2level_size50[7]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[6] mux_2level_size50[7]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[7] mux_2level_size50[7]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[8] mux_2level_size50[7]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[9] mux_2level_size50[7]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[10] mux_2level_size50[7]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[11] mux_2level_size50[7]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[12] mux_2level_size50[7]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[13] mux_2level_size50[7]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[14] mux_2level_size50[7]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[15] mux_2level_size50[7]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[16] mux_2level_size50[7]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[17] mux_2level_size50[7]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[18] mux_2level_size50[7]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[19] mux_2level_size50[7]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[20] mux_2level_size50[7]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[21] mux_2level_size50[7]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[22] mux_2level_size50[7]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[23] mux_2level_size50[7]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[24] mux_2level_size50[7]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[25] mux_2level_size50[7]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[26] mux_2level_size50[7]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[27] mux_2level_size50[7]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[28] mux_2level_size50[7]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[29] mux_2level_size50[7]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[30] mux_2level_size50[7]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[31] mux_2level_size50[7]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[32] mux_2level_size50[7]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[33] mux_2level_size50[7]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[34] mux_2level_size50[7]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[35] mux_2level_size50[7]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[36] mux_2level_size50[7]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[37] mux_2level_size50[7]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[38] mux_2level_size50[7]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[7]->in[39] mux_2level_size50[7]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[7]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[40] mux_2level_size50[7]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[41] mux_2level_size50[7]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[42] mux_2level_size50[7]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[43] mux_2level_size50[7]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[44] mux_2level_size50[7]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[45] mux_2level_size50[7]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[46] mux_2level_size50[7]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[47] mux_2level_size50[7]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[48] mux_2level_size50[7]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[7]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[7]->in[49] mux_2level_size50[7]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[7] gvdd_mux_2level_size50[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[7]_in[1]_crossbar trig v(mux_2level_size50[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[7]_in[1]_crossbar trig v(mux_2level_size50[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[7]_in[1]_crossbar when v(mux_2level_size50[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[7]_in[1]_crossbar trig v(mux_2level_size50[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[7]_in[1]_crossbar when v(mux_2level_size50[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[7]_in[1]_crossbar trig v(mux_2level_size50[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[7]_leakage_power avg p(Vgvdd_mux_2level_size50[7]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[7]_in[1]_crossbar param='mux_2level_size50[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[7]_dynamic_power avg p(Vgvdd_mux_2level_size50[7]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[7]_energy_per_cycle param='mux_2level_size50[7]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[7]_in[1]_crossbar param='mux_2level_size50[7]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[7]_in[1]_crossbar param='dynamic_power_idle_mux50[7]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[7]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[7]) from='start_rise_idle_mux50[7]_in[1]_crossbar' to='start_rise_idle_mux50[7]_in[1]_crossbar+switch_rise_idle_mux50[7]_in[1]_crossbar' -.meas tran dynamic_fall_idle_mux50[7]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[7]) from='start_fall_idle_mux50[7]_in[1]_crossbar' to='start_fall_idle_mux50[7]_in[1]_crossbar+switch_fall_idle_mux50[7]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_idle_mux50[7]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_idle_mux50[7]_in[1]_crossbar' -Xload_inv[7]_no0 mux_2level_size50[7]->out mux_2level_size50[7]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to7] -+ param='sum_leakage_power_pb_mux[0to6]+leakage_idle_mux50[7]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to7] -+ param='sum_energy_per_cycle_pb_mux[0to6]+energy_per_cycle_idle_mux50[7]_in[1]_crossbar' -Xmux_2level_size50[8] mux_2level_size50[8]->in[0] mux_2level_size50[8]->in[1] mux_2level_size50[8]->in[2] mux_2level_size50[8]->in[3] mux_2level_size50[8]->in[4] mux_2level_size50[8]->in[5] mux_2level_size50[8]->in[6] mux_2level_size50[8]->in[7] mux_2level_size50[8]->in[8] mux_2level_size50[8]->in[9] mux_2level_size50[8]->in[10] mux_2level_size50[8]->in[11] mux_2level_size50[8]->in[12] mux_2level_size50[8]->in[13] mux_2level_size50[8]->in[14] mux_2level_size50[8]->in[15] mux_2level_size50[8]->in[16] mux_2level_size50[8]->in[17] mux_2level_size50[8]->in[18] mux_2level_size50[8]->in[19] mux_2level_size50[8]->in[20] mux_2level_size50[8]->in[21] mux_2level_size50[8]->in[22] mux_2level_size50[8]->in[23] mux_2level_size50[8]->in[24] mux_2level_size50[8]->in[25] mux_2level_size50[8]->in[26] mux_2level_size50[8]->in[27] mux_2level_size50[8]->in[28] mux_2level_size50[8]->in[29] mux_2level_size50[8]->in[30] mux_2level_size50[8]->in[31] mux_2level_size50[8]->in[32] mux_2level_size50[8]->in[33] mux_2level_size50[8]->in[34] mux_2level_size50[8]->in[35] mux_2level_size50[8]->in[36] mux_2level_size50[8]->in[37] mux_2level_size50[8]->in[38] mux_2level_size50[8]->in[39] mux_2level_size50[8]->in[40] mux_2level_size50[8]->in[41] mux_2level_size50[8]->in[42] mux_2level_size50[8]->in[43] mux_2level_size50[8]->in[44] mux_2level_size50[8]->in[45] mux_2level_size50[8]->in[46] mux_2level_size50[8]->in[47] mux_2level_size50[8]->in[48] mux_2level_size50[8]->in[49] mux_2level_size50[8]->out sram[128]->outb sram[128]->out sram[129]->out sram[129]->outb sram[130]->out sram[130]->outb sram[131]->out sram[131]->outb sram[132]->out sram[132]->outb sram[133]->out sram[133]->outb sram[134]->out sram[134]->outb sram[135]->out sram[135]->outb sram[136]->outb sram[136]->out sram[137]->out sram[137]->outb sram[138]->out sram[138]->outb sram[139]->out sram[139]->outb sram[140]->out sram[140]->outb sram[141]->out sram[141]->outb sram[142]->out sram[142]->outb sram[143]->out sram[143]->outb gvdd_mux_2level_size50[8] 0 mux_2level_size50 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[128] sram->in sram[128]->out sram[128]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[128]->out) 0 -.nodeset V(sram[128]->outb) vsp -Xsram[129] sram->in sram[129]->out sram[129]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[129]->out) 0 -.nodeset V(sram[129]->outb) vsp -Xsram[130] sram->in sram[130]->out sram[130]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[130]->out) 0 -.nodeset V(sram[130]->outb) vsp -Xsram[131] sram->in sram[131]->out sram[131]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[131]->out) 0 -.nodeset V(sram[131]->outb) vsp -Xsram[132] sram->in sram[132]->out sram[132]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[132]->out) 0 -.nodeset V(sram[132]->outb) vsp -Xsram[133] sram->in sram[133]->out sram[133]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[133]->out) 0 -.nodeset V(sram[133]->outb) vsp -Xsram[134] sram->in sram[134]->out sram[134]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[134]->out) 0 -.nodeset V(sram[134]->outb) vsp -Xsram[135] sram->in sram[135]->out sram[135]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[135]->out) 0 -.nodeset V(sram[135]->outb) vsp -Xsram[136] sram->in sram[136]->out sram[136]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[136]->out) 0 -.nodeset V(sram[136]->outb) vsp -Xsram[137] sram->in sram[137]->out sram[137]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[137]->out) 0 -.nodeset V(sram[137]->outb) vsp -Xsram[138] sram->in sram[138]->out sram[138]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[138]->out) 0 -.nodeset V(sram[138]->outb) vsp -Xsram[139] sram->in sram[139]->out sram[139]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[139]->out) 0 -.nodeset V(sram[139]->outb) vsp -Xsram[140] sram->in sram[140]->out sram[140]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[140]->out) 0 -.nodeset V(sram[140]->outb) vsp -Xsram[141] sram->in sram[141]->out sram[141]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[141]->out) 0 -.nodeset V(sram[141]->outb) vsp -Xsram[142] sram->in sram[142]->out sram[142]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[142]->out) 0 -.nodeset V(sram[142]->outb) vsp -Xsram[143] sram->in sram[143]->out sram[143]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[143]->out) 0 -.nodeset V(sram[143]->outb) vsp -***** Signal mux_2level_size50[8]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[0] mux_2level_size50[8]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[1] mux_2level_size50[8]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[2] mux_2level_size50[8]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[3] mux_2level_size50[8]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[4] mux_2level_size50[8]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[5] mux_2level_size50[8]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[6] mux_2level_size50[8]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[7] mux_2level_size50[8]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[8] mux_2level_size50[8]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[9] mux_2level_size50[8]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[10] mux_2level_size50[8]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[11] mux_2level_size50[8]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[12] mux_2level_size50[8]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[13] mux_2level_size50[8]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[14] mux_2level_size50[8]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[15] mux_2level_size50[8]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[16] mux_2level_size50[8]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[17] mux_2level_size50[8]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[18] mux_2level_size50[8]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[19] mux_2level_size50[8]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[20] mux_2level_size50[8]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[21] mux_2level_size50[8]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[22] mux_2level_size50[8]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[23] mux_2level_size50[8]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[24] mux_2level_size50[8]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[25] mux_2level_size50[8]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[26] mux_2level_size50[8]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[27] mux_2level_size50[8]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[28] mux_2level_size50[8]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[29] mux_2level_size50[8]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[30] mux_2level_size50[8]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[31] mux_2level_size50[8]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[32] mux_2level_size50[8]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[33] mux_2level_size50[8]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[34] mux_2level_size50[8]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[35] mux_2level_size50[8]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[36] mux_2level_size50[8]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[37] mux_2level_size50[8]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[38] mux_2level_size50[8]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[8]->in[39] mux_2level_size50[8]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[8]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[40] mux_2level_size50[8]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[41] mux_2level_size50[8]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[42] mux_2level_size50[8]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[43] mux_2level_size50[8]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[44] mux_2level_size50[8]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[45] mux_2level_size50[8]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[46] mux_2level_size50[8]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[47] mux_2level_size50[8]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[48] mux_2level_size50[8]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[8]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[8]->in[49] mux_2level_size50[8]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[8] gvdd_mux_2level_size50[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[8]_in[2]_crossbar trig v(mux_2level_size50[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[8]_in[2]_crossbar trig v(mux_2level_size50[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[8]_in[2]_crossbar when v(mux_2level_size50[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[8]_in[2]_crossbar trig v(mux_2level_size50[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[8]_in[2]_crossbar when v(mux_2level_size50[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[8]_in[2]_crossbar trig v(mux_2level_size50[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[8]_leakage_power avg p(Vgvdd_mux_2level_size50[8]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[8]_in[2]_crossbar param='mux_2level_size50[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[8]_dynamic_power avg p(Vgvdd_mux_2level_size50[8]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[8]_energy_per_cycle param='mux_2level_size50[8]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[8]_in[2]_crossbar param='mux_2level_size50[8]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[8]_in[2]_crossbar param='dynamic_power_idle_mux50[8]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[8]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[8]) from='start_rise_idle_mux50[8]_in[2]_crossbar' to='start_rise_idle_mux50[8]_in[2]_crossbar+switch_rise_idle_mux50[8]_in[2]_crossbar' -.meas tran dynamic_fall_idle_mux50[8]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[8]) from='start_fall_idle_mux50[8]_in[2]_crossbar' to='start_fall_idle_mux50[8]_in[2]_crossbar+switch_fall_idle_mux50[8]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_idle_mux50[8]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_idle_mux50[8]_in[2]_crossbar' -Xload_inv[8]_no0 mux_2level_size50[8]->out mux_2level_size50[8]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to8] -+ param='sum_leakage_power_pb_mux[0to7]+leakage_idle_mux50[8]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to8] -+ param='sum_energy_per_cycle_pb_mux[0to7]+energy_per_cycle_idle_mux50[8]_in[2]_crossbar' -Xmux_2level_size50[9] mux_2level_size50[9]->in[0] mux_2level_size50[9]->in[1] mux_2level_size50[9]->in[2] mux_2level_size50[9]->in[3] mux_2level_size50[9]->in[4] mux_2level_size50[9]->in[5] mux_2level_size50[9]->in[6] mux_2level_size50[9]->in[7] mux_2level_size50[9]->in[8] mux_2level_size50[9]->in[9] mux_2level_size50[9]->in[10] mux_2level_size50[9]->in[11] mux_2level_size50[9]->in[12] mux_2level_size50[9]->in[13] mux_2level_size50[9]->in[14] mux_2level_size50[9]->in[15] mux_2level_size50[9]->in[16] mux_2level_size50[9]->in[17] mux_2level_size50[9]->in[18] mux_2level_size50[9]->in[19] mux_2level_size50[9]->in[20] mux_2level_size50[9]->in[21] mux_2level_size50[9]->in[22] mux_2level_size50[9]->in[23] mux_2level_size50[9]->in[24] mux_2level_size50[9]->in[25] mux_2level_size50[9]->in[26] mux_2level_size50[9]->in[27] mux_2level_size50[9]->in[28] mux_2level_size50[9]->in[29] mux_2level_size50[9]->in[30] mux_2level_size50[9]->in[31] mux_2level_size50[9]->in[32] mux_2level_size50[9]->in[33] mux_2level_size50[9]->in[34] mux_2level_size50[9]->in[35] mux_2level_size50[9]->in[36] mux_2level_size50[9]->in[37] mux_2level_size50[9]->in[38] mux_2level_size50[9]->in[39] mux_2level_size50[9]->in[40] mux_2level_size50[9]->in[41] mux_2level_size50[9]->in[42] mux_2level_size50[9]->in[43] mux_2level_size50[9]->in[44] mux_2level_size50[9]->in[45] mux_2level_size50[9]->in[46] mux_2level_size50[9]->in[47] mux_2level_size50[9]->in[48] mux_2level_size50[9]->in[49] mux_2level_size50[9]->out sram[144]->outb sram[144]->out sram[145]->out sram[145]->outb sram[146]->out sram[146]->outb sram[147]->out sram[147]->outb sram[148]->out sram[148]->outb sram[149]->out sram[149]->outb sram[150]->out sram[150]->outb sram[151]->out sram[151]->outb sram[152]->outb sram[152]->out sram[153]->out sram[153]->outb sram[154]->out sram[154]->outb sram[155]->out sram[155]->outb sram[156]->out sram[156]->outb sram[157]->out sram[157]->outb sram[158]->out sram[158]->outb sram[159]->out sram[159]->outb gvdd_mux_2level_size50[9] 0 mux_2level_size50 -***** SRAM bits for MUX[9], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[144] sram->in sram[144]->out sram[144]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[144]->out) 0 -.nodeset V(sram[144]->outb) vsp -Xsram[145] sram->in sram[145]->out sram[145]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[145]->out) 0 -.nodeset V(sram[145]->outb) vsp -Xsram[146] sram->in sram[146]->out sram[146]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[146]->out) 0 -.nodeset V(sram[146]->outb) vsp -Xsram[147] sram->in sram[147]->out sram[147]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[147]->out) 0 -.nodeset V(sram[147]->outb) vsp -Xsram[148] sram->in sram[148]->out sram[148]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[148]->out) 0 -.nodeset V(sram[148]->outb) vsp -Xsram[149] sram->in sram[149]->out sram[149]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[149]->out) 0 -.nodeset V(sram[149]->outb) vsp -Xsram[150] sram->in sram[150]->out sram[150]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[150]->out) 0 -.nodeset V(sram[150]->outb) vsp -Xsram[151] sram->in sram[151]->out sram[151]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[151]->out) 0 -.nodeset V(sram[151]->outb) vsp -Xsram[152] sram->in sram[152]->out sram[152]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[152]->out) 0 -.nodeset V(sram[152]->outb) vsp -Xsram[153] sram->in sram[153]->out sram[153]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[153]->out) 0 -.nodeset V(sram[153]->outb) vsp -Xsram[154] sram->in sram[154]->out sram[154]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[154]->out) 0 -.nodeset V(sram[154]->outb) vsp -Xsram[155] sram->in sram[155]->out sram[155]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[155]->out) 0 -.nodeset V(sram[155]->outb) vsp -Xsram[156] sram->in sram[156]->out sram[156]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[156]->out) 0 -.nodeset V(sram[156]->outb) vsp -Xsram[157] sram->in sram[157]->out sram[157]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[157]->out) 0 -.nodeset V(sram[157]->outb) vsp -Xsram[158] sram->in sram[158]->out sram[158]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[158]->out) 0 -.nodeset V(sram[158]->outb) vsp -Xsram[159] sram->in sram[159]->out sram[159]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[159]->out) 0 -.nodeset V(sram[159]->outb) vsp -***** Signal mux_2level_size50[9]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[0] mux_2level_size50[9]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[1] mux_2level_size50[9]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[2] mux_2level_size50[9]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[3] mux_2level_size50[9]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[4] mux_2level_size50[9]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[5] mux_2level_size50[9]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[6] mux_2level_size50[9]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[7] mux_2level_size50[9]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[8] mux_2level_size50[9]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[9] mux_2level_size50[9]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[10] mux_2level_size50[9]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[11] mux_2level_size50[9]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[12] mux_2level_size50[9]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[13] mux_2level_size50[9]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[14] mux_2level_size50[9]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[15] mux_2level_size50[9]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[16] mux_2level_size50[9]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[17] mux_2level_size50[9]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[18] mux_2level_size50[9]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[19] mux_2level_size50[9]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[20] mux_2level_size50[9]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[21] mux_2level_size50[9]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[22] mux_2level_size50[9]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[23] mux_2level_size50[9]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[24] mux_2level_size50[9]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[25] mux_2level_size50[9]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[26] mux_2level_size50[9]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[27] mux_2level_size50[9]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[28] mux_2level_size50[9]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[29] mux_2level_size50[9]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[30] mux_2level_size50[9]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[31] mux_2level_size50[9]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[32] mux_2level_size50[9]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[33] mux_2level_size50[9]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[34] mux_2level_size50[9]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[35] mux_2level_size50[9]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[36] mux_2level_size50[9]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[37] mux_2level_size50[9]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[38] mux_2level_size50[9]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[9]->in[39] mux_2level_size50[9]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[9]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[40] mux_2level_size50[9]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[41] mux_2level_size50[9]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[42] mux_2level_size50[9]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[43] mux_2level_size50[9]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[44] mux_2level_size50[9]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[45] mux_2level_size50[9]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[46] mux_2level_size50[9]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[47] mux_2level_size50[9]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[48] mux_2level_size50[9]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[9]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[9]->in[49] mux_2level_size50[9]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[9] gvdd_mux_2level_size50[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[9]_in[3]_crossbar trig v(mux_2level_size50[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[9]_in[3]_crossbar trig v(mux_2level_size50[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[9]_in[3]_crossbar when v(mux_2level_size50[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[9]_in[3]_crossbar trig v(mux_2level_size50[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[9]_in[3]_crossbar when v(mux_2level_size50[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[9]_in[3]_crossbar trig v(mux_2level_size50[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[9]_leakage_power avg p(Vgvdd_mux_2level_size50[9]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[9]_in[3]_crossbar param='mux_2level_size50[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[9]_dynamic_power avg p(Vgvdd_mux_2level_size50[9]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[9]_energy_per_cycle param='mux_2level_size50[9]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[9]_in[3]_crossbar param='mux_2level_size50[9]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[9]_in[3]_crossbar param='dynamic_power_idle_mux50[9]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[9]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[9]) from='start_rise_idle_mux50[9]_in[3]_crossbar' to='start_rise_idle_mux50[9]_in[3]_crossbar+switch_rise_idle_mux50[9]_in[3]_crossbar' -.meas tran dynamic_fall_idle_mux50[9]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[9]) from='start_fall_idle_mux50[9]_in[3]_crossbar' to='start_fall_idle_mux50[9]_in[3]_crossbar+switch_fall_idle_mux50[9]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_idle_mux50[9]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_idle_mux50[9]_in[3]_crossbar' -Xload_inv[9]_no0 mux_2level_size50[9]->out mux_2level_size50[9]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to9] -+ param='sum_leakage_power_pb_mux[0to8]+leakage_idle_mux50[9]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to9] -+ param='sum_energy_per_cycle_pb_mux[0to8]+energy_per_cycle_idle_mux50[9]_in[3]_crossbar' -Xmux_2level_size50[10] mux_2level_size50[10]->in[0] mux_2level_size50[10]->in[1] mux_2level_size50[10]->in[2] mux_2level_size50[10]->in[3] mux_2level_size50[10]->in[4] mux_2level_size50[10]->in[5] mux_2level_size50[10]->in[6] mux_2level_size50[10]->in[7] mux_2level_size50[10]->in[8] mux_2level_size50[10]->in[9] mux_2level_size50[10]->in[10] mux_2level_size50[10]->in[11] mux_2level_size50[10]->in[12] mux_2level_size50[10]->in[13] mux_2level_size50[10]->in[14] mux_2level_size50[10]->in[15] mux_2level_size50[10]->in[16] mux_2level_size50[10]->in[17] mux_2level_size50[10]->in[18] mux_2level_size50[10]->in[19] mux_2level_size50[10]->in[20] mux_2level_size50[10]->in[21] mux_2level_size50[10]->in[22] mux_2level_size50[10]->in[23] mux_2level_size50[10]->in[24] mux_2level_size50[10]->in[25] mux_2level_size50[10]->in[26] mux_2level_size50[10]->in[27] mux_2level_size50[10]->in[28] mux_2level_size50[10]->in[29] mux_2level_size50[10]->in[30] mux_2level_size50[10]->in[31] mux_2level_size50[10]->in[32] mux_2level_size50[10]->in[33] mux_2level_size50[10]->in[34] mux_2level_size50[10]->in[35] mux_2level_size50[10]->in[36] mux_2level_size50[10]->in[37] mux_2level_size50[10]->in[38] mux_2level_size50[10]->in[39] mux_2level_size50[10]->in[40] mux_2level_size50[10]->in[41] mux_2level_size50[10]->in[42] mux_2level_size50[10]->in[43] mux_2level_size50[10]->in[44] mux_2level_size50[10]->in[45] mux_2level_size50[10]->in[46] mux_2level_size50[10]->in[47] mux_2level_size50[10]->in[48] mux_2level_size50[10]->in[49] mux_2level_size50[10]->out sram[160]->outb sram[160]->out sram[161]->out sram[161]->outb sram[162]->out sram[162]->outb sram[163]->out sram[163]->outb sram[164]->out sram[164]->outb sram[165]->out sram[165]->outb sram[166]->out sram[166]->outb sram[167]->out sram[167]->outb sram[168]->outb sram[168]->out sram[169]->out sram[169]->outb sram[170]->out sram[170]->outb sram[171]->out sram[171]->outb sram[172]->out sram[172]->outb sram[173]->out sram[173]->outb sram[174]->out sram[174]->outb sram[175]->out sram[175]->outb gvdd_mux_2level_size50[10] 0 mux_2level_size50 -***** SRAM bits for MUX[10], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[160] sram->in sram[160]->out sram[160]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[160]->out) 0 -.nodeset V(sram[160]->outb) vsp -Xsram[161] sram->in sram[161]->out sram[161]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[161]->out) 0 -.nodeset V(sram[161]->outb) vsp -Xsram[162] sram->in sram[162]->out sram[162]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[162]->out) 0 -.nodeset V(sram[162]->outb) vsp -Xsram[163] sram->in sram[163]->out sram[163]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[163]->out) 0 -.nodeset V(sram[163]->outb) vsp -Xsram[164] sram->in sram[164]->out sram[164]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[164]->out) 0 -.nodeset V(sram[164]->outb) vsp -Xsram[165] sram->in sram[165]->out sram[165]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[165]->out) 0 -.nodeset V(sram[165]->outb) vsp -Xsram[166] sram->in sram[166]->out sram[166]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[166]->out) 0 -.nodeset V(sram[166]->outb) vsp -Xsram[167] sram->in sram[167]->out sram[167]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[167]->out) 0 -.nodeset V(sram[167]->outb) vsp -Xsram[168] sram->in sram[168]->out sram[168]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[168]->out) 0 -.nodeset V(sram[168]->outb) vsp -Xsram[169] sram->in sram[169]->out sram[169]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[169]->out) 0 -.nodeset V(sram[169]->outb) vsp -Xsram[170] sram->in sram[170]->out sram[170]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[170]->out) 0 -.nodeset V(sram[170]->outb) vsp -Xsram[171] sram->in sram[171]->out sram[171]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[171]->out) 0 -.nodeset V(sram[171]->outb) vsp -Xsram[172] sram->in sram[172]->out sram[172]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[172]->out) 0 -.nodeset V(sram[172]->outb) vsp -Xsram[173] sram->in sram[173]->out sram[173]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[173]->out) 0 -.nodeset V(sram[173]->outb) vsp -Xsram[174] sram->in sram[174]->out sram[174]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[174]->out) 0 -.nodeset V(sram[174]->outb) vsp -Xsram[175] sram->in sram[175]->out sram[175]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[175]->out) 0 -.nodeset V(sram[175]->outb) vsp -***** Signal mux_2level_size50[10]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[0] mux_2level_size50[10]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[1] mux_2level_size50[10]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[2] mux_2level_size50[10]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[3] mux_2level_size50[10]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[4] mux_2level_size50[10]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[5] mux_2level_size50[10]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[6] mux_2level_size50[10]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[7] mux_2level_size50[10]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[8] mux_2level_size50[10]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[9] mux_2level_size50[10]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[10] mux_2level_size50[10]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[11] mux_2level_size50[10]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[12] mux_2level_size50[10]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[13] mux_2level_size50[10]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[14] mux_2level_size50[10]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[15] mux_2level_size50[10]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[16] mux_2level_size50[10]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[17] mux_2level_size50[10]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[18] mux_2level_size50[10]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[19] mux_2level_size50[10]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[20] mux_2level_size50[10]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[21] mux_2level_size50[10]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[22] mux_2level_size50[10]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[23] mux_2level_size50[10]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[24] mux_2level_size50[10]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[25] mux_2level_size50[10]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[26] mux_2level_size50[10]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[27] mux_2level_size50[10]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[28] mux_2level_size50[10]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[29] mux_2level_size50[10]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[30] mux_2level_size50[10]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[31] mux_2level_size50[10]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[32] mux_2level_size50[10]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[33] mux_2level_size50[10]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[34] mux_2level_size50[10]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[35] mux_2level_size50[10]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[36] mux_2level_size50[10]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[37] mux_2level_size50[10]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[38] mux_2level_size50[10]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[10]->in[39] mux_2level_size50[10]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[10]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[40] mux_2level_size50[10]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[41] mux_2level_size50[10]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[42] mux_2level_size50[10]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[43] mux_2level_size50[10]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[44] mux_2level_size50[10]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[45] mux_2level_size50[10]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[46] mux_2level_size50[10]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[47] mux_2level_size50[10]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[48] mux_2level_size50[10]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[10]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[10]->in[49] mux_2level_size50[10]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[10] gvdd_mux_2level_size50[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[10]_in[4]_crossbar trig v(mux_2level_size50[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[10]_in[4]_crossbar trig v(mux_2level_size50[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[10]_in[4]_crossbar when v(mux_2level_size50[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[10]_in[4]_crossbar trig v(mux_2level_size50[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[10]_in[4]_crossbar when v(mux_2level_size50[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[10]_in[4]_crossbar trig v(mux_2level_size50[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[10]_leakage_power avg p(Vgvdd_mux_2level_size50[10]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[10]_in[4]_crossbar param='mux_2level_size50[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[10]_dynamic_power avg p(Vgvdd_mux_2level_size50[10]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[10]_energy_per_cycle param='mux_2level_size50[10]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[10]_in[4]_crossbar param='mux_2level_size50[10]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[10]_in[4]_crossbar param='dynamic_power_idle_mux50[10]_in[4]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[10]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[10]) from='start_rise_idle_mux50[10]_in[4]_crossbar' to='start_rise_idle_mux50[10]_in[4]_crossbar+switch_rise_idle_mux50[10]_in[4]_crossbar' -.meas tran dynamic_fall_idle_mux50[10]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[10]) from='start_fall_idle_mux50[10]_in[4]_crossbar' to='start_fall_idle_mux50[10]_in[4]_crossbar+switch_fall_idle_mux50[10]_in[4]_crossbar' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_idle_mux50[10]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_idle_mux50[10]_in[4]_crossbar' -Xload_inv[10]_no0 mux_2level_size50[10]->out mux_2level_size50[10]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to10] -+ param='sum_leakage_power_pb_mux[0to9]+leakage_idle_mux50[10]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to10] -+ param='sum_energy_per_cycle_pb_mux[0to9]+energy_per_cycle_idle_mux50[10]_in[4]_crossbar' -Xmux_2level_size50[11] mux_2level_size50[11]->in[0] mux_2level_size50[11]->in[1] mux_2level_size50[11]->in[2] mux_2level_size50[11]->in[3] mux_2level_size50[11]->in[4] mux_2level_size50[11]->in[5] mux_2level_size50[11]->in[6] mux_2level_size50[11]->in[7] mux_2level_size50[11]->in[8] mux_2level_size50[11]->in[9] mux_2level_size50[11]->in[10] mux_2level_size50[11]->in[11] mux_2level_size50[11]->in[12] mux_2level_size50[11]->in[13] mux_2level_size50[11]->in[14] mux_2level_size50[11]->in[15] mux_2level_size50[11]->in[16] mux_2level_size50[11]->in[17] mux_2level_size50[11]->in[18] mux_2level_size50[11]->in[19] mux_2level_size50[11]->in[20] mux_2level_size50[11]->in[21] mux_2level_size50[11]->in[22] mux_2level_size50[11]->in[23] mux_2level_size50[11]->in[24] mux_2level_size50[11]->in[25] mux_2level_size50[11]->in[26] mux_2level_size50[11]->in[27] mux_2level_size50[11]->in[28] mux_2level_size50[11]->in[29] mux_2level_size50[11]->in[30] mux_2level_size50[11]->in[31] mux_2level_size50[11]->in[32] mux_2level_size50[11]->in[33] mux_2level_size50[11]->in[34] mux_2level_size50[11]->in[35] mux_2level_size50[11]->in[36] mux_2level_size50[11]->in[37] mux_2level_size50[11]->in[38] mux_2level_size50[11]->in[39] mux_2level_size50[11]->in[40] mux_2level_size50[11]->in[41] mux_2level_size50[11]->in[42] mux_2level_size50[11]->in[43] mux_2level_size50[11]->in[44] mux_2level_size50[11]->in[45] mux_2level_size50[11]->in[46] mux_2level_size50[11]->in[47] mux_2level_size50[11]->in[48] mux_2level_size50[11]->in[49] mux_2level_size50[11]->out sram[176]->outb sram[176]->out sram[177]->out sram[177]->outb sram[178]->out sram[178]->outb sram[179]->out sram[179]->outb sram[180]->out sram[180]->outb sram[181]->out sram[181]->outb sram[182]->out sram[182]->outb sram[183]->out sram[183]->outb sram[184]->outb sram[184]->out sram[185]->out sram[185]->outb sram[186]->out sram[186]->outb sram[187]->out sram[187]->outb sram[188]->out sram[188]->outb sram[189]->out sram[189]->outb sram[190]->out sram[190]->outb sram[191]->out sram[191]->outb gvdd_mux_2level_size50[11] 0 mux_2level_size50 -***** SRAM bits for MUX[11], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[176] sram->in sram[176]->out sram[176]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[176]->out) 0 -.nodeset V(sram[176]->outb) vsp -Xsram[177] sram->in sram[177]->out sram[177]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[177]->out) 0 -.nodeset V(sram[177]->outb) vsp -Xsram[178] sram->in sram[178]->out sram[178]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[178]->out) 0 -.nodeset V(sram[178]->outb) vsp -Xsram[179] sram->in sram[179]->out sram[179]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[179]->out) 0 -.nodeset V(sram[179]->outb) vsp -Xsram[180] sram->in sram[180]->out sram[180]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[180]->out) 0 -.nodeset V(sram[180]->outb) vsp -Xsram[181] sram->in sram[181]->out sram[181]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[181]->out) 0 -.nodeset V(sram[181]->outb) vsp -Xsram[182] sram->in sram[182]->out sram[182]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[182]->out) 0 -.nodeset V(sram[182]->outb) vsp -Xsram[183] sram->in sram[183]->out sram[183]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[183]->out) 0 -.nodeset V(sram[183]->outb) vsp -Xsram[184] sram->in sram[184]->out sram[184]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[184]->out) 0 -.nodeset V(sram[184]->outb) vsp -Xsram[185] sram->in sram[185]->out sram[185]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[185]->out) 0 -.nodeset V(sram[185]->outb) vsp -Xsram[186] sram->in sram[186]->out sram[186]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[186]->out) 0 -.nodeset V(sram[186]->outb) vsp -Xsram[187] sram->in sram[187]->out sram[187]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[187]->out) 0 -.nodeset V(sram[187]->outb) vsp -Xsram[188] sram->in sram[188]->out sram[188]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[188]->out) 0 -.nodeset V(sram[188]->outb) vsp -Xsram[189] sram->in sram[189]->out sram[189]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[189]->out) 0 -.nodeset V(sram[189]->outb) vsp -Xsram[190] sram->in sram[190]->out sram[190]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[190]->out) 0 -.nodeset V(sram[190]->outb) vsp -Xsram[191] sram->in sram[191]->out sram[191]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[191]->out) 0 -.nodeset V(sram[191]->outb) vsp -***** Signal mux_2level_size50[11]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[0] mux_2level_size50[11]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[1] mux_2level_size50[11]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[2] mux_2level_size50[11]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[3] mux_2level_size50[11]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[4] mux_2level_size50[11]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[5] mux_2level_size50[11]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[6] mux_2level_size50[11]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[7] mux_2level_size50[11]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[8] mux_2level_size50[11]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[9] mux_2level_size50[11]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[10] mux_2level_size50[11]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[11] mux_2level_size50[11]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[12] mux_2level_size50[11]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[13] mux_2level_size50[11]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[14] mux_2level_size50[11]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[15] mux_2level_size50[11]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[16] mux_2level_size50[11]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[17] mux_2level_size50[11]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[18] mux_2level_size50[11]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[19] mux_2level_size50[11]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[20] mux_2level_size50[11]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[21] mux_2level_size50[11]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[22] mux_2level_size50[11]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[23] mux_2level_size50[11]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[24] mux_2level_size50[11]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[25] mux_2level_size50[11]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[26] mux_2level_size50[11]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[27] mux_2level_size50[11]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[28] mux_2level_size50[11]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[29] mux_2level_size50[11]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[30] mux_2level_size50[11]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[31] mux_2level_size50[11]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[32] mux_2level_size50[11]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[33] mux_2level_size50[11]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[34] mux_2level_size50[11]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[35] mux_2level_size50[11]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[36] mux_2level_size50[11]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[37] mux_2level_size50[11]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[38] mux_2level_size50[11]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[11]->in[39] mux_2level_size50[11]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[11]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[40] mux_2level_size50[11]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[41] mux_2level_size50[11]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[42] mux_2level_size50[11]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[43] mux_2level_size50[11]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[44] mux_2level_size50[11]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[45] mux_2level_size50[11]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[46] mux_2level_size50[11]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[47] mux_2level_size50[11]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[48] mux_2level_size50[11]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[11]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[11]->in[49] mux_2level_size50[11]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[11] gvdd_mux_2level_size50[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[11]_in[5]_crossbar trig v(mux_2level_size50[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[11]_in[5]_crossbar trig v(mux_2level_size50[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[11]_in[5]_crossbar when v(mux_2level_size50[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[11]_in[5]_crossbar trig v(mux_2level_size50[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[11]_in[5]_crossbar when v(mux_2level_size50[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[11]_in[5]_crossbar trig v(mux_2level_size50[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[11]_leakage_power avg p(Vgvdd_mux_2level_size50[11]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[11]_in[5]_crossbar param='mux_2level_size50[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[11]_dynamic_power avg p(Vgvdd_mux_2level_size50[11]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[11]_energy_per_cycle param='mux_2level_size50[11]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[11]_in[5]_crossbar param='mux_2level_size50[11]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[11]_in[5]_crossbar param='dynamic_power_idle_mux50[11]_in[5]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[11]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[11]) from='start_rise_idle_mux50[11]_in[5]_crossbar' to='start_rise_idle_mux50[11]_in[5]_crossbar+switch_rise_idle_mux50[11]_in[5]_crossbar' -.meas tran dynamic_fall_idle_mux50[11]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[11]) from='start_fall_idle_mux50[11]_in[5]_crossbar' to='start_fall_idle_mux50[11]_in[5]_crossbar+switch_fall_idle_mux50[11]_in[5]_crossbar' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_idle_mux50[11]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_idle_mux50[11]_in[5]_crossbar' -Xload_inv[11]_no0 mux_2level_size50[11]->out mux_2level_size50[11]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to11] -+ param='sum_leakage_power_pb_mux[0to10]+leakage_idle_mux50[11]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to11] -+ param='sum_energy_per_cycle_pb_mux[0to10]+energy_per_cycle_idle_mux50[11]_in[5]_crossbar' -Xmux_2level_size50[12] mux_2level_size50[12]->in[0] mux_2level_size50[12]->in[1] mux_2level_size50[12]->in[2] mux_2level_size50[12]->in[3] mux_2level_size50[12]->in[4] mux_2level_size50[12]->in[5] mux_2level_size50[12]->in[6] mux_2level_size50[12]->in[7] mux_2level_size50[12]->in[8] mux_2level_size50[12]->in[9] mux_2level_size50[12]->in[10] mux_2level_size50[12]->in[11] mux_2level_size50[12]->in[12] mux_2level_size50[12]->in[13] mux_2level_size50[12]->in[14] mux_2level_size50[12]->in[15] mux_2level_size50[12]->in[16] mux_2level_size50[12]->in[17] mux_2level_size50[12]->in[18] mux_2level_size50[12]->in[19] mux_2level_size50[12]->in[20] mux_2level_size50[12]->in[21] mux_2level_size50[12]->in[22] mux_2level_size50[12]->in[23] mux_2level_size50[12]->in[24] mux_2level_size50[12]->in[25] mux_2level_size50[12]->in[26] mux_2level_size50[12]->in[27] mux_2level_size50[12]->in[28] mux_2level_size50[12]->in[29] mux_2level_size50[12]->in[30] mux_2level_size50[12]->in[31] mux_2level_size50[12]->in[32] mux_2level_size50[12]->in[33] mux_2level_size50[12]->in[34] mux_2level_size50[12]->in[35] mux_2level_size50[12]->in[36] mux_2level_size50[12]->in[37] mux_2level_size50[12]->in[38] mux_2level_size50[12]->in[39] mux_2level_size50[12]->in[40] mux_2level_size50[12]->in[41] mux_2level_size50[12]->in[42] mux_2level_size50[12]->in[43] mux_2level_size50[12]->in[44] mux_2level_size50[12]->in[45] mux_2level_size50[12]->in[46] mux_2level_size50[12]->in[47] mux_2level_size50[12]->in[48] mux_2level_size50[12]->in[49] mux_2level_size50[12]->out sram[192]->outb sram[192]->out sram[193]->out sram[193]->outb sram[194]->out sram[194]->outb sram[195]->out sram[195]->outb sram[196]->out sram[196]->outb sram[197]->out sram[197]->outb sram[198]->out sram[198]->outb sram[199]->out sram[199]->outb sram[200]->outb sram[200]->out sram[201]->out sram[201]->outb sram[202]->out sram[202]->outb sram[203]->out sram[203]->outb sram[204]->out sram[204]->outb sram[205]->out sram[205]->outb sram[206]->out sram[206]->outb sram[207]->out sram[207]->outb gvdd_mux_2level_size50[12] 0 mux_2level_size50 -***** SRAM bits for MUX[12], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[192] sram->in sram[192]->out sram[192]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[192]->out) 0 -.nodeset V(sram[192]->outb) vsp -Xsram[193] sram->in sram[193]->out sram[193]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[193]->out) 0 -.nodeset V(sram[193]->outb) vsp -Xsram[194] sram->in sram[194]->out sram[194]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[194]->out) 0 -.nodeset V(sram[194]->outb) vsp -Xsram[195] sram->in sram[195]->out sram[195]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[195]->out) 0 -.nodeset V(sram[195]->outb) vsp -Xsram[196] sram->in sram[196]->out sram[196]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[196]->out) 0 -.nodeset V(sram[196]->outb) vsp -Xsram[197] sram->in sram[197]->out sram[197]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[197]->out) 0 -.nodeset V(sram[197]->outb) vsp -Xsram[198] sram->in sram[198]->out sram[198]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[198]->out) 0 -.nodeset V(sram[198]->outb) vsp -Xsram[199] sram->in sram[199]->out sram[199]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[199]->out) 0 -.nodeset V(sram[199]->outb) vsp -Xsram[200] sram->in sram[200]->out sram[200]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[200]->out) 0 -.nodeset V(sram[200]->outb) vsp -Xsram[201] sram->in sram[201]->out sram[201]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[201]->out) 0 -.nodeset V(sram[201]->outb) vsp -Xsram[202] sram->in sram[202]->out sram[202]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[202]->out) 0 -.nodeset V(sram[202]->outb) vsp -Xsram[203] sram->in sram[203]->out sram[203]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[203]->out) 0 -.nodeset V(sram[203]->outb) vsp -Xsram[204] sram->in sram[204]->out sram[204]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[204]->out) 0 -.nodeset V(sram[204]->outb) vsp -Xsram[205] sram->in sram[205]->out sram[205]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[205]->out) 0 -.nodeset V(sram[205]->outb) vsp -Xsram[206] sram->in sram[206]->out sram[206]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[206]->out) 0 -.nodeset V(sram[206]->outb) vsp -Xsram[207] sram->in sram[207]->out sram[207]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[207]->out) 0 -.nodeset V(sram[207]->outb) vsp -***** Signal mux_2level_size50[12]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[0] mux_2level_size50[12]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[1] mux_2level_size50[12]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[2] mux_2level_size50[12]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[3] mux_2level_size50[12]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[4] mux_2level_size50[12]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[5] mux_2level_size50[12]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[6] mux_2level_size50[12]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[7] mux_2level_size50[12]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[8] mux_2level_size50[12]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[9] mux_2level_size50[12]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[10] mux_2level_size50[12]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[11] mux_2level_size50[12]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[12] mux_2level_size50[12]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[13] mux_2level_size50[12]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[14] mux_2level_size50[12]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[15] mux_2level_size50[12]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[16] mux_2level_size50[12]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[17] mux_2level_size50[12]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[18] mux_2level_size50[12]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[19] mux_2level_size50[12]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[20] mux_2level_size50[12]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[21] mux_2level_size50[12]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[22] mux_2level_size50[12]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[23] mux_2level_size50[12]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[24] mux_2level_size50[12]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[25] mux_2level_size50[12]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[26] mux_2level_size50[12]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[27] mux_2level_size50[12]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[28] mux_2level_size50[12]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[29] mux_2level_size50[12]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[30] mux_2level_size50[12]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[31] mux_2level_size50[12]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[32] mux_2level_size50[12]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[33] mux_2level_size50[12]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[34] mux_2level_size50[12]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[35] mux_2level_size50[12]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[36] mux_2level_size50[12]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[37] mux_2level_size50[12]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[38] mux_2level_size50[12]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[12]->in[39] mux_2level_size50[12]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[12]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[40] mux_2level_size50[12]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[41] mux_2level_size50[12]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[42] mux_2level_size50[12]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[43] mux_2level_size50[12]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[44] mux_2level_size50[12]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[45] mux_2level_size50[12]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[46] mux_2level_size50[12]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[47] mux_2level_size50[12]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[48] mux_2level_size50[12]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[12]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[12]->in[49] mux_2level_size50[12]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[12] gvdd_mux_2level_size50[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[12]_in[0]_crossbar trig v(mux_2level_size50[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[12]_in[0]_crossbar trig v(mux_2level_size50[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[12]_in[0]_crossbar when v(mux_2level_size50[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[12]_in[0]_crossbar trig v(mux_2level_size50[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[12]_in[0]_crossbar when v(mux_2level_size50[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[12]_in[0]_crossbar trig v(mux_2level_size50[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[12]_leakage_power avg p(Vgvdd_mux_2level_size50[12]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[12]_in[0]_crossbar param='mux_2level_size50[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[12]_dynamic_power avg p(Vgvdd_mux_2level_size50[12]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[12]_energy_per_cycle param='mux_2level_size50[12]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[12]_in[0]_crossbar param='mux_2level_size50[12]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[12]_in[0]_crossbar param='dynamic_power_idle_mux50[12]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[12]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[12]) from='start_rise_idle_mux50[12]_in[0]_crossbar' to='start_rise_idle_mux50[12]_in[0]_crossbar+switch_rise_idle_mux50[12]_in[0]_crossbar' -.meas tran dynamic_fall_idle_mux50[12]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[12]) from='start_fall_idle_mux50[12]_in[0]_crossbar' to='start_fall_idle_mux50[12]_in[0]_crossbar+switch_fall_idle_mux50[12]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_idle_mux50[12]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_idle_mux50[12]_in[0]_crossbar' -Xload_inv[12]_no0 mux_2level_size50[12]->out mux_2level_size50[12]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to12] -+ param='sum_leakage_power_pb_mux[0to11]+leakage_idle_mux50[12]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to12] -+ param='sum_energy_per_cycle_pb_mux[0to11]+energy_per_cycle_idle_mux50[12]_in[0]_crossbar' -Xmux_2level_size50[13] mux_2level_size50[13]->in[0] mux_2level_size50[13]->in[1] mux_2level_size50[13]->in[2] mux_2level_size50[13]->in[3] mux_2level_size50[13]->in[4] mux_2level_size50[13]->in[5] mux_2level_size50[13]->in[6] mux_2level_size50[13]->in[7] mux_2level_size50[13]->in[8] mux_2level_size50[13]->in[9] mux_2level_size50[13]->in[10] mux_2level_size50[13]->in[11] mux_2level_size50[13]->in[12] mux_2level_size50[13]->in[13] mux_2level_size50[13]->in[14] mux_2level_size50[13]->in[15] mux_2level_size50[13]->in[16] mux_2level_size50[13]->in[17] mux_2level_size50[13]->in[18] mux_2level_size50[13]->in[19] mux_2level_size50[13]->in[20] mux_2level_size50[13]->in[21] mux_2level_size50[13]->in[22] mux_2level_size50[13]->in[23] mux_2level_size50[13]->in[24] mux_2level_size50[13]->in[25] mux_2level_size50[13]->in[26] mux_2level_size50[13]->in[27] mux_2level_size50[13]->in[28] mux_2level_size50[13]->in[29] mux_2level_size50[13]->in[30] mux_2level_size50[13]->in[31] mux_2level_size50[13]->in[32] mux_2level_size50[13]->in[33] mux_2level_size50[13]->in[34] mux_2level_size50[13]->in[35] mux_2level_size50[13]->in[36] mux_2level_size50[13]->in[37] mux_2level_size50[13]->in[38] mux_2level_size50[13]->in[39] mux_2level_size50[13]->in[40] mux_2level_size50[13]->in[41] mux_2level_size50[13]->in[42] mux_2level_size50[13]->in[43] mux_2level_size50[13]->in[44] mux_2level_size50[13]->in[45] mux_2level_size50[13]->in[46] mux_2level_size50[13]->in[47] mux_2level_size50[13]->in[48] mux_2level_size50[13]->in[49] mux_2level_size50[13]->out sram[208]->outb sram[208]->out sram[209]->out sram[209]->outb sram[210]->out sram[210]->outb sram[211]->out sram[211]->outb sram[212]->out sram[212]->outb sram[213]->out sram[213]->outb sram[214]->out sram[214]->outb sram[215]->out sram[215]->outb sram[216]->outb sram[216]->out sram[217]->out sram[217]->outb sram[218]->out sram[218]->outb sram[219]->out sram[219]->outb sram[220]->out sram[220]->outb sram[221]->out sram[221]->outb sram[222]->out sram[222]->outb sram[223]->out sram[223]->outb gvdd_mux_2level_size50[13] 0 mux_2level_size50 -***** SRAM bits for MUX[13], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[208] sram->in sram[208]->out sram[208]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[208]->out) 0 -.nodeset V(sram[208]->outb) vsp -Xsram[209] sram->in sram[209]->out sram[209]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[209]->out) 0 -.nodeset V(sram[209]->outb) vsp -Xsram[210] sram->in sram[210]->out sram[210]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[210]->out) 0 -.nodeset V(sram[210]->outb) vsp -Xsram[211] sram->in sram[211]->out sram[211]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[211]->out) 0 -.nodeset V(sram[211]->outb) vsp -Xsram[212] sram->in sram[212]->out sram[212]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[212]->out) 0 -.nodeset V(sram[212]->outb) vsp -Xsram[213] sram->in sram[213]->out sram[213]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[213]->out) 0 -.nodeset V(sram[213]->outb) vsp -Xsram[214] sram->in sram[214]->out sram[214]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[214]->out) 0 -.nodeset V(sram[214]->outb) vsp -Xsram[215] sram->in sram[215]->out sram[215]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[215]->out) 0 -.nodeset V(sram[215]->outb) vsp -Xsram[216] sram->in sram[216]->out sram[216]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[216]->out) 0 -.nodeset V(sram[216]->outb) vsp -Xsram[217] sram->in sram[217]->out sram[217]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[217]->out) 0 -.nodeset V(sram[217]->outb) vsp -Xsram[218] sram->in sram[218]->out sram[218]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[218]->out) 0 -.nodeset V(sram[218]->outb) vsp -Xsram[219] sram->in sram[219]->out sram[219]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[219]->out) 0 -.nodeset V(sram[219]->outb) vsp -Xsram[220] sram->in sram[220]->out sram[220]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[220]->out) 0 -.nodeset V(sram[220]->outb) vsp -Xsram[221] sram->in sram[221]->out sram[221]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[221]->out) 0 -.nodeset V(sram[221]->outb) vsp -Xsram[222] sram->in sram[222]->out sram[222]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[222]->out) 0 -.nodeset V(sram[222]->outb) vsp -Xsram[223] sram->in sram[223]->out sram[223]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[223]->out) 0 -.nodeset V(sram[223]->outb) vsp -***** Signal mux_2level_size50[13]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[0] mux_2level_size50[13]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[1] mux_2level_size50[13]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[2] mux_2level_size50[13]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[3] mux_2level_size50[13]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[4] mux_2level_size50[13]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[5] mux_2level_size50[13]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[6] mux_2level_size50[13]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[7] mux_2level_size50[13]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[8] mux_2level_size50[13]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[9] mux_2level_size50[13]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[10] mux_2level_size50[13]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[11] mux_2level_size50[13]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[12] mux_2level_size50[13]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[13] mux_2level_size50[13]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[14] mux_2level_size50[13]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[15] mux_2level_size50[13]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[16] mux_2level_size50[13]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[17] mux_2level_size50[13]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[18] mux_2level_size50[13]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[19] mux_2level_size50[13]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[20] mux_2level_size50[13]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[21] mux_2level_size50[13]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[22] mux_2level_size50[13]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[23] mux_2level_size50[13]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[24] mux_2level_size50[13]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[25] mux_2level_size50[13]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[26] mux_2level_size50[13]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[27] mux_2level_size50[13]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[28] mux_2level_size50[13]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[29] mux_2level_size50[13]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[30] mux_2level_size50[13]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[31] mux_2level_size50[13]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[32] mux_2level_size50[13]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[33] mux_2level_size50[13]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[34] mux_2level_size50[13]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[35] mux_2level_size50[13]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[36] mux_2level_size50[13]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[37] mux_2level_size50[13]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[38] mux_2level_size50[13]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[13]->in[39] mux_2level_size50[13]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[13]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[40] mux_2level_size50[13]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[41] mux_2level_size50[13]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[42] mux_2level_size50[13]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[43] mux_2level_size50[13]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[44] mux_2level_size50[13]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[45] mux_2level_size50[13]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[46] mux_2level_size50[13]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[47] mux_2level_size50[13]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[48] mux_2level_size50[13]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[13]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[13]->in[49] mux_2level_size50[13]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[13] gvdd_mux_2level_size50[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[13]_in[1]_crossbar trig v(mux_2level_size50[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[13]_in[1]_crossbar trig v(mux_2level_size50[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[13]_in[1]_crossbar when v(mux_2level_size50[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[13]_in[1]_crossbar trig v(mux_2level_size50[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[13]_in[1]_crossbar when v(mux_2level_size50[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[13]_in[1]_crossbar trig v(mux_2level_size50[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[13]_leakage_power avg p(Vgvdd_mux_2level_size50[13]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[13]_in[1]_crossbar param='mux_2level_size50[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[13]_dynamic_power avg p(Vgvdd_mux_2level_size50[13]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[13]_energy_per_cycle param='mux_2level_size50[13]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[13]_in[1]_crossbar param='mux_2level_size50[13]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[13]_in[1]_crossbar param='dynamic_power_idle_mux50[13]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[13]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[13]) from='start_rise_idle_mux50[13]_in[1]_crossbar' to='start_rise_idle_mux50[13]_in[1]_crossbar+switch_rise_idle_mux50[13]_in[1]_crossbar' -.meas tran dynamic_fall_idle_mux50[13]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[13]) from='start_fall_idle_mux50[13]_in[1]_crossbar' to='start_fall_idle_mux50[13]_in[1]_crossbar+switch_fall_idle_mux50[13]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_idle_mux50[13]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_idle_mux50[13]_in[1]_crossbar' -Xload_inv[13]_no0 mux_2level_size50[13]->out mux_2level_size50[13]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to13] -+ param='sum_leakage_power_pb_mux[0to12]+leakage_idle_mux50[13]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to13] -+ param='sum_energy_per_cycle_pb_mux[0to12]+energy_per_cycle_idle_mux50[13]_in[1]_crossbar' -Xmux_2level_size50[14] mux_2level_size50[14]->in[0] mux_2level_size50[14]->in[1] mux_2level_size50[14]->in[2] mux_2level_size50[14]->in[3] mux_2level_size50[14]->in[4] mux_2level_size50[14]->in[5] mux_2level_size50[14]->in[6] mux_2level_size50[14]->in[7] mux_2level_size50[14]->in[8] mux_2level_size50[14]->in[9] mux_2level_size50[14]->in[10] mux_2level_size50[14]->in[11] mux_2level_size50[14]->in[12] mux_2level_size50[14]->in[13] mux_2level_size50[14]->in[14] mux_2level_size50[14]->in[15] mux_2level_size50[14]->in[16] mux_2level_size50[14]->in[17] mux_2level_size50[14]->in[18] mux_2level_size50[14]->in[19] mux_2level_size50[14]->in[20] mux_2level_size50[14]->in[21] mux_2level_size50[14]->in[22] mux_2level_size50[14]->in[23] mux_2level_size50[14]->in[24] mux_2level_size50[14]->in[25] mux_2level_size50[14]->in[26] mux_2level_size50[14]->in[27] mux_2level_size50[14]->in[28] mux_2level_size50[14]->in[29] mux_2level_size50[14]->in[30] mux_2level_size50[14]->in[31] mux_2level_size50[14]->in[32] mux_2level_size50[14]->in[33] mux_2level_size50[14]->in[34] mux_2level_size50[14]->in[35] mux_2level_size50[14]->in[36] mux_2level_size50[14]->in[37] mux_2level_size50[14]->in[38] mux_2level_size50[14]->in[39] mux_2level_size50[14]->in[40] mux_2level_size50[14]->in[41] mux_2level_size50[14]->in[42] mux_2level_size50[14]->in[43] mux_2level_size50[14]->in[44] mux_2level_size50[14]->in[45] mux_2level_size50[14]->in[46] mux_2level_size50[14]->in[47] mux_2level_size50[14]->in[48] mux_2level_size50[14]->in[49] mux_2level_size50[14]->out sram[224]->outb sram[224]->out sram[225]->out sram[225]->outb sram[226]->out sram[226]->outb sram[227]->out sram[227]->outb sram[228]->out sram[228]->outb sram[229]->out sram[229]->outb sram[230]->out sram[230]->outb sram[231]->out sram[231]->outb sram[232]->outb sram[232]->out sram[233]->out sram[233]->outb sram[234]->out sram[234]->outb sram[235]->out sram[235]->outb sram[236]->out sram[236]->outb sram[237]->out sram[237]->outb sram[238]->out sram[238]->outb sram[239]->out sram[239]->outb gvdd_mux_2level_size50[14] 0 mux_2level_size50 -***** SRAM bits for MUX[14], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[224] sram->in sram[224]->out sram[224]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[224]->out) 0 -.nodeset V(sram[224]->outb) vsp -Xsram[225] sram->in sram[225]->out sram[225]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[225]->out) 0 -.nodeset V(sram[225]->outb) vsp -Xsram[226] sram->in sram[226]->out sram[226]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[226]->out) 0 -.nodeset V(sram[226]->outb) vsp -Xsram[227] sram->in sram[227]->out sram[227]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[227]->out) 0 -.nodeset V(sram[227]->outb) vsp -Xsram[228] sram->in sram[228]->out sram[228]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[228]->out) 0 -.nodeset V(sram[228]->outb) vsp -Xsram[229] sram->in sram[229]->out sram[229]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[229]->out) 0 -.nodeset V(sram[229]->outb) vsp -Xsram[230] sram->in sram[230]->out sram[230]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[230]->out) 0 -.nodeset V(sram[230]->outb) vsp -Xsram[231] sram->in sram[231]->out sram[231]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[231]->out) 0 -.nodeset V(sram[231]->outb) vsp -Xsram[232] sram->in sram[232]->out sram[232]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[232]->out) 0 -.nodeset V(sram[232]->outb) vsp -Xsram[233] sram->in sram[233]->out sram[233]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[233]->out) 0 -.nodeset V(sram[233]->outb) vsp -Xsram[234] sram->in sram[234]->out sram[234]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[234]->out) 0 -.nodeset V(sram[234]->outb) vsp -Xsram[235] sram->in sram[235]->out sram[235]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[235]->out) 0 -.nodeset V(sram[235]->outb) vsp -Xsram[236] sram->in sram[236]->out sram[236]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[236]->out) 0 -.nodeset V(sram[236]->outb) vsp -Xsram[237] sram->in sram[237]->out sram[237]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[237]->out) 0 -.nodeset V(sram[237]->outb) vsp -Xsram[238] sram->in sram[238]->out sram[238]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[238]->out) 0 -.nodeset V(sram[238]->outb) vsp -Xsram[239] sram->in sram[239]->out sram[239]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[239]->out) 0 -.nodeset V(sram[239]->outb) vsp -***** Signal mux_2level_size50[14]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[0] mux_2level_size50[14]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[1] mux_2level_size50[14]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[2] mux_2level_size50[14]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[3] mux_2level_size50[14]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[4] mux_2level_size50[14]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[5] mux_2level_size50[14]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[6] mux_2level_size50[14]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[7] mux_2level_size50[14]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[8] mux_2level_size50[14]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[9] mux_2level_size50[14]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[10] mux_2level_size50[14]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[11] mux_2level_size50[14]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[12] mux_2level_size50[14]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[13] mux_2level_size50[14]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[14] mux_2level_size50[14]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[15] mux_2level_size50[14]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[16] mux_2level_size50[14]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[17] mux_2level_size50[14]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[18] mux_2level_size50[14]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[19] mux_2level_size50[14]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[20] mux_2level_size50[14]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[21] mux_2level_size50[14]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[22] mux_2level_size50[14]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[23] mux_2level_size50[14]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[24] mux_2level_size50[14]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[25] mux_2level_size50[14]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[26] mux_2level_size50[14]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[27] mux_2level_size50[14]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[28] mux_2level_size50[14]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[29] mux_2level_size50[14]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[30] mux_2level_size50[14]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[31] mux_2level_size50[14]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[32] mux_2level_size50[14]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[33] mux_2level_size50[14]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[34] mux_2level_size50[14]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[35] mux_2level_size50[14]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[36] mux_2level_size50[14]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[37] mux_2level_size50[14]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[38] mux_2level_size50[14]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[14]->in[39] mux_2level_size50[14]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[14]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[40] mux_2level_size50[14]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[41] mux_2level_size50[14]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[42] mux_2level_size50[14]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[43] mux_2level_size50[14]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[44] mux_2level_size50[14]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[45] mux_2level_size50[14]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[46] mux_2level_size50[14]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[47] mux_2level_size50[14]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[48] mux_2level_size50[14]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[14]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[14]->in[49] mux_2level_size50[14]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[14] gvdd_mux_2level_size50[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[14]_in[2]_crossbar trig v(mux_2level_size50[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[14]_in[2]_crossbar trig v(mux_2level_size50[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[14]_in[2]_crossbar when v(mux_2level_size50[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[14]_in[2]_crossbar trig v(mux_2level_size50[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[14]_in[2]_crossbar when v(mux_2level_size50[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[14]_in[2]_crossbar trig v(mux_2level_size50[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[14]_leakage_power avg p(Vgvdd_mux_2level_size50[14]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[14]_in[2]_crossbar param='mux_2level_size50[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[14]_dynamic_power avg p(Vgvdd_mux_2level_size50[14]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[14]_energy_per_cycle param='mux_2level_size50[14]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[14]_in[2]_crossbar param='mux_2level_size50[14]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[14]_in[2]_crossbar param='dynamic_power_idle_mux50[14]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[14]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[14]) from='start_rise_idle_mux50[14]_in[2]_crossbar' to='start_rise_idle_mux50[14]_in[2]_crossbar+switch_rise_idle_mux50[14]_in[2]_crossbar' -.meas tran dynamic_fall_idle_mux50[14]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[14]) from='start_fall_idle_mux50[14]_in[2]_crossbar' to='start_fall_idle_mux50[14]_in[2]_crossbar+switch_fall_idle_mux50[14]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_idle_mux50[14]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_idle_mux50[14]_in[2]_crossbar' -Xload_inv[14]_no0 mux_2level_size50[14]->out mux_2level_size50[14]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to14] -+ param='sum_leakage_power_pb_mux[0to13]+leakage_idle_mux50[14]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to14] -+ param='sum_energy_per_cycle_pb_mux[0to13]+energy_per_cycle_idle_mux50[14]_in[2]_crossbar' -Xmux_2level_size50[15] mux_2level_size50[15]->in[0] mux_2level_size50[15]->in[1] mux_2level_size50[15]->in[2] mux_2level_size50[15]->in[3] mux_2level_size50[15]->in[4] mux_2level_size50[15]->in[5] mux_2level_size50[15]->in[6] mux_2level_size50[15]->in[7] mux_2level_size50[15]->in[8] mux_2level_size50[15]->in[9] mux_2level_size50[15]->in[10] mux_2level_size50[15]->in[11] mux_2level_size50[15]->in[12] mux_2level_size50[15]->in[13] mux_2level_size50[15]->in[14] mux_2level_size50[15]->in[15] mux_2level_size50[15]->in[16] mux_2level_size50[15]->in[17] mux_2level_size50[15]->in[18] mux_2level_size50[15]->in[19] mux_2level_size50[15]->in[20] mux_2level_size50[15]->in[21] mux_2level_size50[15]->in[22] mux_2level_size50[15]->in[23] mux_2level_size50[15]->in[24] mux_2level_size50[15]->in[25] mux_2level_size50[15]->in[26] mux_2level_size50[15]->in[27] mux_2level_size50[15]->in[28] mux_2level_size50[15]->in[29] mux_2level_size50[15]->in[30] mux_2level_size50[15]->in[31] mux_2level_size50[15]->in[32] mux_2level_size50[15]->in[33] mux_2level_size50[15]->in[34] mux_2level_size50[15]->in[35] mux_2level_size50[15]->in[36] mux_2level_size50[15]->in[37] mux_2level_size50[15]->in[38] mux_2level_size50[15]->in[39] mux_2level_size50[15]->in[40] mux_2level_size50[15]->in[41] mux_2level_size50[15]->in[42] mux_2level_size50[15]->in[43] mux_2level_size50[15]->in[44] mux_2level_size50[15]->in[45] mux_2level_size50[15]->in[46] mux_2level_size50[15]->in[47] mux_2level_size50[15]->in[48] mux_2level_size50[15]->in[49] mux_2level_size50[15]->out sram[240]->outb sram[240]->out sram[241]->out sram[241]->outb sram[242]->out sram[242]->outb sram[243]->out sram[243]->outb sram[244]->out sram[244]->outb sram[245]->out sram[245]->outb sram[246]->out sram[246]->outb sram[247]->out sram[247]->outb sram[248]->outb sram[248]->out sram[249]->out sram[249]->outb sram[250]->out sram[250]->outb sram[251]->out sram[251]->outb sram[252]->out sram[252]->outb sram[253]->out sram[253]->outb sram[254]->out sram[254]->outb sram[255]->out sram[255]->outb gvdd_mux_2level_size50[15] 0 mux_2level_size50 -***** SRAM bits for MUX[15], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[240] sram->in sram[240]->out sram[240]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[240]->out) 0 -.nodeset V(sram[240]->outb) vsp -Xsram[241] sram->in sram[241]->out sram[241]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[241]->out) 0 -.nodeset V(sram[241]->outb) vsp -Xsram[242] sram->in sram[242]->out sram[242]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[242]->out) 0 -.nodeset V(sram[242]->outb) vsp -Xsram[243] sram->in sram[243]->out sram[243]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[243]->out) 0 -.nodeset V(sram[243]->outb) vsp -Xsram[244] sram->in sram[244]->out sram[244]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[244]->out) 0 -.nodeset V(sram[244]->outb) vsp -Xsram[245] sram->in sram[245]->out sram[245]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[245]->out) 0 -.nodeset V(sram[245]->outb) vsp -Xsram[246] sram->in sram[246]->out sram[246]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[246]->out) 0 -.nodeset V(sram[246]->outb) vsp -Xsram[247] sram->in sram[247]->out sram[247]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[247]->out) 0 -.nodeset V(sram[247]->outb) vsp -Xsram[248] sram->in sram[248]->out sram[248]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[248]->out) 0 -.nodeset V(sram[248]->outb) vsp -Xsram[249] sram->in sram[249]->out sram[249]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[249]->out) 0 -.nodeset V(sram[249]->outb) vsp -Xsram[250] sram->in sram[250]->out sram[250]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[250]->out) 0 -.nodeset V(sram[250]->outb) vsp -Xsram[251] sram->in sram[251]->out sram[251]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[251]->out) 0 -.nodeset V(sram[251]->outb) vsp -Xsram[252] sram->in sram[252]->out sram[252]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[252]->out) 0 -.nodeset V(sram[252]->outb) vsp -Xsram[253] sram->in sram[253]->out sram[253]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[253]->out) 0 -.nodeset V(sram[253]->outb) vsp -Xsram[254] sram->in sram[254]->out sram[254]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[254]->out) 0 -.nodeset V(sram[254]->outb) vsp -Xsram[255] sram->in sram[255]->out sram[255]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[255]->out) 0 -.nodeset V(sram[255]->outb) vsp -***** Signal mux_2level_size50[15]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[0] mux_2level_size50[15]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[1] mux_2level_size50[15]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[2] mux_2level_size50[15]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[3] mux_2level_size50[15]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[4] mux_2level_size50[15]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[5] mux_2level_size50[15]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[6] mux_2level_size50[15]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[7] mux_2level_size50[15]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[8] mux_2level_size50[15]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[9] mux_2level_size50[15]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[10] mux_2level_size50[15]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[11] mux_2level_size50[15]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[12] mux_2level_size50[15]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[13] mux_2level_size50[15]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[14] mux_2level_size50[15]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[15] mux_2level_size50[15]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[16] mux_2level_size50[15]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[17] mux_2level_size50[15]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[18] mux_2level_size50[15]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[19] mux_2level_size50[15]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[20] mux_2level_size50[15]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[21] mux_2level_size50[15]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[22] mux_2level_size50[15]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[23] mux_2level_size50[15]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[24] mux_2level_size50[15]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[25] mux_2level_size50[15]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[26] mux_2level_size50[15]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[27] mux_2level_size50[15]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[28] mux_2level_size50[15]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[29] mux_2level_size50[15]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[30] mux_2level_size50[15]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[31] mux_2level_size50[15]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[32] mux_2level_size50[15]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[33] mux_2level_size50[15]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[34] mux_2level_size50[15]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[35] mux_2level_size50[15]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[36] mux_2level_size50[15]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[37] mux_2level_size50[15]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[38] mux_2level_size50[15]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[15]->in[39] mux_2level_size50[15]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[15]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[40] mux_2level_size50[15]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[41] mux_2level_size50[15]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[42] mux_2level_size50[15]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[43] mux_2level_size50[15]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[44] mux_2level_size50[15]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[45] mux_2level_size50[15]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[46] mux_2level_size50[15]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[47] mux_2level_size50[15]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[48] mux_2level_size50[15]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[15]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[15]->in[49] mux_2level_size50[15]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[15] gvdd_mux_2level_size50[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[15]_in[3]_crossbar trig v(mux_2level_size50[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[15]_in[3]_crossbar trig v(mux_2level_size50[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[15]_in[3]_crossbar when v(mux_2level_size50[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[15]_in[3]_crossbar trig v(mux_2level_size50[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[15]_in[3]_crossbar when v(mux_2level_size50[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[15]_in[3]_crossbar trig v(mux_2level_size50[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[15]_leakage_power avg p(Vgvdd_mux_2level_size50[15]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[15]_in[3]_crossbar param='mux_2level_size50[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[15]_dynamic_power avg p(Vgvdd_mux_2level_size50[15]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[15]_energy_per_cycle param='mux_2level_size50[15]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[15]_in[3]_crossbar param='mux_2level_size50[15]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[15]_in[3]_crossbar param='dynamic_power_idle_mux50[15]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[15]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[15]) from='start_rise_idle_mux50[15]_in[3]_crossbar' to='start_rise_idle_mux50[15]_in[3]_crossbar+switch_rise_idle_mux50[15]_in[3]_crossbar' -.meas tran dynamic_fall_idle_mux50[15]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[15]) from='start_fall_idle_mux50[15]_in[3]_crossbar' to='start_fall_idle_mux50[15]_in[3]_crossbar+switch_fall_idle_mux50[15]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_idle_mux50[15]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_idle_mux50[15]_in[3]_crossbar' -Xload_inv[15]_no0 mux_2level_size50[15]->out mux_2level_size50[15]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to15] -+ param='sum_leakage_power_pb_mux[0to14]+leakage_idle_mux50[15]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to15] -+ param='sum_energy_per_cycle_pb_mux[0to14]+energy_per_cycle_idle_mux50[15]_in[3]_crossbar' -Xmux_2level_size50[16] mux_2level_size50[16]->in[0] mux_2level_size50[16]->in[1] mux_2level_size50[16]->in[2] mux_2level_size50[16]->in[3] mux_2level_size50[16]->in[4] mux_2level_size50[16]->in[5] mux_2level_size50[16]->in[6] mux_2level_size50[16]->in[7] mux_2level_size50[16]->in[8] mux_2level_size50[16]->in[9] mux_2level_size50[16]->in[10] mux_2level_size50[16]->in[11] mux_2level_size50[16]->in[12] mux_2level_size50[16]->in[13] mux_2level_size50[16]->in[14] mux_2level_size50[16]->in[15] mux_2level_size50[16]->in[16] mux_2level_size50[16]->in[17] mux_2level_size50[16]->in[18] mux_2level_size50[16]->in[19] mux_2level_size50[16]->in[20] mux_2level_size50[16]->in[21] mux_2level_size50[16]->in[22] mux_2level_size50[16]->in[23] mux_2level_size50[16]->in[24] mux_2level_size50[16]->in[25] mux_2level_size50[16]->in[26] mux_2level_size50[16]->in[27] mux_2level_size50[16]->in[28] mux_2level_size50[16]->in[29] mux_2level_size50[16]->in[30] mux_2level_size50[16]->in[31] mux_2level_size50[16]->in[32] mux_2level_size50[16]->in[33] mux_2level_size50[16]->in[34] mux_2level_size50[16]->in[35] mux_2level_size50[16]->in[36] mux_2level_size50[16]->in[37] mux_2level_size50[16]->in[38] mux_2level_size50[16]->in[39] mux_2level_size50[16]->in[40] mux_2level_size50[16]->in[41] mux_2level_size50[16]->in[42] mux_2level_size50[16]->in[43] mux_2level_size50[16]->in[44] mux_2level_size50[16]->in[45] mux_2level_size50[16]->in[46] mux_2level_size50[16]->in[47] mux_2level_size50[16]->in[48] mux_2level_size50[16]->in[49] mux_2level_size50[16]->out sram[256]->outb sram[256]->out sram[257]->out sram[257]->outb sram[258]->out sram[258]->outb sram[259]->out sram[259]->outb sram[260]->out sram[260]->outb sram[261]->out sram[261]->outb sram[262]->out sram[262]->outb sram[263]->out sram[263]->outb sram[264]->outb sram[264]->out sram[265]->out sram[265]->outb sram[266]->out sram[266]->outb sram[267]->out sram[267]->outb sram[268]->out sram[268]->outb sram[269]->out sram[269]->outb sram[270]->out sram[270]->outb sram[271]->out sram[271]->outb gvdd_mux_2level_size50[16] 0 mux_2level_size50 -***** SRAM bits for MUX[16], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[256] sram->in sram[256]->out sram[256]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[256]->out) 0 -.nodeset V(sram[256]->outb) vsp -Xsram[257] sram->in sram[257]->out sram[257]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[257]->out) 0 -.nodeset V(sram[257]->outb) vsp -Xsram[258] sram->in sram[258]->out sram[258]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[258]->out) 0 -.nodeset V(sram[258]->outb) vsp -Xsram[259] sram->in sram[259]->out sram[259]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[259]->out) 0 -.nodeset V(sram[259]->outb) vsp -Xsram[260] sram->in sram[260]->out sram[260]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[260]->out) 0 -.nodeset V(sram[260]->outb) vsp -Xsram[261] sram->in sram[261]->out sram[261]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[261]->out) 0 -.nodeset V(sram[261]->outb) vsp -Xsram[262] sram->in sram[262]->out sram[262]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[262]->out) 0 -.nodeset V(sram[262]->outb) vsp -Xsram[263] sram->in sram[263]->out sram[263]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[263]->out) 0 -.nodeset V(sram[263]->outb) vsp -Xsram[264] sram->in sram[264]->out sram[264]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[264]->out) 0 -.nodeset V(sram[264]->outb) vsp -Xsram[265] sram->in sram[265]->out sram[265]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[265]->out) 0 -.nodeset V(sram[265]->outb) vsp -Xsram[266] sram->in sram[266]->out sram[266]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[266]->out) 0 -.nodeset V(sram[266]->outb) vsp -Xsram[267] sram->in sram[267]->out sram[267]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[267]->out) 0 -.nodeset V(sram[267]->outb) vsp -Xsram[268] sram->in sram[268]->out sram[268]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[268]->out) 0 -.nodeset V(sram[268]->outb) vsp -Xsram[269] sram->in sram[269]->out sram[269]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[269]->out) 0 -.nodeset V(sram[269]->outb) vsp -Xsram[270] sram->in sram[270]->out sram[270]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[270]->out) 0 -.nodeset V(sram[270]->outb) vsp -Xsram[271] sram->in sram[271]->out sram[271]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[271]->out) 0 -.nodeset V(sram[271]->outb) vsp -***** Signal mux_2level_size50[16]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[0] mux_2level_size50[16]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[1] mux_2level_size50[16]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[2] mux_2level_size50[16]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[3] mux_2level_size50[16]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[4] mux_2level_size50[16]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[5] mux_2level_size50[16]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[6] mux_2level_size50[16]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[7] mux_2level_size50[16]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[8] mux_2level_size50[16]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[9] mux_2level_size50[16]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[10] mux_2level_size50[16]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[11] mux_2level_size50[16]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[12] mux_2level_size50[16]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[13] mux_2level_size50[16]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[14] mux_2level_size50[16]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[15] mux_2level_size50[16]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[16] mux_2level_size50[16]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[17] mux_2level_size50[16]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[18] mux_2level_size50[16]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[19] mux_2level_size50[16]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[20] mux_2level_size50[16]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[21] mux_2level_size50[16]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[22] mux_2level_size50[16]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[23] mux_2level_size50[16]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[24] mux_2level_size50[16]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[25] mux_2level_size50[16]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[26] mux_2level_size50[16]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[27] mux_2level_size50[16]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[28] mux_2level_size50[16]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[29] mux_2level_size50[16]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[30] mux_2level_size50[16]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[31] mux_2level_size50[16]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[32] mux_2level_size50[16]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[33] mux_2level_size50[16]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[34] mux_2level_size50[16]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[35] mux_2level_size50[16]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[36] mux_2level_size50[16]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[37] mux_2level_size50[16]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[38] mux_2level_size50[16]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[16]->in[39] mux_2level_size50[16]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[16]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[40] mux_2level_size50[16]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[41] mux_2level_size50[16]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[42] mux_2level_size50[16]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[43] mux_2level_size50[16]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[44] mux_2level_size50[16]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[45] mux_2level_size50[16]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[46] mux_2level_size50[16]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[47] mux_2level_size50[16]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[48] mux_2level_size50[16]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[16]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[16]->in[49] mux_2level_size50[16]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[16] gvdd_mux_2level_size50[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[16]_in[4]_crossbar trig v(mux_2level_size50[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[16]_in[4]_crossbar trig v(mux_2level_size50[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[16]_in[4]_crossbar when v(mux_2level_size50[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[16]_in[4]_crossbar trig v(mux_2level_size50[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[16]_in[4]_crossbar when v(mux_2level_size50[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[16]_in[4]_crossbar trig v(mux_2level_size50[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[16]_leakage_power avg p(Vgvdd_mux_2level_size50[16]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[16]_in[4]_crossbar param='mux_2level_size50[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[16]_dynamic_power avg p(Vgvdd_mux_2level_size50[16]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[16]_energy_per_cycle param='mux_2level_size50[16]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[16]_in[4]_crossbar param='mux_2level_size50[16]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[16]_in[4]_crossbar param='dynamic_power_idle_mux50[16]_in[4]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[16]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[16]) from='start_rise_idle_mux50[16]_in[4]_crossbar' to='start_rise_idle_mux50[16]_in[4]_crossbar+switch_rise_idle_mux50[16]_in[4]_crossbar' -.meas tran dynamic_fall_idle_mux50[16]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[16]) from='start_fall_idle_mux50[16]_in[4]_crossbar' to='start_fall_idle_mux50[16]_in[4]_crossbar+switch_fall_idle_mux50[16]_in[4]_crossbar' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_idle_mux50[16]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_idle_mux50[16]_in[4]_crossbar' -Xload_inv[16]_no0 mux_2level_size50[16]->out mux_2level_size50[16]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to16] -+ param='sum_leakage_power_pb_mux[0to15]+leakage_idle_mux50[16]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to16] -+ param='sum_energy_per_cycle_pb_mux[0to15]+energy_per_cycle_idle_mux50[16]_in[4]_crossbar' -Xmux_2level_size50[17] mux_2level_size50[17]->in[0] mux_2level_size50[17]->in[1] mux_2level_size50[17]->in[2] mux_2level_size50[17]->in[3] mux_2level_size50[17]->in[4] mux_2level_size50[17]->in[5] mux_2level_size50[17]->in[6] mux_2level_size50[17]->in[7] mux_2level_size50[17]->in[8] mux_2level_size50[17]->in[9] mux_2level_size50[17]->in[10] mux_2level_size50[17]->in[11] mux_2level_size50[17]->in[12] mux_2level_size50[17]->in[13] mux_2level_size50[17]->in[14] mux_2level_size50[17]->in[15] mux_2level_size50[17]->in[16] mux_2level_size50[17]->in[17] mux_2level_size50[17]->in[18] mux_2level_size50[17]->in[19] mux_2level_size50[17]->in[20] mux_2level_size50[17]->in[21] mux_2level_size50[17]->in[22] mux_2level_size50[17]->in[23] mux_2level_size50[17]->in[24] mux_2level_size50[17]->in[25] mux_2level_size50[17]->in[26] mux_2level_size50[17]->in[27] mux_2level_size50[17]->in[28] mux_2level_size50[17]->in[29] mux_2level_size50[17]->in[30] mux_2level_size50[17]->in[31] mux_2level_size50[17]->in[32] mux_2level_size50[17]->in[33] mux_2level_size50[17]->in[34] mux_2level_size50[17]->in[35] mux_2level_size50[17]->in[36] mux_2level_size50[17]->in[37] mux_2level_size50[17]->in[38] mux_2level_size50[17]->in[39] mux_2level_size50[17]->in[40] mux_2level_size50[17]->in[41] mux_2level_size50[17]->in[42] mux_2level_size50[17]->in[43] mux_2level_size50[17]->in[44] mux_2level_size50[17]->in[45] mux_2level_size50[17]->in[46] mux_2level_size50[17]->in[47] mux_2level_size50[17]->in[48] mux_2level_size50[17]->in[49] mux_2level_size50[17]->out sram[272]->outb sram[272]->out sram[273]->out sram[273]->outb sram[274]->out sram[274]->outb sram[275]->out sram[275]->outb sram[276]->out sram[276]->outb sram[277]->out sram[277]->outb sram[278]->out sram[278]->outb sram[279]->out sram[279]->outb sram[280]->outb sram[280]->out sram[281]->out sram[281]->outb sram[282]->out sram[282]->outb sram[283]->out sram[283]->outb sram[284]->out sram[284]->outb sram[285]->out sram[285]->outb sram[286]->out sram[286]->outb sram[287]->out sram[287]->outb gvdd_mux_2level_size50[17] 0 mux_2level_size50 -***** SRAM bits for MUX[17], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[272] sram->in sram[272]->out sram[272]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[272]->out) 0 -.nodeset V(sram[272]->outb) vsp -Xsram[273] sram->in sram[273]->out sram[273]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[273]->out) 0 -.nodeset V(sram[273]->outb) vsp -Xsram[274] sram->in sram[274]->out sram[274]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[274]->out) 0 -.nodeset V(sram[274]->outb) vsp -Xsram[275] sram->in sram[275]->out sram[275]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[275]->out) 0 -.nodeset V(sram[275]->outb) vsp -Xsram[276] sram->in sram[276]->out sram[276]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[276]->out) 0 -.nodeset V(sram[276]->outb) vsp -Xsram[277] sram->in sram[277]->out sram[277]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[277]->out) 0 -.nodeset V(sram[277]->outb) vsp -Xsram[278] sram->in sram[278]->out sram[278]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[278]->out) 0 -.nodeset V(sram[278]->outb) vsp -Xsram[279] sram->in sram[279]->out sram[279]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[279]->out) 0 -.nodeset V(sram[279]->outb) vsp -Xsram[280] sram->in sram[280]->out sram[280]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[280]->out) 0 -.nodeset V(sram[280]->outb) vsp -Xsram[281] sram->in sram[281]->out sram[281]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[281]->out) 0 -.nodeset V(sram[281]->outb) vsp -Xsram[282] sram->in sram[282]->out sram[282]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[282]->out) 0 -.nodeset V(sram[282]->outb) vsp -Xsram[283] sram->in sram[283]->out sram[283]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[283]->out) 0 -.nodeset V(sram[283]->outb) vsp -Xsram[284] sram->in sram[284]->out sram[284]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[284]->out) 0 -.nodeset V(sram[284]->outb) vsp -Xsram[285] sram->in sram[285]->out sram[285]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[285]->out) 0 -.nodeset V(sram[285]->outb) vsp -Xsram[286] sram->in sram[286]->out sram[286]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[286]->out) 0 -.nodeset V(sram[286]->outb) vsp -Xsram[287] sram->in sram[287]->out sram[287]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[287]->out) 0 -.nodeset V(sram[287]->outb) vsp -***** Signal mux_2level_size50[17]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[0] mux_2level_size50[17]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[1] mux_2level_size50[17]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[2] mux_2level_size50[17]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[3] mux_2level_size50[17]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[4] mux_2level_size50[17]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[5] mux_2level_size50[17]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[6] mux_2level_size50[17]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[7] mux_2level_size50[17]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[8] mux_2level_size50[17]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[9] mux_2level_size50[17]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[10] mux_2level_size50[17]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[11] mux_2level_size50[17]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[12] mux_2level_size50[17]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[13] mux_2level_size50[17]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[14] mux_2level_size50[17]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[15] mux_2level_size50[17]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[16] mux_2level_size50[17]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[17] mux_2level_size50[17]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[18] mux_2level_size50[17]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[19] mux_2level_size50[17]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[20] mux_2level_size50[17]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[21] mux_2level_size50[17]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[22] mux_2level_size50[17]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[23] mux_2level_size50[17]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[24] mux_2level_size50[17]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[25] mux_2level_size50[17]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[26] mux_2level_size50[17]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[27] mux_2level_size50[17]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[28] mux_2level_size50[17]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[29] mux_2level_size50[17]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[30] mux_2level_size50[17]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[31] mux_2level_size50[17]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[32] mux_2level_size50[17]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[33] mux_2level_size50[17]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[34] mux_2level_size50[17]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[35] mux_2level_size50[17]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[36] mux_2level_size50[17]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[37] mux_2level_size50[17]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[38] mux_2level_size50[17]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[17]->in[39] mux_2level_size50[17]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[17]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[40] mux_2level_size50[17]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[41] mux_2level_size50[17]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[42] mux_2level_size50[17]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[43] mux_2level_size50[17]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[44] mux_2level_size50[17]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[45] mux_2level_size50[17]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[46] mux_2level_size50[17]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[47] mux_2level_size50[17]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[48] mux_2level_size50[17]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[17]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[17]->in[49] mux_2level_size50[17]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[17] gvdd_mux_2level_size50[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[17]_in[5]_crossbar trig v(mux_2level_size50[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[17]_in[5]_crossbar trig v(mux_2level_size50[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[17]_in[5]_crossbar when v(mux_2level_size50[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[17]_in[5]_crossbar trig v(mux_2level_size50[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[17]_in[5]_crossbar when v(mux_2level_size50[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[17]_in[5]_crossbar trig v(mux_2level_size50[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[17]_leakage_power avg p(Vgvdd_mux_2level_size50[17]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[17]_in[5]_crossbar param='mux_2level_size50[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[17]_dynamic_power avg p(Vgvdd_mux_2level_size50[17]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[17]_energy_per_cycle param='mux_2level_size50[17]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[17]_in[5]_crossbar param='mux_2level_size50[17]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[17]_in[5]_crossbar param='dynamic_power_idle_mux50[17]_in[5]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[17]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[17]) from='start_rise_idle_mux50[17]_in[5]_crossbar' to='start_rise_idle_mux50[17]_in[5]_crossbar+switch_rise_idle_mux50[17]_in[5]_crossbar' -.meas tran dynamic_fall_idle_mux50[17]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[17]) from='start_fall_idle_mux50[17]_in[5]_crossbar' to='start_fall_idle_mux50[17]_in[5]_crossbar+switch_fall_idle_mux50[17]_in[5]_crossbar' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_idle_mux50[17]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_idle_mux50[17]_in[5]_crossbar' -Xload_inv[17]_no0 mux_2level_size50[17]->out mux_2level_size50[17]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to17] -+ param='sum_leakage_power_pb_mux[0to16]+leakage_idle_mux50[17]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to17] -+ param='sum_energy_per_cycle_pb_mux[0to16]+energy_per_cycle_idle_mux50[17]_in[5]_crossbar' -Xmux_2level_size50[18] mux_2level_size50[18]->in[0] mux_2level_size50[18]->in[1] mux_2level_size50[18]->in[2] mux_2level_size50[18]->in[3] mux_2level_size50[18]->in[4] mux_2level_size50[18]->in[5] mux_2level_size50[18]->in[6] mux_2level_size50[18]->in[7] mux_2level_size50[18]->in[8] mux_2level_size50[18]->in[9] mux_2level_size50[18]->in[10] mux_2level_size50[18]->in[11] mux_2level_size50[18]->in[12] mux_2level_size50[18]->in[13] mux_2level_size50[18]->in[14] mux_2level_size50[18]->in[15] mux_2level_size50[18]->in[16] mux_2level_size50[18]->in[17] mux_2level_size50[18]->in[18] mux_2level_size50[18]->in[19] mux_2level_size50[18]->in[20] mux_2level_size50[18]->in[21] mux_2level_size50[18]->in[22] mux_2level_size50[18]->in[23] mux_2level_size50[18]->in[24] mux_2level_size50[18]->in[25] mux_2level_size50[18]->in[26] mux_2level_size50[18]->in[27] mux_2level_size50[18]->in[28] mux_2level_size50[18]->in[29] mux_2level_size50[18]->in[30] mux_2level_size50[18]->in[31] mux_2level_size50[18]->in[32] mux_2level_size50[18]->in[33] mux_2level_size50[18]->in[34] mux_2level_size50[18]->in[35] mux_2level_size50[18]->in[36] mux_2level_size50[18]->in[37] mux_2level_size50[18]->in[38] mux_2level_size50[18]->in[39] mux_2level_size50[18]->in[40] mux_2level_size50[18]->in[41] mux_2level_size50[18]->in[42] mux_2level_size50[18]->in[43] mux_2level_size50[18]->in[44] mux_2level_size50[18]->in[45] mux_2level_size50[18]->in[46] mux_2level_size50[18]->in[47] mux_2level_size50[18]->in[48] mux_2level_size50[18]->in[49] mux_2level_size50[18]->out sram[288]->outb sram[288]->out sram[289]->out sram[289]->outb sram[290]->out sram[290]->outb sram[291]->out sram[291]->outb sram[292]->out sram[292]->outb sram[293]->out sram[293]->outb sram[294]->out sram[294]->outb sram[295]->out sram[295]->outb sram[296]->outb sram[296]->out sram[297]->out sram[297]->outb sram[298]->out sram[298]->outb sram[299]->out sram[299]->outb sram[300]->out sram[300]->outb sram[301]->out sram[301]->outb sram[302]->out sram[302]->outb sram[303]->out sram[303]->outb gvdd_mux_2level_size50[18] 0 mux_2level_size50 -***** SRAM bits for MUX[18], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[288] sram->in sram[288]->out sram[288]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[288]->out) 0 -.nodeset V(sram[288]->outb) vsp -Xsram[289] sram->in sram[289]->out sram[289]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[289]->out) 0 -.nodeset V(sram[289]->outb) vsp -Xsram[290] sram->in sram[290]->out sram[290]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[290]->out) 0 -.nodeset V(sram[290]->outb) vsp -Xsram[291] sram->in sram[291]->out sram[291]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[291]->out) 0 -.nodeset V(sram[291]->outb) vsp -Xsram[292] sram->in sram[292]->out sram[292]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[292]->out) 0 -.nodeset V(sram[292]->outb) vsp -Xsram[293] sram->in sram[293]->out sram[293]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[293]->out) 0 -.nodeset V(sram[293]->outb) vsp -Xsram[294] sram->in sram[294]->out sram[294]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[294]->out) 0 -.nodeset V(sram[294]->outb) vsp -Xsram[295] sram->in sram[295]->out sram[295]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[295]->out) 0 -.nodeset V(sram[295]->outb) vsp -Xsram[296] sram->in sram[296]->out sram[296]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[296]->out) 0 -.nodeset V(sram[296]->outb) vsp -Xsram[297] sram->in sram[297]->out sram[297]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[297]->out) 0 -.nodeset V(sram[297]->outb) vsp -Xsram[298] sram->in sram[298]->out sram[298]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[298]->out) 0 -.nodeset V(sram[298]->outb) vsp -Xsram[299] sram->in sram[299]->out sram[299]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[299]->out) 0 -.nodeset V(sram[299]->outb) vsp -Xsram[300] sram->in sram[300]->out sram[300]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[300]->out) 0 -.nodeset V(sram[300]->outb) vsp -Xsram[301] sram->in sram[301]->out sram[301]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[301]->out) 0 -.nodeset V(sram[301]->outb) vsp -Xsram[302] sram->in sram[302]->out sram[302]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[302]->out) 0 -.nodeset V(sram[302]->outb) vsp -Xsram[303] sram->in sram[303]->out sram[303]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[303]->out) 0 -.nodeset V(sram[303]->outb) vsp -***** Signal mux_2level_size50[18]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[0] mux_2level_size50[18]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[1] mux_2level_size50[18]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[2] mux_2level_size50[18]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[3] mux_2level_size50[18]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[4] mux_2level_size50[18]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[5] mux_2level_size50[18]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[6] mux_2level_size50[18]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[7] mux_2level_size50[18]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[8] mux_2level_size50[18]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[9] mux_2level_size50[18]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[10] mux_2level_size50[18]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[11] mux_2level_size50[18]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[12] mux_2level_size50[18]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[13] mux_2level_size50[18]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[14] mux_2level_size50[18]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[15] mux_2level_size50[18]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[16] mux_2level_size50[18]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[17] mux_2level_size50[18]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[18] mux_2level_size50[18]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[19] mux_2level_size50[18]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[20] mux_2level_size50[18]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[21] mux_2level_size50[18]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[22] mux_2level_size50[18]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[23] mux_2level_size50[18]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[24] mux_2level_size50[18]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[25] mux_2level_size50[18]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[26] mux_2level_size50[18]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[27] mux_2level_size50[18]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[28] mux_2level_size50[18]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[29] mux_2level_size50[18]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[30] mux_2level_size50[18]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[31] mux_2level_size50[18]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[32] mux_2level_size50[18]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[33] mux_2level_size50[18]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[34] mux_2level_size50[18]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[35] mux_2level_size50[18]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[36] mux_2level_size50[18]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[37] mux_2level_size50[18]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[38] mux_2level_size50[18]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[18]->in[39] mux_2level_size50[18]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[18]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[40] mux_2level_size50[18]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[41] mux_2level_size50[18]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[42] mux_2level_size50[18]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[43] mux_2level_size50[18]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[44] mux_2level_size50[18]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[45] mux_2level_size50[18]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[46] mux_2level_size50[18]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[47] mux_2level_size50[18]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[48] mux_2level_size50[18]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[18]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[18]->in[49] mux_2level_size50[18]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[18] gvdd_mux_2level_size50[18] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[18]_in[0]_crossbar trig v(mux_2level_size50[18]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[18]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[18]_in[0]_crossbar trig v(mux_2level_size50[18]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[18]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[18]_in[0]_crossbar when v(mux_2level_size50[18]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[18]_in[0]_crossbar trig v(mux_2level_size50[18]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[18]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[18]_in[0]_crossbar when v(mux_2level_size50[18]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[18]_in[0]_crossbar trig v(mux_2level_size50[18]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[18]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[18]_leakage_power avg p(Vgvdd_mux_2level_size50[18]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[18]_in[0]_crossbar param='mux_2level_size50[18]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[18]_dynamic_power avg p(Vgvdd_mux_2level_size50[18]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[18]_energy_per_cycle param='mux_2level_size50[18]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[18]_in[0]_crossbar param='mux_2level_size50[18]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[18]_in[0]_crossbar param='dynamic_power_idle_mux50[18]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[18]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[18]) from='start_rise_idle_mux50[18]_in[0]_crossbar' to='start_rise_idle_mux50[18]_in[0]_crossbar+switch_rise_idle_mux50[18]_in[0]_crossbar' -.meas tran dynamic_fall_idle_mux50[18]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[18]) from='start_fall_idle_mux50[18]_in[0]_crossbar' to='start_fall_idle_mux50[18]_in[0]_crossbar+switch_fall_idle_mux50[18]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to18] -+ param='sum_leakage_power_mux[0to17]+leakage_idle_mux50[18]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to18] -+ param='sum_energy_per_cycle_mux[0to17]+energy_per_cycle_idle_mux50[18]_in[0]_crossbar' -Xload_inv[18]_no0 mux_2level_size50[18]->out mux_2level_size50[18]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to18] -+ param='sum_leakage_power_pb_mux[0to17]+leakage_idle_mux50[18]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to18] -+ param='sum_energy_per_cycle_pb_mux[0to17]+energy_per_cycle_idle_mux50[18]_in[0]_crossbar' -Xmux_2level_size50[19] mux_2level_size50[19]->in[0] mux_2level_size50[19]->in[1] mux_2level_size50[19]->in[2] mux_2level_size50[19]->in[3] mux_2level_size50[19]->in[4] mux_2level_size50[19]->in[5] mux_2level_size50[19]->in[6] mux_2level_size50[19]->in[7] mux_2level_size50[19]->in[8] mux_2level_size50[19]->in[9] mux_2level_size50[19]->in[10] mux_2level_size50[19]->in[11] mux_2level_size50[19]->in[12] mux_2level_size50[19]->in[13] mux_2level_size50[19]->in[14] mux_2level_size50[19]->in[15] mux_2level_size50[19]->in[16] mux_2level_size50[19]->in[17] mux_2level_size50[19]->in[18] mux_2level_size50[19]->in[19] mux_2level_size50[19]->in[20] mux_2level_size50[19]->in[21] mux_2level_size50[19]->in[22] mux_2level_size50[19]->in[23] mux_2level_size50[19]->in[24] mux_2level_size50[19]->in[25] mux_2level_size50[19]->in[26] mux_2level_size50[19]->in[27] mux_2level_size50[19]->in[28] mux_2level_size50[19]->in[29] mux_2level_size50[19]->in[30] mux_2level_size50[19]->in[31] mux_2level_size50[19]->in[32] mux_2level_size50[19]->in[33] mux_2level_size50[19]->in[34] mux_2level_size50[19]->in[35] mux_2level_size50[19]->in[36] mux_2level_size50[19]->in[37] mux_2level_size50[19]->in[38] mux_2level_size50[19]->in[39] mux_2level_size50[19]->in[40] mux_2level_size50[19]->in[41] mux_2level_size50[19]->in[42] mux_2level_size50[19]->in[43] mux_2level_size50[19]->in[44] mux_2level_size50[19]->in[45] mux_2level_size50[19]->in[46] mux_2level_size50[19]->in[47] mux_2level_size50[19]->in[48] mux_2level_size50[19]->in[49] mux_2level_size50[19]->out sram[304]->outb sram[304]->out sram[305]->out sram[305]->outb sram[306]->out sram[306]->outb sram[307]->out sram[307]->outb sram[308]->out sram[308]->outb sram[309]->out sram[309]->outb sram[310]->out sram[310]->outb sram[311]->out sram[311]->outb sram[312]->outb sram[312]->out sram[313]->out sram[313]->outb sram[314]->out sram[314]->outb sram[315]->out sram[315]->outb sram[316]->out sram[316]->outb sram[317]->out sram[317]->outb sram[318]->out sram[318]->outb sram[319]->out sram[319]->outb gvdd_mux_2level_size50[19] 0 mux_2level_size50 -***** SRAM bits for MUX[19], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[304] sram->in sram[304]->out sram[304]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[304]->out) 0 -.nodeset V(sram[304]->outb) vsp -Xsram[305] sram->in sram[305]->out sram[305]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[305]->out) 0 -.nodeset V(sram[305]->outb) vsp -Xsram[306] sram->in sram[306]->out sram[306]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[306]->out) 0 -.nodeset V(sram[306]->outb) vsp -Xsram[307] sram->in sram[307]->out sram[307]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[307]->out) 0 -.nodeset V(sram[307]->outb) vsp -Xsram[308] sram->in sram[308]->out sram[308]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[308]->out) 0 -.nodeset V(sram[308]->outb) vsp -Xsram[309] sram->in sram[309]->out sram[309]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[309]->out) 0 -.nodeset V(sram[309]->outb) vsp -Xsram[310] sram->in sram[310]->out sram[310]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[310]->out) 0 -.nodeset V(sram[310]->outb) vsp -Xsram[311] sram->in sram[311]->out sram[311]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[311]->out) 0 -.nodeset V(sram[311]->outb) vsp -Xsram[312] sram->in sram[312]->out sram[312]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[312]->out) 0 -.nodeset V(sram[312]->outb) vsp -Xsram[313] sram->in sram[313]->out sram[313]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[313]->out) 0 -.nodeset V(sram[313]->outb) vsp -Xsram[314] sram->in sram[314]->out sram[314]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[314]->out) 0 -.nodeset V(sram[314]->outb) vsp -Xsram[315] sram->in sram[315]->out sram[315]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[315]->out) 0 -.nodeset V(sram[315]->outb) vsp -Xsram[316] sram->in sram[316]->out sram[316]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[316]->out) 0 -.nodeset V(sram[316]->outb) vsp -Xsram[317] sram->in sram[317]->out sram[317]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[317]->out) 0 -.nodeset V(sram[317]->outb) vsp -Xsram[318] sram->in sram[318]->out sram[318]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[318]->out) 0 -.nodeset V(sram[318]->outb) vsp -Xsram[319] sram->in sram[319]->out sram[319]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[319]->out) 0 -.nodeset V(sram[319]->outb) vsp -***** Signal mux_2level_size50[19]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[0] mux_2level_size50[19]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[1] mux_2level_size50[19]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[2] mux_2level_size50[19]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[3] mux_2level_size50[19]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[4] mux_2level_size50[19]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[5] mux_2level_size50[19]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[6] mux_2level_size50[19]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[7] mux_2level_size50[19]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[8] mux_2level_size50[19]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[9] mux_2level_size50[19]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[10] mux_2level_size50[19]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[11] mux_2level_size50[19]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[12] mux_2level_size50[19]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[13] mux_2level_size50[19]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[14] mux_2level_size50[19]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[15] mux_2level_size50[19]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[16] mux_2level_size50[19]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[17] mux_2level_size50[19]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[18] mux_2level_size50[19]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[19] mux_2level_size50[19]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[20] mux_2level_size50[19]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[21] mux_2level_size50[19]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[22] mux_2level_size50[19]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[23] mux_2level_size50[19]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[24] mux_2level_size50[19]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[25] mux_2level_size50[19]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[26] mux_2level_size50[19]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[27] mux_2level_size50[19]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[28] mux_2level_size50[19]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[29] mux_2level_size50[19]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[30] mux_2level_size50[19]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[31] mux_2level_size50[19]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[32] mux_2level_size50[19]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[33] mux_2level_size50[19]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[34] mux_2level_size50[19]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[35] mux_2level_size50[19]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[36] mux_2level_size50[19]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[37] mux_2level_size50[19]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[38] mux_2level_size50[19]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[19]->in[39] mux_2level_size50[19]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[19]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[40] mux_2level_size50[19]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[41] mux_2level_size50[19]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[42] mux_2level_size50[19]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[43] mux_2level_size50[19]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[44] mux_2level_size50[19]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[45] mux_2level_size50[19]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[46] mux_2level_size50[19]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[47] mux_2level_size50[19]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[48] mux_2level_size50[19]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[19]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[19]->in[49] mux_2level_size50[19]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[19] gvdd_mux_2level_size50[19] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[19]_in[1]_crossbar trig v(mux_2level_size50[19]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[19]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[19]_in[1]_crossbar trig v(mux_2level_size50[19]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[19]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[19]_in[1]_crossbar when v(mux_2level_size50[19]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[19]_in[1]_crossbar trig v(mux_2level_size50[19]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[19]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[19]_in[1]_crossbar when v(mux_2level_size50[19]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[19]_in[1]_crossbar trig v(mux_2level_size50[19]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[19]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[19]_leakage_power avg p(Vgvdd_mux_2level_size50[19]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[19]_in[1]_crossbar param='mux_2level_size50[19]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[19]_dynamic_power avg p(Vgvdd_mux_2level_size50[19]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[19]_energy_per_cycle param='mux_2level_size50[19]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[19]_in[1]_crossbar param='mux_2level_size50[19]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[19]_in[1]_crossbar param='dynamic_power_idle_mux50[19]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[19]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[19]) from='start_rise_idle_mux50[19]_in[1]_crossbar' to='start_rise_idle_mux50[19]_in[1]_crossbar+switch_rise_idle_mux50[19]_in[1]_crossbar' -.meas tran dynamic_fall_idle_mux50[19]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[19]) from='start_fall_idle_mux50[19]_in[1]_crossbar' to='start_fall_idle_mux50[19]_in[1]_crossbar+switch_fall_idle_mux50[19]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to19] -+ param='sum_leakage_power_mux[0to18]+leakage_idle_mux50[19]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to19] -+ param='sum_energy_per_cycle_mux[0to18]+energy_per_cycle_idle_mux50[19]_in[1]_crossbar' -Xload_inv[19]_no0 mux_2level_size50[19]->out mux_2level_size50[19]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to19] -+ param='sum_leakage_power_pb_mux[0to18]+leakage_idle_mux50[19]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to19] -+ param='sum_energy_per_cycle_pb_mux[0to18]+energy_per_cycle_idle_mux50[19]_in[1]_crossbar' -Xmux_2level_size50[20] mux_2level_size50[20]->in[0] mux_2level_size50[20]->in[1] mux_2level_size50[20]->in[2] mux_2level_size50[20]->in[3] mux_2level_size50[20]->in[4] mux_2level_size50[20]->in[5] mux_2level_size50[20]->in[6] mux_2level_size50[20]->in[7] mux_2level_size50[20]->in[8] mux_2level_size50[20]->in[9] mux_2level_size50[20]->in[10] mux_2level_size50[20]->in[11] mux_2level_size50[20]->in[12] mux_2level_size50[20]->in[13] mux_2level_size50[20]->in[14] mux_2level_size50[20]->in[15] mux_2level_size50[20]->in[16] mux_2level_size50[20]->in[17] mux_2level_size50[20]->in[18] mux_2level_size50[20]->in[19] mux_2level_size50[20]->in[20] mux_2level_size50[20]->in[21] mux_2level_size50[20]->in[22] mux_2level_size50[20]->in[23] mux_2level_size50[20]->in[24] mux_2level_size50[20]->in[25] mux_2level_size50[20]->in[26] mux_2level_size50[20]->in[27] mux_2level_size50[20]->in[28] mux_2level_size50[20]->in[29] mux_2level_size50[20]->in[30] mux_2level_size50[20]->in[31] mux_2level_size50[20]->in[32] mux_2level_size50[20]->in[33] mux_2level_size50[20]->in[34] mux_2level_size50[20]->in[35] mux_2level_size50[20]->in[36] mux_2level_size50[20]->in[37] mux_2level_size50[20]->in[38] mux_2level_size50[20]->in[39] mux_2level_size50[20]->in[40] mux_2level_size50[20]->in[41] mux_2level_size50[20]->in[42] mux_2level_size50[20]->in[43] mux_2level_size50[20]->in[44] mux_2level_size50[20]->in[45] mux_2level_size50[20]->in[46] mux_2level_size50[20]->in[47] mux_2level_size50[20]->in[48] mux_2level_size50[20]->in[49] mux_2level_size50[20]->out sram[320]->outb sram[320]->out sram[321]->out sram[321]->outb sram[322]->out sram[322]->outb sram[323]->out sram[323]->outb sram[324]->out sram[324]->outb sram[325]->out sram[325]->outb sram[326]->out sram[326]->outb sram[327]->out sram[327]->outb sram[328]->outb sram[328]->out sram[329]->out sram[329]->outb sram[330]->out sram[330]->outb sram[331]->out sram[331]->outb sram[332]->out sram[332]->outb sram[333]->out sram[333]->outb sram[334]->out sram[334]->outb sram[335]->out sram[335]->outb gvdd_mux_2level_size50[20] 0 mux_2level_size50 -***** SRAM bits for MUX[20], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[320] sram->in sram[320]->out sram[320]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[320]->out) 0 -.nodeset V(sram[320]->outb) vsp -Xsram[321] sram->in sram[321]->out sram[321]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[321]->out) 0 -.nodeset V(sram[321]->outb) vsp -Xsram[322] sram->in sram[322]->out sram[322]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[322]->out) 0 -.nodeset V(sram[322]->outb) vsp -Xsram[323] sram->in sram[323]->out sram[323]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[323]->out) 0 -.nodeset V(sram[323]->outb) vsp -Xsram[324] sram->in sram[324]->out sram[324]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[324]->out) 0 -.nodeset V(sram[324]->outb) vsp -Xsram[325] sram->in sram[325]->out sram[325]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[325]->out) 0 -.nodeset V(sram[325]->outb) vsp -Xsram[326] sram->in sram[326]->out sram[326]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[326]->out) 0 -.nodeset V(sram[326]->outb) vsp -Xsram[327] sram->in sram[327]->out sram[327]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[327]->out) 0 -.nodeset V(sram[327]->outb) vsp -Xsram[328] sram->in sram[328]->out sram[328]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[328]->out) 0 -.nodeset V(sram[328]->outb) vsp -Xsram[329] sram->in sram[329]->out sram[329]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[329]->out) 0 -.nodeset V(sram[329]->outb) vsp -Xsram[330] sram->in sram[330]->out sram[330]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[330]->out) 0 -.nodeset V(sram[330]->outb) vsp -Xsram[331] sram->in sram[331]->out sram[331]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[331]->out) 0 -.nodeset V(sram[331]->outb) vsp -Xsram[332] sram->in sram[332]->out sram[332]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[332]->out) 0 -.nodeset V(sram[332]->outb) vsp -Xsram[333] sram->in sram[333]->out sram[333]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[333]->out) 0 -.nodeset V(sram[333]->outb) vsp -Xsram[334] sram->in sram[334]->out sram[334]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[334]->out) 0 -.nodeset V(sram[334]->outb) vsp -Xsram[335] sram->in sram[335]->out sram[335]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[335]->out) 0 -.nodeset V(sram[335]->outb) vsp -***** Signal mux_2level_size50[20]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[0] mux_2level_size50[20]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[1] mux_2level_size50[20]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[2] mux_2level_size50[20]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[3] mux_2level_size50[20]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[4] mux_2level_size50[20]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[5] mux_2level_size50[20]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[6] mux_2level_size50[20]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[7] mux_2level_size50[20]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[8] mux_2level_size50[20]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[9] mux_2level_size50[20]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[10] mux_2level_size50[20]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[11] mux_2level_size50[20]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[12] mux_2level_size50[20]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[13] mux_2level_size50[20]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[14] mux_2level_size50[20]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[15] mux_2level_size50[20]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[16] mux_2level_size50[20]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[17] mux_2level_size50[20]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[18] mux_2level_size50[20]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[19] mux_2level_size50[20]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[20] mux_2level_size50[20]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[21] mux_2level_size50[20]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[22] mux_2level_size50[20]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[23] mux_2level_size50[20]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[24] mux_2level_size50[20]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[25] mux_2level_size50[20]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[26] mux_2level_size50[20]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[27] mux_2level_size50[20]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[28] mux_2level_size50[20]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[29] mux_2level_size50[20]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[30] mux_2level_size50[20]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[31] mux_2level_size50[20]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[32] mux_2level_size50[20]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[33] mux_2level_size50[20]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[34] mux_2level_size50[20]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[35] mux_2level_size50[20]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[36] mux_2level_size50[20]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[37] mux_2level_size50[20]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[38] mux_2level_size50[20]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[20]->in[39] mux_2level_size50[20]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[20]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[40] mux_2level_size50[20]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[41] mux_2level_size50[20]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[42] mux_2level_size50[20]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[43] mux_2level_size50[20]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[44] mux_2level_size50[20]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[45] mux_2level_size50[20]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[46] mux_2level_size50[20]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[47] mux_2level_size50[20]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[48] mux_2level_size50[20]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[20]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[20]->in[49] mux_2level_size50[20]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[20] gvdd_mux_2level_size50[20] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[20]_in[2]_crossbar trig v(mux_2level_size50[20]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[20]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[20]_in[2]_crossbar trig v(mux_2level_size50[20]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[20]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[20]_in[2]_crossbar when v(mux_2level_size50[20]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[20]_in[2]_crossbar trig v(mux_2level_size50[20]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[20]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[20]_in[2]_crossbar when v(mux_2level_size50[20]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[20]_in[2]_crossbar trig v(mux_2level_size50[20]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[20]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[20]_leakage_power avg p(Vgvdd_mux_2level_size50[20]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[20]_in[2]_crossbar param='mux_2level_size50[20]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[20]_dynamic_power avg p(Vgvdd_mux_2level_size50[20]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[20]_energy_per_cycle param='mux_2level_size50[20]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[20]_in[2]_crossbar param='mux_2level_size50[20]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[20]_in[2]_crossbar param='dynamic_power_idle_mux50[20]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[20]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[20]) from='start_rise_idle_mux50[20]_in[2]_crossbar' to='start_rise_idle_mux50[20]_in[2]_crossbar+switch_rise_idle_mux50[20]_in[2]_crossbar' -.meas tran dynamic_fall_idle_mux50[20]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[20]) from='start_fall_idle_mux50[20]_in[2]_crossbar' to='start_fall_idle_mux50[20]_in[2]_crossbar+switch_fall_idle_mux50[20]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to20] -+ param='sum_leakage_power_mux[0to19]+leakage_idle_mux50[20]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to20] -+ param='sum_energy_per_cycle_mux[0to19]+energy_per_cycle_idle_mux50[20]_in[2]_crossbar' -Xload_inv[20]_no0 mux_2level_size50[20]->out mux_2level_size50[20]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to20] -+ param='sum_leakage_power_pb_mux[0to19]+leakage_idle_mux50[20]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to20] -+ param='sum_energy_per_cycle_pb_mux[0to19]+energy_per_cycle_idle_mux50[20]_in[2]_crossbar' -Xmux_2level_size50[21] mux_2level_size50[21]->in[0] mux_2level_size50[21]->in[1] mux_2level_size50[21]->in[2] mux_2level_size50[21]->in[3] mux_2level_size50[21]->in[4] mux_2level_size50[21]->in[5] mux_2level_size50[21]->in[6] mux_2level_size50[21]->in[7] mux_2level_size50[21]->in[8] mux_2level_size50[21]->in[9] mux_2level_size50[21]->in[10] mux_2level_size50[21]->in[11] mux_2level_size50[21]->in[12] mux_2level_size50[21]->in[13] mux_2level_size50[21]->in[14] mux_2level_size50[21]->in[15] mux_2level_size50[21]->in[16] mux_2level_size50[21]->in[17] mux_2level_size50[21]->in[18] mux_2level_size50[21]->in[19] mux_2level_size50[21]->in[20] mux_2level_size50[21]->in[21] mux_2level_size50[21]->in[22] mux_2level_size50[21]->in[23] mux_2level_size50[21]->in[24] mux_2level_size50[21]->in[25] mux_2level_size50[21]->in[26] mux_2level_size50[21]->in[27] mux_2level_size50[21]->in[28] mux_2level_size50[21]->in[29] mux_2level_size50[21]->in[30] mux_2level_size50[21]->in[31] mux_2level_size50[21]->in[32] mux_2level_size50[21]->in[33] mux_2level_size50[21]->in[34] mux_2level_size50[21]->in[35] mux_2level_size50[21]->in[36] mux_2level_size50[21]->in[37] mux_2level_size50[21]->in[38] mux_2level_size50[21]->in[39] mux_2level_size50[21]->in[40] mux_2level_size50[21]->in[41] mux_2level_size50[21]->in[42] mux_2level_size50[21]->in[43] mux_2level_size50[21]->in[44] mux_2level_size50[21]->in[45] mux_2level_size50[21]->in[46] mux_2level_size50[21]->in[47] mux_2level_size50[21]->in[48] mux_2level_size50[21]->in[49] mux_2level_size50[21]->out sram[336]->outb sram[336]->out sram[337]->out sram[337]->outb sram[338]->out sram[338]->outb sram[339]->out sram[339]->outb sram[340]->out sram[340]->outb sram[341]->out sram[341]->outb sram[342]->out sram[342]->outb sram[343]->out sram[343]->outb sram[344]->outb sram[344]->out sram[345]->out sram[345]->outb sram[346]->out sram[346]->outb sram[347]->out sram[347]->outb sram[348]->out sram[348]->outb sram[349]->out sram[349]->outb sram[350]->out sram[350]->outb sram[351]->out sram[351]->outb gvdd_mux_2level_size50[21] 0 mux_2level_size50 -***** SRAM bits for MUX[21], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[336] sram->in sram[336]->out sram[336]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[336]->out) 0 -.nodeset V(sram[336]->outb) vsp -Xsram[337] sram->in sram[337]->out sram[337]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[337]->out) 0 -.nodeset V(sram[337]->outb) vsp -Xsram[338] sram->in sram[338]->out sram[338]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[338]->out) 0 -.nodeset V(sram[338]->outb) vsp -Xsram[339] sram->in sram[339]->out sram[339]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[339]->out) 0 -.nodeset V(sram[339]->outb) vsp -Xsram[340] sram->in sram[340]->out sram[340]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[340]->out) 0 -.nodeset V(sram[340]->outb) vsp -Xsram[341] sram->in sram[341]->out sram[341]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[341]->out) 0 -.nodeset V(sram[341]->outb) vsp -Xsram[342] sram->in sram[342]->out sram[342]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[342]->out) 0 -.nodeset V(sram[342]->outb) vsp -Xsram[343] sram->in sram[343]->out sram[343]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[343]->out) 0 -.nodeset V(sram[343]->outb) vsp -Xsram[344] sram->in sram[344]->out sram[344]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[344]->out) 0 -.nodeset V(sram[344]->outb) vsp -Xsram[345] sram->in sram[345]->out sram[345]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[345]->out) 0 -.nodeset V(sram[345]->outb) vsp -Xsram[346] sram->in sram[346]->out sram[346]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[346]->out) 0 -.nodeset V(sram[346]->outb) vsp -Xsram[347] sram->in sram[347]->out sram[347]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[347]->out) 0 -.nodeset V(sram[347]->outb) vsp -Xsram[348] sram->in sram[348]->out sram[348]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[348]->out) 0 -.nodeset V(sram[348]->outb) vsp -Xsram[349] sram->in sram[349]->out sram[349]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[349]->out) 0 -.nodeset V(sram[349]->outb) vsp -Xsram[350] sram->in sram[350]->out sram[350]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[350]->out) 0 -.nodeset V(sram[350]->outb) vsp -Xsram[351] sram->in sram[351]->out sram[351]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[351]->out) 0 -.nodeset V(sram[351]->outb) vsp -***** Signal mux_2level_size50[21]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[0] mux_2level_size50[21]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[1] mux_2level_size50[21]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[2] mux_2level_size50[21]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[3] mux_2level_size50[21]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[4] mux_2level_size50[21]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[5] mux_2level_size50[21]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[6] mux_2level_size50[21]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[7] mux_2level_size50[21]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[8] mux_2level_size50[21]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[9] mux_2level_size50[21]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[10] mux_2level_size50[21]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[11] mux_2level_size50[21]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[12] mux_2level_size50[21]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[13] mux_2level_size50[21]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[14] mux_2level_size50[21]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[15] mux_2level_size50[21]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[16] mux_2level_size50[21]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[17] mux_2level_size50[21]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[18] mux_2level_size50[21]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[19] mux_2level_size50[21]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[20] mux_2level_size50[21]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[21] mux_2level_size50[21]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[22] mux_2level_size50[21]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[23] mux_2level_size50[21]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[24] mux_2level_size50[21]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[25] mux_2level_size50[21]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[26] mux_2level_size50[21]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[27] mux_2level_size50[21]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[28] mux_2level_size50[21]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[29] mux_2level_size50[21]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[30] mux_2level_size50[21]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[31] mux_2level_size50[21]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[32] mux_2level_size50[21]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[33] mux_2level_size50[21]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[34] mux_2level_size50[21]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[35] mux_2level_size50[21]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[36] mux_2level_size50[21]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[37] mux_2level_size50[21]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[38] mux_2level_size50[21]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[21]->in[39] mux_2level_size50[21]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[21]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[40] mux_2level_size50[21]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[41] mux_2level_size50[21]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[42] mux_2level_size50[21]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[43] mux_2level_size50[21]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[44] mux_2level_size50[21]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[45] mux_2level_size50[21]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[46] mux_2level_size50[21]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[47] mux_2level_size50[21]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[48] mux_2level_size50[21]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[21]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[21]->in[49] mux_2level_size50[21]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[21] gvdd_mux_2level_size50[21] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[21]_in[3]_crossbar trig v(mux_2level_size50[21]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[21]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[21]_in[3]_crossbar trig v(mux_2level_size50[21]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[21]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[21]_in[3]_crossbar when v(mux_2level_size50[21]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[21]_in[3]_crossbar trig v(mux_2level_size50[21]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[21]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[21]_in[3]_crossbar when v(mux_2level_size50[21]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[21]_in[3]_crossbar trig v(mux_2level_size50[21]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[21]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[21]_leakage_power avg p(Vgvdd_mux_2level_size50[21]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[21]_in[3]_crossbar param='mux_2level_size50[21]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[21]_dynamic_power avg p(Vgvdd_mux_2level_size50[21]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[21]_energy_per_cycle param='mux_2level_size50[21]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[21]_in[3]_crossbar param='mux_2level_size50[21]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[21]_in[3]_crossbar param='dynamic_power_idle_mux50[21]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[21]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[21]) from='start_rise_idle_mux50[21]_in[3]_crossbar' to='start_rise_idle_mux50[21]_in[3]_crossbar+switch_rise_idle_mux50[21]_in[3]_crossbar' -.meas tran dynamic_fall_idle_mux50[21]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[21]) from='start_fall_idle_mux50[21]_in[3]_crossbar' to='start_fall_idle_mux50[21]_in[3]_crossbar+switch_fall_idle_mux50[21]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to21] -+ param='sum_leakage_power_mux[0to20]+leakage_idle_mux50[21]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to21] -+ param='sum_energy_per_cycle_mux[0to20]+energy_per_cycle_idle_mux50[21]_in[3]_crossbar' -Xload_inv[21]_no0 mux_2level_size50[21]->out mux_2level_size50[21]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to21] -+ param='sum_leakage_power_pb_mux[0to20]+leakage_idle_mux50[21]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to21] -+ param='sum_energy_per_cycle_pb_mux[0to20]+energy_per_cycle_idle_mux50[21]_in[3]_crossbar' -Xmux_2level_size50[22] mux_2level_size50[22]->in[0] mux_2level_size50[22]->in[1] mux_2level_size50[22]->in[2] mux_2level_size50[22]->in[3] mux_2level_size50[22]->in[4] mux_2level_size50[22]->in[5] mux_2level_size50[22]->in[6] mux_2level_size50[22]->in[7] mux_2level_size50[22]->in[8] mux_2level_size50[22]->in[9] mux_2level_size50[22]->in[10] mux_2level_size50[22]->in[11] mux_2level_size50[22]->in[12] mux_2level_size50[22]->in[13] mux_2level_size50[22]->in[14] mux_2level_size50[22]->in[15] mux_2level_size50[22]->in[16] mux_2level_size50[22]->in[17] mux_2level_size50[22]->in[18] mux_2level_size50[22]->in[19] mux_2level_size50[22]->in[20] mux_2level_size50[22]->in[21] mux_2level_size50[22]->in[22] mux_2level_size50[22]->in[23] mux_2level_size50[22]->in[24] mux_2level_size50[22]->in[25] mux_2level_size50[22]->in[26] mux_2level_size50[22]->in[27] mux_2level_size50[22]->in[28] mux_2level_size50[22]->in[29] mux_2level_size50[22]->in[30] mux_2level_size50[22]->in[31] mux_2level_size50[22]->in[32] mux_2level_size50[22]->in[33] mux_2level_size50[22]->in[34] mux_2level_size50[22]->in[35] mux_2level_size50[22]->in[36] mux_2level_size50[22]->in[37] mux_2level_size50[22]->in[38] mux_2level_size50[22]->in[39] mux_2level_size50[22]->in[40] mux_2level_size50[22]->in[41] mux_2level_size50[22]->in[42] mux_2level_size50[22]->in[43] mux_2level_size50[22]->in[44] mux_2level_size50[22]->in[45] mux_2level_size50[22]->in[46] mux_2level_size50[22]->in[47] mux_2level_size50[22]->in[48] mux_2level_size50[22]->in[49] mux_2level_size50[22]->out sram[352]->outb sram[352]->out sram[353]->out sram[353]->outb sram[354]->out sram[354]->outb sram[355]->out sram[355]->outb sram[356]->out sram[356]->outb sram[357]->out sram[357]->outb sram[358]->out sram[358]->outb sram[359]->out sram[359]->outb sram[360]->outb sram[360]->out sram[361]->out sram[361]->outb sram[362]->out sram[362]->outb sram[363]->out sram[363]->outb sram[364]->out sram[364]->outb sram[365]->out sram[365]->outb sram[366]->out sram[366]->outb sram[367]->out sram[367]->outb gvdd_mux_2level_size50[22] 0 mux_2level_size50 -***** SRAM bits for MUX[22], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[352] sram->in sram[352]->out sram[352]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[352]->out) 0 -.nodeset V(sram[352]->outb) vsp -Xsram[353] sram->in sram[353]->out sram[353]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[353]->out) 0 -.nodeset V(sram[353]->outb) vsp -Xsram[354] sram->in sram[354]->out sram[354]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[354]->out) 0 -.nodeset V(sram[354]->outb) vsp -Xsram[355] sram->in sram[355]->out sram[355]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[355]->out) 0 -.nodeset V(sram[355]->outb) vsp -Xsram[356] sram->in sram[356]->out sram[356]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[356]->out) 0 -.nodeset V(sram[356]->outb) vsp -Xsram[357] sram->in sram[357]->out sram[357]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[357]->out) 0 -.nodeset V(sram[357]->outb) vsp -Xsram[358] sram->in sram[358]->out sram[358]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[358]->out) 0 -.nodeset V(sram[358]->outb) vsp -Xsram[359] sram->in sram[359]->out sram[359]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[359]->out) 0 -.nodeset V(sram[359]->outb) vsp -Xsram[360] sram->in sram[360]->out sram[360]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[360]->out) 0 -.nodeset V(sram[360]->outb) vsp -Xsram[361] sram->in sram[361]->out sram[361]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[361]->out) 0 -.nodeset V(sram[361]->outb) vsp -Xsram[362] sram->in sram[362]->out sram[362]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[362]->out) 0 -.nodeset V(sram[362]->outb) vsp -Xsram[363] sram->in sram[363]->out sram[363]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[363]->out) 0 -.nodeset V(sram[363]->outb) vsp -Xsram[364] sram->in sram[364]->out sram[364]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[364]->out) 0 -.nodeset V(sram[364]->outb) vsp -Xsram[365] sram->in sram[365]->out sram[365]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[365]->out) 0 -.nodeset V(sram[365]->outb) vsp -Xsram[366] sram->in sram[366]->out sram[366]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[366]->out) 0 -.nodeset V(sram[366]->outb) vsp -Xsram[367] sram->in sram[367]->out sram[367]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[367]->out) 0 -.nodeset V(sram[367]->outb) vsp -***** Signal mux_2level_size50[22]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[0] mux_2level_size50[22]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[1] mux_2level_size50[22]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[2] mux_2level_size50[22]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[3] mux_2level_size50[22]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[4] mux_2level_size50[22]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[5] mux_2level_size50[22]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[6] mux_2level_size50[22]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[7] mux_2level_size50[22]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[8] mux_2level_size50[22]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[9] mux_2level_size50[22]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[10] mux_2level_size50[22]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[11] mux_2level_size50[22]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[12] mux_2level_size50[22]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[13] mux_2level_size50[22]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[14] mux_2level_size50[22]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[15] mux_2level_size50[22]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[16] mux_2level_size50[22]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[17] mux_2level_size50[22]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[18] mux_2level_size50[22]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[19] mux_2level_size50[22]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[20] mux_2level_size50[22]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[21] mux_2level_size50[22]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[22] mux_2level_size50[22]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[23] mux_2level_size50[22]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[24] mux_2level_size50[22]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[25] mux_2level_size50[22]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[26] mux_2level_size50[22]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[27] mux_2level_size50[22]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[28] mux_2level_size50[22]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[29] mux_2level_size50[22]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[30] mux_2level_size50[22]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[31] mux_2level_size50[22]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[32] mux_2level_size50[22]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[33] mux_2level_size50[22]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[34] mux_2level_size50[22]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[35] mux_2level_size50[22]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[36] mux_2level_size50[22]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[37] mux_2level_size50[22]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[38] mux_2level_size50[22]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[22]->in[39] mux_2level_size50[22]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[22]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[40] mux_2level_size50[22]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[41] mux_2level_size50[22]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[42] mux_2level_size50[22]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[43] mux_2level_size50[22]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[44] mux_2level_size50[22]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[45] mux_2level_size50[22]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[46] mux_2level_size50[22]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[47] mux_2level_size50[22]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[48] mux_2level_size50[22]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[22]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[22]->in[49] mux_2level_size50[22]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[22] gvdd_mux_2level_size50[22] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[22]_in[4]_crossbar trig v(mux_2level_size50[22]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[22]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[22]_in[4]_crossbar trig v(mux_2level_size50[22]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[22]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[22]_in[4]_crossbar when v(mux_2level_size50[22]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[22]_in[4]_crossbar trig v(mux_2level_size50[22]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[22]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[22]_in[4]_crossbar when v(mux_2level_size50[22]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[22]_in[4]_crossbar trig v(mux_2level_size50[22]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[22]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[22]_leakage_power avg p(Vgvdd_mux_2level_size50[22]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[22]_in[4]_crossbar param='mux_2level_size50[22]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[22]_dynamic_power avg p(Vgvdd_mux_2level_size50[22]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[22]_energy_per_cycle param='mux_2level_size50[22]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[22]_in[4]_crossbar param='mux_2level_size50[22]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[22]_in[4]_crossbar param='dynamic_power_idle_mux50[22]_in[4]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[22]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[22]) from='start_rise_idle_mux50[22]_in[4]_crossbar' to='start_rise_idle_mux50[22]_in[4]_crossbar+switch_rise_idle_mux50[22]_in[4]_crossbar' -.meas tran dynamic_fall_idle_mux50[22]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[22]) from='start_fall_idle_mux50[22]_in[4]_crossbar' to='start_fall_idle_mux50[22]_in[4]_crossbar+switch_fall_idle_mux50[22]_in[4]_crossbar' -.meas tran sum_leakage_power_mux[0to22] -+ param='sum_leakage_power_mux[0to21]+leakage_idle_mux50[22]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to22] -+ param='sum_energy_per_cycle_mux[0to21]+energy_per_cycle_idle_mux50[22]_in[4]_crossbar' -Xload_inv[22]_no0 mux_2level_size50[22]->out mux_2level_size50[22]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to22] -+ param='sum_leakage_power_pb_mux[0to21]+leakage_idle_mux50[22]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to22] -+ param='sum_energy_per_cycle_pb_mux[0to21]+energy_per_cycle_idle_mux50[22]_in[4]_crossbar' -Xmux_2level_size50[23] mux_2level_size50[23]->in[0] mux_2level_size50[23]->in[1] mux_2level_size50[23]->in[2] mux_2level_size50[23]->in[3] mux_2level_size50[23]->in[4] mux_2level_size50[23]->in[5] mux_2level_size50[23]->in[6] mux_2level_size50[23]->in[7] mux_2level_size50[23]->in[8] mux_2level_size50[23]->in[9] mux_2level_size50[23]->in[10] mux_2level_size50[23]->in[11] mux_2level_size50[23]->in[12] mux_2level_size50[23]->in[13] mux_2level_size50[23]->in[14] mux_2level_size50[23]->in[15] mux_2level_size50[23]->in[16] mux_2level_size50[23]->in[17] mux_2level_size50[23]->in[18] mux_2level_size50[23]->in[19] mux_2level_size50[23]->in[20] mux_2level_size50[23]->in[21] mux_2level_size50[23]->in[22] mux_2level_size50[23]->in[23] mux_2level_size50[23]->in[24] mux_2level_size50[23]->in[25] mux_2level_size50[23]->in[26] mux_2level_size50[23]->in[27] mux_2level_size50[23]->in[28] mux_2level_size50[23]->in[29] mux_2level_size50[23]->in[30] mux_2level_size50[23]->in[31] mux_2level_size50[23]->in[32] mux_2level_size50[23]->in[33] mux_2level_size50[23]->in[34] mux_2level_size50[23]->in[35] mux_2level_size50[23]->in[36] mux_2level_size50[23]->in[37] mux_2level_size50[23]->in[38] mux_2level_size50[23]->in[39] mux_2level_size50[23]->in[40] mux_2level_size50[23]->in[41] mux_2level_size50[23]->in[42] mux_2level_size50[23]->in[43] mux_2level_size50[23]->in[44] mux_2level_size50[23]->in[45] mux_2level_size50[23]->in[46] mux_2level_size50[23]->in[47] mux_2level_size50[23]->in[48] mux_2level_size50[23]->in[49] mux_2level_size50[23]->out sram[368]->outb sram[368]->out sram[369]->out sram[369]->outb sram[370]->out sram[370]->outb sram[371]->out sram[371]->outb sram[372]->out sram[372]->outb sram[373]->out sram[373]->outb sram[374]->out sram[374]->outb sram[375]->out sram[375]->outb sram[376]->outb sram[376]->out sram[377]->out sram[377]->outb sram[378]->out sram[378]->outb sram[379]->out sram[379]->outb sram[380]->out sram[380]->outb sram[381]->out sram[381]->outb sram[382]->out sram[382]->outb sram[383]->out sram[383]->outb gvdd_mux_2level_size50[23] 0 mux_2level_size50 -***** SRAM bits for MUX[23], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[368] sram->in sram[368]->out sram[368]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[368]->out) 0 -.nodeset V(sram[368]->outb) vsp -Xsram[369] sram->in sram[369]->out sram[369]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[369]->out) 0 -.nodeset V(sram[369]->outb) vsp -Xsram[370] sram->in sram[370]->out sram[370]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[370]->out) 0 -.nodeset V(sram[370]->outb) vsp -Xsram[371] sram->in sram[371]->out sram[371]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[371]->out) 0 -.nodeset V(sram[371]->outb) vsp -Xsram[372] sram->in sram[372]->out sram[372]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[372]->out) 0 -.nodeset V(sram[372]->outb) vsp -Xsram[373] sram->in sram[373]->out sram[373]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[373]->out) 0 -.nodeset V(sram[373]->outb) vsp -Xsram[374] sram->in sram[374]->out sram[374]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[374]->out) 0 -.nodeset V(sram[374]->outb) vsp -Xsram[375] sram->in sram[375]->out sram[375]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[375]->out) 0 -.nodeset V(sram[375]->outb) vsp -Xsram[376] sram->in sram[376]->out sram[376]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[376]->out) 0 -.nodeset V(sram[376]->outb) vsp -Xsram[377] sram->in sram[377]->out sram[377]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[377]->out) 0 -.nodeset V(sram[377]->outb) vsp -Xsram[378] sram->in sram[378]->out sram[378]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[378]->out) 0 -.nodeset V(sram[378]->outb) vsp -Xsram[379] sram->in sram[379]->out sram[379]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[379]->out) 0 -.nodeset V(sram[379]->outb) vsp -Xsram[380] sram->in sram[380]->out sram[380]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[380]->out) 0 -.nodeset V(sram[380]->outb) vsp -Xsram[381] sram->in sram[381]->out sram[381]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[381]->out) 0 -.nodeset V(sram[381]->outb) vsp -Xsram[382] sram->in sram[382]->out sram[382]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[382]->out) 0 -.nodeset V(sram[382]->outb) vsp -Xsram[383] sram->in sram[383]->out sram[383]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[383]->out) 0 -.nodeset V(sram[383]->outb) vsp -***** Signal mux_2level_size50[23]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[0] mux_2level_size50[23]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[1] mux_2level_size50[23]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[2] mux_2level_size50[23]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[3] mux_2level_size50[23]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[4] mux_2level_size50[23]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[5] mux_2level_size50[23]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[6] mux_2level_size50[23]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[7] mux_2level_size50[23]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[8] mux_2level_size50[23]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[9] mux_2level_size50[23]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[10] mux_2level_size50[23]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[11] mux_2level_size50[23]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[12] mux_2level_size50[23]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[13] mux_2level_size50[23]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[14] mux_2level_size50[23]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[15] mux_2level_size50[23]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[16] mux_2level_size50[23]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[17] mux_2level_size50[23]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[18] mux_2level_size50[23]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[19] mux_2level_size50[23]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[20] mux_2level_size50[23]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[21] mux_2level_size50[23]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[22] mux_2level_size50[23]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[23] mux_2level_size50[23]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[24] mux_2level_size50[23]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[25] mux_2level_size50[23]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[26] mux_2level_size50[23]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[27] mux_2level_size50[23]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[28] mux_2level_size50[23]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[29] mux_2level_size50[23]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[30] mux_2level_size50[23]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[31] mux_2level_size50[23]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[32] mux_2level_size50[23]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[33] mux_2level_size50[23]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[34] mux_2level_size50[23]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[35] mux_2level_size50[23]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[36] mux_2level_size50[23]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[37] mux_2level_size50[23]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[38] mux_2level_size50[23]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[23]->in[39] mux_2level_size50[23]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[23]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[40] mux_2level_size50[23]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[41] mux_2level_size50[23]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[42] mux_2level_size50[23]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[43] mux_2level_size50[23]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[44] mux_2level_size50[23]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[45] mux_2level_size50[23]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[46] mux_2level_size50[23]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[47] mux_2level_size50[23]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[48] mux_2level_size50[23]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[23]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[23]->in[49] mux_2level_size50[23]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[23] gvdd_mux_2level_size50[23] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[23]_in[5]_crossbar trig v(mux_2level_size50[23]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[23]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[23]_in[5]_crossbar trig v(mux_2level_size50[23]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[23]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[23]_in[5]_crossbar when v(mux_2level_size50[23]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[23]_in[5]_crossbar trig v(mux_2level_size50[23]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[23]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[23]_in[5]_crossbar when v(mux_2level_size50[23]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[23]_in[5]_crossbar trig v(mux_2level_size50[23]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[23]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[23]_leakage_power avg p(Vgvdd_mux_2level_size50[23]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[23]_in[5]_crossbar param='mux_2level_size50[23]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[23]_dynamic_power avg p(Vgvdd_mux_2level_size50[23]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[23]_energy_per_cycle param='mux_2level_size50[23]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[23]_in[5]_crossbar param='mux_2level_size50[23]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[23]_in[5]_crossbar param='dynamic_power_idle_mux50[23]_in[5]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[23]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[23]) from='start_rise_idle_mux50[23]_in[5]_crossbar' to='start_rise_idle_mux50[23]_in[5]_crossbar+switch_rise_idle_mux50[23]_in[5]_crossbar' -.meas tran dynamic_fall_idle_mux50[23]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[23]) from='start_fall_idle_mux50[23]_in[5]_crossbar' to='start_fall_idle_mux50[23]_in[5]_crossbar+switch_fall_idle_mux50[23]_in[5]_crossbar' -.meas tran sum_leakage_power_mux[0to23] -+ param='sum_leakage_power_mux[0to22]+leakage_idle_mux50[23]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to23] -+ param='sum_energy_per_cycle_mux[0to22]+energy_per_cycle_idle_mux50[23]_in[5]_crossbar' -Xload_inv[23]_no0 mux_2level_size50[23]->out mux_2level_size50[23]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to23] -+ param='sum_leakage_power_pb_mux[0to22]+leakage_idle_mux50[23]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to23] -+ param='sum_energy_per_cycle_pb_mux[0to22]+energy_per_cycle_idle_mux50[23]_in[5]_crossbar' -Xmux_2level_size50[24] mux_2level_size50[24]->in[0] mux_2level_size50[24]->in[1] mux_2level_size50[24]->in[2] mux_2level_size50[24]->in[3] mux_2level_size50[24]->in[4] mux_2level_size50[24]->in[5] mux_2level_size50[24]->in[6] mux_2level_size50[24]->in[7] mux_2level_size50[24]->in[8] mux_2level_size50[24]->in[9] mux_2level_size50[24]->in[10] mux_2level_size50[24]->in[11] mux_2level_size50[24]->in[12] mux_2level_size50[24]->in[13] mux_2level_size50[24]->in[14] mux_2level_size50[24]->in[15] mux_2level_size50[24]->in[16] mux_2level_size50[24]->in[17] mux_2level_size50[24]->in[18] mux_2level_size50[24]->in[19] mux_2level_size50[24]->in[20] mux_2level_size50[24]->in[21] mux_2level_size50[24]->in[22] mux_2level_size50[24]->in[23] mux_2level_size50[24]->in[24] mux_2level_size50[24]->in[25] mux_2level_size50[24]->in[26] mux_2level_size50[24]->in[27] mux_2level_size50[24]->in[28] mux_2level_size50[24]->in[29] mux_2level_size50[24]->in[30] mux_2level_size50[24]->in[31] mux_2level_size50[24]->in[32] mux_2level_size50[24]->in[33] mux_2level_size50[24]->in[34] mux_2level_size50[24]->in[35] mux_2level_size50[24]->in[36] mux_2level_size50[24]->in[37] mux_2level_size50[24]->in[38] mux_2level_size50[24]->in[39] mux_2level_size50[24]->in[40] mux_2level_size50[24]->in[41] mux_2level_size50[24]->in[42] mux_2level_size50[24]->in[43] mux_2level_size50[24]->in[44] mux_2level_size50[24]->in[45] mux_2level_size50[24]->in[46] mux_2level_size50[24]->in[47] mux_2level_size50[24]->in[48] mux_2level_size50[24]->in[49] mux_2level_size50[24]->out sram[384]->outb sram[384]->out sram[385]->out sram[385]->outb sram[386]->out sram[386]->outb sram[387]->out sram[387]->outb sram[388]->out sram[388]->outb sram[389]->out sram[389]->outb sram[390]->out sram[390]->outb sram[391]->out sram[391]->outb sram[392]->outb sram[392]->out sram[393]->out sram[393]->outb sram[394]->out sram[394]->outb sram[395]->out sram[395]->outb sram[396]->out sram[396]->outb sram[397]->out sram[397]->outb sram[398]->out sram[398]->outb sram[399]->out sram[399]->outb gvdd_mux_2level_size50[24] 0 mux_2level_size50 -***** SRAM bits for MUX[24], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[384] sram->in sram[384]->out sram[384]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[384]->out) 0 -.nodeset V(sram[384]->outb) vsp -Xsram[385] sram->in sram[385]->out sram[385]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[385]->out) 0 -.nodeset V(sram[385]->outb) vsp -Xsram[386] sram->in sram[386]->out sram[386]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[386]->out) 0 -.nodeset V(sram[386]->outb) vsp -Xsram[387] sram->in sram[387]->out sram[387]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[387]->out) 0 -.nodeset V(sram[387]->outb) vsp -Xsram[388] sram->in sram[388]->out sram[388]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[388]->out) 0 -.nodeset V(sram[388]->outb) vsp -Xsram[389] sram->in sram[389]->out sram[389]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[389]->out) 0 -.nodeset V(sram[389]->outb) vsp -Xsram[390] sram->in sram[390]->out sram[390]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[390]->out) 0 -.nodeset V(sram[390]->outb) vsp -Xsram[391] sram->in sram[391]->out sram[391]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[391]->out) 0 -.nodeset V(sram[391]->outb) vsp -Xsram[392] sram->in sram[392]->out sram[392]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[392]->out) 0 -.nodeset V(sram[392]->outb) vsp -Xsram[393] sram->in sram[393]->out sram[393]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[393]->out) 0 -.nodeset V(sram[393]->outb) vsp -Xsram[394] sram->in sram[394]->out sram[394]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[394]->out) 0 -.nodeset V(sram[394]->outb) vsp -Xsram[395] sram->in sram[395]->out sram[395]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[395]->out) 0 -.nodeset V(sram[395]->outb) vsp -Xsram[396] sram->in sram[396]->out sram[396]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[396]->out) 0 -.nodeset V(sram[396]->outb) vsp -Xsram[397] sram->in sram[397]->out sram[397]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[397]->out) 0 -.nodeset V(sram[397]->outb) vsp -Xsram[398] sram->in sram[398]->out sram[398]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[398]->out) 0 -.nodeset V(sram[398]->outb) vsp -Xsram[399] sram->in sram[399]->out sram[399]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[399]->out) 0 -.nodeset V(sram[399]->outb) vsp -***** Signal mux_2level_size50[24]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[0] mux_2level_size50[24]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[1] mux_2level_size50[24]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[2] mux_2level_size50[24]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[3] mux_2level_size50[24]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[4] mux_2level_size50[24]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[5] mux_2level_size50[24]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[6] mux_2level_size50[24]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[7] mux_2level_size50[24]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[8] mux_2level_size50[24]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[9] mux_2level_size50[24]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[10] mux_2level_size50[24]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[11] mux_2level_size50[24]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[12] mux_2level_size50[24]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[13] mux_2level_size50[24]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[14] mux_2level_size50[24]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[15] mux_2level_size50[24]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[16] mux_2level_size50[24]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[17] mux_2level_size50[24]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[18] mux_2level_size50[24]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[19] mux_2level_size50[24]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[20] mux_2level_size50[24]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[21] mux_2level_size50[24]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[22] mux_2level_size50[24]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[23] mux_2level_size50[24]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[24] mux_2level_size50[24]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[25] mux_2level_size50[24]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[26] mux_2level_size50[24]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[27] mux_2level_size50[24]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[28] mux_2level_size50[24]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[29] mux_2level_size50[24]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[30] mux_2level_size50[24]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[31] mux_2level_size50[24]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[32] mux_2level_size50[24]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[33] mux_2level_size50[24]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[34] mux_2level_size50[24]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[35] mux_2level_size50[24]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[36] mux_2level_size50[24]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[37] mux_2level_size50[24]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[38] mux_2level_size50[24]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[24]->in[39] mux_2level_size50[24]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[24]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[40] mux_2level_size50[24]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[41] mux_2level_size50[24]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[42] mux_2level_size50[24]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[43] mux_2level_size50[24]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[44] mux_2level_size50[24]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[45] mux_2level_size50[24]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[46] mux_2level_size50[24]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[47] mux_2level_size50[24]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[48] mux_2level_size50[24]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[24]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[24]->in[49] mux_2level_size50[24]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[24] gvdd_mux_2level_size50[24] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[24]_in[0]_crossbar trig v(mux_2level_size50[24]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[24]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[24]_in[0]_crossbar trig v(mux_2level_size50[24]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[24]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[24]_in[0]_crossbar when v(mux_2level_size50[24]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[24]_in[0]_crossbar trig v(mux_2level_size50[24]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[24]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[24]_in[0]_crossbar when v(mux_2level_size50[24]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[24]_in[0]_crossbar trig v(mux_2level_size50[24]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[24]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[24]_leakage_power avg p(Vgvdd_mux_2level_size50[24]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[24]_in[0]_crossbar param='mux_2level_size50[24]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[24]_dynamic_power avg p(Vgvdd_mux_2level_size50[24]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[24]_energy_per_cycle param='mux_2level_size50[24]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[24]_in[0]_crossbar param='mux_2level_size50[24]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[24]_in[0]_crossbar param='dynamic_power_idle_mux50[24]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[24]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[24]) from='start_rise_idle_mux50[24]_in[0]_crossbar' to='start_rise_idle_mux50[24]_in[0]_crossbar+switch_rise_idle_mux50[24]_in[0]_crossbar' -.meas tran dynamic_fall_idle_mux50[24]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[24]) from='start_fall_idle_mux50[24]_in[0]_crossbar' to='start_fall_idle_mux50[24]_in[0]_crossbar+switch_fall_idle_mux50[24]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to24] -+ param='sum_leakage_power_mux[0to23]+leakage_idle_mux50[24]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to24] -+ param='sum_energy_per_cycle_mux[0to23]+energy_per_cycle_idle_mux50[24]_in[0]_crossbar' -Xload_inv[24]_no0 mux_2level_size50[24]->out mux_2level_size50[24]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to24] -+ param='sum_leakage_power_pb_mux[0to23]+leakage_idle_mux50[24]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to24] -+ param='sum_energy_per_cycle_pb_mux[0to23]+energy_per_cycle_idle_mux50[24]_in[0]_crossbar' -Xmux_2level_size50[25] mux_2level_size50[25]->in[0] mux_2level_size50[25]->in[1] mux_2level_size50[25]->in[2] mux_2level_size50[25]->in[3] mux_2level_size50[25]->in[4] mux_2level_size50[25]->in[5] mux_2level_size50[25]->in[6] mux_2level_size50[25]->in[7] mux_2level_size50[25]->in[8] mux_2level_size50[25]->in[9] mux_2level_size50[25]->in[10] mux_2level_size50[25]->in[11] mux_2level_size50[25]->in[12] mux_2level_size50[25]->in[13] mux_2level_size50[25]->in[14] mux_2level_size50[25]->in[15] mux_2level_size50[25]->in[16] mux_2level_size50[25]->in[17] mux_2level_size50[25]->in[18] mux_2level_size50[25]->in[19] mux_2level_size50[25]->in[20] mux_2level_size50[25]->in[21] mux_2level_size50[25]->in[22] mux_2level_size50[25]->in[23] mux_2level_size50[25]->in[24] mux_2level_size50[25]->in[25] mux_2level_size50[25]->in[26] mux_2level_size50[25]->in[27] mux_2level_size50[25]->in[28] mux_2level_size50[25]->in[29] mux_2level_size50[25]->in[30] mux_2level_size50[25]->in[31] mux_2level_size50[25]->in[32] mux_2level_size50[25]->in[33] mux_2level_size50[25]->in[34] mux_2level_size50[25]->in[35] mux_2level_size50[25]->in[36] mux_2level_size50[25]->in[37] mux_2level_size50[25]->in[38] mux_2level_size50[25]->in[39] mux_2level_size50[25]->in[40] mux_2level_size50[25]->in[41] mux_2level_size50[25]->in[42] mux_2level_size50[25]->in[43] mux_2level_size50[25]->in[44] mux_2level_size50[25]->in[45] mux_2level_size50[25]->in[46] mux_2level_size50[25]->in[47] mux_2level_size50[25]->in[48] mux_2level_size50[25]->in[49] mux_2level_size50[25]->out sram[400]->outb sram[400]->out sram[401]->out sram[401]->outb sram[402]->out sram[402]->outb sram[403]->out sram[403]->outb sram[404]->out sram[404]->outb sram[405]->out sram[405]->outb sram[406]->out sram[406]->outb sram[407]->out sram[407]->outb sram[408]->outb sram[408]->out sram[409]->out sram[409]->outb sram[410]->out sram[410]->outb sram[411]->out sram[411]->outb sram[412]->out sram[412]->outb sram[413]->out sram[413]->outb sram[414]->out sram[414]->outb sram[415]->out sram[415]->outb gvdd_mux_2level_size50[25] 0 mux_2level_size50 -***** SRAM bits for MUX[25], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[400] sram->in sram[400]->out sram[400]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[400]->out) 0 -.nodeset V(sram[400]->outb) vsp -Xsram[401] sram->in sram[401]->out sram[401]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[401]->out) 0 -.nodeset V(sram[401]->outb) vsp -Xsram[402] sram->in sram[402]->out sram[402]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[402]->out) 0 -.nodeset V(sram[402]->outb) vsp -Xsram[403] sram->in sram[403]->out sram[403]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[403]->out) 0 -.nodeset V(sram[403]->outb) vsp -Xsram[404] sram->in sram[404]->out sram[404]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[404]->out) 0 -.nodeset V(sram[404]->outb) vsp -Xsram[405] sram->in sram[405]->out sram[405]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[405]->out) 0 -.nodeset V(sram[405]->outb) vsp -Xsram[406] sram->in sram[406]->out sram[406]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[406]->out) 0 -.nodeset V(sram[406]->outb) vsp -Xsram[407] sram->in sram[407]->out sram[407]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[407]->out) 0 -.nodeset V(sram[407]->outb) vsp -Xsram[408] sram->in sram[408]->out sram[408]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[408]->out) 0 -.nodeset V(sram[408]->outb) vsp -Xsram[409] sram->in sram[409]->out sram[409]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[409]->out) 0 -.nodeset V(sram[409]->outb) vsp -Xsram[410] sram->in sram[410]->out sram[410]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[410]->out) 0 -.nodeset V(sram[410]->outb) vsp -Xsram[411] sram->in sram[411]->out sram[411]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[411]->out) 0 -.nodeset V(sram[411]->outb) vsp -Xsram[412] sram->in sram[412]->out sram[412]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[412]->out) 0 -.nodeset V(sram[412]->outb) vsp -Xsram[413] sram->in sram[413]->out sram[413]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[413]->out) 0 -.nodeset V(sram[413]->outb) vsp -Xsram[414] sram->in sram[414]->out sram[414]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[414]->out) 0 -.nodeset V(sram[414]->outb) vsp -Xsram[415] sram->in sram[415]->out sram[415]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[415]->out) 0 -.nodeset V(sram[415]->outb) vsp -***** Signal mux_2level_size50[25]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[0] mux_2level_size50[25]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[1] mux_2level_size50[25]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[2] mux_2level_size50[25]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[3] mux_2level_size50[25]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[4] mux_2level_size50[25]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[5] mux_2level_size50[25]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[6] mux_2level_size50[25]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[7] mux_2level_size50[25]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[8] mux_2level_size50[25]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[9] mux_2level_size50[25]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[10] mux_2level_size50[25]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[11] mux_2level_size50[25]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[12] mux_2level_size50[25]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[13] mux_2level_size50[25]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[14] mux_2level_size50[25]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[15] mux_2level_size50[25]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[16] mux_2level_size50[25]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[17] mux_2level_size50[25]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[18] mux_2level_size50[25]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[19] mux_2level_size50[25]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[20] mux_2level_size50[25]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[21] mux_2level_size50[25]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[22] mux_2level_size50[25]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[23] mux_2level_size50[25]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[24] mux_2level_size50[25]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[25] mux_2level_size50[25]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[26] mux_2level_size50[25]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[27] mux_2level_size50[25]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[28] mux_2level_size50[25]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[29] mux_2level_size50[25]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[30] mux_2level_size50[25]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[31] mux_2level_size50[25]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[32] mux_2level_size50[25]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[33] mux_2level_size50[25]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[34] mux_2level_size50[25]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[35] mux_2level_size50[25]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[36] mux_2level_size50[25]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[37] mux_2level_size50[25]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[38] mux_2level_size50[25]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[25]->in[39] mux_2level_size50[25]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[25]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[40] mux_2level_size50[25]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[41] mux_2level_size50[25]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[42] mux_2level_size50[25]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[43] mux_2level_size50[25]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[44] mux_2level_size50[25]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[45] mux_2level_size50[25]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[46] mux_2level_size50[25]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[47] mux_2level_size50[25]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[48] mux_2level_size50[25]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[25]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[25]->in[49] mux_2level_size50[25]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[25] gvdd_mux_2level_size50[25] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[25]_in[1]_crossbar trig v(mux_2level_size50[25]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[25]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[25]_in[1]_crossbar trig v(mux_2level_size50[25]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[25]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[25]_in[1]_crossbar when v(mux_2level_size50[25]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[25]_in[1]_crossbar trig v(mux_2level_size50[25]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[25]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[25]_in[1]_crossbar when v(mux_2level_size50[25]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[25]_in[1]_crossbar trig v(mux_2level_size50[25]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[25]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[25]_leakage_power avg p(Vgvdd_mux_2level_size50[25]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[25]_in[1]_crossbar param='mux_2level_size50[25]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[25]_dynamic_power avg p(Vgvdd_mux_2level_size50[25]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[25]_energy_per_cycle param='mux_2level_size50[25]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[25]_in[1]_crossbar param='mux_2level_size50[25]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[25]_in[1]_crossbar param='dynamic_power_idle_mux50[25]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[25]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[25]) from='start_rise_idle_mux50[25]_in[1]_crossbar' to='start_rise_idle_mux50[25]_in[1]_crossbar+switch_rise_idle_mux50[25]_in[1]_crossbar' -.meas tran dynamic_fall_idle_mux50[25]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[25]) from='start_fall_idle_mux50[25]_in[1]_crossbar' to='start_fall_idle_mux50[25]_in[1]_crossbar+switch_fall_idle_mux50[25]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to25] -+ param='sum_leakage_power_mux[0to24]+leakage_idle_mux50[25]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to25] -+ param='sum_energy_per_cycle_mux[0to24]+energy_per_cycle_idle_mux50[25]_in[1]_crossbar' -Xload_inv[25]_no0 mux_2level_size50[25]->out mux_2level_size50[25]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to25] -+ param='sum_leakage_power_pb_mux[0to24]+leakage_idle_mux50[25]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to25] -+ param='sum_energy_per_cycle_pb_mux[0to24]+energy_per_cycle_idle_mux50[25]_in[1]_crossbar' -Xmux_2level_size50[26] mux_2level_size50[26]->in[0] mux_2level_size50[26]->in[1] mux_2level_size50[26]->in[2] mux_2level_size50[26]->in[3] mux_2level_size50[26]->in[4] mux_2level_size50[26]->in[5] mux_2level_size50[26]->in[6] mux_2level_size50[26]->in[7] mux_2level_size50[26]->in[8] mux_2level_size50[26]->in[9] mux_2level_size50[26]->in[10] mux_2level_size50[26]->in[11] mux_2level_size50[26]->in[12] mux_2level_size50[26]->in[13] mux_2level_size50[26]->in[14] mux_2level_size50[26]->in[15] mux_2level_size50[26]->in[16] mux_2level_size50[26]->in[17] mux_2level_size50[26]->in[18] mux_2level_size50[26]->in[19] mux_2level_size50[26]->in[20] mux_2level_size50[26]->in[21] mux_2level_size50[26]->in[22] mux_2level_size50[26]->in[23] mux_2level_size50[26]->in[24] mux_2level_size50[26]->in[25] mux_2level_size50[26]->in[26] mux_2level_size50[26]->in[27] mux_2level_size50[26]->in[28] mux_2level_size50[26]->in[29] mux_2level_size50[26]->in[30] mux_2level_size50[26]->in[31] mux_2level_size50[26]->in[32] mux_2level_size50[26]->in[33] mux_2level_size50[26]->in[34] mux_2level_size50[26]->in[35] mux_2level_size50[26]->in[36] mux_2level_size50[26]->in[37] mux_2level_size50[26]->in[38] mux_2level_size50[26]->in[39] mux_2level_size50[26]->in[40] mux_2level_size50[26]->in[41] mux_2level_size50[26]->in[42] mux_2level_size50[26]->in[43] mux_2level_size50[26]->in[44] mux_2level_size50[26]->in[45] mux_2level_size50[26]->in[46] mux_2level_size50[26]->in[47] mux_2level_size50[26]->in[48] mux_2level_size50[26]->in[49] mux_2level_size50[26]->out sram[416]->outb sram[416]->out sram[417]->out sram[417]->outb sram[418]->out sram[418]->outb sram[419]->out sram[419]->outb sram[420]->out sram[420]->outb sram[421]->out sram[421]->outb sram[422]->out sram[422]->outb sram[423]->out sram[423]->outb sram[424]->outb sram[424]->out sram[425]->out sram[425]->outb sram[426]->out sram[426]->outb sram[427]->out sram[427]->outb sram[428]->out sram[428]->outb sram[429]->out sram[429]->outb sram[430]->out sram[430]->outb sram[431]->out sram[431]->outb gvdd_mux_2level_size50[26] 0 mux_2level_size50 -***** SRAM bits for MUX[26], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[416] sram->in sram[416]->out sram[416]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[416]->out) 0 -.nodeset V(sram[416]->outb) vsp -Xsram[417] sram->in sram[417]->out sram[417]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[417]->out) 0 -.nodeset V(sram[417]->outb) vsp -Xsram[418] sram->in sram[418]->out sram[418]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[418]->out) 0 -.nodeset V(sram[418]->outb) vsp -Xsram[419] sram->in sram[419]->out sram[419]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[419]->out) 0 -.nodeset V(sram[419]->outb) vsp -Xsram[420] sram->in sram[420]->out sram[420]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[420]->out) 0 -.nodeset V(sram[420]->outb) vsp -Xsram[421] sram->in sram[421]->out sram[421]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[421]->out) 0 -.nodeset V(sram[421]->outb) vsp -Xsram[422] sram->in sram[422]->out sram[422]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[422]->out) 0 -.nodeset V(sram[422]->outb) vsp -Xsram[423] sram->in sram[423]->out sram[423]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[423]->out) 0 -.nodeset V(sram[423]->outb) vsp -Xsram[424] sram->in sram[424]->out sram[424]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[424]->out) 0 -.nodeset V(sram[424]->outb) vsp -Xsram[425] sram->in sram[425]->out sram[425]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[425]->out) 0 -.nodeset V(sram[425]->outb) vsp -Xsram[426] sram->in sram[426]->out sram[426]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[426]->out) 0 -.nodeset V(sram[426]->outb) vsp -Xsram[427] sram->in sram[427]->out sram[427]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[427]->out) 0 -.nodeset V(sram[427]->outb) vsp -Xsram[428] sram->in sram[428]->out sram[428]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[428]->out) 0 -.nodeset V(sram[428]->outb) vsp -Xsram[429] sram->in sram[429]->out sram[429]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[429]->out) 0 -.nodeset V(sram[429]->outb) vsp -Xsram[430] sram->in sram[430]->out sram[430]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[430]->out) 0 -.nodeset V(sram[430]->outb) vsp -Xsram[431] sram->in sram[431]->out sram[431]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[431]->out) 0 -.nodeset V(sram[431]->outb) vsp -***** Signal mux_2level_size50[26]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[0] mux_2level_size50[26]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[1] mux_2level_size50[26]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[2] mux_2level_size50[26]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[3] mux_2level_size50[26]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[4] mux_2level_size50[26]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[5] mux_2level_size50[26]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[6] mux_2level_size50[26]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[7] mux_2level_size50[26]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[8] mux_2level_size50[26]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[9] mux_2level_size50[26]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[10] mux_2level_size50[26]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[11] mux_2level_size50[26]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[12] mux_2level_size50[26]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[13] mux_2level_size50[26]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[14] mux_2level_size50[26]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[15] mux_2level_size50[26]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[16] mux_2level_size50[26]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[17] mux_2level_size50[26]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[18] mux_2level_size50[26]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[19] mux_2level_size50[26]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[20] mux_2level_size50[26]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[21] mux_2level_size50[26]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[22] mux_2level_size50[26]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[23] mux_2level_size50[26]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[24] mux_2level_size50[26]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[25] mux_2level_size50[26]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[26] mux_2level_size50[26]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[27] mux_2level_size50[26]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[28] mux_2level_size50[26]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[29] mux_2level_size50[26]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[30] mux_2level_size50[26]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[31] mux_2level_size50[26]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[32] mux_2level_size50[26]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[33] mux_2level_size50[26]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[34] mux_2level_size50[26]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[35] mux_2level_size50[26]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[36] mux_2level_size50[26]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[37] mux_2level_size50[26]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[38] mux_2level_size50[26]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[26]->in[39] mux_2level_size50[26]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[26]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[40] mux_2level_size50[26]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[41] mux_2level_size50[26]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[42] mux_2level_size50[26]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[43] mux_2level_size50[26]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[44] mux_2level_size50[26]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[45] mux_2level_size50[26]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[46] mux_2level_size50[26]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[47] mux_2level_size50[26]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[48] mux_2level_size50[26]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[26]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[26]->in[49] mux_2level_size50[26]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[26] gvdd_mux_2level_size50[26] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[26]_in[2]_crossbar trig v(mux_2level_size50[26]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[26]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[26]_in[2]_crossbar trig v(mux_2level_size50[26]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[26]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[26]_in[2]_crossbar when v(mux_2level_size50[26]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[26]_in[2]_crossbar trig v(mux_2level_size50[26]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[26]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[26]_in[2]_crossbar when v(mux_2level_size50[26]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[26]_in[2]_crossbar trig v(mux_2level_size50[26]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[26]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[26]_leakage_power avg p(Vgvdd_mux_2level_size50[26]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[26]_in[2]_crossbar param='mux_2level_size50[26]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[26]_dynamic_power avg p(Vgvdd_mux_2level_size50[26]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[26]_energy_per_cycle param='mux_2level_size50[26]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[26]_in[2]_crossbar param='mux_2level_size50[26]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[26]_in[2]_crossbar param='dynamic_power_idle_mux50[26]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[26]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[26]) from='start_rise_idle_mux50[26]_in[2]_crossbar' to='start_rise_idle_mux50[26]_in[2]_crossbar+switch_rise_idle_mux50[26]_in[2]_crossbar' -.meas tran dynamic_fall_idle_mux50[26]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[26]) from='start_fall_idle_mux50[26]_in[2]_crossbar' to='start_fall_idle_mux50[26]_in[2]_crossbar+switch_fall_idle_mux50[26]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to26] -+ param='sum_leakage_power_mux[0to25]+leakage_idle_mux50[26]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to26] -+ param='sum_energy_per_cycle_mux[0to25]+energy_per_cycle_idle_mux50[26]_in[2]_crossbar' -Xload_inv[26]_no0 mux_2level_size50[26]->out mux_2level_size50[26]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to26] -+ param='sum_leakage_power_pb_mux[0to25]+leakage_idle_mux50[26]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to26] -+ param='sum_energy_per_cycle_pb_mux[0to25]+energy_per_cycle_idle_mux50[26]_in[2]_crossbar' -Xmux_2level_size50[27] mux_2level_size50[27]->in[0] mux_2level_size50[27]->in[1] mux_2level_size50[27]->in[2] mux_2level_size50[27]->in[3] mux_2level_size50[27]->in[4] mux_2level_size50[27]->in[5] mux_2level_size50[27]->in[6] mux_2level_size50[27]->in[7] mux_2level_size50[27]->in[8] mux_2level_size50[27]->in[9] mux_2level_size50[27]->in[10] mux_2level_size50[27]->in[11] mux_2level_size50[27]->in[12] mux_2level_size50[27]->in[13] mux_2level_size50[27]->in[14] mux_2level_size50[27]->in[15] mux_2level_size50[27]->in[16] mux_2level_size50[27]->in[17] mux_2level_size50[27]->in[18] mux_2level_size50[27]->in[19] mux_2level_size50[27]->in[20] mux_2level_size50[27]->in[21] mux_2level_size50[27]->in[22] mux_2level_size50[27]->in[23] mux_2level_size50[27]->in[24] mux_2level_size50[27]->in[25] mux_2level_size50[27]->in[26] mux_2level_size50[27]->in[27] mux_2level_size50[27]->in[28] mux_2level_size50[27]->in[29] mux_2level_size50[27]->in[30] mux_2level_size50[27]->in[31] mux_2level_size50[27]->in[32] mux_2level_size50[27]->in[33] mux_2level_size50[27]->in[34] mux_2level_size50[27]->in[35] mux_2level_size50[27]->in[36] mux_2level_size50[27]->in[37] mux_2level_size50[27]->in[38] mux_2level_size50[27]->in[39] mux_2level_size50[27]->in[40] mux_2level_size50[27]->in[41] mux_2level_size50[27]->in[42] mux_2level_size50[27]->in[43] mux_2level_size50[27]->in[44] mux_2level_size50[27]->in[45] mux_2level_size50[27]->in[46] mux_2level_size50[27]->in[47] mux_2level_size50[27]->in[48] mux_2level_size50[27]->in[49] mux_2level_size50[27]->out sram[432]->outb sram[432]->out sram[433]->out sram[433]->outb sram[434]->out sram[434]->outb sram[435]->out sram[435]->outb sram[436]->out sram[436]->outb sram[437]->out sram[437]->outb sram[438]->out sram[438]->outb sram[439]->out sram[439]->outb sram[440]->outb sram[440]->out sram[441]->out sram[441]->outb sram[442]->out sram[442]->outb sram[443]->out sram[443]->outb sram[444]->out sram[444]->outb sram[445]->out sram[445]->outb sram[446]->out sram[446]->outb sram[447]->out sram[447]->outb gvdd_mux_2level_size50[27] 0 mux_2level_size50 -***** SRAM bits for MUX[27], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[432] sram->in sram[432]->out sram[432]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[432]->out) 0 -.nodeset V(sram[432]->outb) vsp -Xsram[433] sram->in sram[433]->out sram[433]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[433]->out) 0 -.nodeset V(sram[433]->outb) vsp -Xsram[434] sram->in sram[434]->out sram[434]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[434]->out) 0 -.nodeset V(sram[434]->outb) vsp -Xsram[435] sram->in sram[435]->out sram[435]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[435]->out) 0 -.nodeset V(sram[435]->outb) vsp -Xsram[436] sram->in sram[436]->out sram[436]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[436]->out) 0 -.nodeset V(sram[436]->outb) vsp -Xsram[437] sram->in sram[437]->out sram[437]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[437]->out) 0 -.nodeset V(sram[437]->outb) vsp -Xsram[438] sram->in sram[438]->out sram[438]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[438]->out) 0 -.nodeset V(sram[438]->outb) vsp -Xsram[439] sram->in sram[439]->out sram[439]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[439]->out) 0 -.nodeset V(sram[439]->outb) vsp -Xsram[440] sram->in sram[440]->out sram[440]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[440]->out) 0 -.nodeset V(sram[440]->outb) vsp -Xsram[441] sram->in sram[441]->out sram[441]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[441]->out) 0 -.nodeset V(sram[441]->outb) vsp -Xsram[442] sram->in sram[442]->out sram[442]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[442]->out) 0 -.nodeset V(sram[442]->outb) vsp -Xsram[443] sram->in sram[443]->out sram[443]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[443]->out) 0 -.nodeset V(sram[443]->outb) vsp -Xsram[444] sram->in sram[444]->out sram[444]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[444]->out) 0 -.nodeset V(sram[444]->outb) vsp -Xsram[445] sram->in sram[445]->out sram[445]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[445]->out) 0 -.nodeset V(sram[445]->outb) vsp -Xsram[446] sram->in sram[446]->out sram[446]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[446]->out) 0 -.nodeset V(sram[446]->outb) vsp -Xsram[447] sram->in sram[447]->out sram[447]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[447]->out) 0 -.nodeset V(sram[447]->outb) vsp -***** Signal mux_2level_size50[27]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[0] mux_2level_size50[27]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[1] mux_2level_size50[27]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[2] mux_2level_size50[27]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[3] mux_2level_size50[27]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[4] mux_2level_size50[27]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[5] mux_2level_size50[27]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[6] mux_2level_size50[27]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[7] mux_2level_size50[27]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[8] mux_2level_size50[27]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[9] mux_2level_size50[27]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[10] mux_2level_size50[27]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[11] mux_2level_size50[27]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[12] mux_2level_size50[27]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[13] mux_2level_size50[27]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[14] mux_2level_size50[27]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[15] mux_2level_size50[27]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[16] mux_2level_size50[27]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[17] mux_2level_size50[27]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[18] mux_2level_size50[27]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[19] mux_2level_size50[27]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[20] mux_2level_size50[27]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[21] mux_2level_size50[27]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[22] mux_2level_size50[27]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[23] mux_2level_size50[27]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[24] mux_2level_size50[27]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[25] mux_2level_size50[27]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[26] mux_2level_size50[27]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[27] mux_2level_size50[27]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[28] mux_2level_size50[27]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[29] mux_2level_size50[27]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[30] mux_2level_size50[27]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[31] mux_2level_size50[27]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[32] mux_2level_size50[27]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[33] mux_2level_size50[27]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[34] mux_2level_size50[27]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[35] mux_2level_size50[27]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[36] mux_2level_size50[27]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[37] mux_2level_size50[27]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[38] mux_2level_size50[27]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[27]->in[39] mux_2level_size50[27]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[27]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[40] mux_2level_size50[27]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[41] mux_2level_size50[27]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[42] mux_2level_size50[27]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[43] mux_2level_size50[27]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[44] mux_2level_size50[27]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[45] mux_2level_size50[27]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[46] mux_2level_size50[27]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[47] mux_2level_size50[27]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[48] mux_2level_size50[27]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[27]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[27]->in[49] mux_2level_size50[27]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[27] gvdd_mux_2level_size50[27] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[27]_in[3]_crossbar trig v(mux_2level_size50[27]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[27]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[27]_in[3]_crossbar trig v(mux_2level_size50[27]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[27]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[27]_in[3]_crossbar when v(mux_2level_size50[27]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[27]_in[3]_crossbar trig v(mux_2level_size50[27]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[27]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[27]_in[3]_crossbar when v(mux_2level_size50[27]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[27]_in[3]_crossbar trig v(mux_2level_size50[27]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[27]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[27]_leakage_power avg p(Vgvdd_mux_2level_size50[27]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[27]_in[3]_crossbar param='mux_2level_size50[27]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[27]_dynamic_power avg p(Vgvdd_mux_2level_size50[27]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[27]_energy_per_cycle param='mux_2level_size50[27]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[27]_in[3]_crossbar param='mux_2level_size50[27]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[27]_in[3]_crossbar param='dynamic_power_idle_mux50[27]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[27]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[27]) from='start_rise_idle_mux50[27]_in[3]_crossbar' to='start_rise_idle_mux50[27]_in[3]_crossbar+switch_rise_idle_mux50[27]_in[3]_crossbar' -.meas tran dynamic_fall_idle_mux50[27]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[27]) from='start_fall_idle_mux50[27]_in[3]_crossbar' to='start_fall_idle_mux50[27]_in[3]_crossbar+switch_fall_idle_mux50[27]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to27] -+ param='sum_leakage_power_mux[0to26]+leakage_idle_mux50[27]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to27] -+ param='sum_energy_per_cycle_mux[0to26]+energy_per_cycle_idle_mux50[27]_in[3]_crossbar' -Xload_inv[27]_no0 mux_2level_size50[27]->out mux_2level_size50[27]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to27] -+ param='sum_leakage_power_pb_mux[0to26]+leakage_idle_mux50[27]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to27] -+ param='sum_energy_per_cycle_pb_mux[0to26]+energy_per_cycle_idle_mux50[27]_in[3]_crossbar' -Xmux_2level_size50[28] mux_2level_size50[28]->in[0] mux_2level_size50[28]->in[1] mux_2level_size50[28]->in[2] mux_2level_size50[28]->in[3] mux_2level_size50[28]->in[4] mux_2level_size50[28]->in[5] mux_2level_size50[28]->in[6] mux_2level_size50[28]->in[7] mux_2level_size50[28]->in[8] mux_2level_size50[28]->in[9] mux_2level_size50[28]->in[10] mux_2level_size50[28]->in[11] mux_2level_size50[28]->in[12] mux_2level_size50[28]->in[13] mux_2level_size50[28]->in[14] mux_2level_size50[28]->in[15] mux_2level_size50[28]->in[16] mux_2level_size50[28]->in[17] mux_2level_size50[28]->in[18] mux_2level_size50[28]->in[19] mux_2level_size50[28]->in[20] mux_2level_size50[28]->in[21] mux_2level_size50[28]->in[22] mux_2level_size50[28]->in[23] mux_2level_size50[28]->in[24] mux_2level_size50[28]->in[25] mux_2level_size50[28]->in[26] mux_2level_size50[28]->in[27] mux_2level_size50[28]->in[28] mux_2level_size50[28]->in[29] mux_2level_size50[28]->in[30] mux_2level_size50[28]->in[31] mux_2level_size50[28]->in[32] mux_2level_size50[28]->in[33] mux_2level_size50[28]->in[34] mux_2level_size50[28]->in[35] mux_2level_size50[28]->in[36] mux_2level_size50[28]->in[37] mux_2level_size50[28]->in[38] mux_2level_size50[28]->in[39] mux_2level_size50[28]->in[40] mux_2level_size50[28]->in[41] mux_2level_size50[28]->in[42] mux_2level_size50[28]->in[43] mux_2level_size50[28]->in[44] mux_2level_size50[28]->in[45] mux_2level_size50[28]->in[46] mux_2level_size50[28]->in[47] mux_2level_size50[28]->in[48] mux_2level_size50[28]->in[49] mux_2level_size50[28]->out sram[448]->outb sram[448]->out sram[449]->out sram[449]->outb sram[450]->out sram[450]->outb sram[451]->out sram[451]->outb sram[452]->out sram[452]->outb sram[453]->out sram[453]->outb sram[454]->out sram[454]->outb sram[455]->out sram[455]->outb sram[456]->outb sram[456]->out sram[457]->out sram[457]->outb sram[458]->out sram[458]->outb sram[459]->out sram[459]->outb sram[460]->out sram[460]->outb sram[461]->out sram[461]->outb sram[462]->out sram[462]->outb sram[463]->out sram[463]->outb gvdd_mux_2level_size50[28] 0 mux_2level_size50 -***** SRAM bits for MUX[28], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[448] sram->in sram[448]->out sram[448]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[448]->out) 0 -.nodeset V(sram[448]->outb) vsp -Xsram[449] sram->in sram[449]->out sram[449]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[449]->out) 0 -.nodeset V(sram[449]->outb) vsp -Xsram[450] sram->in sram[450]->out sram[450]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[450]->out) 0 -.nodeset V(sram[450]->outb) vsp -Xsram[451] sram->in sram[451]->out sram[451]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[451]->out) 0 -.nodeset V(sram[451]->outb) vsp -Xsram[452] sram->in sram[452]->out sram[452]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[452]->out) 0 -.nodeset V(sram[452]->outb) vsp -Xsram[453] sram->in sram[453]->out sram[453]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[453]->out) 0 -.nodeset V(sram[453]->outb) vsp -Xsram[454] sram->in sram[454]->out sram[454]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[454]->out) 0 -.nodeset V(sram[454]->outb) vsp -Xsram[455] sram->in sram[455]->out sram[455]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[455]->out) 0 -.nodeset V(sram[455]->outb) vsp -Xsram[456] sram->in sram[456]->out sram[456]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[456]->out) 0 -.nodeset V(sram[456]->outb) vsp -Xsram[457] sram->in sram[457]->out sram[457]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[457]->out) 0 -.nodeset V(sram[457]->outb) vsp -Xsram[458] sram->in sram[458]->out sram[458]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[458]->out) 0 -.nodeset V(sram[458]->outb) vsp -Xsram[459] sram->in sram[459]->out sram[459]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[459]->out) 0 -.nodeset V(sram[459]->outb) vsp -Xsram[460] sram->in sram[460]->out sram[460]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[460]->out) 0 -.nodeset V(sram[460]->outb) vsp -Xsram[461] sram->in sram[461]->out sram[461]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[461]->out) 0 -.nodeset V(sram[461]->outb) vsp -Xsram[462] sram->in sram[462]->out sram[462]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[462]->out) 0 -.nodeset V(sram[462]->outb) vsp -Xsram[463] sram->in sram[463]->out sram[463]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[463]->out) 0 -.nodeset V(sram[463]->outb) vsp -***** Signal mux_2level_size50[28]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[0] mux_2level_size50[28]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[1] mux_2level_size50[28]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[2] mux_2level_size50[28]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[3] mux_2level_size50[28]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[4] mux_2level_size50[28]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[5] mux_2level_size50[28]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[6] mux_2level_size50[28]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[7] mux_2level_size50[28]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[8] mux_2level_size50[28]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[9] mux_2level_size50[28]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[10] mux_2level_size50[28]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[11] mux_2level_size50[28]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[12] mux_2level_size50[28]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[13] mux_2level_size50[28]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[14] mux_2level_size50[28]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[15] mux_2level_size50[28]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[16] mux_2level_size50[28]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[17] mux_2level_size50[28]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[18] mux_2level_size50[28]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[19] mux_2level_size50[28]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[20] mux_2level_size50[28]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[21] mux_2level_size50[28]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[22] mux_2level_size50[28]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[23] mux_2level_size50[28]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[24] mux_2level_size50[28]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[25] mux_2level_size50[28]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[26] mux_2level_size50[28]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[27] mux_2level_size50[28]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[28] mux_2level_size50[28]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[29] mux_2level_size50[28]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[30] mux_2level_size50[28]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[31] mux_2level_size50[28]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[32] mux_2level_size50[28]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[33] mux_2level_size50[28]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[34] mux_2level_size50[28]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[35] mux_2level_size50[28]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[36] mux_2level_size50[28]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[37] mux_2level_size50[28]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[38] mux_2level_size50[28]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[28]->in[39] mux_2level_size50[28]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[28]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[40] mux_2level_size50[28]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[41] mux_2level_size50[28]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[42] mux_2level_size50[28]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[43] mux_2level_size50[28]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[44] mux_2level_size50[28]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[45] mux_2level_size50[28]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[46] mux_2level_size50[28]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[47] mux_2level_size50[28]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[48] mux_2level_size50[28]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[28]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[28]->in[49] mux_2level_size50[28]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[28] gvdd_mux_2level_size50[28] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[28]_in[4]_crossbar trig v(mux_2level_size50[28]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[28]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[28]_in[4]_crossbar trig v(mux_2level_size50[28]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[28]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[28]_in[4]_crossbar when v(mux_2level_size50[28]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[28]_in[4]_crossbar trig v(mux_2level_size50[28]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[28]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[28]_in[4]_crossbar when v(mux_2level_size50[28]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[28]_in[4]_crossbar trig v(mux_2level_size50[28]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[28]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[28]_leakage_power avg p(Vgvdd_mux_2level_size50[28]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[28]_in[4]_crossbar param='mux_2level_size50[28]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[28]_dynamic_power avg p(Vgvdd_mux_2level_size50[28]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[28]_energy_per_cycle param='mux_2level_size50[28]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[28]_in[4]_crossbar param='mux_2level_size50[28]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[28]_in[4]_crossbar param='dynamic_power_idle_mux50[28]_in[4]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[28]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[28]) from='start_rise_idle_mux50[28]_in[4]_crossbar' to='start_rise_idle_mux50[28]_in[4]_crossbar+switch_rise_idle_mux50[28]_in[4]_crossbar' -.meas tran dynamic_fall_idle_mux50[28]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[28]) from='start_fall_idle_mux50[28]_in[4]_crossbar' to='start_fall_idle_mux50[28]_in[4]_crossbar+switch_fall_idle_mux50[28]_in[4]_crossbar' -.meas tran sum_leakage_power_mux[0to28] -+ param='sum_leakage_power_mux[0to27]+leakage_idle_mux50[28]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to28] -+ param='sum_energy_per_cycle_mux[0to27]+energy_per_cycle_idle_mux50[28]_in[4]_crossbar' -Xload_inv[28]_no0 mux_2level_size50[28]->out mux_2level_size50[28]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to28] -+ param='sum_leakage_power_pb_mux[0to27]+leakage_idle_mux50[28]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to28] -+ param='sum_energy_per_cycle_pb_mux[0to27]+energy_per_cycle_idle_mux50[28]_in[4]_crossbar' -Xmux_2level_size50[29] mux_2level_size50[29]->in[0] mux_2level_size50[29]->in[1] mux_2level_size50[29]->in[2] mux_2level_size50[29]->in[3] mux_2level_size50[29]->in[4] mux_2level_size50[29]->in[5] mux_2level_size50[29]->in[6] mux_2level_size50[29]->in[7] mux_2level_size50[29]->in[8] mux_2level_size50[29]->in[9] mux_2level_size50[29]->in[10] mux_2level_size50[29]->in[11] mux_2level_size50[29]->in[12] mux_2level_size50[29]->in[13] mux_2level_size50[29]->in[14] mux_2level_size50[29]->in[15] mux_2level_size50[29]->in[16] mux_2level_size50[29]->in[17] mux_2level_size50[29]->in[18] mux_2level_size50[29]->in[19] mux_2level_size50[29]->in[20] mux_2level_size50[29]->in[21] mux_2level_size50[29]->in[22] mux_2level_size50[29]->in[23] mux_2level_size50[29]->in[24] mux_2level_size50[29]->in[25] mux_2level_size50[29]->in[26] mux_2level_size50[29]->in[27] mux_2level_size50[29]->in[28] mux_2level_size50[29]->in[29] mux_2level_size50[29]->in[30] mux_2level_size50[29]->in[31] mux_2level_size50[29]->in[32] mux_2level_size50[29]->in[33] mux_2level_size50[29]->in[34] mux_2level_size50[29]->in[35] mux_2level_size50[29]->in[36] mux_2level_size50[29]->in[37] mux_2level_size50[29]->in[38] mux_2level_size50[29]->in[39] mux_2level_size50[29]->in[40] mux_2level_size50[29]->in[41] mux_2level_size50[29]->in[42] mux_2level_size50[29]->in[43] mux_2level_size50[29]->in[44] mux_2level_size50[29]->in[45] mux_2level_size50[29]->in[46] mux_2level_size50[29]->in[47] mux_2level_size50[29]->in[48] mux_2level_size50[29]->in[49] mux_2level_size50[29]->out sram[464]->outb sram[464]->out sram[465]->out sram[465]->outb sram[466]->out sram[466]->outb sram[467]->out sram[467]->outb sram[468]->out sram[468]->outb sram[469]->out sram[469]->outb sram[470]->out sram[470]->outb sram[471]->out sram[471]->outb sram[472]->outb sram[472]->out sram[473]->out sram[473]->outb sram[474]->out sram[474]->outb sram[475]->out sram[475]->outb sram[476]->out sram[476]->outb sram[477]->out sram[477]->outb sram[478]->out sram[478]->outb sram[479]->out sram[479]->outb gvdd_mux_2level_size50[29] 0 mux_2level_size50 -***** SRAM bits for MUX[29], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[464] sram->in sram[464]->out sram[464]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[464]->out) 0 -.nodeset V(sram[464]->outb) vsp -Xsram[465] sram->in sram[465]->out sram[465]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[465]->out) 0 -.nodeset V(sram[465]->outb) vsp -Xsram[466] sram->in sram[466]->out sram[466]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[466]->out) 0 -.nodeset V(sram[466]->outb) vsp -Xsram[467] sram->in sram[467]->out sram[467]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[467]->out) 0 -.nodeset V(sram[467]->outb) vsp -Xsram[468] sram->in sram[468]->out sram[468]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[468]->out) 0 -.nodeset V(sram[468]->outb) vsp -Xsram[469] sram->in sram[469]->out sram[469]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[469]->out) 0 -.nodeset V(sram[469]->outb) vsp -Xsram[470] sram->in sram[470]->out sram[470]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[470]->out) 0 -.nodeset V(sram[470]->outb) vsp -Xsram[471] sram->in sram[471]->out sram[471]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[471]->out) 0 -.nodeset V(sram[471]->outb) vsp -Xsram[472] sram->in sram[472]->out sram[472]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[472]->out) 0 -.nodeset V(sram[472]->outb) vsp -Xsram[473] sram->in sram[473]->out sram[473]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[473]->out) 0 -.nodeset V(sram[473]->outb) vsp -Xsram[474] sram->in sram[474]->out sram[474]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[474]->out) 0 -.nodeset V(sram[474]->outb) vsp -Xsram[475] sram->in sram[475]->out sram[475]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[475]->out) 0 -.nodeset V(sram[475]->outb) vsp -Xsram[476] sram->in sram[476]->out sram[476]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[476]->out) 0 -.nodeset V(sram[476]->outb) vsp -Xsram[477] sram->in sram[477]->out sram[477]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[477]->out) 0 -.nodeset V(sram[477]->outb) vsp -Xsram[478] sram->in sram[478]->out sram[478]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[478]->out) 0 -.nodeset V(sram[478]->outb) vsp -Xsram[479] sram->in sram[479]->out sram[479]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[479]->out) 0 -.nodeset V(sram[479]->outb) vsp -***** Signal mux_2level_size50[29]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[0] mux_2level_size50[29]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[1] mux_2level_size50[29]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[2] mux_2level_size50[29]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[3] mux_2level_size50[29]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[4] mux_2level_size50[29]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[5] mux_2level_size50[29]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[6] mux_2level_size50[29]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[7] mux_2level_size50[29]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[8] mux_2level_size50[29]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[9] mux_2level_size50[29]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[10] mux_2level_size50[29]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[11] mux_2level_size50[29]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[12] mux_2level_size50[29]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[13] mux_2level_size50[29]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[14] mux_2level_size50[29]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[15] mux_2level_size50[29]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[16] mux_2level_size50[29]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[17] mux_2level_size50[29]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[18] mux_2level_size50[29]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[19] mux_2level_size50[29]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[20] mux_2level_size50[29]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[21] mux_2level_size50[29]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[22] mux_2level_size50[29]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[23] mux_2level_size50[29]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[24] mux_2level_size50[29]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[25] mux_2level_size50[29]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[26] mux_2level_size50[29]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[27] mux_2level_size50[29]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[28] mux_2level_size50[29]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[29] mux_2level_size50[29]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[30] mux_2level_size50[29]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[31] mux_2level_size50[29]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[32] mux_2level_size50[29]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[33] mux_2level_size50[29]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[34] mux_2level_size50[29]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[35] mux_2level_size50[29]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[36] mux_2level_size50[29]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[37] mux_2level_size50[29]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[38] mux_2level_size50[29]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[29]->in[39] mux_2level_size50[29]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[29]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[40] mux_2level_size50[29]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[41] mux_2level_size50[29]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[42] mux_2level_size50[29]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[43] mux_2level_size50[29]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[44] mux_2level_size50[29]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[45] mux_2level_size50[29]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[46] mux_2level_size50[29]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[47] mux_2level_size50[29]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[48] mux_2level_size50[29]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[29]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[29]->in[49] mux_2level_size50[29]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[29] gvdd_mux_2level_size50[29] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[29]_in[5]_crossbar trig v(mux_2level_size50[29]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[29]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[29]_in[5]_crossbar trig v(mux_2level_size50[29]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[29]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[29]_in[5]_crossbar when v(mux_2level_size50[29]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[29]_in[5]_crossbar trig v(mux_2level_size50[29]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[29]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[29]_in[5]_crossbar when v(mux_2level_size50[29]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[29]_in[5]_crossbar trig v(mux_2level_size50[29]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[29]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[29]_leakage_power avg p(Vgvdd_mux_2level_size50[29]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[29]_in[5]_crossbar param='mux_2level_size50[29]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[29]_dynamic_power avg p(Vgvdd_mux_2level_size50[29]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[29]_energy_per_cycle param='mux_2level_size50[29]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[29]_in[5]_crossbar param='mux_2level_size50[29]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[29]_in[5]_crossbar param='dynamic_power_idle_mux50[29]_in[5]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[29]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[29]) from='start_rise_idle_mux50[29]_in[5]_crossbar' to='start_rise_idle_mux50[29]_in[5]_crossbar+switch_rise_idle_mux50[29]_in[5]_crossbar' -.meas tran dynamic_fall_idle_mux50[29]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[29]) from='start_fall_idle_mux50[29]_in[5]_crossbar' to='start_fall_idle_mux50[29]_in[5]_crossbar+switch_fall_idle_mux50[29]_in[5]_crossbar' -.meas tran sum_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to28]+leakage_idle_mux50[29]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to28]+energy_per_cycle_idle_mux50[29]_in[5]_crossbar' -Xload_inv[29]_no0 mux_2level_size50[29]->out mux_2level_size50[29]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to29] -+ param='sum_leakage_power_pb_mux[0to28]+leakage_idle_mux50[29]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to29] -+ param='sum_energy_per_cycle_pb_mux[0to28]+energy_per_cycle_idle_mux50[29]_in[5]_crossbar' -Xmux_2level_size50[30] mux_2level_size50[30]->in[0] mux_2level_size50[30]->in[1] mux_2level_size50[30]->in[2] mux_2level_size50[30]->in[3] mux_2level_size50[30]->in[4] mux_2level_size50[30]->in[5] mux_2level_size50[30]->in[6] mux_2level_size50[30]->in[7] mux_2level_size50[30]->in[8] mux_2level_size50[30]->in[9] mux_2level_size50[30]->in[10] mux_2level_size50[30]->in[11] mux_2level_size50[30]->in[12] mux_2level_size50[30]->in[13] mux_2level_size50[30]->in[14] mux_2level_size50[30]->in[15] mux_2level_size50[30]->in[16] mux_2level_size50[30]->in[17] mux_2level_size50[30]->in[18] mux_2level_size50[30]->in[19] mux_2level_size50[30]->in[20] mux_2level_size50[30]->in[21] mux_2level_size50[30]->in[22] mux_2level_size50[30]->in[23] mux_2level_size50[30]->in[24] mux_2level_size50[30]->in[25] mux_2level_size50[30]->in[26] mux_2level_size50[30]->in[27] mux_2level_size50[30]->in[28] mux_2level_size50[30]->in[29] mux_2level_size50[30]->in[30] mux_2level_size50[30]->in[31] mux_2level_size50[30]->in[32] mux_2level_size50[30]->in[33] mux_2level_size50[30]->in[34] mux_2level_size50[30]->in[35] mux_2level_size50[30]->in[36] mux_2level_size50[30]->in[37] mux_2level_size50[30]->in[38] mux_2level_size50[30]->in[39] mux_2level_size50[30]->in[40] mux_2level_size50[30]->in[41] mux_2level_size50[30]->in[42] mux_2level_size50[30]->in[43] mux_2level_size50[30]->in[44] mux_2level_size50[30]->in[45] mux_2level_size50[30]->in[46] mux_2level_size50[30]->in[47] mux_2level_size50[30]->in[48] mux_2level_size50[30]->in[49] mux_2level_size50[30]->out sram[480]->outb sram[480]->out sram[481]->out sram[481]->outb sram[482]->out sram[482]->outb sram[483]->out sram[483]->outb sram[484]->out sram[484]->outb sram[485]->out sram[485]->outb sram[486]->out sram[486]->outb sram[487]->out sram[487]->outb sram[488]->outb sram[488]->out sram[489]->out sram[489]->outb sram[490]->out sram[490]->outb sram[491]->out sram[491]->outb sram[492]->out sram[492]->outb sram[493]->out sram[493]->outb sram[494]->out sram[494]->outb sram[495]->out sram[495]->outb gvdd_mux_2level_size50[30] 0 mux_2level_size50 -***** SRAM bits for MUX[30], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[480] sram->in sram[480]->out sram[480]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[480]->out) 0 -.nodeset V(sram[480]->outb) vsp -Xsram[481] sram->in sram[481]->out sram[481]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[481]->out) 0 -.nodeset V(sram[481]->outb) vsp -Xsram[482] sram->in sram[482]->out sram[482]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[482]->out) 0 -.nodeset V(sram[482]->outb) vsp -Xsram[483] sram->in sram[483]->out sram[483]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[483]->out) 0 -.nodeset V(sram[483]->outb) vsp -Xsram[484] sram->in sram[484]->out sram[484]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[484]->out) 0 -.nodeset V(sram[484]->outb) vsp -Xsram[485] sram->in sram[485]->out sram[485]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[485]->out) 0 -.nodeset V(sram[485]->outb) vsp -Xsram[486] sram->in sram[486]->out sram[486]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[486]->out) 0 -.nodeset V(sram[486]->outb) vsp -Xsram[487] sram->in sram[487]->out sram[487]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[487]->out) 0 -.nodeset V(sram[487]->outb) vsp -Xsram[488] sram->in sram[488]->out sram[488]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[488]->out) 0 -.nodeset V(sram[488]->outb) vsp -Xsram[489] sram->in sram[489]->out sram[489]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[489]->out) 0 -.nodeset V(sram[489]->outb) vsp -Xsram[490] sram->in sram[490]->out sram[490]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[490]->out) 0 -.nodeset V(sram[490]->outb) vsp -Xsram[491] sram->in sram[491]->out sram[491]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[491]->out) 0 -.nodeset V(sram[491]->outb) vsp -Xsram[492] sram->in sram[492]->out sram[492]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[492]->out) 0 -.nodeset V(sram[492]->outb) vsp -Xsram[493] sram->in sram[493]->out sram[493]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[493]->out) 0 -.nodeset V(sram[493]->outb) vsp -Xsram[494] sram->in sram[494]->out sram[494]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[494]->out) 0 -.nodeset V(sram[494]->outb) vsp -Xsram[495] sram->in sram[495]->out sram[495]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[495]->out) 0 -.nodeset V(sram[495]->outb) vsp -***** Signal mux_2level_size50[30]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[0] mux_2level_size50[30]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[1] mux_2level_size50[30]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[2] mux_2level_size50[30]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[3] mux_2level_size50[30]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[4] mux_2level_size50[30]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[5] mux_2level_size50[30]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[6] mux_2level_size50[30]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[7] mux_2level_size50[30]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[8] mux_2level_size50[30]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[9] mux_2level_size50[30]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[10] mux_2level_size50[30]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[11] mux_2level_size50[30]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[12] mux_2level_size50[30]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[13] mux_2level_size50[30]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[14] mux_2level_size50[30]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[15] mux_2level_size50[30]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[16] mux_2level_size50[30]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[17] mux_2level_size50[30]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[18] mux_2level_size50[30]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[19] mux_2level_size50[30]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[20] mux_2level_size50[30]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[21] mux_2level_size50[30]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[22] mux_2level_size50[30]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[23] mux_2level_size50[30]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[24] mux_2level_size50[30]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[25] mux_2level_size50[30]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[26] mux_2level_size50[30]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[27] mux_2level_size50[30]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[28] mux_2level_size50[30]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[29] mux_2level_size50[30]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[30] mux_2level_size50[30]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[31] mux_2level_size50[30]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[32] mux_2level_size50[30]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[33] mux_2level_size50[30]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[34] mux_2level_size50[30]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[35] mux_2level_size50[30]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[36] mux_2level_size50[30]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[37] mux_2level_size50[30]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[38] mux_2level_size50[30]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[30]->in[39] mux_2level_size50[30]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[30]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[40] mux_2level_size50[30]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[41] mux_2level_size50[30]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[42] mux_2level_size50[30]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[43] mux_2level_size50[30]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[44] mux_2level_size50[30]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[45] mux_2level_size50[30]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[46] mux_2level_size50[30]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[47] mux_2level_size50[30]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[48] mux_2level_size50[30]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[30]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[30]->in[49] mux_2level_size50[30]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[30] gvdd_mux_2level_size50[30] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[30]_in[0]_crossbar trig v(mux_2level_size50[30]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[30]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[30]_in[0]_crossbar trig v(mux_2level_size50[30]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[30]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[30]_in[0]_crossbar when v(mux_2level_size50[30]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[30]_in[0]_crossbar trig v(mux_2level_size50[30]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[30]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[30]_in[0]_crossbar when v(mux_2level_size50[30]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[30]_in[0]_crossbar trig v(mux_2level_size50[30]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[30]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[30]_leakage_power avg p(Vgvdd_mux_2level_size50[30]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[30]_in[0]_crossbar param='mux_2level_size50[30]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[30]_dynamic_power avg p(Vgvdd_mux_2level_size50[30]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[30]_energy_per_cycle param='mux_2level_size50[30]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[30]_in[0]_crossbar param='mux_2level_size50[30]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[30]_in[0]_crossbar param='dynamic_power_idle_mux50[30]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[30]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[30]) from='start_rise_idle_mux50[30]_in[0]_crossbar' to='start_rise_idle_mux50[30]_in[0]_crossbar+switch_rise_idle_mux50[30]_in[0]_crossbar' -.meas tran dynamic_fall_idle_mux50[30]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[30]) from='start_fall_idle_mux50[30]_in[0]_crossbar' to='start_fall_idle_mux50[30]_in[0]_crossbar+switch_fall_idle_mux50[30]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to30] -+ param='sum_leakage_power_mux[0to29]+leakage_idle_mux50[30]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to30] -+ param='sum_energy_per_cycle_mux[0to29]+energy_per_cycle_idle_mux50[30]_in[0]_crossbar' -Xload_inv[30]_no0 mux_2level_size50[30]->out mux_2level_size50[30]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to30] -+ param='sum_leakage_power_pb_mux[0to29]+leakage_idle_mux50[30]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to30] -+ param='sum_energy_per_cycle_pb_mux[0to29]+energy_per_cycle_idle_mux50[30]_in[0]_crossbar' -Xmux_2level_size50[31] mux_2level_size50[31]->in[0] mux_2level_size50[31]->in[1] mux_2level_size50[31]->in[2] mux_2level_size50[31]->in[3] mux_2level_size50[31]->in[4] mux_2level_size50[31]->in[5] mux_2level_size50[31]->in[6] mux_2level_size50[31]->in[7] mux_2level_size50[31]->in[8] mux_2level_size50[31]->in[9] mux_2level_size50[31]->in[10] mux_2level_size50[31]->in[11] mux_2level_size50[31]->in[12] mux_2level_size50[31]->in[13] mux_2level_size50[31]->in[14] mux_2level_size50[31]->in[15] mux_2level_size50[31]->in[16] mux_2level_size50[31]->in[17] mux_2level_size50[31]->in[18] mux_2level_size50[31]->in[19] mux_2level_size50[31]->in[20] mux_2level_size50[31]->in[21] mux_2level_size50[31]->in[22] mux_2level_size50[31]->in[23] mux_2level_size50[31]->in[24] mux_2level_size50[31]->in[25] mux_2level_size50[31]->in[26] mux_2level_size50[31]->in[27] mux_2level_size50[31]->in[28] mux_2level_size50[31]->in[29] mux_2level_size50[31]->in[30] mux_2level_size50[31]->in[31] mux_2level_size50[31]->in[32] mux_2level_size50[31]->in[33] mux_2level_size50[31]->in[34] mux_2level_size50[31]->in[35] mux_2level_size50[31]->in[36] mux_2level_size50[31]->in[37] mux_2level_size50[31]->in[38] mux_2level_size50[31]->in[39] mux_2level_size50[31]->in[40] mux_2level_size50[31]->in[41] mux_2level_size50[31]->in[42] mux_2level_size50[31]->in[43] mux_2level_size50[31]->in[44] mux_2level_size50[31]->in[45] mux_2level_size50[31]->in[46] mux_2level_size50[31]->in[47] mux_2level_size50[31]->in[48] mux_2level_size50[31]->in[49] mux_2level_size50[31]->out sram[496]->outb sram[496]->out sram[497]->out sram[497]->outb sram[498]->out sram[498]->outb sram[499]->out sram[499]->outb sram[500]->out sram[500]->outb sram[501]->out sram[501]->outb sram[502]->out sram[502]->outb sram[503]->out sram[503]->outb sram[504]->outb sram[504]->out sram[505]->out sram[505]->outb sram[506]->out sram[506]->outb sram[507]->out sram[507]->outb sram[508]->out sram[508]->outb sram[509]->out sram[509]->outb sram[510]->out sram[510]->outb sram[511]->out sram[511]->outb gvdd_mux_2level_size50[31] 0 mux_2level_size50 -***** SRAM bits for MUX[31], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[496] sram->in sram[496]->out sram[496]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[496]->out) 0 -.nodeset V(sram[496]->outb) vsp -Xsram[497] sram->in sram[497]->out sram[497]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[497]->out) 0 -.nodeset V(sram[497]->outb) vsp -Xsram[498] sram->in sram[498]->out sram[498]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[498]->out) 0 -.nodeset V(sram[498]->outb) vsp -Xsram[499] sram->in sram[499]->out sram[499]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[499]->out) 0 -.nodeset V(sram[499]->outb) vsp -Xsram[500] sram->in sram[500]->out sram[500]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[500]->out) 0 -.nodeset V(sram[500]->outb) vsp -Xsram[501] sram->in sram[501]->out sram[501]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[501]->out) 0 -.nodeset V(sram[501]->outb) vsp -Xsram[502] sram->in sram[502]->out sram[502]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[502]->out) 0 -.nodeset V(sram[502]->outb) vsp -Xsram[503] sram->in sram[503]->out sram[503]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[503]->out) 0 -.nodeset V(sram[503]->outb) vsp -Xsram[504] sram->in sram[504]->out sram[504]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[504]->out) 0 -.nodeset V(sram[504]->outb) vsp -Xsram[505] sram->in sram[505]->out sram[505]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[505]->out) 0 -.nodeset V(sram[505]->outb) vsp -Xsram[506] sram->in sram[506]->out sram[506]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[506]->out) 0 -.nodeset V(sram[506]->outb) vsp -Xsram[507] sram->in sram[507]->out sram[507]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[507]->out) 0 -.nodeset V(sram[507]->outb) vsp -Xsram[508] sram->in sram[508]->out sram[508]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[508]->out) 0 -.nodeset V(sram[508]->outb) vsp -Xsram[509] sram->in sram[509]->out sram[509]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[509]->out) 0 -.nodeset V(sram[509]->outb) vsp -Xsram[510] sram->in sram[510]->out sram[510]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[510]->out) 0 -.nodeset V(sram[510]->outb) vsp -Xsram[511] sram->in sram[511]->out sram[511]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[511]->out) 0 -.nodeset V(sram[511]->outb) vsp -***** Signal mux_2level_size50[31]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[0] mux_2level_size50[31]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[1] mux_2level_size50[31]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[2] mux_2level_size50[31]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[3] mux_2level_size50[31]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[4] mux_2level_size50[31]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[5] mux_2level_size50[31]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[6] mux_2level_size50[31]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[7] mux_2level_size50[31]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[8] mux_2level_size50[31]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[9] mux_2level_size50[31]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[10] mux_2level_size50[31]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[11] mux_2level_size50[31]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[12] mux_2level_size50[31]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[13] mux_2level_size50[31]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[14] mux_2level_size50[31]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[15] mux_2level_size50[31]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[16] mux_2level_size50[31]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[17] mux_2level_size50[31]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[18] mux_2level_size50[31]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[19] mux_2level_size50[31]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[20] mux_2level_size50[31]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[21] mux_2level_size50[31]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[22] mux_2level_size50[31]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[23] mux_2level_size50[31]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[24] mux_2level_size50[31]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[25] mux_2level_size50[31]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[26] mux_2level_size50[31]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[27] mux_2level_size50[31]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[28] mux_2level_size50[31]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[29] mux_2level_size50[31]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[30] mux_2level_size50[31]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[31] mux_2level_size50[31]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[32] mux_2level_size50[31]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[33] mux_2level_size50[31]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[34] mux_2level_size50[31]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[35] mux_2level_size50[31]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[36] mux_2level_size50[31]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[37] mux_2level_size50[31]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[38] mux_2level_size50[31]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[31]->in[39] mux_2level_size50[31]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[31]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[40] mux_2level_size50[31]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[41] mux_2level_size50[31]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[42] mux_2level_size50[31]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[43] mux_2level_size50[31]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[44] mux_2level_size50[31]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[45] mux_2level_size50[31]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[46] mux_2level_size50[31]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[47] mux_2level_size50[31]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[48] mux_2level_size50[31]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[31]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[31]->in[49] mux_2level_size50[31]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[31] gvdd_mux_2level_size50[31] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[31]_in[1]_crossbar trig v(mux_2level_size50[31]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[31]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[31]_in[1]_crossbar trig v(mux_2level_size50[31]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[31]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[31]_in[1]_crossbar when v(mux_2level_size50[31]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[31]_in[1]_crossbar trig v(mux_2level_size50[31]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[31]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[31]_in[1]_crossbar when v(mux_2level_size50[31]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[31]_in[1]_crossbar trig v(mux_2level_size50[31]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[31]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[31]_leakage_power avg p(Vgvdd_mux_2level_size50[31]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[31]_in[1]_crossbar param='mux_2level_size50[31]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[31]_dynamic_power avg p(Vgvdd_mux_2level_size50[31]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[31]_energy_per_cycle param='mux_2level_size50[31]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[31]_in[1]_crossbar param='mux_2level_size50[31]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[31]_in[1]_crossbar param='dynamic_power_idle_mux50[31]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[31]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[31]) from='start_rise_idle_mux50[31]_in[1]_crossbar' to='start_rise_idle_mux50[31]_in[1]_crossbar+switch_rise_idle_mux50[31]_in[1]_crossbar' -.meas tran dynamic_fall_idle_mux50[31]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[31]) from='start_fall_idle_mux50[31]_in[1]_crossbar' to='start_fall_idle_mux50[31]_in[1]_crossbar+switch_fall_idle_mux50[31]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to31] -+ param='sum_leakage_power_mux[0to30]+leakage_idle_mux50[31]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to31] -+ param='sum_energy_per_cycle_mux[0to30]+energy_per_cycle_idle_mux50[31]_in[1]_crossbar' -Xload_inv[31]_no0 mux_2level_size50[31]->out mux_2level_size50[31]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to31] -+ param='sum_leakage_power_pb_mux[0to30]+leakage_idle_mux50[31]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to31] -+ param='sum_energy_per_cycle_pb_mux[0to30]+energy_per_cycle_idle_mux50[31]_in[1]_crossbar' -Xmux_2level_size50[32] mux_2level_size50[32]->in[0] mux_2level_size50[32]->in[1] mux_2level_size50[32]->in[2] mux_2level_size50[32]->in[3] mux_2level_size50[32]->in[4] mux_2level_size50[32]->in[5] mux_2level_size50[32]->in[6] mux_2level_size50[32]->in[7] mux_2level_size50[32]->in[8] mux_2level_size50[32]->in[9] mux_2level_size50[32]->in[10] mux_2level_size50[32]->in[11] mux_2level_size50[32]->in[12] mux_2level_size50[32]->in[13] mux_2level_size50[32]->in[14] mux_2level_size50[32]->in[15] mux_2level_size50[32]->in[16] mux_2level_size50[32]->in[17] mux_2level_size50[32]->in[18] mux_2level_size50[32]->in[19] mux_2level_size50[32]->in[20] mux_2level_size50[32]->in[21] mux_2level_size50[32]->in[22] mux_2level_size50[32]->in[23] mux_2level_size50[32]->in[24] mux_2level_size50[32]->in[25] mux_2level_size50[32]->in[26] mux_2level_size50[32]->in[27] mux_2level_size50[32]->in[28] mux_2level_size50[32]->in[29] mux_2level_size50[32]->in[30] mux_2level_size50[32]->in[31] mux_2level_size50[32]->in[32] mux_2level_size50[32]->in[33] mux_2level_size50[32]->in[34] mux_2level_size50[32]->in[35] mux_2level_size50[32]->in[36] mux_2level_size50[32]->in[37] mux_2level_size50[32]->in[38] mux_2level_size50[32]->in[39] mux_2level_size50[32]->in[40] mux_2level_size50[32]->in[41] mux_2level_size50[32]->in[42] mux_2level_size50[32]->in[43] mux_2level_size50[32]->in[44] mux_2level_size50[32]->in[45] mux_2level_size50[32]->in[46] mux_2level_size50[32]->in[47] mux_2level_size50[32]->in[48] mux_2level_size50[32]->in[49] mux_2level_size50[32]->out sram[512]->outb sram[512]->out sram[513]->out sram[513]->outb sram[514]->out sram[514]->outb sram[515]->out sram[515]->outb sram[516]->out sram[516]->outb sram[517]->out sram[517]->outb sram[518]->out sram[518]->outb sram[519]->out sram[519]->outb sram[520]->outb sram[520]->out sram[521]->out sram[521]->outb sram[522]->out sram[522]->outb sram[523]->out sram[523]->outb sram[524]->out sram[524]->outb sram[525]->out sram[525]->outb sram[526]->out sram[526]->outb sram[527]->out sram[527]->outb gvdd_mux_2level_size50[32] 0 mux_2level_size50 -***** SRAM bits for MUX[32], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[512] sram->in sram[512]->out sram[512]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[512]->out) 0 -.nodeset V(sram[512]->outb) vsp -Xsram[513] sram->in sram[513]->out sram[513]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[513]->out) 0 -.nodeset V(sram[513]->outb) vsp -Xsram[514] sram->in sram[514]->out sram[514]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[514]->out) 0 -.nodeset V(sram[514]->outb) vsp -Xsram[515] sram->in sram[515]->out sram[515]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[515]->out) 0 -.nodeset V(sram[515]->outb) vsp -Xsram[516] sram->in sram[516]->out sram[516]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[516]->out) 0 -.nodeset V(sram[516]->outb) vsp -Xsram[517] sram->in sram[517]->out sram[517]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[517]->out) 0 -.nodeset V(sram[517]->outb) vsp -Xsram[518] sram->in sram[518]->out sram[518]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[518]->out) 0 -.nodeset V(sram[518]->outb) vsp -Xsram[519] sram->in sram[519]->out sram[519]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[519]->out) 0 -.nodeset V(sram[519]->outb) vsp -Xsram[520] sram->in sram[520]->out sram[520]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[520]->out) 0 -.nodeset V(sram[520]->outb) vsp -Xsram[521] sram->in sram[521]->out sram[521]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[521]->out) 0 -.nodeset V(sram[521]->outb) vsp -Xsram[522] sram->in sram[522]->out sram[522]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[522]->out) 0 -.nodeset V(sram[522]->outb) vsp -Xsram[523] sram->in sram[523]->out sram[523]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[523]->out) 0 -.nodeset V(sram[523]->outb) vsp -Xsram[524] sram->in sram[524]->out sram[524]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[524]->out) 0 -.nodeset V(sram[524]->outb) vsp -Xsram[525] sram->in sram[525]->out sram[525]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[525]->out) 0 -.nodeset V(sram[525]->outb) vsp -Xsram[526] sram->in sram[526]->out sram[526]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[526]->out) 0 -.nodeset V(sram[526]->outb) vsp -Xsram[527] sram->in sram[527]->out sram[527]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[527]->out) 0 -.nodeset V(sram[527]->outb) vsp -***** Signal mux_2level_size50[32]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[0] mux_2level_size50[32]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[1] mux_2level_size50[32]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[2] mux_2level_size50[32]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[3] mux_2level_size50[32]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[4] mux_2level_size50[32]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[5] mux_2level_size50[32]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[6] mux_2level_size50[32]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[7] mux_2level_size50[32]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[8] mux_2level_size50[32]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[9] mux_2level_size50[32]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[10] mux_2level_size50[32]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[11] mux_2level_size50[32]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[12] mux_2level_size50[32]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[13] mux_2level_size50[32]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[14] mux_2level_size50[32]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[15] mux_2level_size50[32]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[16] mux_2level_size50[32]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[17] mux_2level_size50[32]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[18] mux_2level_size50[32]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[19] mux_2level_size50[32]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[20] mux_2level_size50[32]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[21] mux_2level_size50[32]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[22] mux_2level_size50[32]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[23] mux_2level_size50[32]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[24] mux_2level_size50[32]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[25] mux_2level_size50[32]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[26] mux_2level_size50[32]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[27] mux_2level_size50[32]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[28] mux_2level_size50[32]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[29] mux_2level_size50[32]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[30] mux_2level_size50[32]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[31] mux_2level_size50[32]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[32] mux_2level_size50[32]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[33] mux_2level_size50[32]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[34] mux_2level_size50[32]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[35] mux_2level_size50[32]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[36] mux_2level_size50[32]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[37] mux_2level_size50[32]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[38] mux_2level_size50[32]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[32]->in[39] mux_2level_size50[32]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[32]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[40] mux_2level_size50[32]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[41] mux_2level_size50[32]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[42] mux_2level_size50[32]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[43] mux_2level_size50[32]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[44] mux_2level_size50[32]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[45] mux_2level_size50[32]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[46] mux_2level_size50[32]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[47] mux_2level_size50[32]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[48] mux_2level_size50[32]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[32]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[32]->in[49] mux_2level_size50[32]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[32] gvdd_mux_2level_size50[32] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[32]_in[2]_crossbar trig v(mux_2level_size50[32]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[32]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[32]_in[2]_crossbar trig v(mux_2level_size50[32]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[32]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[32]_in[2]_crossbar when v(mux_2level_size50[32]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[32]_in[2]_crossbar trig v(mux_2level_size50[32]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[32]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[32]_in[2]_crossbar when v(mux_2level_size50[32]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[32]_in[2]_crossbar trig v(mux_2level_size50[32]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[32]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[32]_leakage_power avg p(Vgvdd_mux_2level_size50[32]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[32]_in[2]_crossbar param='mux_2level_size50[32]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[32]_dynamic_power avg p(Vgvdd_mux_2level_size50[32]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[32]_energy_per_cycle param='mux_2level_size50[32]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[32]_in[2]_crossbar param='mux_2level_size50[32]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[32]_in[2]_crossbar param='dynamic_power_idle_mux50[32]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[32]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[32]) from='start_rise_idle_mux50[32]_in[2]_crossbar' to='start_rise_idle_mux50[32]_in[2]_crossbar+switch_rise_idle_mux50[32]_in[2]_crossbar' -.meas tran dynamic_fall_idle_mux50[32]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[32]) from='start_fall_idle_mux50[32]_in[2]_crossbar' to='start_fall_idle_mux50[32]_in[2]_crossbar+switch_fall_idle_mux50[32]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to32] -+ param='sum_leakage_power_mux[0to31]+leakage_idle_mux50[32]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to32] -+ param='sum_energy_per_cycle_mux[0to31]+energy_per_cycle_idle_mux50[32]_in[2]_crossbar' -Xload_inv[32]_no0 mux_2level_size50[32]->out mux_2level_size50[32]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to32] -+ param='sum_leakage_power_pb_mux[0to31]+leakage_idle_mux50[32]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to32] -+ param='sum_energy_per_cycle_pb_mux[0to31]+energy_per_cycle_idle_mux50[32]_in[2]_crossbar' -Xmux_2level_size50[33] mux_2level_size50[33]->in[0] mux_2level_size50[33]->in[1] mux_2level_size50[33]->in[2] mux_2level_size50[33]->in[3] mux_2level_size50[33]->in[4] mux_2level_size50[33]->in[5] mux_2level_size50[33]->in[6] mux_2level_size50[33]->in[7] mux_2level_size50[33]->in[8] mux_2level_size50[33]->in[9] mux_2level_size50[33]->in[10] mux_2level_size50[33]->in[11] mux_2level_size50[33]->in[12] mux_2level_size50[33]->in[13] mux_2level_size50[33]->in[14] mux_2level_size50[33]->in[15] mux_2level_size50[33]->in[16] mux_2level_size50[33]->in[17] mux_2level_size50[33]->in[18] mux_2level_size50[33]->in[19] mux_2level_size50[33]->in[20] mux_2level_size50[33]->in[21] mux_2level_size50[33]->in[22] mux_2level_size50[33]->in[23] mux_2level_size50[33]->in[24] mux_2level_size50[33]->in[25] mux_2level_size50[33]->in[26] mux_2level_size50[33]->in[27] mux_2level_size50[33]->in[28] mux_2level_size50[33]->in[29] mux_2level_size50[33]->in[30] mux_2level_size50[33]->in[31] mux_2level_size50[33]->in[32] mux_2level_size50[33]->in[33] mux_2level_size50[33]->in[34] mux_2level_size50[33]->in[35] mux_2level_size50[33]->in[36] mux_2level_size50[33]->in[37] mux_2level_size50[33]->in[38] mux_2level_size50[33]->in[39] mux_2level_size50[33]->in[40] mux_2level_size50[33]->in[41] mux_2level_size50[33]->in[42] mux_2level_size50[33]->in[43] mux_2level_size50[33]->in[44] mux_2level_size50[33]->in[45] mux_2level_size50[33]->in[46] mux_2level_size50[33]->in[47] mux_2level_size50[33]->in[48] mux_2level_size50[33]->in[49] mux_2level_size50[33]->out sram[528]->outb sram[528]->out sram[529]->out sram[529]->outb sram[530]->out sram[530]->outb sram[531]->out sram[531]->outb sram[532]->out sram[532]->outb sram[533]->out sram[533]->outb sram[534]->out sram[534]->outb sram[535]->out sram[535]->outb sram[536]->outb sram[536]->out sram[537]->out sram[537]->outb sram[538]->out sram[538]->outb sram[539]->out sram[539]->outb sram[540]->out sram[540]->outb sram[541]->out sram[541]->outb sram[542]->out sram[542]->outb sram[543]->out sram[543]->outb gvdd_mux_2level_size50[33] 0 mux_2level_size50 -***** SRAM bits for MUX[33], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[528] sram->in sram[528]->out sram[528]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[528]->out) 0 -.nodeset V(sram[528]->outb) vsp -Xsram[529] sram->in sram[529]->out sram[529]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[529]->out) 0 -.nodeset V(sram[529]->outb) vsp -Xsram[530] sram->in sram[530]->out sram[530]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[530]->out) 0 -.nodeset V(sram[530]->outb) vsp -Xsram[531] sram->in sram[531]->out sram[531]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[531]->out) 0 -.nodeset V(sram[531]->outb) vsp -Xsram[532] sram->in sram[532]->out sram[532]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[532]->out) 0 -.nodeset V(sram[532]->outb) vsp -Xsram[533] sram->in sram[533]->out sram[533]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[533]->out) 0 -.nodeset V(sram[533]->outb) vsp -Xsram[534] sram->in sram[534]->out sram[534]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[534]->out) 0 -.nodeset V(sram[534]->outb) vsp -Xsram[535] sram->in sram[535]->out sram[535]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[535]->out) 0 -.nodeset V(sram[535]->outb) vsp -Xsram[536] sram->in sram[536]->out sram[536]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[536]->out) 0 -.nodeset V(sram[536]->outb) vsp -Xsram[537] sram->in sram[537]->out sram[537]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[537]->out) 0 -.nodeset V(sram[537]->outb) vsp -Xsram[538] sram->in sram[538]->out sram[538]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[538]->out) 0 -.nodeset V(sram[538]->outb) vsp -Xsram[539] sram->in sram[539]->out sram[539]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[539]->out) 0 -.nodeset V(sram[539]->outb) vsp -Xsram[540] sram->in sram[540]->out sram[540]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[540]->out) 0 -.nodeset V(sram[540]->outb) vsp -Xsram[541] sram->in sram[541]->out sram[541]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[541]->out) 0 -.nodeset V(sram[541]->outb) vsp -Xsram[542] sram->in sram[542]->out sram[542]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[542]->out) 0 -.nodeset V(sram[542]->outb) vsp -Xsram[543] sram->in sram[543]->out sram[543]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[543]->out) 0 -.nodeset V(sram[543]->outb) vsp -***** Signal mux_2level_size50[33]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[0] mux_2level_size50[33]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[1] mux_2level_size50[33]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[2] mux_2level_size50[33]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[3] mux_2level_size50[33]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[4] mux_2level_size50[33]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[5] mux_2level_size50[33]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[6] mux_2level_size50[33]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[7] mux_2level_size50[33]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[8] mux_2level_size50[33]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[9] mux_2level_size50[33]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[10] mux_2level_size50[33]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[11] mux_2level_size50[33]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[12] mux_2level_size50[33]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[13] mux_2level_size50[33]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[14] mux_2level_size50[33]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[15] mux_2level_size50[33]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[16] mux_2level_size50[33]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[17] mux_2level_size50[33]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[18] mux_2level_size50[33]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[19] mux_2level_size50[33]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[20] mux_2level_size50[33]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[21] mux_2level_size50[33]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[22] mux_2level_size50[33]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[23] mux_2level_size50[33]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[24] mux_2level_size50[33]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[25] mux_2level_size50[33]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[26] mux_2level_size50[33]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[27] mux_2level_size50[33]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[28] mux_2level_size50[33]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[29] mux_2level_size50[33]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[30] mux_2level_size50[33]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[31] mux_2level_size50[33]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[32] mux_2level_size50[33]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[33] mux_2level_size50[33]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[34] mux_2level_size50[33]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[35] mux_2level_size50[33]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[36] mux_2level_size50[33]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[37] mux_2level_size50[33]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[38] mux_2level_size50[33]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[33]->in[39] mux_2level_size50[33]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[33]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[40] mux_2level_size50[33]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[41] mux_2level_size50[33]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[42] mux_2level_size50[33]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[43] mux_2level_size50[33]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[44] mux_2level_size50[33]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[45] mux_2level_size50[33]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[46] mux_2level_size50[33]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[47] mux_2level_size50[33]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[48] mux_2level_size50[33]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[33]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[33]->in[49] mux_2level_size50[33]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[33] gvdd_mux_2level_size50[33] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[33]_in[3]_crossbar trig v(mux_2level_size50[33]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[33]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[33]_in[3]_crossbar trig v(mux_2level_size50[33]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[33]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[33]_in[3]_crossbar when v(mux_2level_size50[33]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[33]_in[3]_crossbar trig v(mux_2level_size50[33]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[33]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[33]_in[3]_crossbar when v(mux_2level_size50[33]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[33]_in[3]_crossbar trig v(mux_2level_size50[33]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[33]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[33]_leakage_power avg p(Vgvdd_mux_2level_size50[33]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[33]_in[3]_crossbar param='mux_2level_size50[33]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[33]_dynamic_power avg p(Vgvdd_mux_2level_size50[33]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[33]_energy_per_cycle param='mux_2level_size50[33]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[33]_in[3]_crossbar param='mux_2level_size50[33]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[33]_in[3]_crossbar param='dynamic_power_idle_mux50[33]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[33]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[33]) from='start_rise_idle_mux50[33]_in[3]_crossbar' to='start_rise_idle_mux50[33]_in[3]_crossbar+switch_rise_idle_mux50[33]_in[3]_crossbar' -.meas tran dynamic_fall_idle_mux50[33]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[33]) from='start_fall_idle_mux50[33]_in[3]_crossbar' to='start_fall_idle_mux50[33]_in[3]_crossbar+switch_fall_idle_mux50[33]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to33] -+ param='sum_leakage_power_mux[0to32]+leakage_idle_mux50[33]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to33] -+ param='sum_energy_per_cycle_mux[0to32]+energy_per_cycle_idle_mux50[33]_in[3]_crossbar' -Xload_inv[33]_no0 mux_2level_size50[33]->out mux_2level_size50[33]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to33] -+ param='sum_leakage_power_pb_mux[0to32]+leakage_idle_mux50[33]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to33] -+ param='sum_energy_per_cycle_pb_mux[0to32]+energy_per_cycle_idle_mux50[33]_in[3]_crossbar' -Xmux_2level_size50[34] mux_2level_size50[34]->in[0] mux_2level_size50[34]->in[1] mux_2level_size50[34]->in[2] mux_2level_size50[34]->in[3] mux_2level_size50[34]->in[4] mux_2level_size50[34]->in[5] mux_2level_size50[34]->in[6] mux_2level_size50[34]->in[7] mux_2level_size50[34]->in[8] mux_2level_size50[34]->in[9] mux_2level_size50[34]->in[10] mux_2level_size50[34]->in[11] mux_2level_size50[34]->in[12] mux_2level_size50[34]->in[13] mux_2level_size50[34]->in[14] mux_2level_size50[34]->in[15] mux_2level_size50[34]->in[16] mux_2level_size50[34]->in[17] mux_2level_size50[34]->in[18] mux_2level_size50[34]->in[19] mux_2level_size50[34]->in[20] mux_2level_size50[34]->in[21] mux_2level_size50[34]->in[22] mux_2level_size50[34]->in[23] mux_2level_size50[34]->in[24] mux_2level_size50[34]->in[25] mux_2level_size50[34]->in[26] mux_2level_size50[34]->in[27] mux_2level_size50[34]->in[28] mux_2level_size50[34]->in[29] mux_2level_size50[34]->in[30] mux_2level_size50[34]->in[31] mux_2level_size50[34]->in[32] mux_2level_size50[34]->in[33] mux_2level_size50[34]->in[34] mux_2level_size50[34]->in[35] mux_2level_size50[34]->in[36] mux_2level_size50[34]->in[37] mux_2level_size50[34]->in[38] mux_2level_size50[34]->in[39] mux_2level_size50[34]->in[40] mux_2level_size50[34]->in[41] mux_2level_size50[34]->in[42] mux_2level_size50[34]->in[43] mux_2level_size50[34]->in[44] mux_2level_size50[34]->in[45] mux_2level_size50[34]->in[46] mux_2level_size50[34]->in[47] mux_2level_size50[34]->in[48] mux_2level_size50[34]->in[49] mux_2level_size50[34]->out sram[544]->outb sram[544]->out sram[545]->out sram[545]->outb sram[546]->out sram[546]->outb sram[547]->out sram[547]->outb sram[548]->out sram[548]->outb sram[549]->out sram[549]->outb sram[550]->out sram[550]->outb sram[551]->out sram[551]->outb sram[552]->outb sram[552]->out sram[553]->out sram[553]->outb sram[554]->out sram[554]->outb sram[555]->out sram[555]->outb sram[556]->out sram[556]->outb sram[557]->out sram[557]->outb sram[558]->out sram[558]->outb sram[559]->out sram[559]->outb gvdd_mux_2level_size50[34] 0 mux_2level_size50 -***** SRAM bits for MUX[34], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[544] sram->in sram[544]->out sram[544]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[544]->out) 0 -.nodeset V(sram[544]->outb) vsp -Xsram[545] sram->in sram[545]->out sram[545]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[545]->out) 0 -.nodeset V(sram[545]->outb) vsp -Xsram[546] sram->in sram[546]->out sram[546]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[546]->out) 0 -.nodeset V(sram[546]->outb) vsp -Xsram[547] sram->in sram[547]->out sram[547]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[547]->out) 0 -.nodeset V(sram[547]->outb) vsp -Xsram[548] sram->in sram[548]->out sram[548]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[548]->out) 0 -.nodeset V(sram[548]->outb) vsp -Xsram[549] sram->in sram[549]->out sram[549]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[549]->out) 0 -.nodeset V(sram[549]->outb) vsp -Xsram[550] sram->in sram[550]->out sram[550]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[550]->out) 0 -.nodeset V(sram[550]->outb) vsp -Xsram[551] sram->in sram[551]->out sram[551]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[551]->out) 0 -.nodeset V(sram[551]->outb) vsp -Xsram[552] sram->in sram[552]->out sram[552]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[552]->out) 0 -.nodeset V(sram[552]->outb) vsp -Xsram[553] sram->in sram[553]->out sram[553]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[553]->out) 0 -.nodeset V(sram[553]->outb) vsp -Xsram[554] sram->in sram[554]->out sram[554]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[554]->out) 0 -.nodeset V(sram[554]->outb) vsp -Xsram[555] sram->in sram[555]->out sram[555]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[555]->out) 0 -.nodeset V(sram[555]->outb) vsp -Xsram[556] sram->in sram[556]->out sram[556]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[556]->out) 0 -.nodeset V(sram[556]->outb) vsp -Xsram[557] sram->in sram[557]->out sram[557]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[557]->out) 0 -.nodeset V(sram[557]->outb) vsp -Xsram[558] sram->in sram[558]->out sram[558]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[558]->out) 0 -.nodeset V(sram[558]->outb) vsp -Xsram[559] sram->in sram[559]->out sram[559]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[559]->out) 0 -.nodeset V(sram[559]->outb) vsp -***** Signal mux_2level_size50[34]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[0] mux_2level_size50[34]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[1] mux_2level_size50[34]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[2] mux_2level_size50[34]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[3] mux_2level_size50[34]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[4] mux_2level_size50[34]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[5] mux_2level_size50[34]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[6] mux_2level_size50[34]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[7] mux_2level_size50[34]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[8] mux_2level_size50[34]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[9] mux_2level_size50[34]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[10] mux_2level_size50[34]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[11] mux_2level_size50[34]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[12] mux_2level_size50[34]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[13] mux_2level_size50[34]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[14] mux_2level_size50[34]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[15] mux_2level_size50[34]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[16] mux_2level_size50[34]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[17] mux_2level_size50[34]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[18] mux_2level_size50[34]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[19] mux_2level_size50[34]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[20] mux_2level_size50[34]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[21] mux_2level_size50[34]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[22] mux_2level_size50[34]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[23] mux_2level_size50[34]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[24] mux_2level_size50[34]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[25] mux_2level_size50[34]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[26] mux_2level_size50[34]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[27] mux_2level_size50[34]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[28] mux_2level_size50[34]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[29] mux_2level_size50[34]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[30] mux_2level_size50[34]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[31] mux_2level_size50[34]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[32] mux_2level_size50[34]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[33] mux_2level_size50[34]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[34] mux_2level_size50[34]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[35] mux_2level_size50[34]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[36] mux_2level_size50[34]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[37] mux_2level_size50[34]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[38] mux_2level_size50[34]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[34]->in[39] mux_2level_size50[34]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[34]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[40] mux_2level_size50[34]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[41] mux_2level_size50[34]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[42] mux_2level_size50[34]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[43] mux_2level_size50[34]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[44] mux_2level_size50[34]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[45] mux_2level_size50[34]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[46] mux_2level_size50[34]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[47] mux_2level_size50[34]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[48] mux_2level_size50[34]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[34]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[34]->in[49] mux_2level_size50[34]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[34] gvdd_mux_2level_size50[34] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[34]_in[4]_crossbar trig v(mux_2level_size50[34]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[34]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[34]_in[4]_crossbar trig v(mux_2level_size50[34]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[34]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[34]_in[4]_crossbar when v(mux_2level_size50[34]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[34]_in[4]_crossbar trig v(mux_2level_size50[34]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[34]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[34]_in[4]_crossbar when v(mux_2level_size50[34]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[34]_in[4]_crossbar trig v(mux_2level_size50[34]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[34]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[34]_leakage_power avg p(Vgvdd_mux_2level_size50[34]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[34]_in[4]_crossbar param='mux_2level_size50[34]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[34]_dynamic_power avg p(Vgvdd_mux_2level_size50[34]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[34]_energy_per_cycle param='mux_2level_size50[34]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[34]_in[4]_crossbar param='mux_2level_size50[34]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[34]_in[4]_crossbar param='dynamic_power_idle_mux50[34]_in[4]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[34]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[34]) from='start_rise_idle_mux50[34]_in[4]_crossbar' to='start_rise_idle_mux50[34]_in[4]_crossbar+switch_rise_idle_mux50[34]_in[4]_crossbar' -.meas tran dynamic_fall_idle_mux50[34]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[34]) from='start_fall_idle_mux50[34]_in[4]_crossbar' to='start_fall_idle_mux50[34]_in[4]_crossbar+switch_fall_idle_mux50[34]_in[4]_crossbar' -.meas tran sum_leakage_power_mux[0to34] -+ param='sum_leakage_power_mux[0to33]+leakage_idle_mux50[34]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to34] -+ param='sum_energy_per_cycle_mux[0to33]+energy_per_cycle_idle_mux50[34]_in[4]_crossbar' -Xload_inv[34]_no0 mux_2level_size50[34]->out mux_2level_size50[34]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to34] -+ param='sum_leakage_power_pb_mux[0to33]+leakage_idle_mux50[34]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to34] -+ param='sum_energy_per_cycle_pb_mux[0to33]+energy_per_cycle_idle_mux50[34]_in[4]_crossbar' -Xmux_2level_size50[35] mux_2level_size50[35]->in[0] mux_2level_size50[35]->in[1] mux_2level_size50[35]->in[2] mux_2level_size50[35]->in[3] mux_2level_size50[35]->in[4] mux_2level_size50[35]->in[5] mux_2level_size50[35]->in[6] mux_2level_size50[35]->in[7] mux_2level_size50[35]->in[8] mux_2level_size50[35]->in[9] mux_2level_size50[35]->in[10] mux_2level_size50[35]->in[11] mux_2level_size50[35]->in[12] mux_2level_size50[35]->in[13] mux_2level_size50[35]->in[14] mux_2level_size50[35]->in[15] mux_2level_size50[35]->in[16] mux_2level_size50[35]->in[17] mux_2level_size50[35]->in[18] mux_2level_size50[35]->in[19] mux_2level_size50[35]->in[20] mux_2level_size50[35]->in[21] mux_2level_size50[35]->in[22] mux_2level_size50[35]->in[23] mux_2level_size50[35]->in[24] mux_2level_size50[35]->in[25] mux_2level_size50[35]->in[26] mux_2level_size50[35]->in[27] mux_2level_size50[35]->in[28] mux_2level_size50[35]->in[29] mux_2level_size50[35]->in[30] mux_2level_size50[35]->in[31] mux_2level_size50[35]->in[32] mux_2level_size50[35]->in[33] mux_2level_size50[35]->in[34] mux_2level_size50[35]->in[35] mux_2level_size50[35]->in[36] mux_2level_size50[35]->in[37] mux_2level_size50[35]->in[38] mux_2level_size50[35]->in[39] mux_2level_size50[35]->in[40] mux_2level_size50[35]->in[41] mux_2level_size50[35]->in[42] mux_2level_size50[35]->in[43] mux_2level_size50[35]->in[44] mux_2level_size50[35]->in[45] mux_2level_size50[35]->in[46] mux_2level_size50[35]->in[47] mux_2level_size50[35]->in[48] mux_2level_size50[35]->in[49] mux_2level_size50[35]->out sram[560]->outb sram[560]->out sram[561]->out sram[561]->outb sram[562]->out sram[562]->outb sram[563]->out sram[563]->outb sram[564]->out sram[564]->outb sram[565]->out sram[565]->outb sram[566]->out sram[566]->outb sram[567]->out sram[567]->outb sram[568]->outb sram[568]->out sram[569]->out sram[569]->outb sram[570]->out sram[570]->outb sram[571]->out sram[571]->outb sram[572]->out sram[572]->outb sram[573]->out sram[573]->outb sram[574]->out sram[574]->outb sram[575]->out sram[575]->outb gvdd_mux_2level_size50[35] 0 mux_2level_size50 -***** SRAM bits for MUX[35], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[560] sram->in sram[560]->out sram[560]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[560]->out) 0 -.nodeset V(sram[560]->outb) vsp -Xsram[561] sram->in sram[561]->out sram[561]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[561]->out) 0 -.nodeset V(sram[561]->outb) vsp -Xsram[562] sram->in sram[562]->out sram[562]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[562]->out) 0 -.nodeset V(sram[562]->outb) vsp -Xsram[563] sram->in sram[563]->out sram[563]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[563]->out) 0 -.nodeset V(sram[563]->outb) vsp -Xsram[564] sram->in sram[564]->out sram[564]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[564]->out) 0 -.nodeset V(sram[564]->outb) vsp -Xsram[565] sram->in sram[565]->out sram[565]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[565]->out) 0 -.nodeset V(sram[565]->outb) vsp -Xsram[566] sram->in sram[566]->out sram[566]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[566]->out) 0 -.nodeset V(sram[566]->outb) vsp -Xsram[567] sram->in sram[567]->out sram[567]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[567]->out) 0 -.nodeset V(sram[567]->outb) vsp -Xsram[568] sram->in sram[568]->out sram[568]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[568]->out) 0 -.nodeset V(sram[568]->outb) vsp -Xsram[569] sram->in sram[569]->out sram[569]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[569]->out) 0 -.nodeset V(sram[569]->outb) vsp -Xsram[570] sram->in sram[570]->out sram[570]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[570]->out) 0 -.nodeset V(sram[570]->outb) vsp -Xsram[571] sram->in sram[571]->out sram[571]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[571]->out) 0 -.nodeset V(sram[571]->outb) vsp -Xsram[572] sram->in sram[572]->out sram[572]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[572]->out) 0 -.nodeset V(sram[572]->outb) vsp -Xsram[573] sram->in sram[573]->out sram[573]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[573]->out) 0 -.nodeset V(sram[573]->outb) vsp -Xsram[574] sram->in sram[574]->out sram[574]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[574]->out) 0 -.nodeset V(sram[574]->outb) vsp -Xsram[575] sram->in sram[575]->out sram[575]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[575]->out) 0 -.nodeset V(sram[575]->outb) vsp -***** Signal mux_2level_size50[35]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[0] mux_2level_size50[35]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[1] mux_2level_size50[35]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[2] mux_2level_size50[35]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[3] mux_2level_size50[35]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[4] mux_2level_size50[35]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[5] mux_2level_size50[35]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[6] mux_2level_size50[35]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[7] mux_2level_size50[35]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[8] mux_2level_size50[35]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[9] mux_2level_size50[35]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[10] mux_2level_size50[35]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[11] mux_2level_size50[35]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[12] mux_2level_size50[35]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[13] mux_2level_size50[35]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[14] mux_2level_size50[35]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[15] mux_2level_size50[35]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[16] mux_2level_size50[35]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[17] mux_2level_size50[35]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[18] mux_2level_size50[35]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[19] mux_2level_size50[35]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[20] mux_2level_size50[35]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[21] mux_2level_size50[35]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[22] mux_2level_size50[35]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[23] mux_2level_size50[35]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[24] mux_2level_size50[35]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[25] mux_2level_size50[35]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[26] mux_2level_size50[35]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[27] mux_2level_size50[35]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[28] mux_2level_size50[35]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[29] mux_2level_size50[35]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[30] mux_2level_size50[35]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[31] mux_2level_size50[35]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[32] mux_2level_size50[35]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[33] mux_2level_size50[35]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[34] mux_2level_size50[35]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[35] mux_2level_size50[35]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[36] mux_2level_size50[35]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[37] mux_2level_size50[35]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[38] mux_2level_size50[35]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[35]->in[39] mux_2level_size50[35]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[35]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[40] mux_2level_size50[35]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[41] mux_2level_size50[35]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[42] mux_2level_size50[35]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[43] mux_2level_size50[35]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[44] mux_2level_size50[35]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[45] mux_2level_size50[35]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[46] mux_2level_size50[35]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[47] mux_2level_size50[35]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[48] mux_2level_size50[35]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[35]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[35]->in[49] mux_2level_size50[35]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[35] gvdd_mux_2level_size50[35] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[35]_in[5]_crossbar trig v(mux_2level_size50[35]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[35]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[35]_in[5]_crossbar trig v(mux_2level_size50[35]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[35]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[35]_in[5]_crossbar when v(mux_2level_size50[35]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[35]_in[5]_crossbar trig v(mux_2level_size50[35]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[35]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[35]_in[5]_crossbar when v(mux_2level_size50[35]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[35]_in[5]_crossbar trig v(mux_2level_size50[35]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[35]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[35]_leakage_power avg p(Vgvdd_mux_2level_size50[35]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[35]_in[5]_crossbar param='mux_2level_size50[35]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[35]_dynamic_power avg p(Vgvdd_mux_2level_size50[35]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[35]_energy_per_cycle param='mux_2level_size50[35]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[35]_in[5]_crossbar param='mux_2level_size50[35]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[35]_in[5]_crossbar param='dynamic_power_idle_mux50[35]_in[5]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[35]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[35]) from='start_rise_idle_mux50[35]_in[5]_crossbar' to='start_rise_idle_mux50[35]_in[5]_crossbar+switch_rise_idle_mux50[35]_in[5]_crossbar' -.meas tran dynamic_fall_idle_mux50[35]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[35]) from='start_fall_idle_mux50[35]_in[5]_crossbar' to='start_fall_idle_mux50[35]_in[5]_crossbar+switch_fall_idle_mux50[35]_in[5]_crossbar' -.meas tran sum_leakage_power_mux[0to35] -+ param='sum_leakage_power_mux[0to34]+leakage_idle_mux50[35]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to35] -+ param='sum_energy_per_cycle_mux[0to34]+energy_per_cycle_idle_mux50[35]_in[5]_crossbar' -Xload_inv[35]_no0 mux_2level_size50[35]->out mux_2level_size50[35]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to35] -+ param='sum_leakage_power_pb_mux[0to34]+leakage_idle_mux50[35]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to35] -+ param='sum_energy_per_cycle_pb_mux[0to34]+energy_per_cycle_idle_mux50[35]_in[5]_crossbar' -Xmux_2level_size50[36] mux_2level_size50[36]->in[0] mux_2level_size50[36]->in[1] mux_2level_size50[36]->in[2] mux_2level_size50[36]->in[3] mux_2level_size50[36]->in[4] mux_2level_size50[36]->in[5] mux_2level_size50[36]->in[6] mux_2level_size50[36]->in[7] mux_2level_size50[36]->in[8] mux_2level_size50[36]->in[9] mux_2level_size50[36]->in[10] mux_2level_size50[36]->in[11] mux_2level_size50[36]->in[12] mux_2level_size50[36]->in[13] mux_2level_size50[36]->in[14] mux_2level_size50[36]->in[15] mux_2level_size50[36]->in[16] mux_2level_size50[36]->in[17] mux_2level_size50[36]->in[18] mux_2level_size50[36]->in[19] mux_2level_size50[36]->in[20] mux_2level_size50[36]->in[21] mux_2level_size50[36]->in[22] mux_2level_size50[36]->in[23] mux_2level_size50[36]->in[24] mux_2level_size50[36]->in[25] mux_2level_size50[36]->in[26] mux_2level_size50[36]->in[27] mux_2level_size50[36]->in[28] mux_2level_size50[36]->in[29] mux_2level_size50[36]->in[30] mux_2level_size50[36]->in[31] mux_2level_size50[36]->in[32] mux_2level_size50[36]->in[33] mux_2level_size50[36]->in[34] mux_2level_size50[36]->in[35] mux_2level_size50[36]->in[36] mux_2level_size50[36]->in[37] mux_2level_size50[36]->in[38] mux_2level_size50[36]->in[39] mux_2level_size50[36]->in[40] mux_2level_size50[36]->in[41] mux_2level_size50[36]->in[42] mux_2level_size50[36]->in[43] mux_2level_size50[36]->in[44] mux_2level_size50[36]->in[45] mux_2level_size50[36]->in[46] mux_2level_size50[36]->in[47] mux_2level_size50[36]->in[48] mux_2level_size50[36]->in[49] mux_2level_size50[36]->out sram[576]->outb sram[576]->out sram[577]->out sram[577]->outb sram[578]->out sram[578]->outb sram[579]->out sram[579]->outb sram[580]->out sram[580]->outb sram[581]->out sram[581]->outb sram[582]->out sram[582]->outb sram[583]->out sram[583]->outb sram[584]->outb sram[584]->out sram[585]->out sram[585]->outb sram[586]->out sram[586]->outb sram[587]->out sram[587]->outb sram[588]->out sram[588]->outb sram[589]->out sram[589]->outb sram[590]->out sram[590]->outb sram[591]->out sram[591]->outb gvdd_mux_2level_size50[36] 0 mux_2level_size50 -***** SRAM bits for MUX[36], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[576] sram->in sram[576]->out sram[576]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[576]->out) 0 -.nodeset V(sram[576]->outb) vsp -Xsram[577] sram->in sram[577]->out sram[577]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[577]->out) 0 -.nodeset V(sram[577]->outb) vsp -Xsram[578] sram->in sram[578]->out sram[578]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[578]->out) 0 -.nodeset V(sram[578]->outb) vsp -Xsram[579] sram->in sram[579]->out sram[579]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[579]->out) 0 -.nodeset V(sram[579]->outb) vsp -Xsram[580] sram->in sram[580]->out sram[580]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[580]->out) 0 -.nodeset V(sram[580]->outb) vsp -Xsram[581] sram->in sram[581]->out sram[581]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[581]->out) 0 -.nodeset V(sram[581]->outb) vsp -Xsram[582] sram->in sram[582]->out sram[582]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[582]->out) 0 -.nodeset V(sram[582]->outb) vsp -Xsram[583] sram->in sram[583]->out sram[583]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[583]->out) 0 -.nodeset V(sram[583]->outb) vsp -Xsram[584] sram->in sram[584]->out sram[584]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[584]->out) 0 -.nodeset V(sram[584]->outb) vsp -Xsram[585] sram->in sram[585]->out sram[585]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[585]->out) 0 -.nodeset V(sram[585]->outb) vsp -Xsram[586] sram->in sram[586]->out sram[586]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[586]->out) 0 -.nodeset V(sram[586]->outb) vsp -Xsram[587] sram->in sram[587]->out sram[587]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[587]->out) 0 -.nodeset V(sram[587]->outb) vsp -Xsram[588] sram->in sram[588]->out sram[588]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[588]->out) 0 -.nodeset V(sram[588]->outb) vsp -Xsram[589] sram->in sram[589]->out sram[589]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[589]->out) 0 -.nodeset V(sram[589]->outb) vsp -Xsram[590] sram->in sram[590]->out sram[590]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[590]->out) 0 -.nodeset V(sram[590]->outb) vsp -Xsram[591] sram->in sram[591]->out sram[591]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[591]->out) 0 -.nodeset V(sram[591]->outb) vsp -***** Signal mux_2level_size50[36]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[0] mux_2level_size50[36]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[1] mux_2level_size50[36]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[2] mux_2level_size50[36]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[3] mux_2level_size50[36]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[4] mux_2level_size50[36]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[5] mux_2level_size50[36]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[6] mux_2level_size50[36]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[7] mux_2level_size50[36]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[8] mux_2level_size50[36]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[9] mux_2level_size50[36]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[10] mux_2level_size50[36]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[11] mux_2level_size50[36]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[12] mux_2level_size50[36]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[13] mux_2level_size50[36]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[14] mux_2level_size50[36]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[15] mux_2level_size50[36]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[16] mux_2level_size50[36]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[17] mux_2level_size50[36]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[18] mux_2level_size50[36]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[19] mux_2level_size50[36]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[20] mux_2level_size50[36]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[21] mux_2level_size50[36]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[22] mux_2level_size50[36]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[23] mux_2level_size50[36]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[24] mux_2level_size50[36]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[25] mux_2level_size50[36]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[26] mux_2level_size50[36]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[27] mux_2level_size50[36]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[28] mux_2level_size50[36]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[29] mux_2level_size50[36]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[30] mux_2level_size50[36]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[31] mux_2level_size50[36]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[32] mux_2level_size50[36]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[33] mux_2level_size50[36]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[34] mux_2level_size50[36]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[35] mux_2level_size50[36]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[36] mux_2level_size50[36]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[37] mux_2level_size50[36]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[38] mux_2level_size50[36]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[36]->in[39] mux_2level_size50[36]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[36]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[40] mux_2level_size50[36]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[41] mux_2level_size50[36]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[42] mux_2level_size50[36]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[43] mux_2level_size50[36]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[44] mux_2level_size50[36]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[45] mux_2level_size50[36]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[46] mux_2level_size50[36]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[47] mux_2level_size50[36]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[48] mux_2level_size50[36]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[36]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[36]->in[49] mux_2level_size50[36]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[36] gvdd_mux_2level_size50[36] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[36]_in[0]_crossbar trig v(mux_2level_size50[36]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[36]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[36]_in[0]_crossbar trig v(mux_2level_size50[36]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[36]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[36]_in[0]_crossbar when v(mux_2level_size50[36]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[36]_in[0]_crossbar trig v(mux_2level_size50[36]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[36]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[36]_in[0]_crossbar when v(mux_2level_size50[36]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[36]_in[0]_crossbar trig v(mux_2level_size50[36]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[36]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[36]_leakage_power avg p(Vgvdd_mux_2level_size50[36]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[36]_in[0]_crossbar param='mux_2level_size50[36]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[36]_dynamic_power avg p(Vgvdd_mux_2level_size50[36]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[36]_energy_per_cycle param='mux_2level_size50[36]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[36]_in[0]_crossbar param='mux_2level_size50[36]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[36]_in[0]_crossbar param='dynamic_power_idle_mux50[36]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[36]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[36]) from='start_rise_idle_mux50[36]_in[0]_crossbar' to='start_rise_idle_mux50[36]_in[0]_crossbar+switch_rise_idle_mux50[36]_in[0]_crossbar' -.meas tran dynamic_fall_idle_mux50[36]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[36]) from='start_fall_idle_mux50[36]_in[0]_crossbar' to='start_fall_idle_mux50[36]_in[0]_crossbar+switch_fall_idle_mux50[36]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to36] -+ param='sum_leakage_power_mux[0to35]+leakage_idle_mux50[36]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to36] -+ param='sum_energy_per_cycle_mux[0to35]+energy_per_cycle_idle_mux50[36]_in[0]_crossbar' -Xload_inv[36]_no0 mux_2level_size50[36]->out mux_2level_size50[36]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to36] -+ param='sum_leakage_power_pb_mux[0to35]+leakage_idle_mux50[36]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to36] -+ param='sum_energy_per_cycle_pb_mux[0to35]+energy_per_cycle_idle_mux50[36]_in[0]_crossbar' -Xmux_2level_size50[37] mux_2level_size50[37]->in[0] mux_2level_size50[37]->in[1] mux_2level_size50[37]->in[2] mux_2level_size50[37]->in[3] mux_2level_size50[37]->in[4] mux_2level_size50[37]->in[5] mux_2level_size50[37]->in[6] mux_2level_size50[37]->in[7] mux_2level_size50[37]->in[8] mux_2level_size50[37]->in[9] mux_2level_size50[37]->in[10] mux_2level_size50[37]->in[11] mux_2level_size50[37]->in[12] mux_2level_size50[37]->in[13] mux_2level_size50[37]->in[14] mux_2level_size50[37]->in[15] mux_2level_size50[37]->in[16] mux_2level_size50[37]->in[17] mux_2level_size50[37]->in[18] mux_2level_size50[37]->in[19] mux_2level_size50[37]->in[20] mux_2level_size50[37]->in[21] mux_2level_size50[37]->in[22] mux_2level_size50[37]->in[23] mux_2level_size50[37]->in[24] mux_2level_size50[37]->in[25] mux_2level_size50[37]->in[26] mux_2level_size50[37]->in[27] mux_2level_size50[37]->in[28] mux_2level_size50[37]->in[29] mux_2level_size50[37]->in[30] mux_2level_size50[37]->in[31] mux_2level_size50[37]->in[32] mux_2level_size50[37]->in[33] mux_2level_size50[37]->in[34] mux_2level_size50[37]->in[35] mux_2level_size50[37]->in[36] mux_2level_size50[37]->in[37] mux_2level_size50[37]->in[38] mux_2level_size50[37]->in[39] mux_2level_size50[37]->in[40] mux_2level_size50[37]->in[41] mux_2level_size50[37]->in[42] mux_2level_size50[37]->in[43] mux_2level_size50[37]->in[44] mux_2level_size50[37]->in[45] mux_2level_size50[37]->in[46] mux_2level_size50[37]->in[47] mux_2level_size50[37]->in[48] mux_2level_size50[37]->in[49] mux_2level_size50[37]->out sram[592]->outb sram[592]->out sram[593]->out sram[593]->outb sram[594]->out sram[594]->outb sram[595]->out sram[595]->outb sram[596]->out sram[596]->outb sram[597]->out sram[597]->outb sram[598]->out sram[598]->outb sram[599]->out sram[599]->outb sram[600]->outb sram[600]->out sram[601]->out sram[601]->outb sram[602]->out sram[602]->outb sram[603]->out sram[603]->outb sram[604]->out sram[604]->outb sram[605]->out sram[605]->outb sram[606]->out sram[606]->outb sram[607]->out sram[607]->outb gvdd_mux_2level_size50[37] 0 mux_2level_size50 -***** SRAM bits for MUX[37], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[592] sram->in sram[592]->out sram[592]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[592]->out) 0 -.nodeset V(sram[592]->outb) vsp -Xsram[593] sram->in sram[593]->out sram[593]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[593]->out) 0 -.nodeset V(sram[593]->outb) vsp -Xsram[594] sram->in sram[594]->out sram[594]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[594]->out) 0 -.nodeset V(sram[594]->outb) vsp -Xsram[595] sram->in sram[595]->out sram[595]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[595]->out) 0 -.nodeset V(sram[595]->outb) vsp -Xsram[596] sram->in sram[596]->out sram[596]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[596]->out) 0 -.nodeset V(sram[596]->outb) vsp -Xsram[597] sram->in sram[597]->out sram[597]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[597]->out) 0 -.nodeset V(sram[597]->outb) vsp -Xsram[598] sram->in sram[598]->out sram[598]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[598]->out) 0 -.nodeset V(sram[598]->outb) vsp -Xsram[599] sram->in sram[599]->out sram[599]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[599]->out) 0 -.nodeset V(sram[599]->outb) vsp -Xsram[600] sram->in sram[600]->out sram[600]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[600]->out) 0 -.nodeset V(sram[600]->outb) vsp -Xsram[601] sram->in sram[601]->out sram[601]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[601]->out) 0 -.nodeset V(sram[601]->outb) vsp -Xsram[602] sram->in sram[602]->out sram[602]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[602]->out) 0 -.nodeset V(sram[602]->outb) vsp -Xsram[603] sram->in sram[603]->out sram[603]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[603]->out) 0 -.nodeset V(sram[603]->outb) vsp -Xsram[604] sram->in sram[604]->out sram[604]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[604]->out) 0 -.nodeset V(sram[604]->outb) vsp -Xsram[605] sram->in sram[605]->out sram[605]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[605]->out) 0 -.nodeset V(sram[605]->outb) vsp -Xsram[606] sram->in sram[606]->out sram[606]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[606]->out) 0 -.nodeset V(sram[606]->outb) vsp -Xsram[607] sram->in sram[607]->out sram[607]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[607]->out) 0 -.nodeset V(sram[607]->outb) vsp -***** Signal mux_2level_size50[37]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[0] mux_2level_size50[37]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[1] mux_2level_size50[37]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[2] mux_2level_size50[37]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[3] mux_2level_size50[37]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[4] mux_2level_size50[37]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[5] mux_2level_size50[37]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[6] mux_2level_size50[37]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[7] mux_2level_size50[37]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[8] mux_2level_size50[37]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[9] mux_2level_size50[37]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[10] mux_2level_size50[37]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[11] mux_2level_size50[37]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[12] mux_2level_size50[37]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[13] mux_2level_size50[37]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[14] mux_2level_size50[37]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[15] mux_2level_size50[37]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[16] mux_2level_size50[37]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[17] mux_2level_size50[37]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[18] mux_2level_size50[37]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[19] mux_2level_size50[37]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[20] mux_2level_size50[37]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[21] mux_2level_size50[37]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[22] mux_2level_size50[37]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[23] mux_2level_size50[37]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[24] mux_2level_size50[37]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[25] mux_2level_size50[37]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[26] mux_2level_size50[37]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[27] mux_2level_size50[37]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[28] mux_2level_size50[37]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[29] mux_2level_size50[37]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[30] mux_2level_size50[37]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[31] mux_2level_size50[37]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[32] mux_2level_size50[37]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[33] mux_2level_size50[37]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[34] mux_2level_size50[37]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[35] mux_2level_size50[37]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[36] mux_2level_size50[37]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[37] mux_2level_size50[37]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[38] mux_2level_size50[37]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[37]->in[39] mux_2level_size50[37]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[37]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[40] mux_2level_size50[37]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[41] mux_2level_size50[37]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[42] mux_2level_size50[37]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[43] mux_2level_size50[37]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[44] mux_2level_size50[37]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[45] mux_2level_size50[37]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[46] mux_2level_size50[37]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[47] mux_2level_size50[37]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[48] mux_2level_size50[37]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[37]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[37]->in[49] mux_2level_size50[37]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[37] gvdd_mux_2level_size50[37] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[37]_in[1]_crossbar trig v(mux_2level_size50[37]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[37]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[37]_in[1]_crossbar trig v(mux_2level_size50[37]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[37]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[37]_in[1]_crossbar when v(mux_2level_size50[37]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[37]_in[1]_crossbar trig v(mux_2level_size50[37]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[37]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[37]_in[1]_crossbar when v(mux_2level_size50[37]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[37]_in[1]_crossbar trig v(mux_2level_size50[37]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[37]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[37]_leakage_power avg p(Vgvdd_mux_2level_size50[37]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[37]_in[1]_crossbar param='mux_2level_size50[37]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[37]_dynamic_power avg p(Vgvdd_mux_2level_size50[37]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[37]_energy_per_cycle param='mux_2level_size50[37]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[37]_in[1]_crossbar param='mux_2level_size50[37]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[37]_in[1]_crossbar param='dynamic_power_idle_mux50[37]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[37]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[37]) from='start_rise_idle_mux50[37]_in[1]_crossbar' to='start_rise_idle_mux50[37]_in[1]_crossbar+switch_rise_idle_mux50[37]_in[1]_crossbar' -.meas tran dynamic_fall_idle_mux50[37]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[37]) from='start_fall_idle_mux50[37]_in[1]_crossbar' to='start_fall_idle_mux50[37]_in[1]_crossbar+switch_fall_idle_mux50[37]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to37] -+ param='sum_leakage_power_mux[0to36]+leakage_idle_mux50[37]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to37] -+ param='sum_energy_per_cycle_mux[0to36]+energy_per_cycle_idle_mux50[37]_in[1]_crossbar' -Xload_inv[37]_no0 mux_2level_size50[37]->out mux_2level_size50[37]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to37] -+ param='sum_leakage_power_pb_mux[0to36]+leakage_idle_mux50[37]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to37] -+ param='sum_energy_per_cycle_pb_mux[0to36]+energy_per_cycle_idle_mux50[37]_in[1]_crossbar' -Xmux_2level_size50[38] mux_2level_size50[38]->in[0] mux_2level_size50[38]->in[1] mux_2level_size50[38]->in[2] mux_2level_size50[38]->in[3] mux_2level_size50[38]->in[4] mux_2level_size50[38]->in[5] mux_2level_size50[38]->in[6] mux_2level_size50[38]->in[7] mux_2level_size50[38]->in[8] mux_2level_size50[38]->in[9] mux_2level_size50[38]->in[10] mux_2level_size50[38]->in[11] mux_2level_size50[38]->in[12] mux_2level_size50[38]->in[13] mux_2level_size50[38]->in[14] mux_2level_size50[38]->in[15] mux_2level_size50[38]->in[16] mux_2level_size50[38]->in[17] mux_2level_size50[38]->in[18] mux_2level_size50[38]->in[19] mux_2level_size50[38]->in[20] mux_2level_size50[38]->in[21] mux_2level_size50[38]->in[22] mux_2level_size50[38]->in[23] mux_2level_size50[38]->in[24] mux_2level_size50[38]->in[25] mux_2level_size50[38]->in[26] mux_2level_size50[38]->in[27] mux_2level_size50[38]->in[28] mux_2level_size50[38]->in[29] mux_2level_size50[38]->in[30] mux_2level_size50[38]->in[31] mux_2level_size50[38]->in[32] mux_2level_size50[38]->in[33] mux_2level_size50[38]->in[34] mux_2level_size50[38]->in[35] mux_2level_size50[38]->in[36] mux_2level_size50[38]->in[37] mux_2level_size50[38]->in[38] mux_2level_size50[38]->in[39] mux_2level_size50[38]->in[40] mux_2level_size50[38]->in[41] mux_2level_size50[38]->in[42] mux_2level_size50[38]->in[43] mux_2level_size50[38]->in[44] mux_2level_size50[38]->in[45] mux_2level_size50[38]->in[46] mux_2level_size50[38]->in[47] mux_2level_size50[38]->in[48] mux_2level_size50[38]->in[49] mux_2level_size50[38]->out sram[608]->outb sram[608]->out sram[609]->out sram[609]->outb sram[610]->out sram[610]->outb sram[611]->out sram[611]->outb sram[612]->out sram[612]->outb sram[613]->out sram[613]->outb sram[614]->out sram[614]->outb sram[615]->out sram[615]->outb sram[616]->outb sram[616]->out sram[617]->out sram[617]->outb sram[618]->out sram[618]->outb sram[619]->out sram[619]->outb sram[620]->out sram[620]->outb sram[621]->out sram[621]->outb sram[622]->out sram[622]->outb sram[623]->out sram[623]->outb gvdd_mux_2level_size50[38] 0 mux_2level_size50 -***** SRAM bits for MUX[38], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[608] sram->in sram[608]->out sram[608]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[608]->out) 0 -.nodeset V(sram[608]->outb) vsp -Xsram[609] sram->in sram[609]->out sram[609]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[609]->out) 0 -.nodeset V(sram[609]->outb) vsp -Xsram[610] sram->in sram[610]->out sram[610]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[610]->out) 0 -.nodeset V(sram[610]->outb) vsp -Xsram[611] sram->in sram[611]->out sram[611]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[611]->out) 0 -.nodeset V(sram[611]->outb) vsp -Xsram[612] sram->in sram[612]->out sram[612]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[612]->out) 0 -.nodeset V(sram[612]->outb) vsp -Xsram[613] sram->in sram[613]->out sram[613]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[613]->out) 0 -.nodeset V(sram[613]->outb) vsp -Xsram[614] sram->in sram[614]->out sram[614]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[614]->out) 0 -.nodeset V(sram[614]->outb) vsp -Xsram[615] sram->in sram[615]->out sram[615]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[615]->out) 0 -.nodeset V(sram[615]->outb) vsp -Xsram[616] sram->in sram[616]->out sram[616]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[616]->out) 0 -.nodeset V(sram[616]->outb) vsp -Xsram[617] sram->in sram[617]->out sram[617]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[617]->out) 0 -.nodeset V(sram[617]->outb) vsp -Xsram[618] sram->in sram[618]->out sram[618]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[618]->out) 0 -.nodeset V(sram[618]->outb) vsp -Xsram[619] sram->in sram[619]->out sram[619]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[619]->out) 0 -.nodeset V(sram[619]->outb) vsp -Xsram[620] sram->in sram[620]->out sram[620]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[620]->out) 0 -.nodeset V(sram[620]->outb) vsp -Xsram[621] sram->in sram[621]->out sram[621]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[621]->out) 0 -.nodeset V(sram[621]->outb) vsp -Xsram[622] sram->in sram[622]->out sram[622]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[622]->out) 0 -.nodeset V(sram[622]->outb) vsp -Xsram[623] sram->in sram[623]->out sram[623]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[623]->out) 0 -.nodeset V(sram[623]->outb) vsp -***** Signal mux_2level_size50[38]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[0] mux_2level_size50[38]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[1] mux_2level_size50[38]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[2] mux_2level_size50[38]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[3] mux_2level_size50[38]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[4] mux_2level_size50[38]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[5] mux_2level_size50[38]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[6] mux_2level_size50[38]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[7] mux_2level_size50[38]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[8] mux_2level_size50[38]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[9] mux_2level_size50[38]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[10] mux_2level_size50[38]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[11] mux_2level_size50[38]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[12] mux_2level_size50[38]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[13] mux_2level_size50[38]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[14] mux_2level_size50[38]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[15] mux_2level_size50[38]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[16] mux_2level_size50[38]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[17] mux_2level_size50[38]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[18] mux_2level_size50[38]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[19] mux_2level_size50[38]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[20] mux_2level_size50[38]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[21] mux_2level_size50[38]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[22] mux_2level_size50[38]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[23] mux_2level_size50[38]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[24] mux_2level_size50[38]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[25] mux_2level_size50[38]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[26] mux_2level_size50[38]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[27] mux_2level_size50[38]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[28] mux_2level_size50[38]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[29] mux_2level_size50[38]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[30] mux_2level_size50[38]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[31] mux_2level_size50[38]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[32] mux_2level_size50[38]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[33] mux_2level_size50[38]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[34] mux_2level_size50[38]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[35] mux_2level_size50[38]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[36] mux_2level_size50[38]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[37] mux_2level_size50[38]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[38] mux_2level_size50[38]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[38]->in[39] mux_2level_size50[38]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[38]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[40] mux_2level_size50[38]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[41] mux_2level_size50[38]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[42] mux_2level_size50[38]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[43] mux_2level_size50[38]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[44] mux_2level_size50[38]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[45] mux_2level_size50[38]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[46] mux_2level_size50[38]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[47] mux_2level_size50[38]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[48] mux_2level_size50[38]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[38]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[38]->in[49] mux_2level_size50[38]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[38] gvdd_mux_2level_size50[38] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[38]_in[2]_crossbar trig v(mux_2level_size50[38]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[38]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[38]_in[2]_crossbar trig v(mux_2level_size50[38]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[38]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[38]_in[2]_crossbar when v(mux_2level_size50[38]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[38]_in[2]_crossbar trig v(mux_2level_size50[38]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[38]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[38]_in[2]_crossbar when v(mux_2level_size50[38]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[38]_in[2]_crossbar trig v(mux_2level_size50[38]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[38]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[38]_leakage_power avg p(Vgvdd_mux_2level_size50[38]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[38]_in[2]_crossbar param='mux_2level_size50[38]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[38]_dynamic_power avg p(Vgvdd_mux_2level_size50[38]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[38]_energy_per_cycle param='mux_2level_size50[38]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[38]_in[2]_crossbar param='mux_2level_size50[38]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[38]_in[2]_crossbar param='dynamic_power_idle_mux50[38]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[38]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[38]) from='start_rise_idle_mux50[38]_in[2]_crossbar' to='start_rise_idle_mux50[38]_in[2]_crossbar+switch_rise_idle_mux50[38]_in[2]_crossbar' -.meas tran dynamic_fall_idle_mux50[38]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[38]) from='start_fall_idle_mux50[38]_in[2]_crossbar' to='start_fall_idle_mux50[38]_in[2]_crossbar+switch_fall_idle_mux50[38]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to38] -+ param='sum_leakage_power_mux[0to37]+leakage_idle_mux50[38]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to38] -+ param='sum_energy_per_cycle_mux[0to37]+energy_per_cycle_idle_mux50[38]_in[2]_crossbar' -Xload_inv[38]_no0 mux_2level_size50[38]->out mux_2level_size50[38]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to38] -+ param='sum_leakage_power_pb_mux[0to37]+leakage_idle_mux50[38]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to38] -+ param='sum_energy_per_cycle_pb_mux[0to37]+energy_per_cycle_idle_mux50[38]_in[2]_crossbar' -Xmux_2level_size50[39] mux_2level_size50[39]->in[0] mux_2level_size50[39]->in[1] mux_2level_size50[39]->in[2] mux_2level_size50[39]->in[3] mux_2level_size50[39]->in[4] mux_2level_size50[39]->in[5] mux_2level_size50[39]->in[6] mux_2level_size50[39]->in[7] mux_2level_size50[39]->in[8] mux_2level_size50[39]->in[9] mux_2level_size50[39]->in[10] mux_2level_size50[39]->in[11] mux_2level_size50[39]->in[12] mux_2level_size50[39]->in[13] mux_2level_size50[39]->in[14] mux_2level_size50[39]->in[15] mux_2level_size50[39]->in[16] mux_2level_size50[39]->in[17] mux_2level_size50[39]->in[18] mux_2level_size50[39]->in[19] mux_2level_size50[39]->in[20] mux_2level_size50[39]->in[21] mux_2level_size50[39]->in[22] mux_2level_size50[39]->in[23] mux_2level_size50[39]->in[24] mux_2level_size50[39]->in[25] mux_2level_size50[39]->in[26] mux_2level_size50[39]->in[27] mux_2level_size50[39]->in[28] mux_2level_size50[39]->in[29] mux_2level_size50[39]->in[30] mux_2level_size50[39]->in[31] mux_2level_size50[39]->in[32] mux_2level_size50[39]->in[33] mux_2level_size50[39]->in[34] mux_2level_size50[39]->in[35] mux_2level_size50[39]->in[36] mux_2level_size50[39]->in[37] mux_2level_size50[39]->in[38] mux_2level_size50[39]->in[39] mux_2level_size50[39]->in[40] mux_2level_size50[39]->in[41] mux_2level_size50[39]->in[42] mux_2level_size50[39]->in[43] mux_2level_size50[39]->in[44] mux_2level_size50[39]->in[45] mux_2level_size50[39]->in[46] mux_2level_size50[39]->in[47] mux_2level_size50[39]->in[48] mux_2level_size50[39]->in[49] mux_2level_size50[39]->out sram[624]->outb sram[624]->out sram[625]->out sram[625]->outb sram[626]->out sram[626]->outb sram[627]->out sram[627]->outb sram[628]->out sram[628]->outb sram[629]->out sram[629]->outb sram[630]->out sram[630]->outb sram[631]->out sram[631]->outb sram[632]->outb sram[632]->out sram[633]->out sram[633]->outb sram[634]->out sram[634]->outb sram[635]->out sram[635]->outb sram[636]->out sram[636]->outb sram[637]->out sram[637]->outb sram[638]->out sram[638]->outb sram[639]->out sram[639]->outb gvdd_mux_2level_size50[39] 0 mux_2level_size50 -***** SRAM bits for MUX[39], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[624] sram->in sram[624]->out sram[624]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[624]->out) 0 -.nodeset V(sram[624]->outb) vsp -Xsram[625] sram->in sram[625]->out sram[625]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[625]->out) 0 -.nodeset V(sram[625]->outb) vsp -Xsram[626] sram->in sram[626]->out sram[626]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[626]->out) 0 -.nodeset V(sram[626]->outb) vsp -Xsram[627] sram->in sram[627]->out sram[627]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[627]->out) 0 -.nodeset V(sram[627]->outb) vsp -Xsram[628] sram->in sram[628]->out sram[628]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[628]->out) 0 -.nodeset V(sram[628]->outb) vsp -Xsram[629] sram->in sram[629]->out sram[629]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[629]->out) 0 -.nodeset V(sram[629]->outb) vsp -Xsram[630] sram->in sram[630]->out sram[630]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[630]->out) 0 -.nodeset V(sram[630]->outb) vsp -Xsram[631] sram->in sram[631]->out sram[631]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[631]->out) 0 -.nodeset V(sram[631]->outb) vsp -Xsram[632] sram->in sram[632]->out sram[632]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[632]->out) 0 -.nodeset V(sram[632]->outb) vsp -Xsram[633] sram->in sram[633]->out sram[633]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[633]->out) 0 -.nodeset V(sram[633]->outb) vsp -Xsram[634] sram->in sram[634]->out sram[634]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[634]->out) 0 -.nodeset V(sram[634]->outb) vsp -Xsram[635] sram->in sram[635]->out sram[635]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[635]->out) 0 -.nodeset V(sram[635]->outb) vsp -Xsram[636] sram->in sram[636]->out sram[636]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[636]->out) 0 -.nodeset V(sram[636]->outb) vsp -Xsram[637] sram->in sram[637]->out sram[637]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[637]->out) 0 -.nodeset V(sram[637]->outb) vsp -Xsram[638] sram->in sram[638]->out sram[638]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[638]->out) 0 -.nodeset V(sram[638]->outb) vsp -Xsram[639] sram->in sram[639]->out sram[639]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[639]->out) 0 -.nodeset V(sram[639]->outb) vsp -***** Signal mux_2level_size50[39]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[0] mux_2level_size50[39]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[1] mux_2level_size50[39]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[2] mux_2level_size50[39]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[3] mux_2level_size50[39]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[4] mux_2level_size50[39]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[5] mux_2level_size50[39]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[6] mux_2level_size50[39]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[7] mux_2level_size50[39]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[8] mux_2level_size50[39]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[9] mux_2level_size50[39]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[10] mux_2level_size50[39]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[11] mux_2level_size50[39]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[12] mux_2level_size50[39]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[13] mux_2level_size50[39]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[14] mux_2level_size50[39]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[15] mux_2level_size50[39]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[16] mux_2level_size50[39]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[17] mux_2level_size50[39]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[18] mux_2level_size50[39]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[19] mux_2level_size50[39]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[20] mux_2level_size50[39]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[21] mux_2level_size50[39]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[22] mux_2level_size50[39]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[23] mux_2level_size50[39]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[24] mux_2level_size50[39]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[25] mux_2level_size50[39]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[26] mux_2level_size50[39]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[27] mux_2level_size50[39]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[28] mux_2level_size50[39]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[29] mux_2level_size50[39]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[30] mux_2level_size50[39]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[31] mux_2level_size50[39]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[32] mux_2level_size50[39]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[33] mux_2level_size50[39]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[34] mux_2level_size50[39]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[35] mux_2level_size50[39]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[36] mux_2level_size50[39]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[37] mux_2level_size50[39]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[38] mux_2level_size50[39]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[39]->in[39] mux_2level_size50[39]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[39]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[40] mux_2level_size50[39]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[41] mux_2level_size50[39]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[42] mux_2level_size50[39]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[43] mux_2level_size50[39]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[44] mux_2level_size50[39]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[45] mux_2level_size50[39]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[46] mux_2level_size50[39]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[47] mux_2level_size50[39]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[48] mux_2level_size50[39]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[39]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[39]->in[49] mux_2level_size50[39]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[39] gvdd_mux_2level_size50[39] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[39]_in[3]_crossbar trig v(mux_2level_size50[39]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[39]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[39]_in[3]_crossbar trig v(mux_2level_size50[39]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[39]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[39]_in[3]_crossbar when v(mux_2level_size50[39]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[39]_in[3]_crossbar trig v(mux_2level_size50[39]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[39]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[39]_in[3]_crossbar when v(mux_2level_size50[39]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[39]_in[3]_crossbar trig v(mux_2level_size50[39]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[39]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[39]_leakage_power avg p(Vgvdd_mux_2level_size50[39]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[39]_in[3]_crossbar param='mux_2level_size50[39]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[39]_dynamic_power avg p(Vgvdd_mux_2level_size50[39]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[39]_energy_per_cycle param='mux_2level_size50[39]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[39]_in[3]_crossbar param='mux_2level_size50[39]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[39]_in[3]_crossbar param='dynamic_power_idle_mux50[39]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[39]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[39]) from='start_rise_idle_mux50[39]_in[3]_crossbar' to='start_rise_idle_mux50[39]_in[3]_crossbar+switch_rise_idle_mux50[39]_in[3]_crossbar' -.meas tran dynamic_fall_idle_mux50[39]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[39]) from='start_fall_idle_mux50[39]_in[3]_crossbar' to='start_fall_idle_mux50[39]_in[3]_crossbar+switch_fall_idle_mux50[39]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to39] -+ param='sum_leakage_power_mux[0to38]+leakage_idle_mux50[39]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to39] -+ param='sum_energy_per_cycle_mux[0to38]+energy_per_cycle_idle_mux50[39]_in[3]_crossbar' -Xload_inv[39]_no0 mux_2level_size50[39]->out mux_2level_size50[39]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to39] -+ param='sum_leakage_power_pb_mux[0to38]+leakage_idle_mux50[39]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to39] -+ param='sum_energy_per_cycle_pb_mux[0to38]+energy_per_cycle_idle_mux50[39]_in[3]_crossbar' -Xmux_2level_size50[40] mux_2level_size50[40]->in[0] mux_2level_size50[40]->in[1] mux_2level_size50[40]->in[2] mux_2level_size50[40]->in[3] mux_2level_size50[40]->in[4] mux_2level_size50[40]->in[5] mux_2level_size50[40]->in[6] mux_2level_size50[40]->in[7] mux_2level_size50[40]->in[8] mux_2level_size50[40]->in[9] mux_2level_size50[40]->in[10] mux_2level_size50[40]->in[11] mux_2level_size50[40]->in[12] mux_2level_size50[40]->in[13] mux_2level_size50[40]->in[14] mux_2level_size50[40]->in[15] mux_2level_size50[40]->in[16] mux_2level_size50[40]->in[17] mux_2level_size50[40]->in[18] mux_2level_size50[40]->in[19] mux_2level_size50[40]->in[20] mux_2level_size50[40]->in[21] mux_2level_size50[40]->in[22] mux_2level_size50[40]->in[23] mux_2level_size50[40]->in[24] mux_2level_size50[40]->in[25] mux_2level_size50[40]->in[26] mux_2level_size50[40]->in[27] mux_2level_size50[40]->in[28] mux_2level_size50[40]->in[29] mux_2level_size50[40]->in[30] mux_2level_size50[40]->in[31] mux_2level_size50[40]->in[32] mux_2level_size50[40]->in[33] mux_2level_size50[40]->in[34] mux_2level_size50[40]->in[35] mux_2level_size50[40]->in[36] mux_2level_size50[40]->in[37] mux_2level_size50[40]->in[38] mux_2level_size50[40]->in[39] mux_2level_size50[40]->in[40] mux_2level_size50[40]->in[41] mux_2level_size50[40]->in[42] mux_2level_size50[40]->in[43] mux_2level_size50[40]->in[44] mux_2level_size50[40]->in[45] mux_2level_size50[40]->in[46] mux_2level_size50[40]->in[47] mux_2level_size50[40]->in[48] mux_2level_size50[40]->in[49] mux_2level_size50[40]->out sram[640]->outb sram[640]->out sram[641]->out sram[641]->outb sram[642]->out sram[642]->outb sram[643]->out sram[643]->outb sram[644]->out sram[644]->outb sram[645]->out sram[645]->outb sram[646]->out sram[646]->outb sram[647]->out sram[647]->outb sram[648]->outb sram[648]->out sram[649]->out sram[649]->outb sram[650]->out sram[650]->outb sram[651]->out sram[651]->outb sram[652]->out sram[652]->outb sram[653]->out sram[653]->outb sram[654]->out sram[654]->outb sram[655]->out sram[655]->outb gvdd_mux_2level_size50[40] 0 mux_2level_size50 -***** SRAM bits for MUX[40], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[640] sram->in sram[640]->out sram[640]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[640]->out) 0 -.nodeset V(sram[640]->outb) vsp -Xsram[641] sram->in sram[641]->out sram[641]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[641]->out) 0 -.nodeset V(sram[641]->outb) vsp -Xsram[642] sram->in sram[642]->out sram[642]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[642]->out) 0 -.nodeset V(sram[642]->outb) vsp -Xsram[643] sram->in sram[643]->out sram[643]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[643]->out) 0 -.nodeset V(sram[643]->outb) vsp -Xsram[644] sram->in sram[644]->out sram[644]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[644]->out) 0 -.nodeset V(sram[644]->outb) vsp -Xsram[645] sram->in sram[645]->out sram[645]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[645]->out) 0 -.nodeset V(sram[645]->outb) vsp -Xsram[646] sram->in sram[646]->out sram[646]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[646]->out) 0 -.nodeset V(sram[646]->outb) vsp -Xsram[647] sram->in sram[647]->out sram[647]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[647]->out) 0 -.nodeset V(sram[647]->outb) vsp -Xsram[648] sram->in sram[648]->out sram[648]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[648]->out) 0 -.nodeset V(sram[648]->outb) vsp -Xsram[649] sram->in sram[649]->out sram[649]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[649]->out) 0 -.nodeset V(sram[649]->outb) vsp -Xsram[650] sram->in sram[650]->out sram[650]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[650]->out) 0 -.nodeset V(sram[650]->outb) vsp -Xsram[651] sram->in sram[651]->out sram[651]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[651]->out) 0 -.nodeset V(sram[651]->outb) vsp -Xsram[652] sram->in sram[652]->out sram[652]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[652]->out) 0 -.nodeset V(sram[652]->outb) vsp -Xsram[653] sram->in sram[653]->out sram[653]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[653]->out) 0 -.nodeset V(sram[653]->outb) vsp -Xsram[654] sram->in sram[654]->out sram[654]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[654]->out) 0 -.nodeset V(sram[654]->outb) vsp -Xsram[655] sram->in sram[655]->out sram[655]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[655]->out) 0 -.nodeset V(sram[655]->outb) vsp -***** Signal mux_2level_size50[40]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[0] mux_2level_size50[40]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[1] mux_2level_size50[40]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[2] mux_2level_size50[40]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[3] mux_2level_size50[40]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[4] mux_2level_size50[40]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[5] mux_2level_size50[40]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[6] mux_2level_size50[40]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[7] mux_2level_size50[40]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[8] mux_2level_size50[40]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[9] mux_2level_size50[40]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[10] mux_2level_size50[40]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[11] mux_2level_size50[40]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[12] mux_2level_size50[40]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[13] mux_2level_size50[40]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[14] mux_2level_size50[40]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[15] mux_2level_size50[40]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[16] mux_2level_size50[40]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[17] mux_2level_size50[40]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[18] mux_2level_size50[40]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[19] mux_2level_size50[40]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[20] mux_2level_size50[40]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[21] mux_2level_size50[40]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[22] mux_2level_size50[40]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[23] mux_2level_size50[40]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[24] mux_2level_size50[40]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[25] mux_2level_size50[40]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[26] mux_2level_size50[40]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[27] mux_2level_size50[40]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[28] mux_2level_size50[40]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[29] mux_2level_size50[40]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[30] mux_2level_size50[40]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[31] mux_2level_size50[40]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[32] mux_2level_size50[40]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[33] mux_2level_size50[40]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[34] mux_2level_size50[40]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[35] mux_2level_size50[40]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[36] mux_2level_size50[40]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[37] mux_2level_size50[40]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[38] mux_2level_size50[40]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[40]->in[39] mux_2level_size50[40]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[40]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[40] mux_2level_size50[40]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[41] mux_2level_size50[40]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[42] mux_2level_size50[40]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[43] mux_2level_size50[40]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[44] mux_2level_size50[40]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[45] mux_2level_size50[40]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[46] mux_2level_size50[40]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[47] mux_2level_size50[40]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[48] mux_2level_size50[40]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[40]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[40]->in[49] mux_2level_size50[40]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[40] gvdd_mux_2level_size50[40] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[40]_in[4]_crossbar trig v(mux_2level_size50[40]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[40]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[40]_in[4]_crossbar trig v(mux_2level_size50[40]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[40]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[40]_in[4]_crossbar when v(mux_2level_size50[40]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[40]_in[4]_crossbar trig v(mux_2level_size50[40]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[40]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[40]_in[4]_crossbar when v(mux_2level_size50[40]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[40]_in[4]_crossbar trig v(mux_2level_size50[40]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[40]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[40]_leakage_power avg p(Vgvdd_mux_2level_size50[40]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[40]_in[4]_crossbar param='mux_2level_size50[40]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[40]_dynamic_power avg p(Vgvdd_mux_2level_size50[40]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[40]_energy_per_cycle param='mux_2level_size50[40]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[40]_in[4]_crossbar param='mux_2level_size50[40]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[40]_in[4]_crossbar param='dynamic_power_idle_mux50[40]_in[4]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[40]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[40]) from='start_rise_idle_mux50[40]_in[4]_crossbar' to='start_rise_idle_mux50[40]_in[4]_crossbar+switch_rise_idle_mux50[40]_in[4]_crossbar' -.meas tran dynamic_fall_idle_mux50[40]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[40]) from='start_fall_idle_mux50[40]_in[4]_crossbar' to='start_fall_idle_mux50[40]_in[4]_crossbar+switch_fall_idle_mux50[40]_in[4]_crossbar' -.meas tran sum_leakage_power_mux[0to40] -+ param='sum_leakage_power_mux[0to39]+leakage_idle_mux50[40]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to40] -+ param='sum_energy_per_cycle_mux[0to39]+energy_per_cycle_idle_mux50[40]_in[4]_crossbar' -Xload_inv[40]_no0 mux_2level_size50[40]->out mux_2level_size50[40]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to40] -+ param='sum_leakage_power_pb_mux[0to39]+leakage_idle_mux50[40]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to40] -+ param='sum_energy_per_cycle_pb_mux[0to39]+energy_per_cycle_idle_mux50[40]_in[4]_crossbar' -Xmux_2level_size50[41] mux_2level_size50[41]->in[0] mux_2level_size50[41]->in[1] mux_2level_size50[41]->in[2] mux_2level_size50[41]->in[3] mux_2level_size50[41]->in[4] mux_2level_size50[41]->in[5] mux_2level_size50[41]->in[6] mux_2level_size50[41]->in[7] mux_2level_size50[41]->in[8] mux_2level_size50[41]->in[9] mux_2level_size50[41]->in[10] mux_2level_size50[41]->in[11] mux_2level_size50[41]->in[12] mux_2level_size50[41]->in[13] mux_2level_size50[41]->in[14] mux_2level_size50[41]->in[15] mux_2level_size50[41]->in[16] mux_2level_size50[41]->in[17] mux_2level_size50[41]->in[18] mux_2level_size50[41]->in[19] mux_2level_size50[41]->in[20] mux_2level_size50[41]->in[21] mux_2level_size50[41]->in[22] mux_2level_size50[41]->in[23] mux_2level_size50[41]->in[24] mux_2level_size50[41]->in[25] mux_2level_size50[41]->in[26] mux_2level_size50[41]->in[27] mux_2level_size50[41]->in[28] mux_2level_size50[41]->in[29] mux_2level_size50[41]->in[30] mux_2level_size50[41]->in[31] mux_2level_size50[41]->in[32] mux_2level_size50[41]->in[33] mux_2level_size50[41]->in[34] mux_2level_size50[41]->in[35] mux_2level_size50[41]->in[36] mux_2level_size50[41]->in[37] mux_2level_size50[41]->in[38] mux_2level_size50[41]->in[39] mux_2level_size50[41]->in[40] mux_2level_size50[41]->in[41] mux_2level_size50[41]->in[42] mux_2level_size50[41]->in[43] mux_2level_size50[41]->in[44] mux_2level_size50[41]->in[45] mux_2level_size50[41]->in[46] mux_2level_size50[41]->in[47] mux_2level_size50[41]->in[48] mux_2level_size50[41]->in[49] mux_2level_size50[41]->out sram[656]->outb sram[656]->out sram[657]->out sram[657]->outb sram[658]->out sram[658]->outb sram[659]->out sram[659]->outb sram[660]->out sram[660]->outb sram[661]->out sram[661]->outb sram[662]->out sram[662]->outb sram[663]->out sram[663]->outb sram[664]->outb sram[664]->out sram[665]->out sram[665]->outb sram[666]->out sram[666]->outb sram[667]->out sram[667]->outb sram[668]->out sram[668]->outb sram[669]->out sram[669]->outb sram[670]->out sram[670]->outb sram[671]->out sram[671]->outb gvdd_mux_2level_size50[41] 0 mux_2level_size50 -***** SRAM bits for MUX[41], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[656] sram->in sram[656]->out sram[656]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[656]->out) 0 -.nodeset V(sram[656]->outb) vsp -Xsram[657] sram->in sram[657]->out sram[657]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[657]->out) 0 -.nodeset V(sram[657]->outb) vsp -Xsram[658] sram->in sram[658]->out sram[658]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[658]->out) 0 -.nodeset V(sram[658]->outb) vsp -Xsram[659] sram->in sram[659]->out sram[659]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[659]->out) 0 -.nodeset V(sram[659]->outb) vsp -Xsram[660] sram->in sram[660]->out sram[660]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[660]->out) 0 -.nodeset V(sram[660]->outb) vsp -Xsram[661] sram->in sram[661]->out sram[661]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[661]->out) 0 -.nodeset V(sram[661]->outb) vsp -Xsram[662] sram->in sram[662]->out sram[662]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[662]->out) 0 -.nodeset V(sram[662]->outb) vsp -Xsram[663] sram->in sram[663]->out sram[663]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[663]->out) 0 -.nodeset V(sram[663]->outb) vsp -Xsram[664] sram->in sram[664]->out sram[664]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[664]->out) 0 -.nodeset V(sram[664]->outb) vsp -Xsram[665] sram->in sram[665]->out sram[665]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[665]->out) 0 -.nodeset V(sram[665]->outb) vsp -Xsram[666] sram->in sram[666]->out sram[666]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[666]->out) 0 -.nodeset V(sram[666]->outb) vsp -Xsram[667] sram->in sram[667]->out sram[667]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[667]->out) 0 -.nodeset V(sram[667]->outb) vsp -Xsram[668] sram->in sram[668]->out sram[668]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[668]->out) 0 -.nodeset V(sram[668]->outb) vsp -Xsram[669] sram->in sram[669]->out sram[669]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[669]->out) 0 -.nodeset V(sram[669]->outb) vsp -Xsram[670] sram->in sram[670]->out sram[670]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[670]->out) 0 -.nodeset V(sram[670]->outb) vsp -Xsram[671] sram->in sram[671]->out sram[671]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[671]->out) 0 -.nodeset V(sram[671]->outb) vsp -***** Signal mux_2level_size50[41]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[0] mux_2level_size50[41]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[1] mux_2level_size50[41]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[2] mux_2level_size50[41]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[3] mux_2level_size50[41]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[4] mux_2level_size50[41]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[5] mux_2level_size50[41]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[6] mux_2level_size50[41]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[7] mux_2level_size50[41]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[8] mux_2level_size50[41]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[9] mux_2level_size50[41]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[10] mux_2level_size50[41]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[11] mux_2level_size50[41]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[12] mux_2level_size50[41]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[13] mux_2level_size50[41]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[14] mux_2level_size50[41]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[15] mux_2level_size50[41]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[16] mux_2level_size50[41]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[17] mux_2level_size50[41]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[18] mux_2level_size50[41]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[19] mux_2level_size50[41]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[20] mux_2level_size50[41]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[21] mux_2level_size50[41]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[22] mux_2level_size50[41]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[23] mux_2level_size50[41]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[24] mux_2level_size50[41]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[25] mux_2level_size50[41]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[26] mux_2level_size50[41]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[27] mux_2level_size50[41]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[28] mux_2level_size50[41]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[29] mux_2level_size50[41]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[30] mux_2level_size50[41]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[31] mux_2level_size50[41]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[32] mux_2level_size50[41]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[33] mux_2level_size50[41]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[34] mux_2level_size50[41]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[35] mux_2level_size50[41]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[36] mux_2level_size50[41]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[37] mux_2level_size50[41]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[38] mux_2level_size50[41]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[41]->in[39] mux_2level_size50[41]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[41]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[40] mux_2level_size50[41]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[41] mux_2level_size50[41]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[42] mux_2level_size50[41]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[43] mux_2level_size50[41]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[44] mux_2level_size50[41]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[45] mux_2level_size50[41]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[46] mux_2level_size50[41]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[47] mux_2level_size50[41]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[48] mux_2level_size50[41]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[41]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[41]->in[49] mux_2level_size50[41]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[41] gvdd_mux_2level_size50[41] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[41]_in[5]_crossbar trig v(mux_2level_size50[41]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[41]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[41]_in[5]_crossbar trig v(mux_2level_size50[41]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[41]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[41]_in[5]_crossbar when v(mux_2level_size50[41]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[41]_in[5]_crossbar trig v(mux_2level_size50[41]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[41]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[41]_in[5]_crossbar when v(mux_2level_size50[41]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[41]_in[5]_crossbar trig v(mux_2level_size50[41]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[41]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[41]_leakage_power avg p(Vgvdd_mux_2level_size50[41]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[41]_in[5]_crossbar param='mux_2level_size50[41]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[41]_dynamic_power avg p(Vgvdd_mux_2level_size50[41]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[41]_energy_per_cycle param='mux_2level_size50[41]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[41]_in[5]_crossbar param='mux_2level_size50[41]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[41]_in[5]_crossbar param='dynamic_power_idle_mux50[41]_in[5]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[41]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[41]) from='start_rise_idle_mux50[41]_in[5]_crossbar' to='start_rise_idle_mux50[41]_in[5]_crossbar+switch_rise_idle_mux50[41]_in[5]_crossbar' -.meas tran dynamic_fall_idle_mux50[41]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[41]) from='start_fall_idle_mux50[41]_in[5]_crossbar' to='start_fall_idle_mux50[41]_in[5]_crossbar+switch_fall_idle_mux50[41]_in[5]_crossbar' -.meas tran sum_leakage_power_mux[0to41] -+ param='sum_leakage_power_mux[0to40]+leakage_idle_mux50[41]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to41] -+ param='sum_energy_per_cycle_mux[0to40]+energy_per_cycle_idle_mux50[41]_in[5]_crossbar' -Xload_inv[41]_no0 mux_2level_size50[41]->out mux_2level_size50[41]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to41] -+ param='sum_leakage_power_pb_mux[0to40]+leakage_idle_mux50[41]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to41] -+ param='sum_energy_per_cycle_pb_mux[0to40]+energy_per_cycle_idle_mux50[41]_in[5]_crossbar' -Xmux_2level_size50[42] mux_2level_size50[42]->in[0] mux_2level_size50[42]->in[1] mux_2level_size50[42]->in[2] mux_2level_size50[42]->in[3] mux_2level_size50[42]->in[4] mux_2level_size50[42]->in[5] mux_2level_size50[42]->in[6] mux_2level_size50[42]->in[7] mux_2level_size50[42]->in[8] mux_2level_size50[42]->in[9] mux_2level_size50[42]->in[10] mux_2level_size50[42]->in[11] mux_2level_size50[42]->in[12] mux_2level_size50[42]->in[13] mux_2level_size50[42]->in[14] mux_2level_size50[42]->in[15] mux_2level_size50[42]->in[16] mux_2level_size50[42]->in[17] mux_2level_size50[42]->in[18] mux_2level_size50[42]->in[19] mux_2level_size50[42]->in[20] mux_2level_size50[42]->in[21] mux_2level_size50[42]->in[22] mux_2level_size50[42]->in[23] mux_2level_size50[42]->in[24] mux_2level_size50[42]->in[25] mux_2level_size50[42]->in[26] mux_2level_size50[42]->in[27] mux_2level_size50[42]->in[28] mux_2level_size50[42]->in[29] mux_2level_size50[42]->in[30] mux_2level_size50[42]->in[31] mux_2level_size50[42]->in[32] mux_2level_size50[42]->in[33] mux_2level_size50[42]->in[34] mux_2level_size50[42]->in[35] mux_2level_size50[42]->in[36] mux_2level_size50[42]->in[37] mux_2level_size50[42]->in[38] mux_2level_size50[42]->in[39] mux_2level_size50[42]->in[40] mux_2level_size50[42]->in[41] mux_2level_size50[42]->in[42] mux_2level_size50[42]->in[43] mux_2level_size50[42]->in[44] mux_2level_size50[42]->in[45] mux_2level_size50[42]->in[46] mux_2level_size50[42]->in[47] mux_2level_size50[42]->in[48] mux_2level_size50[42]->in[49] mux_2level_size50[42]->out sram[672]->outb sram[672]->out sram[673]->out sram[673]->outb sram[674]->out sram[674]->outb sram[675]->out sram[675]->outb sram[676]->out sram[676]->outb sram[677]->out sram[677]->outb sram[678]->out sram[678]->outb sram[679]->out sram[679]->outb sram[680]->outb sram[680]->out sram[681]->out sram[681]->outb sram[682]->out sram[682]->outb sram[683]->out sram[683]->outb sram[684]->out sram[684]->outb sram[685]->out sram[685]->outb sram[686]->out sram[686]->outb sram[687]->out sram[687]->outb gvdd_mux_2level_size50[42] 0 mux_2level_size50 -***** SRAM bits for MUX[42], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[672] sram->in sram[672]->out sram[672]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[672]->out) 0 -.nodeset V(sram[672]->outb) vsp -Xsram[673] sram->in sram[673]->out sram[673]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[673]->out) 0 -.nodeset V(sram[673]->outb) vsp -Xsram[674] sram->in sram[674]->out sram[674]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[674]->out) 0 -.nodeset V(sram[674]->outb) vsp -Xsram[675] sram->in sram[675]->out sram[675]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[675]->out) 0 -.nodeset V(sram[675]->outb) vsp -Xsram[676] sram->in sram[676]->out sram[676]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[676]->out) 0 -.nodeset V(sram[676]->outb) vsp -Xsram[677] sram->in sram[677]->out sram[677]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[677]->out) 0 -.nodeset V(sram[677]->outb) vsp -Xsram[678] sram->in sram[678]->out sram[678]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[678]->out) 0 -.nodeset V(sram[678]->outb) vsp -Xsram[679] sram->in sram[679]->out sram[679]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[679]->out) 0 -.nodeset V(sram[679]->outb) vsp -Xsram[680] sram->in sram[680]->out sram[680]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[680]->out) 0 -.nodeset V(sram[680]->outb) vsp -Xsram[681] sram->in sram[681]->out sram[681]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[681]->out) 0 -.nodeset V(sram[681]->outb) vsp -Xsram[682] sram->in sram[682]->out sram[682]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[682]->out) 0 -.nodeset V(sram[682]->outb) vsp -Xsram[683] sram->in sram[683]->out sram[683]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[683]->out) 0 -.nodeset V(sram[683]->outb) vsp -Xsram[684] sram->in sram[684]->out sram[684]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[684]->out) 0 -.nodeset V(sram[684]->outb) vsp -Xsram[685] sram->in sram[685]->out sram[685]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[685]->out) 0 -.nodeset V(sram[685]->outb) vsp -Xsram[686] sram->in sram[686]->out sram[686]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[686]->out) 0 -.nodeset V(sram[686]->outb) vsp -Xsram[687] sram->in sram[687]->out sram[687]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[687]->out) 0 -.nodeset V(sram[687]->outb) vsp -***** Signal mux_2level_size50[42]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[0] mux_2level_size50[42]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[1] mux_2level_size50[42]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[2] mux_2level_size50[42]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[3] mux_2level_size50[42]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[4] mux_2level_size50[42]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[5] mux_2level_size50[42]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[6] mux_2level_size50[42]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[7] mux_2level_size50[42]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[8] mux_2level_size50[42]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[9] mux_2level_size50[42]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[10] mux_2level_size50[42]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[11] mux_2level_size50[42]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[12] mux_2level_size50[42]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[13] mux_2level_size50[42]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[14] mux_2level_size50[42]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[15] mux_2level_size50[42]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[16] mux_2level_size50[42]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[17] mux_2level_size50[42]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[18] mux_2level_size50[42]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[19] mux_2level_size50[42]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[20] mux_2level_size50[42]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[21] mux_2level_size50[42]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[22] mux_2level_size50[42]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[23] mux_2level_size50[42]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[24] mux_2level_size50[42]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[25] mux_2level_size50[42]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[26] mux_2level_size50[42]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[27] mux_2level_size50[42]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[28] mux_2level_size50[42]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[29] mux_2level_size50[42]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[30] mux_2level_size50[42]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[31] mux_2level_size50[42]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[32] mux_2level_size50[42]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[33] mux_2level_size50[42]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[34] mux_2level_size50[42]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[35] mux_2level_size50[42]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[36] mux_2level_size50[42]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[37] mux_2level_size50[42]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[38] mux_2level_size50[42]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[42]->in[39] mux_2level_size50[42]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[42]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[40] mux_2level_size50[42]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[41] mux_2level_size50[42]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[42] mux_2level_size50[42]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[43] mux_2level_size50[42]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[44] mux_2level_size50[42]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[45] mux_2level_size50[42]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[46] mux_2level_size50[42]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[47] mux_2level_size50[42]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[48] mux_2level_size50[42]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[42]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[42]->in[49] mux_2level_size50[42]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[42] gvdd_mux_2level_size50[42] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[42]_in[0]_crossbar trig v(mux_2level_size50[42]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[42]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[42]_in[0]_crossbar trig v(mux_2level_size50[42]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[42]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[42]_in[0]_crossbar when v(mux_2level_size50[42]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[42]_in[0]_crossbar trig v(mux_2level_size50[42]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[42]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[42]_in[0]_crossbar when v(mux_2level_size50[42]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[42]_in[0]_crossbar trig v(mux_2level_size50[42]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[42]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[42]_leakage_power avg p(Vgvdd_mux_2level_size50[42]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[42]_in[0]_crossbar param='mux_2level_size50[42]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[42]_dynamic_power avg p(Vgvdd_mux_2level_size50[42]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[42]_energy_per_cycle param='mux_2level_size50[42]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[42]_in[0]_crossbar param='mux_2level_size50[42]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[42]_in[0]_crossbar param='dynamic_power_idle_mux50[42]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[42]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[42]) from='start_rise_idle_mux50[42]_in[0]_crossbar' to='start_rise_idle_mux50[42]_in[0]_crossbar+switch_rise_idle_mux50[42]_in[0]_crossbar' -.meas tran dynamic_fall_idle_mux50[42]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[42]) from='start_fall_idle_mux50[42]_in[0]_crossbar' to='start_fall_idle_mux50[42]_in[0]_crossbar+switch_fall_idle_mux50[42]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to42] -+ param='sum_leakage_power_mux[0to41]+leakage_idle_mux50[42]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to42] -+ param='sum_energy_per_cycle_mux[0to41]+energy_per_cycle_idle_mux50[42]_in[0]_crossbar' -Xload_inv[42]_no0 mux_2level_size50[42]->out mux_2level_size50[42]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to42] -+ param='sum_leakage_power_pb_mux[0to41]+leakage_idle_mux50[42]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to42] -+ param='sum_energy_per_cycle_pb_mux[0to41]+energy_per_cycle_idle_mux50[42]_in[0]_crossbar' -Xmux_2level_size50[43] mux_2level_size50[43]->in[0] mux_2level_size50[43]->in[1] mux_2level_size50[43]->in[2] mux_2level_size50[43]->in[3] mux_2level_size50[43]->in[4] mux_2level_size50[43]->in[5] mux_2level_size50[43]->in[6] mux_2level_size50[43]->in[7] mux_2level_size50[43]->in[8] mux_2level_size50[43]->in[9] mux_2level_size50[43]->in[10] mux_2level_size50[43]->in[11] mux_2level_size50[43]->in[12] mux_2level_size50[43]->in[13] mux_2level_size50[43]->in[14] mux_2level_size50[43]->in[15] mux_2level_size50[43]->in[16] mux_2level_size50[43]->in[17] mux_2level_size50[43]->in[18] mux_2level_size50[43]->in[19] mux_2level_size50[43]->in[20] mux_2level_size50[43]->in[21] mux_2level_size50[43]->in[22] mux_2level_size50[43]->in[23] mux_2level_size50[43]->in[24] mux_2level_size50[43]->in[25] mux_2level_size50[43]->in[26] mux_2level_size50[43]->in[27] mux_2level_size50[43]->in[28] mux_2level_size50[43]->in[29] mux_2level_size50[43]->in[30] mux_2level_size50[43]->in[31] mux_2level_size50[43]->in[32] mux_2level_size50[43]->in[33] mux_2level_size50[43]->in[34] mux_2level_size50[43]->in[35] mux_2level_size50[43]->in[36] mux_2level_size50[43]->in[37] mux_2level_size50[43]->in[38] mux_2level_size50[43]->in[39] mux_2level_size50[43]->in[40] mux_2level_size50[43]->in[41] mux_2level_size50[43]->in[42] mux_2level_size50[43]->in[43] mux_2level_size50[43]->in[44] mux_2level_size50[43]->in[45] mux_2level_size50[43]->in[46] mux_2level_size50[43]->in[47] mux_2level_size50[43]->in[48] mux_2level_size50[43]->in[49] mux_2level_size50[43]->out sram[688]->outb sram[688]->out sram[689]->out sram[689]->outb sram[690]->out sram[690]->outb sram[691]->out sram[691]->outb sram[692]->out sram[692]->outb sram[693]->out sram[693]->outb sram[694]->out sram[694]->outb sram[695]->out sram[695]->outb sram[696]->outb sram[696]->out sram[697]->out sram[697]->outb sram[698]->out sram[698]->outb sram[699]->out sram[699]->outb sram[700]->out sram[700]->outb sram[701]->out sram[701]->outb sram[702]->out sram[702]->outb sram[703]->out sram[703]->outb gvdd_mux_2level_size50[43] 0 mux_2level_size50 -***** SRAM bits for MUX[43], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[688] sram->in sram[688]->out sram[688]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[688]->out) 0 -.nodeset V(sram[688]->outb) vsp -Xsram[689] sram->in sram[689]->out sram[689]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[689]->out) 0 -.nodeset V(sram[689]->outb) vsp -Xsram[690] sram->in sram[690]->out sram[690]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[690]->out) 0 -.nodeset V(sram[690]->outb) vsp -Xsram[691] sram->in sram[691]->out sram[691]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[691]->out) 0 -.nodeset V(sram[691]->outb) vsp -Xsram[692] sram->in sram[692]->out sram[692]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[692]->out) 0 -.nodeset V(sram[692]->outb) vsp -Xsram[693] sram->in sram[693]->out sram[693]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[693]->out) 0 -.nodeset V(sram[693]->outb) vsp -Xsram[694] sram->in sram[694]->out sram[694]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[694]->out) 0 -.nodeset V(sram[694]->outb) vsp -Xsram[695] sram->in sram[695]->out sram[695]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[695]->out) 0 -.nodeset V(sram[695]->outb) vsp -Xsram[696] sram->in sram[696]->out sram[696]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[696]->out) 0 -.nodeset V(sram[696]->outb) vsp -Xsram[697] sram->in sram[697]->out sram[697]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[697]->out) 0 -.nodeset V(sram[697]->outb) vsp -Xsram[698] sram->in sram[698]->out sram[698]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[698]->out) 0 -.nodeset V(sram[698]->outb) vsp -Xsram[699] sram->in sram[699]->out sram[699]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[699]->out) 0 -.nodeset V(sram[699]->outb) vsp -Xsram[700] sram->in sram[700]->out sram[700]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[700]->out) 0 -.nodeset V(sram[700]->outb) vsp -Xsram[701] sram->in sram[701]->out sram[701]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[701]->out) 0 -.nodeset V(sram[701]->outb) vsp -Xsram[702] sram->in sram[702]->out sram[702]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[702]->out) 0 -.nodeset V(sram[702]->outb) vsp -Xsram[703] sram->in sram[703]->out sram[703]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[703]->out) 0 -.nodeset V(sram[703]->outb) vsp -***** Signal mux_2level_size50[43]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[0] mux_2level_size50[43]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[1] mux_2level_size50[43]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[2] mux_2level_size50[43]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[3] mux_2level_size50[43]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[4] mux_2level_size50[43]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[5] mux_2level_size50[43]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[6] mux_2level_size50[43]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[7] mux_2level_size50[43]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[8] mux_2level_size50[43]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[9] mux_2level_size50[43]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[10] mux_2level_size50[43]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[11] mux_2level_size50[43]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[12] mux_2level_size50[43]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[13] mux_2level_size50[43]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[14] mux_2level_size50[43]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[15] mux_2level_size50[43]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[16] mux_2level_size50[43]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[17] mux_2level_size50[43]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[18] mux_2level_size50[43]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[19] mux_2level_size50[43]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[20] mux_2level_size50[43]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[21] mux_2level_size50[43]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[22] mux_2level_size50[43]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[23] mux_2level_size50[43]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[24] mux_2level_size50[43]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[25] mux_2level_size50[43]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[26] mux_2level_size50[43]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[27] mux_2level_size50[43]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[28] mux_2level_size50[43]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[29] mux_2level_size50[43]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[30] mux_2level_size50[43]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[31] mux_2level_size50[43]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[32] mux_2level_size50[43]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[33] mux_2level_size50[43]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[34] mux_2level_size50[43]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[35] mux_2level_size50[43]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[36] mux_2level_size50[43]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[37] mux_2level_size50[43]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[38] mux_2level_size50[43]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[43]->in[39] mux_2level_size50[43]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[43]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[40] mux_2level_size50[43]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[41] mux_2level_size50[43]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[42] mux_2level_size50[43]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[43] mux_2level_size50[43]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[44] mux_2level_size50[43]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[45] mux_2level_size50[43]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[46] mux_2level_size50[43]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[47] mux_2level_size50[43]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[48] mux_2level_size50[43]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[43]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[43]->in[49] mux_2level_size50[43]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[43] gvdd_mux_2level_size50[43] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[43]_in[1]_crossbar trig v(mux_2level_size50[43]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[43]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[43]_in[1]_crossbar trig v(mux_2level_size50[43]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[43]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[43]_in[1]_crossbar when v(mux_2level_size50[43]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[43]_in[1]_crossbar trig v(mux_2level_size50[43]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[43]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[43]_in[1]_crossbar when v(mux_2level_size50[43]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[43]_in[1]_crossbar trig v(mux_2level_size50[43]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[43]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[43]_leakage_power avg p(Vgvdd_mux_2level_size50[43]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[43]_in[1]_crossbar param='mux_2level_size50[43]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[43]_dynamic_power avg p(Vgvdd_mux_2level_size50[43]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[43]_energy_per_cycle param='mux_2level_size50[43]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[43]_in[1]_crossbar param='mux_2level_size50[43]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[43]_in[1]_crossbar param='dynamic_power_idle_mux50[43]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[43]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[43]) from='start_rise_idle_mux50[43]_in[1]_crossbar' to='start_rise_idle_mux50[43]_in[1]_crossbar+switch_rise_idle_mux50[43]_in[1]_crossbar' -.meas tran dynamic_fall_idle_mux50[43]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[43]) from='start_fall_idle_mux50[43]_in[1]_crossbar' to='start_fall_idle_mux50[43]_in[1]_crossbar+switch_fall_idle_mux50[43]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to43] -+ param='sum_leakage_power_mux[0to42]+leakage_idle_mux50[43]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to43] -+ param='sum_energy_per_cycle_mux[0to42]+energy_per_cycle_idle_mux50[43]_in[1]_crossbar' -Xload_inv[43]_no0 mux_2level_size50[43]->out mux_2level_size50[43]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to43] -+ param='sum_leakage_power_pb_mux[0to42]+leakage_idle_mux50[43]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to43] -+ param='sum_energy_per_cycle_pb_mux[0to42]+energy_per_cycle_idle_mux50[43]_in[1]_crossbar' -Xmux_2level_size50[44] mux_2level_size50[44]->in[0] mux_2level_size50[44]->in[1] mux_2level_size50[44]->in[2] mux_2level_size50[44]->in[3] mux_2level_size50[44]->in[4] mux_2level_size50[44]->in[5] mux_2level_size50[44]->in[6] mux_2level_size50[44]->in[7] mux_2level_size50[44]->in[8] mux_2level_size50[44]->in[9] mux_2level_size50[44]->in[10] mux_2level_size50[44]->in[11] mux_2level_size50[44]->in[12] mux_2level_size50[44]->in[13] mux_2level_size50[44]->in[14] mux_2level_size50[44]->in[15] mux_2level_size50[44]->in[16] mux_2level_size50[44]->in[17] mux_2level_size50[44]->in[18] mux_2level_size50[44]->in[19] mux_2level_size50[44]->in[20] mux_2level_size50[44]->in[21] mux_2level_size50[44]->in[22] mux_2level_size50[44]->in[23] mux_2level_size50[44]->in[24] mux_2level_size50[44]->in[25] mux_2level_size50[44]->in[26] mux_2level_size50[44]->in[27] mux_2level_size50[44]->in[28] mux_2level_size50[44]->in[29] mux_2level_size50[44]->in[30] mux_2level_size50[44]->in[31] mux_2level_size50[44]->in[32] mux_2level_size50[44]->in[33] mux_2level_size50[44]->in[34] mux_2level_size50[44]->in[35] mux_2level_size50[44]->in[36] mux_2level_size50[44]->in[37] mux_2level_size50[44]->in[38] mux_2level_size50[44]->in[39] mux_2level_size50[44]->in[40] mux_2level_size50[44]->in[41] mux_2level_size50[44]->in[42] mux_2level_size50[44]->in[43] mux_2level_size50[44]->in[44] mux_2level_size50[44]->in[45] mux_2level_size50[44]->in[46] mux_2level_size50[44]->in[47] mux_2level_size50[44]->in[48] mux_2level_size50[44]->in[49] mux_2level_size50[44]->out sram[704]->outb sram[704]->out sram[705]->out sram[705]->outb sram[706]->out sram[706]->outb sram[707]->out sram[707]->outb sram[708]->out sram[708]->outb sram[709]->out sram[709]->outb sram[710]->out sram[710]->outb sram[711]->out sram[711]->outb sram[712]->outb sram[712]->out sram[713]->out sram[713]->outb sram[714]->out sram[714]->outb sram[715]->out sram[715]->outb sram[716]->out sram[716]->outb sram[717]->out sram[717]->outb sram[718]->out sram[718]->outb sram[719]->out sram[719]->outb gvdd_mux_2level_size50[44] 0 mux_2level_size50 -***** SRAM bits for MUX[44], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[704] sram->in sram[704]->out sram[704]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[704]->out) 0 -.nodeset V(sram[704]->outb) vsp -Xsram[705] sram->in sram[705]->out sram[705]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[705]->out) 0 -.nodeset V(sram[705]->outb) vsp -Xsram[706] sram->in sram[706]->out sram[706]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[706]->out) 0 -.nodeset V(sram[706]->outb) vsp -Xsram[707] sram->in sram[707]->out sram[707]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[707]->out) 0 -.nodeset V(sram[707]->outb) vsp -Xsram[708] sram->in sram[708]->out sram[708]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[708]->out) 0 -.nodeset V(sram[708]->outb) vsp -Xsram[709] sram->in sram[709]->out sram[709]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[709]->out) 0 -.nodeset V(sram[709]->outb) vsp -Xsram[710] sram->in sram[710]->out sram[710]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[710]->out) 0 -.nodeset V(sram[710]->outb) vsp -Xsram[711] sram->in sram[711]->out sram[711]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[711]->out) 0 -.nodeset V(sram[711]->outb) vsp -Xsram[712] sram->in sram[712]->out sram[712]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[712]->out) 0 -.nodeset V(sram[712]->outb) vsp -Xsram[713] sram->in sram[713]->out sram[713]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[713]->out) 0 -.nodeset V(sram[713]->outb) vsp -Xsram[714] sram->in sram[714]->out sram[714]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[714]->out) 0 -.nodeset V(sram[714]->outb) vsp -Xsram[715] sram->in sram[715]->out sram[715]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[715]->out) 0 -.nodeset V(sram[715]->outb) vsp -Xsram[716] sram->in sram[716]->out sram[716]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[716]->out) 0 -.nodeset V(sram[716]->outb) vsp -Xsram[717] sram->in sram[717]->out sram[717]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[717]->out) 0 -.nodeset V(sram[717]->outb) vsp -Xsram[718] sram->in sram[718]->out sram[718]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[718]->out) 0 -.nodeset V(sram[718]->outb) vsp -Xsram[719] sram->in sram[719]->out sram[719]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[719]->out) 0 -.nodeset V(sram[719]->outb) vsp -***** Signal mux_2level_size50[44]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[0] mux_2level_size50[44]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[1] mux_2level_size50[44]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[2] mux_2level_size50[44]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[3] mux_2level_size50[44]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[4] mux_2level_size50[44]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[5] mux_2level_size50[44]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[6] mux_2level_size50[44]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[7] mux_2level_size50[44]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[8] mux_2level_size50[44]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[9] mux_2level_size50[44]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[10] mux_2level_size50[44]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[11] mux_2level_size50[44]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[12] mux_2level_size50[44]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[13] mux_2level_size50[44]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[14] mux_2level_size50[44]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[15] mux_2level_size50[44]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[16] mux_2level_size50[44]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[17] mux_2level_size50[44]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[18] mux_2level_size50[44]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[19] mux_2level_size50[44]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[20] mux_2level_size50[44]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[21] mux_2level_size50[44]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[22] mux_2level_size50[44]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[23] mux_2level_size50[44]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[24] mux_2level_size50[44]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[25] mux_2level_size50[44]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[26] mux_2level_size50[44]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[27] mux_2level_size50[44]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[28] mux_2level_size50[44]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[29] mux_2level_size50[44]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[30] mux_2level_size50[44]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[31] mux_2level_size50[44]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[32] mux_2level_size50[44]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[33] mux_2level_size50[44]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[34] mux_2level_size50[44]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[35] mux_2level_size50[44]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[36] mux_2level_size50[44]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[37] mux_2level_size50[44]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[38] mux_2level_size50[44]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[44]->in[39] mux_2level_size50[44]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[44]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[40] mux_2level_size50[44]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[41] mux_2level_size50[44]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[42] mux_2level_size50[44]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[43] mux_2level_size50[44]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[44] mux_2level_size50[44]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[45] mux_2level_size50[44]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[46] mux_2level_size50[44]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[47] mux_2level_size50[44]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[48] mux_2level_size50[44]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[44]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[44]->in[49] mux_2level_size50[44]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[44] gvdd_mux_2level_size50[44] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[44]_in[2]_crossbar trig v(mux_2level_size50[44]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[44]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[44]_in[2]_crossbar trig v(mux_2level_size50[44]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[44]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[44]_in[2]_crossbar when v(mux_2level_size50[44]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[44]_in[2]_crossbar trig v(mux_2level_size50[44]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[44]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[44]_in[2]_crossbar when v(mux_2level_size50[44]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[44]_in[2]_crossbar trig v(mux_2level_size50[44]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[44]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[44]_leakage_power avg p(Vgvdd_mux_2level_size50[44]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[44]_in[2]_crossbar param='mux_2level_size50[44]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[44]_dynamic_power avg p(Vgvdd_mux_2level_size50[44]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[44]_energy_per_cycle param='mux_2level_size50[44]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[44]_in[2]_crossbar param='mux_2level_size50[44]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[44]_in[2]_crossbar param='dynamic_power_idle_mux50[44]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[44]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[44]) from='start_rise_idle_mux50[44]_in[2]_crossbar' to='start_rise_idle_mux50[44]_in[2]_crossbar+switch_rise_idle_mux50[44]_in[2]_crossbar' -.meas tran dynamic_fall_idle_mux50[44]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[44]) from='start_fall_idle_mux50[44]_in[2]_crossbar' to='start_fall_idle_mux50[44]_in[2]_crossbar+switch_fall_idle_mux50[44]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to44] -+ param='sum_leakage_power_mux[0to43]+leakage_idle_mux50[44]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to44] -+ param='sum_energy_per_cycle_mux[0to43]+energy_per_cycle_idle_mux50[44]_in[2]_crossbar' -Xload_inv[44]_no0 mux_2level_size50[44]->out mux_2level_size50[44]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to44] -+ param='sum_leakage_power_pb_mux[0to43]+leakage_idle_mux50[44]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to44] -+ param='sum_energy_per_cycle_pb_mux[0to43]+energy_per_cycle_idle_mux50[44]_in[2]_crossbar' -Xmux_2level_size50[45] mux_2level_size50[45]->in[0] mux_2level_size50[45]->in[1] mux_2level_size50[45]->in[2] mux_2level_size50[45]->in[3] mux_2level_size50[45]->in[4] mux_2level_size50[45]->in[5] mux_2level_size50[45]->in[6] mux_2level_size50[45]->in[7] mux_2level_size50[45]->in[8] mux_2level_size50[45]->in[9] mux_2level_size50[45]->in[10] mux_2level_size50[45]->in[11] mux_2level_size50[45]->in[12] mux_2level_size50[45]->in[13] mux_2level_size50[45]->in[14] mux_2level_size50[45]->in[15] mux_2level_size50[45]->in[16] mux_2level_size50[45]->in[17] mux_2level_size50[45]->in[18] mux_2level_size50[45]->in[19] mux_2level_size50[45]->in[20] mux_2level_size50[45]->in[21] mux_2level_size50[45]->in[22] mux_2level_size50[45]->in[23] mux_2level_size50[45]->in[24] mux_2level_size50[45]->in[25] mux_2level_size50[45]->in[26] mux_2level_size50[45]->in[27] mux_2level_size50[45]->in[28] mux_2level_size50[45]->in[29] mux_2level_size50[45]->in[30] mux_2level_size50[45]->in[31] mux_2level_size50[45]->in[32] mux_2level_size50[45]->in[33] mux_2level_size50[45]->in[34] mux_2level_size50[45]->in[35] mux_2level_size50[45]->in[36] mux_2level_size50[45]->in[37] mux_2level_size50[45]->in[38] mux_2level_size50[45]->in[39] mux_2level_size50[45]->in[40] mux_2level_size50[45]->in[41] mux_2level_size50[45]->in[42] mux_2level_size50[45]->in[43] mux_2level_size50[45]->in[44] mux_2level_size50[45]->in[45] mux_2level_size50[45]->in[46] mux_2level_size50[45]->in[47] mux_2level_size50[45]->in[48] mux_2level_size50[45]->in[49] mux_2level_size50[45]->out sram[720]->outb sram[720]->out sram[721]->out sram[721]->outb sram[722]->out sram[722]->outb sram[723]->out sram[723]->outb sram[724]->out sram[724]->outb sram[725]->out sram[725]->outb sram[726]->out sram[726]->outb sram[727]->out sram[727]->outb sram[728]->outb sram[728]->out sram[729]->out sram[729]->outb sram[730]->out sram[730]->outb sram[731]->out sram[731]->outb sram[732]->out sram[732]->outb sram[733]->out sram[733]->outb sram[734]->out sram[734]->outb sram[735]->out sram[735]->outb gvdd_mux_2level_size50[45] 0 mux_2level_size50 -***** SRAM bits for MUX[45], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[720] sram->in sram[720]->out sram[720]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[720]->out) 0 -.nodeset V(sram[720]->outb) vsp -Xsram[721] sram->in sram[721]->out sram[721]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[721]->out) 0 -.nodeset V(sram[721]->outb) vsp -Xsram[722] sram->in sram[722]->out sram[722]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[722]->out) 0 -.nodeset V(sram[722]->outb) vsp -Xsram[723] sram->in sram[723]->out sram[723]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[723]->out) 0 -.nodeset V(sram[723]->outb) vsp -Xsram[724] sram->in sram[724]->out sram[724]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[724]->out) 0 -.nodeset V(sram[724]->outb) vsp -Xsram[725] sram->in sram[725]->out sram[725]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[725]->out) 0 -.nodeset V(sram[725]->outb) vsp -Xsram[726] sram->in sram[726]->out sram[726]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[726]->out) 0 -.nodeset V(sram[726]->outb) vsp -Xsram[727] sram->in sram[727]->out sram[727]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[727]->out) 0 -.nodeset V(sram[727]->outb) vsp -Xsram[728] sram->in sram[728]->out sram[728]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[728]->out) 0 -.nodeset V(sram[728]->outb) vsp -Xsram[729] sram->in sram[729]->out sram[729]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[729]->out) 0 -.nodeset V(sram[729]->outb) vsp -Xsram[730] sram->in sram[730]->out sram[730]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[730]->out) 0 -.nodeset V(sram[730]->outb) vsp -Xsram[731] sram->in sram[731]->out sram[731]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[731]->out) 0 -.nodeset V(sram[731]->outb) vsp -Xsram[732] sram->in sram[732]->out sram[732]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[732]->out) 0 -.nodeset V(sram[732]->outb) vsp -Xsram[733] sram->in sram[733]->out sram[733]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[733]->out) 0 -.nodeset V(sram[733]->outb) vsp -Xsram[734] sram->in sram[734]->out sram[734]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[734]->out) 0 -.nodeset V(sram[734]->outb) vsp -Xsram[735] sram->in sram[735]->out sram[735]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[735]->out) 0 -.nodeset V(sram[735]->outb) vsp -***** Signal mux_2level_size50[45]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[0] mux_2level_size50[45]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[1] mux_2level_size50[45]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[2] mux_2level_size50[45]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[3] mux_2level_size50[45]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[4] mux_2level_size50[45]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[5] mux_2level_size50[45]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[6] mux_2level_size50[45]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[7] mux_2level_size50[45]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[8] mux_2level_size50[45]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[9] mux_2level_size50[45]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[10] mux_2level_size50[45]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[11] mux_2level_size50[45]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[12] mux_2level_size50[45]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[13] mux_2level_size50[45]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[14] mux_2level_size50[45]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[15] mux_2level_size50[45]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[16] mux_2level_size50[45]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[17] mux_2level_size50[45]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[18] mux_2level_size50[45]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[19] mux_2level_size50[45]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[20] mux_2level_size50[45]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[21] mux_2level_size50[45]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[22] mux_2level_size50[45]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[23] mux_2level_size50[45]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[24] mux_2level_size50[45]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[25] mux_2level_size50[45]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[26] mux_2level_size50[45]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[27] mux_2level_size50[45]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[28] mux_2level_size50[45]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[29] mux_2level_size50[45]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[30] mux_2level_size50[45]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[31] mux_2level_size50[45]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[32] mux_2level_size50[45]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[33] mux_2level_size50[45]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[34] mux_2level_size50[45]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[35] mux_2level_size50[45]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[36] mux_2level_size50[45]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[37] mux_2level_size50[45]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[38] mux_2level_size50[45]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[45]->in[39] mux_2level_size50[45]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[45]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[40] mux_2level_size50[45]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[41] mux_2level_size50[45]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[42] mux_2level_size50[45]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[43] mux_2level_size50[45]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[44] mux_2level_size50[45]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[45] mux_2level_size50[45]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[46] mux_2level_size50[45]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[47] mux_2level_size50[45]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[48] mux_2level_size50[45]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[45]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[45]->in[49] mux_2level_size50[45]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[45] gvdd_mux_2level_size50[45] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[45]_in[3]_crossbar trig v(mux_2level_size50[45]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[45]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[45]_in[3]_crossbar trig v(mux_2level_size50[45]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[45]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[45]_in[3]_crossbar when v(mux_2level_size50[45]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[45]_in[3]_crossbar trig v(mux_2level_size50[45]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[45]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[45]_in[3]_crossbar when v(mux_2level_size50[45]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[45]_in[3]_crossbar trig v(mux_2level_size50[45]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[45]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[45]_leakage_power avg p(Vgvdd_mux_2level_size50[45]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[45]_in[3]_crossbar param='mux_2level_size50[45]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[45]_dynamic_power avg p(Vgvdd_mux_2level_size50[45]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[45]_energy_per_cycle param='mux_2level_size50[45]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[45]_in[3]_crossbar param='mux_2level_size50[45]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[45]_in[3]_crossbar param='dynamic_power_idle_mux50[45]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[45]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[45]) from='start_rise_idle_mux50[45]_in[3]_crossbar' to='start_rise_idle_mux50[45]_in[3]_crossbar+switch_rise_idle_mux50[45]_in[3]_crossbar' -.meas tran dynamic_fall_idle_mux50[45]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[45]) from='start_fall_idle_mux50[45]_in[3]_crossbar' to='start_fall_idle_mux50[45]_in[3]_crossbar+switch_fall_idle_mux50[45]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to45] -+ param='sum_leakage_power_mux[0to44]+leakage_idle_mux50[45]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to45] -+ param='sum_energy_per_cycle_mux[0to44]+energy_per_cycle_idle_mux50[45]_in[3]_crossbar' -Xload_inv[45]_no0 mux_2level_size50[45]->out mux_2level_size50[45]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to45] -+ param='sum_leakage_power_pb_mux[0to44]+leakage_idle_mux50[45]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to45] -+ param='sum_energy_per_cycle_pb_mux[0to44]+energy_per_cycle_idle_mux50[45]_in[3]_crossbar' -Xmux_2level_size50[46] mux_2level_size50[46]->in[0] mux_2level_size50[46]->in[1] mux_2level_size50[46]->in[2] mux_2level_size50[46]->in[3] mux_2level_size50[46]->in[4] mux_2level_size50[46]->in[5] mux_2level_size50[46]->in[6] mux_2level_size50[46]->in[7] mux_2level_size50[46]->in[8] mux_2level_size50[46]->in[9] mux_2level_size50[46]->in[10] mux_2level_size50[46]->in[11] mux_2level_size50[46]->in[12] mux_2level_size50[46]->in[13] mux_2level_size50[46]->in[14] mux_2level_size50[46]->in[15] mux_2level_size50[46]->in[16] mux_2level_size50[46]->in[17] mux_2level_size50[46]->in[18] mux_2level_size50[46]->in[19] mux_2level_size50[46]->in[20] mux_2level_size50[46]->in[21] mux_2level_size50[46]->in[22] mux_2level_size50[46]->in[23] mux_2level_size50[46]->in[24] mux_2level_size50[46]->in[25] mux_2level_size50[46]->in[26] mux_2level_size50[46]->in[27] mux_2level_size50[46]->in[28] mux_2level_size50[46]->in[29] mux_2level_size50[46]->in[30] mux_2level_size50[46]->in[31] mux_2level_size50[46]->in[32] mux_2level_size50[46]->in[33] mux_2level_size50[46]->in[34] mux_2level_size50[46]->in[35] mux_2level_size50[46]->in[36] mux_2level_size50[46]->in[37] mux_2level_size50[46]->in[38] mux_2level_size50[46]->in[39] mux_2level_size50[46]->in[40] mux_2level_size50[46]->in[41] mux_2level_size50[46]->in[42] mux_2level_size50[46]->in[43] mux_2level_size50[46]->in[44] mux_2level_size50[46]->in[45] mux_2level_size50[46]->in[46] mux_2level_size50[46]->in[47] mux_2level_size50[46]->in[48] mux_2level_size50[46]->in[49] mux_2level_size50[46]->out sram[736]->outb sram[736]->out sram[737]->out sram[737]->outb sram[738]->out sram[738]->outb sram[739]->out sram[739]->outb sram[740]->out sram[740]->outb sram[741]->out sram[741]->outb sram[742]->out sram[742]->outb sram[743]->out sram[743]->outb sram[744]->outb sram[744]->out sram[745]->out sram[745]->outb sram[746]->out sram[746]->outb sram[747]->out sram[747]->outb sram[748]->out sram[748]->outb sram[749]->out sram[749]->outb sram[750]->out sram[750]->outb sram[751]->out sram[751]->outb gvdd_mux_2level_size50[46] 0 mux_2level_size50 -***** SRAM bits for MUX[46], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[736] sram->in sram[736]->out sram[736]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[736]->out) 0 -.nodeset V(sram[736]->outb) vsp -Xsram[737] sram->in sram[737]->out sram[737]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[737]->out) 0 -.nodeset V(sram[737]->outb) vsp -Xsram[738] sram->in sram[738]->out sram[738]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[738]->out) 0 -.nodeset V(sram[738]->outb) vsp -Xsram[739] sram->in sram[739]->out sram[739]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[739]->out) 0 -.nodeset V(sram[739]->outb) vsp -Xsram[740] sram->in sram[740]->out sram[740]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[740]->out) 0 -.nodeset V(sram[740]->outb) vsp -Xsram[741] sram->in sram[741]->out sram[741]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[741]->out) 0 -.nodeset V(sram[741]->outb) vsp -Xsram[742] sram->in sram[742]->out sram[742]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[742]->out) 0 -.nodeset V(sram[742]->outb) vsp -Xsram[743] sram->in sram[743]->out sram[743]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[743]->out) 0 -.nodeset V(sram[743]->outb) vsp -Xsram[744] sram->in sram[744]->out sram[744]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[744]->out) 0 -.nodeset V(sram[744]->outb) vsp -Xsram[745] sram->in sram[745]->out sram[745]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[745]->out) 0 -.nodeset V(sram[745]->outb) vsp -Xsram[746] sram->in sram[746]->out sram[746]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[746]->out) 0 -.nodeset V(sram[746]->outb) vsp -Xsram[747] sram->in sram[747]->out sram[747]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[747]->out) 0 -.nodeset V(sram[747]->outb) vsp -Xsram[748] sram->in sram[748]->out sram[748]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[748]->out) 0 -.nodeset V(sram[748]->outb) vsp -Xsram[749] sram->in sram[749]->out sram[749]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[749]->out) 0 -.nodeset V(sram[749]->outb) vsp -Xsram[750] sram->in sram[750]->out sram[750]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[750]->out) 0 -.nodeset V(sram[750]->outb) vsp -Xsram[751] sram->in sram[751]->out sram[751]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[751]->out) 0 -.nodeset V(sram[751]->outb) vsp -***** Signal mux_2level_size50[46]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[0] mux_2level_size50[46]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[1] mux_2level_size50[46]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[2] mux_2level_size50[46]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[3] mux_2level_size50[46]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[4] mux_2level_size50[46]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[5] mux_2level_size50[46]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[6] mux_2level_size50[46]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[7] mux_2level_size50[46]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[8] mux_2level_size50[46]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[9] mux_2level_size50[46]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[10] mux_2level_size50[46]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[11] mux_2level_size50[46]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[12] mux_2level_size50[46]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[13] mux_2level_size50[46]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[14] mux_2level_size50[46]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[15] mux_2level_size50[46]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[16] mux_2level_size50[46]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[17] mux_2level_size50[46]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[18] mux_2level_size50[46]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[19] mux_2level_size50[46]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[20] mux_2level_size50[46]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[21] mux_2level_size50[46]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[22] mux_2level_size50[46]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[23] mux_2level_size50[46]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[24] mux_2level_size50[46]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[25] mux_2level_size50[46]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[26] mux_2level_size50[46]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[27] mux_2level_size50[46]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[28] mux_2level_size50[46]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[29] mux_2level_size50[46]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[30] mux_2level_size50[46]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[31] mux_2level_size50[46]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[32] mux_2level_size50[46]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[33] mux_2level_size50[46]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[34] mux_2level_size50[46]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[35] mux_2level_size50[46]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[36] mux_2level_size50[46]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[37] mux_2level_size50[46]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[38] mux_2level_size50[46]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[46]->in[39] mux_2level_size50[46]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[46]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[40] mux_2level_size50[46]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[41] mux_2level_size50[46]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[42] mux_2level_size50[46]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[43] mux_2level_size50[46]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[44] mux_2level_size50[46]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[45] mux_2level_size50[46]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[46] mux_2level_size50[46]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[47] mux_2level_size50[46]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[48] mux_2level_size50[46]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[46]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[46]->in[49] mux_2level_size50[46]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[46] gvdd_mux_2level_size50[46] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[46]_in[4]_crossbar trig v(mux_2level_size50[46]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[46]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[46]_in[4]_crossbar trig v(mux_2level_size50[46]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[46]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[46]_in[4]_crossbar when v(mux_2level_size50[46]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[46]_in[4]_crossbar trig v(mux_2level_size50[46]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[46]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[46]_in[4]_crossbar when v(mux_2level_size50[46]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[46]_in[4]_crossbar trig v(mux_2level_size50[46]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[46]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[46]_leakage_power avg p(Vgvdd_mux_2level_size50[46]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[46]_in[4]_crossbar param='mux_2level_size50[46]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[46]_dynamic_power avg p(Vgvdd_mux_2level_size50[46]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[46]_energy_per_cycle param='mux_2level_size50[46]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[46]_in[4]_crossbar param='mux_2level_size50[46]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[46]_in[4]_crossbar param='dynamic_power_idle_mux50[46]_in[4]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[46]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[46]) from='start_rise_idle_mux50[46]_in[4]_crossbar' to='start_rise_idle_mux50[46]_in[4]_crossbar+switch_rise_idle_mux50[46]_in[4]_crossbar' -.meas tran dynamic_fall_idle_mux50[46]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[46]) from='start_fall_idle_mux50[46]_in[4]_crossbar' to='start_fall_idle_mux50[46]_in[4]_crossbar+switch_fall_idle_mux50[46]_in[4]_crossbar' -.meas tran sum_leakage_power_mux[0to46] -+ param='sum_leakage_power_mux[0to45]+leakage_idle_mux50[46]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to46] -+ param='sum_energy_per_cycle_mux[0to45]+energy_per_cycle_idle_mux50[46]_in[4]_crossbar' -Xload_inv[46]_no0 mux_2level_size50[46]->out mux_2level_size50[46]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to46] -+ param='sum_leakage_power_pb_mux[0to45]+leakage_idle_mux50[46]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to46] -+ param='sum_energy_per_cycle_pb_mux[0to45]+energy_per_cycle_idle_mux50[46]_in[4]_crossbar' -Xmux_2level_size50[47] mux_2level_size50[47]->in[0] mux_2level_size50[47]->in[1] mux_2level_size50[47]->in[2] mux_2level_size50[47]->in[3] mux_2level_size50[47]->in[4] mux_2level_size50[47]->in[5] mux_2level_size50[47]->in[6] mux_2level_size50[47]->in[7] mux_2level_size50[47]->in[8] mux_2level_size50[47]->in[9] mux_2level_size50[47]->in[10] mux_2level_size50[47]->in[11] mux_2level_size50[47]->in[12] mux_2level_size50[47]->in[13] mux_2level_size50[47]->in[14] mux_2level_size50[47]->in[15] mux_2level_size50[47]->in[16] mux_2level_size50[47]->in[17] mux_2level_size50[47]->in[18] mux_2level_size50[47]->in[19] mux_2level_size50[47]->in[20] mux_2level_size50[47]->in[21] mux_2level_size50[47]->in[22] mux_2level_size50[47]->in[23] mux_2level_size50[47]->in[24] mux_2level_size50[47]->in[25] mux_2level_size50[47]->in[26] mux_2level_size50[47]->in[27] mux_2level_size50[47]->in[28] mux_2level_size50[47]->in[29] mux_2level_size50[47]->in[30] mux_2level_size50[47]->in[31] mux_2level_size50[47]->in[32] mux_2level_size50[47]->in[33] mux_2level_size50[47]->in[34] mux_2level_size50[47]->in[35] mux_2level_size50[47]->in[36] mux_2level_size50[47]->in[37] mux_2level_size50[47]->in[38] mux_2level_size50[47]->in[39] mux_2level_size50[47]->in[40] mux_2level_size50[47]->in[41] mux_2level_size50[47]->in[42] mux_2level_size50[47]->in[43] mux_2level_size50[47]->in[44] mux_2level_size50[47]->in[45] mux_2level_size50[47]->in[46] mux_2level_size50[47]->in[47] mux_2level_size50[47]->in[48] mux_2level_size50[47]->in[49] mux_2level_size50[47]->out sram[752]->outb sram[752]->out sram[753]->out sram[753]->outb sram[754]->out sram[754]->outb sram[755]->out sram[755]->outb sram[756]->out sram[756]->outb sram[757]->out sram[757]->outb sram[758]->out sram[758]->outb sram[759]->out sram[759]->outb sram[760]->outb sram[760]->out sram[761]->out sram[761]->outb sram[762]->out sram[762]->outb sram[763]->out sram[763]->outb sram[764]->out sram[764]->outb sram[765]->out sram[765]->outb sram[766]->out sram[766]->outb sram[767]->out sram[767]->outb gvdd_mux_2level_size50[47] 0 mux_2level_size50 -***** SRAM bits for MUX[47], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[752] sram->in sram[752]->out sram[752]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[752]->out) 0 -.nodeset V(sram[752]->outb) vsp -Xsram[753] sram->in sram[753]->out sram[753]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[753]->out) 0 -.nodeset V(sram[753]->outb) vsp -Xsram[754] sram->in sram[754]->out sram[754]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[754]->out) 0 -.nodeset V(sram[754]->outb) vsp -Xsram[755] sram->in sram[755]->out sram[755]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[755]->out) 0 -.nodeset V(sram[755]->outb) vsp -Xsram[756] sram->in sram[756]->out sram[756]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[756]->out) 0 -.nodeset V(sram[756]->outb) vsp -Xsram[757] sram->in sram[757]->out sram[757]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[757]->out) 0 -.nodeset V(sram[757]->outb) vsp -Xsram[758] sram->in sram[758]->out sram[758]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[758]->out) 0 -.nodeset V(sram[758]->outb) vsp -Xsram[759] sram->in sram[759]->out sram[759]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[759]->out) 0 -.nodeset V(sram[759]->outb) vsp -Xsram[760] sram->in sram[760]->out sram[760]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[760]->out) 0 -.nodeset V(sram[760]->outb) vsp -Xsram[761] sram->in sram[761]->out sram[761]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[761]->out) 0 -.nodeset V(sram[761]->outb) vsp -Xsram[762] sram->in sram[762]->out sram[762]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[762]->out) 0 -.nodeset V(sram[762]->outb) vsp -Xsram[763] sram->in sram[763]->out sram[763]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[763]->out) 0 -.nodeset V(sram[763]->outb) vsp -Xsram[764] sram->in sram[764]->out sram[764]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[764]->out) 0 -.nodeset V(sram[764]->outb) vsp -Xsram[765] sram->in sram[765]->out sram[765]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[765]->out) 0 -.nodeset V(sram[765]->outb) vsp -Xsram[766] sram->in sram[766]->out sram[766]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[766]->out) 0 -.nodeset V(sram[766]->outb) vsp -Xsram[767] sram->in sram[767]->out sram[767]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[767]->out) 0 -.nodeset V(sram[767]->outb) vsp -***** Signal mux_2level_size50[47]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[0] mux_2level_size50[47]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[1] mux_2level_size50[47]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[2] mux_2level_size50[47]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[3] mux_2level_size50[47]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[4] mux_2level_size50[47]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[5] mux_2level_size50[47]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[6] mux_2level_size50[47]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[7] mux_2level_size50[47]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[8] mux_2level_size50[47]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[9] mux_2level_size50[47]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[10] mux_2level_size50[47]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[11] mux_2level_size50[47]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[12] mux_2level_size50[47]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[13] mux_2level_size50[47]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[14] mux_2level_size50[47]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[15] mux_2level_size50[47]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[16] mux_2level_size50[47]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[17] mux_2level_size50[47]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[18] mux_2level_size50[47]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[19] mux_2level_size50[47]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[20] mux_2level_size50[47]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[21] mux_2level_size50[47]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[22] mux_2level_size50[47]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[23] mux_2level_size50[47]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[24] mux_2level_size50[47]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[25] mux_2level_size50[47]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[26] mux_2level_size50[47]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[27] mux_2level_size50[47]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[28] mux_2level_size50[47]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[29] mux_2level_size50[47]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[30] mux_2level_size50[47]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[31] mux_2level_size50[47]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[32] mux_2level_size50[47]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[33] mux_2level_size50[47]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[34] mux_2level_size50[47]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[35] mux_2level_size50[47]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[36] mux_2level_size50[47]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[37] mux_2level_size50[47]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[38] mux_2level_size50[47]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[47]->in[39] mux_2level_size50[47]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[47]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[40] mux_2level_size50[47]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[41] mux_2level_size50[47]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[42] mux_2level_size50[47]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[43] mux_2level_size50[47]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[44] mux_2level_size50[47]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[45] mux_2level_size50[47]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[46] mux_2level_size50[47]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[47] mux_2level_size50[47]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[48] mux_2level_size50[47]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[47]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[47]->in[49] mux_2level_size50[47]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[47] gvdd_mux_2level_size50[47] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[47]_in[5]_crossbar trig v(mux_2level_size50[47]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[47]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[47]_in[5]_crossbar trig v(mux_2level_size50[47]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[47]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[47]_in[5]_crossbar when v(mux_2level_size50[47]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[47]_in[5]_crossbar trig v(mux_2level_size50[47]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[47]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[47]_in[5]_crossbar when v(mux_2level_size50[47]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[47]_in[5]_crossbar trig v(mux_2level_size50[47]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[47]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[47]_leakage_power avg p(Vgvdd_mux_2level_size50[47]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[47]_in[5]_crossbar param='mux_2level_size50[47]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[47]_dynamic_power avg p(Vgvdd_mux_2level_size50[47]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[47]_energy_per_cycle param='mux_2level_size50[47]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[47]_in[5]_crossbar param='mux_2level_size50[47]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[47]_in[5]_crossbar param='dynamic_power_idle_mux50[47]_in[5]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[47]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[47]) from='start_rise_idle_mux50[47]_in[5]_crossbar' to='start_rise_idle_mux50[47]_in[5]_crossbar+switch_rise_idle_mux50[47]_in[5]_crossbar' -.meas tran dynamic_fall_idle_mux50[47]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[47]) from='start_fall_idle_mux50[47]_in[5]_crossbar' to='start_fall_idle_mux50[47]_in[5]_crossbar+switch_fall_idle_mux50[47]_in[5]_crossbar' -.meas tran sum_leakage_power_mux[0to47] -+ param='sum_leakage_power_mux[0to46]+leakage_idle_mux50[47]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to47] -+ param='sum_energy_per_cycle_mux[0to46]+energy_per_cycle_idle_mux50[47]_in[5]_crossbar' -Xload_inv[47]_no0 mux_2level_size50[47]->out mux_2level_size50[47]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to47] -+ param='sum_leakage_power_pb_mux[0to46]+leakage_idle_mux50[47]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to47] -+ param='sum_energy_per_cycle_pb_mux[0to46]+energy_per_cycle_idle_mux50[47]_in[5]_crossbar' -Xmux_2level_size50[48] mux_2level_size50[48]->in[0] mux_2level_size50[48]->in[1] mux_2level_size50[48]->in[2] mux_2level_size50[48]->in[3] mux_2level_size50[48]->in[4] mux_2level_size50[48]->in[5] mux_2level_size50[48]->in[6] mux_2level_size50[48]->in[7] mux_2level_size50[48]->in[8] mux_2level_size50[48]->in[9] mux_2level_size50[48]->in[10] mux_2level_size50[48]->in[11] mux_2level_size50[48]->in[12] mux_2level_size50[48]->in[13] mux_2level_size50[48]->in[14] mux_2level_size50[48]->in[15] mux_2level_size50[48]->in[16] mux_2level_size50[48]->in[17] mux_2level_size50[48]->in[18] mux_2level_size50[48]->in[19] mux_2level_size50[48]->in[20] mux_2level_size50[48]->in[21] mux_2level_size50[48]->in[22] mux_2level_size50[48]->in[23] mux_2level_size50[48]->in[24] mux_2level_size50[48]->in[25] mux_2level_size50[48]->in[26] mux_2level_size50[48]->in[27] mux_2level_size50[48]->in[28] mux_2level_size50[48]->in[29] mux_2level_size50[48]->in[30] mux_2level_size50[48]->in[31] mux_2level_size50[48]->in[32] mux_2level_size50[48]->in[33] mux_2level_size50[48]->in[34] mux_2level_size50[48]->in[35] mux_2level_size50[48]->in[36] mux_2level_size50[48]->in[37] mux_2level_size50[48]->in[38] mux_2level_size50[48]->in[39] mux_2level_size50[48]->in[40] mux_2level_size50[48]->in[41] mux_2level_size50[48]->in[42] mux_2level_size50[48]->in[43] mux_2level_size50[48]->in[44] mux_2level_size50[48]->in[45] mux_2level_size50[48]->in[46] mux_2level_size50[48]->in[47] mux_2level_size50[48]->in[48] mux_2level_size50[48]->in[49] mux_2level_size50[48]->out sram[768]->outb sram[768]->out sram[769]->out sram[769]->outb sram[770]->out sram[770]->outb sram[771]->out sram[771]->outb sram[772]->out sram[772]->outb sram[773]->out sram[773]->outb sram[774]->out sram[774]->outb sram[775]->out sram[775]->outb sram[776]->outb sram[776]->out sram[777]->out sram[777]->outb sram[778]->out sram[778]->outb sram[779]->out sram[779]->outb sram[780]->out sram[780]->outb sram[781]->out sram[781]->outb sram[782]->out sram[782]->outb sram[783]->out sram[783]->outb gvdd_mux_2level_size50[48] 0 mux_2level_size50 -***** SRAM bits for MUX[48], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[768] sram->in sram[768]->out sram[768]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[768]->out) 0 -.nodeset V(sram[768]->outb) vsp -Xsram[769] sram->in sram[769]->out sram[769]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[769]->out) 0 -.nodeset V(sram[769]->outb) vsp -Xsram[770] sram->in sram[770]->out sram[770]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[770]->out) 0 -.nodeset V(sram[770]->outb) vsp -Xsram[771] sram->in sram[771]->out sram[771]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[771]->out) 0 -.nodeset V(sram[771]->outb) vsp -Xsram[772] sram->in sram[772]->out sram[772]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[772]->out) 0 -.nodeset V(sram[772]->outb) vsp -Xsram[773] sram->in sram[773]->out sram[773]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[773]->out) 0 -.nodeset V(sram[773]->outb) vsp -Xsram[774] sram->in sram[774]->out sram[774]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[774]->out) 0 -.nodeset V(sram[774]->outb) vsp -Xsram[775] sram->in sram[775]->out sram[775]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[775]->out) 0 -.nodeset V(sram[775]->outb) vsp -Xsram[776] sram->in sram[776]->out sram[776]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[776]->out) 0 -.nodeset V(sram[776]->outb) vsp -Xsram[777] sram->in sram[777]->out sram[777]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[777]->out) 0 -.nodeset V(sram[777]->outb) vsp -Xsram[778] sram->in sram[778]->out sram[778]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[778]->out) 0 -.nodeset V(sram[778]->outb) vsp -Xsram[779] sram->in sram[779]->out sram[779]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[779]->out) 0 -.nodeset V(sram[779]->outb) vsp -Xsram[780] sram->in sram[780]->out sram[780]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[780]->out) 0 -.nodeset V(sram[780]->outb) vsp -Xsram[781] sram->in sram[781]->out sram[781]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[781]->out) 0 -.nodeset V(sram[781]->outb) vsp -Xsram[782] sram->in sram[782]->out sram[782]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[782]->out) 0 -.nodeset V(sram[782]->outb) vsp -Xsram[783] sram->in sram[783]->out sram[783]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[783]->out) 0 -.nodeset V(sram[783]->outb) vsp -***** Signal mux_2level_size50[48]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[0] mux_2level_size50[48]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[1] mux_2level_size50[48]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[2] mux_2level_size50[48]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[3] mux_2level_size50[48]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[4] mux_2level_size50[48]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[5] mux_2level_size50[48]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[6] mux_2level_size50[48]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[7] mux_2level_size50[48]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[8] mux_2level_size50[48]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[9] mux_2level_size50[48]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[10] mux_2level_size50[48]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[11] mux_2level_size50[48]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[12] mux_2level_size50[48]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[13] mux_2level_size50[48]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[14] mux_2level_size50[48]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[15] mux_2level_size50[48]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[16] mux_2level_size50[48]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[17] mux_2level_size50[48]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[18] mux_2level_size50[48]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[19] mux_2level_size50[48]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[20] mux_2level_size50[48]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[21] mux_2level_size50[48]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[22] mux_2level_size50[48]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[23] mux_2level_size50[48]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[24] mux_2level_size50[48]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[25] mux_2level_size50[48]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[26] mux_2level_size50[48]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[27] mux_2level_size50[48]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[28] mux_2level_size50[48]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[29] mux_2level_size50[48]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[30] mux_2level_size50[48]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[31] mux_2level_size50[48]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[32] mux_2level_size50[48]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[33] mux_2level_size50[48]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[34] mux_2level_size50[48]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[35] mux_2level_size50[48]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[36] mux_2level_size50[48]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[37] mux_2level_size50[48]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[38] mux_2level_size50[48]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[48]->in[39] mux_2level_size50[48]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[48]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[40] mux_2level_size50[48]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[41] mux_2level_size50[48]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[42] mux_2level_size50[48]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[43] mux_2level_size50[48]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[44] mux_2level_size50[48]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[45] mux_2level_size50[48]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[46] mux_2level_size50[48]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[47] mux_2level_size50[48]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[48] mux_2level_size50[48]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[48]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[48]->in[49] mux_2level_size50[48]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[48] gvdd_mux_2level_size50[48] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[48]_in[0]_crossbar trig v(mux_2level_size50[48]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[48]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[48]_in[0]_crossbar trig v(mux_2level_size50[48]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[48]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[48]_in[0]_crossbar when v(mux_2level_size50[48]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[48]_in[0]_crossbar trig v(mux_2level_size50[48]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[48]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[48]_in[0]_crossbar when v(mux_2level_size50[48]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[48]_in[0]_crossbar trig v(mux_2level_size50[48]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[48]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[48]_leakage_power avg p(Vgvdd_mux_2level_size50[48]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[48]_in[0]_crossbar param='mux_2level_size50[48]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[48]_dynamic_power avg p(Vgvdd_mux_2level_size50[48]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[48]_energy_per_cycle param='mux_2level_size50[48]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[48]_in[0]_crossbar param='mux_2level_size50[48]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[48]_in[0]_crossbar param='dynamic_power_idle_mux50[48]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[48]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[48]) from='start_rise_idle_mux50[48]_in[0]_crossbar' to='start_rise_idle_mux50[48]_in[0]_crossbar+switch_rise_idle_mux50[48]_in[0]_crossbar' -.meas tran dynamic_fall_idle_mux50[48]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[48]) from='start_fall_idle_mux50[48]_in[0]_crossbar' to='start_fall_idle_mux50[48]_in[0]_crossbar+switch_fall_idle_mux50[48]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to48] -+ param='sum_leakage_power_mux[0to47]+leakage_idle_mux50[48]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to48] -+ param='sum_energy_per_cycle_mux[0to47]+energy_per_cycle_idle_mux50[48]_in[0]_crossbar' -Xload_inv[48]_no0 mux_2level_size50[48]->out mux_2level_size50[48]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to48] -+ param='sum_leakage_power_pb_mux[0to47]+leakage_idle_mux50[48]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to48] -+ param='sum_energy_per_cycle_pb_mux[0to47]+energy_per_cycle_idle_mux50[48]_in[0]_crossbar' -Xmux_2level_size50[49] mux_2level_size50[49]->in[0] mux_2level_size50[49]->in[1] mux_2level_size50[49]->in[2] mux_2level_size50[49]->in[3] mux_2level_size50[49]->in[4] mux_2level_size50[49]->in[5] mux_2level_size50[49]->in[6] mux_2level_size50[49]->in[7] mux_2level_size50[49]->in[8] mux_2level_size50[49]->in[9] mux_2level_size50[49]->in[10] mux_2level_size50[49]->in[11] mux_2level_size50[49]->in[12] mux_2level_size50[49]->in[13] mux_2level_size50[49]->in[14] mux_2level_size50[49]->in[15] mux_2level_size50[49]->in[16] mux_2level_size50[49]->in[17] mux_2level_size50[49]->in[18] mux_2level_size50[49]->in[19] mux_2level_size50[49]->in[20] mux_2level_size50[49]->in[21] mux_2level_size50[49]->in[22] mux_2level_size50[49]->in[23] mux_2level_size50[49]->in[24] mux_2level_size50[49]->in[25] mux_2level_size50[49]->in[26] mux_2level_size50[49]->in[27] mux_2level_size50[49]->in[28] mux_2level_size50[49]->in[29] mux_2level_size50[49]->in[30] mux_2level_size50[49]->in[31] mux_2level_size50[49]->in[32] mux_2level_size50[49]->in[33] mux_2level_size50[49]->in[34] mux_2level_size50[49]->in[35] mux_2level_size50[49]->in[36] mux_2level_size50[49]->in[37] mux_2level_size50[49]->in[38] mux_2level_size50[49]->in[39] mux_2level_size50[49]->in[40] mux_2level_size50[49]->in[41] mux_2level_size50[49]->in[42] mux_2level_size50[49]->in[43] mux_2level_size50[49]->in[44] mux_2level_size50[49]->in[45] mux_2level_size50[49]->in[46] mux_2level_size50[49]->in[47] mux_2level_size50[49]->in[48] mux_2level_size50[49]->in[49] mux_2level_size50[49]->out sram[784]->outb sram[784]->out sram[785]->out sram[785]->outb sram[786]->out sram[786]->outb sram[787]->out sram[787]->outb sram[788]->out sram[788]->outb sram[789]->out sram[789]->outb sram[790]->out sram[790]->outb sram[791]->out sram[791]->outb sram[792]->outb sram[792]->out sram[793]->out sram[793]->outb sram[794]->out sram[794]->outb sram[795]->out sram[795]->outb sram[796]->out sram[796]->outb sram[797]->out sram[797]->outb sram[798]->out sram[798]->outb sram[799]->out sram[799]->outb gvdd_mux_2level_size50[49] 0 mux_2level_size50 -***** SRAM bits for MUX[49], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[784] sram->in sram[784]->out sram[784]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[784]->out) 0 -.nodeset V(sram[784]->outb) vsp -Xsram[785] sram->in sram[785]->out sram[785]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[785]->out) 0 -.nodeset V(sram[785]->outb) vsp -Xsram[786] sram->in sram[786]->out sram[786]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[786]->out) 0 -.nodeset V(sram[786]->outb) vsp -Xsram[787] sram->in sram[787]->out sram[787]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[787]->out) 0 -.nodeset V(sram[787]->outb) vsp -Xsram[788] sram->in sram[788]->out sram[788]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[788]->out) 0 -.nodeset V(sram[788]->outb) vsp -Xsram[789] sram->in sram[789]->out sram[789]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[789]->out) 0 -.nodeset V(sram[789]->outb) vsp -Xsram[790] sram->in sram[790]->out sram[790]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[790]->out) 0 -.nodeset V(sram[790]->outb) vsp -Xsram[791] sram->in sram[791]->out sram[791]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[791]->out) 0 -.nodeset V(sram[791]->outb) vsp -Xsram[792] sram->in sram[792]->out sram[792]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[792]->out) 0 -.nodeset V(sram[792]->outb) vsp -Xsram[793] sram->in sram[793]->out sram[793]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[793]->out) 0 -.nodeset V(sram[793]->outb) vsp -Xsram[794] sram->in sram[794]->out sram[794]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[794]->out) 0 -.nodeset V(sram[794]->outb) vsp -Xsram[795] sram->in sram[795]->out sram[795]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[795]->out) 0 -.nodeset V(sram[795]->outb) vsp -Xsram[796] sram->in sram[796]->out sram[796]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[796]->out) 0 -.nodeset V(sram[796]->outb) vsp -Xsram[797] sram->in sram[797]->out sram[797]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[797]->out) 0 -.nodeset V(sram[797]->outb) vsp -Xsram[798] sram->in sram[798]->out sram[798]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[798]->out) 0 -.nodeset V(sram[798]->outb) vsp -Xsram[799] sram->in sram[799]->out sram[799]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[799]->out) 0 -.nodeset V(sram[799]->outb) vsp -***** Signal mux_2level_size50[49]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[0] mux_2level_size50[49]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[1] mux_2level_size50[49]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[2] mux_2level_size50[49]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[3] mux_2level_size50[49]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[4] mux_2level_size50[49]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[5] mux_2level_size50[49]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[6] mux_2level_size50[49]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[7] mux_2level_size50[49]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[8] mux_2level_size50[49]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[9] mux_2level_size50[49]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[10] mux_2level_size50[49]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[11] mux_2level_size50[49]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[12] mux_2level_size50[49]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[13] mux_2level_size50[49]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[14] mux_2level_size50[49]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[15] mux_2level_size50[49]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[16] mux_2level_size50[49]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[17] mux_2level_size50[49]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[18] mux_2level_size50[49]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[19] mux_2level_size50[49]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[20] mux_2level_size50[49]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[21] mux_2level_size50[49]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[22] mux_2level_size50[49]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[23] mux_2level_size50[49]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[24] mux_2level_size50[49]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[25] mux_2level_size50[49]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[26] mux_2level_size50[49]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[27] mux_2level_size50[49]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[28] mux_2level_size50[49]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[29] mux_2level_size50[49]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[30] mux_2level_size50[49]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[31] mux_2level_size50[49]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[32] mux_2level_size50[49]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[33] mux_2level_size50[49]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[34] mux_2level_size50[49]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[35] mux_2level_size50[49]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[36] mux_2level_size50[49]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[37] mux_2level_size50[49]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[38] mux_2level_size50[49]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[49]->in[39] mux_2level_size50[49]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[49]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[40] mux_2level_size50[49]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[41] mux_2level_size50[49]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[42] mux_2level_size50[49]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[43] mux_2level_size50[49]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[44] mux_2level_size50[49]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[45] mux_2level_size50[49]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[46] mux_2level_size50[49]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[47] mux_2level_size50[49]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[48] mux_2level_size50[49]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[49]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[49]->in[49] mux_2level_size50[49]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[49] gvdd_mux_2level_size50[49] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[49]_in[1]_crossbar trig v(mux_2level_size50[49]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[49]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[49]_in[1]_crossbar trig v(mux_2level_size50[49]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[49]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[49]_in[1]_crossbar when v(mux_2level_size50[49]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[49]_in[1]_crossbar trig v(mux_2level_size50[49]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[49]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[49]_in[1]_crossbar when v(mux_2level_size50[49]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[49]_in[1]_crossbar trig v(mux_2level_size50[49]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[49]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[49]_leakage_power avg p(Vgvdd_mux_2level_size50[49]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[49]_in[1]_crossbar param='mux_2level_size50[49]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[49]_dynamic_power avg p(Vgvdd_mux_2level_size50[49]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[49]_energy_per_cycle param='mux_2level_size50[49]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[49]_in[1]_crossbar param='mux_2level_size50[49]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[49]_in[1]_crossbar param='dynamic_power_idle_mux50[49]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[49]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[49]) from='start_rise_idle_mux50[49]_in[1]_crossbar' to='start_rise_idle_mux50[49]_in[1]_crossbar+switch_rise_idle_mux50[49]_in[1]_crossbar' -.meas tran dynamic_fall_idle_mux50[49]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[49]) from='start_fall_idle_mux50[49]_in[1]_crossbar' to='start_fall_idle_mux50[49]_in[1]_crossbar+switch_fall_idle_mux50[49]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to49] -+ param='sum_leakage_power_mux[0to48]+leakage_idle_mux50[49]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to49] -+ param='sum_energy_per_cycle_mux[0to48]+energy_per_cycle_idle_mux50[49]_in[1]_crossbar' -Xload_inv[49]_no0 mux_2level_size50[49]->out mux_2level_size50[49]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to49] -+ param='sum_leakage_power_pb_mux[0to48]+leakage_idle_mux50[49]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to49] -+ param='sum_energy_per_cycle_pb_mux[0to48]+energy_per_cycle_idle_mux50[49]_in[1]_crossbar' -Xmux_2level_size50[50] mux_2level_size50[50]->in[0] mux_2level_size50[50]->in[1] mux_2level_size50[50]->in[2] mux_2level_size50[50]->in[3] mux_2level_size50[50]->in[4] mux_2level_size50[50]->in[5] mux_2level_size50[50]->in[6] mux_2level_size50[50]->in[7] mux_2level_size50[50]->in[8] mux_2level_size50[50]->in[9] mux_2level_size50[50]->in[10] mux_2level_size50[50]->in[11] mux_2level_size50[50]->in[12] mux_2level_size50[50]->in[13] mux_2level_size50[50]->in[14] mux_2level_size50[50]->in[15] mux_2level_size50[50]->in[16] mux_2level_size50[50]->in[17] mux_2level_size50[50]->in[18] mux_2level_size50[50]->in[19] mux_2level_size50[50]->in[20] mux_2level_size50[50]->in[21] mux_2level_size50[50]->in[22] mux_2level_size50[50]->in[23] mux_2level_size50[50]->in[24] mux_2level_size50[50]->in[25] mux_2level_size50[50]->in[26] mux_2level_size50[50]->in[27] mux_2level_size50[50]->in[28] mux_2level_size50[50]->in[29] mux_2level_size50[50]->in[30] mux_2level_size50[50]->in[31] mux_2level_size50[50]->in[32] mux_2level_size50[50]->in[33] mux_2level_size50[50]->in[34] mux_2level_size50[50]->in[35] mux_2level_size50[50]->in[36] mux_2level_size50[50]->in[37] mux_2level_size50[50]->in[38] mux_2level_size50[50]->in[39] mux_2level_size50[50]->in[40] mux_2level_size50[50]->in[41] mux_2level_size50[50]->in[42] mux_2level_size50[50]->in[43] mux_2level_size50[50]->in[44] mux_2level_size50[50]->in[45] mux_2level_size50[50]->in[46] mux_2level_size50[50]->in[47] mux_2level_size50[50]->in[48] mux_2level_size50[50]->in[49] mux_2level_size50[50]->out sram[800]->outb sram[800]->out sram[801]->out sram[801]->outb sram[802]->out sram[802]->outb sram[803]->out sram[803]->outb sram[804]->out sram[804]->outb sram[805]->out sram[805]->outb sram[806]->out sram[806]->outb sram[807]->out sram[807]->outb sram[808]->outb sram[808]->out sram[809]->out sram[809]->outb sram[810]->out sram[810]->outb sram[811]->out sram[811]->outb sram[812]->out sram[812]->outb sram[813]->out sram[813]->outb sram[814]->out sram[814]->outb sram[815]->out sram[815]->outb gvdd_mux_2level_size50[50] 0 mux_2level_size50 -***** SRAM bits for MUX[50], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[800] sram->in sram[800]->out sram[800]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[800]->out) 0 -.nodeset V(sram[800]->outb) vsp -Xsram[801] sram->in sram[801]->out sram[801]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[801]->out) 0 -.nodeset V(sram[801]->outb) vsp -Xsram[802] sram->in sram[802]->out sram[802]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[802]->out) 0 -.nodeset V(sram[802]->outb) vsp -Xsram[803] sram->in sram[803]->out sram[803]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[803]->out) 0 -.nodeset V(sram[803]->outb) vsp -Xsram[804] sram->in sram[804]->out sram[804]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[804]->out) 0 -.nodeset V(sram[804]->outb) vsp -Xsram[805] sram->in sram[805]->out sram[805]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[805]->out) 0 -.nodeset V(sram[805]->outb) vsp -Xsram[806] sram->in sram[806]->out sram[806]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[806]->out) 0 -.nodeset V(sram[806]->outb) vsp -Xsram[807] sram->in sram[807]->out sram[807]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[807]->out) 0 -.nodeset V(sram[807]->outb) vsp -Xsram[808] sram->in sram[808]->out sram[808]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[808]->out) 0 -.nodeset V(sram[808]->outb) vsp -Xsram[809] sram->in sram[809]->out sram[809]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[809]->out) 0 -.nodeset V(sram[809]->outb) vsp -Xsram[810] sram->in sram[810]->out sram[810]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[810]->out) 0 -.nodeset V(sram[810]->outb) vsp -Xsram[811] sram->in sram[811]->out sram[811]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[811]->out) 0 -.nodeset V(sram[811]->outb) vsp -Xsram[812] sram->in sram[812]->out sram[812]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[812]->out) 0 -.nodeset V(sram[812]->outb) vsp -Xsram[813] sram->in sram[813]->out sram[813]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[813]->out) 0 -.nodeset V(sram[813]->outb) vsp -Xsram[814] sram->in sram[814]->out sram[814]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[814]->out) 0 -.nodeset V(sram[814]->outb) vsp -Xsram[815] sram->in sram[815]->out sram[815]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[815]->out) 0 -.nodeset V(sram[815]->outb) vsp -***** Signal mux_2level_size50[50]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[0] mux_2level_size50[50]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[1] mux_2level_size50[50]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[2] mux_2level_size50[50]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[3] mux_2level_size50[50]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[4] mux_2level_size50[50]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[5] mux_2level_size50[50]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[6] mux_2level_size50[50]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[7] mux_2level_size50[50]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[8] mux_2level_size50[50]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[9] mux_2level_size50[50]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[10] mux_2level_size50[50]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[11] mux_2level_size50[50]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[12] mux_2level_size50[50]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[13] mux_2level_size50[50]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[14] mux_2level_size50[50]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[15] mux_2level_size50[50]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[16] mux_2level_size50[50]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[17] mux_2level_size50[50]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[18] mux_2level_size50[50]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[19] mux_2level_size50[50]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[20] mux_2level_size50[50]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[21] mux_2level_size50[50]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[22] mux_2level_size50[50]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[23] mux_2level_size50[50]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[24] mux_2level_size50[50]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[25] mux_2level_size50[50]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[26] mux_2level_size50[50]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[27] mux_2level_size50[50]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[28] mux_2level_size50[50]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[29] mux_2level_size50[50]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[30] mux_2level_size50[50]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[31] mux_2level_size50[50]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[32] mux_2level_size50[50]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[33] mux_2level_size50[50]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[34] mux_2level_size50[50]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[35] mux_2level_size50[50]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[36] mux_2level_size50[50]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[37] mux_2level_size50[50]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[38] mux_2level_size50[50]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[50]->in[39] mux_2level_size50[50]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[50]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[40] mux_2level_size50[50]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[41] mux_2level_size50[50]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[42] mux_2level_size50[50]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[43] mux_2level_size50[50]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[44] mux_2level_size50[50]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[45] mux_2level_size50[50]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[46] mux_2level_size50[50]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[47] mux_2level_size50[50]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[48] mux_2level_size50[50]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[50]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[50]->in[49] mux_2level_size50[50]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[50] gvdd_mux_2level_size50[50] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[50]_in[2]_crossbar trig v(mux_2level_size50[50]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[50]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[50]_in[2]_crossbar trig v(mux_2level_size50[50]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[50]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[50]_in[2]_crossbar when v(mux_2level_size50[50]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[50]_in[2]_crossbar trig v(mux_2level_size50[50]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[50]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[50]_in[2]_crossbar when v(mux_2level_size50[50]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[50]_in[2]_crossbar trig v(mux_2level_size50[50]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[50]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[50]_leakage_power avg p(Vgvdd_mux_2level_size50[50]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[50]_in[2]_crossbar param='mux_2level_size50[50]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[50]_dynamic_power avg p(Vgvdd_mux_2level_size50[50]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[50]_energy_per_cycle param='mux_2level_size50[50]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[50]_in[2]_crossbar param='mux_2level_size50[50]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[50]_in[2]_crossbar param='dynamic_power_idle_mux50[50]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[50]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[50]) from='start_rise_idle_mux50[50]_in[2]_crossbar' to='start_rise_idle_mux50[50]_in[2]_crossbar+switch_rise_idle_mux50[50]_in[2]_crossbar' -.meas tran dynamic_fall_idle_mux50[50]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[50]) from='start_fall_idle_mux50[50]_in[2]_crossbar' to='start_fall_idle_mux50[50]_in[2]_crossbar+switch_fall_idle_mux50[50]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to50] -+ param='sum_leakage_power_mux[0to49]+leakage_idle_mux50[50]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to50] -+ param='sum_energy_per_cycle_mux[0to49]+energy_per_cycle_idle_mux50[50]_in[2]_crossbar' -Xload_inv[50]_no0 mux_2level_size50[50]->out mux_2level_size50[50]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to50] -+ param='sum_leakage_power_pb_mux[0to49]+leakage_idle_mux50[50]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to50] -+ param='sum_energy_per_cycle_pb_mux[0to49]+energy_per_cycle_idle_mux50[50]_in[2]_crossbar' -Xmux_2level_size50[51] mux_2level_size50[51]->in[0] mux_2level_size50[51]->in[1] mux_2level_size50[51]->in[2] mux_2level_size50[51]->in[3] mux_2level_size50[51]->in[4] mux_2level_size50[51]->in[5] mux_2level_size50[51]->in[6] mux_2level_size50[51]->in[7] mux_2level_size50[51]->in[8] mux_2level_size50[51]->in[9] mux_2level_size50[51]->in[10] mux_2level_size50[51]->in[11] mux_2level_size50[51]->in[12] mux_2level_size50[51]->in[13] mux_2level_size50[51]->in[14] mux_2level_size50[51]->in[15] mux_2level_size50[51]->in[16] mux_2level_size50[51]->in[17] mux_2level_size50[51]->in[18] mux_2level_size50[51]->in[19] mux_2level_size50[51]->in[20] mux_2level_size50[51]->in[21] mux_2level_size50[51]->in[22] mux_2level_size50[51]->in[23] mux_2level_size50[51]->in[24] mux_2level_size50[51]->in[25] mux_2level_size50[51]->in[26] mux_2level_size50[51]->in[27] mux_2level_size50[51]->in[28] mux_2level_size50[51]->in[29] mux_2level_size50[51]->in[30] mux_2level_size50[51]->in[31] mux_2level_size50[51]->in[32] mux_2level_size50[51]->in[33] mux_2level_size50[51]->in[34] mux_2level_size50[51]->in[35] mux_2level_size50[51]->in[36] mux_2level_size50[51]->in[37] mux_2level_size50[51]->in[38] mux_2level_size50[51]->in[39] mux_2level_size50[51]->in[40] mux_2level_size50[51]->in[41] mux_2level_size50[51]->in[42] mux_2level_size50[51]->in[43] mux_2level_size50[51]->in[44] mux_2level_size50[51]->in[45] mux_2level_size50[51]->in[46] mux_2level_size50[51]->in[47] mux_2level_size50[51]->in[48] mux_2level_size50[51]->in[49] mux_2level_size50[51]->out sram[816]->outb sram[816]->out sram[817]->out sram[817]->outb sram[818]->out sram[818]->outb sram[819]->out sram[819]->outb sram[820]->out sram[820]->outb sram[821]->out sram[821]->outb sram[822]->out sram[822]->outb sram[823]->out sram[823]->outb sram[824]->outb sram[824]->out sram[825]->out sram[825]->outb sram[826]->out sram[826]->outb sram[827]->out sram[827]->outb sram[828]->out sram[828]->outb sram[829]->out sram[829]->outb sram[830]->out sram[830]->outb sram[831]->out sram[831]->outb gvdd_mux_2level_size50[51] 0 mux_2level_size50 -***** SRAM bits for MUX[51], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[816] sram->in sram[816]->out sram[816]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[816]->out) 0 -.nodeset V(sram[816]->outb) vsp -Xsram[817] sram->in sram[817]->out sram[817]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[817]->out) 0 -.nodeset V(sram[817]->outb) vsp -Xsram[818] sram->in sram[818]->out sram[818]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[818]->out) 0 -.nodeset V(sram[818]->outb) vsp -Xsram[819] sram->in sram[819]->out sram[819]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[819]->out) 0 -.nodeset V(sram[819]->outb) vsp -Xsram[820] sram->in sram[820]->out sram[820]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[820]->out) 0 -.nodeset V(sram[820]->outb) vsp -Xsram[821] sram->in sram[821]->out sram[821]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[821]->out) 0 -.nodeset V(sram[821]->outb) vsp -Xsram[822] sram->in sram[822]->out sram[822]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[822]->out) 0 -.nodeset V(sram[822]->outb) vsp -Xsram[823] sram->in sram[823]->out sram[823]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[823]->out) 0 -.nodeset V(sram[823]->outb) vsp -Xsram[824] sram->in sram[824]->out sram[824]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[824]->out) 0 -.nodeset V(sram[824]->outb) vsp -Xsram[825] sram->in sram[825]->out sram[825]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[825]->out) 0 -.nodeset V(sram[825]->outb) vsp -Xsram[826] sram->in sram[826]->out sram[826]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[826]->out) 0 -.nodeset V(sram[826]->outb) vsp -Xsram[827] sram->in sram[827]->out sram[827]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[827]->out) 0 -.nodeset V(sram[827]->outb) vsp -Xsram[828] sram->in sram[828]->out sram[828]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[828]->out) 0 -.nodeset V(sram[828]->outb) vsp -Xsram[829] sram->in sram[829]->out sram[829]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[829]->out) 0 -.nodeset V(sram[829]->outb) vsp -Xsram[830] sram->in sram[830]->out sram[830]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[830]->out) 0 -.nodeset V(sram[830]->outb) vsp -Xsram[831] sram->in sram[831]->out sram[831]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[831]->out) 0 -.nodeset V(sram[831]->outb) vsp -***** Signal mux_2level_size50[51]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[0] mux_2level_size50[51]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[1] mux_2level_size50[51]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[2] mux_2level_size50[51]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[3] mux_2level_size50[51]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[4] mux_2level_size50[51]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[5] mux_2level_size50[51]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[6] mux_2level_size50[51]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[7] mux_2level_size50[51]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[8] mux_2level_size50[51]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[9] mux_2level_size50[51]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[10] mux_2level_size50[51]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[11] mux_2level_size50[51]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[12] mux_2level_size50[51]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[13] mux_2level_size50[51]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[14] mux_2level_size50[51]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[15] mux_2level_size50[51]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[16] mux_2level_size50[51]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[17] mux_2level_size50[51]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[18] mux_2level_size50[51]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[19] mux_2level_size50[51]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[20] mux_2level_size50[51]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[21] mux_2level_size50[51]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[22] mux_2level_size50[51]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[23] mux_2level_size50[51]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[24] mux_2level_size50[51]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[25] mux_2level_size50[51]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[26] mux_2level_size50[51]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[27] mux_2level_size50[51]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[28] mux_2level_size50[51]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[29] mux_2level_size50[51]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[30] mux_2level_size50[51]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[31] mux_2level_size50[51]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[32] mux_2level_size50[51]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[33] mux_2level_size50[51]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[34] mux_2level_size50[51]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[35] mux_2level_size50[51]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[36] mux_2level_size50[51]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[37] mux_2level_size50[51]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[38] mux_2level_size50[51]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[51]->in[39] mux_2level_size50[51]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[51]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[40] mux_2level_size50[51]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[41] mux_2level_size50[51]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[42] mux_2level_size50[51]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[43] mux_2level_size50[51]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[44] mux_2level_size50[51]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[45] mux_2level_size50[51]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[46] mux_2level_size50[51]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[47] mux_2level_size50[51]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[48] mux_2level_size50[51]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[51]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[51]->in[49] mux_2level_size50[51]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[51] gvdd_mux_2level_size50[51] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[51]_in[3]_crossbar trig v(mux_2level_size50[51]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[51]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[51]_in[3]_crossbar trig v(mux_2level_size50[51]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[51]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[51]_in[3]_crossbar when v(mux_2level_size50[51]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[51]_in[3]_crossbar trig v(mux_2level_size50[51]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[51]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[51]_in[3]_crossbar when v(mux_2level_size50[51]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[51]_in[3]_crossbar trig v(mux_2level_size50[51]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[51]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[51]_leakage_power avg p(Vgvdd_mux_2level_size50[51]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[51]_in[3]_crossbar param='mux_2level_size50[51]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[51]_dynamic_power avg p(Vgvdd_mux_2level_size50[51]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[51]_energy_per_cycle param='mux_2level_size50[51]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[51]_in[3]_crossbar param='mux_2level_size50[51]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[51]_in[3]_crossbar param='dynamic_power_idle_mux50[51]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[51]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[51]) from='start_rise_idle_mux50[51]_in[3]_crossbar' to='start_rise_idle_mux50[51]_in[3]_crossbar+switch_rise_idle_mux50[51]_in[3]_crossbar' -.meas tran dynamic_fall_idle_mux50[51]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[51]) from='start_fall_idle_mux50[51]_in[3]_crossbar' to='start_fall_idle_mux50[51]_in[3]_crossbar+switch_fall_idle_mux50[51]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to51] -+ param='sum_leakage_power_mux[0to50]+leakage_idle_mux50[51]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to51] -+ param='sum_energy_per_cycle_mux[0to50]+energy_per_cycle_idle_mux50[51]_in[3]_crossbar' -Xload_inv[51]_no0 mux_2level_size50[51]->out mux_2level_size50[51]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to51] -+ param='sum_leakage_power_pb_mux[0to50]+leakage_idle_mux50[51]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to51] -+ param='sum_energy_per_cycle_pb_mux[0to50]+energy_per_cycle_idle_mux50[51]_in[3]_crossbar' -Xmux_2level_size50[52] mux_2level_size50[52]->in[0] mux_2level_size50[52]->in[1] mux_2level_size50[52]->in[2] mux_2level_size50[52]->in[3] mux_2level_size50[52]->in[4] mux_2level_size50[52]->in[5] mux_2level_size50[52]->in[6] mux_2level_size50[52]->in[7] mux_2level_size50[52]->in[8] mux_2level_size50[52]->in[9] mux_2level_size50[52]->in[10] mux_2level_size50[52]->in[11] mux_2level_size50[52]->in[12] mux_2level_size50[52]->in[13] mux_2level_size50[52]->in[14] mux_2level_size50[52]->in[15] mux_2level_size50[52]->in[16] mux_2level_size50[52]->in[17] mux_2level_size50[52]->in[18] mux_2level_size50[52]->in[19] mux_2level_size50[52]->in[20] mux_2level_size50[52]->in[21] mux_2level_size50[52]->in[22] mux_2level_size50[52]->in[23] mux_2level_size50[52]->in[24] mux_2level_size50[52]->in[25] mux_2level_size50[52]->in[26] mux_2level_size50[52]->in[27] mux_2level_size50[52]->in[28] mux_2level_size50[52]->in[29] mux_2level_size50[52]->in[30] mux_2level_size50[52]->in[31] mux_2level_size50[52]->in[32] mux_2level_size50[52]->in[33] mux_2level_size50[52]->in[34] mux_2level_size50[52]->in[35] mux_2level_size50[52]->in[36] mux_2level_size50[52]->in[37] mux_2level_size50[52]->in[38] mux_2level_size50[52]->in[39] mux_2level_size50[52]->in[40] mux_2level_size50[52]->in[41] mux_2level_size50[52]->in[42] mux_2level_size50[52]->in[43] mux_2level_size50[52]->in[44] mux_2level_size50[52]->in[45] mux_2level_size50[52]->in[46] mux_2level_size50[52]->in[47] mux_2level_size50[52]->in[48] mux_2level_size50[52]->in[49] mux_2level_size50[52]->out sram[832]->outb sram[832]->out sram[833]->out sram[833]->outb sram[834]->out sram[834]->outb sram[835]->out sram[835]->outb sram[836]->out sram[836]->outb sram[837]->out sram[837]->outb sram[838]->out sram[838]->outb sram[839]->out sram[839]->outb sram[840]->outb sram[840]->out sram[841]->out sram[841]->outb sram[842]->out sram[842]->outb sram[843]->out sram[843]->outb sram[844]->out sram[844]->outb sram[845]->out sram[845]->outb sram[846]->out sram[846]->outb sram[847]->out sram[847]->outb gvdd_mux_2level_size50[52] 0 mux_2level_size50 -***** SRAM bits for MUX[52], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[832] sram->in sram[832]->out sram[832]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[832]->out) 0 -.nodeset V(sram[832]->outb) vsp -Xsram[833] sram->in sram[833]->out sram[833]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[833]->out) 0 -.nodeset V(sram[833]->outb) vsp -Xsram[834] sram->in sram[834]->out sram[834]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[834]->out) 0 -.nodeset V(sram[834]->outb) vsp -Xsram[835] sram->in sram[835]->out sram[835]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[835]->out) 0 -.nodeset V(sram[835]->outb) vsp -Xsram[836] sram->in sram[836]->out sram[836]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[836]->out) 0 -.nodeset V(sram[836]->outb) vsp -Xsram[837] sram->in sram[837]->out sram[837]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[837]->out) 0 -.nodeset V(sram[837]->outb) vsp -Xsram[838] sram->in sram[838]->out sram[838]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[838]->out) 0 -.nodeset V(sram[838]->outb) vsp -Xsram[839] sram->in sram[839]->out sram[839]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[839]->out) 0 -.nodeset V(sram[839]->outb) vsp -Xsram[840] sram->in sram[840]->out sram[840]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[840]->out) 0 -.nodeset V(sram[840]->outb) vsp -Xsram[841] sram->in sram[841]->out sram[841]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[841]->out) 0 -.nodeset V(sram[841]->outb) vsp -Xsram[842] sram->in sram[842]->out sram[842]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[842]->out) 0 -.nodeset V(sram[842]->outb) vsp -Xsram[843] sram->in sram[843]->out sram[843]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[843]->out) 0 -.nodeset V(sram[843]->outb) vsp -Xsram[844] sram->in sram[844]->out sram[844]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[844]->out) 0 -.nodeset V(sram[844]->outb) vsp -Xsram[845] sram->in sram[845]->out sram[845]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[845]->out) 0 -.nodeset V(sram[845]->outb) vsp -Xsram[846] sram->in sram[846]->out sram[846]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[846]->out) 0 -.nodeset V(sram[846]->outb) vsp -Xsram[847] sram->in sram[847]->out sram[847]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[847]->out) 0 -.nodeset V(sram[847]->outb) vsp -***** Signal mux_2level_size50[52]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[0] mux_2level_size50[52]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[1] mux_2level_size50[52]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[2] mux_2level_size50[52]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[3] mux_2level_size50[52]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[4] mux_2level_size50[52]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[5] mux_2level_size50[52]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[6] mux_2level_size50[52]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[7] mux_2level_size50[52]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[8] mux_2level_size50[52]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[9] mux_2level_size50[52]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[10] mux_2level_size50[52]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[11] mux_2level_size50[52]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[12] mux_2level_size50[52]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[13] mux_2level_size50[52]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[14] mux_2level_size50[52]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[15] mux_2level_size50[52]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[16] mux_2level_size50[52]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[17] mux_2level_size50[52]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[18] mux_2level_size50[52]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[19] mux_2level_size50[52]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[20] mux_2level_size50[52]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[21] mux_2level_size50[52]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[22] mux_2level_size50[52]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[23] mux_2level_size50[52]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[24] mux_2level_size50[52]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[25] mux_2level_size50[52]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[26] mux_2level_size50[52]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[27] mux_2level_size50[52]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[28] mux_2level_size50[52]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[29] mux_2level_size50[52]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[30] mux_2level_size50[52]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[31] mux_2level_size50[52]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[32] mux_2level_size50[52]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[33] mux_2level_size50[52]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[34] mux_2level_size50[52]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[35] mux_2level_size50[52]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[36] mux_2level_size50[52]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[37] mux_2level_size50[52]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[38] mux_2level_size50[52]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[52]->in[39] mux_2level_size50[52]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[52]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[40] mux_2level_size50[52]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[41] mux_2level_size50[52]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[42] mux_2level_size50[52]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[43] mux_2level_size50[52]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[44] mux_2level_size50[52]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[45] mux_2level_size50[52]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[46] mux_2level_size50[52]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[47] mux_2level_size50[52]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[48] mux_2level_size50[52]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[52]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[52]->in[49] mux_2level_size50[52]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[52] gvdd_mux_2level_size50[52] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[52]_in[4]_crossbar trig v(mux_2level_size50[52]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[52]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[52]_in[4]_crossbar trig v(mux_2level_size50[52]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[52]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[52]_in[4]_crossbar when v(mux_2level_size50[52]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[52]_in[4]_crossbar trig v(mux_2level_size50[52]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[52]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[52]_in[4]_crossbar when v(mux_2level_size50[52]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[52]_in[4]_crossbar trig v(mux_2level_size50[52]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[52]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[52]_leakage_power avg p(Vgvdd_mux_2level_size50[52]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[52]_in[4]_crossbar param='mux_2level_size50[52]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[52]_dynamic_power avg p(Vgvdd_mux_2level_size50[52]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[52]_energy_per_cycle param='mux_2level_size50[52]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[52]_in[4]_crossbar param='mux_2level_size50[52]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[52]_in[4]_crossbar param='dynamic_power_idle_mux50[52]_in[4]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[52]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[52]) from='start_rise_idle_mux50[52]_in[4]_crossbar' to='start_rise_idle_mux50[52]_in[4]_crossbar+switch_rise_idle_mux50[52]_in[4]_crossbar' -.meas tran dynamic_fall_idle_mux50[52]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[52]) from='start_fall_idle_mux50[52]_in[4]_crossbar' to='start_fall_idle_mux50[52]_in[4]_crossbar+switch_fall_idle_mux50[52]_in[4]_crossbar' -.meas tran sum_leakage_power_mux[0to52] -+ param='sum_leakage_power_mux[0to51]+leakage_idle_mux50[52]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to52] -+ param='sum_energy_per_cycle_mux[0to51]+energy_per_cycle_idle_mux50[52]_in[4]_crossbar' -Xload_inv[52]_no0 mux_2level_size50[52]->out mux_2level_size50[52]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to52] -+ param='sum_leakage_power_pb_mux[0to51]+leakage_idle_mux50[52]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to52] -+ param='sum_energy_per_cycle_pb_mux[0to51]+energy_per_cycle_idle_mux50[52]_in[4]_crossbar' -Xmux_2level_size50[53] mux_2level_size50[53]->in[0] mux_2level_size50[53]->in[1] mux_2level_size50[53]->in[2] mux_2level_size50[53]->in[3] mux_2level_size50[53]->in[4] mux_2level_size50[53]->in[5] mux_2level_size50[53]->in[6] mux_2level_size50[53]->in[7] mux_2level_size50[53]->in[8] mux_2level_size50[53]->in[9] mux_2level_size50[53]->in[10] mux_2level_size50[53]->in[11] mux_2level_size50[53]->in[12] mux_2level_size50[53]->in[13] mux_2level_size50[53]->in[14] mux_2level_size50[53]->in[15] mux_2level_size50[53]->in[16] mux_2level_size50[53]->in[17] mux_2level_size50[53]->in[18] mux_2level_size50[53]->in[19] mux_2level_size50[53]->in[20] mux_2level_size50[53]->in[21] mux_2level_size50[53]->in[22] mux_2level_size50[53]->in[23] mux_2level_size50[53]->in[24] mux_2level_size50[53]->in[25] mux_2level_size50[53]->in[26] mux_2level_size50[53]->in[27] mux_2level_size50[53]->in[28] mux_2level_size50[53]->in[29] mux_2level_size50[53]->in[30] mux_2level_size50[53]->in[31] mux_2level_size50[53]->in[32] mux_2level_size50[53]->in[33] mux_2level_size50[53]->in[34] mux_2level_size50[53]->in[35] mux_2level_size50[53]->in[36] mux_2level_size50[53]->in[37] mux_2level_size50[53]->in[38] mux_2level_size50[53]->in[39] mux_2level_size50[53]->in[40] mux_2level_size50[53]->in[41] mux_2level_size50[53]->in[42] mux_2level_size50[53]->in[43] mux_2level_size50[53]->in[44] mux_2level_size50[53]->in[45] mux_2level_size50[53]->in[46] mux_2level_size50[53]->in[47] mux_2level_size50[53]->in[48] mux_2level_size50[53]->in[49] mux_2level_size50[53]->out sram[848]->outb sram[848]->out sram[849]->out sram[849]->outb sram[850]->out sram[850]->outb sram[851]->out sram[851]->outb sram[852]->out sram[852]->outb sram[853]->out sram[853]->outb sram[854]->out sram[854]->outb sram[855]->out sram[855]->outb sram[856]->outb sram[856]->out sram[857]->out sram[857]->outb sram[858]->out sram[858]->outb sram[859]->out sram[859]->outb sram[860]->out sram[860]->outb sram[861]->out sram[861]->outb sram[862]->out sram[862]->outb sram[863]->out sram[863]->outb gvdd_mux_2level_size50[53] 0 mux_2level_size50 -***** SRAM bits for MUX[53], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[848] sram->in sram[848]->out sram[848]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[848]->out) 0 -.nodeset V(sram[848]->outb) vsp -Xsram[849] sram->in sram[849]->out sram[849]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[849]->out) 0 -.nodeset V(sram[849]->outb) vsp -Xsram[850] sram->in sram[850]->out sram[850]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[850]->out) 0 -.nodeset V(sram[850]->outb) vsp -Xsram[851] sram->in sram[851]->out sram[851]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[851]->out) 0 -.nodeset V(sram[851]->outb) vsp -Xsram[852] sram->in sram[852]->out sram[852]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[852]->out) 0 -.nodeset V(sram[852]->outb) vsp -Xsram[853] sram->in sram[853]->out sram[853]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[853]->out) 0 -.nodeset V(sram[853]->outb) vsp -Xsram[854] sram->in sram[854]->out sram[854]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[854]->out) 0 -.nodeset V(sram[854]->outb) vsp -Xsram[855] sram->in sram[855]->out sram[855]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[855]->out) 0 -.nodeset V(sram[855]->outb) vsp -Xsram[856] sram->in sram[856]->out sram[856]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[856]->out) 0 -.nodeset V(sram[856]->outb) vsp -Xsram[857] sram->in sram[857]->out sram[857]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[857]->out) 0 -.nodeset V(sram[857]->outb) vsp -Xsram[858] sram->in sram[858]->out sram[858]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[858]->out) 0 -.nodeset V(sram[858]->outb) vsp -Xsram[859] sram->in sram[859]->out sram[859]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[859]->out) 0 -.nodeset V(sram[859]->outb) vsp -Xsram[860] sram->in sram[860]->out sram[860]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[860]->out) 0 -.nodeset V(sram[860]->outb) vsp -Xsram[861] sram->in sram[861]->out sram[861]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[861]->out) 0 -.nodeset V(sram[861]->outb) vsp -Xsram[862] sram->in sram[862]->out sram[862]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[862]->out) 0 -.nodeset V(sram[862]->outb) vsp -Xsram[863] sram->in sram[863]->out sram[863]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[863]->out) 0 -.nodeset V(sram[863]->outb) vsp -***** Signal mux_2level_size50[53]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[0] mux_2level_size50[53]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[1] mux_2level_size50[53]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[2] mux_2level_size50[53]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[3] mux_2level_size50[53]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[4] mux_2level_size50[53]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[5] mux_2level_size50[53]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[6] mux_2level_size50[53]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[7] mux_2level_size50[53]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[8] mux_2level_size50[53]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[9] mux_2level_size50[53]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[10] mux_2level_size50[53]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[11] mux_2level_size50[53]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[12] mux_2level_size50[53]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[13] mux_2level_size50[53]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[14] mux_2level_size50[53]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[15] mux_2level_size50[53]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[16] mux_2level_size50[53]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[17] mux_2level_size50[53]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[18] mux_2level_size50[53]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[19] mux_2level_size50[53]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[20] mux_2level_size50[53]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[21] mux_2level_size50[53]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[22] mux_2level_size50[53]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[23] mux_2level_size50[53]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[24] mux_2level_size50[53]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[25] mux_2level_size50[53]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[26] mux_2level_size50[53]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[27] mux_2level_size50[53]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[28] mux_2level_size50[53]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[29] mux_2level_size50[53]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[30] mux_2level_size50[53]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[31] mux_2level_size50[53]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[32] mux_2level_size50[53]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[33] mux_2level_size50[53]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[34] mux_2level_size50[53]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[35] mux_2level_size50[53]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[36] mux_2level_size50[53]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[37] mux_2level_size50[53]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[38] mux_2level_size50[53]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[53]->in[39] mux_2level_size50[53]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[53]->in[40] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[40] mux_2level_size50[53]->in[40] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[41] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[41] mux_2level_size50[53]->in[41] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[42] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[42] mux_2level_size50[53]->in[42] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[43] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[43] mux_2level_size50[53]->in[43] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[44] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[44] mux_2level_size50[53]->in[44] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[45] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[45] mux_2level_size50[53]->in[45] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[46] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[46] mux_2level_size50[53]->in[46] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[47] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[47] mux_2level_size50[53]->in[47] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[48] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[48] mux_2level_size50[53]->in[48] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[53]->in[49] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[53]->in[49] mux_2level_size50[53]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[53] gvdd_mux_2level_size50[53] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux50[53]_in[5]_crossbar trig v(mux_2level_size50[53]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[53]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux50[53]_in[5]_crossbar trig v(mux_2level_size50[53]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[53]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux50[53]_in[5]_crossbar when v(mux_2level_size50[53]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux50[53]_in[5]_crossbar trig v(mux_2level_size50[53]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[53]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux50[53]_in[5]_crossbar when v(mux_2level_size50[53]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux50[53]_in[5]_crossbar trig v(mux_2level_size50[53]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[53]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[53]_leakage_power avg p(Vgvdd_mux_2level_size50[53]) from=0 to='clock_period' -.meas tran leakage_idle_mux50[53]_in[5]_crossbar param='mux_2level_size50[53]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[53]_dynamic_power avg p(Vgvdd_mux_2level_size50[53]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[53]_energy_per_cycle param='mux_2level_size50[53]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux50[53]_in[5]_crossbar param='mux_2level_size50[53]_dynamic_power' -.meas tran energy_per_cycle_idle_mux50[53]_in[5]_crossbar param='dynamic_power_idle_mux50[53]_in[5]_crossbar*clock_period' -.meas tran dynamic_rise_idle_mux50[53]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[53]) from='start_rise_idle_mux50[53]_in[5]_crossbar' to='start_rise_idle_mux50[53]_in[5]_crossbar+switch_rise_idle_mux50[53]_in[5]_crossbar' -.meas tran dynamic_fall_idle_mux50[53]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[53]) from='start_fall_idle_mux50[53]_in[5]_crossbar' to='start_fall_idle_mux50[53]_in[5]_crossbar+switch_fall_idle_mux50[53]_in[5]_crossbar' -.meas tran sum_leakage_power_mux[0to53] -+ param='sum_leakage_power_mux[0to52]+leakage_idle_mux50[53]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to53] -+ param='sum_energy_per_cycle_mux[0to52]+energy_per_cycle_idle_mux50[53]_in[5]_crossbar' -Xload_inv[53]_no0 mux_2level_size50[53]->out mux_2level_size50[53]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to53] -+ param='sum_leakage_power_pb_mux[0to52]+leakage_idle_mux50[53]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to53] -+ param='sum_energy_per_cycle_pb_mux[0to52]+energy_per_cycle_idle_mux50[53]_in[5]_crossbar' -Xmux_2level_size50[54] mux_2level_size50[54]->in[0] mux_2level_size50[54]->in[1] mux_2level_size50[54]->in[2] mux_2level_size50[54]->in[3] mux_2level_size50[54]->in[4] mux_2level_size50[54]->in[5] mux_2level_size50[54]->in[6] mux_2level_size50[54]->in[7] mux_2level_size50[54]->in[8] mux_2level_size50[54]->in[9] mux_2level_size50[54]->in[10] mux_2level_size50[54]->in[11] mux_2level_size50[54]->in[12] mux_2level_size50[54]->in[13] mux_2level_size50[54]->in[14] mux_2level_size50[54]->in[15] mux_2level_size50[54]->in[16] mux_2level_size50[54]->in[17] mux_2level_size50[54]->in[18] mux_2level_size50[54]->in[19] mux_2level_size50[54]->in[20] mux_2level_size50[54]->in[21] mux_2level_size50[54]->in[22] mux_2level_size50[54]->in[23] mux_2level_size50[54]->in[24] mux_2level_size50[54]->in[25] mux_2level_size50[54]->in[26] mux_2level_size50[54]->in[27] mux_2level_size50[54]->in[28] mux_2level_size50[54]->in[29] mux_2level_size50[54]->in[30] mux_2level_size50[54]->in[31] mux_2level_size50[54]->in[32] mux_2level_size50[54]->in[33] mux_2level_size50[54]->in[34] mux_2level_size50[54]->in[35] mux_2level_size50[54]->in[36] mux_2level_size50[54]->in[37] mux_2level_size50[54]->in[38] mux_2level_size50[54]->in[39] mux_2level_size50[54]->in[40] mux_2level_size50[54]->in[41] mux_2level_size50[54]->in[42] mux_2level_size50[54]->in[43] mux_2level_size50[54]->in[44] mux_2level_size50[54]->in[45] mux_2level_size50[54]->in[46] mux_2level_size50[54]->in[47] mux_2level_size50[54]->in[48] mux_2level_size50[54]->in[49] mux_2level_size50[54]->out sram[864]->out sram[864]->outb sram[865]->out sram[865]->outb sram[866]->outb sram[866]->out sram[867]->out sram[867]->outb sram[868]->out sram[868]->outb sram[869]->out sram[869]->outb sram[870]->out sram[870]->outb sram[871]->out sram[871]->outb sram[872]->out sram[872]->outb sram[873]->out sram[873]->outb sram[874]->out sram[874]->outb sram[875]->out sram[875]->outb sram[876]->out sram[876]->outb sram[877]->out sram[877]->outb sram[878]->outb sram[878]->out sram[879]->out sram[879]->outb gvdd_mux_2level_size50[54] 0 mux_2level_size50 -***** SRAM bits for MUX[54], level=2, select_path_id=22. ***** -*****0010000000000010***** -Xsram[864] sram->in sram[864]->out sram[864]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[864]->out) 0 -.nodeset V(sram[864]->outb) vsp -Xsram[865] sram->in sram[865]->out sram[865]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[865]->out) 0 -.nodeset V(sram[865]->outb) vsp -Xsram[866] sram->in sram[866]->out sram[866]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[866]->out) 0 -.nodeset V(sram[866]->outb) vsp -Xsram[867] sram->in sram[867]->out sram[867]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[867]->out) 0 -.nodeset V(sram[867]->outb) vsp -Xsram[868] sram->in sram[868]->out sram[868]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[868]->out) 0 -.nodeset V(sram[868]->outb) vsp -Xsram[869] sram->in sram[869]->out sram[869]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[869]->out) 0 -.nodeset V(sram[869]->outb) vsp -Xsram[870] sram->in sram[870]->out sram[870]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[870]->out) 0 -.nodeset V(sram[870]->outb) vsp -Xsram[871] sram->in sram[871]->out sram[871]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[871]->out) 0 -.nodeset V(sram[871]->outb) vsp -Xsram[872] sram->in sram[872]->out sram[872]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[872]->out) 0 -.nodeset V(sram[872]->outb) vsp -Xsram[873] sram->in sram[873]->out sram[873]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[873]->out) 0 -.nodeset V(sram[873]->outb) vsp -Xsram[874] sram->in sram[874]->out sram[874]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[874]->out) 0 -.nodeset V(sram[874]->outb) vsp -Xsram[875] sram->in sram[875]->out sram[875]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[875]->out) 0 -.nodeset V(sram[875]->outb) vsp -Xsram[876] sram->in sram[876]->out sram[876]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[876]->out) 0 -.nodeset V(sram[876]->outb) vsp -Xsram[877] sram->in sram[877]->out sram[877]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[877]->out) 0 -.nodeset V(sram[877]->outb) vsp -Xsram[878] sram->in sram[878]->out sram[878]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[878]->out) 0 -.nodeset V(sram[878]->outb) vsp -Xsram[879] sram->in sram[879]->out sram[879]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[879]->out) 0 -.nodeset V(sram[879]->outb) vsp -***** Signal mux_2level_size50[54]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[0] mux_2level_size50[54]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[1] mux_2level_size50[54]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[2] mux_2level_size50[54]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[3] mux_2level_size50[54]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[4] mux_2level_size50[54]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[5] mux_2level_size50[54]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[6] mux_2level_size50[54]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[7] mux_2level_size50[54]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[8] mux_2level_size50[54]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[9] mux_2level_size50[54]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[10] mux_2level_size50[54]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[11] mux_2level_size50[54]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[12] mux_2level_size50[54]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[13] mux_2level_size50[54]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[14] mux_2level_size50[54]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[15] mux_2level_size50[54]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[16] mux_2level_size50[54]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[17] mux_2level_size50[54]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[18] mux_2level_size50[54]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[19] mux_2level_size50[54]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[20] mux_2level_size50[54]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[21] mux_2level_size50[54]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[54]->in[22] mux_2level_size50[54]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[54]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[23] mux_2level_size50[54]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[24] mux_2level_size50[54]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[25] mux_2level_size50[54]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[26] mux_2level_size50[54]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[27] mux_2level_size50[54]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[28] mux_2level_size50[54]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[29] mux_2level_size50[54]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[30] mux_2level_size50[54]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[31] mux_2level_size50[54]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[32] mux_2level_size50[54]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[33] mux_2level_size50[54]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[54]->in[34] mux_2level_size50[54]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[54]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[35] mux_2level_size50[54]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[36] mux_2level_size50[54]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[37] mux_2level_size50[54]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[54]->in[38] mux_2level_size50[54]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[54]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[39] mux_2level_size50[54]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[40] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[40] mux_2level_size50[54]->in[40] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[41] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[41] mux_2level_size50[54]->in[41] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[42] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[42] mux_2level_size50[54]->in[42] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[43] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[43] mux_2level_size50[54]->in[43] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[44] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[44] mux_2level_size50[54]->in[44] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[45] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[45] mux_2level_size50[54]->in[45] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[46] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[46] mux_2level_size50[54]->in[46] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[47] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[47] mux_2level_size50[54]->in[47] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[48] density = 0, probability=0.***** -Vmux_2level_size50[54]->in[48] mux_2level_size50[54]->in[48] 0 -+ 0 -***** Signal mux_2level_size50[54]->in[49] density = 0.2026, probability=0.4982.***** -Vmux_2level_size50[54]->in[49] mux_2level_size50[54]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[54] gvdd_mux_2level_size50[54] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar trig v(mux_2level_size50[54]->in[22]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[54]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar trig v(mux_2level_size50[54]->in[22]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[54]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar when v(mux_2level_size50[54]->in[22])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar trig v(mux_2level_size50[54]->in[22]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[54]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar when v(mux_2level_size50[54]->in[22])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar trig v(mux_2level_size50[54]->in[22]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[54]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[54]_leakage_power avg p(Vgvdd_mux_2level_size50[54]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar param='mux_2level_size50[54]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[54]_dynamic_power avg p(Vgvdd_mux_2level_size50[54]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[54]_energy_per_cycle param='mux_2level_size50[54]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar param='mux_2level_size50[54]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[54]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar avg p(Vgvdd_mux_2level_size50[54]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar' -.meas tran sum_leakage_power_mux[0to54] -+ param='sum_leakage_power_mux[0to53]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to54] -+ param='sum_energy_per_cycle_mux[0to53]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar' -Xload_inv[54]_no0 mux_2level_size50[54]->out mux_2level_size50[54]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to54] -+ param='sum_leakage_power_pb_mux[0to53]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to54] -+ param='sum_energy_per_cycle_pb_mux[0to53]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[0]_crossbar' -Xmux_2level_size50[55] mux_2level_size50[55]->in[0] mux_2level_size50[55]->in[1] mux_2level_size50[55]->in[2] mux_2level_size50[55]->in[3] mux_2level_size50[55]->in[4] mux_2level_size50[55]->in[5] mux_2level_size50[55]->in[6] mux_2level_size50[55]->in[7] mux_2level_size50[55]->in[8] mux_2level_size50[55]->in[9] mux_2level_size50[55]->in[10] mux_2level_size50[55]->in[11] mux_2level_size50[55]->in[12] mux_2level_size50[55]->in[13] mux_2level_size50[55]->in[14] mux_2level_size50[55]->in[15] mux_2level_size50[55]->in[16] mux_2level_size50[55]->in[17] mux_2level_size50[55]->in[18] mux_2level_size50[55]->in[19] mux_2level_size50[55]->in[20] mux_2level_size50[55]->in[21] mux_2level_size50[55]->in[22] mux_2level_size50[55]->in[23] mux_2level_size50[55]->in[24] mux_2level_size50[55]->in[25] mux_2level_size50[55]->in[26] mux_2level_size50[55]->in[27] mux_2level_size50[55]->in[28] mux_2level_size50[55]->in[29] mux_2level_size50[55]->in[30] mux_2level_size50[55]->in[31] mux_2level_size50[55]->in[32] mux_2level_size50[55]->in[33] mux_2level_size50[55]->in[34] mux_2level_size50[55]->in[35] mux_2level_size50[55]->in[36] mux_2level_size50[55]->in[37] mux_2level_size50[55]->in[38] mux_2level_size50[55]->in[39] mux_2level_size50[55]->in[40] mux_2level_size50[55]->in[41] mux_2level_size50[55]->in[42] mux_2level_size50[55]->in[43] mux_2level_size50[55]->in[44] mux_2level_size50[55]->in[45] mux_2level_size50[55]->in[46] mux_2level_size50[55]->in[47] mux_2level_size50[55]->in[48] mux_2level_size50[55]->in[49] mux_2level_size50[55]->out sram[880]->outb sram[880]->out sram[881]->out sram[881]->outb sram[882]->out sram[882]->outb sram[883]->out sram[883]->outb sram[884]->out sram[884]->outb sram[885]->out sram[885]->outb sram[886]->out sram[886]->outb sram[887]->out sram[887]->outb sram[888]->outb sram[888]->out sram[889]->out sram[889]->outb sram[890]->out sram[890]->outb sram[891]->out sram[891]->outb sram[892]->out sram[892]->outb sram[893]->out sram[893]->outb sram[894]->out sram[894]->outb sram[895]->out sram[895]->outb gvdd_mux_2level_size50[55] 0 mux_2level_size50 -***** SRAM bits for MUX[55], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[880] sram->in sram[880]->out sram[880]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[880]->out) 0 -.nodeset V(sram[880]->outb) vsp -Xsram[881] sram->in sram[881]->out sram[881]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[881]->out) 0 -.nodeset V(sram[881]->outb) vsp -Xsram[882] sram->in sram[882]->out sram[882]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[882]->out) 0 -.nodeset V(sram[882]->outb) vsp -Xsram[883] sram->in sram[883]->out sram[883]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[883]->out) 0 -.nodeset V(sram[883]->outb) vsp -Xsram[884] sram->in sram[884]->out sram[884]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[884]->out) 0 -.nodeset V(sram[884]->outb) vsp -Xsram[885] sram->in sram[885]->out sram[885]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[885]->out) 0 -.nodeset V(sram[885]->outb) vsp -Xsram[886] sram->in sram[886]->out sram[886]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[886]->out) 0 -.nodeset V(sram[886]->outb) vsp -Xsram[887] sram->in sram[887]->out sram[887]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[887]->out) 0 -.nodeset V(sram[887]->outb) vsp -Xsram[888] sram->in sram[888]->out sram[888]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[888]->out) 0 -.nodeset V(sram[888]->outb) vsp -Xsram[889] sram->in sram[889]->out sram[889]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[889]->out) 0 -.nodeset V(sram[889]->outb) vsp -Xsram[890] sram->in sram[890]->out sram[890]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[890]->out) 0 -.nodeset V(sram[890]->outb) vsp -Xsram[891] sram->in sram[891]->out sram[891]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[891]->out) 0 -.nodeset V(sram[891]->outb) vsp -Xsram[892] sram->in sram[892]->out sram[892]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[892]->out) 0 -.nodeset V(sram[892]->outb) vsp -Xsram[893] sram->in sram[893]->out sram[893]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[893]->out) 0 -.nodeset V(sram[893]->outb) vsp -Xsram[894] sram->in sram[894]->out sram[894]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[894]->out) 0 -.nodeset V(sram[894]->outb) vsp -Xsram[895] sram->in sram[895]->out sram[895]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[895]->out) 0 -.nodeset V(sram[895]->outb) vsp -***** Signal mux_2level_size50[55]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[0] mux_2level_size50[55]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[1] mux_2level_size50[55]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[2] mux_2level_size50[55]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[3] mux_2level_size50[55]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[4] mux_2level_size50[55]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[5] mux_2level_size50[55]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[6] mux_2level_size50[55]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[7] mux_2level_size50[55]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[8] mux_2level_size50[55]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[9] mux_2level_size50[55]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[10] mux_2level_size50[55]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[11] mux_2level_size50[55]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[12] mux_2level_size50[55]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[13] mux_2level_size50[55]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[14] mux_2level_size50[55]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[15] mux_2level_size50[55]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[16] mux_2level_size50[55]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[17] mux_2level_size50[55]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[18] mux_2level_size50[55]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[19] mux_2level_size50[55]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[20] mux_2level_size50[55]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[21] mux_2level_size50[55]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[55]->in[22] mux_2level_size50[55]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[55]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[23] mux_2level_size50[55]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[24] mux_2level_size50[55]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[25] mux_2level_size50[55]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[26] mux_2level_size50[55]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[27] mux_2level_size50[55]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[28] mux_2level_size50[55]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[29] mux_2level_size50[55]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[30] mux_2level_size50[55]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[31] mux_2level_size50[55]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[32] mux_2level_size50[55]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[33] mux_2level_size50[55]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[55]->in[34] mux_2level_size50[55]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[55]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[35] mux_2level_size50[55]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[36] mux_2level_size50[55]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[37] mux_2level_size50[55]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[55]->in[38] mux_2level_size50[55]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[55]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[39] mux_2level_size50[55]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[40] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[40] mux_2level_size50[55]->in[40] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[41] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[41] mux_2level_size50[55]->in[41] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[42] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[42] mux_2level_size50[55]->in[42] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[43] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[43] mux_2level_size50[55]->in[43] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[44] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[44] mux_2level_size50[55]->in[44] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[45] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[45] mux_2level_size50[55]->in[45] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[46] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[46] mux_2level_size50[55]->in[46] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[47] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[47] mux_2level_size50[55]->in[47] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[48] density = 0, probability=0.***** -Vmux_2level_size50[55]->in[48] mux_2level_size50[55]->in[48] 0 -+ 0 -***** Signal mux_2level_size50[55]->in[49] density = 0.2026, probability=0.4982.***** -Vmux_2level_size50[55]->in[49] mux_2level_size50[55]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[55] gvdd_mux_2level_size50[55] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar trig v(mux_2level_size50[55]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[55]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar trig v(mux_2level_size50[55]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[55]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar when v(mux_2level_size50[55]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar trig v(mux_2level_size50[55]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[55]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar when v(mux_2level_size50[55]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar trig v(mux_2level_size50[55]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[55]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[55]_leakage_power avg p(Vgvdd_mux_2level_size50[55]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar param='mux_2level_size50[55]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[55]_dynamic_power avg p(Vgvdd_mux_2level_size50[55]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[55]_energy_per_cycle param='mux_2level_size50[55]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar param='mux_2level_size50[55]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[55]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar avg p(Vgvdd_mux_2level_size50[55]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar' -.meas tran sum_leakage_power_mux[0to55] -+ param='sum_leakage_power_mux[0to54]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to55] -+ param='sum_energy_per_cycle_mux[0to54]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar' -Xload_inv[55]_no0 mux_2level_size50[55]->out mux_2level_size50[55]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to55] -+ param='sum_leakage_power_pb_mux[0to54]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to55] -+ param='sum_energy_per_cycle_pb_mux[0to54]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[1]_crossbar' -Xmux_2level_size50[56] mux_2level_size50[56]->in[0] mux_2level_size50[56]->in[1] mux_2level_size50[56]->in[2] mux_2level_size50[56]->in[3] mux_2level_size50[56]->in[4] mux_2level_size50[56]->in[5] mux_2level_size50[56]->in[6] mux_2level_size50[56]->in[7] mux_2level_size50[56]->in[8] mux_2level_size50[56]->in[9] mux_2level_size50[56]->in[10] mux_2level_size50[56]->in[11] mux_2level_size50[56]->in[12] mux_2level_size50[56]->in[13] mux_2level_size50[56]->in[14] mux_2level_size50[56]->in[15] mux_2level_size50[56]->in[16] mux_2level_size50[56]->in[17] mux_2level_size50[56]->in[18] mux_2level_size50[56]->in[19] mux_2level_size50[56]->in[20] mux_2level_size50[56]->in[21] mux_2level_size50[56]->in[22] mux_2level_size50[56]->in[23] mux_2level_size50[56]->in[24] mux_2level_size50[56]->in[25] mux_2level_size50[56]->in[26] mux_2level_size50[56]->in[27] mux_2level_size50[56]->in[28] mux_2level_size50[56]->in[29] mux_2level_size50[56]->in[30] mux_2level_size50[56]->in[31] mux_2level_size50[56]->in[32] mux_2level_size50[56]->in[33] mux_2level_size50[56]->in[34] mux_2level_size50[56]->in[35] mux_2level_size50[56]->in[36] mux_2level_size50[56]->in[37] mux_2level_size50[56]->in[38] mux_2level_size50[56]->in[39] mux_2level_size50[56]->in[40] mux_2level_size50[56]->in[41] mux_2level_size50[56]->in[42] mux_2level_size50[56]->in[43] mux_2level_size50[56]->in[44] mux_2level_size50[56]->in[45] mux_2level_size50[56]->in[46] mux_2level_size50[56]->in[47] mux_2level_size50[56]->in[48] mux_2level_size50[56]->in[49] mux_2level_size50[56]->out sram[896]->outb sram[896]->out sram[897]->out sram[897]->outb sram[898]->out sram[898]->outb sram[899]->out sram[899]->outb sram[900]->out sram[900]->outb sram[901]->out sram[901]->outb sram[902]->out sram[902]->outb sram[903]->out sram[903]->outb sram[904]->outb sram[904]->out sram[905]->out sram[905]->outb sram[906]->out sram[906]->outb sram[907]->out sram[907]->outb sram[908]->out sram[908]->outb sram[909]->out sram[909]->outb sram[910]->out sram[910]->outb sram[911]->out sram[911]->outb gvdd_mux_2level_size50[56] 0 mux_2level_size50 -***** SRAM bits for MUX[56], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[896] sram->in sram[896]->out sram[896]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[896]->out) 0 -.nodeset V(sram[896]->outb) vsp -Xsram[897] sram->in sram[897]->out sram[897]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[897]->out) 0 -.nodeset V(sram[897]->outb) vsp -Xsram[898] sram->in sram[898]->out sram[898]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[898]->out) 0 -.nodeset V(sram[898]->outb) vsp -Xsram[899] sram->in sram[899]->out sram[899]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[899]->out) 0 -.nodeset V(sram[899]->outb) vsp -Xsram[900] sram->in sram[900]->out sram[900]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[900]->out) 0 -.nodeset V(sram[900]->outb) vsp -Xsram[901] sram->in sram[901]->out sram[901]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[901]->out) 0 -.nodeset V(sram[901]->outb) vsp -Xsram[902] sram->in sram[902]->out sram[902]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[902]->out) 0 -.nodeset V(sram[902]->outb) vsp -Xsram[903] sram->in sram[903]->out sram[903]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[903]->out) 0 -.nodeset V(sram[903]->outb) vsp -Xsram[904] sram->in sram[904]->out sram[904]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[904]->out) 0 -.nodeset V(sram[904]->outb) vsp -Xsram[905] sram->in sram[905]->out sram[905]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[905]->out) 0 -.nodeset V(sram[905]->outb) vsp -Xsram[906] sram->in sram[906]->out sram[906]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[906]->out) 0 -.nodeset V(sram[906]->outb) vsp -Xsram[907] sram->in sram[907]->out sram[907]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[907]->out) 0 -.nodeset V(sram[907]->outb) vsp -Xsram[908] sram->in sram[908]->out sram[908]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[908]->out) 0 -.nodeset V(sram[908]->outb) vsp -Xsram[909] sram->in sram[909]->out sram[909]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[909]->out) 0 -.nodeset V(sram[909]->outb) vsp -Xsram[910] sram->in sram[910]->out sram[910]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[910]->out) 0 -.nodeset V(sram[910]->outb) vsp -Xsram[911] sram->in sram[911]->out sram[911]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[911]->out) 0 -.nodeset V(sram[911]->outb) vsp -***** Signal mux_2level_size50[56]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[0] mux_2level_size50[56]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[1] mux_2level_size50[56]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[2] mux_2level_size50[56]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[3] mux_2level_size50[56]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[4] mux_2level_size50[56]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[5] mux_2level_size50[56]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[6] mux_2level_size50[56]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[7] mux_2level_size50[56]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[8] mux_2level_size50[56]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[9] mux_2level_size50[56]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[10] mux_2level_size50[56]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[11] mux_2level_size50[56]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[12] mux_2level_size50[56]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[13] mux_2level_size50[56]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[14] mux_2level_size50[56]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[15] mux_2level_size50[56]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[16] mux_2level_size50[56]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[17] mux_2level_size50[56]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[18] mux_2level_size50[56]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[19] mux_2level_size50[56]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[20] mux_2level_size50[56]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[21] mux_2level_size50[56]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[56]->in[22] mux_2level_size50[56]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[56]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[23] mux_2level_size50[56]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[24] mux_2level_size50[56]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[25] mux_2level_size50[56]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[26] mux_2level_size50[56]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[27] mux_2level_size50[56]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[28] mux_2level_size50[56]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[29] mux_2level_size50[56]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[30] mux_2level_size50[56]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[31] mux_2level_size50[56]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[32] mux_2level_size50[56]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[33] mux_2level_size50[56]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[56]->in[34] mux_2level_size50[56]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[56]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[35] mux_2level_size50[56]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[36] mux_2level_size50[56]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[37] mux_2level_size50[56]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[56]->in[38] mux_2level_size50[56]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[56]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[39] mux_2level_size50[56]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[40] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[40] mux_2level_size50[56]->in[40] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[41] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[41] mux_2level_size50[56]->in[41] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[42] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[42] mux_2level_size50[56]->in[42] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[43] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[43] mux_2level_size50[56]->in[43] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[44] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[44] mux_2level_size50[56]->in[44] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[45] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[45] mux_2level_size50[56]->in[45] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[46] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[46] mux_2level_size50[56]->in[46] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[47] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[47] mux_2level_size50[56]->in[47] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[48] density = 0, probability=0.***** -Vmux_2level_size50[56]->in[48] mux_2level_size50[56]->in[48] 0 -+ 0 -***** Signal mux_2level_size50[56]->in[49] density = 0.2026, probability=0.4982.***** -Vmux_2level_size50[56]->in[49] mux_2level_size50[56]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[56] gvdd_mux_2level_size50[56] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar trig v(mux_2level_size50[56]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[56]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar trig v(mux_2level_size50[56]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[56]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar when v(mux_2level_size50[56]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar trig v(mux_2level_size50[56]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[56]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar when v(mux_2level_size50[56]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar trig v(mux_2level_size50[56]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[56]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[56]_leakage_power avg p(Vgvdd_mux_2level_size50[56]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar param='mux_2level_size50[56]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[56]_dynamic_power avg p(Vgvdd_mux_2level_size50[56]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[56]_energy_per_cycle param='mux_2level_size50[56]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar param='mux_2level_size50[56]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[56]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar avg p(Vgvdd_mux_2level_size50[56]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar' -.meas tran sum_leakage_power_mux[0to56] -+ param='sum_leakage_power_mux[0to55]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to56] -+ param='sum_energy_per_cycle_mux[0to55]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar' -Xload_inv[56]_no0 mux_2level_size50[56]->out mux_2level_size50[56]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to56] -+ param='sum_leakage_power_pb_mux[0to55]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to56] -+ param='sum_energy_per_cycle_pb_mux[0to55]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[2]_crossbar' -Xmux_2level_size50[57] mux_2level_size50[57]->in[0] mux_2level_size50[57]->in[1] mux_2level_size50[57]->in[2] mux_2level_size50[57]->in[3] mux_2level_size50[57]->in[4] mux_2level_size50[57]->in[5] mux_2level_size50[57]->in[6] mux_2level_size50[57]->in[7] mux_2level_size50[57]->in[8] mux_2level_size50[57]->in[9] mux_2level_size50[57]->in[10] mux_2level_size50[57]->in[11] mux_2level_size50[57]->in[12] mux_2level_size50[57]->in[13] mux_2level_size50[57]->in[14] mux_2level_size50[57]->in[15] mux_2level_size50[57]->in[16] mux_2level_size50[57]->in[17] mux_2level_size50[57]->in[18] mux_2level_size50[57]->in[19] mux_2level_size50[57]->in[20] mux_2level_size50[57]->in[21] mux_2level_size50[57]->in[22] mux_2level_size50[57]->in[23] mux_2level_size50[57]->in[24] mux_2level_size50[57]->in[25] mux_2level_size50[57]->in[26] mux_2level_size50[57]->in[27] mux_2level_size50[57]->in[28] mux_2level_size50[57]->in[29] mux_2level_size50[57]->in[30] mux_2level_size50[57]->in[31] mux_2level_size50[57]->in[32] mux_2level_size50[57]->in[33] mux_2level_size50[57]->in[34] mux_2level_size50[57]->in[35] mux_2level_size50[57]->in[36] mux_2level_size50[57]->in[37] mux_2level_size50[57]->in[38] mux_2level_size50[57]->in[39] mux_2level_size50[57]->in[40] mux_2level_size50[57]->in[41] mux_2level_size50[57]->in[42] mux_2level_size50[57]->in[43] mux_2level_size50[57]->in[44] mux_2level_size50[57]->in[45] mux_2level_size50[57]->in[46] mux_2level_size50[57]->in[47] mux_2level_size50[57]->in[48] mux_2level_size50[57]->in[49] mux_2level_size50[57]->out sram[912]->outb sram[912]->out sram[913]->out sram[913]->outb sram[914]->out sram[914]->outb sram[915]->out sram[915]->outb sram[916]->out sram[916]->outb sram[917]->out sram[917]->outb sram[918]->out sram[918]->outb sram[919]->out sram[919]->outb sram[920]->outb sram[920]->out sram[921]->out sram[921]->outb sram[922]->out sram[922]->outb sram[923]->out sram[923]->outb sram[924]->out sram[924]->outb sram[925]->out sram[925]->outb sram[926]->out sram[926]->outb sram[927]->out sram[927]->outb gvdd_mux_2level_size50[57] 0 mux_2level_size50 -***** SRAM bits for MUX[57], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[912] sram->in sram[912]->out sram[912]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[912]->out) 0 -.nodeset V(sram[912]->outb) vsp -Xsram[913] sram->in sram[913]->out sram[913]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[913]->out) 0 -.nodeset V(sram[913]->outb) vsp -Xsram[914] sram->in sram[914]->out sram[914]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[914]->out) 0 -.nodeset V(sram[914]->outb) vsp -Xsram[915] sram->in sram[915]->out sram[915]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[915]->out) 0 -.nodeset V(sram[915]->outb) vsp -Xsram[916] sram->in sram[916]->out sram[916]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[916]->out) 0 -.nodeset V(sram[916]->outb) vsp -Xsram[917] sram->in sram[917]->out sram[917]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[917]->out) 0 -.nodeset V(sram[917]->outb) vsp -Xsram[918] sram->in sram[918]->out sram[918]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[918]->out) 0 -.nodeset V(sram[918]->outb) vsp -Xsram[919] sram->in sram[919]->out sram[919]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[919]->out) 0 -.nodeset V(sram[919]->outb) vsp -Xsram[920] sram->in sram[920]->out sram[920]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[920]->out) 0 -.nodeset V(sram[920]->outb) vsp -Xsram[921] sram->in sram[921]->out sram[921]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[921]->out) 0 -.nodeset V(sram[921]->outb) vsp -Xsram[922] sram->in sram[922]->out sram[922]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[922]->out) 0 -.nodeset V(sram[922]->outb) vsp -Xsram[923] sram->in sram[923]->out sram[923]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[923]->out) 0 -.nodeset V(sram[923]->outb) vsp -Xsram[924] sram->in sram[924]->out sram[924]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[924]->out) 0 -.nodeset V(sram[924]->outb) vsp -Xsram[925] sram->in sram[925]->out sram[925]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[925]->out) 0 -.nodeset V(sram[925]->outb) vsp -Xsram[926] sram->in sram[926]->out sram[926]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[926]->out) 0 -.nodeset V(sram[926]->outb) vsp -Xsram[927] sram->in sram[927]->out sram[927]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[927]->out) 0 -.nodeset V(sram[927]->outb) vsp -***** Signal mux_2level_size50[57]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[0] mux_2level_size50[57]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[1] mux_2level_size50[57]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[2] mux_2level_size50[57]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[3] mux_2level_size50[57]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[4] mux_2level_size50[57]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[5] mux_2level_size50[57]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[6] mux_2level_size50[57]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[7] mux_2level_size50[57]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[8] mux_2level_size50[57]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[9] mux_2level_size50[57]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[10] mux_2level_size50[57]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[11] mux_2level_size50[57]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[12] mux_2level_size50[57]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[13] mux_2level_size50[57]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[14] mux_2level_size50[57]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[15] mux_2level_size50[57]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[16] mux_2level_size50[57]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[17] mux_2level_size50[57]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[18] mux_2level_size50[57]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[19] mux_2level_size50[57]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[20] mux_2level_size50[57]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[21] mux_2level_size50[57]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[57]->in[22] mux_2level_size50[57]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[57]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[23] mux_2level_size50[57]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[24] mux_2level_size50[57]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[25] mux_2level_size50[57]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[26] mux_2level_size50[57]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[27] mux_2level_size50[57]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[28] mux_2level_size50[57]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[29] mux_2level_size50[57]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[30] mux_2level_size50[57]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[31] mux_2level_size50[57]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[32] mux_2level_size50[57]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[33] mux_2level_size50[57]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[57]->in[34] mux_2level_size50[57]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[57]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[35] mux_2level_size50[57]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[36] mux_2level_size50[57]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[37] mux_2level_size50[57]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[57]->in[38] mux_2level_size50[57]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[57]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[39] mux_2level_size50[57]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[40] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[40] mux_2level_size50[57]->in[40] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[41] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[41] mux_2level_size50[57]->in[41] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[42] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[42] mux_2level_size50[57]->in[42] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[43] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[43] mux_2level_size50[57]->in[43] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[44] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[44] mux_2level_size50[57]->in[44] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[45] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[45] mux_2level_size50[57]->in[45] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[46] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[46] mux_2level_size50[57]->in[46] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[47] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[47] mux_2level_size50[57]->in[47] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[48] density = 0, probability=0.***** -Vmux_2level_size50[57]->in[48] mux_2level_size50[57]->in[48] 0 -+ 0 -***** Signal mux_2level_size50[57]->in[49] density = 0.2026, probability=0.4982.***** -Vmux_2level_size50[57]->in[49] mux_2level_size50[57]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[57] gvdd_mux_2level_size50[57] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar trig v(mux_2level_size50[57]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[57]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar trig v(mux_2level_size50[57]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[57]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar when v(mux_2level_size50[57]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar trig v(mux_2level_size50[57]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[57]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar when v(mux_2level_size50[57]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar trig v(mux_2level_size50[57]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[57]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[57]_leakage_power avg p(Vgvdd_mux_2level_size50[57]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar param='mux_2level_size50[57]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[57]_dynamic_power avg p(Vgvdd_mux_2level_size50[57]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[57]_energy_per_cycle param='mux_2level_size50[57]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar param='mux_2level_size50[57]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[57]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar avg p(Vgvdd_mux_2level_size50[57]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar' -.meas tran sum_leakage_power_mux[0to57] -+ param='sum_leakage_power_mux[0to56]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to57] -+ param='sum_energy_per_cycle_mux[0to56]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar' -Xload_inv[57]_no0 mux_2level_size50[57]->out mux_2level_size50[57]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to57] -+ param='sum_leakage_power_pb_mux[0to56]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to57] -+ param='sum_energy_per_cycle_pb_mux[0to56]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[3]_crossbar' -Xmux_2level_size50[58] mux_2level_size50[58]->in[0] mux_2level_size50[58]->in[1] mux_2level_size50[58]->in[2] mux_2level_size50[58]->in[3] mux_2level_size50[58]->in[4] mux_2level_size50[58]->in[5] mux_2level_size50[58]->in[6] mux_2level_size50[58]->in[7] mux_2level_size50[58]->in[8] mux_2level_size50[58]->in[9] mux_2level_size50[58]->in[10] mux_2level_size50[58]->in[11] mux_2level_size50[58]->in[12] mux_2level_size50[58]->in[13] mux_2level_size50[58]->in[14] mux_2level_size50[58]->in[15] mux_2level_size50[58]->in[16] mux_2level_size50[58]->in[17] mux_2level_size50[58]->in[18] mux_2level_size50[58]->in[19] mux_2level_size50[58]->in[20] mux_2level_size50[58]->in[21] mux_2level_size50[58]->in[22] mux_2level_size50[58]->in[23] mux_2level_size50[58]->in[24] mux_2level_size50[58]->in[25] mux_2level_size50[58]->in[26] mux_2level_size50[58]->in[27] mux_2level_size50[58]->in[28] mux_2level_size50[58]->in[29] mux_2level_size50[58]->in[30] mux_2level_size50[58]->in[31] mux_2level_size50[58]->in[32] mux_2level_size50[58]->in[33] mux_2level_size50[58]->in[34] mux_2level_size50[58]->in[35] mux_2level_size50[58]->in[36] mux_2level_size50[58]->in[37] mux_2level_size50[58]->in[38] mux_2level_size50[58]->in[39] mux_2level_size50[58]->in[40] mux_2level_size50[58]->in[41] mux_2level_size50[58]->in[42] mux_2level_size50[58]->in[43] mux_2level_size50[58]->in[44] mux_2level_size50[58]->in[45] mux_2level_size50[58]->in[46] mux_2level_size50[58]->in[47] mux_2level_size50[58]->in[48] mux_2level_size50[58]->in[49] mux_2level_size50[58]->out sram[928]->outb sram[928]->out sram[929]->out sram[929]->outb sram[930]->out sram[930]->outb sram[931]->out sram[931]->outb sram[932]->out sram[932]->outb sram[933]->out sram[933]->outb sram[934]->out sram[934]->outb sram[935]->out sram[935]->outb sram[936]->outb sram[936]->out sram[937]->out sram[937]->outb sram[938]->out sram[938]->outb sram[939]->out sram[939]->outb sram[940]->out sram[940]->outb sram[941]->out sram[941]->outb sram[942]->out sram[942]->outb sram[943]->out sram[943]->outb gvdd_mux_2level_size50[58] 0 mux_2level_size50 -***** SRAM bits for MUX[58], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[928] sram->in sram[928]->out sram[928]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[928]->out) 0 -.nodeset V(sram[928]->outb) vsp -Xsram[929] sram->in sram[929]->out sram[929]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[929]->out) 0 -.nodeset V(sram[929]->outb) vsp -Xsram[930] sram->in sram[930]->out sram[930]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[930]->out) 0 -.nodeset V(sram[930]->outb) vsp -Xsram[931] sram->in sram[931]->out sram[931]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[931]->out) 0 -.nodeset V(sram[931]->outb) vsp -Xsram[932] sram->in sram[932]->out sram[932]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[932]->out) 0 -.nodeset V(sram[932]->outb) vsp -Xsram[933] sram->in sram[933]->out sram[933]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[933]->out) 0 -.nodeset V(sram[933]->outb) vsp -Xsram[934] sram->in sram[934]->out sram[934]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[934]->out) 0 -.nodeset V(sram[934]->outb) vsp -Xsram[935] sram->in sram[935]->out sram[935]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[935]->out) 0 -.nodeset V(sram[935]->outb) vsp -Xsram[936] sram->in sram[936]->out sram[936]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[936]->out) 0 -.nodeset V(sram[936]->outb) vsp -Xsram[937] sram->in sram[937]->out sram[937]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[937]->out) 0 -.nodeset V(sram[937]->outb) vsp -Xsram[938] sram->in sram[938]->out sram[938]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[938]->out) 0 -.nodeset V(sram[938]->outb) vsp -Xsram[939] sram->in sram[939]->out sram[939]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[939]->out) 0 -.nodeset V(sram[939]->outb) vsp -Xsram[940] sram->in sram[940]->out sram[940]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[940]->out) 0 -.nodeset V(sram[940]->outb) vsp -Xsram[941] sram->in sram[941]->out sram[941]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[941]->out) 0 -.nodeset V(sram[941]->outb) vsp -Xsram[942] sram->in sram[942]->out sram[942]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[942]->out) 0 -.nodeset V(sram[942]->outb) vsp -Xsram[943] sram->in sram[943]->out sram[943]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[943]->out) 0 -.nodeset V(sram[943]->outb) vsp -***** Signal mux_2level_size50[58]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[0] mux_2level_size50[58]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[1] mux_2level_size50[58]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[2] mux_2level_size50[58]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[3] mux_2level_size50[58]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[4] mux_2level_size50[58]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[5] mux_2level_size50[58]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[6] mux_2level_size50[58]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[7] mux_2level_size50[58]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[8] mux_2level_size50[58]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[9] mux_2level_size50[58]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[10] mux_2level_size50[58]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[11] mux_2level_size50[58]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[12] mux_2level_size50[58]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[13] mux_2level_size50[58]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[14] mux_2level_size50[58]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[15] mux_2level_size50[58]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[16] mux_2level_size50[58]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[17] mux_2level_size50[58]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[18] mux_2level_size50[58]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[19] mux_2level_size50[58]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[20] mux_2level_size50[58]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[21] mux_2level_size50[58]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[58]->in[22] mux_2level_size50[58]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[58]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[23] mux_2level_size50[58]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[24] mux_2level_size50[58]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[25] mux_2level_size50[58]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[26] mux_2level_size50[58]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[27] mux_2level_size50[58]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[28] mux_2level_size50[58]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[29] mux_2level_size50[58]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[30] mux_2level_size50[58]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[31] mux_2level_size50[58]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[32] mux_2level_size50[58]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[33] mux_2level_size50[58]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[58]->in[34] mux_2level_size50[58]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[58]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[35] mux_2level_size50[58]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[36] mux_2level_size50[58]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[37] mux_2level_size50[58]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[58]->in[38] mux_2level_size50[58]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[58]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[39] mux_2level_size50[58]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[40] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[40] mux_2level_size50[58]->in[40] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[41] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[41] mux_2level_size50[58]->in[41] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[42] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[42] mux_2level_size50[58]->in[42] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[43] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[43] mux_2level_size50[58]->in[43] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[44] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[44] mux_2level_size50[58]->in[44] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[45] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[45] mux_2level_size50[58]->in[45] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[46] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[46] mux_2level_size50[58]->in[46] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[47] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[47] mux_2level_size50[58]->in[47] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[48] density = 0, probability=0.***** -Vmux_2level_size50[58]->in[48] mux_2level_size50[58]->in[48] 0 -+ 0 -***** Signal mux_2level_size50[58]->in[49] density = 0.2026, probability=0.4982.***** -Vmux_2level_size50[58]->in[49] mux_2level_size50[58]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[58] gvdd_mux_2level_size50[58] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar trig v(mux_2level_size50[58]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[58]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar trig v(mux_2level_size50[58]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[58]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar when v(mux_2level_size50[58]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar trig v(mux_2level_size50[58]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[58]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar when v(mux_2level_size50[58]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar trig v(mux_2level_size50[58]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[58]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[58]_leakage_power avg p(Vgvdd_mux_2level_size50[58]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar param='mux_2level_size50[58]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[58]_dynamic_power avg p(Vgvdd_mux_2level_size50[58]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[58]_energy_per_cycle param='mux_2level_size50[58]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar param='mux_2level_size50[58]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[58]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar avg p(Vgvdd_mux_2level_size50[58]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar' -.meas tran sum_leakage_power_mux[0to58] -+ param='sum_leakage_power_mux[0to57]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to58] -+ param='sum_energy_per_cycle_mux[0to57]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar' -Xload_inv[58]_no0 mux_2level_size50[58]->out mux_2level_size50[58]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to58] -+ param='sum_leakage_power_pb_mux[0to57]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to58] -+ param='sum_energy_per_cycle_pb_mux[0to57]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[4]_crossbar' -Xmux_2level_size50[59] mux_2level_size50[59]->in[0] mux_2level_size50[59]->in[1] mux_2level_size50[59]->in[2] mux_2level_size50[59]->in[3] mux_2level_size50[59]->in[4] mux_2level_size50[59]->in[5] mux_2level_size50[59]->in[6] mux_2level_size50[59]->in[7] mux_2level_size50[59]->in[8] mux_2level_size50[59]->in[9] mux_2level_size50[59]->in[10] mux_2level_size50[59]->in[11] mux_2level_size50[59]->in[12] mux_2level_size50[59]->in[13] mux_2level_size50[59]->in[14] mux_2level_size50[59]->in[15] mux_2level_size50[59]->in[16] mux_2level_size50[59]->in[17] mux_2level_size50[59]->in[18] mux_2level_size50[59]->in[19] mux_2level_size50[59]->in[20] mux_2level_size50[59]->in[21] mux_2level_size50[59]->in[22] mux_2level_size50[59]->in[23] mux_2level_size50[59]->in[24] mux_2level_size50[59]->in[25] mux_2level_size50[59]->in[26] mux_2level_size50[59]->in[27] mux_2level_size50[59]->in[28] mux_2level_size50[59]->in[29] mux_2level_size50[59]->in[30] mux_2level_size50[59]->in[31] mux_2level_size50[59]->in[32] mux_2level_size50[59]->in[33] mux_2level_size50[59]->in[34] mux_2level_size50[59]->in[35] mux_2level_size50[59]->in[36] mux_2level_size50[59]->in[37] mux_2level_size50[59]->in[38] mux_2level_size50[59]->in[39] mux_2level_size50[59]->in[40] mux_2level_size50[59]->in[41] mux_2level_size50[59]->in[42] mux_2level_size50[59]->in[43] mux_2level_size50[59]->in[44] mux_2level_size50[59]->in[45] mux_2level_size50[59]->in[46] mux_2level_size50[59]->in[47] mux_2level_size50[59]->in[48] mux_2level_size50[59]->in[49] mux_2level_size50[59]->out sram[944]->outb sram[944]->out sram[945]->out sram[945]->outb sram[946]->out sram[946]->outb sram[947]->out sram[947]->outb sram[948]->out sram[948]->outb sram[949]->out sram[949]->outb sram[950]->out sram[950]->outb sram[951]->out sram[951]->outb sram[952]->outb sram[952]->out sram[953]->out sram[953]->outb sram[954]->out sram[954]->outb sram[955]->out sram[955]->outb sram[956]->out sram[956]->outb sram[957]->out sram[957]->outb sram[958]->out sram[958]->outb sram[959]->out sram[959]->outb gvdd_mux_2level_size50[59] 0 mux_2level_size50 -***** SRAM bits for MUX[59], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[944] sram->in sram[944]->out sram[944]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[944]->out) 0 -.nodeset V(sram[944]->outb) vsp -Xsram[945] sram->in sram[945]->out sram[945]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[945]->out) 0 -.nodeset V(sram[945]->outb) vsp -Xsram[946] sram->in sram[946]->out sram[946]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[946]->out) 0 -.nodeset V(sram[946]->outb) vsp -Xsram[947] sram->in sram[947]->out sram[947]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[947]->out) 0 -.nodeset V(sram[947]->outb) vsp -Xsram[948] sram->in sram[948]->out sram[948]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[948]->out) 0 -.nodeset V(sram[948]->outb) vsp -Xsram[949] sram->in sram[949]->out sram[949]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[949]->out) 0 -.nodeset V(sram[949]->outb) vsp -Xsram[950] sram->in sram[950]->out sram[950]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[950]->out) 0 -.nodeset V(sram[950]->outb) vsp -Xsram[951] sram->in sram[951]->out sram[951]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[951]->out) 0 -.nodeset V(sram[951]->outb) vsp -Xsram[952] sram->in sram[952]->out sram[952]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[952]->out) 0 -.nodeset V(sram[952]->outb) vsp -Xsram[953] sram->in sram[953]->out sram[953]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[953]->out) 0 -.nodeset V(sram[953]->outb) vsp -Xsram[954] sram->in sram[954]->out sram[954]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[954]->out) 0 -.nodeset V(sram[954]->outb) vsp -Xsram[955] sram->in sram[955]->out sram[955]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[955]->out) 0 -.nodeset V(sram[955]->outb) vsp -Xsram[956] sram->in sram[956]->out sram[956]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[956]->out) 0 -.nodeset V(sram[956]->outb) vsp -Xsram[957] sram->in sram[957]->out sram[957]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[957]->out) 0 -.nodeset V(sram[957]->outb) vsp -Xsram[958] sram->in sram[958]->out sram[958]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[958]->out) 0 -.nodeset V(sram[958]->outb) vsp -Xsram[959] sram->in sram[959]->out sram[959]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[959]->out) 0 -.nodeset V(sram[959]->outb) vsp -***** Signal mux_2level_size50[59]->in[0] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[0] mux_2level_size50[59]->in[0] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[1] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[1] mux_2level_size50[59]->in[1] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[2] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[2] mux_2level_size50[59]->in[2] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[3] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[3] mux_2level_size50[59]->in[3] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[4] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[4] mux_2level_size50[59]->in[4] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[5] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[5] mux_2level_size50[59]->in[5] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[6] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[6] mux_2level_size50[59]->in[6] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[7] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[7] mux_2level_size50[59]->in[7] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[8] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[8] mux_2level_size50[59]->in[8] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[9] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[9] mux_2level_size50[59]->in[9] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[10] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[10] mux_2level_size50[59]->in[10] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[11] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[11] mux_2level_size50[59]->in[11] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[12] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[12] mux_2level_size50[59]->in[12] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[13] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[13] mux_2level_size50[59]->in[13] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[14] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[14] mux_2level_size50[59]->in[14] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[15] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[15] mux_2level_size50[59]->in[15] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[16] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[16] mux_2level_size50[59]->in[16] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[17] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[17] mux_2level_size50[59]->in[17] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[18] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[18] mux_2level_size50[59]->in[18] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[19] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[19] mux_2level_size50[59]->in[19] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[20] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[20] mux_2level_size50[59]->in[20] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[21] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[21] mux_2level_size50[59]->in[21] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[22] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[59]->in[22] mux_2level_size50[59]->in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[59]->in[23] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[23] mux_2level_size50[59]->in[23] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[24] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[24] mux_2level_size50[59]->in[24] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[25] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[25] mux_2level_size50[59]->in[25] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[26] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[26] mux_2level_size50[59]->in[26] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[27] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[27] mux_2level_size50[59]->in[27] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[28] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[28] mux_2level_size50[59]->in[28] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[29] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[29] mux_2level_size50[59]->in[29] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[30] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[30] mux_2level_size50[59]->in[30] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[31] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[31] mux_2level_size50[59]->in[31] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[32] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[32] mux_2level_size50[59]->in[32] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[33] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[33] mux_2level_size50[59]->in[33] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[34] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[59]->in[34] mux_2level_size50[59]->in[34] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[59]->in[35] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[35] mux_2level_size50[59]->in[35] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[36] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[36] mux_2level_size50[59]->in[36] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[37] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[37] mux_2level_size50[59]->in[37] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[38] density = 0.2026, probability=0.5018.***** -Vmux_2level_size50[59]->in[38] mux_2level_size50[59]->in[38] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_2level_size50[59]->in[39] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[39] mux_2level_size50[59]->in[39] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[40] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[40] mux_2level_size50[59]->in[40] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[41] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[41] mux_2level_size50[59]->in[41] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[42] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[42] mux_2level_size50[59]->in[42] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[43] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[43] mux_2level_size50[59]->in[43] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[44] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[44] mux_2level_size50[59]->in[44] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[45] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[45] mux_2level_size50[59]->in[45] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[46] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[46] mux_2level_size50[59]->in[46] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[47] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[47] mux_2level_size50[59]->in[47] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[48] density = 0, probability=0.***** -Vmux_2level_size50[59]->in[48] mux_2level_size50[59]->in[48] 0 -+ 0 -***** Signal mux_2level_size50[59]->in[49] density = 0.2026, probability=0.4982.***** -Vmux_2level_size50[59]->in[49] mux_2level_size50[59]->in[49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_2level_size50[59] gvdd_mux_2level_size50[59] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar trig v(mux_2level_size50[59]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[59]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar trig v(mux_2level_size50[59]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[59]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar when v(mux_2level_size50[59]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar trig v(mux_2level_size50[59]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_2level_size50[59]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar when v(mux_2level_size50[59]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar trig v(mux_2level_size50[59]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_2level_size50[59]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_2level_size50[59]_leakage_power avg p(Vgvdd_mux_2level_size50[59]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar param='mux_2level_size50[59]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_2level_size50[59]_dynamic_power avg p(Vgvdd_mux_2level_size50[59]) from='clock_period' to='6*clock_period' -.meas tran mux_2level_size50[59]_energy_per_cycle param='mux_2level_size50[59]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar param='mux_2level_size50[59]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[59]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar avg p(Vgvdd_mux_2level_size50[59]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar' -.meas tran sum_leakage_power_mux[0to59] -+ param='sum_leakage_power_mux[0to58]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_mux[0to59] -+ param='sum_energy_per_cycle_mux[0to58]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar' -Xload_inv[59]_no0 mux_2level_size50[59]->out mux_2level_size50[59]->out_out[0] gvdd_load 0 inv size=5 -.meas tran sum_leakage_power_pb_mux[0to59] -+ param='sum_leakage_power_pb_mux[0to58]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar' -.meas tran sum_energy_per_cycle_pb_mux[0to59] -+ param='sum_energy_per_cycle_pb_mux[0to58]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_in[5]_crossbar' -Xmux_1level_tapbuf_size2[60] mux_1level_tapbuf_size2[60]->in[0] mux_1level_tapbuf_size2[60]->in[1] mux_1level_tapbuf_size2[60]->out sram[960]->outb sram[960]->out gvdd_mux_1level_tapbuf_size2[60] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[60], level=1, select_path_id=0. ***** -*****1***** -Xsram[960] sram->in sram[960]->out sram[960]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[960]->out) 0 -.nodeset V(sram[960]->outb) vsp -***** Signal mux_1level_tapbuf_size2[60]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[60]->in[0] mux_1level_tapbuf_size2[60]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[60]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[60]->in[1] mux_1level_tapbuf_size2[60]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[60] gvdd_mux_1level_tapbuf_size2[60] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux2[60]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[60]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux2[60]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[60]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux2[60]_out[0]_mux1 when v(mux_1level_tapbuf_size2[60]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux2[60]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[60]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux2[60]_out[0]_mux1 when v(mux_1level_tapbuf_size2[60]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux2[60]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[60]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[60]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from=0 to='clock_period' -.meas tran leakage_idle_mux2[60]_out[0]_mux1 param='mux_1level_tapbuf_size2[60]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[60]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[60]_energy_per_cycle param='mux_1level_tapbuf_size2[60]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux2[60]_out[0]_mux1 param='mux_1level_tapbuf_size2[60]_dynamic_power' -.meas tran energy_per_cycle_idle_mux2[60]_out[0]_mux1 param='dynamic_power_idle_mux2[60]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_idle_mux2[60]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='start_rise_idle_mux2[60]_out[0]_mux1' to='start_rise_idle_mux2[60]_out[0]_mux1+switch_rise_idle_mux2[60]_out[0]_mux1' -.meas tran dynamic_fall_idle_mux2[60]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='start_fall_idle_mux2[60]_out[0]_mux1' to='start_fall_idle_mux2[60]_out[0]_mux1+switch_fall_idle_mux2[60]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to60] -+ param='sum_leakage_power_mux[0to59]+leakage_idle_mux2[60]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to60] -+ param='sum_energy_per_cycle_mux[0to59]+energy_per_cycle_idle_mux2[60]_out[0]_mux1' -Xload_inv[60]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[78]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[109]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[112]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_out[59] gvdd_load 0 inv size=1 -Xload_inv[120]_no0 mux_1level_tapbuf_size2[60]->out load_inv[120]_out gvdd_load 0 inv size=1 -Xload_inv[121]_no0 mux_1level_tapbuf_size2[60]->out load_inv[121]_out gvdd_load 0 inv size=1 -Xload_inv[122]_no0 mux_1level_tapbuf_size2[60]->out load_inv[122]_out gvdd_load 0 inv size=1 -Xload_inv[123]_no0 mux_1level_tapbuf_size2[60]->out load_inv[123]_out gvdd_load 0 inv size=1 -Xload_inv[124]_no0 mux_1level_tapbuf_size2[60]->out load_inv[124]_out gvdd_load 0 inv size=1 -Xload_inv[125]_no0 mux_1level_tapbuf_size2[60]->out load_inv[125]_out gvdd_load 0 inv size=1 -Xload_inv[126]_no0 mux_1level_tapbuf_size2[60]->out load_inv[126]_out gvdd_load 0 inv size=1 -Xload_inv[127]_no0 mux_1level_tapbuf_size2[60]->out load_inv[127]_out gvdd_load 0 inv size=1 -Xload_inv[128]_no0 mux_1level_tapbuf_size2[60]->out load_inv[128]_out gvdd_load 0 inv size=1 -Xload_inv[129]_no0 mux_1level_tapbuf_size2[60]->out load_inv[129]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to60] -+ param='sum_leakage_power_pb_mux[0to59]+leakage_idle_mux2[60]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to60] -+ param='sum_energy_per_cycle_pb_mux[0to59]+energy_per_cycle_idle_mux2[60]_out[0]_mux1' -Xmux_1level_tapbuf_size2[61] mux_1level_tapbuf_size2[61]->in[0] mux_1level_tapbuf_size2[61]->in[1] mux_1level_tapbuf_size2[61]->out sram[961]->outb sram[961]->out gvdd_mux_1level_tapbuf_size2[61] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[61], level=1, select_path_id=0. ***** -*****1***** -Xsram[961] sram->in sram[961]->out sram[961]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[961]->out) 0 -.nodeset V(sram[961]->outb) vsp -***** Signal mux_1level_tapbuf_size2[61]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[61]->in[0] mux_1level_tapbuf_size2[61]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[61]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[61]->in[1] mux_1level_tapbuf_size2[61]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[61] gvdd_mux_1level_tapbuf_size2[61] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux2[61]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[61]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux2[61]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[61]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux2[61]_out[0]_mux1 when v(mux_1level_tapbuf_size2[61]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux2[61]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[61]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux2[61]_out[0]_mux1 when v(mux_1level_tapbuf_size2[61]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux2[61]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[61]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[61]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from=0 to='clock_period' -.meas tran leakage_idle_mux2[61]_out[0]_mux1 param='mux_1level_tapbuf_size2[61]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[61]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[61]_energy_per_cycle param='mux_1level_tapbuf_size2[61]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux2[61]_out[0]_mux1 param='mux_1level_tapbuf_size2[61]_dynamic_power' -.meas tran energy_per_cycle_idle_mux2[61]_out[0]_mux1 param='dynamic_power_idle_mux2[61]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_idle_mux2[61]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='start_rise_idle_mux2[61]_out[0]_mux1' to='start_rise_idle_mux2[61]_out[0]_mux1+switch_rise_idle_mux2[61]_out[0]_mux1' -.meas tran dynamic_fall_idle_mux2[61]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='start_fall_idle_mux2[61]_out[0]_mux1' to='start_fall_idle_mux2[61]_out[0]_mux1+switch_fall_idle_mux2[61]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to61] -+ param='sum_leakage_power_mux[0to60]+leakage_idle_mux2[61]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to61] -+ param='sum_energy_per_cycle_mux[0to60]+energy_per_cycle_idle_mux2[61]_out[0]_mux1' -Xload_inv[130]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[180]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_out[59] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 mux_1level_tapbuf_size2[61]->out load_inv[190]_out gvdd_load 0 inv size=1 -Xload_inv[191]_no0 mux_1level_tapbuf_size2[61]->out load_inv[191]_out gvdd_load 0 inv size=1 -Xload_inv[192]_no0 mux_1level_tapbuf_size2[61]->out load_inv[192]_out gvdd_load 0 inv size=1 -Xload_inv[193]_no0 mux_1level_tapbuf_size2[61]->out load_inv[193]_out gvdd_load 0 inv size=1 -Xload_inv[194]_no0 mux_1level_tapbuf_size2[61]->out load_inv[194]_out gvdd_load 0 inv size=1 -Xload_inv[195]_no0 mux_1level_tapbuf_size2[61]->out load_inv[195]_out gvdd_load 0 inv size=1 -Xload_inv[196]_no0 mux_1level_tapbuf_size2[61]->out load_inv[196]_out gvdd_load 0 inv size=1 -Xload_inv[197]_no0 mux_1level_tapbuf_size2[61]->out load_inv[197]_out gvdd_load 0 inv size=1 -Xload_inv[198]_no0 mux_1level_tapbuf_size2[61]->out load_inv[198]_out gvdd_load 0 inv size=1 -Xload_inv[199]_no0 mux_1level_tapbuf_size2[61]->out load_inv[199]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to61] -+ param='sum_leakage_power_pb_mux[0to60]+leakage_idle_mux2[61]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to61] -+ param='sum_energy_per_cycle_pb_mux[0to60]+energy_per_cycle_idle_mux2[61]_out[0]_mux1' -Xmux_1level_tapbuf_size2[62] mux_1level_tapbuf_size2[62]->in[0] mux_1level_tapbuf_size2[62]->in[1] mux_1level_tapbuf_size2[62]->out sram[962]->outb sram[962]->out gvdd_mux_1level_tapbuf_size2[62] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[62], level=1, select_path_id=0. ***** -*****1***** -Xsram[962] sram->in sram[962]->out sram[962]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[962]->out) 0 -.nodeset V(sram[962]->outb) vsp -***** Signal mux_1level_tapbuf_size2[62]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[62]->in[0] mux_1level_tapbuf_size2[62]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[62]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[62]->in[1] mux_1level_tapbuf_size2[62]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[62] gvdd_mux_1level_tapbuf_size2[62] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux2[62]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[62]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux2[62]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[62]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux2[62]_out[0]_mux1 when v(mux_1level_tapbuf_size2[62]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux2[62]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[62]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux2[62]_out[0]_mux1 when v(mux_1level_tapbuf_size2[62]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux2[62]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[62]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[62]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from=0 to='clock_period' -.meas tran leakage_idle_mux2[62]_out[0]_mux1 param='mux_1level_tapbuf_size2[62]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[62]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[62]_energy_per_cycle param='mux_1level_tapbuf_size2[62]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux2[62]_out[0]_mux1 param='mux_1level_tapbuf_size2[62]_dynamic_power' -.meas tran energy_per_cycle_idle_mux2[62]_out[0]_mux1 param='dynamic_power_idle_mux2[62]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_idle_mux2[62]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='start_rise_idle_mux2[62]_out[0]_mux1' to='start_rise_idle_mux2[62]_out[0]_mux1+switch_rise_idle_mux2[62]_out[0]_mux1' -.meas tran dynamic_fall_idle_mux2[62]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='start_fall_idle_mux2[62]_out[0]_mux1' to='start_fall_idle_mux2[62]_out[0]_mux1+switch_fall_idle_mux2[62]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to62] -+ param='sum_leakage_power_mux[0to61]+leakage_idle_mux2[62]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to62] -+ param='sum_energy_per_cycle_mux[0to61]+energy_per_cycle_idle_mux2[62]_out[0]_mux1' -Xload_inv[200]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[240]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_out[59] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 mux_1level_tapbuf_size2[62]->out load_inv[260]_out gvdd_load 0 inv size=1 -Xload_inv[261]_no0 mux_1level_tapbuf_size2[62]->out load_inv[261]_out gvdd_load 0 inv size=1 -Xload_inv[262]_no0 mux_1level_tapbuf_size2[62]->out load_inv[262]_out gvdd_load 0 inv size=1 -Xload_inv[263]_no0 mux_1level_tapbuf_size2[62]->out load_inv[263]_out gvdd_load 0 inv size=1 -Xload_inv[264]_no0 mux_1level_tapbuf_size2[62]->out load_inv[264]_out gvdd_load 0 inv size=1 -Xload_inv[265]_no0 mux_1level_tapbuf_size2[62]->out load_inv[265]_out gvdd_load 0 inv size=1 -Xload_inv[266]_no0 mux_1level_tapbuf_size2[62]->out load_inv[266]_out gvdd_load 0 inv size=1 -Xload_inv[267]_no0 mux_1level_tapbuf_size2[62]->out load_inv[267]_out gvdd_load 0 inv size=1 -Xload_inv[268]_no0 mux_1level_tapbuf_size2[62]->out load_inv[268]_out gvdd_load 0 inv size=1 -Xload_inv[269]_no0 mux_1level_tapbuf_size2[62]->out load_inv[269]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to62] -+ param='sum_leakage_power_pb_mux[0to61]+leakage_idle_mux2[62]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to62] -+ param='sum_energy_per_cycle_pb_mux[0to61]+energy_per_cycle_idle_mux2[62]_out[0]_mux1' -Xmux_1level_tapbuf_size2[63] mux_1level_tapbuf_size2[63]->in[0] mux_1level_tapbuf_size2[63]->in[1] mux_1level_tapbuf_size2[63]->out sram[963]->outb sram[963]->out gvdd_mux_1level_tapbuf_size2[63] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[63], level=1, select_path_id=0. ***** -*****1***** -Xsram[963] sram->in sram[963]->out sram[963]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[963]->out) 0 -.nodeset V(sram[963]->outb) vsp -***** Signal mux_1level_tapbuf_size2[63]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[63]->in[0] mux_1level_tapbuf_size2[63]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[63]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[63]->in[1] mux_1level_tapbuf_size2[63]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[63] gvdd_mux_1level_tapbuf_size2[63] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux2[63]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[63]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux2[63]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[63]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux2[63]_out[0]_mux1 when v(mux_1level_tapbuf_size2[63]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux2[63]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[63]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux2[63]_out[0]_mux1 when v(mux_1level_tapbuf_size2[63]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux2[63]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[63]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[63]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from=0 to='clock_period' -.meas tran leakage_idle_mux2[63]_out[0]_mux1 param='mux_1level_tapbuf_size2[63]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[63]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[63]_energy_per_cycle param='mux_1level_tapbuf_size2[63]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux2[63]_out[0]_mux1 param='mux_1level_tapbuf_size2[63]_dynamic_power' -.meas tran energy_per_cycle_idle_mux2[63]_out[0]_mux1 param='dynamic_power_idle_mux2[63]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_idle_mux2[63]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='start_rise_idle_mux2[63]_out[0]_mux1' to='start_rise_idle_mux2[63]_out[0]_mux1+switch_rise_idle_mux2[63]_out[0]_mux1' -.meas tran dynamic_fall_idle_mux2[63]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='start_fall_idle_mux2[63]_out[0]_mux1' to='start_fall_idle_mux2[63]_out[0]_mux1+switch_fall_idle_mux2[63]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to63] -+ param='sum_leakage_power_mux[0to62]+leakage_idle_mux2[63]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to63] -+ param='sum_energy_per_cycle_mux[0to62]+energy_per_cycle_idle_mux2[63]_out[0]_mux1' -Xload_inv[270]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[300]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[326]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_out[59] gvdd_load 0 inv size=1 -Xload_inv[330]_no0 mux_1level_tapbuf_size2[63]->out load_inv[330]_out gvdd_load 0 inv size=1 -Xload_inv[331]_no0 mux_1level_tapbuf_size2[63]->out load_inv[331]_out gvdd_load 0 inv size=1 -Xload_inv[332]_no0 mux_1level_tapbuf_size2[63]->out load_inv[332]_out gvdd_load 0 inv size=1 -Xload_inv[333]_no0 mux_1level_tapbuf_size2[63]->out load_inv[333]_out gvdd_load 0 inv size=1 -Xload_inv[334]_no0 mux_1level_tapbuf_size2[63]->out load_inv[334]_out gvdd_load 0 inv size=1 -Xload_inv[335]_no0 mux_1level_tapbuf_size2[63]->out load_inv[335]_out gvdd_load 0 inv size=1 -Xload_inv[336]_no0 mux_1level_tapbuf_size2[63]->out load_inv[336]_out gvdd_load 0 inv size=1 -Xload_inv[337]_no0 mux_1level_tapbuf_size2[63]->out load_inv[337]_out gvdd_load 0 inv size=1 -Xload_inv[338]_no0 mux_1level_tapbuf_size2[63]->out load_inv[338]_out gvdd_load 0 inv size=1 -Xload_inv[339]_no0 mux_1level_tapbuf_size2[63]->out load_inv[339]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to63] -+ param='sum_leakage_power_pb_mux[0to62]+leakage_idle_mux2[63]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to63] -+ param='sum_energy_per_cycle_pb_mux[0to62]+energy_per_cycle_idle_mux2[63]_out[0]_mux1' -Xmux_1level_tapbuf_size2[64] mux_1level_tapbuf_size2[64]->in[0] mux_1level_tapbuf_size2[64]->in[1] mux_1level_tapbuf_size2[64]->out sram[964]->outb sram[964]->out gvdd_mux_1level_tapbuf_size2[64] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[64], level=1, select_path_id=0. ***** -*****1***** -Xsram[964] sram->in sram[964]->out sram[964]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[964]->out) 0 -.nodeset V(sram[964]->outb) vsp -***** Signal mux_1level_tapbuf_size2[64]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[64]->in[0] mux_1level_tapbuf_size2[64]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[64]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[64]->in[1] mux_1level_tapbuf_size2[64]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[64] gvdd_mux_1level_tapbuf_size2[64] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux2[64]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[64]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux2[64]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[64]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux2[64]_out[0]_mux1 when v(mux_1level_tapbuf_size2[64]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux2[64]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[64]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux2[64]_out[0]_mux1 when v(mux_1level_tapbuf_size2[64]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux2[64]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[64]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[64]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from=0 to='clock_period' -.meas tran leakage_idle_mux2[64]_out[0]_mux1 param='mux_1level_tapbuf_size2[64]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[64]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[64]_energy_per_cycle param='mux_1level_tapbuf_size2[64]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux2[64]_out[0]_mux1 param='mux_1level_tapbuf_size2[64]_dynamic_power' -.meas tran energy_per_cycle_idle_mux2[64]_out[0]_mux1 param='dynamic_power_idle_mux2[64]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_idle_mux2[64]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='start_rise_idle_mux2[64]_out[0]_mux1' to='start_rise_idle_mux2[64]_out[0]_mux1+switch_rise_idle_mux2[64]_out[0]_mux1' -.meas tran dynamic_fall_idle_mux2[64]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='start_fall_idle_mux2[64]_out[0]_mux1' to='start_fall_idle_mux2[64]_out[0]_mux1+switch_fall_idle_mux2[64]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to64] -+ param='sum_leakage_power_mux[0to63]+leakage_idle_mux2[64]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to64] -+ param='sum_energy_per_cycle_mux[0to63]+energy_per_cycle_idle_mux2[64]_out[0]_mux1' -Xload_inv[340]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[342]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[345]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[357]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[360]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[365]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[369]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[381]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[384]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[388]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[389]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[390]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[391]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[392]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[393]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[394]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[395]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[396]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[397]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[398]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[399]_no0 mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_out[59] gvdd_load 0 inv size=1 -Xload_inv[400]_no0 mux_1level_tapbuf_size2[64]->out load_inv[400]_out gvdd_load 0 inv size=1 -Xload_inv[401]_no0 mux_1level_tapbuf_size2[64]->out load_inv[401]_out gvdd_load 0 inv size=1 -Xload_inv[402]_no0 mux_1level_tapbuf_size2[64]->out load_inv[402]_out gvdd_load 0 inv size=1 -Xload_inv[403]_no0 mux_1level_tapbuf_size2[64]->out load_inv[403]_out gvdd_load 0 inv size=1 -Xload_inv[404]_no0 mux_1level_tapbuf_size2[64]->out load_inv[404]_out gvdd_load 0 inv size=1 -Xload_inv[405]_no0 mux_1level_tapbuf_size2[64]->out load_inv[405]_out gvdd_load 0 inv size=1 -Xload_inv[406]_no0 mux_1level_tapbuf_size2[64]->out load_inv[406]_out gvdd_load 0 inv size=1 -Xload_inv[407]_no0 mux_1level_tapbuf_size2[64]->out load_inv[407]_out gvdd_load 0 inv size=1 -Xload_inv[408]_no0 mux_1level_tapbuf_size2[64]->out load_inv[408]_out gvdd_load 0 inv size=1 -Xload_inv[409]_no0 mux_1level_tapbuf_size2[64]->out load_inv[409]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to64] -+ param='sum_leakage_power_pb_mux[0to63]+leakage_idle_mux2[64]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to64] -+ param='sum_energy_per_cycle_pb_mux[0to63]+energy_per_cycle_idle_mux2[64]_out[0]_mux1' -Xmux_1level_tapbuf_size2[65] mux_1level_tapbuf_size2[65]->in[0] mux_1level_tapbuf_size2[65]->in[1] mux_1level_tapbuf_size2[65]->out sram[965]->outb sram[965]->out gvdd_mux_1level_tapbuf_size2[65] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[65], level=1, select_path_id=0. ***** -*****1***** -Xsram[965] sram->in sram[965]->out sram[965]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[965]->out) 0 -.nodeset V(sram[965]->outb) vsp -***** Signal mux_1level_tapbuf_size2[65]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[65]->in[0] mux_1level_tapbuf_size2[65]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[65]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[65]->in[1] mux_1level_tapbuf_size2[65]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[65] gvdd_mux_1level_tapbuf_size2[65] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux2[65]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[65]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux2[65]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[65]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux2[65]_out[0]_mux1 when v(mux_1level_tapbuf_size2[65]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux2[65]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[65]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux2[65]_out[0]_mux1 when v(mux_1level_tapbuf_size2[65]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux2[65]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[65]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[65]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from=0 to='clock_period' -.meas tran leakage_idle_mux2[65]_out[0]_mux1 param='mux_1level_tapbuf_size2[65]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[65]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[65]_energy_per_cycle param='mux_1level_tapbuf_size2[65]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux2[65]_out[0]_mux1 param='mux_1level_tapbuf_size2[65]_dynamic_power' -.meas tran energy_per_cycle_idle_mux2[65]_out[0]_mux1 param='dynamic_power_idle_mux2[65]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_idle_mux2[65]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='start_rise_idle_mux2[65]_out[0]_mux1' to='start_rise_idle_mux2[65]_out[0]_mux1+switch_rise_idle_mux2[65]_out[0]_mux1' -.meas tran dynamic_fall_idle_mux2[65]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='start_fall_idle_mux2[65]_out[0]_mux1' to='start_fall_idle_mux2[65]_out[0]_mux1+switch_fall_idle_mux2[65]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to65] -+ param='sum_leakage_power_mux[0to64]+leakage_idle_mux2[65]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to65] -+ param='sum_energy_per_cycle_mux[0to64]+energy_per_cycle_idle_mux2[65]_out[0]_mux1' -Xload_inv[410]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[411]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[412]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[413]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[414]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[415]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[416]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[417]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[418]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[419]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[420]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[421]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[422]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[423]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[424]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[425]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[426]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[427]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[428]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[429]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[430]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[431]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[432]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[433]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[434]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[435]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[436]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[437]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[438]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[439]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[440]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[441]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[442]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[443]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[444]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[445]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[446]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[447]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[448]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[449]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[450]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[451]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[452]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[453]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[454]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[455]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[456]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[457]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[458]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[459]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[460]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[461]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[462]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[463]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[464]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[465]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[466]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[467]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[468]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[469]_no0 mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_out[59] gvdd_load 0 inv size=1 -Xload_inv[470]_no0 mux_1level_tapbuf_size2[65]->out load_inv[470]_out gvdd_load 0 inv size=1 -Xload_inv[471]_no0 mux_1level_tapbuf_size2[65]->out load_inv[471]_out gvdd_load 0 inv size=1 -Xload_inv[472]_no0 mux_1level_tapbuf_size2[65]->out load_inv[472]_out gvdd_load 0 inv size=1 -Xload_inv[473]_no0 mux_1level_tapbuf_size2[65]->out load_inv[473]_out gvdd_load 0 inv size=1 -Xload_inv[474]_no0 mux_1level_tapbuf_size2[65]->out load_inv[474]_out gvdd_load 0 inv size=1 -Xload_inv[475]_no0 mux_1level_tapbuf_size2[65]->out load_inv[475]_out gvdd_load 0 inv size=1 -Xload_inv[476]_no0 mux_1level_tapbuf_size2[65]->out load_inv[476]_out gvdd_load 0 inv size=1 -Xload_inv[477]_no0 mux_1level_tapbuf_size2[65]->out load_inv[477]_out gvdd_load 0 inv size=1 -Xload_inv[478]_no0 mux_1level_tapbuf_size2[65]->out load_inv[478]_out gvdd_load 0 inv size=1 -Xload_inv[479]_no0 mux_1level_tapbuf_size2[65]->out load_inv[479]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to65] -+ param='sum_leakage_power_pb_mux[0to64]+leakage_idle_mux2[65]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to65] -+ param='sum_energy_per_cycle_pb_mux[0to64]+energy_per_cycle_idle_mux2[65]_out[0]_mux1' -Xmux_1level_tapbuf_size2[66] mux_1level_tapbuf_size2[66]->in[0] mux_1level_tapbuf_size2[66]->in[1] mux_1level_tapbuf_size2[66]->out sram[966]->outb sram[966]->out gvdd_mux_1level_tapbuf_size2[66] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[66], level=1, select_path_id=0. ***** -*****1***** -Xsram[966] sram->in sram[966]->out sram[966]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[966]->out) 0 -.nodeset V(sram[966]->outb) vsp -***** Signal mux_1level_tapbuf_size2[66]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[66]->in[0] mux_1level_tapbuf_size2[66]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[66]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[66]->in[1] mux_1level_tapbuf_size2[66]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[66] gvdd_mux_1level_tapbuf_size2[66] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux2[66]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[66]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux2[66]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[66]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux2[66]_out[0]_mux1 when v(mux_1level_tapbuf_size2[66]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux2[66]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[66]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux2[66]_out[0]_mux1 when v(mux_1level_tapbuf_size2[66]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux2[66]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[66]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[66]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from=0 to='clock_period' -.meas tran leakage_idle_mux2[66]_out[0]_mux1 param='mux_1level_tapbuf_size2[66]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[66]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[66]_energy_per_cycle param='mux_1level_tapbuf_size2[66]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux2[66]_out[0]_mux1 param='mux_1level_tapbuf_size2[66]_dynamic_power' -.meas tran energy_per_cycle_idle_mux2[66]_out[0]_mux1 param='dynamic_power_idle_mux2[66]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_idle_mux2[66]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='start_rise_idle_mux2[66]_out[0]_mux1' to='start_rise_idle_mux2[66]_out[0]_mux1+switch_rise_idle_mux2[66]_out[0]_mux1' -.meas tran dynamic_fall_idle_mux2[66]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='start_fall_idle_mux2[66]_out[0]_mux1' to='start_fall_idle_mux2[66]_out[0]_mux1+switch_fall_idle_mux2[66]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to66] -+ param='sum_leakage_power_mux[0to65]+leakage_idle_mux2[66]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to66] -+ param='sum_energy_per_cycle_mux[0to65]+energy_per_cycle_idle_mux2[66]_out[0]_mux1' -Xload_inv[480]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[481]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[482]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[483]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[484]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[485]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[486]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[487]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[488]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[489]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[490]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[491]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[492]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[493]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[494]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[495]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[496]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[497]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[498]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[499]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[500]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[501]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[502]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[503]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[504]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[505]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[506]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[507]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[508]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[509]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[510]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[511]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[512]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[513]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[514]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[515]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[516]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[517]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[518]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[519]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[520]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[521]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[522]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[523]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[524]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[525]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[526]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[527]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[528]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[529]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[530]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[531]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[532]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[533]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[534]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[535]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[536]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[537]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[538]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[539]_no0 mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_out[59] gvdd_load 0 inv size=1 -Xload_inv[540]_no0 mux_1level_tapbuf_size2[66]->out load_inv[540]_out gvdd_load 0 inv size=1 -Xload_inv[541]_no0 mux_1level_tapbuf_size2[66]->out load_inv[541]_out gvdd_load 0 inv size=1 -Xload_inv[542]_no0 mux_1level_tapbuf_size2[66]->out load_inv[542]_out gvdd_load 0 inv size=1 -Xload_inv[543]_no0 mux_1level_tapbuf_size2[66]->out load_inv[543]_out gvdd_load 0 inv size=1 -Xload_inv[544]_no0 mux_1level_tapbuf_size2[66]->out load_inv[544]_out gvdd_load 0 inv size=1 -Xload_inv[545]_no0 mux_1level_tapbuf_size2[66]->out load_inv[545]_out gvdd_load 0 inv size=1 -Xload_inv[546]_no0 mux_1level_tapbuf_size2[66]->out load_inv[546]_out gvdd_load 0 inv size=1 -Xload_inv[547]_no0 mux_1level_tapbuf_size2[66]->out load_inv[547]_out gvdd_load 0 inv size=1 -Xload_inv[548]_no0 mux_1level_tapbuf_size2[66]->out load_inv[548]_out gvdd_load 0 inv size=1 -Xload_inv[549]_no0 mux_1level_tapbuf_size2[66]->out load_inv[549]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to66] -+ param='sum_leakage_power_pb_mux[0to65]+leakage_idle_mux2[66]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to66] -+ param='sum_energy_per_cycle_pb_mux[0to65]+energy_per_cycle_idle_mux2[66]_out[0]_mux1' -Xmux_1level_tapbuf_size2[67] mux_1level_tapbuf_size2[67]->in[0] mux_1level_tapbuf_size2[67]->in[1] mux_1level_tapbuf_size2[67]->out sram[967]->outb sram[967]->out gvdd_mux_1level_tapbuf_size2[67] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[67], level=1, select_path_id=0. ***** -*****1***** -Xsram[967] sram->in sram[967]->out sram[967]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[967]->out) 0 -.nodeset V(sram[967]->outb) vsp -***** Signal mux_1level_tapbuf_size2[67]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[67]->in[0] mux_1level_tapbuf_size2[67]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[67]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[67]->in[1] mux_1level_tapbuf_size2[67]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[67] gvdd_mux_1level_tapbuf_size2[67] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux2[67]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[67]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux2[67]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[67]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux2[67]_out[0]_mux1 when v(mux_1level_tapbuf_size2[67]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux2[67]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[67]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux2[67]_out[0]_mux1 when v(mux_1level_tapbuf_size2[67]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux2[67]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[67]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[67]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from=0 to='clock_period' -.meas tran leakage_idle_mux2[67]_out[0]_mux1 param='mux_1level_tapbuf_size2[67]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[67]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[67]_energy_per_cycle param='mux_1level_tapbuf_size2[67]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux2[67]_out[0]_mux1 param='mux_1level_tapbuf_size2[67]_dynamic_power' -.meas tran energy_per_cycle_idle_mux2[67]_out[0]_mux1 param='dynamic_power_idle_mux2[67]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_idle_mux2[67]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='start_rise_idle_mux2[67]_out[0]_mux1' to='start_rise_idle_mux2[67]_out[0]_mux1+switch_rise_idle_mux2[67]_out[0]_mux1' -.meas tran dynamic_fall_idle_mux2[67]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='start_fall_idle_mux2[67]_out[0]_mux1' to='start_fall_idle_mux2[67]_out[0]_mux1+switch_fall_idle_mux2[67]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to67] -+ param='sum_leakage_power_mux[0to66]+leakage_idle_mux2[67]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to67] -+ param='sum_energy_per_cycle_mux[0to66]+energy_per_cycle_idle_mux2[67]_out[0]_mux1' -Xload_inv[550]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[551]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[552]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[553]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[554]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[555]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[556]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[557]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[558]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[559]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[560]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[561]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[562]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[563]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[564]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[565]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[566]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[567]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[568]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[569]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[570]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[571]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[572]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[573]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[574]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[575]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[576]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[577]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[578]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[579]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[580]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[581]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[582]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[583]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[584]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[585]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[586]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[587]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[588]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[589]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[590]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[591]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[592]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[593]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[594]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[595]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[596]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[597]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[598]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[599]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[600]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[601]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[602]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[603]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[604]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[605]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[606]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[607]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[608]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[609]_no0 mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_out[59] gvdd_load 0 inv size=1 -Xload_inv[610]_no0 mux_1level_tapbuf_size2[67]->out load_inv[610]_out gvdd_load 0 inv size=1 -Xload_inv[611]_no0 mux_1level_tapbuf_size2[67]->out load_inv[611]_out gvdd_load 0 inv size=1 -Xload_inv[612]_no0 mux_1level_tapbuf_size2[67]->out load_inv[612]_out gvdd_load 0 inv size=1 -Xload_inv[613]_no0 mux_1level_tapbuf_size2[67]->out load_inv[613]_out gvdd_load 0 inv size=1 -Xload_inv[614]_no0 mux_1level_tapbuf_size2[67]->out load_inv[614]_out gvdd_load 0 inv size=1 -Xload_inv[615]_no0 mux_1level_tapbuf_size2[67]->out load_inv[615]_out gvdd_load 0 inv size=1 -Xload_inv[616]_no0 mux_1level_tapbuf_size2[67]->out load_inv[616]_out gvdd_load 0 inv size=1 -Xload_inv[617]_no0 mux_1level_tapbuf_size2[67]->out load_inv[617]_out gvdd_load 0 inv size=1 -Xload_inv[618]_no0 mux_1level_tapbuf_size2[67]->out load_inv[618]_out gvdd_load 0 inv size=1 -Xload_inv[619]_no0 mux_1level_tapbuf_size2[67]->out load_inv[619]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to67] -+ param='sum_leakage_power_pb_mux[0to66]+leakage_idle_mux2[67]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to67] -+ param='sum_energy_per_cycle_pb_mux[0to66]+energy_per_cycle_idle_mux2[67]_out[0]_mux1' -Xmux_1level_tapbuf_size2[68] mux_1level_tapbuf_size2[68]->in[0] mux_1level_tapbuf_size2[68]->in[1] mux_1level_tapbuf_size2[68]->out sram[968]->outb sram[968]->out gvdd_mux_1level_tapbuf_size2[68] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[68], level=1, select_path_id=0. ***** -*****1***** -Xsram[968] sram->in sram[968]->out sram[968]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[968]->out) 0 -.nodeset V(sram[968]->outb) vsp -***** Signal mux_1level_tapbuf_size2[68]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[68]->in[0] mux_1level_tapbuf_size2[68]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[68]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[68]->in[1] mux_1level_tapbuf_size2[68]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[68] gvdd_mux_1level_tapbuf_size2[68] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_idle_mux2[68]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[68]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_idle_mux2[68]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[68]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_idle_mux2[68]_out[0]_mux1 when v(mux_1level_tapbuf_size2[68]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_idle_mux2[68]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[68]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_idle_mux2[68]_out[0]_mux1 when v(mux_1level_tapbuf_size2[68]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_idle_mux2[68]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[68]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[68]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from=0 to='clock_period' -.meas tran leakage_idle_mux2[68]_out[0]_mux1 param='mux_1level_tapbuf_size2[68]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[68]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[68]_energy_per_cycle param='mux_1level_tapbuf_size2[68]_dynamic_power*clock_period' -.meas tran dynamic_power_idle_mux2[68]_out[0]_mux1 param='mux_1level_tapbuf_size2[68]_dynamic_power' -.meas tran energy_per_cycle_idle_mux2[68]_out[0]_mux1 param='dynamic_power_idle_mux2[68]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_idle_mux2[68]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='start_rise_idle_mux2[68]_out[0]_mux1' to='start_rise_idle_mux2[68]_out[0]_mux1+switch_rise_idle_mux2[68]_out[0]_mux1' -.meas tran dynamic_fall_idle_mux2[68]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='start_fall_idle_mux2[68]_out[0]_mux1' to='start_fall_idle_mux2[68]_out[0]_mux1+switch_fall_idle_mux2[68]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to68] -+ param='sum_leakage_power_mux[0to67]+leakage_idle_mux2[68]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to68] -+ param='sum_energy_per_cycle_mux[0to67]+energy_per_cycle_idle_mux2[68]_out[0]_mux1' -Xload_inv[620]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[621]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[622]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[623]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[624]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[625]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[626]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[627]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[628]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[629]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[630]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[631]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[632]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[633]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[634]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[635]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[636]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[637]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[638]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[639]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[640]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[641]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[642]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[643]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[644]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[645]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[646]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[647]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[648]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[649]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[650]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[651]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[652]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[653]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[654]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[655]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[656]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[657]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[658]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[659]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[660]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[661]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[662]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[663]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[664]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[665]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[666]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[667]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[668]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[669]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[670]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[671]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[672]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[673]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[674]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[675]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[676]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[677]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[678]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[679]_no0 mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_out[59] gvdd_load 0 inv size=1 -Xload_inv[680]_no0 mux_1level_tapbuf_size2[68]->out load_inv[680]_out gvdd_load 0 inv size=1 -Xload_inv[681]_no0 mux_1level_tapbuf_size2[68]->out load_inv[681]_out gvdd_load 0 inv size=1 -Xload_inv[682]_no0 mux_1level_tapbuf_size2[68]->out load_inv[682]_out gvdd_load 0 inv size=1 -Xload_inv[683]_no0 mux_1level_tapbuf_size2[68]->out load_inv[683]_out gvdd_load 0 inv size=1 -Xload_inv[684]_no0 mux_1level_tapbuf_size2[68]->out load_inv[684]_out gvdd_load 0 inv size=1 -Xload_inv[685]_no0 mux_1level_tapbuf_size2[68]->out load_inv[685]_out gvdd_load 0 inv size=1 -Xload_inv[686]_no0 mux_1level_tapbuf_size2[68]->out load_inv[686]_out gvdd_load 0 inv size=1 -Xload_inv[687]_no0 mux_1level_tapbuf_size2[68]->out load_inv[687]_out gvdd_load 0 inv size=1 -Xload_inv[688]_no0 mux_1level_tapbuf_size2[68]->out load_inv[688]_out gvdd_load 0 inv size=1 -Xload_inv[689]_no0 mux_1level_tapbuf_size2[68]->out load_inv[689]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to68] -+ param='sum_leakage_power_pb_mux[0to67]+leakage_idle_mux2[68]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to68] -+ param='sum_energy_per_cycle_pb_mux[0to67]+energy_per_cycle_idle_mux2[68]_out[0]_mux1' -Xmux_1level_tapbuf_size2[69] mux_1level_tapbuf_size2[69]->in[0] mux_1level_tapbuf_size2[69]->in[1] mux_1level_tapbuf_size2[69]->out sram[969]->outb sram[969]->out gvdd_mux_1level_tapbuf_size2[69] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[69], level=1, select_path_id=0. ***** -*****1***** -Xsram[969] sram->in sram[969]->out sram[969]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[969]->out) 0 -.nodeset V(sram[969]->outb) vsp -***** Signal mux_1level_tapbuf_size2[69]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[69]->in[0] mux_1level_tapbuf_size2[69]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[69]->in[1] density = 0.100935, probability=0.4982.***** -Vmux_1level_tapbuf_size2[69]->in[1] mux_1level_tapbuf_size2[69]->in[1] 0 -+ pulse(vsp 0 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*19.8147*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '19.8147*clock_period') -Vgvdd_mux_1level_tapbuf_size2[69] gvdd_mux_1level_tapbuf_size2[69] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[69]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[69]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 when v(mux_1level_tapbuf_size2[69]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[69]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 when v(mux_1level_tapbuf_size2[69]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 trig v(mux_1level_tapbuf_size2[69]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[69]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from=0 to='clock_period' -.meas tran leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 param='mux_1level_tapbuf_size2[69]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[69]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[69]_energy_per_cycle param='mux_1level_tapbuf_size2[69]_dynamic_power*clock_period' -.meas tran dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 param='mux_1level_tapbuf_size2[69]_dynamic_power' -.meas tran energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 param='dynamic_power_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1*clock_period' -.meas tran dynamic_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1' to='start_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1+switch_rise_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1' -.meas tran dynamic_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1 avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1' to='start_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1+switch_fall_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1' -.meas tran sum_leakage_power_mux[0to69] -+ param='sum_leakage_power_mux[0to68]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1' -.meas tran sum_energy_per_cycle_mux[0to69] -+ param='sum_energy_per_cycle_mux[0to68]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1' -Xload_inv[690]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[0] gvdd_load 0 inv size=1 -Xload_inv[691]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[1] gvdd_load 0 inv size=1 -Xload_inv[692]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[2] gvdd_load 0 inv size=1 -Xload_inv[693]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[3] gvdd_load 0 inv size=1 -Xload_inv[694]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[4] gvdd_load 0 inv size=1 -Xload_inv[695]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[5] gvdd_load 0 inv size=1 -Xload_inv[696]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[6] gvdd_load 0 inv size=1 -Xload_inv[697]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[7] gvdd_load 0 inv size=1 -Xload_inv[698]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[8] gvdd_load 0 inv size=1 -Xload_inv[699]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[9] gvdd_load 0 inv size=1 -Xload_inv[700]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[10] gvdd_load 0 inv size=1 -Xload_inv[701]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[11] gvdd_load 0 inv size=1 -Xload_inv[702]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[12] gvdd_load 0 inv size=1 -Xload_inv[703]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[13] gvdd_load 0 inv size=1 -Xload_inv[704]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[14] gvdd_load 0 inv size=1 -Xload_inv[705]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[15] gvdd_load 0 inv size=1 -Xload_inv[706]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[16] gvdd_load 0 inv size=1 -Xload_inv[707]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[17] gvdd_load 0 inv size=1 -Xload_inv[708]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[18] gvdd_load 0 inv size=1 -Xload_inv[709]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[19] gvdd_load 0 inv size=1 -Xload_inv[710]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[20] gvdd_load 0 inv size=1 -Xload_inv[711]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[21] gvdd_load 0 inv size=1 -Xload_inv[712]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[22] gvdd_load 0 inv size=1 -Xload_inv[713]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[23] gvdd_load 0 inv size=1 -Xload_inv[714]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[24] gvdd_load 0 inv size=1 -Xload_inv[715]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[25] gvdd_load 0 inv size=1 -Xload_inv[716]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[26] gvdd_load 0 inv size=1 -Xload_inv[717]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[27] gvdd_load 0 inv size=1 -Xload_inv[718]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[28] gvdd_load 0 inv size=1 -Xload_inv[719]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[29] gvdd_load 0 inv size=1 -Xload_inv[720]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[30] gvdd_load 0 inv size=1 -Xload_inv[721]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[31] gvdd_load 0 inv size=1 -Xload_inv[722]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[32] gvdd_load 0 inv size=1 -Xload_inv[723]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[33] gvdd_load 0 inv size=1 -Xload_inv[724]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[34] gvdd_load 0 inv size=1 -Xload_inv[725]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[35] gvdd_load 0 inv size=1 -Xload_inv[726]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[36] gvdd_load 0 inv size=1 -Xload_inv[727]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[37] gvdd_load 0 inv size=1 -Xload_inv[728]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[38] gvdd_load 0 inv size=1 -Xload_inv[729]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[39] gvdd_load 0 inv size=1 -Xload_inv[730]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[40] gvdd_load 0 inv size=1 -Xload_inv[731]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[41] gvdd_load 0 inv size=1 -Xload_inv[732]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[42] gvdd_load 0 inv size=1 -Xload_inv[733]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[43] gvdd_load 0 inv size=1 -Xload_inv[734]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[44] gvdd_load 0 inv size=1 -Xload_inv[735]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[45] gvdd_load 0 inv size=1 -Xload_inv[736]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[46] gvdd_load 0 inv size=1 -Xload_inv[737]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[47] gvdd_load 0 inv size=1 -Xload_inv[738]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[48] gvdd_load 0 inv size=1 -Xload_inv[739]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[49] gvdd_load 0 inv size=1 -Xload_inv[740]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[50] gvdd_load 0 inv size=1 -Xload_inv[741]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[51] gvdd_load 0 inv size=1 -Xload_inv[742]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[52] gvdd_load 0 inv size=1 -Xload_inv[743]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[53] gvdd_load 0 inv size=1 -Xload_inv[744]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[54] gvdd_load 0 inv size=1 -Xload_inv[745]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[55] gvdd_load 0 inv size=1 -Xload_inv[746]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[56] gvdd_load 0 inv size=1 -Xload_inv[747]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[57] gvdd_load 0 inv size=1 -Xload_inv[748]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[58] gvdd_load 0 inv size=1 -Xload_inv[749]_no0 mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_out[59] gvdd_load 0 inv size=1 -Xload_inv[750]_no0 mux_1level_tapbuf_size2[69]->out load_inv[750]_out gvdd_load 0 inv size=1 -Xload_inv[751]_no0 mux_1level_tapbuf_size2[69]->out load_inv[751]_out gvdd_load 0 inv size=1 -Xload_inv[752]_no0 mux_1level_tapbuf_size2[69]->out load_inv[752]_out gvdd_load 0 inv size=1 -Xload_inv[753]_no0 mux_1level_tapbuf_size2[69]->out load_inv[753]_out gvdd_load 0 inv size=1 -Xload_inv[754]_no0 mux_1level_tapbuf_size2[69]->out load_inv[754]_out gvdd_load 0 inv size=1 -Xload_inv[755]_no0 mux_1level_tapbuf_size2[69]->out load_inv[755]_out gvdd_load 0 inv size=1 -Xload_inv[756]_no0 mux_1level_tapbuf_size2[69]->out load_inv[756]_out gvdd_load 0 inv size=1 -Xload_inv[757]_no0 mux_1level_tapbuf_size2[69]->out load_inv[757]_out gvdd_load 0 inv size=1 -Xload_inv[758]_no0 mux_1level_tapbuf_size2[69]->out load_inv[758]_out gvdd_load 0 inv size=1 -Xload_inv[759]_no0 mux_1level_tapbuf_size2[69]->out load_inv[759]_out gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_pb_mux[0to69] -+ param='sum_leakage_power_pb_mux[0to68]+leakage_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1' -.meas tran sum_energy_per_cycle_pb_mux[0to69] -+ param='sum_energy_per_cycle_pb_mux[0to68]+energy_per_cycle_grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_out[0]_mux1' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='6*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to69] -+ param='sum_leakage_power_mux[0to69]' -.meas tran total_energy_per_cycle_mux[0to69] -+ param='sum_energy_per_cycle_mux[0to69]' -.meas tran total_leakage_power_pb_mux -+ param='sum_leakage_power_pb_mux[0to69]' -.meas tran total_energy_per_cycle_pb_mux -+ param='sum_energy_per_cycle_pb_mux[0to69]' -.end diff --git a/examples/spice_test_example_2/run_hspice_sim.sh b/examples/spice_test_example_2/run_hspice_sim.sh deleted file mode 100644 index 5081e04a5..000000000 --- a/examples/spice_test_example_2/run_hspice_sim.sh +++ /dev/null @@ -1,64 +0,0 @@ -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 0 Finish, 21 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/top_tb/example_2_top.sp -o ./spice_test_example_2/results/example_2_top.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 1 Finish, 20 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/grid_tb/example_2_grid1_1_grid_testbench.sp -o ./spice_test_example_2/results/example_2_grid1_1_grid_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 2 Finish, 19 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/hardlogic_tb/example_2_grid1_1_hardlogic_testbench.sp -o ./spice_test_example_2/results/example_2_grid1_1_hardlogic_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 3 Finish, 18 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/lut_tb/example_2_grid1_1_lut_testbench.sp -o ./spice_test_example_2/results/example_2_grid1_1_lut_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 4 Finish, 17 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/sb_tb/example_2_sb1_1_sb_testbench.sp -o ./spice_test_example_2/results/example_2_sb1_1_sb_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 5 Finish, 16 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/sb_tb/example_2_sb1_0_sb_testbench.sp -o ./spice_test_example_2/results/example_2_sb1_0_sb_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 6 Finish, 15 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/sb_tb/example_2_sb0_1_sb_testbench.sp -o ./spice_test_example_2/results/example_2_sb0_1_sb_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 7 Finish, 14 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/sb_tb/example_2_sb0_0_sb_testbench.sp -o ./spice_test_example_2/results/example_2_sb0_0_sb_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 8 Finish, 13 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/cb_tb/example_2_cby1_1_cb_testbench.sp -o ./spice_test_example_2/results/example_2_cby1_1_cb_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 9 Finish, 12 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/cb_tb/example_2_cby0_1_cb_testbench.sp -o ./spice_test_example_2/results/example_2_cby0_1_cb_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 10 Finish, 11 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/cb_tb/example_2_cbx1_1_cb_testbench.sp -o ./spice_test_example_2/results/example_2_cbx1_1_cb_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 11 Finish, 10 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/cb_tb/example_2_cbx1_0_cb_testbench.sp -o ./spice_test_example_2/results/example_2_cbx1_0_cb_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 12 Finish, 9 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/sb_mux_tb/example_2_sb1_1_sbmux_testbench.sp -o ./spice_test_example_2/results/example_2_sb1_1_sbmux_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 13 Finish, 8 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/sb_mux_tb/example_2_sb1_0_sbmux_testbench.sp -o ./spice_test_example_2/results/example_2_sb1_0_sbmux_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 14 Finish, 7 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/sb_mux_tb/example_2_sb0_1_sbmux_testbench.sp -o ./spice_test_example_2/results/example_2_sb0_1_sbmux_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 15 Finish, 6 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/sb_mux_tb/example_2_sb0_0_sbmux_testbench.sp -o ./spice_test_example_2/results/example_2_sb0_0_sbmux_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 16 Finish, 5 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/cb_mux_tb/example_2_cby1_1_cbmux_testbench.sp -o ./spice_test_example_2/results/example_2_cby1_1_cbmux_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 17 Finish, 4 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/cb_mux_tb/example_2_cby0_1_cbmux_testbench.sp -o ./spice_test_example_2/results/example_2_cby0_1_cbmux_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 18 Finish, 3 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/cb_mux_tb/example_2_cbx1_1_cbmux_testbench.sp -o ./spice_test_example_2/results/example_2_cbx1_1_cbmux_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 19 Finish, 2 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/cb_mux_tb/example_2_cbx1_0_cbmux_testbench.sp -o ./spice_test_example_2/results/example_2_cbx1_0_cbmux_testbench.lis -echo Number of clock cycles in simulation: 6 -echo Simulation progress: 20 Finish, 1 to go, total 21 -hspice64 -mt 8 -i ./spice_test_example_2/pb_mux_tb/example_2_grid1_1_pbmux_testbench.sp -o ./spice_test_example_2/results/example_2_grid1_1_pbmux_testbench.lis -echo Simulation progress: 21 Finish, 0 to go, total 21 diff --git a/examples/spice_test_example_2/sb_mux_tb/example_2_sb0_0_sbmux_testbench.sp b/examples/spice_test_example_2/sb_mux_tb/example_2_sb0_0_sbmux_testbench.sp deleted file mode 100644 index da8fdadf9..000000000 --- a/examples/spice_test_example_2/sb_mux_tb/example_2_sb0_0_sbmux_testbench.sp +++ /dev/null @@ -1,5410 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_1level_tapbuf_size2[0] mux_1level_tapbuf_size2[0]->in[0] mux_1level_tapbuf_size2[0]->in[1] mux_1level_tapbuf_size2[0]->out sram[0]->outb sram[0]->out gvdd_mux_1level_tapbuf_size2[0] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[0], level=1, select_path_id=0. ***** -*****1***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -***** Signal mux_1level_tapbuf_size2[0]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[0]->in[0] mux_1level_tapbuf_size2[0]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[0]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[0]->in[1] mux_1level_tapbuf_size2[0]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[0] gvdd_mux_1level_tapbuf_size2[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[391] trig v(mux_1level_tapbuf_size2[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[391] trig v(mux_1level_tapbuf_size2[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[391] when v(mux_1level_tapbuf_size2[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[391] trig v(mux_1level_tapbuf_size2[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[391] when v(mux_1level_tapbuf_size2[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[391] trig v(mux_1level_tapbuf_size2[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[0]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[0]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[391] param='mux_1level_tapbuf_size2[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[0]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[0]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[0]_energy_per_cycle param='mux_1level_tapbuf_size2[0]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[391] param='mux_1level_tapbuf_size2[0]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[391] param='dynamic_power_sb_mux[0][0]_rrnode[391]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[391] avg p(Vgvdd_mux_1level_tapbuf_size2[0]) from='start_rise_sb_mux[0][0]_rrnode[391]' to='start_rise_sb_mux[0][0]_rrnode[391]+switch_rise_sb_mux[0][0]_rrnode[391]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[391] avg p(Vgvdd_mux_1level_tapbuf_size2[0]) from='start_fall_sb_mux[0][0]_rrnode[391]' to='start_fall_sb_mux[0][0]_rrnode[391]+switch_fall_sb_mux[0][0]_rrnode[391]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_sb_mux[0][0]_rrnode[391]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_sb_mux[0][0]_rrnode[391]' -***** Load for rr_node[391] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=0, type=5 ***** -Xchan_mux_1level_tapbuf_size2[0]->out_loadlvl[0]_out mux_1level_tapbuf_size2[0]->out mux_1level_tapbuf_size2[0]->out_loadlvl[0]_out mux_1level_tapbuf_size2[0]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 mux_1level_tapbuf_size2[0]->out_loadlvl[0]_out mux_1level_tapbuf_size2[0]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_1level_tapbuf_size2[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[0]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 mux_1level_tapbuf_size2[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[0]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_1level_tapbuf_size2[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[0]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to0] -+ param='leakage_sb_mux[0][0]_rrnode[391]' -.meas tran sum_energy_per_cycle_sb_mux[0to0] -+ param='energy_per_cycle_sb_mux[0][0]_rrnode[391]' -Xmux_1level_tapbuf_size2[1] mux_1level_tapbuf_size2[1]->in[0] mux_1level_tapbuf_size2[1]->in[1] mux_1level_tapbuf_size2[1]->out sram[1]->outb sram[1]->out gvdd_mux_1level_tapbuf_size2[1] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[1], level=1, select_path_id=0. ***** -*****1***** -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -***** Signal mux_1level_tapbuf_size2[1]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[1]->in[0] mux_1level_tapbuf_size2[1]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[1]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[1]->in[1] mux_1level_tapbuf_size2[1]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[1] gvdd_mux_1level_tapbuf_size2[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[393] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[393] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[393] when v(mux_1level_tapbuf_size2[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[393] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[393] when v(mux_1level_tapbuf_size2[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[393] trig v(mux_1level_tapbuf_size2[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[1]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[393] param='mux_1level_tapbuf_size2[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[1]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[1]_energy_per_cycle param='mux_1level_tapbuf_size2[1]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[393] param='mux_1level_tapbuf_size2[1]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[393] param='dynamic_power_sb_mux[0][0]_rrnode[393]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[393] avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='start_rise_sb_mux[0][0]_rrnode[393]' to='start_rise_sb_mux[0][0]_rrnode[393]+switch_rise_sb_mux[0][0]_rrnode[393]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[393] avg p(Vgvdd_mux_1level_tapbuf_size2[1]) from='start_fall_sb_mux[0][0]_rrnode[393]' to='start_fall_sb_mux[0][0]_rrnode[393]+switch_fall_sb_mux[0][0]_rrnode[393]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_sb_mux[0][0]_rrnode[393]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_sb_mux[0][0]_rrnode[393]' -***** Load for rr_node[393] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=2, type=5 ***** -Xchan_mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[4]_no0 mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out mux_1level_tapbuf_size2[1]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[1]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to1] -+ param='sum_leakage_power_sb_mux[0to0]+leakage_sb_mux[0][0]_rrnode[393]' -.meas tran sum_energy_per_cycle_sb_mux[0to1] -+ param='sum_energy_per_cycle_sb_mux[0to0]+energy_per_cycle_sb_mux[0][0]_rrnode[393]' -Xmux_1level_tapbuf_size2[2] mux_1level_tapbuf_size2[2]->in[0] mux_1level_tapbuf_size2[2]->in[1] mux_1level_tapbuf_size2[2]->out sram[2]->outb sram[2]->out gvdd_mux_1level_tapbuf_size2[2] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[2], level=1, select_path_id=0. ***** -*****1***** -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -***** Signal mux_1level_tapbuf_size2[2]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[2]->in[0] mux_1level_tapbuf_size2[2]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[2]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[2]->in[1] mux_1level_tapbuf_size2[2]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[2] gvdd_mux_1level_tapbuf_size2[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[395] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[395] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[395] when v(mux_1level_tapbuf_size2[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[395] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[395] when v(mux_1level_tapbuf_size2[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[395] trig v(mux_1level_tapbuf_size2[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[2]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[395] param='mux_1level_tapbuf_size2[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[2]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[2]_energy_per_cycle param='mux_1level_tapbuf_size2[2]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[395] param='mux_1level_tapbuf_size2[2]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[395] param='dynamic_power_sb_mux[0][0]_rrnode[395]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[395] avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='start_rise_sb_mux[0][0]_rrnode[395]' to='start_rise_sb_mux[0][0]_rrnode[395]+switch_rise_sb_mux[0][0]_rrnode[395]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[395] avg p(Vgvdd_mux_1level_tapbuf_size2[2]) from='start_fall_sb_mux[0][0]_rrnode[395]' to='start_fall_sb_mux[0][0]_rrnode[395]+switch_fall_sb_mux[0][0]_rrnode[395]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_sb_mux[0][0]_rrnode[395]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_sb_mux[0][0]_rrnode[395]' -***** Load for rr_node[395] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=4, type=5 ***** -Xchan_mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[8]_no0 mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out mux_1level_tapbuf_size2[2]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[2]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to2] -+ param='sum_leakage_power_sb_mux[0to1]+leakage_sb_mux[0][0]_rrnode[395]' -.meas tran sum_energy_per_cycle_sb_mux[0to2] -+ param='sum_energy_per_cycle_sb_mux[0to1]+energy_per_cycle_sb_mux[0][0]_rrnode[395]' -Xmux_1level_tapbuf_size2[3] mux_1level_tapbuf_size2[3]->in[0] mux_1level_tapbuf_size2[3]->in[1] mux_1level_tapbuf_size2[3]->out sram[3]->outb sram[3]->out gvdd_mux_1level_tapbuf_size2[3] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[3], level=1, select_path_id=0. ***** -*****1***** -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -***** Signal mux_1level_tapbuf_size2[3]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[3]->in[0] mux_1level_tapbuf_size2[3]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[3]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[3]->in[1] mux_1level_tapbuf_size2[3]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[3] gvdd_mux_1level_tapbuf_size2[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[397] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[397] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[397] when v(mux_1level_tapbuf_size2[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[397] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[397] when v(mux_1level_tapbuf_size2[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[397] trig v(mux_1level_tapbuf_size2[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[3]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[397] param='mux_1level_tapbuf_size2[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[3]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[3]_energy_per_cycle param='mux_1level_tapbuf_size2[3]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[397] param='mux_1level_tapbuf_size2[3]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[397] param='dynamic_power_sb_mux[0][0]_rrnode[397]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[397] avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='start_rise_sb_mux[0][0]_rrnode[397]' to='start_rise_sb_mux[0][0]_rrnode[397]+switch_rise_sb_mux[0][0]_rrnode[397]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[397] avg p(Vgvdd_mux_1level_tapbuf_size2[3]) from='start_fall_sb_mux[0][0]_rrnode[397]' to='start_fall_sb_mux[0][0]_rrnode[397]+switch_fall_sb_mux[0][0]_rrnode[397]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_sb_mux[0][0]_rrnode[397]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_sb_mux[0][0]_rrnode[397]' -***** Load for rr_node[397] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=6, type=5 ***** -Xchan_mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[12]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out mux_1level_tapbuf_size2[3]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[3]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to3] -+ param='sum_leakage_power_sb_mux[0to2]+leakage_sb_mux[0][0]_rrnode[397]' -.meas tran sum_energy_per_cycle_sb_mux[0to3] -+ param='sum_energy_per_cycle_sb_mux[0to2]+energy_per_cycle_sb_mux[0][0]_rrnode[397]' -Xmux_1level_tapbuf_size2[4] mux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->out sram[4]->outb sram[4]->out gvdd_mux_1level_tapbuf_size2[4] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****1***** -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -***** Signal mux_1level_tapbuf_size2[4]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[4]->in[0] mux_1level_tapbuf_size2[4]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[4]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[4]->in[1] mux_1level_tapbuf_size2[4]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[4] gvdd_mux_1level_tapbuf_size2[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[399] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[399] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[399] when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[399] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[399] when v(mux_1level_tapbuf_size2[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[399] trig v(mux_1level_tapbuf_size2[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[399] param='mux_1level_tapbuf_size2[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[4]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[4]_energy_per_cycle param='mux_1level_tapbuf_size2[4]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[399] param='mux_1level_tapbuf_size2[4]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[399] param='dynamic_power_sb_mux[0][0]_rrnode[399]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[399] avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_rise_sb_mux[0][0]_rrnode[399]' to='start_rise_sb_mux[0][0]_rrnode[399]+switch_rise_sb_mux[0][0]_rrnode[399]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[399] avg p(Vgvdd_mux_1level_tapbuf_size2[4]) from='start_fall_sb_mux[0][0]_rrnode[399]' to='start_fall_sb_mux[0][0]_rrnode[399]+switch_fall_sb_mux[0][0]_rrnode[399]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_sb_mux[0][0]_rrnode[399]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_sb_mux[0][0]_rrnode[399]' -***** Load for rr_node[399] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=8, type=5 ***** -Xchan_mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[15]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out mux_1level_tapbuf_size2[4]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[4]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to4] -+ param='sum_leakage_power_sb_mux[0to3]+leakage_sb_mux[0][0]_rrnode[399]' -.meas tran sum_energy_per_cycle_sb_mux[0to4] -+ param='sum_energy_per_cycle_sb_mux[0to3]+energy_per_cycle_sb_mux[0][0]_rrnode[399]' -Xmux_1level_tapbuf_size2[5] mux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->out sram[5]->outb sram[5]->out gvdd_mux_1level_tapbuf_size2[5] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[5], level=1, select_path_id=0. ***** -*****1***** -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -***** Signal mux_1level_tapbuf_size2[5]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[5]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[5] gvdd_mux_1level_tapbuf_size2[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[401] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[401] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[401] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[401] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[401] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[401] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[401] param='mux_1level_tapbuf_size2[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[5]_energy_per_cycle param='mux_1level_tapbuf_size2[5]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[401] param='mux_1level_tapbuf_size2[5]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[401] param='dynamic_power_sb_mux[0][0]_rrnode[401]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[401] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_rise_sb_mux[0][0]_rrnode[401]' to='start_rise_sb_mux[0][0]_rrnode[401]+switch_rise_sb_mux[0][0]_rrnode[401]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[401] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_fall_sb_mux[0][0]_rrnode[401]' to='start_fall_sb_mux[0][0]_rrnode[401]+switch_fall_sb_mux[0][0]_rrnode[401]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_sb_mux[0][0]_rrnode[401]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_sb_mux[0][0]_rrnode[401]' -***** Load for rr_node[401] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=10, type=5 ***** -Xchan_mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[20]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to5] -+ param='sum_leakage_power_sb_mux[0to4]+leakage_sb_mux[0][0]_rrnode[401]' -.meas tran sum_energy_per_cycle_sb_mux[0to5] -+ param='sum_energy_per_cycle_sb_mux[0to4]+energy_per_cycle_sb_mux[0][0]_rrnode[401]' -Xmux_1level_tapbuf_size2[6] mux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->out sram[6]->outb sram[6]->out gvdd_mux_1level_tapbuf_size2[6] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[6], level=1, select_path_id=0. ***** -*****1***** -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -***** Signal mux_1level_tapbuf_size2[6]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[6]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[6] gvdd_mux_1level_tapbuf_size2[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[403] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[403] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[403] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[403] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[403] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[403] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[403] param='mux_1level_tapbuf_size2[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[6]_energy_per_cycle param='mux_1level_tapbuf_size2[6]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[403] param='mux_1level_tapbuf_size2[6]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[403] param='dynamic_power_sb_mux[0][0]_rrnode[403]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[403] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_rise_sb_mux[0][0]_rrnode[403]' to='start_rise_sb_mux[0][0]_rrnode[403]+switch_rise_sb_mux[0][0]_rrnode[403]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[403] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_fall_sb_mux[0][0]_rrnode[403]' to='start_fall_sb_mux[0][0]_rrnode[403]+switch_fall_sb_mux[0][0]_rrnode[403]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_sb_mux[0][0]_rrnode[403]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_sb_mux[0][0]_rrnode[403]' -***** Load for rr_node[403] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=12, type=5 ***** -Xchan_mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[23]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to6] -+ param='sum_leakage_power_sb_mux[0to5]+leakage_sb_mux[0][0]_rrnode[403]' -.meas tran sum_energy_per_cycle_sb_mux[0to6] -+ param='sum_energy_per_cycle_sb_mux[0to5]+energy_per_cycle_sb_mux[0][0]_rrnode[403]' -Xmux_1level_tapbuf_size2[7] mux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->out sram[7]->outb sram[7]->out gvdd_mux_1level_tapbuf_size2[7] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[7], level=1, select_path_id=0. ***** -*****1***** -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -***** Signal mux_1level_tapbuf_size2[7]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[7]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[7] gvdd_mux_1level_tapbuf_size2[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[405] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[405] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[405] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[405] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[405] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[405] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[405] param='mux_1level_tapbuf_size2[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[7]_energy_per_cycle param='mux_1level_tapbuf_size2[7]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[405] param='mux_1level_tapbuf_size2[7]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[405] param='dynamic_power_sb_mux[0][0]_rrnode[405]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[405] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_rise_sb_mux[0][0]_rrnode[405]' to='start_rise_sb_mux[0][0]_rrnode[405]+switch_rise_sb_mux[0][0]_rrnode[405]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[405] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_fall_sb_mux[0][0]_rrnode[405]' to='start_fall_sb_mux[0][0]_rrnode[405]+switch_fall_sb_mux[0][0]_rrnode[405]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_sb_mux[0][0]_rrnode[405]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_sb_mux[0][0]_rrnode[405]' -***** Load for rr_node[405] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=14, type=5 ***** -Xchan_mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[27]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to7] -+ param='sum_leakage_power_sb_mux[0to6]+leakage_sb_mux[0][0]_rrnode[405]' -.meas tran sum_energy_per_cycle_sb_mux[0to7] -+ param='sum_energy_per_cycle_sb_mux[0to6]+energy_per_cycle_sb_mux[0][0]_rrnode[405]' -Xmux_1level_tapbuf_size2[8] mux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->out sram[8]->outb sram[8]->out gvdd_mux_1level_tapbuf_size2[8] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[8], level=1, select_path_id=0. ***** -*****1***** -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -***** Signal mux_1level_tapbuf_size2[8]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[8]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[8] gvdd_mux_1level_tapbuf_size2[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[407] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[407] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[407] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[407] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[407] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[407] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[407] param='mux_1level_tapbuf_size2[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[8]_energy_per_cycle param='mux_1level_tapbuf_size2[8]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[407] param='mux_1level_tapbuf_size2[8]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[407] param='dynamic_power_sb_mux[0][0]_rrnode[407]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[407] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_rise_sb_mux[0][0]_rrnode[407]' to='start_rise_sb_mux[0][0]_rrnode[407]+switch_rise_sb_mux[0][0]_rrnode[407]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[407] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_fall_sb_mux[0][0]_rrnode[407]' to='start_fall_sb_mux[0][0]_rrnode[407]+switch_fall_sb_mux[0][0]_rrnode[407]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_sb_mux[0][0]_rrnode[407]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_sb_mux[0][0]_rrnode[407]' -***** Load for rr_node[407] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=16, type=5 ***** -Xchan_mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[31]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to8] -+ param='sum_leakage_power_sb_mux[0to7]+leakage_sb_mux[0][0]_rrnode[407]' -.meas tran sum_energy_per_cycle_sb_mux[0to8] -+ param='sum_energy_per_cycle_sb_mux[0to7]+energy_per_cycle_sb_mux[0][0]_rrnode[407]' -Xmux_1level_tapbuf_size2[9] mux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->out sram[9]->outb sram[9]->out gvdd_mux_1level_tapbuf_size2[9] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[9], level=1, select_path_id=0. ***** -*****1***** -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -***** Signal mux_1level_tapbuf_size2[9]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[9]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[9] gvdd_mux_1level_tapbuf_size2[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[409] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[409] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[409] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[409] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[409] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[409] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[409] param='mux_1level_tapbuf_size2[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[9]_energy_per_cycle param='mux_1level_tapbuf_size2[9]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[409] param='mux_1level_tapbuf_size2[9]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[409] param='dynamic_power_sb_mux[0][0]_rrnode[409]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[409] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_rise_sb_mux[0][0]_rrnode[409]' to='start_rise_sb_mux[0][0]_rrnode[409]+switch_rise_sb_mux[0][0]_rrnode[409]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[409] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_fall_sb_mux[0][0]_rrnode[409]' to='start_fall_sb_mux[0][0]_rrnode[409]+switch_fall_sb_mux[0][0]_rrnode[409]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_sb_mux[0][0]_rrnode[409]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_sb_mux[0][0]_rrnode[409]' -***** Load for rr_node[409] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=18, type=5 ***** -Xchan_mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[35]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to9] -+ param='sum_leakage_power_sb_mux[0to8]+leakage_sb_mux[0][0]_rrnode[409]' -.meas tran sum_energy_per_cycle_sb_mux[0to9] -+ param='sum_energy_per_cycle_sb_mux[0to8]+energy_per_cycle_sb_mux[0][0]_rrnode[409]' -Xmux_1level_tapbuf_size2[10] mux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->out sram[10]->outb sram[10]->out gvdd_mux_1level_tapbuf_size2[10] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[10], level=1, select_path_id=0. ***** -*****1***** -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -***** Signal mux_1level_tapbuf_size2[10]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[10]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[10] gvdd_mux_1level_tapbuf_size2[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[411] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[411] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[411] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[411] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[411] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[411] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[411] param='mux_1level_tapbuf_size2[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[10]_energy_per_cycle param='mux_1level_tapbuf_size2[10]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[411] param='mux_1level_tapbuf_size2[10]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[411] param='dynamic_power_sb_mux[0][0]_rrnode[411]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[411] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_rise_sb_mux[0][0]_rrnode[411]' to='start_rise_sb_mux[0][0]_rrnode[411]+switch_rise_sb_mux[0][0]_rrnode[411]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[411] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_fall_sb_mux[0][0]_rrnode[411]' to='start_fall_sb_mux[0][0]_rrnode[411]+switch_fall_sb_mux[0][0]_rrnode[411]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_sb_mux[0][0]_rrnode[411]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_sb_mux[0][0]_rrnode[411]' -***** Load for rr_node[411] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=20, type=5 ***** -Xchan_mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[39]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to10] -+ param='sum_leakage_power_sb_mux[0to9]+leakage_sb_mux[0][0]_rrnode[411]' -.meas tran sum_energy_per_cycle_sb_mux[0to10] -+ param='sum_energy_per_cycle_sb_mux[0to9]+energy_per_cycle_sb_mux[0][0]_rrnode[411]' -Xmux_1level_tapbuf_size2[11] mux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->out sram[11]->outb sram[11]->out gvdd_mux_1level_tapbuf_size2[11] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[11], level=1, select_path_id=0. ***** -*****1***** -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_1level_tapbuf_size2[11]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[11]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[11] gvdd_mux_1level_tapbuf_size2[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[413] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[413] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[413] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[413] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[413] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[413] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[413] param='mux_1level_tapbuf_size2[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[11]_energy_per_cycle param='mux_1level_tapbuf_size2[11]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[413] param='mux_1level_tapbuf_size2[11]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[413] param='dynamic_power_sb_mux[0][0]_rrnode[413]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[413] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_rise_sb_mux[0][0]_rrnode[413]' to='start_rise_sb_mux[0][0]_rrnode[413]+switch_rise_sb_mux[0][0]_rrnode[413]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[413] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_fall_sb_mux[0][0]_rrnode[413]' to='start_fall_sb_mux[0][0]_rrnode[413]+switch_fall_sb_mux[0][0]_rrnode[413]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_sb_mux[0][0]_rrnode[413]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_sb_mux[0][0]_rrnode[413]' -***** Load for rr_node[413] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=22, type=5 ***** -Xchan_mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[42]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to11] -+ param='sum_leakage_power_sb_mux[0to10]+leakage_sb_mux[0][0]_rrnode[413]' -.meas tran sum_energy_per_cycle_sb_mux[0to11] -+ param='sum_energy_per_cycle_sb_mux[0to10]+energy_per_cycle_sb_mux[0][0]_rrnode[413]' -Xmux_1level_tapbuf_size2[12] mux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->out sram[12]->outb sram[12]->out gvdd_mux_1level_tapbuf_size2[12] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[12], level=1, select_path_id=0. ***** -*****1***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -***** Signal mux_1level_tapbuf_size2[12]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[12]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[12] gvdd_mux_1level_tapbuf_size2[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[415] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[415] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[415] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[415] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[415] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[415] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[415] param='mux_1level_tapbuf_size2[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[12]_energy_per_cycle param='mux_1level_tapbuf_size2[12]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[415] param='mux_1level_tapbuf_size2[12]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[415] param='dynamic_power_sb_mux[0][0]_rrnode[415]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[415] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_rise_sb_mux[0][0]_rrnode[415]' to='start_rise_sb_mux[0][0]_rrnode[415]+switch_rise_sb_mux[0][0]_rrnode[415]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[415] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_fall_sb_mux[0][0]_rrnode[415]' to='start_fall_sb_mux[0][0]_rrnode[415]+switch_fall_sb_mux[0][0]_rrnode[415]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_sb_mux[0][0]_rrnode[415]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_sb_mux[0][0]_rrnode[415]' -***** Load for rr_node[415] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=24, type=5 ***** -Xchan_mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[47]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to12] -+ param='sum_leakage_power_sb_mux[0to11]+leakage_sb_mux[0][0]_rrnode[415]' -.meas tran sum_energy_per_cycle_sb_mux[0to12] -+ param='sum_energy_per_cycle_sb_mux[0to11]+energy_per_cycle_sb_mux[0][0]_rrnode[415]' -Xmux_1level_tapbuf_size2[13] mux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->out sram[13]->outb sram[13]->out gvdd_mux_1level_tapbuf_size2[13] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[13], level=1, select_path_id=0. ***** -*****1***** -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -***** Signal mux_1level_tapbuf_size2[13]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[13]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[13] gvdd_mux_1level_tapbuf_size2[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[417] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[417] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[417] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[417] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[417] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[417] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[417] param='mux_1level_tapbuf_size2[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[13]_energy_per_cycle param='mux_1level_tapbuf_size2[13]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[417] param='mux_1level_tapbuf_size2[13]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[417] param='dynamic_power_sb_mux[0][0]_rrnode[417]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[417] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_rise_sb_mux[0][0]_rrnode[417]' to='start_rise_sb_mux[0][0]_rrnode[417]+switch_rise_sb_mux[0][0]_rrnode[417]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[417] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_fall_sb_mux[0][0]_rrnode[417]' to='start_fall_sb_mux[0][0]_rrnode[417]+switch_fall_sb_mux[0][0]_rrnode[417]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_sb_mux[0][0]_rrnode[417]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_sb_mux[0][0]_rrnode[417]' -***** Load for rr_node[417] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=26, type=5 ***** -Xchan_mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[51]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to13] -+ param='sum_leakage_power_sb_mux[0to12]+leakage_sb_mux[0][0]_rrnode[417]' -.meas tran sum_energy_per_cycle_sb_mux[0to13] -+ param='sum_energy_per_cycle_sb_mux[0to12]+energy_per_cycle_sb_mux[0][0]_rrnode[417]' -Xmux_1level_tapbuf_size2[14] mux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->out sram[14]->outb sram[14]->out gvdd_mux_1level_tapbuf_size2[14] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[14], level=1, select_path_id=0. ***** -*****1***** -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -***** Signal mux_1level_tapbuf_size2[14]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[14]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[14] gvdd_mux_1level_tapbuf_size2[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[419] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[419] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[419] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[419] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[419] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[419] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[419] param='mux_1level_tapbuf_size2[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[14]_energy_per_cycle param='mux_1level_tapbuf_size2[14]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[419] param='mux_1level_tapbuf_size2[14]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[419] param='dynamic_power_sb_mux[0][0]_rrnode[419]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[419] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_rise_sb_mux[0][0]_rrnode[419]' to='start_rise_sb_mux[0][0]_rrnode[419]+switch_rise_sb_mux[0][0]_rrnode[419]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[419] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_fall_sb_mux[0][0]_rrnode[419]' to='start_fall_sb_mux[0][0]_rrnode[419]+switch_fall_sb_mux[0][0]_rrnode[419]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_sb_mux[0][0]_rrnode[419]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_sb_mux[0][0]_rrnode[419]' -***** Load for rr_node[419] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=28, type=5 ***** -Xchan_mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[54]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to14] -+ param='sum_leakage_power_sb_mux[0to13]+leakage_sb_mux[0][0]_rrnode[419]' -.meas tran sum_energy_per_cycle_sb_mux[0to14] -+ param='sum_energy_per_cycle_sb_mux[0to13]+energy_per_cycle_sb_mux[0][0]_rrnode[419]' -Xmux_1level_tapbuf_size2[15] mux_1level_tapbuf_size2[15]->in[0] mux_1level_tapbuf_size2[15]->in[1] mux_1level_tapbuf_size2[15]->out sram[15]->outb sram[15]->out gvdd_mux_1level_tapbuf_size2[15] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[15], level=1, select_path_id=0. ***** -*****1***** -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_1level_tapbuf_size2[15]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[15]->in[0] mux_1level_tapbuf_size2[15]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[15]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[15]->in[1] mux_1level_tapbuf_size2[15]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[15] gvdd_mux_1level_tapbuf_size2[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[421] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[421] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[421] when v(mux_1level_tapbuf_size2[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[421] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[421] when v(mux_1level_tapbuf_size2[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[421] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[15]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[421] param='mux_1level_tapbuf_size2[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[15]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[15]_energy_per_cycle param='mux_1level_tapbuf_size2[15]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[421] param='mux_1level_tapbuf_size2[15]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[421] param='dynamic_power_sb_mux[0][0]_rrnode[421]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[421] avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='start_rise_sb_mux[0][0]_rrnode[421]' to='start_rise_sb_mux[0][0]_rrnode[421]+switch_rise_sb_mux[0][0]_rrnode[421]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[421] avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='start_fall_sb_mux[0][0]_rrnode[421]' to='start_fall_sb_mux[0][0]_rrnode[421]+switch_fall_sb_mux[0][0]_rrnode[421]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_sb_mux[0][0]_rrnode[421]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_sb_mux[0][0]_rrnode[421]' -***** Load for rr_node[421] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=30, type=5 ***** -Xchan_mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[58]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[60]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to15] -+ param='sum_leakage_power_sb_mux[0to14]+leakage_sb_mux[0][0]_rrnode[421]' -.meas tran sum_energy_per_cycle_sb_mux[0to15] -+ param='sum_energy_per_cycle_sb_mux[0to14]+energy_per_cycle_sb_mux[0][0]_rrnode[421]' -Xmux_1level_tapbuf_size2[16] mux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->out sram[16]->outb sram[16]->out gvdd_mux_1level_tapbuf_size2[16] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[16], level=1, select_path_id=0. ***** -*****1***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -***** Signal mux_1level_tapbuf_size2[16]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[16]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[16] gvdd_mux_1level_tapbuf_size2[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[423] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[423] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[423] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[423] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[423] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[423] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[423] param='mux_1level_tapbuf_size2[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[16]_energy_per_cycle param='mux_1level_tapbuf_size2[16]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[423] param='mux_1level_tapbuf_size2[16]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[423] param='dynamic_power_sb_mux[0][0]_rrnode[423]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[423] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_rise_sb_mux[0][0]_rrnode[423]' to='start_rise_sb_mux[0][0]_rrnode[423]+switch_rise_sb_mux[0][0]_rrnode[423]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[423] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_fall_sb_mux[0][0]_rrnode[423]' to='start_fall_sb_mux[0][0]_rrnode[423]+switch_fall_sb_mux[0][0]_rrnode[423]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_sb_mux[0][0]_rrnode[423]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_sb_mux[0][0]_rrnode[423]' -***** Load for rr_node[423] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=32, type=5 ***** -Xchan_mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[62]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to16] -+ param='sum_leakage_power_sb_mux[0to15]+leakage_sb_mux[0][0]_rrnode[423]' -.meas tran sum_energy_per_cycle_sb_mux[0to16] -+ param='sum_energy_per_cycle_sb_mux[0to15]+energy_per_cycle_sb_mux[0][0]_rrnode[423]' -Xmux_1level_tapbuf_size2[17] mux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->out sram[17]->outb sram[17]->out gvdd_mux_1level_tapbuf_size2[17] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[17], level=1, select_path_id=0. ***** -*****1***** -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -***** Signal mux_1level_tapbuf_size2[17]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[17]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[17] gvdd_mux_1level_tapbuf_size2[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[425] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[425] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[425] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[425] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[425] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[425] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[425] param='mux_1level_tapbuf_size2[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[17]_energy_per_cycle param='mux_1level_tapbuf_size2[17]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[425] param='mux_1level_tapbuf_size2[17]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[425] param='dynamic_power_sb_mux[0][0]_rrnode[425]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[425] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_rise_sb_mux[0][0]_rrnode[425]' to='start_rise_sb_mux[0][0]_rrnode[425]+switch_rise_sb_mux[0][0]_rrnode[425]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[425] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_fall_sb_mux[0][0]_rrnode[425]' to='start_fall_sb_mux[0][0]_rrnode[425]+switch_fall_sb_mux[0][0]_rrnode[425]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_sb_mux[0][0]_rrnode[425]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_sb_mux[0][0]_rrnode[425]' -***** Load for rr_node[425] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=34, type=5 ***** -Xchan_mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[66]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to17] -+ param='sum_leakage_power_sb_mux[0to16]+leakage_sb_mux[0][0]_rrnode[425]' -.meas tran sum_energy_per_cycle_sb_mux[0to17] -+ param='sum_energy_per_cycle_sb_mux[0to16]+energy_per_cycle_sb_mux[0][0]_rrnode[425]' -Xmux_1level_tapbuf_size2[18] mux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->out sram[18]->outb sram[18]->out gvdd_mux_1level_tapbuf_size2[18] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[18], level=1, select_path_id=0. ***** -*****1***** -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -***** Signal mux_1level_tapbuf_size2[18]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[18]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[18] gvdd_mux_1level_tapbuf_size2[18] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[427] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[427] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[427] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[427] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[427] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[427] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[427] param='mux_1level_tapbuf_size2[18]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[18]_energy_per_cycle param='mux_1level_tapbuf_size2[18]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[427] param='mux_1level_tapbuf_size2[18]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[427] param='dynamic_power_sb_mux[0][0]_rrnode[427]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[427] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_rise_sb_mux[0][0]_rrnode[427]' to='start_rise_sb_mux[0][0]_rrnode[427]+switch_rise_sb_mux[0][0]_rrnode[427]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[427] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_fall_sb_mux[0][0]_rrnode[427]' to='start_fall_sb_mux[0][0]_rrnode[427]+switch_fall_sb_mux[0][0]_rrnode[427]' -.meas tran sum_leakage_power_mux[0to18] -+ param='sum_leakage_power_mux[0to17]+leakage_sb_mux[0][0]_rrnode[427]' -.meas tran sum_energy_per_cycle_mux[0to18] -+ param='sum_energy_per_cycle_mux[0to17]+energy_per_cycle_sb_mux[0][0]_rrnode[427]' -***** Load for rr_node[427] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=36, type=5 ***** -Xchan_mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[70]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to18] -+ param='sum_leakage_power_sb_mux[0to17]+leakage_sb_mux[0][0]_rrnode[427]' -.meas tran sum_energy_per_cycle_sb_mux[0to18] -+ param='sum_energy_per_cycle_sb_mux[0to17]+energy_per_cycle_sb_mux[0][0]_rrnode[427]' -Xmux_1level_tapbuf_size2[19] mux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->out sram[19]->outb sram[19]->out gvdd_mux_1level_tapbuf_size2[19] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[19], level=1, select_path_id=0. ***** -*****1***** -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_1level_tapbuf_size2[19]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[19]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[19] gvdd_mux_1level_tapbuf_size2[19] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[429] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[429] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[429] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[429] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[429] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[429] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[429] param='mux_1level_tapbuf_size2[19]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[19]_energy_per_cycle param='mux_1level_tapbuf_size2[19]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[429] param='mux_1level_tapbuf_size2[19]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[429] param='dynamic_power_sb_mux[0][0]_rrnode[429]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[429] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_rise_sb_mux[0][0]_rrnode[429]' to='start_rise_sb_mux[0][0]_rrnode[429]+switch_rise_sb_mux[0][0]_rrnode[429]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[429] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_fall_sb_mux[0][0]_rrnode[429]' to='start_fall_sb_mux[0][0]_rrnode[429]+switch_fall_sb_mux[0][0]_rrnode[429]' -.meas tran sum_leakage_power_mux[0to19] -+ param='sum_leakage_power_mux[0to18]+leakage_sb_mux[0][0]_rrnode[429]' -.meas tran sum_energy_per_cycle_mux[0to19] -+ param='sum_energy_per_cycle_mux[0to18]+energy_per_cycle_sb_mux[0][0]_rrnode[429]' -***** Load for rr_node[429] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=38, type=5 ***** -Xchan_mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[74]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to19] -+ param='sum_leakage_power_sb_mux[0to18]+leakage_sb_mux[0][0]_rrnode[429]' -.meas tran sum_energy_per_cycle_sb_mux[0to19] -+ param='sum_energy_per_cycle_sb_mux[0to18]+energy_per_cycle_sb_mux[0][0]_rrnode[429]' -Xmux_1level_tapbuf_size2[20] mux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->out sram[20]->outb sram[20]->out gvdd_mux_1level_tapbuf_size2[20] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[20], level=1, select_path_id=0. ***** -*****1***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -***** Signal mux_1level_tapbuf_size2[20]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[20]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[20] gvdd_mux_1level_tapbuf_size2[20] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[431] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[431] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[431] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[431] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[431] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[431] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[431] param='mux_1level_tapbuf_size2[20]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[20]_energy_per_cycle param='mux_1level_tapbuf_size2[20]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[431] param='mux_1level_tapbuf_size2[20]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[431] param='dynamic_power_sb_mux[0][0]_rrnode[431]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[431] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_rise_sb_mux[0][0]_rrnode[431]' to='start_rise_sb_mux[0][0]_rrnode[431]+switch_rise_sb_mux[0][0]_rrnode[431]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[431] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_fall_sb_mux[0][0]_rrnode[431]' to='start_fall_sb_mux[0][0]_rrnode[431]+switch_fall_sb_mux[0][0]_rrnode[431]' -.meas tran sum_leakage_power_mux[0to20] -+ param='sum_leakage_power_mux[0to19]+leakage_sb_mux[0][0]_rrnode[431]' -.meas tran sum_energy_per_cycle_mux[0to20] -+ param='sum_energy_per_cycle_mux[0to19]+energy_per_cycle_sb_mux[0][0]_rrnode[431]' -***** Load for rr_node[431] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=40, type=5 ***** -Xchan_mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[78]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to20] -+ param='sum_leakage_power_sb_mux[0to19]+leakage_sb_mux[0][0]_rrnode[431]' -.meas tran sum_energy_per_cycle_sb_mux[0to20] -+ param='sum_energy_per_cycle_sb_mux[0to19]+energy_per_cycle_sb_mux[0][0]_rrnode[431]' -Xmux_1level_tapbuf_size2[21] mux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->out sram[21]->outb sram[21]->out gvdd_mux_1level_tapbuf_size2[21] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[21], level=1, select_path_id=0. ***** -*****1***** -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -***** Signal mux_1level_tapbuf_size2[21]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[21]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[21] gvdd_mux_1level_tapbuf_size2[21] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[433] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[433] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[433] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[433] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[433] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[433] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[433] param='mux_1level_tapbuf_size2[21]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[21]_energy_per_cycle param='mux_1level_tapbuf_size2[21]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[433] param='mux_1level_tapbuf_size2[21]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[433] param='dynamic_power_sb_mux[0][0]_rrnode[433]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[433] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_rise_sb_mux[0][0]_rrnode[433]' to='start_rise_sb_mux[0][0]_rrnode[433]+switch_rise_sb_mux[0][0]_rrnode[433]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[433] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_fall_sb_mux[0][0]_rrnode[433]' to='start_fall_sb_mux[0][0]_rrnode[433]+switch_fall_sb_mux[0][0]_rrnode[433]' -.meas tran sum_leakage_power_mux[0to21] -+ param='sum_leakage_power_mux[0to20]+leakage_sb_mux[0][0]_rrnode[433]' -.meas tran sum_energy_per_cycle_mux[0to21] -+ param='sum_energy_per_cycle_mux[0to20]+energy_per_cycle_sb_mux[0][0]_rrnode[433]' -***** Load for rr_node[433] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=42, type=5 ***** -Xchan_mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[81]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to21] -+ param='sum_leakage_power_sb_mux[0to20]+leakage_sb_mux[0][0]_rrnode[433]' -.meas tran sum_energy_per_cycle_sb_mux[0to21] -+ param='sum_energy_per_cycle_sb_mux[0to20]+energy_per_cycle_sb_mux[0][0]_rrnode[433]' -Xmux_1level_tapbuf_size2[22] mux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->out sram[22]->outb sram[22]->out gvdd_mux_1level_tapbuf_size2[22] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[22], level=1, select_path_id=0. ***** -*****1***** -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -***** Signal mux_1level_tapbuf_size2[22]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[22]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[22] gvdd_mux_1level_tapbuf_size2[22] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[435] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[435] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[435] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[435] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[435] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[435] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[435] param='mux_1level_tapbuf_size2[22]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[22]_energy_per_cycle param='mux_1level_tapbuf_size2[22]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[435] param='mux_1level_tapbuf_size2[22]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[435] param='dynamic_power_sb_mux[0][0]_rrnode[435]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[435] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_rise_sb_mux[0][0]_rrnode[435]' to='start_rise_sb_mux[0][0]_rrnode[435]+switch_rise_sb_mux[0][0]_rrnode[435]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[435] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_fall_sb_mux[0][0]_rrnode[435]' to='start_fall_sb_mux[0][0]_rrnode[435]+switch_fall_sb_mux[0][0]_rrnode[435]' -.meas tran sum_leakage_power_mux[0to22] -+ param='sum_leakage_power_mux[0to21]+leakage_sb_mux[0][0]_rrnode[435]' -.meas tran sum_energy_per_cycle_mux[0to22] -+ param='sum_energy_per_cycle_mux[0to21]+energy_per_cycle_sb_mux[0][0]_rrnode[435]' -***** Load for rr_node[435] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=44, type=5 ***** -Xchan_mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[85]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to22] -+ param='sum_leakage_power_sb_mux[0to21]+leakage_sb_mux[0][0]_rrnode[435]' -.meas tran sum_energy_per_cycle_sb_mux[0to22] -+ param='sum_energy_per_cycle_sb_mux[0to21]+energy_per_cycle_sb_mux[0][0]_rrnode[435]' -Xmux_1level_tapbuf_size2[23] mux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->out sram[23]->outb sram[23]->out gvdd_mux_1level_tapbuf_size2[23] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[23], level=1, select_path_id=0. ***** -*****1***** -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_1level_tapbuf_size2[23]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[23]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[23] gvdd_mux_1level_tapbuf_size2[23] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[437] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[437] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[437] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[437] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[437] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[437] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[437] param='mux_1level_tapbuf_size2[23]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[23]_energy_per_cycle param='mux_1level_tapbuf_size2[23]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[437] param='mux_1level_tapbuf_size2[23]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[437] param='dynamic_power_sb_mux[0][0]_rrnode[437]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[437] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_rise_sb_mux[0][0]_rrnode[437]' to='start_rise_sb_mux[0][0]_rrnode[437]+switch_rise_sb_mux[0][0]_rrnode[437]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[437] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_fall_sb_mux[0][0]_rrnode[437]' to='start_fall_sb_mux[0][0]_rrnode[437]+switch_fall_sb_mux[0][0]_rrnode[437]' -.meas tran sum_leakage_power_mux[0to23] -+ param='sum_leakage_power_mux[0to22]+leakage_sb_mux[0][0]_rrnode[437]' -.meas tran sum_energy_per_cycle_mux[0to23] -+ param='sum_energy_per_cycle_mux[0to22]+energy_per_cycle_sb_mux[0][0]_rrnode[437]' -***** Load for rr_node[437] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=46, type=5 ***** -Xchan_mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[90]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to23] -+ param='sum_leakage_power_sb_mux[0to22]+leakage_sb_mux[0][0]_rrnode[437]' -.meas tran sum_energy_per_cycle_sb_mux[0to23] -+ param='sum_energy_per_cycle_sb_mux[0to22]+energy_per_cycle_sb_mux[0][0]_rrnode[437]' -Xmux_1level_tapbuf_size2[24] mux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->out sram[24]->outb sram[24]->out gvdd_mux_1level_tapbuf_size2[24] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[24], level=1, select_path_id=0. ***** -*****1***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -***** Signal mux_1level_tapbuf_size2[24]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[24]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[24] gvdd_mux_1level_tapbuf_size2[24] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[439] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[439] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[439] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[439] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[439] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[439] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[439] param='mux_1level_tapbuf_size2[24]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[24]_energy_per_cycle param='mux_1level_tapbuf_size2[24]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[439] param='mux_1level_tapbuf_size2[24]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[439] param='dynamic_power_sb_mux[0][0]_rrnode[439]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[439] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_rise_sb_mux[0][0]_rrnode[439]' to='start_rise_sb_mux[0][0]_rrnode[439]+switch_rise_sb_mux[0][0]_rrnode[439]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[439] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_fall_sb_mux[0][0]_rrnode[439]' to='start_fall_sb_mux[0][0]_rrnode[439]+switch_fall_sb_mux[0][0]_rrnode[439]' -.meas tran sum_leakage_power_mux[0to24] -+ param='sum_leakage_power_mux[0to23]+leakage_sb_mux[0][0]_rrnode[439]' -.meas tran sum_energy_per_cycle_mux[0to24] -+ param='sum_energy_per_cycle_mux[0to23]+energy_per_cycle_sb_mux[0][0]_rrnode[439]' -***** Load for rr_node[439] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=48, type=5 ***** -Xchan_mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[93]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to24] -+ param='sum_leakage_power_sb_mux[0to23]+leakage_sb_mux[0][0]_rrnode[439]' -.meas tran sum_energy_per_cycle_sb_mux[0to24] -+ param='sum_energy_per_cycle_sb_mux[0to23]+energy_per_cycle_sb_mux[0][0]_rrnode[439]' -Xmux_1level_tapbuf_size2[25] mux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->out sram[25]->outb sram[25]->out gvdd_mux_1level_tapbuf_size2[25] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[25], level=1, select_path_id=0. ***** -*****1***** -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -***** Signal mux_1level_tapbuf_size2[25]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[25]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[25] gvdd_mux_1level_tapbuf_size2[25] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[441] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[441] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[441] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[441] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[441] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[441] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[441] param='mux_1level_tapbuf_size2[25]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[25]_energy_per_cycle param='mux_1level_tapbuf_size2[25]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[441] param='mux_1level_tapbuf_size2[25]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[441] param='dynamic_power_sb_mux[0][0]_rrnode[441]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[441] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_rise_sb_mux[0][0]_rrnode[441]' to='start_rise_sb_mux[0][0]_rrnode[441]+switch_rise_sb_mux[0][0]_rrnode[441]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[441] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_fall_sb_mux[0][0]_rrnode[441]' to='start_fall_sb_mux[0][0]_rrnode[441]+switch_fall_sb_mux[0][0]_rrnode[441]' -.meas tran sum_leakage_power_mux[0to25] -+ param='sum_leakage_power_mux[0to24]+leakage_sb_mux[0][0]_rrnode[441]' -.meas tran sum_energy_per_cycle_mux[0to25] -+ param='sum_energy_per_cycle_mux[0to24]+energy_per_cycle_sb_mux[0][0]_rrnode[441]' -***** Load for rr_node[441] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=50, type=5 ***** -Xchan_mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[97]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to25] -+ param='sum_leakage_power_sb_mux[0to24]+leakage_sb_mux[0][0]_rrnode[441]' -.meas tran sum_energy_per_cycle_sb_mux[0to25] -+ param='sum_energy_per_cycle_sb_mux[0to24]+energy_per_cycle_sb_mux[0][0]_rrnode[441]' -Xmux_1level_tapbuf_size2[26] mux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->out sram[26]->outb sram[26]->out gvdd_mux_1level_tapbuf_size2[26] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[26], level=1, select_path_id=0. ***** -*****1***** -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -***** Signal mux_1level_tapbuf_size2[26]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[26]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[26] gvdd_mux_1level_tapbuf_size2[26] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[443] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[443] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[443] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[443] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[443] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[443] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[443] param='mux_1level_tapbuf_size2[26]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[26]_energy_per_cycle param='mux_1level_tapbuf_size2[26]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[443] param='mux_1level_tapbuf_size2[26]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[443] param='dynamic_power_sb_mux[0][0]_rrnode[443]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[443] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_rise_sb_mux[0][0]_rrnode[443]' to='start_rise_sb_mux[0][0]_rrnode[443]+switch_rise_sb_mux[0][0]_rrnode[443]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[443] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_fall_sb_mux[0][0]_rrnode[443]' to='start_fall_sb_mux[0][0]_rrnode[443]+switch_fall_sb_mux[0][0]_rrnode[443]' -.meas tran sum_leakage_power_mux[0to26] -+ param='sum_leakage_power_mux[0to25]+leakage_sb_mux[0][0]_rrnode[443]' -.meas tran sum_energy_per_cycle_mux[0to26] -+ param='sum_energy_per_cycle_mux[0to25]+energy_per_cycle_sb_mux[0][0]_rrnode[443]' -***** Load for rr_node[443] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=52, type=5 ***** -Xchan_mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[101]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to26] -+ param='sum_leakage_power_sb_mux[0to25]+leakage_sb_mux[0][0]_rrnode[443]' -.meas tran sum_energy_per_cycle_sb_mux[0to26] -+ param='sum_energy_per_cycle_sb_mux[0to25]+energy_per_cycle_sb_mux[0][0]_rrnode[443]' -Xmux_1level_tapbuf_size2[27] mux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->out sram[27]->outb sram[27]->out gvdd_mux_1level_tapbuf_size2[27] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[27], level=1, select_path_id=0. ***** -*****1***** -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_1level_tapbuf_size2[27]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[27]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[27] gvdd_mux_1level_tapbuf_size2[27] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[445] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[445] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[445] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[445] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[445] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[445] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[445] param='mux_1level_tapbuf_size2[27]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[27]_energy_per_cycle param='mux_1level_tapbuf_size2[27]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[445] param='mux_1level_tapbuf_size2[27]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[445] param='dynamic_power_sb_mux[0][0]_rrnode[445]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[445] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_rise_sb_mux[0][0]_rrnode[445]' to='start_rise_sb_mux[0][0]_rrnode[445]+switch_rise_sb_mux[0][0]_rrnode[445]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[445] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_fall_sb_mux[0][0]_rrnode[445]' to='start_fall_sb_mux[0][0]_rrnode[445]+switch_fall_sb_mux[0][0]_rrnode[445]' -.meas tran sum_leakage_power_mux[0to27] -+ param='sum_leakage_power_mux[0to26]+leakage_sb_mux[0][0]_rrnode[445]' -.meas tran sum_energy_per_cycle_mux[0to27] -+ param='sum_energy_per_cycle_mux[0to26]+energy_per_cycle_sb_mux[0][0]_rrnode[445]' -***** Load for rr_node[445] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=54, type=5 ***** -Xchan_mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[105]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to27] -+ param='sum_leakage_power_sb_mux[0to26]+leakage_sb_mux[0][0]_rrnode[445]' -.meas tran sum_energy_per_cycle_sb_mux[0to27] -+ param='sum_energy_per_cycle_sb_mux[0to26]+energy_per_cycle_sb_mux[0][0]_rrnode[445]' -Xmux_1level_tapbuf_size2[28] mux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->out sram[28]->outb sram[28]->out gvdd_mux_1level_tapbuf_size2[28] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[28], level=1, select_path_id=0. ***** -*****1***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -***** Signal mux_1level_tapbuf_size2[28]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[28]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[28] gvdd_mux_1level_tapbuf_size2[28] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[447] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[447] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[447] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[447] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[447] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[447] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[447] param='mux_1level_tapbuf_size2[28]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[28]_energy_per_cycle param='mux_1level_tapbuf_size2[28]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[447] param='mux_1level_tapbuf_size2[28]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[447] param='dynamic_power_sb_mux[0][0]_rrnode[447]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[447] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_rise_sb_mux[0][0]_rrnode[447]' to='start_rise_sb_mux[0][0]_rrnode[447]+switch_rise_sb_mux[0][0]_rrnode[447]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[447] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_fall_sb_mux[0][0]_rrnode[447]' to='start_fall_sb_mux[0][0]_rrnode[447]+switch_fall_sb_mux[0][0]_rrnode[447]' -.meas tran sum_leakage_power_mux[0to28] -+ param='sum_leakage_power_mux[0to27]+leakage_sb_mux[0][0]_rrnode[447]' -.meas tran sum_energy_per_cycle_mux[0to28] -+ param='sum_energy_per_cycle_mux[0to27]+energy_per_cycle_sb_mux[0][0]_rrnode[447]' -***** Load for rr_node[447] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=56, type=5 ***** -Xchan_mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[109]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to28] -+ param='sum_leakage_power_sb_mux[0to27]+leakage_sb_mux[0][0]_rrnode[447]' -.meas tran sum_energy_per_cycle_sb_mux[0to28] -+ param='sum_energy_per_cycle_sb_mux[0to27]+energy_per_cycle_sb_mux[0][0]_rrnode[447]' -Xmux_1level_tapbuf_size2[29] mux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->out sram[29]->outb sram[29]->out gvdd_mux_1level_tapbuf_size2[29] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[29], level=1, select_path_id=0. ***** -*****1***** -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -***** Signal mux_1level_tapbuf_size2[29]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[29]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[29] gvdd_mux_1level_tapbuf_size2[29] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[449] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[449] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[449] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[449] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[449] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[449] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[449] param='mux_1level_tapbuf_size2[29]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[29]_energy_per_cycle param='mux_1level_tapbuf_size2[29]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[449] param='mux_1level_tapbuf_size2[29]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[449] param='dynamic_power_sb_mux[0][0]_rrnode[449]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[449] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_rise_sb_mux[0][0]_rrnode[449]' to='start_rise_sb_mux[0][0]_rrnode[449]+switch_rise_sb_mux[0][0]_rrnode[449]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[449] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_fall_sb_mux[0][0]_rrnode[449]' to='start_fall_sb_mux[0][0]_rrnode[449]+switch_fall_sb_mux[0][0]_rrnode[449]' -.meas tran sum_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to28]+leakage_sb_mux[0][0]_rrnode[449]' -.meas tran sum_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to28]+energy_per_cycle_sb_mux[0][0]_rrnode[449]' -***** Load for rr_node[449] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=58, type=5 ***** -Xchan_mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[112]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to29] -+ param='sum_leakage_power_sb_mux[0to28]+leakage_sb_mux[0][0]_rrnode[449]' -.meas tran sum_energy_per_cycle_sb_mux[0to29] -+ param='sum_energy_per_cycle_sb_mux[0to28]+energy_per_cycle_sb_mux[0][0]_rrnode[449]' -Xmux_1level_tapbuf_size2[30] mux_1level_tapbuf_size2[30]->in[0] mux_1level_tapbuf_size2[30]->in[1] mux_1level_tapbuf_size2[30]->out sram[30]->outb sram[30]->out gvdd_mux_1level_tapbuf_size2[30] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[30], level=1, select_path_id=0. ***** -*****1***** -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -***** Signal mux_1level_tapbuf_size2[30]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[30]->in[0] mux_1level_tapbuf_size2[30]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[30]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[30]->in[1] mux_1level_tapbuf_size2[30]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[30] gvdd_mux_1level_tapbuf_size2[30] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[451] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[451] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[451] when v(mux_1level_tapbuf_size2[30]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[451] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[451] when v(mux_1level_tapbuf_size2[30]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[451] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[30]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[451] param='mux_1level_tapbuf_size2[30]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[30]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[30]_energy_per_cycle param='mux_1level_tapbuf_size2[30]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[451] param='mux_1level_tapbuf_size2[30]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[451] param='dynamic_power_sb_mux[0][0]_rrnode[451]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[451] avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='start_rise_sb_mux[0][0]_rrnode[451]' to='start_rise_sb_mux[0][0]_rrnode[451]+switch_rise_sb_mux[0][0]_rrnode[451]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[451] avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='start_fall_sb_mux[0][0]_rrnode[451]' to='start_fall_sb_mux[0][0]_rrnode[451]+switch_fall_sb_mux[0][0]_rrnode[451]' -.meas tran sum_leakage_power_mux[0to30] -+ param='sum_leakage_power_mux[0to29]+leakage_sb_mux[0][0]_rrnode[451]' -.meas tran sum_energy_per_cycle_mux[0to30] -+ param='sum_energy_per_cycle_mux[0to29]+energy_per_cycle_sb_mux[0][0]_rrnode[451]' -***** Load for rr_node[451] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=60, type=5 ***** -Xchan_mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[117]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to30] -+ param='sum_leakage_power_sb_mux[0to29]+leakage_sb_mux[0][0]_rrnode[451]' -.meas tran sum_energy_per_cycle_sb_mux[0to30] -+ param='sum_energy_per_cycle_sb_mux[0to29]+energy_per_cycle_sb_mux[0][0]_rrnode[451]' -Xmux_1level_tapbuf_size2[31] mux_1level_tapbuf_size2[31]->in[0] mux_1level_tapbuf_size2[31]->in[1] mux_1level_tapbuf_size2[31]->out sram[31]->outb sram[31]->out gvdd_mux_1level_tapbuf_size2[31] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[31], level=1, select_path_id=0. ***** -*****1***** -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_1level_tapbuf_size2[31]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[31]->in[0] mux_1level_tapbuf_size2[31]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[31]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[31]->in[1] mux_1level_tapbuf_size2[31]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[31] gvdd_mux_1level_tapbuf_size2[31] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[453] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[453] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[453] when v(mux_1level_tapbuf_size2[31]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[453] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[453] when v(mux_1level_tapbuf_size2[31]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[453] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[31]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[453] param='mux_1level_tapbuf_size2[31]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[31]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[31]_energy_per_cycle param='mux_1level_tapbuf_size2[31]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[453] param='mux_1level_tapbuf_size2[31]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[453] param='dynamic_power_sb_mux[0][0]_rrnode[453]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[453] avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='start_rise_sb_mux[0][0]_rrnode[453]' to='start_rise_sb_mux[0][0]_rrnode[453]+switch_rise_sb_mux[0][0]_rrnode[453]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[453] avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='start_fall_sb_mux[0][0]_rrnode[453]' to='start_fall_sb_mux[0][0]_rrnode[453]+switch_fall_sb_mux[0][0]_rrnode[453]' -.meas tran sum_leakage_power_mux[0to31] -+ param='sum_leakage_power_mux[0to30]+leakage_sb_mux[0][0]_rrnode[453]' -.meas tran sum_energy_per_cycle_mux[0to31] -+ param='sum_energy_per_cycle_mux[0to30]+energy_per_cycle_sb_mux[0][0]_rrnode[453]' -***** Load for rr_node[453] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=62, type=5 ***** -Xchan_mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[120]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to31] -+ param='sum_leakage_power_sb_mux[0to30]+leakage_sb_mux[0][0]_rrnode[453]' -.meas tran sum_energy_per_cycle_sb_mux[0to31] -+ param='sum_energy_per_cycle_sb_mux[0to30]+energy_per_cycle_sb_mux[0][0]_rrnode[453]' -Xmux_1level_tapbuf_size2[32] mux_1level_tapbuf_size2[32]->in[0] mux_1level_tapbuf_size2[32]->in[1] mux_1level_tapbuf_size2[32]->out sram[32]->outb sram[32]->out gvdd_mux_1level_tapbuf_size2[32] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[32], level=1, select_path_id=0. ***** -*****1***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -***** Signal mux_1level_tapbuf_size2[32]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[32]->in[0] mux_1level_tapbuf_size2[32]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[32]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[32]->in[1] mux_1level_tapbuf_size2[32]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[32] gvdd_mux_1level_tapbuf_size2[32] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[455] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[455] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[455] when v(mux_1level_tapbuf_size2[32]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[455] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[455] when v(mux_1level_tapbuf_size2[32]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[455] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[32]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[455] param='mux_1level_tapbuf_size2[32]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[32]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[32]_energy_per_cycle param='mux_1level_tapbuf_size2[32]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[455] param='mux_1level_tapbuf_size2[32]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[455] param='dynamic_power_sb_mux[0][0]_rrnode[455]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[455] avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='start_rise_sb_mux[0][0]_rrnode[455]' to='start_rise_sb_mux[0][0]_rrnode[455]+switch_rise_sb_mux[0][0]_rrnode[455]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[455] avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='start_fall_sb_mux[0][0]_rrnode[455]' to='start_fall_sb_mux[0][0]_rrnode[455]+switch_fall_sb_mux[0][0]_rrnode[455]' -.meas tran sum_leakage_power_mux[0to32] -+ param='sum_leakage_power_mux[0to31]+leakage_sb_mux[0][0]_rrnode[455]' -.meas tran sum_energy_per_cycle_mux[0to32] -+ param='sum_energy_per_cycle_mux[0to31]+energy_per_cycle_sb_mux[0][0]_rrnode[455]' -***** Load for rr_node[455] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=64, type=5 ***** -Xchan_mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[124]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[125]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to32] -+ param='sum_leakage_power_sb_mux[0to31]+leakage_sb_mux[0][0]_rrnode[455]' -.meas tran sum_energy_per_cycle_sb_mux[0to32] -+ param='sum_energy_per_cycle_sb_mux[0to31]+energy_per_cycle_sb_mux[0][0]_rrnode[455]' -Xmux_1level_tapbuf_size2[33] mux_1level_tapbuf_size2[33]->in[0] mux_1level_tapbuf_size2[33]->in[1] mux_1level_tapbuf_size2[33]->out sram[33]->outb sram[33]->out gvdd_mux_1level_tapbuf_size2[33] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[33], level=1, select_path_id=0. ***** -*****1***** -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -***** Signal mux_1level_tapbuf_size2[33]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[33]->in[0] mux_1level_tapbuf_size2[33]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[33]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[33]->in[1] mux_1level_tapbuf_size2[33]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[33] gvdd_mux_1level_tapbuf_size2[33] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[457] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[457] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[457] when v(mux_1level_tapbuf_size2[33]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[457] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[457] when v(mux_1level_tapbuf_size2[33]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[457] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[33]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[457] param='mux_1level_tapbuf_size2[33]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[33]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[33]_energy_per_cycle param='mux_1level_tapbuf_size2[33]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[457] param='mux_1level_tapbuf_size2[33]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[457] param='dynamic_power_sb_mux[0][0]_rrnode[457]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[457] avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='start_rise_sb_mux[0][0]_rrnode[457]' to='start_rise_sb_mux[0][0]_rrnode[457]+switch_rise_sb_mux[0][0]_rrnode[457]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[457] avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='start_fall_sb_mux[0][0]_rrnode[457]' to='start_fall_sb_mux[0][0]_rrnode[457]+switch_fall_sb_mux[0][0]_rrnode[457]' -.meas tran sum_leakage_power_mux[0to33] -+ param='sum_leakage_power_mux[0to32]+leakage_sb_mux[0][0]_rrnode[457]' -.meas tran sum_energy_per_cycle_mux[0to33] -+ param='sum_energy_per_cycle_mux[0to32]+energy_per_cycle_sb_mux[0][0]_rrnode[457]' -***** Load for rr_node[457] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=66, type=5 ***** -Xchan_mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[128]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[130]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to33] -+ param='sum_leakage_power_sb_mux[0to32]+leakage_sb_mux[0][0]_rrnode[457]' -.meas tran sum_energy_per_cycle_sb_mux[0to33] -+ param='sum_energy_per_cycle_sb_mux[0to32]+energy_per_cycle_sb_mux[0][0]_rrnode[457]' -Xmux_1level_tapbuf_size2[34] mux_1level_tapbuf_size2[34]->in[0] mux_1level_tapbuf_size2[34]->in[1] mux_1level_tapbuf_size2[34]->out sram[34]->outb sram[34]->out gvdd_mux_1level_tapbuf_size2[34] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[34], level=1, select_path_id=0. ***** -*****1***** -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -***** Signal mux_1level_tapbuf_size2[34]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[34]->in[0] mux_1level_tapbuf_size2[34]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[34]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[34]->in[1] mux_1level_tapbuf_size2[34]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[34] gvdd_mux_1level_tapbuf_size2[34] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[459] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[459] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[459] when v(mux_1level_tapbuf_size2[34]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[459] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[459] when v(mux_1level_tapbuf_size2[34]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[459] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[34]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[459] param='mux_1level_tapbuf_size2[34]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[34]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[34]_energy_per_cycle param='mux_1level_tapbuf_size2[34]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[459] param='mux_1level_tapbuf_size2[34]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[459] param='dynamic_power_sb_mux[0][0]_rrnode[459]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[459] avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='start_rise_sb_mux[0][0]_rrnode[459]' to='start_rise_sb_mux[0][0]_rrnode[459]+switch_rise_sb_mux[0][0]_rrnode[459]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[459] avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='start_fall_sb_mux[0][0]_rrnode[459]' to='start_fall_sb_mux[0][0]_rrnode[459]+switch_fall_sb_mux[0][0]_rrnode[459]' -.meas tran sum_leakage_power_mux[0to34] -+ param='sum_leakage_power_mux[0to33]+leakage_sb_mux[0][0]_rrnode[459]' -.meas tran sum_energy_per_cycle_mux[0to34] -+ param='sum_energy_per_cycle_mux[0to33]+energy_per_cycle_sb_mux[0][0]_rrnode[459]' -***** Load for rr_node[459] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=68, type=5 ***** -Xchan_mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[132]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to34] -+ param='sum_leakage_power_sb_mux[0to33]+leakage_sb_mux[0][0]_rrnode[459]' -.meas tran sum_energy_per_cycle_sb_mux[0to34] -+ param='sum_energy_per_cycle_sb_mux[0to33]+energy_per_cycle_sb_mux[0][0]_rrnode[459]' -Xmux_1level_tapbuf_size2[35] mux_1level_tapbuf_size2[35]->in[0] mux_1level_tapbuf_size2[35]->in[1] mux_1level_tapbuf_size2[35]->out sram[35]->outb sram[35]->out gvdd_mux_1level_tapbuf_size2[35] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[35], level=1, select_path_id=0. ***** -*****1***** -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -***** Signal mux_1level_tapbuf_size2[35]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[35]->in[0] mux_1level_tapbuf_size2[35]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[35]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[35]->in[1] mux_1level_tapbuf_size2[35]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[35] gvdd_mux_1level_tapbuf_size2[35] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[461] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[461] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[461] when v(mux_1level_tapbuf_size2[35]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[461] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[461] when v(mux_1level_tapbuf_size2[35]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[461] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[35]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[461] param='mux_1level_tapbuf_size2[35]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[35]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[35]_energy_per_cycle param='mux_1level_tapbuf_size2[35]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[461] param='mux_1level_tapbuf_size2[35]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[461] param='dynamic_power_sb_mux[0][0]_rrnode[461]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[461] avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='start_rise_sb_mux[0][0]_rrnode[461]' to='start_rise_sb_mux[0][0]_rrnode[461]+switch_rise_sb_mux[0][0]_rrnode[461]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[461] avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='start_fall_sb_mux[0][0]_rrnode[461]' to='start_fall_sb_mux[0][0]_rrnode[461]+switch_fall_sb_mux[0][0]_rrnode[461]' -.meas tran sum_leakage_power_mux[0to35] -+ param='sum_leakage_power_mux[0to34]+leakage_sb_mux[0][0]_rrnode[461]' -.meas tran sum_energy_per_cycle_mux[0to35] -+ param='sum_energy_per_cycle_mux[0to34]+energy_per_cycle_sb_mux[0][0]_rrnode[461]' -***** Load for rr_node[461] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=70, type=5 ***** -Xchan_mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[136]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to35] -+ param='sum_leakage_power_sb_mux[0to34]+leakage_sb_mux[0][0]_rrnode[461]' -.meas tran sum_energy_per_cycle_sb_mux[0to35] -+ param='sum_energy_per_cycle_sb_mux[0to34]+energy_per_cycle_sb_mux[0][0]_rrnode[461]' -Xmux_1level_tapbuf_size2[36] mux_1level_tapbuf_size2[36]->in[0] mux_1level_tapbuf_size2[36]->in[1] mux_1level_tapbuf_size2[36]->out sram[36]->outb sram[36]->out gvdd_mux_1level_tapbuf_size2[36] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[36], level=1, select_path_id=0. ***** -*****1***** -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -***** Signal mux_1level_tapbuf_size2[36]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[36]->in[0] mux_1level_tapbuf_size2[36]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[36]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[36]->in[1] mux_1level_tapbuf_size2[36]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[36] gvdd_mux_1level_tapbuf_size2[36] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[463] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[463] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[463] when v(mux_1level_tapbuf_size2[36]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[463] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[463] when v(mux_1level_tapbuf_size2[36]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[463] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[36]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[463] param='mux_1level_tapbuf_size2[36]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[36]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[36]_energy_per_cycle param='mux_1level_tapbuf_size2[36]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[463] param='mux_1level_tapbuf_size2[36]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[463] param='dynamic_power_sb_mux[0][0]_rrnode[463]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[463] avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='start_rise_sb_mux[0][0]_rrnode[463]' to='start_rise_sb_mux[0][0]_rrnode[463]+switch_rise_sb_mux[0][0]_rrnode[463]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[463] avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='start_fall_sb_mux[0][0]_rrnode[463]' to='start_fall_sb_mux[0][0]_rrnode[463]+switch_fall_sb_mux[0][0]_rrnode[463]' -.meas tran sum_leakage_power_mux[0to36] -+ param='sum_leakage_power_mux[0to35]+leakage_sb_mux[0][0]_rrnode[463]' -.meas tran sum_energy_per_cycle_mux[0to36] -+ param='sum_energy_per_cycle_mux[0to35]+energy_per_cycle_sb_mux[0][0]_rrnode[463]' -***** Load for rr_node[463] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=72, type=5 ***** -Xchan_mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[139]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to36] -+ param='sum_leakage_power_sb_mux[0to35]+leakage_sb_mux[0][0]_rrnode[463]' -.meas tran sum_energy_per_cycle_sb_mux[0to36] -+ param='sum_energy_per_cycle_sb_mux[0to35]+energy_per_cycle_sb_mux[0][0]_rrnode[463]' -Xmux_1level_tapbuf_size2[37] mux_1level_tapbuf_size2[37]->in[0] mux_1level_tapbuf_size2[37]->in[1] mux_1level_tapbuf_size2[37]->out sram[37]->outb sram[37]->out gvdd_mux_1level_tapbuf_size2[37] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[37], level=1, select_path_id=0. ***** -*****1***** -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -***** Signal mux_1level_tapbuf_size2[37]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[37]->in[0] mux_1level_tapbuf_size2[37]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[37]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[37]->in[1] mux_1level_tapbuf_size2[37]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[37] gvdd_mux_1level_tapbuf_size2[37] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[465] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[465] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[465] when v(mux_1level_tapbuf_size2[37]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[465] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[465] when v(mux_1level_tapbuf_size2[37]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[465] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[37]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[465] param='mux_1level_tapbuf_size2[37]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[37]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[37]_energy_per_cycle param='mux_1level_tapbuf_size2[37]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[465] param='mux_1level_tapbuf_size2[37]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[465] param='dynamic_power_sb_mux[0][0]_rrnode[465]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[465] avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='start_rise_sb_mux[0][0]_rrnode[465]' to='start_rise_sb_mux[0][0]_rrnode[465]+switch_rise_sb_mux[0][0]_rrnode[465]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[465] avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='start_fall_sb_mux[0][0]_rrnode[465]' to='start_fall_sb_mux[0][0]_rrnode[465]+switch_fall_sb_mux[0][0]_rrnode[465]' -.meas tran sum_leakage_power_mux[0to37] -+ param='sum_leakage_power_mux[0to36]+leakage_sb_mux[0][0]_rrnode[465]' -.meas tran sum_energy_per_cycle_mux[0to37] -+ param='sum_energy_per_cycle_mux[0to36]+energy_per_cycle_sb_mux[0][0]_rrnode[465]' -***** Load for rr_node[465] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=74, type=5 ***** -Xchan_mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[144]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to37] -+ param='sum_leakage_power_sb_mux[0to36]+leakage_sb_mux[0][0]_rrnode[465]' -.meas tran sum_energy_per_cycle_sb_mux[0to37] -+ param='sum_energy_per_cycle_sb_mux[0to36]+energy_per_cycle_sb_mux[0][0]_rrnode[465]' -Xmux_1level_tapbuf_size2[38] mux_1level_tapbuf_size2[38]->in[0] mux_1level_tapbuf_size2[38]->in[1] mux_1level_tapbuf_size2[38]->out sram[38]->out sram[38]->outb gvdd_mux_1level_tapbuf_size2[38] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[38], level=1, select_path_id=1. ***** -*****0***** -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -***** Signal mux_1level_tapbuf_size2[38]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[38]->in[0] mux_1level_tapbuf_size2[38]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[38]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[38]->in[1] mux_1level_tapbuf_size2[38]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[38] gvdd_mux_1level_tapbuf_size2[38] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[467] trig v(mux_1level_tapbuf_size2[38]->in[1]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[467] trig v(mux_1level_tapbuf_size2[38]->in[1]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[467] when v(mux_1level_tapbuf_size2[38]->in[1])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[467] trig v(mux_1level_tapbuf_size2[38]->in[1]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[467] when v(mux_1level_tapbuf_size2[38]->in[1])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[467] trig v(mux_1level_tapbuf_size2[38]->in[1]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[38]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[467] param='mux_1level_tapbuf_size2[38]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[38]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[38]_energy_per_cycle param='mux_1level_tapbuf_size2[38]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[467] param='mux_1level_tapbuf_size2[38]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[467] param='dynamic_power_sb_mux[0][0]_rrnode[467]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[467] avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='start_rise_sb_mux[0][0]_rrnode[467]' to='start_rise_sb_mux[0][0]_rrnode[467]+switch_rise_sb_mux[0][0]_rrnode[467]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[467] avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='start_fall_sb_mux[0][0]_rrnode[467]' to='start_fall_sb_mux[0][0]_rrnode[467]+switch_fall_sb_mux[0][0]_rrnode[467]' -.meas tran sum_leakage_power_mux[0to38] -+ param='sum_leakage_power_mux[0to37]+leakage_sb_mux[0][0]_rrnode[467]' -.meas tran sum_energy_per_cycle_mux[0to38] -+ param='sum_energy_per_cycle_mux[0to37]+energy_per_cycle_sb_mux[0][0]_rrnode[467]' -***** Load for rr_node[467] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=76, type=5 ***** -Xchan_mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[148]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to38] -+ param='sum_leakage_power_sb_mux[0to37]+leakage_sb_mux[0][0]_rrnode[467]' -.meas tran sum_energy_per_cycle_sb_mux[0to38] -+ param='sum_energy_per_cycle_sb_mux[0to37]+energy_per_cycle_sb_mux[0][0]_rrnode[467]' -Xmux_1level_tapbuf_size2[39] mux_1level_tapbuf_size2[39]->in[0] mux_1level_tapbuf_size2[39]->in[1] mux_1level_tapbuf_size2[39]->out sram[39]->outb sram[39]->out gvdd_mux_1level_tapbuf_size2[39] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[39], level=1, select_path_id=0. ***** -*****1***** -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -***** Signal mux_1level_tapbuf_size2[39]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[39]->in[0] mux_1level_tapbuf_size2[39]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[39]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[39]->in[1] mux_1level_tapbuf_size2[39]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[39] gvdd_mux_1level_tapbuf_size2[39] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[469] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[469] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[469] when v(mux_1level_tapbuf_size2[39]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[469] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[469] when v(mux_1level_tapbuf_size2[39]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[469] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[39]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[469] param='mux_1level_tapbuf_size2[39]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[39]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[39]_energy_per_cycle param='mux_1level_tapbuf_size2[39]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[469] param='mux_1level_tapbuf_size2[39]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[469] param='dynamic_power_sb_mux[0][0]_rrnode[469]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[469] avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='start_rise_sb_mux[0][0]_rrnode[469]' to='start_rise_sb_mux[0][0]_rrnode[469]+switch_rise_sb_mux[0][0]_rrnode[469]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[469] avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='start_fall_sb_mux[0][0]_rrnode[469]' to='start_fall_sb_mux[0][0]_rrnode[469]+switch_fall_sb_mux[0][0]_rrnode[469]' -.meas tran sum_leakage_power_mux[0to39] -+ param='sum_leakage_power_mux[0to38]+leakage_sb_mux[0][0]_rrnode[469]' -.meas tran sum_energy_per_cycle_mux[0to39] -+ param='sum_energy_per_cycle_mux[0to38]+energy_per_cycle_sb_mux[0][0]_rrnode[469]' -***** Load for rr_node[469] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=78, type=5 ***** -Xchan_mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[151]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to39] -+ param='sum_leakage_power_sb_mux[0to38]+leakage_sb_mux[0][0]_rrnode[469]' -.meas tran sum_energy_per_cycle_sb_mux[0to39] -+ param='sum_energy_per_cycle_sb_mux[0to38]+energy_per_cycle_sb_mux[0][0]_rrnode[469]' -Xmux_1level_tapbuf_size2[40] mux_1level_tapbuf_size2[40]->in[0] mux_1level_tapbuf_size2[40]->in[1] mux_1level_tapbuf_size2[40]->out sram[40]->outb sram[40]->out gvdd_mux_1level_tapbuf_size2[40] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[40], level=1, select_path_id=0. ***** -*****1***** -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -***** Signal mux_1level_tapbuf_size2[40]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[40]->in[0] mux_1level_tapbuf_size2[40]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[40]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[40]->in[1] mux_1level_tapbuf_size2[40]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[40] gvdd_mux_1level_tapbuf_size2[40] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[471] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[471] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[471] when v(mux_1level_tapbuf_size2[40]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[471] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[471] when v(mux_1level_tapbuf_size2[40]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[471] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[40]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[471] param='mux_1level_tapbuf_size2[40]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[40]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[40]_energy_per_cycle param='mux_1level_tapbuf_size2[40]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[471] param='mux_1level_tapbuf_size2[40]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[471] param='dynamic_power_sb_mux[0][0]_rrnode[471]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[471] avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='start_rise_sb_mux[0][0]_rrnode[471]' to='start_rise_sb_mux[0][0]_rrnode[471]+switch_rise_sb_mux[0][0]_rrnode[471]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[471] avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='start_fall_sb_mux[0][0]_rrnode[471]' to='start_fall_sb_mux[0][0]_rrnode[471]+switch_fall_sb_mux[0][0]_rrnode[471]' -.meas tran sum_leakage_power_mux[0to40] -+ param='sum_leakage_power_mux[0to39]+leakage_sb_mux[0][0]_rrnode[471]' -.meas tran sum_energy_per_cycle_mux[0to40] -+ param='sum_energy_per_cycle_mux[0to39]+energy_per_cycle_sb_mux[0][0]_rrnode[471]' -***** Load for rr_node[471] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=80, type=5 ***** -Xchan_mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[155]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to40] -+ param='sum_leakage_power_sb_mux[0to39]+leakage_sb_mux[0][0]_rrnode[471]' -.meas tran sum_energy_per_cycle_sb_mux[0to40] -+ param='sum_energy_per_cycle_sb_mux[0to39]+energy_per_cycle_sb_mux[0][0]_rrnode[471]' -Xmux_1level_tapbuf_size2[41] mux_1level_tapbuf_size2[41]->in[0] mux_1level_tapbuf_size2[41]->in[1] mux_1level_tapbuf_size2[41]->out sram[41]->outb sram[41]->out gvdd_mux_1level_tapbuf_size2[41] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[41], level=1, select_path_id=0. ***** -*****1***** -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -***** Signal mux_1level_tapbuf_size2[41]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[41]->in[0] mux_1level_tapbuf_size2[41]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[41]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[41]->in[1] mux_1level_tapbuf_size2[41]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[41] gvdd_mux_1level_tapbuf_size2[41] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[473] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[473] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[473] when v(mux_1level_tapbuf_size2[41]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[473] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[473] when v(mux_1level_tapbuf_size2[41]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[473] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[41]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[473] param='mux_1level_tapbuf_size2[41]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[41]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[41]_energy_per_cycle param='mux_1level_tapbuf_size2[41]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[473] param='mux_1level_tapbuf_size2[41]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[473] param='dynamic_power_sb_mux[0][0]_rrnode[473]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[473] avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='start_rise_sb_mux[0][0]_rrnode[473]' to='start_rise_sb_mux[0][0]_rrnode[473]+switch_rise_sb_mux[0][0]_rrnode[473]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[473] avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='start_fall_sb_mux[0][0]_rrnode[473]' to='start_fall_sb_mux[0][0]_rrnode[473]+switch_fall_sb_mux[0][0]_rrnode[473]' -.meas tran sum_leakage_power_mux[0to41] -+ param='sum_leakage_power_mux[0to40]+leakage_sb_mux[0][0]_rrnode[473]' -.meas tran sum_energy_per_cycle_mux[0to41] -+ param='sum_energy_per_cycle_mux[0to40]+energy_per_cycle_sb_mux[0][0]_rrnode[473]' -***** Load for rr_node[473] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=82, type=5 ***** -Xchan_mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[159]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to41] -+ param='sum_leakage_power_sb_mux[0to40]+leakage_sb_mux[0][0]_rrnode[473]' -.meas tran sum_energy_per_cycle_sb_mux[0to41] -+ param='sum_energy_per_cycle_sb_mux[0to40]+energy_per_cycle_sb_mux[0][0]_rrnode[473]' -Xmux_1level_tapbuf_size2[42] mux_1level_tapbuf_size2[42]->in[0] mux_1level_tapbuf_size2[42]->in[1] mux_1level_tapbuf_size2[42]->out sram[42]->outb sram[42]->out gvdd_mux_1level_tapbuf_size2[42] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[42], level=1, select_path_id=0. ***** -*****1***** -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -***** Signal mux_1level_tapbuf_size2[42]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[42]->in[0] mux_1level_tapbuf_size2[42]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[42]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[42]->in[1] mux_1level_tapbuf_size2[42]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[42] gvdd_mux_1level_tapbuf_size2[42] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[475] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[475] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[475] when v(mux_1level_tapbuf_size2[42]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[475] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[475] when v(mux_1level_tapbuf_size2[42]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[475] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[42]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[475] param='mux_1level_tapbuf_size2[42]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[42]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[42]_energy_per_cycle param='mux_1level_tapbuf_size2[42]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[475] param='mux_1level_tapbuf_size2[42]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[475] param='dynamic_power_sb_mux[0][0]_rrnode[475]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[475] avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='start_rise_sb_mux[0][0]_rrnode[475]' to='start_rise_sb_mux[0][0]_rrnode[475]+switch_rise_sb_mux[0][0]_rrnode[475]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[475] avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='start_fall_sb_mux[0][0]_rrnode[475]' to='start_fall_sb_mux[0][0]_rrnode[475]+switch_fall_sb_mux[0][0]_rrnode[475]' -.meas tran sum_leakage_power_mux[0to42] -+ param='sum_leakage_power_mux[0to41]+leakage_sb_mux[0][0]_rrnode[475]' -.meas tran sum_energy_per_cycle_mux[0to42] -+ param='sum_energy_per_cycle_mux[0to41]+energy_per_cycle_sb_mux[0][0]_rrnode[475]' -***** Load for rr_node[475] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=84, type=5 ***** -Xchan_mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[163]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to42] -+ param='sum_leakage_power_sb_mux[0to41]+leakage_sb_mux[0][0]_rrnode[475]' -.meas tran sum_energy_per_cycle_sb_mux[0to42] -+ param='sum_energy_per_cycle_sb_mux[0to41]+energy_per_cycle_sb_mux[0][0]_rrnode[475]' -Xmux_1level_tapbuf_size2[43] mux_1level_tapbuf_size2[43]->in[0] mux_1level_tapbuf_size2[43]->in[1] mux_1level_tapbuf_size2[43]->out sram[43]->outb sram[43]->out gvdd_mux_1level_tapbuf_size2[43] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[43], level=1, select_path_id=0. ***** -*****1***** -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -***** Signal mux_1level_tapbuf_size2[43]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[43]->in[0] mux_1level_tapbuf_size2[43]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[43]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[43]->in[1] mux_1level_tapbuf_size2[43]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[43] gvdd_mux_1level_tapbuf_size2[43] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[477] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[477] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[477] when v(mux_1level_tapbuf_size2[43]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[477] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[477] when v(mux_1level_tapbuf_size2[43]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[477] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[43]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[477] param='mux_1level_tapbuf_size2[43]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[43]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[43]_energy_per_cycle param='mux_1level_tapbuf_size2[43]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[477] param='mux_1level_tapbuf_size2[43]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[477] param='dynamic_power_sb_mux[0][0]_rrnode[477]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[477] avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='start_rise_sb_mux[0][0]_rrnode[477]' to='start_rise_sb_mux[0][0]_rrnode[477]+switch_rise_sb_mux[0][0]_rrnode[477]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[477] avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='start_fall_sb_mux[0][0]_rrnode[477]' to='start_fall_sb_mux[0][0]_rrnode[477]+switch_fall_sb_mux[0][0]_rrnode[477]' -.meas tran sum_leakage_power_mux[0to43] -+ param='sum_leakage_power_mux[0to42]+leakage_sb_mux[0][0]_rrnode[477]' -.meas tran sum_energy_per_cycle_mux[0to43] -+ param='sum_energy_per_cycle_mux[0to42]+energy_per_cycle_sb_mux[0][0]_rrnode[477]' -***** Load for rr_node[477] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=86, type=5 ***** -Xchan_mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[167]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to43] -+ param='sum_leakage_power_sb_mux[0to42]+leakage_sb_mux[0][0]_rrnode[477]' -.meas tran sum_energy_per_cycle_sb_mux[0to43] -+ param='sum_energy_per_cycle_sb_mux[0to42]+energy_per_cycle_sb_mux[0][0]_rrnode[477]' -Xmux_1level_tapbuf_size2[44] mux_1level_tapbuf_size2[44]->in[0] mux_1level_tapbuf_size2[44]->in[1] mux_1level_tapbuf_size2[44]->out sram[44]->outb sram[44]->out gvdd_mux_1level_tapbuf_size2[44] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[44], level=1, select_path_id=0. ***** -*****1***** -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -***** Signal mux_1level_tapbuf_size2[44]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[44]->in[0] mux_1level_tapbuf_size2[44]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[44]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[44]->in[1] mux_1level_tapbuf_size2[44]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[44] gvdd_mux_1level_tapbuf_size2[44] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[479] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[479] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[479] when v(mux_1level_tapbuf_size2[44]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[479] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[479] when v(mux_1level_tapbuf_size2[44]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[479] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[44]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[479] param='mux_1level_tapbuf_size2[44]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[44]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[44]_energy_per_cycle param='mux_1level_tapbuf_size2[44]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[479] param='mux_1level_tapbuf_size2[44]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[479] param='dynamic_power_sb_mux[0][0]_rrnode[479]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[479] avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='start_rise_sb_mux[0][0]_rrnode[479]' to='start_rise_sb_mux[0][0]_rrnode[479]+switch_rise_sb_mux[0][0]_rrnode[479]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[479] avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='start_fall_sb_mux[0][0]_rrnode[479]' to='start_fall_sb_mux[0][0]_rrnode[479]+switch_fall_sb_mux[0][0]_rrnode[479]' -.meas tran sum_leakage_power_mux[0to44] -+ param='sum_leakage_power_mux[0to43]+leakage_sb_mux[0][0]_rrnode[479]' -.meas tran sum_energy_per_cycle_mux[0to44] -+ param='sum_energy_per_cycle_mux[0to43]+energy_per_cycle_sb_mux[0][0]_rrnode[479]' -***** Load for rr_node[479] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=88, type=5 ***** -Xchan_mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[171]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to44] -+ param='sum_leakage_power_sb_mux[0to43]+leakage_sb_mux[0][0]_rrnode[479]' -.meas tran sum_energy_per_cycle_sb_mux[0to44] -+ param='sum_energy_per_cycle_sb_mux[0to43]+energy_per_cycle_sb_mux[0][0]_rrnode[479]' -Xmux_1level_tapbuf_size2[45] mux_1level_tapbuf_size2[45]->in[0] mux_1level_tapbuf_size2[45]->in[1] mux_1level_tapbuf_size2[45]->out sram[45]->outb sram[45]->out gvdd_mux_1level_tapbuf_size2[45] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[45], level=1, select_path_id=0. ***** -*****1***** -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -***** Signal mux_1level_tapbuf_size2[45]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[45]->in[0] mux_1level_tapbuf_size2[45]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[45]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[45]->in[1] mux_1level_tapbuf_size2[45]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[45] gvdd_mux_1level_tapbuf_size2[45] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[481] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[481] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[481] when v(mux_1level_tapbuf_size2[45]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[481] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[481] when v(mux_1level_tapbuf_size2[45]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[481] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[45]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[481] param='mux_1level_tapbuf_size2[45]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[45]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[45]_energy_per_cycle param='mux_1level_tapbuf_size2[45]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[481] param='mux_1level_tapbuf_size2[45]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[481] param='dynamic_power_sb_mux[0][0]_rrnode[481]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[481] avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='start_rise_sb_mux[0][0]_rrnode[481]' to='start_rise_sb_mux[0][0]_rrnode[481]+switch_rise_sb_mux[0][0]_rrnode[481]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[481] avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='start_fall_sb_mux[0][0]_rrnode[481]' to='start_fall_sb_mux[0][0]_rrnode[481]+switch_fall_sb_mux[0][0]_rrnode[481]' -.meas tran sum_leakage_power_mux[0to45] -+ param='sum_leakage_power_mux[0to44]+leakage_sb_mux[0][0]_rrnode[481]' -.meas tran sum_energy_per_cycle_mux[0to45] -+ param='sum_energy_per_cycle_mux[0to44]+energy_per_cycle_sb_mux[0][0]_rrnode[481]' -***** Load for rr_node[481] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=90, type=5 ***** -Xchan_mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[175]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to45] -+ param='sum_leakage_power_sb_mux[0to44]+leakage_sb_mux[0][0]_rrnode[481]' -.meas tran sum_energy_per_cycle_sb_mux[0to45] -+ param='sum_energy_per_cycle_sb_mux[0to44]+energy_per_cycle_sb_mux[0][0]_rrnode[481]' -Xmux_1level_tapbuf_size2[46] mux_1level_tapbuf_size2[46]->in[0] mux_1level_tapbuf_size2[46]->in[1] mux_1level_tapbuf_size2[46]->out sram[46]->outb sram[46]->out gvdd_mux_1level_tapbuf_size2[46] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[46], level=1, select_path_id=0. ***** -*****1***** -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -***** Signal mux_1level_tapbuf_size2[46]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[46]->in[0] mux_1level_tapbuf_size2[46]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[46]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[46]->in[1] mux_1level_tapbuf_size2[46]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[46] gvdd_mux_1level_tapbuf_size2[46] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[483] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[483] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[483] when v(mux_1level_tapbuf_size2[46]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[483] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[483] when v(mux_1level_tapbuf_size2[46]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[483] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[46]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[483] param='mux_1level_tapbuf_size2[46]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[46]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[46]_energy_per_cycle param='mux_1level_tapbuf_size2[46]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[483] param='mux_1level_tapbuf_size2[46]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[483] param='dynamic_power_sb_mux[0][0]_rrnode[483]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[483] avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='start_rise_sb_mux[0][0]_rrnode[483]' to='start_rise_sb_mux[0][0]_rrnode[483]+switch_rise_sb_mux[0][0]_rrnode[483]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[483] avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='start_fall_sb_mux[0][0]_rrnode[483]' to='start_fall_sb_mux[0][0]_rrnode[483]+switch_fall_sb_mux[0][0]_rrnode[483]' -.meas tran sum_leakage_power_mux[0to46] -+ param='sum_leakage_power_mux[0to45]+leakage_sb_mux[0][0]_rrnode[483]' -.meas tran sum_energy_per_cycle_mux[0to46] -+ param='sum_energy_per_cycle_mux[0to45]+energy_per_cycle_sb_mux[0][0]_rrnode[483]' -***** Load for rr_node[483] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=92, type=5 ***** -Xchan_mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[178]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[180]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to46] -+ param='sum_leakage_power_sb_mux[0to45]+leakage_sb_mux[0][0]_rrnode[483]' -.meas tran sum_energy_per_cycle_sb_mux[0to46] -+ param='sum_energy_per_cycle_sb_mux[0to45]+energy_per_cycle_sb_mux[0][0]_rrnode[483]' -Xmux_1level_tapbuf_size2[47] mux_1level_tapbuf_size2[47]->in[0] mux_1level_tapbuf_size2[47]->in[1] mux_1level_tapbuf_size2[47]->out sram[47]->outb sram[47]->out gvdd_mux_1level_tapbuf_size2[47] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[47], level=1, select_path_id=0. ***** -*****1***** -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -***** Signal mux_1level_tapbuf_size2[47]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[47]->in[0] mux_1level_tapbuf_size2[47]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[47]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[47]->in[1] mux_1level_tapbuf_size2[47]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[47] gvdd_mux_1level_tapbuf_size2[47] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[485] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[485] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[485] when v(mux_1level_tapbuf_size2[47]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[485] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[485] when v(mux_1level_tapbuf_size2[47]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[485] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[47]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[485] param='mux_1level_tapbuf_size2[47]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[47]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[47]_energy_per_cycle param='mux_1level_tapbuf_size2[47]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[485] param='mux_1level_tapbuf_size2[47]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[485] param='dynamic_power_sb_mux[0][0]_rrnode[485]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[485] avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='start_rise_sb_mux[0][0]_rrnode[485]' to='start_rise_sb_mux[0][0]_rrnode[485]+switch_rise_sb_mux[0][0]_rrnode[485]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[485] avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='start_fall_sb_mux[0][0]_rrnode[485]' to='start_fall_sb_mux[0][0]_rrnode[485]+switch_fall_sb_mux[0][0]_rrnode[485]' -.meas tran sum_leakage_power_mux[0to47] -+ param='sum_leakage_power_mux[0to46]+leakage_sb_mux[0][0]_rrnode[485]' -.meas tran sum_energy_per_cycle_mux[0to47] -+ param='sum_energy_per_cycle_mux[0to46]+energy_per_cycle_sb_mux[0][0]_rrnode[485]' -***** Load for rr_node[485] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=94, type=5 ***** -Xchan_mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[182]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to47] -+ param='sum_leakage_power_sb_mux[0to46]+leakage_sb_mux[0][0]_rrnode[485]' -.meas tran sum_energy_per_cycle_sb_mux[0to47] -+ param='sum_energy_per_cycle_sb_mux[0to46]+energy_per_cycle_sb_mux[0][0]_rrnode[485]' -Xmux_1level_tapbuf_size2[48] mux_1level_tapbuf_size2[48]->in[0] mux_1level_tapbuf_size2[48]->in[1] mux_1level_tapbuf_size2[48]->out sram[48]->outb sram[48]->out gvdd_mux_1level_tapbuf_size2[48] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[48], level=1, select_path_id=0. ***** -*****1***** -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -***** Signal mux_1level_tapbuf_size2[48]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[48]->in[0] mux_1level_tapbuf_size2[48]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[48]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[48]->in[1] mux_1level_tapbuf_size2[48]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[48] gvdd_mux_1level_tapbuf_size2[48] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[487] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[487] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[487] when v(mux_1level_tapbuf_size2[48]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[487] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[487] when v(mux_1level_tapbuf_size2[48]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[487] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[48]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[487] param='mux_1level_tapbuf_size2[48]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[48]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[48]_energy_per_cycle param='mux_1level_tapbuf_size2[48]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[487] param='mux_1level_tapbuf_size2[48]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[487] param='dynamic_power_sb_mux[0][0]_rrnode[487]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[487] avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='start_rise_sb_mux[0][0]_rrnode[487]' to='start_rise_sb_mux[0][0]_rrnode[487]+switch_rise_sb_mux[0][0]_rrnode[487]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[487] avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='start_fall_sb_mux[0][0]_rrnode[487]' to='start_fall_sb_mux[0][0]_rrnode[487]+switch_fall_sb_mux[0][0]_rrnode[487]' -.meas tran sum_leakage_power_mux[0to48] -+ param='sum_leakage_power_mux[0to47]+leakage_sb_mux[0][0]_rrnode[487]' -.meas tran sum_energy_per_cycle_mux[0to48] -+ param='sum_energy_per_cycle_mux[0to47]+energy_per_cycle_sb_mux[0][0]_rrnode[487]' -***** Load for rr_node[487] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=96, type=5 ***** -Xchan_mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[187]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to48] -+ param='sum_leakage_power_sb_mux[0to47]+leakage_sb_mux[0][0]_rrnode[487]' -.meas tran sum_energy_per_cycle_sb_mux[0to48] -+ param='sum_energy_per_cycle_sb_mux[0to47]+energy_per_cycle_sb_mux[0][0]_rrnode[487]' -Xmux_1level_tapbuf_size2[49] mux_1level_tapbuf_size2[49]->in[0] mux_1level_tapbuf_size2[49]->in[1] mux_1level_tapbuf_size2[49]->out sram[49]->outb sram[49]->out gvdd_mux_1level_tapbuf_size2[49] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[49], level=1, select_path_id=0. ***** -*****1***** -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -***** Signal mux_1level_tapbuf_size2[49]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[49]->in[0] mux_1level_tapbuf_size2[49]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[49]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[49]->in[1] mux_1level_tapbuf_size2[49]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[49] gvdd_mux_1level_tapbuf_size2[49] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[489] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[489] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[489] when v(mux_1level_tapbuf_size2[49]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[489] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[489] when v(mux_1level_tapbuf_size2[49]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[489] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[49]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[489] param='mux_1level_tapbuf_size2[49]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[49]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[49]_energy_per_cycle param='mux_1level_tapbuf_size2[49]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[489] param='mux_1level_tapbuf_size2[49]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[489] param='dynamic_power_sb_mux[0][0]_rrnode[489]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[489] avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='start_rise_sb_mux[0][0]_rrnode[489]' to='start_rise_sb_mux[0][0]_rrnode[489]+switch_rise_sb_mux[0][0]_rrnode[489]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[489] avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='start_fall_sb_mux[0][0]_rrnode[489]' to='start_fall_sb_mux[0][0]_rrnode[489]+switch_fall_sb_mux[0][0]_rrnode[489]' -.meas tran sum_leakage_power_mux[0to49] -+ param='sum_leakage_power_mux[0to48]+leakage_sb_mux[0][0]_rrnode[489]' -.meas tran sum_energy_per_cycle_mux[0to49] -+ param='sum_energy_per_cycle_mux[0to48]+energy_per_cycle_sb_mux[0][0]_rrnode[489]' -***** Load for rr_node[489] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=98, type=5 ***** -Xchan_mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[190]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to49] -+ param='sum_leakage_power_sb_mux[0to48]+leakage_sb_mux[0][0]_rrnode[489]' -.meas tran sum_energy_per_cycle_sb_mux[0to49] -+ param='sum_energy_per_cycle_sb_mux[0to48]+energy_per_cycle_sb_mux[0][0]_rrnode[489]' -Xmux_1level_tapbuf_size2[50] mux_1level_tapbuf_size2[50]->in[0] mux_1level_tapbuf_size2[50]->in[1] mux_1level_tapbuf_size2[50]->out sram[50]->outb sram[50]->out gvdd_mux_1level_tapbuf_size2[50] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[50], level=1, select_path_id=0. ***** -*****1***** -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -***** Signal mux_1level_tapbuf_size2[50]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[50]->in[0] mux_1level_tapbuf_size2[50]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[50]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[50]->in[1] mux_1level_tapbuf_size2[50]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[50] gvdd_mux_1level_tapbuf_size2[50] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[191] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[191] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[191] when v(mux_1level_tapbuf_size2[50]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[191] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[191] when v(mux_1level_tapbuf_size2[50]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[191] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[50]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[191] param='mux_1level_tapbuf_size2[50]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[50]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[50]_energy_per_cycle param='mux_1level_tapbuf_size2[50]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[191] param='mux_1level_tapbuf_size2[50]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[191] param='dynamic_power_sb_mux[0][0]_rrnode[191]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[191] avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from='start_rise_sb_mux[0][0]_rrnode[191]' to='start_rise_sb_mux[0][0]_rrnode[191]+switch_rise_sb_mux[0][0]_rrnode[191]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[191] avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from='start_fall_sb_mux[0][0]_rrnode[191]' to='start_fall_sb_mux[0][0]_rrnode[191]+switch_fall_sb_mux[0][0]_rrnode[191]' -.meas tran sum_leakage_power_mux[0to50] -+ param='sum_leakage_power_mux[0to49]+leakage_sb_mux[0][0]_rrnode[191]' -.meas tran sum_energy_per_cycle_mux[0to50] -+ param='sum_energy_per_cycle_mux[0to49]+energy_per_cycle_sb_mux[0][0]_rrnode[191]' -***** Load for rr_node[191] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=0, type=4 ***** -Xchan_mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out mux_1level_tapbuf_size2[50]->out mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[194]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to50] -+ param='sum_leakage_power_sb_mux[0to49]+leakage_sb_mux[0][0]_rrnode[191]' -.meas tran sum_energy_per_cycle_sb_mux[0to50] -+ param='sum_energy_per_cycle_sb_mux[0to49]+energy_per_cycle_sb_mux[0][0]_rrnode[191]' -Xmux_1level_tapbuf_size2[51] mux_1level_tapbuf_size2[51]->in[0] mux_1level_tapbuf_size2[51]->in[1] mux_1level_tapbuf_size2[51]->out sram[51]->outb sram[51]->out gvdd_mux_1level_tapbuf_size2[51] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[51], level=1, select_path_id=0. ***** -*****1***** -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -***** Signal mux_1level_tapbuf_size2[51]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[51]->in[0] mux_1level_tapbuf_size2[51]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[51]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[51]->in[1] mux_1level_tapbuf_size2[51]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[51] gvdd_mux_1level_tapbuf_size2[51] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[193] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[193] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[193] when v(mux_1level_tapbuf_size2[51]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[193] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[193] when v(mux_1level_tapbuf_size2[51]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[193] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[51]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[193] param='mux_1level_tapbuf_size2[51]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[51]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[51]_energy_per_cycle param='mux_1level_tapbuf_size2[51]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[193] param='mux_1level_tapbuf_size2[51]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[193] param='dynamic_power_sb_mux[0][0]_rrnode[193]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[193] avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from='start_rise_sb_mux[0][0]_rrnode[193]' to='start_rise_sb_mux[0][0]_rrnode[193]+switch_rise_sb_mux[0][0]_rrnode[193]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[193] avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from='start_fall_sb_mux[0][0]_rrnode[193]' to='start_fall_sb_mux[0][0]_rrnode[193]+switch_fall_sb_mux[0][0]_rrnode[193]' -.meas tran sum_leakage_power_mux[0to51] -+ param='sum_leakage_power_mux[0to50]+leakage_sb_mux[0][0]_rrnode[193]' -.meas tran sum_energy_per_cycle_mux[0to51] -+ param='sum_energy_per_cycle_mux[0to50]+energy_per_cycle_sb_mux[0][0]_rrnode[193]' -***** Load for rr_node[193] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=2, type=4 ***** -Xchan_mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out mux_1level_tapbuf_size2[51]->out mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[199]_no0 mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to51] -+ param='sum_leakage_power_sb_mux[0to50]+leakage_sb_mux[0][0]_rrnode[193]' -.meas tran sum_energy_per_cycle_sb_mux[0to51] -+ param='sum_energy_per_cycle_sb_mux[0to50]+energy_per_cycle_sb_mux[0][0]_rrnode[193]' -Xmux_1level_tapbuf_size2[52] mux_1level_tapbuf_size2[52]->in[0] mux_1level_tapbuf_size2[52]->in[1] mux_1level_tapbuf_size2[52]->out sram[52]->outb sram[52]->out gvdd_mux_1level_tapbuf_size2[52] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[52], level=1, select_path_id=0. ***** -*****1***** -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -***** Signal mux_1level_tapbuf_size2[52]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[52]->in[0] mux_1level_tapbuf_size2[52]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[52]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[52]->in[1] mux_1level_tapbuf_size2[52]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[52] gvdd_mux_1level_tapbuf_size2[52] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[195] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[195] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[195] when v(mux_1level_tapbuf_size2[52]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[195] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[195] when v(mux_1level_tapbuf_size2[52]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[195] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[52]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[195] param='mux_1level_tapbuf_size2[52]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[52]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[52]_energy_per_cycle param='mux_1level_tapbuf_size2[52]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[195] param='mux_1level_tapbuf_size2[52]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[195] param='dynamic_power_sb_mux[0][0]_rrnode[195]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[195] avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from='start_rise_sb_mux[0][0]_rrnode[195]' to='start_rise_sb_mux[0][0]_rrnode[195]+switch_rise_sb_mux[0][0]_rrnode[195]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[195] avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from='start_fall_sb_mux[0][0]_rrnode[195]' to='start_fall_sb_mux[0][0]_rrnode[195]+switch_fall_sb_mux[0][0]_rrnode[195]' -.meas tran sum_leakage_power_mux[0to52] -+ param='sum_leakage_power_mux[0to51]+leakage_sb_mux[0][0]_rrnode[195]' -.meas tran sum_energy_per_cycle_mux[0to52] -+ param='sum_energy_per_cycle_mux[0to51]+energy_per_cycle_sb_mux[0][0]_rrnode[195]' -***** Load for rr_node[195] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=4, type=4 ***** -Xchan_mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out mux_1level_tapbuf_size2[52]->out mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[202]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to52] -+ param='sum_leakage_power_sb_mux[0to51]+leakage_sb_mux[0][0]_rrnode[195]' -.meas tran sum_energy_per_cycle_sb_mux[0to52] -+ param='sum_energy_per_cycle_sb_mux[0to51]+energy_per_cycle_sb_mux[0][0]_rrnode[195]' -Xmux_1level_tapbuf_size2[53] mux_1level_tapbuf_size2[53]->in[0] mux_1level_tapbuf_size2[53]->in[1] mux_1level_tapbuf_size2[53]->out sram[53]->outb sram[53]->out gvdd_mux_1level_tapbuf_size2[53] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[53], level=1, select_path_id=0. ***** -*****1***** -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -***** Signal mux_1level_tapbuf_size2[53]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[53]->in[0] mux_1level_tapbuf_size2[53]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[53]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[53]->in[1] mux_1level_tapbuf_size2[53]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[53] gvdd_mux_1level_tapbuf_size2[53] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[197] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[197] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[197] when v(mux_1level_tapbuf_size2[53]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[197] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[197] when v(mux_1level_tapbuf_size2[53]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[197] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[53]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[197] param='mux_1level_tapbuf_size2[53]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[53]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[53]_energy_per_cycle param='mux_1level_tapbuf_size2[53]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[197] param='mux_1level_tapbuf_size2[53]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[197] param='dynamic_power_sb_mux[0][0]_rrnode[197]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[197] avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from='start_rise_sb_mux[0][0]_rrnode[197]' to='start_rise_sb_mux[0][0]_rrnode[197]+switch_rise_sb_mux[0][0]_rrnode[197]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[197] avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from='start_fall_sb_mux[0][0]_rrnode[197]' to='start_fall_sb_mux[0][0]_rrnode[197]+switch_fall_sb_mux[0][0]_rrnode[197]' -.meas tran sum_leakage_power_mux[0to53] -+ param='sum_leakage_power_mux[0to52]+leakage_sb_mux[0][0]_rrnode[197]' -.meas tran sum_energy_per_cycle_mux[0to53] -+ param='sum_energy_per_cycle_mux[0to52]+energy_per_cycle_sb_mux[0][0]_rrnode[197]' -***** Load for rr_node[197] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=6, type=4 ***** -Xchan_mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out mux_1level_tapbuf_size2[53]->out mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[206]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to53] -+ param='sum_leakage_power_sb_mux[0to52]+leakage_sb_mux[0][0]_rrnode[197]' -.meas tran sum_energy_per_cycle_sb_mux[0to53] -+ param='sum_energy_per_cycle_sb_mux[0to52]+energy_per_cycle_sb_mux[0][0]_rrnode[197]' -Xmux_1level_tapbuf_size2[54] mux_1level_tapbuf_size2[54]->in[0] mux_1level_tapbuf_size2[54]->in[1] mux_1level_tapbuf_size2[54]->out sram[54]->outb sram[54]->out gvdd_mux_1level_tapbuf_size2[54] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[54], level=1, select_path_id=0. ***** -*****1***** -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -***** Signal mux_1level_tapbuf_size2[54]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[54]->in[0] mux_1level_tapbuf_size2[54]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[54]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[54]->in[1] mux_1level_tapbuf_size2[54]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[54] gvdd_mux_1level_tapbuf_size2[54] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[199] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[199] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[199] when v(mux_1level_tapbuf_size2[54]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[199] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[199] when v(mux_1level_tapbuf_size2[54]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[199] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[54]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[199] param='mux_1level_tapbuf_size2[54]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[54]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[54]_energy_per_cycle param='mux_1level_tapbuf_size2[54]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[199] param='mux_1level_tapbuf_size2[54]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[199] param='dynamic_power_sb_mux[0][0]_rrnode[199]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[199] avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from='start_rise_sb_mux[0][0]_rrnode[199]' to='start_rise_sb_mux[0][0]_rrnode[199]+switch_rise_sb_mux[0][0]_rrnode[199]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[199] avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from='start_fall_sb_mux[0][0]_rrnode[199]' to='start_fall_sb_mux[0][0]_rrnode[199]+switch_fall_sb_mux[0][0]_rrnode[199]' -.meas tran sum_leakage_power_mux[0to54] -+ param='sum_leakage_power_mux[0to53]+leakage_sb_mux[0][0]_rrnode[199]' -.meas tran sum_energy_per_cycle_mux[0to54] -+ param='sum_energy_per_cycle_mux[0to53]+energy_per_cycle_sb_mux[0][0]_rrnode[199]' -***** Load for rr_node[199] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=8, type=4 ***** -Xchan_mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out mux_1level_tapbuf_size2[54]->out mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[210]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to54] -+ param='sum_leakage_power_sb_mux[0to53]+leakage_sb_mux[0][0]_rrnode[199]' -.meas tran sum_energy_per_cycle_sb_mux[0to54] -+ param='sum_energy_per_cycle_sb_mux[0to53]+energy_per_cycle_sb_mux[0][0]_rrnode[199]' -Xmux_1level_tapbuf_size2[55] mux_1level_tapbuf_size2[55]->in[0] mux_1level_tapbuf_size2[55]->in[1] mux_1level_tapbuf_size2[55]->out sram[55]->outb sram[55]->out gvdd_mux_1level_tapbuf_size2[55] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[55], level=1, select_path_id=0. ***** -*****1***** -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -***** Signal mux_1level_tapbuf_size2[55]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[55]->in[0] mux_1level_tapbuf_size2[55]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[55]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[55]->in[1] mux_1level_tapbuf_size2[55]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[55] gvdd_mux_1level_tapbuf_size2[55] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[201] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[201] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[201] when v(mux_1level_tapbuf_size2[55]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[201] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[201] when v(mux_1level_tapbuf_size2[55]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[201] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[55]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[201] param='mux_1level_tapbuf_size2[55]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[55]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[55]_energy_per_cycle param='mux_1level_tapbuf_size2[55]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[201] param='mux_1level_tapbuf_size2[55]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[201] param='dynamic_power_sb_mux[0][0]_rrnode[201]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[201] avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='start_rise_sb_mux[0][0]_rrnode[201]' to='start_rise_sb_mux[0][0]_rrnode[201]+switch_rise_sb_mux[0][0]_rrnode[201]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[201] avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='start_fall_sb_mux[0][0]_rrnode[201]' to='start_fall_sb_mux[0][0]_rrnode[201]+switch_fall_sb_mux[0][0]_rrnode[201]' -.meas tran sum_leakage_power_mux[0to55] -+ param='sum_leakage_power_mux[0to54]+leakage_sb_mux[0][0]_rrnode[201]' -.meas tran sum_energy_per_cycle_mux[0to55] -+ param='sum_energy_per_cycle_mux[0to54]+energy_per_cycle_sb_mux[0][0]_rrnode[201]' -***** Load for rr_node[201] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=10, type=4 ***** -Xchan_mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[214]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to55] -+ param='sum_leakage_power_sb_mux[0to54]+leakage_sb_mux[0][0]_rrnode[201]' -.meas tran sum_energy_per_cycle_sb_mux[0to55] -+ param='sum_energy_per_cycle_sb_mux[0to54]+energy_per_cycle_sb_mux[0][0]_rrnode[201]' -Xmux_1level_tapbuf_size2[56] mux_1level_tapbuf_size2[56]->in[0] mux_1level_tapbuf_size2[56]->in[1] mux_1level_tapbuf_size2[56]->out sram[56]->outb sram[56]->out gvdd_mux_1level_tapbuf_size2[56] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[56], level=1, select_path_id=0. ***** -*****1***** -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -***** Signal mux_1level_tapbuf_size2[56]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[56]->in[0] mux_1level_tapbuf_size2[56]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[56]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[56]->in[1] mux_1level_tapbuf_size2[56]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[56] gvdd_mux_1level_tapbuf_size2[56] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[203] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[203] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[203] when v(mux_1level_tapbuf_size2[56]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[203] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[203] when v(mux_1level_tapbuf_size2[56]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[203] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[56]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[203] param='mux_1level_tapbuf_size2[56]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[56]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[56]_energy_per_cycle param='mux_1level_tapbuf_size2[56]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[203] param='mux_1level_tapbuf_size2[56]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[203] param='dynamic_power_sb_mux[0][0]_rrnode[203]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[203] avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='start_rise_sb_mux[0][0]_rrnode[203]' to='start_rise_sb_mux[0][0]_rrnode[203]+switch_rise_sb_mux[0][0]_rrnode[203]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[203] avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='start_fall_sb_mux[0][0]_rrnode[203]' to='start_fall_sb_mux[0][0]_rrnode[203]+switch_fall_sb_mux[0][0]_rrnode[203]' -.meas tran sum_leakage_power_mux[0to56] -+ param='sum_leakage_power_mux[0to55]+leakage_sb_mux[0][0]_rrnode[203]' -.meas tran sum_energy_per_cycle_mux[0to56] -+ param='sum_energy_per_cycle_mux[0to55]+energy_per_cycle_sb_mux[0][0]_rrnode[203]' -***** Load for rr_node[203] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=12, type=4 ***** -Xchan_mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[218]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to56] -+ param='sum_leakage_power_sb_mux[0to55]+leakage_sb_mux[0][0]_rrnode[203]' -.meas tran sum_energy_per_cycle_sb_mux[0to56] -+ param='sum_energy_per_cycle_sb_mux[0to55]+energy_per_cycle_sb_mux[0][0]_rrnode[203]' -Xmux_1level_tapbuf_size2[57] mux_1level_tapbuf_size2[57]->in[0] mux_1level_tapbuf_size2[57]->in[1] mux_1level_tapbuf_size2[57]->out sram[57]->outb sram[57]->out gvdd_mux_1level_tapbuf_size2[57] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[57], level=1, select_path_id=0. ***** -*****1***** -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -***** Signal mux_1level_tapbuf_size2[57]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[57]->in[0] mux_1level_tapbuf_size2[57]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[57]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[57]->in[1] mux_1level_tapbuf_size2[57]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[57] gvdd_mux_1level_tapbuf_size2[57] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[205] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[205] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[205] when v(mux_1level_tapbuf_size2[57]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[205] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[205] when v(mux_1level_tapbuf_size2[57]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[205] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[57]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[205] param='mux_1level_tapbuf_size2[57]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[57]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[57]_energy_per_cycle param='mux_1level_tapbuf_size2[57]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[205] param='mux_1level_tapbuf_size2[57]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[205] param='dynamic_power_sb_mux[0][0]_rrnode[205]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[205] avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='start_rise_sb_mux[0][0]_rrnode[205]' to='start_rise_sb_mux[0][0]_rrnode[205]+switch_rise_sb_mux[0][0]_rrnode[205]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[205] avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='start_fall_sb_mux[0][0]_rrnode[205]' to='start_fall_sb_mux[0][0]_rrnode[205]+switch_fall_sb_mux[0][0]_rrnode[205]' -.meas tran sum_leakage_power_mux[0to57] -+ param='sum_leakage_power_mux[0to56]+leakage_sb_mux[0][0]_rrnode[205]' -.meas tran sum_energy_per_cycle_mux[0to57] -+ param='sum_energy_per_cycle_mux[0to56]+energy_per_cycle_sb_mux[0][0]_rrnode[205]' -***** Load for rr_node[205] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=14, type=4 ***** -Xchan_mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[221]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to57] -+ param='sum_leakage_power_sb_mux[0to56]+leakage_sb_mux[0][0]_rrnode[205]' -.meas tran sum_energy_per_cycle_sb_mux[0to57] -+ param='sum_energy_per_cycle_sb_mux[0to56]+energy_per_cycle_sb_mux[0][0]_rrnode[205]' -Xmux_1level_tapbuf_size2[58] mux_1level_tapbuf_size2[58]->in[0] mux_1level_tapbuf_size2[58]->in[1] mux_1level_tapbuf_size2[58]->out sram[58]->outb sram[58]->out gvdd_mux_1level_tapbuf_size2[58] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[58], level=1, select_path_id=0. ***** -*****1***** -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -***** Signal mux_1level_tapbuf_size2[58]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[58]->in[0] mux_1level_tapbuf_size2[58]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[58]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[58]->in[1] mux_1level_tapbuf_size2[58]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[58] gvdd_mux_1level_tapbuf_size2[58] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[207] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[207] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[207] when v(mux_1level_tapbuf_size2[58]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[207] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[207] when v(mux_1level_tapbuf_size2[58]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[207] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[58]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[207] param='mux_1level_tapbuf_size2[58]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[58]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[58]_energy_per_cycle param='mux_1level_tapbuf_size2[58]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[207] param='mux_1level_tapbuf_size2[58]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[207] param='dynamic_power_sb_mux[0][0]_rrnode[207]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[207] avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='start_rise_sb_mux[0][0]_rrnode[207]' to='start_rise_sb_mux[0][0]_rrnode[207]+switch_rise_sb_mux[0][0]_rrnode[207]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[207] avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='start_fall_sb_mux[0][0]_rrnode[207]' to='start_fall_sb_mux[0][0]_rrnode[207]+switch_fall_sb_mux[0][0]_rrnode[207]' -.meas tran sum_leakage_power_mux[0to58] -+ param='sum_leakage_power_mux[0to57]+leakage_sb_mux[0][0]_rrnode[207]' -.meas tran sum_energy_per_cycle_mux[0to58] -+ param='sum_energy_per_cycle_mux[0to57]+energy_per_cycle_sb_mux[0][0]_rrnode[207]' -***** Load for rr_node[207] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=16, type=4 ***** -Xchan_mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[226]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to58] -+ param='sum_leakage_power_sb_mux[0to57]+leakage_sb_mux[0][0]_rrnode[207]' -.meas tran sum_energy_per_cycle_sb_mux[0to58] -+ param='sum_energy_per_cycle_sb_mux[0to57]+energy_per_cycle_sb_mux[0][0]_rrnode[207]' -Xmux_1level_tapbuf_size2[59] mux_1level_tapbuf_size2[59]->in[0] mux_1level_tapbuf_size2[59]->in[1] mux_1level_tapbuf_size2[59]->out sram[59]->outb sram[59]->out gvdd_mux_1level_tapbuf_size2[59] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[59], level=1, select_path_id=0. ***** -*****1***** -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -***** Signal mux_1level_tapbuf_size2[59]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[59]->in[0] mux_1level_tapbuf_size2[59]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[59]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[59]->in[1] mux_1level_tapbuf_size2[59]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[59] gvdd_mux_1level_tapbuf_size2[59] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[209] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[209] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[209] when v(mux_1level_tapbuf_size2[59]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[209] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[209] when v(mux_1level_tapbuf_size2[59]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[209] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[59]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[209] param='mux_1level_tapbuf_size2[59]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[59]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[59]_energy_per_cycle param='mux_1level_tapbuf_size2[59]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[209] param='mux_1level_tapbuf_size2[59]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[209] param='dynamic_power_sb_mux[0][0]_rrnode[209]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[209] avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='start_rise_sb_mux[0][0]_rrnode[209]' to='start_rise_sb_mux[0][0]_rrnode[209]+switch_rise_sb_mux[0][0]_rrnode[209]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[209] avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='start_fall_sb_mux[0][0]_rrnode[209]' to='start_fall_sb_mux[0][0]_rrnode[209]+switch_fall_sb_mux[0][0]_rrnode[209]' -.meas tran sum_leakage_power_mux[0to59] -+ param='sum_leakage_power_mux[0to58]+leakage_sb_mux[0][0]_rrnode[209]' -.meas tran sum_energy_per_cycle_mux[0to59] -+ param='sum_energy_per_cycle_mux[0to58]+energy_per_cycle_sb_mux[0][0]_rrnode[209]' -***** Load for rr_node[209] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=18, type=4 ***** -Xchan_mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[229]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to59] -+ param='sum_leakage_power_sb_mux[0to58]+leakage_sb_mux[0][0]_rrnode[209]' -.meas tran sum_energy_per_cycle_sb_mux[0to59] -+ param='sum_energy_per_cycle_sb_mux[0to58]+energy_per_cycle_sb_mux[0][0]_rrnode[209]' -Xmux_1level_tapbuf_size2[60] mux_1level_tapbuf_size2[60]->in[0] mux_1level_tapbuf_size2[60]->in[1] mux_1level_tapbuf_size2[60]->out sram[60]->outb sram[60]->out gvdd_mux_1level_tapbuf_size2[60] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[60], level=1, select_path_id=0. ***** -*****1***** -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -***** Signal mux_1level_tapbuf_size2[60]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[60]->in[0] mux_1level_tapbuf_size2[60]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[60]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[60]->in[1] mux_1level_tapbuf_size2[60]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[60] gvdd_mux_1level_tapbuf_size2[60] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[211] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[211] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[211] when v(mux_1level_tapbuf_size2[60]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[211] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[211] when v(mux_1level_tapbuf_size2[60]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[211] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[60]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[211] param='mux_1level_tapbuf_size2[60]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[60]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[60]_energy_per_cycle param='mux_1level_tapbuf_size2[60]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[211] param='mux_1level_tapbuf_size2[60]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[211] param='dynamic_power_sb_mux[0][0]_rrnode[211]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[211] avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='start_rise_sb_mux[0][0]_rrnode[211]' to='start_rise_sb_mux[0][0]_rrnode[211]+switch_rise_sb_mux[0][0]_rrnode[211]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[211] avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='start_fall_sb_mux[0][0]_rrnode[211]' to='start_fall_sb_mux[0][0]_rrnode[211]+switch_fall_sb_mux[0][0]_rrnode[211]' -.meas tran sum_leakage_power_mux[0to60] -+ param='sum_leakage_power_mux[0to59]+leakage_sb_mux[0][0]_rrnode[211]' -.meas tran sum_energy_per_cycle_mux[0to60] -+ param='sum_energy_per_cycle_mux[0to59]+energy_per_cycle_sb_mux[0][0]_rrnode[211]' -***** Load for rr_node[211] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=20, type=4 ***** -Xchan_mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[233]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to60] -+ param='sum_leakage_power_sb_mux[0to59]+leakage_sb_mux[0][0]_rrnode[211]' -.meas tran sum_energy_per_cycle_sb_mux[0to60] -+ param='sum_energy_per_cycle_sb_mux[0to59]+energy_per_cycle_sb_mux[0][0]_rrnode[211]' -Xmux_1level_tapbuf_size2[61] mux_1level_tapbuf_size2[61]->in[0] mux_1level_tapbuf_size2[61]->in[1] mux_1level_tapbuf_size2[61]->out sram[61]->outb sram[61]->out gvdd_mux_1level_tapbuf_size2[61] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[61], level=1, select_path_id=0. ***** -*****1***** -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -***** Signal mux_1level_tapbuf_size2[61]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[61]->in[0] mux_1level_tapbuf_size2[61]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[61]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[61]->in[1] mux_1level_tapbuf_size2[61]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[61] gvdd_mux_1level_tapbuf_size2[61] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[213] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[213] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[213] when v(mux_1level_tapbuf_size2[61]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[213] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[213] when v(mux_1level_tapbuf_size2[61]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[213] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[61]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[213] param='mux_1level_tapbuf_size2[61]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[61]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[61]_energy_per_cycle param='mux_1level_tapbuf_size2[61]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[213] param='mux_1level_tapbuf_size2[61]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[213] param='dynamic_power_sb_mux[0][0]_rrnode[213]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[213] avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='start_rise_sb_mux[0][0]_rrnode[213]' to='start_rise_sb_mux[0][0]_rrnode[213]+switch_rise_sb_mux[0][0]_rrnode[213]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[213] avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='start_fall_sb_mux[0][0]_rrnode[213]' to='start_fall_sb_mux[0][0]_rrnode[213]+switch_fall_sb_mux[0][0]_rrnode[213]' -.meas tran sum_leakage_power_mux[0to61] -+ param='sum_leakage_power_mux[0to60]+leakage_sb_mux[0][0]_rrnode[213]' -.meas tran sum_energy_per_cycle_mux[0to61] -+ param='sum_energy_per_cycle_mux[0to60]+energy_per_cycle_sb_mux[0][0]_rrnode[213]' -***** Load for rr_node[213] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=22, type=4 ***** -Xchan_mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[238]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[240]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to61] -+ param='sum_leakage_power_sb_mux[0to60]+leakage_sb_mux[0][0]_rrnode[213]' -.meas tran sum_energy_per_cycle_sb_mux[0to61] -+ param='sum_energy_per_cycle_sb_mux[0to60]+energy_per_cycle_sb_mux[0][0]_rrnode[213]' -Xmux_1level_tapbuf_size2[62] mux_1level_tapbuf_size2[62]->in[0] mux_1level_tapbuf_size2[62]->in[1] mux_1level_tapbuf_size2[62]->out sram[62]->outb sram[62]->out gvdd_mux_1level_tapbuf_size2[62] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[62], level=1, select_path_id=0. ***** -*****1***** -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -***** Signal mux_1level_tapbuf_size2[62]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[62]->in[0] mux_1level_tapbuf_size2[62]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[62]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[62]->in[1] mux_1level_tapbuf_size2[62]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[62] gvdd_mux_1level_tapbuf_size2[62] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[215] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[215] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[215] when v(mux_1level_tapbuf_size2[62]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[215] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[215] when v(mux_1level_tapbuf_size2[62]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[215] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[62]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[215] param='mux_1level_tapbuf_size2[62]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[62]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[62]_energy_per_cycle param='mux_1level_tapbuf_size2[62]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[215] param='mux_1level_tapbuf_size2[62]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[215] param='dynamic_power_sb_mux[0][0]_rrnode[215]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[215] avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='start_rise_sb_mux[0][0]_rrnode[215]' to='start_rise_sb_mux[0][0]_rrnode[215]+switch_rise_sb_mux[0][0]_rrnode[215]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[215] avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='start_fall_sb_mux[0][0]_rrnode[215]' to='start_fall_sb_mux[0][0]_rrnode[215]+switch_fall_sb_mux[0][0]_rrnode[215]' -.meas tran sum_leakage_power_mux[0to62] -+ param='sum_leakage_power_mux[0to61]+leakage_sb_mux[0][0]_rrnode[215]' -.meas tran sum_energy_per_cycle_mux[0to62] -+ param='sum_energy_per_cycle_mux[0to61]+energy_per_cycle_sb_mux[0][0]_rrnode[215]' -***** Load for rr_node[215] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=24, type=4 ***** -Xchan_mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[241]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to62] -+ param='sum_leakage_power_sb_mux[0to61]+leakage_sb_mux[0][0]_rrnode[215]' -.meas tran sum_energy_per_cycle_sb_mux[0to62] -+ param='sum_energy_per_cycle_sb_mux[0to61]+energy_per_cycle_sb_mux[0][0]_rrnode[215]' -Xmux_1level_tapbuf_size2[63] mux_1level_tapbuf_size2[63]->in[0] mux_1level_tapbuf_size2[63]->in[1] mux_1level_tapbuf_size2[63]->out sram[63]->outb sram[63]->out gvdd_mux_1level_tapbuf_size2[63] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[63], level=1, select_path_id=0. ***** -*****1***** -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -***** Signal mux_1level_tapbuf_size2[63]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[63]->in[0] mux_1level_tapbuf_size2[63]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[63]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[63]->in[1] mux_1level_tapbuf_size2[63]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[63] gvdd_mux_1level_tapbuf_size2[63] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[217] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[217] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[217] when v(mux_1level_tapbuf_size2[63]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[217] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[217] when v(mux_1level_tapbuf_size2[63]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[217] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[63]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[217] param='mux_1level_tapbuf_size2[63]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[63]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[63]_energy_per_cycle param='mux_1level_tapbuf_size2[63]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[217] param='mux_1level_tapbuf_size2[63]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[217] param='dynamic_power_sb_mux[0][0]_rrnode[217]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[217] avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='start_rise_sb_mux[0][0]_rrnode[217]' to='start_rise_sb_mux[0][0]_rrnode[217]+switch_rise_sb_mux[0][0]_rrnode[217]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[217] avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='start_fall_sb_mux[0][0]_rrnode[217]' to='start_fall_sb_mux[0][0]_rrnode[217]+switch_fall_sb_mux[0][0]_rrnode[217]' -.meas tran sum_leakage_power_mux[0to63] -+ param='sum_leakage_power_mux[0to62]+leakage_sb_mux[0][0]_rrnode[217]' -.meas tran sum_energy_per_cycle_mux[0to63] -+ param='sum_energy_per_cycle_mux[0to62]+energy_per_cycle_sb_mux[0][0]_rrnode[217]' -***** Load for rr_node[217] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=26, type=4 ***** -Xchan_mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[245]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to63] -+ param='sum_leakage_power_sb_mux[0to62]+leakage_sb_mux[0][0]_rrnode[217]' -.meas tran sum_energy_per_cycle_sb_mux[0to63] -+ param='sum_energy_per_cycle_sb_mux[0to62]+energy_per_cycle_sb_mux[0][0]_rrnode[217]' -Xmux_1level_tapbuf_size2[64] mux_1level_tapbuf_size2[64]->in[0] mux_1level_tapbuf_size2[64]->in[1] mux_1level_tapbuf_size2[64]->out sram[64]->outb sram[64]->out gvdd_mux_1level_tapbuf_size2[64] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[64], level=1, select_path_id=0. ***** -*****1***** -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -***** Signal mux_1level_tapbuf_size2[64]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[64]->in[0] mux_1level_tapbuf_size2[64]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[64]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[64]->in[1] mux_1level_tapbuf_size2[64]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[64] gvdd_mux_1level_tapbuf_size2[64] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[219] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[219] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[219] when v(mux_1level_tapbuf_size2[64]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[219] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[219] when v(mux_1level_tapbuf_size2[64]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[219] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[64]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[219] param='mux_1level_tapbuf_size2[64]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[64]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[64]_energy_per_cycle param='mux_1level_tapbuf_size2[64]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[219] param='mux_1level_tapbuf_size2[64]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[219] param='dynamic_power_sb_mux[0][0]_rrnode[219]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[219] avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='start_rise_sb_mux[0][0]_rrnode[219]' to='start_rise_sb_mux[0][0]_rrnode[219]+switch_rise_sb_mux[0][0]_rrnode[219]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[219] avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='start_fall_sb_mux[0][0]_rrnode[219]' to='start_fall_sb_mux[0][0]_rrnode[219]+switch_fall_sb_mux[0][0]_rrnode[219]' -.meas tran sum_leakage_power_mux[0to64] -+ param='sum_leakage_power_mux[0to63]+leakage_sb_mux[0][0]_rrnode[219]' -.meas tran sum_energy_per_cycle_mux[0to64] -+ param='sum_energy_per_cycle_mux[0to63]+energy_per_cycle_sb_mux[0][0]_rrnode[219]' -***** Load for rr_node[219] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=28, type=4 ***** -Xchan_mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[248]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to64] -+ param='sum_leakage_power_sb_mux[0to63]+leakage_sb_mux[0][0]_rrnode[219]' -.meas tran sum_energy_per_cycle_sb_mux[0to64] -+ param='sum_energy_per_cycle_sb_mux[0to63]+energy_per_cycle_sb_mux[0][0]_rrnode[219]' -Xmux_1level_tapbuf_size2[65] mux_1level_tapbuf_size2[65]->in[0] mux_1level_tapbuf_size2[65]->in[1] mux_1level_tapbuf_size2[65]->out sram[65]->outb sram[65]->out gvdd_mux_1level_tapbuf_size2[65] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[65], level=1, select_path_id=0. ***** -*****1***** -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -***** Signal mux_1level_tapbuf_size2[65]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[65]->in[0] mux_1level_tapbuf_size2[65]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[65]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[65]->in[1] mux_1level_tapbuf_size2[65]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[65] gvdd_mux_1level_tapbuf_size2[65] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[221] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[221] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[221] when v(mux_1level_tapbuf_size2[65]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[221] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[221] when v(mux_1level_tapbuf_size2[65]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[221] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[65]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[221] param='mux_1level_tapbuf_size2[65]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[65]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[65]_energy_per_cycle param='mux_1level_tapbuf_size2[65]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[221] param='mux_1level_tapbuf_size2[65]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[221] param='dynamic_power_sb_mux[0][0]_rrnode[221]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[221] avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='start_rise_sb_mux[0][0]_rrnode[221]' to='start_rise_sb_mux[0][0]_rrnode[221]+switch_rise_sb_mux[0][0]_rrnode[221]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[221] avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='start_fall_sb_mux[0][0]_rrnode[221]' to='start_fall_sb_mux[0][0]_rrnode[221]+switch_fall_sb_mux[0][0]_rrnode[221]' -.meas tran sum_leakage_power_mux[0to65] -+ param='sum_leakage_power_mux[0to64]+leakage_sb_mux[0][0]_rrnode[221]' -.meas tran sum_energy_per_cycle_mux[0to65] -+ param='sum_energy_per_cycle_mux[0to64]+energy_per_cycle_sb_mux[0][0]_rrnode[221]' -***** Load for rr_node[221] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=30, type=4 ***** -Xchan_mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[253]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to65] -+ param='sum_leakage_power_sb_mux[0to64]+leakage_sb_mux[0][0]_rrnode[221]' -.meas tran sum_energy_per_cycle_sb_mux[0to65] -+ param='sum_energy_per_cycle_sb_mux[0to64]+energy_per_cycle_sb_mux[0][0]_rrnode[221]' -Xmux_1level_tapbuf_size2[66] mux_1level_tapbuf_size2[66]->in[0] mux_1level_tapbuf_size2[66]->in[1] mux_1level_tapbuf_size2[66]->out sram[66]->outb sram[66]->out gvdd_mux_1level_tapbuf_size2[66] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[66], level=1, select_path_id=0. ***** -*****1***** -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -***** Signal mux_1level_tapbuf_size2[66]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[66]->in[0] mux_1level_tapbuf_size2[66]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[66]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[66]->in[1] mux_1level_tapbuf_size2[66]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[66] gvdd_mux_1level_tapbuf_size2[66] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[223] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[223] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[223] when v(mux_1level_tapbuf_size2[66]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[223] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[223] when v(mux_1level_tapbuf_size2[66]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[223] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[66]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[223] param='mux_1level_tapbuf_size2[66]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[66]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[66]_energy_per_cycle param='mux_1level_tapbuf_size2[66]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[223] param='mux_1level_tapbuf_size2[66]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[223] param='dynamic_power_sb_mux[0][0]_rrnode[223]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[223] avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='start_rise_sb_mux[0][0]_rrnode[223]' to='start_rise_sb_mux[0][0]_rrnode[223]+switch_rise_sb_mux[0][0]_rrnode[223]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[223] avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='start_fall_sb_mux[0][0]_rrnode[223]' to='start_fall_sb_mux[0][0]_rrnode[223]+switch_fall_sb_mux[0][0]_rrnode[223]' -.meas tran sum_leakage_power_mux[0to66] -+ param='sum_leakage_power_mux[0to65]+leakage_sb_mux[0][0]_rrnode[223]' -.meas tran sum_energy_per_cycle_mux[0to66] -+ param='sum_energy_per_cycle_mux[0to65]+energy_per_cycle_sb_mux[0][0]_rrnode[223]' -***** Load for rr_node[223] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=32, type=4 ***** -Xchan_mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[257]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to66] -+ param='sum_leakage_power_sb_mux[0to65]+leakage_sb_mux[0][0]_rrnode[223]' -.meas tran sum_energy_per_cycle_sb_mux[0to66] -+ param='sum_energy_per_cycle_sb_mux[0to65]+energy_per_cycle_sb_mux[0][0]_rrnode[223]' -Xmux_1level_tapbuf_size2[67] mux_1level_tapbuf_size2[67]->in[0] mux_1level_tapbuf_size2[67]->in[1] mux_1level_tapbuf_size2[67]->out sram[67]->outb sram[67]->out gvdd_mux_1level_tapbuf_size2[67] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[67], level=1, select_path_id=0. ***** -*****1***** -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -***** Signal mux_1level_tapbuf_size2[67]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[67]->in[0] mux_1level_tapbuf_size2[67]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[67]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[67]->in[1] mux_1level_tapbuf_size2[67]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[67] gvdd_mux_1level_tapbuf_size2[67] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[225] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[225] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[225] when v(mux_1level_tapbuf_size2[67]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[225] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[225] when v(mux_1level_tapbuf_size2[67]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[225] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[67]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[225] param='mux_1level_tapbuf_size2[67]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[67]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[67]_energy_per_cycle param='mux_1level_tapbuf_size2[67]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[225] param='mux_1level_tapbuf_size2[67]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[225] param='dynamic_power_sb_mux[0][0]_rrnode[225]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[225] avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='start_rise_sb_mux[0][0]_rrnode[225]' to='start_rise_sb_mux[0][0]_rrnode[225]+switch_rise_sb_mux[0][0]_rrnode[225]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[225] avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='start_fall_sb_mux[0][0]_rrnode[225]' to='start_fall_sb_mux[0][0]_rrnode[225]+switch_fall_sb_mux[0][0]_rrnode[225]' -.meas tran sum_leakage_power_mux[0to67] -+ param='sum_leakage_power_mux[0to66]+leakage_sb_mux[0][0]_rrnode[225]' -.meas tran sum_energy_per_cycle_mux[0to67] -+ param='sum_energy_per_cycle_mux[0to66]+energy_per_cycle_sb_mux[0][0]_rrnode[225]' -***** Load for rr_node[225] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=34, type=4 ***** -Xchan_mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[260]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to67] -+ param='sum_leakage_power_sb_mux[0to66]+leakage_sb_mux[0][0]_rrnode[225]' -.meas tran sum_energy_per_cycle_sb_mux[0to67] -+ param='sum_energy_per_cycle_sb_mux[0to66]+energy_per_cycle_sb_mux[0][0]_rrnode[225]' -Xmux_1level_tapbuf_size2[68] mux_1level_tapbuf_size2[68]->in[0] mux_1level_tapbuf_size2[68]->in[1] mux_1level_tapbuf_size2[68]->out sram[68]->outb sram[68]->out gvdd_mux_1level_tapbuf_size2[68] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[68], level=1, select_path_id=0. ***** -*****1***** -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -***** Signal mux_1level_tapbuf_size2[68]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[68]->in[0] mux_1level_tapbuf_size2[68]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[68]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[68]->in[1] mux_1level_tapbuf_size2[68]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[68] gvdd_mux_1level_tapbuf_size2[68] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[227] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[227] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[227] when v(mux_1level_tapbuf_size2[68]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[227] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[227] when v(mux_1level_tapbuf_size2[68]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[227] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[68]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[227] param='mux_1level_tapbuf_size2[68]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[68]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[68]_energy_per_cycle param='mux_1level_tapbuf_size2[68]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[227] param='mux_1level_tapbuf_size2[68]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[227] param='dynamic_power_sb_mux[0][0]_rrnode[227]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[227] avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='start_rise_sb_mux[0][0]_rrnode[227]' to='start_rise_sb_mux[0][0]_rrnode[227]+switch_rise_sb_mux[0][0]_rrnode[227]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[227] avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='start_fall_sb_mux[0][0]_rrnode[227]' to='start_fall_sb_mux[0][0]_rrnode[227]+switch_fall_sb_mux[0][0]_rrnode[227]' -.meas tran sum_leakage_power_mux[0to68] -+ param='sum_leakage_power_mux[0to67]+leakage_sb_mux[0][0]_rrnode[227]' -.meas tran sum_energy_per_cycle_mux[0to68] -+ param='sum_energy_per_cycle_mux[0to67]+energy_per_cycle_sb_mux[0][0]_rrnode[227]' -***** Load for rr_node[227] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=36, type=4 ***** -Xchan_mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[265]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to68] -+ param='sum_leakage_power_sb_mux[0to67]+leakage_sb_mux[0][0]_rrnode[227]' -.meas tran sum_energy_per_cycle_sb_mux[0to68] -+ param='sum_energy_per_cycle_sb_mux[0to67]+energy_per_cycle_sb_mux[0][0]_rrnode[227]' -Xmux_1level_tapbuf_size2[69] mux_1level_tapbuf_size2[69]->in[0] mux_1level_tapbuf_size2[69]->in[1] mux_1level_tapbuf_size2[69]->out sram[69]->outb sram[69]->out gvdd_mux_1level_tapbuf_size2[69] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[69], level=1, select_path_id=0. ***** -*****1***** -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -***** Signal mux_1level_tapbuf_size2[69]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[69]->in[0] mux_1level_tapbuf_size2[69]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[69]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[69]->in[1] mux_1level_tapbuf_size2[69]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[69] gvdd_mux_1level_tapbuf_size2[69] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[229] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[229] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[229] when v(mux_1level_tapbuf_size2[69]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[229] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[229] when v(mux_1level_tapbuf_size2[69]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[229] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[69]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[229] param='mux_1level_tapbuf_size2[69]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[69]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[69]_energy_per_cycle param='mux_1level_tapbuf_size2[69]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[229] param='mux_1level_tapbuf_size2[69]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[229] param='dynamic_power_sb_mux[0][0]_rrnode[229]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[229] avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='start_rise_sb_mux[0][0]_rrnode[229]' to='start_rise_sb_mux[0][0]_rrnode[229]+switch_rise_sb_mux[0][0]_rrnode[229]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[229] avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='start_fall_sb_mux[0][0]_rrnode[229]' to='start_fall_sb_mux[0][0]_rrnode[229]+switch_fall_sb_mux[0][0]_rrnode[229]' -.meas tran sum_leakage_power_mux[0to69] -+ param='sum_leakage_power_mux[0to68]+leakage_sb_mux[0][0]_rrnode[229]' -.meas tran sum_energy_per_cycle_mux[0to69] -+ param='sum_energy_per_cycle_mux[0to68]+energy_per_cycle_sb_mux[0][0]_rrnode[229]' -***** Load for rr_node[229] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=38, type=4 ***** -Xchan_mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[268]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to69] -+ param='sum_leakage_power_sb_mux[0to68]+leakage_sb_mux[0][0]_rrnode[229]' -.meas tran sum_energy_per_cycle_sb_mux[0to69] -+ param='sum_energy_per_cycle_sb_mux[0to68]+energy_per_cycle_sb_mux[0][0]_rrnode[229]' -Xmux_1level_tapbuf_size2[70] mux_1level_tapbuf_size2[70]->in[0] mux_1level_tapbuf_size2[70]->in[1] mux_1level_tapbuf_size2[70]->out sram[70]->outb sram[70]->out gvdd_mux_1level_tapbuf_size2[70] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[70], level=1, select_path_id=0. ***** -*****1***** -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -***** Signal mux_1level_tapbuf_size2[70]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[70]->in[0] mux_1level_tapbuf_size2[70]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[70]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[70]->in[1] mux_1level_tapbuf_size2[70]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[70] gvdd_mux_1level_tapbuf_size2[70] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[231] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[231] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[231] when v(mux_1level_tapbuf_size2[70]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[231] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[231] when v(mux_1level_tapbuf_size2[70]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[231] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[70]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[231] param='mux_1level_tapbuf_size2[70]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[70]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[70]_energy_per_cycle param='mux_1level_tapbuf_size2[70]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[231] param='mux_1level_tapbuf_size2[70]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[231] param='dynamic_power_sb_mux[0][0]_rrnode[231]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[231] avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='start_rise_sb_mux[0][0]_rrnode[231]' to='start_rise_sb_mux[0][0]_rrnode[231]+switch_rise_sb_mux[0][0]_rrnode[231]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[231] avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='start_fall_sb_mux[0][0]_rrnode[231]' to='start_fall_sb_mux[0][0]_rrnode[231]+switch_fall_sb_mux[0][0]_rrnode[231]' -.meas tran sum_leakage_power_mux[0to70] -+ param='sum_leakage_power_mux[0to69]+leakage_sb_mux[0][0]_rrnode[231]' -.meas tran sum_energy_per_cycle_mux[0to70] -+ param='sum_energy_per_cycle_mux[0to69]+energy_per_cycle_sb_mux[0][0]_rrnode[231]' -***** Load for rr_node[231] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=40, type=4 ***** -Xchan_mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[272]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to70] -+ param='sum_leakage_power_sb_mux[0to69]+leakage_sb_mux[0][0]_rrnode[231]' -.meas tran sum_energy_per_cycle_sb_mux[0to70] -+ param='sum_energy_per_cycle_sb_mux[0to69]+energy_per_cycle_sb_mux[0][0]_rrnode[231]' -Xmux_1level_tapbuf_size2[71] mux_1level_tapbuf_size2[71]->in[0] mux_1level_tapbuf_size2[71]->in[1] mux_1level_tapbuf_size2[71]->out sram[71]->outb sram[71]->out gvdd_mux_1level_tapbuf_size2[71] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[71], level=1, select_path_id=0. ***** -*****1***** -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -***** Signal mux_1level_tapbuf_size2[71]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[71]->in[0] mux_1level_tapbuf_size2[71]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[71]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[71]->in[1] mux_1level_tapbuf_size2[71]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[71] gvdd_mux_1level_tapbuf_size2[71] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[233] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[233] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[233] when v(mux_1level_tapbuf_size2[71]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[233] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[233] when v(mux_1level_tapbuf_size2[71]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[233] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[71]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[233] param='mux_1level_tapbuf_size2[71]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[71]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[71]_energy_per_cycle param='mux_1level_tapbuf_size2[71]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[233] param='mux_1level_tapbuf_size2[71]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[233] param='dynamic_power_sb_mux[0][0]_rrnode[233]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[233] avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='start_rise_sb_mux[0][0]_rrnode[233]' to='start_rise_sb_mux[0][0]_rrnode[233]+switch_rise_sb_mux[0][0]_rrnode[233]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[233] avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='start_fall_sb_mux[0][0]_rrnode[233]' to='start_fall_sb_mux[0][0]_rrnode[233]+switch_fall_sb_mux[0][0]_rrnode[233]' -.meas tran sum_leakage_power_mux[0to71] -+ param='sum_leakage_power_mux[0to70]+leakage_sb_mux[0][0]_rrnode[233]' -.meas tran sum_energy_per_cycle_mux[0to71] -+ param='sum_energy_per_cycle_mux[0to70]+energy_per_cycle_sb_mux[0][0]_rrnode[233]' -***** Load for rr_node[233] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=42, type=4 ***** -Xchan_mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[276]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to71] -+ param='sum_leakage_power_sb_mux[0to70]+leakage_sb_mux[0][0]_rrnode[233]' -.meas tran sum_energy_per_cycle_sb_mux[0to71] -+ param='sum_energy_per_cycle_sb_mux[0to70]+energy_per_cycle_sb_mux[0][0]_rrnode[233]' -Xmux_1level_tapbuf_size2[72] mux_1level_tapbuf_size2[72]->in[0] mux_1level_tapbuf_size2[72]->in[1] mux_1level_tapbuf_size2[72]->out sram[72]->outb sram[72]->out gvdd_mux_1level_tapbuf_size2[72] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[72], level=1, select_path_id=0. ***** -*****1***** -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -***** Signal mux_1level_tapbuf_size2[72]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[72]->in[0] mux_1level_tapbuf_size2[72]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[72]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[72]->in[1] mux_1level_tapbuf_size2[72]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[72] gvdd_mux_1level_tapbuf_size2[72] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[235] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[235] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[235] when v(mux_1level_tapbuf_size2[72]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[235] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[235] when v(mux_1level_tapbuf_size2[72]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[235] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[72]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[235] param='mux_1level_tapbuf_size2[72]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[72]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[72]_energy_per_cycle param='mux_1level_tapbuf_size2[72]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[235] param='mux_1level_tapbuf_size2[72]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[235] param='dynamic_power_sb_mux[0][0]_rrnode[235]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[235] avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='start_rise_sb_mux[0][0]_rrnode[235]' to='start_rise_sb_mux[0][0]_rrnode[235]+switch_rise_sb_mux[0][0]_rrnode[235]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[235] avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='start_fall_sb_mux[0][0]_rrnode[235]' to='start_fall_sb_mux[0][0]_rrnode[235]+switch_fall_sb_mux[0][0]_rrnode[235]' -.meas tran sum_leakage_power_mux[0to72] -+ param='sum_leakage_power_mux[0to71]+leakage_sb_mux[0][0]_rrnode[235]' -.meas tran sum_energy_per_cycle_mux[0to72] -+ param='sum_energy_per_cycle_mux[0to71]+energy_per_cycle_sb_mux[0][0]_rrnode[235]' -***** Load for rr_node[235] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=44, type=4 ***** -Xchan_mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[280]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to72] -+ param='sum_leakage_power_sb_mux[0to71]+leakage_sb_mux[0][0]_rrnode[235]' -.meas tran sum_energy_per_cycle_sb_mux[0to72] -+ param='sum_energy_per_cycle_sb_mux[0to71]+energy_per_cycle_sb_mux[0][0]_rrnode[235]' -Xmux_1level_tapbuf_size2[73] mux_1level_tapbuf_size2[73]->in[0] mux_1level_tapbuf_size2[73]->in[1] mux_1level_tapbuf_size2[73]->out sram[73]->outb sram[73]->out gvdd_mux_1level_tapbuf_size2[73] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[73], level=1, select_path_id=0. ***** -*****1***** -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -***** Signal mux_1level_tapbuf_size2[73]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[73]->in[0] mux_1level_tapbuf_size2[73]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[73]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[73]->in[1] mux_1level_tapbuf_size2[73]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[73] gvdd_mux_1level_tapbuf_size2[73] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[237] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[237] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[237] when v(mux_1level_tapbuf_size2[73]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[237] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[237] when v(mux_1level_tapbuf_size2[73]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[237] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[73]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[237] param='mux_1level_tapbuf_size2[73]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[73]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[73]_energy_per_cycle param='mux_1level_tapbuf_size2[73]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[237] param='mux_1level_tapbuf_size2[73]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[237] param='dynamic_power_sb_mux[0][0]_rrnode[237]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[237] avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='start_rise_sb_mux[0][0]_rrnode[237]' to='start_rise_sb_mux[0][0]_rrnode[237]+switch_rise_sb_mux[0][0]_rrnode[237]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[237] avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='start_fall_sb_mux[0][0]_rrnode[237]' to='start_fall_sb_mux[0][0]_rrnode[237]+switch_fall_sb_mux[0][0]_rrnode[237]' -.meas tran sum_leakage_power_mux[0to73] -+ param='sum_leakage_power_mux[0to72]+leakage_sb_mux[0][0]_rrnode[237]' -.meas tran sum_energy_per_cycle_mux[0to73] -+ param='sum_energy_per_cycle_mux[0to72]+energy_per_cycle_sb_mux[0][0]_rrnode[237]' -***** Load for rr_node[237] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=46, type=4 ***** -Xchan_mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[284]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to73] -+ param='sum_leakage_power_sb_mux[0to72]+leakage_sb_mux[0][0]_rrnode[237]' -.meas tran sum_energy_per_cycle_sb_mux[0to73] -+ param='sum_energy_per_cycle_sb_mux[0to72]+energy_per_cycle_sb_mux[0][0]_rrnode[237]' -Xmux_1level_tapbuf_size2[74] mux_1level_tapbuf_size2[74]->in[0] mux_1level_tapbuf_size2[74]->in[1] mux_1level_tapbuf_size2[74]->out sram[74]->outb sram[74]->out gvdd_mux_1level_tapbuf_size2[74] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[74], level=1, select_path_id=0. ***** -*****1***** -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -***** Signal mux_1level_tapbuf_size2[74]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[74]->in[0] mux_1level_tapbuf_size2[74]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[74]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[74]->in[1] mux_1level_tapbuf_size2[74]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[74] gvdd_mux_1level_tapbuf_size2[74] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[239] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[239] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[239] when v(mux_1level_tapbuf_size2[74]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[239] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[239] when v(mux_1level_tapbuf_size2[74]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[239] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[74]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[239] param='mux_1level_tapbuf_size2[74]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[74]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[74]_energy_per_cycle param='mux_1level_tapbuf_size2[74]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[239] param='mux_1level_tapbuf_size2[74]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[239] param='dynamic_power_sb_mux[0][0]_rrnode[239]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[239] avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='start_rise_sb_mux[0][0]_rrnode[239]' to='start_rise_sb_mux[0][0]_rrnode[239]+switch_rise_sb_mux[0][0]_rrnode[239]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[239] avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='start_fall_sb_mux[0][0]_rrnode[239]' to='start_fall_sb_mux[0][0]_rrnode[239]+switch_fall_sb_mux[0][0]_rrnode[239]' -.meas tran sum_leakage_power_mux[0to74] -+ param='sum_leakage_power_mux[0to73]+leakage_sb_mux[0][0]_rrnode[239]' -.meas tran sum_energy_per_cycle_mux[0to74] -+ param='sum_energy_per_cycle_mux[0to73]+energy_per_cycle_sb_mux[0][0]_rrnode[239]' -***** Load for rr_node[239] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=48, type=4 ***** -Xchan_mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[287]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to74] -+ param='sum_leakage_power_sb_mux[0to73]+leakage_sb_mux[0][0]_rrnode[239]' -.meas tran sum_energy_per_cycle_sb_mux[0to74] -+ param='sum_energy_per_cycle_sb_mux[0to73]+energy_per_cycle_sb_mux[0][0]_rrnode[239]' -Xmux_1level_tapbuf_size2[75] mux_1level_tapbuf_size2[75]->in[0] mux_1level_tapbuf_size2[75]->in[1] mux_1level_tapbuf_size2[75]->out sram[75]->outb sram[75]->out gvdd_mux_1level_tapbuf_size2[75] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[75], level=1, select_path_id=0. ***** -*****1***** -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -***** Signal mux_1level_tapbuf_size2[75]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[75]->in[0] mux_1level_tapbuf_size2[75]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[75]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[75]->in[1] mux_1level_tapbuf_size2[75]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[75] gvdd_mux_1level_tapbuf_size2[75] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[241] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[241] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[241] when v(mux_1level_tapbuf_size2[75]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[241] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[241] when v(mux_1level_tapbuf_size2[75]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[241] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[75]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[241] param='mux_1level_tapbuf_size2[75]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[75]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[75]_energy_per_cycle param='mux_1level_tapbuf_size2[75]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[241] param='mux_1level_tapbuf_size2[75]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[241] param='dynamic_power_sb_mux[0][0]_rrnode[241]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[241] avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='start_rise_sb_mux[0][0]_rrnode[241]' to='start_rise_sb_mux[0][0]_rrnode[241]+switch_rise_sb_mux[0][0]_rrnode[241]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[241] avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='start_fall_sb_mux[0][0]_rrnode[241]' to='start_fall_sb_mux[0][0]_rrnode[241]+switch_fall_sb_mux[0][0]_rrnode[241]' -.meas tran sum_leakage_power_mux[0to75] -+ param='sum_leakage_power_mux[0to74]+leakage_sb_mux[0][0]_rrnode[241]' -.meas tran sum_energy_per_cycle_mux[0to75] -+ param='sum_energy_per_cycle_mux[0to74]+energy_per_cycle_sb_mux[0][0]_rrnode[241]' -***** Load for rr_node[241] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=50, type=4 ***** -Xchan_mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[291]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to75] -+ param='sum_leakage_power_sb_mux[0to74]+leakage_sb_mux[0][0]_rrnode[241]' -.meas tran sum_energy_per_cycle_sb_mux[0to75] -+ param='sum_energy_per_cycle_sb_mux[0to74]+energy_per_cycle_sb_mux[0][0]_rrnode[241]' -Xmux_1level_tapbuf_size2[76] mux_1level_tapbuf_size2[76]->in[0] mux_1level_tapbuf_size2[76]->in[1] mux_1level_tapbuf_size2[76]->out sram[76]->outb sram[76]->out gvdd_mux_1level_tapbuf_size2[76] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[76], level=1, select_path_id=0. ***** -*****1***** -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -***** Signal mux_1level_tapbuf_size2[76]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[76]->in[0] mux_1level_tapbuf_size2[76]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[76]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[76]->in[1] mux_1level_tapbuf_size2[76]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[76] gvdd_mux_1level_tapbuf_size2[76] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[243] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[243] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[243] when v(mux_1level_tapbuf_size2[76]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[243] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[243] when v(mux_1level_tapbuf_size2[76]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[243] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[76]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[243] param='mux_1level_tapbuf_size2[76]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[76]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[76]_energy_per_cycle param='mux_1level_tapbuf_size2[76]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[243] param='mux_1level_tapbuf_size2[76]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[243] param='dynamic_power_sb_mux[0][0]_rrnode[243]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[243] avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='start_rise_sb_mux[0][0]_rrnode[243]' to='start_rise_sb_mux[0][0]_rrnode[243]+switch_rise_sb_mux[0][0]_rrnode[243]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[243] avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='start_fall_sb_mux[0][0]_rrnode[243]' to='start_fall_sb_mux[0][0]_rrnode[243]+switch_fall_sb_mux[0][0]_rrnode[243]' -.meas tran sum_leakage_power_mux[0to76] -+ param='sum_leakage_power_mux[0to75]+leakage_sb_mux[0][0]_rrnode[243]' -.meas tran sum_energy_per_cycle_mux[0to76] -+ param='sum_energy_per_cycle_mux[0to75]+energy_per_cycle_sb_mux[0][0]_rrnode[243]' -***** Load for rr_node[243] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=52, type=4 ***** -Xchan_mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[296]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to76] -+ param='sum_leakage_power_sb_mux[0to75]+leakage_sb_mux[0][0]_rrnode[243]' -.meas tran sum_energy_per_cycle_sb_mux[0to76] -+ param='sum_energy_per_cycle_sb_mux[0to75]+energy_per_cycle_sb_mux[0][0]_rrnode[243]' -Xmux_1level_tapbuf_size2[77] mux_1level_tapbuf_size2[77]->in[0] mux_1level_tapbuf_size2[77]->in[1] mux_1level_tapbuf_size2[77]->out sram[77]->outb sram[77]->out gvdd_mux_1level_tapbuf_size2[77] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[77], level=1, select_path_id=0. ***** -*****1***** -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -***** Signal mux_1level_tapbuf_size2[77]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[77]->in[0] mux_1level_tapbuf_size2[77]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[77]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[77]->in[1] mux_1level_tapbuf_size2[77]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[77] gvdd_mux_1level_tapbuf_size2[77] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[245] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[245] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[245] when v(mux_1level_tapbuf_size2[77]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[245] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[245] when v(mux_1level_tapbuf_size2[77]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[245] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[77]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[245] param='mux_1level_tapbuf_size2[77]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[77]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[77]_energy_per_cycle param='mux_1level_tapbuf_size2[77]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[245] param='mux_1level_tapbuf_size2[77]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[245] param='dynamic_power_sb_mux[0][0]_rrnode[245]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[245] avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='start_rise_sb_mux[0][0]_rrnode[245]' to='start_rise_sb_mux[0][0]_rrnode[245]+switch_rise_sb_mux[0][0]_rrnode[245]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[245] avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='start_fall_sb_mux[0][0]_rrnode[245]' to='start_fall_sb_mux[0][0]_rrnode[245]+switch_fall_sb_mux[0][0]_rrnode[245]' -.meas tran sum_leakage_power_mux[0to77] -+ param='sum_leakage_power_mux[0to76]+leakage_sb_mux[0][0]_rrnode[245]' -.meas tran sum_energy_per_cycle_mux[0to77] -+ param='sum_energy_per_cycle_mux[0to76]+energy_per_cycle_sb_mux[0][0]_rrnode[245]' -***** Load for rr_node[245] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=54, type=4 ***** -Xchan_mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[299]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[300]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to77] -+ param='sum_leakage_power_sb_mux[0to76]+leakage_sb_mux[0][0]_rrnode[245]' -.meas tran sum_energy_per_cycle_sb_mux[0to77] -+ param='sum_energy_per_cycle_sb_mux[0to76]+energy_per_cycle_sb_mux[0][0]_rrnode[245]' -Xmux_1level_tapbuf_size2[78] mux_1level_tapbuf_size2[78]->in[0] mux_1level_tapbuf_size2[78]->in[1] mux_1level_tapbuf_size2[78]->out sram[78]->outb sram[78]->out gvdd_mux_1level_tapbuf_size2[78] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[78], level=1, select_path_id=0. ***** -*****1***** -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -***** Signal mux_1level_tapbuf_size2[78]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[78]->in[0] mux_1level_tapbuf_size2[78]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[78]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[78]->in[1] mux_1level_tapbuf_size2[78]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[78] gvdd_mux_1level_tapbuf_size2[78] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[247] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[247] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[247] when v(mux_1level_tapbuf_size2[78]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[247] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[247] when v(mux_1level_tapbuf_size2[78]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[247] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[78]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[247] param='mux_1level_tapbuf_size2[78]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[78]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[78]_energy_per_cycle param='mux_1level_tapbuf_size2[78]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[247] param='mux_1level_tapbuf_size2[78]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[247] param='dynamic_power_sb_mux[0][0]_rrnode[247]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[247] avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='start_rise_sb_mux[0][0]_rrnode[247]' to='start_rise_sb_mux[0][0]_rrnode[247]+switch_rise_sb_mux[0][0]_rrnode[247]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[247] avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='start_fall_sb_mux[0][0]_rrnode[247]' to='start_fall_sb_mux[0][0]_rrnode[247]+switch_fall_sb_mux[0][0]_rrnode[247]' -.meas tran sum_leakage_power_mux[0to78] -+ param='sum_leakage_power_mux[0to77]+leakage_sb_mux[0][0]_rrnode[247]' -.meas tran sum_energy_per_cycle_mux[0to78] -+ param='sum_energy_per_cycle_mux[0to77]+energy_per_cycle_sb_mux[0][0]_rrnode[247]' -***** Load for rr_node[247] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=56, type=4 ***** -Xchan_mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[303]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to78] -+ param='sum_leakage_power_sb_mux[0to77]+leakage_sb_mux[0][0]_rrnode[247]' -.meas tran sum_energy_per_cycle_sb_mux[0to78] -+ param='sum_energy_per_cycle_sb_mux[0to77]+energy_per_cycle_sb_mux[0][0]_rrnode[247]' -Xmux_1level_tapbuf_size2[79] mux_1level_tapbuf_size2[79]->in[0] mux_1level_tapbuf_size2[79]->in[1] mux_1level_tapbuf_size2[79]->out sram[79]->outb sram[79]->out gvdd_mux_1level_tapbuf_size2[79] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[79], level=1, select_path_id=0. ***** -*****1***** -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -***** Signal mux_1level_tapbuf_size2[79]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[79]->in[0] mux_1level_tapbuf_size2[79]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[79]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[79]->in[1] mux_1level_tapbuf_size2[79]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[79] gvdd_mux_1level_tapbuf_size2[79] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[249] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[249] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[249] when v(mux_1level_tapbuf_size2[79]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[249] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[249] when v(mux_1level_tapbuf_size2[79]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[249] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[79]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[249] param='mux_1level_tapbuf_size2[79]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[79]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[79]_energy_per_cycle param='mux_1level_tapbuf_size2[79]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[249] param='mux_1level_tapbuf_size2[79]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[249] param='dynamic_power_sb_mux[0][0]_rrnode[249]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[249] avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='start_rise_sb_mux[0][0]_rrnode[249]' to='start_rise_sb_mux[0][0]_rrnode[249]+switch_rise_sb_mux[0][0]_rrnode[249]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[249] avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='start_fall_sb_mux[0][0]_rrnode[249]' to='start_fall_sb_mux[0][0]_rrnode[249]+switch_fall_sb_mux[0][0]_rrnode[249]' -.meas tran sum_leakage_power_mux[0to79] -+ param='sum_leakage_power_mux[0to78]+leakage_sb_mux[0][0]_rrnode[249]' -.meas tran sum_energy_per_cycle_mux[0to79] -+ param='sum_energy_per_cycle_mux[0to78]+energy_per_cycle_sb_mux[0][0]_rrnode[249]' -***** Load for rr_node[249] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=58, type=4 ***** -Xchan_mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[307]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to79] -+ param='sum_leakage_power_sb_mux[0to78]+leakage_sb_mux[0][0]_rrnode[249]' -.meas tran sum_energy_per_cycle_sb_mux[0to79] -+ param='sum_energy_per_cycle_sb_mux[0to78]+energy_per_cycle_sb_mux[0][0]_rrnode[249]' -Xmux_1level_tapbuf_size2[80] mux_1level_tapbuf_size2[80]->in[0] mux_1level_tapbuf_size2[80]->in[1] mux_1level_tapbuf_size2[80]->out sram[80]->outb sram[80]->out gvdd_mux_1level_tapbuf_size2[80] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[80], level=1, select_path_id=0. ***** -*****1***** -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -***** Signal mux_1level_tapbuf_size2[80]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[80]->in[0] mux_1level_tapbuf_size2[80]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[80]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[80]->in[1] mux_1level_tapbuf_size2[80]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[80] gvdd_mux_1level_tapbuf_size2[80] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[251] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[251] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[251] when v(mux_1level_tapbuf_size2[80]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[251] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[251] when v(mux_1level_tapbuf_size2[80]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[251] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[80]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[251] param='mux_1level_tapbuf_size2[80]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[80]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[80]_energy_per_cycle param='mux_1level_tapbuf_size2[80]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[251] param='mux_1level_tapbuf_size2[80]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[251] param='dynamic_power_sb_mux[0][0]_rrnode[251]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[251] avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='start_rise_sb_mux[0][0]_rrnode[251]' to='start_rise_sb_mux[0][0]_rrnode[251]+switch_rise_sb_mux[0][0]_rrnode[251]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[251] avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='start_fall_sb_mux[0][0]_rrnode[251]' to='start_fall_sb_mux[0][0]_rrnode[251]+switch_fall_sb_mux[0][0]_rrnode[251]' -.meas tran sum_leakage_power_mux[0to80] -+ param='sum_leakage_power_mux[0to79]+leakage_sb_mux[0][0]_rrnode[251]' -.meas tran sum_energy_per_cycle_mux[0to80] -+ param='sum_energy_per_cycle_mux[0to79]+energy_per_cycle_sb_mux[0][0]_rrnode[251]' -***** Load for rr_node[251] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=60, type=4 ***** -Xchan_mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[311]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to80] -+ param='sum_leakage_power_sb_mux[0to79]+leakage_sb_mux[0][0]_rrnode[251]' -.meas tran sum_energy_per_cycle_sb_mux[0to80] -+ param='sum_energy_per_cycle_sb_mux[0to79]+energy_per_cycle_sb_mux[0][0]_rrnode[251]' -Xmux_1level_tapbuf_size2[81] mux_1level_tapbuf_size2[81]->in[0] mux_1level_tapbuf_size2[81]->in[1] mux_1level_tapbuf_size2[81]->out sram[81]->outb sram[81]->out gvdd_mux_1level_tapbuf_size2[81] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[81], level=1, select_path_id=0. ***** -*****1***** -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -***** Signal mux_1level_tapbuf_size2[81]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[81]->in[0] mux_1level_tapbuf_size2[81]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[81]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[81]->in[1] mux_1level_tapbuf_size2[81]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[81] gvdd_mux_1level_tapbuf_size2[81] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[253] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[253] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[253] when v(mux_1level_tapbuf_size2[81]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[253] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[253] when v(mux_1level_tapbuf_size2[81]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[253] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[81]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[253] param='mux_1level_tapbuf_size2[81]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[81]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[81]_energy_per_cycle param='mux_1level_tapbuf_size2[81]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[253] param='mux_1level_tapbuf_size2[81]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[253] param='dynamic_power_sb_mux[0][0]_rrnode[253]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[253] avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='start_rise_sb_mux[0][0]_rrnode[253]' to='start_rise_sb_mux[0][0]_rrnode[253]+switch_rise_sb_mux[0][0]_rrnode[253]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[253] avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='start_fall_sb_mux[0][0]_rrnode[253]' to='start_fall_sb_mux[0][0]_rrnode[253]+switch_fall_sb_mux[0][0]_rrnode[253]' -.meas tran sum_leakage_power_mux[0to81] -+ param='sum_leakage_power_mux[0to80]+leakage_sb_mux[0][0]_rrnode[253]' -.meas tran sum_energy_per_cycle_mux[0to81] -+ param='sum_energy_per_cycle_mux[0to80]+energy_per_cycle_sb_mux[0][0]_rrnode[253]' -***** Load for rr_node[253] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=62, type=4 ***** -Xchan_mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[315]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to81] -+ param='sum_leakage_power_sb_mux[0to80]+leakage_sb_mux[0][0]_rrnode[253]' -.meas tran sum_energy_per_cycle_sb_mux[0to81] -+ param='sum_energy_per_cycle_sb_mux[0to80]+energy_per_cycle_sb_mux[0][0]_rrnode[253]' -Xmux_1level_tapbuf_size2[82] mux_1level_tapbuf_size2[82]->in[0] mux_1level_tapbuf_size2[82]->in[1] mux_1level_tapbuf_size2[82]->out sram[82]->outb sram[82]->out gvdd_mux_1level_tapbuf_size2[82] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[82], level=1, select_path_id=0. ***** -*****1***** -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -***** Signal mux_1level_tapbuf_size2[82]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[82]->in[0] mux_1level_tapbuf_size2[82]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[82]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[82]->in[1] mux_1level_tapbuf_size2[82]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[82] gvdd_mux_1level_tapbuf_size2[82] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[255] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[255] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[255] when v(mux_1level_tapbuf_size2[82]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[255] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[255] when v(mux_1level_tapbuf_size2[82]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[255] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[82]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[255] param='mux_1level_tapbuf_size2[82]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[82]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[82]_energy_per_cycle param='mux_1level_tapbuf_size2[82]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[255] param='mux_1level_tapbuf_size2[82]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[255] param='dynamic_power_sb_mux[0][0]_rrnode[255]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[255] avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='start_rise_sb_mux[0][0]_rrnode[255]' to='start_rise_sb_mux[0][0]_rrnode[255]+switch_rise_sb_mux[0][0]_rrnode[255]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[255] avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='start_fall_sb_mux[0][0]_rrnode[255]' to='start_fall_sb_mux[0][0]_rrnode[255]+switch_fall_sb_mux[0][0]_rrnode[255]' -.meas tran sum_leakage_power_mux[0to82] -+ param='sum_leakage_power_mux[0to81]+leakage_sb_mux[0][0]_rrnode[255]' -.meas tran sum_energy_per_cycle_mux[0to82] -+ param='sum_energy_per_cycle_mux[0to81]+energy_per_cycle_sb_mux[0][0]_rrnode[255]' -***** Load for rr_node[255] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=64, type=4 ***** -Xchan_mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[318]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to82] -+ param='sum_leakage_power_sb_mux[0to81]+leakage_sb_mux[0][0]_rrnode[255]' -.meas tran sum_energy_per_cycle_sb_mux[0to82] -+ param='sum_energy_per_cycle_sb_mux[0to81]+energy_per_cycle_sb_mux[0][0]_rrnode[255]' -Xmux_1level_tapbuf_size2[83] mux_1level_tapbuf_size2[83]->in[0] mux_1level_tapbuf_size2[83]->in[1] mux_1level_tapbuf_size2[83]->out sram[83]->outb sram[83]->out gvdd_mux_1level_tapbuf_size2[83] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[83], level=1, select_path_id=0. ***** -*****1***** -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -***** Signal mux_1level_tapbuf_size2[83]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[83]->in[0] mux_1level_tapbuf_size2[83]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[83]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[83]->in[1] mux_1level_tapbuf_size2[83]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[83] gvdd_mux_1level_tapbuf_size2[83] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[257] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[257] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[257] when v(mux_1level_tapbuf_size2[83]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[257] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[257] when v(mux_1level_tapbuf_size2[83]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[257] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[83]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[257] param='mux_1level_tapbuf_size2[83]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[83]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[83]_energy_per_cycle param='mux_1level_tapbuf_size2[83]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[257] param='mux_1level_tapbuf_size2[83]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[257] param='dynamic_power_sb_mux[0][0]_rrnode[257]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[257] avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='start_rise_sb_mux[0][0]_rrnode[257]' to='start_rise_sb_mux[0][0]_rrnode[257]+switch_rise_sb_mux[0][0]_rrnode[257]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[257] avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='start_fall_sb_mux[0][0]_rrnode[257]' to='start_fall_sb_mux[0][0]_rrnode[257]+switch_fall_sb_mux[0][0]_rrnode[257]' -.meas tran sum_leakage_power_mux[0to83] -+ param='sum_leakage_power_mux[0to82]+leakage_sb_mux[0][0]_rrnode[257]' -.meas tran sum_energy_per_cycle_mux[0to83] -+ param='sum_energy_per_cycle_mux[0to82]+energy_per_cycle_sb_mux[0][0]_rrnode[257]' -***** Load for rr_node[257] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=66, type=4 ***** -Xchan_mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[323]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to83] -+ param='sum_leakage_power_sb_mux[0to82]+leakage_sb_mux[0][0]_rrnode[257]' -.meas tran sum_energy_per_cycle_sb_mux[0to83] -+ param='sum_energy_per_cycle_sb_mux[0to82]+energy_per_cycle_sb_mux[0][0]_rrnode[257]' -Xmux_1level_tapbuf_size2[84] mux_1level_tapbuf_size2[84]->in[0] mux_1level_tapbuf_size2[84]->in[1] mux_1level_tapbuf_size2[84]->out sram[84]->outb sram[84]->out gvdd_mux_1level_tapbuf_size2[84] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[84], level=1, select_path_id=0. ***** -*****1***** -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -***** Signal mux_1level_tapbuf_size2[84]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[84]->in[0] mux_1level_tapbuf_size2[84]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[84]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[84]->in[1] mux_1level_tapbuf_size2[84]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[84] gvdd_mux_1level_tapbuf_size2[84] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[259] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[259] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[259] when v(mux_1level_tapbuf_size2[84]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[259] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[259] when v(mux_1level_tapbuf_size2[84]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[259] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[84]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[259] param='mux_1level_tapbuf_size2[84]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[84]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[84]_energy_per_cycle param='mux_1level_tapbuf_size2[84]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[259] param='mux_1level_tapbuf_size2[84]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[259] param='dynamic_power_sb_mux[0][0]_rrnode[259]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[259] avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='start_rise_sb_mux[0][0]_rrnode[259]' to='start_rise_sb_mux[0][0]_rrnode[259]+switch_rise_sb_mux[0][0]_rrnode[259]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[259] avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='start_fall_sb_mux[0][0]_rrnode[259]' to='start_fall_sb_mux[0][0]_rrnode[259]+switch_fall_sb_mux[0][0]_rrnode[259]' -.meas tran sum_leakage_power_mux[0to84] -+ param='sum_leakage_power_mux[0to83]+leakage_sb_mux[0][0]_rrnode[259]' -.meas tran sum_energy_per_cycle_mux[0to84] -+ param='sum_energy_per_cycle_mux[0to83]+energy_per_cycle_sb_mux[0][0]_rrnode[259]' -***** Load for rr_node[259] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=68, type=4 ***** -Xchan_mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[326]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to84] -+ param='sum_leakage_power_sb_mux[0to83]+leakage_sb_mux[0][0]_rrnode[259]' -.meas tran sum_energy_per_cycle_sb_mux[0to84] -+ param='sum_energy_per_cycle_sb_mux[0to83]+energy_per_cycle_sb_mux[0][0]_rrnode[259]' -Xmux_1level_tapbuf_size2[85] mux_1level_tapbuf_size2[85]->in[0] mux_1level_tapbuf_size2[85]->in[1] mux_1level_tapbuf_size2[85]->out sram[85]->outb sram[85]->out gvdd_mux_1level_tapbuf_size2[85] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[85], level=1, select_path_id=0. ***** -*****1***** -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -***** Signal mux_1level_tapbuf_size2[85]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[85]->in[0] mux_1level_tapbuf_size2[85]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[85]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[85]->in[1] mux_1level_tapbuf_size2[85]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[85] gvdd_mux_1level_tapbuf_size2[85] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[261] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[261] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[261] when v(mux_1level_tapbuf_size2[85]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[261] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[261] when v(mux_1level_tapbuf_size2[85]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[261] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[85]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[261] param='mux_1level_tapbuf_size2[85]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[85]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[85]_energy_per_cycle param='mux_1level_tapbuf_size2[85]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[261] param='mux_1level_tapbuf_size2[85]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[261] param='dynamic_power_sb_mux[0][0]_rrnode[261]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[261] avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='start_rise_sb_mux[0][0]_rrnode[261]' to='start_rise_sb_mux[0][0]_rrnode[261]+switch_rise_sb_mux[0][0]_rrnode[261]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[261] avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='start_fall_sb_mux[0][0]_rrnode[261]' to='start_fall_sb_mux[0][0]_rrnode[261]+switch_fall_sb_mux[0][0]_rrnode[261]' -.meas tran sum_leakage_power_mux[0to85] -+ param='sum_leakage_power_mux[0to84]+leakage_sb_mux[0][0]_rrnode[261]' -.meas tran sum_energy_per_cycle_mux[0to85] -+ param='sum_energy_per_cycle_mux[0to84]+energy_per_cycle_sb_mux[0][0]_rrnode[261]' -***** Load for rr_node[261] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=70, type=4 ***** -Xchan_mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[330]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[333]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to85] -+ param='sum_leakage_power_sb_mux[0to84]+leakage_sb_mux[0][0]_rrnode[261]' -.meas tran sum_energy_per_cycle_sb_mux[0to85] -+ param='sum_energy_per_cycle_sb_mux[0to84]+energy_per_cycle_sb_mux[0][0]_rrnode[261]' -Xmux_1level_tapbuf_size2[86] mux_1level_tapbuf_size2[86]->in[0] mux_1level_tapbuf_size2[86]->in[1] mux_1level_tapbuf_size2[86]->out sram[86]->outb sram[86]->out gvdd_mux_1level_tapbuf_size2[86] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[86], level=1, select_path_id=0. ***** -*****1***** -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -***** Signal mux_1level_tapbuf_size2[86]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[86]->in[0] mux_1level_tapbuf_size2[86]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[86]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[86]->in[1] mux_1level_tapbuf_size2[86]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[86] gvdd_mux_1level_tapbuf_size2[86] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[263] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[263] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[263] when v(mux_1level_tapbuf_size2[86]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[263] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[263] when v(mux_1level_tapbuf_size2[86]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[263] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[86]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[263] param='mux_1level_tapbuf_size2[86]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[86]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[86]_energy_per_cycle param='mux_1level_tapbuf_size2[86]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[263] param='mux_1level_tapbuf_size2[86]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[263] param='dynamic_power_sb_mux[0][0]_rrnode[263]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[263] avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='start_rise_sb_mux[0][0]_rrnode[263]' to='start_rise_sb_mux[0][0]_rrnode[263]+switch_rise_sb_mux[0][0]_rrnode[263]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[263] avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='start_fall_sb_mux[0][0]_rrnode[263]' to='start_fall_sb_mux[0][0]_rrnode[263]+switch_fall_sb_mux[0][0]_rrnode[263]' -.meas tran sum_leakage_power_mux[0to86] -+ param='sum_leakage_power_mux[0to85]+leakage_sb_mux[0][0]_rrnode[263]' -.meas tran sum_energy_per_cycle_mux[0to86] -+ param='sum_energy_per_cycle_mux[0to85]+energy_per_cycle_sb_mux[0][0]_rrnode[263]' -***** Load for rr_node[263] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=72, type=4 ***** -Xchan_mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[335]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to86] -+ param='sum_leakage_power_sb_mux[0to85]+leakage_sb_mux[0][0]_rrnode[263]' -.meas tran sum_energy_per_cycle_sb_mux[0to86] -+ param='sum_energy_per_cycle_sb_mux[0to85]+energy_per_cycle_sb_mux[0][0]_rrnode[263]' -Xmux_1level_tapbuf_size2[87] mux_1level_tapbuf_size2[87]->in[0] mux_1level_tapbuf_size2[87]->in[1] mux_1level_tapbuf_size2[87]->out sram[87]->outb sram[87]->out gvdd_mux_1level_tapbuf_size2[87] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[87], level=1, select_path_id=0. ***** -*****1***** -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -***** Signal mux_1level_tapbuf_size2[87]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[87]->in[0] mux_1level_tapbuf_size2[87]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[87]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[87]->in[1] mux_1level_tapbuf_size2[87]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[87] gvdd_mux_1level_tapbuf_size2[87] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[265] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[265] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[265] when v(mux_1level_tapbuf_size2[87]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[265] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[265] when v(mux_1level_tapbuf_size2[87]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[265] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[87]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[265] param='mux_1level_tapbuf_size2[87]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[87]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[87]_energy_per_cycle param='mux_1level_tapbuf_size2[87]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[265] param='mux_1level_tapbuf_size2[87]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[265] param='dynamic_power_sb_mux[0][0]_rrnode[265]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[265] avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='start_rise_sb_mux[0][0]_rrnode[265]' to='start_rise_sb_mux[0][0]_rrnode[265]+switch_rise_sb_mux[0][0]_rrnode[265]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[265] avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='start_fall_sb_mux[0][0]_rrnode[265]' to='start_fall_sb_mux[0][0]_rrnode[265]+switch_fall_sb_mux[0][0]_rrnode[265]' -.meas tran sum_leakage_power_mux[0to87] -+ param='sum_leakage_power_mux[0to86]+leakage_sb_mux[0][0]_rrnode[265]' -.meas tran sum_energy_per_cycle_mux[0to87] -+ param='sum_energy_per_cycle_mux[0to86]+energy_per_cycle_sb_mux[0][0]_rrnode[265]' -***** Load for rr_node[265] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=74, type=4 ***** -Xchan_mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[338]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to87] -+ param='sum_leakage_power_sb_mux[0to86]+leakage_sb_mux[0][0]_rrnode[265]' -.meas tran sum_energy_per_cycle_sb_mux[0to87] -+ param='sum_energy_per_cycle_sb_mux[0to86]+energy_per_cycle_sb_mux[0][0]_rrnode[265]' -Xmux_1level_tapbuf_size2[88] mux_1level_tapbuf_size2[88]->in[0] mux_1level_tapbuf_size2[88]->in[1] mux_1level_tapbuf_size2[88]->out sram[88]->outb sram[88]->out gvdd_mux_1level_tapbuf_size2[88] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[88], level=1, select_path_id=0. ***** -*****1***** -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -***** Signal mux_1level_tapbuf_size2[88]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[88]->in[0] mux_1level_tapbuf_size2[88]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[88]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[88]->in[1] mux_1level_tapbuf_size2[88]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[88] gvdd_mux_1level_tapbuf_size2[88] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[267] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[267] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[267] when v(mux_1level_tapbuf_size2[88]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[267] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[267] when v(mux_1level_tapbuf_size2[88]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[267] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[88]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[267] param='mux_1level_tapbuf_size2[88]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[88]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[88]_energy_per_cycle param='mux_1level_tapbuf_size2[88]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[267] param='mux_1level_tapbuf_size2[88]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[267] param='dynamic_power_sb_mux[0][0]_rrnode[267]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[267] avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='start_rise_sb_mux[0][0]_rrnode[267]' to='start_rise_sb_mux[0][0]_rrnode[267]+switch_rise_sb_mux[0][0]_rrnode[267]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[267] avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='start_fall_sb_mux[0][0]_rrnode[267]' to='start_fall_sb_mux[0][0]_rrnode[267]+switch_fall_sb_mux[0][0]_rrnode[267]' -.meas tran sum_leakage_power_mux[0to88] -+ param='sum_leakage_power_mux[0to87]+leakage_sb_mux[0][0]_rrnode[267]' -.meas tran sum_energy_per_cycle_mux[0to88] -+ param='sum_energy_per_cycle_mux[0to87]+energy_per_cycle_sb_mux[0][0]_rrnode[267]' -***** Load for rr_node[267] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=76, type=4 ***** -Xchan_mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[342]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to88] -+ param='sum_leakage_power_sb_mux[0to87]+leakage_sb_mux[0][0]_rrnode[267]' -.meas tran sum_energy_per_cycle_sb_mux[0to88] -+ param='sum_energy_per_cycle_sb_mux[0to87]+energy_per_cycle_sb_mux[0][0]_rrnode[267]' -Xmux_1level_tapbuf_size2[89] mux_1level_tapbuf_size2[89]->in[0] mux_1level_tapbuf_size2[89]->in[1] mux_1level_tapbuf_size2[89]->out sram[89]->outb sram[89]->out gvdd_mux_1level_tapbuf_size2[89] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[89], level=1, select_path_id=0. ***** -*****1***** -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -***** Signal mux_1level_tapbuf_size2[89]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[89]->in[0] mux_1level_tapbuf_size2[89]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[89]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[89]->in[1] mux_1level_tapbuf_size2[89]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[89] gvdd_mux_1level_tapbuf_size2[89] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[269] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[269] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[269] when v(mux_1level_tapbuf_size2[89]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[269] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[269] when v(mux_1level_tapbuf_size2[89]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[269] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[89]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[269] param='mux_1level_tapbuf_size2[89]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[89]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[89]_energy_per_cycle param='mux_1level_tapbuf_size2[89]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[269] param='mux_1level_tapbuf_size2[89]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[269] param='dynamic_power_sb_mux[0][0]_rrnode[269]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[269] avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='start_rise_sb_mux[0][0]_rrnode[269]' to='start_rise_sb_mux[0][0]_rrnode[269]+switch_rise_sb_mux[0][0]_rrnode[269]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[269] avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='start_fall_sb_mux[0][0]_rrnode[269]' to='start_fall_sb_mux[0][0]_rrnode[269]+switch_fall_sb_mux[0][0]_rrnode[269]' -.meas tran sum_leakage_power_mux[0to89] -+ param='sum_leakage_power_mux[0to88]+leakage_sb_mux[0][0]_rrnode[269]' -.meas tran sum_energy_per_cycle_mux[0to89] -+ param='sum_energy_per_cycle_mux[0to88]+energy_per_cycle_sb_mux[0][0]_rrnode[269]' -***** Load for rr_node[269] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=78, type=4 ***** -Xchan_mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[345]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to89] -+ param='sum_leakage_power_sb_mux[0to88]+leakage_sb_mux[0][0]_rrnode[269]' -.meas tran sum_energy_per_cycle_sb_mux[0to89] -+ param='sum_energy_per_cycle_sb_mux[0to88]+energy_per_cycle_sb_mux[0][0]_rrnode[269]' -Xmux_1level_tapbuf_size2[90] mux_1level_tapbuf_size2[90]->in[0] mux_1level_tapbuf_size2[90]->in[1] mux_1level_tapbuf_size2[90]->out sram[90]->outb sram[90]->out gvdd_mux_1level_tapbuf_size2[90] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[90], level=1, select_path_id=0. ***** -*****1***** -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -***** Signal mux_1level_tapbuf_size2[90]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[90]->in[0] mux_1level_tapbuf_size2[90]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[90]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[90]->in[1] mux_1level_tapbuf_size2[90]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[90] gvdd_mux_1level_tapbuf_size2[90] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[271] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[271] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[271] when v(mux_1level_tapbuf_size2[90]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[271] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[271] when v(mux_1level_tapbuf_size2[90]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[271] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[90]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[271] param='mux_1level_tapbuf_size2[90]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[90]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[90]_energy_per_cycle param='mux_1level_tapbuf_size2[90]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[271] param='mux_1level_tapbuf_size2[90]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[271] param='dynamic_power_sb_mux[0][0]_rrnode[271]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[271] avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='start_rise_sb_mux[0][0]_rrnode[271]' to='start_rise_sb_mux[0][0]_rrnode[271]+switch_rise_sb_mux[0][0]_rrnode[271]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[271] avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='start_fall_sb_mux[0][0]_rrnode[271]' to='start_fall_sb_mux[0][0]_rrnode[271]+switch_fall_sb_mux[0][0]_rrnode[271]' -.meas tran sum_leakage_power_mux[0to90] -+ param='sum_leakage_power_mux[0to89]+leakage_sb_mux[0][0]_rrnode[271]' -.meas tran sum_energy_per_cycle_mux[0to90] -+ param='sum_energy_per_cycle_mux[0to89]+energy_per_cycle_sb_mux[0][0]_rrnode[271]' -***** Load for rr_node[271] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=80, type=4 ***** -Xchan_mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[350]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to90] -+ param='sum_leakage_power_sb_mux[0to89]+leakage_sb_mux[0][0]_rrnode[271]' -.meas tran sum_energy_per_cycle_sb_mux[0to90] -+ param='sum_energy_per_cycle_sb_mux[0to89]+energy_per_cycle_sb_mux[0][0]_rrnode[271]' -Xmux_1level_tapbuf_size2[91] mux_1level_tapbuf_size2[91]->in[0] mux_1level_tapbuf_size2[91]->in[1] mux_1level_tapbuf_size2[91]->out sram[91]->outb sram[91]->out gvdd_mux_1level_tapbuf_size2[91] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[91], level=1, select_path_id=0. ***** -*****1***** -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -***** Signal mux_1level_tapbuf_size2[91]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[91]->in[0] mux_1level_tapbuf_size2[91]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[91]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[91]->in[1] mux_1level_tapbuf_size2[91]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[91] gvdd_mux_1level_tapbuf_size2[91] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[273] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[273] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[273] when v(mux_1level_tapbuf_size2[91]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[273] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[273] when v(mux_1level_tapbuf_size2[91]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[273] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[91]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[273] param='mux_1level_tapbuf_size2[91]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[91]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[91]_energy_per_cycle param='mux_1level_tapbuf_size2[91]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[273] param='mux_1level_tapbuf_size2[91]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[273] param='dynamic_power_sb_mux[0][0]_rrnode[273]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[273] avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='start_rise_sb_mux[0][0]_rrnode[273]' to='start_rise_sb_mux[0][0]_rrnode[273]+switch_rise_sb_mux[0][0]_rrnode[273]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[273] avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='start_fall_sb_mux[0][0]_rrnode[273]' to='start_fall_sb_mux[0][0]_rrnode[273]+switch_fall_sb_mux[0][0]_rrnode[273]' -.meas tran sum_leakage_power_mux[0to91] -+ param='sum_leakage_power_mux[0to90]+leakage_sb_mux[0][0]_rrnode[273]' -.meas tran sum_energy_per_cycle_mux[0to91] -+ param='sum_energy_per_cycle_mux[0to90]+energy_per_cycle_sb_mux[0][0]_rrnode[273]' -***** Load for rr_node[273] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=82, type=4 ***** -Xchan_mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[354]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to91] -+ param='sum_leakage_power_sb_mux[0to90]+leakage_sb_mux[0][0]_rrnode[273]' -.meas tran sum_energy_per_cycle_sb_mux[0to91] -+ param='sum_energy_per_cycle_sb_mux[0to90]+energy_per_cycle_sb_mux[0][0]_rrnode[273]' -Xmux_1level_tapbuf_size2[92] mux_1level_tapbuf_size2[92]->in[0] mux_1level_tapbuf_size2[92]->in[1] mux_1level_tapbuf_size2[92]->out sram[92]->outb sram[92]->out gvdd_mux_1level_tapbuf_size2[92] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[92], level=1, select_path_id=0. ***** -*****1***** -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -***** Signal mux_1level_tapbuf_size2[92]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[92]->in[0] mux_1level_tapbuf_size2[92]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[92]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[92]->in[1] mux_1level_tapbuf_size2[92]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[92] gvdd_mux_1level_tapbuf_size2[92] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[275] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[275] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[275] when v(mux_1level_tapbuf_size2[92]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[275] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[275] when v(mux_1level_tapbuf_size2[92]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[275] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[92]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[275] param='mux_1level_tapbuf_size2[92]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[92]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[92]_energy_per_cycle param='mux_1level_tapbuf_size2[92]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[275] param='mux_1level_tapbuf_size2[92]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[275] param='dynamic_power_sb_mux[0][0]_rrnode[275]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[275] avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='start_rise_sb_mux[0][0]_rrnode[275]' to='start_rise_sb_mux[0][0]_rrnode[275]+switch_rise_sb_mux[0][0]_rrnode[275]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[275] avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='start_fall_sb_mux[0][0]_rrnode[275]' to='start_fall_sb_mux[0][0]_rrnode[275]+switch_fall_sb_mux[0][0]_rrnode[275]' -.meas tran sum_leakage_power_mux[0to92] -+ param='sum_leakage_power_mux[0to91]+leakage_sb_mux[0][0]_rrnode[275]' -.meas tran sum_energy_per_cycle_mux[0to92] -+ param='sum_energy_per_cycle_mux[0to91]+energy_per_cycle_sb_mux[0][0]_rrnode[275]' -***** Load for rr_node[275] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=84, type=4 ***** -Xchan_mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[357]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[360]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to92] -+ param='sum_leakage_power_sb_mux[0to91]+leakage_sb_mux[0][0]_rrnode[275]' -.meas tran sum_energy_per_cycle_sb_mux[0to92] -+ param='sum_energy_per_cycle_sb_mux[0to91]+energy_per_cycle_sb_mux[0][0]_rrnode[275]' -Xmux_1level_tapbuf_size2[93] mux_1level_tapbuf_size2[93]->in[0] mux_1level_tapbuf_size2[93]->in[1] mux_1level_tapbuf_size2[93]->out sram[93]->outb sram[93]->out gvdd_mux_1level_tapbuf_size2[93] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[93], level=1, select_path_id=0. ***** -*****1***** -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -***** Signal mux_1level_tapbuf_size2[93]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[93]->in[0] mux_1level_tapbuf_size2[93]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[93]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[93]->in[1] mux_1level_tapbuf_size2[93]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[93] gvdd_mux_1level_tapbuf_size2[93] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[277] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[277] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[277] when v(mux_1level_tapbuf_size2[93]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[277] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[277] when v(mux_1level_tapbuf_size2[93]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[277] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[93]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[277] param='mux_1level_tapbuf_size2[93]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[93]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[93]_energy_per_cycle param='mux_1level_tapbuf_size2[93]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[277] param='mux_1level_tapbuf_size2[93]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[277] param='dynamic_power_sb_mux[0][0]_rrnode[277]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[277] avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='start_rise_sb_mux[0][0]_rrnode[277]' to='start_rise_sb_mux[0][0]_rrnode[277]+switch_rise_sb_mux[0][0]_rrnode[277]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[277] avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='start_fall_sb_mux[0][0]_rrnode[277]' to='start_fall_sb_mux[0][0]_rrnode[277]+switch_fall_sb_mux[0][0]_rrnode[277]' -.meas tran sum_leakage_power_mux[0to93] -+ param='sum_leakage_power_mux[0to92]+leakage_sb_mux[0][0]_rrnode[277]' -.meas tran sum_energy_per_cycle_mux[0to93] -+ param='sum_energy_per_cycle_mux[0to92]+energy_per_cycle_sb_mux[0][0]_rrnode[277]' -***** Load for rr_node[277] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=86, type=4 ***** -Xchan_mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[362]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to93] -+ param='sum_leakage_power_sb_mux[0to92]+leakage_sb_mux[0][0]_rrnode[277]' -.meas tran sum_energy_per_cycle_sb_mux[0to93] -+ param='sum_energy_per_cycle_sb_mux[0to92]+energy_per_cycle_sb_mux[0][0]_rrnode[277]' -Xmux_1level_tapbuf_size2[94] mux_1level_tapbuf_size2[94]->in[0] mux_1level_tapbuf_size2[94]->in[1] mux_1level_tapbuf_size2[94]->out sram[94]->outb sram[94]->out gvdd_mux_1level_tapbuf_size2[94] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[94], level=1, select_path_id=0. ***** -*****1***** -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -***** Signal mux_1level_tapbuf_size2[94]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[94]->in[0] mux_1level_tapbuf_size2[94]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[94]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[94]->in[1] mux_1level_tapbuf_size2[94]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[94] gvdd_mux_1level_tapbuf_size2[94] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[279] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[279] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[279] when v(mux_1level_tapbuf_size2[94]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[279] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[279] when v(mux_1level_tapbuf_size2[94]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[279] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[94]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[279] param='mux_1level_tapbuf_size2[94]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[94]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[94]_energy_per_cycle param='mux_1level_tapbuf_size2[94]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[279] param='mux_1level_tapbuf_size2[94]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[279] param='dynamic_power_sb_mux[0][0]_rrnode[279]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[279] avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='start_rise_sb_mux[0][0]_rrnode[279]' to='start_rise_sb_mux[0][0]_rrnode[279]+switch_rise_sb_mux[0][0]_rrnode[279]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[279] avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='start_fall_sb_mux[0][0]_rrnode[279]' to='start_fall_sb_mux[0][0]_rrnode[279]+switch_fall_sb_mux[0][0]_rrnode[279]' -.meas tran sum_leakage_power_mux[0to94] -+ param='sum_leakage_power_mux[0to93]+leakage_sb_mux[0][0]_rrnode[279]' -.meas tran sum_energy_per_cycle_mux[0to94] -+ param='sum_energy_per_cycle_mux[0to93]+energy_per_cycle_sb_mux[0][0]_rrnode[279]' -***** Load for rr_node[279] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=88, type=4 ***** -Xchan_mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[365]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to94] -+ param='sum_leakage_power_sb_mux[0to93]+leakage_sb_mux[0][0]_rrnode[279]' -.meas tran sum_energy_per_cycle_sb_mux[0to94] -+ param='sum_energy_per_cycle_sb_mux[0to93]+energy_per_cycle_sb_mux[0][0]_rrnode[279]' -Xmux_1level_tapbuf_size2[95] mux_1level_tapbuf_size2[95]->in[0] mux_1level_tapbuf_size2[95]->in[1] mux_1level_tapbuf_size2[95]->out sram[95]->outb sram[95]->out gvdd_mux_1level_tapbuf_size2[95] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[95], level=1, select_path_id=0. ***** -*****1***** -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -***** Signal mux_1level_tapbuf_size2[95]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[95]->in[0] mux_1level_tapbuf_size2[95]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[95]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[95]->in[1] mux_1level_tapbuf_size2[95]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[95] gvdd_mux_1level_tapbuf_size2[95] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[281] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[281] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[281] when v(mux_1level_tapbuf_size2[95]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[281] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[281] when v(mux_1level_tapbuf_size2[95]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[281] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[95]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[281] param='mux_1level_tapbuf_size2[95]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[95]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[95]_energy_per_cycle param='mux_1level_tapbuf_size2[95]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[281] param='mux_1level_tapbuf_size2[95]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[281] param='dynamic_power_sb_mux[0][0]_rrnode[281]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[281] avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='start_rise_sb_mux[0][0]_rrnode[281]' to='start_rise_sb_mux[0][0]_rrnode[281]+switch_rise_sb_mux[0][0]_rrnode[281]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[281] avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='start_fall_sb_mux[0][0]_rrnode[281]' to='start_fall_sb_mux[0][0]_rrnode[281]+switch_fall_sb_mux[0][0]_rrnode[281]' -.meas tran sum_leakage_power_mux[0to95] -+ param='sum_leakage_power_mux[0to94]+leakage_sb_mux[0][0]_rrnode[281]' -.meas tran sum_energy_per_cycle_mux[0to95] -+ param='sum_energy_per_cycle_mux[0to94]+energy_per_cycle_sb_mux[0][0]_rrnode[281]' -***** Load for rr_node[281] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=90, type=4 ***** -Xchan_mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[369]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to95] -+ param='sum_leakage_power_sb_mux[0to94]+leakage_sb_mux[0][0]_rrnode[281]' -.meas tran sum_energy_per_cycle_sb_mux[0to95] -+ param='sum_energy_per_cycle_sb_mux[0to94]+energy_per_cycle_sb_mux[0][0]_rrnode[281]' -Xmux_1level_tapbuf_size2[96] mux_1level_tapbuf_size2[96]->in[0] mux_1level_tapbuf_size2[96]->in[1] mux_1level_tapbuf_size2[96]->out sram[96]->outb sram[96]->out gvdd_mux_1level_tapbuf_size2[96] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[96], level=1, select_path_id=0. ***** -*****1***** -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -***** Signal mux_1level_tapbuf_size2[96]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[96]->in[0] mux_1level_tapbuf_size2[96]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[96]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[96]->in[1] mux_1level_tapbuf_size2[96]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[96] gvdd_mux_1level_tapbuf_size2[96] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[283] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[283] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[283] when v(mux_1level_tapbuf_size2[96]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[283] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[283] when v(mux_1level_tapbuf_size2[96]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[283] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[96]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[283] param='mux_1level_tapbuf_size2[96]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[96]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[96]_energy_per_cycle param='mux_1level_tapbuf_size2[96]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[283] param='mux_1level_tapbuf_size2[96]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[283] param='dynamic_power_sb_mux[0][0]_rrnode[283]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[283] avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='start_rise_sb_mux[0][0]_rrnode[283]' to='start_rise_sb_mux[0][0]_rrnode[283]+switch_rise_sb_mux[0][0]_rrnode[283]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[283] avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='start_fall_sb_mux[0][0]_rrnode[283]' to='start_fall_sb_mux[0][0]_rrnode[283]+switch_fall_sb_mux[0][0]_rrnode[283]' -.meas tran sum_leakage_power_mux[0to96] -+ param='sum_leakage_power_mux[0to95]+leakage_sb_mux[0][0]_rrnode[283]' -.meas tran sum_energy_per_cycle_mux[0to96] -+ param='sum_energy_per_cycle_mux[0to95]+energy_per_cycle_sb_mux[0][0]_rrnode[283]' -***** Load for rr_node[283] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=92, type=4 ***** -Xchan_mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[373]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to96] -+ param='sum_leakage_power_sb_mux[0to95]+leakage_sb_mux[0][0]_rrnode[283]' -.meas tran sum_energy_per_cycle_sb_mux[0to96] -+ param='sum_energy_per_cycle_sb_mux[0to95]+energy_per_cycle_sb_mux[0][0]_rrnode[283]' -Xmux_1level_tapbuf_size2[97] mux_1level_tapbuf_size2[97]->in[0] mux_1level_tapbuf_size2[97]->in[1] mux_1level_tapbuf_size2[97]->out sram[97]->outb sram[97]->out gvdd_mux_1level_tapbuf_size2[97] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[97], level=1, select_path_id=0. ***** -*****1***** -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -***** Signal mux_1level_tapbuf_size2[97]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[97]->in[0] mux_1level_tapbuf_size2[97]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[97]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[97]->in[1] mux_1level_tapbuf_size2[97]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[97] gvdd_mux_1level_tapbuf_size2[97] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[285] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[285] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[285] when v(mux_1level_tapbuf_size2[97]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[285] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[285] when v(mux_1level_tapbuf_size2[97]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[285] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[97]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[285] param='mux_1level_tapbuf_size2[97]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[97]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[97]_energy_per_cycle param='mux_1level_tapbuf_size2[97]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[285] param='mux_1level_tapbuf_size2[97]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[285] param='dynamic_power_sb_mux[0][0]_rrnode[285]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[285] avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='start_rise_sb_mux[0][0]_rrnode[285]' to='start_rise_sb_mux[0][0]_rrnode[285]+switch_rise_sb_mux[0][0]_rrnode[285]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[285] avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='start_fall_sb_mux[0][0]_rrnode[285]' to='start_fall_sb_mux[0][0]_rrnode[285]+switch_fall_sb_mux[0][0]_rrnode[285]' -.meas tran sum_leakage_power_mux[0to97] -+ param='sum_leakage_power_mux[0to96]+leakage_sb_mux[0][0]_rrnode[285]' -.meas tran sum_energy_per_cycle_mux[0to97] -+ param='sum_energy_per_cycle_mux[0to96]+energy_per_cycle_sb_mux[0][0]_rrnode[285]' -***** Load for rr_node[285] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=94, type=4 ***** -Xchan_mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[377]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to97] -+ param='sum_leakage_power_sb_mux[0to96]+leakage_sb_mux[0][0]_rrnode[285]' -.meas tran sum_energy_per_cycle_sb_mux[0to97] -+ param='sum_energy_per_cycle_sb_mux[0to96]+energy_per_cycle_sb_mux[0][0]_rrnode[285]' -Xmux_1level_tapbuf_size2[98] mux_1level_tapbuf_size2[98]->in[0] mux_1level_tapbuf_size2[98]->in[1] mux_1level_tapbuf_size2[98]->out sram[98]->outb sram[98]->out gvdd_mux_1level_tapbuf_size2[98] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[98], level=1, select_path_id=0. ***** -*****1***** -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -***** Signal mux_1level_tapbuf_size2[98]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[98]->in[0] mux_1level_tapbuf_size2[98]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[98]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[98]->in[1] mux_1level_tapbuf_size2[98]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[98] gvdd_mux_1level_tapbuf_size2[98] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[287] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[287] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[287] when v(mux_1level_tapbuf_size2[98]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[287] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[287] when v(mux_1level_tapbuf_size2[98]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[287] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[98]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[287] param='mux_1level_tapbuf_size2[98]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[98]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[98]_energy_per_cycle param='mux_1level_tapbuf_size2[98]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[287] param='mux_1level_tapbuf_size2[98]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[287] param='dynamic_power_sb_mux[0][0]_rrnode[287]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[287] avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='start_rise_sb_mux[0][0]_rrnode[287]' to='start_rise_sb_mux[0][0]_rrnode[287]+switch_rise_sb_mux[0][0]_rrnode[287]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[287] avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='start_fall_sb_mux[0][0]_rrnode[287]' to='start_fall_sb_mux[0][0]_rrnode[287]+switch_fall_sb_mux[0][0]_rrnode[287]' -.meas tran sum_leakage_power_mux[0to98] -+ param='sum_leakage_power_mux[0to97]+leakage_sb_mux[0][0]_rrnode[287]' -.meas tran sum_energy_per_cycle_mux[0to98] -+ param='sum_energy_per_cycle_mux[0to97]+energy_per_cycle_sb_mux[0][0]_rrnode[287]' -***** Load for rr_node[287] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=96, type=4 ***** -Xchan_mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[381]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to98] -+ param='sum_leakage_power_sb_mux[0to97]+leakage_sb_mux[0][0]_rrnode[287]' -.meas tran sum_energy_per_cycle_sb_mux[0to98] -+ param='sum_energy_per_cycle_sb_mux[0to97]+energy_per_cycle_sb_mux[0][0]_rrnode[287]' -Xmux_1level_tapbuf_size2[99] mux_1level_tapbuf_size2[99]->in[0] mux_1level_tapbuf_size2[99]->in[1] mux_1level_tapbuf_size2[99]->out sram[99]->outb sram[99]->out gvdd_mux_1level_tapbuf_size2[99] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[99], level=1, select_path_id=0. ***** -*****1***** -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -***** Signal mux_1level_tapbuf_size2[99]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[99]->in[0] mux_1level_tapbuf_size2[99]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[99]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[99]->in[1] mux_1level_tapbuf_size2[99]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[99] gvdd_mux_1level_tapbuf_size2[99] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][0]_rrnode[289] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][0]_rrnode[289] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][0]_rrnode[289] when v(mux_1level_tapbuf_size2[99]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][0]_rrnode[289] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][0]_rrnode[289] when v(mux_1level_tapbuf_size2[99]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][0]_rrnode[289] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[99]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][0]_rrnode[289] param='mux_1level_tapbuf_size2[99]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[99]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[99]_energy_per_cycle param='mux_1level_tapbuf_size2[99]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][0]_rrnode[289] param='mux_1level_tapbuf_size2[99]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][0]_rrnode[289] param='dynamic_power_sb_mux[0][0]_rrnode[289]*clock_period' -.meas tran dynamic_rise_sb_mux[0][0]_rrnode[289] avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='start_rise_sb_mux[0][0]_rrnode[289]' to='start_rise_sb_mux[0][0]_rrnode[289]+switch_rise_sb_mux[0][0]_rrnode[289]' -.meas tran dynamic_fall_sb_mux[0][0]_rrnode[289] avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='start_fall_sb_mux[0][0]_rrnode[289]' to='start_fall_sb_mux[0][0]_rrnode[289]+switch_fall_sb_mux[0][0]_rrnode[289]' -.meas tran sum_leakage_power_mux[0to99] -+ param='sum_leakage_power_mux[0to98]+leakage_sb_mux[0][0]_rrnode[289]' -.meas tran sum_energy_per_cycle_mux[0to99] -+ param='sum_energy_per_cycle_mux[0to98]+energy_per_cycle_sb_mux[0][0]_rrnode[289]' -***** Load for rr_node[289] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=98, type=4 ***** -Xchan_mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[384]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to99] -+ param='sum_leakage_power_sb_mux[0to98]+leakage_sb_mux[0][0]_rrnode[289]' -.meas tran sum_energy_per_cycle_sb_mux[0to99] -+ param='sum_energy_per_cycle_sb_mux[0to98]+energy_per_cycle_sb_mux[0][0]_rrnode[289]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='6*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to99] -+ param='sum_leakage_power_mux[0to99]' -.meas tran total_energy_per_cycle_mux[0to99] -+ param='sum_energy_per_cycle_mux[0to99]' -.meas tran total_leakage_power_sb_mux -+ param='sum_leakage_power_sb_mux[0to99]' -.meas tran total_energy_per_cycle_sb_mux -+ param='sum_energy_per_cycle_sb_mux[0to99]' -.end diff --git a/examples/spice_test_example_2/sb_mux_tb/example_2_sb0_1_sbmux_testbench.sp b/examples/spice_test_example_2/sb_mux_tb/example_2_sb0_1_sbmux_testbench.sp deleted file mode 100644 index 3c7fb183c..000000000 --- a/examples/spice_test_example_2/sb_mux_tb/example_2_sb0_1_sbmux_testbench.sp +++ /dev/null @@ -1,5435 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_1level_tapbuf_size3[0] mux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb gvdd_mux_1level_tapbuf_size3[0] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[0], level=1, select_path_id=0. ***** -*****100***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -***** Signal mux_1level_tapbuf_size3[0]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[0] gvdd_mux_1level_tapbuf_size3[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[291] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[291] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[291] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[291] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[291] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[291] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[291] param='mux_1level_tapbuf_size3[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[0]_energy_per_cycle param='mux_1level_tapbuf_size3[0]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[291] param='mux_1level_tapbuf_size3[0]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[291] param='dynamic_power_sb_mux[0][1]_rrnode[291]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[291] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_rise_sb_mux[0][1]_rrnode[291]' to='start_rise_sb_mux[0][1]_rrnode[291]+switch_rise_sb_mux[0][1]_rrnode[291]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[291] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_fall_sb_mux[0][1]_rrnode[291]' to='start_fall_sb_mux[0][1]_rrnode[291]+switch_fall_sb_mux[0][1]_rrnode[291]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_sb_mux[0][1]_rrnode[291]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_sb_mux[0][1]_rrnode[291]' -***** Load for rr_node[291] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=0, type=4 ***** -Xchan_mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to0] -+ param='leakage_sb_mux[0][1]_rrnode[291]' -.meas tran sum_energy_per_cycle_sb_mux[0to0] -+ param='energy_per_cycle_sb_mux[0][1]_rrnode[291]' -Xmux_1level_tapbuf_size3[1] mux_1level_tapbuf_size3[1]->in[0] mux_1level_tapbuf_size3[1]->in[1] mux_1level_tapbuf_size3[1]->in[2] mux_1level_tapbuf_size3[1]->out sram[3]->outb sram[3]->out sram[4]->out sram[4]->outb sram[5]->out sram[5]->outb gvdd_mux_1level_tapbuf_size3[1] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[1], level=1, select_path_id=0. ***** -*****100***** -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -***** Signal mux_1level_tapbuf_size3[1]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[0] mux_1level_tapbuf_size3[1]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[1]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[1] mux_1level_tapbuf_size3[1]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[1]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[2] mux_1level_tapbuf_size3[1]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[1] gvdd_mux_1level_tapbuf_size3[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[293] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[293] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[293] when v(mux_1level_tapbuf_size3[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[293] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[293] when v(mux_1level_tapbuf_size3[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[293] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[1]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[293] param='mux_1level_tapbuf_size3[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[1]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[1]_energy_per_cycle param='mux_1level_tapbuf_size3[1]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[293] param='mux_1level_tapbuf_size3[1]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[293] param='dynamic_power_sb_mux[0][1]_rrnode[293]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[293] avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='start_rise_sb_mux[0][1]_rrnode[293]' to='start_rise_sb_mux[0][1]_rrnode[293]+switch_rise_sb_mux[0][1]_rrnode[293]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[293] avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='start_fall_sb_mux[0][1]_rrnode[293]' to='start_fall_sb_mux[0][1]_rrnode[293]+switch_fall_sb_mux[0][1]_rrnode[293]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_sb_mux[0][1]_rrnode[293]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_sb_mux[0][1]_rrnode[293]' -***** Load for rr_node[293] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=2, type=4 ***** -Xchan_mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[5]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to1] -+ param='sum_leakage_power_sb_mux[0to0]+leakage_sb_mux[0][1]_rrnode[293]' -.meas tran sum_energy_per_cycle_sb_mux[0to1] -+ param='sum_energy_per_cycle_sb_mux[0to0]+energy_per_cycle_sb_mux[0][1]_rrnode[293]' -Xmux_1level_tapbuf_size3[2] mux_1level_tapbuf_size3[2]->in[0] mux_1level_tapbuf_size3[2]->in[1] mux_1level_tapbuf_size3[2]->in[2] mux_1level_tapbuf_size3[2]->out sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb sram[8]->out sram[8]->outb gvdd_mux_1level_tapbuf_size3[2] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[2], level=1, select_path_id=0. ***** -*****100***** -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -***** Signal mux_1level_tapbuf_size3[2]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[0] mux_1level_tapbuf_size3[2]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[2]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[1] mux_1level_tapbuf_size3[2]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[2]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[2] mux_1level_tapbuf_size3[2]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[2] gvdd_mux_1level_tapbuf_size3[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[295] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[295] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[295] when v(mux_1level_tapbuf_size3[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[295] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[295] when v(mux_1level_tapbuf_size3[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[295] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[2]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[295] param='mux_1level_tapbuf_size3[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[2]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[2]_energy_per_cycle param='mux_1level_tapbuf_size3[2]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[295] param='mux_1level_tapbuf_size3[2]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[295] param='dynamic_power_sb_mux[0][1]_rrnode[295]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[295] avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='start_rise_sb_mux[0][1]_rrnode[295]' to='start_rise_sb_mux[0][1]_rrnode[295]+switch_rise_sb_mux[0][1]_rrnode[295]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[295] avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='start_fall_sb_mux[0][1]_rrnode[295]' to='start_fall_sb_mux[0][1]_rrnode[295]+switch_fall_sb_mux[0][1]_rrnode[295]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_sb_mux[0][1]_rrnode[295]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_sb_mux[0][1]_rrnode[295]' -***** Load for rr_node[295] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=4, type=4 ***** -Xchan_mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[8]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to2] -+ param='sum_leakage_power_sb_mux[0to1]+leakage_sb_mux[0][1]_rrnode[295]' -.meas tran sum_energy_per_cycle_sb_mux[0to2] -+ param='sum_energy_per_cycle_sb_mux[0to1]+energy_per_cycle_sb_mux[0][1]_rrnode[295]' -Xmux_1level_tapbuf_size3[3] mux_1level_tapbuf_size3[3]->in[0] mux_1level_tapbuf_size3[3]->in[1] mux_1level_tapbuf_size3[3]->in[2] mux_1level_tapbuf_size3[3]->out sram[9]->outb sram[9]->out sram[10]->out sram[10]->outb sram[11]->out sram[11]->outb gvdd_mux_1level_tapbuf_size3[3] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[3], level=1, select_path_id=0. ***** -*****100***** -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_1level_tapbuf_size3[3]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[3]->in[0] mux_1level_tapbuf_size3[3]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[3]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[3]->in[1] mux_1level_tapbuf_size3[3]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[3]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[3]->in[2] mux_1level_tapbuf_size3[3]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[3] gvdd_mux_1level_tapbuf_size3[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[297] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[297] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[297] when v(mux_1level_tapbuf_size3[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[297] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[297] when v(mux_1level_tapbuf_size3[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[297] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[3]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[297] param='mux_1level_tapbuf_size3[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[3]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[3]_energy_per_cycle param='mux_1level_tapbuf_size3[3]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[297] param='mux_1level_tapbuf_size3[3]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[297] param='dynamic_power_sb_mux[0][1]_rrnode[297]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[297] avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from='start_rise_sb_mux[0][1]_rrnode[297]' to='start_rise_sb_mux[0][1]_rrnode[297]+switch_rise_sb_mux[0][1]_rrnode[297]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[297] avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from='start_fall_sb_mux[0][1]_rrnode[297]' to='start_fall_sb_mux[0][1]_rrnode[297]+switch_fall_sb_mux[0][1]_rrnode[297]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_sb_mux[0][1]_rrnode[297]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_sb_mux[0][1]_rrnode[297]' -***** Load for rr_node[297] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=6, type=4 ***** -Xchan_mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out mux_1level_tapbuf_size3[3]->out mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[12]_no0 mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to3] -+ param='sum_leakage_power_sb_mux[0to2]+leakage_sb_mux[0][1]_rrnode[297]' -.meas tran sum_energy_per_cycle_sb_mux[0to3] -+ param='sum_energy_per_cycle_sb_mux[0to2]+energy_per_cycle_sb_mux[0][1]_rrnode[297]' -Xmux_1level_tapbuf_size3[4] mux_1level_tapbuf_size3[4]->in[0] mux_1level_tapbuf_size3[4]->in[1] mux_1level_tapbuf_size3[4]->in[2] mux_1level_tapbuf_size3[4]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->out sram[14]->outb gvdd_mux_1level_tapbuf_size3[4] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****100***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -***** Signal mux_1level_tapbuf_size3[4]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[4]->in[0] mux_1level_tapbuf_size3[4]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[4]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[4]->in[1] mux_1level_tapbuf_size3[4]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[4]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[4]->in[2] mux_1level_tapbuf_size3[4]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[4] gvdd_mux_1level_tapbuf_size3[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[299] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[299] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[299] when v(mux_1level_tapbuf_size3[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[299] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[299] when v(mux_1level_tapbuf_size3[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[299] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[4]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[299] param='mux_1level_tapbuf_size3[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[4]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[4]_energy_per_cycle param='mux_1level_tapbuf_size3[4]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[299] param='mux_1level_tapbuf_size3[4]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[299] param='dynamic_power_sb_mux[0][1]_rrnode[299]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[299] avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from='start_rise_sb_mux[0][1]_rrnode[299]' to='start_rise_sb_mux[0][1]_rrnode[299]+switch_rise_sb_mux[0][1]_rrnode[299]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[299] avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from='start_fall_sb_mux[0][1]_rrnode[299]' to='start_fall_sb_mux[0][1]_rrnode[299]+switch_fall_sb_mux[0][1]_rrnode[299]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_sb_mux[0][1]_rrnode[299]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_sb_mux[0][1]_rrnode[299]' -***** Load for rr_node[299] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=8, type=4 ***** -Xchan_mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out mux_1level_tapbuf_size3[4]->out mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[16]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to4] -+ param='sum_leakage_power_sb_mux[0to3]+leakage_sb_mux[0][1]_rrnode[299]' -.meas tran sum_energy_per_cycle_sb_mux[0to4] -+ param='sum_energy_per_cycle_sb_mux[0to3]+energy_per_cycle_sb_mux[0][1]_rrnode[299]' -Xmux_1level_tapbuf_size2[5] mux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->out sram[15]->outb sram[15]->out gvdd_mux_1level_tapbuf_size2[5] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[5], level=1, select_path_id=0. ***** -*****1***** -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_1level_tapbuf_size2[5]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[5]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[5] gvdd_mux_1level_tapbuf_size2[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[301] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[301] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[301] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[301] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[301] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[301] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[301] param='mux_1level_tapbuf_size2[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[5]_energy_per_cycle param='mux_1level_tapbuf_size2[5]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[301] param='mux_1level_tapbuf_size2[5]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[301] param='dynamic_power_sb_mux[0][1]_rrnode[301]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[301] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_rise_sb_mux[0][1]_rrnode[301]' to='start_rise_sb_mux[0][1]_rrnode[301]+switch_rise_sb_mux[0][1]_rrnode[301]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[301] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_fall_sb_mux[0][1]_rrnode[301]' to='start_fall_sb_mux[0][1]_rrnode[301]+switch_fall_sb_mux[0][1]_rrnode[301]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_sb_mux[0][1]_rrnode[301]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_sb_mux[0][1]_rrnode[301]' -***** Load for rr_node[301] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=10, type=4 ***** -Xchan_mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[21]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to5] -+ param='sum_leakage_power_sb_mux[0to4]+leakage_sb_mux[0][1]_rrnode[301]' -.meas tran sum_energy_per_cycle_sb_mux[0to5] -+ param='sum_energy_per_cycle_sb_mux[0to4]+energy_per_cycle_sb_mux[0][1]_rrnode[301]' -Xmux_1level_tapbuf_size2[6] mux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->out sram[16]->outb sram[16]->out gvdd_mux_1level_tapbuf_size2[6] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[6], level=1, select_path_id=0. ***** -*****1***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -***** Signal mux_1level_tapbuf_size2[6]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[6]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[6] gvdd_mux_1level_tapbuf_size2[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[303] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[303] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[303] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[303] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[303] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[303] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[303] param='mux_1level_tapbuf_size2[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[6]_energy_per_cycle param='mux_1level_tapbuf_size2[6]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[303] param='mux_1level_tapbuf_size2[6]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[303] param='dynamic_power_sb_mux[0][1]_rrnode[303]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[303] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_rise_sb_mux[0][1]_rrnode[303]' to='start_rise_sb_mux[0][1]_rrnode[303]+switch_rise_sb_mux[0][1]_rrnode[303]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[303] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_fall_sb_mux[0][1]_rrnode[303]' to='start_fall_sb_mux[0][1]_rrnode[303]+switch_fall_sb_mux[0][1]_rrnode[303]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_sb_mux[0][1]_rrnode[303]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_sb_mux[0][1]_rrnode[303]' -***** Load for rr_node[303] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=12, type=4 ***** -Xchan_mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[25]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to6] -+ param='sum_leakage_power_sb_mux[0to5]+leakage_sb_mux[0][1]_rrnode[303]' -.meas tran sum_energy_per_cycle_sb_mux[0to6] -+ param='sum_energy_per_cycle_sb_mux[0to5]+energy_per_cycle_sb_mux[0][1]_rrnode[303]' -Xmux_1level_tapbuf_size2[7] mux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->out sram[17]->outb sram[17]->out gvdd_mux_1level_tapbuf_size2[7] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[7], level=1, select_path_id=0. ***** -*****1***** -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -***** Signal mux_1level_tapbuf_size2[7]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[7]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[7] gvdd_mux_1level_tapbuf_size2[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[305] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[305] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[305] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[305] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[305] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[305] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[305] param='mux_1level_tapbuf_size2[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[7]_energy_per_cycle param='mux_1level_tapbuf_size2[7]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[305] param='mux_1level_tapbuf_size2[7]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[305] param='dynamic_power_sb_mux[0][1]_rrnode[305]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[305] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_rise_sb_mux[0][1]_rrnode[305]' to='start_rise_sb_mux[0][1]_rrnode[305]+switch_rise_sb_mux[0][1]_rrnode[305]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[305] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_fall_sb_mux[0][1]_rrnode[305]' to='start_fall_sb_mux[0][1]_rrnode[305]+switch_fall_sb_mux[0][1]_rrnode[305]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_sb_mux[0][1]_rrnode[305]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_sb_mux[0][1]_rrnode[305]' -***** Load for rr_node[305] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=14, type=4 ***** -Xchan_mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[28]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to7] -+ param='sum_leakage_power_sb_mux[0to6]+leakage_sb_mux[0][1]_rrnode[305]' -.meas tran sum_energy_per_cycle_sb_mux[0to7] -+ param='sum_energy_per_cycle_sb_mux[0to6]+energy_per_cycle_sb_mux[0][1]_rrnode[305]' -Xmux_1level_tapbuf_size2[8] mux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->out sram[18]->outb sram[18]->out gvdd_mux_1level_tapbuf_size2[8] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[8], level=1, select_path_id=0. ***** -*****1***** -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -***** Signal mux_1level_tapbuf_size2[8]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[8]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[8] gvdd_mux_1level_tapbuf_size2[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[307] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[307] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[307] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[307] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[307] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[307] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[307] param='mux_1level_tapbuf_size2[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[8]_energy_per_cycle param='mux_1level_tapbuf_size2[8]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[307] param='mux_1level_tapbuf_size2[8]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[307] param='dynamic_power_sb_mux[0][1]_rrnode[307]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[307] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_rise_sb_mux[0][1]_rrnode[307]' to='start_rise_sb_mux[0][1]_rrnode[307]+switch_rise_sb_mux[0][1]_rrnode[307]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[307] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_fall_sb_mux[0][1]_rrnode[307]' to='start_fall_sb_mux[0][1]_rrnode[307]+switch_fall_sb_mux[0][1]_rrnode[307]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_sb_mux[0][1]_rrnode[307]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_sb_mux[0][1]_rrnode[307]' -***** Load for rr_node[307] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=16, type=4 ***** -Xchan_mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[31]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to8] -+ param='sum_leakage_power_sb_mux[0to7]+leakage_sb_mux[0][1]_rrnode[307]' -.meas tran sum_energy_per_cycle_sb_mux[0to8] -+ param='sum_energy_per_cycle_sb_mux[0to7]+energy_per_cycle_sb_mux[0][1]_rrnode[307]' -Xmux_1level_tapbuf_size2[9] mux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->out sram[19]->outb sram[19]->out gvdd_mux_1level_tapbuf_size2[9] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[9], level=1, select_path_id=0. ***** -*****1***** -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_1level_tapbuf_size2[9]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[9]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[9] gvdd_mux_1level_tapbuf_size2[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[309] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[309] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[309] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[309] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[309] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[309] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[309] param='mux_1level_tapbuf_size2[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[9]_energy_per_cycle param='mux_1level_tapbuf_size2[9]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[309] param='mux_1level_tapbuf_size2[9]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[309] param='dynamic_power_sb_mux[0][1]_rrnode[309]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[309] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_rise_sb_mux[0][1]_rrnode[309]' to='start_rise_sb_mux[0][1]_rrnode[309]+switch_rise_sb_mux[0][1]_rrnode[309]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[309] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_fall_sb_mux[0][1]_rrnode[309]' to='start_fall_sb_mux[0][1]_rrnode[309]+switch_fall_sb_mux[0][1]_rrnode[309]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_sb_mux[0][1]_rrnode[309]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_sb_mux[0][1]_rrnode[309]' -***** Load for rr_node[309] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=18, type=4 ***** -Xchan_mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[34]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to9] -+ param='sum_leakage_power_sb_mux[0to8]+leakage_sb_mux[0][1]_rrnode[309]' -.meas tran sum_energy_per_cycle_sb_mux[0to9] -+ param='sum_energy_per_cycle_sb_mux[0to8]+energy_per_cycle_sb_mux[0][1]_rrnode[309]' -Xmux_1level_tapbuf_size2[10] mux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->out sram[20]->out sram[20]->outb gvdd_mux_1level_tapbuf_size2[10] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[10], level=1, select_path_id=1. ***** -*****0***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -***** Signal mux_1level_tapbuf_size2[10]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[10]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[10] gvdd_mux_1level_tapbuf_size2[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[311] trig v(mux_1level_tapbuf_size2[10]->in[1]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[311] trig v(mux_1level_tapbuf_size2[10]->in[1]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[311] when v(mux_1level_tapbuf_size2[10]->in[1])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[311] trig v(mux_1level_tapbuf_size2[10]->in[1]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[311] when v(mux_1level_tapbuf_size2[10]->in[1])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[311] trig v(mux_1level_tapbuf_size2[10]->in[1]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[311] param='mux_1level_tapbuf_size2[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[10]_energy_per_cycle param='mux_1level_tapbuf_size2[10]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[311] param='mux_1level_tapbuf_size2[10]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[311] param='dynamic_power_sb_mux[0][1]_rrnode[311]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[311] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_rise_sb_mux[0][1]_rrnode[311]' to='start_rise_sb_mux[0][1]_rrnode[311]+switch_rise_sb_mux[0][1]_rrnode[311]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[311] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_fall_sb_mux[0][1]_rrnode[311]' to='start_fall_sb_mux[0][1]_rrnode[311]+switch_fall_sb_mux[0][1]_rrnode[311]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_sb_mux[0][1]_rrnode[311]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_sb_mux[0][1]_rrnode[311]' -***** Load for rr_node[311] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=20, type=4 ***** -Xchan_mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[38]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to10] -+ param='sum_leakage_power_sb_mux[0to9]+leakage_sb_mux[0][1]_rrnode[311]' -.meas tran sum_energy_per_cycle_sb_mux[0to10] -+ param='sum_energy_per_cycle_sb_mux[0to9]+energy_per_cycle_sb_mux[0][1]_rrnode[311]' -Xmux_1level_tapbuf_size2[11] mux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->out sram[21]->outb sram[21]->out gvdd_mux_1level_tapbuf_size2[11] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[11], level=1, select_path_id=0. ***** -*****1***** -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -***** Signal mux_1level_tapbuf_size2[11]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[11]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[11] gvdd_mux_1level_tapbuf_size2[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[313] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[313] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[313] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[313] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[313] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[313] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[313] param='mux_1level_tapbuf_size2[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[11]_energy_per_cycle param='mux_1level_tapbuf_size2[11]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[313] param='mux_1level_tapbuf_size2[11]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[313] param='dynamic_power_sb_mux[0][1]_rrnode[313]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[313] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_rise_sb_mux[0][1]_rrnode[313]' to='start_rise_sb_mux[0][1]_rrnode[313]+switch_rise_sb_mux[0][1]_rrnode[313]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[313] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_fall_sb_mux[0][1]_rrnode[313]' to='start_fall_sb_mux[0][1]_rrnode[313]+switch_fall_sb_mux[0][1]_rrnode[313]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_sb_mux[0][1]_rrnode[313]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_sb_mux[0][1]_rrnode[313]' -***** Load for rr_node[313] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=22, type=4 ***** -Xchan_mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[42]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to11] -+ param='sum_leakage_power_sb_mux[0to10]+leakage_sb_mux[0][1]_rrnode[313]' -.meas tran sum_energy_per_cycle_sb_mux[0to11] -+ param='sum_energy_per_cycle_sb_mux[0to10]+energy_per_cycle_sb_mux[0][1]_rrnode[313]' -Xmux_1level_tapbuf_size2[12] mux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->out sram[22]->outb sram[22]->out gvdd_mux_1level_tapbuf_size2[12] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[12], level=1, select_path_id=0. ***** -*****1***** -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -***** Signal mux_1level_tapbuf_size2[12]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[12]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[12] gvdd_mux_1level_tapbuf_size2[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[315] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[315] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[315] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[315] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[315] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[315] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[315] param='mux_1level_tapbuf_size2[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[12]_energy_per_cycle param='mux_1level_tapbuf_size2[12]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[315] param='mux_1level_tapbuf_size2[12]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[315] param='dynamic_power_sb_mux[0][1]_rrnode[315]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[315] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_rise_sb_mux[0][1]_rrnode[315]' to='start_rise_sb_mux[0][1]_rrnode[315]+switch_rise_sb_mux[0][1]_rrnode[315]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[315] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_fall_sb_mux[0][1]_rrnode[315]' to='start_fall_sb_mux[0][1]_rrnode[315]+switch_fall_sb_mux[0][1]_rrnode[315]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_sb_mux[0][1]_rrnode[315]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_sb_mux[0][1]_rrnode[315]' -***** Load for rr_node[315] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=24, type=4 ***** -Xchan_mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[47]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to12] -+ param='sum_leakage_power_sb_mux[0to11]+leakage_sb_mux[0][1]_rrnode[315]' -.meas tran sum_energy_per_cycle_sb_mux[0to12] -+ param='sum_energy_per_cycle_sb_mux[0to11]+energy_per_cycle_sb_mux[0][1]_rrnode[315]' -Xmux_1level_tapbuf_size2[13] mux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->out sram[23]->outb sram[23]->out gvdd_mux_1level_tapbuf_size2[13] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[13], level=1, select_path_id=0. ***** -*****1***** -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_1level_tapbuf_size2[13]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[13]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[13] gvdd_mux_1level_tapbuf_size2[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[317] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[317] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[317] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[317] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[317] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[317] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[317] param='mux_1level_tapbuf_size2[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[13]_energy_per_cycle param='mux_1level_tapbuf_size2[13]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[317] param='mux_1level_tapbuf_size2[13]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[317] param='dynamic_power_sb_mux[0][1]_rrnode[317]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[317] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_rise_sb_mux[0][1]_rrnode[317]' to='start_rise_sb_mux[0][1]_rrnode[317]+switch_rise_sb_mux[0][1]_rrnode[317]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[317] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_fall_sb_mux[0][1]_rrnode[317]' to='start_fall_sb_mux[0][1]_rrnode[317]+switch_fall_sb_mux[0][1]_rrnode[317]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_sb_mux[0][1]_rrnode[317]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_sb_mux[0][1]_rrnode[317]' -***** Load for rr_node[317] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=26, type=4 ***** -Xchan_mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[51]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to13] -+ param='sum_leakage_power_sb_mux[0to12]+leakage_sb_mux[0][1]_rrnode[317]' -.meas tran sum_energy_per_cycle_sb_mux[0to13] -+ param='sum_energy_per_cycle_sb_mux[0to12]+energy_per_cycle_sb_mux[0][1]_rrnode[317]' -Xmux_1level_tapbuf_size2[14] mux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->out sram[24]->outb sram[24]->out gvdd_mux_1level_tapbuf_size2[14] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[14], level=1, select_path_id=0. ***** -*****1***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -***** Signal mux_1level_tapbuf_size2[14]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[14]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[14] gvdd_mux_1level_tapbuf_size2[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[319] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[319] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[319] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[319] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[319] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[319] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[319] param='mux_1level_tapbuf_size2[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[14]_energy_per_cycle param='mux_1level_tapbuf_size2[14]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[319] param='mux_1level_tapbuf_size2[14]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[319] param='dynamic_power_sb_mux[0][1]_rrnode[319]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[319] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_rise_sb_mux[0][1]_rrnode[319]' to='start_rise_sb_mux[0][1]_rrnode[319]+switch_rise_sb_mux[0][1]_rrnode[319]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[319] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_fall_sb_mux[0][1]_rrnode[319]' to='start_fall_sb_mux[0][1]_rrnode[319]+switch_fall_sb_mux[0][1]_rrnode[319]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_sb_mux[0][1]_rrnode[319]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_sb_mux[0][1]_rrnode[319]' -***** Load for rr_node[319] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=28, type=4 ***** -Xchan_mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[54]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to14] -+ param='sum_leakage_power_sb_mux[0to13]+leakage_sb_mux[0][1]_rrnode[319]' -.meas tran sum_energy_per_cycle_sb_mux[0to14] -+ param='sum_energy_per_cycle_sb_mux[0to13]+energy_per_cycle_sb_mux[0][1]_rrnode[319]' -Xmux_1level_tapbuf_size2[15] mux_1level_tapbuf_size2[15]->in[0] mux_1level_tapbuf_size2[15]->in[1] mux_1level_tapbuf_size2[15]->out sram[25]->outb sram[25]->out gvdd_mux_1level_tapbuf_size2[15] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[15], level=1, select_path_id=0. ***** -*****1***** -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -***** Signal mux_1level_tapbuf_size2[15]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[15]->in[0] mux_1level_tapbuf_size2[15]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[15]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[15]->in[1] mux_1level_tapbuf_size2[15]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[15] gvdd_mux_1level_tapbuf_size2[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[321] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[321] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[321] when v(mux_1level_tapbuf_size2[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[321] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[321] when v(mux_1level_tapbuf_size2[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[321] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[15]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[321] param='mux_1level_tapbuf_size2[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[15]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[15]_energy_per_cycle param='mux_1level_tapbuf_size2[15]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[321] param='mux_1level_tapbuf_size2[15]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[321] param='dynamic_power_sb_mux[0][1]_rrnode[321]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[321] avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='start_rise_sb_mux[0][1]_rrnode[321]' to='start_rise_sb_mux[0][1]_rrnode[321]+switch_rise_sb_mux[0][1]_rrnode[321]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[321] avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='start_fall_sb_mux[0][1]_rrnode[321]' to='start_fall_sb_mux[0][1]_rrnode[321]+switch_fall_sb_mux[0][1]_rrnode[321]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_sb_mux[0][1]_rrnode[321]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_sb_mux[0][1]_rrnode[321]' -***** Load for rr_node[321] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=30, type=4 ***** -Xchan_mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[58]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[60]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to15] -+ param='sum_leakage_power_sb_mux[0to14]+leakage_sb_mux[0][1]_rrnode[321]' -.meas tran sum_energy_per_cycle_sb_mux[0to15] -+ param='sum_energy_per_cycle_sb_mux[0to14]+energy_per_cycle_sb_mux[0][1]_rrnode[321]' -Xmux_1level_tapbuf_size2[16] mux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->out sram[26]->outb sram[26]->out gvdd_mux_1level_tapbuf_size2[16] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[16], level=1, select_path_id=0. ***** -*****1***** -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -***** Signal mux_1level_tapbuf_size2[16]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[16]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[16] gvdd_mux_1level_tapbuf_size2[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[323] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[323] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[323] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[323] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[323] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[323] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[323] param='mux_1level_tapbuf_size2[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[16]_energy_per_cycle param='mux_1level_tapbuf_size2[16]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[323] param='mux_1level_tapbuf_size2[16]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[323] param='dynamic_power_sb_mux[0][1]_rrnode[323]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[323] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_rise_sb_mux[0][1]_rrnode[323]' to='start_rise_sb_mux[0][1]_rrnode[323]+switch_rise_sb_mux[0][1]_rrnode[323]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[323] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_fall_sb_mux[0][1]_rrnode[323]' to='start_fall_sb_mux[0][1]_rrnode[323]+switch_fall_sb_mux[0][1]_rrnode[323]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_sb_mux[0][1]_rrnode[323]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_sb_mux[0][1]_rrnode[323]' -***** Load for rr_node[323] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=32, type=4 ***** -Xchan_mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[62]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to16] -+ param='sum_leakage_power_sb_mux[0to15]+leakage_sb_mux[0][1]_rrnode[323]' -.meas tran sum_energy_per_cycle_sb_mux[0to16] -+ param='sum_energy_per_cycle_sb_mux[0to15]+energy_per_cycle_sb_mux[0][1]_rrnode[323]' -Xmux_1level_tapbuf_size2[17] mux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->out sram[27]->outb sram[27]->out gvdd_mux_1level_tapbuf_size2[17] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[17], level=1, select_path_id=0. ***** -*****1***** -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_1level_tapbuf_size2[17]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[17]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[17] gvdd_mux_1level_tapbuf_size2[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[325] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[325] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[325] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[325] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[325] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[325] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[325] param='mux_1level_tapbuf_size2[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[17]_energy_per_cycle param='mux_1level_tapbuf_size2[17]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[325] param='mux_1level_tapbuf_size2[17]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[325] param='dynamic_power_sb_mux[0][1]_rrnode[325]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[325] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_rise_sb_mux[0][1]_rrnode[325]' to='start_rise_sb_mux[0][1]_rrnode[325]+switch_rise_sb_mux[0][1]_rrnode[325]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[325] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_fall_sb_mux[0][1]_rrnode[325]' to='start_fall_sb_mux[0][1]_rrnode[325]+switch_fall_sb_mux[0][1]_rrnode[325]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_sb_mux[0][1]_rrnode[325]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_sb_mux[0][1]_rrnode[325]' -***** Load for rr_node[325] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=34, type=4 ***** -Xchan_mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[65]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to17] -+ param='sum_leakage_power_sb_mux[0to16]+leakage_sb_mux[0][1]_rrnode[325]' -.meas tran sum_energy_per_cycle_sb_mux[0to17] -+ param='sum_energy_per_cycle_sb_mux[0to16]+energy_per_cycle_sb_mux[0][1]_rrnode[325]' -Xmux_1level_tapbuf_size2[18] mux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->out sram[28]->outb sram[28]->out gvdd_mux_1level_tapbuf_size2[18] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[18], level=1, select_path_id=0. ***** -*****1***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -***** Signal mux_1level_tapbuf_size2[18]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[18]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[18] gvdd_mux_1level_tapbuf_size2[18] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[327] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[327] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[327] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[327] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[327] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[327] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[327] param='mux_1level_tapbuf_size2[18]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[18]_energy_per_cycle param='mux_1level_tapbuf_size2[18]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[327] param='mux_1level_tapbuf_size2[18]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[327] param='dynamic_power_sb_mux[0][1]_rrnode[327]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[327] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_rise_sb_mux[0][1]_rrnode[327]' to='start_rise_sb_mux[0][1]_rrnode[327]+switch_rise_sb_mux[0][1]_rrnode[327]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[327] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_fall_sb_mux[0][1]_rrnode[327]' to='start_fall_sb_mux[0][1]_rrnode[327]+switch_fall_sb_mux[0][1]_rrnode[327]' -.meas tran sum_leakage_power_mux[0to18] -+ param='sum_leakage_power_mux[0to17]+leakage_sb_mux[0][1]_rrnode[327]' -.meas tran sum_energy_per_cycle_mux[0to18] -+ param='sum_energy_per_cycle_mux[0to17]+energy_per_cycle_sb_mux[0][1]_rrnode[327]' -***** Load for rr_node[327] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=36, type=4 ***** -Xchan_mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[69]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to18] -+ param='sum_leakage_power_sb_mux[0to17]+leakage_sb_mux[0][1]_rrnode[327]' -.meas tran sum_energy_per_cycle_sb_mux[0to18] -+ param='sum_energy_per_cycle_sb_mux[0to17]+energy_per_cycle_sb_mux[0][1]_rrnode[327]' -Xmux_1level_tapbuf_size2[19] mux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->out sram[29]->outb sram[29]->out gvdd_mux_1level_tapbuf_size2[19] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[19], level=1, select_path_id=0. ***** -*****1***** -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -***** Signal mux_1level_tapbuf_size2[19]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[19]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[19] gvdd_mux_1level_tapbuf_size2[19] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[329] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[329] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[329] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[329] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[329] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[329] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[329] param='mux_1level_tapbuf_size2[19]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[19]_energy_per_cycle param='mux_1level_tapbuf_size2[19]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[329] param='mux_1level_tapbuf_size2[19]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[329] param='dynamic_power_sb_mux[0][1]_rrnode[329]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[329] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_rise_sb_mux[0][1]_rrnode[329]' to='start_rise_sb_mux[0][1]_rrnode[329]+switch_rise_sb_mux[0][1]_rrnode[329]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[329] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_fall_sb_mux[0][1]_rrnode[329]' to='start_fall_sb_mux[0][1]_rrnode[329]+switch_fall_sb_mux[0][1]_rrnode[329]' -.meas tran sum_leakage_power_mux[0to19] -+ param='sum_leakage_power_mux[0to18]+leakage_sb_mux[0][1]_rrnode[329]' -.meas tran sum_energy_per_cycle_mux[0to19] -+ param='sum_energy_per_cycle_mux[0to18]+energy_per_cycle_sb_mux[0][1]_rrnode[329]' -***** Load for rr_node[329] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=38, type=4 ***** -Xchan_mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[73]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to19] -+ param='sum_leakage_power_sb_mux[0to18]+leakage_sb_mux[0][1]_rrnode[329]' -.meas tran sum_energy_per_cycle_sb_mux[0to19] -+ param='sum_energy_per_cycle_sb_mux[0to18]+energy_per_cycle_sb_mux[0][1]_rrnode[329]' -Xmux_1level_tapbuf_size2[20] mux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->out sram[30]->outb sram[30]->out gvdd_mux_1level_tapbuf_size2[20] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[20], level=1, select_path_id=0. ***** -*****1***** -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -***** Signal mux_1level_tapbuf_size2[20]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[20]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[20] gvdd_mux_1level_tapbuf_size2[20] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[331] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[331] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[331] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[331] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[331] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[331] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[331] param='mux_1level_tapbuf_size2[20]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[20]_energy_per_cycle param='mux_1level_tapbuf_size2[20]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[331] param='mux_1level_tapbuf_size2[20]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[331] param='dynamic_power_sb_mux[0][1]_rrnode[331]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[331] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_rise_sb_mux[0][1]_rrnode[331]' to='start_rise_sb_mux[0][1]_rrnode[331]+switch_rise_sb_mux[0][1]_rrnode[331]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[331] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_fall_sb_mux[0][1]_rrnode[331]' to='start_fall_sb_mux[0][1]_rrnode[331]+switch_fall_sb_mux[0][1]_rrnode[331]' -.meas tran sum_leakage_power_mux[0to20] -+ param='sum_leakage_power_mux[0to19]+leakage_sb_mux[0][1]_rrnode[331]' -.meas tran sum_energy_per_cycle_mux[0to20] -+ param='sum_energy_per_cycle_mux[0to19]+energy_per_cycle_sb_mux[0][1]_rrnode[331]' -***** Load for rr_node[331] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=40, type=4 ***** -Xchan_mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[78]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to20] -+ param='sum_leakage_power_sb_mux[0to19]+leakage_sb_mux[0][1]_rrnode[331]' -.meas tran sum_energy_per_cycle_sb_mux[0to20] -+ param='sum_energy_per_cycle_sb_mux[0to19]+energy_per_cycle_sb_mux[0][1]_rrnode[331]' -Xmux_1level_tapbuf_size2[21] mux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->out sram[31]->outb sram[31]->out gvdd_mux_1level_tapbuf_size2[21] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[21], level=1, select_path_id=0. ***** -*****1***** -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_1level_tapbuf_size2[21]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[21]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[21] gvdd_mux_1level_tapbuf_size2[21] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[333] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[333] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[333] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[333] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[333] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[333] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[333] param='mux_1level_tapbuf_size2[21]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[21]_energy_per_cycle param='mux_1level_tapbuf_size2[21]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[333] param='mux_1level_tapbuf_size2[21]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[333] param='dynamic_power_sb_mux[0][1]_rrnode[333]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[333] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_rise_sb_mux[0][1]_rrnode[333]' to='start_rise_sb_mux[0][1]_rrnode[333]+switch_rise_sb_mux[0][1]_rrnode[333]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[333] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_fall_sb_mux[0][1]_rrnode[333]' to='start_fall_sb_mux[0][1]_rrnode[333]+switch_fall_sb_mux[0][1]_rrnode[333]' -.meas tran sum_leakage_power_mux[0to21] -+ param='sum_leakage_power_mux[0to20]+leakage_sb_mux[0][1]_rrnode[333]' -.meas tran sum_energy_per_cycle_mux[0to21] -+ param='sum_energy_per_cycle_mux[0to20]+energy_per_cycle_sb_mux[0][1]_rrnode[333]' -***** Load for rr_node[333] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=42, type=4 ***** -Xchan_mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[82]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to21] -+ param='sum_leakage_power_sb_mux[0to20]+leakage_sb_mux[0][1]_rrnode[333]' -.meas tran sum_energy_per_cycle_sb_mux[0to21] -+ param='sum_energy_per_cycle_sb_mux[0to20]+energy_per_cycle_sb_mux[0][1]_rrnode[333]' -Xmux_1level_tapbuf_size2[22] mux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->out sram[32]->outb sram[32]->out gvdd_mux_1level_tapbuf_size2[22] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[22], level=1, select_path_id=0. ***** -*****1***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -***** Signal mux_1level_tapbuf_size2[22]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[22]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[22] gvdd_mux_1level_tapbuf_size2[22] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[335] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[335] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[335] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[335] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[335] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[335] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[335] param='mux_1level_tapbuf_size2[22]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[22]_energy_per_cycle param='mux_1level_tapbuf_size2[22]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[335] param='mux_1level_tapbuf_size2[22]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[335] param='dynamic_power_sb_mux[0][1]_rrnode[335]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[335] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_rise_sb_mux[0][1]_rrnode[335]' to='start_rise_sb_mux[0][1]_rrnode[335]+switch_rise_sb_mux[0][1]_rrnode[335]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[335] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_fall_sb_mux[0][1]_rrnode[335]' to='start_fall_sb_mux[0][1]_rrnode[335]+switch_fall_sb_mux[0][1]_rrnode[335]' -.meas tran sum_leakage_power_mux[0to22] -+ param='sum_leakage_power_mux[0to21]+leakage_sb_mux[0][1]_rrnode[335]' -.meas tran sum_energy_per_cycle_mux[0to22] -+ param='sum_energy_per_cycle_mux[0to21]+energy_per_cycle_sb_mux[0][1]_rrnode[335]' -***** Load for rr_node[335] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=44, type=4 ***** -Xchan_mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[86]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to22] -+ param='sum_leakage_power_sb_mux[0to21]+leakage_sb_mux[0][1]_rrnode[335]' -.meas tran sum_energy_per_cycle_sb_mux[0to22] -+ param='sum_energy_per_cycle_sb_mux[0to21]+energy_per_cycle_sb_mux[0][1]_rrnode[335]' -Xmux_1level_tapbuf_size2[23] mux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->out sram[33]->outb sram[33]->out gvdd_mux_1level_tapbuf_size2[23] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[23], level=1, select_path_id=0. ***** -*****1***** -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -***** Signal mux_1level_tapbuf_size2[23]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[23]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[23] gvdd_mux_1level_tapbuf_size2[23] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[337] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[337] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[337] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[337] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[337] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[337] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[337] param='mux_1level_tapbuf_size2[23]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[23]_energy_per_cycle param='mux_1level_tapbuf_size2[23]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[337] param='mux_1level_tapbuf_size2[23]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[337] param='dynamic_power_sb_mux[0][1]_rrnode[337]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[337] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_rise_sb_mux[0][1]_rrnode[337]' to='start_rise_sb_mux[0][1]_rrnode[337]+switch_rise_sb_mux[0][1]_rrnode[337]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[337] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_fall_sb_mux[0][1]_rrnode[337]' to='start_fall_sb_mux[0][1]_rrnode[337]+switch_fall_sb_mux[0][1]_rrnode[337]' -.meas tran sum_leakage_power_mux[0to23] -+ param='sum_leakage_power_mux[0to22]+leakage_sb_mux[0][1]_rrnode[337]' -.meas tran sum_energy_per_cycle_mux[0to23] -+ param='sum_energy_per_cycle_mux[0to22]+energy_per_cycle_sb_mux[0][1]_rrnode[337]' -***** Load for rr_node[337] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=46, type=4 ***** -Xchan_mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[91]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to23] -+ param='sum_leakage_power_sb_mux[0to22]+leakage_sb_mux[0][1]_rrnode[337]' -.meas tran sum_energy_per_cycle_sb_mux[0to23] -+ param='sum_energy_per_cycle_sb_mux[0to22]+energy_per_cycle_sb_mux[0][1]_rrnode[337]' -Xmux_1level_tapbuf_size2[24] mux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->out sram[34]->outb sram[34]->out gvdd_mux_1level_tapbuf_size2[24] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[24], level=1, select_path_id=0. ***** -*****1***** -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -***** Signal mux_1level_tapbuf_size2[24]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[24]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[24] gvdd_mux_1level_tapbuf_size2[24] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[339] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[339] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[339] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[339] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[339] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[339] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[339] param='mux_1level_tapbuf_size2[24]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[24]_energy_per_cycle param='mux_1level_tapbuf_size2[24]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[339] param='mux_1level_tapbuf_size2[24]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[339] param='dynamic_power_sb_mux[0][1]_rrnode[339]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[339] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_rise_sb_mux[0][1]_rrnode[339]' to='start_rise_sb_mux[0][1]_rrnode[339]+switch_rise_sb_mux[0][1]_rrnode[339]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[339] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_fall_sb_mux[0][1]_rrnode[339]' to='start_fall_sb_mux[0][1]_rrnode[339]+switch_fall_sb_mux[0][1]_rrnode[339]' -.meas tran sum_leakage_power_mux[0to24] -+ param='sum_leakage_power_mux[0to23]+leakage_sb_mux[0][1]_rrnode[339]' -.meas tran sum_energy_per_cycle_mux[0to24] -+ param='sum_energy_per_cycle_mux[0to23]+energy_per_cycle_sb_mux[0][1]_rrnode[339]' -***** Load for rr_node[339] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=48, type=4 ***** -Xchan_mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[94]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to24] -+ param='sum_leakage_power_sb_mux[0to23]+leakage_sb_mux[0][1]_rrnode[339]' -.meas tran sum_energy_per_cycle_sb_mux[0to24] -+ param='sum_energy_per_cycle_sb_mux[0to23]+energy_per_cycle_sb_mux[0][1]_rrnode[339]' -Xmux_1level_tapbuf_size2[25] mux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->out sram[35]->outb sram[35]->out gvdd_mux_1level_tapbuf_size2[25] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[25], level=1, select_path_id=0. ***** -*****1***** -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -***** Signal mux_1level_tapbuf_size2[25]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[25]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[25] gvdd_mux_1level_tapbuf_size2[25] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[341] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[341] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[341] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[341] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[341] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[341] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[341] param='mux_1level_tapbuf_size2[25]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[25]_energy_per_cycle param='mux_1level_tapbuf_size2[25]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[341] param='mux_1level_tapbuf_size2[25]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[341] param='dynamic_power_sb_mux[0][1]_rrnode[341]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[341] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_rise_sb_mux[0][1]_rrnode[341]' to='start_rise_sb_mux[0][1]_rrnode[341]+switch_rise_sb_mux[0][1]_rrnode[341]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[341] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_fall_sb_mux[0][1]_rrnode[341]' to='start_fall_sb_mux[0][1]_rrnode[341]+switch_fall_sb_mux[0][1]_rrnode[341]' -.meas tran sum_leakage_power_mux[0to25] -+ param='sum_leakage_power_mux[0to24]+leakage_sb_mux[0][1]_rrnode[341]' -.meas tran sum_energy_per_cycle_mux[0to25] -+ param='sum_energy_per_cycle_mux[0to24]+energy_per_cycle_sb_mux[0][1]_rrnode[341]' -***** Load for rr_node[341] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=50, type=4 ***** -Xchan_mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[98]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to25] -+ param='sum_leakage_power_sb_mux[0to24]+leakage_sb_mux[0][1]_rrnode[341]' -.meas tran sum_energy_per_cycle_sb_mux[0to25] -+ param='sum_energy_per_cycle_sb_mux[0to24]+energy_per_cycle_sb_mux[0][1]_rrnode[341]' -Xmux_1level_tapbuf_size2[26] mux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->out sram[36]->outb sram[36]->out gvdd_mux_1level_tapbuf_size2[26] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[26], level=1, select_path_id=0. ***** -*****1***** -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -***** Signal mux_1level_tapbuf_size2[26]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[26]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[26] gvdd_mux_1level_tapbuf_size2[26] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[343] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[343] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[343] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[343] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[343] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[343] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[343] param='mux_1level_tapbuf_size2[26]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[26]_energy_per_cycle param='mux_1level_tapbuf_size2[26]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[343] param='mux_1level_tapbuf_size2[26]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[343] param='dynamic_power_sb_mux[0][1]_rrnode[343]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[343] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_rise_sb_mux[0][1]_rrnode[343]' to='start_rise_sb_mux[0][1]_rrnode[343]+switch_rise_sb_mux[0][1]_rrnode[343]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[343] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_fall_sb_mux[0][1]_rrnode[343]' to='start_fall_sb_mux[0][1]_rrnode[343]+switch_fall_sb_mux[0][1]_rrnode[343]' -.meas tran sum_leakage_power_mux[0to26] -+ param='sum_leakage_power_mux[0to25]+leakage_sb_mux[0][1]_rrnode[343]' -.meas tran sum_energy_per_cycle_mux[0to26] -+ param='sum_energy_per_cycle_mux[0to25]+energy_per_cycle_sb_mux[0][1]_rrnode[343]' -***** Load for rr_node[343] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=52, type=4 ***** -Xchan_mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[101]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to26] -+ param='sum_leakage_power_sb_mux[0to25]+leakage_sb_mux[0][1]_rrnode[343]' -.meas tran sum_energy_per_cycle_sb_mux[0to26] -+ param='sum_energy_per_cycle_sb_mux[0to25]+energy_per_cycle_sb_mux[0][1]_rrnode[343]' -Xmux_1level_tapbuf_size2[27] mux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->out sram[37]->outb sram[37]->out gvdd_mux_1level_tapbuf_size2[27] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[27], level=1, select_path_id=0. ***** -*****1***** -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -***** Signal mux_1level_tapbuf_size2[27]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[27]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[27] gvdd_mux_1level_tapbuf_size2[27] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[345] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[345] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[345] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[345] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[345] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[345] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[345] param='mux_1level_tapbuf_size2[27]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[27]_energy_per_cycle param='mux_1level_tapbuf_size2[27]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[345] param='mux_1level_tapbuf_size2[27]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[345] param='dynamic_power_sb_mux[0][1]_rrnode[345]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[345] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_rise_sb_mux[0][1]_rrnode[345]' to='start_rise_sb_mux[0][1]_rrnode[345]+switch_rise_sb_mux[0][1]_rrnode[345]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[345] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_fall_sb_mux[0][1]_rrnode[345]' to='start_fall_sb_mux[0][1]_rrnode[345]+switch_fall_sb_mux[0][1]_rrnode[345]' -.meas tran sum_leakage_power_mux[0to27] -+ param='sum_leakage_power_mux[0to26]+leakage_sb_mux[0][1]_rrnode[345]' -.meas tran sum_energy_per_cycle_mux[0to27] -+ param='sum_energy_per_cycle_mux[0to26]+energy_per_cycle_sb_mux[0][1]_rrnode[345]' -***** Load for rr_node[345] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=54, type=4 ***** -Xchan_mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[104]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to27] -+ param='sum_leakage_power_sb_mux[0to26]+leakage_sb_mux[0][1]_rrnode[345]' -.meas tran sum_energy_per_cycle_sb_mux[0to27] -+ param='sum_energy_per_cycle_sb_mux[0to26]+energy_per_cycle_sb_mux[0][1]_rrnode[345]' -Xmux_1level_tapbuf_size2[28] mux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->out sram[38]->outb sram[38]->out gvdd_mux_1level_tapbuf_size2[28] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[28], level=1, select_path_id=0. ***** -*****1***** -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -***** Signal mux_1level_tapbuf_size2[28]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[28]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[28] gvdd_mux_1level_tapbuf_size2[28] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[347] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[347] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[347] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[347] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[347] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[347] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[347] param='mux_1level_tapbuf_size2[28]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[28]_energy_per_cycle param='mux_1level_tapbuf_size2[28]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[347] param='mux_1level_tapbuf_size2[28]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[347] param='dynamic_power_sb_mux[0][1]_rrnode[347]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[347] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_rise_sb_mux[0][1]_rrnode[347]' to='start_rise_sb_mux[0][1]_rrnode[347]+switch_rise_sb_mux[0][1]_rrnode[347]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[347] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_fall_sb_mux[0][1]_rrnode[347]' to='start_fall_sb_mux[0][1]_rrnode[347]+switch_fall_sb_mux[0][1]_rrnode[347]' -.meas tran sum_leakage_power_mux[0to28] -+ param='sum_leakage_power_mux[0to27]+leakage_sb_mux[0][1]_rrnode[347]' -.meas tran sum_energy_per_cycle_mux[0to28] -+ param='sum_energy_per_cycle_mux[0to27]+energy_per_cycle_sb_mux[0][1]_rrnode[347]' -***** Load for rr_node[347] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=56, type=4 ***** -Xchan_mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[109]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to28] -+ param='sum_leakage_power_sb_mux[0to27]+leakage_sb_mux[0][1]_rrnode[347]' -.meas tran sum_energy_per_cycle_sb_mux[0to28] -+ param='sum_energy_per_cycle_sb_mux[0to27]+energy_per_cycle_sb_mux[0][1]_rrnode[347]' -Xmux_1level_tapbuf_size2[29] mux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->out sram[39]->outb sram[39]->out gvdd_mux_1level_tapbuf_size2[29] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[29], level=1, select_path_id=0. ***** -*****1***** -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -***** Signal mux_1level_tapbuf_size2[29]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[29]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[29] gvdd_mux_1level_tapbuf_size2[29] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[349] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[349] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[349] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[349] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[349] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[349] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[349] param='mux_1level_tapbuf_size2[29]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[29]_energy_per_cycle param='mux_1level_tapbuf_size2[29]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[349] param='mux_1level_tapbuf_size2[29]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[349] param='dynamic_power_sb_mux[0][1]_rrnode[349]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[349] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_rise_sb_mux[0][1]_rrnode[349]' to='start_rise_sb_mux[0][1]_rrnode[349]+switch_rise_sb_mux[0][1]_rrnode[349]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[349] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_fall_sb_mux[0][1]_rrnode[349]' to='start_fall_sb_mux[0][1]_rrnode[349]+switch_fall_sb_mux[0][1]_rrnode[349]' -.meas tran sum_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to28]+leakage_sb_mux[0][1]_rrnode[349]' -.meas tran sum_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to28]+energy_per_cycle_sb_mux[0][1]_rrnode[349]' -***** Load for rr_node[349] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=58, type=4 ***** -Xchan_mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[112]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to29] -+ param='sum_leakage_power_sb_mux[0to28]+leakage_sb_mux[0][1]_rrnode[349]' -.meas tran sum_energy_per_cycle_sb_mux[0to29] -+ param='sum_energy_per_cycle_sb_mux[0to28]+energy_per_cycle_sb_mux[0][1]_rrnode[349]' -Xmux_1level_tapbuf_size2[30] mux_1level_tapbuf_size2[30]->in[0] mux_1level_tapbuf_size2[30]->in[1] mux_1level_tapbuf_size2[30]->out sram[40]->outb sram[40]->out gvdd_mux_1level_tapbuf_size2[30] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[30], level=1, select_path_id=0. ***** -*****1***** -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -***** Signal mux_1level_tapbuf_size2[30]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[30]->in[0] mux_1level_tapbuf_size2[30]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[30]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[30]->in[1] mux_1level_tapbuf_size2[30]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[30] gvdd_mux_1level_tapbuf_size2[30] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[351] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[351] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[351] when v(mux_1level_tapbuf_size2[30]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[351] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[351] when v(mux_1level_tapbuf_size2[30]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[351] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[30]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[351] param='mux_1level_tapbuf_size2[30]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[30]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[30]_energy_per_cycle param='mux_1level_tapbuf_size2[30]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[351] param='mux_1level_tapbuf_size2[30]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[351] param='dynamic_power_sb_mux[0][1]_rrnode[351]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[351] avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='start_rise_sb_mux[0][1]_rrnode[351]' to='start_rise_sb_mux[0][1]_rrnode[351]+switch_rise_sb_mux[0][1]_rrnode[351]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[351] avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='start_fall_sb_mux[0][1]_rrnode[351]' to='start_fall_sb_mux[0][1]_rrnode[351]+switch_fall_sb_mux[0][1]_rrnode[351]' -.meas tran sum_leakage_power_mux[0to30] -+ param='sum_leakage_power_mux[0to29]+leakage_sb_mux[0][1]_rrnode[351]' -.meas tran sum_energy_per_cycle_mux[0to30] -+ param='sum_energy_per_cycle_mux[0to29]+energy_per_cycle_sb_mux[0][1]_rrnode[351]' -***** Load for rr_node[351] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=60, type=4 ***** -Xchan_mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[116]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to30] -+ param='sum_leakage_power_sb_mux[0to29]+leakage_sb_mux[0][1]_rrnode[351]' -.meas tran sum_energy_per_cycle_sb_mux[0to30] -+ param='sum_energy_per_cycle_sb_mux[0to29]+energy_per_cycle_sb_mux[0][1]_rrnode[351]' -Xmux_1level_tapbuf_size2[31] mux_1level_tapbuf_size2[31]->in[0] mux_1level_tapbuf_size2[31]->in[1] mux_1level_tapbuf_size2[31]->out sram[41]->outb sram[41]->out gvdd_mux_1level_tapbuf_size2[31] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[31], level=1, select_path_id=0. ***** -*****1***** -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -***** Signal mux_1level_tapbuf_size2[31]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[31]->in[0] mux_1level_tapbuf_size2[31]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[31]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[31]->in[1] mux_1level_tapbuf_size2[31]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[31] gvdd_mux_1level_tapbuf_size2[31] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[353] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[353] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[353] when v(mux_1level_tapbuf_size2[31]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[353] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[353] when v(mux_1level_tapbuf_size2[31]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[353] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[31]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[353] param='mux_1level_tapbuf_size2[31]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[31]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[31]_energy_per_cycle param='mux_1level_tapbuf_size2[31]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[353] param='mux_1level_tapbuf_size2[31]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[353] param='dynamic_power_sb_mux[0][1]_rrnode[353]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[353] avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='start_rise_sb_mux[0][1]_rrnode[353]' to='start_rise_sb_mux[0][1]_rrnode[353]+switch_rise_sb_mux[0][1]_rrnode[353]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[353] avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='start_fall_sb_mux[0][1]_rrnode[353]' to='start_fall_sb_mux[0][1]_rrnode[353]+switch_fall_sb_mux[0][1]_rrnode[353]' -.meas tran sum_leakage_power_mux[0to31] -+ param='sum_leakage_power_mux[0to30]+leakage_sb_mux[0][1]_rrnode[353]' -.meas tran sum_energy_per_cycle_mux[0to31] -+ param='sum_energy_per_cycle_mux[0to30]+energy_per_cycle_sb_mux[0][1]_rrnode[353]' -***** Load for rr_node[353] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=62, type=4 ***** -Xchan_mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[120]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to31] -+ param='sum_leakage_power_sb_mux[0to30]+leakage_sb_mux[0][1]_rrnode[353]' -.meas tran sum_energy_per_cycle_sb_mux[0to31] -+ param='sum_energy_per_cycle_sb_mux[0to30]+energy_per_cycle_sb_mux[0][1]_rrnode[353]' -Xmux_1level_tapbuf_size2[32] mux_1level_tapbuf_size2[32]->in[0] mux_1level_tapbuf_size2[32]->in[1] mux_1level_tapbuf_size2[32]->out sram[42]->outb sram[42]->out gvdd_mux_1level_tapbuf_size2[32] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[32], level=1, select_path_id=0. ***** -*****1***** -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -***** Signal mux_1level_tapbuf_size2[32]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[32]->in[0] mux_1level_tapbuf_size2[32]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[32]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[32]->in[1] mux_1level_tapbuf_size2[32]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[32] gvdd_mux_1level_tapbuf_size2[32] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[355] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[355] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[355] when v(mux_1level_tapbuf_size2[32]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[355] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[355] when v(mux_1level_tapbuf_size2[32]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[355] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[32]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[355] param='mux_1level_tapbuf_size2[32]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[32]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[32]_energy_per_cycle param='mux_1level_tapbuf_size2[32]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[355] param='mux_1level_tapbuf_size2[32]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[355] param='dynamic_power_sb_mux[0][1]_rrnode[355]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[355] avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='start_rise_sb_mux[0][1]_rrnode[355]' to='start_rise_sb_mux[0][1]_rrnode[355]+switch_rise_sb_mux[0][1]_rrnode[355]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[355] avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='start_fall_sb_mux[0][1]_rrnode[355]' to='start_fall_sb_mux[0][1]_rrnode[355]+switch_fall_sb_mux[0][1]_rrnode[355]' -.meas tran sum_leakage_power_mux[0to32] -+ param='sum_leakage_power_mux[0to31]+leakage_sb_mux[0][1]_rrnode[355]' -.meas tran sum_energy_per_cycle_mux[0to32] -+ param='sum_energy_per_cycle_mux[0to31]+energy_per_cycle_sb_mux[0][1]_rrnode[355]' -***** Load for rr_node[355] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=64, type=4 ***** -Xchan_mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[125]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[128]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to32] -+ param='sum_leakage_power_sb_mux[0to31]+leakage_sb_mux[0][1]_rrnode[355]' -.meas tran sum_energy_per_cycle_sb_mux[0to32] -+ param='sum_energy_per_cycle_sb_mux[0to31]+energy_per_cycle_sb_mux[0][1]_rrnode[355]' -Xmux_1level_tapbuf_size2[33] mux_1level_tapbuf_size2[33]->in[0] mux_1level_tapbuf_size2[33]->in[1] mux_1level_tapbuf_size2[33]->out sram[43]->outb sram[43]->out gvdd_mux_1level_tapbuf_size2[33] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[33], level=1, select_path_id=0. ***** -*****1***** -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -***** Signal mux_1level_tapbuf_size2[33]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[33]->in[0] mux_1level_tapbuf_size2[33]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[33]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[33]->in[1] mux_1level_tapbuf_size2[33]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[33] gvdd_mux_1level_tapbuf_size2[33] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[357] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[357] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[357] when v(mux_1level_tapbuf_size2[33]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[357] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[357] when v(mux_1level_tapbuf_size2[33]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[357] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[33]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[357] param='mux_1level_tapbuf_size2[33]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[33]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[33]_energy_per_cycle param='mux_1level_tapbuf_size2[33]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[357] param='mux_1level_tapbuf_size2[33]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[357] param='dynamic_power_sb_mux[0][1]_rrnode[357]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[357] avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='start_rise_sb_mux[0][1]_rrnode[357]' to='start_rise_sb_mux[0][1]_rrnode[357]+switch_rise_sb_mux[0][1]_rrnode[357]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[357] avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='start_fall_sb_mux[0][1]_rrnode[357]' to='start_fall_sb_mux[0][1]_rrnode[357]+switch_fall_sb_mux[0][1]_rrnode[357]' -.meas tran sum_leakage_power_mux[0to33] -+ param='sum_leakage_power_mux[0to32]+leakage_sb_mux[0][1]_rrnode[357]' -.meas tran sum_energy_per_cycle_mux[0to33] -+ param='sum_energy_per_cycle_mux[0to32]+energy_per_cycle_sb_mux[0][1]_rrnode[357]' -***** Load for rr_node[357] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=66, type=4 ***** -Xchan_mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[130]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to33] -+ param='sum_leakage_power_sb_mux[0to32]+leakage_sb_mux[0][1]_rrnode[357]' -.meas tran sum_energy_per_cycle_sb_mux[0to33] -+ param='sum_energy_per_cycle_sb_mux[0to32]+energy_per_cycle_sb_mux[0][1]_rrnode[357]' -Xmux_1level_tapbuf_size2[34] mux_1level_tapbuf_size2[34]->in[0] mux_1level_tapbuf_size2[34]->in[1] mux_1level_tapbuf_size2[34]->out sram[44]->outb sram[44]->out gvdd_mux_1level_tapbuf_size2[34] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[34], level=1, select_path_id=0. ***** -*****1***** -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -***** Signal mux_1level_tapbuf_size2[34]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[34]->in[0] mux_1level_tapbuf_size2[34]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[34]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[34]->in[1] mux_1level_tapbuf_size2[34]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[34] gvdd_mux_1level_tapbuf_size2[34] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[359] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[359] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[359] when v(mux_1level_tapbuf_size2[34]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[359] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[359] when v(mux_1level_tapbuf_size2[34]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[359] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[34]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[359] param='mux_1level_tapbuf_size2[34]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[34]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[34]_energy_per_cycle param='mux_1level_tapbuf_size2[34]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[359] param='mux_1level_tapbuf_size2[34]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[359] param='dynamic_power_sb_mux[0][1]_rrnode[359]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[359] avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='start_rise_sb_mux[0][1]_rrnode[359]' to='start_rise_sb_mux[0][1]_rrnode[359]+switch_rise_sb_mux[0][1]_rrnode[359]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[359] avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='start_fall_sb_mux[0][1]_rrnode[359]' to='start_fall_sb_mux[0][1]_rrnode[359]+switch_fall_sb_mux[0][1]_rrnode[359]' -.meas tran sum_leakage_power_mux[0to34] -+ param='sum_leakage_power_mux[0to33]+leakage_sb_mux[0][1]_rrnode[359]' -.meas tran sum_energy_per_cycle_mux[0to34] -+ param='sum_energy_per_cycle_mux[0to33]+energy_per_cycle_sb_mux[0][1]_rrnode[359]' -***** Load for rr_node[359] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=68, type=4 ***** -Xchan_mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[133]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to34] -+ param='sum_leakage_power_sb_mux[0to33]+leakage_sb_mux[0][1]_rrnode[359]' -.meas tran sum_energy_per_cycle_sb_mux[0to34] -+ param='sum_energy_per_cycle_sb_mux[0to33]+energy_per_cycle_sb_mux[0][1]_rrnode[359]' -Xmux_1level_tapbuf_size2[35] mux_1level_tapbuf_size2[35]->in[0] mux_1level_tapbuf_size2[35]->in[1] mux_1level_tapbuf_size2[35]->out sram[45]->outb sram[45]->out gvdd_mux_1level_tapbuf_size2[35] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[35], level=1, select_path_id=0. ***** -*****1***** -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -***** Signal mux_1level_tapbuf_size2[35]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[35]->in[0] mux_1level_tapbuf_size2[35]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[35]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[35]->in[1] mux_1level_tapbuf_size2[35]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[35] gvdd_mux_1level_tapbuf_size2[35] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[361] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[361] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[361] when v(mux_1level_tapbuf_size2[35]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[361] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[361] when v(mux_1level_tapbuf_size2[35]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[361] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[35]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[361] param='mux_1level_tapbuf_size2[35]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[35]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[35]_energy_per_cycle param='mux_1level_tapbuf_size2[35]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[361] param='mux_1level_tapbuf_size2[35]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[361] param='dynamic_power_sb_mux[0][1]_rrnode[361]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[361] avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='start_rise_sb_mux[0][1]_rrnode[361]' to='start_rise_sb_mux[0][1]_rrnode[361]+switch_rise_sb_mux[0][1]_rrnode[361]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[361] avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='start_fall_sb_mux[0][1]_rrnode[361]' to='start_fall_sb_mux[0][1]_rrnode[361]+switch_fall_sb_mux[0][1]_rrnode[361]' -.meas tran sum_leakage_power_mux[0to35] -+ param='sum_leakage_power_mux[0to34]+leakage_sb_mux[0][1]_rrnode[361]' -.meas tran sum_energy_per_cycle_mux[0to35] -+ param='sum_energy_per_cycle_mux[0to34]+energy_per_cycle_sb_mux[0][1]_rrnode[361]' -***** Load for rr_node[361] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=70, type=4 ***** -Xchan_mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[136]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to35] -+ param='sum_leakage_power_sb_mux[0to34]+leakage_sb_mux[0][1]_rrnode[361]' -.meas tran sum_energy_per_cycle_sb_mux[0to35] -+ param='sum_energy_per_cycle_sb_mux[0to34]+energy_per_cycle_sb_mux[0][1]_rrnode[361]' -Xmux_1level_tapbuf_size2[36] mux_1level_tapbuf_size2[36]->in[0] mux_1level_tapbuf_size2[36]->in[1] mux_1level_tapbuf_size2[36]->out sram[46]->outb sram[46]->out gvdd_mux_1level_tapbuf_size2[36] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[36], level=1, select_path_id=0. ***** -*****1***** -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -***** Signal mux_1level_tapbuf_size2[36]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[36]->in[0] mux_1level_tapbuf_size2[36]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[36]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[36]->in[1] mux_1level_tapbuf_size2[36]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[36] gvdd_mux_1level_tapbuf_size2[36] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[363] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[363] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[363] when v(mux_1level_tapbuf_size2[36]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[363] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[363] when v(mux_1level_tapbuf_size2[36]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[363] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[36]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[363] param='mux_1level_tapbuf_size2[36]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[36]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[36]_energy_per_cycle param='mux_1level_tapbuf_size2[36]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[363] param='mux_1level_tapbuf_size2[36]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[363] param='dynamic_power_sb_mux[0][1]_rrnode[363]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[363] avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='start_rise_sb_mux[0][1]_rrnode[363]' to='start_rise_sb_mux[0][1]_rrnode[363]+switch_rise_sb_mux[0][1]_rrnode[363]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[363] avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='start_fall_sb_mux[0][1]_rrnode[363]' to='start_fall_sb_mux[0][1]_rrnode[363]+switch_fall_sb_mux[0][1]_rrnode[363]' -.meas tran sum_leakage_power_mux[0to36] -+ param='sum_leakage_power_mux[0to35]+leakage_sb_mux[0][1]_rrnode[363]' -.meas tran sum_energy_per_cycle_mux[0to36] -+ param='sum_energy_per_cycle_mux[0to35]+energy_per_cycle_sb_mux[0][1]_rrnode[363]' -***** Load for rr_node[363] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=72, type=4 ***** -Xchan_mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[140]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to36] -+ param='sum_leakage_power_sb_mux[0to35]+leakage_sb_mux[0][1]_rrnode[363]' -.meas tran sum_energy_per_cycle_sb_mux[0to36] -+ param='sum_energy_per_cycle_sb_mux[0to35]+energy_per_cycle_sb_mux[0][1]_rrnode[363]' -Xmux_1level_tapbuf_size2[37] mux_1level_tapbuf_size2[37]->in[0] mux_1level_tapbuf_size2[37]->in[1] mux_1level_tapbuf_size2[37]->out sram[47]->outb sram[47]->out gvdd_mux_1level_tapbuf_size2[37] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[37], level=1, select_path_id=0. ***** -*****1***** -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -***** Signal mux_1level_tapbuf_size2[37]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[37]->in[0] mux_1level_tapbuf_size2[37]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[37]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[37]->in[1] mux_1level_tapbuf_size2[37]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[37] gvdd_mux_1level_tapbuf_size2[37] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[365] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[365] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[365] when v(mux_1level_tapbuf_size2[37]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[365] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[365] when v(mux_1level_tapbuf_size2[37]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[365] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[37]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[365] param='mux_1level_tapbuf_size2[37]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[37]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[37]_energy_per_cycle param='mux_1level_tapbuf_size2[37]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[365] param='mux_1level_tapbuf_size2[37]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[365] param='dynamic_power_sb_mux[0][1]_rrnode[365]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[365] avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='start_rise_sb_mux[0][1]_rrnode[365]' to='start_rise_sb_mux[0][1]_rrnode[365]+switch_rise_sb_mux[0][1]_rrnode[365]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[365] avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='start_fall_sb_mux[0][1]_rrnode[365]' to='start_fall_sb_mux[0][1]_rrnode[365]+switch_fall_sb_mux[0][1]_rrnode[365]' -.meas tran sum_leakage_power_mux[0to37] -+ param='sum_leakage_power_mux[0to36]+leakage_sb_mux[0][1]_rrnode[365]' -.meas tran sum_energy_per_cycle_mux[0to37] -+ param='sum_energy_per_cycle_mux[0to36]+energy_per_cycle_sb_mux[0][1]_rrnode[365]' -***** Load for rr_node[365] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=74, type=4 ***** -Xchan_mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[144]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to37] -+ param='sum_leakage_power_sb_mux[0to36]+leakage_sb_mux[0][1]_rrnode[365]' -.meas tran sum_energy_per_cycle_sb_mux[0to37] -+ param='sum_energy_per_cycle_sb_mux[0to36]+energy_per_cycle_sb_mux[0][1]_rrnode[365]' -Xmux_1level_tapbuf_size2[38] mux_1level_tapbuf_size2[38]->in[0] mux_1level_tapbuf_size2[38]->in[1] mux_1level_tapbuf_size2[38]->out sram[48]->outb sram[48]->out gvdd_mux_1level_tapbuf_size2[38] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[38], level=1, select_path_id=0. ***** -*****1***** -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -***** Signal mux_1level_tapbuf_size2[38]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[38]->in[0] mux_1level_tapbuf_size2[38]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[38]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[38]->in[1] mux_1level_tapbuf_size2[38]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[38] gvdd_mux_1level_tapbuf_size2[38] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[367] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[367] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[367] when v(mux_1level_tapbuf_size2[38]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[367] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[367] when v(mux_1level_tapbuf_size2[38]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[367] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[38]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[367] param='mux_1level_tapbuf_size2[38]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[38]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[38]_energy_per_cycle param='mux_1level_tapbuf_size2[38]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[367] param='mux_1level_tapbuf_size2[38]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[367] param='dynamic_power_sb_mux[0][1]_rrnode[367]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[367] avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='start_rise_sb_mux[0][1]_rrnode[367]' to='start_rise_sb_mux[0][1]_rrnode[367]+switch_rise_sb_mux[0][1]_rrnode[367]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[367] avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='start_fall_sb_mux[0][1]_rrnode[367]' to='start_fall_sb_mux[0][1]_rrnode[367]+switch_fall_sb_mux[0][1]_rrnode[367]' -.meas tran sum_leakage_power_mux[0to38] -+ param='sum_leakage_power_mux[0to37]+leakage_sb_mux[0][1]_rrnode[367]' -.meas tran sum_energy_per_cycle_mux[0to38] -+ param='sum_energy_per_cycle_mux[0to37]+energy_per_cycle_sb_mux[0][1]_rrnode[367]' -***** Load for rr_node[367] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=76, type=4 ***** -Xchan_mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[148]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to38] -+ param='sum_leakage_power_sb_mux[0to37]+leakage_sb_mux[0][1]_rrnode[367]' -.meas tran sum_energy_per_cycle_sb_mux[0to38] -+ param='sum_energy_per_cycle_sb_mux[0to37]+energy_per_cycle_sb_mux[0][1]_rrnode[367]' -Xmux_1level_tapbuf_size2[39] mux_1level_tapbuf_size2[39]->in[0] mux_1level_tapbuf_size2[39]->in[1] mux_1level_tapbuf_size2[39]->out sram[49]->outb sram[49]->out gvdd_mux_1level_tapbuf_size2[39] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[39], level=1, select_path_id=0. ***** -*****1***** -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -***** Signal mux_1level_tapbuf_size2[39]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[39]->in[0] mux_1level_tapbuf_size2[39]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[39]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[39]->in[1] mux_1level_tapbuf_size2[39]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[39] gvdd_mux_1level_tapbuf_size2[39] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[369] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[369] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[369] when v(mux_1level_tapbuf_size2[39]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[369] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[369] when v(mux_1level_tapbuf_size2[39]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[369] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[39]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[369] param='mux_1level_tapbuf_size2[39]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[39]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[39]_energy_per_cycle param='mux_1level_tapbuf_size2[39]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[369] param='mux_1level_tapbuf_size2[39]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[369] param='dynamic_power_sb_mux[0][1]_rrnode[369]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[369] avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='start_rise_sb_mux[0][1]_rrnode[369]' to='start_rise_sb_mux[0][1]_rrnode[369]+switch_rise_sb_mux[0][1]_rrnode[369]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[369] avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='start_fall_sb_mux[0][1]_rrnode[369]' to='start_fall_sb_mux[0][1]_rrnode[369]+switch_fall_sb_mux[0][1]_rrnode[369]' -.meas tran sum_leakage_power_mux[0to39] -+ param='sum_leakage_power_mux[0to38]+leakage_sb_mux[0][1]_rrnode[369]' -.meas tran sum_energy_per_cycle_mux[0to39] -+ param='sum_energy_per_cycle_mux[0to38]+energy_per_cycle_sb_mux[0][1]_rrnode[369]' -***** Load for rr_node[369] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=78, type=4 ***** -Xchan_mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[152]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to39] -+ param='sum_leakage_power_sb_mux[0to38]+leakage_sb_mux[0][1]_rrnode[369]' -.meas tran sum_energy_per_cycle_sb_mux[0to39] -+ param='sum_energy_per_cycle_sb_mux[0to38]+energy_per_cycle_sb_mux[0][1]_rrnode[369]' -Xmux_1level_tapbuf_size2[40] mux_1level_tapbuf_size2[40]->in[0] mux_1level_tapbuf_size2[40]->in[1] mux_1level_tapbuf_size2[40]->out sram[50]->outb sram[50]->out gvdd_mux_1level_tapbuf_size2[40] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[40], level=1, select_path_id=0. ***** -*****1***** -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -***** Signal mux_1level_tapbuf_size2[40]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[40]->in[0] mux_1level_tapbuf_size2[40]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[40]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[40]->in[1] mux_1level_tapbuf_size2[40]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[40] gvdd_mux_1level_tapbuf_size2[40] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[371] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[371] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[371] when v(mux_1level_tapbuf_size2[40]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[371] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[371] when v(mux_1level_tapbuf_size2[40]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[371] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[40]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[371] param='mux_1level_tapbuf_size2[40]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[40]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[40]_energy_per_cycle param='mux_1level_tapbuf_size2[40]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[371] param='mux_1level_tapbuf_size2[40]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[371] param='dynamic_power_sb_mux[0][1]_rrnode[371]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[371] avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='start_rise_sb_mux[0][1]_rrnode[371]' to='start_rise_sb_mux[0][1]_rrnode[371]+switch_rise_sb_mux[0][1]_rrnode[371]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[371] avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='start_fall_sb_mux[0][1]_rrnode[371]' to='start_fall_sb_mux[0][1]_rrnode[371]+switch_fall_sb_mux[0][1]_rrnode[371]' -.meas tran sum_leakage_power_mux[0to40] -+ param='sum_leakage_power_mux[0to39]+leakage_sb_mux[0][1]_rrnode[371]' -.meas tran sum_energy_per_cycle_mux[0to40] -+ param='sum_energy_per_cycle_mux[0to39]+energy_per_cycle_sb_mux[0][1]_rrnode[371]' -***** Load for rr_node[371] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=80, type=4 ***** -Xchan_mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[155]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to40] -+ param='sum_leakage_power_sb_mux[0to39]+leakage_sb_mux[0][1]_rrnode[371]' -.meas tran sum_energy_per_cycle_sb_mux[0to40] -+ param='sum_energy_per_cycle_sb_mux[0to39]+energy_per_cycle_sb_mux[0][1]_rrnode[371]' -Xmux_1level_tapbuf_size2[41] mux_1level_tapbuf_size2[41]->in[0] mux_1level_tapbuf_size2[41]->in[1] mux_1level_tapbuf_size2[41]->out sram[51]->outb sram[51]->out gvdd_mux_1level_tapbuf_size2[41] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[41], level=1, select_path_id=0. ***** -*****1***** -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -***** Signal mux_1level_tapbuf_size2[41]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[41]->in[0] mux_1level_tapbuf_size2[41]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[41]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[41]->in[1] mux_1level_tapbuf_size2[41]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[41] gvdd_mux_1level_tapbuf_size2[41] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[373] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[373] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[373] when v(mux_1level_tapbuf_size2[41]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[373] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[373] when v(mux_1level_tapbuf_size2[41]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[373] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[41]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[373] param='mux_1level_tapbuf_size2[41]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[41]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[41]_energy_per_cycle param='mux_1level_tapbuf_size2[41]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[373] param='mux_1level_tapbuf_size2[41]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[373] param='dynamic_power_sb_mux[0][1]_rrnode[373]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[373] avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='start_rise_sb_mux[0][1]_rrnode[373]' to='start_rise_sb_mux[0][1]_rrnode[373]+switch_rise_sb_mux[0][1]_rrnode[373]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[373] avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='start_fall_sb_mux[0][1]_rrnode[373]' to='start_fall_sb_mux[0][1]_rrnode[373]+switch_fall_sb_mux[0][1]_rrnode[373]' -.meas tran sum_leakage_power_mux[0to41] -+ param='sum_leakage_power_mux[0to40]+leakage_sb_mux[0][1]_rrnode[373]' -.meas tran sum_energy_per_cycle_mux[0to41] -+ param='sum_energy_per_cycle_mux[0to40]+energy_per_cycle_sb_mux[0][1]_rrnode[373]' -***** Load for rr_node[373] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=82, type=4 ***** -Xchan_mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[159]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to41] -+ param='sum_leakage_power_sb_mux[0to40]+leakage_sb_mux[0][1]_rrnode[373]' -.meas tran sum_energy_per_cycle_sb_mux[0to41] -+ param='sum_energy_per_cycle_sb_mux[0to40]+energy_per_cycle_sb_mux[0][1]_rrnode[373]' -Xmux_1level_tapbuf_size2[42] mux_1level_tapbuf_size2[42]->in[0] mux_1level_tapbuf_size2[42]->in[1] mux_1level_tapbuf_size2[42]->out sram[52]->outb sram[52]->out gvdd_mux_1level_tapbuf_size2[42] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[42], level=1, select_path_id=0. ***** -*****1***** -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -***** Signal mux_1level_tapbuf_size2[42]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[42]->in[0] mux_1level_tapbuf_size2[42]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[42]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[42]->in[1] mux_1level_tapbuf_size2[42]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[42] gvdd_mux_1level_tapbuf_size2[42] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[375] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[375] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[375] when v(mux_1level_tapbuf_size2[42]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[375] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[375] when v(mux_1level_tapbuf_size2[42]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[375] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[42]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[375] param='mux_1level_tapbuf_size2[42]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[42]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[42]_energy_per_cycle param='mux_1level_tapbuf_size2[42]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[375] param='mux_1level_tapbuf_size2[42]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[375] param='dynamic_power_sb_mux[0][1]_rrnode[375]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[375] avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='start_rise_sb_mux[0][1]_rrnode[375]' to='start_rise_sb_mux[0][1]_rrnode[375]+switch_rise_sb_mux[0][1]_rrnode[375]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[375] avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='start_fall_sb_mux[0][1]_rrnode[375]' to='start_fall_sb_mux[0][1]_rrnode[375]+switch_fall_sb_mux[0][1]_rrnode[375]' -.meas tran sum_leakage_power_mux[0to42] -+ param='sum_leakage_power_mux[0to41]+leakage_sb_mux[0][1]_rrnode[375]' -.meas tran sum_energy_per_cycle_mux[0to42] -+ param='sum_energy_per_cycle_mux[0to41]+energy_per_cycle_sb_mux[0][1]_rrnode[375]' -***** Load for rr_node[375] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=84, type=4 ***** -Xchan_mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[164]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to42] -+ param='sum_leakage_power_sb_mux[0to41]+leakage_sb_mux[0][1]_rrnode[375]' -.meas tran sum_energy_per_cycle_sb_mux[0to42] -+ param='sum_energy_per_cycle_sb_mux[0to41]+energy_per_cycle_sb_mux[0][1]_rrnode[375]' -Xmux_1level_tapbuf_size2[43] mux_1level_tapbuf_size2[43]->in[0] mux_1level_tapbuf_size2[43]->in[1] mux_1level_tapbuf_size2[43]->out sram[53]->outb sram[53]->out gvdd_mux_1level_tapbuf_size2[43] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[43], level=1, select_path_id=0. ***** -*****1***** -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -***** Signal mux_1level_tapbuf_size2[43]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[43]->in[0] mux_1level_tapbuf_size2[43]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[43]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[43]->in[1] mux_1level_tapbuf_size2[43]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[43] gvdd_mux_1level_tapbuf_size2[43] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[377] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[377] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[377] when v(mux_1level_tapbuf_size2[43]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[377] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[377] when v(mux_1level_tapbuf_size2[43]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[377] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[43]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[377] param='mux_1level_tapbuf_size2[43]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[43]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[43]_energy_per_cycle param='mux_1level_tapbuf_size2[43]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[377] param='mux_1level_tapbuf_size2[43]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[377] param='dynamic_power_sb_mux[0][1]_rrnode[377]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[377] avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='start_rise_sb_mux[0][1]_rrnode[377]' to='start_rise_sb_mux[0][1]_rrnode[377]+switch_rise_sb_mux[0][1]_rrnode[377]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[377] avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='start_fall_sb_mux[0][1]_rrnode[377]' to='start_fall_sb_mux[0][1]_rrnode[377]+switch_fall_sb_mux[0][1]_rrnode[377]' -.meas tran sum_leakage_power_mux[0to43] -+ param='sum_leakage_power_mux[0to42]+leakage_sb_mux[0][1]_rrnode[377]' -.meas tran sum_energy_per_cycle_mux[0to43] -+ param='sum_energy_per_cycle_mux[0to42]+energy_per_cycle_sb_mux[0][1]_rrnode[377]' -***** Load for rr_node[377] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=86, type=4 ***** -Xchan_mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[167]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to43] -+ param='sum_leakage_power_sb_mux[0to42]+leakage_sb_mux[0][1]_rrnode[377]' -.meas tran sum_energy_per_cycle_sb_mux[0to43] -+ param='sum_energy_per_cycle_sb_mux[0to42]+energy_per_cycle_sb_mux[0][1]_rrnode[377]' -Xmux_1level_tapbuf_size2[44] mux_1level_tapbuf_size2[44]->in[0] mux_1level_tapbuf_size2[44]->in[1] mux_1level_tapbuf_size2[44]->out sram[54]->outb sram[54]->out gvdd_mux_1level_tapbuf_size2[44] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[44], level=1, select_path_id=0. ***** -*****1***** -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -***** Signal mux_1level_tapbuf_size2[44]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[44]->in[0] mux_1level_tapbuf_size2[44]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[44]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[44]->in[1] mux_1level_tapbuf_size2[44]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[44] gvdd_mux_1level_tapbuf_size2[44] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[379] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[379] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[379] when v(mux_1level_tapbuf_size2[44]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[379] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[379] when v(mux_1level_tapbuf_size2[44]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[379] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[44]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[379] param='mux_1level_tapbuf_size2[44]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[44]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[44]_energy_per_cycle param='mux_1level_tapbuf_size2[44]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[379] param='mux_1level_tapbuf_size2[44]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[379] param='dynamic_power_sb_mux[0][1]_rrnode[379]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[379] avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='start_rise_sb_mux[0][1]_rrnode[379]' to='start_rise_sb_mux[0][1]_rrnode[379]+switch_rise_sb_mux[0][1]_rrnode[379]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[379] avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='start_fall_sb_mux[0][1]_rrnode[379]' to='start_fall_sb_mux[0][1]_rrnode[379]+switch_fall_sb_mux[0][1]_rrnode[379]' -.meas tran sum_leakage_power_mux[0to44] -+ param='sum_leakage_power_mux[0to43]+leakage_sb_mux[0][1]_rrnode[379]' -.meas tran sum_energy_per_cycle_mux[0to44] -+ param='sum_energy_per_cycle_mux[0to43]+energy_per_cycle_sb_mux[0][1]_rrnode[379]' -***** Load for rr_node[379] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=88, type=4 ***** -Xchan_mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[171]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to44] -+ param='sum_leakage_power_sb_mux[0to43]+leakage_sb_mux[0][1]_rrnode[379]' -.meas tran sum_energy_per_cycle_sb_mux[0to44] -+ param='sum_energy_per_cycle_sb_mux[0to43]+energy_per_cycle_sb_mux[0][1]_rrnode[379]' -Xmux_1level_tapbuf_size2[45] mux_1level_tapbuf_size2[45]->in[0] mux_1level_tapbuf_size2[45]->in[1] mux_1level_tapbuf_size2[45]->out sram[55]->outb sram[55]->out gvdd_mux_1level_tapbuf_size2[45] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[45], level=1, select_path_id=0. ***** -*****1***** -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -***** Signal mux_1level_tapbuf_size2[45]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[45]->in[0] mux_1level_tapbuf_size2[45]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[45]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[45]->in[1] mux_1level_tapbuf_size2[45]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[45] gvdd_mux_1level_tapbuf_size2[45] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[381] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[381] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[381] when v(mux_1level_tapbuf_size2[45]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[381] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[381] when v(mux_1level_tapbuf_size2[45]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[381] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[45]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[381] param='mux_1level_tapbuf_size2[45]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[45]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[45]_energy_per_cycle param='mux_1level_tapbuf_size2[45]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[381] param='mux_1level_tapbuf_size2[45]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[381] param='dynamic_power_sb_mux[0][1]_rrnode[381]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[381] avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='start_rise_sb_mux[0][1]_rrnode[381]' to='start_rise_sb_mux[0][1]_rrnode[381]+switch_rise_sb_mux[0][1]_rrnode[381]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[381] avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='start_fall_sb_mux[0][1]_rrnode[381]' to='start_fall_sb_mux[0][1]_rrnode[381]+switch_fall_sb_mux[0][1]_rrnode[381]' -.meas tran sum_leakage_power_mux[0to45] -+ param='sum_leakage_power_mux[0to44]+leakage_sb_mux[0][1]_rrnode[381]' -.meas tran sum_energy_per_cycle_mux[0to45] -+ param='sum_energy_per_cycle_mux[0to44]+energy_per_cycle_sb_mux[0][1]_rrnode[381]' -***** Load for rr_node[381] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=90, type=4 ***** -Xchan_mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[175]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to45] -+ param='sum_leakage_power_sb_mux[0to44]+leakage_sb_mux[0][1]_rrnode[381]' -.meas tran sum_energy_per_cycle_sb_mux[0to45] -+ param='sum_energy_per_cycle_sb_mux[0to44]+energy_per_cycle_sb_mux[0][1]_rrnode[381]' -Xmux_1level_tapbuf_size2[46] mux_1level_tapbuf_size2[46]->in[0] mux_1level_tapbuf_size2[46]->in[1] mux_1level_tapbuf_size2[46]->out sram[56]->outb sram[56]->out gvdd_mux_1level_tapbuf_size2[46] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[46], level=1, select_path_id=0. ***** -*****1***** -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -***** Signal mux_1level_tapbuf_size2[46]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[46]->in[0] mux_1level_tapbuf_size2[46]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[46]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[46]->in[1] mux_1level_tapbuf_size2[46]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[46] gvdd_mux_1level_tapbuf_size2[46] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[383] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[383] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[383] when v(mux_1level_tapbuf_size2[46]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[383] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[383] when v(mux_1level_tapbuf_size2[46]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[383] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[46]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[383] param='mux_1level_tapbuf_size2[46]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[46]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[46]_energy_per_cycle param='mux_1level_tapbuf_size2[46]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[383] param='mux_1level_tapbuf_size2[46]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[383] param='dynamic_power_sb_mux[0][1]_rrnode[383]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[383] avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='start_rise_sb_mux[0][1]_rrnode[383]' to='start_rise_sb_mux[0][1]_rrnode[383]+switch_rise_sb_mux[0][1]_rrnode[383]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[383] avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='start_fall_sb_mux[0][1]_rrnode[383]' to='start_fall_sb_mux[0][1]_rrnode[383]+switch_fall_sb_mux[0][1]_rrnode[383]' -.meas tran sum_leakage_power_mux[0to46] -+ param='sum_leakage_power_mux[0to45]+leakage_sb_mux[0][1]_rrnode[383]' -.meas tran sum_energy_per_cycle_mux[0to46] -+ param='sum_energy_per_cycle_mux[0to45]+energy_per_cycle_sb_mux[0][1]_rrnode[383]' -***** Load for rr_node[383] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=92, type=4 ***** -Xchan_mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[179]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[180]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to46] -+ param='sum_leakage_power_sb_mux[0to45]+leakage_sb_mux[0][1]_rrnode[383]' -.meas tran sum_energy_per_cycle_sb_mux[0to46] -+ param='sum_energy_per_cycle_sb_mux[0to45]+energy_per_cycle_sb_mux[0][1]_rrnode[383]' -Xmux_1level_tapbuf_size2[47] mux_1level_tapbuf_size2[47]->in[0] mux_1level_tapbuf_size2[47]->in[1] mux_1level_tapbuf_size2[47]->out sram[57]->outb sram[57]->out gvdd_mux_1level_tapbuf_size2[47] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[47], level=1, select_path_id=0. ***** -*****1***** -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -***** Signal mux_1level_tapbuf_size2[47]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[47]->in[0] mux_1level_tapbuf_size2[47]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[47]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[47]->in[1] mux_1level_tapbuf_size2[47]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[47] gvdd_mux_1level_tapbuf_size2[47] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[385] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[385] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[385] when v(mux_1level_tapbuf_size2[47]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[385] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[385] when v(mux_1level_tapbuf_size2[47]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[385] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[47]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[385] param='mux_1level_tapbuf_size2[47]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[47]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[47]_energy_per_cycle param='mux_1level_tapbuf_size2[47]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[385] param='mux_1level_tapbuf_size2[47]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[385] param='dynamic_power_sb_mux[0][1]_rrnode[385]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[385] avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='start_rise_sb_mux[0][1]_rrnode[385]' to='start_rise_sb_mux[0][1]_rrnode[385]+switch_rise_sb_mux[0][1]_rrnode[385]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[385] avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='start_fall_sb_mux[0][1]_rrnode[385]' to='start_fall_sb_mux[0][1]_rrnode[385]+switch_fall_sb_mux[0][1]_rrnode[385]' -.meas tran sum_leakage_power_mux[0to47] -+ param='sum_leakage_power_mux[0to46]+leakage_sb_mux[0][1]_rrnode[385]' -.meas tran sum_energy_per_cycle_mux[0to47] -+ param='sum_energy_per_cycle_mux[0to46]+energy_per_cycle_sb_mux[0][1]_rrnode[385]' -***** Load for rr_node[385] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=94, type=4 ***** -Xchan_mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[183]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to47] -+ param='sum_leakage_power_sb_mux[0to46]+leakage_sb_mux[0][1]_rrnode[385]' -.meas tran sum_energy_per_cycle_sb_mux[0to47] -+ param='sum_energy_per_cycle_sb_mux[0to46]+energy_per_cycle_sb_mux[0][1]_rrnode[385]' -Xmux_1level_tapbuf_size2[48] mux_1level_tapbuf_size2[48]->in[0] mux_1level_tapbuf_size2[48]->in[1] mux_1level_tapbuf_size2[48]->out sram[58]->outb sram[58]->out gvdd_mux_1level_tapbuf_size2[48] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[48], level=1, select_path_id=0. ***** -*****1***** -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -***** Signal mux_1level_tapbuf_size2[48]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[48]->in[0] mux_1level_tapbuf_size2[48]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[48]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[48]->in[1] mux_1level_tapbuf_size2[48]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[48] gvdd_mux_1level_tapbuf_size2[48] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[387] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[387] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[387] when v(mux_1level_tapbuf_size2[48]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[387] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[387] when v(mux_1level_tapbuf_size2[48]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[387] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[48]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[387] param='mux_1level_tapbuf_size2[48]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[48]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[48]_energy_per_cycle param='mux_1level_tapbuf_size2[48]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[387] param='mux_1level_tapbuf_size2[48]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[387] param='dynamic_power_sb_mux[0][1]_rrnode[387]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[387] avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='start_rise_sb_mux[0][1]_rrnode[387]' to='start_rise_sb_mux[0][1]_rrnode[387]+switch_rise_sb_mux[0][1]_rrnode[387]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[387] avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='start_fall_sb_mux[0][1]_rrnode[387]' to='start_fall_sb_mux[0][1]_rrnode[387]+switch_fall_sb_mux[0][1]_rrnode[387]' -.meas tran sum_leakage_power_mux[0to48] -+ param='sum_leakage_power_mux[0to47]+leakage_sb_mux[0][1]_rrnode[387]' -.meas tran sum_energy_per_cycle_mux[0to48] -+ param='sum_energy_per_cycle_mux[0to47]+energy_per_cycle_sb_mux[0][1]_rrnode[387]' -***** Load for rr_node[387] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=96, type=4 ***** -Xchan_mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[186]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to48] -+ param='sum_leakage_power_sb_mux[0to47]+leakage_sb_mux[0][1]_rrnode[387]' -.meas tran sum_energy_per_cycle_sb_mux[0to48] -+ param='sum_energy_per_cycle_sb_mux[0to47]+energy_per_cycle_sb_mux[0][1]_rrnode[387]' -Xmux_1level_tapbuf_size2[49] mux_1level_tapbuf_size2[49]->in[0] mux_1level_tapbuf_size2[49]->in[1] mux_1level_tapbuf_size2[49]->out sram[59]->outb sram[59]->out gvdd_mux_1level_tapbuf_size2[49] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[49], level=1, select_path_id=0. ***** -*****1***** -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -***** Signal mux_1level_tapbuf_size2[49]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[49]->in[0] mux_1level_tapbuf_size2[49]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[49]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[49]->in[1] mux_1level_tapbuf_size2[49]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[49] gvdd_mux_1level_tapbuf_size2[49] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[389] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[389] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[389] when v(mux_1level_tapbuf_size2[49]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[389] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[389] when v(mux_1level_tapbuf_size2[49]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[389] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[49]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[389] param='mux_1level_tapbuf_size2[49]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[49]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[49]_energy_per_cycle param='mux_1level_tapbuf_size2[49]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[389] param='mux_1level_tapbuf_size2[49]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[389] param='dynamic_power_sb_mux[0][1]_rrnode[389]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[389] avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='start_rise_sb_mux[0][1]_rrnode[389]' to='start_rise_sb_mux[0][1]_rrnode[389]+switch_rise_sb_mux[0][1]_rrnode[389]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[389] avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='start_fall_sb_mux[0][1]_rrnode[389]' to='start_fall_sb_mux[0][1]_rrnode[389]+switch_fall_sb_mux[0][1]_rrnode[389]' -.meas tran sum_leakage_power_mux[0to49] -+ param='sum_leakage_power_mux[0to48]+leakage_sb_mux[0][1]_rrnode[389]' -.meas tran sum_energy_per_cycle_mux[0to49] -+ param='sum_energy_per_cycle_mux[0to48]+energy_per_cycle_sb_mux[0][1]_rrnode[389]' -***** Load for rr_node[389] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=98, type=4 ***** -Xchan_mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[191]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to49] -+ param='sum_leakage_power_sb_mux[0to48]+leakage_sb_mux[0][1]_rrnode[389]' -.meas tran sum_energy_per_cycle_sb_mux[0to49] -+ param='sum_energy_per_cycle_sb_mux[0to48]+energy_per_cycle_sb_mux[0][1]_rrnode[389]' -Xmux_1level_tapbuf_size2[50] mux_1level_tapbuf_size2[50]->in[0] mux_1level_tapbuf_size2[50]->in[1] mux_1level_tapbuf_size2[50]->out sram[60]->outb sram[60]->out gvdd_mux_1level_tapbuf_size2[50] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[50], level=1, select_path_id=0. ***** -*****1***** -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -***** Signal mux_1level_tapbuf_size2[50]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[50]->in[0] mux_1level_tapbuf_size2[50]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[50]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[50]->in[1] mux_1level_tapbuf_size2[50]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[50] gvdd_mux_1level_tapbuf_size2[50] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[392] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[392] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[392] when v(mux_1level_tapbuf_size2[50]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[392] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[392] when v(mux_1level_tapbuf_size2[50]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[392] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[50]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[392] param='mux_1level_tapbuf_size2[50]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[50]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[50]_energy_per_cycle param='mux_1level_tapbuf_size2[50]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[392] param='mux_1level_tapbuf_size2[50]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[392] param='dynamic_power_sb_mux[0][1]_rrnode[392]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[392] avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from='start_rise_sb_mux[0][1]_rrnode[392]' to='start_rise_sb_mux[0][1]_rrnode[392]+switch_rise_sb_mux[0][1]_rrnode[392]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[392] avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from='start_fall_sb_mux[0][1]_rrnode[392]' to='start_fall_sb_mux[0][1]_rrnode[392]+switch_fall_sb_mux[0][1]_rrnode[392]' -.meas tran sum_leakage_power_mux[0to50] -+ param='sum_leakage_power_mux[0to49]+leakage_sb_mux[0][1]_rrnode[392]' -.meas tran sum_energy_per_cycle_mux[0to50] -+ param='sum_energy_per_cycle_mux[0to49]+energy_per_cycle_sb_mux[0][1]_rrnode[392]' -***** Load for rr_node[392] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=1, type=5 ***** -Xchan_mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out mux_1level_tapbuf_size2[50]->out mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[194]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to50] -+ param='sum_leakage_power_sb_mux[0to49]+leakage_sb_mux[0][1]_rrnode[392]' -.meas tran sum_energy_per_cycle_sb_mux[0to50] -+ param='sum_energy_per_cycle_sb_mux[0to49]+energy_per_cycle_sb_mux[0][1]_rrnode[392]' -Xmux_1level_tapbuf_size2[51] mux_1level_tapbuf_size2[51]->in[0] mux_1level_tapbuf_size2[51]->in[1] mux_1level_tapbuf_size2[51]->out sram[61]->outb sram[61]->out gvdd_mux_1level_tapbuf_size2[51] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[51], level=1, select_path_id=0. ***** -*****1***** -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -***** Signal mux_1level_tapbuf_size2[51]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[51]->in[0] mux_1level_tapbuf_size2[51]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[51]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[51]->in[1] mux_1level_tapbuf_size2[51]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[51] gvdd_mux_1level_tapbuf_size2[51] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[394] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[394] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[394] when v(mux_1level_tapbuf_size2[51]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[394] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[394] when v(mux_1level_tapbuf_size2[51]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[394] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[51]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[394] param='mux_1level_tapbuf_size2[51]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[51]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[51]_energy_per_cycle param='mux_1level_tapbuf_size2[51]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[394] param='mux_1level_tapbuf_size2[51]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[394] param='dynamic_power_sb_mux[0][1]_rrnode[394]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[394] avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from='start_rise_sb_mux[0][1]_rrnode[394]' to='start_rise_sb_mux[0][1]_rrnode[394]+switch_rise_sb_mux[0][1]_rrnode[394]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[394] avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from='start_fall_sb_mux[0][1]_rrnode[394]' to='start_fall_sb_mux[0][1]_rrnode[394]+switch_fall_sb_mux[0][1]_rrnode[394]' -.meas tran sum_leakage_power_mux[0to51] -+ param='sum_leakage_power_mux[0to50]+leakage_sb_mux[0][1]_rrnode[394]' -.meas tran sum_energy_per_cycle_mux[0to51] -+ param='sum_energy_per_cycle_mux[0to50]+energy_per_cycle_sb_mux[0][1]_rrnode[394]' -***** Load for rr_node[394] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=3, type=5 ***** -Xchan_mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out mux_1level_tapbuf_size2[51]->out mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[198]_no0 mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to51] -+ param='sum_leakage_power_sb_mux[0to50]+leakage_sb_mux[0][1]_rrnode[394]' -.meas tran sum_energy_per_cycle_sb_mux[0to51] -+ param='sum_energy_per_cycle_sb_mux[0to50]+energy_per_cycle_sb_mux[0][1]_rrnode[394]' -Xmux_1level_tapbuf_size2[52] mux_1level_tapbuf_size2[52]->in[0] mux_1level_tapbuf_size2[52]->in[1] mux_1level_tapbuf_size2[52]->out sram[62]->outb sram[62]->out gvdd_mux_1level_tapbuf_size2[52] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[52], level=1, select_path_id=0. ***** -*****1***** -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -***** Signal mux_1level_tapbuf_size2[52]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[52]->in[0] mux_1level_tapbuf_size2[52]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[52]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[52]->in[1] mux_1level_tapbuf_size2[52]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[52] gvdd_mux_1level_tapbuf_size2[52] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[396] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[396] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[396] when v(mux_1level_tapbuf_size2[52]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[396] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[396] when v(mux_1level_tapbuf_size2[52]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[396] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[52]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[396] param='mux_1level_tapbuf_size2[52]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[52]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[52]_energy_per_cycle param='mux_1level_tapbuf_size2[52]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[396] param='mux_1level_tapbuf_size2[52]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[396] param='dynamic_power_sb_mux[0][1]_rrnode[396]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[396] avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from='start_rise_sb_mux[0][1]_rrnode[396]' to='start_rise_sb_mux[0][1]_rrnode[396]+switch_rise_sb_mux[0][1]_rrnode[396]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[396] avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from='start_fall_sb_mux[0][1]_rrnode[396]' to='start_fall_sb_mux[0][1]_rrnode[396]+switch_fall_sb_mux[0][1]_rrnode[396]' -.meas tran sum_leakage_power_mux[0to52] -+ param='sum_leakage_power_mux[0to51]+leakage_sb_mux[0][1]_rrnode[396]' -.meas tran sum_energy_per_cycle_mux[0to52] -+ param='sum_energy_per_cycle_mux[0to51]+energy_per_cycle_sb_mux[0][1]_rrnode[396]' -***** Load for rr_node[396] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=5, type=5 ***** -Xchan_mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out mux_1level_tapbuf_size2[52]->out mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[202]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to52] -+ param='sum_leakage_power_sb_mux[0to51]+leakage_sb_mux[0][1]_rrnode[396]' -.meas tran sum_energy_per_cycle_sb_mux[0to52] -+ param='sum_energy_per_cycle_sb_mux[0to51]+energy_per_cycle_sb_mux[0][1]_rrnode[396]' -Xmux_1level_tapbuf_size2[53] mux_1level_tapbuf_size2[53]->in[0] mux_1level_tapbuf_size2[53]->in[1] mux_1level_tapbuf_size2[53]->out sram[63]->outb sram[63]->out gvdd_mux_1level_tapbuf_size2[53] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[53], level=1, select_path_id=0. ***** -*****1***** -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -***** Signal mux_1level_tapbuf_size2[53]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[53]->in[0] mux_1level_tapbuf_size2[53]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[53]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[53]->in[1] mux_1level_tapbuf_size2[53]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[53] gvdd_mux_1level_tapbuf_size2[53] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[398] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[398] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[398] when v(mux_1level_tapbuf_size2[53]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[398] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[398] when v(mux_1level_tapbuf_size2[53]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[398] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[53]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[398] param='mux_1level_tapbuf_size2[53]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[53]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[53]_energy_per_cycle param='mux_1level_tapbuf_size2[53]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[398] param='mux_1level_tapbuf_size2[53]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[398] param='dynamic_power_sb_mux[0][1]_rrnode[398]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[398] avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from='start_rise_sb_mux[0][1]_rrnode[398]' to='start_rise_sb_mux[0][1]_rrnode[398]+switch_rise_sb_mux[0][1]_rrnode[398]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[398] avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from='start_fall_sb_mux[0][1]_rrnode[398]' to='start_fall_sb_mux[0][1]_rrnode[398]+switch_fall_sb_mux[0][1]_rrnode[398]' -.meas tran sum_leakage_power_mux[0to53] -+ param='sum_leakage_power_mux[0to52]+leakage_sb_mux[0][1]_rrnode[398]' -.meas tran sum_energy_per_cycle_mux[0to53] -+ param='sum_energy_per_cycle_mux[0to52]+energy_per_cycle_sb_mux[0][1]_rrnode[398]' -***** Load for rr_node[398] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=7, type=5 ***** -Xchan_mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out mux_1level_tapbuf_size2[53]->out mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[206]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to53] -+ param='sum_leakage_power_sb_mux[0to52]+leakage_sb_mux[0][1]_rrnode[398]' -.meas tran sum_energy_per_cycle_sb_mux[0to53] -+ param='sum_energy_per_cycle_sb_mux[0to52]+energy_per_cycle_sb_mux[0][1]_rrnode[398]' -Xmux_1level_tapbuf_size2[54] mux_1level_tapbuf_size2[54]->in[0] mux_1level_tapbuf_size2[54]->in[1] mux_1level_tapbuf_size2[54]->out sram[64]->outb sram[64]->out gvdd_mux_1level_tapbuf_size2[54] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[54], level=1, select_path_id=0. ***** -*****1***** -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -***** Signal mux_1level_tapbuf_size2[54]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[54]->in[0] mux_1level_tapbuf_size2[54]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[54]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[54]->in[1] mux_1level_tapbuf_size2[54]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[54] gvdd_mux_1level_tapbuf_size2[54] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[400] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[400] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[400] when v(mux_1level_tapbuf_size2[54]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[400] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[400] when v(mux_1level_tapbuf_size2[54]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[400] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[54]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[400] param='mux_1level_tapbuf_size2[54]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[54]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[54]_energy_per_cycle param='mux_1level_tapbuf_size2[54]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[400] param='mux_1level_tapbuf_size2[54]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[400] param='dynamic_power_sb_mux[0][1]_rrnode[400]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[400] avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from='start_rise_sb_mux[0][1]_rrnode[400]' to='start_rise_sb_mux[0][1]_rrnode[400]+switch_rise_sb_mux[0][1]_rrnode[400]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[400] avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from='start_fall_sb_mux[0][1]_rrnode[400]' to='start_fall_sb_mux[0][1]_rrnode[400]+switch_fall_sb_mux[0][1]_rrnode[400]' -.meas tran sum_leakage_power_mux[0to54] -+ param='sum_leakage_power_mux[0to53]+leakage_sb_mux[0][1]_rrnode[400]' -.meas tran sum_energy_per_cycle_mux[0to54] -+ param='sum_energy_per_cycle_mux[0to53]+energy_per_cycle_sb_mux[0][1]_rrnode[400]' -***** Load for rr_node[400] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=9, type=5 ***** -Xchan_mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out mux_1level_tapbuf_size2[54]->out mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[209]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to54] -+ param='sum_leakage_power_sb_mux[0to53]+leakage_sb_mux[0][1]_rrnode[400]' -.meas tran sum_energy_per_cycle_sb_mux[0to54] -+ param='sum_energy_per_cycle_sb_mux[0to53]+energy_per_cycle_sb_mux[0][1]_rrnode[400]' -Xmux_1level_tapbuf_size2[55] mux_1level_tapbuf_size2[55]->in[0] mux_1level_tapbuf_size2[55]->in[1] mux_1level_tapbuf_size2[55]->out sram[65]->outb sram[65]->out gvdd_mux_1level_tapbuf_size2[55] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[55], level=1, select_path_id=0. ***** -*****1***** -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -***** Signal mux_1level_tapbuf_size2[55]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[55]->in[0] mux_1level_tapbuf_size2[55]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[55]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[55]->in[1] mux_1level_tapbuf_size2[55]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[55] gvdd_mux_1level_tapbuf_size2[55] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[402] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[402] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[402] when v(mux_1level_tapbuf_size2[55]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[402] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[402] when v(mux_1level_tapbuf_size2[55]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[402] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[55]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[402] param='mux_1level_tapbuf_size2[55]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[55]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[55]_energy_per_cycle param='mux_1level_tapbuf_size2[55]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[402] param='mux_1level_tapbuf_size2[55]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[402] param='dynamic_power_sb_mux[0][1]_rrnode[402]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[402] avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='start_rise_sb_mux[0][1]_rrnode[402]' to='start_rise_sb_mux[0][1]_rrnode[402]+switch_rise_sb_mux[0][1]_rrnode[402]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[402] avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='start_fall_sb_mux[0][1]_rrnode[402]' to='start_fall_sb_mux[0][1]_rrnode[402]+switch_fall_sb_mux[0][1]_rrnode[402]' -.meas tran sum_leakage_power_mux[0to55] -+ param='sum_leakage_power_mux[0to54]+leakage_sb_mux[0][1]_rrnode[402]' -.meas tran sum_energy_per_cycle_mux[0to55] -+ param='sum_energy_per_cycle_mux[0to54]+energy_per_cycle_sb_mux[0][1]_rrnode[402]' -***** Load for rr_node[402] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=11, type=5 ***** -Xchan_mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[214]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to55] -+ param='sum_leakage_power_sb_mux[0to54]+leakage_sb_mux[0][1]_rrnode[402]' -.meas tran sum_energy_per_cycle_sb_mux[0to55] -+ param='sum_energy_per_cycle_sb_mux[0to54]+energy_per_cycle_sb_mux[0][1]_rrnode[402]' -Xmux_1level_tapbuf_size2[56] mux_1level_tapbuf_size2[56]->in[0] mux_1level_tapbuf_size2[56]->in[1] mux_1level_tapbuf_size2[56]->out sram[66]->outb sram[66]->out gvdd_mux_1level_tapbuf_size2[56] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[56], level=1, select_path_id=0. ***** -*****1***** -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -***** Signal mux_1level_tapbuf_size2[56]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[56]->in[0] mux_1level_tapbuf_size2[56]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[56]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[56]->in[1] mux_1level_tapbuf_size2[56]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[56] gvdd_mux_1level_tapbuf_size2[56] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[404] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[404] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[404] when v(mux_1level_tapbuf_size2[56]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[404] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[404] when v(mux_1level_tapbuf_size2[56]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[404] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[56]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[404] param='mux_1level_tapbuf_size2[56]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[56]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[56]_energy_per_cycle param='mux_1level_tapbuf_size2[56]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[404] param='mux_1level_tapbuf_size2[56]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[404] param='dynamic_power_sb_mux[0][1]_rrnode[404]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[404] avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='start_rise_sb_mux[0][1]_rrnode[404]' to='start_rise_sb_mux[0][1]_rrnode[404]+switch_rise_sb_mux[0][1]_rrnode[404]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[404] avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='start_fall_sb_mux[0][1]_rrnode[404]' to='start_fall_sb_mux[0][1]_rrnode[404]+switch_fall_sb_mux[0][1]_rrnode[404]' -.meas tran sum_leakage_power_mux[0to56] -+ param='sum_leakage_power_mux[0to55]+leakage_sb_mux[0][1]_rrnode[404]' -.meas tran sum_energy_per_cycle_mux[0to56] -+ param='sum_energy_per_cycle_mux[0to55]+energy_per_cycle_sb_mux[0][1]_rrnode[404]' -***** Load for rr_node[404] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=13, type=5 ***** -Xchan_mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[217]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to56] -+ param='sum_leakage_power_sb_mux[0to55]+leakage_sb_mux[0][1]_rrnode[404]' -.meas tran sum_energy_per_cycle_sb_mux[0to56] -+ param='sum_energy_per_cycle_sb_mux[0to55]+energy_per_cycle_sb_mux[0][1]_rrnode[404]' -Xmux_1level_tapbuf_size2[57] mux_1level_tapbuf_size2[57]->in[0] mux_1level_tapbuf_size2[57]->in[1] mux_1level_tapbuf_size2[57]->out sram[67]->outb sram[67]->out gvdd_mux_1level_tapbuf_size2[57] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[57], level=1, select_path_id=0. ***** -*****1***** -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -***** Signal mux_1level_tapbuf_size2[57]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[57]->in[0] mux_1level_tapbuf_size2[57]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[57]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[57]->in[1] mux_1level_tapbuf_size2[57]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[57] gvdd_mux_1level_tapbuf_size2[57] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[406] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[406] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[406] when v(mux_1level_tapbuf_size2[57]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[406] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[406] when v(mux_1level_tapbuf_size2[57]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[406] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[57]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[406] param='mux_1level_tapbuf_size2[57]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[57]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[57]_energy_per_cycle param='mux_1level_tapbuf_size2[57]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[406] param='mux_1level_tapbuf_size2[57]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[406] param='dynamic_power_sb_mux[0][1]_rrnode[406]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[406] avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='start_rise_sb_mux[0][1]_rrnode[406]' to='start_rise_sb_mux[0][1]_rrnode[406]+switch_rise_sb_mux[0][1]_rrnode[406]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[406] avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='start_fall_sb_mux[0][1]_rrnode[406]' to='start_fall_sb_mux[0][1]_rrnode[406]+switch_fall_sb_mux[0][1]_rrnode[406]' -.meas tran sum_leakage_power_mux[0to57] -+ param='sum_leakage_power_mux[0to56]+leakage_sb_mux[0][1]_rrnode[406]' -.meas tran sum_energy_per_cycle_mux[0to57] -+ param='sum_energy_per_cycle_mux[0to56]+energy_per_cycle_sb_mux[0][1]_rrnode[406]' -***** Load for rr_node[406] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=15, type=5 ***** -Xchan_mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[221]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to57] -+ param='sum_leakage_power_sb_mux[0to56]+leakage_sb_mux[0][1]_rrnode[406]' -.meas tran sum_energy_per_cycle_sb_mux[0to57] -+ param='sum_energy_per_cycle_sb_mux[0to56]+energy_per_cycle_sb_mux[0][1]_rrnode[406]' -Xmux_1level_tapbuf_size2[58] mux_1level_tapbuf_size2[58]->in[0] mux_1level_tapbuf_size2[58]->in[1] mux_1level_tapbuf_size2[58]->out sram[68]->outb sram[68]->out gvdd_mux_1level_tapbuf_size2[58] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[58], level=1, select_path_id=0. ***** -*****1***** -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -***** Signal mux_1level_tapbuf_size2[58]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[58]->in[0] mux_1level_tapbuf_size2[58]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[58]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[58]->in[1] mux_1level_tapbuf_size2[58]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[58] gvdd_mux_1level_tapbuf_size2[58] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[408] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[408] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[408] when v(mux_1level_tapbuf_size2[58]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[408] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[408] when v(mux_1level_tapbuf_size2[58]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[408] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[58]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[408] param='mux_1level_tapbuf_size2[58]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[58]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[58]_energy_per_cycle param='mux_1level_tapbuf_size2[58]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[408] param='mux_1level_tapbuf_size2[58]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[408] param='dynamic_power_sb_mux[0][1]_rrnode[408]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[408] avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='start_rise_sb_mux[0][1]_rrnode[408]' to='start_rise_sb_mux[0][1]_rrnode[408]+switch_rise_sb_mux[0][1]_rrnode[408]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[408] avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='start_fall_sb_mux[0][1]_rrnode[408]' to='start_fall_sb_mux[0][1]_rrnode[408]+switch_fall_sb_mux[0][1]_rrnode[408]' -.meas tran sum_leakage_power_mux[0to58] -+ param='sum_leakage_power_mux[0to57]+leakage_sb_mux[0][1]_rrnode[408]' -.meas tran sum_energy_per_cycle_mux[0to58] -+ param='sum_energy_per_cycle_mux[0to57]+energy_per_cycle_sb_mux[0][1]_rrnode[408]' -***** Load for rr_node[408] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=17, type=5 ***** -Xchan_mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[225]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to58] -+ param='sum_leakage_power_sb_mux[0to57]+leakage_sb_mux[0][1]_rrnode[408]' -.meas tran sum_energy_per_cycle_sb_mux[0to58] -+ param='sum_energy_per_cycle_sb_mux[0to57]+energy_per_cycle_sb_mux[0][1]_rrnode[408]' -Xmux_1level_tapbuf_size2[59] mux_1level_tapbuf_size2[59]->in[0] mux_1level_tapbuf_size2[59]->in[1] mux_1level_tapbuf_size2[59]->out sram[69]->outb sram[69]->out gvdd_mux_1level_tapbuf_size2[59] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[59], level=1, select_path_id=0. ***** -*****1***** -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -***** Signal mux_1level_tapbuf_size2[59]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[59]->in[0] mux_1level_tapbuf_size2[59]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[59]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[59]->in[1] mux_1level_tapbuf_size2[59]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[59] gvdd_mux_1level_tapbuf_size2[59] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[410] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[410] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[410] when v(mux_1level_tapbuf_size2[59]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[410] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[410] when v(mux_1level_tapbuf_size2[59]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[410] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[59]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[410] param='mux_1level_tapbuf_size2[59]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[59]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[59]_energy_per_cycle param='mux_1level_tapbuf_size2[59]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[410] param='mux_1level_tapbuf_size2[59]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[410] param='dynamic_power_sb_mux[0][1]_rrnode[410]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[410] avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='start_rise_sb_mux[0][1]_rrnode[410]' to='start_rise_sb_mux[0][1]_rrnode[410]+switch_rise_sb_mux[0][1]_rrnode[410]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[410] avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='start_fall_sb_mux[0][1]_rrnode[410]' to='start_fall_sb_mux[0][1]_rrnode[410]+switch_fall_sb_mux[0][1]_rrnode[410]' -.meas tran sum_leakage_power_mux[0to59] -+ param='sum_leakage_power_mux[0to58]+leakage_sb_mux[0][1]_rrnode[410]' -.meas tran sum_energy_per_cycle_mux[0to59] -+ param='sum_energy_per_cycle_mux[0to58]+energy_per_cycle_sb_mux[0][1]_rrnode[410]' -***** Load for rr_node[410] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=19, type=5 ***** -Xchan_mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[229]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to59] -+ param='sum_leakage_power_sb_mux[0to58]+leakage_sb_mux[0][1]_rrnode[410]' -.meas tran sum_energy_per_cycle_sb_mux[0to59] -+ param='sum_energy_per_cycle_sb_mux[0to58]+energy_per_cycle_sb_mux[0][1]_rrnode[410]' -Xmux_1level_tapbuf_size2[60] mux_1level_tapbuf_size2[60]->in[0] mux_1level_tapbuf_size2[60]->in[1] mux_1level_tapbuf_size2[60]->out sram[70]->outb sram[70]->out gvdd_mux_1level_tapbuf_size2[60] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[60], level=1, select_path_id=0. ***** -*****1***** -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -***** Signal mux_1level_tapbuf_size2[60]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[60]->in[0] mux_1level_tapbuf_size2[60]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[60]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[60]->in[1] mux_1level_tapbuf_size2[60]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[60] gvdd_mux_1level_tapbuf_size2[60] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[412] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[412] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[412] when v(mux_1level_tapbuf_size2[60]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[412] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[412] when v(mux_1level_tapbuf_size2[60]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[412] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[60]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[412] param='mux_1level_tapbuf_size2[60]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[60]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[60]_energy_per_cycle param='mux_1level_tapbuf_size2[60]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[412] param='mux_1level_tapbuf_size2[60]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[412] param='dynamic_power_sb_mux[0][1]_rrnode[412]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[412] avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='start_rise_sb_mux[0][1]_rrnode[412]' to='start_rise_sb_mux[0][1]_rrnode[412]+switch_rise_sb_mux[0][1]_rrnode[412]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[412] avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='start_fall_sb_mux[0][1]_rrnode[412]' to='start_fall_sb_mux[0][1]_rrnode[412]+switch_fall_sb_mux[0][1]_rrnode[412]' -.meas tran sum_leakage_power_mux[0to60] -+ param='sum_leakage_power_mux[0to59]+leakage_sb_mux[0][1]_rrnode[412]' -.meas tran sum_energy_per_cycle_mux[0to60] -+ param='sum_energy_per_cycle_mux[0to59]+energy_per_cycle_sb_mux[0][1]_rrnode[412]' -***** Load for rr_node[412] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=21, type=5 ***** -Xchan_mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[233]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to60] -+ param='sum_leakage_power_sb_mux[0to59]+leakage_sb_mux[0][1]_rrnode[412]' -.meas tran sum_energy_per_cycle_sb_mux[0to60] -+ param='sum_energy_per_cycle_sb_mux[0to59]+energy_per_cycle_sb_mux[0][1]_rrnode[412]' -Xmux_1level_tapbuf_size2[61] mux_1level_tapbuf_size2[61]->in[0] mux_1level_tapbuf_size2[61]->in[1] mux_1level_tapbuf_size2[61]->out sram[71]->outb sram[71]->out gvdd_mux_1level_tapbuf_size2[61] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[61], level=1, select_path_id=0. ***** -*****1***** -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -***** Signal mux_1level_tapbuf_size2[61]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[61]->in[0] mux_1level_tapbuf_size2[61]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[61]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[61]->in[1] mux_1level_tapbuf_size2[61]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[61] gvdd_mux_1level_tapbuf_size2[61] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[414] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[414] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[414] when v(mux_1level_tapbuf_size2[61]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[414] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[414] when v(mux_1level_tapbuf_size2[61]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[414] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[61]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[414] param='mux_1level_tapbuf_size2[61]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[61]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[61]_energy_per_cycle param='mux_1level_tapbuf_size2[61]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[414] param='mux_1level_tapbuf_size2[61]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[414] param='dynamic_power_sb_mux[0][1]_rrnode[414]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[414] avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='start_rise_sb_mux[0][1]_rrnode[414]' to='start_rise_sb_mux[0][1]_rrnode[414]+switch_rise_sb_mux[0][1]_rrnode[414]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[414] avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='start_fall_sb_mux[0][1]_rrnode[414]' to='start_fall_sb_mux[0][1]_rrnode[414]+switch_fall_sb_mux[0][1]_rrnode[414]' -.meas tran sum_leakage_power_mux[0to61] -+ param='sum_leakage_power_mux[0to60]+leakage_sb_mux[0][1]_rrnode[414]' -.meas tran sum_energy_per_cycle_mux[0to61] -+ param='sum_energy_per_cycle_mux[0to60]+energy_per_cycle_sb_mux[0][1]_rrnode[414]' -***** Load for rr_node[414] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=23, type=5 ***** -Xchan_mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[236]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[240]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to61] -+ param='sum_leakage_power_sb_mux[0to60]+leakage_sb_mux[0][1]_rrnode[414]' -.meas tran sum_energy_per_cycle_sb_mux[0to61] -+ param='sum_energy_per_cycle_sb_mux[0to60]+energy_per_cycle_sb_mux[0][1]_rrnode[414]' -Xmux_1level_tapbuf_size2[62] mux_1level_tapbuf_size2[62]->in[0] mux_1level_tapbuf_size2[62]->in[1] mux_1level_tapbuf_size2[62]->out sram[72]->outb sram[72]->out gvdd_mux_1level_tapbuf_size2[62] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[62], level=1, select_path_id=0. ***** -*****1***** -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -***** Signal mux_1level_tapbuf_size2[62]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[62]->in[0] mux_1level_tapbuf_size2[62]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[62]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[62]->in[1] mux_1level_tapbuf_size2[62]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[62] gvdd_mux_1level_tapbuf_size2[62] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[416] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[416] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[416] when v(mux_1level_tapbuf_size2[62]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[416] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[416] when v(mux_1level_tapbuf_size2[62]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[416] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[62]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[416] param='mux_1level_tapbuf_size2[62]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[62]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[62]_energy_per_cycle param='mux_1level_tapbuf_size2[62]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[416] param='mux_1level_tapbuf_size2[62]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[416] param='dynamic_power_sb_mux[0][1]_rrnode[416]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[416] avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='start_rise_sb_mux[0][1]_rrnode[416]' to='start_rise_sb_mux[0][1]_rrnode[416]+switch_rise_sb_mux[0][1]_rrnode[416]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[416] avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='start_fall_sb_mux[0][1]_rrnode[416]' to='start_fall_sb_mux[0][1]_rrnode[416]+switch_fall_sb_mux[0][1]_rrnode[416]' -.meas tran sum_leakage_power_mux[0to62] -+ param='sum_leakage_power_mux[0to61]+leakage_sb_mux[0][1]_rrnode[416]' -.meas tran sum_energy_per_cycle_mux[0to62] -+ param='sum_energy_per_cycle_mux[0to61]+energy_per_cycle_sb_mux[0][1]_rrnode[416]' -***** Load for rr_node[416] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=25, type=5 ***** -Xchan_mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[241]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to62] -+ param='sum_leakage_power_sb_mux[0to61]+leakage_sb_mux[0][1]_rrnode[416]' -.meas tran sum_energy_per_cycle_sb_mux[0to62] -+ param='sum_energy_per_cycle_sb_mux[0to61]+energy_per_cycle_sb_mux[0][1]_rrnode[416]' -Xmux_1level_tapbuf_size2[63] mux_1level_tapbuf_size2[63]->in[0] mux_1level_tapbuf_size2[63]->in[1] mux_1level_tapbuf_size2[63]->out sram[73]->outb sram[73]->out gvdd_mux_1level_tapbuf_size2[63] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[63], level=1, select_path_id=0. ***** -*****1***** -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -***** Signal mux_1level_tapbuf_size2[63]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[63]->in[0] mux_1level_tapbuf_size2[63]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[63]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[63]->in[1] mux_1level_tapbuf_size2[63]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[63] gvdd_mux_1level_tapbuf_size2[63] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[418] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[418] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[418] when v(mux_1level_tapbuf_size2[63]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[418] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[418] when v(mux_1level_tapbuf_size2[63]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[418] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[63]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[418] param='mux_1level_tapbuf_size2[63]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[63]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[63]_energy_per_cycle param='mux_1level_tapbuf_size2[63]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[418] param='mux_1level_tapbuf_size2[63]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[418] param='dynamic_power_sb_mux[0][1]_rrnode[418]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[418] avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='start_rise_sb_mux[0][1]_rrnode[418]' to='start_rise_sb_mux[0][1]_rrnode[418]+switch_rise_sb_mux[0][1]_rrnode[418]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[418] avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='start_fall_sb_mux[0][1]_rrnode[418]' to='start_fall_sb_mux[0][1]_rrnode[418]+switch_fall_sb_mux[0][1]_rrnode[418]' -.meas tran sum_leakage_power_mux[0to63] -+ param='sum_leakage_power_mux[0to62]+leakage_sb_mux[0][1]_rrnode[418]' -.meas tran sum_energy_per_cycle_mux[0to63] -+ param='sum_energy_per_cycle_mux[0to62]+energy_per_cycle_sb_mux[0][1]_rrnode[418]' -***** Load for rr_node[418] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=27, type=5 ***** -Xchan_mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[245]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to63] -+ param='sum_leakage_power_sb_mux[0to62]+leakage_sb_mux[0][1]_rrnode[418]' -.meas tran sum_energy_per_cycle_sb_mux[0to63] -+ param='sum_energy_per_cycle_sb_mux[0to62]+energy_per_cycle_sb_mux[0][1]_rrnode[418]' -Xmux_1level_tapbuf_size2[64] mux_1level_tapbuf_size2[64]->in[0] mux_1level_tapbuf_size2[64]->in[1] mux_1level_tapbuf_size2[64]->out sram[74]->outb sram[74]->out gvdd_mux_1level_tapbuf_size2[64] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[64], level=1, select_path_id=0. ***** -*****1***** -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -***** Signal mux_1level_tapbuf_size2[64]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[64]->in[0] mux_1level_tapbuf_size2[64]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[64]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[64]->in[1] mux_1level_tapbuf_size2[64]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[64] gvdd_mux_1level_tapbuf_size2[64] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[420] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[420] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[420] when v(mux_1level_tapbuf_size2[64]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[420] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[420] when v(mux_1level_tapbuf_size2[64]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[420] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[64]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[420] param='mux_1level_tapbuf_size2[64]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[64]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[64]_energy_per_cycle param='mux_1level_tapbuf_size2[64]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[420] param='mux_1level_tapbuf_size2[64]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[420] param='dynamic_power_sb_mux[0][1]_rrnode[420]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[420] avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='start_rise_sb_mux[0][1]_rrnode[420]' to='start_rise_sb_mux[0][1]_rrnode[420]+switch_rise_sb_mux[0][1]_rrnode[420]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[420] avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='start_fall_sb_mux[0][1]_rrnode[420]' to='start_fall_sb_mux[0][1]_rrnode[420]+switch_fall_sb_mux[0][1]_rrnode[420]' -.meas tran sum_leakage_power_mux[0to64] -+ param='sum_leakage_power_mux[0to63]+leakage_sb_mux[0][1]_rrnode[420]' -.meas tran sum_energy_per_cycle_mux[0to64] -+ param='sum_energy_per_cycle_mux[0to63]+energy_per_cycle_sb_mux[0][1]_rrnode[420]' -***** Load for rr_node[420] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=29, type=5 ***** -Xchan_mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[248]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to64] -+ param='sum_leakage_power_sb_mux[0to63]+leakage_sb_mux[0][1]_rrnode[420]' -.meas tran sum_energy_per_cycle_sb_mux[0to64] -+ param='sum_energy_per_cycle_sb_mux[0to63]+energy_per_cycle_sb_mux[0][1]_rrnode[420]' -Xmux_1level_tapbuf_size2[65] mux_1level_tapbuf_size2[65]->in[0] mux_1level_tapbuf_size2[65]->in[1] mux_1level_tapbuf_size2[65]->out sram[75]->outb sram[75]->out gvdd_mux_1level_tapbuf_size2[65] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[65], level=1, select_path_id=0. ***** -*****1***** -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -***** Signal mux_1level_tapbuf_size2[65]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[65]->in[0] mux_1level_tapbuf_size2[65]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[65]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[65]->in[1] mux_1level_tapbuf_size2[65]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[65] gvdd_mux_1level_tapbuf_size2[65] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[422] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[422] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[422] when v(mux_1level_tapbuf_size2[65]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[422] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[422] when v(mux_1level_tapbuf_size2[65]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[422] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[65]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[422] param='mux_1level_tapbuf_size2[65]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[65]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[65]_energy_per_cycle param='mux_1level_tapbuf_size2[65]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[422] param='mux_1level_tapbuf_size2[65]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[422] param='dynamic_power_sb_mux[0][1]_rrnode[422]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[422] avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='start_rise_sb_mux[0][1]_rrnode[422]' to='start_rise_sb_mux[0][1]_rrnode[422]+switch_rise_sb_mux[0][1]_rrnode[422]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[422] avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='start_fall_sb_mux[0][1]_rrnode[422]' to='start_fall_sb_mux[0][1]_rrnode[422]+switch_fall_sb_mux[0][1]_rrnode[422]' -.meas tran sum_leakage_power_mux[0to65] -+ param='sum_leakage_power_mux[0to64]+leakage_sb_mux[0][1]_rrnode[422]' -.meas tran sum_energy_per_cycle_mux[0to65] -+ param='sum_energy_per_cycle_mux[0to64]+energy_per_cycle_sb_mux[0][1]_rrnode[422]' -***** Load for rr_node[422] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=31, type=5 ***** -Xchan_mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[252]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to65] -+ param='sum_leakage_power_sb_mux[0to64]+leakage_sb_mux[0][1]_rrnode[422]' -.meas tran sum_energy_per_cycle_sb_mux[0to65] -+ param='sum_energy_per_cycle_sb_mux[0to64]+energy_per_cycle_sb_mux[0][1]_rrnode[422]' -Xmux_1level_tapbuf_size2[66] mux_1level_tapbuf_size2[66]->in[0] mux_1level_tapbuf_size2[66]->in[1] mux_1level_tapbuf_size2[66]->out sram[76]->outb sram[76]->out gvdd_mux_1level_tapbuf_size2[66] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[66], level=1, select_path_id=0. ***** -*****1***** -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -***** Signal mux_1level_tapbuf_size2[66]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[66]->in[0] mux_1level_tapbuf_size2[66]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[66]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[66]->in[1] mux_1level_tapbuf_size2[66]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[66] gvdd_mux_1level_tapbuf_size2[66] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[424] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[424] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[424] when v(mux_1level_tapbuf_size2[66]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[424] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[424] when v(mux_1level_tapbuf_size2[66]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[424] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[66]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[424] param='mux_1level_tapbuf_size2[66]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[66]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[66]_energy_per_cycle param='mux_1level_tapbuf_size2[66]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[424] param='mux_1level_tapbuf_size2[66]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[424] param='dynamic_power_sb_mux[0][1]_rrnode[424]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[424] avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='start_rise_sb_mux[0][1]_rrnode[424]' to='start_rise_sb_mux[0][1]_rrnode[424]+switch_rise_sb_mux[0][1]_rrnode[424]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[424] avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='start_fall_sb_mux[0][1]_rrnode[424]' to='start_fall_sb_mux[0][1]_rrnode[424]+switch_fall_sb_mux[0][1]_rrnode[424]' -.meas tran sum_leakage_power_mux[0to66] -+ param='sum_leakage_power_mux[0to65]+leakage_sb_mux[0][1]_rrnode[424]' -.meas tran sum_energy_per_cycle_mux[0to66] -+ param='sum_energy_per_cycle_mux[0to65]+energy_per_cycle_sb_mux[0][1]_rrnode[424]' -***** Load for rr_node[424] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=33, type=5 ***** -Xchan_mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[256]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to66] -+ param='sum_leakage_power_sb_mux[0to65]+leakage_sb_mux[0][1]_rrnode[424]' -.meas tran sum_energy_per_cycle_sb_mux[0to66] -+ param='sum_energy_per_cycle_sb_mux[0to65]+energy_per_cycle_sb_mux[0][1]_rrnode[424]' -Xmux_1level_tapbuf_size2[67] mux_1level_tapbuf_size2[67]->in[0] mux_1level_tapbuf_size2[67]->in[1] mux_1level_tapbuf_size2[67]->out sram[77]->outb sram[77]->out gvdd_mux_1level_tapbuf_size2[67] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[67], level=1, select_path_id=0. ***** -*****1***** -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -***** Signal mux_1level_tapbuf_size2[67]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[67]->in[0] mux_1level_tapbuf_size2[67]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[67]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[67]->in[1] mux_1level_tapbuf_size2[67]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[67] gvdd_mux_1level_tapbuf_size2[67] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[426] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[426] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[426] when v(mux_1level_tapbuf_size2[67]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[426] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[426] when v(mux_1level_tapbuf_size2[67]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[426] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[67]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[426] param='mux_1level_tapbuf_size2[67]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[67]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[67]_energy_per_cycle param='mux_1level_tapbuf_size2[67]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[426] param='mux_1level_tapbuf_size2[67]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[426] param='dynamic_power_sb_mux[0][1]_rrnode[426]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[426] avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='start_rise_sb_mux[0][1]_rrnode[426]' to='start_rise_sb_mux[0][1]_rrnode[426]+switch_rise_sb_mux[0][1]_rrnode[426]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[426] avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='start_fall_sb_mux[0][1]_rrnode[426]' to='start_fall_sb_mux[0][1]_rrnode[426]+switch_fall_sb_mux[0][1]_rrnode[426]' -.meas tran sum_leakage_power_mux[0to67] -+ param='sum_leakage_power_mux[0to66]+leakage_sb_mux[0][1]_rrnode[426]' -.meas tran sum_energy_per_cycle_mux[0to67] -+ param='sum_energy_per_cycle_mux[0to66]+energy_per_cycle_sb_mux[0][1]_rrnode[426]' -***** Load for rr_node[426] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=35, type=5 ***** -Xchan_mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[260]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to67] -+ param='sum_leakage_power_sb_mux[0to66]+leakage_sb_mux[0][1]_rrnode[426]' -.meas tran sum_energy_per_cycle_sb_mux[0to67] -+ param='sum_energy_per_cycle_sb_mux[0to66]+energy_per_cycle_sb_mux[0][1]_rrnode[426]' -Xmux_1level_tapbuf_size2[68] mux_1level_tapbuf_size2[68]->in[0] mux_1level_tapbuf_size2[68]->in[1] mux_1level_tapbuf_size2[68]->out sram[78]->outb sram[78]->out gvdd_mux_1level_tapbuf_size2[68] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[68], level=1, select_path_id=0. ***** -*****1***** -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -***** Signal mux_1level_tapbuf_size2[68]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[68]->in[0] mux_1level_tapbuf_size2[68]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[68]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[68]->in[1] mux_1level_tapbuf_size2[68]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[68] gvdd_mux_1level_tapbuf_size2[68] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[428] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[428] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[428] when v(mux_1level_tapbuf_size2[68]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[428] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[428] when v(mux_1level_tapbuf_size2[68]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[428] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[68]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[428] param='mux_1level_tapbuf_size2[68]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[68]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[68]_energy_per_cycle param='mux_1level_tapbuf_size2[68]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[428] param='mux_1level_tapbuf_size2[68]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[428] param='dynamic_power_sb_mux[0][1]_rrnode[428]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[428] avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='start_rise_sb_mux[0][1]_rrnode[428]' to='start_rise_sb_mux[0][1]_rrnode[428]+switch_rise_sb_mux[0][1]_rrnode[428]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[428] avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='start_fall_sb_mux[0][1]_rrnode[428]' to='start_fall_sb_mux[0][1]_rrnode[428]+switch_fall_sb_mux[0][1]_rrnode[428]' -.meas tran sum_leakage_power_mux[0to68] -+ param='sum_leakage_power_mux[0to67]+leakage_sb_mux[0][1]_rrnode[428]' -.meas tran sum_energy_per_cycle_mux[0to68] -+ param='sum_energy_per_cycle_mux[0to67]+energy_per_cycle_sb_mux[0][1]_rrnode[428]' -***** Load for rr_node[428] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=37, type=5 ***** -Xchan_mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[264]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to68] -+ param='sum_leakage_power_sb_mux[0to67]+leakage_sb_mux[0][1]_rrnode[428]' -.meas tran sum_energy_per_cycle_sb_mux[0to68] -+ param='sum_energy_per_cycle_sb_mux[0to67]+energy_per_cycle_sb_mux[0][1]_rrnode[428]' -Xmux_1level_tapbuf_size2[69] mux_1level_tapbuf_size2[69]->in[0] mux_1level_tapbuf_size2[69]->in[1] mux_1level_tapbuf_size2[69]->out sram[79]->outb sram[79]->out gvdd_mux_1level_tapbuf_size2[69] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[69], level=1, select_path_id=0. ***** -*****1***** -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -***** Signal mux_1level_tapbuf_size2[69]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[69]->in[0] mux_1level_tapbuf_size2[69]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[69]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[69]->in[1] mux_1level_tapbuf_size2[69]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[69] gvdd_mux_1level_tapbuf_size2[69] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[430] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[430] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[430] when v(mux_1level_tapbuf_size2[69]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[430] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[430] when v(mux_1level_tapbuf_size2[69]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[430] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[69]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[430] param='mux_1level_tapbuf_size2[69]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[69]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[69]_energy_per_cycle param='mux_1level_tapbuf_size2[69]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[430] param='mux_1level_tapbuf_size2[69]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[430] param='dynamic_power_sb_mux[0][1]_rrnode[430]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[430] avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='start_rise_sb_mux[0][1]_rrnode[430]' to='start_rise_sb_mux[0][1]_rrnode[430]+switch_rise_sb_mux[0][1]_rrnode[430]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[430] avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='start_fall_sb_mux[0][1]_rrnode[430]' to='start_fall_sb_mux[0][1]_rrnode[430]+switch_fall_sb_mux[0][1]_rrnode[430]' -.meas tran sum_leakage_power_mux[0to69] -+ param='sum_leakage_power_mux[0to68]+leakage_sb_mux[0][1]_rrnode[430]' -.meas tran sum_energy_per_cycle_mux[0to69] -+ param='sum_energy_per_cycle_mux[0to68]+energy_per_cycle_sb_mux[0][1]_rrnode[430]' -***** Load for rr_node[430] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=39, type=5 ***** -Xchan_mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[268]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to69] -+ param='sum_leakage_power_sb_mux[0to68]+leakage_sb_mux[0][1]_rrnode[430]' -.meas tran sum_energy_per_cycle_sb_mux[0to69] -+ param='sum_energy_per_cycle_sb_mux[0to68]+energy_per_cycle_sb_mux[0][1]_rrnode[430]' -Xmux_1level_tapbuf_size2[70] mux_1level_tapbuf_size2[70]->in[0] mux_1level_tapbuf_size2[70]->in[1] mux_1level_tapbuf_size2[70]->out sram[80]->outb sram[80]->out gvdd_mux_1level_tapbuf_size2[70] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[70], level=1, select_path_id=0. ***** -*****1***** -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -***** Signal mux_1level_tapbuf_size2[70]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[70]->in[0] mux_1level_tapbuf_size2[70]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[70]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[70]->in[1] mux_1level_tapbuf_size2[70]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[70] gvdd_mux_1level_tapbuf_size2[70] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[432] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[432] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[432] when v(mux_1level_tapbuf_size2[70]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[432] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[432] when v(mux_1level_tapbuf_size2[70]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[432] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[70]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[432] param='mux_1level_tapbuf_size2[70]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[70]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[70]_energy_per_cycle param='mux_1level_tapbuf_size2[70]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[432] param='mux_1level_tapbuf_size2[70]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[432] param='dynamic_power_sb_mux[0][1]_rrnode[432]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[432] avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='start_rise_sb_mux[0][1]_rrnode[432]' to='start_rise_sb_mux[0][1]_rrnode[432]+switch_rise_sb_mux[0][1]_rrnode[432]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[432] avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='start_fall_sb_mux[0][1]_rrnode[432]' to='start_fall_sb_mux[0][1]_rrnode[432]+switch_fall_sb_mux[0][1]_rrnode[432]' -.meas tran sum_leakage_power_mux[0to70] -+ param='sum_leakage_power_mux[0to69]+leakage_sb_mux[0][1]_rrnode[432]' -.meas tran sum_energy_per_cycle_mux[0to70] -+ param='sum_energy_per_cycle_mux[0to69]+energy_per_cycle_sb_mux[0][1]_rrnode[432]' -***** Load for rr_node[432] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=41, type=5 ***** -Xchan_mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[272]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to70] -+ param='sum_leakage_power_sb_mux[0to69]+leakage_sb_mux[0][1]_rrnode[432]' -.meas tran sum_energy_per_cycle_sb_mux[0to70] -+ param='sum_energy_per_cycle_sb_mux[0to69]+energy_per_cycle_sb_mux[0][1]_rrnode[432]' -Xmux_1level_tapbuf_size2[71] mux_1level_tapbuf_size2[71]->in[0] mux_1level_tapbuf_size2[71]->in[1] mux_1level_tapbuf_size2[71]->out sram[81]->outb sram[81]->out gvdd_mux_1level_tapbuf_size2[71] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[71], level=1, select_path_id=0. ***** -*****1***** -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -***** Signal mux_1level_tapbuf_size2[71]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[71]->in[0] mux_1level_tapbuf_size2[71]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[71]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[71]->in[1] mux_1level_tapbuf_size2[71]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[71] gvdd_mux_1level_tapbuf_size2[71] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[434] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[434] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[434] when v(mux_1level_tapbuf_size2[71]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[434] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[434] when v(mux_1level_tapbuf_size2[71]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[434] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[71]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[434] param='mux_1level_tapbuf_size2[71]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[71]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[71]_energy_per_cycle param='mux_1level_tapbuf_size2[71]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[434] param='mux_1level_tapbuf_size2[71]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[434] param='dynamic_power_sb_mux[0][1]_rrnode[434]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[434] avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='start_rise_sb_mux[0][1]_rrnode[434]' to='start_rise_sb_mux[0][1]_rrnode[434]+switch_rise_sb_mux[0][1]_rrnode[434]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[434] avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='start_fall_sb_mux[0][1]_rrnode[434]' to='start_fall_sb_mux[0][1]_rrnode[434]+switch_fall_sb_mux[0][1]_rrnode[434]' -.meas tran sum_leakage_power_mux[0to71] -+ param='sum_leakage_power_mux[0to70]+leakage_sb_mux[0][1]_rrnode[434]' -.meas tran sum_energy_per_cycle_mux[0to71] -+ param='sum_energy_per_cycle_mux[0to70]+energy_per_cycle_sb_mux[0][1]_rrnode[434]' -***** Load for rr_node[434] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=43, type=5 ***** -Xchan_mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[275]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to71] -+ param='sum_leakage_power_sb_mux[0to70]+leakage_sb_mux[0][1]_rrnode[434]' -.meas tran sum_energy_per_cycle_sb_mux[0to71] -+ param='sum_energy_per_cycle_sb_mux[0to70]+energy_per_cycle_sb_mux[0][1]_rrnode[434]' -Xmux_1level_tapbuf_size2[72] mux_1level_tapbuf_size2[72]->in[0] mux_1level_tapbuf_size2[72]->in[1] mux_1level_tapbuf_size2[72]->out sram[82]->outb sram[82]->out gvdd_mux_1level_tapbuf_size2[72] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[72], level=1, select_path_id=0. ***** -*****1***** -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -***** Signal mux_1level_tapbuf_size2[72]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[72]->in[0] mux_1level_tapbuf_size2[72]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[72]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[72]->in[1] mux_1level_tapbuf_size2[72]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[72] gvdd_mux_1level_tapbuf_size2[72] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[436] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[436] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[436] when v(mux_1level_tapbuf_size2[72]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[436] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[436] when v(mux_1level_tapbuf_size2[72]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[436] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[72]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[436] param='mux_1level_tapbuf_size2[72]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[72]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[72]_energy_per_cycle param='mux_1level_tapbuf_size2[72]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[436] param='mux_1level_tapbuf_size2[72]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[436] param='dynamic_power_sb_mux[0][1]_rrnode[436]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[436] avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='start_rise_sb_mux[0][1]_rrnode[436]' to='start_rise_sb_mux[0][1]_rrnode[436]+switch_rise_sb_mux[0][1]_rrnode[436]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[436] avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='start_fall_sb_mux[0][1]_rrnode[436]' to='start_fall_sb_mux[0][1]_rrnode[436]+switch_fall_sb_mux[0][1]_rrnode[436]' -.meas tran sum_leakage_power_mux[0to72] -+ param='sum_leakage_power_mux[0to71]+leakage_sb_mux[0][1]_rrnode[436]' -.meas tran sum_energy_per_cycle_mux[0to72] -+ param='sum_energy_per_cycle_mux[0to71]+energy_per_cycle_sb_mux[0][1]_rrnode[436]' -***** Load for rr_node[436] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=45, type=5 ***** -Xchan_mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[279]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to72] -+ param='sum_leakage_power_sb_mux[0to71]+leakage_sb_mux[0][1]_rrnode[436]' -.meas tran sum_energy_per_cycle_sb_mux[0to72] -+ param='sum_energy_per_cycle_sb_mux[0to71]+energy_per_cycle_sb_mux[0][1]_rrnode[436]' -Xmux_1level_tapbuf_size2[73] mux_1level_tapbuf_size2[73]->in[0] mux_1level_tapbuf_size2[73]->in[1] mux_1level_tapbuf_size2[73]->out sram[83]->outb sram[83]->out gvdd_mux_1level_tapbuf_size2[73] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[73], level=1, select_path_id=0. ***** -*****1***** -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -***** Signal mux_1level_tapbuf_size2[73]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[73]->in[0] mux_1level_tapbuf_size2[73]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[73]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[73]->in[1] mux_1level_tapbuf_size2[73]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[73] gvdd_mux_1level_tapbuf_size2[73] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[438] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[438] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[438] when v(mux_1level_tapbuf_size2[73]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[438] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[438] when v(mux_1level_tapbuf_size2[73]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[438] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[73]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[438] param='mux_1level_tapbuf_size2[73]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[73]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[73]_energy_per_cycle param='mux_1level_tapbuf_size2[73]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[438] param='mux_1level_tapbuf_size2[73]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[438] param='dynamic_power_sb_mux[0][1]_rrnode[438]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[438] avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='start_rise_sb_mux[0][1]_rrnode[438]' to='start_rise_sb_mux[0][1]_rrnode[438]+switch_rise_sb_mux[0][1]_rrnode[438]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[438] avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='start_fall_sb_mux[0][1]_rrnode[438]' to='start_fall_sb_mux[0][1]_rrnode[438]+switch_fall_sb_mux[0][1]_rrnode[438]' -.meas tran sum_leakage_power_mux[0to73] -+ param='sum_leakage_power_mux[0to72]+leakage_sb_mux[0][1]_rrnode[438]' -.meas tran sum_energy_per_cycle_mux[0to73] -+ param='sum_energy_per_cycle_mux[0to72]+energy_per_cycle_sb_mux[0][1]_rrnode[438]' -***** Load for rr_node[438] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=47, type=5 ***** -Xchan_mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[284]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to73] -+ param='sum_leakage_power_sb_mux[0to72]+leakage_sb_mux[0][1]_rrnode[438]' -.meas tran sum_energy_per_cycle_sb_mux[0to73] -+ param='sum_energy_per_cycle_sb_mux[0to72]+energy_per_cycle_sb_mux[0][1]_rrnode[438]' -Xmux_1level_tapbuf_size2[74] mux_1level_tapbuf_size2[74]->in[0] mux_1level_tapbuf_size2[74]->in[1] mux_1level_tapbuf_size2[74]->out sram[84]->outb sram[84]->out gvdd_mux_1level_tapbuf_size2[74] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[74], level=1, select_path_id=0. ***** -*****1***** -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -***** Signal mux_1level_tapbuf_size2[74]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[74]->in[0] mux_1level_tapbuf_size2[74]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[74]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[74]->in[1] mux_1level_tapbuf_size2[74]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[74] gvdd_mux_1level_tapbuf_size2[74] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[440] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[440] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[440] when v(mux_1level_tapbuf_size2[74]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[440] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[440] when v(mux_1level_tapbuf_size2[74]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[440] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[74]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[440] param='mux_1level_tapbuf_size2[74]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[74]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[74]_energy_per_cycle param='mux_1level_tapbuf_size2[74]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[440] param='mux_1level_tapbuf_size2[74]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[440] param='dynamic_power_sb_mux[0][1]_rrnode[440]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[440] avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='start_rise_sb_mux[0][1]_rrnode[440]' to='start_rise_sb_mux[0][1]_rrnode[440]+switch_rise_sb_mux[0][1]_rrnode[440]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[440] avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='start_fall_sb_mux[0][1]_rrnode[440]' to='start_fall_sb_mux[0][1]_rrnode[440]+switch_fall_sb_mux[0][1]_rrnode[440]' -.meas tran sum_leakage_power_mux[0to74] -+ param='sum_leakage_power_mux[0to73]+leakage_sb_mux[0][1]_rrnode[440]' -.meas tran sum_energy_per_cycle_mux[0to74] -+ param='sum_energy_per_cycle_mux[0to73]+energy_per_cycle_sb_mux[0][1]_rrnode[440]' -***** Load for rr_node[440] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=49, type=5 ***** -Xchan_mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[287]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to74] -+ param='sum_leakage_power_sb_mux[0to73]+leakage_sb_mux[0][1]_rrnode[440]' -.meas tran sum_energy_per_cycle_sb_mux[0to74] -+ param='sum_energy_per_cycle_sb_mux[0to73]+energy_per_cycle_sb_mux[0][1]_rrnode[440]' -Xmux_1level_tapbuf_size2[75] mux_1level_tapbuf_size2[75]->in[0] mux_1level_tapbuf_size2[75]->in[1] mux_1level_tapbuf_size2[75]->out sram[85]->outb sram[85]->out gvdd_mux_1level_tapbuf_size2[75] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[75], level=1, select_path_id=0. ***** -*****1***** -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -***** Signal mux_1level_tapbuf_size2[75]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[75]->in[0] mux_1level_tapbuf_size2[75]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[75]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[75]->in[1] mux_1level_tapbuf_size2[75]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[75] gvdd_mux_1level_tapbuf_size2[75] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[442] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[442] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[442] when v(mux_1level_tapbuf_size2[75]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[442] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[442] when v(mux_1level_tapbuf_size2[75]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[442] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[75]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[442] param='mux_1level_tapbuf_size2[75]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[75]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[75]_energy_per_cycle param='mux_1level_tapbuf_size2[75]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[442] param='mux_1level_tapbuf_size2[75]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[442] param='dynamic_power_sb_mux[0][1]_rrnode[442]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[442] avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='start_rise_sb_mux[0][1]_rrnode[442]' to='start_rise_sb_mux[0][1]_rrnode[442]+switch_rise_sb_mux[0][1]_rrnode[442]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[442] avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='start_fall_sb_mux[0][1]_rrnode[442]' to='start_fall_sb_mux[0][1]_rrnode[442]+switch_fall_sb_mux[0][1]_rrnode[442]' -.meas tran sum_leakage_power_mux[0to75] -+ param='sum_leakage_power_mux[0to74]+leakage_sb_mux[0][1]_rrnode[442]' -.meas tran sum_energy_per_cycle_mux[0to75] -+ param='sum_energy_per_cycle_mux[0to74]+energy_per_cycle_sb_mux[0][1]_rrnode[442]' -***** Load for rr_node[442] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=51, type=5 ***** -Xchan_mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[291]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to75] -+ param='sum_leakage_power_sb_mux[0to74]+leakage_sb_mux[0][1]_rrnode[442]' -.meas tran sum_energy_per_cycle_sb_mux[0to75] -+ param='sum_energy_per_cycle_sb_mux[0to74]+energy_per_cycle_sb_mux[0][1]_rrnode[442]' -Xmux_1level_tapbuf_size2[76] mux_1level_tapbuf_size2[76]->in[0] mux_1level_tapbuf_size2[76]->in[1] mux_1level_tapbuf_size2[76]->out sram[86]->outb sram[86]->out gvdd_mux_1level_tapbuf_size2[76] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[76], level=1, select_path_id=0. ***** -*****1***** -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -***** Signal mux_1level_tapbuf_size2[76]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[76]->in[0] mux_1level_tapbuf_size2[76]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[76]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[76]->in[1] mux_1level_tapbuf_size2[76]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[76] gvdd_mux_1level_tapbuf_size2[76] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[444] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[444] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[444] when v(mux_1level_tapbuf_size2[76]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[444] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[444] when v(mux_1level_tapbuf_size2[76]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[444] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[76]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[444] param='mux_1level_tapbuf_size2[76]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[76]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[76]_energy_per_cycle param='mux_1level_tapbuf_size2[76]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[444] param='mux_1level_tapbuf_size2[76]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[444] param='dynamic_power_sb_mux[0][1]_rrnode[444]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[444] avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='start_rise_sb_mux[0][1]_rrnode[444]' to='start_rise_sb_mux[0][1]_rrnode[444]+switch_rise_sb_mux[0][1]_rrnode[444]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[444] avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='start_fall_sb_mux[0][1]_rrnode[444]' to='start_fall_sb_mux[0][1]_rrnode[444]+switch_fall_sb_mux[0][1]_rrnode[444]' -.meas tran sum_leakage_power_mux[0to76] -+ param='sum_leakage_power_mux[0to75]+leakage_sb_mux[0][1]_rrnode[444]' -.meas tran sum_energy_per_cycle_mux[0to76] -+ param='sum_energy_per_cycle_mux[0to75]+energy_per_cycle_sb_mux[0][1]_rrnode[444]' -***** Load for rr_node[444] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=53, type=5 ***** -Xchan_mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[295]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to76] -+ param='sum_leakage_power_sb_mux[0to75]+leakage_sb_mux[0][1]_rrnode[444]' -.meas tran sum_energy_per_cycle_sb_mux[0to76] -+ param='sum_energy_per_cycle_sb_mux[0to75]+energy_per_cycle_sb_mux[0][1]_rrnode[444]' -Xmux_1level_tapbuf_size2[77] mux_1level_tapbuf_size2[77]->in[0] mux_1level_tapbuf_size2[77]->in[1] mux_1level_tapbuf_size2[77]->out sram[87]->outb sram[87]->out gvdd_mux_1level_tapbuf_size2[77] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[77], level=1, select_path_id=0. ***** -*****1***** -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -***** Signal mux_1level_tapbuf_size2[77]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[77]->in[0] mux_1level_tapbuf_size2[77]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[77]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[77]->in[1] mux_1level_tapbuf_size2[77]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[77] gvdd_mux_1level_tapbuf_size2[77] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[446] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[446] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[446] when v(mux_1level_tapbuf_size2[77]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[446] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[446] when v(mux_1level_tapbuf_size2[77]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[446] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[77]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[446] param='mux_1level_tapbuf_size2[77]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[77]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[77]_energy_per_cycle param='mux_1level_tapbuf_size2[77]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[446] param='mux_1level_tapbuf_size2[77]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[446] param='dynamic_power_sb_mux[0][1]_rrnode[446]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[446] avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='start_rise_sb_mux[0][1]_rrnode[446]' to='start_rise_sb_mux[0][1]_rrnode[446]+switch_rise_sb_mux[0][1]_rrnode[446]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[446] avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='start_fall_sb_mux[0][1]_rrnode[446]' to='start_fall_sb_mux[0][1]_rrnode[446]+switch_fall_sb_mux[0][1]_rrnode[446]' -.meas tran sum_leakage_power_mux[0to77] -+ param='sum_leakage_power_mux[0to76]+leakage_sb_mux[0][1]_rrnode[446]' -.meas tran sum_energy_per_cycle_mux[0to77] -+ param='sum_energy_per_cycle_mux[0to76]+energy_per_cycle_sb_mux[0][1]_rrnode[446]' -***** Load for rr_node[446] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=55, type=5 ***** -Xchan_mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[299]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[300]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to77] -+ param='sum_leakage_power_sb_mux[0to76]+leakage_sb_mux[0][1]_rrnode[446]' -.meas tran sum_energy_per_cycle_sb_mux[0to77] -+ param='sum_energy_per_cycle_sb_mux[0to76]+energy_per_cycle_sb_mux[0][1]_rrnode[446]' -Xmux_1level_tapbuf_size2[78] mux_1level_tapbuf_size2[78]->in[0] mux_1level_tapbuf_size2[78]->in[1] mux_1level_tapbuf_size2[78]->out sram[88]->outb sram[88]->out gvdd_mux_1level_tapbuf_size2[78] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[78], level=1, select_path_id=0. ***** -*****1***** -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -***** Signal mux_1level_tapbuf_size2[78]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[78]->in[0] mux_1level_tapbuf_size2[78]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[78]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[78]->in[1] mux_1level_tapbuf_size2[78]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[78] gvdd_mux_1level_tapbuf_size2[78] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[448] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[448] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[448] when v(mux_1level_tapbuf_size2[78]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[448] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[448] when v(mux_1level_tapbuf_size2[78]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[448] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[78]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[448] param='mux_1level_tapbuf_size2[78]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[78]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[78]_energy_per_cycle param='mux_1level_tapbuf_size2[78]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[448] param='mux_1level_tapbuf_size2[78]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[448] param='dynamic_power_sb_mux[0][1]_rrnode[448]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[448] avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='start_rise_sb_mux[0][1]_rrnode[448]' to='start_rise_sb_mux[0][1]_rrnode[448]+switch_rise_sb_mux[0][1]_rrnode[448]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[448] avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='start_fall_sb_mux[0][1]_rrnode[448]' to='start_fall_sb_mux[0][1]_rrnode[448]+switch_fall_sb_mux[0][1]_rrnode[448]' -.meas tran sum_leakage_power_mux[0to78] -+ param='sum_leakage_power_mux[0to77]+leakage_sb_mux[0][1]_rrnode[448]' -.meas tran sum_energy_per_cycle_mux[0to78] -+ param='sum_energy_per_cycle_mux[0to77]+energy_per_cycle_sb_mux[0][1]_rrnode[448]' -***** Load for rr_node[448] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=57, type=5 ***** -Xchan_mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[303]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to78] -+ param='sum_leakage_power_sb_mux[0to77]+leakage_sb_mux[0][1]_rrnode[448]' -.meas tran sum_energy_per_cycle_sb_mux[0to78] -+ param='sum_energy_per_cycle_sb_mux[0to77]+energy_per_cycle_sb_mux[0][1]_rrnode[448]' -Xmux_1level_tapbuf_size2[79] mux_1level_tapbuf_size2[79]->in[0] mux_1level_tapbuf_size2[79]->in[1] mux_1level_tapbuf_size2[79]->out sram[89]->outb sram[89]->out gvdd_mux_1level_tapbuf_size2[79] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[79], level=1, select_path_id=0. ***** -*****1***** -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -***** Signal mux_1level_tapbuf_size2[79]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[79]->in[0] mux_1level_tapbuf_size2[79]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[79]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[79]->in[1] mux_1level_tapbuf_size2[79]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[79] gvdd_mux_1level_tapbuf_size2[79] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[450] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[450] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[450] when v(mux_1level_tapbuf_size2[79]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[450] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[450] when v(mux_1level_tapbuf_size2[79]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[450] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[79]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[450] param='mux_1level_tapbuf_size2[79]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[79]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[79]_energy_per_cycle param='mux_1level_tapbuf_size2[79]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[450] param='mux_1level_tapbuf_size2[79]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[450] param='dynamic_power_sb_mux[0][1]_rrnode[450]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[450] avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='start_rise_sb_mux[0][1]_rrnode[450]' to='start_rise_sb_mux[0][1]_rrnode[450]+switch_rise_sb_mux[0][1]_rrnode[450]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[450] avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='start_fall_sb_mux[0][1]_rrnode[450]' to='start_fall_sb_mux[0][1]_rrnode[450]+switch_fall_sb_mux[0][1]_rrnode[450]' -.meas tran sum_leakage_power_mux[0to79] -+ param='sum_leakage_power_mux[0to78]+leakage_sb_mux[0][1]_rrnode[450]' -.meas tran sum_energy_per_cycle_mux[0to79] -+ param='sum_energy_per_cycle_mux[0to78]+energy_per_cycle_sb_mux[0][1]_rrnode[450]' -***** Load for rr_node[450] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=59, type=5 ***** -Xchan_mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[306]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to79] -+ param='sum_leakage_power_sb_mux[0to78]+leakage_sb_mux[0][1]_rrnode[450]' -.meas tran sum_energy_per_cycle_sb_mux[0to79] -+ param='sum_energy_per_cycle_sb_mux[0to78]+energy_per_cycle_sb_mux[0][1]_rrnode[450]' -Xmux_1level_tapbuf_size2[80] mux_1level_tapbuf_size2[80]->in[0] mux_1level_tapbuf_size2[80]->in[1] mux_1level_tapbuf_size2[80]->out sram[90]->outb sram[90]->out gvdd_mux_1level_tapbuf_size2[80] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[80], level=1, select_path_id=0. ***** -*****1***** -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -***** Signal mux_1level_tapbuf_size2[80]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[80]->in[0] mux_1level_tapbuf_size2[80]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[80]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[80]->in[1] mux_1level_tapbuf_size2[80]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[80] gvdd_mux_1level_tapbuf_size2[80] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[452] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[452] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[452] when v(mux_1level_tapbuf_size2[80]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[452] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[452] when v(mux_1level_tapbuf_size2[80]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[452] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[80]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[452] param='mux_1level_tapbuf_size2[80]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[80]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[80]_energy_per_cycle param='mux_1level_tapbuf_size2[80]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[452] param='mux_1level_tapbuf_size2[80]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[452] param='dynamic_power_sb_mux[0][1]_rrnode[452]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[452] avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='start_rise_sb_mux[0][1]_rrnode[452]' to='start_rise_sb_mux[0][1]_rrnode[452]+switch_rise_sb_mux[0][1]_rrnode[452]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[452] avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='start_fall_sb_mux[0][1]_rrnode[452]' to='start_fall_sb_mux[0][1]_rrnode[452]+switch_fall_sb_mux[0][1]_rrnode[452]' -.meas tran sum_leakage_power_mux[0to80] -+ param='sum_leakage_power_mux[0to79]+leakage_sb_mux[0][1]_rrnode[452]' -.meas tran sum_energy_per_cycle_mux[0to80] -+ param='sum_energy_per_cycle_mux[0to79]+energy_per_cycle_sb_mux[0][1]_rrnode[452]' -***** Load for rr_node[452] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=61, type=5 ***** -Xchan_mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[311]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to80] -+ param='sum_leakage_power_sb_mux[0to79]+leakage_sb_mux[0][1]_rrnode[452]' -.meas tran sum_energy_per_cycle_sb_mux[0to80] -+ param='sum_energy_per_cycle_sb_mux[0to79]+energy_per_cycle_sb_mux[0][1]_rrnode[452]' -Xmux_1level_tapbuf_size2[81] mux_1level_tapbuf_size2[81]->in[0] mux_1level_tapbuf_size2[81]->in[1] mux_1level_tapbuf_size2[81]->out sram[91]->outb sram[91]->out gvdd_mux_1level_tapbuf_size2[81] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[81], level=1, select_path_id=0. ***** -*****1***** -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -***** Signal mux_1level_tapbuf_size2[81]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[81]->in[0] mux_1level_tapbuf_size2[81]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[81]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[81]->in[1] mux_1level_tapbuf_size2[81]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[81] gvdd_mux_1level_tapbuf_size2[81] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[454] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[454] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[454] when v(mux_1level_tapbuf_size2[81]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[454] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[454] when v(mux_1level_tapbuf_size2[81]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[454] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[81]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[454] param='mux_1level_tapbuf_size2[81]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[81]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[81]_energy_per_cycle param='mux_1level_tapbuf_size2[81]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[454] param='mux_1level_tapbuf_size2[81]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[454] param='dynamic_power_sb_mux[0][1]_rrnode[454]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[454] avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='start_rise_sb_mux[0][1]_rrnode[454]' to='start_rise_sb_mux[0][1]_rrnode[454]+switch_rise_sb_mux[0][1]_rrnode[454]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[454] avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='start_fall_sb_mux[0][1]_rrnode[454]' to='start_fall_sb_mux[0][1]_rrnode[454]+switch_fall_sb_mux[0][1]_rrnode[454]' -.meas tran sum_leakage_power_mux[0to81] -+ param='sum_leakage_power_mux[0to80]+leakage_sb_mux[0][1]_rrnode[454]' -.meas tran sum_energy_per_cycle_mux[0to81] -+ param='sum_energy_per_cycle_mux[0to80]+energy_per_cycle_sb_mux[0][1]_rrnode[454]' -***** Load for rr_node[454] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=63, type=5 ***** -Xchan_mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[314]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to81] -+ param='sum_leakage_power_sb_mux[0to80]+leakage_sb_mux[0][1]_rrnode[454]' -.meas tran sum_energy_per_cycle_sb_mux[0to81] -+ param='sum_energy_per_cycle_sb_mux[0to80]+energy_per_cycle_sb_mux[0][1]_rrnode[454]' -Xmux_1level_tapbuf_size2[82] mux_1level_tapbuf_size2[82]->in[0] mux_1level_tapbuf_size2[82]->in[1] mux_1level_tapbuf_size2[82]->out sram[92]->outb sram[92]->out gvdd_mux_1level_tapbuf_size2[82] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[82], level=1, select_path_id=0. ***** -*****1***** -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -***** Signal mux_1level_tapbuf_size2[82]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[82]->in[0] mux_1level_tapbuf_size2[82]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[82]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[82]->in[1] mux_1level_tapbuf_size2[82]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[82] gvdd_mux_1level_tapbuf_size2[82] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[456] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[456] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[456] when v(mux_1level_tapbuf_size2[82]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[456] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[456] when v(mux_1level_tapbuf_size2[82]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[456] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[82]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[456] param='mux_1level_tapbuf_size2[82]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[82]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[82]_energy_per_cycle param='mux_1level_tapbuf_size2[82]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[456] param='mux_1level_tapbuf_size2[82]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[456] param='dynamic_power_sb_mux[0][1]_rrnode[456]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[456] avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='start_rise_sb_mux[0][1]_rrnode[456]' to='start_rise_sb_mux[0][1]_rrnode[456]+switch_rise_sb_mux[0][1]_rrnode[456]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[456] avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='start_fall_sb_mux[0][1]_rrnode[456]' to='start_fall_sb_mux[0][1]_rrnode[456]+switch_fall_sb_mux[0][1]_rrnode[456]' -.meas tran sum_leakage_power_mux[0to82] -+ param='sum_leakage_power_mux[0to81]+leakage_sb_mux[0][1]_rrnode[456]' -.meas tran sum_energy_per_cycle_mux[0to82] -+ param='sum_energy_per_cycle_mux[0to81]+energy_per_cycle_sb_mux[0][1]_rrnode[456]' -***** Load for rr_node[456] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=65, type=5 ***** -Xchan_mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[318]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to82] -+ param='sum_leakage_power_sb_mux[0to81]+leakage_sb_mux[0][1]_rrnode[456]' -.meas tran sum_energy_per_cycle_sb_mux[0to82] -+ param='sum_energy_per_cycle_sb_mux[0to81]+energy_per_cycle_sb_mux[0][1]_rrnode[456]' -Xmux_1level_tapbuf_size2[83] mux_1level_tapbuf_size2[83]->in[0] mux_1level_tapbuf_size2[83]->in[1] mux_1level_tapbuf_size2[83]->out sram[93]->outb sram[93]->out gvdd_mux_1level_tapbuf_size2[83] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[83], level=1, select_path_id=0. ***** -*****1***** -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -***** Signal mux_1level_tapbuf_size2[83]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[83]->in[0] mux_1level_tapbuf_size2[83]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[83]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[83]->in[1] mux_1level_tapbuf_size2[83]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[83] gvdd_mux_1level_tapbuf_size2[83] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[458] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[458] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[458] when v(mux_1level_tapbuf_size2[83]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[458] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[458] when v(mux_1level_tapbuf_size2[83]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[458] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[83]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[458] param='mux_1level_tapbuf_size2[83]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[83]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[83]_energy_per_cycle param='mux_1level_tapbuf_size2[83]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[458] param='mux_1level_tapbuf_size2[83]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[458] param='dynamic_power_sb_mux[0][1]_rrnode[458]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[458] avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='start_rise_sb_mux[0][1]_rrnode[458]' to='start_rise_sb_mux[0][1]_rrnode[458]+switch_rise_sb_mux[0][1]_rrnode[458]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[458] avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='start_fall_sb_mux[0][1]_rrnode[458]' to='start_fall_sb_mux[0][1]_rrnode[458]+switch_fall_sb_mux[0][1]_rrnode[458]' -.meas tran sum_leakage_power_mux[0to83] -+ param='sum_leakage_power_mux[0to82]+leakage_sb_mux[0][1]_rrnode[458]' -.meas tran sum_energy_per_cycle_mux[0to83] -+ param='sum_energy_per_cycle_mux[0to82]+energy_per_cycle_sb_mux[0][1]_rrnode[458]' -***** Load for rr_node[458] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=67, type=5 ***** -Xchan_mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[322]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to83] -+ param='sum_leakage_power_sb_mux[0to82]+leakage_sb_mux[0][1]_rrnode[458]' -.meas tran sum_energy_per_cycle_sb_mux[0to83] -+ param='sum_energy_per_cycle_sb_mux[0to82]+energy_per_cycle_sb_mux[0][1]_rrnode[458]' -Xmux_1level_tapbuf_size2[84] mux_1level_tapbuf_size2[84]->in[0] mux_1level_tapbuf_size2[84]->in[1] mux_1level_tapbuf_size2[84]->out sram[94]->outb sram[94]->out gvdd_mux_1level_tapbuf_size2[84] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[84], level=1, select_path_id=0. ***** -*****1***** -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -***** Signal mux_1level_tapbuf_size2[84]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[84]->in[0] mux_1level_tapbuf_size2[84]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[84]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[84]->in[1] mux_1level_tapbuf_size2[84]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[84] gvdd_mux_1level_tapbuf_size2[84] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[460] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[460] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[460] when v(mux_1level_tapbuf_size2[84]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[460] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[460] when v(mux_1level_tapbuf_size2[84]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[460] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[84]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[460] param='mux_1level_tapbuf_size2[84]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[84]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[84]_energy_per_cycle param='mux_1level_tapbuf_size2[84]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[460] param='mux_1level_tapbuf_size2[84]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[460] param='dynamic_power_sb_mux[0][1]_rrnode[460]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[460] avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='start_rise_sb_mux[0][1]_rrnode[460]' to='start_rise_sb_mux[0][1]_rrnode[460]+switch_rise_sb_mux[0][1]_rrnode[460]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[460] avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='start_fall_sb_mux[0][1]_rrnode[460]' to='start_fall_sb_mux[0][1]_rrnode[460]+switch_fall_sb_mux[0][1]_rrnode[460]' -.meas tran sum_leakage_power_mux[0to84] -+ param='sum_leakage_power_mux[0to83]+leakage_sb_mux[0][1]_rrnode[460]' -.meas tran sum_energy_per_cycle_mux[0to84] -+ param='sum_energy_per_cycle_mux[0to83]+energy_per_cycle_sb_mux[0][1]_rrnode[460]' -***** Load for rr_node[460] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=69, type=5 ***** -Xchan_mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[326]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to84] -+ param='sum_leakage_power_sb_mux[0to83]+leakage_sb_mux[0][1]_rrnode[460]' -.meas tran sum_energy_per_cycle_sb_mux[0to84] -+ param='sum_energy_per_cycle_sb_mux[0to83]+energy_per_cycle_sb_mux[0][1]_rrnode[460]' -Xmux_1level_tapbuf_size2[85] mux_1level_tapbuf_size2[85]->in[0] mux_1level_tapbuf_size2[85]->in[1] mux_1level_tapbuf_size2[85]->out sram[95]->outb sram[95]->out gvdd_mux_1level_tapbuf_size2[85] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[85], level=1, select_path_id=0. ***** -*****1***** -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -***** Signal mux_1level_tapbuf_size2[85]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[85]->in[0] mux_1level_tapbuf_size2[85]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[85]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[85]->in[1] mux_1level_tapbuf_size2[85]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[85] gvdd_mux_1level_tapbuf_size2[85] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[462] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[462] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[462] when v(mux_1level_tapbuf_size2[85]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[462] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[462] when v(mux_1level_tapbuf_size2[85]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[462] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[85]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[462] param='mux_1level_tapbuf_size2[85]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[85]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[85]_energy_per_cycle param='mux_1level_tapbuf_size2[85]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[462] param='mux_1level_tapbuf_size2[85]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[462] param='dynamic_power_sb_mux[0][1]_rrnode[462]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[462] avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='start_rise_sb_mux[0][1]_rrnode[462]' to='start_rise_sb_mux[0][1]_rrnode[462]+switch_rise_sb_mux[0][1]_rrnode[462]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[462] avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='start_fall_sb_mux[0][1]_rrnode[462]' to='start_fall_sb_mux[0][1]_rrnode[462]+switch_fall_sb_mux[0][1]_rrnode[462]' -.meas tran sum_leakage_power_mux[0to85] -+ param='sum_leakage_power_mux[0to84]+leakage_sb_mux[0][1]_rrnode[462]' -.meas tran sum_energy_per_cycle_mux[0to85] -+ param='sum_energy_per_cycle_mux[0to84]+energy_per_cycle_sb_mux[0][1]_rrnode[462]' -***** Load for rr_node[462] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=71, type=5 ***** -Xchan_mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[330]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to85] -+ param='sum_leakage_power_sb_mux[0to84]+leakage_sb_mux[0][1]_rrnode[462]' -.meas tran sum_energy_per_cycle_sb_mux[0to85] -+ param='sum_energy_per_cycle_sb_mux[0to84]+energy_per_cycle_sb_mux[0][1]_rrnode[462]' -Xmux_1level_tapbuf_size2[86] mux_1level_tapbuf_size2[86]->in[0] mux_1level_tapbuf_size2[86]->in[1] mux_1level_tapbuf_size2[86]->out sram[96]->outb sram[96]->out gvdd_mux_1level_tapbuf_size2[86] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[86], level=1, select_path_id=0. ***** -*****1***** -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -***** Signal mux_1level_tapbuf_size2[86]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[86]->in[0] mux_1level_tapbuf_size2[86]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[86]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[86]->in[1] mux_1level_tapbuf_size2[86]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[86] gvdd_mux_1level_tapbuf_size2[86] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[464] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[464] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[464] when v(mux_1level_tapbuf_size2[86]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[464] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[464] when v(mux_1level_tapbuf_size2[86]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[464] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[86]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[464] param='mux_1level_tapbuf_size2[86]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[86]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[86]_energy_per_cycle param='mux_1level_tapbuf_size2[86]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[464] param='mux_1level_tapbuf_size2[86]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[464] param='dynamic_power_sb_mux[0][1]_rrnode[464]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[464] avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='start_rise_sb_mux[0][1]_rrnode[464]' to='start_rise_sb_mux[0][1]_rrnode[464]+switch_rise_sb_mux[0][1]_rrnode[464]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[464] avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='start_fall_sb_mux[0][1]_rrnode[464]' to='start_fall_sb_mux[0][1]_rrnode[464]+switch_fall_sb_mux[0][1]_rrnode[464]' -.meas tran sum_leakage_power_mux[0to86] -+ param='sum_leakage_power_mux[0to85]+leakage_sb_mux[0][1]_rrnode[464]' -.meas tran sum_energy_per_cycle_mux[0to86] -+ param='sum_energy_per_cycle_mux[0to85]+energy_per_cycle_sb_mux[0][1]_rrnode[464]' -***** Load for rr_node[464] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=73, type=5 ***** -Xchan_mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[333]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[335]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to86] -+ param='sum_leakage_power_sb_mux[0to85]+leakage_sb_mux[0][1]_rrnode[464]' -.meas tran sum_energy_per_cycle_sb_mux[0to86] -+ param='sum_energy_per_cycle_sb_mux[0to85]+energy_per_cycle_sb_mux[0][1]_rrnode[464]' -Xmux_1level_tapbuf_size2[87] mux_1level_tapbuf_size2[87]->in[0] mux_1level_tapbuf_size2[87]->in[1] mux_1level_tapbuf_size2[87]->out sram[97]->outb sram[97]->out gvdd_mux_1level_tapbuf_size2[87] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[87], level=1, select_path_id=0. ***** -*****1***** -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -***** Signal mux_1level_tapbuf_size2[87]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[87]->in[0] mux_1level_tapbuf_size2[87]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[87]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[87]->in[1] mux_1level_tapbuf_size2[87]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[87] gvdd_mux_1level_tapbuf_size2[87] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[466] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[466] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[466] when v(mux_1level_tapbuf_size2[87]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[466] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[466] when v(mux_1level_tapbuf_size2[87]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[466] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[87]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[466] param='mux_1level_tapbuf_size2[87]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[87]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[87]_energy_per_cycle param='mux_1level_tapbuf_size2[87]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[466] param='mux_1level_tapbuf_size2[87]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[466] param='dynamic_power_sb_mux[0][1]_rrnode[466]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[466] avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='start_rise_sb_mux[0][1]_rrnode[466]' to='start_rise_sb_mux[0][1]_rrnode[466]+switch_rise_sb_mux[0][1]_rrnode[466]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[466] avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='start_fall_sb_mux[0][1]_rrnode[466]' to='start_fall_sb_mux[0][1]_rrnode[466]+switch_fall_sb_mux[0][1]_rrnode[466]' -.meas tran sum_leakage_power_mux[0to87] -+ param='sum_leakage_power_mux[0to86]+leakage_sb_mux[0][1]_rrnode[466]' -.meas tran sum_energy_per_cycle_mux[0to87] -+ param='sum_energy_per_cycle_mux[0to86]+energy_per_cycle_sb_mux[0][1]_rrnode[466]' -***** Load for rr_node[466] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=75, type=5 ***** -Xchan_mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[338]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to87] -+ param='sum_leakage_power_sb_mux[0to86]+leakage_sb_mux[0][1]_rrnode[466]' -.meas tran sum_energy_per_cycle_sb_mux[0to87] -+ param='sum_energy_per_cycle_sb_mux[0to86]+energy_per_cycle_sb_mux[0][1]_rrnode[466]' -Xmux_1level_tapbuf_size2[88] mux_1level_tapbuf_size2[88]->in[0] mux_1level_tapbuf_size2[88]->in[1] mux_1level_tapbuf_size2[88]->out sram[98]->outb sram[98]->out gvdd_mux_1level_tapbuf_size2[88] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[88], level=1, select_path_id=0. ***** -*****1***** -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -***** Signal mux_1level_tapbuf_size2[88]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[88]->in[0] mux_1level_tapbuf_size2[88]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[88]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[88]->in[1] mux_1level_tapbuf_size2[88]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[88] gvdd_mux_1level_tapbuf_size2[88] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[468] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[468] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[468] when v(mux_1level_tapbuf_size2[88]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[468] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[468] when v(mux_1level_tapbuf_size2[88]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[468] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[88]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[468] param='mux_1level_tapbuf_size2[88]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[88]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[88]_energy_per_cycle param='mux_1level_tapbuf_size2[88]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[468] param='mux_1level_tapbuf_size2[88]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[468] param='dynamic_power_sb_mux[0][1]_rrnode[468]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[468] avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='start_rise_sb_mux[0][1]_rrnode[468]' to='start_rise_sb_mux[0][1]_rrnode[468]+switch_rise_sb_mux[0][1]_rrnode[468]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[468] avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='start_fall_sb_mux[0][1]_rrnode[468]' to='start_fall_sb_mux[0][1]_rrnode[468]+switch_fall_sb_mux[0][1]_rrnode[468]' -.meas tran sum_leakage_power_mux[0to88] -+ param='sum_leakage_power_mux[0to87]+leakage_sb_mux[0][1]_rrnode[468]' -.meas tran sum_energy_per_cycle_mux[0to88] -+ param='sum_energy_per_cycle_mux[0to87]+energy_per_cycle_sb_mux[0][1]_rrnode[468]' -***** Load for rr_node[468] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=77, type=5 ***** -Xchan_mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[342]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to88] -+ param='sum_leakage_power_sb_mux[0to87]+leakage_sb_mux[0][1]_rrnode[468]' -.meas tran sum_energy_per_cycle_sb_mux[0to88] -+ param='sum_energy_per_cycle_sb_mux[0to87]+energy_per_cycle_sb_mux[0][1]_rrnode[468]' -Xmux_1level_tapbuf_size2[89] mux_1level_tapbuf_size2[89]->in[0] mux_1level_tapbuf_size2[89]->in[1] mux_1level_tapbuf_size2[89]->out sram[99]->outb sram[99]->out gvdd_mux_1level_tapbuf_size2[89] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[89], level=1, select_path_id=0. ***** -*****1***** -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -***** Signal mux_1level_tapbuf_size2[89]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[89]->in[0] mux_1level_tapbuf_size2[89]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[89]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[89]->in[1] mux_1level_tapbuf_size2[89]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[89] gvdd_mux_1level_tapbuf_size2[89] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[470] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[470] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[470] when v(mux_1level_tapbuf_size2[89]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[470] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[470] when v(mux_1level_tapbuf_size2[89]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[470] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[89]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[470] param='mux_1level_tapbuf_size2[89]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[89]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[89]_energy_per_cycle param='mux_1level_tapbuf_size2[89]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[470] param='mux_1level_tapbuf_size2[89]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[470] param='dynamic_power_sb_mux[0][1]_rrnode[470]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[470] avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='start_rise_sb_mux[0][1]_rrnode[470]' to='start_rise_sb_mux[0][1]_rrnode[470]+switch_rise_sb_mux[0][1]_rrnode[470]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[470] avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='start_fall_sb_mux[0][1]_rrnode[470]' to='start_fall_sb_mux[0][1]_rrnode[470]+switch_fall_sb_mux[0][1]_rrnode[470]' -.meas tran sum_leakage_power_mux[0to89] -+ param='sum_leakage_power_mux[0to88]+leakage_sb_mux[0][1]_rrnode[470]' -.meas tran sum_energy_per_cycle_mux[0to89] -+ param='sum_energy_per_cycle_mux[0to88]+energy_per_cycle_sb_mux[0][1]_rrnode[470]' -***** Load for rr_node[470] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=79, type=5 ***** -Xchan_mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[345]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to89] -+ param='sum_leakage_power_sb_mux[0to88]+leakage_sb_mux[0][1]_rrnode[470]' -.meas tran sum_energy_per_cycle_sb_mux[0to89] -+ param='sum_energy_per_cycle_sb_mux[0to88]+energy_per_cycle_sb_mux[0][1]_rrnode[470]' -Xmux_1level_tapbuf_size2[90] mux_1level_tapbuf_size2[90]->in[0] mux_1level_tapbuf_size2[90]->in[1] mux_1level_tapbuf_size2[90]->out sram[100]->outb sram[100]->out gvdd_mux_1level_tapbuf_size2[90] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[90], level=1, select_path_id=0. ***** -*****1***** -Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[100]->out) 0 -.nodeset V(sram[100]->outb) vsp -***** Signal mux_1level_tapbuf_size2[90]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[90]->in[0] mux_1level_tapbuf_size2[90]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[90]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[90]->in[1] mux_1level_tapbuf_size2[90]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[90] gvdd_mux_1level_tapbuf_size2[90] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[472] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[472] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[472] when v(mux_1level_tapbuf_size2[90]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[472] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[472] when v(mux_1level_tapbuf_size2[90]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[472] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[90]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[472] param='mux_1level_tapbuf_size2[90]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[90]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[90]_energy_per_cycle param='mux_1level_tapbuf_size2[90]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[472] param='mux_1level_tapbuf_size2[90]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[472] param='dynamic_power_sb_mux[0][1]_rrnode[472]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[472] avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='start_rise_sb_mux[0][1]_rrnode[472]' to='start_rise_sb_mux[0][1]_rrnode[472]+switch_rise_sb_mux[0][1]_rrnode[472]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[472] avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='start_fall_sb_mux[0][1]_rrnode[472]' to='start_fall_sb_mux[0][1]_rrnode[472]+switch_fall_sb_mux[0][1]_rrnode[472]' -.meas tran sum_leakage_power_mux[0to90] -+ param='sum_leakage_power_mux[0to89]+leakage_sb_mux[0][1]_rrnode[472]' -.meas tran sum_energy_per_cycle_mux[0to90] -+ param='sum_energy_per_cycle_mux[0to89]+energy_per_cycle_sb_mux[0][1]_rrnode[472]' -***** Load for rr_node[472] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=81, type=5 ***** -Xchan_mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[349]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to90] -+ param='sum_leakage_power_sb_mux[0to89]+leakage_sb_mux[0][1]_rrnode[472]' -.meas tran sum_energy_per_cycle_sb_mux[0to90] -+ param='sum_energy_per_cycle_sb_mux[0to89]+energy_per_cycle_sb_mux[0][1]_rrnode[472]' -Xmux_1level_tapbuf_size2[91] mux_1level_tapbuf_size2[91]->in[0] mux_1level_tapbuf_size2[91]->in[1] mux_1level_tapbuf_size2[91]->out sram[101]->outb sram[101]->out gvdd_mux_1level_tapbuf_size2[91] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[91], level=1, select_path_id=0. ***** -*****1***** -Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[101]->out) 0 -.nodeset V(sram[101]->outb) vsp -***** Signal mux_1level_tapbuf_size2[91]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[91]->in[0] mux_1level_tapbuf_size2[91]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[91]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[91]->in[1] mux_1level_tapbuf_size2[91]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[91] gvdd_mux_1level_tapbuf_size2[91] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[474] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[474] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[474] when v(mux_1level_tapbuf_size2[91]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[474] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[474] when v(mux_1level_tapbuf_size2[91]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[474] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[91]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[474] param='mux_1level_tapbuf_size2[91]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[91]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[91]_energy_per_cycle param='mux_1level_tapbuf_size2[91]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[474] param='mux_1level_tapbuf_size2[91]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[474] param='dynamic_power_sb_mux[0][1]_rrnode[474]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[474] avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='start_rise_sb_mux[0][1]_rrnode[474]' to='start_rise_sb_mux[0][1]_rrnode[474]+switch_rise_sb_mux[0][1]_rrnode[474]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[474] avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='start_fall_sb_mux[0][1]_rrnode[474]' to='start_fall_sb_mux[0][1]_rrnode[474]+switch_fall_sb_mux[0][1]_rrnode[474]' -.meas tran sum_leakage_power_mux[0to91] -+ param='sum_leakage_power_mux[0to90]+leakage_sb_mux[0][1]_rrnode[474]' -.meas tran sum_energy_per_cycle_mux[0to91] -+ param='sum_energy_per_cycle_mux[0to90]+energy_per_cycle_sb_mux[0][1]_rrnode[474]' -***** Load for rr_node[474] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=83, type=5 ***** -Xchan_mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[353]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to91] -+ param='sum_leakage_power_sb_mux[0to90]+leakage_sb_mux[0][1]_rrnode[474]' -.meas tran sum_energy_per_cycle_sb_mux[0to91] -+ param='sum_energy_per_cycle_sb_mux[0to90]+energy_per_cycle_sb_mux[0][1]_rrnode[474]' -Xmux_1level_tapbuf_size2[92] mux_1level_tapbuf_size2[92]->in[0] mux_1level_tapbuf_size2[92]->in[1] mux_1level_tapbuf_size2[92]->out sram[102]->outb sram[102]->out gvdd_mux_1level_tapbuf_size2[92] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[92], level=1, select_path_id=0. ***** -*****1***** -Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[102]->out) 0 -.nodeset V(sram[102]->outb) vsp -***** Signal mux_1level_tapbuf_size2[92]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[92]->in[0] mux_1level_tapbuf_size2[92]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[92]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[92]->in[1] mux_1level_tapbuf_size2[92]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[92] gvdd_mux_1level_tapbuf_size2[92] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[476] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[476] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[476] when v(mux_1level_tapbuf_size2[92]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[476] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[476] when v(mux_1level_tapbuf_size2[92]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[476] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[92]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[476] param='mux_1level_tapbuf_size2[92]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[92]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[92]_energy_per_cycle param='mux_1level_tapbuf_size2[92]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[476] param='mux_1level_tapbuf_size2[92]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[476] param='dynamic_power_sb_mux[0][1]_rrnode[476]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[476] avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='start_rise_sb_mux[0][1]_rrnode[476]' to='start_rise_sb_mux[0][1]_rrnode[476]+switch_rise_sb_mux[0][1]_rrnode[476]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[476] avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='start_fall_sb_mux[0][1]_rrnode[476]' to='start_fall_sb_mux[0][1]_rrnode[476]+switch_fall_sb_mux[0][1]_rrnode[476]' -.meas tran sum_leakage_power_mux[0to92] -+ param='sum_leakage_power_mux[0to91]+leakage_sb_mux[0][1]_rrnode[476]' -.meas tran sum_energy_per_cycle_mux[0to92] -+ param='sum_energy_per_cycle_mux[0to91]+energy_per_cycle_sb_mux[0][1]_rrnode[476]' -***** Load for rr_node[476] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=85, type=5 ***** -Xchan_mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[357]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[360]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to92] -+ param='sum_leakage_power_sb_mux[0to91]+leakage_sb_mux[0][1]_rrnode[476]' -.meas tran sum_energy_per_cycle_sb_mux[0to92] -+ param='sum_energy_per_cycle_sb_mux[0to91]+energy_per_cycle_sb_mux[0][1]_rrnode[476]' -Xmux_1level_tapbuf_size2[93] mux_1level_tapbuf_size2[93]->in[0] mux_1level_tapbuf_size2[93]->in[1] mux_1level_tapbuf_size2[93]->out sram[103]->outb sram[103]->out gvdd_mux_1level_tapbuf_size2[93] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[93], level=1, select_path_id=0. ***** -*****1***** -Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[103]->out) 0 -.nodeset V(sram[103]->outb) vsp -***** Signal mux_1level_tapbuf_size2[93]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[93]->in[0] mux_1level_tapbuf_size2[93]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[93]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[93]->in[1] mux_1level_tapbuf_size2[93]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[93] gvdd_mux_1level_tapbuf_size2[93] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[478] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[478] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[478] when v(mux_1level_tapbuf_size2[93]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[478] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[478] when v(mux_1level_tapbuf_size2[93]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[478] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[93]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[478] param='mux_1level_tapbuf_size2[93]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[93]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[93]_energy_per_cycle param='mux_1level_tapbuf_size2[93]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[478] param='mux_1level_tapbuf_size2[93]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[478] param='dynamic_power_sb_mux[0][1]_rrnode[478]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[478] avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='start_rise_sb_mux[0][1]_rrnode[478]' to='start_rise_sb_mux[0][1]_rrnode[478]+switch_rise_sb_mux[0][1]_rrnode[478]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[478] avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='start_fall_sb_mux[0][1]_rrnode[478]' to='start_fall_sb_mux[0][1]_rrnode[478]+switch_fall_sb_mux[0][1]_rrnode[478]' -.meas tran sum_leakage_power_mux[0to93] -+ param='sum_leakage_power_mux[0to92]+leakage_sb_mux[0][1]_rrnode[478]' -.meas tran sum_energy_per_cycle_mux[0to93] -+ param='sum_energy_per_cycle_mux[0to92]+energy_per_cycle_sb_mux[0][1]_rrnode[478]' -***** Load for rr_node[478] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=87, type=5 ***** -Xchan_mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[361]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to93] -+ param='sum_leakage_power_sb_mux[0to92]+leakage_sb_mux[0][1]_rrnode[478]' -.meas tran sum_energy_per_cycle_sb_mux[0to93] -+ param='sum_energy_per_cycle_sb_mux[0to92]+energy_per_cycle_sb_mux[0][1]_rrnode[478]' -Xmux_1level_tapbuf_size2[94] mux_1level_tapbuf_size2[94]->in[0] mux_1level_tapbuf_size2[94]->in[1] mux_1level_tapbuf_size2[94]->out sram[104]->outb sram[104]->out gvdd_mux_1level_tapbuf_size2[94] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[94], level=1, select_path_id=0. ***** -*****1***** -Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[104]->out) 0 -.nodeset V(sram[104]->outb) vsp -***** Signal mux_1level_tapbuf_size2[94]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[94]->in[0] mux_1level_tapbuf_size2[94]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[94]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[94]->in[1] mux_1level_tapbuf_size2[94]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[94] gvdd_mux_1level_tapbuf_size2[94] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[480] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[480] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[480] when v(mux_1level_tapbuf_size2[94]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[480] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[480] when v(mux_1level_tapbuf_size2[94]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[480] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[94]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[480] param='mux_1level_tapbuf_size2[94]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[94]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[94]_energy_per_cycle param='mux_1level_tapbuf_size2[94]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[480] param='mux_1level_tapbuf_size2[94]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[480] param='dynamic_power_sb_mux[0][1]_rrnode[480]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[480] avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='start_rise_sb_mux[0][1]_rrnode[480]' to='start_rise_sb_mux[0][1]_rrnode[480]+switch_rise_sb_mux[0][1]_rrnode[480]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[480] avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='start_fall_sb_mux[0][1]_rrnode[480]' to='start_fall_sb_mux[0][1]_rrnode[480]+switch_fall_sb_mux[0][1]_rrnode[480]' -.meas tran sum_leakage_power_mux[0to94] -+ param='sum_leakage_power_mux[0to93]+leakage_sb_mux[0][1]_rrnode[480]' -.meas tran sum_energy_per_cycle_mux[0to94] -+ param='sum_energy_per_cycle_mux[0to93]+energy_per_cycle_sb_mux[0][1]_rrnode[480]' -***** Load for rr_node[480] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=89, type=5 ***** -Xchan_mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[365]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to94] -+ param='sum_leakage_power_sb_mux[0to93]+leakage_sb_mux[0][1]_rrnode[480]' -.meas tran sum_energy_per_cycle_sb_mux[0to94] -+ param='sum_energy_per_cycle_sb_mux[0to93]+energy_per_cycle_sb_mux[0][1]_rrnode[480]' -Xmux_1level_tapbuf_size2[95] mux_1level_tapbuf_size2[95]->in[0] mux_1level_tapbuf_size2[95]->in[1] mux_1level_tapbuf_size2[95]->out sram[105]->outb sram[105]->out gvdd_mux_1level_tapbuf_size2[95] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[95], level=1, select_path_id=0. ***** -*****1***** -Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[105]->out) 0 -.nodeset V(sram[105]->outb) vsp -***** Signal mux_1level_tapbuf_size2[95]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[95]->in[0] mux_1level_tapbuf_size2[95]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[95]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[95]->in[1] mux_1level_tapbuf_size2[95]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[95] gvdd_mux_1level_tapbuf_size2[95] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[482] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[482] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[482] when v(mux_1level_tapbuf_size2[95]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[482] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[482] when v(mux_1level_tapbuf_size2[95]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[482] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[95]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[482] param='mux_1level_tapbuf_size2[95]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[95]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[95]_energy_per_cycle param='mux_1level_tapbuf_size2[95]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[482] param='mux_1level_tapbuf_size2[95]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[482] param='dynamic_power_sb_mux[0][1]_rrnode[482]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[482] avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='start_rise_sb_mux[0][1]_rrnode[482]' to='start_rise_sb_mux[0][1]_rrnode[482]+switch_rise_sb_mux[0][1]_rrnode[482]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[482] avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='start_fall_sb_mux[0][1]_rrnode[482]' to='start_fall_sb_mux[0][1]_rrnode[482]+switch_fall_sb_mux[0][1]_rrnode[482]' -.meas tran sum_leakage_power_mux[0to95] -+ param='sum_leakage_power_mux[0to94]+leakage_sb_mux[0][1]_rrnode[482]' -.meas tran sum_energy_per_cycle_mux[0to95] -+ param='sum_energy_per_cycle_mux[0to94]+energy_per_cycle_sb_mux[0][1]_rrnode[482]' -***** Load for rr_node[482] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=91, type=5 ***** -Xchan_mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[369]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to95] -+ param='sum_leakage_power_sb_mux[0to94]+leakage_sb_mux[0][1]_rrnode[482]' -.meas tran sum_energy_per_cycle_sb_mux[0to95] -+ param='sum_energy_per_cycle_sb_mux[0to94]+energy_per_cycle_sb_mux[0][1]_rrnode[482]' -Xmux_1level_tapbuf_size2[96] mux_1level_tapbuf_size2[96]->in[0] mux_1level_tapbuf_size2[96]->in[1] mux_1level_tapbuf_size2[96]->out sram[106]->outb sram[106]->out gvdd_mux_1level_tapbuf_size2[96] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[96], level=1, select_path_id=0. ***** -*****1***** -Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[106]->out) 0 -.nodeset V(sram[106]->outb) vsp -***** Signal mux_1level_tapbuf_size2[96]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[96]->in[0] mux_1level_tapbuf_size2[96]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[96]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[96]->in[1] mux_1level_tapbuf_size2[96]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[96] gvdd_mux_1level_tapbuf_size2[96] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[484] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[484] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[484] when v(mux_1level_tapbuf_size2[96]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[484] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[484] when v(mux_1level_tapbuf_size2[96]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[484] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[96]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[484] param='mux_1level_tapbuf_size2[96]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[96]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[96]_energy_per_cycle param='mux_1level_tapbuf_size2[96]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[484] param='mux_1level_tapbuf_size2[96]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[484] param='dynamic_power_sb_mux[0][1]_rrnode[484]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[484] avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='start_rise_sb_mux[0][1]_rrnode[484]' to='start_rise_sb_mux[0][1]_rrnode[484]+switch_rise_sb_mux[0][1]_rrnode[484]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[484] avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='start_fall_sb_mux[0][1]_rrnode[484]' to='start_fall_sb_mux[0][1]_rrnode[484]+switch_fall_sb_mux[0][1]_rrnode[484]' -.meas tran sum_leakage_power_mux[0to96] -+ param='sum_leakage_power_mux[0to95]+leakage_sb_mux[0][1]_rrnode[484]' -.meas tran sum_energy_per_cycle_mux[0to96] -+ param='sum_energy_per_cycle_mux[0to95]+energy_per_cycle_sb_mux[0][1]_rrnode[484]' -***** Load for rr_node[484] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=93, type=5 ***** -Xchan_mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[372]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to96] -+ param='sum_leakage_power_sb_mux[0to95]+leakage_sb_mux[0][1]_rrnode[484]' -.meas tran sum_energy_per_cycle_sb_mux[0to96] -+ param='sum_energy_per_cycle_sb_mux[0to95]+energy_per_cycle_sb_mux[0][1]_rrnode[484]' -Xmux_1level_tapbuf_size2[97] mux_1level_tapbuf_size2[97]->in[0] mux_1level_tapbuf_size2[97]->in[1] mux_1level_tapbuf_size2[97]->out sram[107]->outb sram[107]->out gvdd_mux_1level_tapbuf_size2[97] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[97], level=1, select_path_id=0. ***** -*****1***** -Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[107]->out) 0 -.nodeset V(sram[107]->outb) vsp -***** Signal mux_1level_tapbuf_size2[97]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[97]->in[0] mux_1level_tapbuf_size2[97]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[97]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[97]->in[1] mux_1level_tapbuf_size2[97]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[97] gvdd_mux_1level_tapbuf_size2[97] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[486] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[486] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[486] when v(mux_1level_tapbuf_size2[97]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[486] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[486] when v(mux_1level_tapbuf_size2[97]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[486] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[97]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[486] param='mux_1level_tapbuf_size2[97]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[97]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[97]_energy_per_cycle param='mux_1level_tapbuf_size2[97]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[486] param='mux_1level_tapbuf_size2[97]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[486] param='dynamic_power_sb_mux[0][1]_rrnode[486]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[486] avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='start_rise_sb_mux[0][1]_rrnode[486]' to='start_rise_sb_mux[0][1]_rrnode[486]+switch_rise_sb_mux[0][1]_rrnode[486]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[486] avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='start_fall_sb_mux[0][1]_rrnode[486]' to='start_fall_sb_mux[0][1]_rrnode[486]+switch_fall_sb_mux[0][1]_rrnode[486]' -.meas tran sum_leakage_power_mux[0to97] -+ param='sum_leakage_power_mux[0to96]+leakage_sb_mux[0][1]_rrnode[486]' -.meas tran sum_energy_per_cycle_mux[0to97] -+ param='sum_energy_per_cycle_mux[0to96]+energy_per_cycle_sb_mux[0][1]_rrnode[486]' -***** Load for rr_node[486] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=95, type=5 ***** -Xchan_mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[376]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to97] -+ param='sum_leakage_power_sb_mux[0to96]+leakage_sb_mux[0][1]_rrnode[486]' -.meas tran sum_energy_per_cycle_sb_mux[0to97] -+ param='sum_energy_per_cycle_sb_mux[0to96]+energy_per_cycle_sb_mux[0][1]_rrnode[486]' -Xmux_1level_tapbuf_size2[98] mux_1level_tapbuf_size2[98]->in[0] mux_1level_tapbuf_size2[98]->in[1] mux_1level_tapbuf_size2[98]->out sram[108]->outb sram[108]->out gvdd_mux_1level_tapbuf_size2[98] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[98], level=1, select_path_id=0. ***** -*****1***** -Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[108]->out) 0 -.nodeset V(sram[108]->outb) vsp -***** Signal mux_1level_tapbuf_size2[98]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[98]->in[0] mux_1level_tapbuf_size2[98]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[98]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[98]->in[1] mux_1level_tapbuf_size2[98]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[98] gvdd_mux_1level_tapbuf_size2[98] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[488] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[488] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[488] when v(mux_1level_tapbuf_size2[98]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[488] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[488] when v(mux_1level_tapbuf_size2[98]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[488] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[98]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[488] param='mux_1level_tapbuf_size2[98]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[98]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[98]_energy_per_cycle param='mux_1level_tapbuf_size2[98]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[488] param='mux_1level_tapbuf_size2[98]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[488] param='dynamic_power_sb_mux[0][1]_rrnode[488]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[488] avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='start_rise_sb_mux[0][1]_rrnode[488]' to='start_rise_sb_mux[0][1]_rrnode[488]+switch_rise_sb_mux[0][1]_rrnode[488]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[488] avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='start_fall_sb_mux[0][1]_rrnode[488]' to='start_fall_sb_mux[0][1]_rrnode[488]+switch_fall_sb_mux[0][1]_rrnode[488]' -.meas tran sum_leakage_power_mux[0to98] -+ param='sum_leakage_power_mux[0to97]+leakage_sb_mux[0][1]_rrnode[488]' -.meas tran sum_energy_per_cycle_mux[0to98] -+ param='sum_energy_per_cycle_mux[0to97]+energy_per_cycle_sb_mux[0][1]_rrnode[488]' -***** Load for rr_node[488] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=97, type=5 ***** -Xchan_mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[381]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to98] -+ param='sum_leakage_power_sb_mux[0to97]+leakage_sb_mux[0][1]_rrnode[488]' -.meas tran sum_energy_per_cycle_sb_mux[0to98] -+ param='sum_energy_per_cycle_sb_mux[0to97]+energy_per_cycle_sb_mux[0][1]_rrnode[488]' -Xmux_1level_tapbuf_size2[99] mux_1level_tapbuf_size2[99]->in[0] mux_1level_tapbuf_size2[99]->in[1] mux_1level_tapbuf_size2[99]->out sram[109]->outb sram[109]->out gvdd_mux_1level_tapbuf_size2[99] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[99], level=1, select_path_id=0. ***** -*****1***** -Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[109]->out) 0 -.nodeset V(sram[109]->outb) vsp -***** Signal mux_1level_tapbuf_size2[99]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[99]->in[0] mux_1level_tapbuf_size2[99]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[99]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[99]->in[1] mux_1level_tapbuf_size2[99]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[99] gvdd_mux_1level_tapbuf_size2[99] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[0][1]_rrnode[490] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[0][1]_rrnode[490] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[0][1]_rrnode[490] when v(mux_1level_tapbuf_size2[99]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[0][1]_rrnode[490] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[0][1]_rrnode[490] when v(mux_1level_tapbuf_size2[99]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[0][1]_rrnode[490] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[99]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from=0 to='clock_period' -.meas tran leakage_sb_mux[0][1]_rrnode[490] param='mux_1level_tapbuf_size2[99]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[99]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[99]_energy_per_cycle param='mux_1level_tapbuf_size2[99]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[0][1]_rrnode[490] param='mux_1level_tapbuf_size2[99]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[0][1]_rrnode[490] param='dynamic_power_sb_mux[0][1]_rrnode[490]*clock_period' -.meas tran dynamic_rise_sb_mux[0][1]_rrnode[490] avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='start_rise_sb_mux[0][1]_rrnode[490]' to='start_rise_sb_mux[0][1]_rrnode[490]+switch_rise_sb_mux[0][1]_rrnode[490]' -.meas tran dynamic_fall_sb_mux[0][1]_rrnode[490] avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='start_fall_sb_mux[0][1]_rrnode[490]' to='start_fall_sb_mux[0][1]_rrnode[490]+switch_fall_sb_mux[0][1]_rrnode[490]' -.meas tran sum_leakage_power_mux[0to99] -+ param='sum_leakage_power_mux[0to98]+leakage_sb_mux[0][1]_rrnode[490]' -.meas tran sum_energy_per_cycle_mux[0to99] -+ param='sum_energy_per_cycle_mux[0to98]+energy_per_cycle_sb_mux[0][1]_rrnode[490]' -***** Load for rr_node[490] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=99, type=5 ***** -Xchan_mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[384]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to99] -+ param='sum_leakage_power_sb_mux[0to98]+leakage_sb_mux[0][1]_rrnode[490]' -.meas tran sum_energy_per_cycle_sb_mux[0to99] -+ param='sum_energy_per_cycle_sb_mux[0to98]+energy_per_cycle_sb_mux[0][1]_rrnode[490]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='6*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to99] -+ param='sum_leakage_power_mux[0to99]' -.meas tran total_energy_per_cycle_mux[0to99] -+ param='sum_energy_per_cycle_mux[0to99]' -.meas tran total_leakage_power_sb_mux -+ param='sum_leakage_power_sb_mux[0to99]' -.meas tran total_energy_per_cycle_sb_mux -+ param='sum_energy_per_cycle_sb_mux[0to99]' -.end diff --git a/examples/spice_test_example_2/sb_mux_tb/example_2_sb1_0_sbmux_testbench.sp b/examples/spice_test_example_2/sb_mux_tb/example_2_sb1_0_sbmux_testbench.sp deleted file mode 100644 index f6df0c3fe..000000000 --- a/examples/spice_test_example_2/sb_mux_tb/example_2_sb1_0_sbmux_testbench.sp +++ /dev/null @@ -1,5409 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_1level_tapbuf_size3[0] mux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb gvdd_mux_1level_tapbuf_size3[0] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[0], level=1, select_path_id=0. ***** -*****100***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -***** Signal mux_1level_tapbuf_size3[0]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[0] gvdd_mux_1level_tapbuf_size3[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[491] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[491] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[491] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[491] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[491] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[491] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[491] param='mux_1level_tapbuf_size3[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[0]_energy_per_cycle param='mux_1level_tapbuf_size3[0]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[491] param='mux_1level_tapbuf_size3[0]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[491] param='dynamic_power_sb_mux[1][0]_rrnode[491]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[491] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_rise_sb_mux[1][0]_rrnode[491]' to='start_rise_sb_mux[1][0]_rrnode[491]+switch_rise_sb_mux[1][0]_rrnode[491]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[491] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_fall_sb_mux[1][0]_rrnode[491]' to='start_fall_sb_mux[1][0]_rrnode[491]+switch_fall_sb_mux[1][0]_rrnode[491]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_sb_mux[1][0]_rrnode[491]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_sb_mux[1][0]_rrnode[491]' -***** Load for rr_node[491] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=0, type=5 ***** -Xchan_mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to0] -+ param='leakage_sb_mux[1][0]_rrnode[491]' -.meas tran sum_energy_per_cycle_sb_mux[0to0] -+ param='energy_per_cycle_sb_mux[1][0]_rrnode[491]' -Xmux_1level_tapbuf_size3[1] mux_1level_tapbuf_size3[1]->in[0] mux_1level_tapbuf_size3[1]->in[1] mux_1level_tapbuf_size3[1]->in[2] mux_1level_tapbuf_size3[1]->out sram[3]->outb sram[3]->out sram[4]->out sram[4]->outb sram[5]->out sram[5]->outb gvdd_mux_1level_tapbuf_size3[1] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[1], level=1, select_path_id=0. ***** -*****100***** -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -***** Signal mux_1level_tapbuf_size3[1]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[0] mux_1level_tapbuf_size3[1]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[1]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[1] mux_1level_tapbuf_size3[1]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[1]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[2] mux_1level_tapbuf_size3[1]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[1] gvdd_mux_1level_tapbuf_size3[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[493] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[493] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[493] when v(mux_1level_tapbuf_size3[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[493] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[493] when v(mux_1level_tapbuf_size3[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[493] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[1]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[493] param='mux_1level_tapbuf_size3[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[1]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[1]_energy_per_cycle param='mux_1level_tapbuf_size3[1]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[493] param='mux_1level_tapbuf_size3[1]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[493] param='dynamic_power_sb_mux[1][0]_rrnode[493]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[493] avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='start_rise_sb_mux[1][0]_rrnode[493]' to='start_rise_sb_mux[1][0]_rrnode[493]+switch_rise_sb_mux[1][0]_rrnode[493]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[493] avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='start_fall_sb_mux[1][0]_rrnode[493]' to='start_fall_sb_mux[1][0]_rrnode[493]+switch_fall_sb_mux[1][0]_rrnode[493]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_sb_mux[1][0]_rrnode[493]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_sb_mux[1][0]_rrnode[493]' -***** Load for rr_node[493] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=2, type=5 ***** -Xchan_mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to1] -+ param='sum_leakage_power_sb_mux[0to0]+leakage_sb_mux[1][0]_rrnode[493]' -.meas tran sum_energy_per_cycle_sb_mux[0to1] -+ param='sum_energy_per_cycle_sb_mux[0to0]+energy_per_cycle_sb_mux[1][0]_rrnode[493]' -Xmux_1level_tapbuf_size3[2] mux_1level_tapbuf_size3[2]->in[0] mux_1level_tapbuf_size3[2]->in[1] mux_1level_tapbuf_size3[2]->in[2] mux_1level_tapbuf_size3[2]->out sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb sram[8]->out sram[8]->outb gvdd_mux_1level_tapbuf_size3[2] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[2], level=1, select_path_id=0. ***** -*****100***** -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -***** Signal mux_1level_tapbuf_size3[2]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[0] mux_1level_tapbuf_size3[2]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[2]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[1] mux_1level_tapbuf_size3[2]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[2]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[2] mux_1level_tapbuf_size3[2]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[2] gvdd_mux_1level_tapbuf_size3[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[495] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[495] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[495] when v(mux_1level_tapbuf_size3[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[495] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[495] when v(mux_1level_tapbuf_size3[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[495] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[2]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[495] param='mux_1level_tapbuf_size3[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[2]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[2]_energy_per_cycle param='mux_1level_tapbuf_size3[2]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[495] param='mux_1level_tapbuf_size3[2]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[495] param='dynamic_power_sb_mux[1][0]_rrnode[495]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[495] avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='start_rise_sb_mux[1][0]_rrnode[495]' to='start_rise_sb_mux[1][0]_rrnode[495]+switch_rise_sb_mux[1][0]_rrnode[495]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[495] avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='start_fall_sb_mux[1][0]_rrnode[495]' to='start_fall_sb_mux[1][0]_rrnode[495]+switch_fall_sb_mux[1][0]_rrnode[495]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_sb_mux[1][0]_rrnode[495]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_sb_mux[1][0]_rrnode[495]' -***** Load for rr_node[495] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=4, type=5 ***** -Xchan_mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[5]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to2] -+ param='sum_leakage_power_sb_mux[0to1]+leakage_sb_mux[1][0]_rrnode[495]' -.meas tran sum_energy_per_cycle_sb_mux[0to2] -+ param='sum_energy_per_cycle_sb_mux[0to1]+energy_per_cycle_sb_mux[1][0]_rrnode[495]' -Xmux_1level_tapbuf_size3[3] mux_1level_tapbuf_size3[3]->in[0] mux_1level_tapbuf_size3[3]->in[1] mux_1level_tapbuf_size3[3]->in[2] mux_1level_tapbuf_size3[3]->out sram[9]->outb sram[9]->out sram[10]->out sram[10]->outb sram[11]->out sram[11]->outb gvdd_mux_1level_tapbuf_size3[3] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[3], level=1, select_path_id=0. ***** -*****100***** -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_1level_tapbuf_size3[3]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[3]->in[0] mux_1level_tapbuf_size3[3]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[3]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[3]->in[1] mux_1level_tapbuf_size3[3]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[3]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[3]->in[2] mux_1level_tapbuf_size3[3]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[3] gvdd_mux_1level_tapbuf_size3[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[497] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[497] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[497] when v(mux_1level_tapbuf_size3[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[497] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[497] when v(mux_1level_tapbuf_size3[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[497] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[3]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[497] param='mux_1level_tapbuf_size3[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[3]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[3]_energy_per_cycle param='mux_1level_tapbuf_size3[3]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[497] param='mux_1level_tapbuf_size3[3]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[497] param='dynamic_power_sb_mux[1][0]_rrnode[497]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[497] avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from='start_rise_sb_mux[1][0]_rrnode[497]' to='start_rise_sb_mux[1][0]_rrnode[497]+switch_rise_sb_mux[1][0]_rrnode[497]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[497] avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from='start_fall_sb_mux[1][0]_rrnode[497]' to='start_fall_sb_mux[1][0]_rrnode[497]+switch_fall_sb_mux[1][0]_rrnode[497]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_sb_mux[1][0]_rrnode[497]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_sb_mux[1][0]_rrnode[497]' -***** Load for rr_node[497] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=6, type=5 ***** -Xchan_mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out mux_1level_tapbuf_size3[3]->out mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[8]_no0 mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to3] -+ param='sum_leakage_power_sb_mux[0to2]+leakage_sb_mux[1][0]_rrnode[497]' -.meas tran sum_energy_per_cycle_sb_mux[0to3] -+ param='sum_energy_per_cycle_sb_mux[0to2]+energy_per_cycle_sb_mux[1][0]_rrnode[497]' -Xmux_1level_tapbuf_size3[4] mux_1level_tapbuf_size3[4]->in[0] mux_1level_tapbuf_size3[4]->in[1] mux_1level_tapbuf_size3[4]->in[2] mux_1level_tapbuf_size3[4]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->out sram[14]->outb gvdd_mux_1level_tapbuf_size3[4] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****100***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -***** Signal mux_1level_tapbuf_size3[4]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[4]->in[0] mux_1level_tapbuf_size3[4]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[4]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[4]->in[1] mux_1level_tapbuf_size3[4]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[4]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[4]->in[2] mux_1level_tapbuf_size3[4]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[4] gvdd_mux_1level_tapbuf_size3[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[499] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[499] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[499] when v(mux_1level_tapbuf_size3[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[499] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[499] when v(mux_1level_tapbuf_size3[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[499] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[4]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[499] param='mux_1level_tapbuf_size3[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[4]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[4]_energy_per_cycle param='mux_1level_tapbuf_size3[4]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[499] param='mux_1level_tapbuf_size3[4]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[499] param='dynamic_power_sb_mux[1][0]_rrnode[499]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[499] avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from='start_rise_sb_mux[1][0]_rrnode[499]' to='start_rise_sb_mux[1][0]_rrnode[499]+switch_rise_sb_mux[1][0]_rrnode[499]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[499] avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from='start_fall_sb_mux[1][0]_rrnode[499]' to='start_fall_sb_mux[1][0]_rrnode[499]+switch_fall_sb_mux[1][0]_rrnode[499]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_sb_mux[1][0]_rrnode[499]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_sb_mux[1][0]_rrnode[499]' -***** Load for rr_node[499] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=8, type=5 ***** -Xchan_mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out mux_1level_tapbuf_size3[4]->out mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[11]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to4] -+ param='sum_leakage_power_sb_mux[0to3]+leakage_sb_mux[1][0]_rrnode[499]' -.meas tran sum_energy_per_cycle_sb_mux[0to4] -+ param='sum_energy_per_cycle_sb_mux[0to3]+energy_per_cycle_sb_mux[1][0]_rrnode[499]' -Xmux_1level_tapbuf_size2[5] mux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->out sram[15]->outb sram[15]->out gvdd_mux_1level_tapbuf_size2[5] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[5], level=1, select_path_id=0. ***** -*****1***** -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_1level_tapbuf_size2[5]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[5]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[5] gvdd_mux_1level_tapbuf_size2[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[501] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[501] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[501] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[501] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[501] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[501] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[501] param='mux_1level_tapbuf_size2[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[5]_energy_per_cycle param='mux_1level_tapbuf_size2[5]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[501] param='mux_1level_tapbuf_size2[5]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[501] param='dynamic_power_sb_mux[1][0]_rrnode[501]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[501] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_rise_sb_mux[1][0]_rrnode[501]' to='start_rise_sb_mux[1][0]_rrnode[501]+switch_rise_sb_mux[1][0]_rrnode[501]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[501] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_fall_sb_mux[1][0]_rrnode[501]' to='start_fall_sb_mux[1][0]_rrnode[501]+switch_fall_sb_mux[1][0]_rrnode[501]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_sb_mux[1][0]_rrnode[501]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_sb_mux[1][0]_rrnode[501]' -***** Load for rr_node[501] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=10, type=5 ***** -Xchan_mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[14]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to5] -+ param='sum_leakage_power_sb_mux[0to4]+leakage_sb_mux[1][0]_rrnode[501]' -.meas tran sum_energy_per_cycle_sb_mux[0to5] -+ param='sum_energy_per_cycle_sb_mux[0to4]+energy_per_cycle_sb_mux[1][0]_rrnode[501]' -Xmux_1level_tapbuf_size2[6] mux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->out sram[16]->outb sram[16]->out gvdd_mux_1level_tapbuf_size2[6] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[6], level=1, select_path_id=0. ***** -*****1***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -***** Signal mux_1level_tapbuf_size2[6]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[6]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[6] gvdd_mux_1level_tapbuf_size2[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[503] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[503] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[503] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[503] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[503] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[503] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[503] param='mux_1level_tapbuf_size2[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[6]_energy_per_cycle param='mux_1level_tapbuf_size2[6]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[503] param='mux_1level_tapbuf_size2[6]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[503] param='dynamic_power_sb_mux[1][0]_rrnode[503]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[503] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_rise_sb_mux[1][0]_rrnode[503]' to='start_rise_sb_mux[1][0]_rrnode[503]+switch_rise_sb_mux[1][0]_rrnode[503]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[503] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_fall_sb_mux[1][0]_rrnode[503]' to='start_fall_sb_mux[1][0]_rrnode[503]+switch_fall_sb_mux[1][0]_rrnode[503]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_sb_mux[1][0]_rrnode[503]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_sb_mux[1][0]_rrnode[503]' -***** Load for rr_node[503] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=12, type=5 ***** -Xchan_mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[16]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to6] -+ param='sum_leakage_power_sb_mux[0to5]+leakage_sb_mux[1][0]_rrnode[503]' -.meas tran sum_energy_per_cycle_sb_mux[0to6] -+ param='sum_energy_per_cycle_sb_mux[0to5]+energy_per_cycle_sb_mux[1][0]_rrnode[503]' -Xmux_1level_tapbuf_size2[7] mux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->out sram[17]->outb sram[17]->out gvdd_mux_1level_tapbuf_size2[7] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[7], level=1, select_path_id=0. ***** -*****1***** -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -***** Signal mux_1level_tapbuf_size2[7]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[7]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[7] gvdd_mux_1level_tapbuf_size2[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[505] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[505] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[505] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[505] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[505] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[505] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[505] param='mux_1level_tapbuf_size2[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[7]_energy_per_cycle param='mux_1level_tapbuf_size2[7]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[505] param='mux_1level_tapbuf_size2[7]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[505] param='dynamic_power_sb_mux[1][0]_rrnode[505]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[505] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_rise_sb_mux[1][0]_rrnode[505]' to='start_rise_sb_mux[1][0]_rrnode[505]+switch_rise_sb_mux[1][0]_rrnode[505]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[505] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_fall_sb_mux[1][0]_rrnode[505]' to='start_fall_sb_mux[1][0]_rrnode[505]+switch_fall_sb_mux[1][0]_rrnode[505]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_sb_mux[1][0]_rrnode[505]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_sb_mux[1][0]_rrnode[505]' -***** Load for rr_node[505] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=14, type=5 ***** -Xchan_mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[19]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to7] -+ param='sum_leakage_power_sb_mux[0to6]+leakage_sb_mux[1][0]_rrnode[505]' -.meas tran sum_energy_per_cycle_sb_mux[0to7] -+ param='sum_energy_per_cycle_sb_mux[0to6]+energy_per_cycle_sb_mux[1][0]_rrnode[505]' -Xmux_1level_tapbuf_size2[8] mux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->out sram[18]->outb sram[18]->out gvdd_mux_1level_tapbuf_size2[8] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[8], level=1, select_path_id=0. ***** -*****1***** -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -***** Signal mux_1level_tapbuf_size2[8]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[8]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[8] gvdd_mux_1level_tapbuf_size2[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[507] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[507] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[507] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[507] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[507] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[507] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[507] param='mux_1level_tapbuf_size2[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[8]_energy_per_cycle param='mux_1level_tapbuf_size2[8]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[507] param='mux_1level_tapbuf_size2[8]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[507] param='dynamic_power_sb_mux[1][0]_rrnode[507]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[507] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_rise_sb_mux[1][0]_rrnode[507]' to='start_rise_sb_mux[1][0]_rrnode[507]+switch_rise_sb_mux[1][0]_rrnode[507]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[507] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_fall_sb_mux[1][0]_rrnode[507]' to='start_fall_sb_mux[1][0]_rrnode[507]+switch_fall_sb_mux[1][0]_rrnode[507]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_sb_mux[1][0]_rrnode[507]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_sb_mux[1][0]_rrnode[507]' -***** Load for rr_node[507] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=16, type=5 ***** -Xchan_mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[21]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to8] -+ param='sum_leakage_power_sb_mux[0to7]+leakage_sb_mux[1][0]_rrnode[507]' -.meas tran sum_energy_per_cycle_sb_mux[0to8] -+ param='sum_energy_per_cycle_sb_mux[0to7]+energy_per_cycle_sb_mux[1][0]_rrnode[507]' -Xmux_1level_tapbuf_size2[9] mux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->out sram[19]->outb sram[19]->out gvdd_mux_1level_tapbuf_size2[9] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[9], level=1, select_path_id=0. ***** -*****1***** -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_1level_tapbuf_size2[9]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[9]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[9] gvdd_mux_1level_tapbuf_size2[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[509] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[509] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[509] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[509] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[509] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[509] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[509] param='mux_1level_tapbuf_size2[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[9]_energy_per_cycle param='mux_1level_tapbuf_size2[9]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[509] param='mux_1level_tapbuf_size2[9]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[509] param='dynamic_power_sb_mux[1][0]_rrnode[509]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[509] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_rise_sb_mux[1][0]_rrnode[509]' to='start_rise_sb_mux[1][0]_rrnode[509]+switch_rise_sb_mux[1][0]_rrnode[509]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[509] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_fall_sb_mux[1][0]_rrnode[509]' to='start_fall_sb_mux[1][0]_rrnode[509]+switch_fall_sb_mux[1][0]_rrnode[509]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_sb_mux[1][0]_rrnode[509]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_sb_mux[1][0]_rrnode[509]' -***** Load for rr_node[509] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=18, type=5 ***** -Xchan_mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[23]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to9] -+ param='sum_leakage_power_sb_mux[0to8]+leakage_sb_mux[1][0]_rrnode[509]' -.meas tran sum_energy_per_cycle_sb_mux[0to9] -+ param='sum_energy_per_cycle_sb_mux[0to8]+energy_per_cycle_sb_mux[1][0]_rrnode[509]' -Xmux_1level_tapbuf_size2[10] mux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->out sram[20]->outb sram[20]->out gvdd_mux_1level_tapbuf_size2[10] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[10], level=1, select_path_id=0. ***** -*****1***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -***** Signal mux_1level_tapbuf_size2[10]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[10]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[10] gvdd_mux_1level_tapbuf_size2[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[511] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[511] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[511] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[511] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[511] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[511] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[511] param='mux_1level_tapbuf_size2[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[10]_energy_per_cycle param='mux_1level_tapbuf_size2[10]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[511] param='mux_1level_tapbuf_size2[10]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[511] param='dynamic_power_sb_mux[1][0]_rrnode[511]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[511] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_rise_sb_mux[1][0]_rrnode[511]' to='start_rise_sb_mux[1][0]_rrnode[511]+switch_rise_sb_mux[1][0]_rrnode[511]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[511] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_fall_sb_mux[1][0]_rrnode[511]' to='start_fall_sb_mux[1][0]_rrnode[511]+switch_fall_sb_mux[1][0]_rrnode[511]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_sb_mux[1][0]_rrnode[511]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_sb_mux[1][0]_rrnode[511]' -***** Load for rr_node[511] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=20, type=5 ***** -Xchan_mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[26]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to10] -+ param='sum_leakage_power_sb_mux[0to9]+leakage_sb_mux[1][0]_rrnode[511]' -.meas tran sum_energy_per_cycle_sb_mux[0to10] -+ param='sum_energy_per_cycle_sb_mux[0to9]+energy_per_cycle_sb_mux[1][0]_rrnode[511]' -Xmux_1level_tapbuf_size2[11] mux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->out sram[21]->outb sram[21]->out gvdd_mux_1level_tapbuf_size2[11] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[11], level=1, select_path_id=0. ***** -*****1***** -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -***** Signal mux_1level_tapbuf_size2[11]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[11]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[11] gvdd_mux_1level_tapbuf_size2[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[513] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[513] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[513] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[513] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[513] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[513] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[513] param='mux_1level_tapbuf_size2[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[11]_energy_per_cycle param='mux_1level_tapbuf_size2[11]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[513] param='mux_1level_tapbuf_size2[11]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[513] param='dynamic_power_sb_mux[1][0]_rrnode[513]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[513] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_rise_sb_mux[1][0]_rrnode[513]' to='start_rise_sb_mux[1][0]_rrnode[513]+switch_rise_sb_mux[1][0]_rrnode[513]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[513] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_fall_sb_mux[1][0]_rrnode[513]' to='start_fall_sb_mux[1][0]_rrnode[513]+switch_fall_sb_mux[1][0]_rrnode[513]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_sb_mux[1][0]_rrnode[513]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_sb_mux[1][0]_rrnode[513]' -***** Load for rr_node[513] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=22, type=5 ***** -Xchan_mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[28]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to11] -+ param='sum_leakage_power_sb_mux[0to10]+leakage_sb_mux[1][0]_rrnode[513]' -.meas tran sum_energy_per_cycle_sb_mux[0to11] -+ param='sum_energy_per_cycle_sb_mux[0to10]+energy_per_cycle_sb_mux[1][0]_rrnode[513]' -Xmux_1level_tapbuf_size2[12] mux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->out sram[22]->outb sram[22]->out gvdd_mux_1level_tapbuf_size2[12] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[12], level=1, select_path_id=0. ***** -*****1***** -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -***** Signal mux_1level_tapbuf_size2[12]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[12]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[12] gvdd_mux_1level_tapbuf_size2[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[515] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[515] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[515] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[515] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[515] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[515] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[515] param='mux_1level_tapbuf_size2[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[12]_energy_per_cycle param='mux_1level_tapbuf_size2[12]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[515] param='mux_1level_tapbuf_size2[12]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[515] param='dynamic_power_sb_mux[1][0]_rrnode[515]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[515] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_rise_sb_mux[1][0]_rrnode[515]' to='start_rise_sb_mux[1][0]_rrnode[515]+switch_rise_sb_mux[1][0]_rrnode[515]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[515] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_fall_sb_mux[1][0]_rrnode[515]' to='start_fall_sb_mux[1][0]_rrnode[515]+switch_fall_sb_mux[1][0]_rrnode[515]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_sb_mux[1][0]_rrnode[515]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_sb_mux[1][0]_rrnode[515]' -***** Load for rr_node[515] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=24, type=5 ***** -Xchan_mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[31]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to12] -+ param='sum_leakage_power_sb_mux[0to11]+leakage_sb_mux[1][0]_rrnode[515]' -.meas tran sum_energy_per_cycle_sb_mux[0to12] -+ param='sum_energy_per_cycle_sb_mux[0to11]+energy_per_cycle_sb_mux[1][0]_rrnode[515]' -Xmux_1level_tapbuf_size2[13] mux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->out sram[23]->outb sram[23]->out gvdd_mux_1level_tapbuf_size2[13] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[13], level=1, select_path_id=0. ***** -*****1***** -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_1level_tapbuf_size2[13]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[13]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[13] gvdd_mux_1level_tapbuf_size2[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[517] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[517] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[517] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[517] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[517] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[517] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[517] param='mux_1level_tapbuf_size2[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[13]_energy_per_cycle param='mux_1level_tapbuf_size2[13]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[517] param='mux_1level_tapbuf_size2[13]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[517] param='dynamic_power_sb_mux[1][0]_rrnode[517]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[517] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_rise_sb_mux[1][0]_rrnode[517]' to='start_rise_sb_mux[1][0]_rrnode[517]+switch_rise_sb_mux[1][0]_rrnode[517]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[517] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_fall_sb_mux[1][0]_rrnode[517]' to='start_fall_sb_mux[1][0]_rrnode[517]+switch_fall_sb_mux[1][0]_rrnode[517]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_sb_mux[1][0]_rrnode[517]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_sb_mux[1][0]_rrnode[517]' -***** Load for rr_node[517] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=26, type=5 ***** -Xchan_mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[34]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to13] -+ param='sum_leakage_power_sb_mux[0to12]+leakage_sb_mux[1][0]_rrnode[517]' -.meas tran sum_energy_per_cycle_sb_mux[0to13] -+ param='sum_energy_per_cycle_sb_mux[0to12]+energy_per_cycle_sb_mux[1][0]_rrnode[517]' -Xmux_1level_tapbuf_size2[14] mux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->out sram[24]->outb sram[24]->out gvdd_mux_1level_tapbuf_size2[14] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[14], level=1, select_path_id=0. ***** -*****1***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -***** Signal mux_1level_tapbuf_size2[14]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[14]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[14] gvdd_mux_1level_tapbuf_size2[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[519] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[519] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[519] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[519] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[519] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[519] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[519] param='mux_1level_tapbuf_size2[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[14]_energy_per_cycle param='mux_1level_tapbuf_size2[14]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[519] param='mux_1level_tapbuf_size2[14]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[519] param='dynamic_power_sb_mux[1][0]_rrnode[519]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[519] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_rise_sb_mux[1][0]_rrnode[519]' to='start_rise_sb_mux[1][0]_rrnode[519]+switch_rise_sb_mux[1][0]_rrnode[519]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[519] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_fall_sb_mux[1][0]_rrnode[519]' to='start_fall_sb_mux[1][0]_rrnode[519]+switch_fall_sb_mux[1][0]_rrnode[519]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_sb_mux[1][0]_rrnode[519]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_sb_mux[1][0]_rrnode[519]' -***** Load for rr_node[519] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=28, type=5 ***** -Xchan_mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[36]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to14] -+ param='sum_leakage_power_sb_mux[0to13]+leakage_sb_mux[1][0]_rrnode[519]' -.meas tran sum_energy_per_cycle_sb_mux[0to14] -+ param='sum_energy_per_cycle_sb_mux[0to13]+energy_per_cycle_sb_mux[1][0]_rrnode[519]' -Xmux_1level_tapbuf_size2[15] mux_1level_tapbuf_size2[15]->in[0] mux_1level_tapbuf_size2[15]->in[1] mux_1level_tapbuf_size2[15]->out sram[25]->outb sram[25]->out gvdd_mux_1level_tapbuf_size2[15] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[15], level=1, select_path_id=0. ***** -*****1***** -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -***** Signal mux_1level_tapbuf_size2[15]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[15]->in[0] mux_1level_tapbuf_size2[15]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[15]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[15]->in[1] mux_1level_tapbuf_size2[15]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[15] gvdd_mux_1level_tapbuf_size2[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[521] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[521] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[521] when v(mux_1level_tapbuf_size2[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[521] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[521] when v(mux_1level_tapbuf_size2[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[521] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[15]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[521] param='mux_1level_tapbuf_size2[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[15]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[15]_energy_per_cycle param='mux_1level_tapbuf_size2[15]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[521] param='mux_1level_tapbuf_size2[15]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[521] param='dynamic_power_sb_mux[1][0]_rrnode[521]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[521] avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='start_rise_sb_mux[1][0]_rrnode[521]' to='start_rise_sb_mux[1][0]_rrnode[521]+switch_rise_sb_mux[1][0]_rrnode[521]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[521] avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='start_fall_sb_mux[1][0]_rrnode[521]' to='start_fall_sb_mux[1][0]_rrnode[521]+switch_fall_sb_mux[1][0]_rrnode[521]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_sb_mux[1][0]_rrnode[521]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_sb_mux[1][0]_rrnode[521]' -***** Load for rr_node[521] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=30, type=5 ***** -Xchan_mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[39]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to15] -+ param='sum_leakage_power_sb_mux[0to14]+leakage_sb_mux[1][0]_rrnode[521]' -.meas tran sum_energy_per_cycle_sb_mux[0to15] -+ param='sum_energy_per_cycle_sb_mux[0to14]+energy_per_cycle_sb_mux[1][0]_rrnode[521]' -Xmux_1level_tapbuf_size2[16] mux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->out sram[26]->outb sram[26]->out gvdd_mux_1level_tapbuf_size2[16] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[16], level=1, select_path_id=0. ***** -*****1***** -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -***** Signal mux_1level_tapbuf_size2[16]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[16]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[16] gvdd_mux_1level_tapbuf_size2[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[523] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[523] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[523] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[523] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[523] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[523] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[523] param='mux_1level_tapbuf_size2[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[16]_energy_per_cycle param='mux_1level_tapbuf_size2[16]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[523] param='mux_1level_tapbuf_size2[16]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[523] param='dynamic_power_sb_mux[1][0]_rrnode[523]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[523] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_rise_sb_mux[1][0]_rrnode[523]' to='start_rise_sb_mux[1][0]_rrnode[523]+switch_rise_sb_mux[1][0]_rrnode[523]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[523] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_fall_sb_mux[1][0]_rrnode[523]' to='start_fall_sb_mux[1][0]_rrnode[523]+switch_fall_sb_mux[1][0]_rrnode[523]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_sb_mux[1][0]_rrnode[523]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_sb_mux[1][0]_rrnode[523]' -***** Load for rr_node[523] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=32, type=5 ***** -Xchan_mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[42]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to16] -+ param='sum_leakage_power_sb_mux[0to15]+leakage_sb_mux[1][0]_rrnode[523]' -.meas tran sum_energy_per_cycle_sb_mux[0to16] -+ param='sum_energy_per_cycle_sb_mux[0to15]+energy_per_cycle_sb_mux[1][0]_rrnode[523]' -Xmux_1level_tapbuf_size2[17] mux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->out sram[27]->outb sram[27]->out gvdd_mux_1level_tapbuf_size2[17] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[17], level=1, select_path_id=0. ***** -*****1***** -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_1level_tapbuf_size2[17]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[17]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[17] gvdd_mux_1level_tapbuf_size2[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[525] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[525] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[525] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[525] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[525] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[525] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[525] param='mux_1level_tapbuf_size2[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[17]_energy_per_cycle param='mux_1level_tapbuf_size2[17]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[525] param='mux_1level_tapbuf_size2[17]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[525] param='dynamic_power_sb_mux[1][0]_rrnode[525]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[525] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_rise_sb_mux[1][0]_rrnode[525]' to='start_rise_sb_mux[1][0]_rrnode[525]+switch_rise_sb_mux[1][0]_rrnode[525]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[525] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_fall_sb_mux[1][0]_rrnode[525]' to='start_fall_sb_mux[1][0]_rrnode[525]+switch_fall_sb_mux[1][0]_rrnode[525]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_sb_mux[1][0]_rrnode[525]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_sb_mux[1][0]_rrnode[525]' -***** Load for rr_node[525] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=34, type=5 ***** -Xchan_mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[45]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to17] -+ param='sum_leakage_power_sb_mux[0to16]+leakage_sb_mux[1][0]_rrnode[525]' -.meas tran sum_energy_per_cycle_sb_mux[0to17] -+ param='sum_energy_per_cycle_sb_mux[0to16]+energy_per_cycle_sb_mux[1][0]_rrnode[525]' -Xmux_1level_tapbuf_size2[18] mux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->out sram[28]->outb sram[28]->out gvdd_mux_1level_tapbuf_size2[18] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[18], level=1, select_path_id=0. ***** -*****1***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -***** Signal mux_1level_tapbuf_size2[18]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[18]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[18] gvdd_mux_1level_tapbuf_size2[18] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[527] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[527] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[527] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[527] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[527] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[527] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[527] param='mux_1level_tapbuf_size2[18]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[18]_energy_per_cycle param='mux_1level_tapbuf_size2[18]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[527] param='mux_1level_tapbuf_size2[18]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[527] param='dynamic_power_sb_mux[1][0]_rrnode[527]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[527] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_rise_sb_mux[1][0]_rrnode[527]' to='start_rise_sb_mux[1][0]_rrnode[527]+switch_rise_sb_mux[1][0]_rrnode[527]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[527] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_fall_sb_mux[1][0]_rrnode[527]' to='start_fall_sb_mux[1][0]_rrnode[527]+switch_fall_sb_mux[1][0]_rrnode[527]' -.meas tran sum_leakage_power_mux[0to18] -+ param='sum_leakage_power_mux[0to17]+leakage_sb_mux[1][0]_rrnode[527]' -.meas tran sum_energy_per_cycle_mux[0to18] -+ param='sum_energy_per_cycle_mux[0to17]+energy_per_cycle_sb_mux[1][0]_rrnode[527]' -***** Load for rr_node[527] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=36, type=5 ***** -Xchan_mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[48]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to18] -+ param='sum_leakage_power_sb_mux[0to17]+leakage_sb_mux[1][0]_rrnode[527]' -.meas tran sum_energy_per_cycle_sb_mux[0to18] -+ param='sum_energy_per_cycle_sb_mux[0to17]+energy_per_cycle_sb_mux[1][0]_rrnode[527]' -Xmux_1level_tapbuf_size2[19] mux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->out sram[29]->outb sram[29]->out gvdd_mux_1level_tapbuf_size2[19] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[19], level=1, select_path_id=0. ***** -*****1***** -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -***** Signal mux_1level_tapbuf_size2[19]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[19]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[19] gvdd_mux_1level_tapbuf_size2[19] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[529] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[529] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[529] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[529] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[529] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[529] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[529] param='mux_1level_tapbuf_size2[19]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[19]_energy_per_cycle param='mux_1level_tapbuf_size2[19]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[529] param='mux_1level_tapbuf_size2[19]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[529] param='dynamic_power_sb_mux[1][0]_rrnode[529]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[529] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_rise_sb_mux[1][0]_rrnode[529]' to='start_rise_sb_mux[1][0]_rrnode[529]+switch_rise_sb_mux[1][0]_rrnode[529]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[529] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_fall_sb_mux[1][0]_rrnode[529]' to='start_fall_sb_mux[1][0]_rrnode[529]+switch_fall_sb_mux[1][0]_rrnode[529]' -.meas tran sum_leakage_power_mux[0to19] -+ param='sum_leakage_power_mux[0to18]+leakage_sb_mux[1][0]_rrnode[529]' -.meas tran sum_energy_per_cycle_mux[0to19] -+ param='sum_energy_per_cycle_mux[0to18]+energy_per_cycle_sb_mux[1][0]_rrnode[529]' -***** Load for rr_node[529] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=38, type=5 ***** -Xchan_mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[50]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to19] -+ param='sum_leakage_power_sb_mux[0to18]+leakage_sb_mux[1][0]_rrnode[529]' -.meas tran sum_energy_per_cycle_sb_mux[0to19] -+ param='sum_energy_per_cycle_sb_mux[0to18]+energy_per_cycle_sb_mux[1][0]_rrnode[529]' -Xmux_1level_tapbuf_size2[20] mux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->out sram[30]->outb sram[30]->out gvdd_mux_1level_tapbuf_size2[20] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[20], level=1, select_path_id=0. ***** -*****1***** -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -***** Signal mux_1level_tapbuf_size2[20]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[20]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[20] gvdd_mux_1level_tapbuf_size2[20] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[531] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[531] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[531] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[531] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[531] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[531] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[531] param='mux_1level_tapbuf_size2[20]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[20]_energy_per_cycle param='mux_1level_tapbuf_size2[20]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[531] param='mux_1level_tapbuf_size2[20]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[531] param='dynamic_power_sb_mux[1][0]_rrnode[531]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[531] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_rise_sb_mux[1][0]_rrnode[531]' to='start_rise_sb_mux[1][0]_rrnode[531]+switch_rise_sb_mux[1][0]_rrnode[531]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[531] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_fall_sb_mux[1][0]_rrnode[531]' to='start_fall_sb_mux[1][0]_rrnode[531]+switch_fall_sb_mux[1][0]_rrnode[531]' -.meas tran sum_leakage_power_mux[0to20] -+ param='sum_leakage_power_mux[0to19]+leakage_sb_mux[1][0]_rrnode[531]' -.meas tran sum_energy_per_cycle_mux[0to20] -+ param='sum_energy_per_cycle_mux[0to19]+energy_per_cycle_sb_mux[1][0]_rrnode[531]' -***** Load for rr_node[531] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=40, type=5 ***** -Xchan_mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[52]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to20] -+ param='sum_leakage_power_sb_mux[0to19]+leakage_sb_mux[1][0]_rrnode[531]' -.meas tran sum_energy_per_cycle_sb_mux[0to20] -+ param='sum_energy_per_cycle_sb_mux[0to19]+energy_per_cycle_sb_mux[1][0]_rrnode[531]' -Xmux_1level_tapbuf_size2[21] mux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->out sram[31]->outb sram[31]->out gvdd_mux_1level_tapbuf_size2[21] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[21], level=1, select_path_id=0. ***** -*****1***** -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_1level_tapbuf_size2[21]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[21]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[21] gvdd_mux_1level_tapbuf_size2[21] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[533] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[533] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[533] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[533] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[533] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[533] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[533] param='mux_1level_tapbuf_size2[21]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[21]_energy_per_cycle param='mux_1level_tapbuf_size2[21]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[533] param='mux_1level_tapbuf_size2[21]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[533] param='dynamic_power_sb_mux[1][0]_rrnode[533]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[533] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_rise_sb_mux[1][0]_rrnode[533]' to='start_rise_sb_mux[1][0]_rrnode[533]+switch_rise_sb_mux[1][0]_rrnode[533]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[533] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_fall_sb_mux[1][0]_rrnode[533]' to='start_fall_sb_mux[1][0]_rrnode[533]+switch_fall_sb_mux[1][0]_rrnode[533]' -.meas tran sum_leakage_power_mux[0to21] -+ param='sum_leakage_power_mux[0to20]+leakage_sb_mux[1][0]_rrnode[533]' -.meas tran sum_energy_per_cycle_mux[0to21] -+ param='sum_energy_per_cycle_mux[0to20]+energy_per_cycle_sb_mux[1][0]_rrnode[533]' -***** Load for rr_node[533] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=42, type=5 ***** -Xchan_mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[54]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to21] -+ param='sum_leakage_power_sb_mux[0to20]+leakage_sb_mux[1][0]_rrnode[533]' -.meas tran sum_energy_per_cycle_sb_mux[0to21] -+ param='sum_energy_per_cycle_sb_mux[0to20]+energy_per_cycle_sb_mux[1][0]_rrnode[533]' -Xmux_1level_tapbuf_size2[22] mux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->out sram[32]->outb sram[32]->out gvdd_mux_1level_tapbuf_size2[22] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[22], level=1, select_path_id=0. ***** -*****1***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -***** Signal mux_1level_tapbuf_size2[22]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[22]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[22] gvdd_mux_1level_tapbuf_size2[22] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[535] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[535] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[535] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[535] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[535] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[535] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[535] param='mux_1level_tapbuf_size2[22]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[22]_energy_per_cycle param='mux_1level_tapbuf_size2[22]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[535] param='mux_1level_tapbuf_size2[22]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[535] param='dynamic_power_sb_mux[1][0]_rrnode[535]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[535] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_rise_sb_mux[1][0]_rrnode[535]' to='start_rise_sb_mux[1][0]_rrnode[535]+switch_rise_sb_mux[1][0]_rrnode[535]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[535] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_fall_sb_mux[1][0]_rrnode[535]' to='start_fall_sb_mux[1][0]_rrnode[535]+switch_fall_sb_mux[1][0]_rrnode[535]' -.meas tran sum_leakage_power_mux[0to22] -+ param='sum_leakage_power_mux[0to21]+leakage_sb_mux[1][0]_rrnode[535]' -.meas tran sum_energy_per_cycle_mux[0to22] -+ param='sum_energy_per_cycle_mux[0to21]+energy_per_cycle_sb_mux[1][0]_rrnode[535]' -***** Load for rr_node[535] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=44, type=5 ***** -Xchan_mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[57]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to22] -+ param='sum_leakage_power_sb_mux[0to21]+leakage_sb_mux[1][0]_rrnode[535]' -.meas tran sum_energy_per_cycle_sb_mux[0to22] -+ param='sum_energy_per_cycle_sb_mux[0to21]+energy_per_cycle_sb_mux[1][0]_rrnode[535]' -Xmux_1level_tapbuf_size2[23] mux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->out sram[33]->outb sram[33]->out gvdd_mux_1level_tapbuf_size2[23] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[23], level=1, select_path_id=0. ***** -*****1***** -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -***** Signal mux_1level_tapbuf_size2[23]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[23]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[23] gvdd_mux_1level_tapbuf_size2[23] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[537] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[537] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[537] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[537] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[537] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[537] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[537] param='mux_1level_tapbuf_size2[23]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[23]_energy_per_cycle param='mux_1level_tapbuf_size2[23]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[537] param='mux_1level_tapbuf_size2[23]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[537] param='dynamic_power_sb_mux[1][0]_rrnode[537]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[537] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_rise_sb_mux[1][0]_rrnode[537]' to='start_rise_sb_mux[1][0]_rrnode[537]+switch_rise_sb_mux[1][0]_rrnode[537]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[537] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_fall_sb_mux[1][0]_rrnode[537]' to='start_fall_sb_mux[1][0]_rrnode[537]+switch_fall_sb_mux[1][0]_rrnode[537]' -.meas tran sum_leakage_power_mux[0to23] -+ param='sum_leakage_power_mux[0to22]+leakage_sb_mux[1][0]_rrnode[537]' -.meas tran sum_energy_per_cycle_mux[0to23] -+ param='sum_energy_per_cycle_mux[0to22]+energy_per_cycle_sb_mux[1][0]_rrnode[537]' -***** Load for rr_node[537] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=46, type=5 ***** -Xchan_mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[60]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to23] -+ param='sum_leakage_power_sb_mux[0to22]+leakage_sb_mux[1][0]_rrnode[537]' -.meas tran sum_energy_per_cycle_sb_mux[0to23] -+ param='sum_energy_per_cycle_sb_mux[0to22]+energy_per_cycle_sb_mux[1][0]_rrnode[537]' -Xmux_1level_tapbuf_size2[24] mux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->out sram[34]->outb sram[34]->out gvdd_mux_1level_tapbuf_size2[24] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[24], level=1, select_path_id=0. ***** -*****1***** -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -***** Signal mux_1level_tapbuf_size2[24]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[24]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[24] gvdd_mux_1level_tapbuf_size2[24] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[539] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[539] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[539] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[539] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[539] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[539] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[539] param='mux_1level_tapbuf_size2[24]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[24]_energy_per_cycle param='mux_1level_tapbuf_size2[24]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[539] param='mux_1level_tapbuf_size2[24]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[539] param='dynamic_power_sb_mux[1][0]_rrnode[539]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[539] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_rise_sb_mux[1][0]_rrnode[539]' to='start_rise_sb_mux[1][0]_rrnode[539]+switch_rise_sb_mux[1][0]_rrnode[539]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[539] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_fall_sb_mux[1][0]_rrnode[539]' to='start_fall_sb_mux[1][0]_rrnode[539]+switch_fall_sb_mux[1][0]_rrnode[539]' -.meas tran sum_leakage_power_mux[0to24] -+ param='sum_leakage_power_mux[0to23]+leakage_sb_mux[1][0]_rrnode[539]' -.meas tran sum_energy_per_cycle_mux[0to24] -+ param='sum_energy_per_cycle_mux[0to23]+energy_per_cycle_sb_mux[1][0]_rrnode[539]' -***** Load for rr_node[539] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=48, type=5 ***** -Xchan_mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[63]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to24] -+ param='sum_leakage_power_sb_mux[0to23]+leakage_sb_mux[1][0]_rrnode[539]' -.meas tran sum_energy_per_cycle_sb_mux[0to24] -+ param='sum_energy_per_cycle_sb_mux[0to23]+energy_per_cycle_sb_mux[1][0]_rrnode[539]' -Xmux_1level_tapbuf_size2[25] mux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->out sram[35]->outb sram[35]->out gvdd_mux_1level_tapbuf_size2[25] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[25], level=1, select_path_id=0. ***** -*****1***** -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -***** Signal mux_1level_tapbuf_size2[25]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[25]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[25] gvdd_mux_1level_tapbuf_size2[25] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[541] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[541] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[541] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[541] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[541] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[541] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[541] param='mux_1level_tapbuf_size2[25]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[25]_energy_per_cycle param='mux_1level_tapbuf_size2[25]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[541] param='mux_1level_tapbuf_size2[25]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[541] param='dynamic_power_sb_mux[1][0]_rrnode[541]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[541] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_rise_sb_mux[1][0]_rrnode[541]' to='start_rise_sb_mux[1][0]_rrnode[541]+switch_rise_sb_mux[1][0]_rrnode[541]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[541] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_fall_sb_mux[1][0]_rrnode[541]' to='start_fall_sb_mux[1][0]_rrnode[541]+switch_fall_sb_mux[1][0]_rrnode[541]' -.meas tran sum_leakage_power_mux[0to25] -+ param='sum_leakage_power_mux[0to24]+leakage_sb_mux[1][0]_rrnode[541]' -.meas tran sum_energy_per_cycle_mux[0to25] -+ param='sum_energy_per_cycle_mux[0to24]+energy_per_cycle_sb_mux[1][0]_rrnode[541]' -***** Load for rr_node[541] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=50, type=5 ***** -Xchan_mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[66]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to25] -+ param='sum_leakage_power_sb_mux[0to24]+leakage_sb_mux[1][0]_rrnode[541]' -.meas tran sum_energy_per_cycle_sb_mux[0to25] -+ param='sum_energy_per_cycle_sb_mux[0to24]+energy_per_cycle_sb_mux[1][0]_rrnode[541]' -Xmux_1level_tapbuf_size2[26] mux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->out sram[36]->outb sram[36]->out gvdd_mux_1level_tapbuf_size2[26] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[26], level=1, select_path_id=0. ***** -*****1***** -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -***** Signal mux_1level_tapbuf_size2[26]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[26]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[26] gvdd_mux_1level_tapbuf_size2[26] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[543] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[543] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[543] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[543] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[543] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[543] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[543] param='mux_1level_tapbuf_size2[26]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[26]_energy_per_cycle param='mux_1level_tapbuf_size2[26]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[543] param='mux_1level_tapbuf_size2[26]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[543] param='dynamic_power_sb_mux[1][0]_rrnode[543]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[543] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_rise_sb_mux[1][0]_rrnode[543]' to='start_rise_sb_mux[1][0]_rrnode[543]+switch_rise_sb_mux[1][0]_rrnode[543]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[543] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_fall_sb_mux[1][0]_rrnode[543]' to='start_fall_sb_mux[1][0]_rrnode[543]+switch_fall_sb_mux[1][0]_rrnode[543]' -.meas tran sum_leakage_power_mux[0to26] -+ param='sum_leakage_power_mux[0to25]+leakage_sb_mux[1][0]_rrnode[543]' -.meas tran sum_energy_per_cycle_mux[0to26] -+ param='sum_energy_per_cycle_mux[0to25]+energy_per_cycle_sb_mux[1][0]_rrnode[543]' -***** Load for rr_node[543] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=52, type=5 ***** -Xchan_mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[68]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to26] -+ param='sum_leakage_power_sb_mux[0to25]+leakage_sb_mux[1][0]_rrnode[543]' -.meas tran sum_energy_per_cycle_sb_mux[0to26] -+ param='sum_energy_per_cycle_sb_mux[0to25]+energy_per_cycle_sb_mux[1][0]_rrnode[543]' -Xmux_1level_tapbuf_size2[27] mux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->out sram[37]->outb sram[37]->out gvdd_mux_1level_tapbuf_size2[27] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[27], level=1, select_path_id=0. ***** -*****1***** -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -***** Signal mux_1level_tapbuf_size2[27]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[27]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[27] gvdd_mux_1level_tapbuf_size2[27] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[545] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[545] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[545] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[545] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[545] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[545] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[545] param='mux_1level_tapbuf_size2[27]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[27]_energy_per_cycle param='mux_1level_tapbuf_size2[27]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[545] param='mux_1level_tapbuf_size2[27]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[545] param='dynamic_power_sb_mux[1][0]_rrnode[545]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[545] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_rise_sb_mux[1][0]_rrnode[545]' to='start_rise_sb_mux[1][0]_rrnode[545]+switch_rise_sb_mux[1][0]_rrnode[545]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[545] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_fall_sb_mux[1][0]_rrnode[545]' to='start_fall_sb_mux[1][0]_rrnode[545]+switch_fall_sb_mux[1][0]_rrnode[545]' -.meas tran sum_leakage_power_mux[0to27] -+ param='sum_leakage_power_mux[0to26]+leakage_sb_mux[1][0]_rrnode[545]' -.meas tran sum_energy_per_cycle_mux[0to27] -+ param='sum_energy_per_cycle_mux[0to26]+energy_per_cycle_sb_mux[1][0]_rrnode[545]' -***** Load for rr_node[545] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=54, type=5 ***** -Xchan_mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[71]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to27] -+ param='sum_leakage_power_sb_mux[0to26]+leakage_sb_mux[1][0]_rrnode[545]' -.meas tran sum_energy_per_cycle_sb_mux[0to27] -+ param='sum_energy_per_cycle_sb_mux[0to26]+energy_per_cycle_sb_mux[1][0]_rrnode[545]' -Xmux_1level_tapbuf_size2[28] mux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->out sram[38]->outb sram[38]->out gvdd_mux_1level_tapbuf_size2[28] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[28], level=1, select_path_id=0. ***** -*****1***** -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -***** Signal mux_1level_tapbuf_size2[28]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[28]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[28] gvdd_mux_1level_tapbuf_size2[28] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[547] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[547] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[547] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[547] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[547] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[547] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[547] param='mux_1level_tapbuf_size2[28]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[28]_energy_per_cycle param='mux_1level_tapbuf_size2[28]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[547] param='mux_1level_tapbuf_size2[28]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[547] param='dynamic_power_sb_mux[1][0]_rrnode[547]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[547] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_rise_sb_mux[1][0]_rrnode[547]' to='start_rise_sb_mux[1][0]_rrnode[547]+switch_rise_sb_mux[1][0]_rrnode[547]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[547] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_fall_sb_mux[1][0]_rrnode[547]' to='start_fall_sb_mux[1][0]_rrnode[547]+switch_fall_sb_mux[1][0]_rrnode[547]' -.meas tran sum_leakage_power_mux[0to28] -+ param='sum_leakage_power_mux[0to27]+leakage_sb_mux[1][0]_rrnode[547]' -.meas tran sum_energy_per_cycle_mux[0to28] -+ param='sum_energy_per_cycle_mux[0to27]+energy_per_cycle_sb_mux[1][0]_rrnode[547]' -***** Load for rr_node[547] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=56, type=5 ***** -Xchan_mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[73]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to28] -+ param='sum_leakage_power_sb_mux[0to27]+leakage_sb_mux[1][0]_rrnode[547]' -.meas tran sum_energy_per_cycle_sb_mux[0to28] -+ param='sum_energy_per_cycle_sb_mux[0to27]+energy_per_cycle_sb_mux[1][0]_rrnode[547]' -Xmux_1level_tapbuf_size2[29] mux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->out sram[39]->outb sram[39]->out gvdd_mux_1level_tapbuf_size2[29] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[29], level=1, select_path_id=0. ***** -*****1***** -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -***** Signal mux_1level_tapbuf_size2[29]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[29]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[29] gvdd_mux_1level_tapbuf_size2[29] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[549] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[549] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[549] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[549] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[549] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[549] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[549] param='mux_1level_tapbuf_size2[29]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[29]_energy_per_cycle param='mux_1level_tapbuf_size2[29]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[549] param='mux_1level_tapbuf_size2[29]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[549] param='dynamic_power_sb_mux[1][0]_rrnode[549]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[549] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_rise_sb_mux[1][0]_rrnode[549]' to='start_rise_sb_mux[1][0]_rrnode[549]+switch_rise_sb_mux[1][0]_rrnode[549]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[549] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_fall_sb_mux[1][0]_rrnode[549]' to='start_fall_sb_mux[1][0]_rrnode[549]+switch_fall_sb_mux[1][0]_rrnode[549]' -.meas tran sum_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to28]+leakage_sb_mux[1][0]_rrnode[549]' -.meas tran sum_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to28]+energy_per_cycle_sb_mux[1][0]_rrnode[549]' -***** Load for rr_node[549] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=58, type=5 ***** -Xchan_mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[75]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to29] -+ param='sum_leakage_power_sb_mux[0to28]+leakage_sb_mux[1][0]_rrnode[549]' -.meas tran sum_energy_per_cycle_sb_mux[0to29] -+ param='sum_energy_per_cycle_sb_mux[0to28]+energy_per_cycle_sb_mux[1][0]_rrnode[549]' -Xmux_1level_tapbuf_size2[30] mux_1level_tapbuf_size2[30]->in[0] mux_1level_tapbuf_size2[30]->in[1] mux_1level_tapbuf_size2[30]->out sram[40]->outb sram[40]->out gvdd_mux_1level_tapbuf_size2[30] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[30], level=1, select_path_id=0. ***** -*****1***** -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -***** Signal mux_1level_tapbuf_size2[30]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[30]->in[0] mux_1level_tapbuf_size2[30]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[30]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[30]->in[1] mux_1level_tapbuf_size2[30]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[30] gvdd_mux_1level_tapbuf_size2[30] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[551] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[551] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[551] when v(mux_1level_tapbuf_size2[30]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[551] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[551] when v(mux_1level_tapbuf_size2[30]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[551] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[30]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[551] param='mux_1level_tapbuf_size2[30]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[30]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[30]_energy_per_cycle param='mux_1level_tapbuf_size2[30]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[551] param='mux_1level_tapbuf_size2[30]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[551] param='dynamic_power_sb_mux[1][0]_rrnode[551]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[551] avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='start_rise_sb_mux[1][0]_rrnode[551]' to='start_rise_sb_mux[1][0]_rrnode[551]+switch_rise_sb_mux[1][0]_rrnode[551]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[551] avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='start_fall_sb_mux[1][0]_rrnode[551]' to='start_fall_sb_mux[1][0]_rrnode[551]+switch_fall_sb_mux[1][0]_rrnode[551]' -.meas tran sum_leakage_power_mux[0to30] -+ param='sum_leakage_power_mux[0to29]+leakage_sb_mux[1][0]_rrnode[551]' -.meas tran sum_energy_per_cycle_mux[0to30] -+ param='sum_energy_per_cycle_mux[0to29]+energy_per_cycle_sb_mux[1][0]_rrnode[551]' -***** Load for rr_node[551] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=60, type=5 ***** -Xchan_mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[78]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to30] -+ param='sum_leakage_power_sb_mux[0to29]+leakage_sb_mux[1][0]_rrnode[551]' -.meas tran sum_energy_per_cycle_sb_mux[0to30] -+ param='sum_energy_per_cycle_sb_mux[0to29]+energy_per_cycle_sb_mux[1][0]_rrnode[551]' -Xmux_1level_tapbuf_size2[31] mux_1level_tapbuf_size2[31]->in[0] mux_1level_tapbuf_size2[31]->in[1] mux_1level_tapbuf_size2[31]->out sram[41]->outb sram[41]->out gvdd_mux_1level_tapbuf_size2[31] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[31], level=1, select_path_id=0. ***** -*****1***** -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -***** Signal mux_1level_tapbuf_size2[31]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[31]->in[0] mux_1level_tapbuf_size2[31]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[31]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[31]->in[1] mux_1level_tapbuf_size2[31]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[31] gvdd_mux_1level_tapbuf_size2[31] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[553] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[553] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[553] when v(mux_1level_tapbuf_size2[31]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[553] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[553] when v(mux_1level_tapbuf_size2[31]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[553] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[31]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[553] param='mux_1level_tapbuf_size2[31]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[31]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[31]_energy_per_cycle param='mux_1level_tapbuf_size2[31]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[553] param='mux_1level_tapbuf_size2[31]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[553] param='dynamic_power_sb_mux[1][0]_rrnode[553]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[553] avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='start_rise_sb_mux[1][0]_rrnode[553]' to='start_rise_sb_mux[1][0]_rrnode[553]+switch_rise_sb_mux[1][0]_rrnode[553]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[553] avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='start_fall_sb_mux[1][0]_rrnode[553]' to='start_fall_sb_mux[1][0]_rrnode[553]+switch_fall_sb_mux[1][0]_rrnode[553]' -.meas tran sum_leakage_power_mux[0to31] -+ param='sum_leakage_power_mux[0to30]+leakage_sb_mux[1][0]_rrnode[553]' -.meas tran sum_energy_per_cycle_mux[0to31] -+ param='sum_energy_per_cycle_mux[0to30]+energy_per_cycle_sb_mux[1][0]_rrnode[553]' -***** Load for rr_node[553] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=62, type=5 ***** -Xchan_mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[80]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to31] -+ param='sum_leakage_power_sb_mux[0to30]+leakage_sb_mux[1][0]_rrnode[553]' -.meas tran sum_energy_per_cycle_sb_mux[0to31] -+ param='sum_energy_per_cycle_sb_mux[0to30]+energy_per_cycle_sb_mux[1][0]_rrnode[553]' -Xmux_1level_tapbuf_size2[32] mux_1level_tapbuf_size2[32]->in[0] mux_1level_tapbuf_size2[32]->in[1] mux_1level_tapbuf_size2[32]->out sram[42]->outb sram[42]->out gvdd_mux_1level_tapbuf_size2[32] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[32], level=1, select_path_id=0. ***** -*****1***** -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -***** Signal mux_1level_tapbuf_size2[32]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[32]->in[0] mux_1level_tapbuf_size2[32]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[32]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[32]->in[1] mux_1level_tapbuf_size2[32]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[32] gvdd_mux_1level_tapbuf_size2[32] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[555] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[555] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[555] when v(mux_1level_tapbuf_size2[32]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[555] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[555] when v(mux_1level_tapbuf_size2[32]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[555] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[32]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[555] param='mux_1level_tapbuf_size2[32]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[32]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[32]_energy_per_cycle param='mux_1level_tapbuf_size2[32]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[555] param='mux_1level_tapbuf_size2[32]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[555] param='dynamic_power_sb_mux[1][0]_rrnode[555]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[555] avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='start_rise_sb_mux[1][0]_rrnode[555]' to='start_rise_sb_mux[1][0]_rrnode[555]+switch_rise_sb_mux[1][0]_rrnode[555]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[555] avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='start_fall_sb_mux[1][0]_rrnode[555]' to='start_fall_sb_mux[1][0]_rrnode[555]+switch_fall_sb_mux[1][0]_rrnode[555]' -.meas tran sum_leakage_power_mux[0to32] -+ param='sum_leakage_power_mux[0to31]+leakage_sb_mux[1][0]_rrnode[555]' -.meas tran sum_energy_per_cycle_mux[0to32] -+ param='sum_energy_per_cycle_mux[0to31]+energy_per_cycle_sb_mux[1][0]_rrnode[555]' -***** Load for rr_node[555] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=64, type=5 ***** -Xchan_mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[83]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to32] -+ param='sum_leakage_power_sb_mux[0to31]+leakage_sb_mux[1][0]_rrnode[555]' -.meas tran sum_energy_per_cycle_sb_mux[0to32] -+ param='sum_energy_per_cycle_sb_mux[0to31]+energy_per_cycle_sb_mux[1][0]_rrnode[555]' -Xmux_1level_tapbuf_size2[33] mux_1level_tapbuf_size2[33]->in[0] mux_1level_tapbuf_size2[33]->in[1] mux_1level_tapbuf_size2[33]->out sram[43]->outb sram[43]->out gvdd_mux_1level_tapbuf_size2[33] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[33], level=1, select_path_id=0. ***** -*****1***** -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -***** Signal mux_1level_tapbuf_size2[33]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[33]->in[0] mux_1level_tapbuf_size2[33]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[33]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[33]->in[1] mux_1level_tapbuf_size2[33]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[33] gvdd_mux_1level_tapbuf_size2[33] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[557] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[557] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[557] when v(mux_1level_tapbuf_size2[33]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[557] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[557] when v(mux_1level_tapbuf_size2[33]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[557] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[33]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[557] param='mux_1level_tapbuf_size2[33]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[33]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[33]_energy_per_cycle param='mux_1level_tapbuf_size2[33]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[557] param='mux_1level_tapbuf_size2[33]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[557] param='dynamic_power_sb_mux[1][0]_rrnode[557]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[557] avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='start_rise_sb_mux[1][0]_rrnode[557]' to='start_rise_sb_mux[1][0]_rrnode[557]+switch_rise_sb_mux[1][0]_rrnode[557]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[557] avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='start_fall_sb_mux[1][0]_rrnode[557]' to='start_fall_sb_mux[1][0]_rrnode[557]+switch_fall_sb_mux[1][0]_rrnode[557]' -.meas tran sum_leakage_power_mux[0to33] -+ param='sum_leakage_power_mux[0to32]+leakage_sb_mux[1][0]_rrnode[557]' -.meas tran sum_energy_per_cycle_mux[0to33] -+ param='sum_energy_per_cycle_mux[0to32]+energy_per_cycle_sb_mux[1][0]_rrnode[557]' -***** Load for rr_node[557] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=66, type=5 ***** -Xchan_mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[86]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to33] -+ param='sum_leakage_power_sb_mux[0to32]+leakage_sb_mux[1][0]_rrnode[557]' -.meas tran sum_energy_per_cycle_sb_mux[0to33] -+ param='sum_energy_per_cycle_sb_mux[0to32]+energy_per_cycle_sb_mux[1][0]_rrnode[557]' -Xmux_1level_tapbuf_size2[34] mux_1level_tapbuf_size2[34]->in[0] mux_1level_tapbuf_size2[34]->in[1] mux_1level_tapbuf_size2[34]->out sram[44]->outb sram[44]->out gvdd_mux_1level_tapbuf_size2[34] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[34], level=1, select_path_id=0. ***** -*****1***** -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -***** Signal mux_1level_tapbuf_size2[34]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[34]->in[0] mux_1level_tapbuf_size2[34]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[34]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[34]->in[1] mux_1level_tapbuf_size2[34]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[34] gvdd_mux_1level_tapbuf_size2[34] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[559] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[559] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[559] when v(mux_1level_tapbuf_size2[34]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[559] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[559] when v(mux_1level_tapbuf_size2[34]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[559] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[34]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[559] param='mux_1level_tapbuf_size2[34]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[34]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[34]_energy_per_cycle param='mux_1level_tapbuf_size2[34]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[559] param='mux_1level_tapbuf_size2[34]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[559] param='dynamic_power_sb_mux[1][0]_rrnode[559]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[559] avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='start_rise_sb_mux[1][0]_rrnode[559]' to='start_rise_sb_mux[1][0]_rrnode[559]+switch_rise_sb_mux[1][0]_rrnode[559]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[559] avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='start_fall_sb_mux[1][0]_rrnode[559]' to='start_fall_sb_mux[1][0]_rrnode[559]+switch_fall_sb_mux[1][0]_rrnode[559]' -.meas tran sum_leakage_power_mux[0to34] -+ param='sum_leakage_power_mux[0to33]+leakage_sb_mux[1][0]_rrnode[559]' -.meas tran sum_energy_per_cycle_mux[0to34] -+ param='sum_energy_per_cycle_mux[0to33]+energy_per_cycle_sb_mux[1][0]_rrnode[559]' -***** Load for rr_node[559] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=68, type=5 ***** -Xchan_mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[89]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to34] -+ param='sum_leakage_power_sb_mux[0to33]+leakage_sb_mux[1][0]_rrnode[559]' -.meas tran sum_energy_per_cycle_sb_mux[0to34] -+ param='sum_energy_per_cycle_sb_mux[0to33]+energy_per_cycle_sb_mux[1][0]_rrnode[559]' -Xmux_1level_tapbuf_size2[35] mux_1level_tapbuf_size2[35]->in[0] mux_1level_tapbuf_size2[35]->in[1] mux_1level_tapbuf_size2[35]->out sram[45]->outb sram[45]->out gvdd_mux_1level_tapbuf_size2[35] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[35], level=1, select_path_id=0. ***** -*****1***** -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -***** Signal mux_1level_tapbuf_size2[35]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[35]->in[0] mux_1level_tapbuf_size2[35]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[35]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[35]->in[1] mux_1level_tapbuf_size2[35]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[35] gvdd_mux_1level_tapbuf_size2[35] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[561] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[561] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[561] when v(mux_1level_tapbuf_size2[35]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[561] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[561] when v(mux_1level_tapbuf_size2[35]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[561] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[35]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[561] param='mux_1level_tapbuf_size2[35]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[35]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[35]_energy_per_cycle param='mux_1level_tapbuf_size2[35]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[561] param='mux_1level_tapbuf_size2[35]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[561] param='dynamic_power_sb_mux[1][0]_rrnode[561]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[561] avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='start_rise_sb_mux[1][0]_rrnode[561]' to='start_rise_sb_mux[1][0]_rrnode[561]+switch_rise_sb_mux[1][0]_rrnode[561]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[561] avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='start_fall_sb_mux[1][0]_rrnode[561]' to='start_fall_sb_mux[1][0]_rrnode[561]+switch_fall_sb_mux[1][0]_rrnode[561]' -.meas tran sum_leakage_power_mux[0to35] -+ param='sum_leakage_power_mux[0to34]+leakage_sb_mux[1][0]_rrnode[561]' -.meas tran sum_energy_per_cycle_mux[0to35] -+ param='sum_energy_per_cycle_mux[0to34]+energy_per_cycle_sb_mux[1][0]_rrnode[561]' -***** Load for rr_node[561] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=70, type=5 ***** -Xchan_mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[91]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to35] -+ param='sum_leakage_power_sb_mux[0to34]+leakage_sb_mux[1][0]_rrnode[561]' -.meas tran sum_energy_per_cycle_sb_mux[0to35] -+ param='sum_energy_per_cycle_sb_mux[0to34]+energy_per_cycle_sb_mux[1][0]_rrnode[561]' -Xmux_1level_tapbuf_size2[36] mux_1level_tapbuf_size2[36]->in[0] mux_1level_tapbuf_size2[36]->in[1] mux_1level_tapbuf_size2[36]->out sram[46]->outb sram[46]->out gvdd_mux_1level_tapbuf_size2[36] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[36], level=1, select_path_id=0. ***** -*****1***** -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -***** Signal mux_1level_tapbuf_size2[36]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[36]->in[0] mux_1level_tapbuf_size2[36]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[36]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[36]->in[1] mux_1level_tapbuf_size2[36]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[36] gvdd_mux_1level_tapbuf_size2[36] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[563] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[563] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[563] when v(mux_1level_tapbuf_size2[36]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[563] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[563] when v(mux_1level_tapbuf_size2[36]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[563] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[36]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[563] param='mux_1level_tapbuf_size2[36]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[36]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[36]_energy_per_cycle param='mux_1level_tapbuf_size2[36]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[563] param='mux_1level_tapbuf_size2[36]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[563] param='dynamic_power_sb_mux[1][0]_rrnode[563]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[563] avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='start_rise_sb_mux[1][0]_rrnode[563]' to='start_rise_sb_mux[1][0]_rrnode[563]+switch_rise_sb_mux[1][0]_rrnode[563]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[563] avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='start_fall_sb_mux[1][0]_rrnode[563]' to='start_fall_sb_mux[1][0]_rrnode[563]+switch_fall_sb_mux[1][0]_rrnode[563]' -.meas tran sum_leakage_power_mux[0to36] -+ param='sum_leakage_power_mux[0to35]+leakage_sb_mux[1][0]_rrnode[563]' -.meas tran sum_energy_per_cycle_mux[0to36] -+ param='sum_energy_per_cycle_mux[0to35]+energy_per_cycle_sb_mux[1][0]_rrnode[563]' -***** Load for rr_node[563] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=72, type=5 ***** -Xchan_mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[94]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to36] -+ param='sum_leakage_power_sb_mux[0to35]+leakage_sb_mux[1][0]_rrnode[563]' -.meas tran sum_energy_per_cycle_sb_mux[0to36] -+ param='sum_energy_per_cycle_sb_mux[0to35]+energy_per_cycle_sb_mux[1][0]_rrnode[563]' -Xmux_1level_tapbuf_size2[37] mux_1level_tapbuf_size2[37]->in[0] mux_1level_tapbuf_size2[37]->in[1] mux_1level_tapbuf_size2[37]->out sram[47]->outb sram[47]->out gvdd_mux_1level_tapbuf_size2[37] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[37], level=1, select_path_id=0. ***** -*****1***** -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -***** Signal mux_1level_tapbuf_size2[37]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[37]->in[0] mux_1level_tapbuf_size2[37]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[37]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[37]->in[1] mux_1level_tapbuf_size2[37]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[37] gvdd_mux_1level_tapbuf_size2[37] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[565] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[565] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[565] when v(mux_1level_tapbuf_size2[37]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[565] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[565] when v(mux_1level_tapbuf_size2[37]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[565] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[37]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[565] param='mux_1level_tapbuf_size2[37]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[37]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[37]_energy_per_cycle param='mux_1level_tapbuf_size2[37]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[565] param='mux_1level_tapbuf_size2[37]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[565] param='dynamic_power_sb_mux[1][0]_rrnode[565]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[565] avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='start_rise_sb_mux[1][0]_rrnode[565]' to='start_rise_sb_mux[1][0]_rrnode[565]+switch_rise_sb_mux[1][0]_rrnode[565]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[565] avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='start_fall_sb_mux[1][0]_rrnode[565]' to='start_fall_sb_mux[1][0]_rrnode[565]+switch_fall_sb_mux[1][0]_rrnode[565]' -.meas tran sum_leakage_power_mux[0to37] -+ param='sum_leakage_power_mux[0to36]+leakage_sb_mux[1][0]_rrnode[565]' -.meas tran sum_energy_per_cycle_mux[0to37] -+ param='sum_energy_per_cycle_mux[0to36]+energy_per_cycle_sb_mux[1][0]_rrnode[565]' -***** Load for rr_node[565] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=74, type=5 ***** -Xchan_mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[96]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to37] -+ param='sum_leakage_power_sb_mux[0to36]+leakage_sb_mux[1][0]_rrnode[565]' -.meas tran sum_energy_per_cycle_sb_mux[0to37] -+ param='sum_energy_per_cycle_sb_mux[0to36]+energy_per_cycle_sb_mux[1][0]_rrnode[565]' -Xmux_1level_tapbuf_size2[38] mux_1level_tapbuf_size2[38]->in[0] mux_1level_tapbuf_size2[38]->in[1] mux_1level_tapbuf_size2[38]->out sram[48]->outb sram[48]->out gvdd_mux_1level_tapbuf_size2[38] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[38], level=1, select_path_id=0. ***** -*****1***** -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -***** Signal mux_1level_tapbuf_size2[38]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[38]->in[0] mux_1level_tapbuf_size2[38]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[38]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[38]->in[1] mux_1level_tapbuf_size2[38]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[38] gvdd_mux_1level_tapbuf_size2[38] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[567] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[567] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[567] when v(mux_1level_tapbuf_size2[38]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[567] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[567] when v(mux_1level_tapbuf_size2[38]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[567] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[38]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[567] param='mux_1level_tapbuf_size2[38]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[38]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[38]_energy_per_cycle param='mux_1level_tapbuf_size2[38]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[567] param='mux_1level_tapbuf_size2[38]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[567] param='dynamic_power_sb_mux[1][0]_rrnode[567]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[567] avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='start_rise_sb_mux[1][0]_rrnode[567]' to='start_rise_sb_mux[1][0]_rrnode[567]+switch_rise_sb_mux[1][0]_rrnode[567]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[567] avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='start_fall_sb_mux[1][0]_rrnode[567]' to='start_fall_sb_mux[1][0]_rrnode[567]+switch_fall_sb_mux[1][0]_rrnode[567]' -.meas tran sum_leakage_power_mux[0to38] -+ param='sum_leakage_power_mux[0to37]+leakage_sb_mux[1][0]_rrnode[567]' -.meas tran sum_energy_per_cycle_mux[0to38] -+ param='sum_energy_per_cycle_mux[0to37]+energy_per_cycle_sb_mux[1][0]_rrnode[567]' -***** Load for rr_node[567] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=76, type=5 ***** -Xchan_mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[99]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to38] -+ param='sum_leakage_power_sb_mux[0to37]+leakage_sb_mux[1][0]_rrnode[567]' -.meas tran sum_energy_per_cycle_sb_mux[0to38] -+ param='sum_energy_per_cycle_sb_mux[0to37]+energy_per_cycle_sb_mux[1][0]_rrnode[567]' -Xmux_1level_tapbuf_size2[39] mux_1level_tapbuf_size2[39]->in[0] mux_1level_tapbuf_size2[39]->in[1] mux_1level_tapbuf_size2[39]->out sram[49]->outb sram[49]->out gvdd_mux_1level_tapbuf_size2[39] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[39], level=1, select_path_id=0. ***** -*****1***** -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -***** Signal mux_1level_tapbuf_size2[39]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[39]->in[0] mux_1level_tapbuf_size2[39]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[39]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[39]->in[1] mux_1level_tapbuf_size2[39]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[39] gvdd_mux_1level_tapbuf_size2[39] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[569] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[569] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[569] when v(mux_1level_tapbuf_size2[39]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[569] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[569] when v(mux_1level_tapbuf_size2[39]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[569] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[39]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[569] param='mux_1level_tapbuf_size2[39]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[39]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[39]_energy_per_cycle param='mux_1level_tapbuf_size2[39]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[569] param='mux_1level_tapbuf_size2[39]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[569] param='dynamic_power_sb_mux[1][0]_rrnode[569]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[569] avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='start_rise_sb_mux[1][0]_rrnode[569]' to='start_rise_sb_mux[1][0]_rrnode[569]+switch_rise_sb_mux[1][0]_rrnode[569]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[569] avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='start_fall_sb_mux[1][0]_rrnode[569]' to='start_fall_sb_mux[1][0]_rrnode[569]+switch_fall_sb_mux[1][0]_rrnode[569]' -.meas tran sum_leakage_power_mux[0to39] -+ param='sum_leakage_power_mux[0to38]+leakage_sb_mux[1][0]_rrnode[569]' -.meas tran sum_energy_per_cycle_mux[0to39] -+ param='sum_energy_per_cycle_mux[0to38]+energy_per_cycle_sb_mux[1][0]_rrnode[569]' -***** Load for rr_node[569] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=78, type=5 ***** -Xchan_mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[102]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to39] -+ param='sum_leakage_power_sb_mux[0to38]+leakage_sb_mux[1][0]_rrnode[569]' -.meas tran sum_energy_per_cycle_sb_mux[0to39] -+ param='sum_energy_per_cycle_sb_mux[0to38]+energy_per_cycle_sb_mux[1][0]_rrnode[569]' -Xmux_1level_tapbuf_size2[40] mux_1level_tapbuf_size2[40]->in[0] mux_1level_tapbuf_size2[40]->in[1] mux_1level_tapbuf_size2[40]->out sram[50]->outb sram[50]->out gvdd_mux_1level_tapbuf_size2[40] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[40], level=1, select_path_id=0. ***** -*****1***** -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -***** Signal mux_1level_tapbuf_size2[40]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[40]->in[0] mux_1level_tapbuf_size2[40]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[40]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[40]->in[1] mux_1level_tapbuf_size2[40]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[40] gvdd_mux_1level_tapbuf_size2[40] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[571] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[571] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[571] when v(mux_1level_tapbuf_size2[40]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[571] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[571] when v(mux_1level_tapbuf_size2[40]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[571] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[40]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[571] param='mux_1level_tapbuf_size2[40]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[40]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[40]_energy_per_cycle param='mux_1level_tapbuf_size2[40]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[571] param='mux_1level_tapbuf_size2[40]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[571] param='dynamic_power_sb_mux[1][0]_rrnode[571]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[571] avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='start_rise_sb_mux[1][0]_rrnode[571]' to='start_rise_sb_mux[1][0]_rrnode[571]+switch_rise_sb_mux[1][0]_rrnode[571]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[571] avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='start_fall_sb_mux[1][0]_rrnode[571]' to='start_fall_sb_mux[1][0]_rrnode[571]+switch_fall_sb_mux[1][0]_rrnode[571]' -.meas tran sum_leakage_power_mux[0to40] -+ param='sum_leakage_power_mux[0to39]+leakage_sb_mux[1][0]_rrnode[571]' -.meas tran sum_energy_per_cycle_mux[0to40] -+ param='sum_energy_per_cycle_mux[0to39]+energy_per_cycle_sb_mux[1][0]_rrnode[571]' -***** Load for rr_node[571] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=80, type=5 ***** -Xchan_mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[104]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to40] -+ param='sum_leakage_power_sb_mux[0to39]+leakage_sb_mux[1][0]_rrnode[571]' -.meas tran sum_energy_per_cycle_sb_mux[0to40] -+ param='sum_energy_per_cycle_sb_mux[0to39]+energy_per_cycle_sb_mux[1][0]_rrnode[571]' -Xmux_1level_tapbuf_size2[41] mux_1level_tapbuf_size2[41]->in[0] mux_1level_tapbuf_size2[41]->in[1] mux_1level_tapbuf_size2[41]->out sram[51]->outb sram[51]->out gvdd_mux_1level_tapbuf_size2[41] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[41], level=1, select_path_id=0. ***** -*****1***** -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -***** Signal mux_1level_tapbuf_size2[41]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[41]->in[0] mux_1level_tapbuf_size2[41]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[41]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[41]->in[1] mux_1level_tapbuf_size2[41]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[41] gvdd_mux_1level_tapbuf_size2[41] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[573] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[573] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[573] when v(mux_1level_tapbuf_size2[41]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[573] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[573] when v(mux_1level_tapbuf_size2[41]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[573] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[41]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[573] param='mux_1level_tapbuf_size2[41]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[41]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[41]_energy_per_cycle param='mux_1level_tapbuf_size2[41]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[573] param='mux_1level_tapbuf_size2[41]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[573] param='dynamic_power_sb_mux[1][0]_rrnode[573]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[573] avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='start_rise_sb_mux[1][0]_rrnode[573]' to='start_rise_sb_mux[1][0]_rrnode[573]+switch_rise_sb_mux[1][0]_rrnode[573]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[573] avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='start_fall_sb_mux[1][0]_rrnode[573]' to='start_fall_sb_mux[1][0]_rrnode[573]+switch_fall_sb_mux[1][0]_rrnode[573]' -.meas tran sum_leakage_power_mux[0to41] -+ param='sum_leakage_power_mux[0to40]+leakage_sb_mux[1][0]_rrnode[573]' -.meas tran sum_energy_per_cycle_mux[0to41] -+ param='sum_energy_per_cycle_mux[0to40]+energy_per_cycle_sb_mux[1][0]_rrnode[573]' -***** Load for rr_node[573] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=82, type=5 ***** -Xchan_mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[107]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to41] -+ param='sum_leakage_power_sb_mux[0to40]+leakage_sb_mux[1][0]_rrnode[573]' -.meas tran sum_energy_per_cycle_sb_mux[0to41] -+ param='sum_energy_per_cycle_sb_mux[0to40]+energy_per_cycle_sb_mux[1][0]_rrnode[573]' -Xmux_1level_tapbuf_size2[42] mux_1level_tapbuf_size2[42]->in[0] mux_1level_tapbuf_size2[42]->in[1] mux_1level_tapbuf_size2[42]->out sram[52]->outb sram[52]->out gvdd_mux_1level_tapbuf_size2[42] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[42], level=1, select_path_id=0. ***** -*****1***** -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -***** Signal mux_1level_tapbuf_size2[42]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[42]->in[0] mux_1level_tapbuf_size2[42]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[42]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[42]->in[1] mux_1level_tapbuf_size2[42]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[42] gvdd_mux_1level_tapbuf_size2[42] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[575] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[575] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[575] when v(mux_1level_tapbuf_size2[42]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[575] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[575] when v(mux_1level_tapbuf_size2[42]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[575] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[42]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[575] param='mux_1level_tapbuf_size2[42]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[42]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[42]_energy_per_cycle param='mux_1level_tapbuf_size2[42]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[575] param='mux_1level_tapbuf_size2[42]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[575] param='dynamic_power_sb_mux[1][0]_rrnode[575]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[575] avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='start_rise_sb_mux[1][0]_rrnode[575]' to='start_rise_sb_mux[1][0]_rrnode[575]+switch_rise_sb_mux[1][0]_rrnode[575]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[575] avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='start_fall_sb_mux[1][0]_rrnode[575]' to='start_fall_sb_mux[1][0]_rrnode[575]+switch_fall_sb_mux[1][0]_rrnode[575]' -.meas tran sum_leakage_power_mux[0to42] -+ param='sum_leakage_power_mux[0to41]+leakage_sb_mux[1][0]_rrnode[575]' -.meas tran sum_energy_per_cycle_mux[0to42] -+ param='sum_energy_per_cycle_mux[0to41]+energy_per_cycle_sb_mux[1][0]_rrnode[575]' -***** Load for rr_node[575] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=84, type=5 ***** -Xchan_mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[109]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to42] -+ param='sum_leakage_power_sb_mux[0to41]+leakage_sb_mux[1][0]_rrnode[575]' -.meas tran sum_energy_per_cycle_sb_mux[0to42] -+ param='sum_energy_per_cycle_sb_mux[0to41]+energy_per_cycle_sb_mux[1][0]_rrnode[575]' -Xmux_1level_tapbuf_size2[43] mux_1level_tapbuf_size2[43]->in[0] mux_1level_tapbuf_size2[43]->in[1] mux_1level_tapbuf_size2[43]->out sram[53]->outb sram[53]->out gvdd_mux_1level_tapbuf_size2[43] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[43], level=1, select_path_id=0. ***** -*****1***** -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -***** Signal mux_1level_tapbuf_size2[43]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[43]->in[0] mux_1level_tapbuf_size2[43]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[43]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[43]->in[1] mux_1level_tapbuf_size2[43]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[43] gvdd_mux_1level_tapbuf_size2[43] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[577] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[577] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[577] when v(mux_1level_tapbuf_size2[43]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[577] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[577] when v(mux_1level_tapbuf_size2[43]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[577] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[43]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[577] param='mux_1level_tapbuf_size2[43]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[43]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[43]_energy_per_cycle param='mux_1level_tapbuf_size2[43]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[577] param='mux_1level_tapbuf_size2[43]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[577] param='dynamic_power_sb_mux[1][0]_rrnode[577]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[577] avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='start_rise_sb_mux[1][0]_rrnode[577]' to='start_rise_sb_mux[1][0]_rrnode[577]+switch_rise_sb_mux[1][0]_rrnode[577]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[577] avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='start_fall_sb_mux[1][0]_rrnode[577]' to='start_fall_sb_mux[1][0]_rrnode[577]+switch_fall_sb_mux[1][0]_rrnode[577]' -.meas tran sum_leakage_power_mux[0to43] -+ param='sum_leakage_power_mux[0to42]+leakage_sb_mux[1][0]_rrnode[577]' -.meas tran sum_energy_per_cycle_mux[0to43] -+ param='sum_energy_per_cycle_mux[0to42]+energy_per_cycle_sb_mux[1][0]_rrnode[577]' -***** Load for rr_node[577] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=86, type=5 ***** -Xchan_mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[112]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to43] -+ param='sum_leakage_power_sb_mux[0to42]+leakage_sb_mux[1][0]_rrnode[577]' -.meas tran sum_energy_per_cycle_sb_mux[0to43] -+ param='sum_energy_per_cycle_sb_mux[0to42]+energy_per_cycle_sb_mux[1][0]_rrnode[577]' -Xmux_1level_tapbuf_size2[44] mux_1level_tapbuf_size2[44]->in[0] mux_1level_tapbuf_size2[44]->in[1] mux_1level_tapbuf_size2[44]->out sram[54]->outb sram[54]->out gvdd_mux_1level_tapbuf_size2[44] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[44], level=1, select_path_id=0. ***** -*****1***** -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -***** Signal mux_1level_tapbuf_size2[44]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[44]->in[0] mux_1level_tapbuf_size2[44]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[44]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[44]->in[1] mux_1level_tapbuf_size2[44]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[44] gvdd_mux_1level_tapbuf_size2[44] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[579] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[579] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[579] when v(mux_1level_tapbuf_size2[44]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[579] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[579] when v(mux_1level_tapbuf_size2[44]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[579] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[44]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[579] param='mux_1level_tapbuf_size2[44]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[44]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[44]_energy_per_cycle param='mux_1level_tapbuf_size2[44]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[579] param='mux_1level_tapbuf_size2[44]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[579] param='dynamic_power_sb_mux[1][0]_rrnode[579]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[579] avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='start_rise_sb_mux[1][0]_rrnode[579]' to='start_rise_sb_mux[1][0]_rrnode[579]+switch_rise_sb_mux[1][0]_rrnode[579]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[579] avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='start_fall_sb_mux[1][0]_rrnode[579]' to='start_fall_sb_mux[1][0]_rrnode[579]+switch_fall_sb_mux[1][0]_rrnode[579]' -.meas tran sum_leakage_power_mux[0to44] -+ param='sum_leakage_power_mux[0to43]+leakage_sb_mux[1][0]_rrnode[579]' -.meas tran sum_energy_per_cycle_mux[0to44] -+ param='sum_energy_per_cycle_mux[0to43]+energy_per_cycle_sb_mux[1][0]_rrnode[579]' -***** Load for rr_node[579] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=88, type=5 ***** -Xchan_mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[115]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to44] -+ param='sum_leakage_power_sb_mux[0to43]+leakage_sb_mux[1][0]_rrnode[579]' -.meas tran sum_energy_per_cycle_sb_mux[0to44] -+ param='sum_energy_per_cycle_sb_mux[0to43]+energy_per_cycle_sb_mux[1][0]_rrnode[579]' -Xmux_1level_tapbuf_size2[45] mux_1level_tapbuf_size2[45]->in[0] mux_1level_tapbuf_size2[45]->in[1] mux_1level_tapbuf_size2[45]->out sram[55]->outb sram[55]->out gvdd_mux_1level_tapbuf_size2[45] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[45], level=1, select_path_id=0. ***** -*****1***** -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -***** Signal mux_1level_tapbuf_size2[45]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[45]->in[0] mux_1level_tapbuf_size2[45]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[45]->in[1] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[45]->in[1] mux_1level_tapbuf_size2[45]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[45] gvdd_mux_1level_tapbuf_size2[45] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[581] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[581] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[581] when v(mux_1level_tapbuf_size2[45]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[581] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[581] when v(mux_1level_tapbuf_size2[45]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[581] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[45]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[581] param='mux_1level_tapbuf_size2[45]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[45]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[45]_energy_per_cycle param='mux_1level_tapbuf_size2[45]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[581] param='mux_1level_tapbuf_size2[45]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[581] param='dynamic_power_sb_mux[1][0]_rrnode[581]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[581] avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='start_rise_sb_mux[1][0]_rrnode[581]' to='start_rise_sb_mux[1][0]_rrnode[581]+switch_rise_sb_mux[1][0]_rrnode[581]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[581] avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='start_fall_sb_mux[1][0]_rrnode[581]' to='start_fall_sb_mux[1][0]_rrnode[581]+switch_fall_sb_mux[1][0]_rrnode[581]' -.meas tran sum_leakage_power_mux[0to45] -+ param='sum_leakage_power_mux[0to44]+leakage_sb_mux[1][0]_rrnode[581]' -.meas tran sum_energy_per_cycle_mux[0to45] -+ param='sum_energy_per_cycle_mux[0to44]+energy_per_cycle_sb_mux[1][0]_rrnode[581]' -***** Load for rr_node[581] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=90, type=5 ***** -Xchan_mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[117]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to45] -+ param='sum_leakage_power_sb_mux[0to44]+leakage_sb_mux[1][0]_rrnode[581]' -.meas tran sum_energy_per_cycle_sb_mux[0to45] -+ param='sum_energy_per_cycle_sb_mux[0to44]+energy_per_cycle_sb_mux[1][0]_rrnode[581]' -Xmux_1level_tapbuf_size2[46] mux_1level_tapbuf_size2[46]->in[0] mux_1level_tapbuf_size2[46]->in[1] mux_1level_tapbuf_size2[46]->out sram[56]->outb sram[56]->out gvdd_mux_1level_tapbuf_size2[46] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[46], level=1, select_path_id=0. ***** -*****1***** -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -***** Signal mux_1level_tapbuf_size2[46]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[46]->in[0] mux_1level_tapbuf_size2[46]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[46]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[46]->in[1] mux_1level_tapbuf_size2[46]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[46] gvdd_mux_1level_tapbuf_size2[46] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[583] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[583] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[583] when v(mux_1level_tapbuf_size2[46]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[583] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[583] when v(mux_1level_tapbuf_size2[46]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[583] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[46]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[583] param='mux_1level_tapbuf_size2[46]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[46]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[46]_energy_per_cycle param='mux_1level_tapbuf_size2[46]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[583] param='mux_1level_tapbuf_size2[46]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[583] param='dynamic_power_sb_mux[1][0]_rrnode[583]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[583] avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='start_rise_sb_mux[1][0]_rrnode[583]' to='start_rise_sb_mux[1][0]_rrnode[583]+switch_rise_sb_mux[1][0]_rrnode[583]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[583] avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='start_fall_sb_mux[1][0]_rrnode[583]' to='start_fall_sb_mux[1][0]_rrnode[583]+switch_fall_sb_mux[1][0]_rrnode[583]' -.meas tran sum_leakage_power_mux[0to46] -+ param='sum_leakage_power_mux[0to45]+leakage_sb_mux[1][0]_rrnode[583]' -.meas tran sum_energy_per_cycle_mux[0to46] -+ param='sum_energy_per_cycle_mux[0to45]+energy_per_cycle_sb_mux[1][0]_rrnode[583]' -***** Load for rr_node[583] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=92, type=5 ***** -Xchan_mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[120]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to46] -+ param='sum_leakage_power_sb_mux[0to45]+leakage_sb_mux[1][0]_rrnode[583]' -.meas tran sum_energy_per_cycle_sb_mux[0to46] -+ param='sum_energy_per_cycle_sb_mux[0to45]+energy_per_cycle_sb_mux[1][0]_rrnode[583]' -Xmux_1level_tapbuf_size2[47] mux_1level_tapbuf_size2[47]->in[0] mux_1level_tapbuf_size2[47]->in[1] mux_1level_tapbuf_size2[47]->out sram[57]->outb sram[57]->out gvdd_mux_1level_tapbuf_size2[47] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[47], level=1, select_path_id=0. ***** -*****1***** -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -***** Signal mux_1level_tapbuf_size2[47]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[47]->in[0] mux_1level_tapbuf_size2[47]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[47]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[47]->in[1] mux_1level_tapbuf_size2[47]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[47] gvdd_mux_1level_tapbuf_size2[47] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[585] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[585] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[585] when v(mux_1level_tapbuf_size2[47]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[585] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[585] when v(mux_1level_tapbuf_size2[47]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[585] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[47]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[585] param='mux_1level_tapbuf_size2[47]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[47]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[47]_energy_per_cycle param='mux_1level_tapbuf_size2[47]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[585] param='mux_1level_tapbuf_size2[47]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[585] param='dynamic_power_sb_mux[1][0]_rrnode[585]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[585] avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='start_rise_sb_mux[1][0]_rrnode[585]' to='start_rise_sb_mux[1][0]_rrnode[585]+switch_rise_sb_mux[1][0]_rrnode[585]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[585] avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='start_fall_sb_mux[1][0]_rrnode[585]' to='start_fall_sb_mux[1][0]_rrnode[585]+switch_fall_sb_mux[1][0]_rrnode[585]' -.meas tran sum_leakage_power_mux[0to47] -+ param='sum_leakage_power_mux[0to46]+leakage_sb_mux[1][0]_rrnode[585]' -.meas tran sum_energy_per_cycle_mux[0to47] -+ param='sum_energy_per_cycle_mux[0to46]+energy_per_cycle_sb_mux[1][0]_rrnode[585]' -***** Load for rr_node[585] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=94, type=5 ***** -Xchan_mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[122]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to47] -+ param='sum_leakage_power_sb_mux[0to46]+leakage_sb_mux[1][0]_rrnode[585]' -.meas tran sum_energy_per_cycle_sb_mux[0to47] -+ param='sum_energy_per_cycle_sb_mux[0to46]+energy_per_cycle_sb_mux[1][0]_rrnode[585]' -Xmux_1level_tapbuf_size2[48] mux_1level_tapbuf_size2[48]->in[0] mux_1level_tapbuf_size2[48]->in[1] mux_1level_tapbuf_size2[48]->out sram[58]->outb sram[58]->out gvdd_mux_1level_tapbuf_size2[48] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[48], level=1, select_path_id=0. ***** -*****1***** -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -***** Signal mux_1level_tapbuf_size2[48]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[48]->in[0] mux_1level_tapbuf_size2[48]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[48]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[48]->in[1] mux_1level_tapbuf_size2[48]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[48] gvdd_mux_1level_tapbuf_size2[48] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[587] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[587] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[587] when v(mux_1level_tapbuf_size2[48]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[587] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[587] when v(mux_1level_tapbuf_size2[48]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[587] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[48]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[587] param='mux_1level_tapbuf_size2[48]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[48]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[48]_energy_per_cycle param='mux_1level_tapbuf_size2[48]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[587] param='mux_1level_tapbuf_size2[48]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[587] param='dynamic_power_sb_mux[1][0]_rrnode[587]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[587] avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='start_rise_sb_mux[1][0]_rrnode[587]' to='start_rise_sb_mux[1][0]_rrnode[587]+switch_rise_sb_mux[1][0]_rrnode[587]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[587] avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='start_fall_sb_mux[1][0]_rrnode[587]' to='start_fall_sb_mux[1][0]_rrnode[587]+switch_fall_sb_mux[1][0]_rrnode[587]' -.meas tran sum_leakage_power_mux[0to48] -+ param='sum_leakage_power_mux[0to47]+leakage_sb_mux[1][0]_rrnode[587]' -.meas tran sum_energy_per_cycle_mux[0to48] -+ param='sum_energy_per_cycle_mux[0to47]+energy_per_cycle_sb_mux[1][0]_rrnode[587]' -***** Load for rr_node[587] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=96, type=5 ***** -Xchan_mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[125]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to48] -+ param='sum_leakage_power_sb_mux[0to47]+leakage_sb_mux[1][0]_rrnode[587]' -.meas tran sum_energy_per_cycle_sb_mux[0to48] -+ param='sum_energy_per_cycle_sb_mux[0to47]+energy_per_cycle_sb_mux[1][0]_rrnode[587]' -Xmux_1level_tapbuf_size2[49] mux_1level_tapbuf_size2[49]->in[0] mux_1level_tapbuf_size2[49]->in[1] mux_1level_tapbuf_size2[49]->out sram[59]->outb sram[59]->out gvdd_mux_1level_tapbuf_size2[49] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[49], level=1, select_path_id=0. ***** -*****1***** -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -***** Signal mux_1level_tapbuf_size2[49]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[49]->in[0] mux_1level_tapbuf_size2[49]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[49]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[49]->in[1] mux_1level_tapbuf_size2[49]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[49] gvdd_mux_1level_tapbuf_size2[49] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[589] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[589] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[589] when v(mux_1level_tapbuf_size2[49]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[589] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[589] when v(mux_1level_tapbuf_size2[49]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[589] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[49]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[589] param='mux_1level_tapbuf_size2[49]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[49]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[49]_energy_per_cycle param='mux_1level_tapbuf_size2[49]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[589] param='mux_1level_tapbuf_size2[49]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[589] param='dynamic_power_sb_mux[1][0]_rrnode[589]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[589] avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='start_rise_sb_mux[1][0]_rrnode[589]' to='start_rise_sb_mux[1][0]_rrnode[589]+switch_rise_sb_mux[1][0]_rrnode[589]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[589] avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='start_fall_sb_mux[1][0]_rrnode[589]' to='start_fall_sb_mux[1][0]_rrnode[589]+switch_fall_sb_mux[1][0]_rrnode[589]' -.meas tran sum_leakage_power_mux[0to49] -+ param='sum_leakage_power_mux[0to48]+leakage_sb_mux[1][0]_rrnode[589]' -.meas tran sum_energy_per_cycle_mux[0to49] -+ param='sum_energy_per_cycle_mux[0to48]+energy_per_cycle_sb_mux[1][0]_rrnode[589]' -***** Load for rr_node[589] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=98, type=5 ***** -Xchan_mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[128]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to49] -+ param='sum_leakage_power_sb_mux[0to48]+leakage_sb_mux[1][0]_rrnode[589]' -.meas tran sum_energy_per_cycle_sb_mux[0to49] -+ param='sum_energy_per_cycle_sb_mux[0to48]+energy_per_cycle_sb_mux[1][0]_rrnode[589]' -Xmux_1level_tapbuf_size2[50] mux_1level_tapbuf_size2[50]->in[0] mux_1level_tapbuf_size2[50]->in[1] mux_1level_tapbuf_size2[50]->out sram[60]->outb sram[60]->out gvdd_mux_1level_tapbuf_size2[50] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[50], level=1, select_path_id=0. ***** -*****1***** -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -***** Signal mux_1level_tapbuf_size2[50]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[50]->in[0] mux_1level_tapbuf_size2[50]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[50]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[50]->in[1] mux_1level_tapbuf_size2[50]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[50] gvdd_mux_1level_tapbuf_size2[50] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[192] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[192] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[192] when v(mux_1level_tapbuf_size2[50]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[192] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[192] when v(mux_1level_tapbuf_size2[50]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[192] trig v(mux_1level_tapbuf_size2[50]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[50]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[50]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[192] param='mux_1level_tapbuf_size2[50]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[50]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[50]_energy_per_cycle param='mux_1level_tapbuf_size2[50]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[192] param='mux_1level_tapbuf_size2[50]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[192] param='dynamic_power_sb_mux[1][0]_rrnode[192]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[192] avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from='start_rise_sb_mux[1][0]_rrnode[192]' to='start_rise_sb_mux[1][0]_rrnode[192]+switch_rise_sb_mux[1][0]_rrnode[192]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[192] avg p(Vgvdd_mux_1level_tapbuf_size2[50]) from='start_fall_sb_mux[1][0]_rrnode[192]' to='start_fall_sb_mux[1][0]_rrnode[192]+switch_fall_sb_mux[1][0]_rrnode[192]' -.meas tran sum_leakage_power_mux[0to50] -+ param='sum_leakage_power_mux[0to49]+leakage_sb_mux[1][0]_rrnode[192]' -.meas tran sum_energy_per_cycle_mux[0to50] -+ param='sum_energy_per_cycle_mux[0to49]+energy_per_cycle_sb_mux[1][0]_rrnode[192]' -***** Load for rr_node[192] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=1, type=4 ***** -Xchan_mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out mux_1level_tapbuf_size2[50]->out mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[130]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out mux_1level_tapbuf_size2[50]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[50]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to50] -+ param='sum_leakage_power_sb_mux[0to49]+leakage_sb_mux[1][0]_rrnode[192]' -.meas tran sum_energy_per_cycle_sb_mux[0to50] -+ param='sum_energy_per_cycle_sb_mux[0to49]+energy_per_cycle_sb_mux[1][0]_rrnode[192]' -Xmux_1level_tapbuf_size2[51] mux_1level_tapbuf_size2[51]->in[0] mux_1level_tapbuf_size2[51]->in[1] mux_1level_tapbuf_size2[51]->out sram[61]->outb sram[61]->out gvdd_mux_1level_tapbuf_size2[51] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[51], level=1, select_path_id=0. ***** -*****1***** -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -***** Signal mux_1level_tapbuf_size2[51]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[51]->in[0] mux_1level_tapbuf_size2[51]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[51]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[51]->in[1] mux_1level_tapbuf_size2[51]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[51] gvdd_mux_1level_tapbuf_size2[51] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[194] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[194] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[194] when v(mux_1level_tapbuf_size2[51]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[194] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[194] when v(mux_1level_tapbuf_size2[51]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[194] trig v(mux_1level_tapbuf_size2[51]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[51]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[51]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[194] param='mux_1level_tapbuf_size2[51]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[51]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[51]_energy_per_cycle param='mux_1level_tapbuf_size2[51]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[194] param='mux_1level_tapbuf_size2[51]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[194] param='dynamic_power_sb_mux[1][0]_rrnode[194]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[194] avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from='start_rise_sb_mux[1][0]_rrnode[194]' to='start_rise_sb_mux[1][0]_rrnode[194]+switch_rise_sb_mux[1][0]_rrnode[194]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[194] avg p(Vgvdd_mux_1level_tapbuf_size2[51]) from='start_fall_sb_mux[1][0]_rrnode[194]' to='start_fall_sb_mux[1][0]_rrnode[194]+switch_fall_sb_mux[1][0]_rrnode[194]' -.meas tran sum_leakage_power_mux[0to51] -+ param='sum_leakage_power_mux[0to50]+leakage_sb_mux[1][0]_rrnode[194]' -.meas tran sum_energy_per_cycle_mux[0to51] -+ param='sum_energy_per_cycle_mux[0to50]+energy_per_cycle_sb_mux[1][0]_rrnode[194]' -***** Load for rr_node[194] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=3, type=4 ***** -Xchan_mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out mux_1level_tapbuf_size2[51]->out mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[135]_no0 mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out mux_1level_tapbuf_size2[51]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[51]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to51] -+ param='sum_leakage_power_sb_mux[0to50]+leakage_sb_mux[1][0]_rrnode[194]' -.meas tran sum_energy_per_cycle_sb_mux[0to51] -+ param='sum_energy_per_cycle_sb_mux[0to50]+energy_per_cycle_sb_mux[1][0]_rrnode[194]' -Xmux_1level_tapbuf_size2[52] mux_1level_tapbuf_size2[52]->in[0] mux_1level_tapbuf_size2[52]->in[1] mux_1level_tapbuf_size2[52]->out sram[62]->outb sram[62]->out gvdd_mux_1level_tapbuf_size2[52] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[52], level=1, select_path_id=0. ***** -*****1***** -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -***** Signal mux_1level_tapbuf_size2[52]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[52]->in[0] mux_1level_tapbuf_size2[52]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[52]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[52]->in[1] mux_1level_tapbuf_size2[52]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[52] gvdd_mux_1level_tapbuf_size2[52] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[196] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[196] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[196] when v(mux_1level_tapbuf_size2[52]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[196] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[196] when v(mux_1level_tapbuf_size2[52]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[196] trig v(mux_1level_tapbuf_size2[52]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[52]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[52]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[196] param='mux_1level_tapbuf_size2[52]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[52]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[52]_energy_per_cycle param='mux_1level_tapbuf_size2[52]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[196] param='mux_1level_tapbuf_size2[52]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[196] param='dynamic_power_sb_mux[1][0]_rrnode[196]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[196] avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from='start_rise_sb_mux[1][0]_rrnode[196]' to='start_rise_sb_mux[1][0]_rrnode[196]+switch_rise_sb_mux[1][0]_rrnode[196]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[196] avg p(Vgvdd_mux_1level_tapbuf_size2[52]) from='start_fall_sb_mux[1][0]_rrnode[196]' to='start_fall_sb_mux[1][0]_rrnode[196]+switch_fall_sb_mux[1][0]_rrnode[196]' -.meas tran sum_leakage_power_mux[0to52] -+ param='sum_leakage_power_mux[0to51]+leakage_sb_mux[1][0]_rrnode[196]' -.meas tran sum_energy_per_cycle_mux[0to52] -+ param='sum_energy_per_cycle_mux[0to51]+energy_per_cycle_sb_mux[1][0]_rrnode[196]' -***** Load for rr_node[196] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=5, type=4 ***** -Xchan_mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out mux_1level_tapbuf_size2[52]->out mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[138]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out mux_1level_tapbuf_size2[52]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[52]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to52] -+ param='sum_leakage_power_sb_mux[0to51]+leakage_sb_mux[1][0]_rrnode[196]' -.meas tran sum_energy_per_cycle_sb_mux[0to52] -+ param='sum_energy_per_cycle_sb_mux[0to51]+energy_per_cycle_sb_mux[1][0]_rrnode[196]' -Xmux_1level_tapbuf_size2[53] mux_1level_tapbuf_size2[53]->in[0] mux_1level_tapbuf_size2[53]->in[1] mux_1level_tapbuf_size2[53]->out sram[63]->outb sram[63]->out gvdd_mux_1level_tapbuf_size2[53] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[53], level=1, select_path_id=0. ***** -*****1***** -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -***** Signal mux_1level_tapbuf_size2[53]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[53]->in[0] mux_1level_tapbuf_size2[53]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[53]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[53]->in[1] mux_1level_tapbuf_size2[53]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[53] gvdd_mux_1level_tapbuf_size2[53] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[198] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[198] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[198] when v(mux_1level_tapbuf_size2[53]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[198] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[198] when v(mux_1level_tapbuf_size2[53]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[198] trig v(mux_1level_tapbuf_size2[53]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[53]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[53]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[198] param='mux_1level_tapbuf_size2[53]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[53]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[53]_energy_per_cycle param='mux_1level_tapbuf_size2[53]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[198] param='mux_1level_tapbuf_size2[53]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[198] param='dynamic_power_sb_mux[1][0]_rrnode[198]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[198] avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from='start_rise_sb_mux[1][0]_rrnode[198]' to='start_rise_sb_mux[1][0]_rrnode[198]+switch_rise_sb_mux[1][0]_rrnode[198]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[198] avg p(Vgvdd_mux_1level_tapbuf_size2[53]) from='start_fall_sb_mux[1][0]_rrnode[198]' to='start_fall_sb_mux[1][0]_rrnode[198]+switch_fall_sb_mux[1][0]_rrnode[198]' -.meas tran sum_leakage_power_mux[0to53] -+ param='sum_leakage_power_mux[0to52]+leakage_sb_mux[1][0]_rrnode[198]' -.meas tran sum_energy_per_cycle_mux[0to53] -+ param='sum_energy_per_cycle_mux[0to52]+energy_per_cycle_sb_mux[1][0]_rrnode[198]' -***** Load for rr_node[198] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=7, type=4 ***** -Xchan_mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out mux_1level_tapbuf_size2[53]->out mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[142]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out mux_1level_tapbuf_size2[53]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[53]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to53] -+ param='sum_leakage_power_sb_mux[0to52]+leakage_sb_mux[1][0]_rrnode[198]' -.meas tran sum_energy_per_cycle_sb_mux[0to53] -+ param='sum_energy_per_cycle_sb_mux[0to52]+energy_per_cycle_sb_mux[1][0]_rrnode[198]' -Xmux_1level_tapbuf_size2[54] mux_1level_tapbuf_size2[54]->in[0] mux_1level_tapbuf_size2[54]->in[1] mux_1level_tapbuf_size2[54]->out sram[64]->outb sram[64]->out gvdd_mux_1level_tapbuf_size2[54] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[54], level=1, select_path_id=0. ***** -*****1***** -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -***** Signal mux_1level_tapbuf_size2[54]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[54]->in[0] mux_1level_tapbuf_size2[54]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[54]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[54]->in[1] mux_1level_tapbuf_size2[54]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[54] gvdd_mux_1level_tapbuf_size2[54] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[200] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[200] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[200] when v(mux_1level_tapbuf_size2[54]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[200] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[200] when v(mux_1level_tapbuf_size2[54]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[200] trig v(mux_1level_tapbuf_size2[54]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[54]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[54]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[200] param='mux_1level_tapbuf_size2[54]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[54]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[54]_energy_per_cycle param='mux_1level_tapbuf_size2[54]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[200] param='mux_1level_tapbuf_size2[54]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[200] param='dynamic_power_sb_mux[1][0]_rrnode[200]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[200] avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from='start_rise_sb_mux[1][0]_rrnode[200]' to='start_rise_sb_mux[1][0]_rrnode[200]+switch_rise_sb_mux[1][0]_rrnode[200]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[200] avg p(Vgvdd_mux_1level_tapbuf_size2[54]) from='start_fall_sb_mux[1][0]_rrnode[200]' to='start_fall_sb_mux[1][0]_rrnode[200]+switch_fall_sb_mux[1][0]_rrnode[200]' -.meas tran sum_leakage_power_mux[0to54] -+ param='sum_leakage_power_mux[0to53]+leakage_sb_mux[1][0]_rrnode[200]' -.meas tran sum_energy_per_cycle_mux[0to54] -+ param='sum_energy_per_cycle_mux[0to53]+energy_per_cycle_sb_mux[1][0]_rrnode[200]' -***** Load for rr_node[200] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=9, type=4 ***** -Xchan_mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out mux_1level_tapbuf_size2[54]->out mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[146]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out mux_1level_tapbuf_size2[54]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[54]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to54] -+ param='sum_leakage_power_sb_mux[0to53]+leakage_sb_mux[1][0]_rrnode[200]' -.meas tran sum_energy_per_cycle_sb_mux[0to54] -+ param='sum_energy_per_cycle_sb_mux[0to53]+energy_per_cycle_sb_mux[1][0]_rrnode[200]' -Xmux_1level_tapbuf_size2[55] mux_1level_tapbuf_size2[55]->in[0] mux_1level_tapbuf_size2[55]->in[1] mux_1level_tapbuf_size2[55]->out sram[65]->outb sram[65]->out gvdd_mux_1level_tapbuf_size2[55] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[55], level=1, select_path_id=0. ***** -*****1***** -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -***** Signal mux_1level_tapbuf_size2[55]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[55]->in[0] mux_1level_tapbuf_size2[55]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[55]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[55]->in[1] mux_1level_tapbuf_size2[55]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[55] gvdd_mux_1level_tapbuf_size2[55] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[202] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[202] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[202] when v(mux_1level_tapbuf_size2[55]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[202] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[202] when v(mux_1level_tapbuf_size2[55]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[202] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[55]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[202] param='mux_1level_tapbuf_size2[55]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[55]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[55]_energy_per_cycle param='mux_1level_tapbuf_size2[55]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[202] param='mux_1level_tapbuf_size2[55]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[202] param='dynamic_power_sb_mux[1][0]_rrnode[202]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[202] avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='start_rise_sb_mux[1][0]_rrnode[202]' to='start_rise_sb_mux[1][0]_rrnode[202]+switch_rise_sb_mux[1][0]_rrnode[202]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[202] avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='start_fall_sb_mux[1][0]_rrnode[202]' to='start_fall_sb_mux[1][0]_rrnode[202]+switch_fall_sb_mux[1][0]_rrnode[202]' -.meas tran sum_leakage_power_mux[0to55] -+ param='sum_leakage_power_mux[0to54]+leakage_sb_mux[1][0]_rrnode[202]' -.meas tran sum_energy_per_cycle_mux[0to55] -+ param='sum_energy_per_cycle_mux[0to54]+energy_per_cycle_sb_mux[1][0]_rrnode[202]' -***** Load for rr_node[202] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=11, type=4 ***** -Xchan_mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[150]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to55] -+ param='sum_leakage_power_sb_mux[0to54]+leakage_sb_mux[1][0]_rrnode[202]' -.meas tran sum_energy_per_cycle_sb_mux[0to55] -+ param='sum_energy_per_cycle_sb_mux[0to54]+energy_per_cycle_sb_mux[1][0]_rrnode[202]' -Xmux_1level_tapbuf_size2[56] mux_1level_tapbuf_size2[56]->in[0] mux_1level_tapbuf_size2[56]->in[1] mux_1level_tapbuf_size2[56]->out sram[66]->outb sram[66]->out gvdd_mux_1level_tapbuf_size2[56] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[56], level=1, select_path_id=0. ***** -*****1***** -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -***** Signal mux_1level_tapbuf_size2[56]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[56]->in[0] mux_1level_tapbuf_size2[56]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[56]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[56]->in[1] mux_1level_tapbuf_size2[56]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[56] gvdd_mux_1level_tapbuf_size2[56] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[204] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[204] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[204] when v(mux_1level_tapbuf_size2[56]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[204] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[204] when v(mux_1level_tapbuf_size2[56]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[204] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[56]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[204] param='mux_1level_tapbuf_size2[56]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[56]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[56]_energy_per_cycle param='mux_1level_tapbuf_size2[56]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[204] param='mux_1level_tapbuf_size2[56]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[204] param='dynamic_power_sb_mux[1][0]_rrnode[204]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[204] avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='start_rise_sb_mux[1][0]_rrnode[204]' to='start_rise_sb_mux[1][0]_rrnode[204]+switch_rise_sb_mux[1][0]_rrnode[204]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[204] avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='start_fall_sb_mux[1][0]_rrnode[204]' to='start_fall_sb_mux[1][0]_rrnode[204]+switch_fall_sb_mux[1][0]_rrnode[204]' -.meas tran sum_leakage_power_mux[0to56] -+ param='sum_leakage_power_mux[0to55]+leakage_sb_mux[1][0]_rrnode[204]' -.meas tran sum_energy_per_cycle_mux[0to56] -+ param='sum_energy_per_cycle_mux[0to55]+energy_per_cycle_sb_mux[1][0]_rrnode[204]' -***** Load for rr_node[204] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=13, type=4 ***** -Xchan_mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[154]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to56] -+ param='sum_leakage_power_sb_mux[0to55]+leakage_sb_mux[1][0]_rrnode[204]' -.meas tran sum_energy_per_cycle_sb_mux[0to56] -+ param='sum_energy_per_cycle_sb_mux[0to55]+energy_per_cycle_sb_mux[1][0]_rrnode[204]' -Xmux_1level_tapbuf_size2[57] mux_1level_tapbuf_size2[57]->in[0] mux_1level_tapbuf_size2[57]->in[1] mux_1level_tapbuf_size2[57]->out sram[67]->outb sram[67]->out gvdd_mux_1level_tapbuf_size2[57] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[57], level=1, select_path_id=0. ***** -*****1***** -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -***** Signal mux_1level_tapbuf_size2[57]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[57]->in[0] mux_1level_tapbuf_size2[57]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[57]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[57]->in[1] mux_1level_tapbuf_size2[57]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[57] gvdd_mux_1level_tapbuf_size2[57] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[206] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[206] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[206] when v(mux_1level_tapbuf_size2[57]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[206] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[206] when v(mux_1level_tapbuf_size2[57]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[206] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[57]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[206] param='mux_1level_tapbuf_size2[57]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[57]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[57]_energy_per_cycle param='mux_1level_tapbuf_size2[57]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[206] param='mux_1level_tapbuf_size2[57]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[206] param='dynamic_power_sb_mux[1][0]_rrnode[206]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[206] avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='start_rise_sb_mux[1][0]_rrnode[206]' to='start_rise_sb_mux[1][0]_rrnode[206]+switch_rise_sb_mux[1][0]_rrnode[206]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[206] avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='start_fall_sb_mux[1][0]_rrnode[206]' to='start_fall_sb_mux[1][0]_rrnode[206]+switch_fall_sb_mux[1][0]_rrnode[206]' -.meas tran sum_leakage_power_mux[0to57] -+ param='sum_leakage_power_mux[0to56]+leakage_sb_mux[1][0]_rrnode[206]' -.meas tran sum_energy_per_cycle_mux[0to57] -+ param='sum_energy_per_cycle_mux[0to56]+energy_per_cycle_sb_mux[1][0]_rrnode[206]' -***** Load for rr_node[206] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=15, type=4 ***** -Xchan_mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[157]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to57] -+ param='sum_leakage_power_sb_mux[0to56]+leakage_sb_mux[1][0]_rrnode[206]' -.meas tran sum_energy_per_cycle_sb_mux[0to57] -+ param='sum_energy_per_cycle_sb_mux[0to56]+energy_per_cycle_sb_mux[1][0]_rrnode[206]' -Xmux_1level_tapbuf_size2[58] mux_1level_tapbuf_size2[58]->in[0] mux_1level_tapbuf_size2[58]->in[1] mux_1level_tapbuf_size2[58]->out sram[68]->outb sram[68]->out gvdd_mux_1level_tapbuf_size2[58] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[58], level=1, select_path_id=0. ***** -*****1***** -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -***** Signal mux_1level_tapbuf_size2[58]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[58]->in[0] mux_1level_tapbuf_size2[58]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[58]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[58]->in[1] mux_1level_tapbuf_size2[58]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[58] gvdd_mux_1level_tapbuf_size2[58] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[208] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[208] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[208] when v(mux_1level_tapbuf_size2[58]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[208] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[208] when v(mux_1level_tapbuf_size2[58]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[208] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[58]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[208] param='mux_1level_tapbuf_size2[58]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[58]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[58]_energy_per_cycle param='mux_1level_tapbuf_size2[58]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[208] param='mux_1level_tapbuf_size2[58]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[208] param='dynamic_power_sb_mux[1][0]_rrnode[208]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[208] avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='start_rise_sb_mux[1][0]_rrnode[208]' to='start_rise_sb_mux[1][0]_rrnode[208]+switch_rise_sb_mux[1][0]_rrnode[208]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[208] avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='start_fall_sb_mux[1][0]_rrnode[208]' to='start_fall_sb_mux[1][0]_rrnode[208]+switch_fall_sb_mux[1][0]_rrnode[208]' -.meas tran sum_leakage_power_mux[0to58] -+ param='sum_leakage_power_mux[0to57]+leakage_sb_mux[1][0]_rrnode[208]' -.meas tran sum_energy_per_cycle_mux[0to58] -+ param='sum_energy_per_cycle_mux[0to57]+energy_per_cycle_sb_mux[1][0]_rrnode[208]' -***** Load for rr_node[208] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=17, type=4 ***** -Xchan_mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[162]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to58] -+ param='sum_leakage_power_sb_mux[0to57]+leakage_sb_mux[1][0]_rrnode[208]' -.meas tran sum_energy_per_cycle_sb_mux[0to58] -+ param='sum_energy_per_cycle_sb_mux[0to57]+energy_per_cycle_sb_mux[1][0]_rrnode[208]' -Xmux_1level_tapbuf_size2[59] mux_1level_tapbuf_size2[59]->in[0] mux_1level_tapbuf_size2[59]->in[1] mux_1level_tapbuf_size2[59]->out sram[69]->outb sram[69]->out gvdd_mux_1level_tapbuf_size2[59] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[59], level=1, select_path_id=0. ***** -*****1***** -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -***** Signal mux_1level_tapbuf_size2[59]->in[0] density = 0.2026, probability=0.5018.***** -Vmux_1level_tapbuf_size2[59]->in[0] mux_1level_tapbuf_size2[59]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[59]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[59]->in[1] mux_1level_tapbuf_size2[59]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[59] gvdd_mux_1level_tapbuf_size2[59] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[210] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[210] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[210] when v(mux_1level_tapbuf_size2[59]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[210] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[210] when v(mux_1level_tapbuf_size2[59]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[210] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[59]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[210] param='mux_1level_tapbuf_size2[59]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[59]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[59]_energy_per_cycle param='mux_1level_tapbuf_size2[59]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[210] param='mux_1level_tapbuf_size2[59]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[210] param='dynamic_power_sb_mux[1][0]_rrnode[210]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[210] avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='start_rise_sb_mux[1][0]_rrnode[210]' to='start_rise_sb_mux[1][0]_rrnode[210]+switch_rise_sb_mux[1][0]_rrnode[210]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[210] avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='start_fall_sb_mux[1][0]_rrnode[210]' to='start_fall_sb_mux[1][0]_rrnode[210]+switch_fall_sb_mux[1][0]_rrnode[210]' -.meas tran sum_leakage_power_mux[0to59] -+ param='sum_leakage_power_mux[0to58]+leakage_sb_mux[1][0]_rrnode[210]' -.meas tran sum_energy_per_cycle_mux[0to59] -+ param='sum_energy_per_cycle_mux[0to58]+energy_per_cycle_sb_mux[1][0]_rrnode[210]' -***** Load for rr_node[210] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=19, type=4 ***** -Xchan_mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[165]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to59] -+ param='sum_leakage_power_sb_mux[0to58]+leakage_sb_mux[1][0]_rrnode[210]' -.meas tran sum_energy_per_cycle_sb_mux[0to59] -+ param='sum_energy_per_cycle_sb_mux[0to58]+energy_per_cycle_sb_mux[1][0]_rrnode[210]' -Xmux_1level_tapbuf_size2[60] mux_1level_tapbuf_size2[60]->in[0] mux_1level_tapbuf_size2[60]->in[1] mux_1level_tapbuf_size2[60]->out sram[70]->outb sram[70]->out gvdd_mux_1level_tapbuf_size2[60] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[60], level=1, select_path_id=0. ***** -*****1***** -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -***** Signal mux_1level_tapbuf_size2[60]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[60]->in[0] mux_1level_tapbuf_size2[60]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[60]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[60]->in[1] mux_1level_tapbuf_size2[60]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[60] gvdd_mux_1level_tapbuf_size2[60] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[212] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[212] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[212] when v(mux_1level_tapbuf_size2[60]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[212] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[212] when v(mux_1level_tapbuf_size2[60]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[212] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[60]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[212] param='mux_1level_tapbuf_size2[60]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[60]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[60]_energy_per_cycle param='mux_1level_tapbuf_size2[60]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[212] param='mux_1level_tapbuf_size2[60]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[212] param='dynamic_power_sb_mux[1][0]_rrnode[212]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[212] avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='start_rise_sb_mux[1][0]_rrnode[212]' to='start_rise_sb_mux[1][0]_rrnode[212]+switch_rise_sb_mux[1][0]_rrnode[212]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[212] avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='start_fall_sb_mux[1][0]_rrnode[212]' to='start_fall_sb_mux[1][0]_rrnode[212]+switch_fall_sb_mux[1][0]_rrnode[212]' -.meas tran sum_leakage_power_mux[0to60] -+ param='sum_leakage_power_mux[0to59]+leakage_sb_mux[1][0]_rrnode[212]' -.meas tran sum_energy_per_cycle_mux[0to60] -+ param='sum_energy_per_cycle_mux[0to59]+energy_per_cycle_sb_mux[1][0]_rrnode[212]' -***** Load for rr_node[212] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=21, type=4 ***** -Xchan_mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[169]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to60] -+ param='sum_leakage_power_sb_mux[0to59]+leakage_sb_mux[1][0]_rrnode[212]' -.meas tran sum_energy_per_cycle_sb_mux[0to60] -+ param='sum_energy_per_cycle_sb_mux[0to59]+energy_per_cycle_sb_mux[1][0]_rrnode[212]' -Xmux_1level_tapbuf_size2[61] mux_1level_tapbuf_size2[61]->in[0] mux_1level_tapbuf_size2[61]->in[1] mux_1level_tapbuf_size2[61]->out sram[71]->outb sram[71]->out gvdd_mux_1level_tapbuf_size2[61] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[61], level=1, select_path_id=0. ***** -*****1***** -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -***** Signal mux_1level_tapbuf_size2[61]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[61]->in[0] mux_1level_tapbuf_size2[61]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[61]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[61]->in[1] mux_1level_tapbuf_size2[61]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[61] gvdd_mux_1level_tapbuf_size2[61] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[214] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[214] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[214] when v(mux_1level_tapbuf_size2[61]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[214] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[214] when v(mux_1level_tapbuf_size2[61]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[214] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[61]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[214] param='mux_1level_tapbuf_size2[61]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[61]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[61]_energy_per_cycle param='mux_1level_tapbuf_size2[61]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[214] param='mux_1level_tapbuf_size2[61]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[214] param='dynamic_power_sb_mux[1][0]_rrnode[214]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[214] avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='start_rise_sb_mux[1][0]_rrnode[214]' to='start_rise_sb_mux[1][0]_rrnode[214]+switch_rise_sb_mux[1][0]_rrnode[214]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[214] avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='start_fall_sb_mux[1][0]_rrnode[214]' to='start_fall_sb_mux[1][0]_rrnode[214]+switch_fall_sb_mux[1][0]_rrnode[214]' -.meas tran sum_leakage_power_mux[0to61] -+ param='sum_leakage_power_mux[0to60]+leakage_sb_mux[1][0]_rrnode[214]' -.meas tran sum_energy_per_cycle_mux[0to61] -+ param='sum_energy_per_cycle_mux[0to60]+energy_per_cycle_sb_mux[1][0]_rrnode[214]' -***** Load for rr_node[214] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=23, type=4 ***** -Xchan_mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[174]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to61] -+ param='sum_leakage_power_sb_mux[0to60]+leakage_sb_mux[1][0]_rrnode[214]' -.meas tran sum_energy_per_cycle_sb_mux[0to61] -+ param='sum_energy_per_cycle_sb_mux[0to60]+energy_per_cycle_sb_mux[1][0]_rrnode[214]' -Xmux_1level_tapbuf_size2[62] mux_1level_tapbuf_size2[62]->in[0] mux_1level_tapbuf_size2[62]->in[1] mux_1level_tapbuf_size2[62]->out sram[72]->outb sram[72]->out gvdd_mux_1level_tapbuf_size2[62] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[62], level=1, select_path_id=0. ***** -*****1***** -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -***** Signal mux_1level_tapbuf_size2[62]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[62]->in[0] mux_1level_tapbuf_size2[62]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[62]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[62]->in[1] mux_1level_tapbuf_size2[62]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[62] gvdd_mux_1level_tapbuf_size2[62] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[216] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[216] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[216] when v(mux_1level_tapbuf_size2[62]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[216] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[216] when v(mux_1level_tapbuf_size2[62]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[216] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[62]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[216] param='mux_1level_tapbuf_size2[62]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[62]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[62]_energy_per_cycle param='mux_1level_tapbuf_size2[62]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[216] param='mux_1level_tapbuf_size2[62]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[216] param='dynamic_power_sb_mux[1][0]_rrnode[216]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[216] avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='start_rise_sb_mux[1][0]_rrnode[216]' to='start_rise_sb_mux[1][0]_rrnode[216]+switch_rise_sb_mux[1][0]_rrnode[216]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[216] avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='start_fall_sb_mux[1][0]_rrnode[216]' to='start_fall_sb_mux[1][0]_rrnode[216]+switch_fall_sb_mux[1][0]_rrnode[216]' -.meas tran sum_leakage_power_mux[0to62] -+ param='sum_leakage_power_mux[0to61]+leakage_sb_mux[1][0]_rrnode[216]' -.meas tran sum_energy_per_cycle_mux[0to62] -+ param='sum_energy_per_cycle_mux[0to61]+energy_per_cycle_sb_mux[1][0]_rrnode[216]' -***** Load for rr_node[216] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=25, type=4 ***** -Xchan_mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[177]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[180]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to62] -+ param='sum_leakage_power_sb_mux[0to61]+leakage_sb_mux[1][0]_rrnode[216]' -.meas tran sum_energy_per_cycle_sb_mux[0to62] -+ param='sum_energy_per_cycle_sb_mux[0to61]+energy_per_cycle_sb_mux[1][0]_rrnode[216]' -Xmux_1level_tapbuf_size2[63] mux_1level_tapbuf_size2[63]->in[0] mux_1level_tapbuf_size2[63]->in[1] mux_1level_tapbuf_size2[63]->out sram[73]->outb sram[73]->out gvdd_mux_1level_tapbuf_size2[63] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[63], level=1, select_path_id=0. ***** -*****1***** -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -***** Signal mux_1level_tapbuf_size2[63]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[63]->in[0] mux_1level_tapbuf_size2[63]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[63]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[63]->in[1] mux_1level_tapbuf_size2[63]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[63] gvdd_mux_1level_tapbuf_size2[63] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[218] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[218] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[218] when v(mux_1level_tapbuf_size2[63]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[218] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[218] when v(mux_1level_tapbuf_size2[63]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[218] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[63]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[218] param='mux_1level_tapbuf_size2[63]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[63]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[63]_energy_per_cycle param='mux_1level_tapbuf_size2[63]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[218] param='mux_1level_tapbuf_size2[63]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[218] param='dynamic_power_sb_mux[1][0]_rrnode[218]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[218] avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='start_rise_sb_mux[1][0]_rrnode[218]' to='start_rise_sb_mux[1][0]_rrnode[218]+switch_rise_sb_mux[1][0]_rrnode[218]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[218] avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='start_fall_sb_mux[1][0]_rrnode[218]' to='start_fall_sb_mux[1][0]_rrnode[218]+switch_fall_sb_mux[1][0]_rrnode[218]' -.meas tran sum_leakage_power_mux[0to63] -+ param='sum_leakage_power_mux[0to62]+leakage_sb_mux[1][0]_rrnode[218]' -.meas tran sum_energy_per_cycle_mux[0to63] -+ param='sum_energy_per_cycle_mux[0to62]+energy_per_cycle_sb_mux[1][0]_rrnode[218]' -***** Load for rr_node[218] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=27, type=4 ***** -Xchan_mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[181]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to63] -+ param='sum_leakage_power_sb_mux[0to62]+leakage_sb_mux[1][0]_rrnode[218]' -.meas tran sum_energy_per_cycle_sb_mux[0to63] -+ param='sum_energy_per_cycle_sb_mux[0to62]+energy_per_cycle_sb_mux[1][0]_rrnode[218]' -Xmux_1level_tapbuf_size2[64] mux_1level_tapbuf_size2[64]->in[0] mux_1level_tapbuf_size2[64]->in[1] mux_1level_tapbuf_size2[64]->out sram[74]->outb sram[74]->out gvdd_mux_1level_tapbuf_size2[64] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[64], level=1, select_path_id=0. ***** -*****1***** -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -***** Signal mux_1level_tapbuf_size2[64]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[64]->in[0] mux_1level_tapbuf_size2[64]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[64]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[64]->in[1] mux_1level_tapbuf_size2[64]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[64] gvdd_mux_1level_tapbuf_size2[64] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[220] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[220] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[220] when v(mux_1level_tapbuf_size2[64]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[220] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[220] when v(mux_1level_tapbuf_size2[64]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[220] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[64]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[220] param='mux_1level_tapbuf_size2[64]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[64]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[64]_energy_per_cycle param='mux_1level_tapbuf_size2[64]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[220] param='mux_1level_tapbuf_size2[64]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[220] param='dynamic_power_sb_mux[1][0]_rrnode[220]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[220] avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='start_rise_sb_mux[1][0]_rrnode[220]' to='start_rise_sb_mux[1][0]_rrnode[220]+switch_rise_sb_mux[1][0]_rrnode[220]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[220] avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='start_fall_sb_mux[1][0]_rrnode[220]' to='start_fall_sb_mux[1][0]_rrnode[220]+switch_fall_sb_mux[1][0]_rrnode[220]' -.meas tran sum_leakage_power_mux[0to64] -+ param='sum_leakage_power_mux[0to63]+leakage_sb_mux[1][0]_rrnode[220]' -.meas tran sum_energy_per_cycle_mux[0to64] -+ param='sum_energy_per_cycle_mux[0to63]+energy_per_cycle_sb_mux[1][0]_rrnode[220]' -***** Load for rr_node[220] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=29, type=4 ***** -Xchan_mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[184]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to64] -+ param='sum_leakage_power_sb_mux[0to63]+leakage_sb_mux[1][0]_rrnode[220]' -.meas tran sum_energy_per_cycle_sb_mux[0to64] -+ param='sum_energy_per_cycle_sb_mux[0to63]+energy_per_cycle_sb_mux[1][0]_rrnode[220]' -Xmux_1level_tapbuf_size2[65] mux_1level_tapbuf_size2[65]->in[0] mux_1level_tapbuf_size2[65]->in[1] mux_1level_tapbuf_size2[65]->out sram[75]->outb sram[75]->out gvdd_mux_1level_tapbuf_size2[65] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[65], level=1, select_path_id=0. ***** -*****1***** -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -***** Signal mux_1level_tapbuf_size2[65]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[65]->in[0] mux_1level_tapbuf_size2[65]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[65]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[65]->in[1] mux_1level_tapbuf_size2[65]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[65] gvdd_mux_1level_tapbuf_size2[65] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[222] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[222] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[222] when v(mux_1level_tapbuf_size2[65]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[222] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[222] when v(mux_1level_tapbuf_size2[65]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[222] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[65]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[222] param='mux_1level_tapbuf_size2[65]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[65]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[65]_energy_per_cycle param='mux_1level_tapbuf_size2[65]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[222] param='mux_1level_tapbuf_size2[65]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[222] param='dynamic_power_sb_mux[1][0]_rrnode[222]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[222] avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='start_rise_sb_mux[1][0]_rrnode[222]' to='start_rise_sb_mux[1][0]_rrnode[222]+switch_rise_sb_mux[1][0]_rrnode[222]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[222] avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='start_fall_sb_mux[1][0]_rrnode[222]' to='start_fall_sb_mux[1][0]_rrnode[222]+switch_fall_sb_mux[1][0]_rrnode[222]' -.meas tran sum_leakage_power_mux[0to65] -+ param='sum_leakage_power_mux[0to64]+leakage_sb_mux[1][0]_rrnode[222]' -.meas tran sum_energy_per_cycle_mux[0to65] -+ param='sum_energy_per_cycle_mux[0to64]+energy_per_cycle_sb_mux[1][0]_rrnode[222]' -***** Load for rr_node[222] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=31, type=4 ***** -Xchan_mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[189]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to65] -+ param='sum_leakage_power_sb_mux[0to64]+leakage_sb_mux[1][0]_rrnode[222]' -.meas tran sum_energy_per_cycle_sb_mux[0to65] -+ param='sum_energy_per_cycle_sb_mux[0to64]+energy_per_cycle_sb_mux[1][0]_rrnode[222]' -Xmux_1level_tapbuf_size2[66] mux_1level_tapbuf_size2[66]->in[0] mux_1level_tapbuf_size2[66]->in[1] mux_1level_tapbuf_size2[66]->out sram[76]->outb sram[76]->out gvdd_mux_1level_tapbuf_size2[66] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[66], level=1, select_path_id=0. ***** -*****1***** -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -***** Signal mux_1level_tapbuf_size2[66]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[66]->in[0] mux_1level_tapbuf_size2[66]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[66]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[66]->in[1] mux_1level_tapbuf_size2[66]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[66] gvdd_mux_1level_tapbuf_size2[66] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[224] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[224] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[224] when v(mux_1level_tapbuf_size2[66]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[224] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[224] when v(mux_1level_tapbuf_size2[66]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[224] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[66]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[224] param='mux_1level_tapbuf_size2[66]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[66]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[66]_energy_per_cycle param='mux_1level_tapbuf_size2[66]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[224] param='mux_1level_tapbuf_size2[66]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[224] param='dynamic_power_sb_mux[1][0]_rrnode[224]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[224] avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='start_rise_sb_mux[1][0]_rrnode[224]' to='start_rise_sb_mux[1][0]_rrnode[224]+switch_rise_sb_mux[1][0]_rrnode[224]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[224] avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='start_fall_sb_mux[1][0]_rrnode[224]' to='start_fall_sb_mux[1][0]_rrnode[224]+switch_fall_sb_mux[1][0]_rrnode[224]' -.meas tran sum_leakage_power_mux[0to66] -+ param='sum_leakage_power_mux[0to65]+leakage_sb_mux[1][0]_rrnode[224]' -.meas tran sum_energy_per_cycle_mux[0to66] -+ param='sum_energy_per_cycle_mux[0to65]+energy_per_cycle_sb_mux[1][0]_rrnode[224]' -***** Load for rr_node[224] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=33, type=4 ***** -Xchan_mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[193]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to66] -+ param='sum_leakage_power_sb_mux[0to65]+leakage_sb_mux[1][0]_rrnode[224]' -.meas tran sum_energy_per_cycle_sb_mux[0to66] -+ param='sum_energy_per_cycle_sb_mux[0to65]+energy_per_cycle_sb_mux[1][0]_rrnode[224]' -Xmux_1level_tapbuf_size2[67] mux_1level_tapbuf_size2[67]->in[0] mux_1level_tapbuf_size2[67]->in[1] mux_1level_tapbuf_size2[67]->out sram[77]->outb sram[77]->out gvdd_mux_1level_tapbuf_size2[67] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[67], level=1, select_path_id=0. ***** -*****1***** -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -***** Signal mux_1level_tapbuf_size2[67]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[67]->in[0] mux_1level_tapbuf_size2[67]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[67]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[67]->in[1] mux_1level_tapbuf_size2[67]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[67] gvdd_mux_1level_tapbuf_size2[67] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[226] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[226] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[226] when v(mux_1level_tapbuf_size2[67]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[226] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[226] when v(mux_1level_tapbuf_size2[67]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[226] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[67]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[226] param='mux_1level_tapbuf_size2[67]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[67]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[67]_energy_per_cycle param='mux_1level_tapbuf_size2[67]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[226] param='mux_1level_tapbuf_size2[67]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[226] param='dynamic_power_sb_mux[1][0]_rrnode[226]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[226] avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='start_rise_sb_mux[1][0]_rrnode[226]' to='start_rise_sb_mux[1][0]_rrnode[226]+switch_rise_sb_mux[1][0]_rrnode[226]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[226] avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='start_fall_sb_mux[1][0]_rrnode[226]' to='start_fall_sb_mux[1][0]_rrnode[226]+switch_fall_sb_mux[1][0]_rrnode[226]' -.meas tran sum_leakage_power_mux[0to67] -+ param='sum_leakage_power_mux[0to66]+leakage_sb_mux[1][0]_rrnode[226]' -.meas tran sum_energy_per_cycle_mux[0to67] -+ param='sum_energy_per_cycle_mux[0to66]+energy_per_cycle_sb_mux[1][0]_rrnode[226]' -***** Load for rr_node[226] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=35, type=4 ***** -Xchan_mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[196]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to67] -+ param='sum_leakage_power_sb_mux[0to66]+leakage_sb_mux[1][0]_rrnode[226]' -.meas tran sum_energy_per_cycle_sb_mux[0to67] -+ param='sum_energy_per_cycle_sb_mux[0to66]+energy_per_cycle_sb_mux[1][0]_rrnode[226]' -Xmux_1level_tapbuf_size2[68] mux_1level_tapbuf_size2[68]->in[0] mux_1level_tapbuf_size2[68]->in[1] mux_1level_tapbuf_size2[68]->out sram[78]->outb sram[78]->out gvdd_mux_1level_tapbuf_size2[68] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[68], level=1, select_path_id=0. ***** -*****1***** -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -***** Signal mux_1level_tapbuf_size2[68]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[68]->in[0] mux_1level_tapbuf_size2[68]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[68]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[68]->in[1] mux_1level_tapbuf_size2[68]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[68] gvdd_mux_1level_tapbuf_size2[68] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[228] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[228] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[228] when v(mux_1level_tapbuf_size2[68]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[228] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[228] when v(mux_1level_tapbuf_size2[68]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[228] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[68]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[228] param='mux_1level_tapbuf_size2[68]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[68]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[68]_energy_per_cycle param='mux_1level_tapbuf_size2[68]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[228] param='mux_1level_tapbuf_size2[68]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[228] param='dynamic_power_sb_mux[1][0]_rrnode[228]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[228] avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='start_rise_sb_mux[1][0]_rrnode[228]' to='start_rise_sb_mux[1][0]_rrnode[228]+switch_rise_sb_mux[1][0]_rrnode[228]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[228] avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='start_fall_sb_mux[1][0]_rrnode[228]' to='start_fall_sb_mux[1][0]_rrnode[228]+switch_fall_sb_mux[1][0]_rrnode[228]' -.meas tran sum_leakage_power_mux[0to68] -+ param='sum_leakage_power_mux[0to67]+leakage_sb_mux[1][0]_rrnode[228]' -.meas tran sum_energy_per_cycle_mux[0to68] -+ param='sum_energy_per_cycle_mux[0to67]+energy_per_cycle_sb_mux[1][0]_rrnode[228]' -***** Load for rr_node[228] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=37, type=4 ***** -Xchan_mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[201]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to68] -+ param='sum_leakage_power_sb_mux[0to67]+leakage_sb_mux[1][0]_rrnode[228]' -.meas tran sum_energy_per_cycle_sb_mux[0to68] -+ param='sum_energy_per_cycle_sb_mux[0to67]+energy_per_cycle_sb_mux[1][0]_rrnode[228]' -Xmux_1level_tapbuf_size2[69] mux_1level_tapbuf_size2[69]->in[0] mux_1level_tapbuf_size2[69]->in[1] mux_1level_tapbuf_size2[69]->out sram[79]->outb sram[79]->out gvdd_mux_1level_tapbuf_size2[69] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[69], level=1, select_path_id=0. ***** -*****1***** -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -***** Signal mux_1level_tapbuf_size2[69]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[69]->in[0] mux_1level_tapbuf_size2[69]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[69]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[69]->in[1] mux_1level_tapbuf_size2[69]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[69] gvdd_mux_1level_tapbuf_size2[69] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[230] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[230] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[230] when v(mux_1level_tapbuf_size2[69]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[230] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[230] when v(mux_1level_tapbuf_size2[69]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[230] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[69]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[230] param='mux_1level_tapbuf_size2[69]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[69]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[69]_energy_per_cycle param='mux_1level_tapbuf_size2[69]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[230] param='mux_1level_tapbuf_size2[69]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[230] param='dynamic_power_sb_mux[1][0]_rrnode[230]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[230] avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='start_rise_sb_mux[1][0]_rrnode[230]' to='start_rise_sb_mux[1][0]_rrnode[230]+switch_rise_sb_mux[1][0]_rrnode[230]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[230] avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='start_fall_sb_mux[1][0]_rrnode[230]' to='start_fall_sb_mux[1][0]_rrnode[230]+switch_fall_sb_mux[1][0]_rrnode[230]' -.meas tran sum_leakage_power_mux[0to69] -+ param='sum_leakage_power_mux[0to68]+leakage_sb_mux[1][0]_rrnode[230]' -.meas tran sum_energy_per_cycle_mux[0to69] -+ param='sum_energy_per_cycle_mux[0to68]+energy_per_cycle_sb_mux[1][0]_rrnode[230]' -***** Load for rr_node[230] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=39, type=4 ***** -Xchan_mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[204]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to69] -+ param='sum_leakage_power_sb_mux[0to68]+leakage_sb_mux[1][0]_rrnode[230]' -.meas tran sum_energy_per_cycle_sb_mux[0to69] -+ param='sum_energy_per_cycle_sb_mux[0to68]+energy_per_cycle_sb_mux[1][0]_rrnode[230]' -Xmux_1level_tapbuf_size2[70] mux_1level_tapbuf_size2[70]->in[0] mux_1level_tapbuf_size2[70]->in[1] mux_1level_tapbuf_size2[70]->out sram[80]->outb sram[80]->out gvdd_mux_1level_tapbuf_size2[70] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[70], level=1, select_path_id=0. ***** -*****1***** -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -***** Signal mux_1level_tapbuf_size2[70]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[70]->in[0] mux_1level_tapbuf_size2[70]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[70]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[70]->in[1] mux_1level_tapbuf_size2[70]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[70] gvdd_mux_1level_tapbuf_size2[70] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[232] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[232] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[232] when v(mux_1level_tapbuf_size2[70]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[232] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[232] when v(mux_1level_tapbuf_size2[70]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[232] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[70]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[232] param='mux_1level_tapbuf_size2[70]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[70]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[70]_energy_per_cycle param='mux_1level_tapbuf_size2[70]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[232] param='mux_1level_tapbuf_size2[70]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[232] param='dynamic_power_sb_mux[1][0]_rrnode[232]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[232] avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='start_rise_sb_mux[1][0]_rrnode[232]' to='start_rise_sb_mux[1][0]_rrnode[232]+switch_rise_sb_mux[1][0]_rrnode[232]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[232] avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='start_fall_sb_mux[1][0]_rrnode[232]' to='start_fall_sb_mux[1][0]_rrnode[232]+switch_fall_sb_mux[1][0]_rrnode[232]' -.meas tran sum_leakage_power_mux[0to70] -+ param='sum_leakage_power_mux[0to69]+leakage_sb_mux[1][0]_rrnode[232]' -.meas tran sum_energy_per_cycle_mux[0to70] -+ param='sum_energy_per_cycle_mux[0to69]+energy_per_cycle_sb_mux[1][0]_rrnode[232]' -***** Load for rr_node[232] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=41, type=4 ***** -Xchan_mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[208]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to70] -+ param='sum_leakage_power_sb_mux[0to69]+leakage_sb_mux[1][0]_rrnode[232]' -.meas tran sum_energy_per_cycle_sb_mux[0to70] -+ param='sum_energy_per_cycle_sb_mux[0to69]+energy_per_cycle_sb_mux[1][0]_rrnode[232]' -Xmux_1level_tapbuf_size2[71] mux_1level_tapbuf_size2[71]->in[0] mux_1level_tapbuf_size2[71]->in[1] mux_1level_tapbuf_size2[71]->out sram[81]->outb sram[81]->out gvdd_mux_1level_tapbuf_size2[71] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[71], level=1, select_path_id=0. ***** -*****1***** -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -***** Signal mux_1level_tapbuf_size2[71]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[71]->in[0] mux_1level_tapbuf_size2[71]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[71]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[71]->in[1] mux_1level_tapbuf_size2[71]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[71] gvdd_mux_1level_tapbuf_size2[71] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[234] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[234] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[234] when v(mux_1level_tapbuf_size2[71]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[234] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[234] when v(mux_1level_tapbuf_size2[71]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[234] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[71]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[234] param='mux_1level_tapbuf_size2[71]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[71]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[71]_energy_per_cycle param='mux_1level_tapbuf_size2[71]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[234] param='mux_1level_tapbuf_size2[71]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[234] param='dynamic_power_sb_mux[1][0]_rrnode[234]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[234] avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='start_rise_sb_mux[1][0]_rrnode[234]' to='start_rise_sb_mux[1][0]_rrnode[234]+switch_rise_sb_mux[1][0]_rrnode[234]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[234] avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='start_fall_sb_mux[1][0]_rrnode[234]' to='start_fall_sb_mux[1][0]_rrnode[234]+switch_fall_sb_mux[1][0]_rrnode[234]' -.meas tran sum_leakage_power_mux[0to71] -+ param='sum_leakage_power_mux[0to70]+leakage_sb_mux[1][0]_rrnode[234]' -.meas tran sum_energy_per_cycle_mux[0to71] -+ param='sum_energy_per_cycle_mux[0to70]+energy_per_cycle_sb_mux[1][0]_rrnode[234]' -***** Load for rr_node[234] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=43, type=4 ***** -Xchan_mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[212]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to71] -+ param='sum_leakage_power_sb_mux[0to70]+leakage_sb_mux[1][0]_rrnode[234]' -.meas tran sum_energy_per_cycle_sb_mux[0to71] -+ param='sum_energy_per_cycle_sb_mux[0to70]+energy_per_cycle_sb_mux[1][0]_rrnode[234]' -Xmux_1level_tapbuf_size2[72] mux_1level_tapbuf_size2[72]->in[0] mux_1level_tapbuf_size2[72]->in[1] mux_1level_tapbuf_size2[72]->out sram[82]->outb sram[82]->out gvdd_mux_1level_tapbuf_size2[72] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[72], level=1, select_path_id=0. ***** -*****1***** -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -***** Signal mux_1level_tapbuf_size2[72]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[72]->in[0] mux_1level_tapbuf_size2[72]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[72]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[72]->in[1] mux_1level_tapbuf_size2[72]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[72] gvdd_mux_1level_tapbuf_size2[72] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[236] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[236] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[236] when v(mux_1level_tapbuf_size2[72]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[236] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[236] when v(mux_1level_tapbuf_size2[72]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[236] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[72]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[236] param='mux_1level_tapbuf_size2[72]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[72]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[72]_energy_per_cycle param='mux_1level_tapbuf_size2[72]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[236] param='mux_1level_tapbuf_size2[72]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[236] param='dynamic_power_sb_mux[1][0]_rrnode[236]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[236] avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='start_rise_sb_mux[1][0]_rrnode[236]' to='start_rise_sb_mux[1][0]_rrnode[236]+switch_rise_sb_mux[1][0]_rrnode[236]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[236] avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='start_fall_sb_mux[1][0]_rrnode[236]' to='start_fall_sb_mux[1][0]_rrnode[236]+switch_fall_sb_mux[1][0]_rrnode[236]' -.meas tran sum_leakage_power_mux[0to72] -+ param='sum_leakage_power_mux[0to71]+leakage_sb_mux[1][0]_rrnode[236]' -.meas tran sum_energy_per_cycle_mux[0to72] -+ param='sum_energy_per_cycle_mux[0to71]+energy_per_cycle_sb_mux[1][0]_rrnode[236]' -***** Load for rr_node[236] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=45, type=4 ***** -Xchan_mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[216]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to72] -+ param='sum_leakage_power_sb_mux[0to71]+leakage_sb_mux[1][0]_rrnode[236]' -.meas tran sum_energy_per_cycle_sb_mux[0to72] -+ param='sum_energy_per_cycle_sb_mux[0to71]+energy_per_cycle_sb_mux[1][0]_rrnode[236]' -Xmux_1level_tapbuf_size2[73] mux_1level_tapbuf_size2[73]->in[0] mux_1level_tapbuf_size2[73]->in[1] mux_1level_tapbuf_size2[73]->out sram[83]->outb sram[83]->out gvdd_mux_1level_tapbuf_size2[73] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[73], level=1, select_path_id=0. ***** -*****1***** -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -***** Signal mux_1level_tapbuf_size2[73]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[73]->in[0] mux_1level_tapbuf_size2[73]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[73]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[73]->in[1] mux_1level_tapbuf_size2[73]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[73] gvdd_mux_1level_tapbuf_size2[73] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[238] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[238] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[238] when v(mux_1level_tapbuf_size2[73]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[238] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[238] when v(mux_1level_tapbuf_size2[73]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[238] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[73]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[238] param='mux_1level_tapbuf_size2[73]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[73]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[73]_energy_per_cycle param='mux_1level_tapbuf_size2[73]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[238] param='mux_1level_tapbuf_size2[73]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[238] param='dynamic_power_sb_mux[1][0]_rrnode[238]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[238] avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='start_rise_sb_mux[1][0]_rrnode[238]' to='start_rise_sb_mux[1][0]_rrnode[238]+switch_rise_sb_mux[1][0]_rrnode[238]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[238] avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='start_fall_sb_mux[1][0]_rrnode[238]' to='start_fall_sb_mux[1][0]_rrnode[238]+switch_fall_sb_mux[1][0]_rrnode[238]' -.meas tran sum_leakage_power_mux[0to73] -+ param='sum_leakage_power_mux[0to72]+leakage_sb_mux[1][0]_rrnode[238]' -.meas tran sum_energy_per_cycle_mux[0to73] -+ param='sum_energy_per_cycle_mux[0to72]+energy_per_cycle_sb_mux[1][0]_rrnode[238]' -***** Load for rr_node[238] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=47, type=4 ***** -Xchan_mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[220]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to73] -+ param='sum_leakage_power_sb_mux[0to72]+leakage_sb_mux[1][0]_rrnode[238]' -.meas tran sum_energy_per_cycle_sb_mux[0to73] -+ param='sum_energy_per_cycle_sb_mux[0to72]+energy_per_cycle_sb_mux[1][0]_rrnode[238]' -Xmux_1level_tapbuf_size2[74] mux_1level_tapbuf_size2[74]->in[0] mux_1level_tapbuf_size2[74]->in[1] mux_1level_tapbuf_size2[74]->out sram[84]->outb sram[84]->out gvdd_mux_1level_tapbuf_size2[74] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[74], level=1, select_path_id=0. ***** -*****1***** -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -***** Signal mux_1level_tapbuf_size2[74]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[74]->in[0] mux_1level_tapbuf_size2[74]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[74]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[74]->in[1] mux_1level_tapbuf_size2[74]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[74] gvdd_mux_1level_tapbuf_size2[74] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[240] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[240] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[240] when v(mux_1level_tapbuf_size2[74]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[240] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[240] when v(mux_1level_tapbuf_size2[74]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[240] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[74]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[240] param='mux_1level_tapbuf_size2[74]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[74]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[74]_energy_per_cycle param='mux_1level_tapbuf_size2[74]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[240] param='mux_1level_tapbuf_size2[74]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[240] param='dynamic_power_sb_mux[1][0]_rrnode[240]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[240] avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='start_rise_sb_mux[1][0]_rrnode[240]' to='start_rise_sb_mux[1][0]_rrnode[240]+switch_rise_sb_mux[1][0]_rrnode[240]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[240] avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='start_fall_sb_mux[1][0]_rrnode[240]' to='start_fall_sb_mux[1][0]_rrnode[240]+switch_fall_sb_mux[1][0]_rrnode[240]' -.meas tran sum_leakage_power_mux[0to74] -+ param='sum_leakage_power_mux[0to73]+leakage_sb_mux[1][0]_rrnode[240]' -.meas tran sum_energy_per_cycle_mux[0to74] -+ param='sum_energy_per_cycle_mux[0to73]+energy_per_cycle_sb_mux[1][0]_rrnode[240]' -***** Load for rr_node[240] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=49, type=4 ***** -Xchan_mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[223]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to74] -+ param='sum_leakage_power_sb_mux[0to73]+leakage_sb_mux[1][0]_rrnode[240]' -.meas tran sum_energy_per_cycle_sb_mux[0to74] -+ param='sum_energy_per_cycle_sb_mux[0to73]+energy_per_cycle_sb_mux[1][0]_rrnode[240]' -Xmux_1level_tapbuf_size2[75] mux_1level_tapbuf_size2[75]->in[0] mux_1level_tapbuf_size2[75]->in[1] mux_1level_tapbuf_size2[75]->out sram[85]->outb sram[85]->out gvdd_mux_1level_tapbuf_size2[75] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[75], level=1, select_path_id=0. ***** -*****1***** -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -***** Signal mux_1level_tapbuf_size2[75]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[75]->in[0] mux_1level_tapbuf_size2[75]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[75]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[75]->in[1] mux_1level_tapbuf_size2[75]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[75] gvdd_mux_1level_tapbuf_size2[75] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[242] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[242] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[242] when v(mux_1level_tapbuf_size2[75]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[242] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[242] when v(mux_1level_tapbuf_size2[75]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[242] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[75]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[242] param='mux_1level_tapbuf_size2[75]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[75]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[75]_energy_per_cycle param='mux_1level_tapbuf_size2[75]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[242] param='mux_1level_tapbuf_size2[75]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[242] param='dynamic_power_sb_mux[1][0]_rrnode[242]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[242] avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='start_rise_sb_mux[1][0]_rrnode[242]' to='start_rise_sb_mux[1][0]_rrnode[242]+switch_rise_sb_mux[1][0]_rrnode[242]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[242] avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='start_fall_sb_mux[1][0]_rrnode[242]' to='start_fall_sb_mux[1][0]_rrnode[242]+switch_fall_sb_mux[1][0]_rrnode[242]' -.meas tran sum_leakage_power_mux[0to75] -+ param='sum_leakage_power_mux[0to74]+leakage_sb_mux[1][0]_rrnode[242]' -.meas tran sum_energy_per_cycle_mux[0to75] -+ param='sum_energy_per_cycle_mux[0to74]+energy_per_cycle_sb_mux[1][0]_rrnode[242]' -***** Load for rr_node[242] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=51, type=4 ***** -Xchan_mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[227]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to75] -+ param='sum_leakage_power_sb_mux[0to74]+leakage_sb_mux[1][0]_rrnode[242]' -.meas tran sum_energy_per_cycle_sb_mux[0to75] -+ param='sum_energy_per_cycle_sb_mux[0to74]+energy_per_cycle_sb_mux[1][0]_rrnode[242]' -Xmux_1level_tapbuf_size2[76] mux_1level_tapbuf_size2[76]->in[0] mux_1level_tapbuf_size2[76]->in[1] mux_1level_tapbuf_size2[76]->out sram[86]->outb sram[86]->out gvdd_mux_1level_tapbuf_size2[76] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[76], level=1, select_path_id=0. ***** -*****1***** -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -***** Signal mux_1level_tapbuf_size2[76]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[76]->in[0] mux_1level_tapbuf_size2[76]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[76]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[76]->in[1] mux_1level_tapbuf_size2[76]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[76] gvdd_mux_1level_tapbuf_size2[76] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[244] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[244] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[244] when v(mux_1level_tapbuf_size2[76]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[244] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[244] when v(mux_1level_tapbuf_size2[76]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[244] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[76]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[244] param='mux_1level_tapbuf_size2[76]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[76]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[76]_energy_per_cycle param='mux_1level_tapbuf_size2[76]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[244] param='mux_1level_tapbuf_size2[76]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[244] param='dynamic_power_sb_mux[1][0]_rrnode[244]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[244] avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='start_rise_sb_mux[1][0]_rrnode[244]' to='start_rise_sb_mux[1][0]_rrnode[244]+switch_rise_sb_mux[1][0]_rrnode[244]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[244] avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='start_fall_sb_mux[1][0]_rrnode[244]' to='start_fall_sb_mux[1][0]_rrnode[244]+switch_fall_sb_mux[1][0]_rrnode[244]' -.meas tran sum_leakage_power_mux[0to76] -+ param='sum_leakage_power_mux[0to75]+leakage_sb_mux[1][0]_rrnode[244]' -.meas tran sum_energy_per_cycle_mux[0to76] -+ param='sum_energy_per_cycle_mux[0to75]+energy_per_cycle_sb_mux[1][0]_rrnode[244]' -***** Load for rr_node[244] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=53, type=4 ***** -Xchan_mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[232]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to76] -+ param='sum_leakage_power_sb_mux[0to75]+leakage_sb_mux[1][0]_rrnode[244]' -.meas tran sum_energy_per_cycle_sb_mux[0to76] -+ param='sum_energy_per_cycle_sb_mux[0to75]+energy_per_cycle_sb_mux[1][0]_rrnode[244]' -Xmux_1level_tapbuf_size2[77] mux_1level_tapbuf_size2[77]->in[0] mux_1level_tapbuf_size2[77]->in[1] mux_1level_tapbuf_size2[77]->out sram[87]->outb sram[87]->out gvdd_mux_1level_tapbuf_size2[77] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[77], level=1, select_path_id=0. ***** -*****1***** -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -***** Signal mux_1level_tapbuf_size2[77]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[77]->in[0] mux_1level_tapbuf_size2[77]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[77]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[77]->in[1] mux_1level_tapbuf_size2[77]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[77] gvdd_mux_1level_tapbuf_size2[77] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[246] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[246] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[246] when v(mux_1level_tapbuf_size2[77]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[246] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[246] when v(mux_1level_tapbuf_size2[77]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[246] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[77]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[246] param='mux_1level_tapbuf_size2[77]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[77]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[77]_energy_per_cycle param='mux_1level_tapbuf_size2[77]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[246] param='mux_1level_tapbuf_size2[77]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[246] param='dynamic_power_sb_mux[1][0]_rrnode[246]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[246] avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='start_rise_sb_mux[1][0]_rrnode[246]' to='start_rise_sb_mux[1][0]_rrnode[246]+switch_rise_sb_mux[1][0]_rrnode[246]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[246] avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='start_fall_sb_mux[1][0]_rrnode[246]' to='start_fall_sb_mux[1][0]_rrnode[246]+switch_fall_sb_mux[1][0]_rrnode[246]' -.meas tran sum_leakage_power_mux[0to77] -+ param='sum_leakage_power_mux[0to76]+leakage_sb_mux[1][0]_rrnode[246]' -.meas tran sum_energy_per_cycle_mux[0to77] -+ param='sum_energy_per_cycle_mux[0to76]+energy_per_cycle_sb_mux[1][0]_rrnode[246]' -***** Load for rr_node[246] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=55, type=4 ***** -Xchan_mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[235]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to77] -+ param='sum_leakage_power_sb_mux[0to76]+leakage_sb_mux[1][0]_rrnode[246]' -.meas tran sum_energy_per_cycle_sb_mux[0to77] -+ param='sum_energy_per_cycle_sb_mux[0to76]+energy_per_cycle_sb_mux[1][0]_rrnode[246]' -Xmux_1level_tapbuf_size2[78] mux_1level_tapbuf_size2[78]->in[0] mux_1level_tapbuf_size2[78]->in[1] mux_1level_tapbuf_size2[78]->out sram[88]->outb sram[88]->out gvdd_mux_1level_tapbuf_size2[78] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[78], level=1, select_path_id=0. ***** -*****1***** -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -***** Signal mux_1level_tapbuf_size2[78]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[78]->in[0] mux_1level_tapbuf_size2[78]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[78]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[78]->in[1] mux_1level_tapbuf_size2[78]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[78] gvdd_mux_1level_tapbuf_size2[78] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[248] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[248] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[248] when v(mux_1level_tapbuf_size2[78]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[248] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[248] when v(mux_1level_tapbuf_size2[78]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[248] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[78]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[248] param='mux_1level_tapbuf_size2[78]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[78]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[78]_energy_per_cycle param='mux_1level_tapbuf_size2[78]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[248] param='mux_1level_tapbuf_size2[78]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[248] param='dynamic_power_sb_mux[1][0]_rrnode[248]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[248] avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='start_rise_sb_mux[1][0]_rrnode[248]' to='start_rise_sb_mux[1][0]_rrnode[248]+switch_rise_sb_mux[1][0]_rrnode[248]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[248] avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='start_fall_sb_mux[1][0]_rrnode[248]' to='start_fall_sb_mux[1][0]_rrnode[248]+switch_fall_sb_mux[1][0]_rrnode[248]' -.meas tran sum_leakage_power_mux[0to78] -+ param='sum_leakage_power_mux[0to77]+leakage_sb_mux[1][0]_rrnode[248]' -.meas tran sum_energy_per_cycle_mux[0to78] -+ param='sum_energy_per_cycle_mux[0to77]+energy_per_cycle_sb_mux[1][0]_rrnode[248]' -***** Load for rr_node[248] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=57, type=4 ***** -Xchan_mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[239]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[240]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to78] -+ param='sum_leakage_power_sb_mux[0to77]+leakage_sb_mux[1][0]_rrnode[248]' -.meas tran sum_energy_per_cycle_sb_mux[0to78] -+ param='sum_energy_per_cycle_sb_mux[0to77]+energy_per_cycle_sb_mux[1][0]_rrnode[248]' -Xmux_1level_tapbuf_size2[79] mux_1level_tapbuf_size2[79]->in[0] mux_1level_tapbuf_size2[79]->in[1] mux_1level_tapbuf_size2[79]->out sram[89]->outb sram[89]->out gvdd_mux_1level_tapbuf_size2[79] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[79], level=1, select_path_id=0. ***** -*****1***** -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -***** Signal mux_1level_tapbuf_size2[79]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[79]->in[0] mux_1level_tapbuf_size2[79]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[79]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[79]->in[1] mux_1level_tapbuf_size2[79]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[79] gvdd_mux_1level_tapbuf_size2[79] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[250] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[250] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[250] when v(mux_1level_tapbuf_size2[79]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[250] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[250] when v(mux_1level_tapbuf_size2[79]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[250] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[79]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[250] param='mux_1level_tapbuf_size2[79]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[79]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[79]_energy_per_cycle param='mux_1level_tapbuf_size2[79]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[250] param='mux_1level_tapbuf_size2[79]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[250] param='dynamic_power_sb_mux[1][0]_rrnode[250]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[250] avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='start_rise_sb_mux[1][0]_rrnode[250]' to='start_rise_sb_mux[1][0]_rrnode[250]+switch_rise_sb_mux[1][0]_rrnode[250]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[250] avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='start_fall_sb_mux[1][0]_rrnode[250]' to='start_fall_sb_mux[1][0]_rrnode[250]+switch_fall_sb_mux[1][0]_rrnode[250]' -.meas tran sum_leakage_power_mux[0to79] -+ param='sum_leakage_power_mux[0to78]+leakage_sb_mux[1][0]_rrnode[250]' -.meas tran sum_energy_per_cycle_mux[0to79] -+ param='sum_energy_per_cycle_mux[0to78]+energy_per_cycle_sb_mux[1][0]_rrnode[250]' -***** Load for rr_node[250] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=59, type=4 ***** -Xchan_mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[243]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to79] -+ param='sum_leakage_power_sb_mux[0to78]+leakage_sb_mux[1][0]_rrnode[250]' -.meas tran sum_energy_per_cycle_sb_mux[0to79] -+ param='sum_energy_per_cycle_sb_mux[0to78]+energy_per_cycle_sb_mux[1][0]_rrnode[250]' -Xmux_1level_tapbuf_size2[80] mux_1level_tapbuf_size2[80]->in[0] mux_1level_tapbuf_size2[80]->in[1] mux_1level_tapbuf_size2[80]->out sram[90]->outb sram[90]->out gvdd_mux_1level_tapbuf_size2[80] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[80], level=1, select_path_id=0. ***** -*****1***** -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -***** Signal mux_1level_tapbuf_size2[80]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[80]->in[0] mux_1level_tapbuf_size2[80]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[80]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[80]->in[1] mux_1level_tapbuf_size2[80]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[80] gvdd_mux_1level_tapbuf_size2[80] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[252] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[252] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[252] when v(mux_1level_tapbuf_size2[80]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[252] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[252] when v(mux_1level_tapbuf_size2[80]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[252] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[80]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[252] param='mux_1level_tapbuf_size2[80]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[80]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[80]_energy_per_cycle param='mux_1level_tapbuf_size2[80]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[252] param='mux_1level_tapbuf_size2[80]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[252] param='dynamic_power_sb_mux[1][0]_rrnode[252]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[252] avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='start_rise_sb_mux[1][0]_rrnode[252]' to='start_rise_sb_mux[1][0]_rrnode[252]+switch_rise_sb_mux[1][0]_rrnode[252]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[252] avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='start_fall_sb_mux[1][0]_rrnode[252]' to='start_fall_sb_mux[1][0]_rrnode[252]+switch_fall_sb_mux[1][0]_rrnode[252]' -.meas tran sum_leakage_power_mux[0to80] -+ param='sum_leakage_power_mux[0to79]+leakage_sb_mux[1][0]_rrnode[252]' -.meas tran sum_energy_per_cycle_mux[0to80] -+ param='sum_energy_per_cycle_mux[0to79]+energy_per_cycle_sb_mux[1][0]_rrnode[252]' -***** Load for rr_node[252] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=61, type=4 ***** -Xchan_mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[247]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to80] -+ param='sum_leakage_power_sb_mux[0to79]+leakage_sb_mux[1][0]_rrnode[252]' -.meas tran sum_energy_per_cycle_sb_mux[0to80] -+ param='sum_energy_per_cycle_sb_mux[0to79]+energy_per_cycle_sb_mux[1][0]_rrnode[252]' -Xmux_1level_tapbuf_size2[81] mux_1level_tapbuf_size2[81]->in[0] mux_1level_tapbuf_size2[81]->in[1] mux_1level_tapbuf_size2[81]->out sram[91]->outb sram[91]->out gvdd_mux_1level_tapbuf_size2[81] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[81], level=1, select_path_id=0. ***** -*****1***** -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -***** Signal mux_1level_tapbuf_size2[81]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[81]->in[0] mux_1level_tapbuf_size2[81]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[81]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[81]->in[1] mux_1level_tapbuf_size2[81]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[81] gvdd_mux_1level_tapbuf_size2[81] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[254] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[254] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[254] when v(mux_1level_tapbuf_size2[81]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[254] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[254] when v(mux_1level_tapbuf_size2[81]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[254] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[81]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[254] param='mux_1level_tapbuf_size2[81]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[81]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[81]_energy_per_cycle param='mux_1level_tapbuf_size2[81]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[254] param='mux_1level_tapbuf_size2[81]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[254] param='dynamic_power_sb_mux[1][0]_rrnode[254]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[254] avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='start_rise_sb_mux[1][0]_rrnode[254]' to='start_rise_sb_mux[1][0]_rrnode[254]+switch_rise_sb_mux[1][0]_rrnode[254]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[254] avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='start_fall_sb_mux[1][0]_rrnode[254]' to='start_fall_sb_mux[1][0]_rrnode[254]+switch_fall_sb_mux[1][0]_rrnode[254]' -.meas tran sum_leakage_power_mux[0to81] -+ param='sum_leakage_power_mux[0to80]+leakage_sb_mux[1][0]_rrnode[254]' -.meas tran sum_energy_per_cycle_mux[0to81] -+ param='sum_energy_per_cycle_mux[0to80]+energy_per_cycle_sb_mux[1][0]_rrnode[254]' -***** Load for rr_node[254] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=63, type=4 ***** -Xchan_mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[251]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to81] -+ param='sum_leakage_power_sb_mux[0to80]+leakage_sb_mux[1][0]_rrnode[254]' -.meas tran sum_energy_per_cycle_sb_mux[0to81] -+ param='sum_energy_per_cycle_sb_mux[0to80]+energy_per_cycle_sb_mux[1][0]_rrnode[254]' -Xmux_1level_tapbuf_size2[82] mux_1level_tapbuf_size2[82]->in[0] mux_1level_tapbuf_size2[82]->in[1] mux_1level_tapbuf_size2[82]->out sram[92]->outb sram[92]->out gvdd_mux_1level_tapbuf_size2[82] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[82], level=1, select_path_id=0. ***** -*****1***** -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -***** Signal mux_1level_tapbuf_size2[82]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[82]->in[0] mux_1level_tapbuf_size2[82]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[82]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[82]->in[1] mux_1level_tapbuf_size2[82]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[82] gvdd_mux_1level_tapbuf_size2[82] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[256] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[256] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[256] when v(mux_1level_tapbuf_size2[82]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[256] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[256] when v(mux_1level_tapbuf_size2[82]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[256] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[82]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[256] param='mux_1level_tapbuf_size2[82]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[82]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[82]_energy_per_cycle param='mux_1level_tapbuf_size2[82]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[256] param='mux_1level_tapbuf_size2[82]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[256] param='dynamic_power_sb_mux[1][0]_rrnode[256]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[256] avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='start_rise_sb_mux[1][0]_rrnode[256]' to='start_rise_sb_mux[1][0]_rrnode[256]+switch_rise_sb_mux[1][0]_rrnode[256]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[256] avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='start_fall_sb_mux[1][0]_rrnode[256]' to='start_fall_sb_mux[1][0]_rrnode[256]+switch_fall_sb_mux[1][0]_rrnode[256]' -.meas tran sum_leakage_power_mux[0to82] -+ param='sum_leakage_power_mux[0to81]+leakage_sb_mux[1][0]_rrnode[256]' -.meas tran sum_energy_per_cycle_mux[0to82] -+ param='sum_energy_per_cycle_mux[0to81]+energy_per_cycle_sb_mux[1][0]_rrnode[256]' -***** Load for rr_node[256] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=65, type=4 ***** -Xchan_mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[254]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to82] -+ param='sum_leakage_power_sb_mux[0to81]+leakage_sb_mux[1][0]_rrnode[256]' -.meas tran sum_energy_per_cycle_sb_mux[0to82] -+ param='sum_energy_per_cycle_sb_mux[0to81]+energy_per_cycle_sb_mux[1][0]_rrnode[256]' -Xmux_1level_tapbuf_size2[83] mux_1level_tapbuf_size2[83]->in[0] mux_1level_tapbuf_size2[83]->in[1] mux_1level_tapbuf_size2[83]->out sram[93]->outb sram[93]->out gvdd_mux_1level_tapbuf_size2[83] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[83], level=1, select_path_id=0. ***** -*****1***** -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -***** Signal mux_1level_tapbuf_size2[83]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[83]->in[0] mux_1level_tapbuf_size2[83]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[83]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[83]->in[1] mux_1level_tapbuf_size2[83]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[83] gvdd_mux_1level_tapbuf_size2[83] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[258] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[258] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[258] when v(mux_1level_tapbuf_size2[83]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[258] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[258] when v(mux_1level_tapbuf_size2[83]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[258] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[83]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[258] param='mux_1level_tapbuf_size2[83]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[83]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[83]_energy_per_cycle param='mux_1level_tapbuf_size2[83]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[258] param='mux_1level_tapbuf_size2[83]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[258] param='dynamic_power_sb_mux[1][0]_rrnode[258]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[258] avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='start_rise_sb_mux[1][0]_rrnode[258]' to='start_rise_sb_mux[1][0]_rrnode[258]+switch_rise_sb_mux[1][0]_rrnode[258]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[258] avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='start_fall_sb_mux[1][0]_rrnode[258]' to='start_fall_sb_mux[1][0]_rrnode[258]+switch_fall_sb_mux[1][0]_rrnode[258]' -.meas tran sum_leakage_power_mux[0to83] -+ param='sum_leakage_power_mux[0to82]+leakage_sb_mux[1][0]_rrnode[258]' -.meas tran sum_energy_per_cycle_mux[0to83] -+ param='sum_energy_per_cycle_mux[0to82]+energy_per_cycle_sb_mux[1][0]_rrnode[258]' -***** Load for rr_node[258] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=67, type=4 ***** -Xchan_mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[259]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to83] -+ param='sum_leakage_power_sb_mux[0to82]+leakage_sb_mux[1][0]_rrnode[258]' -.meas tran sum_energy_per_cycle_sb_mux[0to83] -+ param='sum_energy_per_cycle_sb_mux[0to82]+energy_per_cycle_sb_mux[1][0]_rrnode[258]' -Xmux_1level_tapbuf_size2[84] mux_1level_tapbuf_size2[84]->in[0] mux_1level_tapbuf_size2[84]->in[1] mux_1level_tapbuf_size2[84]->out sram[94]->outb sram[94]->out gvdd_mux_1level_tapbuf_size2[84] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[84], level=1, select_path_id=0. ***** -*****1***** -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -***** Signal mux_1level_tapbuf_size2[84]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[84]->in[0] mux_1level_tapbuf_size2[84]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[84]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[84]->in[1] mux_1level_tapbuf_size2[84]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[84] gvdd_mux_1level_tapbuf_size2[84] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[260] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[260] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[260] when v(mux_1level_tapbuf_size2[84]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[260] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[260] when v(mux_1level_tapbuf_size2[84]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[260] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[84]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[260] param='mux_1level_tapbuf_size2[84]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[84]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[84]_energy_per_cycle param='mux_1level_tapbuf_size2[84]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[260] param='mux_1level_tapbuf_size2[84]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[260] param='dynamic_power_sb_mux[1][0]_rrnode[260]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[260] avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='start_rise_sb_mux[1][0]_rrnode[260]' to='start_rise_sb_mux[1][0]_rrnode[260]+switch_rise_sb_mux[1][0]_rrnode[260]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[260] avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='start_fall_sb_mux[1][0]_rrnode[260]' to='start_fall_sb_mux[1][0]_rrnode[260]+switch_fall_sb_mux[1][0]_rrnode[260]' -.meas tran sum_leakage_power_mux[0to84] -+ param='sum_leakage_power_mux[0to83]+leakage_sb_mux[1][0]_rrnode[260]' -.meas tran sum_energy_per_cycle_mux[0to84] -+ param='sum_energy_per_cycle_mux[0to83]+energy_per_cycle_sb_mux[1][0]_rrnode[260]' -***** Load for rr_node[260] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=69, type=4 ***** -Xchan_mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[262]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to84] -+ param='sum_leakage_power_sb_mux[0to83]+leakage_sb_mux[1][0]_rrnode[260]' -.meas tran sum_energy_per_cycle_sb_mux[0to84] -+ param='sum_energy_per_cycle_sb_mux[0to83]+energy_per_cycle_sb_mux[1][0]_rrnode[260]' -Xmux_1level_tapbuf_size2[85] mux_1level_tapbuf_size2[85]->in[0] mux_1level_tapbuf_size2[85]->in[1] mux_1level_tapbuf_size2[85]->out sram[95]->outb sram[95]->out gvdd_mux_1level_tapbuf_size2[85] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[85], level=1, select_path_id=0. ***** -*****1***** -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -***** Signal mux_1level_tapbuf_size2[85]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[85]->in[0] mux_1level_tapbuf_size2[85]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[85]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[85]->in[1] mux_1level_tapbuf_size2[85]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[85] gvdd_mux_1level_tapbuf_size2[85] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[262] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[262] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[262] when v(mux_1level_tapbuf_size2[85]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[262] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[262] when v(mux_1level_tapbuf_size2[85]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[262] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[85]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[262] param='mux_1level_tapbuf_size2[85]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[85]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[85]_energy_per_cycle param='mux_1level_tapbuf_size2[85]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[262] param='mux_1level_tapbuf_size2[85]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[262] param='dynamic_power_sb_mux[1][0]_rrnode[262]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[262] avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='start_rise_sb_mux[1][0]_rrnode[262]' to='start_rise_sb_mux[1][0]_rrnode[262]+switch_rise_sb_mux[1][0]_rrnode[262]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[262] avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='start_fall_sb_mux[1][0]_rrnode[262]' to='start_fall_sb_mux[1][0]_rrnode[262]+switch_fall_sb_mux[1][0]_rrnode[262]' -.meas tran sum_leakage_power_mux[0to85] -+ param='sum_leakage_power_mux[0to84]+leakage_sb_mux[1][0]_rrnode[262]' -.meas tran sum_energy_per_cycle_mux[0to85] -+ param='sum_energy_per_cycle_mux[0to84]+energy_per_cycle_sb_mux[1][0]_rrnode[262]' -***** Load for rr_node[262] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=71, type=4 ***** -Xchan_mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[266]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to85] -+ param='sum_leakage_power_sb_mux[0to84]+leakage_sb_mux[1][0]_rrnode[262]' -.meas tran sum_energy_per_cycle_sb_mux[0to85] -+ param='sum_energy_per_cycle_sb_mux[0to84]+energy_per_cycle_sb_mux[1][0]_rrnode[262]' -Xmux_1level_tapbuf_size2[86] mux_1level_tapbuf_size2[86]->in[0] mux_1level_tapbuf_size2[86]->in[1] mux_1level_tapbuf_size2[86]->out sram[96]->outb sram[96]->out gvdd_mux_1level_tapbuf_size2[86] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[86], level=1, select_path_id=0. ***** -*****1***** -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -***** Signal mux_1level_tapbuf_size2[86]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[86]->in[0] mux_1level_tapbuf_size2[86]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[86]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[86]->in[1] mux_1level_tapbuf_size2[86]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[86] gvdd_mux_1level_tapbuf_size2[86] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[264] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[264] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[264] when v(mux_1level_tapbuf_size2[86]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[264] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[264] when v(mux_1level_tapbuf_size2[86]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[264] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[86]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[264] param='mux_1level_tapbuf_size2[86]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[86]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[86]_energy_per_cycle param='mux_1level_tapbuf_size2[86]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[264] param='mux_1level_tapbuf_size2[86]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[264] param='dynamic_power_sb_mux[1][0]_rrnode[264]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[264] avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='start_rise_sb_mux[1][0]_rrnode[264]' to='start_rise_sb_mux[1][0]_rrnode[264]+switch_rise_sb_mux[1][0]_rrnode[264]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[264] avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='start_fall_sb_mux[1][0]_rrnode[264]' to='start_fall_sb_mux[1][0]_rrnode[264]+switch_fall_sb_mux[1][0]_rrnode[264]' -.meas tran sum_leakage_power_mux[0to86] -+ param='sum_leakage_power_mux[0to85]+leakage_sb_mux[1][0]_rrnode[264]' -.meas tran sum_energy_per_cycle_mux[0to86] -+ param='sum_energy_per_cycle_mux[0to85]+energy_per_cycle_sb_mux[1][0]_rrnode[264]' -***** Load for rr_node[264] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=73, type=4 ***** -Xchan_mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[271]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to86] -+ param='sum_leakage_power_sb_mux[0to85]+leakage_sb_mux[1][0]_rrnode[264]' -.meas tran sum_energy_per_cycle_sb_mux[0to86] -+ param='sum_energy_per_cycle_sb_mux[0to85]+energy_per_cycle_sb_mux[1][0]_rrnode[264]' -Xmux_1level_tapbuf_size2[87] mux_1level_tapbuf_size2[87]->in[0] mux_1level_tapbuf_size2[87]->in[1] mux_1level_tapbuf_size2[87]->out sram[97]->outb sram[97]->out gvdd_mux_1level_tapbuf_size2[87] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[87], level=1, select_path_id=0. ***** -*****1***** -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -***** Signal mux_1level_tapbuf_size2[87]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[87]->in[0] mux_1level_tapbuf_size2[87]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[87]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[87]->in[1] mux_1level_tapbuf_size2[87]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[87] gvdd_mux_1level_tapbuf_size2[87] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[266] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[266] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[266] when v(mux_1level_tapbuf_size2[87]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[266] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[266] when v(mux_1level_tapbuf_size2[87]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[266] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[87]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[266] param='mux_1level_tapbuf_size2[87]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[87]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[87]_energy_per_cycle param='mux_1level_tapbuf_size2[87]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[266] param='mux_1level_tapbuf_size2[87]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[266] param='dynamic_power_sb_mux[1][0]_rrnode[266]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[266] avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='start_rise_sb_mux[1][0]_rrnode[266]' to='start_rise_sb_mux[1][0]_rrnode[266]+switch_rise_sb_mux[1][0]_rrnode[266]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[266] avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='start_fall_sb_mux[1][0]_rrnode[266]' to='start_fall_sb_mux[1][0]_rrnode[266]+switch_fall_sb_mux[1][0]_rrnode[266]' -.meas tran sum_leakage_power_mux[0to87] -+ param='sum_leakage_power_mux[0to86]+leakage_sb_mux[1][0]_rrnode[266]' -.meas tran sum_energy_per_cycle_mux[0to87] -+ param='sum_energy_per_cycle_mux[0to86]+energy_per_cycle_sb_mux[1][0]_rrnode[266]' -***** Load for rr_node[266] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=75, type=4 ***** -Xchan_mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[274]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to87] -+ param='sum_leakage_power_sb_mux[0to86]+leakage_sb_mux[1][0]_rrnode[266]' -.meas tran sum_energy_per_cycle_sb_mux[0to87] -+ param='sum_energy_per_cycle_sb_mux[0to86]+energy_per_cycle_sb_mux[1][0]_rrnode[266]' -Xmux_1level_tapbuf_size2[88] mux_1level_tapbuf_size2[88]->in[0] mux_1level_tapbuf_size2[88]->in[1] mux_1level_tapbuf_size2[88]->out sram[98]->outb sram[98]->out gvdd_mux_1level_tapbuf_size2[88] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[88], level=1, select_path_id=0. ***** -*****1***** -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -***** Signal mux_1level_tapbuf_size2[88]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[88]->in[0] mux_1level_tapbuf_size2[88]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[88]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[88]->in[1] mux_1level_tapbuf_size2[88]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[88] gvdd_mux_1level_tapbuf_size2[88] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[268] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[268] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[268] when v(mux_1level_tapbuf_size2[88]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[268] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[268] when v(mux_1level_tapbuf_size2[88]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[268] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[88]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[268] param='mux_1level_tapbuf_size2[88]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[88]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[88]_energy_per_cycle param='mux_1level_tapbuf_size2[88]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[268] param='mux_1level_tapbuf_size2[88]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[268] param='dynamic_power_sb_mux[1][0]_rrnode[268]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[268] avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='start_rise_sb_mux[1][0]_rrnode[268]' to='start_rise_sb_mux[1][0]_rrnode[268]+switch_rise_sb_mux[1][0]_rrnode[268]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[268] avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='start_fall_sb_mux[1][0]_rrnode[268]' to='start_fall_sb_mux[1][0]_rrnode[268]+switch_fall_sb_mux[1][0]_rrnode[268]' -.meas tran sum_leakage_power_mux[0to88] -+ param='sum_leakage_power_mux[0to87]+leakage_sb_mux[1][0]_rrnode[268]' -.meas tran sum_energy_per_cycle_mux[0to88] -+ param='sum_energy_per_cycle_mux[0to87]+energy_per_cycle_sb_mux[1][0]_rrnode[268]' -***** Load for rr_node[268] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=77, type=4 ***** -Xchan_mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[278]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to88] -+ param='sum_leakage_power_sb_mux[0to87]+leakage_sb_mux[1][0]_rrnode[268]' -.meas tran sum_energy_per_cycle_sb_mux[0to88] -+ param='sum_energy_per_cycle_sb_mux[0to87]+energy_per_cycle_sb_mux[1][0]_rrnode[268]' -Xmux_1level_tapbuf_size2[89] mux_1level_tapbuf_size2[89]->in[0] mux_1level_tapbuf_size2[89]->in[1] mux_1level_tapbuf_size2[89]->out sram[99]->out sram[99]->outb gvdd_mux_1level_tapbuf_size2[89] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[89], level=1, select_path_id=1. ***** -*****0***** -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -***** Signal mux_1level_tapbuf_size2[89]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[89]->in[0] mux_1level_tapbuf_size2[89]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[89]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[89]->in[1] mux_1level_tapbuf_size2[89]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[89] gvdd_mux_1level_tapbuf_size2[89] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[270] trig v(mux_1level_tapbuf_size2[89]->in[1]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[270] trig v(mux_1level_tapbuf_size2[89]->in[1]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[270] when v(mux_1level_tapbuf_size2[89]->in[1])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[270] trig v(mux_1level_tapbuf_size2[89]->in[1]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[270] when v(mux_1level_tapbuf_size2[89]->in[1])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[270] trig v(mux_1level_tapbuf_size2[89]->in[1]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[89]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[270] param='mux_1level_tapbuf_size2[89]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[89]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[89]_energy_per_cycle param='mux_1level_tapbuf_size2[89]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[270] param='mux_1level_tapbuf_size2[89]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[270] param='dynamic_power_sb_mux[1][0]_rrnode[270]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[270] avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='start_rise_sb_mux[1][0]_rrnode[270]' to='start_rise_sb_mux[1][0]_rrnode[270]+switch_rise_sb_mux[1][0]_rrnode[270]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[270] avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='start_fall_sb_mux[1][0]_rrnode[270]' to='start_fall_sb_mux[1][0]_rrnode[270]+switch_fall_sb_mux[1][0]_rrnode[270]' -.meas tran sum_leakage_power_mux[0to89] -+ param='sum_leakage_power_mux[0to88]+leakage_sb_mux[1][0]_rrnode[270]' -.meas tran sum_energy_per_cycle_mux[0to89] -+ param='sum_energy_per_cycle_mux[0to88]+energy_per_cycle_sb_mux[1][0]_rrnode[270]' -***** Load for rr_node[270] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=79, type=4 ***** -Xchan_mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[281]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to89] -+ param='sum_leakage_power_sb_mux[0to88]+leakage_sb_mux[1][0]_rrnode[270]' -.meas tran sum_energy_per_cycle_sb_mux[0to89] -+ param='sum_energy_per_cycle_sb_mux[0to88]+energy_per_cycle_sb_mux[1][0]_rrnode[270]' -Xmux_1level_tapbuf_size2[90] mux_1level_tapbuf_size2[90]->in[0] mux_1level_tapbuf_size2[90]->in[1] mux_1level_tapbuf_size2[90]->out sram[100]->outb sram[100]->out gvdd_mux_1level_tapbuf_size2[90] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[90], level=1, select_path_id=0. ***** -*****1***** -Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[100]->out) 0 -.nodeset V(sram[100]->outb) vsp -***** Signal mux_1level_tapbuf_size2[90]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[90]->in[0] mux_1level_tapbuf_size2[90]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[90]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[90]->in[1] mux_1level_tapbuf_size2[90]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[90] gvdd_mux_1level_tapbuf_size2[90] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[272] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[272] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[272] when v(mux_1level_tapbuf_size2[90]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[272] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[272] when v(mux_1level_tapbuf_size2[90]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[272] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[90]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[272] param='mux_1level_tapbuf_size2[90]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[90]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[90]_energy_per_cycle param='mux_1level_tapbuf_size2[90]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[272] param='mux_1level_tapbuf_size2[90]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[272] param='dynamic_power_sb_mux[1][0]_rrnode[272]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[272] avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='start_rise_sb_mux[1][0]_rrnode[272]' to='start_rise_sb_mux[1][0]_rrnode[272]+switch_rise_sb_mux[1][0]_rrnode[272]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[272] avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='start_fall_sb_mux[1][0]_rrnode[272]' to='start_fall_sb_mux[1][0]_rrnode[272]+switch_fall_sb_mux[1][0]_rrnode[272]' -.meas tran sum_leakage_power_mux[0to90] -+ param='sum_leakage_power_mux[0to89]+leakage_sb_mux[1][0]_rrnode[272]' -.meas tran sum_energy_per_cycle_mux[0to90] -+ param='sum_energy_per_cycle_mux[0to89]+energy_per_cycle_sb_mux[1][0]_rrnode[272]' -***** Load for rr_node[272] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=81, type=4 ***** -Xchan_mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[286]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to90] -+ param='sum_leakage_power_sb_mux[0to89]+leakage_sb_mux[1][0]_rrnode[272]' -.meas tran sum_energy_per_cycle_sb_mux[0to90] -+ param='sum_energy_per_cycle_sb_mux[0to89]+energy_per_cycle_sb_mux[1][0]_rrnode[272]' -Xmux_1level_tapbuf_size2[91] mux_1level_tapbuf_size2[91]->in[0] mux_1level_tapbuf_size2[91]->in[1] mux_1level_tapbuf_size2[91]->out sram[101]->outb sram[101]->out gvdd_mux_1level_tapbuf_size2[91] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[91], level=1, select_path_id=0. ***** -*****1***** -Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[101]->out) 0 -.nodeset V(sram[101]->outb) vsp -***** Signal mux_1level_tapbuf_size2[91]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[91]->in[0] mux_1level_tapbuf_size2[91]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[91]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[91]->in[1] mux_1level_tapbuf_size2[91]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[91] gvdd_mux_1level_tapbuf_size2[91] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[274] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[274] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[274] when v(mux_1level_tapbuf_size2[91]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[274] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[274] when v(mux_1level_tapbuf_size2[91]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[274] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[91]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[274] param='mux_1level_tapbuf_size2[91]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[91]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[91]_energy_per_cycle param='mux_1level_tapbuf_size2[91]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[274] param='mux_1level_tapbuf_size2[91]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[274] param='dynamic_power_sb_mux[1][0]_rrnode[274]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[274] avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='start_rise_sb_mux[1][0]_rrnode[274]' to='start_rise_sb_mux[1][0]_rrnode[274]+switch_rise_sb_mux[1][0]_rrnode[274]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[274] avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='start_fall_sb_mux[1][0]_rrnode[274]' to='start_fall_sb_mux[1][0]_rrnode[274]+switch_fall_sb_mux[1][0]_rrnode[274]' -.meas tran sum_leakage_power_mux[0to91] -+ param='sum_leakage_power_mux[0to90]+leakage_sb_mux[1][0]_rrnode[274]' -.meas tran sum_energy_per_cycle_mux[0to91] -+ param='sum_energy_per_cycle_mux[0to90]+energy_per_cycle_sb_mux[1][0]_rrnode[274]' -***** Load for rr_node[274] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=83, type=4 ***** -Xchan_mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[290]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to91] -+ param='sum_leakage_power_sb_mux[0to90]+leakage_sb_mux[1][0]_rrnode[274]' -.meas tran sum_energy_per_cycle_sb_mux[0to91] -+ param='sum_energy_per_cycle_sb_mux[0to90]+energy_per_cycle_sb_mux[1][0]_rrnode[274]' -Xmux_1level_tapbuf_size2[92] mux_1level_tapbuf_size2[92]->in[0] mux_1level_tapbuf_size2[92]->in[1] mux_1level_tapbuf_size2[92]->out sram[102]->outb sram[102]->out gvdd_mux_1level_tapbuf_size2[92] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[92], level=1, select_path_id=0. ***** -*****1***** -Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[102]->out) 0 -.nodeset V(sram[102]->outb) vsp -***** Signal mux_1level_tapbuf_size2[92]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[92]->in[0] mux_1level_tapbuf_size2[92]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[92]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[92]->in[1] mux_1level_tapbuf_size2[92]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[92] gvdd_mux_1level_tapbuf_size2[92] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[276] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[276] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[276] when v(mux_1level_tapbuf_size2[92]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[276] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[276] when v(mux_1level_tapbuf_size2[92]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[276] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[92]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[276] param='mux_1level_tapbuf_size2[92]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[92]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[92]_energy_per_cycle param='mux_1level_tapbuf_size2[92]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[276] param='mux_1level_tapbuf_size2[92]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[276] param='dynamic_power_sb_mux[1][0]_rrnode[276]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[276] avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='start_rise_sb_mux[1][0]_rrnode[276]' to='start_rise_sb_mux[1][0]_rrnode[276]+switch_rise_sb_mux[1][0]_rrnode[276]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[276] avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='start_fall_sb_mux[1][0]_rrnode[276]' to='start_fall_sb_mux[1][0]_rrnode[276]+switch_fall_sb_mux[1][0]_rrnode[276]' -.meas tran sum_leakage_power_mux[0to92] -+ param='sum_leakage_power_mux[0to91]+leakage_sb_mux[1][0]_rrnode[276]' -.meas tran sum_energy_per_cycle_mux[0to92] -+ param='sum_energy_per_cycle_mux[0to91]+energy_per_cycle_sb_mux[1][0]_rrnode[276]' -***** Load for rr_node[276] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=85, type=4 ***** -Xchan_mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[293]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to92] -+ param='sum_leakage_power_sb_mux[0to91]+leakage_sb_mux[1][0]_rrnode[276]' -.meas tran sum_energy_per_cycle_sb_mux[0to92] -+ param='sum_energy_per_cycle_sb_mux[0to91]+energy_per_cycle_sb_mux[1][0]_rrnode[276]' -Xmux_1level_tapbuf_size2[93] mux_1level_tapbuf_size2[93]->in[0] mux_1level_tapbuf_size2[93]->in[1] mux_1level_tapbuf_size2[93]->out sram[103]->outb sram[103]->out gvdd_mux_1level_tapbuf_size2[93] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[93], level=1, select_path_id=0. ***** -*****1***** -Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[103]->out) 0 -.nodeset V(sram[103]->outb) vsp -***** Signal mux_1level_tapbuf_size2[93]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[93]->in[0] mux_1level_tapbuf_size2[93]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[93]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[93]->in[1] mux_1level_tapbuf_size2[93]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[93] gvdd_mux_1level_tapbuf_size2[93] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[278] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[278] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[278] when v(mux_1level_tapbuf_size2[93]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[278] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[278] when v(mux_1level_tapbuf_size2[93]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[278] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[93]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[278] param='mux_1level_tapbuf_size2[93]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[93]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[93]_energy_per_cycle param='mux_1level_tapbuf_size2[93]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[278] param='mux_1level_tapbuf_size2[93]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[278] param='dynamic_power_sb_mux[1][0]_rrnode[278]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[278] avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='start_rise_sb_mux[1][0]_rrnode[278]' to='start_rise_sb_mux[1][0]_rrnode[278]+switch_rise_sb_mux[1][0]_rrnode[278]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[278] avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='start_fall_sb_mux[1][0]_rrnode[278]' to='start_fall_sb_mux[1][0]_rrnode[278]+switch_fall_sb_mux[1][0]_rrnode[278]' -.meas tran sum_leakage_power_mux[0to93] -+ param='sum_leakage_power_mux[0to92]+leakage_sb_mux[1][0]_rrnode[278]' -.meas tran sum_energy_per_cycle_mux[0to93] -+ param='sum_energy_per_cycle_mux[0to92]+energy_per_cycle_sb_mux[1][0]_rrnode[278]' -***** Load for rr_node[278] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=87, type=4 ***** -Xchan_mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[298]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[300]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to93] -+ param='sum_leakage_power_sb_mux[0to92]+leakage_sb_mux[1][0]_rrnode[278]' -.meas tran sum_energy_per_cycle_sb_mux[0to93] -+ param='sum_energy_per_cycle_sb_mux[0to92]+energy_per_cycle_sb_mux[1][0]_rrnode[278]' -Xmux_1level_tapbuf_size2[94] mux_1level_tapbuf_size2[94]->in[0] mux_1level_tapbuf_size2[94]->in[1] mux_1level_tapbuf_size2[94]->out sram[104]->outb sram[104]->out gvdd_mux_1level_tapbuf_size2[94] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[94], level=1, select_path_id=0. ***** -*****1***** -Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[104]->out) 0 -.nodeset V(sram[104]->outb) vsp -***** Signal mux_1level_tapbuf_size2[94]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[94]->in[0] mux_1level_tapbuf_size2[94]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[94]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[94]->in[1] mux_1level_tapbuf_size2[94]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[94] gvdd_mux_1level_tapbuf_size2[94] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[280] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[280] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[280] when v(mux_1level_tapbuf_size2[94]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[280] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[280] when v(mux_1level_tapbuf_size2[94]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[280] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[94]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[280] param='mux_1level_tapbuf_size2[94]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[94]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[94]_energy_per_cycle param='mux_1level_tapbuf_size2[94]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[280] param='mux_1level_tapbuf_size2[94]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[280] param='dynamic_power_sb_mux[1][0]_rrnode[280]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[280] avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='start_rise_sb_mux[1][0]_rrnode[280]' to='start_rise_sb_mux[1][0]_rrnode[280]+switch_rise_sb_mux[1][0]_rrnode[280]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[280] avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='start_fall_sb_mux[1][0]_rrnode[280]' to='start_fall_sb_mux[1][0]_rrnode[280]+switch_fall_sb_mux[1][0]_rrnode[280]' -.meas tran sum_leakage_power_mux[0to94] -+ param='sum_leakage_power_mux[0to93]+leakage_sb_mux[1][0]_rrnode[280]' -.meas tran sum_energy_per_cycle_mux[0to94] -+ param='sum_energy_per_cycle_mux[0to93]+energy_per_cycle_sb_mux[1][0]_rrnode[280]' -***** Load for rr_node[280] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=89, type=4 ***** -Xchan_mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[301]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to94] -+ param='sum_leakage_power_sb_mux[0to93]+leakage_sb_mux[1][0]_rrnode[280]' -.meas tran sum_energy_per_cycle_sb_mux[0to94] -+ param='sum_energy_per_cycle_sb_mux[0to93]+energy_per_cycle_sb_mux[1][0]_rrnode[280]' -Xmux_1level_tapbuf_size2[95] mux_1level_tapbuf_size2[95]->in[0] mux_1level_tapbuf_size2[95]->in[1] mux_1level_tapbuf_size2[95]->out sram[105]->outb sram[105]->out gvdd_mux_1level_tapbuf_size2[95] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[95], level=1, select_path_id=0. ***** -*****1***** -Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[105]->out) 0 -.nodeset V(sram[105]->outb) vsp -***** Signal mux_1level_tapbuf_size2[95]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[95]->in[0] mux_1level_tapbuf_size2[95]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[95]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[95]->in[1] mux_1level_tapbuf_size2[95]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[95] gvdd_mux_1level_tapbuf_size2[95] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[282] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[282] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[282] when v(mux_1level_tapbuf_size2[95]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[282] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[282] when v(mux_1level_tapbuf_size2[95]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[282] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[95]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[282] param='mux_1level_tapbuf_size2[95]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[95]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[95]_energy_per_cycle param='mux_1level_tapbuf_size2[95]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[282] param='mux_1level_tapbuf_size2[95]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[282] param='dynamic_power_sb_mux[1][0]_rrnode[282]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[282] avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='start_rise_sb_mux[1][0]_rrnode[282]' to='start_rise_sb_mux[1][0]_rrnode[282]+switch_rise_sb_mux[1][0]_rrnode[282]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[282] avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='start_fall_sb_mux[1][0]_rrnode[282]' to='start_fall_sb_mux[1][0]_rrnode[282]+switch_fall_sb_mux[1][0]_rrnode[282]' -.meas tran sum_leakage_power_mux[0to95] -+ param='sum_leakage_power_mux[0to94]+leakage_sb_mux[1][0]_rrnode[282]' -.meas tran sum_energy_per_cycle_mux[0to95] -+ param='sum_energy_per_cycle_mux[0to94]+energy_per_cycle_sb_mux[1][0]_rrnode[282]' -***** Load for rr_node[282] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=91, type=4 ***** -Xchan_mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[305]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to95] -+ param='sum_leakage_power_sb_mux[0to94]+leakage_sb_mux[1][0]_rrnode[282]' -.meas tran sum_energy_per_cycle_sb_mux[0to95] -+ param='sum_energy_per_cycle_sb_mux[0to94]+energy_per_cycle_sb_mux[1][0]_rrnode[282]' -Xmux_1level_tapbuf_size2[96] mux_1level_tapbuf_size2[96]->in[0] mux_1level_tapbuf_size2[96]->in[1] mux_1level_tapbuf_size2[96]->out sram[106]->outb sram[106]->out gvdd_mux_1level_tapbuf_size2[96] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[96], level=1, select_path_id=0. ***** -*****1***** -Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[106]->out) 0 -.nodeset V(sram[106]->outb) vsp -***** Signal mux_1level_tapbuf_size2[96]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[96]->in[0] mux_1level_tapbuf_size2[96]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[96]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[96]->in[1] mux_1level_tapbuf_size2[96]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[96] gvdd_mux_1level_tapbuf_size2[96] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[284] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[284] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[284] when v(mux_1level_tapbuf_size2[96]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[284] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[284] when v(mux_1level_tapbuf_size2[96]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[284] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[96]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[284] param='mux_1level_tapbuf_size2[96]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[96]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[96]_energy_per_cycle param='mux_1level_tapbuf_size2[96]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[284] param='mux_1level_tapbuf_size2[96]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[284] param='dynamic_power_sb_mux[1][0]_rrnode[284]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[284] avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='start_rise_sb_mux[1][0]_rrnode[284]' to='start_rise_sb_mux[1][0]_rrnode[284]+switch_rise_sb_mux[1][0]_rrnode[284]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[284] avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='start_fall_sb_mux[1][0]_rrnode[284]' to='start_fall_sb_mux[1][0]_rrnode[284]+switch_fall_sb_mux[1][0]_rrnode[284]' -.meas tran sum_leakage_power_mux[0to96] -+ param='sum_leakage_power_mux[0to95]+leakage_sb_mux[1][0]_rrnode[284]' -.meas tran sum_energy_per_cycle_mux[0to96] -+ param='sum_energy_per_cycle_mux[0to95]+energy_per_cycle_sb_mux[1][0]_rrnode[284]' -***** Load for rr_node[284] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=93, type=4 ***** -Xchan_mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[309]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to96] -+ param='sum_leakage_power_sb_mux[0to95]+leakage_sb_mux[1][0]_rrnode[284]' -.meas tran sum_energy_per_cycle_sb_mux[0to96] -+ param='sum_energy_per_cycle_sb_mux[0to95]+energy_per_cycle_sb_mux[1][0]_rrnode[284]' -Xmux_1level_tapbuf_size2[97] mux_1level_tapbuf_size2[97]->in[0] mux_1level_tapbuf_size2[97]->in[1] mux_1level_tapbuf_size2[97]->out sram[107]->outb sram[107]->out gvdd_mux_1level_tapbuf_size2[97] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[97], level=1, select_path_id=0. ***** -*****1***** -Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[107]->out) 0 -.nodeset V(sram[107]->outb) vsp -***** Signal mux_1level_tapbuf_size2[97]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[97]->in[0] mux_1level_tapbuf_size2[97]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[97]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[97]->in[1] mux_1level_tapbuf_size2[97]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[97] gvdd_mux_1level_tapbuf_size2[97] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[286] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[286] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[286] when v(mux_1level_tapbuf_size2[97]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[286] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[286] when v(mux_1level_tapbuf_size2[97]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[286] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[97]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[286] param='mux_1level_tapbuf_size2[97]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[97]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[97]_energy_per_cycle param='mux_1level_tapbuf_size2[97]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[286] param='mux_1level_tapbuf_size2[97]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[286] param='dynamic_power_sb_mux[1][0]_rrnode[286]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[286] avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='start_rise_sb_mux[1][0]_rrnode[286]' to='start_rise_sb_mux[1][0]_rrnode[286]+switch_rise_sb_mux[1][0]_rrnode[286]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[286] avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='start_fall_sb_mux[1][0]_rrnode[286]' to='start_fall_sb_mux[1][0]_rrnode[286]+switch_fall_sb_mux[1][0]_rrnode[286]' -.meas tran sum_leakage_power_mux[0to97] -+ param='sum_leakage_power_mux[0to96]+leakage_sb_mux[1][0]_rrnode[286]' -.meas tran sum_energy_per_cycle_mux[0to97] -+ param='sum_energy_per_cycle_mux[0to96]+energy_per_cycle_sb_mux[1][0]_rrnode[286]' -***** Load for rr_node[286] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=95, type=4 ***** -Xchan_mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[313]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to97] -+ param='sum_leakage_power_sb_mux[0to96]+leakage_sb_mux[1][0]_rrnode[286]' -.meas tran sum_energy_per_cycle_sb_mux[0to97] -+ param='sum_energy_per_cycle_sb_mux[0to96]+energy_per_cycle_sb_mux[1][0]_rrnode[286]' -Xmux_1level_tapbuf_size2[98] mux_1level_tapbuf_size2[98]->in[0] mux_1level_tapbuf_size2[98]->in[1] mux_1level_tapbuf_size2[98]->out sram[108]->outb sram[108]->out gvdd_mux_1level_tapbuf_size2[98] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[98], level=1, select_path_id=0. ***** -*****1***** -Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[108]->out) 0 -.nodeset V(sram[108]->outb) vsp -***** Signal mux_1level_tapbuf_size2[98]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[98]->in[0] mux_1level_tapbuf_size2[98]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[98]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[98]->in[1] mux_1level_tapbuf_size2[98]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[98] gvdd_mux_1level_tapbuf_size2[98] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[288] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[288] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[288] when v(mux_1level_tapbuf_size2[98]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[288] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[288] when v(mux_1level_tapbuf_size2[98]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[288] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[98]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[288] param='mux_1level_tapbuf_size2[98]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[98]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[98]_energy_per_cycle param='mux_1level_tapbuf_size2[98]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[288] param='mux_1level_tapbuf_size2[98]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[288] param='dynamic_power_sb_mux[1][0]_rrnode[288]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[288] avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='start_rise_sb_mux[1][0]_rrnode[288]' to='start_rise_sb_mux[1][0]_rrnode[288]+switch_rise_sb_mux[1][0]_rrnode[288]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[288] avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='start_fall_sb_mux[1][0]_rrnode[288]' to='start_fall_sb_mux[1][0]_rrnode[288]+switch_fall_sb_mux[1][0]_rrnode[288]' -.meas tran sum_leakage_power_mux[0to98] -+ param='sum_leakage_power_mux[0to97]+leakage_sb_mux[1][0]_rrnode[288]' -.meas tran sum_energy_per_cycle_mux[0to98] -+ param='sum_energy_per_cycle_mux[0to97]+energy_per_cycle_sb_mux[1][0]_rrnode[288]' -***** Load for rr_node[288] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=97, type=4 ***** -Xchan_mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[317]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to98] -+ param='sum_leakage_power_sb_mux[0to97]+leakage_sb_mux[1][0]_rrnode[288]' -.meas tran sum_energy_per_cycle_sb_mux[0to98] -+ param='sum_energy_per_cycle_sb_mux[0to97]+energy_per_cycle_sb_mux[1][0]_rrnode[288]' -Xmux_1level_tapbuf_size2[99] mux_1level_tapbuf_size2[99]->in[0] mux_1level_tapbuf_size2[99]->in[1] mux_1level_tapbuf_size2[99]->out sram[109]->outb sram[109]->out gvdd_mux_1level_tapbuf_size2[99] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[99], level=1, select_path_id=0. ***** -*****1***** -Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[109]->out) 0 -.nodeset V(sram[109]->outb) vsp -***** Signal mux_1level_tapbuf_size2[99]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[99]->in[0] mux_1level_tapbuf_size2[99]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[99]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[99]->in[1] mux_1level_tapbuf_size2[99]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[99] gvdd_mux_1level_tapbuf_size2[99] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][0]_rrnode[290] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][0]_rrnode[290] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][0]_rrnode[290] when v(mux_1level_tapbuf_size2[99]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][0]_rrnode[290] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][0]_rrnode[290] when v(mux_1level_tapbuf_size2[99]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][0]_rrnode[290] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[99]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][0]_rrnode[290] param='mux_1level_tapbuf_size2[99]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[99]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[99]_energy_per_cycle param='mux_1level_tapbuf_size2[99]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][0]_rrnode[290] param='mux_1level_tapbuf_size2[99]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][0]_rrnode[290] param='dynamic_power_sb_mux[1][0]_rrnode[290]*clock_period' -.meas tran dynamic_rise_sb_mux[1][0]_rrnode[290] avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='start_rise_sb_mux[1][0]_rrnode[290]' to='start_rise_sb_mux[1][0]_rrnode[290]+switch_rise_sb_mux[1][0]_rrnode[290]' -.meas tran dynamic_fall_sb_mux[1][0]_rrnode[290] avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='start_fall_sb_mux[1][0]_rrnode[290]' to='start_fall_sb_mux[1][0]_rrnode[290]+switch_fall_sb_mux[1][0]_rrnode[290]' -.meas tran sum_leakage_power_mux[0to99] -+ param='sum_leakage_power_mux[0to98]+leakage_sb_mux[1][0]_rrnode[290]' -.meas tran sum_energy_per_cycle_mux[0to99] -+ param='sum_energy_per_cycle_mux[0to98]+energy_per_cycle_sb_mux[1][0]_rrnode[290]' -***** Load for rr_node[290] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=99, type=4 ***** -Xchan_mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[320]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to99] -+ param='sum_leakage_power_sb_mux[0to98]+leakage_sb_mux[1][0]_rrnode[290]' -.meas tran sum_energy_per_cycle_sb_mux[0to99] -+ param='sum_energy_per_cycle_sb_mux[0to98]+energy_per_cycle_sb_mux[1][0]_rrnode[290]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='6*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to99] -+ param='sum_leakage_power_mux[0to99]' -.meas tran total_energy_per_cycle_mux[0to99] -+ param='sum_energy_per_cycle_mux[0to99]' -.meas tran total_leakage_power_sb_mux -+ param='sum_leakage_power_sb_mux[0to99]' -.meas tran total_energy_per_cycle_sb_mux -+ param='sum_energy_per_cycle_sb_mux[0to99]' -.end diff --git a/examples/spice_test_example_2/sb_mux_tb/example_2_sb1_1_sbmux_testbench.sp b/examples/spice_test_example_2/sb_mux_tb/example_2_sb1_1_sbmux_testbench.sp deleted file mode 100644 index 0786e4603..000000000 --- a/examples/spice_test_example_2/sb_mux_tb/example_2_sb1_1_sbmux_testbench.sp +++ /dev/null @@ -1,5436 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Routing MUX Test Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -Xmux_1level_tapbuf_size3[0] mux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->out sram[0]->outb sram[0]->out sram[1]->out sram[1]->outb sram[2]->out sram[2]->outb gvdd_mux_1level_tapbuf_size3[0] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[0], level=1, select_path_id=0. ***** -*****100***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -***** Signal mux_1level_tapbuf_size3[0]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[0] mux_1level_tapbuf_size3[0]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[1] mux_1level_tapbuf_size3[0]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[0]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[0]->in[2] mux_1level_tapbuf_size3[0]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[0] gvdd_mux_1level_tapbuf_size3[0] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[492] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[492] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[492] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[492] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[492] when v(mux_1level_tapbuf_size3[0]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[492] trig v(mux_1level_tapbuf_size3[0]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[0]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[492] param='mux_1level_tapbuf_size3[0]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[0]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[0]_energy_per_cycle param='mux_1level_tapbuf_size3[0]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[492] param='mux_1level_tapbuf_size3[0]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[492] param='dynamic_power_sb_mux[1][1]_rrnode[492]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[492] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_rise_sb_mux[1][1]_rrnode[492]' to='start_rise_sb_mux[1][1]_rrnode[492]+switch_rise_sb_mux[1][1]_rrnode[492]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[492] avg p(Vgvdd_mux_1level_tapbuf_size3[0]) from='start_fall_sb_mux[1][1]_rrnode[492]' to='start_fall_sb_mux[1][1]_rrnode[492]+switch_fall_sb_mux[1][1]_rrnode[492]' -.meas tran sum_leakage_power_mux[0to0] -+ param='leakage_sb_mux[1][1]_rrnode[492]' -.meas tran sum_energy_per_cycle_mux[0to0] -+ param='energy_per_cycle_sb_mux[1][1]_rrnode[492]' -***** Load for rr_node[492] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=1, type=5 ***** -Xchan_mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out mux_1level_tapbuf_size3[0]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[0]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to0] -+ param='leakage_sb_mux[1][1]_rrnode[492]' -.meas tran sum_energy_per_cycle_sb_mux[0to0] -+ param='energy_per_cycle_sb_mux[1][1]_rrnode[492]' -Xmux_1level_tapbuf_size3[1] mux_1level_tapbuf_size3[1]->in[0] mux_1level_tapbuf_size3[1]->in[1] mux_1level_tapbuf_size3[1]->in[2] mux_1level_tapbuf_size3[1]->out sram[3]->outb sram[3]->out sram[4]->out sram[4]->outb sram[5]->out sram[5]->outb gvdd_mux_1level_tapbuf_size3[1] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[1], level=1, select_path_id=0. ***** -*****100***** -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -***** Signal mux_1level_tapbuf_size3[1]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[0] mux_1level_tapbuf_size3[1]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[1]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[1] mux_1level_tapbuf_size3[1]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[1]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[1]->in[2] mux_1level_tapbuf_size3[1]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[1] gvdd_mux_1level_tapbuf_size3[1] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[494] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[494] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[494] when v(mux_1level_tapbuf_size3[1]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[494] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[494] when v(mux_1level_tapbuf_size3[1]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[494] trig v(mux_1level_tapbuf_size3[1]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[1]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[1]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[494] param='mux_1level_tapbuf_size3[1]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[1]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[1]_energy_per_cycle param='mux_1level_tapbuf_size3[1]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[494] param='mux_1level_tapbuf_size3[1]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[494] param='dynamic_power_sb_mux[1][1]_rrnode[494]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[494] avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='start_rise_sb_mux[1][1]_rrnode[494]' to='start_rise_sb_mux[1][1]_rrnode[494]+switch_rise_sb_mux[1][1]_rrnode[494]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[494] avg p(Vgvdd_mux_1level_tapbuf_size3[1]) from='start_fall_sb_mux[1][1]_rrnode[494]' to='start_fall_sb_mux[1][1]_rrnode[494]+switch_fall_sb_mux[1][1]_rrnode[494]' -.meas tran sum_leakage_power_mux[0to1] -+ param='sum_leakage_power_mux[0to0]+leakage_sb_mux[1][1]_rrnode[494]' -.meas tran sum_energy_per_cycle_mux[0to1] -+ param='sum_energy_per_cycle_mux[0to0]+energy_per_cycle_sb_mux[1][1]_rrnode[494]' -***** Load for rr_node[494] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=3, type=5 ***** -Xchan_mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out mux_1level_tapbuf_size3[1]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[1]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to1] -+ param='sum_leakage_power_sb_mux[0to0]+leakage_sb_mux[1][1]_rrnode[494]' -.meas tran sum_energy_per_cycle_sb_mux[0to1] -+ param='sum_energy_per_cycle_sb_mux[0to0]+energy_per_cycle_sb_mux[1][1]_rrnode[494]' -Xmux_1level_tapbuf_size3[2] mux_1level_tapbuf_size3[2]->in[0] mux_1level_tapbuf_size3[2]->in[1] mux_1level_tapbuf_size3[2]->in[2] mux_1level_tapbuf_size3[2]->out sram[6]->outb sram[6]->out sram[7]->out sram[7]->outb sram[8]->out sram[8]->outb gvdd_mux_1level_tapbuf_size3[2] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[2], level=1, select_path_id=0. ***** -*****100***** -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -***** Signal mux_1level_tapbuf_size3[2]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[0] mux_1level_tapbuf_size3[2]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[2]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[1] mux_1level_tapbuf_size3[2]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[2]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[2]->in[2] mux_1level_tapbuf_size3[2]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[2] gvdd_mux_1level_tapbuf_size3[2] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[496] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[496] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[496] when v(mux_1level_tapbuf_size3[2]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[496] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[496] when v(mux_1level_tapbuf_size3[2]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[496] trig v(mux_1level_tapbuf_size3[2]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[2]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[2]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[496] param='mux_1level_tapbuf_size3[2]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[2]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[2]_energy_per_cycle param='mux_1level_tapbuf_size3[2]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[496] param='mux_1level_tapbuf_size3[2]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[496] param='dynamic_power_sb_mux[1][1]_rrnode[496]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[496] avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='start_rise_sb_mux[1][1]_rrnode[496]' to='start_rise_sb_mux[1][1]_rrnode[496]+switch_rise_sb_mux[1][1]_rrnode[496]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[496] avg p(Vgvdd_mux_1level_tapbuf_size3[2]) from='start_fall_sb_mux[1][1]_rrnode[496]' to='start_fall_sb_mux[1][1]_rrnode[496]+switch_fall_sb_mux[1][1]_rrnode[496]' -.meas tran sum_leakage_power_mux[0to2] -+ param='sum_leakage_power_mux[0to1]+leakage_sb_mux[1][1]_rrnode[496]' -.meas tran sum_energy_per_cycle_mux[0to2] -+ param='sum_energy_per_cycle_mux[0to1]+energy_per_cycle_sb_mux[1][1]_rrnode[496]' -***** Load for rr_node[496] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=5, type=5 ***** -Xchan_mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[5]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out mux_1level_tapbuf_size3[2]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[2]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to2] -+ param='sum_leakage_power_sb_mux[0to1]+leakage_sb_mux[1][1]_rrnode[496]' -.meas tran sum_energy_per_cycle_sb_mux[0to2] -+ param='sum_energy_per_cycle_sb_mux[0to1]+energy_per_cycle_sb_mux[1][1]_rrnode[496]' -Xmux_1level_tapbuf_size3[3] mux_1level_tapbuf_size3[3]->in[0] mux_1level_tapbuf_size3[3]->in[1] mux_1level_tapbuf_size3[3]->in[2] mux_1level_tapbuf_size3[3]->out sram[9]->outb sram[9]->out sram[10]->out sram[10]->outb sram[11]->out sram[11]->outb gvdd_mux_1level_tapbuf_size3[3] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[3], level=1, select_path_id=0. ***** -*****100***** -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -***** Signal mux_1level_tapbuf_size3[3]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[3]->in[0] mux_1level_tapbuf_size3[3]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[3]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[3]->in[1] mux_1level_tapbuf_size3[3]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[3]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[3]->in[2] mux_1level_tapbuf_size3[3]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[3] gvdd_mux_1level_tapbuf_size3[3] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[498] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[498] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[498] when v(mux_1level_tapbuf_size3[3]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[498] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[498] when v(mux_1level_tapbuf_size3[3]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[498] trig v(mux_1level_tapbuf_size3[3]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[3]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[3]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[498] param='mux_1level_tapbuf_size3[3]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[3]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[3]_energy_per_cycle param='mux_1level_tapbuf_size3[3]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[498] param='mux_1level_tapbuf_size3[3]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[498] param='dynamic_power_sb_mux[1][1]_rrnode[498]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[498] avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from='start_rise_sb_mux[1][1]_rrnode[498]' to='start_rise_sb_mux[1][1]_rrnode[498]+switch_rise_sb_mux[1][1]_rrnode[498]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[498] avg p(Vgvdd_mux_1level_tapbuf_size3[3]) from='start_fall_sb_mux[1][1]_rrnode[498]' to='start_fall_sb_mux[1][1]_rrnode[498]+switch_fall_sb_mux[1][1]_rrnode[498]' -.meas tran sum_leakage_power_mux[0to3] -+ param='sum_leakage_power_mux[0to2]+leakage_sb_mux[1][1]_rrnode[498]' -.meas tran sum_energy_per_cycle_mux[0to3] -+ param='sum_energy_per_cycle_mux[0to2]+energy_per_cycle_sb_mux[1][1]_rrnode[498]' -***** Load for rr_node[498] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=7, type=5 ***** -Xchan_mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out mux_1level_tapbuf_size3[3]->out mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[8]_no0 mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out mux_1level_tapbuf_size3[3]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[3]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to3] -+ param='sum_leakage_power_sb_mux[0to2]+leakage_sb_mux[1][1]_rrnode[498]' -.meas tran sum_energy_per_cycle_sb_mux[0to3] -+ param='sum_energy_per_cycle_sb_mux[0to2]+energy_per_cycle_sb_mux[1][1]_rrnode[498]' -Xmux_1level_tapbuf_size3[4] mux_1level_tapbuf_size3[4]->in[0] mux_1level_tapbuf_size3[4]->in[1] mux_1level_tapbuf_size3[4]->in[2] mux_1level_tapbuf_size3[4]->out sram[12]->outb sram[12]->out sram[13]->out sram[13]->outb sram[14]->out sram[14]->outb gvdd_mux_1level_tapbuf_size3[4] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****100***** -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -***** Signal mux_1level_tapbuf_size3[4]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[4]->in[0] mux_1level_tapbuf_size3[4]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[4]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[4]->in[1] mux_1level_tapbuf_size3[4]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[4]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[4]->in[2] mux_1level_tapbuf_size3[4]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[4] gvdd_mux_1level_tapbuf_size3[4] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[500] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[500] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[500] when v(mux_1level_tapbuf_size3[4]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[500] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[500] when v(mux_1level_tapbuf_size3[4]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[500] trig v(mux_1level_tapbuf_size3[4]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[4]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[4]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[500] param='mux_1level_tapbuf_size3[4]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[4]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[4]_energy_per_cycle param='mux_1level_tapbuf_size3[4]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[500] param='mux_1level_tapbuf_size3[4]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[500] param='dynamic_power_sb_mux[1][1]_rrnode[500]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[500] avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from='start_rise_sb_mux[1][1]_rrnode[500]' to='start_rise_sb_mux[1][1]_rrnode[500]+switch_rise_sb_mux[1][1]_rrnode[500]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[500] avg p(Vgvdd_mux_1level_tapbuf_size3[4]) from='start_fall_sb_mux[1][1]_rrnode[500]' to='start_fall_sb_mux[1][1]_rrnode[500]+switch_fall_sb_mux[1][1]_rrnode[500]' -.meas tran sum_leakage_power_mux[0to4] -+ param='sum_leakage_power_mux[0to3]+leakage_sb_mux[1][1]_rrnode[500]' -.meas tran sum_energy_per_cycle_mux[0to4] -+ param='sum_energy_per_cycle_mux[0to3]+energy_per_cycle_sb_mux[1][1]_rrnode[500]' -***** Load for rr_node[500] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=9, type=5 ***** -Xchan_mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out mux_1level_tapbuf_size3[4]->out mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[11]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out mux_1level_tapbuf_size3[4]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[4]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to4] -+ param='sum_leakage_power_sb_mux[0to3]+leakage_sb_mux[1][1]_rrnode[500]' -.meas tran sum_energy_per_cycle_sb_mux[0to4] -+ param='sum_energy_per_cycle_sb_mux[0to3]+energy_per_cycle_sb_mux[1][1]_rrnode[500]' -Xmux_1level_tapbuf_size2[5] mux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->out sram[15]->outb sram[15]->out gvdd_mux_1level_tapbuf_size2[5] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[5], level=1, select_path_id=0. ***** -*****1***** -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -***** Signal mux_1level_tapbuf_size2[5]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[0] mux_1level_tapbuf_size2[5]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[5]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[5]->in[1] mux_1level_tapbuf_size2[5]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[5] gvdd_mux_1level_tapbuf_size2[5] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[502] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[502] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[502] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[502] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[502] when v(mux_1level_tapbuf_size2[5]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[502] trig v(mux_1level_tapbuf_size2[5]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[5]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[502] param='mux_1level_tapbuf_size2[5]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[5]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[5]_energy_per_cycle param='mux_1level_tapbuf_size2[5]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[502] param='mux_1level_tapbuf_size2[5]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[502] param='dynamic_power_sb_mux[1][1]_rrnode[502]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[502] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_rise_sb_mux[1][1]_rrnode[502]' to='start_rise_sb_mux[1][1]_rrnode[502]+switch_rise_sb_mux[1][1]_rrnode[502]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[502] avg p(Vgvdd_mux_1level_tapbuf_size2[5]) from='start_fall_sb_mux[1][1]_rrnode[502]' to='start_fall_sb_mux[1][1]_rrnode[502]+switch_fall_sb_mux[1][1]_rrnode[502]' -.meas tran sum_leakage_power_mux[0to5] -+ param='sum_leakage_power_mux[0to4]+leakage_sb_mux[1][1]_rrnode[502]' -.meas tran sum_energy_per_cycle_mux[0to5] -+ param='sum_energy_per_cycle_mux[0to4]+energy_per_cycle_sb_mux[1][1]_rrnode[502]' -***** Load for rr_node[502] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=11, type=5 ***** -Xchan_mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[14]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out mux_1level_tapbuf_size2[5]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[5]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to5] -+ param='sum_leakage_power_sb_mux[0to4]+leakage_sb_mux[1][1]_rrnode[502]' -.meas tran sum_energy_per_cycle_sb_mux[0to5] -+ param='sum_energy_per_cycle_sb_mux[0to4]+energy_per_cycle_sb_mux[1][1]_rrnode[502]' -Xmux_1level_tapbuf_size2[6] mux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->out sram[16]->outb sram[16]->out gvdd_mux_1level_tapbuf_size2[6] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[6], level=1, select_path_id=0. ***** -*****1***** -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -***** Signal mux_1level_tapbuf_size2[6]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[0] mux_1level_tapbuf_size2[6]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[6]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[6]->in[1] mux_1level_tapbuf_size2[6]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[6] gvdd_mux_1level_tapbuf_size2[6] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[504] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[504] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[504] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[504] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[504] when v(mux_1level_tapbuf_size2[6]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[504] trig v(mux_1level_tapbuf_size2[6]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[6]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[504] param='mux_1level_tapbuf_size2[6]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[6]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[6]_energy_per_cycle param='mux_1level_tapbuf_size2[6]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[504] param='mux_1level_tapbuf_size2[6]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[504] param='dynamic_power_sb_mux[1][1]_rrnode[504]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[504] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_rise_sb_mux[1][1]_rrnode[504]' to='start_rise_sb_mux[1][1]_rrnode[504]+switch_rise_sb_mux[1][1]_rrnode[504]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[504] avg p(Vgvdd_mux_1level_tapbuf_size2[6]) from='start_fall_sb_mux[1][1]_rrnode[504]' to='start_fall_sb_mux[1][1]_rrnode[504]+switch_fall_sb_mux[1][1]_rrnode[504]' -.meas tran sum_leakage_power_mux[0to6] -+ param='sum_leakage_power_mux[0to5]+leakage_sb_mux[1][1]_rrnode[504]' -.meas tran sum_energy_per_cycle_mux[0to6] -+ param='sum_energy_per_cycle_mux[0to5]+energy_per_cycle_sb_mux[1][1]_rrnode[504]' -***** Load for rr_node[504] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=13, type=5 ***** -Xchan_mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[16]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out mux_1level_tapbuf_size2[6]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[6]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to6] -+ param='sum_leakage_power_sb_mux[0to5]+leakage_sb_mux[1][1]_rrnode[504]' -.meas tran sum_energy_per_cycle_sb_mux[0to6] -+ param='sum_energy_per_cycle_sb_mux[0to5]+energy_per_cycle_sb_mux[1][1]_rrnode[504]' -Xmux_1level_tapbuf_size2[7] mux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->out sram[17]->outb sram[17]->out gvdd_mux_1level_tapbuf_size2[7] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[7], level=1, select_path_id=0. ***** -*****1***** -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -***** Signal mux_1level_tapbuf_size2[7]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[0] mux_1level_tapbuf_size2[7]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[7]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[7]->in[1] mux_1level_tapbuf_size2[7]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[7] gvdd_mux_1level_tapbuf_size2[7] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[506] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[506] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[506] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[506] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[506] when v(mux_1level_tapbuf_size2[7]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[506] trig v(mux_1level_tapbuf_size2[7]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[7]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[506] param='mux_1level_tapbuf_size2[7]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[7]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[7]_energy_per_cycle param='mux_1level_tapbuf_size2[7]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[506] param='mux_1level_tapbuf_size2[7]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[506] param='dynamic_power_sb_mux[1][1]_rrnode[506]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[506] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_rise_sb_mux[1][1]_rrnode[506]' to='start_rise_sb_mux[1][1]_rrnode[506]+switch_rise_sb_mux[1][1]_rrnode[506]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[506] avg p(Vgvdd_mux_1level_tapbuf_size2[7]) from='start_fall_sb_mux[1][1]_rrnode[506]' to='start_fall_sb_mux[1][1]_rrnode[506]+switch_fall_sb_mux[1][1]_rrnode[506]' -.meas tran sum_leakage_power_mux[0to7] -+ param='sum_leakage_power_mux[0to6]+leakage_sb_mux[1][1]_rrnode[506]' -.meas tran sum_energy_per_cycle_mux[0to7] -+ param='sum_energy_per_cycle_mux[0to6]+energy_per_cycle_sb_mux[1][1]_rrnode[506]' -***** Load for rr_node[506] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=15, type=5 ***** -Xchan_mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[19]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out mux_1level_tapbuf_size2[7]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[7]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to7] -+ param='sum_leakage_power_sb_mux[0to6]+leakage_sb_mux[1][1]_rrnode[506]' -.meas tran sum_energy_per_cycle_sb_mux[0to7] -+ param='sum_energy_per_cycle_sb_mux[0to6]+energy_per_cycle_sb_mux[1][1]_rrnode[506]' -Xmux_1level_tapbuf_size2[8] mux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->out sram[18]->outb sram[18]->out gvdd_mux_1level_tapbuf_size2[8] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[8], level=1, select_path_id=0. ***** -*****1***** -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -***** Signal mux_1level_tapbuf_size2[8]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[0] mux_1level_tapbuf_size2[8]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[8]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[8]->in[1] mux_1level_tapbuf_size2[8]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[8] gvdd_mux_1level_tapbuf_size2[8] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[508] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[508] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[508] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[508] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[508] when v(mux_1level_tapbuf_size2[8]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[508] trig v(mux_1level_tapbuf_size2[8]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[8]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[508] param='mux_1level_tapbuf_size2[8]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[8]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[8]_energy_per_cycle param='mux_1level_tapbuf_size2[8]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[508] param='mux_1level_tapbuf_size2[8]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[508] param='dynamic_power_sb_mux[1][1]_rrnode[508]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[508] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_rise_sb_mux[1][1]_rrnode[508]' to='start_rise_sb_mux[1][1]_rrnode[508]+switch_rise_sb_mux[1][1]_rrnode[508]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[508] avg p(Vgvdd_mux_1level_tapbuf_size2[8]) from='start_fall_sb_mux[1][1]_rrnode[508]' to='start_fall_sb_mux[1][1]_rrnode[508]+switch_fall_sb_mux[1][1]_rrnode[508]' -.meas tran sum_leakage_power_mux[0to8] -+ param='sum_leakage_power_mux[0to7]+leakage_sb_mux[1][1]_rrnode[508]' -.meas tran sum_energy_per_cycle_mux[0to8] -+ param='sum_energy_per_cycle_mux[0to7]+energy_per_cycle_sb_mux[1][1]_rrnode[508]' -***** Load for rr_node[508] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=17, type=5 ***** -Xchan_mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[21]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out mux_1level_tapbuf_size2[8]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[8]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to8] -+ param='sum_leakage_power_sb_mux[0to7]+leakage_sb_mux[1][1]_rrnode[508]' -.meas tran sum_energy_per_cycle_sb_mux[0to8] -+ param='sum_energy_per_cycle_sb_mux[0to7]+energy_per_cycle_sb_mux[1][1]_rrnode[508]' -Xmux_1level_tapbuf_size2[9] mux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->out sram[19]->outb sram[19]->out gvdd_mux_1level_tapbuf_size2[9] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[9], level=1, select_path_id=0. ***** -*****1***** -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -***** Signal mux_1level_tapbuf_size2[9]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[9]->in[0] mux_1level_tapbuf_size2[9]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[9]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[9]->in[1] mux_1level_tapbuf_size2[9]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[9] gvdd_mux_1level_tapbuf_size2[9] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[510] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[510] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[510] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[510] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[510] when v(mux_1level_tapbuf_size2[9]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[510] trig v(mux_1level_tapbuf_size2[9]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[9]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[510] param='mux_1level_tapbuf_size2[9]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[9]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[9]_energy_per_cycle param='mux_1level_tapbuf_size2[9]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[510] param='mux_1level_tapbuf_size2[9]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[510] param='dynamic_power_sb_mux[1][1]_rrnode[510]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[510] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_rise_sb_mux[1][1]_rrnode[510]' to='start_rise_sb_mux[1][1]_rrnode[510]+switch_rise_sb_mux[1][1]_rrnode[510]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[510] avg p(Vgvdd_mux_1level_tapbuf_size2[9]) from='start_fall_sb_mux[1][1]_rrnode[510]' to='start_fall_sb_mux[1][1]_rrnode[510]+switch_fall_sb_mux[1][1]_rrnode[510]' -.meas tran sum_leakage_power_mux[0to9] -+ param='sum_leakage_power_mux[0to8]+leakage_sb_mux[1][1]_rrnode[510]' -.meas tran sum_energy_per_cycle_mux[0to9] -+ param='sum_energy_per_cycle_mux[0to8]+energy_per_cycle_sb_mux[1][1]_rrnode[510]' -***** Load for rr_node[510] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=19, type=5 ***** -Xchan_mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[23]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out mux_1level_tapbuf_size2[9]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[9]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to9] -+ param='sum_leakage_power_sb_mux[0to8]+leakage_sb_mux[1][1]_rrnode[510]' -.meas tran sum_energy_per_cycle_sb_mux[0to9] -+ param='sum_energy_per_cycle_sb_mux[0to8]+energy_per_cycle_sb_mux[1][1]_rrnode[510]' -Xmux_1level_tapbuf_size2[10] mux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->out sram[20]->outb sram[20]->out gvdd_mux_1level_tapbuf_size2[10] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[10], level=1, select_path_id=0. ***** -*****1***** -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -***** Signal mux_1level_tapbuf_size2[10]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[10]->in[0] mux_1level_tapbuf_size2[10]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[10]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[10]->in[1] mux_1level_tapbuf_size2[10]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[10] gvdd_mux_1level_tapbuf_size2[10] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[512] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[512] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[512] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[512] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[512] when v(mux_1level_tapbuf_size2[10]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[512] trig v(mux_1level_tapbuf_size2[10]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[10]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[512] param='mux_1level_tapbuf_size2[10]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[10]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[10]_energy_per_cycle param='mux_1level_tapbuf_size2[10]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[512] param='mux_1level_tapbuf_size2[10]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[512] param='dynamic_power_sb_mux[1][1]_rrnode[512]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[512] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_rise_sb_mux[1][1]_rrnode[512]' to='start_rise_sb_mux[1][1]_rrnode[512]+switch_rise_sb_mux[1][1]_rrnode[512]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[512] avg p(Vgvdd_mux_1level_tapbuf_size2[10]) from='start_fall_sb_mux[1][1]_rrnode[512]' to='start_fall_sb_mux[1][1]_rrnode[512]+switch_fall_sb_mux[1][1]_rrnode[512]' -.meas tran sum_leakage_power_mux[0to10] -+ param='sum_leakage_power_mux[0to9]+leakage_sb_mux[1][1]_rrnode[512]' -.meas tran sum_energy_per_cycle_mux[0to10] -+ param='sum_energy_per_cycle_mux[0to9]+energy_per_cycle_sb_mux[1][1]_rrnode[512]' -***** Load for rr_node[512] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=21, type=5 ***** -Xchan_mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[26]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out mux_1level_tapbuf_size2[10]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[10]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to10] -+ param='sum_leakage_power_sb_mux[0to9]+leakage_sb_mux[1][1]_rrnode[512]' -.meas tran sum_energy_per_cycle_sb_mux[0to10] -+ param='sum_energy_per_cycle_sb_mux[0to9]+energy_per_cycle_sb_mux[1][1]_rrnode[512]' -Xmux_1level_tapbuf_size2[11] mux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->out sram[21]->outb sram[21]->out gvdd_mux_1level_tapbuf_size2[11] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[11], level=1, select_path_id=0. ***** -*****1***** -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -***** Signal mux_1level_tapbuf_size2[11]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[11]->in[0] mux_1level_tapbuf_size2[11]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[11]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[11]->in[1] mux_1level_tapbuf_size2[11]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[11] gvdd_mux_1level_tapbuf_size2[11] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[514] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[514] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[514] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[514] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[514] when v(mux_1level_tapbuf_size2[11]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[514] trig v(mux_1level_tapbuf_size2[11]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[11]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[514] param='mux_1level_tapbuf_size2[11]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[11]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[11]_energy_per_cycle param='mux_1level_tapbuf_size2[11]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[514] param='mux_1level_tapbuf_size2[11]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[514] param='dynamic_power_sb_mux[1][1]_rrnode[514]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[514] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_rise_sb_mux[1][1]_rrnode[514]' to='start_rise_sb_mux[1][1]_rrnode[514]+switch_rise_sb_mux[1][1]_rrnode[514]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[514] avg p(Vgvdd_mux_1level_tapbuf_size2[11]) from='start_fall_sb_mux[1][1]_rrnode[514]' to='start_fall_sb_mux[1][1]_rrnode[514]+switch_fall_sb_mux[1][1]_rrnode[514]' -.meas tran sum_leakage_power_mux[0to11] -+ param='sum_leakage_power_mux[0to10]+leakage_sb_mux[1][1]_rrnode[514]' -.meas tran sum_energy_per_cycle_mux[0to11] -+ param='sum_energy_per_cycle_mux[0to10]+energy_per_cycle_sb_mux[1][1]_rrnode[514]' -***** Load for rr_node[514] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=23, type=5 ***** -Xchan_mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[28]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out mux_1level_tapbuf_size2[11]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[11]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to11] -+ param='sum_leakage_power_sb_mux[0to10]+leakage_sb_mux[1][1]_rrnode[514]' -.meas tran sum_energy_per_cycle_sb_mux[0to11] -+ param='sum_energy_per_cycle_sb_mux[0to10]+energy_per_cycle_sb_mux[1][1]_rrnode[514]' -Xmux_1level_tapbuf_size2[12] mux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->out sram[22]->outb sram[22]->out gvdd_mux_1level_tapbuf_size2[12] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[12], level=1, select_path_id=0. ***** -*****1***** -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -***** Signal mux_1level_tapbuf_size2[12]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[12]->in[0] mux_1level_tapbuf_size2[12]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[12]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[12]->in[1] mux_1level_tapbuf_size2[12]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[12] gvdd_mux_1level_tapbuf_size2[12] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[516] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[516] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[516] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[516] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[516] when v(mux_1level_tapbuf_size2[12]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[516] trig v(mux_1level_tapbuf_size2[12]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[12]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[516] param='mux_1level_tapbuf_size2[12]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[12]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[12]_energy_per_cycle param='mux_1level_tapbuf_size2[12]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[516] param='mux_1level_tapbuf_size2[12]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[516] param='dynamic_power_sb_mux[1][1]_rrnode[516]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[516] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_rise_sb_mux[1][1]_rrnode[516]' to='start_rise_sb_mux[1][1]_rrnode[516]+switch_rise_sb_mux[1][1]_rrnode[516]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[516] avg p(Vgvdd_mux_1level_tapbuf_size2[12]) from='start_fall_sb_mux[1][1]_rrnode[516]' to='start_fall_sb_mux[1][1]_rrnode[516]+switch_fall_sb_mux[1][1]_rrnode[516]' -.meas tran sum_leakage_power_mux[0to12] -+ param='sum_leakage_power_mux[0to11]+leakage_sb_mux[1][1]_rrnode[516]' -.meas tran sum_energy_per_cycle_mux[0to12] -+ param='sum_energy_per_cycle_mux[0to11]+energy_per_cycle_sb_mux[1][1]_rrnode[516]' -***** Load for rr_node[516] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=25, type=5 ***** -Xchan_mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[31]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out mux_1level_tapbuf_size2[12]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[12]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to12] -+ param='sum_leakage_power_sb_mux[0to11]+leakage_sb_mux[1][1]_rrnode[516]' -.meas tran sum_energy_per_cycle_sb_mux[0to12] -+ param='sum_energy_per_cycle_sb_mux[0to11]+energy_per_cycle_sb_mux[1][1]_rrnode[516]' -Xmux_1level_tapbuf_size2[13] mux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->out sram[23]->outb sram[23]->out gvdd_mux_1level_tapbuf_size2[13] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[13], level=1, select_path_id=0. ***** -*****1***** -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -***** Signal mux_1level_tapbuf_size2[13]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[13]->in[0] mux_1level_tapbuf_size2[13]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[13]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[13]->in[1] mux_1level_tapbuf_size2[13]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[13] gvdd_mux_1level_tapbuf_size2[13] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[518] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[518] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[518] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[518] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[518] when v(mux_1level_tapbuf_size2[13]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[518] trig v(mux_1level_tapbuf_size2[13]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[13]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[518] param='mux_1level_tapbuf_size2[13]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[13]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[13]_energy_per_cycle param='mux_1level_tapbuf_size2[13]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[518] param='mux_1level_tapbuf_size2[13]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[518] param='dynamic_power_sb_mux[1][1]_rrnode[518]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[518] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_rise_sb_mux[1][1]_rrnode[518]' to='start_rise_sb_mux[1][1]_rrnode[518]+switch_rise_sb_mux[1][1]_rrnode[518]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[518] avg p(Vgvdd_mux_1level_tapbuf_size2[13]) from='start_fall_sb_mux[1][1]_rrnode[518]' to='start_fall_sb_mux[1][1]_rrnode[518]+switch_fall_sb_mux[1][1]_rrnode[518]' -.meas tran sum_leakage_power_mux[0to13] -+ param='sum_leakage_power_mux[0to12]+leakage_sb_mux[1][1]_rrnode[518]' -.meas tran sum_energy_per_cycle_mux[0to13] -+ param='sum_energy_per_cycle_mux[0to12]+energy_per_cycle_sb_mux[1][1]_rrnode[518]' -***** Load for rr_node[518] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=27, type=5 ***** -Xchan_mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[34]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out mux_1level_tapbuf_size2[13]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[13]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to13] -+ param='sum_leakage_power_sb_mux[0to12]+leakage_sb_mux[1][1]_rrnode[518]' -.meas tran sum_energy_per_cycle_sb_mux[0to13] -+ param='sum_energy_per_cycle_sb_mux[0to12]+energy_per_cycle_sb_mux[1][1]_rrnode[518]' -Xmux_1level_tapbuf_size2[14] mux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->out sram[24]->outb sram[24]->out gvdd_mux_1level_tapbuf_size2[14] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[14], level=1, select_path_id=0. ***** -*****1***** -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -***** Signal mux_1level_tapbuf_size2[14]->in[0] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[14]->in[0] mux_1level_tapbuf_size2[14]->in[0] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -***** Signal mux_1level_tapbuf_size2[14]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[14]->in[1] mux_1level_tapbuf_size2[14]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[14] gvdd_mux_1level_tapbuf_size2[14] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[520] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[520] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[520] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[520] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[520] when v(mux_1level_tapbuf_size2[14]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[520] trig v(mux_1level_tapbuf_size2[14]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[14]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[520] param='mux_1level_tapbuf_size2[14]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[14]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[14]_energy_per_cycle param='mux_1level_tapbuf_size2[14]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[520] param='mux_1level_tapbuf_size2[14]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[520] param='dynamic_power_sb_mux[1][1]_rrnode[520]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[520] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_rise_sb_mux[1][1]_rrnode[520]' to='start_rise_sb_mux[1][1]_rrnode[520]+switch_rise_sb_mux[1][1]_rrnode[520]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[520] avg p(Vgvdd_mux_1level_tapbuf_size2[14]) from='start_fall_sb_mux[1][1]_rrnode[520]' to='start_fall_sb_mux[1][1]_rrnode[520]+switch_fall_sb_mux[1][1]_rrnode[520]' -.meas tran sum_leakage_power_mux[0to14] -+ param='sum_leakage_power_mux[0to13]+leakage_sb_mux[1][1]_rrnode[520]' -.meas tran sum_energy_per_cycle_mux[0to14] -+ param='sum_energy_per_cycle_mux[0to13]+energy_per_cycle_sb_mux[1][1]_rrnode[520]' -***** Load for rr_node[520] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=29, type=5 ***** -Xchan_mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[36]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out mux_1level_tapbuf_size2[14]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[14]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to14] -+ param='sum_leakage_power_sb_mux[0to13]+leakage_sb_mux[1][1]_rrnode[520]' -.meas tran sum_energy_per_cycle_sb_mux[0to14] -+ param='sum_energy_per_cycle_sb_mux[0to13]+energy_per_cycle_sb_mux[1][1]_rrnode[520]' -Xmux_1level_tapbuf_size2[15] mux_1level_tapbuf_size2[15]->in[0] mux_1level_tapbuf_size2[15]->in[1] mux_1level_tapbuf_size2[15]->out sram[25]->outb sram[25]->out gvdd_mux_1level_tapbuf_size2[15] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[15], level=1, select_path_id=0. ***** -*****1***** -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -***** Signal mux_1level_tapbuf_size2[15]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[15]->in[0] mux_1level_tapbuf_size2[15]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[15]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[15]->in[1] mux_1level_tapbuf_size2[15]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[15] gvdd_mux_1level_tapbuf_size2[15] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[522] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[522] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[522] when v(mux_1level_tapbuf_size2[15]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[522] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[522] when v(mux_1level_tapbuf_size2[15]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[522] trig v(mux_1level_tapbuf_size2[15]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[15]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[15]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[522] param='mux_1level_tapbuf_size2[15]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[15]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[15]_energy_per_cycle param='mux_1level_tapbuf_size2[15]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[522] param='mux_1level_tapbuf_size2[15]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[522] param='dynamic_power_sb_mux[1][1]_rrnode[522]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[522] avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='start_rise_sb_mux[1][1]_rrnode[522]' to='start_rise_sb_mux[1][1]_rrnode[522]+switch_rise_sb_mux[1][1]_rrnode[522]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[522] avg p(Vgvdd_mux_1level_tapbuf_size2[15]) from='start_fall_sb_mux[1][1]_rrnode[522]' to='start_fall_sb_mux[1][1]_rrnode[522]+switch_fall_sb_mux[1][1]_rrnode[522]' -.meas tran sum_leakage_power_mux[0to15] -+ param='sum_leakage_power_mux[0to14]+leakage_sb_mux[1][1]_rrnode[522]' -.meas tran sum_energy_per_cycle_mux[0to15] -+ param='sum_energy_per_cycle_mux[0to14]+energy_per_cycle_sb_mux[1][1]_rrnode[522]' -***** Load for rr_node[522] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=31, type=5 ***** -Xchan_mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[39]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out mux_1level_tapbuf_size2[15]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[15]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to15] -+ param='sum_leakage_power_sb_mux[0to14]+leakage_sb_mux[1][1]_rrnode[522]' -.meas tran sum_energy_per_cycle_sb_mux[0to15] -+ param='sum_energy_per_cycle_sb_mux[0to14]+energy_per_cycle_sb_mux[1][1]_rrnode[522]' -Xmux_1level_tapbuf_size2[16] mux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->out sram[26]->outb sram[26]->out gvdd_mux_1level_tapbuf_size2[16] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[16], level=1, select_path_id=0. ***** -*****1***** -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -***** Signal mux_1level_tapbuf_size2[16]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[0] mux_1level_tapbuf_size2[16]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[16]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[16]->in[1] mux_1level_tapbuf_size2[16]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[16] gvdd_mux_1level_tapbuf_size2[16] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[524] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[524] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[524] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[524] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[524] when v(mux_1level_tapbuf_size2[16]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[524] trig v(mux_1level_tapbuf_size2[16]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[16]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[524] param='mux_1level_tapbuf_size2[16]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[16]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[16]_energy_per_cycle param='mux_1level_tapbuf_size2[16]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[524] param='mux_1level_tapbuf_size2[16]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[524] param='dynamic_power_sb_mux[1][1]_rrnode[524]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[524] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_rise_sb_mux[1][1]_rrnode[524]' to='start_rise_sb_mux[1][1]_rrnode[524]+switch_rise_sb_mux[1][1]_rrnode[524]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[524] avg p(Vgvdd_mux_1level_tapbuf_size2[16]) from='start_fall_sb_mux[1][1]_rrnode[524]' to='start_fall_sb_mux[1][1]_rrnode[524]+switch_fall_sb_mux[1][1]_rrnode[524]' -.meas tran sum_leakage_power_mux[0to16] -+ param='sum_leakage_power_mux[0to15]+leakage_sb_mux[1][1]_rrnode[524]' -.meas tran sum_energy_per_cycle_mux[0to16] -+ param='sum_energy_per_cycle_mux[0to15]+energy_per_cycle_sb_mux[1][1]_rrnode[524]' -***** Load for rr_node[524] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=33, type=5 ***** -Xchan_mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[42]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out mux_1level_tapbuf_size2[16]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[16]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to16] -+ param='sum_leakage_power_sb_mux[0to15]+leakage_sb_mux[1][1]_rrnode[524]' -.meas tran sum_energy_per_cycle_sb_mux[0to16] -+ param='sum_energy_per_cycle_sb_mux[0to15]+energy_per_cycle_sb_mux[1][1]_rrnode[524]' -Xmux_1level_tapbuf_size2[17] mux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->out sram[27]->outb sram[27]->out gvdd_mux_1level_tapbuf_size2[17] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[17], level=1, select_path_id=0. ***** -*****1***** -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -***** Signal mux_1level_tapbuf_size2[17]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[0] mux_1level_tapbuf_size2[17]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[17]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[17]->in[1] mux_1level_tapbuf_size2[17]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[17] gvdd_mux_1level_tapbuf_size2[17] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[526] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[526] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[526] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[526] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[526] when v(mux_1level_tapbuf_size2[17]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[526] trig v(mux_1level_tapbuf_size2[17]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[17]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[526] param='mux_1level_tapbuf_size2[17]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[17]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[17]_energy_per_cycle param='mux_1level_tapbuf_size2[17]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[526] param='mux_1level_tapbuf_size2[17]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[526] param='dynamic_power_sb_mux[1][1]_rrnode[526]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[526] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_rise_sb_mux[1][1]_rrnode[526]' to='start_rise_sb_mux[1][1]_rrnode[526]+switch_rise_sb_mux[1][1]_rrnode[526]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[526] avg p(Vgvdd_mux_1level_tapbuf_size2[17]) from='start_fall_sb_mux[1][1]_rrnode[526]' to='start_fall_sb_mux[1][1]_rrnode[526]+switch_fall_sb_mux[1][1]_rrnode[526]' -.meas tran sum_leakage_power_mux[0to17] -+ param='sum_leakage_power_mux[0to16]+leakage_sb_mux[1][1]_rrnode[526]' -.meas tran sum_energy_per_cycle_mux[0to17] -+ param='sum_energy_per_cycle_mux[0to16]+energy_per_cycle_sb_mux[1][1]_rrnode[526]' -***** Load for rr_node[526] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=35, type=5 ***** -Xchan_mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[45]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out mux_1level_tapbuf_size2[17]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[17]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to17] -+ param='sum_leakage_power_sb_mux[0to16]+leakage_sb_mux[1][1]_rrnode[526]' -.meas tran sum_energy_per_cycle_sb_mux[0to17] -+ param='sum_energy_per_cycle_sb_mux[0to16]+energy_per_cycle_sb_mux[1][1]_rrnode[526]' -Xmux_1level_tapbuf_size2[18] mux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->out sram[28]->outb sram[28]->out gvdd_mux_1level_tapbuf_size2[18] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[18], level=1, select_path_id=0. ***** -*****1***** -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -***** Signal mux_1level_tapbuf_size2[18]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[0] mux_1level_tapbuf_size2[18]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[18]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[18]->in[1] mux_1level_tapbuf_size2[18]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[18] gvdd_mux_1level_tapbuf_size2[18] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[528] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[528] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[528] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[528] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[528] when v(mux_1level_tapbuf_size2[18]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[528] trig v(mux_1level_tapbuf_size2[18]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[18]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[528] param='mux_1level_tapbuf_size2[18]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[18]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[18]_energy_per_cycle param='mux_1level_tapbuf_size2[18]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[528] param='mux_1level_tapbuf_size2[18]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[528] param='dynamic_power_sb_mux[1][1]_rrnode[528]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[528] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_rise_sb_mux[1][1]_rrnode[528]' to='start_rise_sb_mux[1][1]_rrnode[528]+switch_rise_sb_mux[1][1]_rrnode[528]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[528] avg p(Vgvdd_mux_1level_tapbuf_size2[18]) from='start_fall_sb_mux[1][1]_rrnode[528]' to='start_fall_sb_mux[1][1]_rrnode[528]+switch_fall_sb_mux[1][1]_rrnode[528]' -.meas tran sum_leakage_power_mux[0to18] -+ param='sum_leakage_power_mux[0to17]+leakage_sb_mux[1][1]_rrnode[528]' -.meas tran sum_energy_per_cycle_mux[0to18] -+ param='sum_energy_per_cycle_mux[0to17]+energy_per_cycle_sb_mux[1][1]_rrnode[528]' -***** Load for rr_node[528] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=37, type=5 ***** -Xchan_mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[48]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out mux_1level_tapbuf_size2[18]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[18]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to18] -+ param='sum_leakage_power_sb_mux[0to17]+leakage_sb_mux[1][1]_rrnode[528]' -.meas tran sum_energy_per_cycle_sb_mux[0to18] -+ param='sum_energy_per_cycle_sb_mux[0to17]+energy_per_cycle_sb_mux[1][1]_rrnode[528]' -Xmux_1level_tapbuf_size2[19] mux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->out sram[29]->outb sram[29]->out gvdd_mux_1level_tapbuf_size2[19] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[19], level=1, select_path_id=0. ***** -*****1***** -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -***** Signal mux_1level_tapbuf_size2[19]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[0] mux_1level_tapbuf_size2[19]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[19]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[19]->in[1] mux_1level_tapbuf_size2[19]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[19] gvdd_mux_1level_tapbuf_size2[19] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[530] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[530] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[530] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[530] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[530] when v(mux_1level_tapbuf_size2[19]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[530] trig v(mux_1level_tapbuf_size2[19]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[19]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[530] param='mux_1level_tapbuf_size2[19]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[19]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[19]_energy_per_cycle param='mux_1level_tapbuf_size2[19]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[530] param='mux_1level_tapbuf_size2[19]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[530] param='dynamic_power_sb_mux[1][1]_rrnode[530]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[530] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_rise_sb_mux[1][1]_rrnode[530]' to='start_rise_sb_mux[1][1]_rrnode[530]+switch_rise_sb_mux[1][1]_rrnode[530]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[530] avg p(Vgvdd_mux_1level_tapbuf_size2[19]) from='start_fall_sb_mux[1][1]_rrnode[530]' to='start_fall_sb_mux[1][1]_rrnode[530]+switch_fall_sb_mux[1][1]_rrnode[530]' -.meas tran sum_leakage_power_mux[0to19] -+ param='sum_leakage_power_mux[0to18]+leakage_sb_mux[1][1]_rrnode[530]' -.meas tran sum_energy_per_cycle_mux[0to19] -+ param='sum_energy_per_cycle_mux[0to18]+energy_per_cycle_sb_mux[1][1]_rrnode[530]' -***** Load for rr_node[530] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=39, type=5 ***** -Xchan_mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[50]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out mux_1level_tapbuf_size2[19]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[19]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to19] -+ param='sum_leakage_power_sb_mux[0to18]+leakage_sb_mux[1][1]_rrnode[530]' -.meas tran sum_energy_per_cycle_sb_mux[0to19] -+ param='sum_energy_per_cycle_sb_mux[0to18]+energy_per_cycle_sb_mux[1][1]_rrnode[530]' -Xmux_1level_tapbuf_size2[20] mux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->out sram[30]->outb sram[30]->out gvdd_mux_1level_tapbuf_size2[20] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[20], level=1, select_path_id=0. ***** -*****1***** -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -***** Signal mux_1level_tapbuf_size2[20]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[0] mux_1level_tapbuf_size2[20]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[20]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[20]->in[1] mux_1level_tapbuf_size2[20]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[20] gvdd_mux_1level_tapbuf_size2[20] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[532] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[532] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[532] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[532] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[532] when v(mux_1level_tapbuf_size2[20]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[532] trig v(mux_1level_tapbuf_size2[20]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[20]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[532] param='mux_1level_tapbuf_size2[20]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[20]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[20]_energy_per_cycle param='mux_1level_tapbuf_size2[20]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[532] param='mux_1level_tapbuf_size2[20]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[532] param='dynamic_power_sb_mux[1][1]_rrnode[532]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[532] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_rise_sb_mux[1][1]_rrnode[532]' to='start_rise_sb_mux[1][1]_rrnode[532]+switch_rise_sb_mux[1][1]_rrnode[532]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[532] avg p(Vgvdd_mux_1level_tapbuf_size2[20]) from='start_fall_sb_mux[1][1]_rrnode[532]' to='start_fall_sb_mux[1][1]_rrnode[532]+switch_fall_sb_mux[1][1]_rrnode[532]' -.meas tran sum_leakage_power_mux[0to20] -+ param='sum_leakage_power_mux[0to19]+leakage_sb_mux[1][1]_rrnode[532]' -.meas tran sum_energy_per_cycle_mux[0to20] -+ param='sum_energy_per_cycle_mux[0to19]+energy_per_cycle_sb_mux[1][1]_rrnode[532]' -***** Load for rr_node[532] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=41, type=5 ***** -Xchan_mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[52]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out mux_1level_tapbuf_size2[20]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[20]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to20] -+ param='sum_leakage_power_sb_mux[0to19]+leakage_sb_mux[1][1]_rrnode[532]' -.meas tran sum_energy_per_cycle_sb_mux[0to20] -+ param='sum_energy_per_cycle_sb_mux[0to19]+energy_per_cycle_sb_mux[1][1]_rrnode[532]' -Xmux_1level_tapbuf_size2[21] mux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->out sram[31]->outb sram[31]->out gvdd_mux_1level_tapbuf_size2[21] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[21], level=1, select_path_id=0. ***** -*****1***** -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -***** Signal mux_1level_tapbuf_size2[21]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[0] mux_1level_tapbuf_size2[21]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[21]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[21]->in[1] mux_1level_tapbuf_size2[21]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[21] gvdd_mux_1level_tapbuf_size2[21] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[534] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[534] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[534] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[534] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[534] when v(mux_1level_tapbuf_size2[21]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[534] trig v(mux_1level_tapbuf_size2[21]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[21]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[534] param='mux_1level_tapbuf_size2[21]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[21]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[21]_energy_per_cycle param='mux_1level_tapbuf_size2[21]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[534] param='mux_1level_tapbuf_size2[21]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[534] param='dynamic_power_sb_mux[1][1]_rrnode[534]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[534] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_rise_sb_mux[1][1]_rrnode[534]' to='start_rise_sb_mux[1][1]_rrnode[534]+switch_rise_sb_mux[1][1]_rrnode[534]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[534] avg p(Vgvdd_mux_1level_tapbuf_size2[21]) from='start_fall_sb_mux[1][1]_rrnode[534]' to='start_fall_sb_mux[1][1]_rrnode[534]+switch_fall_sb_mux[1][1]_rrnode[534]' -.meas tran sum_leakage_power_mux[0to21] -+ param='sum_leakage_power_mux[0to20]+leakage_sb_mux[1][1]_rrnode[534]' -.meas tran sum_energy_per_cycle_mux[0to21] -+ param='sum_energy_per_cycle_mux[0to20]+energy_per_cycle_sb_mux[1][1]_rrnode[534]' -***** Load for rr_node[534] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=43, type=5 ***** -Xchan_mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[54]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out mux_1level_tapbuf_size2[21]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[21]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to21] -+ param='sum_leakage_power_sb_mux[0to20]+leakage_sb_mux[1][1]_rrnode[534]' -.meas tran sum_energy_per_cycle_sb_mux[0to21] -+ param='sum_energy_per_cycle_sb_mux[0to20]+energy_per_cycle_sb_mux[1][1]_rrnode[534]' -Xmux_1level_tapbuf_size2[22] mux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->out sram[32]->outb sram[32]->out gvdd_mux_1level_tapbuf_size2[22] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[22], level=1, select_path_id=0. ***** -*****1***** -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -***** Signal mux_1level_tapbuf_size2[22]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[0] mux_1level_tapbuf_size2[22]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[22]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[22]->in[1] mux_1level_tapbuf_size2[22]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[22] gvdd_mux_1level_tapbuf_size2[22] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[536] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[536] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[536] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[536] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[536] when v(mux_1level_tapbuf_size2[22]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[536] trig v(mux_1level_tapbuf_size2[22]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[22]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[536] param='mux_1level_tapbuf_size2[22]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[22]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[22]_energy_per_cycle param='mux_1level_tapbuf_size2[22]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[536] param='mux_1level_tapbuf_size2[22]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[536] param='dynamic_power_sb_mux[1][1]_rrnode[536]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[536] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_rise_sb_mux[1][1]_rrnode[536]' to='start_rise_sb_mux[1][1]_rrnode[536]+switch_rise_sb_mux[1][1]_rrnode[536]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[536] avg p(Vgvdd_mux_1level_tapbuf_size2[22]) from='start_fall_sb_mux[1][1]_rrnode[536]' to='start_fall_sb_mux[1][1]_rrnode[536]+switch_fall_sb_mux[1][1]_rrnode[536]' -.meas tran sum_leakage_power_mux[0to22] -+ param='sum_leakage_power_mux[0to21]+leakage_sb_mux[1][1]_rrnode[536]' -.meas tran sum_energy_per_cycle_mux[0to22] -+ param='sum_energy_per_cycle_mux[0to21]+energy_per_cycle_sb_mux[1][1]_rrnode[536]' -***** Load for rr_node[536] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=45, type=5 ***** -Xchan_mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[57]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out mux_1level_tapbuf_size2[22]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[22]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to22] -+ param='sum_leakage_power_sb_mux[0to21]+leakage_sb_mux[1][1]_rrnode[536]' -.meas tran sum_energy_per_cycle_sb_mux[0to22] -+ param='sum_energy_per_cycle_sb_mux[0to21]+energy_per_cycle_sb_mux[1][1]_rrnode[536]' -Xmux_1level_tapbuf_size2[23] mux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->out sram[33]->outb sram[33]->out gvdd_mux_1level_tapbuf_size2[23] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[23], level=1, select_path_id=0. ***** -*****1***** -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -***** Signal mux_1level_tapbuf_size2[23]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[0] mux_1level_tapbuf_size2[23]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[23]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[23]->in[1] mux_1level_tapbuf_size2[23]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[23] gvdd_mux_1level_tapbuf_size2[23] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[538] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[538] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[538] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[538] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[538] when v(mux_1level_tapbuf_size2[23]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[538] trig v(mux_1level_tapbuf_size2[23]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[23]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[538] param='mux_1level_tapbuf_size2[23]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[23]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[23]_energy_per_cycle param='mux_1level_tapbuf_size2[23]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[538] param='mux_1level_tapbuf_size2[23]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[538] param='dynamic_power_sb_mux[1][1]_rrnode[538]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[538] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_rise_sb_mux[1][1]_rrnode[538]' to='start_rise_sb_mux[1][1]_rrnode[538]+switch_rise_sb_mux[1][1]_rrnode[538]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[538] avg p(Vgvdd_mux_1level_tapbuf_size2[23]) from='start_fall_sb_mux[1][1]_rrnode[538]' to='start_fall_sb_mux[1][1]_rrnode[538]+switch_fall_sb_mux[1][1]_rrnode[538]' -.meas tran sum_leakage_power_mux[0to23] -+ param='sum_leakage_power_mux[0to22]+leakage_sb_mux[1][1]_rrnode[538]' -.meas tran sum_energy_per_cycle_mux[0to23] -+ param='sum_energy_per_cycle_mux[0to22]+energy_per_cycle_sb_mux[1][1]_rrnode[538]' -***** Load for rr_node[538] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=47, type=5 ***** -Xchan_mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[60]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out mux_1level_tapbuf_size2[23]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[23]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to23] -+ param='sum_leakage_power_sb_mux[0to22]+leakage_sb_mux[1][1]_rrnode[538]' -.meas tran sum_energy_per_cycle_sb_mux[0to23] -+ param='sum_energy_per_cycle_sb_mux[0to22]+energy_per_cycle_sb_mux[1][1]_rrnode[538]' -Xmux_1level_tapbuf_size2[24] mux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->out sram[34]->outb sram[34]->out gvdd_mux_1level_tapbuf_size2[24] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[24], level=1, select_path_id=0. ***** -*****1***** -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -***** Signal mux_1level_tapbuf_size2[24]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[0] mux_1level_tapbuf_size2[24]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[24]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[24]->in[1] mux_1level_tapbuf_size2[24]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[24] gvdd_mux_1level_tapbuf_size2[24] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[540] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[540] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[540] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[540] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[540] when v(mux_1level_tapbuf_size2[24]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[540] trig v(mux_1level_tapbuf_size2[24]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[24]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[540] param='mux_1level_tapbuf_size2[24]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[24]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[24]_energy_per_cycle param='mux_1level_tapbuf_size2[24]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[540] param='mux_1level_tapbuf_size2[24]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[540] param='dynamic_power_sb_mux[1][1]_rrnode[540]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[540] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_rise_sb_mux[1][1]_rrnode[540]' to='start_rise_sb_mux[1][1]_rrnode[540]+switch_rise_sb_mux[1][1]_rrnode[540]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[540] avg p(Vgvdd_mux_1level_tapbuf_size2[24]) from='start_fall_sb_mux[1][1]_rrnode[540]' to='start_fall_sb_mux[1][1]_rrnode[540]+switch_fall_sb_mux[1][1]_rrnode[540]' -.meas tran sum_leakage_power_mux[0to24] -+ param='sum_leakage_power_mux[0to23]+leakage_sb_mux[1][1]_rrnode[540]' -.meas tran sum_energy_per_cycle_mux[0to24] -+ param='sum_energy_per_cycle_mux[0to23]+energy_per_cycle_sb_mux[1][1]_rrnode[540]' -***** Load for rr_node[540] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=49, type=5 ***** -Xchan_mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[63]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out mux_1level_tapbuf_size2[24]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[24]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to24] -+ param='sum_leakage_power_sb_mux[0to23]+leakage_sb_mux[1][1]_rrnode[540]' -.meas tran sum_energy_per_cycle_sb_mux[0to24] -+ param='sum_energy_per_cycle_sb_mux[0to23]+energy_per_cycle_sb_mux[1][1]_rrnode[540]' -Xmux_1level_tapbuf_size2[25] mux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->out sram[35]->outb sram[35]->out gvdd_mux_1level_tapbuf_size2[25] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[25], level=1, select_path_id=0. ***** -*****1***** -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -***** Signal mux_1level_tapbuf_size2[25]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[0] mux_1level_tapbuf_size2[25]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[25]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[25]->in[1] mux_1level_tapbuf_size2[25]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[25] gvdd_mux_1level_tapbuf_size2[25] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[542] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[542] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[542] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[542] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[542] when v(mux_1level_tapbuf_size2[25]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[542] trig v(mux_1level_tapbuf_size2[25]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[25]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[542] param='mux_1level_tapbuf_size2[25]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[25]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[25]_energy_per_cycle param='mux_1level_tapbuf_size2[25]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[542] param='mux_1level_tapbuf_size2[25]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[542] param='dynamic_power_sb_mux[1][1]_rrnode[542]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[542] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_rise_sb_mux[1][1]_rrnode[542]' to='start_rise_sb_mux[1][1]_rrnode[542]+switch_rise_sb_mux[1][1]_rrnode[542]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[542] avg p(Vgvdd_mux_1level_tapbuf_size2[25]) from='start_fall_sb_mux[1][1]_rrnode[542]' to='start_fall_sb_mux[1][1]_rrnode[542]+switch_fall_sb_mux[1][1]_rrnode[542]' -.meas tran sum_leakage_power_mux[0to25] -+ param='sum_leakage_power_mux[0to24]+leakage_sb_mux[1][1]_rrnode[542]' -.meas tran sum_energy_per_cycle_mux[0to25] -+ param='sum_energy_per_cycle_mux[0to24]+energy_per_cycle_sb_mux[1][1]_rrnode[542]' -***** Load for rr_node[542] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=51, type=5 ***** -Xchan_mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[66]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out mux_1level_tapbuf_size2[25]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[25]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to25] -+ param='sum_leakage_power_sb_mux[0to24]+leakage_sb_mux[1][1]_rrnode[542]' -.meas tran sum_energy_per_cycle_sb_mux[0to25] -+ param='sum_energy_per_cycle_sb_mux[0to24]+energy_per_cycle_sb_mux[1][1]_rrnode[542]' -Xmux_1level_tapbuf_size2[26] mux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->out sram[36]->outb sram[36]->out gvdd_mux_1level_tapbuf_size2[26] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[26], level=1, select_path_id=0. ***** -*****1***** -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -***** Signal mux_1level_tapbuf_size2[26]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[0] mux_1level_tapbuf_size2[26]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[26]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[26]->in[1] mux_1level_tapbuf_size2[26]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[26] gvdd_mux_1level_tapbuf_size2[26] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[544] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[544] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[544] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[544] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[544] when v(mux_1level_tapbuf_size2[26]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[544] trig v(mux_1level_tapbuf_size2[26]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[26]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[544] param='mux_1level_tapbuf_size2[26]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[26]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[26]_energy_per_cycle param='mux_1level_tapbuf_size2[26]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[544] param='mux_1level_tapbuf_size2[26]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[544] param='dynamic_power_sb_mux[1][1]_rrnode[544]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[544] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_rise_sb_mux[1][1]_rrnode[544]' to='start_rise_sb_mux[1][1]_rrnode[544]+switch_rise_sb_mux[1][1]_rrnode[544]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[544] avg p(Vgvdd_mux_1level_tapbuf_size2[26]) from='start_fall_sb_mux[1][1]_rrnode[544]' to='start_fall_sb_mux[1][1]_rrnode[544]+switch_fall_sb_mux[1][1]_rrnode[544]' -.meas tran sum_leakage_power_mux[0to26] -+ param='sum_leakage_power_mux[0to25]+leakage_sb_mux[1][1]_rrnode[544]' -.meas tran sum_energy_per_cycle_mux[0to26] -+ param='sum_energy_per_cycle_mux[0to25]+energy_per_cycle_sb_mux[1][1]_rrnode[544]' -***** Load for rr_node[544] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=53, type=5 ***** -Xchan_mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[68]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out mux_1level_tapbuf_size2[26]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[26]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to26] -+ param='sum_leakage_power_sb_mux[0to25]+leakage_sb_mux[1][1]_rrnode[544]' -.meas tran sum_energy_per_cycle_sb_mux[0to26] -+ param='sum_energy_per_cycle_sb_mux[0to25]+energy_per_cycle_sb_mux[1][1]_rrnode[544]' -Xmux_1level_tapbuf_size2[27] mux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->out sram[37]->outb sram[37]->out gvdd_mux_1level_tapbuf_size2[27] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[27], level=1, select_path_id=0. ***** -*****1***** -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -***** Signal mux_1level_tapbuf_size2[27]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[0] mux_1level_tapbuf_size2[27]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[27]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[27]->in[1] mux_1level_tapbuf_size2[27]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[27] gvdd_mux_1level_tapbuf_size2[27] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[546] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[546] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[546] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[546] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[546] when v(mux_1level_tapbuf_size2[27]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[546] trig v(mux_1level_tapbuf_size2[27]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[27]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[546] param='mux_1level_tapbuf_size2[27]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[27]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[27]_energy_per_cycle param='mux_1level_tapbuf_size2[27]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[546] param='mux_1level_tapbuf_size2[27]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[546] param='dynamic_power_sb_mux[1][1]_rrnode[546]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[546] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_rise_sb_mux[1][1]_rrnode[546]' to='start_rise_sb_mux[1][1]_rrnode[546]+switch_rise_sb_mux[1][1]_rrnode[546]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[546] avg p(Vgvdd_mux_1level_tapbuf_size2[27]) from='start_fall_sb_mux[1][1]_rrnode[546]' to='start_fall_sb_mux[1][1]_rrnode[546]+switch_fall_sb_mux[1][1]_rrnode[546]' -.meas tran sum_leakage_power_mux[0to27] -+ param='sum_leakage_power_mux[0to26]+leakage_sb_mux[1][1]_rrnode[546]' -.meas tran sum_energy_per_cycle_mux[0to27] -+ param='sum_energy_per_cycle_mux[0to26]+energy_per_cycle_sb_mux[1][1]_rrnode[546]' -***** Load for rr_node[546] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=55, type=5 ***** -Xchan_mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[71]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out mux_1level_tapbuf_size2[27]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[27]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to27] -+ param='sum_leakage_power_sb_mux[0to26]+leakage_sb_mux[1][1]_rrnode[546]' -.meas tran sum_energy_per_cycle_sb_mux[0to27] -+ param='sum_energy_per_cycle_sb_mux[0to26]+energy_per_cycle_sb_mux[1][1]_rrnode[546]' -Xmux_1level_tapbuf_size2[28] mux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->out sram[38]->outb sram[38]->out gvdd_mux_1level_tapbuf_size2[28] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[28], level=1, select_path_id=0. ***** -*****1***** -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -***** Signal mux_1level_tapbuf_size2[28]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[0] mux_1level_tapbuf_size2[28]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[28]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[28]->in[1] mux_1level_tapbuf_size2[28]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[28] gvdd_mux_1level_tapbuf_size2[28] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[548] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[548] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[548] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[548] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[548] when v(mux_1level_tapbuf_size2[28]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[548] trig v(mux_1level_tapbuf_size2[28]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[28]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[548] param='mux_1level_tapbuf_size2[28]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[28]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[28]_energy_per_cycle param='mux_1level_tapbuf_size2[28]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[548] param='mux_1level_tapbuf_size2[28]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[548] param='dynamic_power_sb_mux[1][1]_rrnode[548]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[548] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_rise_sb_mux[1][1]_rrnode[548]' to='start_rise_sb_mux[1][1]_rrnode[548]+switch_rise_sb_mux[1][1]_rrnode[548]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[548] avg p(Vgvdd_mux_1level_tapbuf_size2[28]) from='start_fall_sb_mux[1][1]_rrnode[548]' to='start_fall_sb_mux[1][1]_rrnode[548]+switch_fall_sb_mux[1][1]_rrnode[548]' -.meas tran sum_leakage_power_mux[0to28] -+ param='sum_leakage_power_mux[0to27]+leakage_sb_mux[1][1]_rrnode[548]' -.meas tran sum_energy_per_cycle_mux[0to28] -+ param='sum_energy_per_cycle_mux[0to27]+energy_per_cycle_sb_mux[1][1]_rrnode[548]' -***** Load for rr_node[548] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=57, type=5 ***** -Xchan_mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[73]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out mux_1level_tapbuf_size2[28]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[28]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to28] -+ param='sum_leakage_power_sb_mux[0to27]+leakage_sb_mux[1][1]_rrnode[548]' -.meas tran sum_energy_per_cycle_sb_mux[0to28] -+ param='sum_energy_per_cycle_sb_mux[0to27]+energy_per_cycle_sb_mux[1][1]_rrnode[548]' -Xmux_1level_tapbuf_size2[29] mux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->out sram[39]->outb sram[39]->out gvdd_mux_1level_tapbuf_size2[29] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[29], level=1, select_path_id=0. ***** -*****1***** -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -***** Signal mux_1level_tapbuf_size2[29]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[0] mux_1level_tapbuf_size2[29]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[29]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[29]->in[1] mux_1level_tapbuf_size2[29]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[29] gvdd_mux_1level_tapbuf_size2[29] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[550] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[550] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[550] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[550] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[550] when v(mux_1level_tapbuf_size2[29]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[550] trig v(mux_1level_tapbuf_size2[29]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[29]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[550] param='mux_1level_tapbuf_size2[29]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[29]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[29]_energy_per_cycle param='mux_1level_tapbuf_size2[29]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[550] param='mux_1level_tapbuf_size2[29]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[550] param='dynamic_power_sb_mux[1][1]_rrnode[550]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[550] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_rise_sb_mux[1][1]_rrnode[550]' to='start_rise_sb_mux[1][1]_rrnode[550]+switch_rise_sb_mux[1][1]_rrnode[550]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[550] avg p(Vgvdd_mux_1level_tapbuf_size2[29]) from='start_fall_sb_mux[1][1]_rrnode[550]' to='start_fall_sb_mux[1][1]_rrnode[550]+switch_fall_sb_mux[1][1]_rrnode[550]' -.meas tran sum_leakage_power_mux[0to29] -+ param='sum_leakage_power_mux[0to28]+leakage_sb_mux[1][1]_rrnode[550]' -.meas tran sum_energy_per_cycle_mux[0to29] -+ param='sum_energy_per_cycle_mux[0to28]+energy_per_cycle_sb_mux[1][1]_rrnode[550]' -***** Load for rr_node[550] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=59, type=5 ***** -Xchan_mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[75]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out mux_1level_tapbuf_size2[29]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[29]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to29] -+ param='sum_leakage_power_sb_mux[0to28]+leakage_sb_mux[1][1]_rrnode[550]' -.meas tran sum_energy_per_cycle_sb_mux[0to29] -+ param='sum_energy_per_cycle_sb_mux[0to28]+energy_per_cycle_sb_mux[1][1]_rrnode[550]' -Xmux_1level_tapbuf_size2[30] mux_1level_tapbuf_size2[30]->in[0] mux_1level_tapbuf_size2[30]->in[1] mux_1level_tapbuf_size2[30]->out sram[40]->outb sram[40]->out gvdd_mux_1level_tapbuf_size2[30] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[30], level=1, select_path_id=0. ***** -*****1***** -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -***** Signal mux_1level_tapbuf_size2[30]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[30]->in[0] mux_1level_tapbuf_size2[30]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[30]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[30]->in[1] mux_1level_tapbuf_size2[30]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[30] gvdd_mux_1level_tapbuf_size2[30] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[552] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[552] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[552] when v(mux_1level_tapbuf_size2[30]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[552] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[552] when v(mux_1level_tapbuf_size2[30]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[552] trig v(mux_1level_tapbuf_size2[30]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[30]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[30]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[552] param='mux_1level_tapbuf_size2[30]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[30]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[30]_energy_per_cycle param='mux_1level_tapbuf_size2[30]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[552] param='mux_1level_tapbuf_size2[30]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[552] param='dynamic_power_sb_mux[1][1]_rrnode[552]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[552] avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='start_rise_sb_mux[1][1]_rrnode[552]' to='start_rise_sb_mux[1][1]_rrnode[552]+switch_rise_sb_mux[1][1]_rrnode[552]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[552] avg p(Vgvdd_mux_1level_tapbuf_size2[30]) from='start_fall_sb_mux[1][1]_rrnode[552]' to='start_fall_sb_mux[1][1]_rrnode[552]+switch_fall_sb_mux[1][1]_rrnode[552]' -.meas tran sum_leakage_power_mux[0to30] -+ param='sum_leakage_power_mux[0to29]+leakage_sb_mux[1][1]_rrnode[552]' -.meas tran sum_energy_per_cycle_mux[0to30] -+ param='sum_energy_per_cycle_mux[0to29]+energy_per_cycle_sb_mux[1][1]_rrnode[552]' -***** Load for rr_node[552] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=61, type=5 ***** -Xchan_mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[78]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out mux_1level_tapbuf_size2[30]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[30]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to30] -+ param='sum_leakage_power_sb_mux[0to29]+leakage_sb_mux[1][1]_rrnode[552]' -.meas tran sum_energy_per_cycle_sb_mux[0to30] -+ param='sum_energy_per_cycle_sb_mux[0to29]+energy_per_cycle_sb_mux[1][1]_rrnode[552]' -Xmux_1level_tapbuf_size2[31] mux_1level_tapbuf_size2[31]->in[0] mux_1level_tapbuf_size2[31]->in[1] mux_1level_tapbuf_size2[31]->out sram[41]->outb sram[41]->out gvdd_mux_1level_tapbuf_size2[31] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[31], level=1, select_path_id=0. ***** -*****1***** -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -***** Signal mux_1level_tapbuf_size2[31]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[31]->in[0] mux_1level_tapbuf_size2[31]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[31]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[31]->in[1] mux_1level_tapbuf_size2[31]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[31] gvdd_mux_1level_tapbuf_size2[31] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[554] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[554] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[554] when v(mux_1level_tapbuf_size2[31]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[554] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[554] when v(mux_1level_tapbuf_size2[31]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[554] trig v(mux_1level_tapbuf_size2[31]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[31]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[31]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[554] param='mux_1level_tapbuf_size2[31]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[31]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[31]_energy_per_cycle param='mux_1level_tapbuf_size2[31]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[554] param='mux_1level_tapbuf_size2[31]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[554] param='dynamic_power_sb_mux[1][1]_rrnode[554]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[554] avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='start_rise_sb_mux[1][1]_rrnode[554]' to='start_rise_sb_mux[1][1]_rrnode[554]+switch_rise_sb_mux[1][1]_rrnode[554]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[554] avg p(Vgvdd_mux_1level_tapbuf_size2[31]) from='start_fall_sb_mux[1][1]_rrnode[554]' to='start_fall_sb_mux[1][1]_rrnode[554]+switch_fall_sb_mux[1][1]_rrnode[554]' -.meas tran sum_leakage_power_mux[0to31] -+ param='sum_leakage_power_mux[0to30]+leakage_sb_mux[1][1]_rrnode[554]' -.meas tran sum_energy_per_cycle_mux[0to31] -+ param='sum_energy_per_cycle_mux[0to30]+energy_per_cycle_sb_mux[1][1]_rrnode[554]' -***** Load for rr_node[554] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=63, type=5 ***** -Xchan_mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[80]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out mux_1level_tapbuf_size2[31]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[31]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to31] -+ param='sum_leakage_power_sb_mux[0to30]+leakage_sb_mux[1][1]_rrnode[554]' -.meas tran sum_energy_per_cycle_sb_mux[0to31] -+ param='sum_energy_per_cycle_sb_mux[0to30]+energy_per_cycle_sb_mux[1][1]_rrnode[554]' -Xmux_1level_tapbuf_size2[32] mux_1level_tapbuf_size2[32]->in[0] mux_1level_tapbuf_size2[32]->in[1] mux_1level_tapbuf_size2[32]->out sram[42]->outb sram[42]->out gvdd_mux_1level_tapbuf_size2[32] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[32], level=1, select_path_id=0. ***** -*****1***** -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -***** Signal mux_1level_tapbuf_size2[32]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[32]->in[0] mux_1level_tapbuf_size2[32]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[32]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[32]->in[1] mux_1level_tapbuf_size2[32]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[32] gvdd_mux_1level_tapbuf_size2[32] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[556] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[556] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[556] when v(mux_1level_tapbuf_size2[32]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[556] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[556] when v(mux_1level_tapbuf_size2[32]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[556] trig v(mux_1level_tapbuf_size2[32]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[32]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[32]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[556] param='mux_1level_tapbuf_size2[32]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[32]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[32]_energy_per_cycle param='mux_1level_tapbuf_size2[32]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[556] param='mux_1level_tapbuf_size2[32]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[556] param='dynamic_power_sb_mux[1][1]_rrnode[556]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[556] avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='start_rise_sb_mux[1][1]_rrnode[556]' to='start_rise_sb_mux[1][1]_rrnode[556]+switch_rise_sb_mux[1][1]_rrnode[556]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[556] avg p(Vgvdd_mux_1level_tapbuf_size2[32]) from='start_fall_sb_mux[1][1]_rrnode[556]' to='start_fall_sb_mux[1][1]_rrnode[556]+switch_fall_sb_mux[1][1]_rrnode[556]' -.meas tran sum_leakage_power_mux[0to32] -+ param='sum_leakage_power_mux[0to31]+leakage_sb_mux[1][1]_rrnode[556]' -.meas tran sum_energy_per_cycle_mux[0to32] -+ param='sum_energy_per_cycle_mux[0to31]+energy_per_cycle_sb_mux[1][1]_rrnode[556]' -***** Load for rr_node[556] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=65, type=5 ***** -Xchan_mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[83]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out mux_1level_tapbuf_size2[32]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[32]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to32] -+ param='sum_leakage_power_sb_mux[0to31]+leakage_sb_mux[1][1]_rrnode[556]' -.meas tran sum_energy_per_cycle_sb_mux[0to32] -+ param='sum_energy_per_cycle_sb_mux[0to31]+energy_per_cycle_sb_mux[1][1]_rrnode[556]' -Xmux_1level_tapbuf_size2[33] mux_1level_tapbuf_size2[33]->in[0] mux_1level_tapbuf_size2[33]->in[1] mux_1level_tapbuf_size2[33]->out sram[43]->outb sram[43]->out gvdd_mux_1level_tapbuf_size2[33] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[33], level=1, select_path_id=0. ***** -*****1***** -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -***** Signal mux_1level_tapbuf_size2[33]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[33]->in[0] mux_1level_tapbuf_size2[33]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[33]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[33]->in[1] mux_1level_tapbuf_size2[33]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[33] gvdd_mux_1level_tapbuf_size2[33] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[558] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[558] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[558] when v(mux_1level_tapbuf_size2[33]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[558] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[558] when v(mux_1level_tapbuf_size2[33]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[558] trig v(mux_1level_tapbuf_size2[33]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[33]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[33]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[558] param='mux_1level_tapbuf_size2[33]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[33]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[33]_energy_per_cycle param='mux_1level_tapbuf_size2[33]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[558] param='mux_1level_tapbuf_size2[33]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[558] param='dynamic_power_sb_mux[1][1]_rrnode[558]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[558] avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='start_rise_sb_mux[1][1]_rrnode[558]' to='start_rise_sb_mux[1][1]_rrnode[558]+switch_rise_sb_mux[1][1]_rrnode[558]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[558] avg p(Vgvdd_mux_1level_tapbuf_size2[33]) from='start_fall_sb_mux[1][1]_rrnode[558]' to='start_fall_sb_mux[1][1]_rrnode[558]+switch_fall_sb_mux[1][1]_rrnode[558]' -.meas tran sum_leakage_power_mux[0to33] -+ param='sum_leakage_power_mux[0to32]+leakage_sb_mux[1][1]_rrnode[558]' -.meas tran sum_energy_per_cycle_mux[0to33] -+ param='sum_energy_per_cycle_mux[0to32]+energy_per_cycle_sb_mux[1][1]_rrnode[558]' -***** Load for rr_node[558] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=67, type=5 ***** -Xchan_mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[86]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out mux_1level_tapbuf_size2[33]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[33]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to33] -+ param='sum_leakage_power_sb_mux[0to32]+leakage_sb_mux[1][1]_rrnode[558]' -.meas tran sum_energy_per_cycle_sb_mux[0to33] -+ param='sum_energy_per_cycle_sb_mux[0to32]+energy_per_cycle_sb_mux[1][1]_rrnode[558]' -Xmux_1level_tapbuf_size2[34] mux_1level_tapbuf_size2[34]->in[0] mux_1level_tapbuf_size2[34]->in[1] mux_1level_tapbuf_size2[34]->out sram[44]->outb sram[44]->out gvdd_mux_1level_tapbuf_size2[34] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[34], level=1, select_path_id=0. ***** -*****1***** -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -***** Signal mux_1level_tapbuf_size2[34]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[34]->in[0] mux_1level_tapbuf_size2[34]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[34]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[34]->in[1] mux_1level_tapbuf_size2[34]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[34] gvdd_mux_1level_tapbuf_size2[34] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[560] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[560] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[560] when v(mux_1level_tapbuf_size2[34]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[560] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[560] when v(mux_1level_tapbuf_size2[34]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[560] trig v(mux_1level_tapbuf_size2[34]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[34]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[34]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[560] param='mux_1level_tapbuf_size2[34]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[34]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[34]_energy_per_cycle param='mux_1level_tapbuf_size2[34]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[560] param='mux_1level_tapbuf_size2[34]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[560] param='dynamic_power_sb_mux[1][1]_rrnode[560]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[560] avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='start_rise_sb_mux[1][1]_rrnode[560]' to='start_rise_sb_mux[1][1]_rrnode[560]+switch_rise_sb_mux[1][1]_rrnode[560]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[560] avg p(Vgvdd_mux_1level_tapbuf_size2[34]) from='start_fall_sb_mux[1][1]_rrnode[560]' to='start_fall_sb_mux[1][1]_rrnode[560]+switch_fall_sb_mux[1][1]_rrnode[560]' -.meas tran sum_leakage_power_mux[0to34] -+ param='sum_leakage_power_mux[0to33]+leakage_sb_mux[1][1]_rrnode[560]' -.meas tran sum_energy_per_cycle_mux[0to34] -+ param='sum_energy_per_cycle_mux[0to33]+energy_per_cycle_sb_mux[1][1]_rrnode[560]' -***** Load for rr_node[560] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=69, type=5 ***** -Xchan_mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[89]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out mux_1level_tapbuf_size2[34]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[34]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to34] -+ param='sum_leakage_power_sb_mux[0to33]+leakage_sb_mux[1][1]_rrnode[560]' -.meas tran sum_energy_per_cycle_sb_mux[0to34] -+ param='sum_energy_per_cycle_sb_mux[0to33]+energy_per_cycle_sb_mux[1][1]_rrnode[560]' -Xmux_1level_tapbuf_size2[35] mux_1level_tapbuf_size2[35]->in[0] mux_1level_tapbuf_size2[35]->in[1] mux_1level_tapbuf_size2[35]->out sram[45]->outb sram[45]->out gvdd_mux_1level_tapbuf_size2[35] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[35], level=1, select_path_id=0. ***** -*****1***** -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -***** Signal mux_1level_tapbuf_size2[35]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[35]->in[0] mux_1level_tapbuf_size2[35]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[35]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[35]->in[1] mux_1level_tapbuf_size2[35]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[35] gvdd_mux_1level_tapbuf_size2[35] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[562] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[562] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[562] when v(mux_1level_tapbuf_size2[35]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[562] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[562] when v(mux_1level_tapbuf_size2[35]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[562] trig v(mux_1level_tapbuf_size2[35]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[35]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[35]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[562] param='mux_1level_tapbuf_size2[35]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[35]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[35]_energy_per_cycle param='mux_1level_tapbuf_size2[35]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[562] param='mux_1level_tapbuf_size2[35]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[562] param='dynamic_power_sb_mux[1][1]_rrnode[562]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[562] avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='start_rise_sb_mux[1][1]_rrnode[562]' to='start_rise_sb_mux[1][1]_rrnode[562]+switch_rise_sb_mux[1][1]_rrnode[562]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[562] avg p(Vgvdd_mux_1level_tapbuf_size2[35]) from='start_fall_sb_mux[1][1]_rrnode[562]' to='start_fall_sb_mux[1][1]_rrnode[562]+switch_fall_sb_mux[1][1]_rrnode[562]' -.meas tran sum_leakage_power_mux[0to35] -+ param='sum_leakage_power_mux[0to34]+leakage_sb_mux[1][1]_rrnode[562]' -.meas tran sum_energy_per_cycle_mux[0to35] -+ param='sum_energy_per_cycle_mux[0to34]+energy_per_cycle_sb_mux[1][1]_rrnode[562]' -***** Load for rr_node[562] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=71, type=5 ***** -Xchan_mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[91]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out mux_1level_tapbuf_size2[35]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[35]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to35] -+ param='sum_leakage_power_sb_mux[0to34]+leakage_sb_mux[1][1]_rrnode[562]' -.meas tran sum_energy_per_cycle_sb_mux[0to35] -+ param='sum_energy_per_cycle_sb_mux[0to34]+energy_per_cycle_sb_mux[1][1]_rrnode[562]' -Xmux_1level_tapbuf_size2[36] mux_1level_tapbuf_size2[36]->in[0] mux_1level_tapbuf_size2[36]->in[1] mux_1level_tapbuf_size2[36]->out sram[46]->outb sram[46]->out gvdd_mux_1level_tapbuf_size2[36] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[36], level=1, select_path_id=0. ***** -*****1***** -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -***** Signal mux_1level_tapbuf_size2[36]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[36]->in[0] mux_1level_tapbuf_size2[36]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[36]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[36]->in[1] mux_1level_tapbuf_size2[36]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[36] gvdd_mux_1level_tapbuf_size2[36] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[564] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[564] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[564] when v(mux_1level_tapbuf_size2[36]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[564] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[564] when v(mux_1level_tapbuf_size2[36]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[564] trig v(mux_1level_tapbuf_size2[36]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[36]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[36]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[564] param='mux_1level_tapbuf_size2[36]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[36]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[36]_energy_per_cycle param='mux_1level_tapbuf_size2[36]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[564] param='mux_1level_tapbuf_size2[36]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[564] param='dynamic_power_sb_mux[1][1]_rrnode[564]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[564] avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='start_rise_sb_mux[1][1]_rrnode[564]' to='start_rise_sb_mux[1][1]_rrnode[564]+switch_rise_sb_mux[1][1]_rrnode[564]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[564] avg p(Vgvdd_mux_1level_tapbuf_size2[36]) from='start_fall_sb_mux[1][1]_rrnode[564]' to='start_fall_sb_mux[1][1]_rrnode[564]+switch_fall_sb_mux[1][1]_rrnode[564]' -.meas tran sum_leakage_power_mux[0to36] -+ param='sum_leakage_power_mux[0to35]+leakage_sb_mux[1][1]_rrnode[564]' -.meas tran sum_energy_per_cycle_mux[0to36] -+ param='sum_energy_per_cycle_mux[0to35]+energy_per_cycle_sb_mux[1][1]_rrnode[564]' -***** Load for rr_node[564] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=73, type=5 ***** -Xchan_mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[94]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out mux_1level_tapbuf_size2[36]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[36]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to36] -+ param='sum_leakage_power_sb_mux[0to35]+leakage_sb_mux[1][1]_rrnode[564]' -.meas tran sum_energy_per_cycle_sb_mux[0to36] -+ param='sum_energy_per_cycle_sb_mux[0to35]+energy_per_cycle_sb_mux[1][1]_rrnode[564]' -Xmux_1level_tapbuf_size2[37] mux_1level_tapbuf_size2[37]->in[0] mux_1level_tapbuf_size2[37]->in[1] mux_1level_tapbuf_size2[37]->out sram[47]->outb sram[47]->out gvdd_mux_1level_tapbuf_size2[37] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[37], level=1, select_path_id=0. ***** -*****1***** -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -***** Signal mux_1level_tapbuf_size2[37]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[37]->in[0] mux_1level_tapbuf_size2[37]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[37]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[37]->in[1] mux_1level_tapbuf_size2[37]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[37] gvdd_mux_1level_tapbuf_size2[37] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[566] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[566] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[566] when v(mux_1level_tapbuf_size2[37]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[566] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[566] when v(mux_1level_tapbuf_size2[37]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[566] trig v(mux_1level_tapbuf_size2[37]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[37]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[37]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[566] param='mux_1level_tapbuf_size2[37]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[37]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[37]_energy_per_cycle param='mux_1level_tapbuf_size2[37]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[566] param='mux_1level_tapbuf_size2[37]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[566] param='dynamic_power_sb_mux[1][1]_rrnode[566]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[566] avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='start_rise_sb_mux[1][1]_rrnode[566]' to='start_rise_sb_mux[1][1]_rrnode[566]+switch_rise_sb_mux[1][1]_rrnode[566]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[566] avg p(Vgvdd_mux_1level_tapbuf_size2[37]) from='start_fall_sb_mux[1][1]_rrnode[566]' to='start_fall_sb_mux[1][1]_rrnode[566]+switch_fall_sb_mux[1][1]_rrnode[566]' -.meas tran sum_leakage_power_mux[0to37] -+ param='sum_leakage_power_mux[0to36]+leakage_sb_mux[1][1]_rrnode[566]' -.meas tran sum_energy_per_cycle_mux[0to37] -+ param='sum_energy_per_cycle_mux[0to36]+energy_per_cycle_sb_mux[1][1]_rrnode[566]' -***** Load for rr_node[566] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=75, type=5 ***** -Xchan_mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[96]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out mux_1level_tapbuf_size2[37]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[37]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to37] -+ param='sum_leakage_power_sb_mux[0to36]+leakage_sb_mux[1][1]_rrnode[566]' -.meas tran sum_energy_per_cycle_sb_mux[0to37] -+ param='sum_energy_per_cycle_sb_mux[0to36]+energy_per_cycle_sb_mux[1][1]_rrnode[566]' -Xmux_1level_tapbuf_size2[38] mux_1level_tapbuf_size2[38]->in[0] mux_1level_tapbuf_size2[38]->in[1] mux_1level_tapbuf_size2[38]->out sram[48]->outb sram[48]->out gvdd_mux_1level_tapbuf_size2[38] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[38], level=1, select_path_id=0. ***** -*****1***** -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -***** Signal mux_1level_tapbuf_size2[38]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[38]->in[0] mux_1level_tapbuf_size2[38]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[38]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[38]->in[1] mux_1level_tapbuf_size2[38]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[38] gvdd_mux_1level_tapbuf_size2[38] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[568] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[568] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[568] when v(mux_1level_tapbuf_size2[38]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[568] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[568] when v(mux_1level_tapbuf_size2[38]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[568] trig v(mux_1level_tapbuf_size2[38]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[38]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[38]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[568] param='mux_1level_tapbuf_size2[38]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[38]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[38]_energy_per_cycle param='mux_1level_tapbuf_size2[38]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[568] param='mux_1level_tapbuf_size2[38]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[568] param='dynamic_power_sb_mux[1][1]_rrnode[568]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[568] avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='start_rise_sb_mux[1][1]_rrnode[568]' to='start_rise_sb_mux[1][1]_rrnode[568]+switch_rise_sb_mux[1][1]_rrnode[568]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[568] avg p(Vgvdd_mux_1level_tapbuf_size2[38]) from='start_fall_sb_mux[1][1]_rrnode[568]' to='start_fall_sb_mux[1][1]_rrnode[568]+switch_fall_sb_mux[1][1]_rrnode[568]' -.meas tran sum_leakage_power_mux[0to38] -+ param='sum_leakage_power_mux[0to37]+leakage_sb_mux[1][1]_rrnode[568]' -.meas tran sum_energy_per_cycle_mux[0to38] -+ param='sum_energy_per_cycle_mux[0to37]+energy_per_cycle_sb_mux[1][1]_rrnode[568]' -***** Load for rr_node[568] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=77, type=5 ***** -Xchan_mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[99]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out mux_1level_tapbuf_size2[38]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[38]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to38] -+ param='sum_leakage_power_sb_mux[0to37]+leakage_sb_mux[1][1]_rrnode[568]' -.meas tran sum_energy_per_cycle_sb_mux[0to38] -+ param='sum_energy_per_cycle_sb_mux[0to37]+energy_per_cycle_sb_mux[1][1]_rrnode[568]' -Xmux_1level_tapbuf_size2[39] mux_1level_tapbuf_size2[39]->in[0] mux_1level_tapbuf_size2[39]->in[1] mux_1level_tapbuf_size2[39]->out sram[49]->outb sram[49]->out gvdd_mux_1level_tapbuf_size2[39] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[39], level=1, select_path_id=0. ***** -*****1***** -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -***** Signal mux_1level_tapbuf_size2[39]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[39]->in[0] mux_1level_tapbuf_size2[39]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[39]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[39]->in[1] mux_1level_tapbuf_size2[39]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[39] gvdd_mux_1level_tapbuf_size2[39] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[570] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[570] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[570] when v(mux_1level_tapbuf_size2[39]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[570] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[570] when v(mux_1level_tapbuf_size2[39]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[570] trig v(mux_1level_tapbuf_size2[39]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[39]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[39]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[570] param='mux_1level_tapbuf_size2[39]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[39]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[39]_energy_per_cycle param='mux_1level_tapbuf_size2[39]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[570] param='mux_1level_tapbuf_size2[39]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[570] param='dynamic_power_sb_mux[1][1]_rrnode[570]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[570] avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='start_rise_sb_mux[1][1]_rrnode[570]' to='start_rise_sb_mux[1][1]_rrnode[570]+switch_rise_sb_mux[1][1]_rrnode[570]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[570] avg p(Vgvdd_mux_1level_tapbuf_size2[39]) from='start_fall_sb_mux[1][1]_rrnode[570]' to='start_fall_sb_mux[1][1]_rrnode[570]+switch_fall_sb_mux[1][1]_rrnode[570]' -.meas tran sum_leakage_power_mux[0to39] -+ param='sum_leakage_power_mux[0to38]+leakage_sb_mux[1][1]_rrnode[570]' -.meas tran sum_energy_per_cycle_mux[0to39] -+ param='sum_energy_per_cycle_mux[0to38]+energy_per_cycle_sb_mux[1][1]_rrnode[570]' -***** Load for rr_node[570] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=79, type=5 ***** -Xchan_mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[102]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out mux_1level_tapbuf_size2[39]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[39]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to39] -+ param='sum_leakage_power_sb_mux[0to38]+leakage_sb_mux[1][1]_rrnode[570]' -.meas tran sum_energy_per_cycle_sb_mux[0to39] -+ param='sum_energy_per_cycle_sb_mux[0to38]+energy_per_cycle_sb_mux[1][1]_rrnode[570]' -Xmux_1level_tapbuf_size2[40] mux_1level_tapbuf_size2[40]->in[0] mux_1level_tapbuf_size2[40]->in[1] mux_1level_tapbuf_size2[40]->out sram[50]->outb sram[50]->out gvdd_mux_1level_tapbuf_size2[40] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[40], level=1, select_path_id=0. ***** -*****1***** -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -***** Signal mux_1level_tapbuf_size2[40]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[40]->in[0] mux_1level_tapbuf_size2[40]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[40]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[40]->in[1] mux_1level_tapbuf_size2[40]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[40] gvdd_mux_1level_tapbuf_size2[40] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[572] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[572] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[572] when v(mux_1level_tapbuf_size2[40]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[572] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[572] when v(mux_1level_tapbuf_size2[40]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[572] trig v(mux_1level_tapbuf_size2[40]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[40]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[40]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[572] param='mux_1level_tapbuf_size2[40]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[40]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[40]_energy_per_cycle param='mux_1level_tapbuf_size2[40]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[572] param='mux_1level_tapbuf_size2[40]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[572] param='dynamic_power_sb_mux[1][1]_rrnode[572]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[572] avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='start_rise_sb_mux[1][1]_rrnode[572]' to='start_rise_sb_mux[1][1]_rrnode[572]+switch_rise_sb_mux[1][1]_rrnode[572]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[572] avg p(Vgvdd_mux_1level_tapbuf_size2[40]) from='start_fall_sb_mux[1][1]_rrnode[572]' to='start_fall_sb_mux[1][1]_rrnode[572]+switch_fall_sb_mux[1][1]_rrnode[572]' -.meas tran sum_leakage_power_mux[0to40] -+ param='sum_leakage_power_mux[0to39]+leakage_sb_mux[1][1]_rrnode[572]' -.meas tran sum_energy_per_cycle_mux[0to40] -+ param='sum_energy_per_cycle_mux[0to39]+energy_per_cycle_sb_mux[1][1]_rrnode[572]' -***** Load for rr_node[572] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=81, type=5 ***** -Xchan_mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[104]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out mux_1level_tapbuf_size2[40]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[40]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to40] -+ param='sum_leakage_power_sb_mux[0to39]+leakage_sb_mux[1][1]_rrnode[572]' -.meas tran sum_energy_per_cycle_sb_mux[0to40] -+ param='sum_energy_per_cycle_sb_mux[0to39]+energy_per_cycle_sb_mux[1][1]_rrnode[572]' -Xmux_1level_tapbuf_size2[41] mux_1level_tapbuf_size2[41]->in[0] mux_1level_tapbuf_size2[41]->in[1] mux_1level_tapbuf_size2[41]->out sram[51]->outb sram[51]->out gvdd_mux_1level_tapbuf_size2[41] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[41], level=1, select_path_id=0. ***** -*****1***** -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -***** Signal mux_1level_tapbuf_size2[41]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[41]->in[0] mux_1level_tapbuf_size2[41]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[41]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[41]->in[1] mux_1level_tapbuf_size2[41]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[41] gvdd_mux_1level_tapbuf_size2[41] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[574] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[574] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[574] when v(mux_1level_tapbuf_size2[41]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[574] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[574] when v(mux_1level_tapbuf_size2[41]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[574] trig v(mux_1level_tapbuf_size2[41]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[41]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[41]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[574] param='mux_1level_tapbuf_size2[41]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[41]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[41]_energy_per_cycle param='mux_1level_tapbuf_size2[41]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[574] param='mux_1level_tapbuf_size2[41]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[574] param='dynamic_power_sb_mux[1][1]_rrnode[574]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[574] avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='start_rise_sb_mux[1][1]_rrnode[574]' to='start_rise_sb_mux[1][1]_rrnode[574]+switch_rise_sb_mux[1][1]_rrnode[574]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[574] avg p(Vgvdd_mux_1level_tapbuf_size2[41]) from='start_fall_sb_mux[1][1]_rrnode[574]' to='start_fall_sb_mux[1][1]_rrnode[574]+switch_fall_sb_mux[1][1]_rrnode[574]' -.meas tran sum_leakage_power_mux[0to41] -+ param='sum_leakage_power_mux[0to40]+leakage_sb_mux[1][1]_rrnode[574]' -.meas tran sum_energy_per_cycle_mux[0to41] -+ param='sum_energy_per_cycle_mux[0to40]+energy_per_cycle_sb_mux[1][1]_rrnode[574]' -***** Load for rr_node[574] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=83, type=5 ***** -Xchan_mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[107]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out mux_1level_tapbuf_size2[41]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[41]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to41] -+ param='sum_leakage_power_sb_mux[0to40]+leakage_sb_mux[1][1]_rrnode[574]' -.meas tran sum_energy_per_cycle_sb_mux[0to41] -+ param='sum_energy_per_cycle_sb_mux[0to40]+energy_per_cycle_sb_mux[1][1]_rrnode[574]' -Xmux_1level_tapbuf_size2[42] mux_1level_tapbuf_size2[42]->in[0] mux_1level_tapbuf_size2[42]->in[1] mux_1level_tapbuf_size2[42]->out sram[52]->outb sram[52]->out gvdd_mux_1level_tapbuf_size2[42] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[42], level=1, select_path_id=0. ***** -*****1***** -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -***** Signal mux_1level_tapbuf_size2[42]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[42]->in[0] mux_1level_tapbuf_size2[42]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[42]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[42]->in[1] mux_1level_tapbuf_size2[42]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[42] gvdd_mux_1level_tapbuf_size2[42] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[576] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[576] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[576] when v(mux_1level_tapbuf_size2[42]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[576] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[576] when v(mux_1level_tapbuf_size2[42]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[576] trig v(mux_1level_tapbuf_size2[42]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[42]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[42]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[576] param='mux_1level_tapbuf_size2[42]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[42]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[42]_energy_per_cycle param='mux_1level_tapbuf_size2[42]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[576] param='mux_1level_tapbuf_size2[42]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[576] param='dynamic_power_sb_mux[1][1]_rrnode[576]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[576] avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='start_rise_sb_mux[1][1]_rrnode[576]' to='start_rise_sb_mux[1][1]_rrnode[576]+switch_rise_sb_mux[1][1]_rrnode[576]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[576] avg p(Vgvdd_mux_1level_tapbuf_size2[42]) from='start_fall_sb_mux[1][1]_rrnode[576]' to='start_fall_sb_mux[1][1]_rrnode[576]+switch_fall_sb_mux[1][1]_rrnode[576]' -.meas tran sum_leakage_power_mux[0to42] -+ param='sum_leakage_power_mux[0to41]+leakage_sb_mux[1][1]_rrnode[576]' -.meas tran sum_energy_per_cycle_mux[0to42] -+ param='sum_energy_per_cycle_mux[0to41]+energy_per_cycle_sb_mux[1][1]_rrnode[576]' -***** Load for rr_node[576] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=85, type=5 ***** -Xchan_mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[109]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out mux_1level_tapbuf_size2[42]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[42]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to42] -+ param='sum_leakage_power_sb_mux[0to41]+leakage_sb_mux[1][1]_rrnode[576]' -.meas tran sum_energy_per_cycle_sb_mux[0to42] -+ param='sum_energy_per_cycle_sb_mux[0to41]+energy_per_cycle_sb_mux[1][1]_rrnode[576]' -Xmux_1level_tapbuf_size2[43] mux_1level_tapbuf_size2[43]->in[0] mux_1level_tapbuf_size2[43]->in[1] mux_1level_tapbuf_size2[43]->out sram[53]->outb sram[53]->out gvdd_mux_1level_tapbuf_size2[43] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[43], level=1, select_path_id=0. ***** -*****1***** -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -***** Signal mux_1level_tapbuf_size2[43]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[43]->in[0] mux_1level_tapbuf_size2[43]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[43]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[43]->in[1] mux_1level_tapbuf_size2[43]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[43] gvdd_mux_1level_tapbuf_size2[43] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[578] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[578] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[578] when v(mux_1level_tapbuf_size2[43]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[578] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[578] when v(mux_1level_tapbuf_size2[43]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[578] trig v(mux_1level_tapbuf_size2[43]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[43]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[43]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[578] param='mux_1level_tapbuf_size2[43]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[43]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[43]_energy_per_cycle param='mux_1level_tapbuf_size2[43]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[578] param='mux_1level_tapbuf_size2[43]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[578] param='dynamic_power_sb_mux[1][1]_rrnode[578]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[578] avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='start_rise_sb_mux[1][1]_rrnode[578]' to='start_rise_sb_mux[1][1]_rrnode[578]+switch_rise_sb_mux[1][1]_rrnode[578]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[578] avg p(Vgvdd_mux_1level_tapbuf_size2[43]) from='start_fall_sb_mux[1][1]_rrnode[578]' to='start_fall_sb_mux[1][1]_rrnode[578]+switch_fall_sb_mux[1][1]_rrnode[578]' -.meas tran sum_leakage_power_mux[0to43] -+ param='sum_leakage_power_mux[0to42]+leakage_sb_mux[1][1]_rrnode[578]' -.meas tran sum_energy_per_cycle_mux[0to43] -+ param='sum_energy_per_cycle_mux[0to42]+energy_per_cycle_sb_mux[1][1]_rrnode[578]' -***** Load for rr_node[578] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=87, type=5 ***** -Xchan_mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[112]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out mux_1level_tapbuf_size2[43]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[43]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to43] -+ param='sum_leakage_power_sb_mux[0to42]+leakage_sb_mux[1][1]_rrnode[578]' -.meas tran sum_energy_per_cycle_sb_mux[0to43] -+ param='sum_energy_per_cycle_sb_mux[0to42]+energy_per_cycle_sb_mux[1][1]_rrnode[578]' -Xmux_1level_tapbuf_size2[44] mux_1level_tapbuf_size2[44]->in[0] mux_1level_tapbuf_size2[44]->in[1] mux_1level_tapbuf_size2[44]->out sram[54]->outb sram[54]->out gvdd_mux_1level_tapbuf_size2[44] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[44], level=1, select_path_id=0. ***** -*****1***** -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -***** Signal mux_1level_tapbuf_size2[44]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[44]->in[0] mux_1level_tapbuf_size2[44]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[44]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[44]->in[1] mux_1level_tapbuf_size2[44]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[44] gvdd_mux_1level_tapbuf_size2[44] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[580] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[580] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[580] when v(mux_1level_tapbuf_size2[44]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[580] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[580] when v(mux_1level_tapbuf_size2[44]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[580] trig v(mux_1level_tapbuf_size2[44]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[44]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[44]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[580] param='mux_1level_tapbuf_size2[44]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[44]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[44]_energy_per_cycle param='mux_1level_tapbuf_size2[44]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[580] param='mux_1level_tapbuf_size2[44]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[580] param='dynamic_power_sb_mux[1][1]_rrnode[580]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[580] avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='start_rise_sb_mux[1][1]_rrnode[580]' to='start_rise_sb_mux[1][1]_rrnode[580]+switch_rise_sb_mux[1][1]_rrnode[580]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[580] avg p(Vgvdd_mux_1level_tapbuf_size2[44]) from='start_fall_sb_mux[1][1]_rrnode[580]' to='start_fall_sb_mux[1][1]_rrnode[580]+switch_fall_sb_mux[1][1]_rrnode[580]' -.meas tran sum_leakage_power_mux[0to44] -+ param='sum_leakage_power_mux[0to43]+leakage_sb_mux[1][1]_rrnode[580]' -.meas tran sum_energy_per_cycle_mux[0to44] -+ param='sum_energy_per_cycle_mux[0to43]+energy_per_cycle_sb_mux[1][1]_rrnode[580]' -***** Load for rr_node[580] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=89, type=5 ***** -Xchan_mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[115]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out mux_1level_tapbuf_size2[44]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[44]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to44] -+ param='sum_leakage_power_sb_mux[0to43]+leakage_sb_mux[1][1]_rrnode[580]' -.meas tran sum_energy_per_cycle_sb_mux[0to44] -+ param='sum_energy_per_cycle_sb_mux[0to43]+energy_per_cycle_sb_mux[1][1]_rrnode[580]' -Xmux_1level_tapbuf_size2[45] mux_1level_tapbuf_size2[45]->in[0] mux_1level_tapbuf_size2[45]->in[1] mux_1level_tapbuf_size2[45]->out sram[55]->outb sram[55]->out gvdd_mux_1level_tapbuf_size2[45] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[45], level=1, select_path_id=0. ***** -*****1***** -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -***** Signal mux_1level_tapbuf_size2[45]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[45]->in[0] mux_1level_tapbuf_size2[45]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[45]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[45]->in[1] mux_1level_tapbuf_size2[45]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[45] gvdd_mux_1level_tapbuf_size2[45] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[582] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[582] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[582] when v(mux_1level_tapbuf_size2[45]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[582] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[582] when v(mux_1level_tapbuf_size2[45]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[582] trig v(mux_1level_tapbuf_size2[45]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[45]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[45]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[582] param='mux_1level_tapbuf_size2[45]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[45]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[45]_energy_per_cycle param='mux_1level_tapbuf_size2[45]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[582] param='mux_1level_tapbuf_size2[45]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[582] param='dynamic_power_sb_mux[1][1]_rrnode[582]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[582] avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='start_rise_sb_mux[1][1]_rrnode[582]' to='start_rise_sb_mux[1][1]_rrnode[582]+switch_rise_sb_mux[1][1]_rrnode[582]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[582] avg p(Vgvdd_mux_1level_tapbuf_size2[45]) from='start_fall_sb_mux[1][1]_rrnode[582]' to='start_fall_sb_mux[1][1]_rrnode[582]+switch_fall_sb_mux[1][1]_rrnode[582]' -.meas tran sum_leakage_power_mux[0to45] -+ param='sum_leakage_power_mux[0to44]+leakage_sb_mux[1][1]_rrnode[582]' -.meas tran sum_energy_per_cycle_mux[0to45] -+ param='sum_energy_per_cycle_mux[0to44]+energy_per_cycle_sb_mux[1][1]_rrnode[582]' -***** Load for rr_node[582] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=91, type=5 ***** -Xchan_mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[117]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out mux_1level_tapbuf_size2[45]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[45]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to45] -+ param='sum_leakage_power_sb_mux[0to44]+leakage_sb_mux[1][1]_rrnode[582]' -.meas tran sum_energy_per_cycle_sb_mux[0to45] -+ param='sum_energy_per_cycle_sb_mux[0to44]+energy_per_cycle_sb_mux[1][1]_rrnode[582]' -Xmux_1level_tapbuf_size2[46] mux_1level_tapbuf_size2[46]->in[0] mux_1level_tapbuf_size2[46]->in[1] mux_1level_tapbuf_size2[46]->out sram[56]->outb sram[56]->out gvdd_mux_1level_tapbuf_size2[46] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[46], level=1, select_path_id=0. ***** -*****1***** -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -***** Signal mux_1level_tapbuf_size2[46]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[46]->in[0] mux_1level_tapbuf_size2[46]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[46]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[46]->in[1] mux_1level_tapbuf_size2[46]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[46] gvdd_mux_1level_tapbuf_size2[46] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[584] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[584] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[584] when v(mux_1level_tapbuf_size2[46]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[584] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[584] when v(mux_1level_tapbuf_size2[46]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[584] trig v(mux_1level_tapbuf_size2[46]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[46]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[46]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[584] param='mux_1level_tapbuf_size2[46]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[46]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[46]_energy_per_cycle param='mux_1level_tapbuf_size2[46]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[584] param='mux_1level_tapbuf_size2[46]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[584] param='dynamic_power_sb_mux[1][1]_rrnode[584]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[584] avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='start_rise_sb_mux[1][1]_rrnode[584]' to='start_rise_sb_mux[1][1]_rrnode[584]+switch_rise_sb_mux[1][1]_rrnode[584]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[584] avg p(Vgvdd_mux_1level_tapbuf_size2[46]) from='start_fall_sb_mux[1][1]_rrnode[584]' to='start_fall_sb_mux[1][1]_rrnode[584]+switch_fall_sb_mux[1][1]_rrnode[584]' -.meas tran sum_leakage_power_mux[0to46] -+ param='sum_leakage_power_mux[0to45]+leakage_sb_mux[1][1]_rrnode[584]' -.meas tran sum_energy_per_cycle_mux[0to46] -+ param='sum_energy_per_cycle_mux[0to45]+energy_per_cycle_sb_mux[1][1]_rrnode[584]' -***** Load for rr_node[584] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=93, type=5 ***** -Xchan_mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[120]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out mux_1level_tapbuf_size2[46]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[46]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to46] -+ param='sum_leakage_power_sb_mux[0to45]+leakage_sb_mux[1][1]_rrnode[584]' -.meas tran sum_energy_per_cycle_sb_mux[0to46] -+ param='sum_energy_per_cycle_sb_mux[0to45]+energy_per_cycle_sb_mux[1][1]_rrnode[584]' -Xmux_1level_tapbuf_size2[47] mux_1level_tapbuf_size2[47]->in[0] mux_1level_tapbuf_size2[47]->in[1] mux_1level_tapbuf_size2[47]->out sram[57]->outb sram[57]->out gvdd_mux_1level_tapbuf_size2[47] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[47], level=1, select_path_id=0. ***** -*****1***** -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -***** Signal mux_1level_tapbuf_size2[47]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[47]->in[0] mux_1level_tapbuf_size2[47]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[47]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[47]->in[1] mux_1level_tapbuf_size2[47]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[47] gvdd_mux_1level_tapbuf_size2[47] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[586] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[586] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[586] when v(mux_1level_tapbuf_size2[47]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[586] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[586] when v(mux_1level_tapbuf_size2[47]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[586] trig v(mux_1level_tapbuf_size2[47]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[47]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[47]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[586] param='mux_1level_tapbuf_size2[47]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[47]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[47]_energy_per_cycle param='mux_1level_tapbuf_size2[47]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[586] param='mux_1level_tapbuf_size2[47]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[586] param='dynamic_power_sb_mux[1][1]_rrnode[586]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[586] avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='start_rise_sb_mux[1][1]_rrnode[586]' to='start_rise_sb_mux[1][1]_rrnode[586]+switch_rise_sb_mux[1][1]_rrnode[586]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[586] avg p(Vgvdd_mux_1level_tapbuf_size2[47]) from='start_fall_sb_mux[1][1]_rrnode[586]' to='start_fall_sb_mux[1][1]_rrnode[586]+switch_fall_sb_mux[1][1]_rrnode[586]' -.meas tran sum_leakage_power_mux[0to47] -+ param='sum_leakage_power_mux[0to46]+leakage_sb_mux[1][1]_rrnode[586]' -.meas tran sum_energy_per_cycle_mux[0to47] -+ param='sum_energy_per_cycle_mux[0to46]+energy_per_cycle_sb_mux[1][1]_rrnode[586]' -***** Load for rr_node[586] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=95, type=5 ***** -Xchan_mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[122]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out mux_1level_tapbuf_size2[47]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[47]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to47] -+ param='sum_leakage_power_sb_mux[0to46]+leakage_sb_mux[1][1]_rrnode[586]' -.meas tran sum_energy_per_cycle_sb_mux[0to47] -+ param='sum_energy_per_cycle_sb_mux[0to46]+energy_per_cycle_sb_mux[1][1]_rrnode[586]' -Xmux_1level_tapbuf_size2[48] mux_1level_tapbuf_size2[48]->in[0] mux_1level_tapbuf_size2[48]->in[1] mux_1level_tapbuf_size2[48]->out sram[58]->outb sram[58]->out gvdd_mux_1level_tapbuf_size2[48] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[48], level=1, select_path_id=0. ***** -*****1***** -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -***** Signal mux_1level_tapbuf_size2[48]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[48]->in[0] mux_1level_tapbuf_size2[48]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[48]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[48]->in[1] mux_1level_tapbuf_size2[48]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[48] gvdd_mux_1level_tapbuf_size2[48] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[588] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[588] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[588] when v(mux_1level_tapbuf_size2[48]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[588] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[588] when v(mux_1level_tapbuf_size2[48]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[588] trig v(mux_1level_tapbuf_size2[48]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[48]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[48]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[588] param='mux_1level_tapbuf_size2[48]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[48]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[48]_energy_per_cycle param='mux_1level_tapbuf_size2[48]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[588] param='mux_1level_tapbuf_size2[48]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[588] param='dynamic_power_sb_mux[1][1]_rrnode[588]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[588] avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='start_rise_sb_mux[1][1]_rrnode[588]' to='start_rise_sb_mux[1][1]_rrnode[588]+switch_rise_sb_mux[1][1]_rrnode[588]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[588] avg p(Vgvdd_mux_1level_tapbuf_size2[48]) from='start_fall_sb_mux[1][1]_rrnode[588]' to='start_fall_sb_mux[1][1]_rrnode[588]+switch_fall_sb_mux[1][1]_rrnode[588]' -.meas tran sum_leakage_power_mux[0to48] -+ param='sum_leakage_power_mux[0to47]+leakage_sb_mux[1][1]_rrnode[588]' -.meas tran sum_energy_per_cycle_mux[0to48] -+ param='sum_energy_per_cycle_mux[0to47]+energy_per_cycle_sb_mux[1][1]_rrnode[588]' -***** Load for rr_node[588] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=97, type=5 ***** -Xchan_mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[125]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out mux_1level_tapbuf_size2[48]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[48]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to48] -+ param='sum_leakage_power_sb_mux[0to47]+leakage_sb_mux[1][1]_rrnode[588]' -.meas tran sum_energy_per_cycle_sb_mux[0to48] -+ param='sum_energy_per_cycle_sb_mux[0to47]+energy_per_cycle_sb_mux[1][1]_rrnode[588]' -Xmux_1level_tapbuf_size2[49] mux_1level_tapbuf_size2[49]->in[0] mux_1level_tapbuf_size2[49]->in[1] mux_1level_tapbuf_size2[49]->out sram[59]->outb sram[59]->out gvdd_mux_1level_tapbuf_size2[49] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[49], level=1, select_path_id=0. ***** -*****1***** -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -***** Signal mux_1level_tapbuf_size2[49]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[49]->in[0] mux_1level_tapbuf_size2[49]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[49]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[49]->in[1] mux_1level_tapbuf_size2[49]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[49] gvdd_mux_1level_tapbuf_size2[49] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[590] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[590] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[590] when v(mux_1level_tapbuf_size2[49]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[590] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[590] when v(mux_1level_tapbuf_size2[49]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[590] trig v(mux_1level_tapbuf_size2[49]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[49]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[49]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[590] param='mux_1level_tapbuf_size2[49]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[49]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[49]_energy_per_cycle param='mux_1level_tapbuf_size2[49]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[590] param='mux_1level_tapbuf_size2[49]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[590] param='dynamic_power_sb_mux[1][1]_rrnode[590]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[590] avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='start_rise_sb_mux[1][1]_rrnode[590]' to='start_rise_sb_mux[1][1]_rrnode[590]+switch_rise_sb_mux[1][1]_rrnode[590]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[590] avg p(Vgvdd_mux_1level_tapbuf_size2[49]) from='start_fall_sb_mux[1][1]_rrnode[590]' to='start_fall_sb_mux[1][1]_rrnode[590]+switch_fall_sb_mux[1][1]_rrnode[590]' -.meas tran sum_leakage_power_mux[0to49] -+ param='sum_leakage_power_mux[0to48]+leakage_sb_mux[1][1]_rrnode[590]' -.meas tran sum_energy_per_cycle_mux[0to49] -+ param='sum_energy_per_cycle_mux[0to48]+energy_per_cycle_sb_mux[1][1]_rrnode[590]' -***** Load for rr_node[590] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=99, type=5 ***** -Xchan_mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[128]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out mux_1level_tapbuf_size2[49]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[49]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to49] -+ param='sum_leakage_power_sb_mux[0to48]+leakage_sb_mux[1][1]_rrnode[590]' -.meas tran sum_energy_per_cycle_sb_mux[0to49] -+ param='sum_energy_per_cycle_sb_mux[0to48]+energy_per_cycle_sb_mux[1][1]_rrnode[590]' -Xmux_1level_tapbuf_size3[50] mux_1level_tapbuf_size3[50]->in[0] mux_1level_tapbuf_size3[50]->in[1] mux_1level_tapbuf_size3[50]->in[2] mux_1level_tapbuf_size3[50]->out sram[60]->outb sram[60]->out sram[61]->out sram[61]->outb sram[62]->out sram[62]->outb gvdd_mux_1level_tapbuf_size3[50] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[50], level=1, select_path_id=0. ***** -*****100***** -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -***** Signal mux_1level_tapbuf_size3[50]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[50]->in[0] mux_1level_tapbuf_size3[50]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[50]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[50]->in[1] mux_1level_tapbuf_size3[50]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[50]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[50]->in[2] mux_1level_tapbuf_size3[50]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[50] gvdd_mux_1level_tapbuf_size3[50] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[292] trig v(mux_1level_tapbuf_size3[50]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[50]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[292] trig v(mux_1level_tapbuf_size3[50]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[50]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[292] when v(mux_1level_tapbuf_size3[50]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[292] trig v(mux_1level_tapbuf_size3[50]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[50]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[292] when v(mux_1level_tapbuf_size3[50]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[292] trig v(mux_1level_tapbuf_size3[50]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[50]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[50]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[50]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[292] param='mux_1level_tapbuf_size3[50]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[50]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[50]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[50]_energy_per_cycle param='mux_1level_tapbuf_size3[50]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[292] param='mux_1level_tapbuf_size3[50]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[292] param='dynamic_power_sb_mux[1][1]_rrnode[292]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[292] avg p(Vgvdd_mux_1level_tapbuf_size3[50]) from='start_rise_sb_mux[1][1]_rrnode[292]' to='start_rise_sb_mux[1][1]_rrnode[292]+switch_rise_sb_mux[1][1]_rrnode[292]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[292] avg p(Vgvdd_mux_1level_tapbuf_size3[50]) from='start_fall_sb_mux[1][1]_rrnode[292]' to='start_fall_sb_mux[1][1]_rrnode[292]+switch_fall_sb_mux[1][1]_rrnode[292]' -.meas tran sum_leakage_power_mux[0to50] -+ param='sum_leakage_power_mux[0to49]+leakage_sb_mux[1][1]_rrnode[292]' -.meas tran sum_energy_per_cycle_mux[0to50] -+ param='sum_energy_per_cycle_mux[0to49]+energy_per_cycle_sb_mux[1][1]_rrnode[292]' -***** Load for rr_node[292] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=1, type=4 ***** -Xchan_mux_1level_tapbuf_size3[50]->out_loadlvl[0]_out mux_1level_tapbuf_size3[50]->out mux_1level_tapbuf_size3[50]->out_loadlvl[0]_out mux_1level_tapbuf_size3[50]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[130]_no0 mux_1level_tapbuf_size3[50]->out_loadlvl[0]_out mux_1level_tapbuf_size3[50]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 mux_1level_tapbuf_size3[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[50]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 mux_1level_tapbuf_size3[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[50]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 mux_1level_tapbuf_size3[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[50]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 mux_1level_tapbuf_size3[50]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[50]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to50] -+ param='sum_leakage_power_sb_mux[0to49]+leakage_sb_mux[1][1]_rrnode[292]' -.meas tran sum_energy_per_cycle_sb_mux[0to50] -+ param='sum_energy_per_cycle_sb_mux[0to49]+energy_per_cycle_sb_mux[1][1]_rrnode[292]' -Xmux_1level_tapbuf_size3[51] mux_1level_tapbuf_size3[51]->in[0] mux_1level_tapbuf_size3[51]->in[1] mux_1level_tapbuf_size3[51]->in[2] mux_1level_tapbuf_size3[51]->out sram[63]->outb sram[63]->out sram[64]->out sram[64]->outb sram[65]->out sram[65]->outb gvdd_mux_1level_tapbuf_size3[51] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[51], level=1, select_path_id=0. ***** -*****100***** -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -***** Signal mux_1level_tapbuf_size3[51]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[51]->in[0] mux_1level_tapbuf_size3[51]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[51]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[51]->in[1] mux_1level_tapbuf_size3[51]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[51]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[51]->in[2] mux_1level_tapbuf_size3[51]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[51] gvdd_mux_1level_tapbuf_size3[51] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[294] trig v(mux_1level_tapbuf_size3[51]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[51]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[294] trig v(mux_1level_tapbuf_size3[51]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[51]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[294] when v(mux_1level_tapbuf_size3[51]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[294] trig v(mux_1level_tapbuf_size3[51]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[51]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[294] when v(mux_1level_tapbuf_size3[51]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[294] trig v(mux_1level_tapbuf_size3[51]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[51]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[51]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[51]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[294] param='mux_1level_tapbuf_size3[51]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[51]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[51]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[51]_energy_per_cycle param='mux_1level_tapbuf_size3[51]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[294] param='mux_1level_tapbuf_size3[51]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[294] param='dynamic_power_sb_mux[1][1]_rrnode[294]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[294] avg p(Vgvdd_mux_1level_tapbuf_size3[51]) from='start_rise_sb_mux[1][1]_rrnode[294]' to='start_rise_sb_mux[1][1]_rrnode[294]+switch_rise_sb_mux[1][1]_rrnode[294]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[294] avg p(Vgvdd_mux_1level_tapbuf_size3[51]) from='start_fall_sb_mux[1][1]_rrnode[294]' to='start_fall_sb_mux[1][1]_rrnode[294]+switch_fall_sb_mux[1][1]_rrnode[294]' -.meas tran sum_leakage_power_mux[0to51] -+ param='sum_leakage_power_mux[0to50]+leakage_sb_mux[1][1]_rrnode[294]' -.meas tran sum_energy_per_cycle_mux[0to51] -+ param='sum_energy_per_cycle_mux[0to50]+energy_per_cycle_sb_mux[1][1]_rrnode[294]' -***** Load for rr_node[294] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=3, type=4 ***** -Xchan_mux_1level_tapbuf_size3[51]->out_loadlvl[0]_out mux_1level_tapbuf_size3[51]->out mux_1level_tapbuf_size3[51]->out_loadlvl[0]_out mux_1level_tapbuf_size3[51]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[135]_no0 mux_1level_tapbuf_size3[51]->out_loadlvl[0]_out mux_1level_tapbuf_size3[51]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 mux_1level_tapbuf_size3[51]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[51]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 mux_1level_tapbuf_size3[51]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[51]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to51] -+ param='sum_leakage_power_sb_mux[0to50]+leakage_sb_mux[1][1]_rrnode[294]' -.meas tran sum_energy_per_cycle_sb_mux[0to51] -+ param='sum_energy_per_cycle_sb_mux[0to50]+energy_per_cycle_sb_mux[1][1]_rrnode[294]' -Xmux_1level_tapbuf_size3[52] mux_1level_tapbuf_size3[52]->in[0] mux_1level_tapbuf_size3[52]->in[1] mux_1level_tapbuf_size3[52]->in[2] mux_1level_tapbuf_size3[52]->out sram[66]->outb sram[66]->out sram[67]->out sram[67]->outb sram[68]->out sram[68]->outb gvdd_mux_1level_tapbuf_size3[52] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[52], level=1, select_path_id=0. ***** -*****100***** -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -***** Signal mux_1level_tapbuf_size3[52]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[52]->in[0] mux_1level_tapbuf_size3[52]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[52]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[52]->in[1] mux_1level_tapbuf_size3[52]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[52]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[52]->in[2] mux_1level_tapbuf_size3[52]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[52] gvdd_mux_1level_tapbuf_size3[52] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[296] trig v(mux_1level_tapbuf_size3[52]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[52]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[296] trig v(mux_1level_tapbuf_size3[52]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[52]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[296] when v(mux_1level_tapbuf_size3[52]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[296] trig v(mux_1level_tapbuf_size3[52]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[52]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[296] when v(mux_1level_tapbuf_size3[52]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[296] trig v(mux_1level_tapbuf_size3[52]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[52]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[52]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[52]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[296] param='mux_1level_tapbuf_size3[52]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[52]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[52]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[52]_energy_per_cycle param='mux_1level_tapbuf_size3[52]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[296] param='mux_1level_tapbuf_size3[52]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[296] param='dynamic_power_sb_mux[1][1]_rrnode[296]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[296] avg p(Vgvdd_mux_1level_tapbuf_size3[52]) from='start_rise_sb_mux[1][1]_rrnode[296]' to='start_rise_sb_mux[1][1]_rrnode[296]+switch_rise_sb_mux[1][1]_rrnode[296]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[296] avg p(Vgvdd_mux_1level_tapbuf_size3[52]) from='start_fall_sb_mux[1][1]_rrnode[296]' to='start_fall_sb_mux[1][1]_rrnode[296]+switch_fall_sb_mux[1][1]_rrnode[296]' -.meas tran sum_leakage_power_mux[0to52] -+ param='sum_leakage_power_mux[0to51]+leakage_sb_mux[1][1]_rrnode[296]' -.meas tran sum_energy_per_cycle_mux[0to52] -+ param='sum_energy_per_cycle_mux[0to51]+energy_per_cycle_sb_mux[1][1]_rrnode[296]' -***** Load for rr_node[296] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=5, type=4 ***** -Xchan_mux_1level_tapbuf_size3[52]->out_loadlvl[0]_out mux_1level_tapbuf_size3[52]->out mux_1level_tapbuf_size3[52]->out_loadlvl[0]_out mux_1level_tapbuf_size3[52]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[138]_no0 mux_1level_tapbuf_size3[52]->out_loadlvl[0]_out mux_1level_tapbuf_size3[52]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 mux_1level_tapbuf_size3[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[52]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 mux_1level_tapbuf_size3[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[52]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 mux_1level_tapbuf_size3[52]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[52]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to52] -+ param='sum_leakage_power_sb_mux[0to51]+leakage_sb_mux[1][1]_rrnode[296]' -.meas tran sum_energy_per_cycle_sb_mux[0to52] -+ param='sum_energy_per_cycle_sb_mux[0to51]+energy_per_cycle_sb_mux[1][1]_rrnode[296]' -Xmux_1level_tapbuf_size3[53] mux_1level_tapbuf_size3[53]->in[0] mux_1level_tapbuf_size3[53]->in[1] mux_1level_tapbuf_size3[53]->in[2] mux_1level_tapbuf_size3[53]->out sram[69]->outb sram[69]->out sram[70]->out sram[70]->outb sram[71]->out sram[71]->outb gvdd_mux_1level_tapbuf_size3[53] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[53], level=1, select_path_id=0. ***** -*****100***** -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -***** Signal mux_1level_tapbuf_size3[53]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[53]->in[0] mux_1level_tapbuf_size3[53]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[53]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[53]->in[1] mux_1level_tapbuf_size3[53]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[53]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[53]->in[2] mux_1level_tapbuf_size3[53]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[53] gvdd_mux_1level_tapbuf_size3[53] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[298] trig v(mux_1level_tapbuf_size3[53]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[53]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[298] trig v(mux_1level_tapbuf_size3[53]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[53]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[298] when v(mux_1level_tapbuf_size3[53]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[298] trig v(mux_1level_tapbuf_size3[53]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[53]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[298] when v(mux_1level_tapbuf_size3[53]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[298] trig v(mux_1level_tapbuf_size3[53]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[53]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[53]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[53]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[298] param='mux_1level_tapbuf_size3[53]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[53]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[53]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[53]_energy_per_cycle param='mux_1level_tapbuf_size3[53]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[298] param='mux_1level_tapbuf_size3[53]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[298] param='dynamic_power_sb_mux[1][1]_rrnode[298]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[298] avg p(Vgvdd_mux_1level_tapbuf_size3[53]) from='start_rise_sb_mux[1][1]_rrnode[298]' to='start_rise_sb_mux[1][1]_rrnode[298]+switch_rise_sb_mux[1][1]_rrnode[298]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[298] avg p(Vgvdd_mux_1level_tapbuf_size3[53]) from='start_fall_sb_mux[1][1]_rrnode[298]' to='start_fall_sb_mux[1][1]_rrnode[298]+switch_fall_sb_mux[1][1]_rrnode[298]' -.meas tran sum_leakage_power_mux[0to53] -+ param='sum_leakage_power_mux[0to52]+leakage_sb_mux[1][1]_rrnode[298]' -.meas tran sum_energy_per_cycle_mux[0to53] -+ param='sum_energy_per_cycle_mux[0to52]+energy_per_cycle_sb_mux[1][1]_rrnode[298]' -***** Load for rr_node[298] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=7, type=4 ***** -Xchan_mux_1level_tapbuf_size3[53]->out_loadlvl[0]_out mux_1level_tapbuf_size3[53]->out mux_1level_tapbuf_size3[53]->out_loadlvl[0]_out mux_1level_tapbuf_size3[53]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[142]_no0 mux_1level_tapbuf_size3[53]->out_loadlvl[0]_out mux_1level_tapbuf_size3[53]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 mux_1level_tapbuf_size3[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[53]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 mux_1level_tapbuf_size3[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[53]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 mux_1level_tapbuf_size3[53]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[53]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to53] -+ param='sum_leakage_power_sb_mux[0to52]+leakage_sb_mux[1][1]_rrnode[298]' -.meas tran sum_energy_per_cycle_sb_mux[0to53] -+ param='sum_energy_per_cycle_sb_mux[0to52]+energy_per_cycle_sb_mux[1][1]_rrnode[298]' -Xmux_1level_tapbuf_size3[54] mux_1level_tapbuf_size3[54]->in[0] mux_1level_tapbuf_size3[54]->in[1] mux_1level_tapbuf_size3[54]->in[2] mux_1level_tapbuf_size3[54]->out sram[72]->outb sram[72]->out sram[73]->out sram[73]->outb sram[74]->out sram[74]->outb gvdd_mux_1level_tapbuf_size3[54] 0 mux_1level_tapbuf_size3 -***** SRAM bits for MUX[54], level=1, select_path_id=0. ***** -*****100***** -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -***** Signal mux_1level_tapbuf_size3[54]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[54]->in[0] mux_1level_tapbuf_size3[54]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[54]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[54]->in[1] mux_1level_tapbuf_size3[54]->in[1] 0 -+ 0 -***** Signal mux_1level_tapbuf_size3[54]->in[2] density = 0, probability=0.***** -Vmux_1level_tapbuf_size3[54]->in[2] mux_1level_tapbuf_size3[54]->in[2] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size3[54] gvdd_mux_1level_tapbuf_size3[54] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[300] trig v(mux_1level_tapbuf_size3[54]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[54]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[300] trig v(mux_1level_tapbuf_size3[54]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[54]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[300] when v(mux_1level_tapbuf_size3[54]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[300] trig v(mux_1level_tapbuf_size3[54]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[54]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[300] when v(mux_1level_tapbuf_size3[54]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[300] trig v(mux_1level_tapbuf_size3[54]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size3[54]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[54]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size3[54]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[300] param='mux_1level_tapbuf_size3[54]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size3[54]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size3[54]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size3[54]_energy_per_cycle param='mux_1level_tapbuf_size3[54]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[300] param='mux_1level_tapbuf_size3[54]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[300] param='dynamic_power_sb_mux[1][1]_rrnode[300]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[300] avg p(Vgvdd_mux_1level_tapbuf_size3[54]) from='start_rise_sb_mux[1][1]_rrnode[300]' to='start_rise_sb_mux[1][1]_rrnode[300]+switch_rise_sb_mux[1][1]_rrnode[300]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[300] avg p(Vgvdd_mux_1level_tapbuf_size3[54]) from='start_fall_sb_mux[1][1]_rrnode[300]' to='start_fall_sb_mux[1][1]_rrnode[300]+switch_fall_sb_mux[1][1]_rrnode[300]' -.meas tran sum_leakage_power_mux[0to54] -+ param='sum_leakage_power_mux[0to53]+leakage_sb_mux[1][1]_rrnode[300]' -.meas tran sum_energy_per_cycle_mux[0to54] -+ param='sum_energy_per_cycle_mux[0to53]+energy_per_cycle_sb_mux[1][1]_rrnode[300]' -***** Load for rr_node[300] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=9, type=4 ***** -Xchan_mux_1level_tapbuf_size3[54]->out_loadlvl[0]_out mux_1level_tapbuf_size3[54]->out mux_1level_tapbuf_size3[54]->out_loadlvl[0]_out mux_1level_tapbuf_size3[54]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[146]_no0 mux_1level_tapbuf_size3[54]->out_loadlvl[0]_out mux_1level_tapbuf_size3[54]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 mux_1level_tapbuf_size3[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[54]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 mux_1level_tapbuf_size3[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[54]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 mux_1level_tapbuf_size3[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[54]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 mux_1level_tapbuf_size3[54]->out_loadlvl[0]_midout mux_1level_tapbuf_size3[54]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to54] -+ param='sum_leakage_power_sb_mux[0to53]+leakage_sb_mux[1][1]_rrnode[300]' -.meas tran sum_energy_per_cycle_sb_mux[0to54] -+ param='sum_energy_per_cycle_sb_mux[0to53]+energy_per_cycle_sb_mux[1][1]_rrnode[300]' -Xmux_1level_tapbuf_size2[55] mux_1level_tapbuf_size2[55]->in[0] mux_1level_tapbuf_size2[55]->in[1] mux_1level_tapbuf_size2[55]->out sram[75]->outb sram[75]->out gvdd_mux_1level_tapbuf_size2[55] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[55], level=1, select_path_id=0. ***** -*****1***** -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -***** Signal mux_1level_tapbuf_size2[55]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[55]->in[0] mux_1level_tapbuf_size2[55]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[55]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[55]->in[1] mux_1level_tapbuf_size2[55]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[55] gvdd_mux_1level_tapbuf_size2[55] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[302] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[302] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[302] when v(mux_1level_tapbuf_size2[55]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[302] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[302] when v(mux_1level_tapbuf_size2[55]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[302] trig v(mux_1level_tapbuf_size2[55]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[55]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[55]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[302] param='mux_1level_tapbuf_size2[55]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[55]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[55]_energy_per_cycle param='mux_1level_tapbuf_size2[55]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[302] param='mux_1level_tapbuf_size2[55]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[302] param='dynamic_power_sb_mux[1][1]_rrnode[302]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[302] avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='start_rise_sb_mux[1][1]_rrnode[302]' to='start_rise_sb_mux[1][1]_rrnode[302]+switch_rise_sb_mux[1][1]_rrnode[302]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[302] avg p(Vgvdd_mux_1level_tapbuf_size2[55]) from='start_fall_sb_mux[1][1]_rrnode[302]' to='start_fall_sb_mux[1][1]_rrnode[302]+switch_fall_sb_mux[1][1]_rrnode[302]' -.meas tran sum_leakage_power_mux[0to55] -+ param='sum_leakage_power_mux[0to54]+leakage_sb_mux[1][1]_rrnode[302]' -.meas tran sum_energy_per_cycle_mux[0to55] -+ param='sum_energy_per_cycle_mux[0to54]+energy_per_cycle_sb_mux[1][1]_rrnode[302]' -***** Load for rr_node[302] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=11, type=4 ***** -Xchan_mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[151]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out mux_1level_tapbuf_size2[55]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[55]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to55] -+ param='sum_leakage_power_sb_mux[0to54]+leakage_sb_mux[1][1]_rrnode[302]' -.meas tran sum_energy_per_cycle_sb_mux[0to55] -+ param='sum_energy_per_cycle_sb_mux[0to54]+energy_per_cycle_sb_mux[1][1]_rrnode[302]' -Xmux_1level_tapbuf_size2[56] mux_1level_tapbuf_size2[56]->in[0] mux_1level_tapbuf_size2[56]->in[1] mux_1level_tapbuf_size2[56]->out sram[76]->outb sram[76]->out gvdd_mux_1level_tapbuf_size2[56] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[56], level=1, select_path_id=0. ***** -*****1***** -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -***** Signal mux_1level_tapbuf_size2[56]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[56]->in[0] mux_1level_tapbuf_size2[56]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[56]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[56]->in[1] mux_1level_tapbuf_size2[56]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[56] gvdd_mux_1level_tapbuf_size2[56] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[304] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[304] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[304] when v(mux_1level_tapbuf_size2[56]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[304] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[304] when v(mux_1level_tapbuf_size2[56]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[304] trig v(mux_1level_tapbuf_size2[56]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[56]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[56]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[304] param='mux_1level_tapbuf_size2[56]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[56]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[56]_energy_per_cycle param='mux_1level_tapbuf_size2[56]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[304] param='mux_1level_tapbuf_size2[56]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[304] param='dynamic_power_sb_mux[1][1]_rrnode[304]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[304] avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='start_rise_sb_mux[1][1]_rrnode[304]' to='start_rise_sb_mux[1][1]_rrnode[304]+switch_rise_sb_mux[1][1]_rrnode[304]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[304] avg p(Vgvdd_mux_1level_tapbuf_size2[56]) from='start_fall_sb_mux[1][1]_rrnode[304]' to='start_fall_sb_mux[1][1]_rrnode[304]+switch_fall_sb_mux[1][1]_rrnode[304]' -.meas tran sum_leakage_power_mux[0to56] -+ param='sum_leakage_power_mux[0to55]+leakage_sb_mux[1][1]_rrnode[304]' -.meas tran sum_energy_per_cycle_mux[0to56] -+ param='sum_energy_per_cycle_mux[0to55]+energy_per_cycle_sb_mux[1][1]_rrnode[304]' -***** Load for rr_node[304] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=13, type=4 ***** -Xchan_mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[155]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out mux_1level_tapbuf_size2[56]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[56]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to56] -+ param='sum_leakage_power_sb_mux[0to55]+leakage_sb_mux[1][1]_rrnode[304]' -.meas tran sum_energy_per_cycle_sb_mux[0to56] -+ param='sum_energy_per_cycle_sb_mux[0to55]+energy_per_cycle_sb_mux[1][1]_rrnode[304]' -Xmux_1level_tapbuf_size2[57] mux_1level_tapbuf_size2[57]->in[0] mux_1level_tapbuf_size2[57]->in[1] mux_1level_tapbuf_size2[57]->out sram[77]->outb sram[77]->out gvdd_mux_1level_tapbuf_size2[57] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[57], level=1, select_path_id=0. ***** -*****1***** -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -***** Signal mux_1level_tapbuf_size2[57]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[57]->in[0] mux_1level_tapbuf_size2[57]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[57]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[57]->in[1] mux_1level_tapbuf_size2[57]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[57] gvdd_mux_1level_tapbuf_size2[57] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[306] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[306] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[306] when v(mux_1level_tapbuf_size2[57]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[306] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[306] when v(mux_1level_tapbuf_size2[57]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[306] trig v(mux_1level_tapbuf_size2[57]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[57]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[57]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[306] param='mux_1level_tapbuf_size2[57]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[57]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[57]_energy_per_cycle param='mux_1level_tapbuf_size2[57]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[306] param='mux_1level_tapbuf_size2[57]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[306] param='dynamic_power_sb_mux[1][1]_rrnode[306]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[306] avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='start_rise_sb_mux[1][1]_rrnode[306]' to='start_rise_sb_mux[1][1]_rrnode[306]+switch_rise_sb_mux[1][1]_rrnode[306]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[306] avg p(Vgvdd_mux_1level_tapbuf_size2[57]) from='start_fall_sb_mux[1][1]_rrnode[306]' to='start_fall_sb_mux[1][1]_rrnode[306]+switch_fall_sb_mux[1][1]_rrnode[306]' -.meas tran sum_leakage_power_mux[0to57] -+ param='sum_leakage_power_mux[0to56]+leakage_sb_mux[1][1]_rrnode[306]' -.meas tran sum_energy_per_cycle_mux[0to57] -+ param='sum_energy_per_cycle_mux[0to56]+energy_per_cycle_sb_mux[1][1]_rrnode[306]' -***** Load for rr_node[306] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=15, type=4 ***** -Xchan_mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[158]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out mux_1level_tapbuf_size2[57]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[57]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to57] -+ param='sum_leakage_power_sb_mux[0to56]+leakage_sb_mux[1][1]_rrnode[306]' -.meas tran sum_energy_per_cycle_sb_mux[0to57] -+ param='sum_energy_per_cycle_sb_mux[0to56]+energy_per_cycle_sb_mux[1][1]_rrnode[306]' -Xmux_1level_tapbuf_size2[58] mux_1level_tapbuf_size2[58]->in[0] mux_1level_tapbuf_size2[58]->in[1] mux_1level_tapbuf_size2[58]->out sram[78]->outb sram[78]->out gvdd_mux_1level_tapbuf_size2[58] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[58], level=1, select_path_id=0. ***** -*****1***** -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -***** Signal mux_1level_tapbuf_size2[58]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[58]->in[0] mux_1level_tapbuf_size2[58]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[58]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[58]->in[1] mux_1level_tapbuf_size2[58]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[58] gvdd_mux_1level_tapbuf_size2[58] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[308] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[308] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[308] when v(mux_1level_tapbuf_size2[58]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[308] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[308] when v(mux_1level_tapbuf_size2[58]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[308] trig v(mux_1level_tapbuf_size2[58]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[58]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[58]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[308] param='mux_1level_tapbuf_size2[58]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[58]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[58]_energy_per_cycle param='mux_1level_tapbuf_size2[58]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[308] param='mux_1level_tapbuf_size2[58]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[308] param='dynamic_power_sb_mux[1][1]_rrnode[308]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[308] avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='start_rise_sb_mux[1][1]_rrnode[308]' to='start_rise_sb_mux[1][1]_rrnode[308]+switch_rise_sb_mux[1][1]_rrnode[308]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[308] avg p(Vgvdd_mux_1level_tapbuf_size2[58]) from='start_fall_sb_mux[1][1]_rrnode[308]' to='start_fall_sb_mux[1][1]_rrnode[308]+switch_fall_sb_mux[1][1]_rrnode[308]' -.meas tran sum_leakage_power_mux[0to58] -+ param='sum_leakage_power_mux[0to57]+leakage_sb_mux[1][1]_rrnode[308]' -.meas tran sum_energy_per_cycle_mux[0to58] -+ param='sum_energy_per_cycle_mux[0to57]+energy_per_cycle_sb_mux[1][1]_rrnode[308]' -***** Load for rr_node[308] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=17, type=4 ***** -Xchan_mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[161]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out mux_1level_tapbuf_size2[58]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[58]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to58] -+ param='sum_leakage_power_sb_mux[0to57]+leakage_sb_mux[1][1]_rrnode[308]' -.meas tran sum_energy_per_cycle_sb_mux[0to58] -+ param='sum_energy_per_cycle_sb_mux[0to57]+energy_per_cycle_sb_mux[1][1]_rrnode[308]' -Xmux_1level_tapbuf_size2[59] mux_1level_tapbuf_size2[59]->in[0] mux_1level_tapbuf_size2[59]->in[1] mux_1level_tapbuf_size2[59]->out sram[79]->outb sram[79]->out gvdd_mux_1level_tapbuf_size2[59] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[59], level=1, select_path_id=0. ***** -*****1***** -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -***** Signal mux_1level_tapbuf_size2[59]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[59]->in[0] mux_1level_tapbuf_size2[59]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[59]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[59]->in[1] mux_1level_tapbuf_size2[59]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[59] gvdd_mux_1level_tapbuf_size2[59] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[310] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[310] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[310] when v(mux_1level_tapbuf_size2[59]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[310] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[310] when v(mux_1level_tapbuf_size2[59]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[310] trig v(mux_1level_tapbuf_size2[59]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[59]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[59]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[310] param='mux_1level_tapbuf_size2[59]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[59]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[59]_energy_per_cycle param='mux_1level_tapbuf_size2[59]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[310] param='mux_1level_tapbuf_size2[59]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[310] param='dynamic_power_sb_mux[1][1]_rrnode[310]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[310] avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='start_rise_sb_mux[1][1]_rrnode[310]' to='start_rise_sb_mux[1][1]_rrnode[310]+switch_rise_sb_mux[1][1]_rrnode[310]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[310] avg p(Vgvdd_mux_1level_tapbuf_size2[59]) from='start_fall_sb_mux[1][1]_rrnode[310]' to='start_fall_sb_mux[1][1]_rrnode[310]+switch_fall_sb_mux[1][1]_rrnode[310]' -.meas tran sum_leakage_power_mux[0to59] -+ param='sum_leakage_power_mux[0to58]+leakage_sb_mux[1][1]_rrnode[310]' -.meas tran sum_energy_per_cycle_mux[0to59] -+ param='sum_energy_per_cycle_mux[0to58]+energy_per_cycle_sb_mux[1][1]_rrnode[310]' -***** Load for rr_node[310] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=19, type=4 ***** -Xchan_mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[164]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out mux_1level_tapbuf_size2[59]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[59]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to59] -+ param='sum_leakage_power_sb_mux[0to58]+leakage_sb_mux[1][1]_rrnode[310]' -.meas tran sum_energy_per_cycle_sb_mux[0to59] -+ param='sum_energy_per_cycle_sb_mux[0to58]+energy_per_cycle_sb_mux[1][1]_rrnode[310]' -Xmux_1level_tapbuf_size2[60] mux_1level_tapbuf_size2[60]->in[0] mux_1level_tapbuf_size2[60]->in[1] mux_1level_tapbuf_size2[60]->out sram[80]->outb sram[80]->out gvdd_mux_1level_tapbuf_size2[60] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[60], level=1, select_path_id=0. ***** -*****1***** -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -***** Signal mux_1level_tapbuf_size2[60]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[60]->in[0] mux_1level_tapbuf_size2[60]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[60]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[60]->in[1] mux_1level_tapbuf_size2[60]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[60] gvdd_mux_1level_tapbuf_size2[60] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[312] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[312] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[312] when v(mux_1level_tapbuf_size2[60]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[312] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[312] when v(mux_1level_tapbuf_size2[60]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[312] trig v(mux_1level_tapbuf_size2[60]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[60]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[60]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[312] param='mux_1level_tapbuf_size2[60]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[60]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[60]_energy_per_cycle param='mux_1level_tapbuf_size2[60]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[312] param='mux_1level_tapbuf_size2[60]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[312] param='dynamic_power_sb_mux[1][1]_rrnode[312]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[312] avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='start_rise_sb_mux[1][1]_rrnode[312]' to='start_rise_sb_mux[1][1]_rrnode[312]+switch_rise_sb_mux[1][1]_rrnode[312]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[312] avg p(Vgvdd_mux_1level_tapbuf_size2[60]) from='start_fall_sb_mux[1][1]_rrnode[312]' to='start_fall_sb_mux[1][1]_rrnode[312]+switch_fall_sb_mux[1][1]_rrnode[312]' -.meas tran sum_leakage_power_mux[0to60] -+ param='sum_leakage_power_mux[0to59]+leakage_sb_mux[1][1]_rrnode[312]' -.meas tran sum_energy_per_cycle_mux[0to60] -+ param='sum_energy_per_cycle_mux[0to59]+energy_per_cycle_sb_mux[1][1]_rrnode[312]' -***** Load for rr_node[312] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=21, type=4 ***** -Xchan_mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[168]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out mux_1level_tapbuf_size2[60]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[60]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to60] -+ param='sum_leakage_power_sb_mux[0to59]+leakage_sb_mux[1][1]_rrnode[312]' -.meas tran sum_energy_per_cycle_sb_mux[0to60] -+ param='sum_energy_per_cycle_sb_mux[0to59]+energy_per_cycle_sb_mux[1][1]_rrnode[312]' -Xmux_1level_tapbuf_size2[61] mux_1level_tapbuf_size2[61]->in[0] mux_1level_tapbuf_size2[61]->in[1] mux_1level_tapbuf_size2[61]->out sram[81]->outb sram[81]->out gvdd_mux_1level_tapbuf_size2[61] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[61], level=1, select_path_id=0. ***** -*****1***** -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -***** Signal mux_1level_tapbuf_size2[61]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[61]->in[0] mux_1level_tapbuf_size2[61]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[61]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[61]->in[1] mux_1level_tapbuf_size2[61]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[61] gvdd_mux_1level_tapbuf_size2[61] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[314] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[314] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[314] when v(mux_1level_tapbuf_size2[61]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[314] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[314] when v(mux_1level_tapbuf_size2[61]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[314] trig v(mux_1level_tapbuf_size2[61]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[61]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[61]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[314] param='mux_1level_tapbuf_size2[61]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[61]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[61]_energy_per_cycle param='mux_1level_tapbuf_size2[61]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[314] param='mux_1level_tapbuf_size2[61]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[314] param='dynamic_power_sb_mux[1][1]_rrnode[314]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[314] avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='start_rise_sb_mux[1][1]_rrnode[314]' to='start_rise_sb_mux[1][1]_rrnode[314]+switch_rise_sb_mux[1][1]_rrnode[314]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[314] avg p(Vgvdd_mux_1level_tapbuf_size2[61]) from='start_fall_sb_mux[1][1]_rrnode[314]' to='start_fall_sb_mux[1][1]_rrnode[314]+switch_fall_sb_mux[1][1]_rrnode[314]' -.meas tran sum_leakage_power_mux[0to61] -+ param='sum_leakage_power_mux[0to60]+leakage_sb_mux[1][1]_rrnode[314]' -.meas tran sum_energy_per_cycle_mux[0to61] -+ param='sum_energy_per_cycle_mux[0to60]+energy_per_cycle_sb_mux[1][1]_rrnode[314]' -***** Load for rr_node[314] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=23, type=4 ***** -Xchan_mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[172]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out mux_1level_tapbuf_size2[61]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[61]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to61] -+ param='sum_leakage_power_sb_mux[0to60]+leakage_sb_mux[1][1]_rrnode[314]' -.meas tran sum_energy_per_cycle_sb_mux[0to61] -+ param='sum_energy_per_cycle_sb_mux[0to60]+energy_per_cycle_sb_mux[1][1]_rrnode[314]' -Xmux_1level_tapbuf_size2[62] mux_1level_tapbuf_size2[62]->in[0] mux_1level_tapbuf_size2[62]->in[1] mux_1level_tapbuf_size2[62]->out sram[82]->outb sram[82]->out gvdd_mux_1level_tapbuf_size2[62] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[62], level=1, select_path_id=0. ***** -*****1***** -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -***** Signal mux_1level_tapbuf_size2[62]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[62]->in[0] mux_1level_tapbuf_size2[62]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[62]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[62]->in[1] mux_1level_tapbuf_size2[62]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[62] gvdd_mux_1level_tapbuf_size2[62] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[316] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[316] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[316] when v(mux_1level_tapbuf_size2[62]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[316] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[316] when v(mux_1level_tapbuf_size2[62]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[316] trig v(mux_1level_tapbuf_size2[62]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[62]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[62]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[316] param='mux_1level_tapbuf_size2[62]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[62]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[62]_energy_per_cycle param='mux_1level_tapbuf_size2[62]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[316] param='mux_1level_tapbuf_size2[62]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[316] param='dynamic_power_sb_mux[1][1]_rrnode[316]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[316] avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='start_rise_sb_mux[1][1]_rrnode[316]' to='start_rise_sb_mux[1][1]_rrnode[316]+switch_rise_sb_mux[1][1]_rrnode[316]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[316] avg p(Vgvdd_mux_1level_tapbuf_size2[62]) from='start_fall_sb_mux[1][1]_rrnode[316]' to='start_fall_sb_mux[1][1]_rrnode[316]+switch_fall_sb_mux[1][1]_rrnode[316]' -.meas tran sum_leakage_power_mux[0to62] -+ param='sum_leakage_power_mux[0to61]+leakage_sb_mux[1][1]_rrnode[316]' -.meas tran sum_energy_per_cycle_mux[0to62] -+ param='sum_energy_per_cycle_mux[0to61]+energy_per_cycle_sb_mux[1][1]_rrnode[316]' -***** Load for rr_node[316] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=25, type=4 ***** -Xchan_mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[177]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out mux_1level_tapbuf_size2[62]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[180]_no0 mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[62]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to62] -+ param='sum_leakage_power_sb_mux[0to61]+leakage_sb_mux[1][1]_rrnode[316]' -.meas tran sum_energy_per_cycle_sb_mux[0to62] -+ param='sum_energy_per_cycle_sb_mux[0to61]+energy_per_cycle_sb_mux[1][1]_rrnode[316]' -Xmux_1level_tapbuf_size2[63] mux_1level_tapbuf_size2[63]->in[0] mux_1level_tapbuf_size2[63]->in[1] mux_1level_tapbuf_size2[63]->out sram[83]->outb sram[83]->out gvdd_mux_1level_tapbuf_size2[63] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[63], level=1, select_path_id=0. ***** -*****1***** -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -***** Signal mux_1level_tapbuf_size2[63]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[63]->in[0] mux_1level_tapbuf_size2[63]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[63]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[63]->in[1] mux_1level_tapbuf_size2[63]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[63] gvdd_mux_1level_tapbuf_size2[63] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[318] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[318] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[318] when v(mux_1level_tapbuf_size2[63]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[318] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[318] when v(mux_1level_tapbuf_size2[63]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[318] trig v(mux_1level_tapbuf_size2[63]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[63]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[63]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[318] param='mux_1level_tapbuf_size2[63]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[63]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[63]_energy_per_cycle param='mux_1level_tapbuf_size2[63]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[318] param='mux_1level_tapbuf_size2[63]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[318] param='dynamic_power_sb_mux[1][1]_rrnode[318]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[318] avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='start_rise_sb_mux[1][1]_rrnode[318]' to='start_rise_sb_mux[1][1]_rrnode[318]+switch_rise_sb_mux[1][1]_rrnode[318]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[318] avg p(Vgvdd_mux_1level_tapbuf_size2[63]) from='start_fall_sb_mux[1][1]_rrnode[318]' to='start_fall_sb_mux[1][1]_rrnode[318]+switch_fall_sb_mux[1][1]_rrnode[318]' -.meas tran sum_leakage_power_mux[0to63] -+ param='sum_leakage_power_mux[0to62]+leakage_sb_mux[1][1]_rrnode[318]' -.meas tran sum_energy_per_cycle_mux[0to63] -+ param='sum_energy_per_cycle_mux[0to62]+energy_per_cycle_sb_mux[1][1]_rrnode[318]' -***** Load for rr_node[318] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=27, type=4 ***** -Xchan_mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[181]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out mux_1level_tapbuf_size2[63]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[63]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to63] -+ param='sum_leakage_power_sb_mux[0to62]+leakage_sb_mux[1][1]_rrnode[318]' -.meas tran sum_energy_per_cycle_sb_mux[0to63] -+ param='sum_energy_per_cycle_sb_mux[0to62]+energy_per_cycle_sb_mux[1][1]_rrnode[318]' -Xmux_1level_tapbuf_size2[64] mux_1level_tapbuf_size2[64]->in[0] mux_1level_tapbuf_size2[64]->in[1] mux_1level_tapbuf_size2[64]->out sram[84]->outb sram[84]->out gvdd_mux_1level_tapbuf_size2[64] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[64], level=1, select_path_id=0. ***** -*****1***** -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -***** Signal mux_1level_tapbuf_size2[64]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[64]->in[0] mux_1level_tapbuf_size2[64]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[64]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[64]->in[1] mux_1level_tapbuf_size2[64]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[64] gvdd_mux_1level_tapbuf_size2[64] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[320] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[320] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[320] when v(mux_1level_tapbuf_size2[64]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[320] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[320] when v(mux_1level_tapbuf_size2[64]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[320] trig v(mux_1level_tapbuf_size2[64]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[64]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[64]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[320] param='mux_1level_tapbuf_size2[64]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[64]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[64]_energy_per_cycle param='mux_1level_tapbuf_size2[64]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[320] param='mux_1level_tapbuf_size2[64]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[320] param='dynamic_power_sb_mux[1][1]_rrnode[320]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[320] avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='start_rise_sb_mux[1][1]_rrnode[320]' to='start_rise_sb_mux[1][1]_rrnode[320]+switch_rise_sb_mux[1][1]_rrnode[320]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[320] avg p(Vgvdd_mux_1level_tapbuf_size2[64]) from='start_fall_sb_mux[1][1]_rrnode[320]' to='start_fall_sb_mux[1][1]_rrnode[320]+switch_fall_sb_mux[1][1]_rrnode[320]' -.meas tran sum_leakage_power_mux[0to64] -+ param='sum_leakage_power_mux[0to63]+leakage_sb_mux[1][1]_rrnode[320]' -.meas tran sum_energy_per_cycle_mux[0to64] -+ param='sum_energy_per_cycle_mux[0to63]+energy_per_cycle_sb_mux[1][1]_rrnode[320]' -***** Load for rr_node[320] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=29, type=4 ***** -Xchan_mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[184]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out mux_1level_tapbuf_size2[64]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[64]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to64] -+ param='sum_leakage_power_sb_mux[0to63]+leakage_sb_mux[1][1]_rrnode[320]' -.meas tran sum_energy_per_cycle_sb_mux[0to64] -+ param='sum_energy_per_cycle_sb_mux[0to63]+energy_per_cycle_sb_mux[1][1]_rrnode[320]' -Xmux_1level_tapbuf_size2[65] mux_1level_tapbuf_size2[65]->in[0] mux_1level_tapbuf_size2[65]->in[1] mux_1level_tapbuf_size2[65]->out sram[85]->outb sram[85]->out gvdd_mux_1level_tapbuf_size2[65] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[65], level=1, select_path_id=0. ***** -*****1***** -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -***** Signal mux_1level_tapbuf_size2[65]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[65]->in[0] mux_1level_tapbuf_size2[65]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[65]->in[1] density = 0.2026, probability=0.4982.***** -Vmux_1level_tapbuf_size2[65]->in[1] mux_1level_tapbuf_size2[65]->in[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgvdd_mux_1level_tapbuf_size2[65] gvdd_mux_1level_tapbuf_size2[65] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[322] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[322] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[322] when v(mux_1level_tapbuf_size2[65]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[322] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[322] when v(mux_1level_tapbuf_size2[65]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[322] trig v(mux_1level_tapbuf_size2[65]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[65]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[65]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[322] param='mux_1level_tapbuf_size2[65]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[65]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='clock_period' to='6*clock_period' -.meas tran mux_1level_tapbuf_size2[65]_energy_per_cycle param='mux_1level_tapbuf_size2[65]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[322] param='mux_1level_tapbuf_size2[65]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[322] param='dynamic_power_sb_mux[1][1]_rrnode[322]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[322] avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='start_rise_sb_mux[1][1]_rrnode[322]' to='start_rise_sb_mux[1][1]_rrnode[322]+switch_rise_sb_mux[1][1]_rrnode[322]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[322] avg p(Vgvdd_mux_1level_tapbuf_size2[65]) from='start_fall_sb_mux[1][1]_rrnode[322]' to='start_fall_sb_mux[1][1]_rrnode[322]+switch_fall_sb_mux[1][1]_rrnode[322]' -.meas tran sum_leakage_power_mux[0to65] -+ param='sum_leakage_power_mux[0to64]+leakage_sb_mux[1][1]_rrnode[322]' -.meas tran sum_energy_per_cycle_mux[0to65] -+ param='sum_energy_per_cycle_mux[0to64]+energy_per_cycle_sb_mux[1][1]_rrnode[322]' -***** Load for rr_node[322] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=31, type=4 ***** -Xchan_mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[188]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out mux_1level_tapbuf_size2[65]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[65]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to65] -+ param='sum_leakage_power_sb_mux[0to64]+leakage_sb_mux[1][1]_rrnode[322]' -.meas tran sum_energy_per_cycle_sb_mux[0to65] -+ param='sum_energy_per_cycle_sb_mux[0to64]+energy_per_cycle_sb_mux[1][1]_rrnode[322]' -Xmux_1level_tapbuf_size2[66] mux_1level_tapbuf_size2[66]->in[0] mux_1level_tapbuf_size2[66]->in[1] mux_1level_tapbuf_size2[66]->out sram[86]->outb sram[86]->out gvdd_mux_1level_tapbuf_size2[66] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[66], level=1, select_path_id=0. ***** -*****1***** -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -***** Signal mux_1level_tapbuf_size2[66]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[66]->in[0] mux_1level_tapbuf_size2[66]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[66]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[66]->in[1] mux_1level_tapbuf_size2[66]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[66] gvdd_mux_1level_tapbuf_size2[66] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[324] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[324] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[324] when v(mux_1level_tapbuf_size2[66]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[324] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[324] when v(mux_1level_tapbuf_size2[66]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[324] trig v(mux_1level_tapbuf_size2[66]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[66]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[66]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[324] param='mux_1level_tapbuf_size2[66]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[66]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[66]_energy_per_cycle param='mux_1level_tapbuf_size2[66]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[324] param='mux_1level_tapbuf_size2[66]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[324] param='dynamic_power_sb_mux[1][1]_rrnode[324]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[324] avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='start_rise_sb_mux[1][1]_rrnode[324]' to='start_rise_sb_mux[1][1]_rrnode[324]+switch_rise_sb_mux[1][1]_rrnode[324]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[324] avg p(Vgvdd_mux_1level_tapbuf_size2[66]) from='start_fall_sb_mux[1][1]_rrnode[324]' to='start_fall_sb_mux[1][1]_rrnode[324]+switch_fall_sb_mux[1][1]_rrnode[324]' -.meas tran sum_leakage_power_mux[0to66] -+ param='sum_leakage_power_mux[0to65]+leakage_sb_mux[1][1]_rrnode[324]' -.meas tran sum_energy_per_cycle_mux[0to66] -+ param='sum_energy_per_cycle_mux[0to65]+energy_per_cycle_sb_mux[1][1]_rrnode[324]' -***** Load for rr_node[324] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=33, type=4 ***** -Xchan_mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[192]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out mux_1level_tapbuf_size2[66]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[66]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to66] -+ param='sum_leakage_power_sb_mux[0to65]+leakage_sb_mux[1][1]_rrnode[324]' -.meas tran sum_energy_per_cycle_sb_mux[0to66] -+ param='sum_energy_per_cycle_sb_mux[0to65]+energy_per_cycle_sb_mux[1][1]_rrnode[324]' -Xmux_1level_tapbuf_size2[67] mux_1level_tapbuf_size2[67]->in[0] mux_1level_tapbuf_size2[67]->in[1] mux_1level_tapbuf_size2[67]->out sram[87]->outb sram[87]->out gvdd_mux_1level_tapbuf_size2[67] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[67], level=1, select_path_id=0. ***** -*****1***** -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -***** Signal mux_1level_tapbuf_size2[67]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[67]->in[0] mux_1level_tapbuf_size2[67]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[67]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[67]->in[1] mux_1level_tapbuf_size2[67]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[67] gvdd_mux_1level_tapbuf_size2[67] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[326] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[326] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[326] when v(mux_1level_tapbuf_size2[67]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[326] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[326] when v(mux_1level_tapbuf_size2[67]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[326] trig v(mux_1level_tapbuf_size2[67]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[67]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[67]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[326] param='mux_1level_tapbuf_size2[67]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[67]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[67]_energy_per_cycle param='mux_1level_tapbuf_size2[67]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[326] param='mux_1level_tapbuf_size2[67]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[326] param='dynamic_power_sb_mux[1][1]_rrnode[326]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[326] avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='start_rise_sb_mux[1][1]_rrnode[326]' to='start_rise_sb_mux[1][1]_rrnode[326]+switch_rise_sb_mux[1][1]_rrnode[326]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[326] avg p(Vgvdd_mux_1level_tapbuf_size2[67]) from='start_fall_sb_mux[1][1]_rrnode[326]' to='start_fall_sb_mux[1][1]_rrnode[326]+switch_fall_sb_mux[1][1]_rrnode[326]' -.meas tran sum_leakage_power_mux[0to67] -+ param='sum_leakage_power_mux[0to66]+leakage_sb_mux[1][1]_rrnode[326]' -.meas tran sum_energy_per_cycle_mux[0to67] -+ param='sum_energy_per_cycle_mux[0to66]+energy_per_cycle_sb_mux[1][1]_rrnode[326]' -***** Load for rr_node[326] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=35, type=4 ***** -Xchan_mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[195]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out mux_1level_tapbuf_size2[67]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[67]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to67] -+ param='sum_leakage_power_sb_mux[0to66]+leakage_sb_mux[1][1]_rrnode[326]' -.meas tran sum_energy_per_cycle_sb_mux[0to67] -+ param='sum_energy_per_cycle_sb_mux[0to66]+energy_per_cycle_sb_mux[1][1]_rrnode[326]' -Xmux_1level_tapbuf_size2[68] mux_1level_tapbuf_size2[68]->in[0] mux_1level_tapbuf_size2[68]->in[1] mux_1level_tapbuf_size2[68]->out sram[88]->outb sram[88]->out gvdd_mux_1level_tapbuf_size2[68] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[68], level=1, select_path_id=0. ***** -*****1***** -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -***** Signal mux_1level_tapbuf_size2[68]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[68]->in[0] mux_1level_tapbuf_size2[68]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[68]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[68]->in[1] mux_1level_tapbuf_size2[68]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[68] gvdd_mux_1level_tapbuf_size2[68] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[328] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[328] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[328] when v(mux_1level_tapbuf_size2[68]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[328] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[328] when v(mux_1level_tapbuf_size2[68]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[328] trig v(mux_1level_tapbuf_size2[68]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[68]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[68]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[328] param='mux_1level_tapbuf_size2[68]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[68]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[68]_energy_per_cycle param='mux_1level_tapbuf_size2[68]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[328] param='mux_1level_tapbuf_size2[68]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[328] param='dynamic_power_sb_mux[1][1]_rrnode[328]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[328] avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='start_rise_sb_mux[1][1]_rrnode[328]' to='start_rise_sb_mux[1][1]_rrnode[328]+switch_rise_sb_mux[1][1]_rrnode[328]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[328] avg p(Vgvdd_mux_1level_tapbuf_size2[68]) from='start_fall_sb_mux[1][1]_rrnode[328]' to='start_fall_sb_mux[1][1]_rrnode[328]+switch_fall_sb_mux[1][1]_rrnode[328]' -.meas tran sum_leakage_power_mux[0to68] -+ param='sum_leakage_power_mux[0to67]+leakage_sb_mux[1][1]_rrnode[328]' -.meas tran sum_energy_per_cycle_mux[0to68] -+ param='sum_energy_per_cycle_mux[0to67]+energy_per_cycle_sb_mux[1][1]_rrnode[328]' -***** Load for rr_node[328] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=37, type=4 ***** -Xchan_mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[199]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out mux_1level_tapbuf_size2[68]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[68]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to68] -+ param='sum_leakage_power_sb_mux[0to67]+leakage_sb_mux[1][1]_rrnode[328]' -.meas tran sum_energy_per_cycle_sb_mux[0to68] -+ param='sum_energy_per_cycle_sb_mux[0to67]+energy_per_cycle_sb_mux[1][1]_rrnode[328]' -Xmux_1level_tapbuf_size2[69] mux_1level_tapbuf_size2[69]->in[0] mux_1level_tapbuf_size2[69]->in[1] mux_1level_tapbuf_size2[69]->out sram[89]->outb sram[89]->out gvdd_mux_1level_tapbuf_size2[69] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[69], level=1, select_path_id=0. ***** -*****1***** -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -***** Signal mux_1level_tapbuf_size2[69]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[69]->in[0] mux_1level_tapbuf_size2[69]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[69]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[69]->in[1] mux_1level_tapbuf_size2[69]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[69] gvdd_mux_1level_tapbuf_size2[69] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[330] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[330] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[330] when v(mux_1level_tapbuf_size2[69]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[330] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[330] when v(mux_1level_tapbuf_size2[69]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[330] trig v(mux_1level_tapbuf_size2[69]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[69]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[69]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[330] param='mux_1level_tapbuf_size2[69]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[69]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[69]_energy_per_cycle param='mux_1level_tapbuf_size2[69]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[330] param='mux_1level_tapbuf_size2[69]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[330] param='dynamic_power_sb_mux[1][1]_rrnode[330]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[330] avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='start_rise_sb_mux[1][1]_rrnode[330]' to='start_rise_sb_mux[1][1]_rrnode[330]+switch_rise_sb_mux[1][1]_rrnode[330]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[330] avg p(Vgvdd_mux_1level_tapbuf_size2[69]) from='start_fall_sb_mux[1][1]_rrnode[330]' to='start_fall_sb_mux[1][1]_rrnode[330]+switch_fall_sb_mux[1][1]_rrnode[330]' -.meas tran sum_leakage_power_mux[0to69] -+ param='sum_leakage_power_mux[0to68]+leakage_sb_mux[1][1]_rrnode[330]' -.meas tran sum_energy_per_cycle_mux[0to69] -+ param='sum_energy_per_cycle_mux[0to68]+energy_per_cycle_sb_mux[1][1]_rrnode[330]' -***** Load for rr_node[330] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=39, type=4 ***** -Xchan_mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[203]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out mux_1level_tapbuf_size2[69]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[69]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to69] -+ param='sum_leakage_power_sb_mux[0to68]+leakage_sb_mux[1][1]_rrnode[330]' -.meas tran sum_energy_per_cycle_sb_mux[0to69] -+ param='sum_energy_per_cycle_sb_mux[0to68]+energy_per_cycle_sb_mux[1][1]_rrnode[330]' -Xmux_1level_tapbuf_size2[70] mux_1level_tapbuf_size2[70]->in[0] mux_1level_tapbuf_size2[70]->in[1] mux_1level_tapbuf_size2[70]->out sram[90]->outb sram[90]->out gvdd_mux_1level_tapbuf_size2[70] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[70], level=1, select_path_id=0. ***** -*****1***** -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -***** Signal mux_1level_tapbuf_size2[70]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[70]->in[0] mux_1level_tapbuf_size2[70]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[70]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[70]->in[1] mux_1level_tapbuf_size2[70]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[70] gvdd_mux_1level_tapbuf_size2[70] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[332] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[332] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[332] when v(mux_1level_tapbuf_size2[70]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[332] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[332] when v(mux_1level_tapbuf_size2[70]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[332] trig v(mux_1level_tapbuf_size2[70]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[70]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[70]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[332] param='mux_1level_tapbuf_size2[70]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[70]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[70]_energy_per_cycle param='mux_1level_tapbuf_size2[70]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[332] param='mux_1level_tapbuf_size2[70]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[332] param='dynamic_power_sb_mux[1][1]_rrnode[332]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[332] avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='start_rise_sb_mux[1][1]_rrnode[332]' to='start_rise_sb_mux[1][1]_rrnode[332]+switch_rise_sb_mux[1][1]_rrnode[332]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[332] avg p(Vgvdd_mux_1level_tapbuf_size2[70]) from='start_fall_sb_mux[1][1]_rrnode[332]' to='start_fall_sb_mux[1][1]_rrnode[332]+switch_fall_sb_mux[1][1]_rrnode[332]' -.meas tran sum_leakage_power_mux[0to70] -+ param='sum_leakage_power_mux[0to69]+leakage_sb_mux[1][1]_rrnode[332]' -.meas tran sum_energy_per_cycle_mux[0to70] -+ param='sum_energy_per_cycle_mux[0to69]+energy_per_cycle_sb_mux[1][1]_rrnode[332]' -***** Load for rr_node[332] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=41, type=4 ***** -Xchan_mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[208]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out mux_1level_tapbuf_size2[70]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[70]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to70] -+ param='sum_leakage_power_sb_mux[0to69]+leakage_sb_mux[1][1]_rrnode[332]' -.meas tran sum_energy_per_cycle_sb_mux[0to70] -+ param='sum_energy_per_cycle_sb_mux[0to69]+energy_per_cycle_sb_mux[1][1]_rrnode[332]' -Xmux_1level_tapbuf_size2[71] mux_1level_tapbuf_size2[71]->in[0] mux_1level_tapbuf_size2[71]->in[1] mux_1level_tapbuf_size2[71]->out sram[91]->outb sram[91]->out gvdd_mux_1level_tapbuf_size2[71] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[71], level=1, select_path_id=0. ***** -*****1***** -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -***** Signal mux_1level_tapbuf_size2[71]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[71]->in[0] mux_1level_tapbuf_size2[71]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[71]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[71]->in[1] mux_1level_tapbuf_size2[71]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[71] gvdd_mux_1level_tapbuf_size2[71] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[334] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[334] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[334] when v(mux_1level_tapbuf_size2[71]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[334] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[334] when v(mux_1level_tapbuf_size2[71]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[334] trig v(mux_1level_tapbuf_size2[71]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[71]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[71]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[334] param='mux_1level_tapbuf_size2[71]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[71]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[71]_energy_per_cycle param='mux_1level_tapbuf_size2[71]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[334] param='mux_1level_tapbuf_size2[71]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[334] param='dynamic_power_sb_mux[1][1]_rrnode[334]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[334] avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='start_rise_sb_mux[1][1]_rrnode[334]' to='start_rise_sb_mux[1][1]_rrnode[334]+switch_rise_sb_mux[1][1]_rrnode[334]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[334] avg p(Vgvdd_mux_1level_tapbuf_size2[71]) from='start_fall_sb_mux[1][1]_rrnode[334]' to='start_fall_sb_mux[1][1]_rrnode[334]+switch_fall_sb_mux[1][1]_rrnode[334]' -.meas tran sum_leakage_power_mux[0to71] -+ param='sum_leakage_power_mux[0to70]+leakage_sb_mux[1][1]_rrnode[334]' -.meas tran sum_energy_per_cycle_mux[0to71] -+ param='sum_energy_per_cycle_mux[0to70]+energy_per_cycle_sb_mux[1][1]_rrnode[334]' -***** Load for rr_node[334] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=43, type=4 ***** -Xchan_mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[212]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out mux_1level_tapbuf_size2[71]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[71]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to71] -+ param='sum_leakage_power_sb_mux[0to70]+leakage_sb_mux[1][1]_rrnode[334]' -.meas tran sum_energy_per_cycle_sb_mux[0to71] -+ param='sum_energy_per_cycle_sb_mux[0to70]+energy_per_cycle_sb_mux[1][1]_rrnode[334]' -Xmux_1level_tapbuf_size2[72] mux_1level_tapbuf_size2[72]->in[0] mux_1level_tapbuf_size2[72]->in[1] mux_1level_tapbuf_size2[72]->out sram[92]->outb sram[92]->out gvdd_mux_1level_tapbuf_size2[72] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[72], level=1, select_path_id=0. ***** -*****1***** -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -***** Signal mux_1level_tapbuf_size2[72]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[72]->in[0] mux_1level_tapbuf_size2[72]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[72]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[72]->in[1] mux_1level_tapbuf_size2[72]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[72] gvdd_mux_1level_tapbuf_size2[72] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[336] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[336] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[336] when v(mux_1level_tapbuf_size2[72]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[336] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[336] when v(mux_1level_tapbuf_size2[72]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[336] trig v(mux_1level_tapbuf_size2[72]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[72]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[72]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[336] param='mux_1level_tapbuf_size2[72]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[72]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[72]_energy_per_cycle param='mux_1level_tapbuf_size2[72]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[336] param='mux_1level_tapbuf_size2[72]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[336] param='dynamic_power_sb_mux[1][1]_rrnode[336]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[336] avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='start_rise_sb_mux[1][1]_rrnode[336]' to='start_rise_sb_mux[1][1]_rrnode[336]+switch_rise_sb_mux[1][1]_rrnode[336]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[336] avg p(Vgvdd_mux_1level_tapbuf_size2[72]) from='start_fall_sb_mux[1][1]_rrnode[336]' to='start_fall_sb_mux[1][1]_rrnode[336]+switch_fall_sb_mux[1][1]_rrnode[336]' -.meas tran sum_leakage_power_mux[0to72] -+ param='sum_leakage_power_mux[0to71]+leakage_sb_mux[1][1]_rrnode[336]' -.meas tran sum_energy_per_cycle_mux[0to72] -+ param='sum_energy_per_cycle_mux[0to71]+energy_per_cycle_sb_mux[1][1]_rrnode[336]' -***** Load for rr_node[336] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=45, type=4 ***** -Xchan_mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[216]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out mux_1level_tapbuf_size2[72]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[72]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to72] -+ param='sum_leakage_power_sb_mux[0to71]+leakage_sb_mux[1][1]_rrnode[336]' -.meas tran sum_energy_per_cycle_sb_mux[0to72] -+ param='sum_energy_per_cycle_sb_mux[0to71]+energy_per_cycle_sb_mux[1][1]_rrnode[336]' -Xmux_1level_tapbuf_size2[73] mux_1level_tapbuf_size2[73]->in[0] mux_1level_tapbuf_size2[73]->in[1] mux_1level_tapbuf_size2[73]->out sram[93]->outb sram[93]->out gvdd_mux_1level_tapbuf_size2[73] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[73], level=1, select_path_id=0. ***** -*****1***** -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -***** Signal mux_1level_tapbuf_size2[73]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[73]->in[0] mux_1level_tapbuf_size2[73]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[73]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[73]->in[1] mux_1level_tapbuf_size2[73]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[73] gvdd_mux_1level_tapbuf_size2[73] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[338] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[338] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[338] when v(mux_1level_tapbuf_size2[73]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[338] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[338] when v(mux_1level_tapbuf_size2[73]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[338] trig v(mux_1level_tapbuf_size2[73]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[73]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[73]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[338] param='mux_1level_tapbuf_size2[73]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[73]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[73]_energy_per_cycle param='mux_1level_tapbuf_size2[73]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[338] param='mux_1level_tapbuf_size2[73]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[338] param='dynamic_power_sb_mux[1][1]_rrnode[338]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[338] avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='start_rise_sb_mux[1][1]_rrnode[338]' to='start_rise_sb_mux[1][1]_rrnode[338]+switch_rise_sb_mux[1][1]_rrnode[338]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[338] avg p(Vgvdd_mux_1level_tapbuf_size2[73]) from='start_fall_sb_mux[1][1]_rrnode[338]' to='start_fall_sb_mux[1][1]_rrnode[338]+switch_fall_sb_mux[1][1]_rrnode[338]' -.meas tran sum_leakage_power_mux[0to73] -+ param='sum_leakage_power_mux[0to72]+leakage_sb_mux[1][1]_rrnode[338]' -.meas tran sum_energy_per_cycle_mux[0to73] -+ param='sum_energy_per_cycle_mux[0to72]+energy_per_cycle_sb_mux[1][1]_rrnode[338]' -***** Load for rr_node[338] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=47, type=4 ***** -Xchan_mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[221]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out mux_1level_tapbuf_size2[73]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[73]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to73] -+ param='sum_leakage_power_sb_mux[0to72]+leakage_sb_mux[1][1]_rrnode[338]' -.meas tran sum_energy_per_cycle_sb_mux[0to73] -+ param='sum_energy_per_cycle_sb_mux[0to72]+energy_per_cycle_sb_mux[1][1]_rrnode[338]' -Xmux_1level_tapbuf_size2[74] mux_1level_tapbuf_size2[74]->in[0] mux_1level_tapbuf_size2[74]->in[1] mux_1level_tapbuf_size2[74]->out sram[94]->outb sram[94]->out gvdd_mux_1level_tapbuf_size2[74] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[74], level=1, select_path_id=0. ***** -*****1***** -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -***** Signal mux_1level_tapbuf_size2[74]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[74]->in[0] mux_1level_tapbuf_size2[74]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[74]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[74]->in[1] mux_1level_tapbuf_size2[74]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[74] gvdd_mux_1level_tapbuf_size2[74] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[340] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[340] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[340] when v(mux_1level_tapbuf_size2[74]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[340] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[340] when v(mux_1level_tapbuf_size2[74]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[340] trig v(mux_1level_tapbuf_size2[74]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[74]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[74]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[340] param='mux_1level_tapbuf_size2[74]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[74]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[74]_energy_per_cycle param='mux_1level_tapbuf_size2[74]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[340] param='mux_1level_tapbuf_size2[74]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[340] param='dynamic_power_sb_mux[1][1]_rrnode[340]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[340] avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='start_rise_sb_mux[1][1]_rrnode[340]' to='start_rise_sb_mux[1][1]_rrnode[340]+switch_rise_sb_mux[1][1]_rrnode[340]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[340] avg p(Vgvdd_mux_1level_tapbuf_size2[74]) from='start_fall_sb_mux[1][1]_rrnode[340]' to='start_fall_sb_mux[1][1]_rrnode[340]+switch_fall_sb_mux[1][1]_rrnode[340]' -.meas tran sum_leakage_power_mux[0to74] -+ param='sum_leakage_power_mux[0to73]+leakage_sb_mux[1][1]_rrnode[340]' -.meas tran sum_energy_per_cycle_mux[0to74] -+ param='sum_energy_per_cycle_mux[0to73]+energy_per_cycle_sb_mux[1][1]_rrnode[340]' -***** Load for rr_node[340] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=49, type=4 ***** -Xchan_mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[224]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out mux_1level_tapbuf_size2[74]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[74]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to74] -+ param='sum_leakage_power_sb_mux[0to73]+leakage_sb_mux[1][1]_rrnode[340]' -.meas tran sum_energy_per_cycle_sb_mux[0to74] -+ param='sum_energy_per_cycle_sb_mux[0to73]+energy_per_cycle_sb_mux[1][1]_rrnode[340]' -Xmux_1level_tapbuf_size2[75] mux_1level_tapbuf_size2[75]->in[0] mux_1level_tapbuf_size2[75]->in[1] mux_1level_tapbuf_size2[75]->out sram[95]->outb sram[95]->out gvdd_mux_1level_tapbuf_size2[75] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[75], level=1, select_path_id=0. ***** -*****1***** -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -***** Signal mux_1level_tapbuf_size2[75]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[75]->in[0] mux_1level_tapbuf_size2[75]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[75]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[75]->in[1] mux_1level_tapbuf_size2[75]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[75] gvdd_mux_1level_tapbuf_size2[75] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[342] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[342] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[342] when v(mux_1level_tapbuf_size2[75]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[342] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[342] when v(mux_1level_tapbuf_size2[75]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[342] trig v(mux_1level_tapbuf_size2[75]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[75]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[75]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[342] param='mux_1level_tapbuf_size2[75]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[75]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[75]_energy_per_cycle param='mux_1level_tapbuf_size2[75]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[342] param='mux_1level_tapbuf_size2[75]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[342] param='dynamic_power_sb_mux[1][1]_rrnode[342]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[342] avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='start_rise_sb_mux[1][1]_rrnode[342]' to='start_rise_sb_mux[1][1]_rrnode[342]+switch_rise_sb_mux[1][1]_rrnode[342]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[342] avg p(Vgvdd_mux_1level_tapbuf_size2[75]) from='start_fall_sb_mux[1][1]_rrnode[342]' to='start_fall_sb_mux[1][1]_rrnode[342]+switch_fall_sb_mux[1][1]_rrnode[342]' -.meas tran sum_leakage_power_mux[0to75] -+ param='sum_leakage_power_mux[0to74]+leakage_sb_mux[1][1]_rrnode[342]' -.meas tran sum_energy_per_cycle_mux[0to75] -+ param='sum_energy_per_cycle_mux[0to74]+energy_per_cycle_sb_mux[1][1]_rrnode[342]' -***** Load for rr_node[342] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=51, type=4 ***** -Xchan_mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[228]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out mux_1level_tapbuf_size2[75]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[75]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to75] -+ param='sum_leakage_power_sb_mux[0to74]+leakage_sb_mux[1][1]_rrnode[342]' -.meas tran sum_energy_per_cycle_sb_mux[0to75] -+ param='sum_energy_per_cycle_sb_mux[0to74]+energy_per_cycle_sb_mux[1][1]_rrnode[342]' -Xmux_1level_tapbuf_size2[76] mux_1level_tapbuf_size2[76]->in[0] mux_1level_tapbuf_size2[76]->in[1] mux_1level_tapbuf_size2[76]->out sram[96]->outb sram[96]->out gvdd_mux_1level_tapbuf_size2[76] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[76], level=1, select_path_id=0. ***** -*****1***** -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -***** Signal mux_1level_tapbuf_size2[76]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[76]->in[0] mux_1level_tapbuf_size2[76]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[76]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[76]->in[1] mux_1level_tapbuf_size2[76]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[76] gvdd_mux_1level_tapbuf_size2[76] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[344] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[344] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[344] when v(mux_1level_tapbuf_size2[76]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[344] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[344] when v(mux_1level_tapbuf_size2[76]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[344] trig v(mux_1level_tapbuf_size2[76]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[76]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[76]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[344] param='mux_1level_tapbuf_size2[76]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[76]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[76]_energy_per_cycle param='mux_1level_tapbuf_size2[76]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[344] param='mux_1level_tapbuf_size2[76]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[344] param='dynamic_power_sb_mux[1][1]_rrnode[344]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[344] avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='start_rise_sb_mux[1][1]_rrnode[344]' to='start_rise_sb_mux[1][1]_rrnode[344]+switch_rise_sb_mux[1][1]_rrnode[344]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[344] avg p(Vgvdd_mux_1level_tapbuf_size2[76]) from='start_fall_sb_mux[1][1]_rrnode[344]' to='start_fall_sb_mux[1][1]_rrnode[344]+switch_fall_sb_mux[1][1]_rrnode[344]' -.meas tran sum_leakage_power_mux[0to76] -+ param='sum_leakage_power_mux[0to75]+leakage_sb_mux[1][1]_rrnode[344]' -.meas tran sum_energy_per_cycle_mux[0to76] -+ param='sum_energy_per_cycle_mux[0to75]+energy_per_cycle_sb_mux[1][1]_rrnode[344]' -***** Load for rr_node[344] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=53, type=4 ***** -Xchan_mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[231]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out mux_1level_tapbuf_size2[76]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[76]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to76] -+ param='sum_leakage_power_sb_mux[0to75]+leakage_sb_mux[1][1]_rrnode[344]' -.meas tran sum_energy_per_cycle_sb_mux[0to76] -+ param='sum_energy_per_cycle_sb_mux[0to75]+energy_per_cycle_sb_mux[1][1]_rrnode[344]' -Xmux_1level_tapbuf_size2[77] mux_1level_tapbuf_size2[77]->in[0] mux_1level_tapbuf_size2[77]->in[1] mux_1level_tapbuf_size2[77]->out sram[97]->outb sram[97]->out gvdd_mux_1level_tapbuf_size2[77] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[77], level=1, select_path_id=0. ***** -*****1***** -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -***** Signal mux_1level_tapbuf_size2[77]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[77]->in[0] mux_1level_tapbuf_size2[77]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[77]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[77]->in[1] mux_1level_tapbuf_size2[77]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[77] gvdd_mux_1level_tapbuf_size2[77] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[346] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[346] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[346] when v(mux_1level_tapbuf_size2[77]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[346] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[346] when v(mux_1level_tapbuf_size2[77]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[346] trig v(mux_1level_tapbuf_size2[77]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[77]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[77]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[346] param='mux_1level_tapbuf_size2[77]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[77]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[77]_energy_per_cycle param='mux_1level_tapbuf_size2[77]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[346] param='mux_1level_tapbuf_size2[77]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[346] param='dynamic_power_sb_mux[1][1]_rrnode[346]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[346] avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='start_rise_sb_mux[1][1]_rrnode[346]' to='start_rise_sb_mux[1][1]_rrnode[346]+switch_rise_sb_mux[1][1]_rrnode[346]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[346] avg p(Vgvdd_mux_1level_tapbuf_size2[77]) from='start_fall_sb_mux[1][1]_rrnode[346]' to='start_fall_sb_mux[1][1]_rrnode[346]+switch_fall_sb_mux[1][1]_rrnode[346]' -.meas tran sum_leakage_power_mux[0to77] -+ param='sum_leakage_power_mux[0to76]+leakage_sb_mux[1][1]_rrnode[346]' -.meas tran sum_energy_per_cycle_mux[0to77] -+ param='sum_energy_per_cycle_mux[0to76]+energy_per_cycle_sb_mux[1][1]_rrnode[346]' -***** Load for rr_node[346] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=55, type=4 ***** -Xchan_mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[234]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out mux_1level_tapbuf_size2[77]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[77]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to77] -+ param='sum_leakage_power_sb_mux[0to76]+leakage_sb_mux[1][1]_rrnode[346]' -.meas tran sum_energy_per_cycle_sb_mux[0to77] -+ param='sum_energy_per_cycle_sb_mux[0to76]+energy_per_cycle_sb_mux[1][1]_rrnode[346]' -Xmux_1level_tapbuf_size2[78] mux_1level_tapbuf_size2[78]->in[0] mux_1level_tapbuf_size2[78]->in[1] mux_1level_tapbuf_size2[78]->out sram[98]->outb sram[98]->out gvdd_mux_1level_tapbuf_size2[78] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[78], level=1, select_path_id=0. ***** -*****1***** -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -***** Signal mux_1level_tapbuf_size2[78]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[78]->in[0] mux_1level_tapbuf_size2[78]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[78]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[78]->in[1] mux_1level_tapbuf_size2[78]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[78] gvdd_mux_1level_tapbuf_size2[78] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[348] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[348] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[348] when v(mux_1level_tapbuf_size2[78]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[348] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[348] when v(mux_1level_tapbuf_size2[78]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[348] trig v(mux_1level_tapbuf_size2[78]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[78]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[78]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[348] param='mux_1level_tapbuf_size2[78]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[78]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[78]_energy_per_cycle param='mux_1level_tapbuf_size2[78]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[348] param='mux_1level_tapbuf_size2[78]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[348] param='dynamic_power_sb_mux[1][1]_rrnode[348]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[348] avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='start_rise_sb_mux[1][1]_rrnode[348]' to='start_rise_sb_mux[1][1]_rrnode[348]+switch_rise_sb_mux[1][1]_rrnode[348]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[348] avg p(Vgvdd_mux_1level_tapbuf_size2[78]) from='start_fall_sb_mux[1][1]_rrnode[348]' to='start_fall_sb_mux[1][1]_rrnode[348]+switch_fall_sb_mux[1][1]_rrnode[348]' -.meas tran sum_leakage_power_mux[0to78] -+ param='sum_leakage_power_mux[0to77]+leakage_sb_mux[1][1]_rrnode[348]' -.meas tran sum_energy_per_cycle_mux[0to78] -+ param='sum_energy_per_cycle_mux[0to77]+energy_per_cycle_sb_mux[1][1]_rrnode[348]' -***** Load for rr_node[348] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=57, type=4 ***** -Xchan_mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[239]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out mux_1level_tapbuf_size2[78]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[240]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[78]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to78] -+ param='sum_leakage_power_sb_mux[0to77]+leakage_sb_mux[1][1]_rrnode[348]' -.meas tran sum_energy_per_cycle_sb_mux[0to78] -+ param='sum_energy_per_cycle_sb_mux[0to77]+energy_per_cycle_sb_mux[1][1]_rrnode[348]' -Xmux_1level_tapbuf_size2[79] mux_1level_tapbuf_size2[79]->in[0] mux_1level_tapbuf_size2[79]->in[1] mux_1level_tapbuf_size2[79]->out sram[99]->outb sram[99]->out gvdd_mux_1level_tapbuf_size2[79] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[79], level=1, select_path_id=0. ***** -*****1***** -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -***** Signal mux_1level_tapbuf_size2[79]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[79]->in[0] mux_1level_tapbuf_size2[79]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[79]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[79]->in[1] mux_1level_tapbuf_size2[79]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[79] gvdd_mux_1level_tapbuf_size2[79] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[350] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[350] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[350] when v(mux_1level_tapbuf_size2[79]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[350] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[350] when v(mux_1level_tapbuf_size2[79]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[350] trig v(mux_1level_tapbuf_size2[79]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[79]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[79]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[350] param='mux_1level_tapbuf_size2[79]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[79]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[79]_energy_per_cycle param='mux_1level_tapbuf_size2[79]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[350] param='mux_1level_tapbuf_size2[79]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[350] param='dynamic_power_sb_mux[1][1]_rrnode[350]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[350] avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='start_rise_sb_mux[1][1]_rrnode[350]' to='start_rise_sb_mux[1][1]_rrnode[350]+switch_rise_sb_mux[1][1]_rrnode[350]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[350] avg p(Vgvdd_mux_1level_tapbuf_size2[79]) from='start_fall_sb_mux[1][1]_rrnode[350]' to='start_fall_sb_mux[1][1]_rrnode[350]+switch_fall_sb_mux[1][1]_rrnode[350]' -.meas tran sum_leakage_power_mux[0to79] -+ param='sum_leakage_power_mux[0to78]+leakage_sb_mux[1][1]_rrnode[350]' -.meas tran sum_energy_per_cycle_mux[0to79] -+ param='sum_energy_per_cycle_mux[0to78]+energy_per_cycle_sb_mux[1][1]_rrnode[350]' -***** Load for rr_node[350] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=59, type=4 ***** -Xchan_mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[242]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out mux_1level_tapbuf_size2[79]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[79]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to79] -+ param='sum_leakage_power_sb_mux[0to78]+leakage_sb_mux[1][1]_rrnode[350]' -.meas tran sum_energy_per_cycle_sb_mux[0to79] -+ param='sum_energy_per_cycle_sb_mux[0to78]+energy_per_cycle_sb_mux[1][1]_rrnode[350]' -Xmux_1level_tapbuf_size2[80] mux_1level_tapbuf_size2[80]->in[0] mux_1level_tapbuf_size2[80]->in[1] mux_1level_tapbuf_size2[80]->out sram[100]->outb sram[100]->out gvdd_mux_1level_tapbuf_size2[80] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[80], level=1, select_path_id=0. ***** -*****1***** -Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[100]->out) 0 -.nodeset V(sram[100]->outb) vsp -***** Signal mux_1level_tapbuf_size2[80]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[80]->in[0] mux_1level_tapbuf_size2[80]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[80]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[80]->in[1] mux_1level_tapbuf_size2[80]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[80] gvdd_mux_1level_tapbuf_size2[80] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[352] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[352] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[352] when v(mux_1level_tapbuf_size2[80]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[352] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[352] when v(mux_1level_tapbuf_size2[80]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[352] trig v(mux_1level_tapbuf_size2[80]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[80]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[80]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[352] param='mux_1level_tapbuf_size2[80]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[80]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[80]_energy_per_cycle param='mux_1level_tapbuf_size2[80]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[352] param='mux_1level_tapbuf_size2[80]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[352] param='dynamic_power_sb_mux[1][1]_rrnode[352]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[352] avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='start_rise_sb_mux[1][1]_rrnode[352]' to='start_rise_sb_mux[1][1]_rrnode[352]+switch_rise_sb_mux[1][1]_rrnode[352]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[352] avg p(Vgvdd_mux_1level_tapbuf_size2[80]) from='start_fall_sb_mux[1][1]_rrnode[352]' to='start_fall_sb_mux[1][1]_rrnode[352]+switch_fall_sb_mux[1][1]_rrnode[352]' -.meas tran sum_leakage_power_mux[0to80] -+ param='sum_leakage_power_mux[0to79]+leakage_sb_mux[1][1]_rrnode[352]' -.meas tran sum_energy_per_cycle_mux[0to80] -+ param='sum_energy_per_cycle_mux[0to79]+energy_per_cycle_sb_mux[1][1]_rrnode[352]' -***** Load for rr_node[352] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=61, type=4 ***** -Xchan_mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[246]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out mux_1level_tapbuf_size2[80]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[80]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to80] -+ param='sum_leakage_power_sb_mux[0to79]+leakage_sb_mux[1][1]_rrnode[352]' -.meas tran sum_energy_per_cycle_sb_mux[0to80] -+ param='sum_energy_per_cycle_sb_mux[0to79]+energy_per_cycle_sb_mux[1][1]_rrnode[352]' -Xmux_1level_tapbuf_size2[81] mux_1level_tapbuf_size2[81]->in[0] mux_1level_tapbuf_size2[81]->in[1] mux_1level_tapbuf_size2[81]->out sram[101]->outb sram[101]->out gvdd_mux_1level_tapbuf_size2[81] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[81], level=1, select_path_id=0. ***** -*****1***** -Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[101]->out) 0 -.nodeset V(sram[101]->outb) vsp -***** Signal mux_1level_tapbuf_size2[81]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[81]->in[0] mux_1level_tapbuf_size2[81]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[81]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[81]->in[1] mux_1level_tapbuf_size2[81]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[81] gvdd_mux_1level_tapbuf_size2[81] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[354] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[354] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[354] when v(mux_1level_tapbuf_size2[81]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[354] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[354] when v(mux_1level_tapbuf_size2[81]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[354] trig v(mux_1level_tapbuf_size2[81]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[81]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[81]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[354] param='mux_1level_tapbuf_size2[81]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[81]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[81]_energy_per_cycle param='mux_1level_tapbuf_size2[81]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[354] param='mux_1level_tapbuf_size2[81]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[354] param='dynamic_power_sb_mux[1][1]_rrnode[354]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[354] avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='start_rise_sb_mux[1][1]_rrnode[354]' to='start_rise_sb_mux[1][1]_rrnode[354]+switch_rise_sb_mux[1][1]_rrnode[354]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[354] avg p(Vgvdd_mux_1level_tapbuf_size2[81]) from='start_fall_sb_mux[1][1]_rrnode[354]' to='start_fall_sb_mux[1][1]_rrnode[354]+switch_fall_sb_mux[1][1]_rrnode[354]' -.meas tran sum_leakage_power_mux[0to81] -+ param='sum_leakage_power_mux[0to80]+leakage_sb_mux[1][1]_rrnode[354]' -.meas tran sum_energy_per_cycle_mux[0to81] -+ param='sum_energy_per_cycle_mux[0to80]+energy_per_cycle_sb_mux[1][1]_rrnode[354]' -***** Load for rr_node[354] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=63, type=4 ***** -Xchan_mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[250]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out mux_1level_tapbuf_size2[81]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[81]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to81] -+ param='sum_leakage_power_sb_mux[0to80]+leakage_sb_mux[1][1]_rrnode[354]' -.meas tran sum_energy_per_cycle_sb_mux[0to81] -+ param='sum_energy_per_cycle_sb_mux[0to80]+energy_per_cycle_sb_mux[1][1]_rrnode[354]' -Xmux_1level_tapbuf_size2[82] mux_1level_tapbuf_size2[82]->in[0] mux_1level_tapbuf_size2[82]->in[1] mux_1level_tapbuf_size2[82]->out sram[102]->outb sram[102]->out gvdd_mux_1level_tapbuf_size2[82] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[82], level=1, select_path_id=0. ***** -*****1***** -Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[102]->out) 0 -.nodeset V(sram[102]->outb) vsp -***** Signal mux_1level_tapbuf_size2[82]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[82]->in[0] mux_1level_tapbuf_size2[82]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[82]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[82]->in[1] mux_1level_tapbuf_size2[82]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[82] gvdd_mux_1level_tapbuf_size2[82] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[356] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[356] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[356] when v(mux_1level_tapbuf_size2[82]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[356] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[356] when v(mux_1level_tapbuf_size2[82]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[356] trig v(mux_1level_tapbuf_size2[82]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[82]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[82]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[356] param='mux_1level_tapbuf_size2[82]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[82]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[82]_energy_per_cycle param='mux_1level_tapbuf_size2[82]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[356] param='mux_1level_tapbuf_size2[82]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[356] param='dynamic_power_sb_mux[1][1]_rrnode[356]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[356] avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='start_rise_sb_mux[1][1]_rrnode[356]' to='start_rise_sb_mux[1][1]_rrnode[356]+switch_rise_sb_mux[1][1]_rrnode[356]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[356] avg p(Vgvdd_mux_1level_tapbuf_size2[82]) from='start_fall_sb_mux[1][1]_rrnode[356]' to='start_fall_sb_mux[1][1]_rrnode[356]+switch_fall_sb_mux[1][1]_rrnode[356]' -.meas tran sum_leakage_power_mux[0to82] -+ param='sum_leakage_power_mux[0to81]+leakage_sb_mux[1][1]_rrnode[356]' -.meas tran sum_energy_per_cycle_mux[0to82] -+ param='sum_energy_per_cycle_mux[0to81]+energy_per_cycle_sb_mux[1][1]_rrnode[356]' -***** Load for rr_node[356] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=65, type=4 ***** -Xchan_mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[255]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out mux_1level_tapbuf_size2[82]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[82]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to82] -+ param='sum_leakage_power_sb_mux[0to81]+leakage_sb_mux[1][1]_rrnode[356]' -.meas tran sum_energy_per_cycle_sb_mux[0to82] -+ param='sum_energy_per_cycle_sb_mux[0to81]+energy_per_cycle_sb_mux[1][1]_rrnode[356]' -Xmux_1level_tapbuf_size2[83] mux_1level_tapbuf_size2[83]->in[0] mux_1level_tapbuf_size2[83]->in[1] mux_1level_tapbuf_size2[83]->out sram[103]->outb sram[103]->out gvdd_mux_1level_tapbuf_size2[83] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[83], level=1, select_path_id=0. ***** -*****1***** -Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[103]->out) 0 -.nodeset V(sram[103]->outb) vsp -***** Signal mux_1level_tapbuf_size2[83]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[83]->in[0] mux_1level_tapbuf_size2[83]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[83]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[83]->in[1] mux_1level_tapbuf_size2[83]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[83] gvdd_mux_1level_tapbuf_size2[83] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[358] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[358] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[358] when v(mux_1level_tapbuf_size2[83]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[358] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[358] when v(mux_1level_tapbuf_size2[83]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[358] trig v(mux_1level_tapbuf_size2[83]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[83]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[83]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[358] param='mux_1level_tapbuf_size2[83]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[83]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[83]_energy_per_cycle param='mux_1level_tapbuf_size2[83]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[358] param='mux_1level_tapbuf_size2[83]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[358] param='dynamic_power_sb_mux[1][1]_rrnode[358]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[358] avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='start_rise_sb_mux[1][1]_rrnode[358]' to='start_rise_sb_mux[1][1]_rrnode[358]+switch_rise_sb_mux[1][1]_rrnode[358]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[358] avg p(Vgvdd_mux_1level_tapbuf_size2[83]) from='start_fall_sb_mux[1][1]_rrnode[358]' to='start_fall_sb_mux[1][1]_rrnode[358]+switch_fall_sb_mux[1][1]_rrnode[358]' -.meas tran sum_leakage_power_mux[0to83] -+ param='sum_leakage_power_mux[0to82]+leakage_sb_mux[1][1]_rrnode[358]' -.meas tran sum_energy_per_cycle_mux[0to83] -+ param='sum_energy_per_cycle_mux[0to82]+energy_per_cycle_sb_mux[1][1]_rrnode[358]' -***** Load for rr_node[358] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=67, type=4 ***** -Xchan_mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[260]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out mux_1level_tapbuf_size2[83]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[83]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to83] -+ param='sum_leakage_power_sb_mux[0to82]+leakage_sb_mux[1][1]_rrnode[358]' -.meas tran sum_energy_per_cycle_sb_mux[0to83] -+ param='sum_energy_per_cycle_sb_mux[0to82]+energy_per_cycle_sb_mux[1][1]_rrnode[358]' -Xmux_1level_tapbuf_size2[84] mux_1level_tapbuf_size2[84]->in[0] mux_1level_tapbuf_size2[84]->in[1] mux_1level_tapbuf_size2[84]->out sram[104]->outb sram[104]->out gvdd_mux_1level_tapbuf_size2[84] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[84], level=1, select_path_id=0. ***** -*****1***** -Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[104]->out) 0 -.nodeset V(sram[104]->outb) vsp -***** Signal mux_1level_tapbuf_size2[84]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[84]->in[0] mux_1level_tapbuf_size2[84]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[84]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[84]->in[1] mux_1level_tapbuf_size2[84]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[84] gvdd_mux_1level_tapbuf_size2[84] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[360] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[360] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[360] when v(mux_1level_tapbuf_size2[84]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[360] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[360] when v(mux_1level_tapbuf_size2[84]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[360] trig v(mux_1level_tapbuf_size2[84]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[84]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[84]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[360] param='mux_1level_tapbuf_size2[84]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[84]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[84]_energy_per_cycle param='mux_1level_tapbuf_size2[84]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[360] param='mux_1level_tapbuf_size2[84]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[360] param='dynamic_power_sb_mux[1][1]_rrnode[360]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[360] avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='start_rise_sb_mux[1][1]_rrnode[360]' to='start_rise_sb_mux[1][1]_rrnode[360]+switch_rise_sb_mux[1][1]_rrnode[360]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[360] avg p(Vgvdd_mux_1level_tapbuf_size2[84]) from='start_fall_sb_mux[1][1]_rrnode[360]' to='start_fall_sb_mux[1][1]_rrnode[360]+switch_fall_sb_mux[1][1]_rrnode[360]' -.meas tran sum_leakage_power_mux[0to84] -+ param='sum_leakage_power_mux[0to83]+leakage_sb_mux[1][1]_rrnode[360]' -.meas tran sum_energy_per_cycle_mux[0to84] -+ param='sum_energy_per_cycle_mux[0to83]+energy_per_cycle_sb_mux[1][1]_rrnode[360]' -***** Load for rr_node[360] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=69, type=4 ***** -Xchan_mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[263]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out mux_1level_tapbuf_size2[84]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[84]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to84] -+ param='sum_leakage_power_sb_mux[0to83]+leakage_sb_mux[1][1]_rrnode[360]' -.meas tran sum_energy_per_cycle_sb_mux[0to84] -+ param='sum_energy_per_cycle_sb_mux[0to83]+energy_per_cycle_sb_mux[1][1]_rrnode[360]' -Xmux_1level_tapbuf_size2[85] mux_1level_tapbuf_size2[85]->in[0] mux_1level_tapbuf_size2[85]->in[1] mux_1level_tapbuf_size2[85]->out sram[105]->outb sram[105]->out gvdd_mux_1level_tapbuf_size2[85] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[85], level=1, select_path_id=0. ***** -*****1***** -Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[105]->out) 0 -.nodeset V(sram[105]->outb) vsp -***** Signal mux_1level_tapbuf_size2[85]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[85]->in[0] mux_1level_tapbuf_size2[85]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[85]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[85]->in[1] mux_1level_tapbuf_size2[85]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[85] gvdd_mux_1level_tapbuf_size2[85] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[362] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[362] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[362] when v(mux_1level_tapbuf_size2[85]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[362] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[362] when v(mux_1level_tapbuf_size2[85]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[362] trig v(mux_1level_tapbuf_size2[85]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[85]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[85]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[362] param='mux_1level_tapbuf_size2[85]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[85]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[85]_energy_per_cycle param='mux_1level_tapbuf_size2[85]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[362] param='mux_1level_tapbuf_size2[85]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[362] param='dynamic_power_sb_mux[1][1]_rrnode[362]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[362] avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='start_rise_sb_mux[1][1]_rrnode[362]' to='start_rise_sb_mux[1][1]_rrnode[362]+switch_rise_sb_mux[1][1]_rrnode[362]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[362] avg p(Vgvdd_mux_1level_tapbuf_size2[85]) from='start_fall_sb_mux[1][1]_rrnode[362]' to='start_fall_sb_mux[1][1]_rrnode[362]+switch_fall_sb_mux[1][1]_rrnode[362]' -.meas tran sum_leakage_power_mux[0to85] -+ param='sum_leakage_power_mux[0to84]+leakage_sb_mux[1][1]_rrnode[362]' -.meas tran sum_energy_per_cycle_mux[0to85] -+ param='sum_energy_per_cycle_mux[0to84]+energy_per_cycle_sb_mux[1][1]_rrnode[362]' -***** Load for rr_node[362] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=71, type=4 ***** -Xchan_mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[266]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out mux_1level_tapbuf_size2[85]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[85]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to85] -+ param='sum_leakage_power_sb_mux[0to84]+leakage_sb_mux[1][1]_rrnode[362]' -.meas tran sum_energy_per_cycle_sb_mux[0to85] -+ param='sum_energy_per_cycle_sb_mux[0to84]+energy_per_cycle_sb_mux[1][1]_rrnode[362]' -Xmux_1level_tapbuf_size2[86] mux_1level_tapbuf_size2[86]->in[0] mux_1level_tapbuf_size2[86]->in[1] mux_1level_tapbuf_size2[86]->out sram[106]->outb sram[106]->out gvdd_mux_1level_tapbuf_size2[86] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[86], level=1, select_path_id=0. ***** -*****1***** -Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[106]->out) 0 -.nodeset V(sram[106]->outb) vsp -***** Signal mux_1level_tapbuf_size2[86]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[86]->in[0] mux_1level_tapbuf_size2[86]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[86]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[86]->in[1] mux_1level_tapbuf_size2[86]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[86] gvdd_mux_1level_tapbuf_size2[86] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[364] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[364] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[364] when v(mux_1level_tapbuf_size2[86]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[364] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[364] when v(mux_1level_tapbuf_size2[86]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[364] trig v(mux_1level_tapbuf_size2[86]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[86]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[86]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[364] param='mux_1level_tapbuf_size2[86]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[86]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[86]_energy_per_cycle param='mux_1level_tapbuf_size2[86]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[364] param='mux_1level_tapbuf_size2[86]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[364] param='dynamic_power_sb_mux[1][1]_rrnode[364]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[364] avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='start_rise_sb_mux[1][1]_rrnode[364]' to='start_rise_sb_mux[1][1]_rrnode[364]+switch_rise_sb_mux[1][1]_rrnode[364]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[364] avg p(Vgvdd_mux_1level_tapbuf_size2[86]) from='start_fall_sb_mux[1][1]_rrnode[364]' to='start_fall_sb_mux[1][1]_rrnode[364]+switch_fall_sb_mux[1][1]_rrnode[364]' -.meas tran sum_leakage_power_mux[0to86] -+ param='sum_leakage_power_mux[0to85]+leakage_sb_mux[1][1]_rrnode[364]' -.meas tran sum_energy_per_cycle_mux[0to86] -+ param='sum_energy_per_cycle_mux[0to85]+energy_per_cycle_sb_mux[1][1]_rrnode[364]' -***** Load for rr_node[364] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=73, type=4 ***** -Xchan_mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[270]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out mux_1level_tapbuf_size2[86]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[86]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to86] -+ param='sum_leakage_power_sb_mux[0to85]+leakage_sb_mux[1][1]_rrnode[364]' -.meas tran sum_energy_per_cycle_sb_mux[0to86] -+ param='sum_energy_per_cycle_sb_mux[0to85]+energy_per_cycle_sb_mux[1][1]_rrnode[364]' -Xmux_1level_tapbuf_size2[87] mux_1level_tapbuf_size2[87]->in[0] mux_1level_tapbuf_size2[87]->in[1] mux_1level_tapbuf_size2[87]->out sram[107]->outb sram[107]->out gvdd_mux_1level_tapbuf_size2[87] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[87], level=1, select_path_id=0. ***** -*****1***** -Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[107]->out) 0 -.nodeset V(sram[107]->outb) vsp -***** Signal mux_1level_tapbuf_size2[87]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[87]->in[0] mux_1level_tapbuf_size2[87]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[87]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[87]->in[1] mux_1level_tapbuf_size2[87]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[87] gvdd_mux_1level_tapbuf_size2[87] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[366] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[366] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[366] when v(mux_1level_tapbuf_size2[87]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[366] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[366] when v(mux_1level_tapbuf_size2[87]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[366] trig v(mux_1level_tapbuf_size2[87]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[87]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[87]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[366] param='mux_1level_tapbuf_size2[87]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[87]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[87]_energy_per_cycle param='mux_1level_tapbuf_size2[87]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[366] param='mux_1level_tapbuf_size2[87]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[366] param='dynamic_power_sb_mux[1][1]_rrnode[366]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[366] avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='start_rise_sb_mux[1][1]_rrnode[366]' to='start_rise_sb_mux[1][1]_rrnode[366]+switch_rise_sb_mux[1][1]_rrnode[366]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[366] avg p(Vgvdd_mux_1level_tapbuf_size2[87]) from='start_fall_sb_mux[1][1]_rrnode[366]' to='start_fall_sb_mux[1][1]_rrnode[366]+switch_fall_sb_mux[1][1]_rrnode[366]' -.meas tran sum_leakage_power_mux[0to87] -+ param='sum_leakage_power_mux[0to86]+leakage_sb_mux[1][1]_rrnode[366]' -.meas tran sum_energy_per_cycle_mux[0to87] -+ param='sum_energy_per_cycle_mux[0to86]+energy_per_cycle_sb_mux[1][1]_rrnode[366]' -***** Load for rr_node[366] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=75, type=4 ***** -Xchan_mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[274]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out mux_1level_tapbuf_size2[87]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[87]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to87] -+ param='sum_leakage_power_sb_mux[0to86]+leakage_sb_mux[1][1]_rrnode[366]' -.meas tran sum_energy_per_cycle_sb_mux[0to87] -+ param='sum_energy_per_cycle_sb_mux[0to86]+energy_per_cycle_sb_mux[1][1]_rrnode[366]' -Xmux_1level_tapbuf_size2[88] mux_1level_tapbuf_size2[88]->in[0] mux_1level_tapbuf_size2[88]->in[1] mux_1level_tapbuf_size2[88]->out sram[108]->outb sram[108]->out gvdd_mux_1level_tapbuf_size2[88] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[88], level=1, select_path_id=0. ***** -*****1***** -Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[108]->out) 0 -.nodeset V(sram[108]->outb) vsp -***** Signal mux_1level_tapbuf_size2[88]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[88]->in[0] mux_1level_tapbuf_size2[88]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[88]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[88]->in[1] mux_1level_tapbuf_size2[88]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[88] gvdd_mux_1level_tapbuf_size2[88] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[368] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[368] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[368] when v(mux_1level_tapbuf_size2[88]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[368] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[368] when v(mux_1level_tapbuf_size2[88]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[368] trig v(mux_1level_tapbuf_size2[88]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[88]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[88]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[368] param='mux_1level_tapbuf_size2[88]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[88]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[88]_energy_per_cycle param='mux_1level_tapbuf_size2[88]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[368] param='mux_1level_tapbuf_size2[88]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[368] param='dynamic_power_sb_mux[1][1]_rrnode[368]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[368] avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='start_rise_sb_mux[1][1]_rrnode[368]' to='start_rise_sb_mux[1][1]_rrnode[368]+switch_rise_sb_mux[1][1]_rrnode[368]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[368] avg p(Vgvdd_mux_1level_tapbuf_size2[88]) from='start_fall_sb_mux[1][1]_rrnode[368]' to='start_fall_sb_mux[1][1]_rrnode[368]+switch_fall_sb_mux[1][1]_rrnode[368]' -.meas tran sum_leakage_power_mux[0to88] -+ param='sum_leakage_power_mux[0to87]+leakage_sb_mux[1][1]_rrnode[368]' -.meas tran sum_energy_per_cycle_mux[0to88] -+ param='sum_energy_per_cycle_mux[0to87]+energy_per_cycle_sb_mux[1][1]_rrnode[368]' -***** Load for rr_node[368] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=77, type=4 ***** -Xchan_mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[278]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out mux_1level_tapbuf_size2[88]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[88]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to88] -+ param='sum_leakage_power_sb_mux[0to87]+leakage_sb_mux[1][1]_rrnode[368]' -.meas tran sum_energy_per_cycle_sb_mux[0to88] -+ param='sum_energy_per_cycle_sb_mux[0to87]+energy_per_cycle_sb_mux[1][1]_rrnode[368]' -Xmux_1level_tapbuf_size2[89] mux_1level_tapbuf_size2[89]->in[0] mux_1level_tapbuf_size2[89]->in[1] mux_1level_tapbuf_size2[89]->out sram[109]->outb sram[109]->out gvdd_mux_1level_tapbuf_size2[89] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[89], level=1, select_path_id=0. ***** -*****1***** -Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[109]->out) 0 -.nodeset V(sram[109]->outb) vsp -***** Signal mux_1level_tapbuf_size2[89]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[89]->in[0] mux_1level_tapbuf_size2[89]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[89]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[89]->in[1] mux_1level_tapbuf_size2[89]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[89] gvdd_mux_1level_tapbuf_size2[89] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[370] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[370] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[370] when v(mux_1level_tapbuf_size2[89]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[370] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[370] when v(mux_1level_tapbuf_size2[89]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[370] trig v(mux_1level_tapbuf_size2[89]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[89]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[89]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[370] param='mux_1level_tapbuf_size2[89]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[89]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[89]_energy_per_cycle param='mux_1level_tapbuf_size2[89]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[370] param='mux_1level_tapbuf_size2[89]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[370] param='dynamic_power_sb_mux[1][1]_rrnode[370]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[370] avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='start_rise_sb_mux[1][1]_rrnode[370]' to='start_rise_sb_mux[1][1]_rrnode[370]+switch_rise_sb_mux[1][1]_rrnode[370]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[370] avg p(Vgvdd_mux_1level_tapbuf_size2[89]) from='start_fall_sb_mux[1][1]_rrnode[370]' to='start_fall_sb_mux[1][1]_rrnode[370]+switch_fall_sb_mux[1][1]_rrnode[370]' -.meas tran sum_leakage_power_mux[0to89] -+ param='sum_leakage_power_mux[0to88]+leakage_sb_mux[1][1]_rrnode[370]' -.meas tran sum_energy_per_cycle_mux[0to89] -+ param='sum_energy_per_cycle_mux[0to88]+energy_per_cycle_sb_mux[1][1]_rrnode[370]' -***** Load for rr_node[370] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=79, type=4 ***** -Xchan_mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[282]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out mux_1level_tapbuf_size2[89]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[89]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to89] -+ param='sum_leakage_power_sb_mux[0to88]+leakage_sb_mux[1][1]_rrnode[370]' -.meas tran sum_energy_per_cycle_sb_mux[0to89] -+ param='sum_energy_per_cycle_sb_mux[0to88]+energy_per_cycle_sb_mux[1][1]_rrnode[370]' -Xmux_1level_tapbuf_size2[90] mux_1level_tapbuf_size2[90]->in[0] mux_1level_tapbuf_size2[90]->in[1] mux_1level_tapbuf_size2[90]->out sram[110]->outb sram[110]->out gvdd_mux_1level_tapbuf_size2[90] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[90], level=1, select_path_id=0. ***** -*****1***** -Xsram[110] sram->in sram[110]->out sram[110]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[110]->out) 0 -.nodeset V(sram[110]->outb) vsp -***** Signal mux_1level_tapbuf_size2[90]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[90]->in[0] mux_1level_tapbuf_size2[90]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[90]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[90]->in[1] mux_1level_tapbuf_size2[90]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[90] gvdd_mux_1level_tapbuf_size2[90] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[372] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[372] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[372] when v(mux_1level_tapbuf_size2[90]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[372] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[372] when v(mux_1level_tapbuf_size2[90]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[372] trig v(mux_1level_tapbuf_size2[90]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[90]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[90]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[372] param='mux_1level_tapbuf_size2[90]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[90]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[90]_energy_per_cycle param='mux_1level_tapbuf_size2[90]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[372] param='mux_1level_tapbuf_size2[90]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[372] param='dynamic_power_sb_mux[1][1]_rrnode[372]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[372] avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='start_rise_sb_mux[1][1]_rrnode[372]' to='start_rise_sb_mux[1][1]_rrnode[372]+switch_rise_sb_mux[1][1]_rrnode[372]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[372] avg p(Vgvdd_mux_1level_tapbuf_size2[90]) from='start_fall_sb_mux[1][1]_rrnode[372]' to='start_fall_sb_mux[1][1]_rrnode[372]+switch_fall_sb_mux[1][1]_rrnode[372]' -.meas tran sum_leakage_power_mux[0to90] -+ param='sum_leakage_power_mux[0to89]+leakage_sb_mux[1][1]_rrnode[372]' -.meas tran sum_energy_per_cycle_mux[0to90] -+ param='sum_energy_per_cycle_mux[0to89]+energy_per_cycle_sb_mux[1][1]_rrnode[372]' -***** Load for rr_node[372] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=81, type=4 ***** -Xchan_mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[285]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out mux_1level_tapbuf_size2[90]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[90]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to90] -+ param='sum_leakage_power_sb_mux[0to89]+leakage_sb_mux[1][1]_rrnode[372]' -.meas tran sum_energy_per_cycle_sb_mux[0to90] -+ param='sum_energy_per_cycle_sb_mux[0to89]+energy_per_cycle_sb_mux[1][1]_rrnode[372]' -Xmux_1level_tapbuf_size2[91] mux_1level_tapbuf_size2[91]->in[0] mux_1level_tapbuf_size2[91]->in[1] mux_1level_tapbuf_size2[91]->out sram[111]->outb sram[111]->out gvdd_mux_1level_tapbuf_size2[91] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[91], level=1, select_path_id=0. ***** -*****1***** -Xsram[111] sram->in sram[111]->out sram[111]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[111]->out) 0 -.nodeset V(sram[111]->outb) vsp -***** Signal mux_1level_tapbuf_size2[91]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[91]->in[0] mux_1level_tapbuf_size2[91]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[91]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[91]->in[1] mux_1level_tapbuf_size2[91]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[91] gvdd_mux_1level_tapbuf_size2[91] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[374] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[374] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[374] when v(mux_1level_tapbuf_size2[91]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[374] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[374] when v(mux_1level_tapbuf_size2[91]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[374] trig v(mux_1level_tapbuf_size2[91]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[91]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[91]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[374] param='mux_1level_tapbuf_size2[91]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[91]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[91]_energy_per_cycle param='mux_1level_tapbuf_size2[91]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[374] param='mux_1level_tapbuf_size2[91]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[374] param='dynamic_power_sb_mux[1][1]_rrnode[374]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[374] avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='start_rise_sb_mux[1][1]_rrnode[374]' to='start_rise_sb_mux[1][1]_rrnode[374]+switch_rise_sb_mux[1][1]_rrnode[374]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[374] avg p(Vgvdd_mux_1level_tapbuf_size2[91]) from='start_fall_sb_mux[1][1]_rrnode[374]' to='start_fall_sb_mux[1][1]_rrnode[374]+switch_fall_sb_mux[1][1]_rrnode[374]' -.meas tran sum_leakage_power_mux[0to91] -+ param='sum_leakage_power_mux[0to90]+leakage_sb_mux[1][1]_rrnode[374]' -.meas tran sum_energy_per_cycle_mux[0to91] -+ param='sum_energy_per_cycle_mux[0to90]+energy_per_cycle_sb_mux[1][1]_rrnode[374]' -***** Load for rr_node[374] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=83, type=4 ***** -Xchan_mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[289]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out mux_1level_tapbuf_size2[91]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[91]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to91] -+ param='sum_leakage_power_sb_mux[0to90]+leakage_sb_mux[1][1]_rrnode[374]' -.meas tran sum_energy_per_cycle_sb_mux[0to91] -+ param='sum_energy_per_cycle_sb_mux[0to90]+energy_per_cycle_sb_mux[1][1]_rrnode[374]' -Xmux_1level_tapbuf_size2[92] mux_1level_tapbuf_size2[92]->in[0] mux_1level_tapbuf_size2[92]->in[1] mux_1level_tapbuf_size2[92]->out sram[112]->outb sram[112]->out gvdd_mux_1level_tapbuf_size2[92] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[92], level=1, select_path_id=0. ***** -*****1***** -Xsram[112] sram->in sram[112]->out sram[112]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[112]->out) 0 -.nodeset V(sram[112]->outb) vsp -***** Signal mux_1level_tapbuf_size2[92]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[92]->in[0] mux_1level_tapbuf_size2[92]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[92]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[92]->in[1] mux_1level_tapbuf_size2[92]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[92] gvdd_mux_1level_tapbuf_size2[92] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[376] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[376] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[376] when v(mux_1level_tapbuf_size2[92]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[376] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[376] when v(mux_1level_tapbuf_size2[92]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[376] trig v(mux_1level_tapbuf_size2[92]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[92]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[92]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[376] param='mux_1level_tapbuf_size2[92]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[92]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[92]_energy_per_cycle param='mux_1level_tapbuf_size2[92]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[376] param='mux_1level_tapbuf_size2[92]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[376] param='dynamic_power_sb_mux[1][1]_rrnode[376]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[376] avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='start_rise_sb_mux[1][1]_rrnode[376]' to='start_rise_sb_mux[1][1]_rrnode[376]+switch_rise_sb_mux[1][1]_rrnode[376]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[376] avg p(Vgvdd_mux_1level_tapbuf_size2[92]) from='start_fall_sb_mux[1][1]_rrnode[376]' to='start_fall_sb_mux[1][1]_rrnode[376]+switch_fall_sb_mux[1][1]_rrnode[376]' -.meas tran sum_leakage_power_mux[0to92] -+ param='sum_leakage_power_mux[0to91]+leakage_sb_mux[1][1]_rrnode[376]' -.meas tran sum_energy_per_cycle_mux[0to92] -+ param='sum_energy_per_cycle_mux[0to91]+energy_per_cycle_sb_mux[1][1]_rrnode[376]' -***** Load for rr_node[376] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=85, type=4 ***** -Xchan_mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[294]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out mux_1level_tapbuf_size2[92]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[92]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to92] -+ param='sum_leakage_power_sb_mux[0to91]+leakage_sb_mux[1][1]_rrnode[376]' -.meas tran sum_energy_per_cycle_sb_mux[0to92] -+ param='sum_energy_per_cycle_sb_mux[0to91]+energy_per_cycle_sb_mux[1][1]_rrnode[376]' -Xmux_1level_tapbuf_size2[93] mux_1level_tapbuf_size2[93]->in[0] mux_1level_tapbuf_size2[93]->in[1] mux_1level_tapbuf_size2[93]->out sram[113]->outb sram[113]->out gvdd_mux_1level_tapbuf_size2[93] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[93], level=1, select_path_id=0. ***** -*****1***** -Xsram[113] sram->in sram[113]->out sram[113]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[113]->out) 0 -.nodeset V(sram[113]->outb) vsp -***** Signal mux_1level_tapbuf_size2[93]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[93]->in[0] mux_1level_tapbuf_size2[93]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[93]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[93]->in[1] mux_1level_tapbuf_size2[93]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[93] gvdd_mux_1level_tapbuf_size2[93] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[378] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[378] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[378] when v(mux_1level_tapbuf_size2[93]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[378] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[378] when v(mux_1level_tapbuf_size2[93]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[378] trig v(mux_1level_tapbuf_size2[93]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[93]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[93]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[378] param='mux_1level_tapbuf_size2[93]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[93]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[93]_energy_per_cycle param='mux_1level_tapbuf_size2[93]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[378] param='mux_1level_tapbuf_size2[93]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[378] param='dynamic_power_sb_mux[1][1]_rrnode[378]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[378] avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='start_rise_sb_mux[1][1]_rrnode[378]' to='start_rise_sb_mux[1][1]_rrnode[378]+switch_rise_sb_mux[1][1]_rrnode[378]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[378] avg p(Vgvdd_mux_1level_tapbuf_size2[93]) from='start_fall_sb_mux[1][1]_rrnode[378]' to='start_fall_sb_mux[1][1]_rrnode[378]+switch_fall_sb_mux[1][1]_rrnode[378]' -.meas tran sum_leakage_power_mux[0to93] -+ param='sum_leakage_power_mux[0to92]+leakage_sb_mux[1][1]_rrnode[378]' -.meas tran sum_energy_per_cycle_mux[0to93] -+ param='sum_energy_per_cycle_mux[0to92]+energy_per_cycle_sb_mux[1][1]_rrnode[378]' -***** Load for rr_node[378] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=87, type=4 ***** -Xchan_mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[297]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out mux_1level_tapbuf_size2[93]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[300]_no0 mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[93]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to93] -+ param='sum_leakage_power_sb_mux[0to92]+leakage_sb_mux[1][1]_rrnode[378]' -.meas tran sum_energy_per_cycle_sb_mux[0to93] -+ param='sum_energy_per_cycle_sb_mux[0to92]+energy_per_cycle_sb_mux[1][1]_rrnode[378]' -Xmux_1level_tapbuf_size2[94] mux_1level_tapbuf_size2[94]->in[0] mux_1level_tapbuf_size2[94]->in[1] mux_1level_tapbuf_size2[94]->out sram[114]->outb sram[114]->out gvdd_mux_1level_tapbuf_size2[94] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[94], level=1, select_path_id=0. ***** -*****1***** -Xsram[114] sram->in sram[114]->out sram[114]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[114]->out) 0 -.nodeset V(sram[114]->outb) vsp -***** Signal mux_1level_tapbuf_size2[94]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[94]->in[0] mux_1level_tapbuf_size2[94]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[94]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[94]->in[1] mux_1level_tapbuf_size2[94]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[94] gvdd_mux_1level_tapbuf_size2[94] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[380] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[380] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[380] when v(mux_1level_tapbuf_size2[94]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[380] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[380] when v(mux_1level_tapbuf_size2[94]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[380] trig v(mux_1level_tapbuf_size2[94]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[94]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[94]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[380] param='mux_1level_tapbuf_size2[94]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[94]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[94]_energy_per_cycle param='mux_1level_tapbuf_size2[94]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[380] param='mux_1level_tapbuf_size2[94]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[380] param='dynamic_power_sb_mux[1][1]_rrnode[380]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[380] avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='start_rise_sb_mux[1][1]_rrnode[380]' to='start_rise_sb_mux[1][1]_rrnode[380]+switch_rise_sb_mux[1][1]_rrnode[380]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[380] avg p(Vgvdd_mux_1level_tapbuf_size2[94]) from='start_fall_sb_mux[1][1]_rrnode[380]' to='start_fall_sb_mux[1][1]_rrnode[380]+switch_fall_sb_mux[1][1]_rrnode[380]' -.meas tran sum_leakage_power_mux[0to94] -+ param='sum_leakage_power_mux[0to93]+leakage_sb_mux[1][1]_rrnode[380]' -.meas tran sum_energy_per_cycle_mux[0to94] -+ param='sum_energy_per_cycle_mux[0to93]+energy_per_cycle_sb_mux[1][1]_rrnode[380]' -***** Load for rr_node[380] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=89, type=4 ***** -Xchan_mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[301]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out mux_1level_tapbuf_size2[94]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[94]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to94] -+ param='sum_leakage_power_sb_mux[0to93]+leakage_sb_mux[1][1]_rrnode[380]' -.meas tran sum_energy_per_cycle_sb_mux[0to94] -+ param='sum_energy_per_cycle_sb_mux[0to93]+energy_per_cycle_sb_mux[1][1]_rrnode[380]' -Xmux_1level_tapbuf_size2[95] mux_1level_tapbuf_size2[95]->in[0] mux_1level_tapbuf_size2[95]->in[1] mux_1level_tapbuf_size2[95]->out sram[115]->outb sram[115]->out gvdd_mux_1level_tapbuf_size2[95] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[95], level=1, select_path_id=0. ***** -*****1***** -Xsram[115] sram->in sram[115]->out sram[115]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[115]->out) 0 -.nodeset V(sram[115]->outb) vsp -***** Signal mux_1level_tapbuf_size2[95]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[95]->in[0] mux_1level_tapbuf_size2[95]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[95]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[95]->in[1] mux_1level_tapbuf_size2[95]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[95] gvdd_mux_1level_tapbuf_size2[95] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[382] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[382] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[382] when v(mux_1level_tapbuf_size2[95]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[382] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[382] when v(mux_1level_tapbuf_size2[95]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[382] trig v(mux_1level_tapbuf_size2[95]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[95]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[95]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[382] param='mux_1level_tapbuf_size2[95]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[95]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[95]_energy_per_cycle param='mux_1level_tapbuf_size2[95]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[382] param='mux_1level_tapbuf_size2[95]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[382] param='dynamic_power_sb_mux[1][1]_rrnode[382]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[382] avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='start_rise_sb_mux[1][1]_rrnode[382]' to='start_rise_sb_mux[1][1]_rrnode[382]+switch_rise_sb_mux[1][1]_rrnode[382]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[382] avg p(Vgvdd_mux_1level_tapbuf_size2[95]) from='start_fall_sb_mux[1][1]_rrnode[382]' to='start_fall_sb_mux[1][1]_rrnode[382]+switch_fall_sb_mux[1][1]_rrnode[382]' -.meas tran sum_leakage_power_mux[0to95] -+ param='sum_leakage_power_mux[0to94]+leakage_sb_mux[1][1]_rrnode[382]' -.meas tran sum_energy_per_cycle_mux[0to95] -+ param='sum_energy_per_cycle_mux[0to94]+energy_per_cycle_sb_mux[1][1]_rrnode[382]' -***** Load for rr_node[382] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=91, type=4 ***** -Xchan_mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[305]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out mux_1level_tapbuf_size2[95]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[95]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to95] -+ param='sum_leakage_power_sb_mux[0to94]+leakage_sb_mux[1][1]_rrnode[382]' -.meas tran sum_energy_per_cycle_sb_mux[0to95] -+ param='sum_energy_per_cycle_sb_mux[0to94]+energy_per_cycle_sb_mux[1][1]_rrnode[382]' -Xmux_1level_tapbuf_size2[96] mux_1level_tapbuf_size2[96]->in[0] mux_1level_tapbuf_size2[96]->in[1] mux_1level_tapbuf_size2[96]->out sram[116]->outb sram[116]->out gvdd_mux_1level_tapbuf_size2[96] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[96], level=1, select_path_id=0. ***** -*****1***** -Xsram[116] sram->in sram[116]->out sram[116]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[116]->out) 0 -.nodeset V(sram[116]->outb) vsp -***** Signal mux_1level_tapbuf_size2[96]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[96]->in[0] mux_1level_tapbuf_size2[96]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[96]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[96]->in[1] mux_1level_tapbuf_size2[96]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[96] gvdd_mux_1level_tapbuf_size2[96] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[384] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[384] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[384] when v(mux_1level_tapbuf_size2[96]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[384] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[384] when v(mux_1level_tapbuf_size2[96]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[384] trig v(mux_1level_tapbuf_size2[96]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[96]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[96]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[384] param='mux_1level_tapbuf_size2[96]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[96]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[96]_energy_per_cycle param='mux_1level_tapbuf_size2[96]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[384] param='mux_1level_tapbuf_size2[96]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[384] param='dynamic_power_sb_mux[1][1]_rrnode[384]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[384] avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='start_rise_sb_mux[1][1]_rrnode[384]' to='start_rise_sb_mux[1][1]_rrnode[384]+switch_rise_sb_mux[1][1]_rrnode[384]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[384] avg p(Vgvdd_mux_1level_tapbuf_size2[96]) from='start_fall_sb_mux[1][1]_rrnode[384]' to='start_fall_sb_mux[1][1]_rrnode[384]+switch_fall_sb_mux[1][1]_rrnode[384]' -.meas tran sum_leakage_power_mux[0to96] -+ param='sum_leakage_power_mux[0to95]+leakage_sb_mux[1][1]_rrnode[384]' -.meas tran sum_energy_per_cycle_mux[0to96] -+ param='sum_energy_per_cycle_mux[0to95]+energy_per_cycle_sb_mux[1][1]_rrnode[384]' -***** Load for rr_node[384] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=93, type=4 ***** -Xchan_mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[309]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out mux_1level_tapbuf_size2[96]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[96]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to96] -+ param='sum_leakage_power_sb_mux[0to95]+leakage_sb_mux[1][1]_rrnode[384]' -.meas tran sum_energy_per_cycle_sb_mux[0to96] -+ param='sum_energy_per_cycle_sb_mux[0to95]+energy_per_cycle_sb_mux[1][1]_rrnode[384]' -Xmux_1level_tapbuf_size2[97] mux_1level_tapbuf_size2[97]->in[0] mux_1level_tapbuf_size2[97]->in[1] mux_1level_tapbuf_size2[97]->out sram[117]->outb sram[117]->out gvdd_mux_1level_tapbuf_size2[97] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[97], level=1, select_path_id=0. ***** -*****1***** -Xsram[117] sram->in sram[117]->out sram[117]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[117]->out) 0 -.nodeset V(sram[117]->outb) vsp -***** Signal mux_1level_tapbuf_size2[97]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[97]->in[0] mux_1level_tapbuf_size2[97]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[97]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[97]->in[1] mux_1level_tapbuf_size2[97]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[97] gvdd_mux_1level_tapbuf_size2[97] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[386] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[386] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[386] when v(mux_1level_tapbuf_size2[97]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[386] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[386] when v(mux_1level_tapbuf_size2[97]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[386] trig v(mux_1level_tapbuf_size2[97]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[97]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[97]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[386] param='mux_1level_tapbuf_size2[97]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[97]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[97]_energy_per_cycle param='mux_1level_tapbuf_size2[97]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[386] param='mux_1level_tapbuf_size2[97]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[386] param='dynamic_power_sb_mux[1][1]_rrnode[386]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[386] avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='start_rise_sb_mux[1][1]_rrnode[386]' to='start_rise_sb_mux[1][1]_rrnode[386]+switch_rise_sb_mux[1][1]_rrnode[386]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[386] avg p(Vgvdd_mux_1level_tapbuf_size2[97]) from='start_fall_sb_mux[1][1]_rrnode[386]' to='start_fall_sb_mux[1][1]_rrnode[386]+switch_fall_sb_mux[1][1]_rrnode[386]' -.meas tran sum_leakage_power_mux[0to97] -+ param='sum_leakage_power_mux[0to96]+leakage_sb_mux[1][1]_rrnode[386]' -.meas tran sum_energy_per_cycle_mux[0to97] -+ param='sum_energy_per_cycle_mux[0to96]+energy_per_cycle_sb_mux[1][1]_rrnode[386]' -***** Load for rr_node[386] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=95, type=4 ***** -Xchan_mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[313]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out mux_1level_tapbuf_size2[97]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[97]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to97] -+ param='sum_leakage_power_sb_mux[0to96]+leakage_sb_mux[1][1]_rrnode[386]' -.meas tran sum_energy_per_cycle_sb_mux[0to97] -+ param='sum_energy_per_cycle_sb_mux[0to96]+energy_per_cycle_sb_mux[1][1]_rrnode[386]' -Xmux_1level_tapbuf_size2[98] mux_1level_tapbuf_size2[98]->in[0] mux_1level_tapbuf_size2[98]->in[1] mux_1level_tapbuf_size2[98]->out sram[118]->outb sram[118]->out gvdd_mux_1level_tapbuf_size2[98] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[98], level=1, select_path_id=0. ***** -*****1***** -Xsram[118] sram->in sram[118]->out sram[118]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[118]->out) 0 -.nodeset V(sram[118]->outb) vsp -***** Signal mux_1level_tapbuf_size2[98]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[98]->in[0] mux_1level_tapbuf_size2[98]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[98]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[98]->in[1] mux_1level_tapbuf_size2[98]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[98] gvdd_mux_1level_tapbuf_size2[98] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[388] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[388] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[388] when v(mux_1level_tapbuf_size2[98]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[388] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[388] when v(mux_1level_tapbuf_size2[98]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[388] trig v(mux_1level_tapbuf_size2[98]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[98]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[98]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[388] param='mux_1level_tapbuf_size2[98]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[98]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[98]_energy_per_cycle param='mux_1level_tapbuf_size2[98]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[388] param='mux_1level_tapbuf_size2[98]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[388] param='dynamic_power_sb_mux[1][1]_rrnode[388]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[388] avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='start_rise_sb_mux[1][1]_rrnode[388]' to='start_rise_sb_mux[1][1]_rrnode[388]+switch_rise_sb_mux[1][1]_rrnode[388]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[388] avg p(Vgvdd_mux_1level_tapbuf_size2[98]) from='start_fall_sb_mux[1][1]_rrnode[388]' to='start_fall_sb_mux[1][1]_rrnode[388]+switch_fall_sb_mux[1][1]_rrnode[388]' -.meas tran sum_leakage_power_mux[0to98] -+ param='sum_leakage_power_mux[0to97]+leakage_sb_mux[1][1]_rrnode[388]' -.meas tran sum_energy_per_cycle_mux[0to98] -+ param='sum_energy_per_cycle_mux[0to97]+energy_per_cycle_sb_mux[1][1]_rrnode[388]' -***** Load for rr_node[388] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=97, type=4 ***** -Xchan_mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[316]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out mux_1level_tapbuf_size2[98]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[98]->out_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to98] -+ param='sum_leakage_power_sb_mux[0to97]+leakage_sb_mux[1][1]_rrnode[388]' -.meas tran sum_energy_per_cycle_sb_mux[0to98] -+ param='sum_energy_per_cycle_sb_mux[0to97]+energy_per_cycle_sb_mux[1][1]_rrnode[388]' -Xmux_1level_tapbuf_size2[99] mux_1level_tapbuf_size2[99]->in[0] mux_1level_tapbuf_size2[99]->in[1] mux_1level_tapbuf_size2[99]->out sram[119]->outb sram[119]->out gvdd_mux_1level_tapbuf_size2[99] 0 mux_1level_tapbuf_size2 -***** SRAM bits for MUX[99], level=1, select_path_id=0. ***** -*****1***** -Xsram[119] sram->in sram[119]->out sram[119]->outb gvdd_sram sgnd sram6T -.nodeset V(sram[119]->out) 0 -.nodeset V(sram[119]->outb) vsp -***** Signal mux_1level_tapbuf_size2[99]->in[0] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[99]->in[0] mux_1level_tapbuf_size2[99]->in[0] 0 -+ 0 -***** Signal mux_1level_tapbuf_size2[99]->in[1] density = 0, probability=0.***** -Vmux_1level_tapbuf_size2[99]->in[1] mux_1level_tapbuf_size2[99]->in[1] 0 -+ 0 -Vgvdd_mux_1level_tapbuf_size2[99] gvdd_mux_1level_tapbuf_size2[99] 0 vsp -***** Measurements ***** -***** Rise delay ***** -.meas tran delay_rise_sb_mux[1][1]_rrnode[390] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='input_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='output_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall delay ***** -.meas tran delay_fall_sb_mux[1][1]_rrnode[390] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='input_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='output_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Rise timing period ***** -.meas start_rise_sb_mux[1][1]_rrnode[390] when v(mux_1level_tapbuf_size2[99]->in[0])='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -.meas tran switch_rise_sb_mux[1][1]_rrnode[390] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='slew_lower_thres_pct_rise*vsp' rise=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='slew_upper_thres_pct_rise*vsp' rise=1 td='clock_period' -***** Fall timing period ***** -.meas start_fall_sb_mux[1][1]_rrnode[390] when v(mux_1level_tapbuf_size2[99]->in[0])='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -.meas tran switch_fall_sb_mux[1][1]_rrnode[390] trig v(mux_1level_tapbuf_size2[99]->in[0]) val='slew_lower_thres_pct_fall*vsp' fall=1 td='clock_period' -+ targ v(mux_1level_tapbuf_size2[99]->out) val='slew_upper_thres_pct_fall*vsp' fall=1 td='clock_period' -***** Leakage Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[99]_leakage_power avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from=0 to='clock_period' -.meas tran leakage_sb_mux[1][1]_rrnode[390] param='mux_1level_tapbuf_size2[99]_leakage_power' -***** Dynamic Power Measurement ***** -.meas tran mux_1level_tapbuf_size2[99]_dynamic_power avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='clock_period' to='2*clock_period' -.meas tran mux_1level_tapbuf_size2[99]_energy_per_cycle param='mux_1level_tapbuf_size2[99]_dynamic_power*clock_period' -.meas tran dynamic_power_sb_mux[1][1]_rrnode[390] param='mux_1level_tapbuf_size2[99]_dynamic_power' -.meas tran energy_per_cycle_sb_mux[1][1]_rrnode[390] param='dynamic_power_sb_mux[1][1]_rrnode[390]*clock_period' -.meas tran dynamic_rise_sb_mux[1][1]_rrnode[390] avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='start_rise_sb_mux[1][1]_rrnode[390]' to='start_rise_sb_mux[1][1]_rrnode[390]+switch_rise_sb_mux[1][1]_rrnode[390]' -.meas tran dynamic_fall_sb_mux[1][1]_rrnode[390] avg p(Vgvdd_mux_1level_tapbuf_size2[99]) from='start_fall_sb_mux[1][1]_rrnode[390]' to='start_fall_sb_mux[1][1]_rrnode[390]+switch_fall_sb_mux[1][1]_rrnode[390]' -.meas tran sum_leakage_power_mux[0to99] -+ param='sum_leakage_power_mux[0to98]+leakage_sb_mux[1][1]_rrnode[390]' -.meas tran sum_energy_per_cycle_mux[0to99] -+ param='sum_energy_per_cycle_mux[0to98]+energy_per_cycle_sb_mux[1][1]_rrnode[390]' -***** Load for rr_node[390] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=99, type=4 ***** -Xchan_mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[321]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out mux_1level_tapbuf_size2[99]->out_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout mux_1level_tapbuf_size2[99]->out_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -.meas tran sum_leakage_power_sb_mux[0to99] -+ param='sum_leakage_power_sb_mux[0to98]+leakage_sb_mux[1][1]_rrnode[390]' -.meas tran sum_energy_per_cycle_sb_mux[0to99] -+ param='sum_energy_per_cycle_sb_mux[0to98]+energy_per_cycle_sb_mux[1][1]_rrnode[390]' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.meas tran total_leakage_srams avg p(Vgvdd_sram) from=0 to='clock_period' -.meas tran total_dynamic_srams avg p(Vgvdd_sram) from='clock_period' to='6*clock_period' -.meas tran total_energy_per_cycle_srams param='total_dynamic_srams*clock_period' -.meas tran total_leakage_power_mux[0to99] -+ param='sum_leakage_power_mux[0to99]' -.meas tran total_energy_per_cycle_mux[0to99] -+ param='sum_energy_per_cycle_mux[0to99]' -.meas tran total_leakage_power_sb_mux -+ param='sum_leakage_power_sb_mux[0to99]' -.meas tran total_energy_per_cycle_sb_mux -+ param='sum_energy_per_cycle_sb_mux[0to99]' -.end diff --git a/examples/spice_test_example_2/sb_tb/example_2_sb0_0_sb_testbench.sp b/examples/spice_test_example_2/sb_tb/example_2_sb0_0_sb_testbench.sp deleted file mode 100644 index 744d77277..000000000 --- a/examples/spice_test_example_2/sb_tb/example_2_sb0_0_sb_testbench.sp +++ /dev/null @@ -1,1161 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_sbs -****** Include subckt netlists: Switch Block[0][0] ***** -.include './spice_test_example_2/subckt/sb_0_0.sp' -***** Call defined Switch Box[0][0] ***** -Xsb[0][0] -+ chany[0][1]_out[0] chany[0][1]_in[1] chany[0][1]_out[2] chany[0][1]_in[3] chany[0][1]_out[4] chany[0][1]_in[5] chany[0][1]_out[6] chany[0][1]_in[7] chany[0][1]_out[8] chany[0][1]_in[9] chany[0][1]_out[10] chany[0][1]_in[11] chany[0][1]_out[12] chany[0][1]_in[13] chany[0][1]_out[14] chany[0][1]_in[15] chany[0][1]_out[16] chany[0][1]_in[17] chany[0][1]_out[18] chany[0][1]_in[19] chany[0][1]_out[20] chany[0][1]_in[21] chany[0][1]_out[22] chany[0][1]_in[23] chany[0][1]_out[24] chany[0][1]_in[25] chany[0][1]_out[26] chany[0][1]_in[27] chany[0][1]_out[28] chany[0][1]_in[29] chany[0][1]_out[30] chany[0][1]_in[31] chany[0][1]_out[32] chany[0][1]_in[33] chany[0][1]_out[34] chany[0][1]_in[35] chany[0][1]_out[36] chany[0][1]_in[37] chany[0][1]_out[38] chany[0][1]_in[39] chany[0][1]_out[40] chany[0][1]_in[41] chany[0][1]_out[42] chany[0][1]_in[43] chany[0][1]_out[44] chany[0][1]_in[45] chany[0][1]_out[46] chany[0][1]_in[47] chany[0][1]_out[48] chany[0][1]_in[49] chany[0][1]_out[50] chany[0][1]_in[51] chany[0][1]_out[52] chany[0][1]_in[53] chany[0][1]_out[54] chany[0][1]_in[55] chany[0][1]_out[56] chany[0][1]_in[57] chany[0][1]_out[58] chany[0][1]_in[59] chany[0][1]_out[60] chany[0][1]_in[61] chany[0][1]_out[62] chany[0][1]_in[63] chany[0][1]_out[64] chany[0][1]_in[65] chany[0][1]_out[66] chany[0][1]_in[67] chany[0][1]_out[68] chany[0][1]_in[69] chany[0][1]_out[70] chany[0][1]_in[71] chany[0][1]_out[72] chany[0][1]_in[73] chany[0][1]_out[74] chany[0][1]_in[75] chany[0][1]_out[76] chany[0][1]_in[77] chany[0][1]_out[78] chany[0][1]_in[79] chany[0][1]_out[80] chany[0][1]_in[81] chany[0][1]_out[82] chany[0][1]_in[83] chany[0][1]_out[84] chany[0][1]_in[85] chany[0][1]_out[86] chany[0][1]_in[87] chany[0][1]_out[88] chany[0][1]_in[89] chany[0][1]_out[90] chany[0][1]_in[91] chany[0][1]_out[92] chany[0][1]_in[93] chany[0][1]_out[94] chany[0][1]_in[95] chany[0][1]_out[96] chany[0][1]_in[97] chany[0][1]_out[98] chany[0][1]_in[99] -+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][47] -+ chanx[1][0]_out[0] chanx[1][0]_in[1] chanx[1][0]_out[2] chanx[1][0]_in[3] chanx[1][0]_out[4] chanx[1][0]_in[5] chanx[1][0]_out[6] chanx[1][0]_in[7] chanx[1][0]_out[8] chanx[1][0]_in[9] chanx[1][0]_out[10] chanx[1][0]_in[11] chanx[1][0]_out[12] chanx[1][0]_in[13] chanx[1][0]_out[14] chanx[1][0]_in[15] chanx[1][0]_out[16] chanx[1][0]_in[17] chanx[1][0]_out[18] chanx[1][0]_in[19] chanx[1][0]_out[20] chanx[1][0]_in[21] chanx[1][0]_out[22] chanx[1][0]_in[23] chanx[1][0]_out[24] chanx[1][0]_in[25] chanx[1][0]_out[26] chanx[1][0]_in[27] chanx[1][0]_out[28] chanx[1][0]_in[29] chanx[1][0]_out[30] chanx[1][0]_in[31] chanx[1][0]_out[32] chanx[1][0]_in[33] chanx[1][0]_out[34] chanx[1][0]_in[35] chanx[1][0]_out[36] chanx[1][0]_in[37] chanx[1][0]_out[38] chanx[1][0]_in[39] chanx[1][0]_out[40] chanx[1][0]_in[41] chanx[1][0]_out[42] chanx[1][0]_in[43] chanx[1][0]_out[44] chanx[1][0]_in[45] chanx[1][0]_out[46] chanx[1][0]_in[47] chanx[1][0]_out[48] chanx[1][0]_in[49] chanx[1][0]_out[50] chanx[1][0]_in[51] chanx[1][0]_out[52] chanx[1][0]_in[53] chanx[1][0]_out[54] chanx[1][0]_in[55] chanx[1][0]_out[56] chanx[1][0]_in[57] chanx[1][0]_out[58] chanx[1][0]_in[59] chanx[1][0]_out[60] chanx[1][0]_in[61] chanx[1][0]_out[62] chanx[1][0]_in[63] chanx[1][0]_out[64] chanx[1][0]_in[65] chanx[1][0]_out[66] chanx[1][0]_in[67] chanx[1][0]_out[68] chanx[1][0]_in[69] chanx[1][0]_out[70] chanx[1][0]_in[71] chanx[1][0]_out[72] chanx[1][0]_in[73] chanx[1][0]_out[74] chanx[1][0]_in[75] chanx[1][0]_out[76] chanx[1][0]_in[77] chanx[1][0]_out[78] chanx[1][0]_in[79] chanx[1][0]_out[80] chanx[1][0]_in[81] chanx[1][0]_out[82] chanx[1][0]_in[83] chanx[1][0]_out[84] chanx[1][0]_in[85] chanx[1][0]_out[86] chanx[1][0]_in[87] chanx[1][0]_out[88] chanx[1][0]_in[89] chanx[1][0]_out[90] chanx[1][0]_in[91] chanx[1][0]_out[92] chanx[1][0]_in[93] chanx[1][0]_out[94] chanx[1][0]_in[95] chanx[1][0]_out[96] chanx[1][0]_in[97] chanx[1][0]_out[98] chanx[1][0]_in[99] -+ grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][46] grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ -+ -+ -+ -+ gvdd_sb[0][0] 0 sb[0][0] -**** Load for rr_node[391] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=0, type=5 ***** -Xchan_chany[0][1]_out[0]_loadlvl[0]_out chany[0][1]_out[0] chany[0][1]_out[0]_loadlvl[0]_out chany[0][1]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 chany[0][1]_out[0]_loadlvl[0]_out chany[0][1]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 chany[0][1]_out[0]_loadlvl[0]_midout chany[0][1]_out[0]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 chany[0][1]_out[0]_loadlvl[0]_midout chany[0][1]_out[0]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 chany[0][1]_out[0]_loadlvl[0]_midout chany[0][1]_out[0]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[1] density = 0, probability=0.***** -Vchany[0][1]_in[1] chany[0][1]_in[1] 0 -+ 0 -**** Load for rr_node[393] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=2, type=5 ***** -Xchan_chany[0][1]_out[2]_loadlvl[0]_out chany[0][1]_out[2] chany[0][1]_out[2]_loadlvl[0]_out chany[0][1]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[4]_no0 chany[0][1]_out[2]_loadlvl[0]_out chany[0][1]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[5]_no0 chany[0][1]_out[2]_loadlvl[0]_midout chany[0][1]_out[2]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 chany[0][1]_out[2]_loadlvl[0]_midout chany[0][1]_out[2]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 chany[0][1]_out[2]_loadlvl[0]_midout chany[0][1]_out[2]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[3] density = 0, probability=0.***** -Vchany[0][1]_in[3] chany[0][1]_in[3] 0 -+ 0 -**** Load for rr_node[395] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=4, type=5 ***** -Xchan_chany[0][1]_out[4]_loadlvl[0]_out chany[0][1]_out[4] chany[0][1]_out[4]_loadlvl[0]_out chany[0][1]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[8]_no0 chany[0][1]_out[4]_loadlvl[0]_out chany[0][1]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 chany[0][1]_out[4]_loadlvl[0]_midout chany[0][1]_out[4]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 chany[0][1]_out[4]_loadlvl[0]_midout chany[0][1]_out[4]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 chany[0][1]_out[4]_loadlvl[0]_midout chany[0][1]_out[4]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[5] density = 0, probability=0.***** -Vchany[0][1]_in[5] chany[0][1]_in[5] 0 -+ 0 -**** Load for rr_node[397] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=6, type=5 ***** -Xchan_chany[0][1]_out[6]_loadlvl[0]_out chany[0][1]_out[6] chany[0][1]_out[6]_loadlvl[0]_out chany[0][1]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[12]_no0 chany[0][1]_out[6]_loadlvl[0]_out chany[0][1]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 chany[0][1]_out[6]_loadlvl[0]_midout chany[0][1]_out[6]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 chany[0][1]_out[6]_loadlvl[0]_midout chany[0][1]_out[6]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[7] density = 0, probability=0.***** -Vchany[0][1]_in[7] chany[0][1]_in[7] 0 -+ 0 -**** Load for rr_node[399] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=8, type=5 ***** -Xchan_chany[0][1]_out[8]_loadlvl[0]_out chany[0][1]_out[8] chany[0][1]_out[8]_loadlvl[0]_out chany[0][1]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[15]_no0 chany[0][1]_out[8]_loadlvl[0]_out chany[0][1]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[16]_no0 chany[0][1]_out[8]_loadlvl[0]_midout chany[0][1]_out[8]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 chany[0][1]_out[8]_loadlvl[0]_midout chany[0][1]_out[8]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 chany[0][1]_out[8]_loadlvl[0]_midout chany[0][1]_out[8]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 chany[0][1]_out[8]_loadlvl[0]_midout chany[0][1]_out[8]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[9] density = 0, probability=0.***** -Vchany[0][1]_in[9] chany[0][1]_in[9] 0 -+ 0 -**** Load for rr_node[401] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=10, type=5 ***** -Xchan_chany[0][1]_out[10]_loadlvl[0]_out chany[0][1]_out[10] chany[0][1]_out[10]_loadlvl[0]_out chany[0][1]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[20]_no0 chany[0][1]_out[10]_loadlvl[0]_out chany[0][1]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[21]_no0 chany[0][1]_out[10]_loadlvl[0]_midout chany[0][1]_out[10]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 chany[0][1]_out[10]_loadlvl[0]_midout chany[0][1]_out[10]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[11] density = 0, probability=0.***** -Vchany[0][1]_in[11] chany[0][1]_in[11] 0 -+ 0 -**** Load for rr_node[403] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=12, type=5 ***** -Xchan_chany[0][1]_out[12]_loadlvl[0]_out chany[0][1]_out[12] chany[0][1]_out[12]_loadlvl[0]_out chany[0][1]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[23]_no0 chany[0][1]_out[12]_loadlvl[0]_out chany[0][1]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 chany[0][1]_out[12]_loadlvl[0]_midout chany[0][1]_out[12]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 chany[0][1]_out[12]_loadlvl[0]_midout chany[0][1]_out[12]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 chany[0][1]_out[12]_loadlvl[0]_midout chany[0][1]_out[12]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[13] density = 0, probability=0.***** -Vchany[0][1]_in[13] chany[0][1]_in[13] 0 -+ 0 -**** Load for rr_node[405] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=14, type=5 ***** -Xchan_chany[0][1]_out[14]_loadlvl[0]_out chany[0][1]_out[14] chany[0][1]_out[14]_loadlvl[0]_out chany[0][1]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[27]_no0 chany[0][1]_out[14]_loadlvl[0]_out chany[0][1]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[28]_no0 chany[0][1]_out[14]_loadlvl[0]_midout chany[0][1]_out[14]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 chany[0][1]_out[14]_loadlvl[0]_midout chany[0][1]_out[14]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 chany[0][1]_out[14]_loadlvl[0]_midout chany[0][1]_out[14]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[15] density = 0, probability=0.***** -Vchany[0][1]_in[15] chany[0][1]_in[15] 0 -+ 0 -**** Load for rr_node[407] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=16, type=5 ***** -Xchan_chany[0][1]_out[16]_loadlvl[0]_out chany[0][1]_out[16] chany[0][1]_out[16]_loadlvl[0]_out chany[0][1]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[31]_no0 chany[0][1]_out[16]_loadlvl[0]_out chany[0][1]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 chany[0][1]_out[16]_loadlvl[0]_midout chany[0][1]_out[16]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 chany[0][1]_out[16]_loadlvl[0]_midout chany[0][1]_out[16]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[34]_no0 chany[0][1]_out[16]_loadlvl[0]_midout chany[0][1]_out[16]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[17] density = 0, probability=0.***** -Vchany[0][1]_in[17] chany[0][1]_in[17] 0 -+ 0 -**** Load for rr_node[409] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=18, type=5 ***** -Xchan_chany[0][1]_out[18]_loadlvl[0]_out chany[0][1]_out[18] chany[0][1]_out[18]_loadlvl[0]_out chany[0][1]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[35]_no0 chany[0][1]_out[18]_loadlvl[0]_out chany[0][1]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 chany[0][1]_out[18]_loadlvl[0]_midout chany[0][1]_out[18]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 chany[0][1]_out[18]_loadlvl[0]_midout chany[0][1]_out[18]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 chany[0][1]_out[18]_loadlvl[0]_midout chany[0][1]_out[18]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[19] density = 0, probability=0.***** -Vchany[0][1]_in[19] chany[0][1]_in[19] 0 -+ 0 -**** Load for rr_node[411] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=20, type=5 ***** -Xchan_chany[0][1]_out[20]_loadlvl[0]_out chany[0][1]_out[20] chany[0][1]_out[20]_loadlvl[0]_out chany[0][1]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[39]_no0 chany[0][1]_out[20]_loadlvl[0]_out chany[0][1]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 chany[0][1]_out[20]_loadlvl[0]_midout chany[0][1]_out[20]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 chany[0][1]_out[20]_loadlvl[0]_midout chany[0][1]_out[20]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[21] density = 0, probability=0.***** -Vchany[0][1]_in[21] chany[0][1]_in[21] 0 -+ 0 -**** Load for rr_node[413] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=22, type=5 ***** -Xchan_chany[0][1]_out[22]_loadlvl[0]_out chany[0][1]_out[22] chany[0][1]_out[22]_loadlvl[0]_out chany[0][1]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[42]_no0 chany[0][1]_out[22]_loadlvl[0]_out chany[0][1]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 chany[0][1]_out[22]_loadlvl[0]_midout chany[0][1]_out[22]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 chany[0][1]_out[22]_loadlvl[0]_midout chany[0][1]_out[22]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 chany[0][1]_out[22]_loadlvl[0]_midout chany[0][1]_out[22]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 chany[0][1]_out[22]_loadlvl[0]_midout chany[0][1]_out[22]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[23] density = 0, probability=0.***** -Vchany[0][1]_in[23] chany[0][1]_in[23] 0 -+ 0 -**** Load for rr_node[415] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=24, type=5 ***** -Xchan_chany[0][1]_out[24]_loadlvl[0]_out chany[0][1]_out[24] chany[0][1]_out[24]_loadlvl[0]_out chany[0][1]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[47]_no0 chany[0][1]_out[24]_loadlvl[0]_out chany[0][1]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 chany[0][1]_out[24]_loadlvl[0]_midout chany[0][1]_out[24]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 chany[0][1]_out[24]_loadlvl[0]_midout chany[0][1]_out[24]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 chany[0][1]_out[24]_loadlvl[0]_midout chany[0][1]_out[24]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[25] density = 0, probability=0.***** -Vchany[0][1]_in[25] chany[0][1]_in[25] 0 -+ 0 -**** Load for rr_node[417] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=26, type=5 ***** -Xchan_chany[0][1]_out[26]_loadlvl[0]_out chany[0][1]_out[26] chany[0][1]_out[26]_loadlvl[0]_out chany[0][1]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[51]_no0 chany[0][1]_out[26]_loadlvl[0]_out chany[0][1]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 chany[0][1]_out[26]_loadlvl[0]_midout chany[0][1]_out[26]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 chany[0][1]_out[26]_loadlvl[0]_midout chany[0][1]_out[26]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[27] density = 0, probability=0.***** -Vchany[0][1]_in[27] chany[0][1]_in[27] 0 -+ 0 -**** Load for rr_node[419] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=28, type=5 ***** -Xchan_chany[0][1]_out[28]_loadlvl[0]_out chany[0][1]_out[28] chany[0][1]_out[28]_loadlvl[0]_out chany[0][1]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[54]_no0 chany[0][1]_out[28]_loadlvl[0]_out chany[0][1]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 chany[0][1]_out[28]_loadlvl[0]_midout chany[0][1]_out[28]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 chany[0][1]_out[28]_loadlvl[0]_midout chany[0][1]_out[28]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 chany[0][1]_out[28]_loadlvl[0]_midout chany[0][1]_out[28]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[29] density = 0, probability=0.***** -Vchany[0][1]_in[29] chany[0][1]_in[29] 0 -+ 0 -**** Load for rr_node[421] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=30, type=5 ***** -Xchan_chany[0][1]_out[30]_loadlvl[0]_out chany[0][1]_out[30] chany[0][1]_out[30]_loadlvl[0]_out chany[0][1]_out[30]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[58]_no0 chany[0][1]_out[30]_loadlvl[0]_out chany[0][1]_out[30]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 chany[0][1]_out[30]_loadlvl[0]_midout chany[0][1]_out[30]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[60]_no0 chany[0][1]_out[30]_loadlvl[0]_midout chany[0][1]_out[30]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 chany[0][1]_out[30]_loadlvl[0]_midout chany[0][1]_out[30]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[31] density = 0, probability=0.***** -Vchany[0][1]_in[31] chany[0][1]_in[31] 0 -+ 0 -**** Load for rr_node[423] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=32, type=5 ***** -Xchan_chany[0][1]_out[32]_loadlvl[0]_out chany[0][1]_out[32] chany[0][1]_out[32]_loadlvl[0]_out chany[0][1]_out[32]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[62]_no0 chany[0][1]_out[32]_loadlvl[0]_out chany[0][1]_out[32]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 chany[0][1]_out[32]_loadlvl[0]_midout chany[0][1]_out[32]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 chany[0][1]_out[32]_loadlvl[0]_midout chany[0][1]_out[32]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 chany[0][1]_out[32]_loadlvl[0]_midout chany[0][1]_out[32]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[33] density = 0, probability=0.***** -Vchany[0][1]_in[33] chany[0][1]_in[33] 0 -+ 0 -**** Load for rr_node[425] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=34, type=5 ***** -Xchan_chany[0][1]_out[34]_loadlvl[0]_out chany[0][1]_out[34] chany[0][1]_out[34]_loadlvl[0]_out chany[0][1]_out[34]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[66]_no0 chany[0][1]_out[34]_loadlvl[0]_out chany[0][1]_out[34]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 chany[0][1]_out[34]_loadlvl[0]_midout chany[0][1]_out[34]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 chany[0][1]_out[34]_loadlvl[0]_midout chany[0][1]_out[34]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 chany[0][1]_out[34]_loadlvl[0]_midout chany[0][1]_out[34]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[35] density = 0, probability=0.***** -Vchany[0][1]_in[35] chany[0][1]_in[35] 0 -+ 0 -**** Load for rr_node[427] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=36, type=5 ***** -Xchan_chany[0][1]_out[36]_loadlvl[0]_out chany[0][1]_out[36] chany[0][1]_out[36]_loadlvl[0]_out chany[0][1]_out[36]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[70]_no0 chany[0][1]_out[36]_loadlvl[0]_out chany[0][1]_out[36]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 chany[0][1]_out[36]_loadlvl[0]_midout chany[0][1]_out[36]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 chany[0][1]_out[36]_loadlvl[0]_midout chany[0][1]_out[36]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[73]_no0 chany[0][1]_out[36]_loadlvl[0]_midout chany[0][1]_out[36]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[37] density = 0, probability=0.***** -Vchany[0][1]_in[37] chany[0][1]_in[37] 0 -+ 0 -**** Load for rr_node[429] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=38, type=5 ***** -Xchan_chany[0][1]_out[38]_loadlvl[0]_out chany[0][1]_out[38] chany[0][1]_out[38]_loadlvl[0]_out chany[0][1]_out[38]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[74]_no0 chany[0][1]_out[38]_loadlvl[0]_out chany[0][1]_out[38]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 chany[0][1]_out[38]_loadlvl[0]_midout chany[0][1]_out[38]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 chany[0][1]_out[38]_loadlvl[0]_midout chany[0][1]_out[38]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 chany[0][1]_out[38]_loadlvl[0]_midout chany[0][1]_out[38]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[39] density = 0, probability=0.***** -Vchany[0][1]_in[39] chany[0][1]_in[39] 0 -+ 0 -**** Load for rr_node[431] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=40, type=5 ***** -Xchan_chany[0][1]_out[40]_loadlvl[0]_out chany[0][1]_out[40] chany[0][1]_out[40]_loadlvl[0]_out chany[0][1]_out[40]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[78]_no0 chany[0][1]_out[40]_loadlvl[0]_out chany[0][1]_out[40]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 chany[0][1]_out[40]_loadlvl[0]_midout chany[0][1]_out[40]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 chany[0][1]_out[40]_loadlvl[0]_midout chany[0][1]_out[40]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[41] density = 0, probability=0.***** -Vchany[0][1]_in[41] chany[0][1]_in[41] 0 -+ 0 -**** Load for rr_node[433] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=42, type=5 ***** -Xchan_chany[0][1]_out[42]_loadlvl[0]_out chany[0][1]_out[42] chany[0][1]_out[42]_loadlvl[0]_out chany[0][1]_out[42]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[81]_no0 chany[0][1]_out[42]_loadlvl[0]_out chany[0][1]_out[42]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 chany[0][1]_out[42]_loadlvl[0]_midout chany[0][1]_out[42]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 chany[0][1]_out[42]_loadlvl[0]_midout chany[0][1]_out[42]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 chany[0][1]_out[42]_loadlvl[0]_midout chany[0][1]_out[42]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[43] density = 0, probability=0.***** -Vchany[0][1]_in[43] chany[0][1]_in[43] 0 -+ 0 -**** Load for rr_node[435] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=44, type=5 ***** -Xchan_chany[0][1]_out[44]_loadlvl[0]_out chany[0][1]_out[44] chany[0][1]_out[44]_loadlvl[0]_out chany[0][1]_out[44]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[85]_no0 chany[0][1]_out[44]_loadlvl[0]_out chany[0][1]_out[44]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[86]_no0 chany[0][1]_out[44]_loadlvl[0]_midout chany[0][1]_out[44]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 chany[0][1]_out[44]_loadlvl[0]_midout chany[0][1]_out[44]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 chany[0][1]_out[44]_loadlvl[0]_midout chany[0][1]_out[44]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 chany[0][1]_out[44]_loadlvl[0]_midout chany[0][1]_out[44]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[45] density = 0, probability=0.***** -Vchany[0][1]_in[45] chany[0][1]_in[45] 0 -+ 0 -**** Load for rr_node[437] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=46, type=5 ***** -Xchan_chany[0][1]_out[46]_loadlvl[0]_out chany[0][1]_out[46] chany[0][1]_out[46]_loadlvl[0]_out chany[0][1]_out[46]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[90]_no0 chany[0][1]_out[46]_loadlvl[0]_out chany[0][1]_out[46]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[91]_no0 chany[0][1]_out[46]_loadlvl[0]_midout chany[0][1]_out[46]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 chany[0][1]_out[46]_loadlvl[0]_midout chany[0][1]_out[46]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[47] density = 0, probability=0.***** -Vchany[0][1]_in[47] chany[0][1]_in[47] 0 -+ 0 -**** Load for rr_node[439] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=48, type=5 ***** -Xchan_chany[0][1]_out[48]_loadlvl[0]_out chany[0][1]_out[48] chany[0][1]_out[48]_loadlvl[0]_out chany[0][1]_out[48]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[93]_no0 chany[0][1]_out[48]_loadlvl[0]_out chany[0][1]_out[48]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[94]_no0 chany[0][1]_out[48]_loadlvl[0]_midout chany[0][1]_out[48]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 chany[0][1]_out[48]_loadlvl[0]_midout chany[0][1]_out[48]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 chany[0][1]_out[48]_loadlvl[0]_midout chany[0][1]_out[48]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[49] density = 0, probability=0.***** -Vchany[0][1]_in[49] chany[0][1]_in[49] 0 -+ 0 -**** Load for rr_node[441] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=50, type=5 ***** -Xchan_chany[0][1]_out[50]_loadlvl[0]_out chany[0][1]_out[50] chany[0][1]_out[50]_loadlvl[0]_out chany[0][1]_out[50]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[97]_no0 chany[0][1]_out[50]_loadlvl[0]_out chany[0][1]_out[50]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 chany[0][1]_out[50]_loadlvl[0]_midout chany[0][1]_out[50]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 chany[0][1]_out[50]_loadlvl[0]_midout chany[0][1]_out[50]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 chany[0][1]_out[50]_loadlvl[0]_midout chany[0][1]_out[50]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[51] density = 0, probability=0.***** -Vchany[0][1]_in[51] chany[0][1]_in[51] 0 -+ 0 -**** Load for rr_node[443] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=52, type=5 ***** -Xchan_chany[0][1]_out[52]_loadlvl[0]_out chany[0][1]_out[52] chany[0][1]_out[52]_loadlvl[0]_out chany[0][1]_out[52]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[101]_no0 chany[0][1]_out[52]_loadlvl[0]_out chany[0][1]_out[52]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 chany[0][1]_out[52]_loadlvl[0]_midout chany[0][1]_out[52]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 chany[0][1]_out[52]_loadlvl[0]_midout chany[0][1]_out[52]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[104]_no0 chany[0][1]_out[52]_loadlvl[0]_midout chany[0][1]_out[52]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[53] density = 0, probability=0.***** -Vchany[0][1]_in[53] chany[0][1]_in[53] 0 -+ 0 -**** Load for rr_node[445] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=54, type=5 ***** -Xchan_chany[0][1]_out[54]_loadlvl[0]_out chany[0][1]_out[54] chany[0][1]_out[54]_loadlvl[0]_out chany[0][1]_out[54]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[105]_no0 chany[0][1]_out[54]_loadlvl[0]_out chany[0][1]_out[54]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 chany[0][1]_out[54]_loadlvl[0]_midout chany[0][1]_out[54]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 chany[0][1]_out[54]_loadlvl[0]_midout chany[0][1]_out[54]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 chany[0][1]_out[54]_loadlvl[0]_midout chany[0][1]_out[54]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[55] density = 0, probability=0.***** -Vchany[0][1]_in[55] chany[0][1]_in[55] 0 -+ 0 -**** Load for rr_node[447] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=56, type=5 ***** -Xchan_chany[0][1]_out[56]_loadlvl[0]_out chany[0][1]_out[56] chany[0][1]_out[56]_loadlvl[0]_out chany[0][1]_out[56]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[109]_no0 chany[0][1]_out[56]_loadlvl[0]_out chany[0][1]_out[56]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 chany[0][1]_out[56]_loadlvl[0]_midout chany[0][1]_out[56]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 chany[0][1]_out[56]_loadlvl[0]_midout chany[0][1]_out[56]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[57] density = 0, probability=0.***** -Vchany[0][1]_in[57] chany[0][1]_in[57] 0 -+ 0 -**** Load for rr_node[449] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=58, type=5 ***** -Xchan_chany[0][1]_out[58]_loadlvl[0]_out chany[0][1]_out[58] chany[0][1]_out[58]_loadlvl[0]_out chany[0][1]_out[58]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[112]_no0 chany[0][1]_out[58]_loadlvl[0]_out chany[0][1]_out[58]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 chany[0][1]_out[58]_loadlvl[0]_midout chany[0][1]_out[58]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 chany[0][1]_out[58]_loadlvl[0]_midout chany[0][1]_out[58]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 chany[0][1]_out[58]_loadlvl[0]_midout chany[0][1]_out[58]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 chany[0][1]_out[58]_loadlvl[0]_midout chany[0][1]_out[58]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[59] density = 0, probability=0.***** -Vchany[0][1]_in[59] chany[0][1]_in[59] 0 -+ 0 -**** Load for rr_node[451] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=60, type=5 ***** -Xchan_chany[0][1]_out[60]_loadlvl[0]_out chany[0][1]_out[60] chany[0][1]_out[60]_loadlvl[0]_out chany[0][1]_out[60]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[117]_no0 chany[0][1]_out[60]_loadlvl[0]_out chany[0][1]_out[60]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 chany[0][1]_out[60]_loadlvl[0]_midout chany[0][1]_out[60]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 chany[0][1]_out[60]_loadlvl[0]_midout chany[0][1]_out[60]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[61] density = 0, probability=0.***** -Vchany[0][1]_in[61] chany[0][1]_in[61] 0 -+ 0 -**** Load for rr_node[453] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=62, type=5 ***** -Xchan_chany[0][1]_out[62]_loadlvl[0]_out chany[0][1]_out[62] chany[0][1]_out[62]_loadlvl[0]_out chany[0][1]_out[62]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[120]_no0 chany[0][1]_out[62]_loadlvl[0]_out chany[0][1]_out[62]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 chany[0][1]_out[62]_loadlvl[0]_midout chany[0][1]_out[62]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 chany[0][1]_out[62]_loadlvl[0]_midout chany[0][1]_out[62]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 chany[0][1]_out[62]_loadlvl[0]_midout chany[0][1]_out[62]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[63] density = 0, probability=0.***** -Vchany[0][1]_in[63] chany[0][1]_in[63] 0 -+ 0 -**** Load for rr_node[455] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=64, type=5 ***** -Xchan_chany[0][1]_out[64]_loadlvl[0]_out chany[0][1]_out[64] chany[0][1]_out[64]_loadlvl[0]_out chany[0][1]_out[64]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[124]_no0 chany[0][1]_out[64]_loadlvl[0]_out chany[0][1]_out[64]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[125]_no0 chany[0][1]_out[64]_loadlvl[0]_midout chany[0][1]_out[64]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 chany[0][1]_out[64]_loadlvl[0]_midout chany[0][1]_out[64]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 chany[0][1]_out[64]_loadlvl[0]_midout chany[0][1]_out[64]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[65] density = 0, probability=0.***** -Vchany[0][1]_in[65] chany[0][1]_in[65] 0 -+ 0 -**** Load for rr_node[457] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=66, type=5 ***** -Xchan_chany[0][1]_out[66]_loadlvl[0]_out chany[0][1]_out[66] chany[0][1]_out[66]_loadlvl[0]_out chany[0][1]_out[66]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[128]_no0 chany[0][1]_out[66]_loadlvl[0]_out chany[0][1]_out[66]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 chany[0][1]_out[66]_loadlvl[0]_midout chany[0][1]_out[66]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[130]_no0 chany[0][1]_out[66]_loadlvl[0]_midout chany[0][1]_out[66]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 chany[0][1]_out[66]_loadlvl[0]_midout chany[0][1]_out[66]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[67] density = 0, probability=0.***** -Vchany[0][1]_in[67] chany[0][1]_in[67] 0 -+ 0 -**** Load for rr_node[459] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=68, type=5 ***** -Xchan_chany[0][1]_out[68]_loadlvl[0]_out chany[0][1]_out[68] chany[0][1]_out[68]_loadlvl[0]_out chany[0][1]_out[68]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[132]_no0 chany[0][1]_out[68]_loadlvl[0]_out chany[0][1]_out[68]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 chany[0][1]_out[68]_loadlvl[0]_midout chany[0][1]_out[68]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 chany[0][1]_out[68]_loadlvl[0]_midout chany[0][1]_out[68]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 chany[0][1]_out[68]_loadlvl[0]_midout chany[0][1]_out[68]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[69] density = 0, probability=0.***** -Vchany[0][1]_in[69] chany[0][1]_in[69] 0 -+ 0 -**** Load for rr_node[461] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=70, type=5 ***** -Xchan_chany[0][1]_out[70]_loadlvl[0]_out chany[0][1]_out[70] chany[0][1]_out[70]_loadlvl[0]_out chany[0][1]_out[70]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[136]_no0 chany[0][1]_out[70]_loadlvl[0]_out chany[0][1]_out[70]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 chany[0][1]_out[70]_loadlvl[0]_midout chany[0][1]_out[70]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 chany[0][1]_out[70]_loadlvl[0]_midout chany[0][1]_out[70]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[71] density = 0, probability=0.***** -Vchany[0][1]_in[71] chany[0][1]_in[71] 0 -+ 0 -**** Load for rr_node[463] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=72, type=5 ***** -Xchan_chany[0][1]_out[72]_loadlvl[0]_out chany[0][1]_out[72] chany[0][1]_out[72]_loadlvl[0]_out chany[0][1]_out[72]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[139]_no0 chany[0][1]_out[72]_loadlvl[0]_out chany[0][1]_out[72]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 chany[0][1]_out[72]_loadlvl[0]_midout chany[0][1]_out[72]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 chany[0][1]_out[72]_loadlvl[0]_midout chany[0][1]_out[72]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 chany[0][1]_out[72]_loadlvl[0]_midout chany[0][1]_out[72]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 chany[0][1]_out[72]_loadlvl[0]_midout chany[0][1]_out[72]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[73] density = 0, probability=0.***** -Vchany[0][1]_in[73] chany[0][1]_in[73] 0 -+ 0 -**** Load for rr_node[465] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=74, type=5 ***** -Xchan_chany[0][1]_out[74]_loadlvl[0]_out chany[0][1]_out[74] chany[0][1]_out[74]_loadlvl[0]_out chany[0][1]_out[74]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[144]_no0 chany[0][1]_out[74]_loadlvl[0]_out chany[0][1]_out[74]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 chany[0][1]_out[74]_loadlvl[0]_midout chany[0][1]_out[74]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 chany[0][1]_out[74]_loadlvl[0]_midout chany[0][1]_out[74]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 chany[0][1]_out[74]_loadlvl[0]_midout chany[0][1]_out[74]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[75] density = 0, probability=0.***** -Vchany[0][1]_in[75] chany[0][1]_in[75] 0 -+ 0 -**** Load for rr_node[467] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=76, type=5 ***** -Xchan_chany[0][1]_out[76]_loadlvl[0]_out chany[0][1]_out[76] chany[0][1]_out[76]_loadlvl[0]_out chany[0][1]_out[76]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[148]_no0 chany[0][1]_out[76]_loadlvl[0]_out chany[0][1]_out[76]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 chany[0][1]_out[76]_loadlvl[0]_midout chany[0][1]_out[76]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 chany[0][1]_out[76]_loadlvl[0]_midout chany[0][1]_out[76]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[77] density = 0, probability=0.***** -Vchany[0][1]_in[77] chany[0][1]_in[77] 0 -+ 0 -**** Load for rr_node[469] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=78, type=5 ***** -Xchan_chany[0][1]_out[78]_loadlvl[0]_out chany[0][1]_out[78] chany[0][1]_out[78]_loadlvl[0]_out chany[0][1]_out[78]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[151]_no0 chany[0][1]_out[78]_loadlvl[0]_out chany[0][1]_out[78]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 chany[0][1]_out[78]_loadlvl[0]_midout chany[0][1]_out[78]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 chany[0][1]_out[78]_loadlvl[0]_midout chany[0][1]_out[78]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 chany[0][1]_out[78]_loadlvl[0]_midout chany[0][1]_out[78]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[79] density = 0, probability=0.***** -Vchany[0][1]_in[79] chany[0][1]_in[79] 0 -+ 0 -**** Load for rr_node[471] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=80, type=5 ***** -Xchan_chany[0][1]_out[80]_loadlvl[0]_out chany[0][1]_out[80] chany[0][1]_out[80]_loadlvl[0]_out chany[0][1]_out[80]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[155]_no0 chany[0][1]_out[80]_loadlvl[0]_out chany[0][1]_out[80]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 chany[0][1]_out[80]_loadlvl[0]_midout chany[0][1]_out[80]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 chany[0][1]_out[80]_loadlvl[0]_midout chany[0][1]_out[80]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 chany[0][1]_out[80]_loadlvl[0]_midout chany[0][1]_out[80]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[81] density = 0, probability=0.***** -Vchany[0][1]_in[81] chany[0][1]_in[81] 0 -+ 0 -**** Load for rr_node[473] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=82, type=5 ***** -Xchan_chany[0][1]_out[82]_loadlvl[0]_out chany[0][1]_out[82] chany[0][1]_out[82]_loadlvl[0]_out chany[0][1]_out[82]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[159]_no0 chany[0][1]_out[82]_loadlvl[0]_out chany[0][1]_out[82]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 chany[0][1]_out[82]_loadlvl[0]_midout chany[0][1]_out[82]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 chany[0][1]_out[82]_loadlvl[0]_midout chany[0][1]_out[82]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 chany[0][1]_out[82]_loadlvl[0]_midout chany[0][1]_out[82]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[83] density = 0, probability=0.***** -Vchany[0][1]_in[83] chany[0][1]_in[83] 0 -+ 0 -**** Load for rr_node[475] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=84, type=5 ***** -Xchan_chany[0][1]_out[84]_loadlvl[0]_out chany[0][1]_out[84] chany[0][1]_out[84]_loadlvl[0]_out chany[0][1]_out[84]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[163]_no0 chany[0][1]_out[84]_loadlvl[0]_out chany[0][1]_out[84]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 chany[0][1]_out[84]_loadlvl[0]_midout chany[0][1]_out[84]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 chany[0][1]_out[84]_loadlvl[0]_midout chany[0][1]_out[84]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 chany[0][1]_out[84]_loadlvl[0]_midout chany[0][1]_out[84]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[85] density = 0, probability=0.***** -Vchany[0][1]_in[85] chany[0][1]_in[85] 0 -+ 0 -**** Load for rr_node[477] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=86, type=5 ***** -Xchan_chany[0][1]_out[86]_loadlvl[0]_out chany[0][1]_out[86] chany[0][1]_out[86]_loadlvl[0]_out chany[0][1]_out[86]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[167]_no0 chany[0][1]_out[86]_loadlvl[0]_out chany[0][1]_out[86]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 chany[0][1]_out[86]_loadlvl[0]_midout chany[0][1]_out[86]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 chany[0][1]_out[86]_loadlvl[0]_midout chany[0][1]_out[86]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 chany[0][1]_out[86]_loadlvl[0]_midout chany[0][1]_out[86]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[87] density = 0, probability=0.***** -Vchany[0][1]_in[87] chany[0][1]_in[87] 0 -+ 0 -**** Load for rr_node[479] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=88, type=5 ***** -Xchan_chany[0][1]_out[88]_loadlvl[0]_out chany[0][1]_out[88] chany[0][1]_out[88]_loadlvl[0]_out chany[0][1]_out[88]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[171]_no0 chany[0][1]_out[88]_loadlvl[0]_out chany[0][1]_out[88]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 chany[0][1]_out[88]_loadlvl[0]_midout chany[0][1]_out[88]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 chany[0][1]_out[88]_loadlvl[0]_midout chany[0][1]_out[88]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 chany[0][1]_out[88]_loadlvl[0]_midout chany[0][1]_out[88]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[89] density = 0, probability=0.***** -Vchany[0][1]_in[89] chany[0][1]_in[89] 0 -+ 0 -**** Load for rr_node[481] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=90, type=5 ***** -Xchan_chany[0][1]_out[90]_loadlvl[0]_out chany[0][1]_out[90] chany[0][1]_out[90]_loadlvl[0]_out chany[0][1]_out[90]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[175]_no0 chany[0][1]_out[90]_loadlvl[0]_out chany[0][1]_out[90]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 chany[0][1]_out[90]_loadlvl[0]_midout chany[0][1]_out[90]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 chany[0][1]_out[90]_loadlvl[0]_midout chany[0][1]_out[90]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[91] density = 0, probability=0.***** -Vchany[0][1]_in[91] chany[0][1]_in[91] 0 -+ 0 -**** Load for rr_node[483] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=92, type=5 ***** -Xchan_chany[0][1]_out[92]_loadlvl[0]_out chany[0][1]_out[92] chany[0][1]_out[92]_loadlvl[0]_out chany[0][1]_out[92]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[178]_no0 chany[0][1]_out[92]_loadlvl[0]_out chany[0][1]_out[92]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 chany[0][1]_out[92]_loadlvl[0]_midout chany[0][1]_out[92]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[180]_no0 chany[0][1]_out[92]_loadlvl[0]_midout chany[0][1]_out[92]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 chany[0][1]_out[92]_loadlvl[0]_midout chany[0][1]_out[92]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[93] density = 0, probability=0.***** -Vchany[0][1]_in[93] chany[0][1]_in[93] 0 -+ 0 -**** Load for rr_node[485] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=94, type=5 ***** -Xchan_chany[0][1]_out[94]_loadlvl[0]_out chany[0][1]_out[94] chany[0][1]_out[94]_loadlvl[0]_out chany[0][1]_out[94]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[182]_no0 chany[0][1]_out[94]_loadlvl[0]_out chany[0][1]_out[94]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 chany[0][1]_out[94]_loadlvl[0]_midout chany[0][1]_out[94]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 chany[0][1]_out[94]_loadlvl[0]_midout chany[0][1]_out[94]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 chany[0][1]_out[94]_loadlvl[0]_midout chany[0][1]_out[94]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 chany[0][1]_out[94]_loadlvl[0]_midout chany[0][1]_out[94]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[95] density = 0, probability=0.***** -Vchany[0][1]_in[95] chany[0][1]_in[95] 0 -+ 0 -**** Load for rr_node[487] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=96, type=5 ***** -Xchan_chany[0][1]_out[96]_loadlvl[0]_out chany[0][1]_out[96] chany[0][1]_out[96]_loadlvl[0]_out chany[0][1]_out[96]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[187]_no0 chany[0][1]_out[96]_loadlvl[0]_out chany[0][1]_out[96]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 chany[0][1]_out[96]_loadlvl[0]_midout chany[0][1]_out[96]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 chany[0][1]_out[96]_loadlvl[0]_midout chany[0][1]_out[96]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[97] density = 0, probability=0.***** -Vchany[0][1]_in[97] chany[0][1]_in[97] 0 -+ 0 -**** Load for rr_node[489] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=98, type=5 ***** -Xchan_chany[0][1]_out[98]_loadlvl[0]_out chany[0][1]_out[98] chany[0][1]_out[98]_loadlvl[0]_out chany[0][1]_out[98]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[190]_no0 chany[0][1]_out[98]_loadlvl[0]_out chany[0][1]_out[98]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 chany[0][1]_out[98]_loadlvl[0]_midout chany[0][1]_out[98]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 chany[0][1]_out[98]_loadlvl[0]_midout chany[0][1]_out[98]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 chany[0][1]_out[98]_loadlvl[0]_midout chany[0][1]_out[98]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[99] density = 0, probability=0.***** -Vchany[0][1]_in[99] chany[0][1]_in[99] 0 -+ 0 -Vgrid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][1] 0 -+ 0 -Vgrid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][3] 0 -+ 0 -Vgrid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][5] 0 -+ 0 -Vgrid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][7] 0 -+ 0 -Vgrid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][9] 0 -+ 0 -Vgrid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][11] 0 -+ 0 -Vgrid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][13] 0 -+ 0 -Vgrid[0][1]_pin[0][1][15] grid[0][1]_pin[0][1][15] 0 -+ 0 -Vgrid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43] 0 -+ 0 -Vgrid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47] 0 -+ 0 - -**** Load for rr_node[191] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=0, type=4 ***** -Xchan_chanx[1][0]_out[0]_loadlvl[0]_out chanx[1][0]_out[0] chanx[1][0]_out[0]_loadlvl[0]_out chanx[1][0]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[194]_no0 chanx[1][0]_out[0]_loadlvl[0]_out chanx[1][0]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 chanx[1][0]_out[0]_loadlvl[0]_midout chanx[1][0]_out[0]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 chanx[1][0]_out[0]_loadlvl[0]_midout chanx[1][0]_out[0]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 chanx[1][0]_out[0]_loadlvl[0]_midout chanx[1][0]_out[0]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 chanx[1][0]_out[0]_loadlvl[0]_midout chanx[1][0]_out[0]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[1] density = 0, probability=0.***** -Vchanx[1][0]_in[1] chanx[1][0]_in[1] 0 -+ 0 -**** Load for rr_node[193] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=2, type=4 ***** -Xchan_chanx[1][0]_out[2]_loadlvl[0]_out chanx[1][0]_out[2] chanx[1][0]_out[2]_loadlvl[0]_out chanx[1][0]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[199]_no0 chanx[1][0]_out[2]_loadlvl[0]_out chanx[1][0]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 chanx[1][0]_out[2]_loadlvl[0]_midout chanx[1][0]_out[2]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 chanx[1][0]_out[2]_loadlvl[0]_midout chanx[1][0]_out[2]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[3] density = 0, probability=0.***** -Vchanx[1][0]_in[3] chanx[1][0]_in[3] 0 -+ 0 -**** Load for rr_node[195] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=4, type=4 ***** -Xchan_chanx[1][0]_out[4]_loadlvl[0]_out chanx[1][0]_out[4] chanx[1][0]_out[4]_loadlvl[0]_out chanx[1][0]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[202]_no0 chanx[1][0]_out[4]_loadlvl[0]_out chanx[1][0]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 chanx[1][0]_out[4]_loadlvl[0]_midout chanx[1][0]_out[4]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 chanx[1][0]_out[4]_loadlvl[0]_midout chanx[1][0]_out[4]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 chanx[1][0]_out[4]_loadlvl[0]_midout chanx[1][0]_out[4]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[5] density = 0, probability=0.***** -Vchanx[1][0]_in[5] chanx[1][0]_in[5] 0 -+ 0 -**** Load for rr_node[197] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=6, type=4 ***** -Xchan_chanx[1][0]_out[6]_loadlvl[0]_out chanx[1][0]_out[6] chanx[1][0]_out[6]_loadlvl[0]_out chanx[1][0]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[206]_no0 chanx[1][0]_out[6]_loadlvl[0]_out chanx[1][0]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 chanx[1][0]_out[6]_loadlvl[0]_midout chanx[1][0]_out[6]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 chanx[1][0]_out[6]_loadlvl[0]_midout chanx[1][0]_out[6]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 chanx[1][0]_out[6]_loadlvl[0]_midout chanx[1][0]_out[6]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[7] density = 0, probability=0.***** -Vchanx[1][0]_in[7] chanx[1][0]_in[7] 0 -+ 0 -**** Load for rr_node[199] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=8, type=4 ***** -Xchan_chanx[1][0]_out[8]_loadlvl[0]_out chanx[1][0]_out[8] chanx[1][0]_out[8]_loadlvl[0]_out chanx[1][0]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[210]_no0 chanx[1][0]_out[8]_loadlvl[0]_out chanx[1][0]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 chanx[1][0]_out[8]_loadlvl[0]_midout chanx[1][0]_out[8]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 chanx[1][0]_out[8]_loadlvl[0]_midout chanx[1][0]_out[8]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 chanx[1][0]_out[8]_loadlvl[0]_midout chanx[1][0]_out[8]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[9] density = 0, probability=0.***** -Vchanx[1][0]_in[9] chanx[1][0]_in[9] 0 -+ 0 -**** Load for rr_node[201] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=10, type=4 ***** -Xchan_chanx[1][0]_out[10]_loadlvl[0]_out chanx[1][0]_out[10] chanx[1][0]_out[10]_loadlvl[0]_out chanx[1][0]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[214]_no0 chanx[1][0]_out[10]_loadlvl[0]_out chanx[1][0]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 chanx[1][0]_out[10]_loadlvl[0]_midout chanx[1][0]_out[10]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 chanx[1][0]_out[10]_loadlvl[0]_midout chanx[1][0]_out[10]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 chanx[1][0]_out[10]_loadlvl[0]_midout chanx[1][0]_out[10]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[11] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_in[11] chanx[1][0]_in[11] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[203] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=12, type=4 ***** -Xchan_chanx[1][0]_out[12]_loadlvl[0]_out chanx[1][0]_out[12] chanx[1][0]_out[12]_loadlvl[0]_out chanx[1][0]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[218]_no0 chanx[1][0]_out[12]_loadlvl[0]_out chanx[1][0]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 chanx[1][0]_out[12]_loadlvl[0]_midout chanx[1][0]_out[12]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 chanx[1][0]_out[12]_loadlvl[0]_midout chanx[1][0]_out[12]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[13] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_in[13] chanx[1][0]_in[13] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[205] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=14, type=4 ***** -Xchan_chanx[1][0]_out[14]_loadlvl[0]_out chanx[1][0]_out[14] chanx[1][0]_out[14]_loadlvl[0]_out chanx[1][0]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[221]_no0 chanx[1][0]_out[14]_loadlvl[0]_out chanx[1][0]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 chanx[1][0]_out[14]_loadlvl[0]_midout chanx[1][0]_out[14]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 chanx[1][0]_out[14]_loadlvl[0]_midout chanx[1][0]_out[14]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 chanx[1][0]_out[14]_loadlvl[0]_midout chanx[1][0]_out[14]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 chanx[1][0]_out[14]_loadlvl[0]_midout chanx[1][0]_out[14]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[15] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_in[15] chanx[1][0]_in[15] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[207] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=16, type=4 ***** -Xchan_chanx[1][0]_out[16]_loadlvl[0]_out chanx[1][0]_out[16] chanx[1][0]_out[16]_loadlvl[0]_out chanx[1][0]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[226]_no0 chanx[1][0]_out[16]_loadlvl[0]_out chanx[1][0]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 chanx[1][0]_out[16]_loadlvl[0]_midout chanx[1][0]_out[16]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 chanx[1][0]_out[16]_loadlvl[0]_midout chanx[1][0]_out[16]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[17] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_in[17] chanx[1][0]_in[17] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[209] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=18, type=4 ***** -Xchan_chanx[1][0]_out[18]_loadlvl[0]_out chanx[1][0]_out[18] chanx[1][0]_out[18]_loadlvl[0]_out chanx[1][0]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[229]_no0 chanx[1][0]_out[18]_loadlvl[0]_out chanx[1][0]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 chanx[1][0]_out[18]_loadlvl[0]_midout chanx[1][0]_out[18]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 chanx[1][0]_out[18]_loadlvl[0]_midout chanx[1][0]_out[18]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 chanx[1][0]_out[18]_loadlvl[0]_midout chanx[1][0]_out[18]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[19] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_in[19] chanx[1][0]_in[19] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[211] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=20, type=4 ***** -Xchan_chanx[1][0]_out[20]_loadlvl[0]_out chanx[1][0]_out[20] chanx[1][0]_out[20]_loadlvl[0]_out chanx[1][0]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[233]_no0 chanx[1][0]_out[20]_loadlvl[0]_out chanx[1][0]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 chanx[1][0]_out[20]_loadlvl[0]_midout chanx[1][0]_out[20]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 chanx[1][0]_out[20]_loadlvl[0]_midout chanx[1][0]_out[20]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 chanx[1][0]_out[20]_loadlvl[0]_midout chanx[1][0]_out[20]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 chanx[1][0]_out[20]_loadlvl[0]_midout chanx[1][0]_out[20]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[21] density = 0, probability=0.***** -Vchanx[1][0]_in[21] chanx[1][0]_in[21] 0 -+ 0 -**** Load for rr_node[213] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=22, type=4 ***** -Xchan_chanx[1][0]_out[22]_loadlvl[0]_out chanx[1][0]_out[22] chanx[1][0]_out[22]_loadlvl[0]_out chanx[1][0]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[238]_no0 chanx[1][0]_out[22]_loadlvl[0]_out chanx[1][0]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 chanx[1][0]_out[22]_loadlvl[0]_midout chanx[1][0]_out[22]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[240]_no0 chanx[1][0]_out[22]_loadlvl[0]_midout chanx[1][0]_out[22]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[23] density = 0, probability=0.***** -Vchanx[1][0]_in[23] chanx[1][0]_in[23] 0 -+ 0 -**** Load for rr_node[215] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=24, type=4 ***** -Xchan_chanx[1][0]_out[24]_loadlvl[0]_out chanx[1][0]_out[24] chanx[1][0]_out[24]_loadlvl[0]_out chanx[1][0]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[241]_no0 chanx[1][0]_out[24]_loadlvl[0]_out chanx[1][0]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 chanx[1][0]_out[24]_loadlvl[0]_midout chanx[1][0]_out[24]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 chanx[1][0]_out[24]_loadlvl[0]_midout chanx[1][0]_out[24]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 chanx[1][0]_out[24]_loadlvl[0]_midout chanx[1][0]_out[24]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[25] density = 0, probability=0.***** -Vchanx[1][0]_in[25] chanx[1][0]_in[25] 0 -+ 0 -**** Load for rr_node[217] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=26, type=4 ***** -Xchan_chanx[1][0]_out[26]_loadlvl[0]_out chanx[1][0]_out[26] chanx[1][0]_out[26]_loadlvl[0]_out chanx[1][0]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[245]_no0 chanx[1][0]_out[26]_loadlvl[0]_out chanx[1][0]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 chanx[1][0]_out[26]_loadlvl[0]_midout chanx[1][0]_out[26]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 chanx[1][0]_out[26]_loadlvl[0]_midout chanx[1][0]_out[26]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[27] density = 0, probability=0.***** -Vchanx[1][0]_in[27] chanx[1][0]_in[27] 0 -+ 0 -**** Load for rr_node[219] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=28, type=4 ***** -Xchan_chanx[1][0]_out[28]_loadlvl[0]_out chanx[1][0]_out[28] chanx[1][0]_out[28]_loadlvl[0]_out chanx[1][0]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[248]_no0 chanx[1][0]_out[28]_loadlvl[0]_out chanx[1][0]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 chanx[1][0]_out[28]_loadlvl[0]_midout chanx[1][0]_out[28]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 chanx[1][0]_out[28]_loadlvl[0]_midout chanx[1][0]_out[28]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 chanx[1][0]_out[28]_loadlvl[0]_midout chanx[1][0]_out[28]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 chanx[1][0]_out[28]_loadlvl[0]_midout chanx[1][0]_out[28]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[29] density = 0, probability=0.***** -Vchanx[1][0]_in[29] chanx[1][0]_in[29] 0 -+ 0 -**** Load for rr_node[221] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=30, type=4 ***** -Xchan_chanx[1][0]_out[30]_loadlvl[0]_out chanx[1][0]_out[30] chanx[1][0]_out[30]_loadlvl[0]_out chanx[1][0]_out[30]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[253]_no0 chanx[1][0]_out[30]_loadlvl[0]_out chanx[1][0]_out[30]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 chanx[1][0]_out[30]_loadlvl[0]_midout chanx[1][0]_out[30]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 chanx[1][0]_out[30]_loadlvl[0]_midout chanx[1][0]_out[30]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 chanx[1][0]_out[30]_loadlvl[0]_midout chanx[1][0]_out[30]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[31] density = 0, probability=0.***** -Vchanx[1][0]_in[31] chanx[1][0]_in[31] 0 -+ 0 -**** Load for rr_node[223] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=32, type=4 ***** -Xchan_chanx[1][0]_out[32]_loadlvl[0]_out chanx[1][0]_out[32] chanx[1][0]_out[32]_loadlvl[0]_out chanx[1][0]_out[32]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[257]_no0 chanx[1][0]_out[32]_loadlvl[0]_out chanx[1][0]_out[32]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 chanx[1][0]_out[32]_loadlvl[0]_midout chanx[1][0]_out[32]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 chanx[1][0]_out[32]_loadlvl[0]_midout chanx[1][0]_out[32]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[33] density = 0, probability=0.***** -Vchanx[1][0]_in[33] chanx[1][0]_in[33] 0 -+ 0 -**** Load for rr_node[225] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=34, type=4 ***** -Xchan_chanx[1][0]_out[34]_loadlvl[0]_out chanx[1][0]_out[34] chanx[1][0]_out[34]_loadlvl[0]_out chanx[1][0]_out[34]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[260]_no0 chanx[1][0]_out[34]_loadlvl[0]_out chanx[1][0]_out[34]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 chanx[1][0]_out[34]_loadlvl[0]_midout chanx[1][0]_out[34]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 chanx[1][0]_out[34]_loadlvl[0]_midout chanx[1][0]_out[34]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 chanx[1][0]_out[34]_loadlvl[0]_midout chanx[1][0]_out[34]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 chanx[1][0]_out[34]_loadlvl[0]_midout chanx[1][0]_out[34]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[35] density = 0, probability=0.***** -Vchanx[1][0]_in[35] chanx[1][0]_in[35] 0 -+ 0 -**** Load for rr_node[227] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=36, type=4 ***** -Xchan_chanx[1][0]_out[36]_loadlvl[0]_out chanx[1][0]_out[36] chanx[1][0]_out[36]_loadlvl[0]_out chanx[1][0]_out[36]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[265]_no0 chanx[1][0]_out[36]_loadlvl[0]_out chanx[1][0]_out[36]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 chanx[1][0]_out[36]_loadlvl[0]_midout chanx[1][0]_out[36]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 chanx[1][0]_out[36]_loadlvl[0]_midout chanx[1][0]_out[36]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[37] density = 0, probability=0.***** -Vchanx[1][0]_in[37] chanx[1][0]_in[37] 0 -+ 0 -**** Load for rr_node[229] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=38, type=4 ***** -Xchan_chanx[1][0]_out[38]_loadlvl[0]_out chanx[1][0]_out[38] chanx[1][0]_out[38]_loadlvl[0]_out chanx[1][0]_out[38]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[268]_no0 chanx[1][0]_out[38]_loadlvl[0]_out chanx[1][0]_out[38]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 chanx[1][0]_out[38]_loadlvl[0]_midout chanx[1][0]_out[38]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 chanx[1][0]_out[38]_loadlvl[0]_midout chanx[1][0]_out[38]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 chanx[1][0]_out[38]_loadlvl[0]_midout chanx[1][0]_out[38]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[39] density = 0, probability=0.***** -Vchanx[1][0]_in[39] chanx[1][0]_in[39] 0 -+ 0 -**** Load for rr_node[231] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=40, type=4 ***** -Xchan_chanx[1][0]_out[40]_loadlvl[0]_out chanx[1][0]_out[40] chanx[1][0]_out[40]_loadlvl[0]_out chanx[1][0]_out[40]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[272]_no0 chanx[1][0]_out[40]_loadlvl[0]_out chanx[1][0]_out[40]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 chanx[1][0]_out[40]_loadlvl[0]_midout chanx[1][0]_out[40]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 chanx[1][0]_out[40]_loadlvl[0]_midout chanx[1][0]_out[40]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 chanx[1][0]_out[40]_loadlvl[0]_midout chanx[1][0]_out[40]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[41] density = 0, probability=0.***** -Vchanx[1][0]_in[41] chanx[1][0]_in[41] 0 -+ 0 -**** Load for rr_node[233] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=42, type=4 ***** -Xchan_chanx[1][0]_out[42]_loadlvl[0]_out chanx[1][0]_out[42] chanx[1][0]_out[42]_loadlvl[0]_out chanx[1][0]_out[42]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[276]_no0 chanx[1][0]_out[42]_loadlvl[0]_out chanx[1][0]_out[42]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 chanx[1][0]_out[42]_loadlvl[0]_midout chanx[1][0]_out[42]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 chanx[1][0]_out[42]_loadlvl[0]_midout chanx[1][0]_out[42]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 chanx[1][0]_out[42]_loadlvl[0]_midout chanx[1][0]_out[42]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[43] density = 0, probability=0.***** -Vchanx[1][0]_in[43] chanx[1][0]_in[43] 0 -+ 0 -**** Load for rr_node[235] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=44, type=4 ***** -Xchan_chanx[1][0]_out[44]_loadlvl[0]_out chanx[1][0]_out[44] chanx[1][0]_out[44]_loadlvl[0]_out chanx[1][0]_out[44]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[280]_no0 chanx[1][0]_out[44]_loadlvl[0]_out chanx[1][0]_out[44]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 chanx[1][0]_out[44]_loadlvl[0]_midout chanx[1][0]_out[44]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 chanx[1][0]_out[44]_loadlvl[0]_midout chanx[1][0]_out[44]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 chanx[1][0]_out[44]_loadlvl[0]_midout chanx[1][0]_out[44]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[45] density = 0, probability=0.***** -Vchanx[1][0]_in[45] chanx[1][0]_in[45] 0 -+ 0 -**** Load for rr_node[237] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=46, type=4 ***** -Xchan_chanx[1][0]_out[46]_loadlvl[0]_out chanx[1][0]_out[46] chanx[1][0]_out[46]_loadlvl[0]_out chanx[1][0]_out[46]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[284]_no0 chanx[1][0]_out[46]_loadlvl[0]_out chanx[1][0]_out[46]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 chanx[1][0]_out[46]_loadlvl[0]_midout chanx[1][0]_out[46]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 chanx[1][0]_out[46]_loadlvl[0]_midout chanx[1][0]_out[46]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[47] density = 0, probability=0.***** -Vchanx[1][0]_in[47] chanx[1][0]_in[47] 0 -+ 0 -**** Load for rr_node[239] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=48, type=4 ***** -Xchan_chanx[1][0]_out[48]_loadlvl[0]_out chanx[1][0]_out[48] chanx[1][0]_out[48]_loadlvl[0]_out chanx[1][0]_out[48]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[287]_no0 chanx[1][0]_out[48]_loadlvl[0]_out chanx[1][0]_out[48]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 chanx[1][0]_out[48]_loadlvl[0]_midout chanx[1][0]_out[48]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 chanx[1][0]_out[48]_loadlvl[0]_midout chanx[1][0]_out[48]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 chanx[1][0]_out[48]_loadlvl[0]_midout chanx[1][0]_out[48]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[49] density = 0, probability=0.***** -Vchanx[1][0]_in[49] chanx[1][0]_in[49] 0 -+ 0 -**** Load for rr_node[241] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=50, type=4 ***** -Xchan_chanx[1][0]_out[50]_loadlvl[0]_out chanx[1][0]_out[50] chanx[1][0]_out[50]_loadlvl[0]_out chanx[1][0]_out[50]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[291]_no0 chanx[1][0]_out[50]_loadlvl[0]_out chanx[1][0]_out[50]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 chanx[1][0]_out[50]_loadlvl[0]_midout chanx[1][0]_out[50]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 chanx[1][0]_out[50]_loadlvl[0]_midout chanx[1][0]_out[50]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 chanx[1][0]_out[50]_loadlvl[0]_midout chanx[1][0]_out[50]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 chanx[1][0]_out[50]_loadlvl[0]_midout chanx[1][0]_out[50]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[51] density = 0, probability=0.***** -Vchanx[1][0]_in[51] chanx[1][0]_in[51] 0 -+ 0 -**** Load for rr_node[243] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=52, type=4 ***** -Xchan_chanx[1][0]_out[52]_loadlvl[0]_out chanx[1][0]_out[52] chanx[1][0]_out[52]_loadlvl[0]_out chanx[1][0]_out[52]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[296]_no0 chanx[1][0]_out[52]_loadlvl[0]_out chanx[1][0]_out[52]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 chanx[1][0]_out[52]_loadlvl[0]_midout chanx[1][0]_out[52]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 chanx[1][0]_out[52]_loadlvl[0]_midout chanx[1][0]_out[52]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[53] density = 0, probability=0.***** -Vchanx[1][0]_in[53] chanx[1][0]_in[53] 0 -+ 0 -**** Load for rr_node[245] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=54, type=4 ***** -Xchan_chanx[1][0]_out[54]_loadlvl[0]_out chanx[1][0]_out[54] chanx[1][0]_out[54]_loadlvl[0]_out chanx[1][0]_out[54]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[299]_no0 chanx[1][0]_out[54]_loadlvl[0]_out chanx[1][0]_out[54]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[300]_no0 chanx[1][0]_out[54]_loadlvl[0]_midout chanx[1][0]_out[54]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 chanx[1][0]_out[54]_loadlvl[0]_midout chanx[1][0]_out[54]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 chanx[1][0]_out[54]_loadlvl[0]_midout chanx[1][0]_out[54]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[55] density = 0, probability=0.***** -Vchanx[1][0]_in[55] chanx[1][0]_in[55] 0 -+ 0 -**** Load for rr_node[247] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=56, type=4 ***** -Xchan_chanx[1][0]_out[56]_loadlvl[0]_out chanx[1][0]_out[56] chanx[1][0]_out[56]_loadlvl[0]_out chanx[1][0]_out[56]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[303]_no0 chanx[1][0]_out[56]_loadlvl[0]_out chanx[1][0]_out[56]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 chanx[1][0]_out[56]_loadlvl[0]_midout chanx[1][0]_out[56]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 chanx[1][0]_out[56]_loadlvl[0]_midout chanx[1][0]_out[56]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 chanx[1][0]_out[56]_loadlvl[0]_midout chanx[1][0]_out[56]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[57] density = 0, probability=0.***** -Vchanx[1][0]_in[57] chanx[1][0]_in[57] 0 -+ 0 -**** Load for rr_node[249] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=58, type=4 ***** -Xchan_chanx[1][0]_out[58]_loadlvl[0]_out chanx[1][0]_out[58] chanx[1][0]_out[58]_loadlvl[0]_out chanx[1][0]_out[58]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[307]_no0 chanx[1][0]_out[58]_loadlvl[0]_out chanx[1][0]_out[58]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 chanx[1][0]_out[58]_loadlvl[0]_midout chanx[1][0]_out[58]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 chanx[1][0]_out[58]_loadlvl[0]_midout chanx[1][0]_out[58]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 chanx[1][0]_out[58]_loadlvl[0]_midout chanx[1][0]_out[58]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[59] density = 0, probability=0.***** -Vchanx[1][0]_in[59] chanx[1][0]_in[59] 0 -+ 0 -**** Load for rr_node[251] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=60, type=4 ***** -Xchan_chanx[1][0]_out[60]_loadlvl[0]_out chanx[1][0]_out[60] chanx[1][0]_out[60]_loadlvl[0]_out chanx[1][0]_out[60]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[311]_no0 chanx[1][0]_out[60]_loadlvl[0]_out chanx[1][0]_out[60]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 chanx[1][0]_out[60]_loadlvl[0]_midout chanx[1][0]_out[60]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 chanx[1][0]_out[60]_loadlvl[0]_midout chanx[1][0]_out[60]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 chanx[1][0]_out[60]_loadlvl[0]_midout chanx[1][0]_out[60]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[61] density = 0, probability=0.***** -Vchanx[1][0]_in[61] chanx[1][0]_in[61] 0 -+ 0 -**** Load for rr_node[253] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=62, type=4 ***** -Xchan_chanx[1][0]_out[62]_loadlvl[0]_out chanx[1][0]_out[62] chanx[1][0]_out[62]_loadlvl[0]_out chanx[1][0]_out[62]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[315]_no0 chanx[1][0]_out[62]_loadlvl[0]_out chanx[1][0]_out[62]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 chanx[1][0]_out[62]_loadlvl[0]_midout chanx[1][0]_out[62]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 chanx[1][0]_out[62]_loadlvl[0]_midout chanx[1][0]_out[62]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[63] density = 0, probability=0.***** -Vchanx[1][0]_in[63] chanx[1][0]_in[63] 0 -+ 0 -**** Load for rr_node[255] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=64, type=4 ***** -Xchan_chanx[1][0]_out[64]_loadlvl[0]_out chanx[1][0]_out[64] chanx[1][0]_out[64]_loadlvl[0]_out chanx[1][0]_out[64]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[318]_no0 chanx[1][0]_out[64]_loadlvl[0]_out chanx[1][0]_out[64]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 chanx[1][0]_out[64]_loadlvl[0]_midout chanx[1][0]_out[64]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 chanx[1][0]_out[64]_loadlvl[0]_midout chanx[1][0]_out[64]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 chanx[1][0]_out[64]_loadlvl[0]_midout chanx[1][0]_out[64]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 chanx[1][0]_out[64]_loadlvl[0]_midout chanx[1][0]_out[64]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[65] density = 0, probability=0.***** -Vchanx[1][0]_in[65] chanx[1][0]_in[65] 0 -+ 0 -**** Load for rr_node[257] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=66, type=4 ***** -Xchan_chanx[1][0]_out[66]_loadlvl[0]_out chanx[1][0]_out[66] chanx[1][0]_out[66]_loadlvl[0]_out chanx[1][0]_out[66]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[323]_no0 chanx[1][0]_out[66]_loadlvl[0]_out chanx[1][0]_out[66]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 chanx[1][0]_out[66]_loadlvl[0]_midout chanx[1][0]_out[66]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 chanx[1][0]_out[66]_loadlvl[0]_midout chanx[1][0]_out[66]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[67] density = 0, probability=0.***** -Vchanx[1][0]_in[67] chanx[1][0]_in[67] 0 -+ 0 -**** Load for rr_node[259] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=68, type=4 ***** -Xchan_chanx[1][0]_out[68]_loadlvl[0]_out chanx[1][0]_out[68] chanx[1][0]_out[68]_loadlvl[0]_out chanx[1][0]_out[68]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[326]_no0 chanx[1][0]_out[68]_loadlvl[0]_out chanx[1][0]_out[68]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 chanx[1][0]_out[68]_loadlvl[0]_midout chanx[1][0]_out[68]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 chanx[1][0]_out[68]_loadlvl[0]_midout chanx[1][0]_out[68]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 chanx[1][0]_out[68]_loadlvl[0]_midout chanx[1][0]_out[68]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[69] density = 0, probability=0.***** -Vchanx[1][0]_in[69] chanx[1][0]_in[69] 0 -+ 0 -**** Load for rr_node[261] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=70, type=4 ***** -Xchan_chanx[1][0]_out[70]_loadlvl[0]_out chanx[1][0]_out[70] chanx[1][0]_out[70]_loadlvl[0]_out chanx[1][0]_out[70]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[330]_no0 chanx[1][0]_out[70]_loadlvl[0]_out chanx[1][0]_out[70]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 chanx[1][0]_out[70]_loadlvl[0]_midout chanx[1][0]_out[70]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 chanx[1][0]_out[70]_loadlvl[0]_midout chanx[1][0]_out[70]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[333]_no0 chanx[1][0]_out[70]_loadlvl[0]_midout chanx[1][0]_out[70]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 chanx[1][0]_out[70]_loadlvl[0]_midout chanx[1][0]_out[70]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[71] density = 0, probability=0.***** -Vchanx[1][0]_in[71] chanx[1][0]_in[71] 0 -+ 0 -**** Load for rr_node[263] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=72, type=4 ***** -Xchan_chanx[1][0]_out[72]_loadlvl[0]_out chanx[1][0]_out[72] chanx[1][0]_out[72]_loadlvl[0]_out chanx[1][0]_out[72]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[335]_no0 chanx[1][0]_out[72]_loadlvl[0]_out chanx[1][0]_out[72]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 chanx[1][0]_out[72]_loadlvl[0]_midout chanx[1][0]_out[72]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 chanx[1][0]_out[72]_loadlvl[0]_midout chanx[1][0]_out[72]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[73] density = 0, probability=0.***** -Vchanx[1][0]_in[73] chanx[1][0]_in[73] 0 -+ 0 -**** Load for rr_node[265] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=74, type=4 ***** -Xchan_chanx[1][0]_out[74]_loadlvl[0]_out chanx[1][0]_out[74] chanx[1][0]_out[74]_loadlvl[0]_out chanx[1][0]_out[74]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[338]_no0 chanx[1][0]_out[74]_loadlvl[0]_out chanx[1][0]_out[74]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 chanx[1][0]_out[74]_loadlvl[0]_midout chanx[1][0]_out[74]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 chanx[1][0]_out[74]_loadlvl[0]_midout chanx[1][0]_out[74]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 chanx[1][0]_out[74]_loadlvl[0]_midout chanx[1][0]_out[74]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[75] density = 0, probability=0.***** -Vchanx[1][0]_in[75] chanx[1][0]_in[75] 0 -+ 0 -**** Load for rr_node[267] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=76, type=4 ***** -Xchan_chanx[1][0]_out[76]_loadlvl[0]_out chanx[1][0]_out[76] chanx[1][0]_out[76]_loadlvl[0]_out chanx[1][0]_out[76]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[342]_no0 chanx[1][0]_out[76]_loadlvl[0]_out chanx[1][0]_out[76]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 chanx[1][0]_out[76]_loadlvl[0]_midout chanx[1][0]_out[76]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 chanx[1][0]_out[76]_loadlvl[0]_midout chanx[1][0]_out[76]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[77] density = 0, probability=0.***** -Vchanx[1][0]_in[77] chanx[1][0]_in[77] 0 -+ 0 -**** Load for rr_node[269] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=78, type=4 ***** -Xchan_chanx[1][0]_out[78]_loadlvl[0]_out chanx[1][0]_out[78] chanx[1][0]_out[78]_loadlvl[0]_out chanx[1][0]_out[78]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[345]_no0 chanx[1][0]_out[78]_loadlvl[0]_out chanx[1][0]_out[78]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 chanx[1][0]_out[78]_loadlvl[0]_midout chanx[1][0]_out[78]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 chanx[1][0]_out[78]_loadlvl[0]_midout chanx[1][0]_out[78]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 chanx[1][0]_out[78]_loadlvl[0]_midout chanx[1][0]_out[78]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[349]_no0 chanx[1][0]_out[78]_loadlvl[0]_midout chanx[1][0]_out[78]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[79] density = 0.2026, probability=0.4982.***** -Vchanx[1][0]_in[79] chanx[1][0]_in[79] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[271] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=80, type=4 ***** -Xchan_chanx[1][0]_out[80]_loadlvl[0]_out chanx[1][0]_out[80] chanx[1][0]_out[80]_loadlvl[0]_out chanx[1][0]_out[80]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[350]_no0 chanx[1][0]_out[80]_loadlvl[0]_out chanx[1][0]_out[80]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 chanx[1][0]_out[80]_loadlvl[0]_midout chanx[1][0]_out[80]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 chanx[1][0]_out[80]_loadlvl[0]_midout chanx[1][0]_out[80]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[353]_no0 chanx[1][0]_out[80]_loadlvl[0]_midout chanx[1][0]_out[80]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[81] density = 0, probability=0.***** -Vchanx[1][0]_in[81] chanx[1][0]_in[81] 0 -+ 0 -**** Load for rr_node[273] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=82, type=4 ***** -Xchan_chanx[1][0]_out[82]_loadlvl[0]_out chanx[1][0]_out[82] chanx[1][0]_out[82]_loadlvl[0]_out chanx[1][0]_out[82]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[354]_no0 chanx[1][0]_out[82]_loadlvl[0]_out chanx[1][0]_out[82]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 chanx[1][0]_out[82]_loadlvl[0]_midout chanx[1][0]_out[82]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 chanx[1][0]_out[82]_loadlvl[0]_midout chanx[1][0]_out[82]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[83] density = 0, probability=0.***** -Vchanx[1][0]_in[83] chanx[1][0]_in[83] 0 -+ 0 -**** Load for rr_node[275] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=84, type=4 ***** -Xchan_chanx[1][0]_out[84]_loadlvl[0]_out chanx[1][0]_out[84] chanx[1][0]_out[84]_loadlvl[0]_out chanx[1][0]_out[84]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[357]_no0 chanx[1][0]_out[84]_loadlvl[0]_out chanx[1][0]_out[84]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 chanx[1][0]_out[84]_loadlvl[0]_midout chanx[1][0]_out[84]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 chanx[1][0]_out[84]_loadlvl[0]_midout chanx[1][0]_out[84]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[360]_no0 chanx[1][0]_out[84]_loadlvl[0]_midout chanx[1][0]_out[84]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[361]_no0 chanx[1][0]_out[84]_loadlvl[0]_midout chanx[1][0]_out[84]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[85] density = 0, probability=0.***** -Vchanx[1][0]_in[85] chanx[1][0]_in[85] 0 -+ 0 -**** Load for rr_node[277] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=86, type=4 ***** -Xchan_chanx[1][0]_out[86]_loadlvl[0]_out chanx[1][0]_out[86] chanx[1][0]_out[86]_loadlvl[0]_out chanx[1][0]_out[86]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[362]_no0 chanx[1][0]_out[86]_loadlvl[0]_out chanx[1][0]_out[86]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 chanx[1][0]_out[86]_loadlvl[0]_midout chanx[1][0]_out[86]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 chanx[1][0]_out[86]_loadlvl[0]_midout chanx[1][0]_out[86]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[87] density = 0, probability=0.***** -Vchanx[1][0]_in[87] chanx[1][0]_in[87] 0 -+ 0 -**** Load for rr_node[279] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=88, type=4 ***** -Xchan_chanx[1][0]_out[88]_loadlvl[0]_out chanx[1][0]_out[88] chanx[1][0]_out[88]_loadlvl[0]_out chanx[1][0]_out[88]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[365]_no0 chanx[1][0]_out[88]_loadlvl[0]_out chanx[1][0]_out[88]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 chanx[1][0]_out[88]_loadlvl[0]_midout chanx[1][0]_out[88]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 chanx[1][0]_out[88]_loadlvl[0]_midout chanx[1][0]_out[88]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 chanx[1][0]_out[88]_loadlvl[0]_midout chanx[1][0]_out[88]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[89] density = 0, probability=0.***** -Vchanx[1][0]_in[89] chanx[1][0]_in[89] 0 -+ 0 -**** Load for rr_node[281] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=90, type=4 ***** -Xchan_chanx[1][0]_out[90]_loadlvl[0]_out chanx[1][0]_out[90] chanx[1][0]_out[90]_loadlvl[0]_out chanx[1][0]_out[90]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[369]_no0 chanx[1][0]_out[90]_loadlvl[0]_out chanx[1][0]_out[90]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 chanx[1][0]_out[90]_loadlvl[0]_midout chanx[1][0]_out[90]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 chanx[1][0]_out[90]_loadlvl[0]_midout chanx[1][0]_out[90]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[372]_no0 chanx[1][0]_out[90]_loadlvl[0]_midout chanx[1][0]_out[90]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[91] density = 0, probability=0.***** -Vchanx[1][0]_in[91] chanx[1][0]_in[91] 0 -+ 0 -**** Load for rr_node[283] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=92, type=4 ***** -Xchan_chanx[1][0]_out[92]_loadlvl[0]_out chanx[1][0]_out[92] chanx[1][0]_out[92]_loadlvl[0]_out chanx[1][0]_out[92]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[373]_no0 chanx[1][0]_out[92]_loadlvl[0]_out chanx[1][0]_out[92]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 chanx[1][0]_out[92]_loadlvl[0]_midout chanx[1][0]_out[92]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 chanx[1][0]_out[92]_loadlvl[0]_midout chanx[1][0]_out[92]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[376]_no0 chanx[1][0]_out[92]_loadlvl[0]_midout chanx[1][0]_out[92]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[93] density = 0, probability=0.***** -Vchanx[1][0]_in[93] chanx[1][0]_in[93] 0 -+ 0 -**** Load for rr_node[285] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=94, type=4 ***** -Xchan_chanx[1][0]_out[94]_loadlvl[0]_out chanx[1][0]_out[94] chanx[1][0]_out[94]_loadlvl[0]_out chanx[1][0]_out[94]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[377]_no0 chanx[1][0]_out[94]_loadlvl[0]_out chanx[1][0]_out[94]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 chanx[1][0]_out[94]_loadlvl[0]_midout chanx[1][0]_out[94]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 chanx[1][0]_out[94]_loadlvl[0]_midout chanx[1][0]_out[94]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 chanx[1][0]_out[94]_loadlvl[0]_midout chanx[1][0]_out[94]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[95] density = 0, probability=0.***** -Vchanx[1][0]_in[95] chanx[1][0]_in[95] 0 -+ 0 -**** Load for rr_node[287] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=96, type=4 ***** -Xchan_chanx[1][0]_out[96]_loadlvl[0]_out chanx[1][0]_out[96] chanx[1][0]_out[96]_loadlvl[0]_out chanx[1][0]_out[96]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[381]_no0 chanx[1][0]_out[96]_loadlvl[0]_out chanx[1][0]_out[96]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 chanx[1][0]_out[96]_loadlvl[0]_midout chanx[1][0]_out[96]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 chanx[1][0]_out[96]_loadlvl[0]_midout chanx[1][0]_out[96]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[97] density = 0, probability=0.***** -Vchanx[1][0]_in[97] chanx[1][0]_in[97] 0 -+ 0 -**** Load for rr_node[289] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=98, type=4 ***** -Xchan_chanx[1][0]_out[98]_loadlvl[0]_out chanx[1][0]_out[98] chanx[1][0]_out[98]_loadlvl[0]_out chanx[1][0]_out[98]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[384]_no0 chanx[1][0]_out[98]_loadlvl[0]_out chanx[1][0]_out[98]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 chanx[1][0]_out[98]_loadlvl[0]_midout chanx[1][0]_out[98]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 chanx[1][0]_out[98]_loadlvl[0]_midout chanx[1][0]_out[98]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 chanx[1][0]_out[98]_loadlvl[0]_midout chanx[1][0]_out[98]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[99] density = 0, probability=0.***** -Vchanx[1][0]_in[99] chanx[1][0]_in[99] 0 -+ 0 -Vgrid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42] 0 -+ 0 -Vgrid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46] 0 -+ 0 -Vgrid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][1] 0 -+ 0 -Vgrid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgrid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][5] 0 -+ 0 -Vgrid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][7] 0 -+ 0 -Vgrid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][9] 0 -+ 0 -Vgrid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][11] 0 -+ 0 -Vgrid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][13] 0 -+ 0 -Vgrid[1][0]_pin[0][0][15] grid[1][0]_pin[0][0][15] 0 -+ 0 - - - -***** Voltage supplies ***** -Vgvdd_sb[0][0] gvdd_sb[0][0] 0 vsp -Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_sb avg p(Vgvdd_sb[0][0]) from=0 to='clock_period' -.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_sb avg p(Vgvdd_sb[0][0]) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period' -.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_2/sb_tb/example_2_sb0_1_sb_testbench.sp b/examples/spice_test_example_2/sb_tb/example_2_sb0_1_sb_testbench.sp deleted file mode 100644 index 022b6b830..000000000 --- a/examples/spice_test_example_2/sb_tb/example_2_sb0_1_sb_testbench.sp +++ /dev/null @@ -1,1151 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_sbs -****** Include subckt netlists: Switch Block[0][1] ***** -.include './spice_test_example_2/subckt/sb_0_1.sp' -***** Call defined Switch Box[0][1] ***** -Xsb[0][1] -+ -+ -+ chanx[1][1]_out[0] chanx[1][1]_in[1] chanx[1][1]_out[2] chanx[1][1]_in[3] chanx[1][1]_out[4] chanx[1][1]_in[5] chanx[1][1]_out[6] chanx[1][1]_in[7] chanx[1][1]_out[8] chanx[1][1]_in[9] chanx[1][1]_out[10] chanx[1][1]_in[11] chanx[1][1]_out[12] chanx[1][1]_in[13] chanx[1][1]_out[14] chanx[1][1]_in[15] chanx[1][1]_out[16] chanx[1][1]_in[17] chanx[1][1]_out[18] chanx[1][1]_in[19] chanx[1][1]_out[20] chanx[1][1]_in[21] chanx[1][1]_out[22] chanx[1][1]_in[23] chanx[1][1]_out[24] chanx[1][1]_in[25] chanx[1][1]_out[26] chanx[1][1]_in[27] chanx[1][1]_out[28] chanx[1][1]_in[29] chanx[1][1]_out[30] chanx[1][1]_in[31] chanx[1][1]_out[32] chanx[1][1]_in[33] chanx[1][1]_out[34] chanx[1][1]_in[35] chanx[1][1]_out[36] chanx[1][1]_in[37] chanx[1][1]_out[38] chanx[1][1]_in[39] chanx[1][1]_out[40] chanx[1][1]_in[41] chanx[1][1]_out[42] chanx[1][1]_in[43] chanx[1][1]_out[44] chanx[1][1]_in[45] chanx[1][1]_out[46] chanx[1][1]_in[47] chanx[1][1]_out[48] chanx[1][1]_in[49] chanx[1][1]_out[50] chanx[1][1]_in[51] chanx[1][1]_out[52] chanx[1][1]_in[53] chanx[1][1]_out[54] chanx[1][1]_in[55] chanx[1][1]_out[56] chanx[1][1]_in[57] chanx[1][1]_out[58] chanx[1][1]_in[59] chanx[1][1]_out[60] chanx[1][1]_in[61] chanx[1][1]_out[62] chanx[1][1]_in[63] chanx[1][1]_out[64] chanx[1][1]_in[65] chanx[1][1]_out[66] chanx[1][1]_in[67] chanx[1][1]_out[68] chanx[1][1]_in[69] chanx[1][1]_out[70] chanx[1][1]_in[71] chanx[1][1]_out[72] chanx[1][1]_in[73] chanx[1][1]_out[74] chanx[1][1]_in[75] chanx[1][1]_out[76] chanx[1][1]_in[77] chanx[1][1]_out[78] chanx[1][1]_in[79] chanx[1][1]_out[80] chanx[1][1]_in[81] chanx[1][1]_out[82] chanx[1][1]_in[83] chanx[1][1]_out[84] chanx[1][1]_in[85] chanx[1][1]_out[86] chanx[1][1]_in[87] chanx[1][1]_out[88] chanx[1][1]_in[89] chanx[1][1]_out[90] chanx[1][1]_in[91] chanx[1][1]_out[92] chanx[1][1]_in[93] chanx[1][1]_out[94] chanx[1][1]_in[95] chanx[1][1]_out[96] chanx[1][1]_in[97] chanx[1][1]_out[98] chanx[1][1]_in[99] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][48] -+ chany[0][1]_in[0] chany[0][1]_out[1] chany[0][1]_in[2] chany[0][1]_out[3] chany[0][1]_in[4] chany[0][1]_out[5] chany[0][1]_in[6] chany[0][1]_out[7] chany[0][1]_in[8] chany[0][1]_out[9] chany[0][1]_in[10] chany[0][1]_out[11] chany[0][1]_in[12] chany[0][1]_out[13] chany[0][1]_in[14] chany[0][1]_out[15] chany[0][1]_in[16] chany[0][1]_out[17] chany[0][1]_in[18] chany[0][1]_out[19] chany[0][1]_in[20] chany[0][1]_out[21] chany[0][1]_in[22] chany[0][1]_out[23] chany[0][1]_in[24] chany[0][1]_out[25] chany[0][1]_in[26] chany[0][1]_out[27] chany[0][1]_in[28] chany[0][1]_out[29] chany[0][1]_in[30] chany[0][1]_out[31] chany[0][1]_in[32] chany[0][1]_out[33] chany[0][1]_in[34] chany[0][1]_out[35] chany[0][1]_in[36] chany[0][1]_out[37] chany[0][1]_in[38] chany[0][1]_out[39] chany[0][1]_in[40] chany[0][1]_out[41] chany[0][1]_in[42] chany[0][1]_out[43] chany[0][1]_in[44] chany[0][1]_out[45] chany[0][1]_in[46] chany[0][1]_out[47] chany[0][1]_in[48] chany[0][1]_out[49] chany[0][1]_in[50] chany[0][1]_out[51] chany[0][1]_in[52] chany[0][1]_out[53] chany[0][1]_in[54] chany[0][1]_out[55] chany[0][1]_in[56] chany[0][1]_out[57] chany[0][1]_in[58] chany[0][1]_out[59] chany[0][1]_in[60] chany[0][1]_out[61] chany[0][1]_in[62] chany[0][1]_out[63] chany[0][1]_in[64] chany[0][1]_out[65] chany[0][1]_in[66] chany[0][1]_out[67] chany[0][1]_in[68] chany[0][1]_out[69] chany[0][1]_in[70] chany[0][1]_out[71] chany[0][1]_in[72] chany[0][1]_out[73] chany[0][1]_in[74] chany[0][1]_out[75] chany[0][1]_in[76] chany[0][1]_out[77] chany[0][1]_in[78] chany[0][1]_out[79] chany[0][1]_in[80] chany[0][1]_out[81] chany[0][1]_in[82] chany[0][1]_out[83] chany[0][1]_in[84] chany[0][1]_out[85] chany[0][1]_in[86] chany[0][1]_out[87] chany[0][1]_in[88] chany[0][1]_out[89] chany[0][1]_in[90] chany[0][1]_out[91] chany[0][1]_in[92] chany[0][1]_out[93] chany[0][1]_in[94] chany[0][1]_out[95] chany[0][1]_in[96] chany[0][1]_out[97] chany[0][1]_in[98] chany[0][1]_out[99] -+ grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][47] grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] -+ -+ -+ gvdd_sb[0][1] 0 sb[0][1] - -**** Load for rr_node[291] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=0, type=4 ***** -Xchan_chanx[1][1]_out[0]_loadlvl[0]_out chanx[1][1]_out[0] chanx[1][1]_out[0]_loadlvl[0]_out chanx[1][1]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 chanx[1][1]_out[0]_loadlvl[0]_out chanx[1][1]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 chanx[1][1]_out[0]_loadlvl[0]_midout chanx[1][1]_out[0]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[2]_no0 chanx[1][1]_out[0]_loadlvl[0]_midout chanx[1][1]_out[0]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 chanx[1][1]_out[0]_loadlvl[0]_midout chanx[1][1]_out[0]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 chanx[1][1]_out[0]_loadlvl[0]_midout chanx[1][1]_out[0]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[1] density = 0, probability=0.***** -Vchanx[1][1]_in[1] chanx[1][1]_in[1] 0 -+ 0 -**** Load for rr_node[293] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=2, type=4 ***** -Xchan_chanx[1][1]_out[2]_loadlvl[0]_out chanx[1][1]_out[2] chanx[1][1]_out[2]_loadlvl[0]_out chanx[1][1]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[5]_no0 chanx[1][1]_out[2]_loadlvl[0]_out chanx[1][1]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 chanx[1][1]_out[2]_loadlvl[0]_midout chanx[1][1]_out[2]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 chanx[1][1]_out[2]_loadlvl[0]_midout chanx[1][1]_out[2]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[3] density = 0, probability=0.***** -Vchanx[1][1]_in[3] chanx[1][1]_in[3] 0 -+ 0 -**** Load for rr_node[295] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=4, type=4 ***** -Xchan_chanx[1][1]_out[4]_loadlvl[0]_out chanx[1][1]_out[4] chanx[1][1]_out[4]_loadlvl[0]_out chanx[1][1]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[8]_no0 chanx[1][1]_out[4]_loadlvl[0]_out chanx[1][1]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 chanx[1][1]_out[4]_loadlvl[0]_midout chanx[1][1]_out[4]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 chanx[1][1]_out[4]_loadlvl[0]_midout chanx[1][1]_out[4]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[11]_no0 chanx[1][1]_out[4]_loadlvl[0]_midout chanx[1][1]_out[4]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[5] density = 0, probability=0.***** -Vchanx[1][1]_in[5] chanx[1][1]_in[5] 0 -+ 0 -**** Load for rr_node[297] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=6, type=4 ***** -Xchan_chanx[1][1]_out[6]_loadlvl[0]_out chanx[1][1]_out[6] chanx[1][1]_out[6]_loadlvl[0]_out chanx[1][1]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[12]_no0 chanx[1][1]_out[6]_loadlvl[0]_out chanx[1][1]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 chanx[1][1]_out[6]_loadlvl[0]_midout chanx[1][1]_out[6]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[14]_no0 chanx[1][1]_out[6]_loadlvl[0]_midout chanx[1][1]_out[6]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 chanx[1][1]_out[6]_loadlvl[0]_midout chanx[1][1]_out[6]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[7] density = 0, probability=0.***** -Vchanx[1][1]_in[7] chanx[1][1]_in[7] 0 -+ 0 -**** Load for rr_node[299] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=8, type=4 ***** -Xchan_chanx[1][1]_out[8]_loadlvl[0]_out chanx[1][1]_out[8] chanx[1][1]_out[8]_loadlvl[0]_out chanx[1][1]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[16]_no0 chanx[1][1]_out[8]_loadlvl[0]_out chanx[1][1]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 chanx[1][1]_out[8]_loadlvl[0]_midout chanx[1][1]_out[8]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 chanx[1][1]_out[8]_loadlvl[0]_midout chanx[1][1]_out[8]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[19]_no0 chanx[1][1]_out[8]_loadlvl[0]_midout chanx[1][1]_out[8]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 chanx[1][1]_out[8]_loadlvl[0]_midout chanx[1][1]_out[8]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[9] density = 0, probability=0.***** -Vchanx[1][1]_in[9] chanx[1][1]_in[9] 0 -+ 0 -**** Load for rr_node[301] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=10, type=4 ***** -Xchan_chanx[1][1]_out[10]_loadlvl[0]_out chanx[1][1]_out[10] chanx[1][1]_out[10]_loadlvl[0]_out chanx[1][1]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[21]_no0 chanx[1][1]_out[10]_loadlvl[0]_out chanx[1][1]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 chanx[1][1]_out[10]_loadlvl[0]_midout chanx[1][1]_out[10]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[23]_no0 chanx[1][1]_out[10]_loadlvl[0]_midout chanx[1][1]_out[10]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 chanx[1][1]_out[10]_loadlvl[0]_midout chanx[1][1]_out[10]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[11] density = 0, probability=0.***** -Vchanx[1][1]_in[11] chanx[1][1]_in[11] 0 -+ 0 -**** Load for rr_node[303] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=12, type=4 ***** -Xchan_chanx[1][1]_out[12]_loadlvl[0]_out chanx[1][1]_out[12] chanx[1][1]_out[12]_loadlvl[0]_out chanx[1][1]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[25]_no0 chanx[1][1]_out[12]_loadlvl[0]_out chanx[1][1]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[26]_no0 chanx[1][1]_out[12]_loadlvl[0]_midout chanx[1][1]_out[12]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 chanx[1][1]_out[12]_loadlvl[0]_midout chanx[1][1]_out[12]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[13] density = 0, probability=0.***** -Vchanx[1][1]_in[13] chanx[1][1]_in[13] 0 -+ 0 -**** Load for rr_node[305] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=14, type=4 ***** -Xchan_chanx[1][1]_out[14]_loadlvl[0]_out chanx[1][1]_out[14] chanx[1][1]_out[14]_loadlvl[0]_out chanx[1][1]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[28]_no0 chanx[1][1]_out[14]_loadlvl[0]_out chanx[1][1]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 chanx[1][1]_out[14]_loadlvl[0]_midout chanx[1][1]_out[14]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 chanx[1][1]_out[14]_loadlvl[0]_midout chanx[1][1]_out[14]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[15] density = 0, probability=0.***** -Vchanx[1][1]_in[15] chanx[1][1]_in[15] 0 -+ 0 -**** Load for rr_node[307] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=16, type=4 ***** -Xchan_chanx[1][1]_out[16]_loadlvl[0]_out chanx[1][1]_out[16] chanx[1][1]_out[16]_loadlvl[0]_out chanx[1][1]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[31]_no0 chanx[1][1]_out[16]_loadlvl[0]_out chanx[1][1]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 chanx[1][1]_out[16]_loadlvl[0]_midout chanx[1][1]_out[16]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 chanx[1][1]_out[16]_loadlvl[0]_midout chanx[1][1]_out[16]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[17] density = 0, probability=0.***** -Vchanx[1][1]_in[17] chanx[1][1]_in[17] 0 -+ 0 -**** Load for rr_node[309] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=18, type=4 ***** -Xchan_chanx[1][1]_out[18]_loadlvl[0]_out chanx[1][1]_out[18] chanx[1][1]_out[18]_loadlvl[0]_out chanx[1][1]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[34]_no0 chanx[1][1]_out[18]_loadlvl[0]_out chanx[1][1]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 chanx[1][1]_out[18]_loadlvl[0]_midout chanx[1][1]_out[18]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[36]_no0 chanx[1][1]_out[18]_loadlvl[0]_midout chanx[1][1]_out[18]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 chanx[1][1]_out[18]_loadlvl[0]_midout chanx[1][1]_out[18]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[19] density = 0, probability=0.***** -Vchanx[1][1]_in[19] chanx[1][1]_in[19] 0 -+ 0 -**** Load for rr_node[311] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=20, type=4 ***** -Xchan_chanx[1][1]_out[20]_loadlvl[0]_out chanx[1][1]_out[20] chanx[1][1]_out[20]_loadlvl[0]_out chanx[1][1]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[38]_no0 chanx[1][1]_out[20]_loadlvl[0]_out chanx[1][1]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[39]_no0 chanx[1][1]_out[20]_loadlvl[0]_midout chanx[1][1]_out[20]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 chanx[1][1]_out[20]_loadlvl[0]_midout chanx[1][1]_out[20]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 chanx[1][1]_out[20]_loadlvl[0]_midout chanx[1][1]_out[20]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[21] density = 0, probability=0.***** -Vchanx[1][1]_in[21] chanx[1][1]_in[21] 0 -+ 0 -**** Load for rr_node[313] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=22, type=4 ***** -Xchan_chanx[1][1]_out[22]_loadlvl[0]_out chanx[1][1]_out[22] chanx[1][1]_out[22]_loadlvl[0]_out chanx[1][1]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[42]_no0 chanx[1][1]_out[22]_loadlvl[0]_out chanx[1][1]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 chanx[1][1]_out[22]_loadlvl[0]_midout chanx[1][1]_out[22]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 chanx[1][1]_out[22]_loadlvl[0]_midout chanx[1][1]_out[22]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[45]_no0 chanx[1][1]_out[22]_loadlvl[0]_midout chanx[1][1]_out[22]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 chanx[1][1]_out[22]_loadlvl[0]_midout chanx[1][1]_out[22]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[23] density = 0, probability=0.***** -Vchanx[1][1]_in[23] chanx[1][1]_in[23] 0 -+ 0 -**** Load for rr_node[315] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=24, type=4 ***** -Xchan_chanx[1][1]_out[24]_loadlvl[0]_out chanx[1][1]_out[24] chanx[1][1]_out[24]_loadlvl[0]_out chanx[1][1]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[47]_no0 chanx[1][1]_out[24]_loadlvl[0]_out chanx[1][1]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[48]_no0 chanx[1][1]_out[24]_loadlvl[0]_midout chanx[1][1]_out[24]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 chanx[1][1]_out[24]_loadlvl[0]_midout chanx[1][1]_out[24]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[50]_no0 chanx[1][1]_out[24]_loadlvl[0]_midout chanx[1][1]_out[24]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[25] density = 0, probability=0.***** -Vchanx[1][1]_in[25] chanx[1][1]_in[25] 0 -+ 0 -**** Load for rr_node[317] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=26, type=4 ***** -Xchan_chanx[1][1]_out[26]_loadlvl[0]_out chanx[1][1]_out[26] chanx[1][1]_out[26]_loadlvl[0]_out chanx[1][1]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[51]_no0 chanx[1][1]_out[26]_loadlvl[0]_out chanx[1][1]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[52]_no0 chanx[1][1]_out[26]_loadlvl[0]_midout chanx[1][1]_out[26]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 chanx[1][1]_out[26]_loadlvl[0]_midout chanx[1][1]_out[26]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[27] density = 0, probability=0.***** -Vchanx[1][1]_in[27] chanx[1][1]_in[27] 0 -+ 0 -**** Load for rr_node[319] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=28, type=4 ***** -Xchan_chanx[1][1]_out[28]_loadlvl[0]_out chanx[1][1]_out[28] chanx[1][1]_out[28]_loadlvl[0]_out chanx[1][1]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[54]_no0 chanx[1][1]_out[28]_loadlvl[0]_out chanx[1][1]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 chanx[1][1]_out[28]_loadlvl[0]_midout chanx[1][1]_out[28]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 chanx[1][1]_out[28]_loadlvl[0]_midout chanx[1][1]_out[28]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[57]_no0 chanx[1][1]_out[28]_loadlvl[0]_midout chanx[1][1]_out[28]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[29] density = 0, probability=0.***** -Vchanx[1][1]_in[29] chanx[1][1]_in[29] 0 -+ 0 -**** Load for rr_node[321] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=30, type=4 ***** -Xchan_chanx[1][1]_out[30]_loadlvl[0]_out chanx[1][1]_out[30] chanx[1][1]_out[30]_loadlvl[0]_out chanx[1][1]_out[30]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[58]_no0 chanx[1][1]_out[30]_loadlvl[0]_out chanx[1][1]_out[30]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 chanx[1][1]_out[30]_loadlvl[0]_midout chanx[1][1]_out[30]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[60]_no0 chanx[1][1]_out[30]_loadlvl[0]_midout chanx[1][1]_out[30]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 chanx[1][1]_out[30]_loadlvl[0]_midout chanx[1][1]_out[30]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[31] density = 0, probability=0.***** -Vchanx[1][1]_in[31] chanx[1][1]_in[31] 0 -+ 0 -**** Load for rr_node[323] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=32, type=4 ***** -Xchan_chanx[1][1]_out[32]_loadlvl[0]_out chanx[1][1]_out[32] chanx[1][1]_out[32]_loadlvl[0]_out chanx[1][1]_out[32]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[62]_no0 chanx[1][1]_out[32]_loadlvl[0]_out chanx[1][1]_out[32]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[63]_no0 chanx[1][1]_out[32]_loadlvl[0]_midout chanx[1][1]_out[32]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 chanx[1][1]_out[32]_loadlvl[0]_midout chanx[1][1]_out[32]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[33] density = 0, probability=0.***** -Vchanx[1][1]_in[33] chanx[1][1]_in[33] 0 -+ 0 -**** Load for rr_node[325] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=34, type=4 ***** -Xchan_chanx[1][1]_out[34]_loadlvl[0]_out chanx[1][1]_out[34] chanx[1][1]_out[34]_loadlvl[0]_out chanx[1][1]_out[34]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[65]_no0 chanx[1][1]_out[34]_loadlvl[0]_out chanx[1][1]_out[34]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[66]_no0 chanx[1][1]_out[34]_loadlvl[0]_midout chanx[1][1]_out[34]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 chanx[1][1]_out[34]_loadlvl[0]_midout chanx[1][1]_out[34]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[68]_no0 chanx[1][1]_out[34]_loadlvl[0]_midout chanx[1][1]_out[34]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[35] density = 0, probability=0.***** -Vchanx[1][1]_in[35] chanx[1][1]_in[35] 0 -+ 0 -**** Load for rr_node[327] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=36, type=4 ***** -Xchan_chanx[1][1]_out[36]_loadlvl[0]_out chanx[1][1]_out[36] chanx[1][1]_out[36]_loadlvl[0]_out chanx[1][1]_out[36]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[69]_no0 chanx[1][1]_out[36]_loadlvl[0]_out chanx[1][1]_out[36]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 chanx[1][1]_out[36]_loadlvl[0]_midout chanx[1][1]_out[36]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[71]_no0 chanx[1][1]_out[36]_loadlvl[0]_midout chanx[1][1]_out[36]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 chanx[1][1]_out[36]_loadlvl[0]_midout chanx[1][1]_out[36]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[37] density = 0, probability=0.***** -Vchanx[1][1]_in[37] chanx[1][1]_in[37] 0 -+ 0 -**** Load for rr_node[329] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=38, type=4 ***** -Xchan_chanx[1][1]_out[38]_loadlvl[0]_out chanx[1][1]_out[38] chanx[1][1]_out[38]_loadlvl[0]_out chanx[1][1]_out[38]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[73]_no0 chanx[1][1]_out[38]_loadlvl[0]_out chanx[1][1]_out[38]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 chanx[1][1]_out[38]_loadlvl[0]_midout chanx[1][1]_out[38]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[75]_no0 chanx[1][1]_out[38]_loadlvl[0]_midout chanx[1][1]_out[38]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 chanx[1][1]_out[38]_loadlvl[0]_midout chanx[1][1]_out[38]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 chanx[1][1]_out[38]_loadlvl[0]_midout chanx[1][1]_out[38]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[39] density = 0, probability=0.***** -Vchanx[1][1]_in[39] chanx[1][1]_in[39] 0 -+ 0 -**** Load for rr_node[331] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=40, type=4 ***** -Xchan_chanx[1][1]_out[40]_loadlvl[0]_out chanx[1][1]_out[40] chanx[1][1]_out[40]_loadlvl[0]_out chanx[1][1]_out[40]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[78]_no0 chanx[1][1]_out[40]_loadlvl[0]_out chanx[1][1]_out[40]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 chanx[1][1]_out[40]_loadlvl[0]_midout chanx[1][1]_out[40]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[80]_no0 chanx[1][1]_out[40]_loadlvl[0]_midout chanx[1][1]_out[40]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 chanx[1][1]_out[40]_loadlvl[0]_midout chanx[1][1]_out[40]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[41] density = 0, probability=0.***** -Vchanx[1][1]_in[41] chanx[1][1]_in[41] 0 -+ 0 -**** Load for rr_node[333] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=42, type=4 ***** -Xchan_chanx[1][1]_out[42]_loadlvl[0]_out chanx[1][1]_out[42] chanx[1][1]_out[42]_loadlvl[0]_out chanx[1][1]_out[42]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[82]_no0 chanx[1][1]_out[42]_loadlvl[0]_out chanx[1][1]_out[42]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[83]_no0 chanx[1][1]_out[42]_loadlvl[0]_midout chanx[1][1]_out[42]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 chanx[1][1]_out[42]_loadlvl[0]_midout chanx[1][1]_out[42]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 chanx[1][1]_out[42]_loadlvl[0]_midout chanx[1][1]_out[42]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[43] density = 0, probability=0.***** -Vchanx[1][1]_in[43] chanx[1][1]_in[43] 0 -+ 0 -**** Load for rr_node[335] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=44, type=4 ***** -Xchan_chanx[1][1]_out[44]_loadlvl[0]_out chanx[1][1]_out[44] chanx[1][1]_out[44]_loadlvl[0]_out chanx[1][1]_out[44]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[86]_no0 chanx[1][1]_out[44]_loadlvl[0]_out chanx[1][1]_out[44]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 chanx[1][1]_out[44]_loadlvl[0]_midout chanx[1][1]_out[44]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 chanx[1][1]_out[44]_loadlvl[0]_midout chanx[1][1]_out[44]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[89]_no0 chanx[1][1]_out[44]_loadlvl[0]_midout chanx[1][1]_out[44]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 chanx[1][1]_out[44]_loadlvl[0]_midout chanx[1][1]_out[44]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[45] density = 0, probability=0.***** -Vchanx[1][1]_in[45] chanx[1][1]_in[45] 0 -+ 0 -**** Load for rr_node[337] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=46, type=4 ***** -Xchan_chanx[1][1]_out[46]_loadlvl[0]_out chanx[1][1]_out[46] chanx[1][1]_out[46]_loadlvl[0]_out chanx[1][1]_out[46]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[91]_no0 chanx[1][1]_out[46]_loadlvl[0]_out chanx[1][1]_out[46]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 chanx[1][1]_out[46]_loadlvl[0]_midout chanx[1][1]_out[46]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 chanx[1][1]_out[46]_loadlvl[0]_midout chanx[1][1]_out[46]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[47] density = 0, probability=0.***** -Vchanx[1][1]_in[47] chanx[1][1]_in[47] 0 -+ 0 -**** Load for rr_node[339] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=48, type=4 ***** -Xchan_chanx[1][1]_out[48]_loadlvl[0]_out chanx[1][1]_out[48] chanx[1][1]_out[48]_loadlvl[0]_out chanx[1][1]_out[48]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[94]_no0 chanx[1][1]_out[48]_loadlvl[0]_out chanx[1][1]_out[48]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 chanx[1][1]_out[48]_loadlvl[0]_midout chanx[1][1]_out[48]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[96]_no0 chanx[1][1]_out[48]_loadlvl[0]_midout chanx[1][1]_out[48]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 chanx[1][1]_out[48]_loadlvl[0]_midout chanx[1][1]_out[48]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[49] density = 0, probability=0.***** -Vchanx[1][1]_in[49] chanx[1][1]_in[49] 0 -+ 0 -**** Load for rr_node[341] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=50, type=4 ***** -Xchan_chanx[1][1]_out[50]_loadlvl[0]_out chanx[1][1]_out[50] chanx[1][1]_out[50]_loadlvl[0]_out chanx[1][1]_out[50]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[98]_no0 chanx[1][1]_out[50]_loadlvl[0]_out chanx[1][1]_out[50]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[99]_no0 chanx[1][1]_out[50]_loadlvl[0]_midout chanx[1][1]_out[50]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 chanx[1][1]_out[50]_loadlvl[0]_midout chanx[1][1]_out[50]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[51] density = 0, probability=0.***** -Vchanx[1][1]_in[51] chanx[1][1]_in[51] 0 -+ 0 -**** Load for rr_node[343] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=52, type=4 ***** -Xchan_chanx[1][1]_out[52]_loadlvl[0]_out chanx[1][1]_out[52] chanx[1][1]_out[52]_loadlvl[0]_out chanx[1][1]_out[52]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[101]_no0 chanx[1][1]_out[52]_loadlvl[0]_out chanx[1][1]_out[52]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[102]_no0 chanx[1][1]_out[52]_loadlvl[0]_midout chanx[1][1]_out[52]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 chanx[1][1]_out[52]_loadlvl[0]_midout chanx[1][1]_out[52]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[53] density = 0, probability=0.***** -Vchanx[1][1]_in[53] chanx[1][1]_in[53] 0 -+ 0 -**** Load for rr_node[345] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=54, type=4 ***** -Xchan_chanx[1][1]_out[54]_loadlvl[0]_out chanx[1][1]_out[54] chanx[1][1]_out[54]_loadlvl[0]_out chanx[1][1]_out[54]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[104]_no0 chanx[1][1]_out[54]_loadlvl[0]_out chanx[1][1]_out[54]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 chanx[1][1]_out[54]_loadlvl[0]_midout chanx[1][1]_out[54]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 chanx[1][1]_out[54]_loadlvl[0]_midout chanx[1][1]_out[54]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[107]_no0 chanx[1][1]_out[54]_loadlvl[0]_midout chanx[1][1]_out[54]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 chanx[1][1]_out[54]_loadlvl[0]_midout chanx[1][1]_out[54]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[55] density = 0, probability=0.***** -Vchanx[1][1]_in[55] chanx[1][1]_in[55] 0 -+ 0 -**** Load for rr_node[347] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=56, type=4 ***** -Xchan_chanx[1][1]_out[56]_loadlvl[0]_out chanx[1][1]_out[56] chanx[1][1]_out[56]_loadlvl[0]_out chanx[1][1]_out[56]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[109]_no0 chanx[1][1]_out[56]_loadlvl[0]_out chanx[1][1]_out[56]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 chanx[1][1]_out[56]_loadlvl[0]_midout chanx[1][1]_out[56]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 chanx[1][1]_out[56]_loadlvl[0]_midout chanx[1][1]_out[56]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[57] density = 0, probability=0.***** -Vchanx[1][1]_in[57] chanx[1][1]_in[57] 0 -+ 0 -**** Load for rr_node[349] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=58, type=4 ***** -Xchan_chanx[1][1]_out[58]_loadlvl[0]_out chanx[1][1]_out[58] chanx[1][1]_out[58]_loadlvl[0]_out chanx[1][1]_out[58]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[112]_no0 chanx[1][1]_out[58]_loadlvl[0]_out chanx[1][1]_out[58]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 chanx[1][1]_out[58]_loadlvl[0]_midout chanx[1][1]_out[58]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 chanx[1][1]_out[58]_loadlvl[0]_midout chanx[1][1]_out[58]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[115]_no0 chanx[1][1]_out[58]_loadlvl[0]_midout chanx[1][1]_out[58]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[59] density = 0, probability=0.***** -Vchanx[1][1]_in[59] chanx[1][1]_in[59] 0 -+ 0 -**** Load for rr_node[351] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=60, type=4 ***** -Xchan_chanx[1][1]_out[60]_loadlvl[0]_out chanx[1][1]_out[60] chanx[1][1]_out[60]_loadlvl[0]_out chanx[1][1]_out[60]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[116]_no0 chanx[1][1]_out[60]_loadlvl[0]_out chanx[1][1]_out[60]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[117]_no0 chanx[1][1]_out[60]_loadlvl[0]_midout chanx[1][1]_out[60]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 chanx[1][1]_out[60]_loadlvl[0]_midout chanx[1][1]_out[60]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 chanx[1][1]_out[60]_loadlvl[0]_midout chanx[1][1]_out[60]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[61] density = 0, probability=0.***** -Vchanx[1][1]_in[61] chanx[1][1]_in[61] 0 -+ 0 -**** Load for rr_node[353] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=62, type=4 ***** -Xchan_chanx[1][1]_out[62]_loadlvl[0]_out chanx[1][1]_out[62] chanx[1][1]_out[62]_loadlvl[0]_out chanx[1][1]_out[62]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[120]_no0 chanx[1][1]_out[62]_loadlvl[0]_out chanx[1][1]_out[62]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 chanx[1][1]_out[62]_loadlvl[0]_midout chanx[1][1]_out[62]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[122]_no0 chanx[1][1]_out[62]_loadlvl[0]_midout chanx[1][1]_out[62]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 chanx[1][1]_out[62]_loadlvl[0]_midout chanx[1][1]_out[62]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 chanx[1][1]_out[62]_loadlvl[0]_midout chanx[1][1]_out[62]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[63] density = 0, probability=0.***** -Vchanx[1][1]_in[63] chanx[1][1]_in[63] 0 -+ 0 -**** Load for rr_node[355] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=64, type=4 ***** -Xchan_chanx[1][1]_out[64]_loadlvl[0]_out chanx[1][1]_out[64] chanx[1][1]_out[64]_loadlvl[0]_out chanx[1][1]_out[64]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[125]_no0 chanx[1][1]_out[64]_loadlvl[0]_out chanx[1][1]_out[64]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 chanx[1][1]_out[64]_loadlvl[0]_midout chanx[1][1]_out[64]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 chanx[1][1]_out[64]_loadlvl[0]_midout chanx[1][1]_out[64]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[128]_no0 chanx[1][1]_out[64]_loadlvl[0]_midout chanx[1][1]_out[64]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 chanx[1][1]_out[64]_loadlvl[0]_midout chanx[1][1]_out[64]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[65] density = 0, probability=0.***** -Vchanx[1][1]_in[65] chanx[1][1]_in[65] 0 -+ 0 -**** Load for rr_node[357] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=66, type=4 ***** -Xchan_chanx[1][1]_out[66]_loadlvl[0]_out chanx[1][1]_out[66] chanx[1][1]_out[66]_loadlvl[0]_out chanx[1][1]_out[66]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[130]_no0 chanx[1][1]_out[66]_loadlvl[0]_out chanx[1][1]_out[66]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 chanx[1][1]_out[66]_loadlvl[0]_midout chanx[1][1]_out[66]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 chanx[1][1]_out[66]_loadlvl[0]_midout chanx[1][1]_out[66]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[67] density = 0, probability=0.***** -Vchanx[1][1]_in[67] chanx[1][1]_in[67] 0 -+ 0 -**** Load for rr_node[359] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=68, type=4 ***** -Xchan_chanx[1][1]_out[68]_loadlvl[0]_out chanx[1][1]_out[68] chanx[1][1]_out[68]_loadlvl[0]_out chanx[1][1]_out[68]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[133]_no0 chanx[1][1]_out[68]_loadlvl[0]_out chanx[1][1]_out[68]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 chanx[1][1]_out[68]_loadlvl[0]_midout chanx[1][1]_out[68]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[135]_no0 chanx[1][1]_out[68]_loadlvl[0]_midout chanx[1][1]_out[68]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[69] density = 0, probability=0.***** -Vchanx[1][1]_in[69] chanx[1][1]_in[69] 0 -+ 0 -**** Load for rr_node[361] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=70, type=4 ***** -Xchan_chanx[1][1]_out[70]_loadlvl[0]_out chanx[1][1]_out[70] chanx[1][1]_out[70]_loadlvl[0]_out chanx[1][1]_out[70]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[136]_no0 chanx[1][1]_out[70]_loadlvl[0]_out chanx[1][1]_out[70]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 chanx[1][1]_out[70]_loadlvl[0]_midout chanx[1][1]_out[70]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[138]_no0 chanx[1][1]_out[70]_loadlvl[0]_midout chanx[1][1]_out[70]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 chanx[1][1]_out[70]_loadlvl[0]_midout chanx[1][1]_out[70]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[71] density = 0, probability=0.***** -Vchanx[1][1]_in[71] chanx[1][1]_in[71] 0 -+ 0 -**** Load for rr_node[363] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=72, type=4 ***** -Xchan_chanx[1][1]_out[72]_loadlvl[0]_out chanx[1][1]_out[72] chanx[1][1]_out[72]_loadlvl[0]_out chanx[1][1]_out[72]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[140]_no0 chanx[1][1]_out[72]_loadlvl[0]_out chanx[1][1]_out[72]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 chanx[1][1]_out[72]_loadlvl[0]_midout chanx[1][1]_out[72]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[142]_no0 chanx[1][1]_out[72]_loadlvl[0]_midout chanx[1][1]_out[72]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 chanx[1][1]_out[72]_loadlvl[0]_midout chanx[1][1]_out[72]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[73] density = 0, probability=0.***** -Vchanx[1][1]_in[73] chanx[1][1]_in[73] 0 -+ 0 -**** Load for rr_node[365] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=74, type=4 ***** -Xchan_chanx[1][1]_out[74]_loadlvl[0]_out chanx[1][1]_out[74] chanx[1][1]_out[74]_loadlvl[0]_out chanx[1][1]_out[74]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[144]_no0 chanx[1][1]_out[74]_loadlvl[0]_out chanx[1][1]_out[74]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 chanx[1][1]_out[74]_loadlvl[0]_midout chanx[1][1]_out[74]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[146]_no0 chanx[1][1]_out[74]_loadlvl[0]_midout chanx[1][1]_out[74]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 chanx[1][1]_out[74]_loadlvl[0]_midout chanx[1][1]_out[74]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[75] density = 0, probability=0.***** -Vchanx[1][1]_in[75] chanx[1][1]_in[75] 0 -+ 0 -**** Load for rr_node[367] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=76, type=4 ***** -Xchan_chanx[1][1]_out[76]_loadlvl[0]_out chanx[1][1]_out[76] chanx[1][1]_out[76]_loadlvl[0]_out chanx[1][1]_out[76]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[148]_no0 chanx[1][1]_out[76]_loadlvl[0]_out chanx[1][1]_out[76]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 chanx[1][1]_out[76]_loadlvl[0]_midout chanx[1][1]_out[76]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 chanx[1][1]_out[76]_loadlvl[0]_midout chanx[1][1]_out[76]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 chanx[1][1]_out[76]_loadlvl[0]_midout chanx[1][1]_out[76]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[77] density = 0, probability=0.***** -Vchanx[1][1]_in[77] chanx[1][1]_in[77] 0 -+ 0 -**** Load for rr_node[369] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=78, type=4 ***** -Xchan_chanx[1][1]_out[78]_loadlvl[0]_out chanx[1][1]_out[78] chanx[1][1]_out[78]_loadlvl[0]_out chanx[1][1]_out[78]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[152]_no0 chanx[1][1]_out[78]_loadlvl[0]_out chanx[1][1]_out[78]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 chanx[1][1]_out[78]_loadlvl[0]_midout chanx[1][1]_out[78]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 chanx[1][1]_out[78]_loadlvl[0]_midout chanx[1][1]_out[78]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[79] density = 0, probability=0.***** -Vchanx[1][1]_in[79] chanx[1][1]_in[79] 0 -+ 0 -**** Load for rr_node[371] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=80, type=4 ***** -Xchan_chanx[1][1]_out[80]_loadlvl[0]_out chanx[1][1]_out[80] chanx[1][1]_out[80]_loadlvl[0]_out chanx[1][1]_out[80]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[155]_no0 chanx[1][1]_out[80]_loadlvl[0]_out chanx[1][1]_out[80]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 chanx[1][1]_out[80]_loadlvl[0]_midout chanx[1][1]_out[80]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 chanx[1][1]_out[80]_loadlvl[0]_midout chanx[1][1]_out[80]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 chanx[1][1]_out[80]_loadlvl[0]_midout chanx[1][1]_out[80]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[81] density = 0, probability=0.***** -Vchanx[1][1]_in[81] chanx[1][1]_in[81] 0 -+ 0 -**** Load for rr_node[373] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=82, type=4 ***** -Xchan_chanx[1][1]_out[82]_loadlvl[0]_out chanx[1][1]_out[82] chanx[1][1]_out[82]_loadlvl[0]_out chanx[1][1]_out[82]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[159]_no0 chanx[1][1]_out[82]_loadlvl[0]_out chanx[1][1]_out[82]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 chanx[1][1]_out[82]_loadlvl[0]_midout chanx[1][1]_out[82]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 chanx[1][1]_out[82]_loadlvl[0]_midout chanx[1][1]_out[82]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 chanx[1][1]_out[82]_loadlvl[0]_midout chanx[1][1]_out[82]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 chanx[1][1]_out[82]_loadlvl[0]_midout chanx[1][1]_out[82]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[83] density = 0, probability=0.***** -Vchanx[1][1]_in[83] chanx[1][1]_in[83] 0 -+ 0 -**** Load for rr_node[375] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=84, type=4 ***** -Xchan_chanx[1][1]_out[84]_loadlvl[0]_out chanx[1][1]_out[84] chanx[1][1]_out[84]_loadlvl[0]_out chanx[1][1]_out[84]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[164]_no0 chanx[1][1]_out[84]_loadlvl[0]_out chanx[1][1]_out[84]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 chanx[1][1]_out[84]_loadlvl[0]_midout chanx[1][1]_out[84]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 chanx[1][1]_out[84]_loadlvl[0]_midout chanx[1][1]_out[84]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[85] density = 0, probability=0.***** -Vchanx[1][1]_in[85] chanx[1][1]_in[85] 0 -+ 0 -**** Load for rr_node[377] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=86, type=4 ***** -Xchan_chanx[1][1]_out[86]_loadlvl[0]_out chanx[1][1]_out[86] chanx[1][1]_out[86]_loadlvl[0]_out chanx[1][1]_out[86]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[167]_no0 chanx[1][1]_out[86]_loadlvl[0]_out chanx[1][1]_out[86]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 chanx[1][1]_out[86]_loadlvl[0]_midout chanx[1][1]_out[86]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 chanx[1][1]_out[86]_loadlvl[0]_midout chanx[1][1]_out[86]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 chanx[1][1]_out[86]_loadlvl[0]_midout chanx[1][1]_out[86]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[87] density = 0, probability=0.***** -Vchanx[1][1]_in[87] chanx[1][1]_in[87] 0 -+ 0 -**** Load for rr_node[379] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=88, type=4 ***** -Xchan_chanx[1][1]_out[88]_loadlvl[0]_out chanx[1][1]_out[88] chanx[1][1]_out[88]_loadlvl[0]_out chanx[1][1]_out[88]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[171]_no0 chanx[1][1]_out[88]_loadlvl[0]_out chanx[1][1]_out[88]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 chanx[1][1]_out[88]_loadlvl[0]_midout chanx[1][1]_out[88]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 chanx[1][1]_out[88]_loadlvl[0]_midout chanx[1][1]_out[88]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 chanx[1][1]_out[88]_loadlvl[0]_midout chanx[1][1]_out[88]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[89] density = 0, probability=0.***** -Vchanx[1][1]_in[89] chanx[1][1]_in[89] 0 -+ 0 -**** Load for rr_node[381] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=90, type=4 ***** -Xchan_chanx[1][1]_out[90]_loadlvl[0]_out chanx[1][1]_out[90] chanx[1][1]_out[90]_loadlvl[0]_out chanx[1][1]_out[90]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[175]_no0 chanx[1][1]_out[90]_loadlvl[0]_out chanx[1][1]_out[90]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 chanx[1][1]_out[90]_loadlvl[0]_midout chanx[1][1]_out[90]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[177]_no0 chanx[1][1]_out[90]_loadlvl[0]_midout chanx[1][1]_out[90]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 chanx[1][1]_out[90]_loadlvl[0]_midout chanx[1][1]_out[90]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[91] density = 0, probability=0.***** -Vchanx[1][1]_in[91] chanx[1][1]_in[91] 0 -+ 0 -**** Load for rr_node[383] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=92, type=4 ***** -Xchan_chanx[1][1]_out[92]_loadlvl[0]_out chanx[1][1]_out[92] chanx[1][1]_out[92]_loadlvl[0]_out chanx[1][1]_out[92]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[179]_no0 chanx[1][1]_out[92]_loadlvl[0]_out chanx[1][1]_out[92]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[180]_no0 chanx[1][1]_out[92]_loadlvl[0]_midout chanx[1][1]_out[92]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[181]_no0 chanx[1][1]_out[92]_loadlvl[0]_midout chanx[1][1]_out[92]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 chanx[1][1]_out[92]_loadlvl[0]_midout chanx[1][1]_out[92]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[93] density = 0, probability=0.***** -Vchanx[1][1]_in[93] chanx[1][1]_in[93] 0 -+ 0 -**** Load for rr_node[385] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=94, type=4 ***** -Xchan_chanx[1][1]_out[94]_loadlvl[0]_out chanx[1][1]_out[94] chanx[1][1]_out[94]_loadlvl[0]_out chanx[1][1]_out[94]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[183]_no0 chanx[1][1]_out[94]_loadlvl[0]_out chanx[1][1]_out[94]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[184]_no0 chanx[1][1]_out[94]_loadlvl[0]_midout chanx[1][1]_out[94]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 chanx[1][1]_out[94]_loadlvl[0]_midout chanx[1][1]_out[94]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[95] density = 0, probability=0.***** -Vchanx[1][1]_in[95] chanx[1][1]_in[95] 0 -+ 0 -**** Load for rr_node[387] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=96, type=4 ***** -Xchan_chanx[1][1]_out[96]_loadlvl[0]_out chanx[1][1]_out[96] chanx[1][1]_out[96]_loadlvl[0]_out chanx[1][1]_out[96]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[186]_no0 chanx[1][1]_out[96]_loadlvl[0]_out chanx[1][1]_out[96]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 chanx[1][1]_out[96]_loadlvl[0]_midout chanx[1][1]_out[96]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 chanx[1][1]_out[96]_loadlvl[0]_midout chanx[1][1]_out[96]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 chanx[1][1]_out[96]_loadlvl[0]_midout chanx[1][1]_out[96]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 chanx[1][1]_out[96]_loadlvl[0]_midout chanx[1][1]_out[96]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[97] density = 0, probability=0.***** -Vchanx[1][1]_in[97] chanx[1][1]_in[97] 0 -+ 0 -**** Load for rr_node[389] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=98, type=4 ***** -Xchan_chanx[1][1]_out[98]_loadlvl[0]_out chanx[1][1]_out[98] chanx[1][1]_out[98]_loadlvl[0]_out chanx[1][1]_out[98]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[191]_no0 chanx[1][1]_out[98]_loadlvl[0]_out chanx[1][1]_out[98]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 chanx[1][1]_out[98]_loadlvl[0]_midout chanx[1][1]_out[98]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 chanx[1][1]_out[98]_loadlvl[0]_midout chanx[1][1]_out[98]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[99] density = 0, probability=0.***** -Vchanx[1][1]_in[99] chanx[1][1]_in[99] 0 -+ 0 -Vgrid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][1] 0 -+ 0 -Vgrid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][3] 0 -+ 0 -Vgrid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][5] 0 -+ 0 -Vgrid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][7] 0 -+ 0 -Vgrid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][9] 0 -+ 0 -Vgrid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][11] 0 -+ 0 -Vgrid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][13] 0 -+ 0 -Vgrid[1][2]_pin[0][2][15] grid[1][2]_pin[0][2][15] 0 -+ 0 -Vgrid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40] 0 -+ 0 -Vgrid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44] 0 -+ 0 -Vgrid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48] 0 -+ 0 - -***** Signal chany[0][1]_in[0] density = 0, probability=0.***** -Vchany[0][1]_in[0] chany[0][1]_in[0] 0 -+ 0 -**** Load for rr_node[392] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=1, type=5 ***** -Xchan_chany[0][1]_out[1]_loadlvl[0]_out chany[0][1]_out[1] chany[0][1]_out[1]_loadlvl[0]_out chany[0][1]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[194]_no0 chany[0][1]_out[1]_loadlvl[0]_out chany[0][1]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 chany[0][1]_out[1]_loadlvl[0]_midout chany[0][1]_out[1]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 chany[0][1]_out[1]_loadlvl[0]_midout chany[0][1]_out[1]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 chany[0][1]_out[1]_loadlvl[0]_midout chany[0][1]_out[1]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[2] density = 0, probability=0.***** -Vchany[0][1]_in[2] chany[0][1]_in[2] 0 -+ 0 -**** Load for rr_node[394] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=3, type=5 ***** -Xchan_chany[0][1]_out[3]_loadlvl[0]_out chany[0][1]_out[3] chany[0][1]_out[3]_loadlvl[0]_out chany[0][1]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[198]_no0 chany[0][1]_out[3]_loadlvl[0]_out chany[0][1]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 chany[0][1]_out[3]_loadlvl[0]_midout chany[0][1]_out[3]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 chany[0][1]_out[3]_loadlvl[0]_midout chany[0][1]_out[3]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 chany[0][1]_out[3]_loadlvl[0]_midout chany[0][1]_out[3]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[4] density = 0, probability=0.***** -Vchany[0][1]_in[4] chany[0][1]_in[4] 0 -+ 0 -**** Load for rr_node[396] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=5, type=5 ***** -Xchan_chany[0][1]_out[5]_loadlvl[0]_out chany[0][1]_out[5] chany[0][1]_out[5]_loadlvl[0]_out chany[0][1]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[202]_no0 chany[0][1]_out[5]_loadlvl[0]_out chany[0][1]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 chany[0][1]_out[5]_loadlvl[0]_midout chany[0][1]_out[5]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 chany[0][1]_out[5]_loadlvl[0]_midout chany[0][1]_out[5]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 chany[0][1]_out[5]_loadlvl[0]_midout chany[0][1]_out[5]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[6] density = 0, probability=0.***** -Vchany[0][1]_in[6] chany[0][1]_in[6] 0 -+ 0 -**** Load for rr_node[398] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=7, type=5 ***** -Xchan_chany[0][1]_out[7]_loadlvl[0]_out chany[0][1]_out[7] chany[0][1]_out[7]_loadlvl[0]_out chany[0][1]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[206]_no0 chany[0][1]_out[7]_loadlvl[0]_out chany[0][1]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 chany[0][1]_out[7]_loadlvl[0]_midout chany[0][1]_out[7]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[208]_no0 chany[0][1]_out[7]_loadlvl[0]_midout chany[0][1]_out[7]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[8] density = 0, probability=0.***** -Vchany[0][1]_in[8] chany[0][1]_in[8] 0 -+ 0 -**** Load for rr_node[400] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=9, type=5 ***** -Xchan_chany[0][1]_out[9]_loadlvl[0]_out chany[0][1]_out[9] chany[0][1]_out[9]_loadlvl[0]_out chany[0][1]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[209]_no0 chany[0][1]_out[9]_loadlvl[0]_out chany[0][1]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 chany[0][1]_out[9]_loadlvl[0]_midout chany[0][1]_out[9]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 chany[0][1]_out[9]_loadlvl[0]_midout chany[0][1]_out[9]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[212]_no0 chany[0][1]_out[9]_loadlvl[0]_midout chany[0][1]_out[9]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 chany[0][1]_out[9]_loadlvl[0]_midout chany[0][1]_out[9]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[10] density = 0, probability=0.***** -Vchany[0][1]_in[10] chany[0][1]_in[10] 0 -+ 0 -**** Load for rr_node[402] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=11, type=5 ***** -Xchan_chany[0][1]_out[11]_loadlvl[0]_out chany[0][1]_out[11] chany[0][1]_out[11]_loadlvl[0]_out chany[0][1]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[214]_no0 chany[0][1]_out[11]_loadlvl[0]_out chany[0][1]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 chany[0][1]_out[11]_loadlvl[0]_midout chany[0][1]_out[11]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[216]_no0 chany[0][1]_out[11]_loadlvl[0]_midout chany[0][1]_out[11]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[12] density = 0, probability=0.***** -Vchany[0][1]_in[12] chany[0][1]_in[12] 0 -+ 0 -**** Load for rr_node[404] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=13, type=5 ***** -Xchan_chany[0][1]_out[13]_loadlvl[0]_out chany[0][1]_out[13] chany[0][1]_out[13]_loadlvl[0]_out chany[0][1]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[217]_no0 chany[0][1]_out[13]_loadlvl[0]_out chany[0][1]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 chany[0][1]_out[13]_loadlvl[0]_midout chany[0][1]_out[13]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 chany[0][1]_out[13]_loadlvl[0]_midout chany[0][1]_out[13]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 chany[0][1]_out[13]_loadlvl[0]_midout chany[0][1]_out[13]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[14] density = 0, probability=0.***** -Vchany[0][1]_in[14] chany[0][1]_in[14] 0 -+ 0 -**** Load for rr_node[406] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=15, type=5 ***** -Xchan_chany[0][1]_out[15]_loadlvl[0]_out chany[0][1]_out[15] chany[0][1]_out[15]_loadlvl[0]_out chany[0][1]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[221]_no0 chany[0][1]_out[15]_loadlvl[0]_out chany[0][1]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 chany[0][1]_out[15]_loadlvl[0]_midout chany[0][1]_out[15]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 chany[0][1]_out[15]_loadlvl[0]_midout chany[0][1]_out[15]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 chany[0][1]_out[15]_loadlvl[0]_midout chany[0][1]_out[15]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[16] density = 0, probability=0.***** -Vchany[0][1]_in[16] chany[0][1]_in[16] 0 -+ 0 -**** Load for rr_node[408] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=17, type=5 ***** -Xchan_chany[0][1]_out[17]_loadlvl[0]_out chany[0][1]_out[17] chany[0][1]_out[17]_loadlvl[0]_out chany[0][1]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[225]_no0 chany[0][1]_out[17]_loadlvl[0]_out chany[0][1]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 chany[0][1]_out[17]_loadlvl[0]_midout chany[0][1]_out[17]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 chany[0][1]_out[17]_loadlvl[0]_midout chany[0][1]_out[17]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 chany[0][1]_out[17]_loadlvl[0]_midout chany[0][1]_out[17]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[18] density = 0, probability=0.***** -Vchany[0][1]_in[18] chany[0][1]_in[18] 0 -+ 0 -**** Load for rr_node[410] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=19, type=5 ***** -Xchan_chany[0][1]_out[19]_loadlvl[0]_out chany[0][1]_out[19] chany[0][1]_out[19]_loadlvl[0]_out chany[0][1]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[229]_no0 chany[0][1]_out[19]_loadlvl[0]_out chany[0][1]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 chany[0][1]_out[19]_loadlvl[0]_midout chany[0][1]_out[19]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 chany[0][1]_out[19]_loadlvl[0]_midout chany[0][1]_out[19]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 chany[0][1]_out[19]_loadlvl[0]_midout chany[0][1]_out[19]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[20] density = 0, probability=0.***** -Vchany[0][1]_in[20] chany[0][1]_in[20] 0 -+ 0 -**** Load for rr_node[412] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=21, type=5 ***** -Xchan_chany[0][1]_out[21]_loadlvl[0]_out chany[0][1]_out[21] chany[0][1]_out[21]_loadlvl[0]_out chany[0][1]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[233]_no0 chany[0][1]_out[21]_loadlvl[0]_out chany[0][1]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 chany[0][1]_out[21]_loadlvl[0]_midout chany[0][1]_out[21]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 chany[0][1]_out[21]_loadlvl[0]_midout chany[0][1]_out[21]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[22] density = 0, probability=0.***** -Vchany[0][1]_in[22] chany[0][1]_in[22] 0 -+ 0 -**** Load for rr_node[414] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=23, type=5 ***** -Xchan_chany[0][1]_out[23]_loadlvl[0]_out chany[0][1]_out[23] chany[0][1]_out[23]_loadlvl[0]_out chany[0][1]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[236]_no0 chany[0][1]_out[23]_loadlvl[0]_out chany[0][1]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 chany[0][1]_out[23]_loadlvl[0]_midout chany[0][1]_out[23]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 chany[0][1]_out[23]_loadlvl[0]_midout chany[0][1]_out[23]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[239]_no0 chany[0][1]_out[23]_loadlvl[0]_midout chany[0][1]_out[23]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[240]_no0 chany[0][1]_out[23]_loadlvl[0]_midout chany[0][1]_out[23]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[24] density = 0, probability=0.***** -Vchany[0][1]_in[24] chany[0][1]_in[24] 0 -+ 0 -**** Load for rr_node[416] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=25, type=5 ***** -Xchan_chany[0][1]_out[25]_loadlvl[0]_out chany[0][1]_out[25] chany[0][1]_out[25]_loadlvl[0]_out chany[0][1]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[241]_no0 chany[0][1]_out[25]_loadlvl[0]_out chany[0][1]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 chany[0][1]_out[25]_loadlvl[0]_midout chany[0][1]_out[25]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 chany[0][1]_out[25]_loadlvl[0]_midout chany[0][1]_out[25]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 chany[0][1]_out[25]_loadlvl[0]_midout chany[0][1]_out[25]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[26] density = 0, probability=0.***** -Vchany[0][1]_in[26] chany[0][1]_in[26] 0 -+ 0 -**** Load for rr_node[418] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=27, type=5 ***** -Xchan_chany[0][1]_out[27]_loadlvl[0]_out chany[0][1]_out[27] chany[0][1]_out[27]_loadlvl[0]_out chany[0][1]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[245]_no0 chany[0][1]_out[27]_loadlvl[0]_out chany[0][1]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 chany[0][1]_out[27]_loadlvl[0]_midout chany[0][1]_out[27]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 chany[0][1]_out[27]_loadlvl[0]_midout chany[0][1]_out[27]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[28] density = 0, probability=0.***** -Vchany[0][1]_in[28] chany[0][1]_in[28] 0 -+ 0 -**** Load for rr_node[420] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=29, type=5 ***** -Xchan_chany[0][1]_out[29]_loadlvl[0]_out chany[0][1]_out[29] chany[0][1]_out[29]_loadlvl[0]_out chany[0][1]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[248]_no0 chany[0][1]_out[29]_loadlvl[0]_out chany[0][1]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 chany[0][1]_out[29]_loadlvl[0]_midout chany[0][1]_out[29]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 chany[0][1]_out[29]_loadlvl[0]_midout chany[0][1]_out[29]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 chany[0][1]_out[29]_loadlvl[0]_midout chany[0][1]_out[29]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[30] density = 0, probability=0.***** -Vchany[0][1]_in[30] chany[0][1]_in[30] 0 -+ 0 -**** Load for rr_node[422] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=31, type=5 ***** -Xchan_chany[0][1]_out[31]_loadlvl[0]_out chany[0][1]_out[31] chany[0][1]_out[31]_loadlvl[0]_out chany[0][1]_out[31]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[252]_no0 chany[0][1]_out[31]_loadlvl[0]_out chany[0][1]_out[31]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 chany[0][1]_out[31]_loadlvl[0]_midout chany[0][1]_out[31]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 chany[0][1]_out[31]_loadlvl[0]_midout chany[0][1]_out[31]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 chany[0][1]_out[31]_loadlvl[0]_midout chany[0][1]_out[31]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[32] density = 0, probability=0.***** -Vchany[0][1]_in[32] chany[0][1]_in[32] 0 -+ 0 -**** Load for rr_node[424] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=33, type=5 ***** -Xchan_chany[0][1]_out[33]_loadlvl[0]_out chany[0][1]_out[33] chany[0][1]_out[33]_loadlvl[0]_out chany[0][1]_out[33]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[256]_no0 chany[0][1]_out[33]_loadlvl[0]_out chany[0][1]_out[33]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 chany[0][1]_out[33]_loadlvl[0]_midout chany[0][1]_out[33]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 chany[0][1]_out[33]_loadlvl[0]_midout chany[0][1]_out[33]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 chany[0][1]_out[33]_loadlvl[0]_midout chany[0][1]_out[33]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[34] density = 0, probability=0.***** -Vchany[0][1]_in[34] chany[0][1]_in[34] 0 -+ 0 -**** Load for rr_node[426] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=35, type=5 ***** -Xchan_chany[0][1]_out[35]_loadlvl[0]_out chany[0][1]_out[35] chany[0][1]_out[35]_loadlvl[0]_out chany[0][1]_out[35]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[260]_no0 chany[0][1]_out[35]_loadlvl[0]_out chany[0][1]_out[35]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 chany[0][1]_out[35]_loadlvl[0]_midout chany[0][1]_out[35]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 chany[0][1]_out[35]_loadlvl[0]_midout chany[0][1]_out[35]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 chany[0][1]_out[35]_loadlvl[0]_midout chany[0][1]_out[35]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[36] density = 0, probability=0.***** -Vchany[0][1]_in[36] chany[0][1]_in[36] 0 -+ 0 -**** Load for rr_node[428] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=37, type=5 ***** -Xchan_chany[0][1]_out[37]_loadlvl[0]_out chany[0][1]_out[37] chany[0][1]_out[37]_loadlvl[0]_out chany[0][1]_out[37]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[264]_no0 chany[0][1]_out[37]_loadlvl[0]_out chany[0][1]_out[37]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 chany[0][1]_out[37]_loadlvl[0]_midout chany[0][1]_out[37]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[266]_no0 chany[0][1]_out[37]_loadlvl[0]_midout chany[0][1]_out[37]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 chany[0][1]_out[37]_loadlvl[0]_midout chany[0][1]_out[37]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[38] density = 0, probability=0.***** -Vchany[0][1]_in[38] chany[0][1]_in[38] 0 -+ 0 -**** Load for rr_node[430] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=39, type=5 ***** -Xchan_chany[0][1]_out[39]_loadlvl[0]_out chany[0][1]_out[39] chany[0][1]_out[39]_loadlvl[0]_out chany[0][1]_out[39]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[268]_no0 chany[0][1]_out[39]_loadlvl[0]_out chany[0][1]_out[39]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 chany[0][1]_out[39]_loadlvl[0]_midout chany[0][1]_out[39]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 chany[0][1]_out[39]_loadlvl[0]_midout chany[0][1]_out[39]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 chany[0][1]_out[39]_loadlvl[0]_midout chany[0][1]_out[39]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[40] density = 0, probability=0.***** -Vchany[0][1]_in[40] chany[0][1]_in[40] 0 -+ 0 -**** Load for rr_node[432] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=41, type=5 ***** -Xchan_chany[0][1]_out[41]_loadlvl[0]_out chany[0][1]_out[41] chany[0][1]_out[41]_loadlvl[0]_out chany[0][1]_out[41]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[272]_no0 chany[0][1]_out[41]_loadlvl[0]_out chany[0][1]_out[41]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 chany[0][1]_out[41]_loadlvl[0]_midout chany[0][1]_out[41]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[274]_no0 chany[0][1]_out[41]_loadlvl[0]_midout chany[0][1]_out[41]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[42] density = 0, probability=0.***** -Vchany[0][1]_in[42] chany[0][1]_in[42] 0 -+ 0 -**** Load for rr_node[434] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=43, type=5 ***** -Xchan_chany[0][1]_out[43]_loadlvl[0]_out chany[0][1]_out[43] chany[0][1]_out[43]_loadlvl[0]_out chany[0][1]_out[43]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[275]_no0 chany[0][1]_out[43]_loadlvl[0]_out chany[0][1]_out[43]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 chany[0][1]_out[43]_loadlvl[0]_midout chany[0][1]_out[43]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 chany[0][1]_out[43]_loadlvl[0]_midout chany[0][1]_out[43]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[278]_no0 chany[0][1]_out[43]_loadlvl[0]_midout chany[0][1]_out[43]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[44] density = 0, probability=0.***** -Vchany[0][1]_in[44] chany[0][1]_in[44] 0 -+ 0 -**** Load for rr_node[436] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=45, type=5 ***** -Xchan_chany[0][1]_out[45]_loadlvl[0]_out chany[0][1]_out[45] chany[0][1]_out[45]_loadlvl[0]_out chany[0][1]_out[45]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[279]_no0 chany[0][1]_out[45]_loadlvl[0]_out chany[0][1]_out[45]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 chany[0][1]_out[45]_loadlvl[0]_midout chany[0][1]_out[45]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 chany[0][1]_out[45]_loadlvl[0]_midout chany[0][1]_out[45]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 chany[0][1]_out[45]_loadlvl[0]_midout chany[0][1]_out[45]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 chany[0][1]_out[45]_loadlvl[0]_midout chany[0][1]_out[45]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[46] density = 0, probability=0.***** -Vchany[0][1]_in[46] chany[0][1]_in[46] 0 -+ 0 -**** Load for rr_node[438] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=47, type=5 ***** -Xchan_chany[0][1]_out[47]_loadlvl[0]_out chany[0][1]_out[47] chany[0][1]_out[47]_loadlvl[0]_out chany[0][1]_out[47]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[284]_no0 chany[0][1]_out[47]_loadlvl[0]_out chany[0][1]_out[47]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 chany[0][1]_out[47]_loadlvl[0]_midout chany[0][1]_out[47]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 chany[0][1]_out[47]_loadlvl[0]_midout chany[0][1]_out[47]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[48] density = 0, probability=0.***** -Vchany[0][1]_in[48] chany[0][1]_in[48] 0 -+ 0 -**** Load for rr_node[440] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=49, type=5 ***** -Xchan_chany[0][1]_out[49]_loadlvl[0]_out chany[0][1]_out[49] chany[0][1]_out[49]_loadlvl[0]_out chany[0][1]_out[49]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[287]_no0 chany[0][1]_out[49]_loadlvl[0]_out chany[0][1]_out[49]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 chany[0][1]_out[49]_loadlvl[0]_midout chany[0][1]_out[49]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 chany[0][1]_out[49]_loadlvl[0]_midout chany[0][1]_out[49]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 chany[0][1]_out[49]_loadlvl[0]_midout chany[0][1]_out[49]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[50] density = 0, probability=0.***** -Vchany[0][1]_in[50] chany[0][1]_in[50] 0 -+ 0 -**** Load for rr_node[442] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=51, type=5 ***** -Xchan_chany[0][1]_out[51]_loadlvl[0]_out chany[0][1]_out[51] chany[0][1]_out[51]_loadlvl[0]_out chany[0][1]_out[51]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[291]_no0 chany[0][1]_out[51]_loadlvl[0]_out chany[0][1]_out[51]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 chany[0][1]_out[51]_loadlvl[0]_midout chany[0][1]_out[51]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 chany[0][1]_out[51]_loadlvl[0]_midout chany[0][1]_out[51]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 chany[0][1]_out[51]_loadlvl[0]_midout chany[0][1]_out[51]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[52] density = 0, probability=0.***** -Vchany[0][1]_in[52] chany[0][1]_in[52] 0 -+ 0 -**** Load for rr_node[444] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=53, type=5 ***** -Xchan_chany[0][1]_out[53]_loadlvl[0]_out chany[0][1]_out[53] chany[0][1]_out[53]_loadlvl[0]_out chany[0][1]_out[53]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[295]_no0 chany[0][1]_out[53]_loadlvl[0]_out chany[0][1]_out[53]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 chany[0][1]_out[53]_loadlvl[0]_midout chany[0][1]_out[53]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 chany[0][1]_out[53]_loadlvl[0]_midout chany[0][1]_out[53]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 chany[0][1]_out[53]_loadlvl[0]_midout chany[0][1]_out[53]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[54] density = 0, probability=0.***** -Vchany[0][1]_in[54] chany[0][1]_in[54] 0 -+ 0 -**** Load for rr_node[446] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=55, type=5 ***** -Xchan_chany[0][1]_out[55]_loadlvl[0]_out chany[0][1]_out[55] chany[0][1]_out[55]_loadlvl[0]_out chany[0][1]_out[55]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[299]_no0 chany[0][1]_out[55]_loadlvl[0]_out chany[0][1]_out[55]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[300]_no0 chany[0][1]_out[55]_loadlvl[0]_midout chany[0][1]_out[55]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[301]_no0 chany[0][1]_out[55]_loadlvl[0]_midout chany[0][1]_out[55]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 chany[0][1]_out[55]_loadlvl[0]_midout chany[0][1]_out[55]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[56] density = 0, probability=0.***** -Vchany[0][1]_in[56] chany[0][1]_in[56] 0 -+ 0 -**** Load for rr_node[448] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=57, type=5 ***** -Xchan_chany[0][1]_out[57]_loadlvl[0]_out chany[0][1]_out[57] chany[0][1]_out[57]_loadlvl[0]_out chany[0][1]_out[57]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[303]_no0 chany[0][1]_out[57]_loadlvl[0]_out chany[0][1]_out[57]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 chany[0][1]_out[57]_loadlvl[0]_midout chany[0][1]_out[57]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[305]_no0 chany[0][1]_out[57]_loadlvl[0]_midout chany[0][1]_out[57]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[58] density = 0, probability=0.***** -Vchany[0][1]_in[58] chany[0][1]_in[58] 0 -+ 0 -**** Load for rr_node[450] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=59, type=5 ***** -Xchan_chany[0][1]_out[59]_loadlvl[0]_out chany[0][1]_out[59] chany[0][1]_out[59]_loadlvl[0]_out chany[0][1]_out[59]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[306]_no0 chany[0][1]_out[59]_loadlvl[0]_out chany[0][1]_out[59]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 chany[0][1]_out[59]_loadlvl[0]_midout chany[0][1]_out[59]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 chany[0][1]_out[59]_loadlvl[0]_midout chany[0][1]_out[59]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[309]_no0 chany[0][1]_out[59]_loadlvl[0]_midout chany[0][1]_out[59]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 chany[0][1]_out[59]_loadlvl[0]_midout chany[0][1]_out[59]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[60] density = 0, probability=0.***** -Vchany[0][1]_in[60] chany[0][1]_in[60] 0 -+ 0 -**** Load for rr_node[452] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=61, type=5 ***** -Xchan_chany[0][1]_out[61]_loadlvl[0]_out chany[0][1]_out[61] chany[0][1]_out[61]_loadlvl[0]_out chany[0][1]_out[61]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[311]_no0 chany[0][1]_out[61]_loadlvl[0]_out chany[0][1]_out[61]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 chany[0][1]_out[61]_loadlvl[0]_midout chany[0][1]_out[61]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[313]_no0 chany[0][1]_out[61]_loadlvl[0]_midout chany[0][1]_out[61]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[62] density = 0, probability=0.***** -Vchany[0][1]_in[62] chany[0][1]_in[62] 0 -+ 0 -**** Load for rr_node[454] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=63, type=5 ***** -Xchan_chany[0][1]_out[63]_loadlvl[0]_out chany[0][1]_out[63] chany[0][1]_out[63]_loadlvl[0]_out chany[0][1]_out[63]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[314]_no0 chany[0][1]_out[63]_loadlvl[0]_out chany[0][1]_out[63]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 chany[0][1]_out[63]_loadlvl[0]_midout chany[0][1]_out[63]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 chany[0][1]_out[63]_loadlvl[0]_midout chany[0][1]_out[63]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 chany[0][1]_out[63]_loadlvl[0]_midout chany[0][1]_out[63]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[64] density = 0, probability=0.***** -Vchany[0][1]_in[64] chany[0][1]_in[64] 0 -+ 0 -**** Load for rr_node[456] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=65, type=5 ***** -Xchan_chany[0][1]_out[65]_loadlvl[0]_out chany[0][1]_out[65] chany[0][1]_out[65]_loadlvl[0]_out chany[0][1]_out[65]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[318]_no0 chany[0][1]_out[65]_loadlvl[0]_out chany[0][1]_out[65]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 chany[0][1]_out[65]_loadlvl[0]_midout chany[0][1]_out[65]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 chany[0][1]_out[65]_loadlvl[0]_midout chany[0][1]_out[65]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 chany[0][1]_out[65]_loadlvl[0]_midout chany[0][1]_out[65]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[66] density = 0, probability=0.***** -Vchany[0][1]_in[66] chany[0][1]_in[66] 0 -+ 0 -**** Load for rr_node[458] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=67, type=5 ***** -Xchan_chany[0][1]_out[67]_loadlvl[0]_out chany[0][1]_out[67] chany[0][1]_out[67]_loadlvl[0]_out chany[0][1]_out[67]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[322]_no0 chany[0][1]_out[67]_loadlvl[0]_out chany[0][1]_out[67]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 chany[0][1]_out[67]_loadlvl[0]_midout chany[0][1]_out[67]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[324]_no0 chany[0][1]_out[67]_loadlvl[0]_midout chany[0][1]_out[67]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[325]_no0 chany[0][1]_out[67]_loadlvl[0]_midout chany[0][1]_out[67]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[68] density = 0, probability=0.***** -Vchany[0][1]_in[68] chany[0][1]_in[68] 0 -+ 0 -**** Load for rr_node[460] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=69, type=5 ***** -Xchan_chany[0][1]_out[69]_loadlvl[0]_out chany[0][1]_out[69] chany[0][1]_out[69]_loadlvl[0]_out chany[0][1]_out[69]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[326]_no0 chany[0][1]_out[69]_loadlvl[0]_out chany[0][1]_out[69]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[327]_no0 chany[0][1]_out[69]_loadlvl[0]_midout chany[0][1]_out[69]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[328]_no0 chany[0][1]_out[69]_loadlvl[0]_midout chany[0][1]_out[69]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[329]_no0 chany[0][1]_out[69]_loadlvl[0]_midout chany[0][1]_out[69]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[70] density = 0, probability=0.***** -Vchany[0][1]_in[70] chany[0][1]_in[70] 0 -+ 0 -**** Load for rr_node[462] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=71, type=5 ***** -Xchan_chany[0][1]_out[71]_loadlvl[0]_out chany[0][1]_out[71] chany[0][1]_out[71]_loadlvl[0]_out chany[0][1]_out[71]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[330]_no0 chany[0][1]_out[71]_loadlvl[0]_out chany[0][1]_out[71]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[331]_no0 chany[0][1]_out[71]_loadlvl[0]_midout chany[0][1]_out[71]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[332]_no0 chany[0][1]_out[71]_loadlvl[0]_midout chany[0][1]_out[71]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[72] density = 0, probability=0.***** -Vchany[0][1]_in[72] chany[0][1]_in[72] 0 -+ 0 -**** Load for rr_node[464] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=73, type=5 ***** -Xchan_chany[0][1]_out[73]_loadlvl[0]_out chany[0][1]_out[73] chany[0][1]_out[73]_loadlvl[0]_out chany[0][1]_out[73]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[333]_no0 chany[0][1]_out[73]_loadlvl[0]_out chany[0][1]_out[73]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[334]_no0 chany[0][1]_out[73]_loadlvl[0]_midout chany[0][1]_out[73]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[335]_no0 chany[0][1]_out[73]_loadlvl[0]_midout chany[0][1]_out[73]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[336]_no0 chany[0][1]_out[73]_loadlvl[0]_midout chany[0][1]_out[73]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[337]_no0 chany[0][1]_out[73]_loadlvl[0]_midout chany[0][1]_out[73]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[74] density = 0, probability=0.***** -Vchany[0][1]_in[74] chany[0][1]_in[74] 0 -+ 0 -**** Load for rr_node[466] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=75, type=5 ***** -Xchan_chany[0][1]_out[75]_loadlvl[0]_out chany[0][1]_out[75] chany[0][1]_out[75]_loadlvl[0]_out chany[0][1]_out[75]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[338]_no0 chany[0][1]_out[75]_loadlvl[0]_out chany[0][1]_out[75]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[339]_no0 chany[0][1]_out[75]_loadlvl[0]_midout chany[0][1]_out[75]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[340]_no0 chany[0][1]_out[75]_loadlvl[0]_midout chany[0][1]_out[75]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[341]_no0 chany[0][1]_out[75]_loadlvl[0]_midout chany[0][1]_out[75]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[76] density = 0.2026, probability=0.4982.***** -Vchany[0][1]_in[76] chany[0][1]_in[76] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[468] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=77, type=5 ***** -Xchan_chany[0][1]_out[77]_loadlvl[0]_out chany[0][1]_out[77] chany[0][1]_out[77]_loadlvl[0]_out chany[0][1]_out[77]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[342]_no0 chany[0][1]_out[77]_loadlvl[0]_out chany[0][1]_out[77]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[343]_no0 chany[0][1]_out[77]_loadlvl[0]_midout chany[0][1]_out[77]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[344]_no0 chany[0][1]_out[77]_loadlvl[0]_midout chany[0][1]_out[77]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[78] density = 0, probability=0.***** -Vchany[0][1]_in[78] chany[0][1]_in[78] 0 -+ 0 -**** Load for rr_node[470] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=79, type=5 ***** -Xchan_chany[0][1]_out[79]_loadlvl[0]_out chany[0][1]_out[79] chany[0][1]_out[79]_loadlvl[0]_out chany[0][1]_out[79]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[345]_no0 chany[0][1]_out[79]_loadlvl[0]_out chany[0][1]_out[79]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[346]_no0 chany[0][1]_out[79]_loadlvl[0]_midout chany[0][1]_out[79]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[347]_no0 chany[0][1]_out[79]_loadlvl[0]_midout chany[0][1]_out[79]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[348]_no0 chany[0][1]_out[79]_loadlvl[0]_midout chany[0][1]_out[79]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[80] density = 0, probability=0.***** -Vchany[0][1]_in[80] chany[0][1]_in[80] 0 -+ 0 -**** Load for rr_node[472] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=81, type=5 ***** -Xchan_chany[0][1]_out[81]_loadlvl[0]_out chany[0][1]_out[81] chany[0][1]_out[81]_loadlvl[0]_out chany[0][1]_out[81]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[349]_no0 chany[0][1]_out[81]_loadlvl[0]_out chany[0][1]_out[81]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[350]_no0 chany[0][1]_out[81]_loadlvl[0]_midout chany[0][1]_out[81]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[351]_no0 chany[0][1]_out[81]_loadlvl[0]_midout chany[0][1]_out[81]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[352]_no0 chany[0][1]_out[81]_loadlvl[0]_midout chany[0][1]_out[81]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[82] density = 0, probability=0.***** -Vchany[0][1]_in[82] chany[0][1]_in[82] 0 -+ 0 -**** Load for rr_node[474] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=83, type=5 ***** -Xchan_chany[0][1]_out[83]_loadlvl[0]_out chany[0][1]_out[83] chany[0][1]_out[83]_loadlvl[0]_out chany[0][1]_out[83]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[353]_no0 chany[0][1]_out[83]_loadlvl[0]_out chany[0][1]_out[83]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[354]_no0 chany[0][1]_out[83]_loadlvl[0]_midout chany[0][1]_out[83]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[355]_no0 chany[0][1]_out[83]_loadlvl[0]_midout chany[0][1]_out[83]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[356]_no0 chany[0][1]_out[83]_loadlvl[0]_midout chany[0][1]_out[83]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[84] density = 0, probability=0.***** -Vchany[0][1]_in[84] chany[0][1]_in[84] 0 -+ 0 -**** Load for rr_node[476] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=85, type=5 ***** -Xchan_chany[0][1]_out[85]_loadlvl[0]_out chany[0][1]_out[85] chany[0][1]_out[85]_loadlvl[0]_out chany[0][1]_out[85]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[357]_no0 chany[0][1]_out[85]_loadlvl[0]_out chany[0][1]_out[85]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[358]_no0 chany[0][1]_out[85]_loadlvl[0]_midout chany[0][1]_out[85]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[359]_no0 chany[0][1]_out[85]_loadlvl[0]_midout chany[0][1]_out[85]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[360]_no0 chany[0][1]_out[85]_loadlvl[0]_midout chany[0][1]_out[85]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[86] density = 0, probability=0.***** -Vchany[0][1]_in[86] chany[0][1]_in[86] 0 -+ 0 -**** Load for rr_node[478] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=87, type=5 ***** -Xchan_chany[0][1]_out[87]_loadlvl[0]_out chany[0][1]_out[87] chany[0][1]_out[87]_loadlvl[0]_out chany[0][1]_out[87]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[361]_no0 chany[0][1]_out[87]_loadlvl[0]_out chany[0][1]_out[87]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[362]_no0 chany[0][1]_out[87]_loadlvl[0]_midout chany[0][1]_out[87]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[363]_no0 chany[0][1]_out[87]_loadlvl[0]_midout chany[0][1]_out[87]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[364]_no0 chany[0][1]_out[87]_loadlvl[0]_midout chany[0][1]_out[87]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[88] density = 0, probability=0.***** -Vchany[0][1]_in[88] chany[0][1]_in[88] 0 -+ 0 -**** Load for rr_node[480] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=89, type=5 ***** -Xchan_chany[0][1]_out[89]_loadlvl[0]_out chany[0][1]_out[89] chany[0][1]_out[89]_loadlvl[0]_out chany[0][1]_out[89]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[365]_no0 chany[0][1]_out[89]_loadlvl[0]_out chany[0][1]_out[89]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[366]_no0 chany[0][1]_out[89]_loadlvl[0]_midout chany[0][1]_out[89]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[367]_no0 chany[0][1]_out[89]_loadlvl[0]_midout chany[0][1]_out[89]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[368]_no0 chany[0][1]_out[89]_loadlvl[0]_midout chany[0][1]_out[89]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[90] density = 0, probability=0.***** -Vchany[0][1]_in[90] chany[0][1]_in[90] 0 -+ 0 -**** Load for rr_node[482] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=91, type=5 ***** -Xchan_chany[0][1]_out[91]_loadlvl[0]_out chany[0][1]_out[91] chany[0][1]_out[91]_loadlvl[0]_out chany[0][1]_out[91]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[369]_no0 chany[0][1]_out[91]_loadlvl[0]_out chany[0][1]_out[91]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[370]_no0 chany[0][1]_out[91]_loadlvl[0]_midout chany[0][1]_out[91]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[371]_no0 chany[0][1]_out[91]_loadlvl[0]_midout chany[0][1]_out[91]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[92] density = 0, probability=0.***** -Vchany[0][1]_in[92] chany[0][1]_in[92] 0 -+ 0 -**** Load for rr_node[484] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=93, type=5 ***** -Xchan_chany[0][1]_out[93]_loadlvl[0]_out chany[0][1]_out[93] chany[0][1]_out[93]_loadlvl[0]_out chany[0][1]_out[93]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[372]_no0 chany[0][1]_out[93]_loadlvl[0]_out chany[0][1]_out[93]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[373]_no0 chany[0][1]_out[93]_loadlvl[0]_midout chany[0][1]_out[93]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[374]_no0 chany[0][1]_out[93]_loadlvl[0]_midout chany[0][1]_out[93]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[375]_no0 chany[0][1]_out[93]_loadlvl[0]_midout chany[0][1]_out[93]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[94] density = 0, probability=0.***** -Vchany[0][1]_in[94] chany[0][1]_in[94] 0 -+ 0 -**** Load for rr_node[486] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=95, type=5 ***** -Xchan_chany[0][1]_out[95]_loadlvl[0]_out chany[0][1]_out[95] chany[0][1]_out[95]_loadlvl[0]_out chany[0][1]_out[95]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[376]_no0 chany[0][1]_out[95]_loadlvl[0]_out chany[0][1]_out[95]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[377]_no0 chany[0][1]_out[95]_loadlvl[0]_midout chany[0][1]_out[95]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[378]_no0 chany[0][1]_out[95]_loadlvl[0]_midout chany[0][1]_out[95]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[379]_no0 chany[0][1]_out[95]_loadlvl[0]_midout chany[0][1]_out[95]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[380]_no0 chany[0][1]_out[95]_loadlvl[0]_midout chany[0][1]_out[95]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[96] density = 0, probability=0.***** -Vchany[0][1]_in[96] chany[0][1]_in[96] 0 -+ 0 -**** Load for rr_node[488] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=97, type=5 ***** -Xchan_chany[0][1]_out[97]_loadlvl[0]_out chany[0][1]_out[97] chany[0][1]_out[97]_loadlvl[0]_out chany[0][1]_out[97]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[381]_no0 chany[0][1]_out[97]_loadlvl[0]_out chany[0][1]_out[97]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[382]_no0 chany[0][1]_out[97]_loadlvl[0]_midout chany[0][1]_out[97]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[383]_no0 chany[0][1]_out[97]_loadlvl[0]_midout chany[0][1]_out[97]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[0][1]_in[98] density = 0, probability=0.***** -Vchany[0][1]_in[98] chany[0][1]_in[98] 0 -+ 0 -**** Load for rr_node[490] ***** -**** Loads for rr_node: xlow=0, ylow=1, xhigh=0, yhigh=1, ptc_num=99, type=5 ***** -Xchan_chany[0][1]_out[99]_loadlvl[0]_out chany[0][1]_out[99] chany[0][1]_out[99]_loadlvl[0]_out chany[0][1]_out[99]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[384]_no0 chany[0][1]_out[99]_loadlvl[0]_out chany[0][1]_out[99]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[385]_no0 chany[0][1]_out[99]_loadlvl[0]_midout chany[0][1]_out[99]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[386]_no0 chany[0][1]_out[99]_loadlvl[0]_midout chany[0][1]_out[99]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[387]_no0 chany[0][1]_out[99]_loadlvl[0]_midout chany[0][1]_out[99]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Vgrid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][43] 0 -+ 0 -Vgrid[1][1]_pin[0][3][47] grid[1][1]_pin[0][3][47] 0 -+ 0 -Vgrid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][1] 0 -+ 0 -Vgrid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][3] 0 -+ 0 -Vgrid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][5] 0 -+ 0 -Vgrid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][7] 0 -+ 0 -Vgrid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][9] 0 -+ 0 -Vgrid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][11] 0 -+ 0 -Vgrid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][13] 0 -+ 0 -Vgrid[0][1]_pin[0][1][15] grid[0][1]_pin[0][1][15] 0 -+ 0 - - -***** Voltage supplies ***** -Vgvdd_sb[0][1] gvdd_sb[0][1] 0 vsp -Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_sb avg p(Vgvdd_sb[0][1]) from=0 to='clock_period' -.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_sb avg p(Vgvdd_sb[0][1]) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period' -.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_2/sb_tb/example_2_sb1_0_sb_testbench.sp b/examples/spice_test_example_2/sb_tb/example_2_sb1_0_sb_testbench.sp deleted file mode 100644 index 263405be2..000000000 --- a/examples/spice_test_example_2/sb_tb/example_2_sb1_0_sb_testbench.sp +++ /dev/null @@ -1,1109 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_sbs -****** Include subckt netlists: Switch Block[1][0] ***** -.include './spice_test_example_2/subckt/sb_1_0.sp' -***** Call defined Switch Box[1][0] ***** -Xsb[1][0] -+ chany[1][1]_out[0] chany[1][1]_in[1] chany[1][1]_out[2] chany[1][1]_in[3] chany[1][1]_out[4] chany[1][1]_in[5] chany[1][1]_out[6] chany[1][1]_in[7] chany[1][1]_out[8] chany[1][1]_in[9] chany[1][1]_out[10] chany[1][1]_in[11] chany[1][1]_out[12] chany[1][1]_in[13] chany[1][1]_out[14] chany[1][1]_in[15] chany[1][1]_out[16] chany[1][1]_in[17] chany[1][1]_out[18] chany[1][1]_in[19] chany[1][1]_out[20] chany[1][1]_in[21] chany[1][1]_out[22] chany[1][1]_in[23] chany[1][1]_out[24] chany[1][1]_in[25] chany[1][1]_out[26] chany[1][1]_in[27] chany[1][1]_out[28] chany[1][1]_in[29] chany[1][1]_out[30] chany[1][1]_in[31] chany[1][1]_out[32] chany[1][1]_in[33] chany[1][1]_out[34] chany[1][1]_in[35] chany[1][1]_out[36] chany[1][1]_in[37] chany[1][1]_out[38] chany[1][1]_in[39] chany[1][1]_out[40] chany[1][1]_in[41] chany[1][1]_out[42] chany[1][1]_in[43] chany[1][1]_out[44] chany[1][1]_in[45] chany[1][1]_out[46] chany[1][1]_in[47] chany[1][1]_out[48] chany[1][1]_in[49] chany[1][1]_out[50] chany[1][1]_in[51] chany[1][1]_out[52] chany[1][1]_in[53] chany[1][1]_out[54] chany[1][1]_in[55] chany[1][1]_out[56] chany[1][1]_in[57] chany[1][1]_out[58] chany[1][1]_in[59] chany[1][1]_out[60] chany[1][1]_in[61] chany[1][1]_out[62] chany[1][1]_in[63] chany[1][1]_out[64] chany[1][1]_in[65] chany[1][1]_out[66] chany[1][1]_in[67] chany[1][1]_out[68] chany[1][1]_in[69] chany[1][1]_out[70] chany[1][1]_in[71] chany[1][1]_out[72] chany[1][1]_in[73] chany[1][1]_out[74] chany[1][1]_in[75] chany[1][1]_out[76] chany[1][1]_in[77] chany[1][1]_out[78] chany[1][1]_in[79] chany[1][1]_out[80] chany[1][1]_in[81] chany[1][1]_out[82] chany[1][1]_in[83] chany[1][1]_out[84] chany[1][1]_in[85] chany[1][1]_out[86] chany[1][1]_in[87] chany[1][1]_out[88] chany[1][1]_in[89] chany[1][1]_out[90] chany[1][1]_in[91] chany[1][1]_out[92] chany[1][1]_in[93] chany[1][1]_out[94] chany[1][1]_in[95] chany[1][1]_out[96] chany[1][1]_in[97] chany[1][1]_out[98] chany[1][1]_in[99] -+ grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][49] grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] -+ -+ -+ -+ -+ chanx[1][0]_in[0] chanx[1][0]_out[1] chanx[1][0]_in[2] chanx[1][0]_out[3] chanx[1][0]_in[4] chanx[1][0]_out[5] chanx[1][0]_in[6] chanx[1][0]_out[7] chanx[1][0]_in[8] chanx[1][0]_out[9] chanx[1][0]_in[10] chanx[1][0]_out[11] chanx[1][0]_in[12] chanx[1][0]_out[13] chanx[1][0]_in[14] chanx[1][0]_out[15] chanx[1][0]_in[16] chanx[1][0]_out[17] chanx[1][0]_in[18] chanx[1][0]_out[19] chanx[1][0]_in[20] chanx[1][0]_out[21] chanx[1][0]_in[22] chanx[1][0]_out[23] chanx[1][0]_in[24] chanx[1][0]_out[25] chanx[1][0]_in[26] chanx[1][0]_out[27] chanx[1][0]_in[28] chanx[1][0]_out[29] chanx[1][0]_in[30] chanx[1][0]_out[31] chanx[1][0]_in[32] chanx[1][0]_out[33] chanx[1][0]_in[34] chanx[1][0]_out[35] chanx[1][0]_in[36] chanx[1][0]_out[37] chanx[1][0]_in[38] chanx[1][0]_out[39] chanx[1][0]_in[40] chanx[1][0]_out[41] chanx[1][0]_in[42] chanx[1][0]_out[43] chanx[1][0]_in[44] chanx[1][0]_out[45] chanx[1][0]_in[46] chanx[1][0]_out[47] chanx[1][0]_in[48] chanx[1][0]_out[49] chanx[1][0]_in[50] chanx[1][0]_out[51] chanx[1][0]_in[52] chanx[1][0]_out[53] chanx[1][0]_in[54] chanx[1][0]_out[55] chanx[1][0]_in[56] chanx[1][0]_out[57] chanx[1][0]_in[58] chanx[1][0]_out[59] chanx[1][0]_in[60] chanx[1][0]_out[61] chanx[1][0]_in[62] chanx[1][0]_out[63] chanx[1][0]_in[64] chanx[1][0]_out[65] chanx[1][0]_in[66] chanx[1][0]_out[67] chanx[1][0]_in[68] chanx[1][0]_out[69] chanx[1][0]_in[70] chanx[1][0]_out[71] chanx[1][0]_in[72] chanx[1][0]_out[73] chanx[1][0]_in[74] chanx[1][0]_out[75] chanx[1][0]_in[76] chanx[1][0]_out[77] chanx[1][0]_in[78] chanx[1][0]_out[79] chanx[1][0]_in[80] chanx[1][0]_out[81] chanx[1][0]_in[82] chanx[1][0]_out[83] chanx[1][0]_in[84] chanx[1][0]_out[85] chanx[1][0]_in[86] chanx[1][0]_out[87] chanx[1][0]_in[88] chanx[1][0]_out[89] chanx[1][0]_in[90] chanx[1][0]_out[91] chanx[1][0]_in[92] chanx[1][0]_out[93] chanx[1][0]_in[94] chanx[1][0]_out[95] chanx[1][0]_in[96] chanx[1][0]_out[97] chanx[1][0]_in[98] chanx[1][0]_out[99] -+ grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][46] grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ gvdd_sb[1][0] 0 sb[1][0] -**** Load for rr_node[491] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=0, type=5 ***** -Xchan_chany[1][1]_out[0]_loadlvl[0]_out chany[1][1]_out[0] chany[1][1]_out[0]_loadlvl[0]_out chany[1][1]_out[0]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 chany[1][1]_out[0]_loadlvl[0]_out chany[1][1]_out[0]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 chany[1][1]_out[0]_loadlvl[0]_midout chany[1][1]_out[0]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[1] density = 0, probability=0.***** -Vchany[1][1]_in[1] chany[1][1]_in[1] 0 -+ 0 -**** Load for rr_node[493] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=2, type=5 ***** -Xchan_chany[1][1]_out[2]_loadlvl[0]_out chany[1][1]_out[2] chany[1][1]_out[2]_loadlvl[0]_out chany[1][1]_out[2]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 chany[1][1]_out[2]_loadlvl[0]_out chany[1][1]_out[2]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 chany[1][1]_out[2]_loadlvl[0]_midout chany[1][1]_out[2]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 chany[1][1]_out[2]_loadlvl[0]_midout chany[1][1]_out[2]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[3] density = 0, probability=0.***** -Vchany[1][1]_in[3] chany[1][1]_in[3] 0 -+ 0 -**** Load for rr_node[495] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=4, type=5 ***** -Xchan_chany[1][1]_out[4]_loadlvl[0]_out chany[1][1]_out[4] chany[1][1]_out[4]_loadlvl[0]_out chany[1][1]_out[4]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[5]_no0 chany[1][1]_out[4]_loadlvl[0]_out chany[1][1]_out[4]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 chany[1][1]_out[4]_loadlvl[0]_midout chany[1][1]_out[4]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 chany[1][1]_out[4]_loadlvl[0]_midout chany[1][1]_out[4]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[5] density = 0, probability=0.***** -Vchany[1][1]_in[5] chany[1][1]_in[5] 0 -+ 0 -**** Load for rr_node[497] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=6, type=5 ***** -Xchan_chany[1][1]_out[6]_loadlvl[0]_out chany[1][1]_out[6] chany[1][1]_out[6]_loadlvl[0]_out chany[1][1]_out[6]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[8]_no0 chany[1][1]_out[6]_loadlvl[0]_out chany[1][1]_out[6]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 chany[1][1]_out[6]_loadlvl[0]_midout chany[1][1]_out[6]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 chany[1][1]_out[6]_loadlvl[0]_midout chany[1][1]_out[6]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[7] density = 0, probability=0.***** -Vchany[1][1]_in[7] chany[1][1]_in[7] 0 -+ 0 -**** Load for rr_node[499] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=8, type=5 ***** -Xchan_chany[1][1]_out[8]_loadlvl[0]_out chany[1][1]_out[8] chany[1][1]_out[8]_loadlvl[0]_out chany[1][1]_out[8]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[11]_no0 chany[1][1]_out[8]_loadlvl[0]_out chany[1][1]_out[8]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 chany[1][1]_out[8]_loadlvl[0]_midout chany[1][1]_out[8]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 chany[1][1]_out[8]_loadlvl[0]_midout chany[1][1]_out[8]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[9] density = 0, probability=0.***** -Vchany[1][1]_in[9] chany[1][1]_in[9] 0 -+ 0 -**** Load for rr_node[501] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=10, type=5 ***** -Xchan_chany[1][1]_out[10]_loadlvl[0]_out chany[1][1]_out[10] chany[1][1]_out[10]_loadlvl[0]_out chany[1][1]_out[10]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[14]_no0 chany[1][1]_out[10]_loadlvl[0]_out chany[1][1]_out[10]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 chany[1][1]_out[10]_loadlvl[0]_midout chany[1][1]_out[10]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[11] density = 0, probability=0.***** -Vchany[1][1]_in[11] chany[1][1]_in[11] 0 -+ 0 -**** Load for rr_node[503] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=12, type=5 ***** -Xchan_chany[1][1]_out[12]_loadlvl[0]_out chany[1][1]_out[12] chany[1][1]_out[12]_loadlvl[0]_out chany[1][1]_out[12]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[16]_no0 chany[1][1]_out[12]_loadlvl[0]_out chany[1][1]_out[12]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 chany[1][1]_out[12]_loadlvl[0]_midout chany[1][1]_out[12]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 chany[1][1]_out[12]_loadlvl[0]_midout chany[1][1]_out[12]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[13] density = 0, probability=0.***** -Vchany[1][1]_in[13] chany[1][1]_in[13] 0 -+ 0 -**** Load for rr_node[505] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=14, type=5 ***** -Xchan_chany[1][1]_out[14]_loadlvl[0]_out chany[1][1]_out[14] chany[1][1]_out[14]_loadlvl[0]_out chany[1][1]_out[14]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[19]_no0 chany[1][1]_out[14]_loadlvl[0]_out chany[1][1]_out[14]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 chany[1][1]_out[14]_loadlvl[0]_midout chany[1][1]_out[14]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[15] density = 0, probability=0.***** -Vchany[1][1]_in[15] chany[1][1]_in[15] 0 -+ 0 -**** Load for rr_node[507] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=16, type=5 ***** -Xchan_chany[1][1]_out[16]_loadlvl[0]_out chany[1][1]_out[16] chany[1][1]_out[16]_loadlvl[0]_out chany[1][1]_out[16]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[21]_no0 chany[1][1]_out[16]_loadlvl[0]_out chany[1][1]_out[16]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 chany[1][1]_out[16]_loadlvl[0]_midout chany[1][1]_out[16]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[17] density = 0, probability=0.***** -Vchany[1][1]_in[17] chany[1][1]_in[17] 0 -+ 0 -**** Load for rr_node[509] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=18, type=5 ***** -Xchan_chany[1][1]_out[18]_loadlvl[0]_out chany[1][1]_out[18] chany[1][1]_out[18]_loadlvl[0]_out chany[1][1]_out[18]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[23]_no0 chany[1][1]_out[18]_loadlvl[0]_out chany[1][1]_out[18]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 chany[1][1]_out[18]_loadlvl[0]_midout chany[1][1]_out[18]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 chany[1][1]_out[18]_loadlvl[0]_midout chany[1][1]_out[18]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[19] density = 0, probability=0.***** -Vchany[1][1]_in[19] chany[1][1]_in[19] 0 -+ 0 -**** Load for rr_node[511] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=20, type=5 ***** -Xchan_chany[1][1]_out[20]_loadlvl[0]_out chany[1][1]_out[20] chany[1][1]_out[20]_loadlvl[0]_out chany[1][1]_out[20]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[26]_no0 chany[1][1]_out[20]_loadlvl[0]_out chany[1][1]_out[20]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 chany[1][1]_out[20]_loadlvl[0]_midout chany[1][1]_out[20]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[21] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_in[21] chany[1][1]_in[21] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[513] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=22, type=5 ***** -Xchan_chany[1][1]_out[22]_loadlvl[0]_out chany[1][1]_out[22] chany[1][1]_out[22]_loadlvl[0]_out chany[1][1]_out[22]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[28]_no0 chany[1][1]_out[22]_loadlvl[0]_out chany[1][1]_out[22]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 chany[1][1]_out[22]_loadlvl[0]_midout chany[1][1]_out[22]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 chany[1][1]_out[22]_loadlvl[0]_midout chany[1][1]_out[22]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[23] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_in[23] chany[1][1]_in[23] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[515] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=24, type=5 ***** -Xchan_chany[1][1]_out[24]_loadlvl[0]_out chany[1][1]_out[24] chany[1][1]_out[24]_loadlvl[0]_out chany[1][1]_out[24]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[31]_no0 chany[1][1]_out[24]_loadlvl[0]_out chany[1][1]_out[24]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 chany[1][1]_out[24]_loadlvl[0]_midout chany[1][1]_out[24]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 chany[1][1]_out[24]_loadlvl[0]_midout chany[1][1]_out[24]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[25] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_in[25] chany[1][1]_in[25] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[517] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=26, type=5 ***** -Xchan_chany[1][1]_out[26]_loadlvl[0]_out chany[1][1]_out[26] chany[1][1]_out[26]_loadlvl[0]_out chany[1][1]_out[26]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[34]_no0 chany[1][1]_out[26]_loadlvl[0]_out chany[1][1]_out[26]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 chany[1][1]_out[26]_loadlvl[0]_midout chany[1][1]_out[26]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[27] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_in[27] chany[1][1]_in[27] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[519] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=28, type=5 ***** -Xchan_chany[1][1]_out[28]_loadlvl[0]_out chany[1][1]_out[28] chany[1][1]_out[28]_loadlvl[0]_out chany[1][1]_out[28]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[36]_no0 chany[1][1]_out[28]_loadlvl[0]_out chany[1][1]_out[28]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 chany[1][1]_out[28]_loadlvl[0]_midout chany[1][1]_out[28]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 chany[1][1]_out[28]_loadlvl[0]_midout chany[1][1]_out[28]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[29] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_in[29] chany[1][1]_in[29] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[521] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=30, type=5 ***** -Xchan_chany[1][1]_out[30]_loadlvl[0]_out chany[1][1]_out[30] chany[1][1]_out[30]_loadlvl[0]_out chany[1][1]_out[30]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[39]_no0 chany[1][1]_out[30]_loadlvl[0]_out chany[1][1]_out[30]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 chany[1][1]_out[30]_loadlvl[0]_midout chany[1][1]_out[30]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 chany[1][1]_out[30]_loadlvl[0]_midout chany[1][1]_out[30]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[31] density = 0, probability=0.***** -Vchany[1][1]_in[31] chany[1][1]_in[31] 0 -+ 0 -**** Load for rr_node[523] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=32, type=5 ***** -Xchan_chany[1][1]_out[32]_loadlvl[0]_out chany[1][1]_out[32] chany[1][1]_out[32]_loadlvl[0]_out chany[1][1]_out[32]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[42]_no0 chany[1][1]_out[32]_loadlvl[0]_out chany[1][1]_out[32]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 chany[1][1]_out[32]_loadlvl[0]_midout chany[1][1]_out[32]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 chany[1][1]_out[32]_loadlvl[0]_midout chany[1][1]_out[32]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[33] density = 0, probability=0.***** -Vchany[1][1]_in[33] chany[1][1]_in[33] 0 -+ 0 -**** Load for rr_node[525] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=34, type=5 ***** -Xchan_chany[1][1]_out[34]_loadlvl[0]_out chany[1][1]_out[34] chany[1][1]_out[34]_loadlvl[0]_out chany[1][1]_out[34]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[45]_no0 chany[1][1]_out[34]_loadlvl[0]_out chany[1][1]_out[34]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 chany[1][1]_out[34]_loadlvl[0]_midout chany[1][1]_out[34]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 chany[1][1]_out[34]_loadlvl[0]_midout chany[1][1]_out[34]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[35] density = 0, probability=0.***** -Vchany[1][1]_in[35] chany[1][1]_in[35] 0 -+ 0 -**** Load for rr_node[527] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=36, type=5 ***** -Xchan_chany[1][1]_out[36]_loadlvl[0]_out chany[1][1]_out[36] chany[1][1]_out[36]_loadlvl[0]_out chany[1][1]_out[36]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[48]_no0 chany[1][1]_out[36]_loadlvl[0]_out chany[1][1]_out[36]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 chany[1][1]_out[36]_loadlvl[0]_midout chany[1][1]_out[36]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[37] density = 0, probability=0.***** -Vchany[1][1]_in[37] chany[1][1]_in[37] 0 -+ 0 -**** Load for rr_node[529] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=38, type=5 ***** -Xchan_chany[1][1]_out[38]_loadlvl[0]_out chany[1][1]_out[38] chany[1][1]_out[38]_loadlvl[0]_out chany[1][1]_out[38]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[50]_no0 chany[1][1]_out[38]_loadlvl[0]_out chany[1][1]_out[38]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 chany[1][1]_out[38]_loadlvl[0]_midout chany[1][1]_out[38]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[39] density = 0, probability=0.***** -Vchany[1][1]_in[39] chany[1][1]_in[39] 0 -+ 0 -**** Load for rr_node[531] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=40, type=5 ***** -Xchan_chany[1][1]_out[40]_loadlvl[0]_out chany[1][1]_out[40] chany[1][1]_out[40]_loadlvl[0]_out chany[1][1]_out[40]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[52]_no0 chany[1][1]_out[40]_loadlvl[0]_out chany[1][1]_out[40]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 chany[1][1]_out[40]_loadlvl[0]_midout chany[1][1]_out[40]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[41] density = 0, probability=0.***** -Vchany[1][1]_in[41] chany[1][1]_in[41] 0 -+ 0 -**** Load for rr_node[533] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=42, type=5 ***** -Xchan_chany[1][1]_out[42]_loadlvl[0]_out chany[1][1]_out[42] chany[1][1]_out[42]_loadlvl[0]_out chany[1][1]_out[42]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[54]_no0 chany[1][1]_out[42]_loadlvl[0]_out chany[1][1]_out[42]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 chany[1][1]_out[42]_loadlvl[0]_midout chany[1][1]_out[42]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 chany[1][1]_out[42]_loadlvl[0]_midout chany[1][1]_out[42]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[43] density = 0, probability=0.***** -Vchany[1][1]_in[43] chany[1][1]_in[43] 0 -+ 0 -**** Load for rr_node[535] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=44, type=5 ***** -Xchan_chany[1][1]_out[44]_loadlvl[0]_out chany[1][1]_out[44] chany[1][1]_out[44]_loadlvl[0]_out chany[1][1]_out[44]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[57]_no0 chany[1][1]_out[44]_loadlvl[0]_out chany[1][1]_out[44]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 chany[1][1]_out[44]_loadlvl[0]_midout chany[1][1]_out[44]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 chany[1][1]_out[44]_loadlvl[0]_midout chany[1][1]_out[44]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[45] density = 0, probability=0.***** -Vchany[1][1]_in[45] chany[1][1]_in[45] 0 -+ 0 -**** Load for rr_node[537] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=46, type=5 ***** -Xchan_chany[1][1]_out[46]_loadlvl[0]_out chany[1][1]_out[46] chany[1][1]_out[46]_loadlvl[0]_out chany[1][1]_out[46]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[60]_no0 chany[1][1]_out[46]_loadlvl[0]_out chany[1][1]_out[46]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 chany[1][1]_out[46]_loadlvl[0]_midout chany[1][1]_out[46]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 chany[1][1]_out[46]_loadlvl[0]_midout chany[1][1]_out[46]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[47] density = 0, probability=0.***** -Vchany[1][1]_in[47] chany[1][1]_in[47] 0 -+ 0 -**** Load for rr_node[539] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=48, type=5 ***** -Xchan_chany[1][1]_out[48]_loadlvl[0]_out chany[1][1]_out[48] chany[1][1]_out[48]_loadlvl[0]_out chany[1][1]_out[48]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[63]_no0 chany[1][1]_out[48]_loadlvl[0]_out chany[1][1]_out[48]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 chany[1][1]_out[48]_loadlvl[0]_midout chany[1][1]_out[48]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 chany[1][1]_out[48]_loadlvl[0]_midout chany[1][1]_out[48]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[49] density = 0, probability=0.***** -Vchany[1][1]_in[49] chany[1][1]_in[49] 0 -+ 0 -**** Load for rr_node[541] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=50, type=5 ***** -Xchan_chany[1][1]_out[50]_loadlvl[0]_out chany[1][1]_out[50] chany[1][1]_out[50]_loadlvl[0]_out chany[1][1]_out[50]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[66]_no0 chany[1][1]_out[50]_loadlvl[0]_out chany[1][1]_out[50]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 chany[1][1]_out[50]_loadlvl[0]_midout chany[1][1]_out[50]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[51] density = 0, probability=0.***** -Vchany[1][1]_in[51] chany[1][1]_in[51] 0 -+ 0 -**** Load for rr_node[543] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=52, type=5 ***** -Xchan_chany[1][1]_out[52]_loadlvl[0]_out chany[1][1]_out[52] chany[1][1]_out[52]_loadlvl[0]_out chany[1][1]_out[52]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[68]_no0 chany[1][1]_out[52]_loadlvl[0]_out chany[1][1]_out[52]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 chany[1][1]_out[52]_loadlvl[0]_midout chany[1][1]_out[52]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 chany[1][1]_out[52]_loadlvl[0]_midout chany[1][1]_out[52]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[53] density = 0, probability=0.***** -Vchany[1][1]_in[53] chany[1][1]_in[53] 0 -+ 0 -**** Load for rr_node[545] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=54, type=5 ***** -Xchan_chany[1][1]_out[54]_loadlvl[0]_out chany[1][1]_out[54] chany[1][1]_out[54]_loadlvl[0]_out chany[1][1]_out[54]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[71]_no0 chany[1][1]_out[54]_loadlvl[0]_out chany[1][1]_out[54]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 chany[1][1]_out[54]_loadlvl[0]_midout chany[1][1]_out[54]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[55] density = 0, probability=0.***** -Vchany[1][1]_in[55] chany[1][1]_in[55] 0 -+ 0 -**** Load for rr_node[547] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=56, type=5 ***** -Xchan_chany[1][1]_out[56]_loadlvl[0]_out chany[1][1]_out[56] chany[1][1]_out[56]_loadlvl[0]_out chany[1][1]_out[56]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[73]_no0 chany[1][1]_out[56]_loadlvl[0]_out chany[1][1]_out[56]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 chany[1][1]_out[56]_loadlvl[0]_midout chany[1][1]_out[56]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[57] density = 0, probability=0.***** -Vchany[1][1]_in[57] chany[1][1]_in[57] 0 -+ 0 -**** Load for rr_node[549] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=58, type=5 ***** -Xchan_chany[1][1]_out[58]_loadlvl[0]_out chany[1][1]_out[58] chany[1][1]_out[58]_loadlvl[0]_out chany[1][1]_out[58]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[75]_no0 chany[1][1]_out[58]_loadlvl[0]_out chany[1][1]_out[58]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 chany[1][1]_out[58]_loadlvl[0]_midout chany[1][1]_out[58]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 chany[1][1]_out[58]_loadlvl[0]_midout chany[1][1]_out[58]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[59] density = 0, probability=0.***** -Vchany[1][1]_in[59] chany[1][1]_in[59] 0 -+ 0 -**** Load for rr_node[551] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=60, type=5 ***** -Xchan_chany[1][1]_out[60]_loadlvl[0]_out chany[1][1]_out[60] chany[1][1]_out[60]_loadlvl[0]_out chany[1][1]_out[60]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[78]_no0 chany[1][1]_out[60]_loadlvl[0]_out chany[1][1]_out[60]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 chany[1][1]_out[60]_loadlvl[0]_midout chany[1][1]_out[60]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[61] density = 0, probability=0.***** -Vchany[1][1]_in[61] chany[1][1]_in[61] 0 -+ 0 -**** Load for rr_node[553] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=62, type=5 ***** -Xchan_chany[1][1]_out[62]_loadlvl[0]_out chany[1][1]_out[62] chany[1][1]_out[62]_loadlvl[0]_out chany[1][1]_out[62]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[80]_no0 chany[1][1]_out[62]_loadlvl[0]_out chany[1][1]_out[62]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 chany[1][1]_out[62]_loadlvl[0]_midout chany[1][1]_out[62]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 chany[1][1]_out[62]_loadlvl[0]_midout chany[1][1]_out[62]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[63] density = 0, probability=0.***** -Vchany[1][1]_in[63] chany[1][1]_in[63] 0 -+ 0 -**** Load for rr_node[555] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=64, type=5 ***** -Xchan_chany[1][1]_out[64]_loadlvl[0]_out chany[1][1]_out[64] chany[1][1]_out[64]_loadlvl[0]_out chany[1][1]_out[64]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[83]_no0 chany[1][1]_out[64]_loadlvl[0]_out chany[1][1]_out[64]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 chany[1][1]_out[64]_loadlvl[0]_midout chany[1][1]_out[64]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 chany[1][1]_out[64]_loadlvl[0]_midout chany[1][1]_out[64]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[65] density = 0, probability=0.***** -Vchany[1][1]_in[65] chany[1][1]_in[65] 0 -+ 0 -**** Load for rr_node[557] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=66, type=5 ***** -Xchan_chany[1][1]_out[66]_loadlvl[0]_out chany[1][1]_out[66] chany[1][1]_out[66]_loadlvl[0]_out chany[1][1]_out[66]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[86]_no0 chany[1][1]_out[66]_loadlvl[0]_out chany[1][1]_out[66]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 chany[1][1]_out[66]_loadlvl[0]_midout chany[1][1]_out[66]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 chany[1][1]_out[66]_loadlvl[0]_midout chany[1][1]_out[66]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[67] density = 0, probability=0.***** -Vchany[1][1]_in[67] chany[1][1]_in[67] 0 -+ 0 -**** Load for rr_node[559] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=68, type=5 ***** -Xchan_chany[1][1]_out[68]_loadlvl[0]_out chany[1][1]_out[68] chany[1][1]_out[68]_loadlvl[0]_out chany[1][1]_out[68]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[89]_no0 chany[1][1]_out[68]_loadlvl[0]_out chany[1][1]_out[68]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 chany[1][1]_out[68]_loadlvl[0]_midout chany[1][1]_out[68]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[69] density = 0, probability=0.***** -Vchany[1][1]_in[69] chany[1][1]_in[69] 0 -+ 0 -**** Load for rr_node[561] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=70, type=5 ***** -Xchan_chany[1][1]_out[70]_loadlvl[0]_out chany[1][1]_out[70] chany[1][1]_out[70]_loadlvl[0]_out chany[1][1]_out[70]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[91]_no0 chany[1][1]_out[70]_loadlvl[0]_out chany[1][1]_out[70]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 chany[1][1]_out[70]_loadlvl[0]_midout chany[1][1]_out[70]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 chany[1][1]_out[70]_loadlvl[0]_midout chany[1][1]_out[70]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[71] density = 0, probability=0.***** -Vchany[1][1]_in[71] chany[1][1]_in[71] 0 -+ 0 -**** Load for rr_node[563] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=72, type=5 ***** -Xchan_chany[1][1]_out[72]_loadlvl[0]_out chany[1][1]_out[72] chany[1][1]_out[72]_loadlvl[0]_out chany[1][1]_out[72]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[94]_no0 chany[1][1]_out[72]_loadlvl[0]_out chany[1][1]_out[72]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 chany[1][1]_out[72]_loadlvl[0]_midout chany[1][1]_out[72]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[73] density = 0, probability=0.***** -Vchany[1][1]_in[73] chany[1][1]_in[73] 0 -+ 0 -**** Load for rr_node[565] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=74, type=5 ***** -Xchan_chany[1][1]_out[74]_loadlvl[0]_out chany[1][1]_out[74] chany[1][1]_out[74]_loadlvl[0]_out chany[1][1]_out[74]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[96]_no0 chany[1][1]_out[74]_loadlvl[0]_out chany[1][1]_out[74]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 chany[1][1]_out[74]_loadlvl[0]_midout chany[1][1]_out[74]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 chany[1][1]_out[74]_loadlvl[0]_midout chany[1][1]_out[74]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[75] density = 0, probability=0.***** -Vchany[1][1]_in[75] chany[1][1]_in[75] 0 -+ 0 -**** Load for rr_node[567] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=76, type=5 ***** -Xchan_chany[1][1]_out[76]_loadlvl[0]_out chany[1][1]_out[76] chany[1][1]_out[76]_loadlvl[0]_out chany[1][1]_out[76]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[99]_no0 chany[1][1]_out[76]_loadlvl[0]_out chany[1][1]_out[76]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 chany[1][1]_out[76]_loadlvl[0]_midout chany[1][1]_out[76]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 chany[1][1]_out[76]_loadlvl[0]_midout chany[1][1]_out[76]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[77] density = 0, probability=0.***** -Vchany[1][1]_in[77] chany[1][1]_in[77] 0 -+ 0 -**** Load for rr_node[569] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=78, type=5 ***** -Xchan_chany[1][1]_out[78]_loadlvl[0]_out chany[1][1]_out[78] chany[1][1]_out[78]_loadlvl[0]_out chany[1][1]_out[78]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[102]_no0 chany[1][1]_out[78]_loadlvl[0]_out chany[1][1]_out[78]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 chany[1][1]_out[78]_loadlvl[0]_midout chany[1][1]_out[78]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[79] density = 0, probability=0.***** -Vchany[1][1]_in[79] chany[1][1]_in[79] 0 -+ 0 -**** Load for rr_node[571] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=80, type=5 ***** -Xchan_chany[1][1]_out[80]_loadlvl[0]_out chany[1][1]_out[80] chany[1][1]_out[80]_loadlvl[0]_out chany[1][1]_out[80]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[104]_no0 chany[1][1]_out[80]_loadlvl[0]_out chany[1][1]_out[80]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 chany[1][1]_out[80]_loadlvl[0]_midout chany[1][1]_out[80]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 chany[1][1]_out[80]_loadlvl[0]_midout chany[1][1]_out[80]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[81] density = 0, probability=0.***** -Vchany[1][1]_in[81] chany[1][1]_in[81] 0 -+ 0 -**** Load for rr_node[573] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=82, type=5 ***** -Xchan_chany[1][1]_out[82]_loadlvl[0]_out chany[1][1]_out[82] chany[1][1]_out[82]_loadlvl[0]_out chany[1][1]_out[82]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[107]_no0 chany[1][1]_out[82]_loadlvl[0]_out chany[1][1]_out[82]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 chany[1][1]_out[82]_loadlvl[0]_midout chany[1][1]_out[82]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[83] density = 0, probability=0.***** -Vchany[1][1]_in[83] chany[1][1]_in[83] 0 -+ 0 -**** Load for rr_node[575] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=84, type=5 ***** -Xchan_chany[1][1]_out[84]_loadlvl[0]_out chany[1][1]_out[84] chany[1][1]_out[84]_loadlvl[0]_out chany[1][1]_out[84]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[109]_no0 chany[1][1]_out[84]_loadlvl[0]_out chany[1][1]_out[84]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 chany[1][1]_out[84]_loadlvl[0]_midout chany[1][1]_out[84]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 chany[1][1]_out[84]_loadlvl[0]_midout chany[1][1]_out[84]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[85] density = 0, probability=0.***** -Vchany[1][1]_in[85] chany[1][1]_in[85] 0 -+ 0 -**** Load for rr_node[577] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=86, type=5 ***** -Xchan_chany[1][1]_out[86]_loadlvl[0]_out chany[1][1]_out[86] chany[1][1]_out[86]_loadlvl[0]_out chany[1][1]_out[86]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[112]_no0 chany[1][1]_out[86]_loadlvl[0]_out chany[1][1]_out[86]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 chany[1][1]_out[86]_loadlvl[0]_midout chany[1][1]_out[86]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 chany[1][1]_out[86]_loadlvl[0]_midout chany[1][1]_out[86]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[87] density = 0, probability=0.***** -Vchany[1][1]_in[87] chany[1][1]_in[87] 0 -+ 0 -**** Load for rr_node[579] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=88, type=5 ***** -Xchan_chany[1][1]_out[88]_loadlvl[0]_out chany[1][1]_out[88] chany[1][1]_out[88]_loadlvl[0]_out chany[1][1]_out[88]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[115]_no0 chany[1][1]_out[88]_loadlvl[0]_out chany[1][1]_out[88]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 chany[1][1]_out[88]_loadlvl[0]_midout chany[1][1]_out[88]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[89] density = 0, probability=0.***** -Vchany[1][1]_in[89] chany[1][1]_in[89] 0 -+ 0 -**** Load for rr_node[581] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=90, type=5 ***** -Xchan_chany[1][1]_out[90]_loadlvl[0]_out chany[1][1]_out[90] chany[1][1]_out[90]_loadlvl[0]_out chany[1][1]_out[90]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[117]_no0 chany[1][1]_out[90]_loadlvl[0]_out chany[1][1]_out[90]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 chany[1][1]_out[90]_loadlvl[0]_midout chany[1][1]_out[90]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 chany[1][1]_out[90]_loadlvl[0]_midout chany[1][1]_out[90]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[91] density = 0, probability=0.***** -Vchany[1][1]_in[91] chany[1][1]_in[91] 0 -+ 0 -**** Load for rr_node[583] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=92, type=5 ***** -Xchan_chany[1][1]_out[92]_loadlvl[0]_out chany[1][1]_out[92] chany[1][1]_out[92]_loadlvl[0]_out chany[1][1]_out[92]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[120]_no0 chany[1][1]_out[92]_loadlvl[0]_out chany[1][1]_out[92]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 chany[1][1]_out[92]_loadlvl[0]_midout chany[1][1]_out[92]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[93] density = 0, probability=0.***** -Vchany[1][1]_in[93] chany[1][1]_in[93] 0 -+ 0 -**** Load for rr_node[585] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=94, type=5 ***** -Xchan_chany[1][1]_out[94]_loadlvl[0]_out chany[1][1]_out[94] chany[1][1]_out[94]_loadlvl[0]_out chany[1][1]_out[94]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[122]_no0 chany[1][1]_out[94]_loadlvl[0]_out chany[1][1]_out[94]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 chany[1][1]_out[94]_loadlvl[0]_midout chany[1][1]_out[94]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 chany[1][1]_out[94]_loadlvl[0]_midout chany[1][1]_out[94]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[95] density = 0, probability=0.***** -Vchany[1][1]_in[95] chany[1][1]_in[95] 0 -+ 0 -**** Load for rr_node[587] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=96, type=5 ***** -Xchan_chany[1][1]_out[96]_loadlvl[0]_out chany[1][1]_out[96] chany[1][1]_out[96]_loadlvl[0]_out chany[1][1]_out[96]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[125]_no0 chany[1][1]_out[96]_loadlvl[0]_out chany[1][1]_out[96]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 chany[1][1]_out[96]_loadlvl[0]_midout chany[1][1]_out[96]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 chany[1][1]_out[96]_loadlvl[0]_midout chany[1][1]_out[96]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[97] density = 0, probability=0.***** -Vchany[1][1]_in[97] chany[1][1]_in[97] 0 -+ 0 -**** Load for rr_node[589] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=98, type=5 ***** -Xchan_chany[1][1]_out[98]_loadlvl[0]_out chany[1][1]_out[98] chany[1][1]_out[98]_loadlvl[0]_out chany[1][1]_out[98]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[128]_no0 chany[1][1]_out[98]_loadlvl[0]_out chany[1][1]_out[98]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 chany[1][1]_out[98]_loadlvl[0]_midout chany[1][1]_out[98]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[99] density = 0, probability=0.***** -Vchany[1][1]_in[99] chany[1][1]_in[99] 0 -+ 0 -Vgrid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41] 0 -+ 0 -Vgrid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45] 0 -+ 0 -Vgrid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgrid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][1] 0 -+ 0 -Vgrid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][3] 0 -+ 0 -Vgrid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][5] 0 -+ 0 -Vgrid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][7] 0 -+ 0 -Vgrid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][9] 0 -+ 0 -Vgrid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][11] 0 -+ 0 -Vgrid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][13] 0 -+ 0 -Vgrid[2][1]_pin[0][3][15] grid[2][1]_pin[0][3][15] 0 -+ 0 - - - -***** Signal chanx[1][0]_in[0] density = 0, probability=0.***** -Vchanx[1][0]_in[0] chanx[1][0]_in[0] 0 -+ 0 -**** Load for rr_node[192] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=1, type=4 ***** -Xchan_chanx[1][0]_out[1]_loadlvl[0]_out chanx[1][0]_out[1] chanx[1][0]_out[1]_loadlvl[0]_out chanx[1][0]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[130]_no0 chanx[1][0]_out[1]_loadlvl[0]_out chanx[1][0]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 chanx[1][0]_out[1]_loadlvl[0]_midout chanx[1][0]_out[1]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 chanx[1][0]_out[1]_loadlvl[0]_midout chanx[1][0]_out[1]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 chanx[1][0]_out[1]_loadlvl[0]_midout chanx[1][0]_out[1]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 chanx[1][0]_out[1]_loadlvl[0]_midout chanx[1][0]_out[1]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[2] density = 0, probability=0.***** -Vchanx[1][0]_in[2] chanx[1][0]_in[2] 0 -+ 0 -**** Load for rr_node[194] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=3, type=4 ***** -Xchan_chanx[1][0]_out[3]_loadlvl[0]_out chanx[1][0]_out[3] chanx[1][0]_out[3]_loadlvl[0]_out chanx[1][0]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[135]_no0 chanx[1][0]_out[3]_loadlvl[0]_out chanx[1][0]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 chanx[1][0]_out[3]_loadlvl[0]_midout chanx[1][0]_out[3]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 chanx[1][0]_out[3]_loadlvl[0]_midout chanx[1][0]_out[3]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[4] density = 0, probability=0.***** -Vchanx[1][0]_in[4] chanx[1][0]_in[4] 0 -+ 0 -**** Load for rr_node[196] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=5, type=4 ***** -Xchan_chanx[1][0]_out[5]_loadlvl[0]_out chanx[1][0]_out[5] chanx[1][0]_out[5]_loadlvl[0]_out chanx[1][0]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[138]_no0 chanx[1][0]_out[5]_loadlvl[0]_out chanx[1][0]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 chanx[1][0]_out[5]_loadlvl[0]_midout chanx[1][0]_out[5]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 chanx[1][0]_out[5]_loadlvl[0]_midout chanx[1][0]_out[5]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 chanx[1][0]_out[5]_loadlvl[0]_midout chanx[1][0]_out[5]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[6] density = 0, probability=0.***** -Vchanx[1][0]_in[6] chanx[1][0]_in[6] 0 -+ 0 -**** Load for rr_node[198] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=7, type=4 ***** -Xchan_chanx[1][0]_out[7]_loadlvl[0]_out chanx[1][0]_out[7] chanx[1][0]_out[7]_loadlvl[0]_out chanx[1][0]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[142]_no0 chanx[1][0]_out[7]_loadlvl[0]_out chanx[1][0]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 chanx[1][0]_out[7]_loadlvl[0]_midout chanx[1][0]_out[7]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 chanx[1][0]_out[7]_loadlvl[0]_midout chanx[1][0]_out[7]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 chanx[1][0]_out[7]_loadlvl[0]_midout chanx[1][0]_out[7]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[8] density = 0, probability=0.***** -Vchanx[1][0]_in[8] chanx[1][0]_in[8] 0 -+ 0 -**** Load for rr_node[200] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=9, type=4 ***** -Xchan_chanx[1][0]_out[9]_loadlvl[0]_out chanx[1][0]_out[9] chanx[1][0]_out[9]_loadlvl[0]_out chanx[1][0]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[146]_no0 chanx[1][0]_out[9]_loadlvl[0]_out chanx[1][0]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 chanx[1][0]_out[9]_loadlvl[0]_midout chanx[1][0]_out[9]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 chanx[1][0]_out[9]_loadlvl[0]_midout chanx[1][0]_out[9]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 chanx[1][0]_out[9]_loadlvl[0]_midout chanx[1][0]_out[9]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[10] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_in[10] chanx[1][0]_in[10] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[202] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=11, type=4 ***** -Xchan_chanx[1][0]_out[11]_loadlvl[0]_out chanx[1][0]_out[11] chanx[1][0]_out[11]_loadlvl[0]_out chanx[1][0]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[150]_no0 chanx[1][0]_out[11]_loadlvl[0]_out chanx[1][0]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[151]_no0 chanx[1][0]_out[11]_loadlvl[0]_midout chanx[1][0]_out[11]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 chanx[1][0]_out[11]_loadlvl[0]_midout chanx[1][0]_out[11]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 chanx[1][0]_out[11]_loadlvl[0]_midout chanx[1][0]_out[11]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[12] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_in[12] chanx[1][0]_in[12] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[204] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=13, type=4 ***** -Xchan_chanx[1][0]_out[13]_loadlvl[0]_out chanx[1][0]_out[13] chanx[1][0]_out[13]_loadlvl[0]_out chanx[1][0]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[154]_no0 chanx[1][0]_out[13]_loadlvl[0]_out chanx[1][0]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[155]_no0 chanx[1][0]_out[13]_loadlvl[0]_midout chanx[1][0]_out[13]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 chanx[1][0]_out[13]_loadlvl[0]_midout chanx[1][0]_out[13]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[14] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_in[14] chanx[1][0]_in[14] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[206] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=15, type=4 ***** -Xchan_chanx[1][0]_out[15]_loadlvl[0]_out chanx[1][0]_out[15] chanx[1][0]_out[15]_loadlvl[0]_out chanx[1][0]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[157]_no0 chanx[1][0]_out[15]_loadlvl[0]_out chanx[1][0]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[158]_no0 chanx[1][0]_out[15]_loadlvl[0]_midout chanx[1][0]_out[15]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 chanx[1][0]_out[15]_loadlvl[0]_midout chanx[1][0]_out[15]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 chanx[1][0]_out[15]_loadlvl[0]_midout chanx[1][0]_out[15]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[161]_no0 chanx[1][0]_out[15]_loadlvl[0]_midout chanx[1][0]_out[15]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[16] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_in[16] chanx[1][0]_in[16] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[208] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=17, type=4 ***** -Xchan_chanx[1][0]_out[17]_loadlvl[0]_out chanx[1][0]_out[17] chanx[1][0]_out[17]_loadlvl[0]_out chanx[1][0]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[162]_no0 chanx[1][0]_out[17]_loadlvl[0]_out chanx[1][0]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 chanx[1][0]_out[17]_loadlvl[0]_midout chanx[1][0]_out[17]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[164]_no0 chanx[1][0]_out[17]_loadlvl[0]_midout chanx[1][0]_out[17]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[18] density = 0.2026, probability=0.5018.***** -Vchanx[1][0]_in[18] chanx[1][0]_in[18] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[210] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=19, type=4 ***** -Xchan_chanx[1][0]_out[19]_loadlvl[0]_out chanx[1][0]_out[19] chanx[1][0]_out[19]_loadlvl[0]_out chanx[1][0]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[165]_no0 chanx[1][0]_out[19]_loadlvl[0]_out chanx[1][0]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 chanx[1][0]_out[19]_loadlvl[0]_midout chanx[1][0]_out[19]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 chanx[1][0]_out[19]_loadlvl[0]_midout chanx[1][0]_out[19]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[168]_no0 chanx[1][0]_out[19]_loadlvl[0]_midout chanx[1][0]_out[19]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[20] density = 0, probability=0.***** -Vchanx[1][0]_in[20] chanx[1][0]_in[20] 0 -+ 0 -**** Load for rr_node[212] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=21, type=4 ***** -Xchan_chanx[1][0]_out[21]_loadlvl[0]_out chanx[1][0]_out[21] chanx[1][0]_out[21]_loadlvl[0]_out chanx[1][0]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[169]_no0 chanx[1][0]_out[21]_loadlvl[0]_out chanx[1][0]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 chanx[1][0]_out[21]_loadlvl[0]_midout chanx[1][0]_out[21]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 chanx[1][0]_out[21]_loadlvl[0]_midout chanx[1][0]_out[21]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[172]_no0 chanx[1][0]_out[21]_loadlvl[0]_midout chanx[1][0]_out[21]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 chanx[1][0]_out[21]_loadlvl[0]_midout chanx[1][0]_out[21]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[22] density = 0, probability=0.***** -Vchanx[1][0]_in[22] chanx[1][0]_in[22] 0 -+ 0 -**** Load for rr_node[214] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=23, type=4 ***** -Xchan_chanx[1][0]_out[23]_loadlvl[0]_out chanx[1][0]_out[23] chanx[1][0]_out[23]_loadlvl[0]_out chanx[1][0]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[174]_no0 chanx[1][0]_out[23]_loadlvl[0]_out chanx[1][0]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 chanx[1][0]_out[23]_loadlvl[0]_midout chanx[1][0]_out[23]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 chanx[1][0]_out[23]_loadlvl[0]_midout chanx[1][0]_out[23]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[24] density = 0, probability=0.***** -Vchanx[1][0]_in[24] chanx[1][0]_in[24] 0 -+ 0 -**** Load for rr_node[216] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=25, type=4 ***** -Xchan_chanx[1][0]_out[25]_loadlvl[0]_out chanx[1][0]_out[25] chanx[1][0]_out[25]_loadlvl[0]_out chanx[1][0]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[177]_no0 chanx[1][0]_out[25]_loadlvl[0]_out chanx[1][0]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 chanx[1][0]_out[25]_loadlvl[0]_midout chanx[1][0]_out[25]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 chanx[1][0]_out[25]_loadlvl[0]_midout chanx[1][0]_out[25]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[180]_no0 chanx[1][0]_out[25]_loadlvl[0]_midout chanx[1][0]_out[25]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[26] density = 0, probability=0.***** -Vchanx[1][0]_in[26] chanx[1][0]_in[26] 0 -+ 0 -**** Load for rr_node[218] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=27, type=4 ***** -Xchan_chanx[1][0]_out[27]_loadlvl[0]_out chanx[1][0]_out[27] chanx[1][0]_out[27]_loadlvl[0]_out chanx[1][0]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[181]_no0 chanx[1][0]_out[27]_loadlvl[0]_out chanx[1][0]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 chanx[1][0]_out[27]_loadlvl[0]_midout chanx[1][0]_out[27]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 chanx[1][0]_out[27]_loadlvl[0]_midout chanx[1][0]_out[27]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[28] density = 0, probability=0.***** -Vchanx[1][0]_in[28] chanx[1][0]_in[28] 0 -+ 0 -**** Load for rr_node[220] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=29, type=4 ***** -Xchan_chanx[1][0]_out[29]_loadlvl[0]_out chanx[1][0]_out[29] chanx[1][0]_out[29]_loadlvl[0]_out chanx[1][0]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[184]_no0 chanx[1][0]_out[29]_loadlvl[0]_out chanx[1][0]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 chanx[1][0]_out[29]_loadlvl[0]_midout chanx[1][0]_out[29]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 chanx[1][0]_out[29]_loadlvl[0]_midout chanx[1][0]_out[29]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 chanx[1][0]_out[29]_loadlvl[0]_midout chanx[1][0]_out[29]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[188]_no0 chanx[1][0]_out[29]_loadlvl[0]_midout chanx[1][0]_out[29]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[30] density = 0, probability=0.***** -Vchanx[1][0]_in[30] chanx[1][0]_in[30] 0 -+ 0 -**** Load for rr_node[222] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=31, type=4 ***** -Xchan_chanx[1][0]_out[31]_loadlvl[0]_out chanx[1][0]_out[31] chanx[1][0]_out[31]_loadlvl[0]_out chanx[1][0]_out[31]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[189]_no0 chanx[1][0]_out[31]_loadlvl[0]_out chanx[1][0]_out[31]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 chanx[1][0]_out[31]_loadlvl[0]_midout chanx[1][0]_out[31]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 chanx[1][0]_out[31]_loadlvl[0]_midout chanx[1][0]_out[31]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[192]_no0 chanx[1][0]_out[31]_loadlvl[0]_midout chanx[1][0]_out[31]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[32] density = 0, probability=0.***** -Vchanx[1][0]_in[32] chanx[1][0]_in[32] 0 -+ 0 -**** Load for rr_node[224] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=33, type=4 ***** -Xchan_chanx[1][0]_out[33]_loadlvl[0]_out chanx[1][0]_out[33] chanx[1][0]_out[33]_loadlvl[0]_out chanx[1][0]_out[33]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[193]_no0 chanx[1][0]_out[33]_loadlvl[0]_out chanx[1][0]_out[33]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 chanx[1][0]_out[33]_loadlvl[0]_midout chanx[1][0]_out[33]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[195]_no0 chanx[1][0]_out[33]_loadlvl[0]_midout chanx[1][0]_out[33]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[34] density = 0, probability=0.***** -Vchanx[1][0]_in[34] chanx[1][0]_in[34] 0 -+ 0 -**** Load for rr_node[226] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=35, type=4 ***** -Xchan_chanx[1][0]_out[35]_loadlvl[0]_out chanx[1][0]_out[35] chanx[1][0]_out[35]_loadlvl[0]_out chanx[1][0]_out[35]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[196]_no0 chanx[1][0]_out[35]_loadlvl[0]_out chanx[1][0]_out[35]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 chanx[1][0]_out[35]_loadlvl[0]_midout chanx[1][0]_out[35]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 chanx[1][0]_out[35]_loadlvl[0]_midout chanx[1][0]_out[35]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[199]_no0 chanx[1][0]_out[35]_loadlvl[0]_midout chanx[1][0]_out[35]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 chanx[1][0]_out[35]_loadlvl[0]_midout chanx[1][0]_out[35]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[36] density = 0, probability=0.***** -Vchanx[1][0]_in[36] chanx[1][0]_in[36] 0 -+ 0 -**** Load for rr_node[228] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=37, type=4 ***** -Xchan_chanx[1][0]_out[37]_loadlvl[0]_out chanx[1][0]_out[37] chanx[1][0]_out[37]_loadlvl[0]_out chanx[1][0]_out[37]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[201]_no0 chanx[1][0]_out[37]_loadlvl[0]_out chanx[1][0]_out[37]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 chanx[1][0]_out[37]_loadlvl[0]_midout chanx[1][0]_out[37]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[203]_no0 chanx[1][0]_out[37]_loadlvl[0]_midout chanx[1][0]_out[37]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[38] density = 0, probability=0.***** -Vchanx[1][0]_in[38] chanx[1][0]_in[38] 0 -+ 0 -**** Load for rr_node[230] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=39, type=4 ***** -Xchan_chanx[1][0]_out[39]_loadlvl[0]_out chanx[1][0]_out[39] chanx[1][0]_out[39]_loadlvl[0]_out chanx[1][0]_out[39]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[204]_no0 chanx[1][0]_out[39]_loadlvl[0]_out chanx[1][0]_out[39]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 chanx[1][0]_out[39]_loadlvl[0]_midout chanx[1][0]_out[39]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 chanx[1][0]_out[39]_loadlvl[0]_midout chanx[1][0]_out[39]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 chanx[1][0]_out[39]_loadlvl[0]_midout chanx[1][0]_out[39]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[40] density = 0, probability=0.***** -Vchanx[1][0]_in[40] chanx[1][0]_in[40] 0 -+ 0 -**** Load for rr_node[232] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=41, type=4 ***** -Xchan_chanx[1][0]_out[41]_loadlvl[0]_out chanx[1][0]_out[41] chanx[1][0]_out[41]_loadlvl[0]_out chanx[1][0]_out[41]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[208]_no0 chanx[1][0]_out[41]_loadlvl[0]_out chanx[1][0]_out[41]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 chanx[1][0]_out[41]_loadlvl[0]_midout chanx[1][0]_out[41]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 chanx[1][0]_out[41]_loadlvl[0]_midout chanx[1][0]_out[41]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 chanx[1][0]_out[41]_loadlvl[0]_midout chanx[1][0]_out[41]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[42] density = 0, probability=0.***** -Vchanx[1][0]_in[42] chanx[1][0]_in[42] 0 -+ 0 -**** Load for rr_node[234] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=43, type=4 ***** -Xchan_chanx[1][0]_out[43]_loadlvl[0]_out chanx[1][0]_out[43] chanx[1][0]_out[43]_loadlvl[0]_out chanx[1][0]_out[43]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[212]_no0 chanx[1][0]_out[43]_loadlvl[0]_out chanx[1][0]_out[43]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 chanx[1][0]_out[43]_loadlvl[0]_midout chanx[1][0]_out[43]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 chanx[1][0]_out[43]_loadlvl[0]_midout chanx[1][0]_out[43]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 chanx[1][0]_out[43]_loadlvl[0]_midout chanx[1][0]_out[43]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[44] density = 0, probability=0.***** -Vchanx[1][0]_in[44] chanx[1][0]_in[44] 0 -+ 0 -**** Load for rr_node[236] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=45, type=4 ***** -Xchan_chanx[1][0]_out[45]_loadlvl[0]_out chanx[1][0]_out[45] chanx[1][0]_out[45]_loadlvl[0]_out chanx[1][0]_out[45]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[216]_no0 chanx[1][0]_out[45]_loadlvl[0]_out chanx[1][0]_out[45]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 chanx[1][0]_out[45]_loadlvl[0]_midout chanx[1][0]_out[45]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 chanx[1][0]_out[45]_loadlvl[0]_midout chanx[1][0]_out[45]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 chanx[1][0]_out[45]_loadlvl[0]_midout chanx[1][0]_out[45]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[46] density = 0, probability=0.***** -Vchanx[1][0]_in[46] chanx[1][0]_in[46] 0 -+ 0 -**** Load for rr_node[238] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=47, type=4 ***** -Xchan_chanx[1][0]_out[47]_loadlvl[0]_out chanx[1][0]_out[47] chanx[1][0]_out[47]_loadlvl[0]_out chanx[1][0]_out[47]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[220]_no0 chanx[1][0]_out[47]_loadlvl[0]_out chanx[1][0]_out[47]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[221]_no0 chanx[1][0]_out[47]_loadlvl[0]_midout chanx[1][0]_out[47]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 chanx[1][0]_out[47]_loadlvl[0]_midout chanx[1][0]_out[47]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[48] density = 0, probability=0.***** -Vchanx[1][0]_in[48] chanx[1][0]_in[48] 0 -+ 0 -**** Load for rr_node[240] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=49, type=4 ***** -Xchan_chanx[1][0]_out[49]_loadlvl[0]_out chanx[1][0]_out[49] chanx[1][0]_out[49]_loadlvl[0]_out chanx[1][0]_out[49]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[223]_no0 chanx[1][0]_out[49]_loadlvl[0]_out chanx[1][0]_out[49]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[224]_no0 chanx[1][0]_out[49]_loadlvl[0]_midout chanx[1][0]_out[49]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 chanx[1][0]_out[49]_loadlvl[0]_midout chanx[1][0]_out[49]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 chanx[1][0]_out[49]_loadlvl[0]_midout chanx[1][0]_out[49]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[50] density = 0, probability=0.***** -Vchanx[1][0]_in[50] chanx[1][0]_in[50] 0 -+ 0 -**** Load for rr_node[242] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=51, type=4 ***** -Xchan_chanx[1][0]_out[51]_loadlvl[0]_out chanx[1][0]_out[51] chanx[1][0]_out[51]_loadlvl[0]_out chanx[1][0]_out[51]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[227]_no0 chanx[1][0]_out[51]_loadlvl[0]_out chanx[1][0]_out[51]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[228]_no0 chanx[1][0]_out[51]_loadlvl[0]_midout chanx[1][0]_out[51]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 chanx[1][0]_out[51]_loadlvl[0]_midout chanx[1][0]_out[51]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 chanx[1][0]_out[51]_loadlvl[0]_midout chanx[1][0]_out[51]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[231]_no0 chanx[1][0]_out[51]_loadlvl[0]_midout chanx[1][0]_out[51]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[52] density = 0, probability=0.***** -Vchanx[1][0]_in[52] chanx[1][0]_in[52] 0 -+ 0 -**** Load for rr_node[244] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=53, type=4 ***** -Xchan_chanx[1][0]_out[53]_loadlvl[0]_out chanx[1][0]_out[53] chanx[1][0]_out[53]_loadlvl[0]_out chanx[1][0]_out[53]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[232]_no0 chanx[1][0]_out[53]_loadlvl[0]_out chanx[1][0]_out[53]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 chanx[1][0]_out[53]_loadlvl[0]_midout chanx[1][0]_out[53]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[234]_no0 chanx[1][0]_out[53]_loadlvl[0]_midout chanx[1][0]_out[53]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[54] density = 0, probability=0.***** -Vchanx[1][0]_in[54] chanx[1][0]_in[54] 0 -+ 0 -**** Load for rr_node[246] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=55, type=4 ***** -Xchan_chanx[1][0]_out[55]_loadlvl[0]_out chanx[1][0]_out[55] chanx[1][0]_out[55]_loadlvl[0]_out chanx[1][0]_out[55]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[235]_no0 chanx[1][0]_out[55]_loadlvl[0]_out chanx[1][0]_out[55]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 chanx[1][0]_out[55]_loadlvl[0]_midout chanx[1][0]_out[55]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 chanx[1][0]_out[55]_loadlvl[0]_midout chanx[1][0]_out[55]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 chanx[1][0]_out[55]_loadlvl[0]_midout chanx[1][0]_out[55]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[56] density = 0, probability=0.***** -Vchanx[1][0]_in[56] chanx[1][0]_in[56] 0 -+ 0 -**** Load for rr_node[248] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=57, type=4 ***** -Xchan_chanx[1][0]_out[57]_loadlvl[0]_out chanx[1][0]_out[57] chanx[1][0]_out[57]_loadlvl[0]_out chanx[1][0]_out[57]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[239]_no0 chanx[1][0]_out[57]_loadlvl[0]_out chanx[1][0]_out[57]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[240]_no0 chanx[1][0]_out[57]_loadlvl[0]_midout chanx[1][0]_out[57]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 chanx[1][0]_out[57]_loadlvl[0]_midout chanx[1][0]_out[57]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[242]_no0 chanx[1][0]_out[57]_loadlvl[0]_midout chanx[1][0]_out[57]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[58] density = 0, probability=0.***** -Vchanx[1][0]_in[58] chanx[1][0]_in[58] 0 -+ 0 -**** Load for rr_node[250] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=59, type=4 ***** -Xchan_chanx[1][0]_out[59]_loadlvl[0]_out chanx[1][0]_out[59] chanx[1][0]_out[59]_loadlvl[0]_out chanx[1][0]_out[59]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[243]_no0 chanx[1][0]_out[59]_loadlvl[0]_out chanx[1][0]_out[59]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 chanx[1][0]_out[59]_loadlvl[0]_midout chanx[1][0]_out[59]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 chanx[1][0]_out[59]_loadlvl[0]_midout chanx[1][0]_out[59]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[246]_no0 chanx[1][0]_out[59]_loadlvl[0]_midout chanx[1][0]_out[59]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[60] density = 0, probability=0.***** -Vchanx[1][0]_in[60] chanx[1][0]_in[60] 0 -+ 0 -**** Load for rr_node[252] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=61, type=4 ***** -Xchan_chanx[1][0]_out[61]_loadlvl[0]_out chanx[1][0]_out[61] chanx[1][0]_out[61]_loadlvl[0]_out chanx[1][0]_out[61]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[247]_no0 chanx[1][0]_out[61]_loadlvl[0]_out chanx[1][0]_out[61]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 chanx[1][0]_out[61]_loadlvl[0]_midout chanx[1][0]_out[61]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 chanx[1][0]_out[61]_loadlvl[0]_midout chanx[1][0]_out[61]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[250]_no0 chanx[1][0]_out[61]_loadlvl[0]_midout chanx[1][0]_out[61]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[62] density = 0, probability=0.***** -Vchanx[1][0]_in[62] chanx[1][0]_in[62] 0 -+ 0 -**** Load for rr_node[254] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=63, type=4 ***** -Xchan_chanx[1][0]_out[63]_loadlvl[0]_out chanx[1][0]_out[63] chanx[1][0]_out[63]_loadlvl[0]_out chanx[1][0]_out[63]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[251]_no0 chanx[1][0]_out[63]_loadlvl[0]_out chanx[1][0]_out[63]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 chanx[1][0]_out[63]_loadlvl[0]_midout chanx[1][0]_out[63]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 chanx[1][0]_out[63]_loadlvl[0]_midout chanx[1][0]_out[63]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[64] density = 0, probability=0.***** -Vchanx[1][0]_in[64] chanx[1][0]_in[64] 0 -+ 0 -**** Load for rr_node[256] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=65, type=4 ***** -Xchan_chanx[1][0]_out[65]_loadlvl[0]_out chanx[1][0]_out[65] chanx[1][0]_out[65]_loadlvl[0]_out chanx[1][0]_out[65]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[254]_no0 chanx[1][0]_out[65]_loadlvl[0]_out chanx[1][0]_out[65]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[255]_no0 chanx[1][0]_out[65]_loadlvl[0]_midout chanx[1][0]_out[65]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 chanx[1][0]_out[65]_loadlvl[0]_midout chanx[1][0]_out[65]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 chanx[1][0]_out[65]_loadlvl[0]_midout chanx[1][0]_out[65]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 chanx[1][0]_out[65]_loadlvl[0]_midout chanx[1][0]_out[65]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[66] density = 0, probability=0.***** -Vchanx[1][0]_in[66] chanx[1][0]_in[66] 0 -+ 0 -**** Load for rr_node[258] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=67, type=4 ***** -Xchan_chanx[1][0]_out[67]_loadlvl[0]_out chanx[1][0]_out[67] chanx[1][0]_out[67]_loadlvl[0]_out chanx[1][0]_out[67]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[259]_no0 chanx[1][0]_out[67]_loadlvl[0]_out chanx[1][0]_out[67]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[260]_no0 chanx[1][0]_out[67]_loadlvl[0]_midout chanx[1][0]_out[67]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 chanx[1][0]_out[67]_loadlvl[0]_midout chanx[1][0]_out[67]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[68] density = 0, probability=0.***** -Vchanx[1][0]_in[68] chanx[1][0]_in[68] 0 -+ 0 -**** Load for rr_node[260] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=69, type=4 ***** -Xchan_chanx[1][0]_out[69]_loadlvl[0]_out chanx[1][0]_out[69] chanx[1][0]_out[69]_loadlvl[0]_out chanx[1][0]_out[69]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[262]_no0 chanx[1][0]_out[69]_loadlvl[0]_out chanx[1][0]_out[69]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[263]_no0 chanx[1][0]_out[69]_loadlvl[0]_midout chanx[1][0]_out[69]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 chanx[1][0]_out[69]_loadlvl[0]_midout chanx[1][0]_out[69]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 chanx[1][0]_out[69]_loadlvl[0]_midout chanx[1][0]_out[69]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[70] density = 0, probability=0.***** -Vchanx[1][0]_in[70] chanx[1][0]_in[70] 0 -+ 0 -**** Load for rr_node[262] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=71, type=4 ***** -Xchan_chanx[1][0]_out[71]_loadlvl[0]_out chanx[1][0]_out[71] chanx[1][0]_out[71]_loadlvl[0]_out chanx[1][0]_out[71]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[266]_no0 chanx[1][0]_out[71]_loadlvl[0]_out chanx[1][0]_out[71]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 chanx[1][0]_out[71]_loadlvl[0]_midout chanx[1][0]_out[71]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 chanx[1][0]_out[71]_loadlvl[0]_midout chanx[1][0]_out[71]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 chanx[1][0]_out[71]_loadlvl[0]_midout chanx[1][0]_out[71]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[270]_no0 chanx[1][0]_out[71]_loadlvl[0]_midout chanx[1][0]_out[71]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[72] density = 0, probability=0.***** -Vchanx[1][0]_in[72] chanx[1][0]_in[72] 0 -+ 0 -**** Load for rr_node[264] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=73, type=4 ***** -Xchan_chanx[1][0]_out[73]_loadlvl[0]_out chanx[1][0]_out[73] chanx[1][0]_out[73]_loadlvl[0]_out chanx[1][0]_out[73]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[271]_no0 chanx[1][0]_out[73]_loadlvl[0]_out chanx[1][0]_out[73]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 chanx[1][0]_out[73]_loadlvl[0]_midout chanx[1][0]_out[73]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 chanx[1][0]_out[73]_loadlvl[0]_midout chanx[1][0]_out[73]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[74] density = 0, probability=0.***** -Vchanx[1][0]_in[74] chanx[1][0]_in[74] 0 -+ 0 -**** Load for rr_node[266] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=75, type=4 ***** -Xchan_chanx[1][0]_out[75]_loadlvl[0]_out chanx[1][0]_out[75] chanx[1][0]_out[75]_loadlvl[0]_out chanx[1][0]_out[75]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[274]_no0 chanx[1][0]_out[75]_loadlvl[0]_out chanx[1][0]_out[75]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 chanx[1][0]_out[75]_loadlvl[0]_midout chanx[1][0]_out[75]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 chanx[1][0]_out[75]_loadlvl[0]_midout chanx[1][0]_out[75]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 chanx[1][0]_out[75]_loadlvl[0]_midout chanx[1][0]_out[75]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[76] density = 0, probability=0.***** -Vchanx[1][0]_in[76] chanx[1][0]_in[76] 0 -+ 0 -**** Load for rr_node[268] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=77, type=4 ***** -Xchan_chanx[1][0]_out[77]_loadlvl[0]_out chanx[1][0]_out[77] chanx[1][0]_out[77]_loadlvl[0]_out chanx[1][0]_out[77]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[278]_no0 chanx[1][0]_out[77]_loadlvl[0]_out chanx[1][0]_out[77]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 chanx[1][0]_out[77]_loadlvl[0]_midout chanx[1][0]_out[77]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 chanx[1][0]_out[77]_loadlvl[0]_midout chanx[1][0]_out[77]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[78] density = 0, probability=0.***** -Vchanx[1][0]_in[78] chanx[1][0]_in[78] 0 -+ 0 -**** Load for rr_node[270] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=79, type=4 ***** -Xchan_chanx[1][0]_out[79]_loadlvl[0]_out chanx[1][0]_out[79] chanx[1][0]_out[79]_loadlvl[0]_out chanx[1][0]_out[79]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[281]_no0 chanx[1][0]_out[79]_loadlvl[0]_out chanx[1][0]_out[79]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[282]_no0 chanx[1][0]_out[79]_loadlvl[0]_midout chanx[1][0]_out[79]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 chanx[1][0]_out[79]_loadlvl[0]_midout chanx[1][0]_out[79]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 chanx[1][0]_out[79]_loadlvl[0]_midout chanx[1][0]_out[79]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[285]_no0 chanx[1][0]_out[79]_loadlvl[0]_midout chanx[1][0]_out[79]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[80] density = 0, probability=0.***** -Vchanx[1][0]_in[80] chanx[1][0]_in[80] 0 -+ 0 -**** Load for rr_node[272] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=81, type=4 ***** -Xchan_chanx[1][0]_out[81]_loadlvl[0]_out chanx[1][0]_out[81] chanx[1][0]_out[81]_loadlvl[0]_out chanx[1][0]_out[81]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[286]_no0 chanx[1][0]_out[81]_loadlvl[0]_out chanx[1][0]_out[81]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 chanx[1][0]_out[81]_loadlvl[0]_midout chanx[1][0]_out[81]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 chanx[1][0]_out[81]_loadlvl[0]_midout chanx[1][0]_out[81]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[289]_no0 chanx[1][0]_out[81]_loadlvl[0]_midout chanx[1][0]_out[81]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[82] density = 0, probability=0.***** -Vchanx[1][0]_in[82] chanx[1][0]_in[82] 0 -+ 0 -**** Load for rr_node[274] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=83, type=4 ***** -Xchan_chanx[1][0]_out[83]_loadlvl[0]_out chanx[1][0]_out[83] chanx[1][0]_out[83]_loadlvl[0]_out chanx[1][0]_out[83]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[290]_no0 chanx[1][0]_out[83]_loadlvl[0]_out chanx[1][0]_out[83]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 chanx[1][0]_out[83]_loadlvl[0]_midout chanx[1][0]_out[83]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 chanx[1][0]_out[83]_loadlvl[0]_midout chanx[1][0]_out[83]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[84] density = 0, probability=0.***** -Vchanx[1][0]_in[84] chanx[1][0]_in[84] 0 -+ 0 -**** Load for rr_node[276] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=85, type=4 ***** -Xchan_chanx[1][0]_out[85]_loadlvl[0]_out chanx[1][0]_out[85] chanx[1][0]_out[85]_loadlvl[0]_out chanx[1][0]_out[85]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[293]_no0 chanx[1][0]_out[85]_loadlvl[0]_out chanx[1][0]_out[85]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[294]_no0 chanx[1][0]_out[85]_loadlvl[0]_midout chanx[1][0]_out[85]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 chanx[1][0]_out[85]_loadlvl[0]_midout chanx[1][0]_out[85]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 chanx[1][0]_out[85]_loadlvl[0]_midout chanx[1][0]_out[85]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[297]_no0 chanx[1][0]_out[85]_loadlvl[0]_midout chanx[1][0]_out[85]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[86] density = 0, probability=0.***** -Vchanx[1][0]_in[86] chanx[1][0]_in[86] 0 -+ 0 -**** Load for rr_node[278] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=87, type=4 ***** -Xchan_chanx[1][0]_out[87]_loadlvl[0]_out chanx[1][0]_out[87] chanx[1][0]_out[87]_loadlvl[0]_out chanx[1][0]_out[87]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[298]_no0 chanx[1][0]_out[87]_loadlvl[0]_out chanx[1][0]_out[87]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 chanx[1][0]_out[87]_loadlvl[0]_midout chanx[1][0]_out[87]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[300]_no0 chanx[1][0]_out[87]_loadlvl[0]_midout chanx[1][0]_out[87]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[88] density = 0, probability=0.***** -Vchanx[1][0]_in[88] chanx[1][0]_in[88] 0 -+ 0 -**** Load for rr_node[280] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=89, type=4 ***** -Xchan_chanx[1][0]_out[89]_loadlvl[0]_out chanx[1][0]_out[89] chanx[1][0]_out[89]_loadlvl[0]_out chanx[1][0]_out[89]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[301]_no0 chanx[1][0]_out[89]_loadlvl[0]_out chanx[1][0]_out[89]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 chanx[1][0]_out[89]_loadlvl[0]_midout chanx[1][0]_out[89]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 chanx[1][0]_out[89]_loadlvl[0]_midout chanx[1][0]_out[89]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 chanx[1][0]_out[89]_loadlvl[0]_midout chanx[1][0]_out[89]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[90] density = 0, probability=0.***** -Vchanx[1][0]_in[90] chanx[1][0]_in[90] 0 -+ 0 -**** Load for rr_node[282] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=91, type=4 ***** -Xchan_chanx[1][0]_out[91]_loadlvl[0]_out chanx[1][0]_out[91] chanx[1][0]_out[91]_loadlvl[0]_out chanx[1][0]_out[91]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[305]_no0 chanx[1][0]_out[91]_loadlvl[0]_out chanx[1][0]_out[91]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 chanx[1][0]_out[91]_loadlvl[0]_midout chanx[1][0]_out[91]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 chanx[1][0]_out[91]_loadlvl[0]_midout chanx[1][0]_out[91]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 chanx[1][0]_out[91]_loadlvl[0]_midout chanx[1][0]_out[91]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[92] density = 0, probability=0.***** -Vchanx[1][0]_in[92] chanx[1][0]_in[92] 0 -+ 0 -**** Load for rr_node[284] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=93, type=4 ***** -Xchan_chanx[1][0]_out[93]_loadlvl[0]_out chanx[1][0]_out[93] chanx[1][0]_out[93]_loadlvl[0]_out chanx[1][0]_out[93]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[309]_no0 chanx[1][0]_out[93]_loadlvl[0]_out chanx[1][0]_out[93]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 chanx[1][0]_out[93]_loadlvl[0]_midout chanx[1][0]_out[93]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 chanx[1][0]_out[93]_loadlvl[0]_midout chanx[1][0]_out[93]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 chanx[1][0]_out[93]_loadlvl[0]_midout chanx[1][0]_out[93]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[94] density = 0, probability=0.***** -Vchanx[1][0]_in[94] chanx[1][0]_in[94] 0 -+ 0 -**** Load for rr_node[286] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=95, type=4 ***** -Xchan_chanx[1][0]_out[95]_loadlvl[0]_out chanx[1][0]_out[95] chanx[1][0]_out[95]_loadlvl[0]_out chanx[1][0]_out[95]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[313]_no0 chanx[1][0]_out[95]_loadlvl[0]_out chanx[1][0]_out[95]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 chanx[1][0]_out[95]_loadlvl[0]_midout chanx[1][0]_out[95]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 chanx[1][0]_out[95]_loadlvl[0]_midout chanx[1][0]_out[95]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[316]_no0 chanx[1][0]_out[95]_loadlvl[0]_midout chanx[1][0]_out[95]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[96] density = 0, probability=0.***** -Vchanx[1][0]_in[96] chanx[1][0]_in[96] 0 -+ 0 -**** Load for rr_node[288] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=97, type=4 ***** -Xchan_chanx[1][0]_out[97]_loadlvl[0]_out chanx[1][0]_out[97] chanx[1][0]_out[97]_loadlvl[0]_out chanx[1][0]_out[97]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[317]_no0 chanx[1][0]_out[97]_loadlvl[0]_out chanx[1][0]_out[97]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 chanx[1][0]_out[97]_loadlvl[0]_midout chanx[1][0]_out[97]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 chanx[1][0]_out[97]_loadlvl[0]_midout chanx[1][0]_out[97]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][0]_in[98] density = 0, probability=0.***** -Vchanx[1][0]_in[98] chanx[1][0]_in[98] 0 -+ 0 -**** Load for rr_node[290] ***** -**** Loads for rr_node: xlow=1, ylow=0, xhigh=1, yhigh=0, ptc_num=99, type=4 ***** -Xchan_chanx[1][0]_out[99]_loadlvl[0]_out chanx[1][0]_out[99] chanx[1][0]_out[99]_loadlvl[0]_out chanx[1][0]_out[99]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[320]_no0 chanx[1][0]_out[99]_loadlvl[0]_out chanx[1][0]_out[99]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[321]_no0 chanx[1][0]_out[99]_loadlvl[0]_midout chanx[1][0]_out[99]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 chanx[1][0]_out[99]_loadlvl[0]_midout chanx[1][0]_out[99]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 chanx[1][0]_out[99]_loadlvl[0]_midout chanx[1][0]_out[99]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Vgrid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][42] 0 -+ 0 -Vgrid[1][1]_pin[0][2][46] grid[1][1]_pin[0][2][46] 0 -+ 0 -Vgrid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][1] 0 -+ 0 -Vgrid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][3] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgrid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][5] 0 -+ 0 -Vgrid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][7] 0 -+ 0 -Vgrid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][9] 0 -+ 0 -Vgrid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][11] 0 -+ 0 -Vgrid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][13] 0 -+ 0 -Vgrid[1][0]_pin[0][0][15] grid[1][0]_pin[0][0][15] 0 -+ 0 - -***** Voltage supplies ***** -Vgvdd_sb[1][0] gvdd_sb[1][0] 0 vsp -Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_sb avg p(Vgvdd_sb[1][0]) from=0 to='clock_period' -.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_sb avg p(Vgvdd_sb[1][0]) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period' -.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_2/sb_tb/example_2_sb1_1_sb_testbench.sp b/examples/spice_test_example_2/sb_tb/example_2_sb1_1_sb_testbench.sp deleted file mode 100644 index f9f0eaad7..000000000 --- a/examples/spice_test_example_2/sb_tb/example_2_sb1_1_sb_testbench.sp +++ /dev/null @@ -1,1101 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Switch Block Testbench Bench for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -.temp 25 -.option fast -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_sram_sbs -****** Include subckt netlists: Switch Block[1][1] ***** -.include './spice_test_example_2/subckt/sb_1_1.sp' -***** Call defined Switch Box[1][1] ***** -Xsb[1][1] -+ -+ -+ -+ -+ chany[1][1]_in[0] chany[1][1]_out[1] chany[1][1]_in[2] chany[1][1]_out[3] chany[1][1]_in[4] chany[1][1]_out[5] chany[1][1]_in[6] chany[1][1]_out[7] chany[1][1]_in[8] chany[1][1]_out[9] chany[1][1]_in[10] chany[1][1]_out[11] chany[1][1]_in[12] chany[1][1]_out[13] chany[1][1]_in[14] chany[1][1]_out[15] chany[1][1]_in[16] chany[1][1]_out[17] chany[1][1]_in[18] chany[1][1]_out[19] chany[1][1]_in[20] chany[1][1]_out[21] chany[1][1]_in[22] chany[1][1]_out[23] chany[1][1]_in[24] chany[1][1]_out[25] chany[1][1]_in[26] chany[1][1]_out[27] chany[1][1]_in[28] chany[1][1]_out[29] chany[1][1]_in[30] chany[1][1]_out[31] chany[1][1]_in[32] chany[1][1]_out[33] chany[1][1]_in[34] chany[1][1]_out[35] chany[1][1]_in[36] chany[1][1]_out[37] chany[1][1]_in[38] chany[1][1]_out[39] chany[1][1]_in[40] chany[1][1]_out[41] chany[1][1]_in[42] chany[1][1]_out[43] chany[1][1]_in[44] chany[1][1]_out[45] chany[1][1]_in[46] chany[1][1]_out[47] chany[1][1]_in[48] chany[1][1]_out[49] chany[1][1]_in[50] chany[1][1]_out[51] chany[1][1]_in[52] chany[1][1]_out[53] chany[1][1]_in[54] chany[1][1]_out[55] chany[1][1]_in[56] chany[1][1]_out[57] chany[1][1]_in[58] chany[1][1]_out[59] chany[1][1]_in[60] chany[1][1]_out[61] chany[1][1]_in[62] chany[1][1]_out[63] chany[1][1]_in[64] chany[1][1]_out[65] chany[1][1]_in[66] chany[1][1]_out[67] chany[1][1]_in[68] chany[1][1]_out[69] chany[1][1]_in[70] chany[1][1]_out[71] chany[1][1]_in[72] chany[1][1]_out[73] chany[1][1]_in[74] chany[1][1]_out[75] chany[1][1]_in[76] chany[1][1]_out[77] chany[1][1]_in[78] chany[1][1]_out[79] chany[1][1]_in[80] chany[1][1]_out[81] chany[1][1]_in[82] chany[1][1]_out[83] chany[1][1]_in[84] chany[1][1]_out[85] chany[1][1]_in[86] chany[1][1]_out[87] chany[1][1]_in[88] chany[1][1]_out[89] chany[1][1]_in[90] chany[1][1]_out[91] chany[1][1]_in[92] chany[1][1]_out[93] chany[1][1]_in[94] chany[1][1]_out[95] chany[1][1]_in[96] chany[1][1]_out[97] chany[1][1]_in[98] chany[1][1]_out[99] -+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][49] -+ chanx[1][1]_in[0] chanx[1][1]_out[1] chanx[1][1]_in[2] chanx[1][1]_out[3] chanx[1][1]_in[4] chanx[1][1]_out[5] chanx[1][1]_in[6] chanx[1][1]_out[7] chanx[1][1]_in[8] chanx[1][1]_out[9] chanx[1][1]_in[10] chanx[1][1]_out[11] chanx[1][1]_in[12] chanx[1][1]_out[13] chanx[1][1]_in[14] chanx[1][1]_out[15] chanx[1][1]_in[16] chanx[1][1]_out[17] chanx[1][1]_in[18] chanx[1][1]_out[19] chanx[1][1]_in[20] chanx[1][1]_out[21] chanx[1][1]_in[22] chanx[1][1]_out[23] chanx[1][1]_in[24] chanx[1][1]_out[25] chanx[1][1]_in[26] chanx[1][1]_out[27] chanx[1][1]_in[28] chanx[1][1]_out[29] chanx[1][1]_in[30] chanx[1][1]_out[31] chanx[1][1]_in[32] chanx[1][1]_out[33] chanx[1][1]_in[34] chanx[1][1]_out[35] chanx[1][1]_in[36] chanx[1][1]_out[37] chanx[1][1]_in[38] chanx[1][1]_out[39] chanx[1][1]_in[40] chanx[1][1]_out[41] chanx[1][1]_in[42] chanx[1][1]_out[43] chanx[1][1]_in[44] chanx[1][1]_out[45] chanx[1][1]_in[46] chanx[1][1]_out[47] chanx[1][1]_in[48] chanx[1][1]_out[49] chanx[1][1]_in[50] chanx[1][1]_out[51] chanx[1][1]_in[52] chanx[1][1]_out[53] chanx[1][1]_in[54] chanx[1][1]_out[55] chanx[1][1]_in[56] chanx[1][1]_out[57] chanx[1][1]_in[58] chanx[1][1]_out[59] chanx[1][1]_in[60] chanx[1][1]_out[61] chanx[1][1]_in[62] chanx[1][1]_out[63] chanx[1][1]_in[64] chanx[1][1]_out[65] chanx[1][1]_in[66] chanx[1][1]_out[67] chanx[1][1]_in[68] chanx[1][1]_out[69] chanx[1][1]_in[70] chanx[1][1]_out[71] chanx[1][1]_in[72] chanx[1][1]_out[73] chanx[1][1]_in[74] chanx[1][1]_out[75] chanx[1][1]_in[76] chanx[1][1]_out[77] chanx[1][1]_in[78] chanx[1][1]_out[79] chanx[1][1]_in[80] chanx[1][1]_out[81] chanx[1][1]_in[82] chanx[1][1]_out[83] chanx[1][1]_in[84] chanx[1][1]_out[85] chanx[1][1]_in[86] chanx[1][1]_out[87] chanx[1][1]_in[88] chanx[1][1]_out[89] chanx[1][1]_in[90] chanx[1][1]_out[91] chanx[1][1]_in[92] chanx[1][1]_out[93] chanx[1][1]_in[94] chanx[1][1]_out[95] chanx[1][1]_in[96] chanx[1][1]_out[97] chanx[1][1]_in[98] chanx[1][1]_out[99] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][48] -+ gvdd_sb[1][1] 0 sb[1][1] - - -***** Signal chany[1][1]_in[0] density = 0, probability=0.***** -Vchany[1][1]_in[0] chany[1][1]_in[0] 0 -+ 0 -**** Load for rr_node[492] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=1, type=5 ***** -Xchan_chany[1][1]_out[1]_loadlvl[0]_out chany[1][1]_out[1] chany[1][1]_out[1]_loadlvl[0]_out chany[1][1]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[0]_no0 chany[1][1]_out[1]_loadlvl[0]_out chany[1][1]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[1]_no0 chany[1][1]_out[1]_loadlvl[0]_midout chany[1][1]_out[1]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[2] density = 0, probability=0.***** -Vchany[1][1]_in[2] chany[1][1]_in[2] 0 -+ 0 -**** Load for rr_node[494] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=3, type=5 ***** -Xchan_chany[1][1]_out[3]_loadlvl[0]_out chany[1][1]_out[3] chany[1][1]_out[3]_loadlvl[0]_out chany[1][1]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[2]_no0 chany[1][1]_out[3]_loadlvl[0]_out chany[1][1]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[3]_no0 chany[1][1]_out[3]_loadlvl[0]_midout chany[1][1]_out[3]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[4]_no0 chany[1][1]_out[3]_loadlvl[0]_midout chany[1][1]_out[3]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[4] density = 0, probability=0.***** -Vchany[1][1]_in[4] chany[1][1]_in[4] 0 -+ 0 -**** Load for rr_node[496] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=5, type=5 ***** -Xchan_chany[1][1]_out[5]_loadlvl[0]_out chany[1][1]_out[5] chany[1][1]_out[5]_loadlvl[0]_out chany[1][1]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[5]_no0 chany[1][1]_out[5]_loadlvl[0]_out chany[1][1]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[6]_no0 chany[1][1]_out[5]_loadlvl[0]_midout chany[1][1]_out[5]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[7]_no0 chany[1][1]_out[5]_loadlvl[0]_midout chany[1][1]_out[5]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[6] density = 0, probability=0.***** -Vchany[1][1]_in[6] chany[1][1]_in[6] 0 -+ 0 -**** Load for rr_node[498] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=7, type=5 ***** -Xchan_chany[1][1]_out[7]_loadlvl[0]_out chany[1][1]_out[7] chany[1][1]_out[7]_loadlvl[0]_out chany[1][1]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[8]_no0 chany[1][1]_out[7]_loadlvl[0]_out chany[1][1]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[9]_no0 chany[1][1]_out[7]_loadlvl[0]_midout chany[1][1]_out[7]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[10]_no0 chany[1][1]_out[7]_loadlvl[0]_midout chany[1][1]_out[7]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[8] density = 0, probability=0.***** -Vchany[1][1]_in[8] chany[1][1]_in[8] 0 -+ 0 -**** Load for rr_node[500] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=9, type=5 ***** -Xchan_chany[1][1]_out[9]_loadlvl[0]_out chany[1][1]_out[9] chany[1][1]_out[9]_loadlvl[0]_out chany[1][1]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[11]_no0 chany[1][1]_out[9]_loadlvl[0]_out chany[1][1]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[12]_no0 chany[1][1]_out[9]_loadlvl[0]_midout chany[1][1]_out[9]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[13]_no0 chany[1][1]_out[9]_loadlvl[0]_midout chany[1][1]_out[9]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[10] density = 0, probability=0.***** -Vchany[1][1]_in[10] chany[1][1]_in[10] 0 -+ 0 -**** Load for rr_node[502] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=11, type=5 ***** -Xchan_chany[1][1]_out[11]_loadlvl[0]_out chany[1][1]_out[11] chany[1][1]_out[11]_loadlvl[0]_out chany[1][1]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[14]_no0 chany[1][1]_out[11]_loadlvl[0]_out chany[1][1]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[15]_no0 chany[1][1]_out[11]_loadlvl[0]_midout chany[1][1]_out[11]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[12] density = 0, probability=0.***** -Vchany[1][1]_in[12] chany[1][1]_in[12] 0 -+ 0 -**** Load for rr_node[504] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=13, type=5 ***** -Xchan_chany[1][1]_out[13]_loadlvl[0]_out chany[1][1]_out[13] chany[1][1]_out[13]_loadlvl[0]_out chany[1][1]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[16]_no0 chany[1][1]_out[13]_loadlvl[0]_out chany[1][1]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[17]_no0 chany[1][1]_out[13]_loadlvl[0]_midout chany[1][1]_out[13]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[18]_no0 chany[1][1]_out[13]_loadlvl[0]_midout chany[1][1]_out[13]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[14] density = 0, probability=0.***** -Vchany[1][1]_in[14] chany[1][1]_in[14] 0 -+ 0 -**** Load for rr_node[506] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=15, type=5 ***** -Xchan_chany[1][1]_out[15]_loadlvl[0]_out chany[1][1]_out[15] chany[1][1]_out[15]_loadlvl[0]_out chany[1][1]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[19]_no0 chany[1][1]_out[15]_loadlvl[0]_out chany[1][1]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[20]_no0 chany[1][1]_out[15]_loadlvl[0]_midout chany[1][1]_out[15]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[16] density = 0, probability=0.***** -Vchany[1][1]_in[16] chany[1][1]_in[16] 0 -+ 0 -**** Load for rr_node[508] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=17, type=5 ***** -Xchan_chany[1][1]_out[17]_loadlvl[0]_out chany[1][1]_out[17] chany[1][1]_out[17]_loadlvl[0]_out chany[1][1]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[21]_no0 chany[1][1]_out[17]_loadlvl[0]_out chany[1][1]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[22]_no0 chany[1][1]_out[17]_loadlvl[0]_midout chany[1][1]_out[17]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[18] density = 0, probability=0.***** -Vchany[1][1]_in[18] chany[1][1]_in[18] 0 -+ 0 -**** Load for rr_node[510] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=19, type=5 ***** -Xchan_chany[1][1]_out[19]_loadlvl[0]_out chany[1][1]_out[19] chany[1][1]_out[19]_loadlvl[0]_out chany[1][1]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[23]_no0 chany[1][1]_out[19]_loadlvl[0]_out chany[1][1]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[24]_no0 chany[1][1]_out[19]_loadlvl[0]_midout chany[1][1]_out[19]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[25]_no0 chany[1][1]_out[19]_loadlvl[0]_midout chany[1][1]_out[19]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[20] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_in[20] chany[1][1]_in[20] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[512] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=21, type=5 ***** -Xchan_chany[1][1]_out[21]_loadlvl[0]_out chany[1][1]_out[21] chany[1][1]_out[21]_loadlvl[0]_out chany[1][1]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[26]_no0 chany[1][1]_out[21]_loadlvl[0]_out chany[1][1]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[27]_no0 chany[1][1]_out[21]_loadlvl[0]_midout chany[1][1]_out[21]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[22] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_in[22] chany[1][1]_in[22] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[514] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=23, type=5 ***** -Xchan_chany[1][1]_out[23]_loadlvl[0]_out chany[1][1]_out[23] chany[1][1]_out[23]_loadlvl[0]_out chany[1][1]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[28]_no0 chany[1][1]_out[23]_loadlvl[0]_out chany[1][1]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[29]_no0 chany[1][1]_out[23]_loadlvl[0]_midout chany[1][1]_out[23]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[30]_no0 chany[1][1]_out[23]_loadlvl[0]_midout chany[1][1]_out[23]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[24] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_in[24] chany[1][1]_in[24] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[516] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=25, type=5 ***** -Xchan_chany[1][1]_out[25]_loadlvl[0]_out chany[1][1]_out[25] chany[1][1]_out[25]_loadlvl[0]_out chany[1][1]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[31]_no0 chany[1][1]_out[25]_loadlvl[0]_out chany[1][1]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[32]_no0 chany[1][1]_out[25]_loadlvl[0]_midout chany[1][1]_out[25]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[33]_no0 chany[1][1]_out[25]_loadlvl[0]_midout chany[1][1]_out[25]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[26] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_in[26] chany[1][1]_in[26] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[518] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=27, type=5 ***** -Xchan_chany[1][1]_out[27]_loadlvl[0]_out chany[1][1]_out[27] chany[1][1]_out[27]_loadlvl[0]_out chany[1][1]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[34]_no0 chany[1][1]_out[27]_loadlvl[0]_out chany[1][1]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[35]_no0 chany[1][1]_out[27]_loadlvl[0]_midout chany[1][1]_out[27]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[28] density = 0.2026, probability=0.4982.***** -Vchany[1][1]_in[28] chany[1][1]_in[28] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[520] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=29, type=5 ***** -Xchan_chany[1][1]_out[29]_loadlvl[0]_out chany[1][1]_out[29] chany[1][1]_out[29]_loadlvl[0]_out chany[1][1]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[36]_no0 chany[1][1]_out[29]_loadlvl[0]_out chany[1][1]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[37]_no0 chany[1][1]_out[29]_loadlvl[0]_midout chany[1][1]_out[29]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[38]_no0 chany[1][1]_out[29]_loadlvl[0]_midout chany[1][1]_out[29]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[30] density = 0, probability=0.***** -Vchany[1][1]_in[30] chany[1][1]_in[30] 0 -+ 0 -**** Load for rr_node[522] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=31, type=5 ***** -Xchan_chany[1][1]_out[31]_loadlvl[0]_out chany[1][1]_out[31] chany[1][1]_out[31]_loadlvl[0]_out chany[1][1]_out[31]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[39]_no0 chany[1][1]_out[31]_loadlvl[0]_out chany[1][1]_out[31]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[40]_no0 chany[1][1]_out[31]_loadlvl[0]_midout chany[1][1]_out[31]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[41]_no0 chany[1][1]_out[31]_loadlvl[0]_midout chany[1][1]_out[31]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[32] density = 0, probability=0.***** -Vchany[1][1]_in[32] chany[1][1]_in[32] 0 -+ 0 -**** Load for rr_node[524] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=33, type=5 ***** -Xchan_chany[1][1]_out[33]_loadlvl[0]_out chany[1][1]_out[33] chany[1][1]_out[33]_loadlvl[0]_out chany[1][1]_out[33]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[42]_no0 chany[1][1]_out[33]_loadlvl[0]_out chany[1][1]_out[33]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[43]_no0 chany[1][1]_out[33]_loadlvl[0]_midout chany[1][1]_out[33]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[44]_no0 chany[1][1]_out[33]_loadlvl[0]_midout chany[1][1]_out[33]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[34] density = 0, probability=0.***** -Vchany[1][1]_in[34] chany[1][1]_in[34] 0 -+ 0 -**** Load for rr_node[526] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=35, type=5 ***** -Xchan_chany[1][1]_out[35]_loadlvl[0]_out chany[1][1]_out[35] chany[1][1]_out[35]_loadlvl[0]_out chany[1][1]_out[35]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[45]_no0 chany[1][1]_out[35]_loadlvl[0]_out chany[1][1]_out[35]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[46]_no0 chany[1][1]_out[35]_loadlvl[0]_midout chany[1][1]_out[35]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[47]_no0 chany[1][1]_out[35]_loadlvl[0]_midout chany[1][1]_out[35]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[36] density = 0, probability=0.***** -Vchany[1][1]_in[36] chany[1][1]_in[36] 0 -+ 0 -**** Load for rr_node[528] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=37, type=5 ***** -Xchan_chany[1][1]_out[37]_loadlvl[0]_out chany[1][1]_out[37] chany[1][1]_out[37]_loadlvl[0]_out chany[1][1]_out[37]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[48]_no0 chany[1][1]_out[37]_loadlvl[0]_out chany[1][1]_out[37]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[49]_no0 chany[1][1]_out[37]_loadlvl[0]_midout chany[1][1]_out[37]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[38] density = 0, probability=0.***** -Vchany[1][1]_in[38] chany[1][1]_in[38] 0 -+ 0 -**** Load for rr_node[530] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=39, type=5 ***** -Xchan_chany[1][1]_out[39]_loadlvl[0]_out chany[1][1]_out[39] chany[1][1]_out[39]_loadlvl[0]_out chany[1][1]_out[39]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[50]_no0 chany[1][1]_out[39]_loadlvl[0]_out chany[1][1]_out[39]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[51]_no0 chany[1][1]_out[39]_loadlvl[0]_midout chany[1][1]_out[39]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[40] density = 0, probability=0.***** -Vchany[1][1]_in[40] chany[1][1]_in[40] 0 -+ 0 -**** Load for rr_node[532] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=41, type=5 ***** -Xchan_chany[1][1]_out[41]_loadlvl[0]_out chany[1][1]_out[41] chany[1][1]_out[41]_loadlvl[0]_out chany[1][1]_out[41]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[52]_no0 chany[1][1]_out[41]_loadlvl[0]_out chany[1][1]_out[41]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[53]_no0 chany[1][1]_out[41]_loadlvl[0]_midout chany[1][1]_out[41]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[42] density = 0, probability=0.***** -Vchany[1][1]_in[42] chany[1][1]_in[42] 0 -+ 0 -**** Load for rr_node[534] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=43, type=5 ***** -Xchan_chany[1][1]_out[43]_loadlvl[0]_out chany[1][1]_out[43] chany[1][1]_out[43]_loadlvl[0]_out chany[1][1]_out[43]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[54]_no0 chany[1][1]_out[43]_loadlvl[0]_out chany[1][1]_out[43]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[55]_no0 chany[1][1]_out[43]_loadlvl[0]_midout chany[1][1]_out[43]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[56]_no0 chany[1][1]_out[43]_loadlvl[0]_midout chany[1][1]_out[43]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[44] density = 0, probability=0.***** -Vchany[1][1]_in[44] chany[1][1]_in[44] 0 -+ 0 -**** Load for rr_node[536] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=45, type=5 ***** -Xchan_chany[1][1]_out[45]_loadlvl[0]_out chany[1][1]_out[45] chany[1][1]_out[45]_loadlvl[0]_out chany[1][1]_out[45]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[57]_no0 chany[1][1]_out[45]_loadlvl[0]_out chany[1][1]_out[45]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[58]_no0 chany[1][1]_out[45]_loadlvl[0]_midout chany[1][1]_out[45]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[59]_no0 chany[1][1]_out[45]_loadlvl[0]_midout chany[1][1]_out[45]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[46] density = 0, probability=0.***** -Vchany[1][1]_in[46] chany[1][1]_in[46] 0 -+ 0 -**** Load for rr_node[538] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=47, type=5 ***** -Xchan_chany[1][1]_out[47]_loadlvl[0]_out chany[1][1]_out[47] chany[1][1]_out[47]_loadlvl[0]_out chany[1][1]_out[47]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[60]_no0 chany[1][1]_out[47]_loadlvl[0]_out chany[1][1]_out[47]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[61]_no0 chany[1][1]_out[47]_loadlvl[0]_midout chany[1][1]_out[47]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[62]_no0 chany[1][1]_out[47]_loadlvl[0]_midout chany[1][1]_out[47]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[48] density = 0, probability=0.***** -Vchany[1][1]_in[48] chany[1][1]_in[48] 0 -+ 0 -**** Load for rr_node[540] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=49, type=5 ***** -Xchan_chany[1][1]_out[49]_loadlvl[0]_out chany[1][1]_out[49] chany[1][1]_out[49]_loadlvl[0]_out chany[1][1]_out[49]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[63]_no0 chany[1][1]_out[49]_loadlvl[0]_out chany[1][1]_out[49]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[64]_no0 chany[1][1]_out[49]_loadlvl[0]_midout chany[1][1]_out[49]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[65]_no0 chany[1][1]_out[49]_loadlvl[0]_midout chany[1][1]_out[49]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[50] density = 0, probability=0.***** -Vchany[1][1]_in[50] chany[1][1]_in[50] 0 -+ 0 -**** Load for rr_node[542] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=51, type=5 ***** -Xchan_chany[1][1]_out[51]_loadlvl[0]_out chany[1][1]_out[51] chany[1][1]_out[51]_loadlvl[0]_out chany[1][1]_out[51]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[66]_no0 chany[1][1]_out[51]_loadlvl[0]_out chany[1][1]_out[51]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[67]_no0 chany[1][1]_out[51]_loadlvl[0]_midout chany[1][1]_out[51]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[52] density = 0, probability=0.***** -Vchany[1][1]_in[52] chany[1][1]_in[52] 0 -+ 0 -**** Load for rr_node[544] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=53, type=5 ***** -Xchan_chany[1][1]_out[53]_loadlvl[0]_out chany[1][1]_out[53] chany[1][1]_out[53]_loadlvl[0]_out chany[1][1]_out[53]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[68]_no0 chany[1][1]_out[53]_loadlvl[0]_out chany[1][1]_out[53]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[69]_no0 chany[1][1]_out[53]_loadlvl[0]_midout chany[1][1]_out[53]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[70]_no0 chany[1][1]_out[53]_loadlvl[0]_midout chany[1][1]_out[53]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[54] density = 0, probability=0.***** -Vchany[1][1]_in[54] chany[1][1]_in[54] 0 -+ 0 -**** Load for rr_node[546] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=55, type=5 ***** -Xchan_chany[1][1]_out[55]_loadlvl[0]_out chany[1][1]_out[55] chany[1][1]_out[55]_loadlvl[0]_out chany[1][1]_out[55]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[71]_no0 chany[1][1]_out[55]_loadlvl[0]_out chany[1][1]_out[55]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[72]_no0 chany[1][1]_out[55]_loadlvl[0]_midout chany[1][1]_out[55]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[56] density = 0, probability=0.***** -Vchany[1][1]_in[56] chany[1][1]_in[56] 0 -+ 0 -**** Load for rr_node[548] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=57, type=5 ***** -Xchan_chany[1][1]_out[57]_loadlvl[0]_out chany[1][1]_out[57] chany[1][1]_out[57]_loadlvl[0]_out chany[1][1]_out[57]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[73]_no0 chany[1][1]_out[57]_loadlvl[0]_out chany[1][1]_out[57]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[74]_no0 chany[1][1]_out[57]_loadlvl[0]_midout chany[1][1]_out[57]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[58] density = 0, probability=0.***** -Vchany[1][1]_in[58] chany[1][1]_in[58] 0 -+ 0 -**** Load for rr_node[550] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=59, type=5 ***** -Xchan_chany[1][1]_out[59]_loadlvl[0]_out chany[1][1]_out[59] chany[1][1]_out[59]_loadlvl[0]_out chany[1][1]_out[59]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[75]_no0 chany[1][1]_out[59]_loadlvl[0]_out chany[1][1]_out[59]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[76]_no0 chany[1][1]_out[59]_loadlvl[0]_midout chany[1][1]_out[59]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[77]_no0 chany[1][1]_out[59]_loadlvl[0]_midout chany[1][1]_out[59]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[60] density = 0, probability=0.***** -Vchany[1][1]_in[60] chany[1][1]_in[60] 0 -+ 0 -**** Load for rr_node[552] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=61, type=5 ***** -Xchan_chany[1][1]_out[61]_loadlvl[0]_out chany[1][1]_out[61] chany[1][1]_out[61]_loadlvl[0]_out chany[1][1]_out[61]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[78]_no0 chany[1][1]_out[61]_loadlvl[0]_out chany[1][1]_out[61]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[79]_no0 chany[1][1]_out[61]_loadlvl[0]_midout chany[1][1]_out[61]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[62] density = 0, probability=0.***** -Vchany[1][1]_in[62] chany[1][1]_in[62] 0 -+ 0 -**** Load for rr_node[554] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=63, type=5 ***** -Xchan_chany[1][1]_out[63]_loadlvl[0]_out chany[1][1]_out[63] chany[1][1]_out[63]_loadlvl[0]_out chany[1][1]_out[63]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[80]_no0 chany[1][1]_out[63]_loadlvl[0]_out chany[1][1]_out[63]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[81]_no0 chany[1][1]_out[63]_loadlvl[0]_midout chany[1][1]_out[63]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[82]_no0 chany[1][1]_out[63]_loadlvl[0]_midout chany[1][1]_out[63]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[64] density = 0, probability=0.***** -Vchany[1][1]_in[64] chany[1][1]_in[64] 0 -+ 0 -**** Load for rr_node[556] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=65, type=5 ***** -Xchan_chany[1][1]_out[65]_loadlvl[0]_out chany[1][1]_out[65] chany[1][1]_out[65]_loadlvl[0]_out chany[1][1]_out[65]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[83]_no0 chany[1][1]_out[65]_loadlvl[0]_out chany[1][1]_out[65]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[84]_no0 chany[1][1]_out[65]_loadlvl[0]_midout chany[1][1]_out[65]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[85]_no0 chany[1][1]_out[65]_loadlvl[0]_midout chany[1][1]_out[65]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[66] density = 0, probability=0.***** -Vchany[1][1]_in[66] chany[1][1]_in[66] 0 -+ 0 -**** Load for rr_node[558] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=67, type=5 ***** -Xchan_chany[1][1]_out[67]_loadlvl[0]_out chany[1][1]_out[67] chany[1][1]_out[67]_loadlvl[0]_out chany[1][1]_out[67]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[86]_no0 chany[1][1]_out[67]_loadlvl[0]_out chany[1][1]_out[67]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[87]_no0 chany[1][1]_out[67]_loadlvl[0]_midout chany[1][1]_out[67]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[88]_no0 chany[1][1]_out[67]_loadlvl[0]_midout chany[1][1]_out[67]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[68] density = 0, probability=0.***** -Vchany[1][1]_in[68] chany[1][1]_in[68] 0 -+ 0 -**** Load for rr_node[560] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=69, type=5 ***** -Xchan_chany[1][1]_out[69]_loadlvl[0]_out chany[1][1]_out[69] chany[1][1]_out[69]_loadlvl[0]_out chany[1][1]_out[69]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[89]_no0 chany[1][1]_out[69]_loadlvl[0]_out chany[1][1]_out[69]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[90]_no0 chany[1][1]_out[69]_loadlvl[0]_midout chany[1][1]_out[69]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[70] density = 0, probability=0.***** -Vchany[1][1]_in[70] chany[1][1]_in[70] 0 -+ 0 -**** Load for rr_node[562] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=71, type=5 ***** -Xchan_chany[1][1]_out[71]_loadlvl[0]_out chany[1][1]_out[71] chany[1][1]_out[71]_loadlvl[0]_out chany[1][1]_out[71]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[91]_no0 chany[1][1]_out[71]_loadlvl[0]_out chany[1][1]_out[71]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[92]_no0 chany[1][1]_out[71]_loadlvl[0]_midout chany[1][1]_out[71]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[93]_no0 chany[1][1]_out[71]_loadlvl[0]_midout chany[1][1]_out[71]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[72] density = 0, probability=0.***** -Vchany[1][1]_in[72] chany[1][1]_in[72] 0 -+ 0 -**** Load for rr_node[564] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=73, type=5 ***** -Xchan_chany[1][1]_out[73]_loadlvl[0]_out chany[1][1]_out[73] chany[1][1]_out[73]_loadlvl[0]_out chany[1][1]_out[73]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[94]_no0 chany[1][1]_out[73]_loadlvl[0]_out chany[1][1]_out[73]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[95]_no0 chany[1][1]_out[73]_loadlvl[0]_midout chany[1][1]_out[73]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[74] density = 0, probability=0.***** -Vchany[1][1]_in[74] chany[1][1]_in[74] 0 -+ 0 -**** Load for rr_node[566] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=75, type=5 ***** -Xchan_chany[1][1]_out[75]_loadlvl[0]_out chany[1][1]_out[75] chany[1][1]_out[75]_loadlvl[0]_out chany[1][1]_out[75]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[96]_no0 chany[1][1]_out[75]_loadlvl[0]_out chany[1][1]_out[75]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[97]_no0 chany[1][1]_out[75]_loadlvl[0]_midout chany[1][1]_out[75]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[98]_no0 chany[1][1]_out[75]_loadlvl[0]_midout chany[1][1]_out[75]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[76] density = 0, probability=0.***** -Vchany[1][1]_in[76] chany[1][1]_in[76] 0 -+ 0 -**** Load for rr_node[568] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=77, type=5 ***** -Xchan_chany[1][1]_out[77]_loadlvl[0]_out chany[1][1]_out[77] chany[1][1]_out[77]_loadlvl[0]_out chany[1][1]_out[77]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[99]_no0 chany[1][1]_out[77]_loadlvl[0]_out chany[1][1]_out[77]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[100]_no0 chany[1][1]_out[77]_loadlvl[0]_midout chany[1][1]_out[77]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[101]_no0 chany[1][1]_out[77]_loadlvl[0]_midout chany[1][1]_out[77]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[78] density = 0, probability=0.***** -Vchany[1][1]_in[78] chany[1][1]_in[78] 0 -+ 0 -**** Load for rr_node[570] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=79, type=5 ***** -Xchan_chany[1][1]_out[79]_loadlvl[0]_out chany[1][1]_out[79] chany[1][1]_out[79]_loadlvl[0]_out chany[1][1]_out[79]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[102]_no0 chany[1][1]_out[79]_loadlvl[0]_out chany[1][1]_out[79]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[103]_no0 chany[1][1]_out[79]_loadlvl[0]_midout chany[1][1]_out[79]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[80] density = 0, probability=0.***** -Vchany[1][1]_in[80] chany[1][1]_in[80] 0 -+ 0 -**** Load for rr_node[572] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=81, type=5 ***** -Xchan_chany[1][1]_out[81]_loadlvl[0]_out chany[1][1]_out[81] chany[1][1]_out[81]_loadlvl[0]_out chany[1][1]_out[81]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[104]_no0 chany[1][1]_out[81]_loadlvl[0]_out chany[1][1]_out[81]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[105]_no0 chany[1][1]_out[81]_loadlvl[0]_midout chany[1][1]_out[81]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[106]_no0 chany[1][1]_out[81]_loadlvl[0]_midout chany[1][1]_out[81]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[82] density = 0, probability=0.***** -Vchany[1][1]_in[82] chany[1][1]_in[82] 0 -+ 0 -**** Load for rr_node[574] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=83, type=5 ***** -Xchan_chany[1][1]_out[83]_loadlvl[0]_out chany[1][1]_out[83] chany[1][1]_out[83]_loadlvl[0]_out chany[1][1]_out[83]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[107]_no0 chany[1][1]_out[83]_loadlvl[0]_out chany[1][1]_out[83]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[108]_no0 chany[1][1]_out[83]_loadlvl[0]_midout chany[1][1]_out[83]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[84] density = 0, probability=0.***** -Vchany[1][1]_in[84] chany[1][1]_in[84] 0 -+ 0 -**** Load for rr_node[576] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=85, type=5 ***** -Xchan_chany[1][1]_out[85]_loadlvl[0]_out chany[1][1]_out[85] chany[1][1]_out[85]_loadlvl[0]_out chany[1][1]_out[85]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[109]_no0 chany[1][1]_out[85]_loadlvl[0]_out chany[1][1]_out[85]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[110]_no0 chany[1][1]_out[85]_loadlvl[0]_midout chany[1][1]_out[85]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[111]_no0 chany[1][1]_out[85]_loadlvl[0]_midout chany[1][1]_out[85]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[86] density = 0, probability=0.***** -Vchany[1][1]_in[86] chany[1][1]_in[86] 0 -+ 0 -**** Load for rr_node[578] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=87, type=5 ***** -Xchan_chany[1][1]_out[87]_loadlvl[0]_out chany[1][1]_out[87] chany[1][1]_out[87]_loadlvl[0]_out chany[1][1]_out[87]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[112]_no0 chany[1][1]_out[87]_loadlvl[0]_out chany[1][1]_out[87]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[113]_no0 chany[1][1]_out[87]_loadlvl[0]_midout chany[1][1]_out[87]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[114]_no0 chany[1][1]_out[87]_loadlvl[0]_midout chany[1][1]_out[87]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[88] density = 0, probability=0.***** -Vchany[1][1]_in[88] chany[1][1]_in[88] 0 -+ 0 -**** Load for rr_node[580] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=89, type=5 ***** -Xchan_chany[1][1]_out[89]_loadlvl[0]_out chany[1][1]_out[89] chany[1][1]_out[89]_loadlvl[0]_out chany[1][1]_out[89]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[115]_no0 chany[1][1]_out[89]_loadlvl[0]_out chany[1][1]_out[89]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[116]_no0 chany[1][1]_out[89]_loadlvl[0]_midout chany[1][1]_out[89]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[90] density = 0, probability=0.***** -Vchany[1][1]_in[90] chany[1][1]_in[90] 0 -+ 0 -**** Load for rr_node[582] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=91, type=5 ***** -Xchan_chany[1][1]_out[91]_loadlvl[0]_out chany[1][1]_out[91] chany[1][1]_out[91]_loadlvl[0]_out chany[1][1]_out[91]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[117]_no0 chany[1][1]_out[91]_loadlvl[0]_out chany[1][1]_out[91]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[118]_no0 chany[1][1]_out[91]_loadlvl[0]_midout chany[1][1]_out[91]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[119]_no0 chany[1][1]_out[91]_loadlvl[0]_midout chany[1][1]_out[91]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[92] density = 0, probability=0.***** -Vchany[1][1]_in[92] chany[1][1]_in[92] 0 -+ 0 -**** Load for rr_node[584] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=93, type=5 ***** -Xchan_chany[1][1]_out[93]_loadlvl[0]_out chany[1][1]_out[93] chany[1][1]_out[93]_loadlvl[0]_out chany[1][1]_out[93]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[120]_no0 chany[1][1]_out[93]_loadlvl[0]_out chany[1][1]_out[93]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[121]_no0 chany[1][1]_out[93]_loadlvl[0]_midout chany[1][1]_out[93]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[94] density = 0, probability=0.***** -Vchany[1][1]_in[94] chany[1][1]_in[94] 0 -+ 0 -**** Load for rr_node[586] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=95, type=5 ***** -Xchan_chany[1][1]_out[95]_loadlvl[0]_out chany[1][1]_out[95] chany[1][1]_out[95]_loadlvl[0]_out chany[1][1]_out[95]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[122]_no0 chany[1][1]_out[95]_loadlvl[0]_out chany[1][1]_out[95]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[123]_no0 chany[1][1]_out[95]_loadlvl[0]_midout chany[1][1]_out[95]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[124]_no0 chany[1][1]_out[95]_loadlvl[0]_midout chany[1][1]_out[95]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[96] density = 0, probability=0.***** -Vchany[1][1]_in[96] chany[1][1]_in[96] 0 -+ 0 -**** Load for rr_node[588] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=97, type=5 ***** -Xchan_chany[1][1]_out[97]_loadlvl[0]_out chany[1][1]_out[97] chany[1][1]_out[97]_loadlvl[0]_out chany[1][1]_out[97]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[125]_no0 chany[1][1]_out[97]_loadlvl[0]_out chany[1][1]_out[97]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[126]_no0 chany[1][1]_out[97]_loadlvl[0]_midout chany[1][1]_out[97]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[127]_no0 chany[1][1]_out[97]_loadlvl[0]_midout chany[1][1]_out[97]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chany[1][1]_in[98] density = 0, probability=0.***** -Vchany[1][1]_in[98] chany[1][1]_in[98] 0 -+ 0 -**** Load for rr_node[590] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=99, type=5 ***** -Xchan_chany[1][1]_out[99]_loadlvl[0]_out chany[1][1]_out[99] chany[1][1]_out[99]_loadlvl[0]_out chany[1][1]_out[99]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[128]_no0 chany[1][1]_out[99]_loadlvl[0]_out chany[1][1]_out[99]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[129]_no0 chany[1][1]_out[99]_loadlvl[0]_midout chany[1][1]_out[99]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Vgrid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][1] 0 -+ 0 -Vgrid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][3] 0 -+ 0 -Vgrid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][5] 0 -+ 0 -Vgrid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][7] 0 -+ 0 -Vgrid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][9] 0 -+ 0 -Vgrid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][11] 0 -+ 0 -Vgrid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][13] 0 -+ 0 -Vgrid[2][1]_pin[0][3][15] grid[2][1]_pin[0][3][15] 0 -+ 0 -Vgrid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][41] 0 -+ 0 -Vgrid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][45] 0 -+ 0 -Vgrid[1][1]_pin[0][1][49] grid[1][1]_pin[0][1][49] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') - -***** Signal chanx[1][1]_in[0] density = 0, probability=0.***** -Vchanx[1][1]_in[0] chanx[1][1]_in[0] 0 -+ 0 -**** Load for rr_node[292] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=1, type=4 ***** -Xchan_chanx[1][1]_out[1]_loadlvl[0]_out chanx[1][1]_out[1] chanx[1][1]_out[1]_loadlvl[0]_out chanx[1][1]_out[1]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[130]_no0 chanx[1][1]_out[1]_loadlvl[0]_out chanx[1][1]_out[1]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[131]_no0 chanx[1][1]_out[1]_loadlvl[0]_midout chanx[1][1]_out[1]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[132]_no0 chanx[1][1]_out[1]_loadlvl[0]_midout chanx[1][1]_out[1]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[133]_no0 chanx[1][1]_out[1]_loadlvl[0]_midout chanx[1][1]_out[1]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[134]_no0 chanx[1][1]_out[1]_loadlvl[0]_midout chanx[1][1]_out[1]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[2] density = 0, probability=0.***** -Vchanx[1][1]_in[2] chanx[1][1]_in[2] 0 -+ 0 -**** Load for rr_node[294] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=3, type=4 ***** -Xchan_chanx[1][1]_out[3]_loadlvl[0]_out chanx[1][1]_out[3] chanx[1][1]_out[3]_loadlvl[0]_out chanx[1][1]_out[3]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[135]_no0 chanx[1][1]_out[3]_loadlvl[0]_out chanx[1][1]_out[3]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[136]_no0 chanx[1][1]_out[3]_loadlvl[0]_midout chanx[1][1]_out[3]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[137]_no0 chanx[1][1]_out[3]_loadlvl[0]_midout chanx[1][1]_out[3]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[4] density = 0, probability=0.***** -Vchanx[1][1]_in[4] chanx[1][1]_in[4] 0 -+ 0 -**** Load for rr_node[296] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=5, type=4 ***** -Xchan_chanx[1][1]_out[5]_loadlvl[0]_out chanx[1][1]_out[5] chanx[1][1]_out[5]_loadlvl[0]_out chanx[1][1]_out[5]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[138]_no0 chanx[1][1]_out[5]_loadlvl[0]_out chanx[1][1]_out[5]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[139]_no0 chanx[1][1]_out[5]_loadlvl[0]_midout chanx[1][1]_out[5]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[140]_no0 chanx[1][1]_out[5]_loadlvl[0]_midout chanx[1][1]_out[5]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[141]_no0 chanx[1][1]_out[5]_loadlvl[0]_midout chanx[1][1]_out[5]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[6] density = 0, probability=0.***** -Vchanx[1][1]_in[6] chanx[1][1]_in[6] 0 -+ 0 -**** Load for rr_node[298] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=7, type=4 ***** -Xchan_chanx[1][1]_out[7]_loadlvl[0]_out chanx[1][1]_out[7] chanx[1][1]_out[7]_loadlvl[0]_out chanx[1][1]_out[7]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[142]_no0 chanx[1][1]_out[7]_loadlvl[0]_out chanx[1][1]_out[7]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[143]_no0 chanx[1][1]_out[7]_loadlvl[0]_midout chanx[1][1]_out[7]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[144]_no0 chanx[1][1]_out[7]_loadlvl[0]_midout chanx[1][1]_out[7]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[145]_no0 chanx[1][1]_out[7]_loadlvl[0]_midout chanx[1][1]_out[7]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[8] density = 0, probability=0.***** -Vchanx[1][1]_in[8] chanx[1][1]_in[8] 0 -+ 0 -**** Load for rr_node[300] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=9, type=4 ***** -Xchan_chanx[1][1]_out[9]_loadlvl[0]_out chanx[1][1]_out[9] chanx[1][1]_out[9]_loadlvl[0]_out chanx[1][1]_out[9]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[146]_no0 chanx[1][1]_out[9]_loadlvl[0]_out chanx[1][1]_out[9]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[147]_no0 chanx[1][1]_out[9]_loadlvl[0]_midout chanx[1][1]_out[9]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[148]_no0 chanx[1][1]_out[9]_loadlvl[0]_midout chanx[1][1]_out[9]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[149]_no0 chanx[1][1]_out[9]_loadlvl[0]_midout chanx[1][1]_out[9]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[150]_no0 chanx[1][1]_out[9]_loadlvl[0]_midout chanx[1][1]_out[9]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[10] density = 0, probability=0.***** -Vchanx[1][1]_in[10] chanx[1][1]_in[10] 0 -+ 0 -**** Load for rr_node[302] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=11, type=4 ***** -Xchan_chanx[1][1]_out[11]_loadlvl[0]_out chanx[1][1]_out[11] chanx[1][1]_out[11]_loadlvl[0]_out chanx[1][1]_out[11]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[151]_no0 chanx[1][1]_out[11]_loadlvl[0]_out chanx[1][1]_out[11]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[152]_no0 chanx[1][1]_out[11]_loadlvl[0]_midout chanx[1][1]_out[11]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[153]_no0 chanx[1][1]_out[11]_loadlvl[0]_midout chanx[1][1]_out[11]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[154]_no0 chanx[1][1]_out[11]_loadlvl[0]_midout chanx[1][1]_out[11]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[12] density = 0, probability=0.***** -Vchanx[1][1]_in[12] chanx[1][1]_in[12] 0 -+ 0 -**** Load for rr_node[304] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=13, type=4 ***** -Xchan_chanx[1][1]_out[13]_loadlvl[0]_out chanx[1][1]_out[13] chanx[1][1]_out[13]_loadlvl[0]_out chanx[1][1]_out[13]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[155]_no0 chanx[1][1]_out[13]_loadlvl[0]_out chanx[1][1]_out[13]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[156]_no0 chanx[1][1]_out[13]_loadlvl[0]_midout chanx[1][1]_out[13]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[157]_no0 chanx[1][1]_out[13]_loadlvl[0]_midout chanx[1][1]_out[13]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[14] density = 0, probability=0.***** -Vchanx[1][1]_in[14] chanx[1][1]_in[14] 0 -+ 0 -**** Load for rr_node[306] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=15, type=4 ***** -Xchan_chanx[1][1]_out[15]_loadlvl[0]_out chanx[1][1]_out[15] chanx[1][1]_out[15]_loadlvl[0]_out chanx[1][1]_out[15]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[158]_no0 chanx[1][1]_out[15]_loadlvl[0]_out chanx[1][1]_out[15]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[159]_no0 chanx[1][1]_out[15]_loadlvl[0]_midout chanx[1][1]_out[15]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[160]_no0 chanx[1][1]_out[15]_loadlvl[0]_midout chanx[1][1]_out[15]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[16] density = 0, probability=0.***** -Vchanx[1][1]_in[16] chanx[1][1]_in[16] 0 -+ 0 -**** Load for rr_node[308] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=17, type=4 ***** -Xchan_chanx[1][1]_out[17]_loadlvl[0]_out chanx[1][1]_out[17] chanx[1][1]_out[17]_loadlvl[0]_out chanx[1][1]_out[17]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[161]_no0 chanx[1][1]_out[17]_loadlvl[0]_out chanx[1][1]_out[17]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[162]_no0 chanx[1][1]_out[17]_loadlvl[0]_midout chanx[1][1]_out[17]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[163]_no0 chanx[1][1]_out[17]_loadlvl[0]_midout chanx[1][1]_out[17]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[18] density = 0, probability=0.***** -Vchanx[1][1]_in[18] chanx[1][1]_in[18] 0 -+ 0 -**** Load for rr_node[310] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=19, type=4 ***** -Xchan_chanx[1][1]_out[19]_loadlvl[0]_out chanx[1][1]_out[19] chanx[1][1]_out[19]_loadlvl[0]_out chanx[1][1]_out[19]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[164]_no0 chanx[1][1]_out[19]_loadlvl[0]_out chanx[1][1]_out[19]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[165]_no0 chanx[1][1]_out[19]_loadlvl[0]_midout chanx[1][1]_out[19]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[166]_no0 chanx[1][1]_out[19]_loadlvl[0]_midout chanx[1][1]_out[19]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[167]_no0 chanx[1][1]_out[19]_loadlvl[0]_midout chanx[1][1]_out[19]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[20] density = 0.2026, probability=0.4982.***** -Vchanx[1][1]_in[20] chanx[1][1]_in[20] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4982*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -**** Load for rr_node[312] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=21, type=4 ***** -Xchan_chanx[1][1]_out[21]_loadlvl[0]_out chanx[1][1]_out[21] chanx[1][1]_out[21]_loadlvl[0]_out chanx[1][1]_out[21]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[168]_no0 chanx[1][1]_out[21]_loadlvl[0]_out chanx[1][1]_out[21]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[169]_no0 chanx[1][1]_out[21]_loadlvl[0]_midout chanx[1][1]_out[21]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[170]_no0 chanx[1][1]_out[21]_loadlvl[0]_midout chanx[1][1]_out[21]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[171]_no0 chanx[1][1]_out[21]_loadlvl[0]_midout chanx[1][1]_out[21]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[22] density = 0, probability=0.***** -Vchanx[1][1]_in[22] chanx[1][1]_in[22] 0 -+ 0 -**** Load for rr_node[314] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=23, type=4 ***** -Xchan_chanx[1][1]_out[23]_loadlvl[0]_out chanx[1][1]_out[23] chanx[1][1]_out[23]_loadlvl[0]_out chanx[1][1]_out[23]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[172]_no0 chanx[1][1]_out[23]_loadlvl[0]_out chanx[1][1]_out[23]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[173]_no0 chanx[1][1]_out[23]_loadlvl[0]_midout chanx[1][1]_out[23]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[174]_no0 chanx[1][1]_out[23]_loadlvl[0]_midout chanx[1][1]_out[23]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[175]_no0 chanx[1][1]_out[23]_loadlvl[0]_midout chanx[1][1]_out[23]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[176]_no0 chanx[1][1]_out[23]_loadlvl[0]_midout chanx[1][1]_out[23]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[24] density = 0, probability=0.***** -Vchanx[1][1]_in[24] chanx[1][1]_in[24] 0 -+ 0 -**** Load for rr_node[316] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=25, type=4 ***** -Xchan_chanx[1][1]_out[25]_loadlvl[0]_out chanx[1][1]_out[25] chanx[1][1]_out[25]_loadlvl[0]_out chanx[1][1]_out[25]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[177]_no0 chanx[1][1]_out[25]_loadlvl[0]_out chanx[1][1]_out[25]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[178]_no0 chanx[1][1]_out[25]_loadlvl[0]_midout chanx[1][1]_out[25]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[179]_no0 chanx[1][1]_out[25]_loadlvl[0]_midout chanx[1][1]_out[25]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[180]_no0 chanx[1][1]_out[25]_loadlvl[0]_midout chanx[1][1]_out[25]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[26] density = 0, probability=0.***** -Vchanx[1][1]_in[26] chanx[1][1]_in[26] 0 -+ 0 -**** Load for rr_node[318] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=27, type=4 ***** -Xchan_chanx[1][1]_out[27]_loadlvl[0]_out chanx[1][1]_out[27] chanx[1][1]_out[27]_loadlvl[0]_out chanx[1][1]_out[27]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[181]_no0 chanx[1][1]_out[27]_loadlvl[0]_out chanx[1][1]_out[27]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[182]_no0 chanx[1][1]_out[27]_loadlvl[0]_midout chanx[1][1]_out[27]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[183]_no0 chanx[1][1]_out[27]_loadlvl[0]_midout chanx[1][1]_out[27]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[28] density = 0, probability=0.***** -Vchanx[1][1]_in[28] chanx[1][1]_in[28] 0 -+ 0 -**** Load for rr_node[320] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=29, type=4 ***** -Xchan_chanx[1][1]_out[29]_loadlvl[0]_out chanx[1][1]_out[29] chanx[1][1]_out[29]_loadlvl[0]_out chanx[1][1]_out[29]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[184]_no0 chanx[1][1]_out[29]_loadlvl[0]_out chanx[1][1]_out[29]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[185]_no0 chanx[1][1]_out[29]_loadlvl[0]_midout chanx[1][1]_out[29]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[186]_no0 chanx[1][1]_out[29]_loadlvl[0]_midout chanx[1][1]_out[29]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[187]_no0 chanx[1][1]_out[29]_loadlvl[0]_midout chanx[1][1]_out[29]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[30] density = 0, probability=0.***** -Vchanx[1][1]_in[30] chanx[1][1]_in[30] 0 -+ 0 -**** Load for rr_node[322] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=31, type=4 ***** -Xchan_chanx[1][1]_out[31]_loadlvl[0]_out chanx[1][1]_out[31] chanx[1][1]_out[31]_loadlvl[0]_out chanx[1][1]_out[31]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[188]_no0 chanx[1][1]_out[31]_loadlvl[0]_out chanx[1][1]_out[31]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[189]_no0 chanx[1][1]_out[31]_loadlvl[0]_midout chanx[1][1]_out[31]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[190]_no0 chanx[1][1]_out[31]_loadlvl[0]_midout chanx[1][1]_out[31]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[191]_no0 chanx[1][1]_out[31]_loadlvl[0]_midout chanx[1][1]_out[31]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[32] density = 0, probability=0.***** -Vchanx[1][1]_in[32] chanx[1][1]_in[32] 0 -+ 0 -**** Load for rr_node[324] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=33, type=4 ***** -Xchan_chanx[1][1]_out[33]_loadlvl[0]_out chanx[1][1]_out[33] chanx[1][1]_out[33]_loadlvl[0]_out chanx[1][1]_out[33]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[192]_no0 chanx[1][1]_out[33]_loadlvl[0]_out chanx[1][1]_out[33]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[193]_no0 chanx[1][1]_out[33]_loadlvl[0]_midout chanx[1][1]_out[33]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[194]_no0 chanx[1][1]_out[33]_loadlvl[0]_midout chanx[1][1]_out[33]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[34] density = 0, probability=0.***** -Vchanx[1][1]_in[34] chanx[1][1]_in[34] 0 -+ 0 -**** Load for rr_node[326] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=35, type=4 ***** -Xchan_chanx[1][1]_out[35]_loadlvl[0]_out chanx[1][1]_out[35] chanx[1][1]_out[35]_loadlvl[0]_out chanx[1][1]_out[35]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[195]_no0 chanx[1][1]_out[35]_loadlvl[0]_out chanx[1][1]_out[35]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[196]_no0 chanx[1][1]_out[35]_loadlvl[0]_midout chanx[1][1]_out[35]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[197]_no0 chanx[1][1]_out[35]_loadlvl[0]_midout chanx[1][1]_out[35]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[198]_no0 chanx[1][1]_out[35]_loadlvl[0]_midout chanx[1][1]_out[35]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[36] density = 0, probability=0.***** -Vchanx[1][1]_in[36] chanx[1][1]_in[36] 0 -+ 0 -**** Load for rr_node[328] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=37, type=4 ***** -Xchan_chanx[1][1]_out[37]_loadlvl[0]_out chanx[1][1]_out[37] chanx[1][1]_out[37]_loadlvl[0]_out chanx[1][1]_out[37]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[199]_no0 chanx[1][1]_out[37]_loadlvl[0]_out chanx[1][1]_out[37]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[200]_no0 chanx[1][1]_out[37]_loadlvl[0]_midout chanx[1][1]_out[37]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[201]_no0 chanx[1][1]_out[37]_loadlvl[0]_midout chanx[1][1]_out[37]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[202]_no0 chanx[1][1]_out[37]_loadlvl[0]_midout chanx[1][1]_out[37]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[38] density = 0, probability=0.***** -Vchanx[1][1]_in[38] chanx[1][1]_in[38] 0 -+ 0 -**** Load for rr_node[330] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=39, type=4 ***** -Xchan_chanx[1][1]_out[39]_loadlvl[0]_out chanx[1][1]_out[39] chanx[1][1]_out[39]_loadlvl[0]_out chanx[1][1]_out[39]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg0 -Xload_inv[203]_no0 chanx[1][1]_out[39]_loadlvl[0]_out chanx[1][1]_out[39]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[204]_no0 chanx[1][1]_out[39]_loadlvl[0]_midout chanx[1][1]_out[39]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[205]_no0 chanx[1][1]_out[39]_loadlvl[0]_midout chanx[1][1]_out[39]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[206]_no0 chanx[1][1]_out[39]_loadlvl[0]_midout chanx[1][1]_out[39]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[207]_no0 chanx[1][1]_out[39]_loadlvl[0]_midout chanx[1][1]_out[39]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[40] density = 0, probability=0.***** -Vchanx[1][1]_in[40] chanx[1][1]_in[40] 0 -+ 0 -**** Load for rr_node[332] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=41, type=4 ***** -Xchan_chanx[1][1]_out[41]_loadlvl[0]_out chanx[1][1]_out[41] chanx[1][1]_out[41]_loadlvl[0]_out chanx[1][1]_out[41]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[208]_no0 chanx[1][1]_out[41]_loadlvl[0]_out chanx[1][1]_out[41]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[209]_no0 chanx[1][1]_out[41]_loadlvl[0]_midout chanx[1][1]_out[41]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[210]_no0 chanx[1][1]_out[41]_loadlvl[0]_midout chanx[1][1]_out[41]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[211]_no0 chanx[1][1]_out[41]_loadlvl[0]_midout chanx[1][1]_out[41]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[42] density = 0, probability=0.***** -Vchanx[1][1]_in[42] chanx[1][1]_in[42] 0 -+ 0 -**** Load for rr_node[334] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=43, type=4 ***** -Xchan_chanx[1][1]_out[43]_loadlvl[0]_out chanx[1][1]_out[43] chanx[1][1]_out[43]_loadlvl[0]_out chanx[1][1]_out[43]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[212]_no0 chanx[1][1]_out[43]_loadlvl[0]_out chanx[1][1]_out[43]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[213]_no0 chanx[1][1]_out[43]_loadlvl[0]_midout chanx[1][1]_out[43]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[214]_no0 chanx[1][1]_out[43]_loadlvl[0]_midout chanx[1][1]_out[43]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[215]_no0 chanx[1][1]_out[43]_loadlvl[0]_midout chanx[1][1]_out[43]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[44] density = 0, probability=0.***** -Vchanx[1][1]_in[44] chanx[1][1]_in[44] 0 -+ 0 -**** Load for rr_node[336] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=45, type=4 ***** -Xchan_chanx[1][1]_out[45]_loadlvl[0]_out chanx[1][1]_out[45] chanx[1][1]_out[45]_loadlvl[0]_out chanx[1][1]_out[45]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[216]_no0 chanx[1][1]_out[45]_loadlvl[0]_out chanx[1][1]_out[45]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[217]_no0 chanx[1][1]_out[45]_loadlvl[0]_midout chanx[1][1]_out[45]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[218]_no0 chanx[1][1]_out[45]_loadlvl[0]_midout chanx[1][1]_out[45]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[219]_no0 chanx[1][1]_out[45]_loadlvl[0]_midout chanx[1][1]_out[45]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[220]_no0 chanx[1][1]_out[45]_loadlvl[0]_midout chanx[1][1]_out[45]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[46] density = 0, probability=0.***** -Vchanx[1][1]_in[46] chanx[1][1]_in[46] 0 -+ 0 -**** Load for rr_node[338] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=47, type=4 ***** -Xchan_chanx[1][1]_out[47]_loadlvl[0]_out chanx[1][1]_out[47] chanx[1][1]_out[47]_loadlvl[0]_out chanx[1][1]_out[47]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[221]_no0 chanx[1][1]_out[47]_loadlvl[0]_out chanx[1][1]_out[47]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[222]_no0 chanx[1][1]_out[47]_loadlvl[0]_midout chanx[1][1]_out[47]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[223]_no0 chanx[1][1]_out[47]_loadlvl[0]_midout chanx[1][1]_out[47]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[48] density = 0, probability=0.***** -Vchanx[1][1]_in[48] chanx[1][1]_in[48] 0 -+ 0 -**** Load for rr_node[340] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=49, type=4 ***** -Xchan_chanx[1][1]_out[49]_loadlvl[0]_out chanx[1][1]_out[49] chanx[1][1]_out[49]_loadlvl[0]_out chanx[1][1]_out[49]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[224]_no0 chanx[1][1]_out[49]_loadlvl[0]_out chanx[1][1]_out[49]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[225]_no0 chanx[1][1]_out[49]_loadlvl[0]_midout chanx[1][1]_out[49]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[226]_no0 chanx[1][1]_out[49]_loadlvl[0]_midout chanx[1][1]_out[49]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[227]_no0 chanx[1][1]_out[49]_loadlvl[0]_midout chanx[1][1]_out[49]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[50] density = 0, probability=0.***** -Vchanx[1][1]_in[50] chanx[1][1]_in[50] 0 -+ 0 -**** Load for rr_node[342] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=51, type=4 ***** -Xchan_chanx[1][1]_out[51]_loadlvl[0]_out chanx[1][1]_out[51] chanx[1][1]_out[51]_loadlvl[0]_out chanx[1][1]_out[51]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[228]_no0 chanx[1][1]_out[51]_loadlvl[0]_out chanx[1][1]_out[51]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[229]_no0 chanx[1][1]_out[51]_loadlvl[0]_midout chanx[1][1]_out[51]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[230]_no0 chanx[1][1]_out[51]_loadlvl[0]_midout chanx[1][1]_out[51]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[52] density = 0, probability=0.***** -Vchanx[1][1]_in[52] chanx[1][1]_in[52] 0 -+ 0 -**** Load for rr_node[344] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=53, type=4 ***** -Xchan_chanx[1][1]_out[53]_loadlvl[0]_out chanx[1][1]_out[53] chanx[1][1]_out[53]_loadlvl[0]_out chanx[1][1]_out[53]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[231]_no0 chanx[1][1]_out[53]_loadlvl[0]_out chanx[1][1]_out[53]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[232]_no0 chanx[1][1]_out[53]_loadlvl[0]_midout chanx[1][1]_out[53]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[233]_no0 chanx[1][1]_out[53]_loadlvl[0]_midout chanx[1][1]_out[53]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[54] density = 0, probability=0.***** -Vchanx[1][1]_in[54] chanx[1][1]_in[54] 0 -+ 0 -**** Load for rr_node[346] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=55, type=4 ***** -Xchan_chanx[1][1]_out[55]_loadlvl[0]_out chanx[1][1]_out[55] chanx[1][1]_out[55]_loadlvl[0]_out chanx[1][1]_out[55]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[234]_no0 chanx[1][1]_out[55]_loadlvl[0]_out chanx[1][1]_out[55]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[235]_no0 chanx[1][1]_out[55]_loadlvl[0]_midout chanx[1][1]_out[55]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[236]_no0 chanx[1][1]_out[55]_loadlvl[0]_midout chanx[1][1]_out[55]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[237]_no0 chanx[1][1]_out[55]_loadlvl[0]_midout chanx[1][1]_out[55]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[238]_no0 chanx[1][1]_out[55]_loadlvl[0]_midout chanx[1][1]_out[55]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[56] density = 0, probability=0.***** -Vchanx[1][1]_in[56] chanx[1][1]_in[56] 0 -+ 0 -**** Load for rr_node[348] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=57, type=4 ***** -Xchan_chanx[1][1]_out[57]_loadlvl[0]_out chanx[1][1]_out[57] chanx[1][1]_out[57]_loadlvl[0]_out chanx[1][1]_out[57]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[239]_no0 chanx[1][1]_out[57]_loadlvl[0]_out chanx[1][1]_out[57]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[240]_no0 chanx[1][1]_out[57]_loadlvl[0]_midout chanx[1][1]_out[57]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[241]_no0 chanx[1][1]_out[57]_loadlvl[0]_midout chanx[1][1]_out[57]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[58] density = 0, probability=0.***** -Vchanx[1][1]_in[58] chanx[1][1]_in[58] 0 -+ 0 -**** Load for rr_node[350] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=59, type=4 ***** -Xchan_chanx[1][1]_out[59]_loadlvl[0]_out chanx[1][1]_out[59] chanx[1][1]_out[59]_loadlvl[0]_out chanx[1][1]_out[59]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[242]_no0 chanx[1][1]_out[59]_loadlvl[0]_out chanx[1][1]_out[59]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[243]_no0 chanx[1][1]_out[59]_loadlvl[0]_midout chanx[1][1]_out[59]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[244]_no0 chanx[1][1]_out[59]_loadlvl[0]_midout chanx[1][1]_out[59]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[245]_no0 chanx[1][1]_out[59]_loadlvl[0]_midout chanx[1][1]_out[59]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[60] density = 0, probability=0.***** -Vchanx[1][1]_in[60] chanx[1][1]_in[60] 0 -+ 0 -**** Load for rr_node[352] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=61, type=4 ***** -Xchan_chanx[1][1]_out[61]_loadlvl[0]_out chanx[1][1]_out[61] chanx[1][1]_out[61]_loadlvl[0]_out chanx[1][1]_out[61]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[246]_no0 chanx[1][1]_out[61]_loadlvl[0]_out chanx[1][1]_out[61]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[247]_no0 chanx[1][1]_out[61]_loadlvl[0]_midout chanx[1][1]_out[61]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[248]_no0 chanx[1][1]_out[61]_loadlvl[0]_midout chanx[1][1]_out[61]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[249]_no0 chanx[1][1]_out[61]_loadlvl[0]_midout chanx[1][1]_out[61]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[62] density = 0, probability=0.***** -Vchanx[1][1]_in[62] chanx[1][1]_in[62] 0 -+ 0 -**** Load for rr_node[354] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=63, type=4 ***** -Xchan_chanx[1][1]_out[63]_loadlvl[0]_out chanx[1][1]_out[63] chanx[1][1]_out[63]_loadlvl[0]_out chanx[1][1]_out[63]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[250]_no0 chanx[1][1]_out[63]_loadlvl[0]_out chanx[1][1]_out[63]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[251]_no0 chanx[1][1]_out[63]_loadlvl[0]_midout chanx[1][1]_out[63]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[252]_no0 chanx[1][1]_out[63]_loadlvl[0]_midout chanx[1][1]_out[63]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[253]_no0 chanx[1][1]_out[63]_loadlvl[0]_midout chanx[1][1]_out[63]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[254]_no0 chanx[1][1]_out[63]_loadlvl[0]_midout chanx[1][1]_out[63]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[64] density = 0, probability=0.***** -Vchanx[1][1]_in[64] chanx[1][1]_in[64] 0 -+ 0 -**** Load for rr_node[356] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=65, type=4 ***** -Xchan_chanx[1][1]_out[65]_loadlvl[0]_out chanx[1][1]_out[65] chanx[1][1]_out[65]_loadlvl[0]_out chanx[1][1]_out[65]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[255]_no0 chanx[1][1]_out[65]_loadlvl[0]_out chanx[1][1]_out[65]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[256]_no0 chanx[1][1]_out[65]_loadlvl[0]_midout chanx[1][1]_out[65]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[257]_no0 chanx[1][1]_out[65]_loadlvl[0]_midout chanx[1][1]_out[65]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[258]_no0 chanx[1][1]_out[65]_loadlvl[0]_midout chanx[1][1]_out[65]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[259]_no0 chanx[1][1]_out[65]_loadlvl[0]_midout chanx[1][1]_out[65]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[66] density = 0, probability=0.***** -Vchanx[1][1]_in[66] chanx[1][1]_in[66] 0 -+ 0 -**** Load for rr_node[358] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=67, type=4 ***** -Xchan_chanx[1][1]_out[67]_loadlvl[0]_out chanx[1][1]_out[67] chanx[1][1]_out[67]_loadlvl[0]_out chanx[1][1]_out[67]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[260]_no0 chanx[1][1]_out[67]_loadlvl[0]_out chanx[1][1]_out[67]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[261]_no0 chanx[1][1]_out[67]_loadlvl[0]_midout chanx[1][1]_out[67]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[262]_no0 chanx[1][1]_out[67]_loadlvl[0]_midout chanx[1][1]_out[67]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[68] density = 0, probability=0.***** -Vchanx[1][1]_in[68] chanx[1][1]_in[68] 0 -+ 0 -**** Load for rr_node[360] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=69, type=4 ***** -Xchan_chanx[1][1]_out[69]_loadlvl[0]_out chanx[1][1]_out[69] chanx[1][1]_out[69]_loadlvl[0]_out chanx[1][1]_out[69]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg1 -Xload_inv[263]_no0 chanx[1][1]_out[69]_loadlvl[0]_out chanx[1][1]_out[69]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[264]_no0 chanx[1][1]_out[69]_loadlvl[0]_midout chanx[1][1]_out[69]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[265]_no0 chanx[1][1]_out[69]_loadlvl[0]_midout chanx[1][1]_out[69]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[70] density = 0, probability=0.***** -Vchanx[1][1]_in[70] chanx[1][1]_in[70] 0 -+ 0 -**** Load for rr_node[362] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=71, type=4 ***** -Xchan_chanx[1][1]_out[71]_loadlvl[0]_out chanx[1][1]_out[71] chanx[1][1]_out[71]_loadlvl[0]_out chanx[1][1]_out[71]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[266]_no0 chanx[1][1]_out[71]_loadlvl[0]_out chanx[1][1]_out[71]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[267]_no0 chanx[1][1]_out[71]_loadlvl[0]_midout chanx[1][1]_out[71]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[268]_no0 chanx[1][1]_out[71]_loadlvl[0]_midout chanx[1][1]_out[71]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[269]_no0 chanx[1][1]_out[71]_loadlvl[0]_midout chanx[1][1]_out[71]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[72] density = 0, probability=0.***** -Vchanx[1][1]_in[72] chanx[1][1]_in[72] 0 -+ 0 -**** Load for rr_node[364] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=73, type=4 ***** -Xchan_chanx[1][1]_out[73]_loadlvl[0]_out chanx[1][1]_out[73] chanx[1][1]_out[73]_loadlvl[0]_out chanx[1][1]_out[73]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[270]_no0 chanx[1][1]_out[73]_loadlvl[0]_out chanx[1][1]_out[73]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[271]_no0 chanx[1][1]_out[73]_loadlvl[0]_midout chanx[1][1]_out[73]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[272]_no0 chanx[1][1]_out[73]_loadlvl[0]_midout chanx[1][1]_out[73]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[273]_no0 chanx[1][1]_out[73]_loadlvl[0]_midout chanx[1][1]_out[73]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[74] density = 0, probability=0.***** -Vchanx[1][1]_in[74] chanx[1][1]_in[74] 0 -+ 0 -**** Load for rr_node[366] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=75, type=4 ***** -Xchan_chanx[1][1]_out[75]_loadlvl[0]_out chanx[1][1]_out[75] chanx[1][1]_out[75]_loadlvl[0]_out chanx[1][1]_out[75]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[274]_no0 chanx[1][1]_out[75]_loadlvl[0]_out chanx[1][1]_out[75]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[275]_no0 chanx[1][1]_out[75]_loadlvl[0]_midout chanx[1][1]_out[75]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[276]_no0 chanx[1][1]_out[75]_loadlvl[0]_midout chanx[1][1]_out[75]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[277]_no0 chanx[1][1]_out[75]_loadlvl[0]_midout chanx[1][1]_out[75]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[76] density = 0, probability=0.***** -Vchanx[1][1]_in[76] chanx[1][1]_in[76] 0 -+ 0 -**** Load for rr_node[368] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=77, type=4 ***** -Xchan_chanx[1][1]_out[77]_loadlvl[0]_out chanx[1][1]_out[77] chanx[1][1]_out[77]_loadlvl[0]_out chanx[1][1]_out[77]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[278]_no0 chanx[1][1]_out[77]_loadlvl[0]_out chanx[1][1]_out[77]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[279]_no0 chanx[1][1]_out[77]_loadlvl[0]_midout chanx[1][1]_out[77]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[280]_no0 chanx[1][1]_out[77]_loadlvl[0]_midout chanx[1][1]_out[77]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[281]_no0 chanx[1][1]_out[77]_loadlvl[0]_midout chanx[1][1]_out[77]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[78] density = 0, probability=0.***** -Vchanx[1][1]_in[78] chanx[1][1]_in[78] 0 -+ 0 -**** Load for rr_node[370] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=79, type=4 ***** -Xchan_chanx[1][1]_out[79]_loadlvl[0]_out chanx[1][1]_out[79] chanx[1][1]_out[79]_loadlvl[0]_out chanx[1][1]_out[79]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[282]_no0 chanx[1][1]_out[79]_loadlvl[0]_out chanx[1][1]_out[79]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[283]_no0 chanx[1][1]_out[79]_loadlvl[0]_midout chanx[1][1]_out[79]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[284]_no0 chanx[1][1]_out[79]_loadlvl[0]_midout chanx[1][1]_out[79]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[80] density = 0, probability=0.***** -Vchanx[1][1]_in[80] chanx[1][1]_in[80] 0 -+ 0 -**** Load for rr_node[372] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=81, type=4 ***** -Xchan_chanx[1][1]_out[81]_loadlvl[0]_out chanx[1][1]_out[81] chanx[1][1]_out[81]_loadlvl[0]_out chanx[1][1]_out[81]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[285]_no0 chanx[1][1]_out[81]_loadlvl[0]_out chanx[1][1]_out[81]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[286]_no0 chanx[1][1]_out[81]_loadlvl[0]_midout chanx[1][1]_out[81]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[287]_no0 chanx[1][1]_out[81]_loadlvl[0]_midout chanx[1][1]_out[81]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[288]_no0 chanx[1][1]_out[81]_loadlvl[0]_midout chanx[1][1]_out[81]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[82] density = 0, probability=0.***** -Vchanx[1][1]_in[82] chanx[1][1]_in[82] 0 -+ 0 -**** Load for rr_node[374] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=83, type=4 ***** -Xchan_chanx[1][1]_out[83]_loadlvl[0]_out chanx[1][1]_out[83] chanx[1][1]_out[83]_loadlvl[0]_out chanx[1][1]_out[83]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[289]_no0 chanx[1][1]_out[83]_loadlvl[0]_out chanx[1][1]_out[83]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[290]_no0 chanx[1][1]_out[83]_loadlvl[0]_midout chanx[1][1]_out[83]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[291]_no0 chanx[1][1]_out[83]_loadlvl[0]_midout chanx[1][1]_out[83]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[292]_no0 chanx[1][1]_out[83]_loadlvl[0]_midout chanx[1][1]_out[83]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[293]_no0 chanx[1][1]_out[83]_loadlvl[0]_midout chanx[1][1]_out[83]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[84] density = 0, probability=0.***** -Vchanx[1][1]_in[84] chanx[1][1]_in[84] 0 -+ 0 -**** Load for rr_node[376] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=85, type=4 ***** -Xchan_chanx[1][1]_out[85]_loadlvl[0]_out chanx[1][1]_out[85] chanx[1][1]_out[85]_loadlvl[0]_out chanx[1][1]_out[85]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[294]_no0 chanx[1][1]_out[85]_loadlvl[0]_out chanx[1][1]_out[85]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[295]_no0 chanx[1][1]_out[85]_loadlvl[0]_midout chanx[1][1]_out[85]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[296]_no0 chanx[1][1]_out[85]_loadlvl[0]_midout chanx[1][1]_out[85]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[86] density = 0, probability=0.***** -Vchanx[1][1]_in[86] chanx[1][1]_in[86] 0 -+ 0 -**** Load for rr_node[378] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=87, type=4 ***** -Xchan_chanx[1][1]_out[87]_loadlvl[0]_out chanx[1][1]_out[87] chanx[1][1]_out[87]_loadlvl[0]_out chanx[1][1]_out[87]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[297]_no0 chanx[1][1]_out[87]_loadlvl[0]_out chanx[1][1]_out[87]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[298]_no0 chanx[1][1]_out[87]_loadlvl[0]_midout chanx[1][1]_out[87]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[299]_no0 chanx[1][1]_out[87]_loadlvl[0]_midout chanx[1][1]_out[87]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[300]_no0 chanx[1][1]_out[87]_loadlvl[0]_midout chanx[1][1]_out[87]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[88] density = 0, probability=0.***** -Vchanx[1][1]_in[88] chanx[1][1]_in[88] 0 -+ 0 -**** Load for rr_node[380] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=89, type=4 ***** -Xchan_chanx[1][1]_out[89]_loadlvl[0]_out chanx[1][1]_out[89] chanx[1][1]_out[89]_loadlvl[0]_out chanx[1][1]_out[89]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[301]_no0 chanx[1][1]_out[89]_loadlvl[0]_out chanx[1][1]_out[89]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[302]_no0 chanx[1][1]_out[89]_loadlvl[0]_midout chanx[1][1]_out[89]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[303]_no0 chanx[1][1]_out[89]_loadlvl[0]_midout chanx[1][1]_out[89]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[304]_no0 chanx[1][1]_out[89]_loadlvl[0]_midout chanx[1][1]_out[89]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[90] density = 0, probability=0.***** -Vchanx[1][1]_in[90] chanx[1][1]_in[90] 0 -+ 0 -**** Load for rr_node[382] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=91, type=4 ***** -Xchan_chanx[1][1]_out[91]_loadlvl[0]_out chanx[1][1]_out[91] chanx[1][1]_out[91]_loadlvl[0]_out chanx[1][1]_out[91]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[305]_no0 chanx[1][1]_out[91]_loadlvl[0]_out chanx[1][1]_out[91]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[306]_no0 chanx[1][1]_out[91]_loadlvl[0]_midout chanx[1][1]_out[91]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[307]_no0 chanx[1][1]_out[91]_loadlvl[0]_midout chanx[1][1]_out[91]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[308]_no0 chanx[1][1]_out[91]_loadlvl[0]_midout chanx[1][1]_out[91]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[92] density = 0, probability=0.***** -Vchanx[1][1]_in[92] chanx[1][1]_in[92] 0 -+ 0 -**** Load for rr_node[384] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=93, type=4 ***** -Xchan_chanx[1][1]_out[93]_loadlvl[0]_out chanx[1][1]_out[93] chanx[1][1]_out[93]_loadlvl[0]_out chanx[1][1]_out[93]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[309]_no0 chanx[1][1]_out[93]_loadlvl[0]_out chanx[1][1]_out[93]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[310]_no0 chanx[1][1]_out[93]_loadlvl[0]_midout chanx[1][1]_out[93]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[311]_no0 chanx[1][1]_out[93]_loadlvl[0]_midout chanx[1][1]_out[93]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[312]_no0 chanx[1][1]_out[93]_loadlvl[0]_midout chanx[1][1]_out[93]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[94] density = 0, probability=0.***** -Vchanx[1][1]_in[94] chanx[1][1]_in[94] 0 -+ 0 -**** Load for rr_node[386] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=95, type=4 ***** -Xchan_chanx[1][1]_out[95]_loadlvl[0]_out chanx[1][1]_out[95] chanx[1][1]_out[95]_loadlvl[0]_out chanx[1][1]_out[95]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[313]_no0 chanx[1][1]_out[95]_loadlvl[0]_out chanx[1][1]_out[95]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[314]_no0 chanx[1][1]_out[95]_loadlvl[0]_midout chanx[1][1]_out[95]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[315]_no0 chanx[1][1]_out[95]_loadlvl[0]_midout chanx[1][1]_out[95]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[96] density = 0, probability=0.***** -Vchanx[1][1]_in[96] chanx[1][1]_in[96] 0 -+ 0 -**** Load for rr_node[388] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=97, type=4 ***** -Xchan_chanx[1][1]_out[97]_loadlvl[0]_out chanx[1][1]_out[97] chanx[1][1]_out[97]_loadlvl[0]_out chanx[1][1]_out[97]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[316]_no0 chanx[1][1]_out[97]_loadlvl[0]_out chanx[1][1]_out[97]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[317]_no0 chanx[1][1]_out[97]_loadlvl[0]_midout chanx[1][1]_out[97]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[318]_no0 chanx[1][1]_out[97]_loadlvl[0]_midout chanx[1][1]_out[97]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Xload_inv[319]_no0 chanx[1][1]_out[97]_loadlvl[0]_midout chanx[1][1]_out[97]_loadlvl[0]_midout_out[3] gvdd_load 0 inv size=1 -Xload_inv[320]_no0 chanx[1][1]_out[97]_loadlvl[0]_midout chanx[1][1]_out[97]_loadlvl[0]_midout_out[4] gvdd_load 0 inv size=1 -***** Signal chanx[1][1]_in[98] density = 0, probability=0.***** -Vchanx[1][1]_in[98] chanx[1][1]_in[98] 0 -+ 0 -**** Load for rr_node[390] ***** -**** Loads for rr_node: xlow=1, ylow=1, xhigh=1, yhigh=1, ptc_num=99, type=4 ***** -Xchan_chanx[1][1]_out[99]_loadlvl[0]_out chanx[1][1]_out[99] chanx[1][1]_out[99]_loadlvl[0]_out chanx[1][1]_out[99]_loadlvl[0]_midout gvdd_load 0 chan_segment_seg2 -Xload_inv[321]_no0 chanx[1][1]_out[99]_loadlvl[0]_out chanx[1][1]_out[99]_loadlvl[0]_out_out[0] gvdd_load 0 inv size=1 -Xload_inv[322]_no0 chanx[1][1]_out[99]_loadlvl[0]_midout chanx[1][1]_out[99]_loadlvl[0]_midout_out[1] gvdd_load 0 inv size=1 -Xload_inv[323]_no0 chanx[1][1]_out[99]_loadlvl[0]_midout chanx[1][1]_out[99]_loadlvl[0]_midout_out[2] gvdd_load 0 inv size=1 -Vgrid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][1] 0 -+ 0 -Vgrid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][3] 0 -+ 0 -Vgrid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][5] 0 -+ 0 -Vgrid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][7] 0 -+ 0 -Vgrid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][9] 0 -+ 0 -Vgrid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][11] 0 -+ 0 -Vgrid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][13] 0 -+ 0 -Vgrid[1][2]_pin[0][2][15] grid[1][2]_pin[0][2][15] 0 -+ 0 -Vgrid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][40] 0 -+ 0 -Vgrid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][44] 0 -+ 0 -Vgrid[1][1]_pin[0][0][48] grid[1][1]_pin[0][0][48] 0 -+ 0 - -***** Voltage supplies ***** -Vgvdd_sb[1][1] gvdd_sb[1][1] 0 vsp -Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -***** Measurements ***** -***** Leakage Power Measurement ***** -.meas tran leakage_power_sb avg p(Vgvdd_sb[1][1]) from=0 to='clock_period' -.meas tran leakage_power_sram_sb avg p(Vgvdd_sram_sbs) from=0 to='clock_period' -***** Dynamic Power Measurement ***** -.meas tran dynamic_power_sb avg p(Vgvdd_sb[1][1]) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sb param='dynamic_power_sb*clock_period' -.meas tran dynamic_power_sram_sb avg p(Vgvdd_sram_sbs) from='clock_period' to='6*clock_period' -.meas tran energy_per_cycle_sram_sb param='dynamic_power_sram_sb*clock_period' -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for load inverters ***** -Vgvdd_load gvdd_load 0 vsp -.end diff --git a/examples/spice_test_example_2/subckt/cbx_1_0.sp b/examples/spice_test_example_2/subckt/cbx_1_0.sp deleted file mode 100644 index 9e1b6f7bc..000000000 --- a/examples/spice_test_example_2/subckt/cbx_1_0.sp +++ /dev/null @@ -1,616 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Connection Block X-channel [1][0] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -.subckt cbx[1][0] -+ chanx[1][0]_midout[0] -+ chanx[1][0]_midout[1] -+ chanx[1][0]_midout[2] -+ chanx[1][0]_midout[3] -+ chanx[1][0]_midout[4] -+ chanx[1][0]_midout[5] -+ chanx[1][0]_midout[6] -+ chanx[1][0]_midout[7] -+ chanx[1][0]_midout[8] -+ chanx[1][0]_midout[9] -+ chanx[1][0]_midout[10] -+ chanx[1][0]_midout[11] -+ chanx[1][0]_midout[12] -+ chanx[1][0]_midout[13] -+ chanx[1][0]_midout[14] -+ chanx[1][0]_midout[15] -+ chanx[1][0]_midout[16] -+ chanx[1][0]_midout[17] -+ chanx[1][0]_midout[18] -+ chanx[1][0]_midout[19] -+ chanx[1][0]_midout[20] -+ chanx[1][0]_midout[21] -+ chanx[1][0]_midout[22] -+ chanx[1][0]_midout[23] -+ chanx[1][0]_midout[24] -+ chanx[1][0]_midout[25] -+ chanx[1][0]_midout[26] -+ chanx[1][0]_midout[27] -+ chanx[1][0]_midout[28] -+ chanx[1][0]_midout[29] -+ chanx[1][0]_midout[30] -+ chanx[1][0]_midout[31] -+ chanx[1][0]_midout[32] -+ chanx[1][0]_midout[33] -+ chanx[1][0]_midout[34] -+ chanx[1][0]_midout[35] -+ chanx[1][0]_midout[36] -+ chanx[1][0]_midout[37] -+ chanx[1][0]_midout[38] -+ chanx[1][0]_midout[39] -+ chanx[1][0]_midout[40] -+ chanx[1][0]_midout[41] -+ chanx[1][0]_midout[42] -+ chanx[1][0]_midout[43] -+ chanx[1][0]_midout[44] -+ chanx[1][0]_midout[45] -+ chanx[1][0]_midout[46] -+ chanx[1][0]_midout[47] -+ chanx[1][0]_midout[48] -+ chanx[1][0]_midout[49] -+ chanx[1][0]_midout[50] -+ chanx[1][0]_midout[51] -+ chanx[1][0]_midout[52] -+ chanx[1][0]_midout[53] -+ chanx[1][0]_midout[54] -+ chanx[1][0]_midout[55] -+ chanx[1][0]_midout[56] -+ chanx[1][0]_midout[57] -+ chanx[1][0]_midout[58] -+ chanx[1][0]_midout[59] -+ chanx[1][0]_midout[60] -+ chanx[1][0]_midout[61] -+ chanx[1][0]_midout[62] -+ chanx[1][0]_midout[63] -+ chanx[1][0]_midout[64] -+ chanx[1][0]_midout[65] -+ chanx[1][0]_midout[66] -+ chanx[1][0]_midout[67] -+ chanx[1][0]_midout[68] -+ chanx[1][0]_midout[69] -+ chanx[1][0]_midout[70] -+ chanx[1][0]_midout[71] -+ chanx[1][0]_midout[72] -+ chanx[1][0]_midout[73] -+ chanx[1][0]_midout[74] -+ chanx[1][0]_midout[75] -+ chanx[1][0]_midout[76] -+ chanx[1][0]_midout[77] -+ chanx[1][0]_midout[78] -+ chanx[1][0]_midout[79] -+ chanx[1][0]_midout[80] -+ chanx[1][0]_midout[81] -+ chanx[1][0]_midout[82] -+ chanx[1][0]_midout[83] -+ chanx[1][0]_midout[84] -+ chanx[1][0]_midout[85] -+ chanx[1][0]_midout[86] -+ chanx[1][0]_midout[87] -+ chanx[1][0]_midout[88] -+ chanx[1][0]_midout[89] -+ chanx[1][0]_midout[90] -+ chanx[1][0]_midout[91] -+ chanx[1][0]_midout[92] -+ chanx[1][0]_midout[93] -+ chanx[1][0]_midout[94] -+ chanx[1][0]_midout[95] -+ chanx[1][0]_midout[96] -+ chanx[1][0]_midout[97] -+ chanx[1][0]_midout[98] -+ chanx[1][0]_midout[99] -+ grid[1][1]_pin[0][2][2] -+ grid[1][1]_pin[0][2][6] -+ grid[1][1]_pin[0][2][10] -+ grid[1][1]_pin[0][2][14] -+ grid[1][1]_pin[0][2][18] -+ grid[1][1]_pin[0][2][22] -+ grid[1][1]_pin[0][2][26] -+ grid[1][1]_pin[0][2][30] -+ grid[1][1]_pin[0][2][34] -+ grid[1][1]_pin[0][2][38] -+ grid[1][1]_pin[0][2][50] -+ grid[1][0]_pin[0][0][0] -+ grid[1][0]_pin[0][0][2] -+ grid[1][0]_pin[0][0][4] -+ grid[1][0]_pin[0][0][6] -+ grid[1][0]_pin[0][0][8] -+ grid[1][0]_pin[0][0][10] -+ grid[1][0]_pin[0][0][12] -+ grid[1][0]_pin[0][0][14] -+ svdd sgnd -Xmux_2level_tapbuf_size16[0] chanx[1][0]_midout[0] chanx[1][0]_midout[1] chanx[1][0]_midout[12] chanx[1][0]_midout[13] chanx[1][0]_midout[24] chanx[1][0]_midout[25] chanx[1][0]_midout[38] chanx[1][0]_midout[39] chanx[1][0]_midout[50] chanx[1][0]_midout[51] chanx[1][0]_midout[62] chanx[1][0]_midout[63] chanx[1][0]_midout[74] chanx[1][0]_midout[75] chanx[1][0]_midout[88] chanx[1][0]_midout[89] grid[1][1]_pin[0][2][2] sram[2082]->outb sram[2082]->out sram[2083]->out sram[2083]->outb sram[2084]->out sram[2084]->outb sram[2085]->out sram[2085]->outb sram[2086]->outb sram[2086]->out sram[2087]->out sram[2087]->outb sram[2088]->out sram[2088]->outb sram[2089]->out sram[2089]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2082] sram->in sram[2082]->out sram[2082]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2082]->out) 0 -.nodeset V(sram[2082]->outb) vsp -Xsram[2083] sram->in sram[2083]->out sram[2083]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2083]->out) 0 -.nodeset V(sram[2083]->outb) vsp -Xsram[2084] sram->in sram[2084]->out sram[2084]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2084]->out) 0 -.nodeset V(sram[2084]->outb) vsp -Xsram[2085] sram->in sram[2085]->out sram[2085]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2085]->out) 0 -.nodeset V(sram[2085]->outb) vsp -Xsram[2086] sram->in sram[2086]->out sram[2086]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2086]->out) 0 -.nodeset V(sram[2086]->outb) vsp -Xsram[2087] sram->in sram[2087]->out sram[2087]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2087]->out) 0 -.nodeset V(sram[2087]->outb) vsp -Xsram[2088] sram->in sram[2088]->out sram[2088]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2088]->out) 0 -.nodeset V(sram[2088]->outb) vsp -Xsram[2089] sram->in sram[2089]->out sram[2089]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2089]->out) 0 -.nodeset V(sram[2089]->outb) vsp -Xmux_2level_tapbuf_size16[1] chanx[1][0]_midout[0] chanx[1][0]_midout[1] chanx[1][0]_midout[14] chanx[1][0]_midout[15] chanx[1][0]_midout[26] chanx[1][0]_midout[27] chanx[1][0]_midout[38] chanx[1][0]_midout[39] chanx[1][0]_midout[50] chanx[1][0]_midout[51] chanx[1][0]_midout[64] chanx[1][0]_midout[65] chanx[1][0]_midout[76] chanx[1][0]_midout[77] chanx[1][0]_midout[88] chanx[1][0]_midout[89] grid[1][1]_pin[0][2][6] sram[2090]->outb sram[2090]->out sram[2091]->out sram[2091]->outb sram[2092]->out sram[2092]->outb sram[2093]->out sram[2093]->outb sram[2094]->outb sram[2094]->out sram[2095]->out sram[2095]->outb sram[2096]->out sram[2096]->outb sram[2097]->out sram[2097]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2090] sram->in sram[2090]->out sram[2090]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2090]->out) 0 -.nodeset V(sram[2090]->outb) vsp -Xsram[2091] sram->in sram[2091]->out sram[2091]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2091]->out) 0 -.nodeset V(sram[2091]->outb) vsp -Xsram[2092] sram->in sram[2092]->out sram[2092]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2092]->out) 0 -.nodeset V(sram[2092]->outb) vsp -Xsram[2093] sram->in sram[2093]->out sram[2093]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2093]->out) 0 -.nodeset V(sram[2093]->outb) vsp -Xsram[2094] sram->in sram[2094]->out sram[2094]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2094]->out) 0 -.nodeset V(sram[2094]->outb) vsp -Xsram[2095] sram->in sram[2095]->out sram[2095]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2095]->out) 0 -.nodeset V(sram[2095]->outb) vsp -Xsram[2096] sram->in sram[2096]->out sram[2096]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2096]->out) 0 -.nodeset V(sram[2096]->outb) vsp -Xsram[2097] sram->in sram[2097]->out sram[2097]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2097]->out) 0 -.nodeset V(sram[2097]->outb) vsp -Xmux_2level_tapbuf_size16[2] chanx[1][0]_midout[2] chanx[1][0]_midout[3] chanx[1][0]_midout[14] chanx[1][0]_midout[15] chanx[1][0]_midout[28] chanx[1][0]_midout[29] chanx[1][0]_midout[40] chanx[1][0]_midout[41] chanx[1][0]_midout[52] chanx[1][0]_midout[53] chanx[1][0]_midout[64] chanx[1][0]_midout[65] chanx[1][0]_midout[78] chanx[1][0]_midout[79] chanx[1][0]_midout[90] chanx[1][0]_midout[91] grid[1][1]_pin[0][2][10] sram[2098]->outb sram[2098]->out sram[2099]->out sram[2099]->outb sram[2100]->out sram[2100]->outb sram[2101]->out sram[2101]->outb sram[2102]->outb sram[2102]->out sram[2103]->out sram[2103]->outb sram[2104]->out sram[2104]->outb sram[2105]->out sram[2105]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2098] sram->in sram[2098]->out sram[2098]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2098]->out) 0 -.nodeset V(sram[2098]->outb) vsp -Xsram[2099] sram->in sram[2099]->out sram[2099]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2099]->out) 0 -.nodeset V(sram[2099]->outb) vsp -Xsram[2100] sram->in sram[2100]->out sram[2100]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2100]->out) 0 -.nodeset V(sram[2100]->outb) vsp -Xsram[2101] sram->in sram[2101]->out sram[2101]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2101]->out) 0 -.nodeset V(sram[2101]->outb) vsp -Xsram[2102] sram->in sram[2102]->out sram[2102]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2102]->out) 0 -.nodeset V(sram[2102]->outb) vsp -Xsram[2103] sram->in sram[2103]->out sram[2103]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2103]->out) 0 -.nodeset V(sram[2103]->outb) vsp -Xsram[2104] sram->in sram[2104]->out sram[2104]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2104]->out) 0 -.nodeset V(sram[2104]->outb) vsp -Xsram[2105] sram->in sram[2105]->out sram[2105]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2105]->out) 0 -.nodeset V(sram[2105]->outb) vsp -Xmux_2level_tapbuf_size16[3] chanx[1][0]_midout[4] chanx[1][0]_midout[5] chanx[1][0]_midout[16] chanx[1][0]_midout[17] chanx[1][0]_midout[28] chanx[1][0]_midout[29] chanx[1][0]_midout[40] chanx[1][0]_midout[41] chanx[1][0]_midout[54] chanx[1][0]_midout[55] chanx[1][0]_midout[66] chanx[1][0]_midout[67] chanx[1][0]_midout[78] chanx[1][0]_midout[79] chanx[1][0]_midout[90] chanx[1][0]_midout[91] grid[1][1]_pin[0][2][14] sram[2106]->outb sram[2106]->out sram[2107]->out sram[2107]->outb sram[2108]->out sram[2108]->outb sram[2109]->out sram[2109]->outb sram[2110]->outb sram[2110]->out sram[2111]->out sram[2111]->outb sram[2112]->out sram[2112]->outb sram[2113]->out sram[2113]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2106] sram->in sram[2106]->out sram[2106]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2106]->out) 0 -.nodeset V(sram[2106]->outb) vsp -Xsram[2107] sram->in sram[2107]->out sram[2107]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2107]->out) 0 -.nodeset V(sram[2107]->outb) vsp -Xsram[2108] sram->in sram[2108]->out sram[2108]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2108]->out) 0 -.nodeset V(sram[2108]->outb) vsp -Xsram[2109] sram->in sram[2109]->out sram[2109]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2109]->out) 0 -.nodeset V(sram[2109]->outb) vsp -Xsram[2110] sram->in sram[2110]->out sram[2110]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2110]->out) 0 -.nodeset V(sram[2110]->outb) vsp -Xsram[2111] sram->in sram[2111]->out sram[2111]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2111]->out) 0 -.nodeset V(sram[2111]->outb) vsp -Xsram[2112] sram->in sram[2112]->out sram[2112]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2112]->out) 0 -.nodeset V(sram[2112]->outb) vsp -Xsram[2113] sram->in sram[2113]->out sram[2113]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2113]->out) 0 -.nodeset V(sram[2113]->outb) vsp -Xmux_2level_tapbuf_size16[4] chanx[1][0]_midout[4] chanx[1][0]_midout[5] chanx[1][0]_midout[18] chanx[1][0]_midout[19] chanx[1][0]_midout[30] chanx[1][0]_midout[31] chanx[1][0]_midout[42] chanx[1][0]_midout[43] chanx[1][0]_midout[54] chanx[1][0]_midout[55] chanx[1][0]_midout[68] chanx[1][0]_midout[69] chanx[1][0]_midout[80] chanx[1][0]_midout[81] chanx[1][0]_midout[92] chanx[1][0]_midout[93] grid[1][1]_pin[0][2][18] sram[2114]->outb sram[2114]->out sram[2115]->out sram[2115]->outb sram[2116]->out sram[2116]->outb sram[2117]->out sram[2117]->outb sram[2118]->outb sram[2118]->out sram[2119]->out sram[2119]->outb sram[2120]->out sram[2120]->outb sram[2121]->out sram[2121]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2114] sram->in sram[2114]->out sram[2114]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2114]->out) 0 -.nodeset V(sram[2114]->outb) vsp -Xsram[2115] sram->in sram[2115]->out sram[2115]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2115]->out) 0 -.nodeset V(sram[2115]->outb) vsp -Xsram[2116] sram->in sram[2116]->out sram[2116]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2116]->out) 0 -.nodeset V(sram[2116]->outb) vsp -Xsram[2117] sram->in sram[2117]->out sram[2117]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2117]->out) 0 -.nodeset V(sram[2117]->outb) vsp -Xsram[2118] sram->in sram[2118]->out sram[2118]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2118]->out) 0 -.nodeset V(sram[2118]->outb) vsp -Xsram[2119] sram->in sram[2119]->out sram[2119]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2119]->out) 0 -.nodeset V(sram[2119]->outb) vsp -Xsram[2120] sram->in sram[2120]->out sram[2120]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2120]->out) 0 -.nodeset V(sram[2120]->outb) vsp -Xsram[2121] sram->in sram[2121]->out sram[2121]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2121]->out) 0 -.nodeset V(sram[2121]->outb) vsp -Xmux_2level_tapbuf_size16[5] chanx[1][0]_midout[6] chanx[1][0]_midout[7] chanx[1][0]_midout[18] chanx[1][0]_midout[19] chanx[1][0]_midout[30] chanx[1][0]_midout[31] chanx[1][0]_midout[44] chanx[1][0]_midout[45] chanx[1][0]_midout[56] chanx[1][0]_midout[57] chanx[1][0]_midout[68] chanx[1][0]_midout[69] chanx[1][0]_midout[80] chanx[1][0]_midout[81] chanx[1][0]_midout[94] chanx[1][0]_midout[95] grid[1][1]_pin[0][2][22] sram[2122]->outb sram[2122]->out sram[2123]->out sram[2123]->outb sram[2124]->out sram[2124]->outb sram[2125]->out sram[2125]->outb sram[2126]->out sram[2126]->outb sram[2127]->out sram[2127]->outb sram[2128]->out sram[2128]->outb sram[2129]->outb sram[2129]->out svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[5], level=2, select_path_id=3. ***** -*****10000001***** -Xsram[2122] sram->in sram[2122]->out sram[2122]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2122]->out) 0 -.nodeset V(sram[2122]->outb) vsp -Xsram[2123] sram->in sram[2123]->out sram[2123]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2123]->out) 0 -.nodeset V(sram[2123]->outb) vsp -Xsram[2124] sram->in sram[2124]->out sram[2124]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2124]->out) 0 -.nodeset V(sram[2124]->outb) vsp -Xsram[2125] sram->in sram[2125]->out sram[2125]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2125]->out) 0 -.nodeset V(sram[2125]->outb) vsp -Xsram[2126] sram->in sram[2126]->out sram[2126]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2126]->out) 0 -.nodeset V(sram[2126]->outb) vsp -Xsram[2127] sram->in sram[2127]->out sram[2127]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2127]->out) 0 -.nodeset V(sram[2127]->outb) vsp -Xsram[2128] sram->in sram[2128]->out sram[2128]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2128]->out) 0 -.nodeset V(sram[2128]->outb) vsp -Xsram[2129] sram->in sram[2129]->out sram[2129]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2129]->out) 0 -.nodeset V(sram[2129]->outb) vsp -Xmux_2level_tapbuf_size16[6] chanx[1][0]_midout[8] chanx[1][0]_midout[9] chanx[1][0]_midout[20] chanx[1][0]_midout[21] chanx[1][0]_midout[32] chanx[1][0]_midout[33] chanx[1][0]_midout[44] chanx[1][0]_midout[45] chanx[1][0]_midout[58] chanx[1][0]_midout[59] chanx[1][0]_midout[70] chanx[1][0]_midout[71] chanx[1][0]_midout[82] chanx[1][0]_midout[83] chanx[1][0]_midout[94] chanx[1][0]_midout[95] grid[1][1]_pin[0][2][26] sram[2130]->outb sram[2130]->out sram[2131]->out sram[2131]->outb sram[2132]->out sram[2132]->outb sram[2133]->out sram[2133]->outb sram[2134]->outb sram[2134]->out sram[2135]->out sram[2135]->outb sram[2136]->out sram[2136]->outb sram[2137]->out sram[2137]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2130] sram->in sram[2130]->out sram[2130]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2130]->out) 0 -.nodeset V(sram[2130]->outb) vsp -Xsram[2131] sram->in sram[2131]->out sram[2131]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2131]->out) 0 -.nodeset V(sram[2131]->outb) vsp -Xsram[2132] sram->in sram[2132]->out sram[2132]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2132]->out) 0 -.nodeset V(sram[2132]->outb) vsp -Xsram[2133] sram->in sram[2133]->out sram[2133]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2133]->out) 0 -.nodeset V(sram[2133]->outb) vsp -Xsram[2134] sram->in sram[2134]->out sram[2134]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2134]->out) 0 -.nodeset V(sram[2134]->outb) vsp -Xsram[2135] sram->in sram[2135]->out sram[2135]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2135]->out) 0 -.nodeset V(sram[2135]->outb) vsp -Xsram[2136] sram->in sram[2136]->out sram[2136]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2136]->out) 0 -.nodeset V(sram[2136]->outb) vsp -Xsram[2137] sram->in sram[2137]->out sram[2137]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2137]->out) 0 -.nodeset V(sram[2137]->outb) vsp -Xmux_2level_tapbuf_size16[7] chanx[1][0]_midout[8] chanx[1][0]_midout[9] chanx[1][0]_midout[20] chanx[1][0]_midout[21] chanx[1][0]_midout[34] chanx[1][0]_midout[35] chanx[1][0]_midout[46] chanx[1][0]_midout[47] chanx[1][0]_midout[58] chanx[1][0]_midout[59] chanx[1][0]_midout[70] chanx[1][0]_midout[71] chanx[1][0]_midout[84] chanx[1][0]_midout[85] chanx[1][0]_midout[96] chanx[1][0]_midout[97] grid[1][1]_pin[0][2][30] sram[2138]->outb sram[2138]->out sram[2139]->out sram[2139]->outb sram[2140]->out sram[2140]->outb sram[2141]->out sram[2141]->outb sram[2142]->outb sram[2142]->out sram[2143]->out sram[2143]->outb sram[2144]->out sram[2144]->outb sram[2145]->out sram[2145]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2138] sram->in sram[2138]->out sram[2138]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2138]->out) 0 -.nodeset V(sram[2138]->outb) vsp -Xsram[2139] sram->in sram[2139]->out sram[2139]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2139]->out) 0 -.nodeset V(sram[2139]->outb) vsp -Xsram[2140] sram->in sram[2140]->out sram[2140]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2140]->out) 0 -.nodeset V(sram[2140]->outb) vsp -Xsram[2141] sram->in sram[2141]->out sram[2141]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2141]->out) 0 -.nodeset V(sram[2141]->outb) vsp -Xsram[2142] sram->in sram[2142]->out sram[2142]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2142]->out) 0 -.nodeset V(sram[2142]->outb) vsp -Xsram[2143] sram->in sram[2143]->out sram[2143]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2143]->out) 0 -.nodeset V(sram[2143]->outb) vsp -Xsram[2144] sram->in sram[2144]->out sram[2144]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2144]->out) 0 -.nodeset V(sram[2144]->outb) vsp -Xsram[2145] sram->in sram[2145]->out sram[2145]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2145]->out) 0 -.nodeset V(sram[2145]->outb) vsp -Xmux_2level_tapbuf_size16[8] chanx[1][0]_midout[10] chanx[1][0]_midout[11] chanx[1][0]_midout[22] chanx[1][0]_midout[23] chanx[1][0]_midout[34] chanx[1][0]_midout[35] chanx[1][0]_midout[48] chanx[1][0]_midout[49] chanx[1][0]_midout[60] chanx[1][0]_midout[61] chanx[1][0]_midout[72] chanx[1][0]_midout[73] chanx[1][0]_midout[84] chanx[1][0]_midout[85] chanx[1][0]_midout[98] chanx[1][0]_midout[99] grid[1][1]_pin[0][2][34] sram[2146]->outb sram[2146]->out sram[2147]->out sram[2147]->outb sram[2148]->out sram[2148]->outb sram[2149]->out sram[2149]->outb sram[2150]->outb sram[2150]->out sram[2151]->out sram[2151]->outb sram[2152]->out sram[2152]->outb sram[2153]->out sram[2153]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2146] sram->in sram[2146]->out sram[2146]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2146]->out) 0 -.nodeset V(sram[2146]->outb) vsp -Xsram[2147] sram->in sram[2147]->out sram[2147]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2147]->out) 0 -.nodeset V(sram[2147]->outb) vsp -Xsram[2148] sram->in sram[2148]->out sram[2148]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2148]->out) 0 -.nodeset V(sram[2148]->outb) vsp -Xsram[2149] sram->in sram[2149]->out sram[2149]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2149]->out) 0 -.nodeset V(sram[2149]->outb) vsp -Xsram[2150] sram->in sram[2150]->out sram[2150]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2150]->out) 0 -.nodeset V(sram[2150]->outb) vsp -Xsram[2151] sram->in sram[2151]->out sram[2151]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2151]->out) 0 -.nodeset V(sram[2151]->outb) vsp -Xsram[2152] sram->in sram[2152]->out sram[2152]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2152]->out) 0 -.nodeset V(sram[2152]->outb) vsp -Xsram[2153] sram->in sram[2153]->out sram[2153]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2153]->out) 0 -.nodeset V(sram[2153]->outb) vsp -Xmux_2level_tapbuf_size16[9] chanx[1][0]_midout[10] chanx[1][0]_midout[11] chanx[1][0]_midout[24] chanx[1][0]_midout[25] chanx[1][0]_midout[36] chanx[1][0]_midout[37] chanx[1][0]_midout[48] chanx[1][0]_midout[49] chanx[1][0]_midout[60] chanx[1][0]_midout[61] chanx[1][0]_midout[74] chanx[1][0]_midout[75] chanx[1][0]_midout[86] chanx[1][0]_midout[87] chanx[1][0]_midout[98] chanx[1][0]_midout[99] grid[1][1]_pin[0][2][38] sram[2154]->outb sram[2154]->out sram[2155]->out sram[2155]->outb sram[2156]->out sram[2156]->outb sram[2157]->out sram[2157]->outb sram[2158]->outb sram[2158]->out sram[2159]->out sram[2159]->outb sram[2160]->out sram[2160]->outb sram[2161]->out sram[2161]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[9], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2154] sram->in sram[2154]->out sram[2154]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2154]->out) 0 -.nodeset V(sram[2154]->outb) vsp -Xsram[2155] sram->in sram[2155]->out sram[2155]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2155]->out) 0 -.nodeset V(sram[2155]->outb) vsp -Xsram[2156] sram->in sram[2156]->out sram[2156]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2156]->out) 0 -.nodeset V(sram[2156]->outb) vsp -Xsram[2157] sram->in sram[2157]->out sram[2157]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2157]->out) 0 -.nodeset V(sram[2157]->outb) vsp -Xsram[2158] sram->in sram[2158]->out sram[2158]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2158]->out) 0 -.nodeset V(sram[2158]->outb) vsp -Xsram[2159] sram->in sram[2159]->out sram[2159]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2159]->out) 0 -.nodeset V(sram[2159]->outb) vsp -Xsram[2160] sram->in sram[2160]->out sram[2160]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2160]->out) 0 -.nodeset V(sram[2160]->outb) vsp -Xsram[2161] sram->in sram[2161]->out sram[2161]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2161]->out) 0 -.nodeset V(sram[2161]->outb) vsp -Xmux_2level_tapbuf_size16[10] chanx[1][0]_midout[0] chanx[1][0]_midout[1] chanx[1][0]_midout[12] chanx[1][0]_midout[13] chanx[1][0]_midout[24] chanx[1][0]_midout[25] chanx[1][0]_midout[36] chanx[1][0]_midout[37] chanx[1][0]_midout[50] chanx[1][0]_midout[51] chanx[1][0]_midout[62] chanx[1][0]_midout[63] chanx[1][0]_midout[74] chanx[1][0]_midout[75] chanx[1][0]_midout[86] chanx[1][0]_midout[87] grid[1][0]_pin[0][0][0] sram[2162]->outb sram[2162]->out sram[2163]->out sram[2163]->outb sram[2164]->out sram[2164]->outb sram[2165]->out sram[2165]->outb sram[2166]->outb sram[2166]->out sram[2167]->out sram[2167]->outb sram[2168]->out sram[2168]->outb sram[2169]->out sram[2169]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[10], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2162] sram->in sram[2162]->out sram[2162]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2162]->out) 0 -.nodeset V(sram[2162]->outb) vsp -Xsram[2163] sram->in sram[2163]->out sram[2163]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2163]->out) 0 -.nodeset V(sram[2163]->outb) vsp -Xsram[2164] sram->in sram[2164]->out sram[2164]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2164]->out) 0 -.nodeset V(sram[2164]->outb) vsp -Xsram[2165] sram->in sram[2165]->out sram[2165]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2165]->out) 0 -.nodeset V(sram[2165]->outb) vsp -Xsram[2166] sram->in sram[2166]->out sram[2166]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2166]->out) 0 -.nodeset V(sram[2166]->outb) vsp -Xsram[2167] sram->in sram[2167]->out sram[2167]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2167]->out) 0 -.nodeset V(sram[2167]->outb) vsp -Xsram[2168] sram->in sram[2168]->out sram[2168]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2168]->out) 0 -.nodeset V(sram[2168]->outb) vsp -Xsram[2169] sram->in sram[2169]->out sram[2169]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2169]->out) 0 -.nodeset V(sram[2169]->outb) vsp -Xmux_2level_tapbuf_size16[11] chanx[1][0]_midout[0] chanx[1][0]_midout[1] chanx[1][0]_midout[14] chanx[1][0]_midout[15] chanx[1][0]_midout[26] chanx[1][0]_midout[27] chanx[1][0]_midout[38] chanx[1][0]_midout[39] chanx[1][0]_midout[50] chanx[1][0]_midout[51] chanx[1][0]_midout[64] chanx[1][0]_midout[65] chanx[1][0]_midout[76] chanx[1][0]_midout[77] chanx[1][0]_midout[88] chanx[1][0]_midout[89] grid[1][0]_pin[0][0][2] sram[2170]->outb sram[2170]->out sram[2171]->out sram[2171]->outb sram[2172]->out sram[2172]->outb sram[2173]->out sram[2173]->outb sram[2174]->outb sram[2174]->out sram[2175]->out sram[2175]->outb sram[2176]->out sram[2176]->outb sram[2177]->out sram[2177]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[11], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2170] sram->in sram[2170]->out sram[2170]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2170]->out) 0 -.nodeset V(sram[2170]->outb) vsp -Xsram[2171] sram->in sram[2171]->out sram[2171]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2171]->out) 0 -.nodeset V(sram[2171]->outb) vsp -Xsram[2172] sram->in sram[2172]->out sram[2172]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2172]->out) 0 -.nodeset V(sram[2172]->outb) vsp -Xsram[2173] sram->in sram[2173]->out sram[2173]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2173]->out) 0 -.nodeset V(sram[2173]->outb) vsp -Xsram[2174] sram->in sram[2174]->out sram[2174]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2174]->out) 0 -.nodeset V(sram[2174]->outb) vsp -Xsram[2175] sram->in sram[2175]->out sram[2175]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2175]->out) 0 -.nodeset V(sram[2175]->outb) vsp -Xsram[2176] sram->in sram[2176]->out sram[2176]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2176]->out) 0 -.nodeset V(sram[2176]->outb) vsp -Xsram[2177] sram->in sram[2177]->out sram[2177]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2177]->out) 0 -.nodeset V(sram[2177]->outb) vsp -Xmux_2level_tapbuf_size16[12] chanx[1][0]_midout[2] chanx[1][0]_midout[3] chanx[1][0]_midout[14] chanx[1][0]_midout[15] chanx[1][0]_midout[28] chanx[1][0]_midout[29] chanx[1][0]_midout[40] chanx[1][0]_midout[41] chanx[1][0]_midout[52] chanx[1][0]_midout[53] chanx[1][0]_midout[64] chanx[1][0]_midout[65] chanx[1][0]_midout[78] chanx[1][0]_midout[79] chanx[1][0]_midout[90] chanx[1][0]_midout[91] grid[1][0]_pin[0][0][4] sram[2178]->outb sram[2178]->out sram[2179]->out sram[2179]->outb sram[2180]->out sram[2180]->outb sram[2181]->out sram[2181]->outb sram[2182]->outb sram[2182]->out sram[2183]->out sram[2183]->outb sram[2184]->out sram[2184]->outb sram[2185]->out sram[2185]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[12], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2178] sram->in sram[2178]->out sram[2178]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2178]->out) 0 -.nodeset V(sram[2178]->outb) vsp -Xsram[2179] sram->in sram[2179]->out sram[2179]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2179]->out) 0 -.nodeset V(sram[2179]->outb) vsp -Xsram[2180] sram->in sram[2180]->out sram[2180]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2180]->out) 0 -.nodeset V(sram[2180]->outb) vsp -Xsram[2181] sram->in sram[2181]->out sram[2181]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2181]->out) 0 -.nodeset V(sram[2181]->outb) vsp -Xsram[2182] sram->in sram[2182]->out sram[2182]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2182]->out) 0 -.nodeset V(sram[2182]->outb) vsp -Xsram[2183] sram->in sram[2183]->out sram[2183]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2183]->out) 0 -.nodeset V(sram[2183]->outb) vsp -Xsram[2184] sram->in sram[2184]->out sram[2184]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2184]->out) 0 -.nodeset V(sram[2184]->outb) vsp -Xsram[2185] sram->in sram[2185]->out sram[2185]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2185]->out) 0 -.nodeset V(sram[2185]->outb) vsp -Xmux_2level_tapbuf_size16[13] chanx[1][0]_midout[4] chanx[1][0]_midout[5] chanx[1][0]_midout[16] chanx[1][0]_midout[17] chanx[1][0]_midout[28] chanx[1][0]_midout[29] chanx[1][0]_midout[42] chanx[1][0]_midout[43] chanx[1][0]_midout[54] chanx[1][0]_midout[55] chanx[1][0]_midout[66] chanx[1][0]_midout[67] chanx[1][0]_midout[78] chanx[1][0]_midout[79] chanx[1][0]_midout[92] chanx[1][0]_midout[93] grid[1][0]_pin[0][0][6] sram[2186]->outb sram[2186]->out sram[2187]->out sram[2187]->outb sram[2188]->out sram[2188]->outb sram[2189]->out sram[2189]->outb sram[2190]->outb sram[2190]->out sram[2191]->out sram[2191]->outb sram[2192]->out sram[2192]->outb sram[2193]->out sram[2193]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[13], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2186] sram->in sram[2186]->out sram[2186]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2186]->out) 0 -.nodeset V(sram[2186]->outb) vsp -Xsram[2187] sram->in sram[2187]->out sram[2187]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2187]->out) 0 -.nodeset V(sram[2187]->outb) vsp -Xsram[2188] sram->in sram[2188]->out sram[2188]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2188]->out) 0 -.nodeset V(sram[2188]->outb) vsp -Xsram[2189] sram->in sram[2189]->out sram[2189]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2189]->out) 0 -.nodeset V(sram[2189]->outb) vsp -Xsram[2190] sram->in sram[2190]->out sram[2190]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2190]->out) 0 -.nodeset V(sram[2190]->outb) vsp -Xsram[2191] sram->in sram[2191]->out sram[2191]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2191]->out) 0 -.nodeset V(sram[2191]->outb) vsp -Xsram[2192] sram->in sram[2192]->out sram[2192]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2192]->out) 0 -.nodeset V(sram[2192]->outb) vsp -Xsram[2193] sram->in sram[2193]->out sram[2193]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2193]->out) 0 -.nodeset V(sram[2193]->outb) vsp -Xmux_2level_tapbuf_size16[14] chanx[1][0]_midout[6] chanx[1][0]_midout[7] chanx[1][0]_midout[18] chanx[1][0]_midout[19] chanx[1][0]_midout[30] chanx[1][0]_midout[31] chanx[1][0]_midout[42] chanx[1][0]_midout[43] chanx[1][0]_midout[56] chanx[1][0]_midout[57] chanx[1][0]_midout[68] chanx[1][0]_midout[69] chanx[1][0]_midout[80] chanx[1][0]_midout[81] chanx[1][0]_midout[92] chanx[1][0]_midout[93] grid[1][0]_pin[0][0][8] sram[2194]->outb sram[2194]->out sram[2195]->out sram[2195]->outb sram[2196]->out sram[2196]->outb sram[2197]->out sram[2197]->outb sram[2198]->outb sram[2198]->out sram[2199]->out sram[2199]->outb sram[2200]->out sram[2200]->outb sram[2201]->out sram[2201]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[14], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2194] sram->in sram[2194]->out sram[2194]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2194]->out) 0 -.nodeset V(sram[2194]->outb) vsp -Xsram[2195] sram->in sram[2195]->out sram[2195]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2195]->out) 0 -.nodeset V(sram[2195]->outb) vsp -Xsram[2196] sram->in sram[2196]->out sram[2196]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2196]->out) 0 -.nodeset V(sram[2196]->outb) vsp -Xsram[2197] sram->in sram[2197]->out sram[2197]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2197]->out) 0 -.nodeset V(sram[2197]->outb) vsp -Xsram[2198] sram->in sram[2198]->out sram[2198]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2198]->out) 0 -.nodeset V(sram[2198]->outb) vsp -Xsram[2199] sram->in sram[2199]->out sram[2199]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2199]->out) 0 -.nodeset V(sram[2199]->outb) vsp -Xsram[2200] sram->in sram[2200]->out sram[2200]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2200]->out) 0 -.nodeset V(sram[2200]->outb) vsp -Xsram[2201] sram->in sram[2201]->out sram[2201]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2201]->out) 0 -.nodeset V(sram[2201]->outb) vsp -Xmux_2level_tapbuf_size16[15] chanx[1][0]_midout[6] chanx[1][0]_midout[7] chanx[1][0]_midout[20] chanx[1][0]_midout[21] chanx[1][0]_midout[32] chanx[1][0]_midout[33] chanx[1][0]_midout[44] chanx[1][0]_midout[45] chanx[1][0]_midout[56] chanx[1][0]_midout[57] chanx[1][0]_midout[70] chanx[1][0]_midout[71] chanx[1][0]_midout[82] chanx[1][0]_midout[83] chanx[1][0]_midout[94] chanx[1][0]_midout[95] grid[1][0]_pin[0][0][10] sram[2202]->outb sram[2202]->out sram[2203]->out sram[2203]->outb sram[2204]->out sram[2204]->outb sram[2205]->out sram[2205]->outb sram[2206]->outb sram[2206]->out sram[2207]->out sram[2207]->outb sram[2208]->out sram[2208]->outb sram[2209]->out sram[2209]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[15], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2202] sram->in sram[2202]->out sram[2202]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2202]->out) 0 -.nodeset V(sram[2202]->outb) vsp -Xsram[2203] sram->in sram[2203]->out sram[2203]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2203]->out) 0 -.nodeset V(sram[2203]->outb) vsp -Xsram[2204] sram->in sram[2204]->out sram[2204]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2204]->out) 0 -.nodeset V(sram[2204]->outb) vsp -Xsram[2205] sram->in sram[2205]->out sram[2205]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2205]->out) 0 -.nodeset V(sram[2205]->outb) vsp -Xsram[2206] sram->in sram[2206]->out sram[2206]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2206]->out) 0 -.nodeset V(sram[2206]->outb) vsp -Xsram[2207] sram->in sram[2207]->out sram[2207]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2207]->out) 0 -.nodeset V(sram[2207]->outb) vsp -Xsram[2208] sram->in sram[2208]->out sram[2208]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2208]->out) 0 -.nodeset V(sram[2208]->outb) vsp -Xsram[2209] sram->in sram[2209]->out sram[2209]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2209]->out) 0 -.nodeset V(sram[2209]->outb) vsp -Xmux_2level_tapbuf_size16[16] chanx[1][0]_midout[8] chanx[1][0]_midout[9] chanx[1][0]_midout[20] chanx[1][0]_midout[21] chanx[1][0]_midout[34] chanx[1][0]_midout[35] chanx[1][0]_midout[46] chanx[1][0]_midout[47] chanx[1][0]_midout[58] chanx[1][0]_midout[59] chanx[1][0]_midout[70] chanx[1][0]_midout[71] chanx[1][0]_midout[84] chanx[1][0]_midout[85] chanx[1][0]_midout[96] chanx[1][0]_midout[97] grid[1][0]_pin[0][0][12] sram[2210]->outb sram[2210]->out sram[2211]->out sram[2211]->outb sram[2212]->out sram[2212]->outb sram[2213]->out sram[2213]->outb sram[2214]->outb sram[2214]->out sram[2215]->out sram[2215]->outb sram[2216]->out sram[2216]->outb sram[2217]->out sram[2217]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[16], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2210] sram->in sram[2210]->out sram[2210]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2210]->out) 0 -.nodeset V(sram[2210]->outb) vsp -Xsram[2211] sram->in sram[2211]->out sram[2211]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2211]->out) 0 -.nodeset V(sram[2211]->outb) vsp -Xsram[2212] sram->in sram[2212]->out sram[2212]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2212]->out) 0 -.nodeset V(sram[2212]->outb) vsp -Xsram[2213] sram->in sram[2213]->out sram[2213]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2213]->out) 0 -.nodeset V(sram[2213]->outb) vsp -Xsram[2214] sram->in sram[2214]->out sram[2214]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2214]->out) 0 -.nodeset V(sram[2214]->outb) vsp -Xsram[2215] sram->in sram[2215]->out sram[2215]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2215]->out) 0 -.nodeset V(sram[2215]->outb) vsp -Xsram[2216] sram->in sram[2216]->out sram[2216]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2216]->out) 0 -.nodeset V(sram[2216]->outb) vsp -Xsram[2217] sram->in sram[2217]->out sram[2217]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2217]->out) 0 -.nodeset V(sram[2217]->outb) vsp -Xmux_2level_tapbuf_size16[17] chanx[1][0]_midout[10] chanx[1][0]_midout[11] chanx[1][0]_midout[22] chanx[1][0]_midout[23] chanx[1][0]_midout[34] chanx[1][0]_midout[35] chanx[1][0]_midout[48] chanx[1][0]_midout[49] chanx[1][0]_midout[60] chanx[1][0]_midout[61] chanx[1][0]_midout[72] chanx[1][0]_midout[73] chanx[1][0]_midout[84] chanx[1][0]_midout[85] chanx[1][0]_midout[98] chanx[1][0]_midout[99] grid[1][0]_pin[0][0][14] sram[2218]->outb sram[2218]->out sram[2219]->out sram[2219]->outb sram[2220]->out sram[2220]->outb sram[2221]->out sram[2221]->outb sram[2222]->outb sram[2222]->out sram[2223]->out sram[2223]->outb sram[2224]->out sram[2224]->outb sram[2225]->out sram[2225]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[17], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2218] sram->in sram[2218]->out sram[2218]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2218]->out) 0 -.nodeset V(sram[2218]->outb) vsp -Xsram[2219] sram->in sram[2219]->out sram[2219]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2219]->out) 0 -.nodeset V(sram[2219]->outb) vsp -Xsram[2220] sram->in sram[2220]->out sram[2220]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2220]->out) 0 -.nodeset V(sram[2220]->outb) vsp -Xsram[2221] sram->in sram[2221]->out sram[2221]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2221]->out) 0 -.nodeset V(sram[2221]->outb) vsp -Xsram[2222] sram->in sram[2222]->out sram[2222]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2222]->out) 0 -.nodeset V(sram[2222]->outb) vsp -Xsram[2223] sram->in sram[2223]->out sram[2223]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2223]->out) 0 -.nodeset V(sram[2223]->outb) vsp -Xsram[2224] sram->in sram[2224]->out sram[2224]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2224]->out) 0 -.nodeset V(sram[2224]->outb) vsp -Xsram[2225] sram->in sram[2225]->out sram[2225]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2225]->out) 0 -.nodeset V(sram[2225]->outb) vsp -.eom diff --git a/examples/spice_test_example_2/subckt/cbx_1_1.sp b/examples/spice_test_example_2/subckt/cbx_1_1.sp deleted file mode 100644 index 83661b7a5..000000000 --- a/examples/spice_test_example_2/subckt/cbx_1_1.sp +++ /dev/null @@ -1,615 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Connection Block X-channel [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -.subckt cbx[1][1] -+ chanx[1][1]_midout[0] -+ chanx[1][1]_midout[1] -+ chanx[1][1]_midout[2] -+ chanx[1][1]_midout[3] -+ chanx[1][1]_midout[4] -+ chanx[1][1]_midout[5] -+ chanx[1][1]_midout[6] -+ chanx[1][1]_midout[7] -+ chanx[1][1]_midout[8] -+ chanx[1][1]_midout[9] -+ chanx[1][1]_midout[10] -+ chanx[1][1]_midout[11] -+ chanx[1][1]_midout[12] -+ chanx[1][1]_midout[13] -+ chanx[1][1]_midout[14] -+ chanx[1][1]_midout[15] -+ chanx[1][1]_midout[16] -+ chanx[1][1]_midout[17] -+ chanx[1][1]_midout[18] -+ chanx[1][1]_midout[19] -+ chanx[1][1]_midout[20] -+ chanx[1][1]_midout[21] -+ chanx[1][1]_midout[22] -+ chanx[1][1]_midout[23] -+ chanx[1][1]_midout[24] -+ chanx[1][1]_midout[25] -+ chanx[1][1]_midout[26] -+ chanx[1][1]_midout[27] -+ chanx[1][1]_midout[28] -+ chanx[1][1]_midout[29] -+ chanx[1][1]_midout[30] -+ chanx[1][1]_midout[31] -+ chanx[1][1]_midout[32] -+ chanx[1][1]_midout[33] -+ chanx[1][1]_midout[34] -+ chanx[1][1]_midout[35] -+ chanx[1][1]_midout[36] -+ chanx[1][1]_midout[37] -+ chanx[1][1]_midout[38] -+ chanx[1][1]_midout[39] -+ chanx[1][1]_midout[40] -+ chanx[1][1]_midout[41] -+ chanx[1][1]_midout[42] -+ chanx[1][1]_midout[43] -+ chanx[1][1]_midout[44] -+ chanx[1][1]_midout[45] -+ chanx[1][1]_midout[46] -+ chanx[1][1]_midout[47] -+ chanx[1][1]_midout[48] -+ chanx[1][1]_midout[49] -+ chanx[1][1]_midout[50] -+ chanx[1][1]_midout[51] -+ chanx[1][1]_midout[52] -+ chanx[1][1]_midout[53] -+ chanx[1][1]_midout[54] -+ chanx[1][1]_midout[55] -+ chanx[1][1]_midout[56] -+ chanx[1][1]_midout[57] -+ chanx[1][1]_midout[58] -+ chanx[1][1]_midout[59] -+ chanx[1][1]_midout[60] -+ chanx[1][1]_midout[61] -+ chanx[1][1]_midout[62] -+ chanx[1][1]_midout[63] -+ chanx[1][1]_midout[64] -+ chanx[1][1]_midout[65] -+ chanx[1][1]_midout[66] -+ chanx[1][1]_midout[67] -+ chanx[1][1]_midout[68] -+ chanx[1][1]_midout[69] -+ chanx[1][1]_midout[70] -+ chanx[1][1]_midout[71] -+ chanx[1][1]_midout[72] -+ chanx[1][1]_midout[73] -+ chanx[1][1]_midout[74] -+ chanx[1][1]_midout[75] -+ chanx[1][1]_midout[76] -+ chanx[1][1]_midout[77] -+ chanx[1][1]_midout[78] -+ chanx[1][1]_midout[79] -+ chanx[1][1]_midout[80] -+ chanx[1][1]_midout[81] -+ chanx[1][1]_midout[82] -+ chanx[1][1]_midout[83] -+ chanx[1][1]_midout[84] -+ chanx[1][1]_midout[85] -+ chanx[1][1]_midout[86] -+ chanx[1][1]_midout[87] -+ chanx[1][1]_midout[88] -+ chanx[1][1]_midout[89] -+ chanx[1][1]_midout[90] -+ chanx[1][1]_midout[91] -+ chanx[1][1]_midout[92] -+ chanx[1][1]_midout[93] -+ chanx[1][1]_midout[94] -+ chanx[1][1]_midout[95] -+ chanx[1][1]_midout[96] -+ chanx[1][1]_midout[97] -+ chanx[1][1]_midout[98] -+ chanx[1][1]_midout[99] -+ grid[1][2]_pin[0][2][0] -+ grid[1][2]_pin[0][2][2] -+ grid[1][2]_pin[0][2][4] -+ grid[1][2]_pin[0][2][6] -+ grid[1][2]_pin[0][2][8] -+ grid[1][2]_pin[0][2][10] -+ grid[1][2]_pin[0][2][12] -+ grid[1][2]_pin[0][2][14] -+ grid[1][1]_pin[0][0][0] -+ grid[1][1]_pin[0][0][4] -+ grid[1][1]_pin[0][0][8] -+ grid[1][1]_pin[0][0][12] -+ grid[1][1]_pin[0][0][16] -+ grid[1][1]_pin[0][0][20] -+ grid[1][1]_pin[0][0][24] -+ grid[1][1]_pin[0][0][28] -+ grid[1][1]_pin[0][0][32] -+ grid[1][1]_pin[0][0][36] -+ svdd sgnd -Xmux_2level_tapbuf_size16[18] chanx[1][1]_midout[6] chanx[1][1]_midout[7] chanx[1][1]_midout[10] chanx[1][1]_midout[11] chanx[1][1]_midout[30] chanx[1][1]_midout[31] chanx[1][1]_midout[36] chanx[1][1]_midout[37] chanx[1][1]_midout[48] chanx[1][1]_midout[49] chanx[1][1]_midout[60] chanx[1][1]_midout[61] chanx[1][1]_midout[74] chanx[1][1]_midout[75] chanx[1][1]_midout[88] chanx[1][1]_midout[89] grid[1][2]_pin[0][2][0] sram[2226]->outb sram[2226]->out sram[2227]->out sram[2227]->outb sram[2228]->out sram[2228]->outb sram[2229]->out sram[2229]->outb sram[2230]->outb sram[2230]->out sram[2231]->out sram[2231]->outb sram[2232]->out sram[2232]->outb sram[2233]->out sram[2233]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[18], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2226] sram->in sram[2226]->out sram[2226]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2226]->out) 0 -.nodeset V(sram[2226]->outb) vsp -Xsram[2227] sram->in sram[2227]->out sram[2227]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2227]->out) 0 -.nodeset V(sram[2227]->outb) vsp -Xsram[2228] sram->in sram[2228]->out sram[2228]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2228]->out) 0 -.nodeset V(sram[2228]->outb) vsp -Xsram[2229] sram->in sram[2229]->out sram[2229]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2229]->out) 0 -.nodeset V(sram[2229]->outb) vsp -Xsram[2230] sram->in sram[2230]->out sram[2230]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2230]->out) 0 -.nodeset V(sram[2230]->outb) vsp -Xsram[2231] sram->in sram[2231]->out sram[2231]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2231]->out) 0 -.nodeset V(sram[2231]->outb) vsp -Xsram[2232] sram->in sram[2232]->out sram[2232]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2232]->out) 0 -.nodeset V(sram[2232]->outb) vsp -Xsram[2233] sram->in sram[2233]->out sram[2233]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2233]->out) 0 -.nodeset V(sram[2233]->outb) vsp -Xmux_2level_tapbuf_size16[19] chanx[1][1]_midout[0] chanx[1][1]_midout[1] chanx[1][1]_midout[12] chanx[1][1]_midout[13] chanx[1][1]_midout[24] chanx[1][1]_midout[25] chanx[1][1]_midout[36] chanx[1][1]_midout[37] chanx[1][1]_midout[54] chanx[1][1]_midout[55] chanx[1][1]_midout[66] chanx[1][1]_midout[67] chanx[1][1]_midout[76] chanx[1][1]_midout[77] chanx[1][1]_midout[88] chanx[1][1]_midout[89] grid[1][2]_pin[0][2][2] sram[2234]->outb sram[2234]->out sram[2235]->out sram[2235]->outb sram[2236]->out sram[2236]->outb sram[2237]->out sram[2237]->outb sram[2238]->outb sram[2238]->out sram[2239]->out sram[2239]->outb sram[2240]->out sram[2240]->outb sram[2241]->out sram[2241]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[19], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2234] sram->in sram[2234]->out sram[2234]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2234]->out) 0 -.nodeset V(sram[2234]->outb) vsp -Xsram[2235] sram->in sram[2235]->out sram[2235]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2235]->out) 0 -.nodeset V(sram[2235]->outb) vsp -Xsram[2236] sram->in sram[2236]->out sram[2236]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2236]->out) 0 -.nodeset V(sram[2236]->outb) vsp -Xsram[2237] sram->in sram[2237]->out sram[2237]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2237]->out) 0 -.nodeset V(sram[2237]->outb) vsp -Xsram[2238] sram->in sram[2238]->out sram[2238]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2238]->out) 0 -.nodeset V(sram[2238]->outb) vsp -Xsram[2239] sram->in sram[2239]->out sram[2239]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2239]->out) 0 -.nodeset V(sram[2239]->outb) vsp -Xsram[2240] sram->in sram[2240]->out sram[2240]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2240]->out) 0 -.nodeset V(sram[2240]->outb) vsp -Xsram[2241] sram->in sram[2241]->out sram[2241]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2241]->out) 0 -.nodeset V(sram[2241]->outb) vsp -Xmux_2level_tapbuf_size16[20] chanx[1][1]_midout[0] chanx[1][1]_midout[1] chanx[1][1]_midout[22] chanx[1][1]_midout[23] chanx[1][1]_midout[26] chanx[1][1]_midout[27] chanx[1][1]_midout[42] chanx[1][1]_midout[43] chanx[1][1]_midout[54] chanx[1][1]_midout[55] chanx[1][1]_midout[64] chanx[1][1]_midout[65] chanx[1][1]_midout[78] chanx[1][1]_midout[79] chanx[1][1]_midout[90] chanx[1][1]_midout[91] grid[1][2]_pin[0][2][4] sram[2242]->outb sram[2242]->out sram[2243]->out sram[2243]->outb sram[2244]->out sram[2244]->outb sram[2245]->out sram[2245]->outb sram[2246]->outb sram[2246]->out sram[2247]->out sram[2247]->outb sram[2248]->out sram[2248]->outb sram[2249]->out sram[2249]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[20], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2242] sram->in sram[2242]->out sram[2242]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2242]->out) 0 -.nodeset V(sram[2242]->outb) vsp -Xsram[2243] sram->in sram[2243]->out sram[2243]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2243]->out) 0 -.nodeset V(sram[2243]->outb) vsp -Xsram[2244] sram->in sram[2244]->out sram[2244]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2244]->out) 0 -.nodeset V(sram[2244]->outb) vsp -Xsram[2245] sram->in sram[2245]->out sram[2245]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2245]->out) 0 -.nodeset V(sram[2245]->outb) vsp -Xsram[2246] sram->in sram[2246]->out sram[2246]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2246]->out) 0 -.nodeset V(sram[2246]->outb) vsp -Xsram[2247] sram->in sram[2247]->out sram[2247]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2247]->out) 0 -.nodeset V(sram[2247]->outb) vsp -Xsram[2248] sram->in sram[2248]->out sram[2248]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2248]->out) 0 -.nodeset V(sram[2248]->outb) vsp -Xsram[2249] sram->in sram[2249]->out sram[2249]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2249]->out) 0 -.nodeset V(sram[2249]->outb) vsp -Xmux_2level_tapbuf_size16[21] chanx[1][1]_midout[2] chanx[1][1]_midout[3] chanx[1][1]_midout[22] chanx[1][1]_midout[23] chanx[1][1]_midout[28] chanx[1][1]_midout[29] chanx[1][1]_midout[40] chanx[1][1]_midout[41] chanx[1][1]_midout[52] chanx[1][1]_midout[53] chanx[1][1]_midout[64] chanx[1][1]_midout[65] chanx[1][1]_midout[80] chanx[1][1]_midout[81] chanx[1][1]_midout[92] chanx[1][1]_midout[93] grid[1][2]_pin[0][2][6] sram[2250]->outb sram[2250]->out sram[2251]->out sram[2251]->outb sram[2252]->out sram[2252]->outb sram[2253]->out sram[2253]->outb sram[2254]->outb sram[2254]->out sram[2255]->out sram[2255]->outb sram[2256]->out sram[2256]->outb sram[2257]->out sram[2257]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[21], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2250] sram->in sram[2250]->out sram[2250]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2250]->out) 0 -.nodeset V(sram[2250]->outb) vsp -Xsram[2251] sram->in sram[2251]->out sram[2251]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2251]->out) 0 -.nodeset V(sram[2251]->outb) vsp -Xsram[2252] sram->in sram[2252]->out sram[2252]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2252]->out) 0 -.nodeset V(sram[2252]->outb) vsp -Xsram[2253] sram->in sram[2253]->out sram[2253]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2253]->out) 0 -.nodeset V(sram[2253]->outb) vsp -Xsram[2254] sram->in sram[2254]->out sram[2254]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2254]->out) 0 -.nodeset V(sram[2254]->outb) vsp -Xsram[2255] sram->in sram[2255]->out sram[2255]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2255]->out) 0 -.nodeset V(sram[2255]->outb) vsp -Xsram[2256] sram->in sram[2256]->out sram[2256]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2256]->out) 0 -.nodeset V(sram[2256]->outb) vsp -Xsram[2257] sram->in sram[2257]->out sram[2257]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2257]->out) 0 -.nodeset V(sram[2257]->outb) vsp -Xmux_2level_tapbuf_size16[22] chanx[1][1]_midout[4] chanx[1][1]_midout[5] chanx[1][1]_midout[16] chanx[1][1]_midout[17] chanx[1][1]_midout[38] chanx[1][1]_midout[39] chanx[1][1]_midout[46] chanx[1][1]_midout[47] chanx[1][1]_midout[58] chanx[1][1]_midout[59] chanx[1][1]_midout[68] chanx[1][1]_midout[69] chanx[1][1]_midout[82] chanx[1][1]_midout[83] chanx[1][1]_midout[94] chanx[1][1]_midout[95] grid[1][2]_pin[0][2][8] sram[2258]->outb sram[2258]->out sram[2259]->out sram[2259]->outb sram[2260]->out sram[2260]->outb sram[2261]->out sram[2261]->outb sram[2262]->outb sram[2262]->out sram[2263]->out sram[2263]->outb sram[2264]->out sram[2264]->outb sram[2265]->out sram[2265]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[22], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2258] sram->in sram[2258]->out sram[2258]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2258]->out) 0 -.nodeset V(sram[2258]->outb) vsp -Xsram[2259] sram->in sram[2259]->out sram[2259]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2259]->out) 0 -.nodeset V(sram[2259]->outb) vsp -Xsram[2260] sram->in sram[2260]->out sram[2260]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2260]->out) 0 -.nodeset V(sram[2260]->outb) vsp -Xsram[2261] sram->in sram[2261]->out sram[2261]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2261]->out) 0 -.nodeset V(sram[2261]->outb) vsp -Xsram[2262] sram->in sram[2262]->out sram[2262]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2262]->out) 0 -.nodeset V(sram[2262]->outb) vsp -Xsram[2263] sram->in sram[2263]->out sram[2263]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2263]->out) 0 -.nodeset V(sram[2263]->outb) vsp -Xsram[2264] sram->in sram[2264]->out sram[2264]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2264]->out) 0 -.nodeset V(sram[2264]->outb) vsp -Xsram[2265] sram->in sram[2265]->out sram[2265]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2265]->out) 0 -.nodeset V(sram[2265]->outb) vsp -Xmux_2level_tapbuf_size16[23] chanx[1][1]_midout[14] chanx[1][1]_midout[15] chanx[1][1]_midout[18] chanx[1][1]_midout[19] chanx[1][1]_midout[38] chanx[1][1]_midout[39] chanx[1][1]_midout[44] chanx[1][1]_midout[45] chanx[1][1]_midout[56] chanx[1][1]_midout[57] chanx[1][1]_midout[70] chanx[1][1]_midout[71] chanx[1][1]_midout[82] chanx[1][1]_midout[83] chanx[1][1]_midout[96] chanx[1][1]_midout[97] grid[1][2]_pin[0][2][10] sram[2266]->outb sram[2266]->out sram[2267]->out sram[2267]->outb sram[2268]->out sram[2268]->outb sram[2269]->out sram[2269]->outb sram[2270]->outb sram[2270]->out sram[2271]->out sram[2271]->outb sram[2272]->out sram[2272]->outb sram[2273]->out sram[2273]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[23], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2266] sram->in sram[2266]->out sram[2266]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2266]->out) 0 -.nodeset V(sram[2266]->outb) vsp -Xsram[2267] sram->in sram[2267]->out sram[2267]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2267]->out) 0 -.nodeset V(sram[2267]->outb) vsp -Xsram[2268] sram->in sram[2268]->out sram[2268]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2268]->out) 0 -.nodeset V(sram[2268]->outb) vsp -Xsram[2269] sram->in sram[2269]->out sram[2269]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2269]->out) 0 -.nodeset V(sram[2269]->outb) vsp -Xsram[2270] sram->in sram[2270]->out sram[2270]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2270]->out) 0 -.nodeset V(sram[2270]->outb) vsp -Xsram[2271] sram->in sram[2271]->out sram[2271]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2271]->out) 0 -.nodeset V(sram[2271]->outb) vsp -Xsram[2272] sram->in sram[2272]->out sram[2272]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2272]->out) 0 -.nodeset V(sram[2272]->outb) vsp -Xsram[2273] sram->in sram[2273]->out sram[2273]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2273]->out) 0 -.nodeset V(sram[2273]->outb) vsp -Xmux_2level_tapbuf_size16[24] chanx[1][1]_midout[8] chanx[1][1]_midout[9] chanx[1][1]_midout[20] chanx[1][1]_midout[21] chanx[1][1]_midout[32] chanx[1][1]_midout[33] chanx[1][1]_midout[44] chanx[1][1]_midout[45] chanx[1][1]_midout[62] chanx[1][1]_midout[63] chanx[1][1]_midout[72] chanx[1][1]_midout[73] chanx[1][1]_midout[84] chanx[1][1]_midout[85] chanx[1][1]_midout[96] chanx[1][1]_midout[97] grid[1][2]_pin[0][2][12] sram[2274]->outb sram[2274]->out sram[2275]->out sram[2275]->outb sram[2276]->out sram[2276]->outb sram[2277]->out sram[2277]->outb sram[2278]->out sram[2278]->outb sram[2279]->out sram[2279]->outb sram[2280]->outb sram[2280]->out sram[2281]->out sram[2281]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[24], level=2, select_path_id=2. ***** -*****10000010***** -Xsram[2274] sram->in sram[2274]->out sram[2274]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2274]->out) 0 -.nodeset V(sram[2274]->outb) vsp -Xsram[2275] sram->in sram[2275]->out sram[2275]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2275]->out) 0 -.nodeset V(sram[2275]->outb) vsp -Xsram[2276] sram->in sram[2276]->out sram[2276]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2276]->out) 0 -.nodeset V(sram[2276]->outb) vsp -Xsram[2277] sram->in sram[2277]->out sram[2277]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2277]->out) 0 -.nodeset V(sram[2277]->outb) vsp -Xsram[2278] sram->in sram[2278]->out sram[2278]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2278]->out) 0 -.nodeset V(sram[2278]->outb) vsp -Xsram[2279] sram->in sram[2279]->out sram[2279]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2279]->out) 0 -.nodeset V(sram[2279]->outb) vsp -Xsram[2280] sram->in sram[2280]->out sram[2280]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2280]->out) 0 -.nodeset V(sram[2280]->outb) vsp -Xsram[2281] sram->in sram[2281]->out sram[2281]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2281]->out) 0 -.nodeset V(sram[2281]->outb) vsp -Xmux_2level_tapbuf_size16[25] chanx[1][1]_midout[8] chanx[1][1]_midout[9] chanx[1][1]_midout[30] chanx[1][1]_midout[31] chanx[1][1]_midout[34] chanx[1][1]_midout[35] chanx[1][1]_midout[50] chanx[1][1]_midout[51] chanx[1][1]_midout[62] chanx[1][1]_midout[63] chanx[1][1]_midout[74] chanx[1][1]_midout[75] chanx[1][1]_midout[86] chanx[1][1]_midout[87] chanx[1][1]_midout[98] chanx[1][1]_midout[99] grid[1][2]_pin[0][2][14] sram[2282]->outb sram[2282]->out sram[2283]->out sram[2283]->outb sram[2284]->out sram[2284]->outb sram[2285]->out sram[2285]->outb sram[2286]->outb sram[2286]->out sram[2287]->out sram[2287]->outb sram[2288]->out sram[2288]->outb sram[2289]->out sram[2289]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[25], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2282] sram->in sram[2282]->out sram[2282]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2282]->out) 0 -.nodeset V(sram[2282]->outb) vsp -Xsram[2283] sram->in sram[2283]->out sram[2283]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2283]->out) 0 -.nodeset V(sram[2283]->outb) vsp -Xsram[2284] sram->in sram[2284]->out sram[2284]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2284]->out) 0 -.nodeset V(sram[2284]->outb) vsp -Xsram[2285] sram->in sram[2285]->out sram[2285]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2285]->out) 0 -.nodeset V(sram[2285]->outb) vsp -Xsram[2286] sram->in sram[2286]->out sram[2286]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2286]->out) 0 -.nodeset V(sram[2286]->outb) vsp -Xsram[2287] sram->in sram[2287]->out sram[2287]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2287]->out) 0 -.nodeset V(sram[2287]->outb) vsp -Xsram[2288] sram->in sram[2288]->out sram[2288]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2288]->out) 0 -.nodeset V(sram[2288]->outb) vsp -Xsram[2289] sram->in sram[2289]->out sram[2289]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2289]->out) 0 -.nodeset V(sram[2289]->outb) vsp -Xmux_2level_tapbuf_size16[26] chanx[1][1]_midout[6] chanx[1][1]_midout[7] chanx[1][1]_midout[10] chanx[1][1]_midout[11] chanx[1][1]_midout[30] chanx[1][1]_midout[31] chanx[1][1]_midout[34] chanx[1][1]_midout[35] chanx[1][1]_midout[48] chanx[1][1]_midout[49] chanx[1][1]_midout[60] chanx[1][1]_midout[61] chanx[1][1]_midout[74] chanx[1][1]_midout[75] chanx[1][1]_midout[86] chanx[1][1]_midout[87] grid[1][1]_pin[0][0][0] sram[2290]->outb sram[2290]->out sram[2291]->out sram[2291]->outb sram[2292]->out sram[2292]->outb sram[2293]->out sram[2293]->outb sram[2294]->outb sram[2294]->out sram[2295]->out sram[2295]->outb sram[2296]->out sram[2296]->outb sram[2297]->out sram[2297]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[26], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2290] sram->in sram[2290]->out sram[2290]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2290]->out) 0 -.nodeset V(sram[2290]->outb) vsp -Xsram[2291] sram->in sram[2291]->out sram[2291]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2291]->out) 0 -.nodeset V(sram[2291]->outb) vsp -Xsram[2292] sram->in sram[2292]->out sram[2292]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2292]->out) 0 -.nodeset V(sram[2292]->outb) vsp -Xsram[2293] sram->in sram[2293]->out sram[2293]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2293]->out) 0 -.nodeset V(sram[2293]->outb) vsp -Xsram[2294] sram->in sram[2294]->out sram[2294]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2294]->out) 0 -.nodeset V(sram[2294]->outb) vsp -Xsram[2295] sram->in sram[2295]->out sram[2295]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2295]->out) 0 -.nodeset V(sram[2295]->outb) vsp -Xsram[2296] sram->in sram[2296]->out sram[2296]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2296]->out) 0 -.nodeset V(sram[2296]->outb) vsp -Xsram[2297] sram->in sram[2297]->out sram[2297]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2297]->out) 0 -.nodeset V(sram[2297]->outb) vsp -Xmux_2level_tapbuf_size16[27] chanx[1][1]_midout[6] chanx[1][1]_midout[7] chanx[1][1]_midout[10] chanx[1][1]_midout[11] chanx[1][1]_midout[24] chanx[1][1]_midout[25] chanx[1][1]_midout[36] chanx[1][1]_midout[37] chanx[1][1]_midout[48] chanx[1][1]_midout[49] chanx[1][1]_midout[60] chanx[1][1]_midout[61] chanx[1][1]_midout[76] chanx[1][1]_midout[77] chanx[1][1]_midout[88] chanx[1][1]_midout[89] grid[1][1]_pin[0][0][4] sram[2298]->outb sram[2298]->out sram[2299]->out sram[2299]->outb sram[2300]->out sram[2300]->outb sram[2301]->out sram[2301]->outb sram[2302]->outb sram[2302]->out sram[2303]->out sram[2303]->outb sram[2304]->out sram[2304]->outb sram[2305]->out sram[2305]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[27], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2298] sram->in sram[2298]->out sram[2298]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2298]->out) 0 -.nodeset V(sram[2298]->outb) vsp -Xsram[2299] sram->in sram[2299]->out sram[2299]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2299]->out) 0 -.nodeset V(sram[2299]->outb) vsp -Xsram[2300] sram->in sram[2300]->out sram[2300]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2300]->out) 0 -.nodeset V(sram[2300]->outb) vsp -Xsram[2301] sram->in sram[2301]->out sram[2301]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2301]->out) 0 -.nodeset V(sram[2301]->outb) vsp -Xsram[2302] sram->in sram[2302]->out sram[2302]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2302]->out) 0 -.nodeset V(sram[2302]->outb) vsp -Xsram[2303] sram->in sram[2303]->out sram[2303]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2303]->out) 0 -.nodeset V(sram[2303]->outb) vsp -Xsram[2304] sram->in sram[2304]->out sram[2304]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2304]->out) 0 -.nodeset V(sram[2304]->outb) vsp -Xsram[2305] sram->in sram[2305]->out sram[2305]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2305]->out) 0 -.nodeset V(sram[2305]->outb) vsp -Xmux_2level_tapbuf_size16[28] chanx[1][1]_midout[0] chanx[1][1]_midout[1] chanx[1][1]_midout[12] chanx[1][1]_midout[13] chanx[1][1]_midout[24] chanx[1][1]_midout[25] chanx[1][1]_midout[42] chanx[1][1]_midout[43] chanx[1][1]_midout[54] chanx[1][1]_midout[55] chanx[1][1]_midout[66] chanx[1][1]_midout[67] chanx[1][1]_midout[76] chanx[1][1]_midout[77] chanx[1][1]_midout[90] chanx[1][1]_midout[91] grid[1][1]_pin[0][0][8] sram[2306]->outb sram[2306]->out sram[2307]->out sram[2307]->outb sram[2308]->out sram[2308]->outb sram[2309]->out sram[2309]->outb sram[2310]->outb sram[2310]->out sram[2311]->out sram[2311]->outb sram[2312]->out sram[2312]->outb sram[2313]->out sram[2313]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[28], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2306] sram->in sram[2306]->out sram[2306]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2306]->out) 0 -.nodeset V(sram[2306]->outb) vsp -Xsram[2307] sram->in sram[2307]->out sram[2307]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2307]->out) 0 -.nodeset V(sram[2307]->outb) vsp -Xsram[2308] sram->in sram[2308]->out sram[2308]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2308]->out) 0 -.nodeset V(sram[2308]->outb) vsp -Xsram[2309] sram->in sram[2309]->out sram[2309]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2309]->out) 0 -.nodeset V(sram[2309]->outb) vsp -Xsram[2310] sram->in sram[2310]->out sram[2310]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2310]->out) 0 -.nodeset V(sram[2310]->outb) vsp -Xsram[2311] sram->in sram[2311]->out sram[2311]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2311]->out) 0 -.nodeset V(sram[2311]->outb) vsp -Xsram[2312] sram->in sram[2312]->out sram[2312]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2312]->out) 0 -.nodeset V(sram[2312]->outb) vsp -Xsram[2313] sram->in sram[2313]->out sram[2313]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2313]->out) 0 -.nodeset V(sram[2313]->outb) vsp -Xmux_2level_tapbuf_size16[29] chanx[1][1]_midout[0] chanx[1][1]_midout[1] chanx[1][1]_midout[22] chanx[1][1]_midout[23] chanx[1][1]_midout[26] chanx[1][1]_midout[27] chanx[1][1]_midout[42] chanx[1][1]_midout[43] chanx[1][1]_midout[54] chanx[1][1]_midout[55] chanx[1][1]_midout[64] chanx[1][1]_midout[65] chanx[1][1]_midout[78] chanx[1][1]_midout[79] chanx[1][1]_midout[90] chanx[1][1]_midout[91] grid[1][1]_pin[0][0][12] sram[2314]->outb sram[2314]->out sram[2315]->out sram[2315]->outb sram[2316]->out sram[2316]->outb sram[2317]->out sram[2317]->outb sram[2318]->outb sram[2318]->out sram[2319]->out sram[2319]->outb sram[2320]->out sram[2320]->outb sram[2321]->out sram[2321]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[29], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2314] sram->in sram[2314]->out sram[2314]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2314]->out) 0 -.nodeset V(sram[2314]->outb) vsp -Xsram[2315] sram->in sram[2315]->out sram[2315]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2315]->out) 0 -.nodeset V(sram[2315]->outb) vsp -Xsram[2316] sram->in sram[2316]->out sram[2316]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2316]->out) 0 -.nodeset V(sram[2316]->outb) vsp -Xsram[2317] sram->in sram[2317]->out sram[2317]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2317]->out) 0 -.nodeset V(sram[2317]->outb) vsp -Xsram[2318] sram->in sram[2318]->out sram[2318]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2318]->out) 0 -.nodeset V(sram[2318]->outb) vsp -Xsram[2319] sram->in sram[2319]->out sram[2319]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2319]->out) 0 -.nodeset V(sram[2319]->outb) vsp -Xsram[2320] sram->in sram[2320]->out sram[2320]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2320]->out) 0 -.nodeset V(sram[2320]->outb) vsp -Xsram[2321] sram->in sram[2321]->out sram[2321]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2321]->out) 0 -.nodeset V(sram[2321]->outb) vsp -Xmux_2level_tapbuf_size16[30] chanx[1][1]_midout[2] chanx[1][1]_midout[3] chanx[1][1]_midout[22] chanx[1][1]_midout[23] chanx[1][1]_midout[28] chanx[1][1]_midout[29] chanx[1][1]_midout[40] chanx[1][1]_midout[41] chanx[1][1]_midout[52] chanx[1][1]_midout[53] chanx[1][1]_midout[64] chanx[1][1]_midout[65] chanx[1][1]_midout[80] chanx[1][1]_midout[81] chanx[1][1]_midout[92] chanx[1][1]_midout[93] grid[1][1]_pin[0][0][16] sram[2322]->outb sram[2322]->out sram[2323]->out sram[2323]->outb sram[2324]->out sram[2324]->outb sram[2325]->out sram[2325]->outb sram[2326]->outb sram[2326]->out sram[2327]->out sram[2327]->outb sram[2328]->out sram[2328]->outb sram[2329]->out sram[2329]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[30], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2322] sram->in sram[2322]->out sram[2322]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2322]->out) 0 -.nodeset V(sram[2322]->outb) vsp -Xsram[2323] sram->in sram[2323]->out sram[2323]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2323]->out) 0 -.nodeset V(sram[2323]->outb) vsp -Xsram[2324] sram->in sram[2324]->out sram[2324]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2324]->out) 0 -.nodeset V(sram[2324]->outb) vsp -Xsram[2325] sram->in sram[2325]->out sram[2325]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2325]->out) 0 -.nodeset V(sram[2325]->outb) vsp -Xsram[2326] sram->in sram[2326]->out sram[2326]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2326]->out) 0 -.nodeset V(sram[2326]->outb) vsp -Xsram[2327] sram->in sram[2327]->out sram[2327]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2327]->out) 0 -.nodeset V(sram[2327]->outb) vsp -Xsram[2328] sram->in sram[2328]->out sram[2328]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2328]->out) 0 -.nodeset V(sram[2328]->outb) vsp -Xsram[2329] sram->in sram[2329]->out sram[2329]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2329]->out) 0 -.nodeset V(sram[2329]->outb) vsp -Xmux_2level_tapbuf_size16[31] chanx[1][1]_midout[4] chanx[1][1]_midout[5] chanx[1][1]_midout[16] chanx[1][1]_midout[17] chanx[1][1]_midout[28] chanx[1][1]_midout[29] chanx[1][1]_midout[40] chanx[1][1]_midout[41] chanx[1][1]_midout[58] chanx[1][1]_midout[59] chanx[1][1]_midout[68] chanx[1][1]_midout[69] chanx[1][1]_midout[80] chanx[1][1]_midout[81] chanx[1][1]_midout[92] chanx[1][1]_midout[93] grid[1][1]_pin[0][0][20] sram[2330]->outb sram[2330]->out sram[2331]->out sram[2331]->outb sram[2332]->out sram[2332]->outb sram[2333]->out sram[2333]->outb sram[2334]->outb sram[2334]->out sram[2335]->out sram[2335]->outb sram[2336]->out sram[2336]->outb sram[2337]->out sram[2337]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[31], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2330] sram->in sram[2330]->out sram[2330]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2330]->out) 0 -.nodeset V(sram[2330]->outb) vsp -Xsram[2331] sram->in sram[2331]->out sram[2331]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2331]->out) 0 -.nodeset V(sram[2331]->outb) vsp -Xsram[2332] sram->in sram[2332]->out sram[2332]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2332]->out) 0 -.nodeset V(sram[2332]->outb) vsp -Xsram[2333] sram->in sram[2333]->out sram[2333]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2333]->out) 0 -.nodeset V(sram[2333]->outb) vsp -Xsram[2334] sram->in sram[2334]->out sram[2334]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2334]->out) 0 -.nodeset V(sram[2334]->outb) vsp -Xsram[2335] sram->in sram[2335]->out sram[2335]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2335]->out) 0 -.nodeset V(sram[2335]->outb) vsp -Xsram[2336] sram->in sram[2336]->out sram[2336]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2336]->out) 0 -.nodeset V(sram[2336]->outb) vsp -Xsram[2337] sram->in sram[2337]->out sram[2337]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2337]->out) 0 -.nodeset V(sram[2337]->outb) vsp -Xmux_2level_tapbuf_size16[32] chanx[1][1]_midout[4] chanx[1][1]_midout[5] chanx[1][1]_midout[18] chanx[1][1]_midout[19] chanx[1][1]_midout[38] chanx[1][1]_midout[39] chanx[1][1]_midout[46] chanx[1][1]_midout[47] chanx[1][1]_midout[58] chanx[1][1]_midout[59] chanx[1][1]_midout[70] chanx[1][1]_midout[71] chanx[1][1]_midout[82] chanx[1][1]_midout[83] chanx[1][1]_midout[94] chanx[1][1]_midout[95] grid[1][1]_pin[0][0][24] sram[2338]->outb sram[2338]->out sram[2339]->out sram[2339]->outb sram[2340]->out sram[2340]->outb sram[2341]->out sram[2341]->outb sram[2342]->outb sram[2342]->out sram[2343]->out sram[2343]->outb sram[2344]->out sram[2344]->outb sram[2345]->out sram[2345]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[32], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2338] sram->in sram[2338]->out sram[2338]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2338]->out) 0 -.nodeset V(sram[2338]->outb) vsp -Xsram[2339] sram->in sram[2339]->out sram[2339]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2339]->out) 0 -.nodeset V(sram[2339]->outb) vsp -Xsram[2340] sram->in sram[2340]->out sram[2340]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2340]->out) 0 -.nodeset V(sram[2340]->outb) vsp -Xsram[2341] sram->in sram[2341]->out sram[2341]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2341]->out) 0 -.nodeset V(sram[2341]->outb) vsp -Xsram[2342] sram->in sram[2342]->out sram[2342]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2342]->out) 0 -.nodeset V(sram[2342]->outb) vsp -Xsram[2343] sram->in sram[2343]->out sram[2343]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2343]->out) 0 -.nodeset V(sram[2343]->outb) vsp -Xsram[2344] sram->in sram[2344]->out sram[2344]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2344]->out) 0 -.nodeset V(sram[2344]->outb) vsp -Xsram[2345] sram->in sram[2345]->out sram[2345]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2345]->out) 0 -.nodeset V(sram[2345]->outb) vsp -Xmux_2level_tapbuf_size16[33] chanx[1][1]_midout[14] chanx[1][1]_midout[15] chanx[1][1]_midout[18] chanx[1][1]_midout[19] chanx[1][1]_midout[38] chanx[1][1]_midout[39] chanx[1][1]_midout[44] chanx[1][1]_midout[45] chanx[1][1]_midout[56] chanx[1][1]_midout[57] chanx[1][1]_midout[70] chanx[1][1]_midout[71] chanx[1][1]_midout[82] chanx[1][1]_midout[83] chanx[1][1]_midout[96] chanx[1][1]_midout[97] grid[1][1]_pin[0][0][28] sram[2346]->outb sram[2346]->out sram[2347]->out sram[2347]->outb sram[2348]->out sram[2348]->outb sram[2349]->out sram[2349]->outb sram[2350]->outb sram[2350]->out sram[2351]->out sram[2351]->outb sram[2352]->out sram[2352]->outb sram[2353]->out sram[2353]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[33], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2346] sram->in sram[2346]->out sram[2346]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2346]->out) 0 -.nodeset V(sram[2346]->outb) vsp -Xsram[2347] sram->in sram[2347]->out sram[2347]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2347]->out) 0 -.nodeset V(sram[2347]->outb) vsp -Xsram[2348] sram->in sram[2348]->out sram[2348]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2348]->out) 0 -.nodeset V(sram[2348]->outb) vsp -Xsram[2349] sram->in sram[2349]->out sram[2349]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2349]->out) 0 -.nodeset V(sram[2349]->outb) vsp -Xsram[2350] sram->in sram[2350]->out sram[2350]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2350]->out) 0 -.nodeset V(sram[2350]->outb) vsp -Xsram[2351] sram->in sram[2351]->out sram[2351]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2351]->out) 0 -.nodeset V(sram[2351]->outb) vsp -Xsram[2352] sram->in sram[2352]->out sram[2352]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2352]->out) 0 -.nodeset V(sram[2352]->outb) vsp -Xsram[2353] sram->in sram[2353]->out sram[2353]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2353]->out) 0 -.nodeset V(sram[2353]->outb) vsp -Xmux_2level_tapbuf_size16[34] chanx[1][1]_midout[8] chanx[1][1]_midout[9] chanx[1][1]_midout[20] chanx[1][1]_midout[21] chanx[1][1]_midout[32] chanx[1][1]_midout[33] chanx[1][1]_midout[44] chanx[1][1]_midout[45] chanx[1][1]_midout[62] chanx[1][1]_midout[63] chanx[1][1]_midout[72] chanx[1][1]_midout[73] chanx[1][1]_midout[84] chanx[1][1]_midout[85] chanx[1][1]_midout[96] chanx[1][1]_midout[97] grid[1][1]_pin[0][0][32] sram[2354]->outb sram[2354]->out sram[2355]->out sram[2355]->outb sram[2356]->out sram[2356]->outb sram[2357]->out sram[2357]->outb sram[2358]->outb sram[2358]->out sram[2359]->out sram[2359]->outb sram[2360]->out sram[2360]->outb sram[2361]->out sram[2361]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[34], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2354] sram->in sram[2354]->out sram[2354]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2354]->out) 0 -.nodeset V(sram[2354]->outb) vsp -Xsram[2355] sram->in sram[2355]->out sram[2355]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2355]->out) 0 -.nodeset V(sram[2355]->outb) vsp -Xsram[2356] sram->in sram[2356]->out sram[2356]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2356]->out) 0 -.nodeset V(sram[2356]->outb) vsp -Xsram[2357] sram->in sram[2357]->out sram[2357]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2357]->out) 0 -.nodeset V(sram[2357]->outb) vsp -Xsram[2358] sram->in sram[2358]->out sram[2358]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2358]->out) 0 -.nodeset V(sram[2358]->outb) vsp -Xsram[2359] sram->in sram[2359]->out sram[2359]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2359]->out) 0 -.nodeset V(sram[2359]->outb) vsp -Xsram[2360] sram->in sram[2360]->out sram[2360]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2360]->out) 0 -.nodeset V(sram[2360]->outb) vsp -Xsram[2361] sram->in sram[2361]->out sram[2361]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2361]->out) 0 -.nodeset V(sram[2361]->outb) vsp -Xmux_2level_tapbuf_size16[35] chanx[1][1]_midout[8] chanx[1][1]_midout[9] chanx[1][1]_midout[20] chanx[1][1]_midout[21] chanx[1][1]_midout[34] chanx[1][1]_midout[35] chanx[1][1]_midout[50] chanx[1][1]_midout[51] chanx[1][1]_midout[62] chanx[1][1]_midout[63] chanx[1][1]_midout[72] chanx[1][1]_midout[73] chanx[1][1]_midout[86] chanx[1][1]_midout[87] chanx[1][1]_midout[98] chanx[1][1]_midout[99] grid[1][1]_pin[0][0][36] sram[2362]->outb sram[2362]->out sram[2363]->out sram[2363]->outb sram[2364]->out sram[2364]->outb sram[2365]->out sram[2365]->outb sram[2366]->outb sram[2366]->out sram[2367]->out sram[2367]->outb sram[2368]->out sram[2368]->outb sram[2369]->out sram[2369]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[35], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2362] sram->in sram[2362]->out sram[2362]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2362]->out) 0 -.nodeset V(sram[2362]->outb) vsp -Xsram[2363] sram->in sram[2363]->out sram[2363]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2363]->out) 0 -.nodeset V(sram[2363]->outb) vsp -Xsram[2364] sram->in sram[2364]->out sram[2364]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2364]->out) 0 -.nodeset V(sram[2364]->outb) vsp -Xsram[2365] sram->in sram[2365]->out sram[2365]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2365]->out) 0 -.nodeset V(sram[2365]->outb) vsp -Xsram[2366] sram->in sram[2366]->out sram[2366]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2366]->out) 0 -.nodeset V(sram[2366]->outb) vsp -Xsram[2367] sram->in sram[2367]->out sram[2367]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2367]->out) 0 -.nodeset V(sram[2367]->outb) vsp -Xsram[2368] sram->in sram[2368]->out sram[2368]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2368]->out) 0 -.nodeset V(sram[2368]->outb) vsp -Xsram[2369] sram->in sram[2369]->out sram[2369]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2369]->out) 0 -.nodeset V(sram[2369]->outb) vsp -.eom diff --git a/examples/spice_test_example_2/subckt/cby_0_1.sp b/examples/spice_test_example_2/subckt/cby_0_1.sp deleted file mode 100644 index 05704879a..000000000 --- a/examples/spice_test_example_2/subckt/cby_0_1.sp +++ /dev/null @@ -1,615 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Connection Block Y-channel [0][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -.subckt cby[0][1] -+ chany[0][1]_midout[0] -+ chany[0][1]_midout[1] -+ chany[0][1]_midout[2] -+ chany[0][1]_midout[3] -+ chany[0][1]_midout[4] -+ chany[0][1]_midout[5] -+ chany[0][1]_midout[6] -+ chany[0][1]_midout[7] -+ chany[0][1]_midout[8] -+ chany[0][1]_midout[9] -+ chany[0][1]_midout[10] -+ chany[0][1]_midout[11] -+ chany[0][1]_midout[12] -+ chany[0][1]_midout[13] -+ chany[0][1]_midout[14] -+ chany[0][1]_midout[15] -+ chany[0][1]_midout[16] -+ chany[0][1]_midout[17] -+ chany[0][1]_midout[18] -+ chany[0][1]_midout[19] -+ chany[0][1]_midout[20] -+ chany[0][1]_midout[21] -+ chany[0][1]_midout[22] -+ chany[0][1]_midout[23] -+ chany[0][1]_midout[24] -+ chany[0][1]_midout[25] -+ chany[0][1]_midout[26] -+ chany[0][1]_midout[27] -+ chany[0][1]_midout[28] -+ chany[0][1]_midout[29] -+ chany[0][1]_midout[30] -+ chany[0][1]_midout[31] -+ chany[0][1]_midout[32] -+ chany[0][1]_midout[33] -+ chany[0][1]_midout[34] -+ chany[0][1]_midout[35] -+ chany[0][1]_midout[36] -+ chany[0][1]_midout[37] -+ chany[0][1]_midout[38] -+ chany[0][1]_midout[39] -+ chany[0][1]_midout[40] -+ chany[0][1]_midout[41] -+ chany[0][1]_midout[42] -+ chany[0][1]_midout[43] -+ chany[0][1]_midout[44] -+ chany[0][1]_midout[45] -+ chany[0][1]_midout[46] -+ chany[0][1]_midout[47] -+ chany[0][1]_midout[48] -+ chany[0][1]_midout[49] -+ chany[0][1]_midout[50] -+ chany[0][1]_midout[51] -+ chany[0][1]_midout[52] -+ chany[0][1]_midout[53] -+ chany[0][1]_midout[54] -+ chany[0][1]_midout[55] -+ chany[0][1]_midout[56] -+ chany[0][1]_midout[57] -+ chany[0][1]_midout[58] -+ chany[0][1]_midout[59] -+ chany[0][1]_midout[60] -+ chany[0][1]_midout[61] -+ chany[0][1]_midout[62] -+ chany[0][1]_midout[63] -+ chany[0][1]_midout[64] -+ chany[0][1]_midout[65] -+ chany[0][1]_midout[66] -+ chany[0][1]_midout[67] -+ chany[0][1]_midout[68] -+ chany[0][1]_midout[69] -+ chany[0][1]_midout[70] -+ chany[0][1]_midout[71] -+ chany[0][1]_midout[72] -+ chany[0][1]_midout[73] -+ chany[0][1]_midout[74] -+ chany[0][1]_midout[75] -+ chany[0][1]_midout[76] -+ chany[0][1]_midout[77] -+ chany[0][1]_midout[78] -+ chany[0][1]_midout[79] -+ chany[0][1]_midout[80] -+ chany[0][1]_midout[81] -+ chany[0][1]_midout[82] -+ chany[0][1]_midout[83] -+ chany[0][1]_midout[84] -+ chany[0][1]_midout[85] -+ chany[0][1]_midout[86] -+ chany[0][1]_midout[87] -+ chany[0][1]_midout[88] -+ chany[0][1]_midout[89] -+ chany[0][1]_midout[90] -+ chany[0][1]_midout[91] -+ chany[0][1]_midout[92] -+ chany[0][1]_midout[93] -+ chany[0][1]_midout[94] -+ chany[0][1]_midout[95] -+ chany[0][1]_midout[96] -+ chany[0][1]_midout[97] -+ chany[0][1]_midout[98] -+ chany[0][1]_midout[99] -+ grid[1][1]_pin[0][3][3] -+ grid[1][1]_pin[0][3][7] -+ grid[1][1]_pin[0][3][11] -+ grid[1][1]_pin[0][3][15] -+ grid[1][1]_pin[0][3][19] -+ grid[1][1]_pin[0][3][23] -+ grid[1][1]_pin[0][3][27] -+ grid[1][1]_pin[0][3][31] -+ grid[1][1]_pin[0][3][35] -+ grid[1][1]_pin[0][3][39] -+ grid[0][1]_pin[0][1][0] -+ grid[0][1]_pin[0][1][2] -+ grid[0][1]_pin[0][1][4] -+ grid[0][1]_pin[0][1][6] -+ grid[0][1]_pin[0][1][8] -+ grid[0][1]_pin[0][1][10] -+ grid[0][1]_pin[0][1][12] -+ grid[0][1]_pin[0][1][14] -+ svdd sgnd -Xmux_2level_tapbuf_size16[36] chany[0][1]_midout[0] chany[0][1]_midout[1] chany[0][1]_midout[12] chany[0][1]_midout[13] chany[0][1]_midout[24] chany[0][1]_midout[25] chany[0][1]_midout[38] chany[0][1]_midout[39] chany[0][1]_midout[50] chany[0][1]_midout[51] chany[0][1]_midout[62] chany[0][1]_midout[63] chany[0][1]_midout[74] chany[0][1]_midout[75] chany[0][1]_midout[88] chany[0][1]_midout[89] grid[1][1]_pin[0][3][3] sram[2370]->outb sram[2370]->out sram[2371]->out sram[2371]->outb sram[2372]->out sram[2372]->outb sram[2373]->out sram[2373]->outb sram[2374]->outb sram[2374]->out sram[2375]->out sram[2375]->outb sram[2376]->out sram[2376]->outb sram[2377]->out sram[2377]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[36], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2370] sram->in sram[2370]->out sram[2370]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2370]->out) 0 -.nodeset V(sram[2370]->outb) vsp -Xsram[2371] sram->in sram[2371]->out sram[2371]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2371]->out) 0 -.nodeset V(sram[2371]->outb) vsp -Xsram[2372] sram->in sram[2372]->out sram[2372]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2372]->out) 0 -.nodeset V(sram[2372]->outb) vsp -Xsram[2373] sram->in sram[2373]->out sram[2373]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2373]->out) 0 -.nodeset V(sram[2373]->outb) vsp -Xsram[2374] sram->in sram[2374]->out sram[2374]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2374]->out) 0 -.nodeset V(sram[2374]->outb) vsp -Xsram[2375] sram->in sram[2375]->out sram[2375]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2375]->out) 0 -.nodeset V(sram[2375]->outb) vsp -Xsram[2376] sram->in sram[2376]->out sram[2376]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2376]->out) 0 -.nodeset V(sram[2376]->outb) vsp -Xsram[2377] sram->in sram[2377]->out sram[2377]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2377]->out) 0 -.nodeset V(sram[2377]->outb) vsp -Xmux_2level_tapbuf_size16[37] chany[0][1]_midout[2] chany[0][1]_midout[3] chany[0][1]_midout[14] chany[0][1]_midout[15] chany[0][1]_midout[26] chany[0][1]_midout[27] chany[0][1]_midout[38] chany[0][1]_midout[39] chany[0][1]_midout[52] chany[0][1]_midout[53] chany[0][1]_midout[64] chany[0][1]_midout[65] chany[0][1]_midout[76] chany[0][1]_midout[77] chany[0][1]_midout[88] chany[0][1]_midout[89] grid[1][1]_pin[0][3][7] sram[2378]->outb sram[2378]->out sram[2379]->out sram[2379]->outb sram[2380]->out sram[2380]->outb sram[2381]->out sram[2381]->outb sram[2382]->outb sram[2382]->out sram[2383]->out sram[2383]->outb sram[2384]->out sram[2384]->outb sram[2385]->out sram[2385]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[37], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2378] sram->in sram[2378]->out sram[2378]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2378]->out) 0 -.nodeset V(sram[2378]->outb) vsp -Xsram[2379] sram->in sram[2379]->out sram[2379]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2379]->out) 0 -.nodeset V(sram[2379]->outb) vsp -Xsram[2380] sram->in sram[2380]->out sram[2380]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2380]->out) 0 -.nodeset V(sram[2380]->outb) vsp -Xsram[2381] sram->in sram[2381]->out sram[2381]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2381]->out) 0 -.nodeset V(sram[2381]->outb) vsp -Xsram[2382] sram->in sram[2382]->out sram[2382]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2382]->out) 0 -.nodeset V(sram[2382]->outb) vsp -Xsram[2383] sram->in sram[2383]->out sram[2383]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2383]->out) 0 -.nodeset V(sram[2383]->outb) vsp -Xsram[2384] sram->in sram[2384]->out sram[2384]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2384]->out) 0 -.nodeset V(sram[2384]->outb) vsp -Xsram[2385] sram->in sram[2385]->out sram[2385]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2385]->out) 0 -.nodeset V(sram[2385]->outb) vsp -Xmux_2level_tapbuf_size16[38] chany[0][1]_midout[2] chany[0][1]_midout[3] chany[0][1]_midout[14] chany[0][1]_midout[15] chany[0][1]_midout[28] chany[0][1]_midout[29] chany[0][1]_midout[40] chany[0][1]_midout[41] chany[0][1]_midout[52] chany[0][1]_midout[53] chany[0][1]_midout[64] chany[0][1]_midout[65] chany[0][1]_midout[78] chany[0][1]_midout[79] chany[0][1]_midout[90] chany[0][1]_midout[91] grid[1][1]_pin[0][3][11] sram[2386]->outb sram[2386]->out sram[2387]->out sram[2387]->outb sram[2388]->out sram[2388]->outb sram[2389]->out sram[2389]->outb sram[2390]->outb sram[2390]->out sram[2391]->out sram[2391]->outb sram[2392]->out sram[2392]->outb sram[2393]->out sram[2393]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[38], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2386] sram->in sram[2386]->out sram[2386]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2386]->out) 0 -.nodeset V(sram[2386]->outb) vsp -Xsram[2387] sram->in sram[2387]->out sram[2387]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2387]->out) 0 -.nodeset V(sram[2387]->outb) vsp -Xsram[2388] sram->in sram[2388]->out sram[2388]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2388]->out) 0 -.nodeset V(sram[2388]->outb) vsp -Xsram[2389] sram->in sram[2389]->out sram[2389]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2389]->out) 0 -.nodeset V(sram[2389]->outb) vsp -Xsram[2390] sram->in sram[2390]->out sram[2390]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2390]->out) 0 -.nodeset V(sram[2390]->outb) vsp -Xsram[2391] sram->in sram[2391]->out sram[2391]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2391]->out) 0 -.nodeset V(sram[2391]->outb) vsp -Xsram[2392] sram->in sram[2392]->out sram[2392]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2392]->out) 0 -.nodeset V(sram[2392]->outb) vsp -Xsram[2393] sram->in sram[2393]->out sram[2393]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2393]->out) 0 -.nodeset V(sram[2393]->outb) vsp -Xmux_2level_tapbuf_size16[39] chany[0][1]_midout[4] chany[0][1]_midout[5] chany[0][1]_midout[16] chany[0][1]_midout[17] chany[0][1]_midout[28] chany[0][1]_midout[29] chany[0][1]_midout[42] chany[0][1]_midout[43] chany[0][1]_midout[54] chany[0][1]_midout[55] chany[0][1]_midout[66] chany[0][1]_midout[67] chany[0][1]_midout[78] chany[0][1]_midout[79] chany[0][1]_midout[92] chany[0][1]_midout[93] grid[1][1]_pin[0][3][15] sram[2394]->outb sram[2394]->out sram[2395]->out sram[2395]->outb sram[2396]->out sram[2396]->outb sram[2397]->out sram[2397]->outb sram[2398]->outb sram[2398]->out sram[2399]->out sram[2399]->outb sram[2400]->out sram[2400]->outb sram[2401]->out sram[2401]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[39], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2394] sram->in sram[2394]->out sram[2394]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2394]->out) 0 -.nodeset V(sram[2394]->outb) vsp -Xsram[2395] sram->in sram[2395]->out sram[2395]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2395]->out) 0 -.nodeset V(sram[2395]->outb) vsp -Xsram[2396] sram->in sram[2396]->out sram[2396]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2396]->out) 0 -.nodeset V(sram[2396]->outb) vsp -Xsram[2397] sram->in sram[2397]->out sram[2397]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2397]->out) 0 -.nodeset V(sram[2397]->outb) vsp -Xsram[2398] sram->in sram[2398]->out sram[2398]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2398]->out) 0 -.nodeset V(sram[2398]->outb) vsp -Xsram[2399] sram->in sram[2399]->out sram[2399]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2399]->out) 0 -.nodeset V(sram[2399]->outb) vsp -Xsram[2400] sram->in sram[2400]->out sram[2400]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2400]->out) 0 -.nodeset V(sram[2400]->outb) vsp -Xsram[2401] sram->in sram[2401]->out sram[2401]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2401]->out) 0 -.nodeset V(sram[2401]->outb) vsp -Xmux_2level_tapbuf_size16[40] chany[0][1]_midout[4] chany[0][1]_midout[5] chany[0][1]_midout[18] chany[0][1]_midout[19] chany[0][1]_midout[30] chany[0][1]_midout[31] chany[0][1]_midout[42] chany[0][1]_midout[43] chany[0][1]_midout[54] chany[0][1]_midout[55] chany[0][1]_midout[68] chany[0][1]_midout[69] chany[0][1]_midout[80] chany[0][1]_midout[81] chany[0][1]_midout[92] chany[0][1]_midout[93] grid[1][1]_pin[0][3][19] sram[2402]->outb sram[2402]->out sram[2403]->out sram[2403]->outb sram[2404]->out sram[2404]->outb sram[2405]->out sram[2405]->outb sram[2406]->outb sram[2406]->out sram[2407]->out sram[2407]->outb sram[2408]->out sram[2408]->outb sram[2409]->out sram[2409]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[40], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2402] sram->in sram[2402]->out sram[2402]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2402]->out) 0 -.nodeset V(sram[2402]->outb) vsp -Xsram[2403] sram->in sram[2403]->out sram[2403]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2403]->out) 0 -.nodeset V(sram[2403]->outb) vsp -Xsram[2404] sram->in sram[2404]->out sram[2404]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2404]->out) 0 -.nodeset V(sram[2404]->outb) vsp -Xsram[2405] sram->in sram[2405]->out sram[2405]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2405]->out) 0 -.nodeset V(sram[2405]->outb) vsp -Xsram[2406] sram->in sram[2406]->out sram[2406]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2406]->out) 0 -.nodeset V(sram[2406]->outb) vsp -Xsram[2407] sram->in sram[2407]->out sram[2407]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2407]->out) 0 -.nodeset V(sram[2407]->outb) vsp -Xsram[2408] sram->in sram[2408]->out sram[2408]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2408]->out) 0 -.nodeset V(sram[2408]->outb) vsp -Xsram[2409] sram->in sram[2409]->out sram[2409]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2409]->out) 0 -.nodeset V(sram[2409]->outb) vsp -Xmux_2level_tapbuf_size16[41] chany[0][1]_midout[6] chany[0][1]_midout[7] chany[0][1]_midout[18] chany[0][1]_midout[19] chany[0][1]_midout[32] chany[0][1]_midout[33] chany[0][1]_midout[44] chany[0][1]_midout[45] chany[0][1]_midout[56] chany[0][1]_midout[57] chany[0][1]_midout[68] chany[0][1]_midout[69] chany[0][1]_midout[82] chany[0][1]_midout[83] chany[0][1]_midout[94] chany[0][1]_midout[95] grid[1][1]_pin[0][3][23] sram[2410]->outb sram[2410]->out sram[2411]->out sram[2411]->outb sram[2412]->out sram[2412]->outb sram[2413]->out sram[2413]->outb sram[2414]->outb sram[2414]->out sram[2415]->out sram[2415]->outb sram[2416]->out sram[2416]->outb sram[2417]->out sram[2417]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[41], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2410] sram->in sram[2410]->out sram[2410]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2410]->out) 0 -.nodeset V(sram[2410]->outb) vsp -Xsram[2411] sram->in sram[2411]->out sram[2411]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2411]->out) 0 -.nodeset V(sram[2411]->outb) vsp -Xsram[2412] sram->in sram[2412]->out sram[2412]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2412]->out) 0 -.nodeset V(sram[2412]->outb) vsp -Xsram[2413] sram->in sram[2413]->out sram[2413]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2413]->out) 0 -.nodeset V(sram[2413]->outb) vsp -Xsram[2414] sram->in sram[2414]->out sram[2414]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2414]->out) 0 -.nodeset V(sram[2414]->outb) vsp -Xsram[2415] sram->in sram[2415]->out sram[2415]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2415]->out) 0 -.nodeset V(sram[2415]->outb) vsp -Xsram[2416] sram->in sram[2416]->out sram[2416]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2416]->out) 0 -.nodeset V(sram[2416]->outb) vsp -Xsram[2417] sram->in sram[2417]->out sram[2417]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2417]->out) 0 -.nodeset V(sram[2417]->outb) vsp -Xmux_2level_tapbuf_size16[42] chany[0][1]_midout[8] chany[0][1]_midout[9] chany[0][1]_midout[20] chany[0][1]_midout[21] chany[0][1]_midout[32] chany[0][1]_midout[33] chany[0][1]_midout[44] chany[0][1]_midout[45] chany[0][1]_midout[58] chany[0][1]_midout[59] chany[0][1]_midout[70] chany[0][1]_midout[71] chany[0][1]_midout[82] chany[0][1]_midout[83] chany[0][1]_midout[94] chany[0][1]_midout[95] grid[1][1]_pin[0][3][27] sram[2418]->outb sram[2418]->out sram[2419]->out sram[2419]->outb sram[2420]->out sram[2420]->outb sram[2421]->out sram[2421]->outb sram[2422]->outb sram[2422]->out sram[2423]->out sram[2423]->outb sram[2424]->out sram[2424]->outb sram[2425]->out sram[2425]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[42], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2418] sram->in sram[2418]->out sram[2418]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2418]->out) 0 -.nodeset V(sram[2418]->outb) vsp -Xsram[2419] sram->in sram[2419]->out sram[2419]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2419]->out) 0 -.nodeset V(sram[2419]->outb) vsp -Xsram[2420] sram->in sram[2420]->out sram[2420]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2420]->out) 0 -.nodeset V(sram[2420]->outb) vsp -Xsram[2421] sram->in sram[2421]->out sram[2421]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2421]->out) 0 -.nodeset V(sram[2421]->outb) vsp -Xsram[2422] sram->in sram[2422]->out sram[2422]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2422]->out) 0 -.nodeset V(sram[2422]->outb) vsp -Xsram[2423] sram->in sram[2423]->out sram[2423]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2423]->out) 0 -.nodeset V(sram[2423]->outb) vsp -Xsram[2424] sram->in sram[2424]->out sram[2424]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2424]->out) 0 -.nodeset V(sram[2424]->outb) vsp -Xsram[2425] sram->in sram[2425]->out sram[2425]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2425]->out) 0 -.nodeset V(sram[2425]->outb) vsp -Xmux_2level_tapbuf_size16[43] chany[0][1]_midout[8] chany[0][1]_midout[9] chany[0][1]_midout[22] chany[0][1]_midout[23] chany[0][1]_midout[34] chany[0][1]_midout[35] chany[0][1]_midout[46] chany[0][1]_midout[47] chany[0][1]_midout[58] chany[0][1]_midout[59] chany[0][1]_midout[72] chany[0][1]_midout[73] chany[0][1]_midout[84] chany[0][1]_midout[85] chany[0][1]_midout[96] chany[0][1]_midout[97] grid[1][1]_pin[0][3][31] sram[2426]->outb sram[2426]->out sram[2427]->out sram[2427]->outb sram[2428]->out sram[2428]->outb sram[2429]->out sram[2429]->outb sram[2430]->outb sram[2430]->out sram[2431]->out sram[2431]->outb sram[2432]->out sram[2432]->outb sram[2433]->out sram[2433]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[43], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2426] sram->in sram[2426]->out sram[2426]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2426]->out) 0 -.nodeset V(sram[2426]->outb) vsp -Xsram[2427] sram->in sram[2427]->out sram[2427]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2427]->out) 0 -.nodeset V(sram[2427]->outb) vsp -Xsram[2428] sram->in sram[2428]->out sram[2428]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2428]->out) 0 -.nodeset V(sram[2428]->outb) vsp -Xsram[2429] sram->in sram[2429]->out sram[2429]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2429]->out) 0 -.nodeset V(sram[2429]->outb) vsp -Xsram[2430] sram->in sram[2430]->out sram[2430]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2430]->out) 0 -.nodeset V(sram[2430]->outb) vsp -Xsram[2431] sram->in sram[2431]->out sram[2431]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2431]->out) 0 -.nodeset V(sram[2431]->outb) vsp -Xsram[2432] sram->in sram[2432]->out sram[2432]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2432]->out) 0 -.nodeset V(sram[2432]->outb) vsp -Xsram[2433] sram->in sram[2433]->out sram[2433]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2433]->out) 0 -.nodeset V(sram[2433]->outb) vsp -Xmux_2level_tapbuf_size16[44] chany[0][1]_midout[10] chany[0][1]_midout[11] chany[0][1]_midout[22] chany[0][1]_midout[23] chany[0][1]_midout[34] chany[0][1]_midout[35] chany[0][1]_midout[48] chany[0][1]_midout[49] chany[0][1]_midout[60] chany[0][1]_midout[61] chany[0][1]_midout[72] chany[0][1]_midout[73] chany[0][1]_midout[84] chany[0][1]_midout[85] chany[0][1]_midout[98] chany[0][1]_midout[99] grid[1][1]_pin[0][3][35] sram[2434]->outb sram[2434]->out sram[2435]->out sram[2435]->outb sram[2436]->out sram[2436]->outb sram[2437]->out sram[2437]->outb sram[2438]->outb sram[2438]->out sram[2439]->out sram[2439]->outb sram[2440]->out sram[2440]->outb sram[2441]->out sram[2441]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[44], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2434] sram->in sram[2434]->out sram[2434]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2434]->out) 0 -.nodeset V(sram[2434]->outb) vsp -Xsram[2435] sram->in sram[2435]->out sram[2435]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2435]->out) 0 -.nodeset V(sram[2435]->outb) vsp -Xsram[2436] sram->in sram[2436]->out sram[2436]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2436]->out) 0 -.nodeset V(sram[2436]->outb) vsp -Xsram[2437] sram->in sram[2437]->out sram[2437]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2437]->out) 0 -.nodeset V(sram[2437]->outb) vsp -Xsram[2438] sram->in sram[2438]->out sram[2438]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2438]->out) 0 -.nodeset V(sram[2438]->outb) vsp -Xsram[2439] sram->in sram[2439]->out sram[2439]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2439]->out) 0 -.nodeset V(sram[2439]->outb) vsp -Xsram[2440] sram->in sram[2440]->out sram[2440]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2440]->out) 0 -.nodeset V(sram[2440]->outb) vsp -Xsram[2441] sram->in sram[2441]->out sram[2441]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2441]->out) 0 -.nodeset V(sram[2441]->outb) vsp -Xmux_2level_tapbuf_size16[45] chany[0][1]_midout[12] chany[0][1]_midout[13] chany[0][1]_midout[24] chany[0][1]_midout[25] chany[0][1]_midout[36] chany[0][1]_midout[37] chany[0][1]_midout[48] chany[0][1]_midout[49] chany[0][1]_midout[62] chany[0][1]_midout[63] chany[0][1]_midout[74] chany[0][1]_midout[75] chany[0][1]_midout[86] chany[0][1]_midout[87] chany[0][1]_midout[98] chany[0][1]_midout[99] grid[1][1]_pin[0][3][39] sram[2442]->outb sram[2442]->out sram[2443]->out sram[2443]->outb sram[2444]->out sram[2444]->outb sram[2445]->out sram[2445]->outb sram[2446]->outb sram[2446]->out sram[2447]->out sram[2447]->outb sram[2448]->out sram[2448]->outb sram[2449]->out sram[2449]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[45], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2442] sram->in sram[2442]->out sram[2442]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2442]->out) 0 -.nodeset V(sram[2442]->outb) vsp -Xsram[2443] sram->in sram[2443]->out sram[2443]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2443]->out) 0 -.nodeset V(sram[2443]->outb) vsp -Xsram[2444] sram->in sram[2444]->out sram[2444]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2444]->out) 0 -.nodeset V(sram[2444]->outb) vsp -Xsram[2445] sram->in sram[2445]->out sram[2445]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2445]->out) 0 -.nodeset V(sram[2445]->outb) vsp -Xsram[2446] sram->in sram[2446]->out sram[2446]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2446]->out) 0 -.nodeset V(sram[2446]->outb) vsp -Xsram[2447] sram->in sram[2447]->out sram[2447]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2447]->out) 0 -.nodeset V(sram[2447]->outb) vsp -Xsram[2448] sram->in sram[2448]->out sram[2448]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2448]->out) 0 -.nodeset V(sram[2448]->outb) vsp -Xsram[2449] sram->in sram[2449]->out sram[2449]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2449]->out) 0 -.nodeset V(sram[2449]->outb) vsp -Xmux_2level_tapbuf_size16[46] chany[0][1]_midout[0] chany[0][1]_midout[1] chany[0][1]_midout[12] chany[0][1]_midout[13] chany[0][1]_midout[24] chany[0][1]_midout[25] chany[0][1]_midout[36] chany[0][1]_midout[37] chany[0][1]_midout[50] chany[0][1]_midout[51] chany[0][1]_midout[62] chany[0][1]_midout[63] chany[0][1]_midout[74] chany[0][1]_midout[75] chany[0][1]_midout[86] chany[0][1]_midout[87] grid[0][1]_pin[0][1][0] sram[2450]->outb sram[2450]->out sram[2451]->out sram[2451]->outb sram[2452]->out sram[2452]->outb sram[2453]->out sram[2453]->outb sram[2454]->outb sram[2454]->out sram[2455]->out sram[2455]->outb sram[2456]->out sram[2456]->outb sram[2457]->out sram[2457]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[46], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2450] sram->in sram[2450]->out sram[2450]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2450]->out) 0 -.nodeset V(sram[2450]->outb) vsp -Xsram[2451] sram->in sram[2451]->out sram[2451]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2451]->out) 0 -.nodeset V(sram[2451]->outb) vsp -Xsram[2452] sram->in sram[2452]->out sram[2452]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2452]->out) 0 -.nodeset V(sram[2452]->outb) vsp -Xsram[2453] sram->in sram[2453]->out sram[2453]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2453]->out) 0 -.nodeset V(sram[2453]->outb) vsp -Xsram[2454] sram->in sram[2454]->out sram[2454]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2454]->out) 0 -.nodeset V(sram[2454]->outb) vsp -Xsram[2455] sram->in sram[2455]->out sram[2455]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2455]->out) 0 -.nodeset V(sram[2455]->outb) vsp -Xsram[2456] sram->in sram[2456]->out sram[2456]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2456]->out) 0 -.nodeset V(sram[2456]->outb) vsp -Xsram[2457] sram->in sram[2457]->out sram[2457]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2457]->out) 0 -.nodeset V(sram[2457]->outb) vsp -Xmux_2level_tapbuf_size16[47] chany[0][1]_midout[0] chany[0][1]_midout[1] chany[0][1]_midout[14] chany[0][1]_midout[15] chany[0][1]_midout[26] chany[0][1]_midout[27] chany[0][1]_midout[38] chany[0][1]_midout[39] chany[0][1]_midout[50] chany[0][1]_midout[51] chany[0][1]_midout[64] chany[0][1]_midout[65] chany[0][1]_midout[76] chany[0][1]_midout[77] chany[0][1]_midout[88] chany[0][1]_midout[89] grid[0][1]_pin[0][1][2] sram[2458]->outb sram[2458]->out sram[2459]->out sram[2459]->outb sram[2460]->out sram[2460]->outb sram[2461]->out sram[2461]->outb sram[2462]->outb sram[2462]->out sram[2463]->out sram[2463]->outb sram[2464]->out sram[2464]->outb sram[2465]->out sram[2465]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[47], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2458] sram->in sram[2458]->out sram[2458]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2458]->out) 0 -.nodeset V(sram[2458]->outb) vsp -Xsram[2459] sram->in sram[2459]->out sram[2459]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2459]->out) 0 -.nodeset V(sram[2459]->outb) vsp -Xsram[2460] sram->in sram[2460]->out sram[2460]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2460]->out) 0 -.nodeset V(sram[2460]->outb) vsp -Xsram[2461] sram->in sram[2461]->out sram[2461]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2461]->out) 0 -.nodeset V(sram[2461]->outb) vsp -Xsram[2462] sram->in sram[2462]->out sram[2462]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2462]->out) 0 -.nodeset V(sram[2462]->outb) vsp -Xsram[2463] sram->in sram[2463]->out sram[2463]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2463]->out) 0 -.nodeset V(sram[2463]->outb) vsp -Xsram[2464] sram->in sram[2464]->out sram[2464]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2464]->out) 0 -.nodeset V(sram[2464]->outb) vsp -Xsram[2465] sram->in sram[2465]->out sram[2465]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2465]->out) 0 -.nodeset V(sram[2465]->outb) vsp -Xmux_2level_tapbuf_size16[48] chany[0][1]_midout[2] chany[0][1]_midout[3] chany[0][1]_midout[16] chany[0][1]_midout[17] chany[0][1]_midout[28] chany[0][1]_midout[29] chany[0][1]_midout[40] chany[0][1]_midout[41] chany[0][1]_midout[52] chany[0][1]_midout[53] chany[0][1]_midout[66] chany[0][1]_midout[67] chany[0][1]_midout[78] chany[0][1]_midout[79] chany[0][1]_midout[90] chany[0][1]_midout[91] grid[0][1]_pin[0][1][4] sram[2466]->outb sram[2466]->out sram[2467]->out sram[2467]->outb sram[2468]->out sram[2468]->outb sram[2469]->out sram[2469]->outb sram[2470]->outb sram[2470]->out sram[2471]->out sram[2471]->outb sram[2472]->out sram[2472]->outb sram[2473]->out sram[2473]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[48], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2466] sram->in sram[2466]->out sram[2466]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2466]->out) 0 -.nodeset V(sram[2466]->outb) vsp -Xsram[2467] sram->in sram[2467]->out sram[2467]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2467]->out) 0 -.nodeset V(sram[2467]->outb) vsp -Xsram[2468] sram->in sram[2468]->out sram[2468]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2468]->out) 0 -.nodeset V(sram[2468]->outb) vsp -Xsram[2469] sram->in sram[2469]->out sram[2469]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2469]->out) 0 -.nodeset V(sram[2469]->outb) vsp -Xsram[2470] sram->in sram[2470]->out sram[2470]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2470]->out) 0 -.nodeset V(sram[2470]->outb) vsp -Xsram[2471] sram->in sram[2471]->out sram[2471]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2471]->out) 0 -.nodeset V(sram[2471]->outb) vsp -Xsram[2472] sram->in sram[2472]->out sram[2472]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2472]->out) 0 -.nodeset V(sram[2472]->outb) vsp -Xsram[2473] sram->in sram[2473]->out sram[2473]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2473]->out) 0 -.nodeset V(sram[2473]->outb) vsp -Xmux_2level_tapbuf_size16[49] chany[0][1]_midout[4] chany[0][1]_midout[5] chany[0][1]_midout[16] chany[0][1]_midout[17] chany[0][1]_midout[30] chany[0][1]_midout[31] chany[0][1]_midout[42] chany[0][1]_midout[43] chany[0][1]_midout[54] chany[0][1]_midout[55] chany[0][1]_midout[66] chany[0][1]_midout[67] chany[0][1]_midout[80] chany[0][1]_midout[81] chany[0][1]_midout[92] chany[0][1]_midout[93] grid[0][1]_pin[0][1][6] sram[2474]->outb sram[2474]->out sram[2475]->out sram[2475]->outb sram[2476]->out sram[2476]->outb sram[2477]->out sram[2477]->outb sram[2478]->outb sram[2478]->out sram[2479]->out sram[2479]->outb sram[2480]->out sram[2480]->outb sram[2481]->out sram[2481]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[49], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2474] sram->in sram[2474]->out sram[2474]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2474]->out) 0 -.nodeset V(sram[2474]->outb) vsp -Xsram[2475] sram->in sram[2475]->out sram[2475]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2475]->out) 0 -.nodeset V(sram[2475]->outb) vsp -Xsram[2476] sram->in sram[2476]->out sram[2476]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2476]->out) 0 -.nodeset V(sram[2476]->outb) vsp -Xsram[2477] sram->in sram[2477]->out sram[2477]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2477]->out) 0 -.nodeset V(sram[2477]->outb) vsp -Xsram[2478] sram->in sram[2478]->out sram[2478]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2478]->out) 0 -.nodeset V(sram[2478]->outb) vsp -Xsram[2479] sram->in sram[2479]->out sram[2479]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2479]->out) 0 -.nodeset V(sram[2479]->outb) vsp -Xsram[2480] sram->in sram[2480]->out sram[2480]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2480]->out) 0 -.nodeset V(sram[2480]->outb) vsp -Xsram[2481] sram->in sram[2481]->out sram[2481]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2481]->out) 0 -.nodeset V(sram[2481]->outb) vsp -Xmux_2level_tapbuf_size16[50] chany[0][1]_midout[6] chany[0][1]_midout[7] chany[0][1]_midout[18] chany[0][1]_midout[19] chany[0][1]_midout[30] chany[0][1]_midout[31] chany[0][1]_midout[44] chany[0][1]_midout[45] chany[0][1]_midout[56] chany[0][1]_midout[57] chany[0][1]_midout[68] chany[0][1]_midout[69] chany[0][1]_midout[80] chany[0][1]_midout[81] chany[0][1]_midout[94] chany[0][1]_midout[95] grid[0][1]_pin[0][1][8] sram[2482]->outb sram[2482]->out sram[2483]->out sram[2483]->outb sram[2484]->out sram[2484]->outb sram[2485]->out sram[2485]->outb sram[2486]->outb sram[2486]->out sram[2487]->out sram[2487]->outb sram[2488]->out sram[2488]->outb sram[2489]->out sram[2489]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[50], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2482] sram->in sram[2482]->out sram[2482]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2482]->out) 0 -.nodeset V(sram[2482]->outb) vsp -Xsram[2483] sram->in sram[2483]->out sram[2483]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2483]->out) 0 -.nodeset V(sram[2483]->outb) vsp -Xsram[2484] sram->in sram[2484]->out sram[2484]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2484]->out) 0 -.nodeset V(sram[2484]->outb) vsp -Xsram[2485] sram->in sram[2485]->out sram[2485]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2485]->out) 0 -.nodeset V(sram[2485]->outb) vsp -Xsram[2486] sram->in sram[2486]->out sram[2486]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2486]->out) 0 -.nodeset V(sram[2486]->outb) vsp -Xsram[2487] sram->in sram[2487]->out sram[2487]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2487]->out) 0 -.nodeset V(sram[2487]->outb) vsp -Xsram[2488] sram->in sram[2488]->out sram[2488]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2488]->out) 0 -.nodeset V(sram[2488]->outb) vsp -Xsram[2489] sram->in sram[2489]->out sram[2489]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2489]->out) 0 -.nodeset V(sram[2489]->outb) vsp -Xmux_2level_tapbuf_size16[51] chany[0][1]_midout[8] chany[0][1]_midout[9] chany[0][1]_midout[20] chany[0][1]_midout[21] chany[0][1]_midout[32] chany[0][1]_midout[33] chany[0][1]_midout[44] chany[0][1]_midout[45] chany[0][1]_midout[58] chany[0][1]_midout[59] chany[0][1]_midout[70] chany[0][1]_midout[71] chany[0][1]_midout[82] chany[0][1]_midout[83] chany[0][1]_midout[94] chany[0][1]_midout[95] grid[0][1]_pin[0][1][10] sram[2490]->outb sram[2490]->out sram[2491]->out sram[2491]->outb sram[2492]->out sram[2492]->outb sram[2493]->out sram[2493]->outb sram[2494]->outb sram[2494]->out sram[2495]->out sram[2495]->outb sram[2496]->out sram[2496]->outb sram[2497]->out sram[2497]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[51], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2490] sram->in sram[2490]->out sram[2490]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2490]->out) 0 -.nodeset V(sram[2490]->outb) vsp -Xsram[2491] sram->in sram[2491]->out sram[2491]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2491]->out) 0 -.nodeset V(sram[2491]->outb) vsp -Xsram[2492] sram->in sram[2492]->out sram[2492]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2492]->out) 0 -.nodeset V(sram[2492]->outb) vsp -Xsram[2493] sram->in sram[2493]->out sram[2493]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2493]->out) 0 -.nodeset V(sram[2493]->outb) vsp -Xsram[2494] sram->in sram[2494]->out sram[2494]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2494]->out) 0 -.nodeset V(sram[2494]->outb) vsp -Xsram[2495] sram->in sram[2495]->out sram[2495]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2495]->out) 0 -.nodeset V(sram[2495]->outb) vsp -Xsram[2496] sram->in sram[2496]->out sram[2496]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2496]->out) 0 -.nodeset V(sram[2496]->outb) vsp -Xsram[2497] sram->in sram[2497]->out sram[2497]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2497]->out) 0 -.nodeset V(sram[2497]->outb) vsp -Xmux_2level_tapbuf_size16[52] chany[0][1]_midout[8] chany[0][1]_midout[9] chany[0][1]_midout[22] chany[0][1]_midout[23] chany[0][1]_midout[34] chany[0][1]_midout[35] chany[0][1]_midout[46] chany[0][1]_midout[47] chany[0][1]_midout[58] chany[0][1]_midout[59] chany[0][1]_midout[72] chany[0][1]_midout[73] chany[0][1]_midout[84] chany[0][1]_midout[85] chany[0][1]_midout[96] chany[0][1]_midout[97] grid[0][1]_pin[0][1][12] sram[2498]->outb sram[2498]->out sram[2499]->out sram[2499]->outb sram[2500]->out sram[2500]->outb sram[2501]->out sram[2501]->outb sram[2502]->outb sram[2502]->out sram[2503]->out sram[2503]->outb sram[2504]->out sram[2504]->outb sram[2505]->out sram[2505]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[52], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2498] sram->in sram[2498]->out sram[2498]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2498]->out) 0 -.nodeset V(sram[2498]->outb) vsp -Xsram[2499] sram->in sram[2499]->out sram[2499]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2499]->out) 0 -.nodeset V(sram[2499]->outb) vsp -Xsram[2500] sram->in sram[2500]->out sram[2500]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2500]->out) 0 -.nodeset V(sram[2500]->outb) vsp -Xsram[2501] sram->in sram[2501]->out sram[2501]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2501]->out) 0 -.nodeset V(sram[2501]->outb) vsp -Xsram[2502] sram->in sram[2502]->out sram[2502]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2502]->out) 0 -.nodeset V(sram[2502]->outb) vsp -Xsram[2503] sram->in sram[2503]->out sram[2503]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2503]->out) 0 -.nodeset V(sram[2503]->outb) vsp -Xsram[2504] sram->in sram[2504]->out sram[2504]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2504]->out) 0 -.nodeset V(sram[2504]->outb) vsp -Xsram[2505] sram->in sram[2505]->out sram[2505]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2505]->out) 0 -.nodeset V(sram[2505]->outb) vsp -Xmux_2level_tapbuf_size16[53] chany[0][1]_midout[10] chany[0][1]_midout[11] chany[0][1]_midout[22] chany[0][1]_midout[23] chany[0][1]_midout[36] chany[0][1]_midout[37] chany[0][1]_midout[48] chany[0][1]_midout[49] chany[0][1]_midout[60] chany[0][1]_midout[61] chany[0][1]_midout[72] chany[0][1]_midout[73] chany[0][1]_midout[86] chany[0][1]_midout[87] chany[0][1]_midout[98] chany[0][1]_midout[99] grid[0][1]_pin[0][1][14] sram[2506]->outb sram[2506]->out sram[2507]->out sram[2507]->outb sram[2508]->out sram[2508]->outb sram[2509]->out sram[2509]->outb sram[2510]->outb sram[2510]->out sram[2511]->out sram[2511]->outb sram[2512]->out sram[2512]->outb sram[2513]->out sram[2513]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[53], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2506] sram->in sram[2506]->out sram[2506]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2506]->out) 0 -.nodeset V(sram[2506]->outb) vsp -Xsram[2507] sram->in sram[2507]->out sram[2507]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2507]->out) 0 -.nodeset V(sram[2507]->outb) vsp -Xsram[2508] sram->in sram[2508]->out sram[2508]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2508]->out) 0 -.nodeset V(sram[2508]->outb) vsp -Xsram[2509] sram->in sram[2509]->out sram[2509]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2509]->out) 0 -.nodeset V(sram[2509]->outb) vsp -Xsram[2510] sram->in sram[2510]->out sram[2510]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2510]->out) 0 -.nodeset V(sram[2510]->outb) vsp -Xsram[2511] sram->in sram[2511]->out sram[2511]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2511]->out) 0 -.nodeset V(sram[2511]->outb) vsp -Xsram[2512] sram->in sram[2512]->out sram[2512]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2512]->out) 0 -.nodeset V(sram[2512]->outb) vsp -Xsram[2513] sram->in sram[2513]->out sram[2513]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2513]->out) 0 -.nodeset V(sram[2513]->outb) vsp -.eom diff --git a/examples/spice_test_example_2/subckt/cby_1_1.sp b/examples/spice_test_example_2/subckt/cby_1_1.sp deleted file mode 100644 index 4ec8cd4d0..000000000 --- a/examples/spice_test_example_2/subckt/cby_1_1.sp +++ /dev/null @@ -1,615 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Connection Block Y-channel [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -.subckt cby[1][1] -+ chany[1][1]_midout[0] -+ chany[1][1]_midout[1] -+ chany[1][1]_midout[2] -+ chany[1][1]_midout[3] -+ chany[1][1]_midout[4] -+ chany[1][1]_midout[5] -+ chany[1][1]_midout[6] -+ chany[1][1]_midout[7] -+ chany[1][1]_midout[8] -+ chany[1][1]_midout[9] -+ chany[1][1]_midout[10] -+ chany[1][1]_midout[11] -+ chany[1][1]_midout[12] -+ chany[1][1]_midout[13] -+ chany[1][1]_midout[14] -+ chany[1][1]_midout[15] -+ chany[1][1]_midout[16] -+ chany[1][1]_midout[17] -+ chany[1][1]_midout[18] -+ chany[1][1]_midout[19] -+ chany[1][1]_midout[20] -+ chany[1][1]_midout[21] -+ chany[1][1]_midout[22] -+ chany[1][1]_midout[23] -+ chany[1][1]_midout[24] -+ chany[1][1]_midout[25] -+ chany[1][1]_midout[26] -+ chany[1][1]_midout[27] -+ chany[1][1]_midout[28] -+ chany[1][1]_midout[29] -+ chany[1][1]_midout[30] -+ chany[1][1]_midout[31] -+ chany[1][1]_midout[32] -+ chany[1][1]_midout[33] -+ chany[1][1]_midout[34] -+ chany[1][1]_midout[35] -+ chany[1][1]_midout[36] -+ chany[1][1]_midout[37] -+ chany[1][1]_midout[38] -+ chany[1][1]_midout[39] -+ chany[1][1]_midout[40] -+ chany[1][1]_midout[41] -+ chany[1][1]_midout[42] -+ chany[1][1]_midout[43] -+ chany[1][1]_midout[44] -+ chany[1][1]_midout[45] -+ chany[1][1]_midout[46] -+ chany[1][1]_midout[47] -+ chany[1][1]_midout[48] -+ chany[1][1]_midout[49] -+ chany[1][1]_midout[50] -+ chany[1][1]_midout[51] -+ chany[1][1]_midout[52] -+ chany[1][1]_midout[53] -+ chany[1][1]_midout[54] -+ chany[1][1]_midout[55] -+ chany[1][1]_midout[56] -+ chany[1][1]_midout[57] -+ chany[1][1]_midout[58] -+ chany[1][1]_midout[59] -+ chany[1][1]_midout[60] -+ chany[1][1]_midout[61] -+ chany[1][1]_midout[62] -+ chany[1][1]_midout[63] -+ chany[1][1]_midout[64] -+ chany[1][1]_midout[65] -+ chany[1][1]_midout[66] -+ chany[1][1]_midout[67] -+ chany[1][1]_midout[68] -+ chany[1][1]_midout[69] -+ chany[1][1]_midout[70] -+ chany[1][1]_midout[71] -+ chany[1][1]_midout[72] -+ chany[1][1]_midout[73] -+ chany[1][1]_midout[74] -+ chany[1][1]_midout[75] -+ chany[1][1]_midout[76] -+ chany[1][1]_midout[77] -+ chany[1][1]_midout[78] -+ chany[1][1]_midout[79] -+ chany[1][1]_midout[80] -+ chany[1][1]_midout[81] -+ chany[1][1]_midout[82] -+ chany[1][1]_midout[83] -+ chany[1][1]_midout[84] -+ chany[1][1]_midout[85] -+ chany[1][1]_midout[86] -+ chany[1][1]_midout[87] -+ chany[1][1]_midout[88] -+ chany[1][1]_midout[89] -+ chany[1][1]_midout[90] -+ chany[1][1]_midout[91] -+ chany[1][1]_midout[92] -+ chany[1][1]_midout[93] -+ chany[1][1]_midout[94] -+ chany[1][1]_midout[95] -+ chany[1][1]_midout[96] -+ chany[1][1]_midout[97] -+ chany[1][1]_midout[98] -+ chany[1][1]_midout[99] -+ grid[2][1]_pin[0][3][0] -+ grid[2][1]_pin[0][3][2] -+ grid[2][1]_pin[0][3][4] -+ grid[2][1]_pin[0][3][6] -+ grid[2][1]_pin[0][3][8] -+ grid[2][1]_pin[0][3][10] -+ grid[2][1]_pin[0][3][12] -+ grid[2][1]_pin[0][3][14] -+ grid[1][1]_pin[0][1][1] -+ grid[1][1]_pin[0][1][5] -+ grid[1][1]_pin[0][1][9] -+ grid[1][1]_pin[0][1][13] -+ grid[1][1]_pin[0][1][17] -+ grid[1][1]_pin[0][1][21] -+ grid[1][1]_pin[0][1][25] -+ grid[1][1]_pin[0][1][29] -+ grid[1][1]_pin[0][1][33] -+ grid[1][1]_pin[0][1][37] -+ svdd sgnd -Xmux_2level_tapbuf_size16[54] chany[1][1]_midout[6] chany[1][1]_midout[7] chany[1][1]_midout[10] chany[1][1]_midout[11] chany[1][1]_midout[24] chany[1][1]_midout[25] chany[1][1]_midout[36] chany[1][1]_midout[37] chany[1][1]_midout[48] chany[1][1]_midout[49] chany[1][1]_midout[60] chany[1][1]_midout[61] chany[1][1]_midout[76] chany[1][1]_midout[77] chany[1][1]_midout[88] chany[1][1]_midout[89] grid[2][1]_pin[0][3][0] sram[2514]->outb sram[2514]->out sram[2515]->out sram[2515]->outb sram[2516]->out sram[2516]->outb sram[2517]->out sram[2517]->outb sram[2518]->outb sram[2518]->out sram[2519]->out sram[2519]->outb sram[2520]->out sram[2520]->outb sram[2521]->out sram[2521]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[54], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2514] sram->in sram[2514]->out sram[2514]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2514]->out) 0 -.nodeset V(sram[2514]->outb) vsp -Xsram[2515] sram->in sram[2515]->out sram[2515]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2515]->out) 0 -.nodeset V(sram[2515]->outb) vsp -Xsram[2516] sram->in sram[2516]->out sram[2516]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2516]->out) 0 -.nodeset V(sram[2516]->outb) vsp -Xsram[2517] sram->in sram[2517]->out sram[2517]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2517]->out) 0 -.nodeset V(sram[2517]->outb) vsp -Xsram[2518] sram->in sram[2518]->out sram[2518]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2518]->out) 0 -.nodeset V(sram[2518]->outb) vsp -Xsram[2519] sram->in sram[2519]->out sram[2519]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2519]->out) 0 -.nodeset V(sram[2519]->outb) vsp -Xsram[2520] sram->in sram[2520]->out sram[2520]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2520]->out) 0 -.nodeset V(sram[2520]->outb) vsp -Xsram[2521] sram->in sram[2521]->out sram[2521]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2521]->out) 0 -.nodeset V(sram[2521]->outb) vsp -Xmux_2level_tapbuf_size16[55] chany[1][1]_midout[0] chany[1][1]_midout[1] chany[1][1]_midout[12] chany[1][1]_midout[13] chany[1][1]_midout[24] chany[1][1]_midout[25] chany[1][1]_midout[42] chany[1][1]_midout[43] chany[1][1]_midout[54] chany[1][1]_midout[55] chany[1][1]_midout[66] chany[1][1]_midout[67] chany[1][1]_midout[76] chany[1][1]_midout[77] chany[1][1]_midout[90] chany[1][1]_midout[91] grid[2][1]_pin[0][3][2] sram[2522]->outb sram[2522]->out sram[2523]->out sram[2523]->outb sram[2524]->out sram[2524]->outb sram[2525]->out sram[2525]->outb sram[2526]->outb sram[2526]->out sram[2527]->out sram[2527]->outb sram[2528]->out sram[2528]->outb sram[2529]->out sram[2529]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[55], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2522] sram->in sram[2522]->out sram[2522]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2522]->out) 0 -.nodeset V(sram[2522]->outb) vsp -Xsram[2523] sram->in sram[2523]->out sram[2523]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2523]->out) 0 -.nodeset V(sram[2523]->outb) vsp -Xsram[2524] sram->in sram[2524]->out sram[2524]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2524]->out) 0 -.nodeset V(sram[2524]->outb) vsp -Xsram[2525] sram->in sram[2525]->out sram[2525]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2525]->out) 0 -.nodeset V(sram[2525]->outb) vsp -Xsram[2526] sram->in sram[2526]->out sram[2526]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2526]->out) 0 -.nodeset V(sram[2526]->outb) vsp -Xsram[2527] sram->in sram[2527]->out sram[2527]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2527]->out) 0 -.nodeset V(sram[2527]->outb) vsp -Xsram[2528] sram->in sram[2528]->out sram[2528]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2528]->out) 0 -.nodeset V(sram[2528]->outb) vsp -Xsram[2529] sram->in sram[2529]->out sram[2529]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2529]->out) 0 -.nodeset V(sram[2529]->outb) vsp -Xmux_2level_tapbuf_size16[56] chany[1][1]_midout[2] chany[1][1]_midout[3] chany[1][1]_midout[22] chany[1][1]_midout[23] chany[1][1]_midout[26] chany[1][1]_midout[27] chany[1][1]_midout[42] chany[1][1]_midout[43] chany[1][1]_midout[52] chany[1][1]_midout[53] chany[1][1]_midout[64] chany[1][1]_midout[65] chany[1][1]_midout[78] chany[1][1]_midout[79] chany[1][1]_midout[90] chany[1][1]_midout[91] grid[2][1]_pin[0][3][4] sram[2530]->outb sram[2530]->out sram[2531]->out sram[2531]->outb sram[2532]->out sram[2532]->outb sram[2533]->out sram[2533]->outb sram[2534]->outb sram[2534]->out sram[2535]->out sram[2535]->outb sram[2536]->out sram[2536]->outb sram[2537]->out sram[2537]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[56], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2530] sram->in sram[2530]->out sram[2530]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2530]->out) 0 -.nodeset V(sram[2530]->outb) vsp -Xsram[2531] sram->in sram[2531]->out sram[2531]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2531]->out) 0 -.nodeset V(sram[2531]->outb) vsp -Xsram[2532] sram->in sram[2532]->out sram[2532]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2532]->out) 0 -.nodeset V(sram[2532]->outb) vsp -Xsram[2533] sram->in sram[2533]->out sram[2533]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2533]->out) 0 -.nodeset V(sram[2533]->outb) vsp -Xsram[2534] sram->in sram[2534]->out sram[2534]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2534]->out) 0 -.nodeset V(sram[2534]->outb) vsp -Xsram[2535] sram->in sram[2535]->out sram[2535]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2535]->out) 0 -.nodeset V(sram[2535]->outb) vsp -Xsram[2536] sram->in sram[2536]->out sram[2536]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2536]->out) 0 -.nodeset V(sram[2536]->outb) vsp -Xsram[2537] sram->in sram[2537]->out sram[2537]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2537]->out) 0 -.nodeset V(sram[2537]->outb) vsp -Xmux_2level_tapbuf_size16[57] chany[1][1]_midout[2] chany[1][1]_midout[3] chany[1][1]_midout[16] chany[1][1]_midout[17] chany[1][1]_midout[28] chany[1][1]_midout[29] chany[1][1]_midout[40] chany[1][1]_midout[41] chany[1][1]_midout[52] chany[1][1]_midout[53] chany[1][1]_midout[68] chany[1][1]_midout[69] chany[1][1]_midout[80] chany[1][1]_midout[81] chany[1][1]_midout[92] chany[1][1]_midout[93] grid[2][1]_pin[0][3][6] sram[2538]->outb sram[2538]->out sram[2539]->out sram[2539]->outb sram[2540]->out sram[2540]->outb sram[2541]->out sram[2541]->outb sram[2542]->outb sram[2542]->out sram[2543]->out sram[2543]->outb sram[2544]->out sram[2544]->outb sram[2545]->out sram[2545]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[57], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2538] sram->in sram[2538]->out sram[2538]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2538]->out) 0 -.nodeset V(sram[2538]->outb) vsp -Xsram[2539] sram->in sram[2539]->out sram[2539]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2539]->out) 0 -.nodeset V(sram[2539]->outb) vsp -Xsram[2540] sram->in sram[2540]->out sram[2540]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2540]->out) 0 -.nodeset V(sram[2540]->outb) vsp -Xsram[2541] sram->in sram[2541]->out sram[2541]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2541]->out) 0 -.nodeset V(sram[2541]->outb) vsp -Xsram[2542] sram->in sram[2542]->out sram[2542]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2542]->out) 0 -.nodeset V(sram[2542]->outb) vsp -Xsram[2543] sram->in sram[2543]->out sram[2543]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2543]->out) 0 -.nodeset V(sram[2543]->outb) vsp -Xsram[2544] sram->in sram[2544]->out sram[2544]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2544]->out) 0 -.nodeset V(sram[2544]->outb) vsp -Xsram[2545] sram->in sram[2545]->out sram[2545]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2545]->out) 0 -.nodeset V(sram[2545]->outb) vsp -Xmux_2level_tapbuf_size16[58] chany[1][1]_midout[4] chany[1][1]_midout[5] chany[1][1]_midout[16] chany[1][1]_midout[17] chany[1][1]_midout[38] chany[1][1]_midout[39] chany[1][1]_midout[46] chany[1][1]_midout[47] chany[1][1]_midout[58] chany[1][1]_midout[59] chany[1][1]_midout[68] chany[1][1]_midout[69] chany[1][1]_midout[82] chany[1][1]_midout[83] chany[1][1]_midout[94] chany[1][1]_midout[95] grid[2][1]_pin[0][3][8] sram[2546]->outb sram[2546]->out sram[2547]->out sram[2547]->outb sram[2548]->out sram[2548]->outb sram[2549]->out sram[2549]->outb sram[2550]->outb sram[2550]->out sram[2551]->out sram[2551]->outb sram[2552]->out sram[2552]->outb sram[2553]->out sram[2553]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[58], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2546] sram->in sram[2546]->out sram[2546]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2546]->out) 0 -.nodeset V(sram[2546]->outb) vsp -Xsram[2547] sram->in sram[2547]->out sram[2547]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2547]->out) 0 -.nodeset V(sram[2547]->outb) vsp -Xsram[2548] sram->in sram[2548]->out sram[2548]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2548]->out) 0 -.nodeset V(sram[2548]->outb) vsp -Xsram[2549] sram->in sram[2549]->out sram[2549]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2549]->out) 0 -.nodeset V(sram[2549]->outb) vsp -Xsram[2550] sram->in sram[2550]->out sram[2550]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2550]->out) 0 -.nodeset V(sram[2550]->outb) vsp -Xsram[2551] sram->in sram[2551]->out sram[2551]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2551]->out) 0 -.nodeset V(sram[2551]->outb) vsp -Xsram[2552] sram->in sram[2552]->out sram[2552]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2552]->out) 0 -.nodeset V(sram[2552]->outb) vsp -Xsram[2553] sram->in sram[2553]->out sram[2553]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2553]->out) 0 -.nodeset V(sram[2553]->outb) vsp -Xmux_2level_tapbuf_size16[59] chany[1][1]_midout[14] chany[1][1]_midout[15] chany[1][1]_midout[18] chany[1][1]_midout[19] chany[1][1]_midout[38] chany[1][1]_midout[39] chany[1][1]_midout[44] chany[1][1]_midout[45] chany[1][1]_midout[56] chany[1][1]_midout[57] chany[1][1]_midout[70] chany[1][1]_midout[71] chany[1][1]_midout[82] chany[1][1]_midout[83] chany[1][1]_midout[96] chany[1][1]_midout[97] grid[2][1]_pin[0][3][10] sram[2554]->outb sram[2554]->out sram[2555]->out sram[2555]->outb sram[2556]->out sram[2556]->outb sram[2557]->out sram[2557]->outb sram[2558]->outb sram[2558]->out sram[2559]->out sram[2559]->outb sram[2560]->out sram[2560]->outb sram[2561]->out sram[2561]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[59], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2554] sram->in sram[2554]->out sram[2554]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2554]->out) 0 -.nodeset V(sram[2554]->outb) vsp -Xsram[2555] sram->in sram[2555]->out sram[2555]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2555]->out) 0 -.nodeset V(sram[2555]->outb) vsp -Xsram[2556] sram->in sram[2556]->out sram[2556]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2556]->out) 0 -.nodeset V(sram[2556]->outb) vsp -Xsram[2557] sram->in sram[2557]->out sram[2557]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2557]->out) 0 -.nodeset V(sram[2557]->outb) vsp -Xsram[2558] sram->in sram[2558]->out sram[2558]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2558]->out) 0 -.nodeset V(sram[2558]->outb) vsp -Xsram[2559] sram->in sram[2559]->out sram[2559]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2559]->out) 0 -.nodeset V(sram[2559]->outb) vsp -Xsram[2560] sram->in sram[2560]->out sram[2560]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2560]->out) 0 -.nodeset V(sram[2560]->outb) vsp -Xsram[2561] sram->in sram[2561]->out sram[2561]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2561]->out) 0 -.nodeset V(sram[2561]->outb) vsp -Xmux_2level_tapbuf_size16[60] chany[1][1]_midout[8] chany[1][1]_midout[9] chany[1][1]_midout[20] chany[1][1]_midout[21] chany[1][1]_midout[32] chany[1][1]_midout[33] chany[1][1]_midout[50] chany[1][1]_midout[51] chany[1][1]_midout[62] chany[1][1]_midout[63] chany[1][1]_midout[72] chany[1][1]_midout[73] chany[1][1]_midout[84] chany[1][1]_midout[85] chany[1][1]_midout[98] chany[1][1]_midout[99] grid[2][1]_pin[0][3][12] sram[2562]->outb sram[2562]->out sram[2563]->out sram[2563]->outb sram[2564]->out sram[2564]->outb sram[2565]->out sram[2565]->outb sram[2566]->outb sram[2566]->out sram[2567]->out sram[2567]->outb sram[2568]->out sram[2568]->outb sram[2569]->out sram[2569]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[60], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2562] sram->in sram[2562]->out sram[2562]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2562]->out) 0 -.nodeset V(sram[2562]->outb) vsp -Xsram[2563] sram->in sram[2563]->out sram[2563]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2563]->out) 0 -.nodeset V(sram[2563]->outb) vsp -Xsram[2564] sram->in sram[2564]->out sram[2564]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2564]->out) 0 -.nodeset V(sram[2564]->outb) vsp -Xsram[2565] sram->in sram[2565]->out sram[2565]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2565]->out) 0 -.nodeset V(sram[2565]->outb) vsp -Xsram[2566] sram->in sram[2566]->out sram[2566]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2566]->out) 0 -.nodeset V(sram[2566]->outb) vsp -Xsram[2567] sram->in sram[2567]->out sram[2567]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2567]->out) 0 -.nodeset V(sram[2567]->outb) vsp -Xsram[2568] sram->in sram[2568]->out sram[2568]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2568]->out) 0 -.nodeset V(sram[2568]->outb) vsp -Xsram[2569] sram->in sram[2569]->out sram[2569]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2569]->out) 0 -.nodeset V(sram[2569]->outb) vsp -Xmux_2level_tapbuf_size16[61] chany[1][1]_midout[10] chany[1][1]_midout[11] chany[1][1]_midout[30] chany[1][1]_midout[31] chany[1][1]_midout[34] chany[1][1]_midout[35] chany[1][1]_midout[50] chany[1][1]_midout[51] chany[1][1]_midout[60] chany[1][1]_midout[61] chany[1][1]_midout[74] chany[1][1]_midout[75] chany[1][1]_midout[86] chany[1][1]_midout[87] chany[1][1]_midout[98] chany[1][1]_midout[99] grid[2][1]_pin[0][3][14] sram[2570]->outb sram[2570]->out sram[2571]->out sram[2571]->outb sram[2572]->out sram[2572]->outb sram[2573]->out sram[2573]->outb sram[2574]->outb sram[2574]->out sram[2575]->out sram[2575]->outb sram[2576]->out sram[2576]->outb sram[2577]->out sram[2577]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[61], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2570] sram->in sram[2570]->out sram[2570]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2570]->out) 0 -.nodeset V(sram[2570]->outb) vsp -Xsram[2571] sram->in sram[2571]->out sram[2571]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2571]->out) 0 -.nodeset V(sram[2571]->outb) vsp -Xsram[2572] sram->in sram[2572]->out sram[2572]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2572]->out) 0 -.nodeset V(sram[2572]->outb) vsp -Xsram[2573] sram->in sram[2573]->out sram[2573]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2573]->out) 0 -.nodeset V(sram[2573]->outb) vsp -Xsram[2574] sram->in sram[2574]->out sram[2574]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2574]->out) 0 -.nodeset V(sram[2574]->outb) vsp -Xsram[2575] sram->in sram[2575]->out sram[2575]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2575]->out) 0 -.nodeset V(sram[2575]->outb) vsp -Xsram[2576] sram->in sram[2576]->out sram[2576]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2576]->out) 0 -.nodeset V(sram[2576]->outb) vsp -Xsram[2577] sram->in sram[2577]->out sram[2577]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2577]->out) 0 -.nodeset V(sram[2577]->outb) vsp -Xmux_2level_tapbuf_size16[62] chany[1][1]_midout[6] chany[1][1]_midout[7] chany[1][1]_midout[10] chany[1][1]_midout[11] chany[1][1]_midout[30] chany[1][1]_midout[31] chany[1][1]_midout[34] chany[1][1]_midout[35] chany[1][1]_midout[48] chany[1][1]_midout[49] chany[1][1]_midout[60] chany[1][1]_midout[61] chany[1][1]_midout[74] chany[1][1]_midout[75] chany[1][1]_midout[86] chany[1][1]_midout[87] grid[1][1]_pin[0][1][1] sram[2578]->outb sram[2578]->out sram[2579]->out sram[2579]->outb sram[2580]->out sram[2580]->outb sram[2581]->out sram[2581]->outb sram[2582]->outb sram[2582]->out sram[2583]->out sram[2583]->outb sram[2584]->out sram[2584]->outb sram[2585]->out sram[2585]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[62], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2578] sram->in sram[2578]->out sram[2578]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2578]->out) 0 -.nodeset V(sram[2578]->outb) vsp -Xsram[2579] sram->in sram[2579]->out sram[2579]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2579]->out) 0 -.nodeset V(sram[2579]->outb) vsp -Xsram[2580] sram->in sram[2580]->out sram[2580]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2580]->out) 0 -.nodeset V(sram[2580]->outb) vsp -Xsram[2581] sram->in sram[2581]->out sram[2581]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2581]->out) 0 -.nodeset V(sram[2581]->outb) vsp -Xsram[2582] sram->in sram[2582]->out sram[2582]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2582]->out) 0 -.nodeset V(sram[2582]->outb) vsp -Xsram[2583] sram->in sram[2583]->out sram[2583]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2583]->out) 0 -.nodeset V(sram[2583]->outb) vsp -Xsram[2584] sram->in sram[2584]->out sram[2584]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2584]->out) 0 -.nodeset V(sram[2584]->outb) vsp -Xsram[2585] sram->in sram[2585]->out sram[2585]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2585]->out) 0 -.nodeset V(sram[2585]->outb) vsp -Xmux_2level_tapbuf_size16[63] chany[1][1]_midout[6] chany[1][1]_midout[7] chany[1][1]_midout[12] chany[1][1]_midout[13] chany[1][1]_midout[24] chany[1][1]_midout[25] chany[1][1]_midout[36] chany[1][1]_midout[37] chany[1][1]_midout[48] chany[1][1]_midout[49] chany[1][1]_midout[66] chany[1][1]_midout[67] chany[1][1]_midout[76] chany[1][1]_midout[77] chany[1][1]_midout[88] chany[1][1]_midout[89] grid[1][1]_pin[0][1][5] sram[2586]->outb sram[2586]->out sram[2587]->out sram[2587]->outb sram[2588]->out sram[2588]->outb sram[2589]->out sram[2589]->outb sram[2590]->outb sram[2590]->out sram[2591]->out sram[2591]->outb sram[2592]->out sram[2592]->outb sram[2593]->out sram[2593]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[63], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2586] sram->in sram[2586]->out sram[2586]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2586]->out) 0 -.nodeset V(sram[2586]->outb) vsp -Xsram[2587] sram->in sram[2587]->out sram[2587]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2587]->out) 0 -.nodeset V(sram[2587]->outb) vsp -Xsram[2588] sram->in sram[2588]->out sram[2588]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2588]->out) 0 -.nodeset V(sram[2588]->outb) vsp -Xsram[2589] sram->in sram[2589]->out sram[2589]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2589]->out) 0 -.nodeset V(sram[2589]->outb) vsp -Xsram[2590] sram->in sram[2590]->out sram[2590]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2590]->out) 0 -.nodeset V(sram[2590]->outb) vsp -Xsram[2591] sram->in sram[2591]->out sram[2591]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2591]->out) 0 -.nodeset V(sram[2591]->outb) vsp -Xsram[2592] sram->in sram[2592]->out sram[2592]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2592]->out) 0 -.nodeset V(sram[2592]->outb) vsp -Xsram[2593] sram->in sram[2593]->out sram[2593]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2593]->out) 0 -.nodeset V(sram[2593]->outb) vsp -Xmux_2level_tapbuf_size16[64] chany[1][1]_midout[0] chany[1][1]_midout[1] chany[1][1]_midout[12] chany[1][1]_midout[13] chany[1][1]_midout[24] chany[1][1]_midout[25] chany[1][1]_midout[42] chany[1][1]_midout[43] chany[1][1]_midout[54] chany[1][1]_midout[55] chany[1][1]_midout[66] chany[1][1]_midout[67] chany[1][1]_midout[76] chany[1][1]_midout[77] chany[1][1]_midout[90] chany[1][1]_midout[91] grid[1][1]_pin[0][1][9] sram[2594]->outb sram[2594]->out sram[2595]->out sram[2595]->outb sram[2596]->out sram[2596]->outb sram[2597]->out sram[2597]->outb sram[2598]->outb sram[2598]->out sram[2599]->out sram[2599]->outb sram[2600]->out sram[2600]->outb sram[2601]->out sram[2601]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[64], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2594] sram->in sram[2594]->out sram[2594]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2594]->out) 0 -.nodeset V(sram[2594]->outb) vsp -Xsram[2595] sram->in sram[2595]->out sram[2595]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2595]->out) 0 -.nodeset V(sram[2595]->outb) vsp -Xsram[2596] sram->in sram[2596]->out sram[2596]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2596]->out) 0 -.nodeset V(sram[2596]->outb) vsp -Xsram[2597] sram->in sram[2597]->out sram[2597]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2597]->out) 0 -.nodeset V(sram[2597]->outb) vsp -Xsram[2598] sram->in sram[2598]->out sram[2598]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2598]->out) 0 -.nodeset V(sram[2598]->outb) vsp -Xsram[2599] sram->in sram[2599]->out sram[2599]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2599]->out) 0 -.nodeset V(sram[2599]->outb) vsp -Xsram[2600] sram->in sram[2600]->out sram[2600]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2600]->out) 0 -.nodeset V(sram[2600]->outb) vsp -Xsram[2601] sram->in sram[2601]->out sram[2601]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2601]->out) 0 -.nodeset V(sram[2601]->outb) vsp -Xmux_2level_tapbuf_size16[65] chany[1][1]_midout[2] chany[1][1]_midout[3] chany[1][1]_midout[22] chany[1][1]_midout[23] chany[1][1]_midout[26] chany[1][1]_midout[27] chany[1][1]_midout[42] chany[1][1]_midout[43] chany[1][1]_midout[52] chany[1][1]_midout[53] chany[1][1]_midout[64] chany[1][1]_midout[65] chany[1][1]_midout[78] chany[1][1]_midout[79] chany[1][1]_midout[90] chany[1][1]_midout[91] grid[1][1]_pin[0][1][13] sram[2602]->outb sram[2602]->out sram[2603]->out sram[2603]->outb sram[2604]->out sram[2604]->outb sram[2605]->out sram[2605]->outb sram[2606]->outb sram[2606]->out sram[2607]->out sram[2607]->outb sram[2608]->out sram[2608]->outb sram[2609]->out sram[2609]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[65], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2602] sram->in sram[2602]->out sram[2602]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2602]->out) 0 -.nodeset V(sram[2602]->outb) vsp -Xsram[2603] sram->in sram[2603]->out sram[2603]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2603]->out) 0 -.nodeset V(sram[2603]->outb) vsp -Xsram[2604] sram->in sram[2604]->out sram[2604]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2604]->out) 0 -.nodeset V(sram[2604]->outb) vsp -Xsram[2605] sram->in sram[2605]->out sram[2605]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2605]->out) 0 -.nodeset V(sram[2605]->outb) vsp -Xsram[2606] sram->in sram[2606]->out sram[2606]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2606]->out) 0 -.nodeset V(sram[2606]->outb) vsp -Xsram[2607] sram->in sram[2607]->out sram[2607]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2607]->out) 0 -.nodeset V(sram[2607]->outb) vsp -Xsram[2608] sram->in sram[2608]->out sram[2608]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2608]->out) 0 -.nodeset V(sram[2608]->outb) vsp -Xsram[2609] sram->in sram[2609]->out sram[2609]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2609]->out) 0 -.nodeset V(sram[2609]->outb) vsp -Xmux_2level_tapbuf_size16[66] chany[1][1]_midout[2] chany[1][1]_midout[3] chany[1][1]_midout[22] chany[1][1]_midout[23] chany[1][1]_midout[28] chany[1][1]_midout[29] chany[1][1]_midout[40] chany[1][1]_midout[41] chany[1][1]_midout[52] chany[1][1]_midout[53] chany[1][1]_midout[64] chany[1][1]_midout[65] chany[1][1]_midout[80] chany[1][1]_midout[81] chany[1][1]_midout[92] chany[1][1]_midout[93] grid[1][1]_pin[0][1][17] sram[2610]->outb sram[2610]->out sram[2611]->out sram[2611]->outb sram[2612]->out sram[2612]->outb sram[2613]->out sram[2613]->outb sram[2614]->outb sram[2614]->out sram[2615]->out sram[2615]->outb sram[2616]->out sram[2616]->outb sram[2617]->out sram[2617]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[66], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2610] sram->in sram[2610]->out sram[2610]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2610]->out) 0 -.nodeset V(sram[2610]->outb) vsp -Xsram[2611] sram->in sram[2611]->out sram[2611]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2611]->out) 0 -.nodeset V(sram[2611]->outb) vsp -Xsram[2612] sram->in sram[2612]->out sram[2612]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2612]->out) 0 -.nodeset V(sram[2612]->outb) vsp -Xsram[2613] sram->in sram[2613]->out sram[2613]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2613]->out) 0 -.nodeset V(sram[2613]->outb) vsp -Xsram[2614] sram->in sram[2614]->out sram[2614]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2614]->out) 0 -.nodeset V(sram[2614]->outb) vsp -Xsram[2615] sram->in sram[2615]->out sram[2615]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2615]->out) 0 -.nodeset V(sram[2615]->outb) vsp -Xsram[2616] sram->in sram[2616]->out sram[2616]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2616]->out) 0 -.nodeset V(sram[2616]->outb) vsp -Xsram[2617] sram->in sram[2617]->out sram[2617]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2617]->out) 0 -.nodeset V(sram[2617]->outb) vsp -Xmux_2level_tapbuf_size16[67] chany[1][1]_midout[4] chany[1][1]_midout[5] chany[1][1]_midout[16] chany[1][1]_midout[17] chany[1][1]_midout[28] chany[1][1]_midout[29] chany[1][1]_midout[46] chany[1][1]_midout[47] chany[1][1]_midout[58] chany[1][1]_midout[59] chany[1][1]_midout[68] chany[1][1]_midout[69] chany[1][1]_midout[80] chany[1][1]_midout[81] chany[1][1]_midout[94] chany[1][1]_midout[95] grid[1][1]_pin[0][1][21] sram[2618]->outb sram[2618]->out sram[2619]->out sram[2619]->outb sram[2620]->out sram[2620]->outb sram[2621]->out sram[2621]->outb sram[2622]->outb sram[2622]->out sram[2623]->out sram[2623]->outb sram[2624]->out sram[2624]->outb sram[2625]->out sram[2625]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[67], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2618] sram->in sram[2618]->out sram[2618]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2618]->out) 0 -.nodeset V(sram[2618]->outb) vsp -Xsram[2619] sram->in sram[2619]->out sram[2619]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2619]->out) 0 -.nodeset V(sram[2619]->outb) vsp -Xsram[2620] sram->in sram[2620]->out sram[2620]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2620]->out) 0 -.nodeset V(sram[2620]->outb) vsp -Xsram[2621] sram->in sram[2621]->out sram[2621]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2621]->out) 0 -.nodeset V(sram[2621]->outb) vsp -Xsram[2622] sram->in sram[2622]->out sram[2622]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2622]->out) 0 -.nodeset V(sram[2622]->outb) vsp -Xsram[2623] sram->in sram[2623]->out sram[2623]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2623]->out) 0 -.nodeset V(sram[2623]->outb) vsp -Xsram[2624] sram->in sram[2624]->out sram[2624]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2624]->out) 0 -.nodeset V(sram[2624]->outb) vsp -Xsram[2625] sram->in sram[2625]->out sram[2625]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2625]->out) 0 -.nodeset V(sram[2625]->outb) vsp -Xmux_2level_tapbuf_size16[68] chany[1][1]_midout[4] chany[1][1]_midout[5] chany[1][1]_midout[18] chany[1][1]_midout[19] chany[1][1]_midout[38] chany[1][1]_midout[39] chany[1][1]_midout[46] chany[1][1]_midout[47] chany[1][1]_midout[58] chany[1][1]_midout[59] chany[1][1]_midout[70] chany[1][1]_midout[71] chany[1][1]_midout[82] chany[1][1]_midout[83] chany[1][1]_midout[94] chany[1][1]_midout[95] grid[1][1]_pin[0][1][25] sram[2626]->outb sram[2626]->out sram[2627]->out sram[2627]->outb sram[2628]->out sram[2628]->outb sram[2629]->out sram[2629]->outb sram[2630]->outb sram[2630]->out sram[2631]->out sram[2631]->outb sram[2632]->out sram[2632]->outb sram[2633]->out sram[2633]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[68], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2626] sram->in sram[2626]->out sram[2626]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2626]->out) 0 -.nodeset V(sram[2626]->outb) vsp -Xsram[2627] sram->in sram[2627]->out sram[2627]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2627]->out) 0 -.nodeset V(sram[2627]->outb) vsp -Xsram[2628] sram->in sram[2628]->out sram[2628]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2628]->out) 0 -.nodeset V(sram[2628]->outb) vsp -Xsram[2629] sram->in sram[2629]->out sram[2629]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2629]->out) 0 -.nodeset V(sram[2629]->outb) vsp -Xsram[2630] sram->in sram[2630]->out sram[2630]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2630]->out) 0 -.nodeset V(sram[2630]->outb) vsp -Xsram[2631] sram->in sram[2631]->out sram[2631]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2631]->out) 0 -.nodeset V(sram[2631]->outb) vsp -Xsram[2632] sram->in sram[2632]->out sram[2632]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2632]->out) 0 -.nodeset V(sram[2632]->outb) vsp -Xsram[2633] sram->in sram[2633]->out sram[2633]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2633]->out) 0 -.nodeset V(sram[2633]->outb) vsp -Xmux_2level_tapbuf_size16[69] chany[1][1]_midout[14] chany[1][1]_midout[15] chany[1][1]_midout[18] chany[1][1]_midout[19] chany[1][1]_midout[32] chany[1][1]_midout[33] chany[1][1]_midout[44] chany[1][1]_midout[45] chany[1][1]_midout[56] chany[1][1]_midout[57] chany[1][1]_midout[70] chany[1][1]_midout[71] chany[1][1]_midout[84] chany[1][1]_midout[85] chany[1][1]_midout[96] chany[1][1]_midout[97] grid[1][1]_pin[0][1][29] sram[2634]->outb sram[2634]->out sram[2635]->out sram[2635]->outb sram[2636]->out sram[2636]->outb sram[2637]->out sram[2637]->outb sram[2638]->outb sram[2638]->out sram[2639]->out sram[2639]->outb sram[2640]->out sram[2640]->outb sram[2641]->out sram[2641]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[69], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2634] sram->in sram[2634]->out sram[2634]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2634]->out) 0 -.nodeset V(sram[2634]->outb) vsp -Xsram[2635] sram->in sram[2635]->out sram[2635]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2635]->out) 0 -.nodeset V(sram[2635]->outb) vsp -Xsram[2636] sram->in sram[2636]->out sram[2636]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2636]->out) 0 -.nodeset V(sram[2636]->outb) vsp -Xsram[2637] sram->in sram[2637]->out sram[2637]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2637]->out) 0 -.nodeset V(sram[2637]->outb) vsp -Xsram[2638] sram->in sram[2638]->out sram[2638]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2638]->out) 0 -.nodeset V(sram[2638]->outb) vsp -Xsram[2639] sram->in sram[2639]->out sram[2639]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2639]->out) 0 -.nodeset V(sram[2639]->outb) vsp -Xsram[2640] sram->in sram[2640]->out sram[2640]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2640]->out) 0 -.nodeset V(sram[2640]->outb) vsp -Xsram[2641] sram->in sram[2641]->out sram[2641]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2641]->out) 0 -.nodeset V(sram[2641]->outb) vsp -Xmux_2level_tapbuf_size16[70] chany[1][1]_midout[8] chany[1][1]_midout[9] chany[1][1]_midout[20] chany[1][1]_midout[21] chany[1][1]_midout[32] chany[1][1]_midout[33] chany[1][1]_midout[44] chany[1][1]_midout[45] chany[1][1]_midout[62] chany[1][1]_midout[63] chany[1][1]_midout[72] chany[1][1]_midout[73] chany[1][1]_midout[84] chany[1][1]_midout[85] chany[1][1]_midout[96] chany[1][1]_midout[97] grid[1][1]_pin[0][1][33] sram[2642]->outb sram[2642]->out sram[2643]->out sram[2643]->outb sram[2644]->out sram[2644]->outb sram[2645]->out sram[2645]->outb sram[2646]->outb sram[2646]->out sram[2647]->out sram[2647]->outb sram[2648]->out sram[2648]->outb sram[2649]->out sram[2649]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[70], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2642] sram->in sram[2642]->out sram[2642]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2642]->out) 0 -.nodeset V(sram[2642]->outb) vsp -Xsram[2643] sram->in sram[2643]->out sram[2643]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2643]->out) 0 -.nodeset V(sram[2643]->outb) vsp -Xsram[2644] sram->in sram[2644]->out sram[2644]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2644]->out) 0 -.nodeset V(sram[2644]->outb) vsp -Xsram[2645] sram->in sram[2645]->out sram[2645]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2645]->out) 0 -.nodeset V(sram[2645]->outb) vsp -Xsram[2646] sram->in sram[2646]->out sram[2646]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2646]->out) 0 -.nodeset V(sram[2646]->outb) vsp -Xsram[2647] sram->in sram[2647]->out sram[2647]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2647]->out) 0 -.nodeset V(sram[2647]->outb) vsp -Xsram[2648] sram->in sram[2648]->out sram[2648]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2648]->out) 0 -.nodeset V(sram[2648]->outb) vsp -Xsram[2649] sram->in sram[2649]->out sram[2649]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2649]->out) 0 -.nodeset V(sram[2649]->outb) vsp -Xmux_2level_tapbuf_size16[71] chany[1][1]_midout[8] chany[1][1]_midout[9] chany[1][1]_midout[30] chany[1][1]_midout[31] chany[1][1]_midout[34] chany[1][1]_midout[35] chany[1][1]_midout[50] chany[1][1]_midout[51] chany[1][1]_midout[62] chany[1][1]_midout[63] chany[1][1]_midout[74] chany[1][1]_midout[75] chany[1][1]_midout[86] chany[1][1]_midout[87] chany[1][1]_midout[98] chany[1][1]_midout[99] grid[1][1]_pin[0][1][37] sram[2650]->outb sram[2650]->out sram[2651]->out sram[2651]->outb sram[2652]->out sram[2652]->outb sram[2653]->out sram[2653]->outb sram[2654]->outb sram[2654]->out sram[2655]->out sram[2655]->outb sram[2656]->out sram[2656]->outb sram[2657]->out sram[2657]->outb svdd sgnd mux_2level_tapbuf_size16 -***** SRAM bits for MUX[71], level=2, select_path_id=0. ***** -*****10001000***** -Xsram[2650] sram->in sram[2650]->out sram[2650]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2650]->out) 0 -.nodeset V(sram[2650]->outb) vsp -Xsram[2651] sram->in sram[2651]->out sram[2651]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2651]->out) 0 -.nodeset V(sram[2651]->outb) vsp -Xsram[2652] sram->in sram[2652]->out sram[2652]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2652]->out) 0 -.nodeset V(sram[2652]->outb) vsp -Xsram[2653] sram->in sram[2653]->out sram[2653]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2653]->out) 0 -.nodeset V(sram[2653]->outb) vsp -Xsram[2654] sram->in sram[2654]->out sram[2654]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2654]->out) 0 -.nodeset V(sram[2654]->outb) vsp -Xsram[2655] sram->in sram[2655]->out sram[2655]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2655]->out) 0 -.nodeset V(sram[2655]->outb) vsp -Xsram[2656] sram->in sram[2656]->out sram[2656]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2656]->out) 0 -.nodeset V(sram[2656]->outb) vsp -Xsram[2657] sram->in sram[2657]->out sram[2657]->outb gvdd_sram_cbs sgnd sram6T -.nodeset V(sram[2657]->out) 0 -.nodeset V(sram[2657]->outb) vsp -.eom diff --git a/examples/spice_test_example_2/subckt/chanx_1_0.sp b/examples/spice_test_example_2/subckt/chanx_1_0.sp deleted file mode 100644 index ee700548e..000000000 --- a/examples/spice_test_example_2/subckt/chanx_1_0.sp +++ /dev/null @@ -1,115 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Channel X-direction [1][0] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Subckt for Channel X [1][0] ***** -.subckt chanx[1][0] -+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29 in30 out31 in32 out33 in34 out35 in36 out37 in38 out39 in40 out41 in42 out43 in44 out45 in46 out47 in48 out49 in50 out51 in52 out53 in54 out55 in56 out57 in58 out59 in60 out61 in62 out63 in64 out65 in66 out67 in68 out69 in70 out71 in72 out73 in74 out75 in76 out77 in78 out79 in80 out81 in82 out83 in84 out85 in86 out87 in88 out89 in90 out91 in92 out93 in94 out95 in96 out97 in98 out99 -+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29 out30 in31 out32 in33 out34 in35 out36 in37 out38 in39 out40 in41 out42 in43 out44 in45 out46 in47 out48 in49 out50 in51 out52 in53 out54 in55 out56 in57 out58 in59 out60 in61 out62 in63 out64 in65 out66 in67 out68 in69 out70 in71 out72 in73 out74 in75 out76 in77 out78 in79 out80 in81 out82 in83 out84 in85 out86 in87 out88 in89 out90 in91 out92 in93 out94 in95 out96 in97 out98 in99 -+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29 mid_out30 mid_out31 mid_out32 mid_out33 mid_out34 mid_out35 mid_out36 mid_out37 mid_out38 mid_out39 mid_out40 mid_out41 mid_out42 mid_out43 mid_out44 mid_out45 mid_out46 mid_out47 mid_out48 mid_out49 mid_out50 mid_out51 mid_out52 mid_out53 mid_out54 mid_out55 mid_out56 mid_out57 mid_out58 mid_out59 mid_out60 mid_out61 mid_out62 mid_out63 mid_out64 mid_out65 mid_out66 mid_out67 mid_out68 mid_out69 mid_out70 mid_out71 mid_out72 mid_out73 mid_out74 mid_out75 mid_out76 mid_out77 mid_out78 mid_out79 mid_out80 mid_out81 mid_out82 mid_out83 mid_out84 mid_out85 mid_out86 mid_out87 mid_out88 mid_out89 mid_out90 mid_out91 mid_out92 mid_out93 mid_out94 mid_out95 mid_out96 mid_out97 mid_out98 mid_out99 -+ svdd sgnd -Xtrack_seg[0] in0 out0 mid_out0 svdd sgnd chan_segment_seg0 -Xtrack_seg[1] in1 out1 mid_out1 svdd sgnd chan_segment_seg0 -Xtrack_seg[2] in2 out2 mid_out2 svdd sgnd chan_segment_seg0 -Xtrack_seg[3] in3 out3 mid_out3 svdd sgnd chan_segment_seg0 -Xtrack_seg[4] in4 out4 mid_out4 svdd sgnd chan_segment_seg0 -Xtrack_seg[5] in5 out5 mid_out5 svdd sgnd chan_segment_seg0 -Xtrack_seg[6] in6 out6 mid_out6 svdd sgnd chan_segment_seg0 -Xtrack_seg[7] in7 out7 mid_out7 svdd sgnd chan_segment_seg0 -Xtrack_seg[8] in8 out8 mid_out8 svdd sgnd chan_segment_seg0 -Xtrack_seg[9] in9 out9 mid_out9 svdd sgnd chan_segment_seg0 -Xtrack_seg[10] in10 out10 mid_out10 svdd sgnd chan_segment_seg0 -Xtrack_seg[11] in11 out11 mid_out11 svdd sgnd chan_segment_seg0 -Xtrack_seg[12] in12 out12 mid_out12 svdd sgnd chan_segment_seg0 -Xtrack_seg[13] in13 out13 mid_out13 svdd sgnd chan_segment_seg0 -Xtrack_seg[14] in14 out14 mid_out14 svdd sgnd chan_segment_seg0 -Xtrack_seg[15] in15 out15 mid_out15 svdd sgnd chan_segment_seg0 -Xtrack_seg[16] in16 out16 mid_out16 svdd sgnd chan_segment_seg0 -Xtrack_seg[17] in17 out17 mid_out17 svdd sgnd chan_segment_seg0 -Xtrack_seg[18] in18 out18 mid_out18 svdd sgnd chan_segment_seg0 -Xtrack_seg[19] in19 out19 mid_out19 svdd sgnd chan_segment_seg0 -Xtrack_seg[20] in20 out20 mid_out20 svdd sgnd chan_segment_seg0 -Xtrack_seg[21] in21 out21 mid_out21 svdd sgnd chan_segment_seg0 -Xtrack_seg[22] in22 out22 mid_out22 svdd sgnd chan_segment_seg0 -Xtrack_seg[23] in23 out23 mid_out23 svdd sgnd chan_segment_seg0 -Xtrack_seg[24] in24 out24 mid_out24 svdd sgnd chan_segment_seg0 -Xtrack_seg[25] in25 out25 mid_out25 svdd sgnd chan_segment_seg0 -Xtrack_seg[26] in26 out26 mid_out26 svdd sgnd chan_segment_seg0 -Xtrack_seg[27] in27 out27 mid_out27 svdd sgnd chan_segment_seg0 -Xtrack_seg[28] in28 out28 mid_out28 svdd sgnd chan_segment_seg0 -Xtrack_seg[29] in29 out29 mid_out29 svdd sgnd chan_segment_seg0 -Xtrack_seg[30] in30 out30 mid_out30 svdd sgnd chan_segment_seg0 -Xtrack_seg[31] in31 out31 mid_out31 svdd sgnd chan_segment_seg0 -Xtrack_seg[32] in32 out32 mid_out32 svdd sgnd chan_segment_seg0 -Xtrack_seg[33] in33 out33 mid_out33 svdd sgnd chan_segment_seg0 -Xtrack_seg[34] in34 out34 mid_out34 svdd sgnd chan_segment_seg0 -Xtrack_seg[35] in35 out35 mid_out35 svdd sgnd chan_segment_seg0 -Xtrack_seg[36] in36 out36 mid_out36 svdd sgnd chan_segment_seg0 -Xtrack_seg[37] in37 out37 mid_out37 svdd sgnd chan_segment_seg0 -Xtrack_seg[38] in38 out38 mid_out38 svdd sgnd chan_segment_seg0 -Xtrack_seg[39] in39 out39 mid_out39 svdd sgnd chan_segment_seg0 -Xtrack_seg[40] in40 out40 mid_out40 svdd sgnd chan_segment_seg1 -Xtrack_seg[41] in41 out41 mid_out41 svdd sgnd chan_segment_seg1 -Xtrack_seg[42] in42 out42 mid_out42 svdd sgnd chan_segment_seg1 -Xtrack_seg[43] in43 out43 mid_out43 svdd sgnd chan_segment_seg1 -Xtrack_seg[44] in44 out44 mid_out44 svdd sgnd chan_segment_seg1 -Xtrack_seg[45] in45 out45 mid_out45 svdd sgnd chan_segment_seg1 -Xtrack_seg[46] in46 out46 mid_out46 svdd sgnd chan_segment_seg1 -Xtrack_seg[47] in47 out47 mid_out47 svdd sgnd chan_segment_seg1 -Xtrack_seg[48] in48 out48 mid_out48 svdd sgnd chan_segment_seg1 -Xtrack_seg[49] in49 out49 mid_out49 svdd sgnd chan_segment_seg1 -Xtrack_seg[50] in50 out50 mid_out50 svdd sgnd chan_segment_seg1 -Xtrack_seg[51] in51 out51 mid_out51 svdd sgnd chan_segment_seg1 -Xtrack_seg[52] in52 out52 mid_out52 svdd sgnd chan_segment_seg1 -Xtrack_seg[53] in53 out53 mid_out53 svdd sgnd chan_segment_seg1 -Xtrack_seg[54] in54 out54 mid_out54 svdd sgnd chan_segment_seg1 -Xtrack_seg[55] in55 out55 mid_out55 svdd sgnd chan_segment_seg1 -Xtrack_seg[56] in56 out56 mid_out56 svdd sgnd chan_segment_seg1 -Xtrack_seg[57] in57 out57 mid_out57 svdd sgnd chan_segment_seg1 -Xtrack_seg[58] in58 out58 mid_out58 svdd sgnd chan_segment_seg1 -Xtrack_seg[59] in59 out59 mid_out59 svdd sgnd chan_segment_seg1 -Xtrack_seg[60] in60 out60 mid_out60 svdd sgnd chan_segment_seg1 -Xtrack_seg[61] in61 out61 mid_out61 svdd sgnd chan_segment_seg1 -Xtrack_seg[62] in62 out62 mid_out62 svdd sgnd chan_segment_seg1 -Xtrack_seg[63] in63 out63 mid_out63 svdd sgnd chan_segment_seg1 -Xtrack_seg[64] in64 out64 mid_out64 svdd sgnd chan_segment_seg1 -Xtrack_seg[65] in65 out65 mid_out65 svdd sgnd chan_segment_seg1 -Xtrack_seg[66] in66 out66 mid_out66 svdd sgnd chan_segment_seg1 -Xtrack_seg[67] in67 out67 mid_out67 svdd sgnd chan_segment_seg1 -Xtrack_seg[68] in68 out68 mid_out68 svdd sgnd chan_segment_seg1 -Xtrack_seg[69] in69 out69 mid_out69 svdd sgnd chan_segment_seg1 -Xtrack_seg[70] in70 out70 mid_out70 svdd sgnd chan_segment_seg2 -Xtrack_seg[71] in71 out71 mid_out71 svdd sgnd chan_segment_seg2 -Xtrack_seg[72] in72 out72 mid_out72 svdd sgnd chan_segment_seg2 -Xtrack_seg[73] in73 out73 mid_out73 svdd sgnd chan_segment_seg2 -Xtrack_seg[74] in74 out74 mid_out74 svdd sgnd chan_segment_seg2 -Xtrack_seg[75] in75 out75 mid_out75 svdd sgnd chan_segment_seg2 -Xtrack_seg[76] in76 out76 mid_out76 svdd sgnd chan_segment_seg2 -Xtrack_seg[77] in77 out77 mid_out77 svdd sgnd chan_segment_seg2 -Xtrack_seg[78] in78 out78 mid_out78 svdd sgnd chan_segment_seg2 -Xtrack_seg[79] in79 out79 mid_out79 svdd sgnd chan_segment_seg2 -Xtrack_seg[80] in80 out80 mid_out80 svdd sgnd chan_segment_seg2 -Xtrack_seg[81] in81 out81 mid_out81 svdd sgnd chan_segment_seg2 -Xtrack_seg[82] in82 out82 mid_out82 svdd sgnd chan_segment_seg2 -Xtrack_seg[83] in83 out83 mid_out83 svdd sgnd chan_segment_seg2 -Xtrack_seg[84] in84 out84 mid_out84 svdd sgnd chan_segment_seg2 -Xtrack_seg[85] in85 out85 mid_out85 svdd sgnd chan_segment_seg2 -Xtrack_seg[86] in86 out86 mid_out86 svdd sgnd chan_segment_seg2 -Xtrack_seg[87] in87 out87 mid_out87 svdd sgnd chan_segment_seg2 -Xtrack_seg[88] in88 out88 mid_out88 svdd sgnd chan_segment_seg2 -Xtrack_seg[89] in89 out89 mid_out89 svdd sgnd chan_segment_seg2 -Xtrack_seg[90] in90 out90 mid_out90 svdd sgnd chan_segment_seg2 -Xtrack_seg[91] in91 out91 mid_out91 svdd sgnd chan_segment_seg2 -Xtrack_seg[92] in92 out92 mid_out92 svdd sgnd chan_segment_seg2 -Xtrack_seg[93] in93 out93 mid_out93 svdd sgnd chan_segment_seg2 -Xtrack_seg[94] in94 out94 mid_out94 svdd sgnd chan_segment_seg2 -Xtrack_seg[95] in95 out95 mid_out95 svdd sgnd chan_segment_seg2 -Xtrack_seg[96] in96 out96 mid_out96 svdd sgnd chan_segment_seg2 -Xtrack_seg[97] in97 out97 mid_out97 svdd sgnd chan_segment_seg2 -Xtrack_seg[98] in98 out98 mid_out98 svdd sgnd chan_segment_seg2 -Xtrack_seg[99] in99 out99 mid_out99 svdd sgnd chan_segment_seg2 -.eom diff --git a/examples/spice_test_example_2/subckt/chanx_1_1.sp b/examples/spice_test_example_2/subckt/chanx_1_1.sp deleted file mode 100644 index e3d1987ff..000000000 --- a/examples/spice_test_example_2/subckt/chanx_1_1.sp +++ /dev/null @@ -1,115 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Channel X-direction [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Subckt for Channel X [1][1] ***** -.subckt chanx[1][1] -+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29 in30 out31 in32 out33 in34 out35 in36 out37 in38 out39 in40 out41 in42 out43 in44 out45 in46 out47 in48 out49 in50 out51 in52 out53 in54 out55 in56 out57 in58 out59 in60 out61 in62 out63 in64 out65 in66 out67 in68 out69 in70 out71 in72 out73 in74 out75 in76 out77 in78 out79 in80 out81 in82 out83 in84 out85 in86 out87 in88 out89 in90 out91 in92 out93 in94 out95 in96 out97 in98 out99 -+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29 out30 in31 out32 in33 out34 in35 out36 in37 out38 in39 out40 in41 out42 in43 out44 in45 out46 in47 out48 in49 out50 in51 out52 in53 out54 in55 out56 in57 out58 in59 out60 in61 out62 in63 out64 in65 out66 in67 out68 in69 out70 in71 out72 in73 out74 in75 out76 in77 out78 in79 out80 in81 out82 in83 out84 in85 out86 in87 out88 in89 out90 in91 out92 in93 out94 in95 out96 in97 out98 in99 -+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29 mid_out30 mid_out31 mid_out32 mid_out33 mid_out34 mid_out35 mid_out36 mid_out37 mid_out38 mid_out39 mid_out40 mid_out41 mid_out42 mid_out43 mid_out44 mid_out45 mid_out46 mid_out47 mid_out48 mid_out49 mid_out50 mid_out51 mid_out52 mid_out53 mid_out54 mid_out55 mid_out56 mid_out57 mid_out58 mid_out59 mid_out60 mid_out61 mid_out62 mid_out63 mid_out64 mid_out65 mid_out66 mid_out67 mid_out68 mid_out69 mid_out70 mid_out71 mid_out72 mid_out73 mid_out74 mid_out75 mid_out76 mid_out77 mid_out78 mid_out79 mid_out80 mid_out81 mid_out82 mid_out83 mid_out84 mid_out85 mid_out86 mid_out87 mid_out88 mid_out89 mid_out90 mid_out91 mid_out92 mid_out93 mid_out94 mid_out95 mid_out96 mid_out97 mid_out98 mid_out99 -+ svdd sgnd -Xtrack_seg[100] in0 out0 mid_out0 svdd sgnd chan_segment_seg0 -Xtrack_seg[101] in1 out1 mid_out1 svdd sgnd chan_segment_seg0 -Xtrack_seg[102] in2 out2 mid_out2 svdd sgnd chan_segment_seg0 -Xtrack_seg[103] in3 out3 mid_out3 svdd sgnd chan_segment_seg0 -Xtrack_seg[104] in4 out4 mid_out4 svdd sgnd chan_segment_seg0 -Xtrack_seg[105] in5 out5 mid_out5 svdd sgnd chan_segment_seg0 -Xtrack_seg[106] in6 out6 mid_out6 svdd sgnd chan_segment_seg0 -Xtrack_seg[107] in7 out7 mid_out7 svdd sgnd chan_segment_seg0 -Xtrack_seg[108] in8 out8 mid_out8 svdd sgnd chan_segment_seg0 -Xtrack_seg[109] in9 out9 mid_out9 svdd sgnd chan_segment_seg0 -Xtrack_seg[110] in10 out10 mid_out10 svdd sgnd chan_segment_seg0 -Xtrack_seg[111] in11 out11 mid_out11 svdd sgnd chan_segment_seg0 -Xtrack_seg[112] in12 out12 mid_out12 svdd sgnd chan_segment_seg0 -Xtrack_seg[113] in13 out13 mid_out13 svdd sgnd chan_segment_seg0 -Xtrack_seg[114] in14 out14 mid_out14 svdd sgnd chan_segment_seg0 -Xtrack_seg[115] in15 out15 mid_out15 svdd sgnd chan_segment_seg0 -Xtrack_seg[116] in16 out16 mid_out16 svdd sgnd chan_segment_seg0 -Xtrack_seg[117] in17 out17 mid_out17 svdd sgnd chan_segment_seg0 -Xtrack_seg[118] in18 out18 mid_out18 svdd sgnd chan_segment_seg0 -Xtrack_seg[119] in19 out19 mid_out19 svdd sgnd chan_segment_seg0 -Xtrack_seg[120] in20 out20 mid_out20 svdd sgnd chan_segment_seg0 -Xtrack_seg[121] in21 out21 mid_out21 svdd sgnd chan_segment_seg0 -Xtrack_seg[122] in22 out22 mid_out22 svdd sgnd chan_segment_seg0 -Xtrack_seg[123] in23 out23 mid_out23 svdd sgnd chan_segment_seg0 -Xtrack_seg[124] in24 out24 mid_out24 svdd sgnd chan_segment_seg0 -Xtrack_seg[125] in25 out25 mid_out25 svdd sgnd chan_segment_seg0 -Xtrack_seg[126] in26 out26 mid_out26 svdd sgnd chan_segment_seg0 -Xtrack_seg[127] in27 out27 mid_out27 svdd sgnd chan_segment_seg0 -Xtrack_seg[128] in28 out28 mid_out28 svdd sgnd chan_segment_seg0 -Xtrack_seg[129] in29 out29 mid_out29 svdd sgnd chan_segment_seg0 -Xtrack_seg[130] in30 out30 mid_out30 svdd sgnd chan_segment_seg0 -Xtrack_seg[131] in31 out31 mid_out31 svdd sgnd chan_segment_seg0 -Xtrack_seg[132] in32 out32 mid_out32 svdd sgnd chan_segment_seg0 -Xtrack_seg[133] in33 out33 mid_out33 svdd sgnd chan_segment_seg0 -Xtrack_seg[134] in34 out34 mid_out34 svdd sgnd chan_segment_seg0 -Xtrack_seg[135] in35 out35 mid_out35 svdd sgnd chan_segment_seg0 -Xtrack_seg[136] in36 out36 mid_out36 svdd sgnd chan_segment_seg0 -Xtrack_seg[137] in37 out37 mid_out37 svdd sgnd chan_segment_seg0 -Xtrack_seg[138] in38 out38 mid_out38 svdd sgnd chan_segment_seg0 -Xtrack_seg[139] in39 out39 mid_out39 svdd sgnd chan_segment_seg0 -Xtrack_seg[140] in40 out40 mid_out40 svdd sgnd chan_segment_seg1 -Xtrack_seg[141] in41 out41 mid_out41 svdd sgnd chan_segment_seg1 -Xtrack_seg[142] in42 out42 mid_out42 svdd sgnd chan_segment_seg1 -Xtrack_seg[143] in43 out43 mid_out43 svdd sgnd chan_segment_seg1 -Xtrack_seg[144] in44 out44 mid_out44 svdd sgnd chan_segment_seg1 -Xtrack_seg[145] in45 out45 mid_out45 svdd sgnd chan_segment_seg1 -Xtrack_seg[146] in46 out46 mid_out46 svdd sgnd chan_segment_seg1 -Xtrack_seg[147] in47 out47 mid_out47 svdd sgnd chan_segment_seg1 -Xtrack_seg[148] in48 out48 mid_out48 svdd sgnd chan_segment_seg1 -Xtrack_seg[149] in49 out49 mid_out49 svdd sgnd chan_segment_seg1 -Xtrack_seg[150] in50 out50 mid_out50 svdd sgnd chan_segment_seg1 -Xtrack_seg[151] in51 out51 mid_out51 svdd sgnd chan_segment_seg1 -Xtrack_seg[152] in52 out52 mid_out52 svdd sgnd chan_segment_seg1 -Xtrack_seg[153] in53 out53 mid_out53 svdd sgnd chan_segment_seg1 -Xtrack_seg[154] in54 out54 mid_out54 svdd sgnd chan_segment_seg1 -Xtrack_seg[155] in55 out55 mid_out55 svdd sgnd chan_segment_seg1 -Xtrack_seg[156] in56 out56 mid_out56 svdd sgnd chan_segment_seg1 -Xtrack_seg[157] in57 out57 mid_out57 svdd sgnd chan_segment_seg1 -Xtrack_seg[158] in58 out58 mid_out58 svdd sgnd chan_segment_seg1 -Xtrack_seg[159] in59 out59 mid_out59 svdd sgnd chan_segment_seg1 -Xtrack_seg[160] in60 out60 mid_out60 svdd sgnd chan_segment_seg1 -Xtrack_seg[161] in61 out61 mid_out61 svdd sgnd chan_segment_seg1 -Xtrack_seg[162] in62 out62 mid_out62 svdd sgnd chan_segment_seg1 -Xtrack_seg[163] in63 out63 mid_out63 svdd sgnd chan_segment_seg1 -Xtrack_seg[164] in64 out64 mid_out64 svdd sgnd chan_segment_seg1 -Xtrack_seg[165] in65 out65 mid_out65 svdd sgnd chan_segment_seg1 -Xtrack_seg[166] in66 out66 mid_out66 svdd sgnd chan_segment_seg1 -Xtrack_seg[167] in67 out67 mid_out67 svdd sgnd chan_segment_seg1 -Xtrack_seg[168] in68 out68 mid_out68 svdd sgnd chan_segment_seg1 -Xtrack_seg[169] in69 out69 mid_out69 svdd sgnd chan_segment_seg1 -Xtrack_seg[170] in70 out70 mid_out70 svdd sgnd chan_segment_seg2 -Xtrack_seg[171] in71 out71 mid_out71 svdd sgnd chan_segment_seg2 -Xtrack_seg[172] in72 out72 mid_out72 svdd sgnd chan_segment_seg2 -Xtrack_seg[173] in73 out73 mid_out73 svdd sgnd chan_segment_seg2 -Xtrack_seg[174] in74 out74 mid_out74 svdd sgnd chan_segment_seg2 -Xtrack_seg[175] in75 out75 mid_out75 svdd sgnd chan_segment_seg2 -Xtrack_seg[176] in76 out76 mid_out76 svdd sgnd chan_segment_seg2 -Xtrack_seg[177] in77 out77 mid_out77 svdd sgnd chan_segment_seg2 -Xtrack_seg[178] in78 out78 mid_out78 svdd sgnd chan_segment_seg2 -Xtrack_seg[179] in79 out79 mid_out79 svdd sgnd chan_segment_seg2 -Xtrack_seg[180] in80 out80 mid_out80 svdd sgnd chan_segment_seg2 -Xtrack_seg[181] in81 out81 mid_out81 svdd sgnd chan_segment_seg2 -Xtrack_seg[182] in82 out82 mid_out82 svdd sgnd chan_segment_seg2 -Xtrack_seg[183] in83 out83 mid_out83 svdd sgnd chan_segment_seg2 -Xtrack_seg[184] in84 out84 mid_out84 svdd sgnd chan_segment_seg2 -Xtrack_seg[185] in85 out85 mid_out85 svdd sgnd chan_segment_seg2 -Xtrack_seg[186] in86 out86 mid_out86 svdd sgnd chan_segment_seg2 -Xtrack_seg[187] in87 out87 mid_out87 svdd sgnd chan_segment_seg2 -Xtrack_seg[188] in88 out88 mid_out88 svdd sgnd chan_segment_seg2 -Xtrack_seg[189] in89 out89 mid_out89 svdd sgnd chan_segment_seg2 -Xtrack_seg[190] in90 out90 mid_out90 svdd sgnd chan_segment_seg2 -Xtrack_seg[191] in91 out91 mid_out91 svdd sgnd chan_segment_seg2 -Xtrack_seg[192] in92 out92 mid_out92 svdd sgnd chan_segment_seg2 -Xtrack_seg[193] in93 out93 mid_out93 svdd sgnd chan_segment_seg2 -Xtrack_seg[194] in94 out94 mid_out94 svdd sgnd chan_segment_seg2 -Xtrack_seg[195] in95 out95 mid_out95 svdd sgnd chan_segment_seg2 -Xtrack_seg[196] in96 out96 mid_out96 svdd sgnd chan_segment_seg2 -Xtrack_seg[197] in97 out97 mid_out97 svdd sgnd chan_segment_seg2 -Xtrack_seg[198] in98 out98 mid_out98 svdd sgnd chan_segment_seg2 -Xtrack_seg[199] in99 out99 mid_out99 svdd sgnd chan_segment_seg2 -.eom diff --git a/examples/spice_test_example_2/subckt/chany_0_1.sp b/examples/spice_test_example_2/subckt/chany_0_1.sp deleted file mode 100644 index e0d9e32b8..000000000 --- a/examples/spice_test_example_2/subckt/chany_0_1.sp +++ /dev/null @@ -1,115 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Channel Y-direction [0][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Subckt for Channel Y [0][1] ***** -.subckt chany[0][1] -+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29 in30 out31 in32 out33 in34 out35 in36 out37 in38 out39 in40 out41 in42 out43 in44 out45 in46 out47 in48 out49 in50 out51 in52 out53 in54 out55 in56 out57 in58 out59 in60 out61 in62 out63 in64 out65 in66 out67 in68 out69 in70 out71 in72 out73 in74 out75 in76 out77 in78 out79 in80 out81 in82 out83 in84 out85 in86 out87 in88 out89 in90 out91 in92 out93 in94 out95 in96 out97 in98 out99 -+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29 out30 in31 out32 in33 out34 in35 out36 in37 out38 in39 out40 in41 out42 in43 out44 in45 out46 in47 out48 in49 out50 in51 out52 in53 out54 in55 out56 in57 out58 in59 out60 in61 out62 in63 out64 in65 out66 in67 out68 in69 out70 in71 out72 in73 out74 in75 out76 in77 out78 in79 out80 in81 out82 in83 out84 in85 out86 in87 out88 in89 out90 in91 out92 in93 out94 in95 out96 in97 out98 in99 -+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29 mid_out30 mid_out31 mid_out32 mid_out33 mid_out34 mid_out35 mid_out36 mid_out37 mid_out38 mid_out39 mid_out40 mid_out41 mid_out42 mid_out43 mid_out44 mid_out45 mid_out46 mid_out47 mid_out48 mid_out49 mid_out50 mid_out51 mid_out52 mid_out53 mid_out54 mid_out55 mid_out56 mid_out57 mid_out58 mid_out59 mid_out60 mid_out61 mid_out62 mid_out63 mid_out64 mid_out65 mid_out66 mid_out67 mid_out68 mid_out69 mid_out70 mid_out71 mid_out72 mid_out73 mid_out74 mid_out75 mid_out76 mid_out77 mid_out78 mid_out79 mid_out80 mid_out81 mid_out82 mid_out83 mid_out84 mid_out85 mid_out86 mid_out87 mid_out88 mid_out89 mid_out90 mid_out91 mid_out92 mid_out93 mid_out94 mid_out95 mid_out96 mid_out97 mid_out98 mid_out99 -+ svdd sgnd -Xtrack_seg[200] in0 out0 mid_out0 svdd sgnd chan_segment_seg0 -Xtrack_seg[201] in1 out1 mid_out1 svdd sgnd chan_segment_seg0 -Xtrack_seg[202] in2 out2 mid_out2 svdd sgnd chan_segment_seg0 -Xtrack_seg[203] in3 out3 mid_out3 svdd sgnd chan_segment_seg0 -Xtrack_seg[204] in4 out4 mid_out4 svdd sgnd chan_segment_seg0 -Xtrack_seg[205] in5 out5 mid_out5 svdd sgnd chan_segment_seg0 -Xtrack_seg[206] in6 out6 mid_out6 svdd sgnd chan_segment_seg0 -Xtrack_seg[207] in7 out7 mid_out7 svdd sgnd chan_segment_seg0 -Xtrack_seg[208] in8 out8 mid_out8 svdd sgnd chan_segment_seg0 -Xtrack_seg[209] in9 out9 mid_out9 svdd sgnd chan_segment_seg0 -Xtrack_seg[210] in10 out10 mid_out10 svdd sgnd chan_segment_seg0 -Xtrack_seg[211] in11 out11 mid_out11 svdd sgnd chan_segment_seg0 -Xtrack_seg[212] in12 out12 mid_out12 svdd sgnd chan_segment_seg0 -Xtrack_seg[213] in13 out13 mid_out13 svdd sgnd chan_segment_seg0 -Xtrack_seg[214] in14 out14 mid_out14 svdd sgnd chan_segment_seg0 -Xtrack_seg[215] in15 out15 mid_out15 svdd sgnd chan_segment_seg0 -Xtrack_seg[216] in16 out16 mid_out16 svdd sgnd chan_segment_seg0 -Xtrack_seg[217] in17 out17 mid_out17 svdd sgnd chan_segment_seg0 -Xtrack_seg[218] in18 out18 mid_out18 svdd sgnd chan_segment_seg0 -Xtrack_seg[219] in19 out19 mid_out19 svdd sgnd chan_segment_seg0 -Xtrack_seg[220] in20 out20 mid_out20 svdd sgnd chan_segment_seg0 -Xtrack_seg[221] in21 out21 mid_out21 svdd sgnd chan_segment_seg0 -Xtrack_seg[222] in22 out22 mid_out22 svdd sgnd chan_segment_seg0 -Xtrack_seg[223] in23 out23 mid_out23 svdd sgnd chan_segment_seg0 -Xtrack_seg[224] in24 out24 mid_out24 svdd sgnd chan_segment_seg0 -Xtrack_seg[225] in25 out25 mid_out25 svdd sgnd chan_segment_seg0 -Xtrack_seg[226] in26 out26 mid_out26 svdd sgnd chan_segment_seg0 -Xtrack_seg[227] in27 out27 mid_out27 svdd sgnd chan_segment_seg0 -Xtrack_seg[228] in28 out28 mid_out28 svdd sgnd chan_segment_seg0 -Xtrack_seg[229] in29 out29 mid_out29 svdd sgnd chan_segment_seg0 -Xtrack_seg[230] in30 out30 mid_out30 svdd sgnd chan_segment_seg0 -Xtrack_seg[231] in31 out31 mid_out31 svdd sgnd chan_segment_seg0 -Xtrack_seg[232] in32 out32 mid_out32 svdd sgnd chan_segment_seg0 -Xtrack_seg[233] in33 out33 mid_out33 svdd sgnd chan_segment_seg0 -Xtrack_seg[234] in34 out34 mid_out34 svdd sgnd chan_segment_seg0 -Xtrack_seg[235] in35 out35 mid_out35 svdd sgnd chan_segment_seg0 -Xtrack_seg[236] in36 out36 mid_out36 svdd sgnd chan_segment_seg0 -Xtrack_seg[237] in37 out37 mid_out37 svdd sgnd chan_segment_seg0 -Xtrack_seg[238] in38 out38 mid_out38 svdd sgnd chan_segment_seg0 -Xtrack_seg[239] in39 out39 mid_out39 svdd sgnd chan_segment_seg0 -Xtrack_seg[240] in40 out40 mid_out40 svdd sgnd chan_segment_seg1 -Xtrack_seg[241] in41 out41 mid_out41 svdd sgnd chan_segment_seg1 -Xtrack_seg[242] in42 out42 mid_out42 svdd sgnd chan_segment_seg1 -Xtrack_seg[243] in43 out43 mid_out43 svdd sgnd chan_segment_seg1 -Xtrack_seg[244] in44 out44 mid_out44 svdd sgnd chan_segment_seg1 -Xtrack_seg[245] in45 out45 mid_out45 svdd sgnd chan_segment_seg1 -Xtrack_seg[246] in46 out46 mid_out46 svdd sgnd chan_segment_seg1 -Xtrack_seg[247] in47 out47 mid_out47 svdd sgnd chan_segment_seg1 -Xtrack_seg[248] in48 out48 mid_out48 svdd sgnd chan_segment_seg1 -Xtrack_seg[249] in49 out49 mid_out49 svdd sgnd chan_segment_seg1 -Xtrack_seg[250] in50 out50 mid_out50 svdd sgnd chan_segment_seg1 -Xtrack_seg[251] in51 out51 mid_out51 svdd sgnd chan_segment_seg1 -Xtrack_seg[252] in52 out52 mid_out52 svdd sgnd chan_segment_seg1 -Xtrack_seg[253] in53 out53 mid_out53 svdd sgnd chan_segment_seg1 -Xtrack_seg[254] in54 out54 mid_out54 svdd sgnd chan_segment_seg1 -Xtrack_seg[255] in55 out55 mid_out55 svdd sgnd chan_segment_seg1 -Xtrack_seg[256] in56 out56 mid_out56 svdd sgnd chan_segment_seg1 -Xtrack_seg[257] in57 out57 mid_out57 svdd sgnd chan_segment_seg1 -Xtrack_seg[258] in58 out58 mid_out58 svdd sgnd chan_segment_seg1 -Xtrack_seg[259] in59 out59 mid_out59 svdd sgnd chan_segment_seg1 -Xtrack_seg[260] in60 out60 mid_out60 svdd sgnd chan_segment_seg1 -Xtrack_seg[261] in61 out61 mid_out61 svdd sgnd chan_segment_seg1 -Xtrack_seg[262] in62 out62 mid_out62 svdd sgnd chan_segment_seg1 -Xtrack_seg[263] in63 out63 mid_out63 svdd sgnd chan_segment_seg1 -Xtrack_seg[264] in64 out64 mid_out64 svdd sgnd chan_segment_seg1 -Xtrack_seg[265] in65 out65 mid_out65 svdd sgnd chan_segment_seg1 -Xtrack_seg[266] in66 out66 mid_out66 svdd sgnd chan_segment_seg1 -Xtrack_seg[267] in67 out67 mid_out67 svdd sgnd chan_segment_seg1 -Xtrack_seg[268] in68 out68 mid_out68 svdd sgnd chan_segment_seg1 -Xtrack_seg[269] in69 out69 mid_out69 svdd sgnd chan_segment_seg1 -Xtrack_seg[270] in70 out70 mid_out70 svdd sgnd chan_segment_seg2 -Xtrack_seg[271] in71 out71 mid_out71 svdd sgnd chan_segment_seg2 -Xtrack_seg[272] in72 out72 mid_out72 svdd sgnd chan_segment_seg2 -Xtrack_seg[273] in73 out73 mid_out73 svdd sgnd chan_segment_seg2 -Xtrack_seg[274] in74 out74 mid_out74 svdd sgnd chan_segment_seg2 -Xtrack_seg[275] in75 out75 mid_out75 svdd sgnd chan_segment_seg2 -Xtrack_seg[276] in76 out76 mid_out76 svdd sgnd chan_segment_seg2 -Xtrack_seg[277] in77 out77 mid_out77 svdd sgnd chan_segment_seg2 -Xtrack_seg[278] in78 out78 mid_out78 svdd sgnd chan_segment_seg2 -Xtrack_seg[279] in79 out79 mid_out79 svdd sgnd chan_segment_seg2 -Xtrack_seg[280] in80 out80 mid_out80 svdd sgnd chan_segment_seg2 -Xtrack_seg[281] in81 out81 mid_out81 svdd sgnd chan_segment_seg2 -Xtrack_seg[282] in82 out82 mid_out82 svdd sgnd chan_segment_seg2 -Xtrack_seg[283] in83 out83 mid_out83 svdd sgnd chan_segment_seg2 -Xtrack_seg[284] in84 out84 mid_out84 svdd sgnd chan_segment_seg2 -Xtrack_seg[285] in85 out85 mid_out85 svdd sgnd chan_segment_seg2 -Xtrack_seg[286] in86 out86 mid_out86 svdd sgnd chan_segment_seg2 -Xtrack_seg[287] in87 out87 mid_out87 svdd sgnd chan_segment_seg2 -Xtrack_seg[288] in88 out88 mid_out88 svdd sgnd chan_segment_seg2 -Xtrack_seg[289] in89 out89 mid_out89 svdd sgnd chan_segment_seg2 -Xtrack_seg[290] in90 out90 mid_out90 svdd sgnd chan_segment_seg2 -Xtrack_seg[291] in91 out91 mid_out91 svdd sgnd chan_segment_seg2 -Xtrack_seg[292] in92 out92 mid_out92 svdd sgnd chan_segment_seg2 -Xtrack_seg[293] in93 out93 mid_out93 svdd sgnd chan_segment_seg2 -Xtrack_seg[294] in94 out94 mid_out94 svdd sgnd chan_segment_seg2 -Xtrack_seg[295] in95 out95 mid_out95 svdd sgnd chan_segment_seg2 -Xtrack_seg[296] in96 out96 mid_out96 svdd sgnd chan_segment_seg2 -Xtrack_seg[297] in97 out97 mid_out97 svdd sgnd chan_segment_seg2 -Xtrack_seg[298] in98 out98 mid_out98 svdd sgnd chan_segment_seg2 -Xtrack_seg[299] in99 out99 mid_out99 svdd sgnd chan_segment_seg2 -.eom diff --git a/examples/spice_test_example_2/subckt/chany_1_1.sp b/examples/spice_test_example_2/subckt/chany_1_1.sp deleted file mode 100644 index 53aa7d9ea..000000000 --- a/examples/spice_test_example_2/subckt/chany_1_1.sp +++ /dev/null @@ -1,115 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Channel Y-direction [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Subckt for Channel Y [1][1] ***** -.subckt chany[1][1] -+ in0 out1 in2 out3 in4 out5 in6 out7 in8 out9 in10 out11 in12 out13 in14 out15 in16 out17 in18 out19 in20 out21 in22 out23 in24 out25 in26 out27 in28 out29 in30 out31 in32 out33 in34 out35 in36 out37 in38 out39 in40 out41 in42 out43 in44 out45 in46 out47 in48 out49 in50 out51 in52 out53 in54 out55 in56 out57 in58 out59 in60 out61 in62 out63 in64 out65 in66 out67 in68 out69 in70 out71 in72 out73 in74 out75 in76 out77 in78 out79 in80 out81 in82 out83 in84 out85 in86 out87 in88 out89 in90 out91 in92 out93 in94 out95 in96 out97 in98 out99 -+ out0 in1 out2 in3 out4 in5 out6 in7 out8 in9 out10 in11 out12 in13 out14 in15 out16 in17 out18 in19 out20 in21 out22 in23 out24 in25 out26 in27 out28 in29 out30 in31 out32 in33 out34 in35 out36 in37 out38 in39 out40 in41 out42 in43 out44 in45 out46 in47 out48 in49 out50 in51 out52 in53 out54 in55 out56 in57 out58 in59 out60 in61 out62 in63 out64 in65 out66 in67 out68 in69 out70 in71 out72 in73 out74 in75 out76 in77 out78 in79 out80 in81 out82 in83 out84 in85 out86 in87 out88 in89 out90 in91 out92 in93 out94 in95 out96 in97 out98 in99 -+ mid_out0 mid_out1 mid_out2 mid_out3 mid_out4 mid_out5 mid_out6 mid_out7 mid_out8 mid_out9 mid_out10 mid_out11 mid_out12 mid_out13 mid_out14 mid_out15 mid_out16 mid_out17 mid_out18 mid_out19 mid_out20 mid_out21 mid_out22 mid_out23 mid_out24 mid_out25 mid_out26 mid_out27 mid_out28 mid_out29 mid_out30 mid_out31 mid_out32 mid_out33 mid_out34 mid_out35 mid_out36 mid_out37 mid_out38 mid_out39 mid_out40 mid_out41 mid_out42 mid_out43 mid_out44 mid_out45 mid_out46 mid_out47 mid_out48 mid_out49 mid_out50 mid_out51 mid_out52 mid_out53 mid_out54 mid_out55 mid_out56 mid_out57 mid_out58 mid_out59 mid_out60 mid_out61 mid_out62 mid_out63 mid_out64 mid_out65 mid_out66 mid_out67 mid_out68 mid_out69 mid_out70 mid_out71 mid_out72 mid_out73 mid_out74 mid_out75 mid_out76 mid_out77 mid_out78 mid_out79 mid_out80 mid_out81 mid_out82 mid_out83 mid_out84 mid_out85 mid_out86 mid_out87 mid_out88 mid_out89 mid_out90 mid_out91 mid_out92 mid_out93 mid_out94 mid_out95 mid_out96 mid_out97 mid_out98 mid_out99 -+ svdd sgnd -Xtrack_seg[300] in0 out0 mid_out0 svdd sgnd chan_segment_seg0 -Xtrack_seg[301] in1 out1 mid_out1 svdd sgnd chan_segment_seg0 -Xtrack_seg[302] in2 out2 mid_out2 svdd sgnd chan_segment_seg0 -Xtrack_seg[303] in3 out3 mid_out3 svdd sgnd chan_segment_seg0 -Xtrack_seg[304] in4 out4 mid_out4 svdd sgnd chan_segment_seg0 -Xtrack_seg[305] in5 out5 mid_out5 svdd sgnd chan_segment_seg0 -Xtrack_seg[306] in6 out6 mid_out6 svdd sgnd chan_segment_seg0 -Xtrack_seg[307] in7 out7 mid_out7 svdd sgnd chan_segment_seg0 -Xtrack_seg[308] in8 out8 mid_out8 svdd sgnd chan_segment_seg0 -Xtrack_seg[309] in9 out9 mid_out9 svdd sgnd chan_segment_seg0 -Xtrack_seg[310] in10 out10 mid_out10 svdd sgnd chan_segment_seg0 -Xtrack_seg[311] in11 out11 mid_out11 svdd sgnd chan_segment_seg0 -Xtrack_seg[312] in12 out12 mid_out12 svdd sgnd chan_segment_seg0 -Xtrack_seg[313] in13 out13 mid_out13 svdd sgnd chan_segment_seg0 -Xtrack_seg[314] in14 out14 mid_out14 svdd sgnd chan_segment_seg0 -Xtrack_seg[315] in15 out15 mid_out15 svdd sgnd chan_segment_seg0 -Xtrack_seg[316] in16 out16 mid_out16 svdd sgnd chan_segment_seg0 -Xtrack_seg[317] in17 out17 mid_out17 svdd sgnd chan_segment_seg0 -Xtrack_seg[318] in18 out18 mid_out18 svdd sgnd chan_segment_seg0 -Xtrack_seg[319] in19 out19 mid_out19 svdd sgnd chan_segment_seg0 -Xtrack_seg[320] in20 out20 mid_out20 svdd sgnd chan_segment_seg0 -Xtrack_seg[321] in21 out21 mid_out21 svdd sgnd chan_segment_seg0 -Xtrack_seg[322] in22 out22 mid_out22 svdd sgnd chan_segment_seg0 -Xtrack_seg[323] in23 out23 mid_out23 svdd sgnd chan_segment_seg0 -Xtrack_seg[324] in24 out24 mid_out24 svdd sgnd chan_segment_seg0 -Xtrack_seg[325] in25 out25 mid_out25 svdd sgnd chan_segment_seg0 -Xtrack_seg[326] in26 out26 mid_out26 svdd sgnd chan_segment_seg0 -Xtrack_seg[327] in27 out27 mid_out27 svdd sgnd chan_segment_seg0 -Xtrack_seg[328] in28 out28 mid_out28 svdd sgnd chan_segment_seg0 -Xtrack_seg[329] in29 out29 mid_out29 svdd sgnd chan_segment_seg0 -Xtrack_seg[330] in30 out30 mid_out30 svdd sgnd chan_segment_seg0 -Xtrack_seg[331] in31 out31 mid_out31 svdd sgnd chan_segment_seg0 -Xtrack_seg[332] in32 out32 mid_out32 svdd sgnd chan_segment_seg0 -Xtrack_seg[333] in33 out33 mid_out33 svdd sgnd chan_segment_seg0 -Xtrack_seg[334] in34 out34 mid_out34 svdd sgnd chan_segment_seg0 -Xtrack_seg[335] in35 out35 mid_out35 svdd sgnd chan_segment_seg0 -Xtrack_seg[336] in36 out36 mid_out36 svdd sgnd chan_segment_seg0 -Xtrack_seg[337] in37 out37 mid_out37 svdd sgnd chan_segment_seg0 -Xtrack_seg[338] in38 out38 mid_out38 svdd sgnd chan_segment_seg0 -Xtrack_seg[339] in39 out39 mid_out39 svdd sgnd chan_segment_seg0 -Xtrack_seg[340] in40 out40 mid_out40 svdd sgnd chan_segment_seg1 -Xtrack_seg[341] in41 out41 mid_out41 svdd sgnd chan_segment_seg1 -Xtrack_seg[342] in42 out42 mid_out42 svdd sgnd chan_segment_seg1 -Xtrack_seg[343] in43 out43 mid_out43 svdd sgnd chan_segment_seg1 -Xtrack_seg[344] in44 out44 mid_out44 svdd sgnd chan_segment_seg1 -Xtrack_seg[345] in45 out45 mid_out45 svdd sgnd chan_segment_seg1 -Xtrack_seg[346] in46 out46 mid_out46 svdd sgnd chan_segment_seg1 -Xtrack_seg[347] in47 out47 mid_out47 svdd sgnd chan_segment_seg1 -Xtrack_seg[348] in48 out48 mid_out48 svdd sgnd chan_segment_seg1 -Xtrack_seg[349] in49 out49 mid_out49 svdd sgnd chan_segment_seg1 -Xtrack_seg[350] in50 out50 mid_out50 svdd sgnd chan_segment_seg1 -Xtrack_seg[351] in51 out51 mid_out51 svdd sgnd chan_segment_seg1 -Xtrack_seg[352] in52 out52 mid_out52 svdd sgnd chan_segment_seg1 -Xtrack_seg[353] in53 out53 mid_out53 svdd sgnd chan_segment_seg1 -Xtrack_seg[354] in54 out54 mid_out54 svdd sgnd chan_segment_seg1 -Xtrack_seg[355] in55 out55 mid_out55 svdd sgnd chan_segment_seg1 -Xtrack_seg[356] in56 out56 mid_out56 svdd sgnd chan_segment_seg1 -Xtrack_seg[357] in57 out57 mid_out57 svdd sgnd chan_segment_seg1 -Xtrack_seg[358] in58 out58 mid_out58 svdd sgnd chan_segment_seg1 -Xtrack_seg[359] in59 out59 mid_out59 svdd sgnd chan_segment_seg1 -Xtrack_seg[360] in60 out60 mid_out60 svdd sgnd chan_segment_seg1 -Xtrack_seg[361] in61 out61 mid_out61 svdd sgnd chan_segment_seg1 -Xtrack_seg[362] in62 out62 mid_out62 svdd sgnd chan_segment_seg1 -Xtrack_seg[363] in63 out63 mid_out63 svdd sgnd chan_segment_seg1 -Xtrack_seg[364] in64 out64 mid_out64 svdd sgnd chan_segment_seg1 -Xtrack_seg[365] in65 out65 mid_out65 svdd sgnd chan_segment_seg1 -Xtrack_seg[366] in66 out66 mid_out66 svdd sgnd chan_segment_seg1 -Xtrack_seg[367] in67 out67 mid_out67 svdd sgnd chan_segment_seg1 -Xtrack_seg[368] in68 out68 mid_out68 svdd sgnd chan_segment_seg1 -Xtrack_seg[369] in69 out69 mid_out69 svdd sgnd chan_segment_seg1 -Xtrack_seg[370] in70 out70 mid_out70 svdd sgnd chan_segment_seg2 -Xtrack_seg[371] in71 out71 mid_out71 svdd sgnd chan_segment_seg2 -Xtrack_seg[372] in72 out72 mid_out72 svdd sgnd chan_segment_seg2 -Xtrack_seg[373] in73 out73 mid_out73 svdd sgnd chan_segment_seg2 -Xtrack_seg[374] in74 out74 mid_out74 svdd sgnd chan_segment_seg2 -Xtrack_seg[375] in75 out75 mid_out75 svdd sgnd chan_segment_seg2 -Xtrack_seg[376] in76 out76 mid_out76 svdd sgnd chan_segment_seg2 -Xtrack_seg[377] in77 out77 mid_out77 svdd sgnd chan_segment_seg2 -Xtrack_seg[378] in78 out78 mid_out78 svdd sgnd chan_segment_seg2 -Xtrack_seg[379] in79 out79 mid_out79 svdd sgnd chan_segment_seg2 -Xtrack_seg[380] in80 out80 mid_out80 svdd sgnd chan_segment_seg2 -Xtrack_seg[381] in81 out81 mid_out81 svdd sgnd chan_segment_seg2 -Xtrack_seg[382] in82 out82 mid_out82 svdd sgnd chan_segment_seg2 -Xtrack_seg[383] in83 out83 mid_out83 svdd sgnd chan_segment_seg2 -Xtrack_seg[384] in84 out84 mid_out84 svdd sgnd chan_segment_seg2 -Xtrack_seg[385] in85 out85 mid_out85 svdd sgnd chan_segment_seg2 -Xtrack_seg[386] in86 out86 mid_out86 svdd sgnd chan_segment_seg2 -Xtrack_seg[387] in87 out87 mid_out87 svdd sgnd chan_segment_seg2 -Xtrack_seg[388] in88 out88 mid_out88 svdd sgnd chan_segment_seg2 -Xtrack_seg[389] in89 out89 mid_out89 svdd sgnd chan_segment_seg2 -Xtrack_seg[390] in90 out90 mid_out90 svdd sgnd chan_segment_seg2 -Xtrack_seg[391] in91 out91 mid_out91 svdd sgnd chan_segment_seg2 -Xtrack_seg[392] in92 out92 mid_out92 svdd sgnd chan_segment_seg2 -Xtrack_seg[393] in93 out93 mid_out93 svdd sgnd chan_segment_seg2 -Xtrack_seg[394] in94 out94 mid_out94 svdd sgnd chan_segment_seg2 -Xtrack_seg[395] in95 out95 mid_out95 svdd sgnd chan_segment_seg2 -Xtrack_seg[396] in96 out96 mid_out96 svdd sgnd chan_segment_seg2 -Xtrack_seg[397] in97 out97 mid_out97 svdd sgnd chan_segment_seg2 -Xtrack_seg[398] in98 out98 mid_out98 svdd sgnd chan_segment_seg2 -Xtrack_seg[399] in99 out99 mid_out99 svdd sgnd chan_segment_seg2 -.eom diff --git a/examples/spice_test_example_2/subckt/grid_0_1.sp b/examples/spice_test_example_2/subckt/grid_0_1.sp deleted file mode 100644 index 0fe614e71..000000000 --- a/examples/spice_test_example_2/subckt/grid_0_1.sp +++ /dev/null @@ -1,222 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Phyiscal Logic Block [0][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Grid[0][1] type_descriptor: io[0] ***** -.subckt grid[0][1]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[0] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[0] sram[1610]->outb sram[1610]->out gvdd_iopad[0] sgnd iopad -***** SRAM bits for IOPAD[0] ***** -*****1***** -Xsram[1610] sram->in sram[1610]->out sram[1610]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1610]->out) 0 -.nodeset V(sram[1610]->outb) vsp -.eom -.subckt grid[0][1]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[0]_mode[io_phy]_iopad[0] -Xdirect_interc[180] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[181] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[1] ***** -***** Logical block mapped to this IO: clk ***** -.subckt grid[0][1]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[1] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[1] sram[1611]->outb sram[1611]->out gvdd_iopad[1] sgnd iopad -***** SRAM bits for IOPAD[1] ***** -*****1***** -Xsram[1611] sram->in sram[1611]->out sram[1611]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1611]->out) 0 -.nodeset V(sram[1611]->outb) vsp -.eom -.subckt grid[0][1]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[1]_mode[io_phy]_iopad[0] -Xdirect_interc[182] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[183] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[2] ***** -.subckt grid[0][1]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[2] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[2] sram[1612]->outb sram[1612]->out gvdd_iopad[2] sgnd iopad -***** SRAM bits for IOPAD[2] ***** -*****1***** -Xsram[1612] sram->in sram[1612]->out sram[1612]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1612]->out) 0 -.nodeset V(sram[1612]->outb) vsp -.eom -.subckt grid[0][1]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[2]_mode[io_phy]_iopad[0] -Xdirect_interc[184] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[185] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[3] ***** -.subckt grid[0][1]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[3] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[3] sram[1613]->outb sram[1613]->out gvdd_iopad[3] sgnd iopad -***** SRAM bits for IOPAD[3] ***** -*****1***** -Xsram[1613] sram->in sram[1613]->out sram[1613]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1613]->out) 0 -.nodeset V(sram[1613]->outb) vsp -.eom -.subckt grid[0][1]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[3]_mode[io_phy]_iopad[0] -Xdirect_interc[186] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[187] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[4] ***** -.subckt grid[0][1]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[4] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[4] sram[1614]->outb sram[1614]->out gvdd_iopad[4] sgnd iopad -***** SRAM bits for IOPAD[4] ***** -*****1***** -Xsram[1614] sram->in sram[1614]->out sram[1614]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1614]->out) 0 -.nodeset V(sram[1614]->outb) vsp -.eom -.subckt grid[0][1]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[4]_mode[io_phy]_iopad[0] -Xdirect_interc[188] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[189] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[5] ***** -.subckt grid[0][1]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[5] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[5] sram[1615]->outb sram[1615]->out gvdd_iopad[5] sgnd iopad -***** SRAM bits for IOPAD[5] ***** -*****1***** -Xsram[1615] sram->in sram[1615]->out sram[1615]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1615]->out) 0 -.nodeset V(sram[1615]->outb) vsp -.eom -.subckt grid[0][1]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[5]_mode[io_phy]_iopad[0] -Xdirect_interc[190] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[191] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[6] ***** -.subckt grid[0][1]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[6] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[6] sram[1616]->outb sram[1616]->out gvdd_iopad[6] sgnd iopad -***** SRAM bits for IOPAD[6] ***** -*****1***** -Xsram[1616] sram->in sram[1616]->out sram[1616]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1616]->out) 0 -.nodeset V(sram[1616]->outb) vsp -.eom -.subckt grid[0][1]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[6]_mode[io_phy]_iopad[0] -Xdirect_interc[192] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[193] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1] type_descriptor: io[7] ***** -.subckt grid[0][1]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[7] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[7] sram[1617]->outb sram[1617]->out gvdd_iopad[7] sgnd iopad -***** SRAM bits for IOPAD[7] ***** -*****1***** -Xsram[1617] sram->in sram[1617]->out sram[1617]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1617]->out) 0 -.nodeset V(sram[1617]->outb) vsp -.eom -.subckt grid[0][1]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[0][1]_io[7]_mode[io_phy]_iopad[0] -Xdirect_interc[194] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[195] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[0][1], Capactity: 8 ***** -***** Top Protocol ***** -.subckt grid[0][1] -+ right_height[0]_pin[0] -+ right_height[0]_pin[1] -+ right_height[0]_pin[2] -+ right_height[0]_pin[3] -+ right_height[0]_pin[4] -+ right_height[0]_pin[5] -+ right_height[0]_pin[6] -+ right_height[0]_pin[7] -+ right_height[0]_pin[8] -+ right_height[0]_pin[9] -+ right_height[0]_pin[10] -+ right_height[0]_pin[11] -+ right_height[0]_pin[12] -+ right_height[0]_pin[13] -+ right_height[0]_pin[14] -+ right_height[0]_pin[15] -+ svdd sgnd -Xgrid[0][1][0] -+ right_height[0]_pin[0] -+ right_height[0]_pin[1] -+ svdd sgnd grid[0][1]_io[0]_mode[io_phy] -Xgrid[0][1][1] -+ right_height[0]_pin[2] -+ right_height[0]_pin[3] -+ svdd sgnd grid[0][1]_io[1]_mode[io_phy] -Xgrid[0][1][2] -+ right_height[0]_pin[4] -+ right_height[0]_pin[5] -+ svdd sgnd grid[0][1]_io[2]_mode[io_phy] -Xgrid[0][1][3] -+ right_height[0]_pin[6] -+ right_height[0]_pin[7] -+ svdd sgnd grid[0][1]_io[3]_mode[io_phy] -Xgrid[0][1][4] -+ right_height[0]_pin[8] -+ right_height[0]_pin[9] -+ svdd sgnd grid[0][1]_io[4]_mode[io_phy] -Xgrid[0][1][5] -+ right_height[0]_pin[10] -+ right_height[0]_pin[11] -+ svdd sgnd grid[0][1]_io[5]_mode[io_phy] -Xgrid[0][1][6] -+ right_height[0]_pin[12] -+ right_height[0]_pin[13] -+ svdd sgnd grid[0][1]_io[6]_mode[io_phy] -Xgrid[0][1][7] -+ right_height[0]_pin[14] -+ right_height[0]_pin[15] -+ svdd sgnd grid[0][1]_io[7]_mode[io_phy] -.eom diff --git a/examples/spice_test_example_2/subckt/grid_1_0.sp b/examples/spice_test_example_2/subckt/grid_1_0.sp deleted file mode 100644 index 5e15fdbc6..000000000 --- a/examples/spice_test_example_2/subckt/grid_1_0.sp +++ /dev/null @@ -1,222 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Phyiscal Logic Block [1][0] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Grid[1][0] type_descriptor: io[0] ***** -.subckt grid[1][0]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[16] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[16] sram[1626]->outb sram[1626]->out gvdd_iopad[16] sgnd iopad -***** SRAM bits for IOPAD[16] ***** -*****1***** -Xsram[1626] sram->in sram[1626]->out sram[1626]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1626]->out) 0 -.nodeset V(sram[1626]->outb) vsp -.eom -.subckt grid[1][0]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[0]_mode[io_phy]_iopad[0] -Xdirect_interc[212] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[213] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[1] ***** -***** Logical block mapped to this IO: I0 ***** -.subckt grid[1][0]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[17] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[17] sram[1627]->outb sram[1627]->out gvdd_iopad[17] sgnd iopad -***** SRAM bits for IOPAD[17] ***** -*****1***** -Xsram[1627] sram->in sram[1627]->out sram[1627]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1627]->out) 0 -.nodeset V(sram[1627]->outb) vsp -.eom -.subckt grid[1][0]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[1]_mode[io_phy]_iopad[0] -Xdirect_interc[214] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[215] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[2] ***** -.subckt grid[1][0]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[18] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[18] sram[1628]->outb sram[1628]->out gvdd_iopad[18] sgnd iopad -***** SRAM bits for IOPAD[18] ***** -*****1***** -Xsram[1628] sram->in sram[1628]->out sram[1628]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1628]->out) 0 -.nodeset V(sram[1628]->outb) vsp -.eom -.subckt grid[1][0]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[2]_mode[io_phy]_iopad[0] -Xdirect_interc[216] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[217] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[3] ***** -.subckt grid[1][0]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[19] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[19] sram[1629]->outb sram[1629]->out gvdd_iopad[19] sgnd iopad -***** SRAM bits for IOPAD[19] ***** -*****1***** -Xsram[1629] sram->in sram[1629]->out sram[1629]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1629]->out) 0 -.nodeset V(sram[1629]->outb) vsp -.eom -.subckt grid[1][0]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[3]_mode[io_phy]_iopad[0] -Xdirect_interc[218] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[219] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[4] ***** -.subckt grid[1][0]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[20] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[20] sram[1630]->outb sram[1630]->out gvdd_iopad[20] sgnd iopad -***** SRAM bits for IOPAD[20] ***** -*****1***** -Xsram[1630] sram->in sram[1630]->out sram[1630]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1630]->out) 0 -.nodeset V(sram[1630]->outb) vsp -.eom -.subckt grid[1][0]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[4]_mode[io_phy]_iopad[0] -Xdirect_interc[220] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[221] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[5] ***** -.subckt grid[1][0]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[21] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[21] sram[1631]->outb sram[1631]->out gvdd_iopad[21] sgnd iopad -***** SRAM bits for IOPAD[21] ***** -*****1***** -Xsram[1631] sram->in sram[1631]->out sram[1631]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1631]->out) 0 -.nodeset V(sram[1631]->outb) vsp -.eom -.subckt grid[1][0]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[5]_mode[io_phy]_iopad[0] -Xdirect_interc[222] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[223] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[6] ***** -.subckt grid[1][0]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[22] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[22] sram[1632]->outb sram[1632]->out gvdd_iopad[22] sgnd iopad -***** SRAM bits for IOPAD[22] ***** -*****1***** -Xsram[1632] sram->in sram[1632]->out sram[1632]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1632]->out) 0 -.nodeset V(sram[1632]->outb) vsp -.eom -.subckt grid[1][0]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[6]_mode[io_phy]_iopad[0] -Xdirect_interc[224] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[225] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0] type_descriptor: io[7] ***** -.subckt grid[1][0]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[23] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[23] sram[1633]->outb sram[1633]->out gvdd_iopad[23] sgnd iopad -***** SRAM bits for IOPAD[23] ***** -*****1***** -Xsram[1633] sram->in sram[1633]->out sram[1633]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1633]->out) 0 -.nodeset V(sram[1633]->outb) vsp -.eom -.subckt grid[1][0]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][0]_io[7]_mode[io_phy]_iopad[0] -Xdirect_interc[226] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[227] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][0], Capactity: 8 ***** -***** Top Protocol ***** -.subckt grid[1][0] -+ top_height[0]_pin[0] -+ top_height[0]_pin[1] -+ top_height[0]_pin[2] -+ top_height[0]_pin[3] -+ top_height[0]_pin[4] -+ top_height[0]_pin[5] -+ top_height[0]_pin[6] -+ top_height[0]_pin[7] -+ top_height[0]_pin[8] -+ top_height[0]_pin[9] -+ top_height[0]_pin[10] -+ top_height[0]_pin[11] -+ top_height[0]_pin[12] -+ top_height[0]_pin[13] -+ top_height[0]_pin[14] -+ top_height[0]_pin[15] -+ svdd sgnd -Xgrid[1][0][0] -+ top_height[0]_pin[0] -+ top_height[0]_pin[1] -+ svdd sgnd grid[1][0]_io[0]_mode[io_phy] -Xgrid[1][0][1] -+ top_height[0]_pin[2] -+ top_height[0]_pin[3] -+ svdd sgnd grid[1][0]_io[1]_mode[io_phy] -Xgrid[1][0][2] -+ top_height[0]_pin[4] -+ top_height[0]_pin[5] -+ svdd sgnd grid[1][0]_io[2]_mode[io_phy] -Xgrid[1][0][3] -+ top_height[0]_pin[6] -+ top_height[0]_pin[7] -+ svdd sgnd grid[1][0]_io[3]_mode[io_phy] -Xgrid[1][0][4] -+ top_height[0]_pin[8] -+ top_height[0]_pin[9] -+ svdd sgnd grid[1][0]_io[4]_mode[io_phy] -Xgrid[1][0][5] -+ top_height[0]_pin[10] -+ top_height[0]_pin[11] -+ svdd sgnd grid[1][0]_io[5]_mode[io_phy] -Xgrid[1][0][6] -+ top_height[0]_pin[12] -+ top_height[0]_pin[13] -+ svdd sgnd grid[1][0]_io[6]_mode[io_phy] -Xgrid[1][0][7] -+ top_height[0]_pin[14] -+ top_height[0]_pin[15] -+ svdd sgnd grid[1][0]_io[7]_mode[io_phy] -.eom diff --git a/examples/spice_test_example_2/subckt/grid_1_1.sp b/examples/spice_test_example_2/subckt/grid_1_1.sp deleted file mode 100644 index 5e539f403..000000000 --- a/examples/spice_test_example_2/subckt/grid_1_1.sp +++ /dev/null @@ -1,5565 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Logic Block [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Grid[1][1] type_descriptor: clb[0] ***** -.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd -***** Truth Table for LUT[0], size=6. ***** -***** SRAM bits for LUT[0], size=6, num_sram=64. ***** -*****0000000000000000000000000000000000000000000000000000000000000000***** -Xsram[0] sram->in sram[0]->out sram[0]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[0]->out) 0 -.nodeset V(sram[0]->outb) vsp -Xsram[1] sram->in sram[1]->out sram[1]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[1]->out) 0 -.nodeset V(sram[1]->outb) vsp -Xsram[2] sram->in sram[2]->out sram[2]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[2]->out) 0 -.nodeset V(sram[2]->outb) vsp -Xsram[3] sram->in sram[3]->out sram[3]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[3]->out) 0 -.nodeset V(sram[3]->outb) vsp -Xsram[4] sram->in sram[4]->out sram[4]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[4]->out) 0 -.nodeset V(sram[4]->outb) vsp -Xsram[5] sram->in sram[5]->out sram[5]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[5]->out) 0 -.nodeset V(sram[5]->outb) vsp -Xsram[6] sram->in sram[6]->out sram[6]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[6]->out) 0 -.nodeset V(sram[6]->outb) vsp -Xsram[7] sram->in sram[7]->out sram[7]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[7]->out) 0 -.nodeset V(sram[7]->outb) vsp -Xsram[8] sram->in sram[8]->out sram[8]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[8]->out) 0 -.nodeset V(sram[8]->outb) vsp -Xsram[9] sram->in sram[9]->out sram[9]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[9]->out) 0 -.nodeset V(sram[9]->outb) vsp -Xsram[10] sram->in sram[10]->out sram[10]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[10]->out) 0 -.nodeset V(sram[10]->outb) vsp -Xsram[11] sram->in sram[11]->out sram[11]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[11]->out) 0 -.nodeset V(sram[11]->outb) vsp -Xsram[12] sram->in sram[12]->out sram[12]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[12]->out) 0 -.nodeset V(sram[12]->outb) vsp -Xsram[13] sram->in sram[13]->out sram[13]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[13]->out) 0 -.nodeset V(sram[13]->outb) vsp -Xsram[14] sram->in sram[14]->out sram[14]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[14]->out) 0 -.nodeset V(sram[14]->outb) vsp -Xsram[15] sram->in sram[15]->out sram[15]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[15]->out) 0 -.nodeset V(sram[15]->outb) vsp -Xsram[16] sram->in sram[16]->out sram[16]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[16]->out) 0 -.nodeset V(sram[16]->outb) vsp -Xsram[17] sram->in sram[17]->out sram[17]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[17]->out) 0 -.nodeset V(sram[17]->outb) vsp -Xsram[18] sram->in sram[18]->out sram[18]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[18]->out) 0 -.nodeset V(sram[18]->outb) vsp -Xsram[19] sram->in sram[19]->out sram[19]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[19]->out) 0 -.nodeset V(sram[19]->outb) vsp -Xsram[20] sram->in sram[20]->out sram[20]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[20]->out) 0 -.nodeset V(sram[20]->outb) vsp -Xsram[21] sram->in sram[21]->out sram[21]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[21]->out) 0 -.nodeset V(sram[21]->outb) vsp -Xsram[22] sram->in sram[22]->out sram[22]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[22]->out) 0 -.nodeset V(sram[22]->outb) vsp -Xsram[23] sram->in sram[23]->out sram[23]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[23]->out) 0 -.nodeset V(sram[23]->outb) vsp -Xsram[24] sram->in sram[24]->out sram[24]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[24]->out) 0 -.nodeset V(sram[24]->outb) vsp -Xsram[25] sram->in sram[25]->out sram[25]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[25]->out) 0 -.nodeset V(sram[25]->outb) vsp -Xsram[26] sram->in sram[26]->out sram[26]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[26]->out) 0 -.nodeset V(sram[26]->outb) vsp -Xsram[27] sram->in sram[27]->out sram[27]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[27]->out) 0 -.nodeset V(sram[27]->outb) vsp -Xsram[28] sram->in sram[28]->out sram[28]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[28]->out) 0 -.nodeset V(sram[28]->outb) vsp -Xsram[29] sram->in sram[29]->out sram[29]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[29]->out) 0 -.nodeset V(sram[29]->outb) vsp -Xsram[30] sram->in sram[30]->out sram[30]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[30]->out) 0 -.nodeset V(sram[30]->outb) vsp -Xsram[31] sram->in sram[31]->out sram[31]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[31]->out) 0 -.nodeset V(sram[31]->outb) vsp -Xsram[32] sram->in sram[32]->out sram[32]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[32]->out) 0 -.nodeset V(sram[32]->outb) vsp -Xsram[33] sram->in sram[33]->out sram[33]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[33]->out) 0 -.nodeset V(sram[33]->outb) vsp -Xsram[34] sram->in sram[34]->out sram[34]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[34]->out) 0 -.nodeset V(sram[34]->outb) vsp -Xsram[35] sram->in sram[35]->out sram[35]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[35]->out) 0 -.nodeset V(sram[35]->outb) vsp -Xsram[36] sram->in sram[36]->out sram[36]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[36]->out) 0 -.nodeset V(sram[36]->outb) vsp -Xsram[37] sram->in sram[37]->out sram[37]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[37]->out) 0 -.nodeset V(sram[37]->outb) vsp -Xsram[38] sram->in sram[38]->out sram[38]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[38]->out) 0 -.nodeset V(sram[38]->outb) vsp -Xsram[39] sram->in sram[39]->out sram[39]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[39]->out) 0 -.nodeset V(sram[39]->outb) vsp -Xsram[40] sram->in sram[40]->out sram[40]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[40]->out) 0 -.nodeset V(sram[40]->outb) vsp -Xsram[41] sram->in sram[41]->out sram[41]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[41]->out) 0 -.nodeset V(sram[41]->outb) vsp -Xsram[42] sram->in sram[42]->out sram[42]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[42]->out) 0 -.nodeset V(sram[42]->outb) vsp -Xsram[43] sram->in sram[43]->out sram[43]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[43]->out) 0 -.nodeset V(sram[43]->outb) vsp -Xsram[44] sram->in sram[44]->out sram[44]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[44]->out) 0 -.nodeset V(sram[44]->outb) vsp -Xsram[45] sram->in sram[45]->out sram[45]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[45]->out) 0 -.nodeset V(sram[45]->outb) vsp -Xsram[46] sram->in sram[46]->out sram[46]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[46]->out) 0 -.nodeset V(sram[46]->outb) vsp -Xsram[47] sram->in sram[47]->out sram[47]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[47]->out) 0 -.nodeset V(sram[47]->outb) vsp -Xsram[48] sram->in sram[48]->out sram[48]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[48]->out) 0 -.nodeset V(sram[48]->outb) vsp -Xsram[49] sram->in sram[49]->out sram[49]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[49]->out) 0 -.nodeset V(sram[49]->outb) vsp -Xsram[50] sram->in sram[50]->out sram[50]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[50]->out) 0 -.nodeset V(sram[50]->outb) vsp -Xsram[51] sram->in sram[51]->out sram[51]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[51]->out) 0 -.nodeset V(sram[51]->outb) vsp -Xsram[52] sram->in sram[52]->out sram[52]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[52]->out) 0 -.nodeset V(sram[52]->outb) vsp -Xsram[53] sram->in sram[53]->out sram[53]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[53]->out) 0 -.nodeset V(sram[53]->outb) vsp -Xsram[54] sram->in sram[54]->out sram[54]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[54]->out) 0 -.nodeset V(sram[54]->outb) vsp -Xsram[55] sram->in sram[55]->out sram[55]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[55]->out) 0 -.nodeset V(sram[55]->outb) vsp -Xsram[56] sram->in sram[56]->out sram[56]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[56]->out) 0 -.nodeset V(sram[56]->outb) vsp -Xsram[57] sram->in sram[57]->out sram[57]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[57]->out) 0 -.nodeset V(sram[57]->outb) vsp -Xsram[58] sram->in sram[58]->out sram[58]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[58]->out) 0 -.nodeset V(sram[58]->outb) vsp -Xsram[59] sram->in sram[59]->out sram[59]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[59]->out) 0 -.nodeset V(sram[59]->outb) vsp -Xsram[60] sram->in sram[60]->out sram[60]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[60]->out) 0 -.nodeset V(sram[60]->outb) vsp -Xsram[61] sram->in sram[61]->out sram[61]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[61]->out) 0 -.nodeset V(sram[61]->outb) vsp -Xsram[62] sram->in sram[62]->out sram[62]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[62]->out) 0 -.nodeset V(sram[62]->outb) vsp -Xsram[63] sram->in sram[63]->out sram[63]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[63]->out) 0 -.nodeset V(sram[63]->outb) vsp -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] sram[0]->out sram[1]->out sram[2]->out sram[3]->out sram[4]->out sram[5]->out sram[6]->out sram[7]->out sram[8]->out sram[9]->out sram[10]->out sram[11]->out sram[12]->out sram[13]->out sram[14]->out sram[15]->out sram[16]->out sram[17]->out sram[18]->out sram[19]->out sram[20]->out sram[21]->out sram[22]->out sram[23]->out sram[24]->out sram[25]->out sram[26]->out sram[27]->out sram[28]->out sram[29]->out sram[30]->out sram[31]->out sram[32]->out sram[33]->out sram[34]->out sram[35]->out sram[36]->out sram[37]->out sram[38]->out sram[39]->out sram[40]->out sram[41]->out sram[42]->out sram[43]->out sram[44]->out sram[45]->out sram[46]->out sram[47]->out sram[48]->out sram[49]->out sram[50]->out sram[51]->out sram[52]->out sram[53]->out sram[54]->out sram[55]->out sram[56]->out sram[57]->out sram[58]->out sram[59]->out sram[60]->out sram[61]->out sram[62]->out sram[63]->out gvdd_lut6[0] sgnd lut6 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[0] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[0] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut6]_ble6[0]_mode[ble6] mode[ble6]->in[0] mode[ble6]->in[1] mode[ble6]->in[2] mode[ble6]->in[3] mode[ble6]->in[4] mode[ble6]->in[5] mode[ble6]->out[0] mode[ble6]->clk[0] svdd sgnd -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] -Xmux_1level_tapbuf_size2[0] ff[0]->Q[0] lut6[0]->out[0] mode[ble6]->out[0] sram[64]->outb sram[64]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[0], level=1, select_path_id=0. ***** -*****1***** -Xsram[64] sram->in sram[64]->out sram[64]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[64]->out) 0 -.nodeset V(sram[64]->outb) vsp -Xdirect_interc[0] mode[ble6]->in[0] lut6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[1] mode[ble6]->in[1] lut6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[2] mode[ble6]->in[2] lut6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[3] mode[ble6]->in[3] lut6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[4] mode[ble6]->in[4] lut6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[5] mode[ble6]->in[5] lut6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[6] lut6[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[7] mode[ble6]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut6] mode[n1_lut6]->in[0] mode[n1_lut6]->in[1] mode[n1_lut6]->in[2] mode[n1_lut6]->in[3] mode[n1_lut6]->in[4] mode[n1_lut6]->in[5] mode[n1_lut6]->out[0] mode[n1_lut6]->clk[0] svdd sgnd -Xble6[0] ble6[0]->in[0] ble6[0]->in[1] ble6[0]->in[2] ble6[0]->in[3] ble6[0]->in[4] ble6[0]->in[5] ble6[0]->out[0] ble6[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut6]_ble6[0]_mode[ble6] -Xdirect_interc[8] ble6[0]->out[0] mode[n1_lut6]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[9] mode[n1_lut6]->in[0] ble6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[10] mode[n1_lut6]->in[1] ble6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[11] mode[n1_lut6]->in[2] ble6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[12] mode[n1_lut6]->in[3] ble6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[13] mode[n1_lut6]->in[4] ble6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[14] mode[n1_lut6]->in[5] ble6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[15] mode[n1_lut6]->clk[0] ble6[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[1]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd -***** Truth Table for LUT[1], size=6. ***** -***** SRAM bits for LUT[1], size=6, num_sram=64. ***** -*****0000000000000000000000000000000000000000000000000000000000000000***** -Xsram[65] sram->in sram[65]->out sram[65]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[65]->out) 0 -.nodeset V(sram[65]->outb) vsp -Xsram[66] sram->in sram[66]->out sram[66]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[66]->out) 0 -.nodeset V(sram[66]->outb) vsp -Xsram[67] sram->in sram[67]->out sram[67]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[67]->out) 0 -.nodeset V(sram[67]->outb) vsp -Xsram[68] sram->in sram[68]->out sram[68]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[68]->out) 0 -.nodeset V(sram[68]->outb) vsp -Xsram[69] sram->in sram[69]->out sram[69]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[69]->out) 0 -.nodeset V(sram[69]->outb) vsp -Xsram[70] sram->in sram[70]->out sram[70]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[70]->out) 0 -.nodeset V(sram[70]->outb) vsp -Xsram[71] sram->in sram[71]->out sram[71]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[71]->out) 0 -.nodeset V(sram[71]->outb) vsp -Xsram[72] sram->in sram[72]->out sram[72]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[72]->out) 0 -.nodeset V(sram[72]->outb) vsp -Xsram[73] sram->in sram[73]->out sram[73]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[73]->out) 0 -.nodeset V(sram[73]->outb) vsp -Xsram[74] sram->in sram[74]->out sram[74]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[74]->out) 0 -.nodeset V(sram[74]->outb) vsp -Xsram[75] sram->in sram[75]->out sram[75]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[75]->out) 0 -.nodeset V(sram[75]->outb) vsp -Xsram[76] sram->in sram[76]->out sram[76]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[76]->out) 0 -.nodeset V(sram[76]->outb) vsp -Xsram[77] sram->in sram[77]->out sram[77]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[77]->out) 0 -.nodeset V(sram[77]->outb) vsp -Xsram[78] sram->in sram[78]->out sram[78]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[78]->out) 0 -.nodeset V(sram[78]->outb) vsp -Xsram[79] sram->in sram[79]->out sram[79]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[79]->out) 0 -.nodeset V(sram[79]->outb) vsp -Xsram[80] sram->in sram[80]->out sram[80]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[80]->out) 0 -.nodeset V(sram[80]->outb) vsp -Xsram[81] sram->in sram[81]->out sram[81]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[81]->out) 0 -.nodeset V(sram[81]->outb) vsp -Xsram[82] sram->in sram[82]->out sram[82]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[82]->out) 0 -.nodeset V(sram[82]->outb) vsp -Xsram[83] sram->in sram[83]->out sram[83]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[83]->out) 0 -.nodeset V(sram[83]->outb) vsp -Xsram[84] sram->in sram[84]->out sram[84]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[84]->out) 0 -.nodeset V(sram[84]->outb) vsp -Xsram[85] sram->in sram[85]->out sram[85]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[85]->out) 0 -.nodeset V(sram[85]->outb) vsp -Xsram[86] sram->in sram[86]->out sram[86]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[86]->out) 0 -.nodeset V(sram[86]->outb) vsp -Xsram[87] sram->in sram[87]->out sram[87]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[87]->out) 0 -.nodeset V(sram[87]->outb) vsp -Xsram[88] sram->in sram[88]->out sram[88]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[88]->out) 0 -.nodeset V(sram[88]->outb) vsp -Xsram[89] sram->in sram[89]->out sram[89]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[89]->out) 0 -.nodeset V(sram[89]->outb) vsp -Xsram[90] sram->in sram[90]->out sram[90]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[90]->out) 0 -.nodeset V(sram[90]->outb) vsp -Xsram[91] sram->in sram[91]->out sram[91]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[91]->out) 0 -.nodeset V(sram[91]->outb) vsp -Xsram[92] sram->in sram[92]->out sram[92]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[92]->out) 0 -.nodeset V(sram[92]->outb) vsp -Xsram[93] sram->in sram[93]->out sram[93]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[93]->out) 0 -.nodeset V(sram[93]->outb) vsp -Xsram[94] sram->in sram[94]->out sram[94]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[94]->out) 0 -.nodeset V(sram[94]->outb) vsp -Xsram[95] sram->in sram[95]->out sram[95]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[95]->out) 0 -.nodeset V(sram[95]->outb) vsp -Xsram[96] sram->in sram[96]->out sram[96]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[96]->out) 0 -.nodeset V(sram[96]->outb) vsp -Xsram[97] sram->in sram[97]->out sram[97]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[97]->out) 0 -.nodeset V(sram[97]->outb) vsp -Xsram[98] sram->in sram[98]->out sram[98]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[98]->out) 0 -.nodeset V(sram[98]->outb) vsp -Xsram[99] sram->in sram[99]->out sram[99]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[99]->out) 0 -.nodeset V(sram[99]->outb) vsp -Xsram[100] sram->in sram[100]->out sram[100]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[100]->out) 0 -.nodeset V(sram[100]->outb) vsp -Xsram[101] sram->in sram[101]->out sram[101]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[101]->out) 0 -.nodeset V(sram[101]->outb) vsp -Xsram[102] sram->in sram[102]->out sram[102]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[102]->out) 0 -.nodeset V(sram[102]->outb) vsp -Xsram[103] sram->in sram[103]->out sram[103]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[103]->out) 0 -.nodeset V(sram[103]->outb) vsp -Xsram[104] sram->in sram[104]->out sram[104]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[104]->out) 0 -.nodeset V(sram[104]->outb) vsp -Xsram[105] sram->in sram[105]->out sram[105]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[105]->out) 0 -.nodeset V(sram[105]->outb) vsp -Xsram[106] sram->in sram[106]->out sram[106]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[106]->out) 0 -.nodeset V(sram[106]->outb) vsp -Xsram[107] sram->in sram[107]->out sram[107]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[107]->out) 0 -.nodeset V(sram[107]->outb) vsp -Xsram[108] sram->in sram[108]->out sram[108]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[108]->out) 0 -.nodeset V(sram[108]->outb) vsp -Xsram[109] sram->in sram[109]->out sram[109]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[109]->out) 0 -.nodeset V(sram[109]->outb) vsp -Xsram[110] sram->in sram[110]->out sram[110]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[110]->out) 0 -.nodeset V(sram[110]->outb) vsp -Xsram[111] sram->in sram[111]->out sram[111]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[111]->out) 0 -.nodeset V(sram[111]->outb) vsp -Xsram[112] sram->in sram[112]->out sram[112]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[112]->out) 0 -.nodeset V(sram[112]->outb) vsp -Xsram[113] sram->in sram[113]->out sram[113]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[113]->out) 0 -.nodeset V(sram[113]->outb) vsp -Xsram[114] sram->in sram[114]->out sram[114]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[114]->out) 0 -.nodeset V(sram[114]->outb) vsp -Xsram[115] sram->in sram[115]->out sram[115]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[115]->out) 0 -.nodeset V(sram[115]->outb) vsp -Xsram[116] sram->in sram[116]->out sram[116]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[116]->out) 0 -.nodeset V(sram[116]->outb) vsp -Xsram[117] sram->in sram[117]->out sram[117]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[117]->out) 0 -.nodeset V(sram[117]->outb) vsp -Xsram[118] sram->in sram[118]->out sram[118]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[118]->out) 0 -.nodeset V(sram[118]->outb) vsp -Xsram[119] sram->in sram[119]->out sram[119]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[119]->out) 0 -.nodeset V(sram[119]->outb) vsp -Xsram[120] sram->in sram[120]->out sram[120]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[120]->out) 0 -.nodeset V(sram[120]->outb) vsp -Xsram[121] sram->in sram[121]->out sram[121]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[121]->out) 0 -.nodeset V(sram[121]->outb) vsp -Xsram[122] sram->in sram[122]->out sram[122]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[122]->out) 0 -.nodeset V(sram[122]->outb) vsp -Xsram[123] sram->in sram[123]->out sram[123]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[123]->out) 0 -.nodeset V(sram[123]->outb) vsp -Xsram[124] sram->in sram[124]->out sram[124]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[124]->out) 0 -.nodeset V(sram[124]->outb) vsp -Xsram[125] sram->in sram[125]->out sram[125]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[125]->out) 0 -.nodeset V(sram[125]->outb) vsp -Xsram[126] sram->in sram[126]->out sram[126]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[126]->out) 0 -.nodeset V(sram[126]->outb) vsp -Xsram[127] sram->in sram[127]->out sram[127]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[127]->out) 0 -.nodeset V(sram[127]->outb) vsp -Xsram[128] sram->in sram[128]->out sram[128]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[128]->out) 0 -.nodeset V(sram[128]->outb) vsp -Xlut6[1] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] sram[65]->out sram[66]->out sram[67]->out sram[68]->out sram[69]->out sram[70]->out sram[71]->out sram[72]->out sram[73]->out sram[74]->out sram[75]->out sram[76]->out sram[77]->out sram[78]->out sram[79]->out sram[80]->out sram[81]->out sram[82]->out sram[83]->out sram[84]->out sram[85]->out sram[86]->out sram[87]->out sram[88]->out sram[89]->out sram[90]->out sram[91]->out sram[92]->out sram[93]->out sram[94]->out sram[95]->out sram[96]->out sram[97]->out sram[98]->out sram[99]->out sram[100]->out sram[101]->out sram[102]->out sram[103]->out sram[104]->out sram[105]->out sram[106]->out sram[107]->out sram[108]->out sram[109]->out sram[110]->out sram[111]->out sram[112]->out sram[113]->out sram[114]->out sram[115]->out sram[116]->out sram[117]->out sram[118]->out sram[119]->out sram[120]->out sram[121]->out sram[122]->out sram[123]->out sram[124]->out sram[125]->out sram[126]->out sram[127]->out sram[128]->out gvdd_lut6[1] sgnd lut6 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[1]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[1] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[1] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[1]_mode[n1_lut6]_ble6[0]_mode[ble6] mode[ble6]->in[0] mode[ble6]->in[1] mode[ble6]->in[2] mode[ble6]->in[3] mode[ble6]->in[4] mode[ble6]->in[5] mode[ble6]->out[0] mode[ble6]->clk[0] svdd sgnd -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[1]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[1]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] -Xmux_1level_tapbuf_size2[1] ff[0]->Q[0] lut6[0]->out[0] mode[ble6]->out[0] sram[129]->outb sram[129]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[1], level=1, select_path_id=0. ***** -*****1***** -Xsram[129] sram->in sram[129]->out sram[129]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[129]->out) 0 -.nodeset V(sram[129]->outb) vsp -Xdirect_interc[16] mode[ble6]->in[0] lut6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[17] mode[ble6]->in[1] lut6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[18] mode[ble6]->in[2] lut6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[19] mode[ble6]->in[3] lut6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[20] mode[ble6]->in[4] lut6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[21] mode[ble6]->in[5] lut6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[22] lut6[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[23] mode[ble6]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[1]_mode[n1_lut6] mode[n1_lut6]->in[0] mode[n1_lut6]->in[1] mode[n1_lut6]->in[2] mode[n1_lut6]->in[3] mode[n1_lut6]->in[4] mode[n1_lut6]->in[5] mode[n1_lut6]->out[0] mode[n1_lut6]->clk[0] svdd sgnd -Xble6[0] ble6[0]->in[0] ble6[0]->in[1] ble6[0]->in[2] ble6[0]->in[3] ble6[0]->in[4] ble6[0]->in[5] ble6[0]->out[0] ble6[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[1]_mode[n1_lut6]_ble6[0]_mode[ble6] -Xdirect_interc[24] ble6[0]->out[0] mode[n1_lut6]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[25] mode[n1_lut6]->in[0] ble6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[26] mode[n1_lut6]->in[1] ble6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[27] mode[n1_lut6]->in[2] ble6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[28] mode[n1_lut6]->in[3] ble6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[29] mode[n1_lut6]->in[4] ble6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[30] mode[n1_lut6]->in[5] ble6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[31] mode[n1_lut6]->clk[0] ble6[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[2]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd -***** Truth Table for LUT[2], size=6. ***** -***** SRAM bits for LUT[2], size=6, num_sram=64. ***** -*****0000000000000000000000000000000000000000000000000000000000000000***** -Xsram[130] sram->in sram[130]->out sram[130]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[130]->out) 0 -.nodeset V(sram[130]->outb) vsp -Xsram[131] sram->in sram[131]->out sram[131]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[131]->out) 0 -.nodeset V(sram[131]->outb) vsp -Xsram[132] sram->in sram[132]->out sram[132]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[132]->out) 0 -.nodeset V(sram[132]->outb) vsp -Xsram[133] sram->in sram[133]->out sram[133]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[133]->out) 0 -.nodeset V(sram[133]->outb) vsp -Xsram[134] sram->in sram[134]->out sram[134]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[134]->out) 0 -.nodeset V(sram[134]->outb) vsp -Xsram[135] sram->in sram[135]->out sram[135]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[135]->out) 0 -.nodeset V(sram[135]->outb) vsp -Xsram[136] sram->in sram[136]->out sram[136]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[136]->out) 0 -.nodeset V(sram[136]->outb) vsp -Xsram[137] sram->in sram[137]->out sram[137]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[137]->out) 0 -.nodeset V(sram[137]->outb) vsp -Xsram[138] sram->in sram[138]->out sram[138]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[138]->out) 0 -.nodeset V(sram[138]->outb) vsp -Xsram[139] sram->in sram[139]->out sram[139]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[139]->out) 0 -.nodeset V(sram[139]->outb) vsp -Xsram[140] sram->in sram[140]->out sram[140]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[140]->out) 0 -.nodeset V(sram[140]->outb) vsp -Xsram[141] sram->in sram[141]->out sram[141]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[141]->out) 0 -.nodeset V(sram[141]->outb) vsp -Xsram[142] sram->in sram[142]->out sram[142]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[142]->out) 0 -.nodeset V(sram[142]->outb) vsp -Xsram[143] sram->in sram[143]->out sram[143]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[143]->out) 0 -.nodeset V(sram[143]->outb) vsp -Xsram[144] sram->in sram[144]->out sram[144]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[144]->out) 0 -.nodeset V(sram[144]->outb) vsp -Xsram[145] sram->in sram[145]->out sram[145]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[145]->out) 0 -.nodeset V(sram[145]->outb) vsp -Xsram[146] sram->in sram[146]->out sram[146]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[146]->out) 0 -.nodeset V(sram[146]->outb) vsp -Xsram[147] sram->in sram[147]->out sram[147]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[147]->out) 0 -.nodeset V(sram[147]->outb) vsp -Xsram[148] sram->in sram[148]->out sram[148]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[148]->out) 0 -.nodeset V(sram[148]->outb) vsp -Xsram[149] sram->in sram[149]->out sram[149]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[149]->out) 0 -.nodeset V(sram[149]->outb) vsp -Xsram[150] sram->in sram[150]->out sram[150]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[150]->out) 0 -.nodeset V(sram[150]->outb) vsp -Xsram[151] sram->in sram[151]->out sram[151]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[151]->out) 0 -.nodeset V(sram[151]->outb) vsp -Xsram[152] sram->in sram[152]->out sram[152]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[152]->out) 0 -.nodeset V(sram[152]->outb) vsp -Xsram[153] sram->in sram[153]->out sram[153]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[153]->out) 0 -.nodeset V(sram[153]->outb) vsp -Xsram[154] sram->in sram[154]->out sram[154]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[154]->out) 0 -.nodeset V(sram[154]->outb) vsp -Xsram[155] sram->in sram[155]->out sram[155]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[155]->out) 0 -.nodeset V(sram[155]->outb) vsp -Xsram[156] sram->in sram[156]->out sram[156]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[156]->out) 0 -.nodeset V(sram[156]->outb) vsp -Xsram[157] sram->in sram[157]->out sram[157]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[157]->out) 0 -.nodeset V(sram[157]->outb) vsp -Xsram[158] sram->in sram[158]->out sram[158]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[158]->out) 0 -.nodeset V(sram[158]->outb) vsp -Xsram[159] sram->in sram[159]->out sram[159]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[159]->out) 0 -.nodeset V(sram[159]->outb) vsp -Xsram[160] sram->in sram[160]->out sram[160]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[160]->out) 0 -.nodeset V(sram[160]->outb) vsp -Xsram[161] sram->in sram[161]->out sram[161]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[161]->out) 0 -.nodeset V(sram[161]->outb) vsp -Xsram[162] sram->in sram[162]->out sram[162]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[162]->out) 0 -.nodeset V(sram[162]->outb) vsp -Xsram[163] sram->in sram[163]->out sram[163]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[163]->out) 0 -.nodeset V(sram[163]->outb) vsp -Xsram[164] sram->in sram[164]->out sram[164]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[164]->out) 0 -.nodeset V(sram[164]->outb) vsp -Xsram[165] sram->in sram[165]->out sram[165]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[165]->out) 0 -.nodeset V(sram[165]->outb) vsp -Xsram[166] sram->in sram[166]->out sram[166]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[166]->out) 0 -.nodeset V(sram[166]->outb) vsp -Xsram[167] sram->in sram[167]->out sram[167]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[167]->out) 0 -.nodeset V(sram[167]->outb) vsp -Xsram[168] sram->in sram[168]->out sram[168]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[168]->out) 0 -.nodeset V(sram[168]->outb) vsp -Xsram[169] sram->in sram[169]->out sram[169]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[169]->out) 0 -.nodeset V(sram[169]->outb) vsp -Xsram[170] sram->in sram[170]->out sram[170]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[170]->out) 0 -.nodeset V(sram[170]->outb) vsp -Xsram[171] sram->in sram[171]->out sram[171]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[171]->out) 0 -.nodeset V(sram[171]->outb) vsp -Xsram[172] sram->in sram[172]->out sram[172]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[172]->out) 0 -.nodeset V(sram[172]->outb) vsp -Xsram[173] sram->in sram[173]->out sram[173]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[173]->out) 0 -.nodeset V(sram[173]->outb) vsp -Xsram[174] sram->in sram[174]->out sram[174]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[174]->out) 0 -.nodeset V(sram[174]->outb) vsp -Xsram[175] sram->in sram[175]->out sram[175]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[175]->out) 0 -.nodeset V(sram[175]->outb) vsp -Xsram[176] sram->in sram[176]->out sram[176]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[176]->out) 0 -.nodeset V(sram[176]->outb) vsp -Xsram[177] sram->in sram[177]->out sram[177]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[177]->out) 0 -.nodeset V(sram[177]->outb) vsp -Xsram[178] sram->in sram[178]->out sram[178]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[178]->out) 0 -.nodeset V(sram[178]->outb) vsp -Xsram[179] sram->in sram[179]->out sram[179]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[179]->out) 0 -.nodeset V(sram[179]->outb) vsp -Xsram[180] sram->in sram[180]->out sram[180]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[180]->out) 0 -.nodeset V(sram[180]->outb) vsp -Xsram[181] sram->in sram[181]->out sram[181]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[181]->out) 0 -.nodeset V(sram[181]->outb) vsp -Xsram[182] sram->in sram[182]->out sram[182]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[182]->out) 0 -.nodeset V(sram[182]->outb) vsp -Xsram[183] sram->in sram[183]->out sram[183]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[183]->out) 0 -.nodeset V(sram[183]->outb) vsp -Xsram[184] sram->in sram[184]->out sram[184]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[184]->out) 0 -.nodeset V(sram[184]->outb) vsp -Xsram[185] sram->in sram[185]->out sram[185]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[185]->out) 0 -.nodeset V(sram[185]->outb) vsp -Xsram[186] sram->in sram[186]->out sram[186]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[186]->out) 0 -.nodeset V(sram[186]->outb) vsp -Xsram[187] sram->in sram[187]->out sram[187]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[187]->out) 0 -.nodeset V(sram[187]->outb) vsp -Xsram[188] sram->in sram[188]->out sram[188]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[188]->out) 0 -.nodeset V(sram[188]->outb) vsp -Xsram[189] sram->in sram[189]->out sram[189]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[189]->out) 0 -.nodeset V(sram[189]->outb) vsp -Xsram[190] sram->in sram[190]->out sram[190]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[190]->out) 0 -.nodeset V(sram[190]->outb) vsp -Xsram[191] sram->in sram[191]->out sram[191]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[191]->out) 0 -.nodeset V(sram[191]->outb) vsp -Xsram[192] sram->in sram[192]->out sram[192]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[192]->out) 0 -.nodeset V(sram[192]->outb) vsp -Xsram[193] sram->in sram[193]->out sram[193]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[193]->out) 0 -.nodeset V(sram[193]->outb) vsp -Xlut6[2] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] sram[130]->out sram[131]->out sram[132]->out sram[133]->out sram[134]->out sram[135]->out sram[136]->out sram[137]->out sram[138]->out sram[139]->out sram[140]->out sram[141]->out sram[142]->out sram[143]->out sram[144]->out sram[145]->out sram[146]->out sram[147]->out sram[148]->out sram[149]->out sram[150]->out sram[151]->out sram[152]->out sram[153]->out sram[154]->out sram[155]->out sram[156]->out sram[157]->out sram[158]->out sram[159]->out sram[160]->out sram[161]->out sram[162]->out sram[163]->out sram[164]->out sram[165]->out sram[166]->out sram[167]->out sram[168]->out sram[169]->out sram[170]->out sram[171]->out sram[172]->out sram[173]->out sram[174]->out sram[175]->out sram[176]->out sram[177]->out sram[178]->out sram[179]->out sram[180]->out sram[181]->out sram[182]->out sram[183]->out sram[184]->out sram[185]->out sram[186]->out sram[187]->out sram[188]->out sram[189]->out sram[190]->out sram[191]->out sram[192]->out sram[193]->out gvdd_lut6[2] sgnd lut6 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[2]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[2] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[2] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[2]_mode[n1_lut6]_ble6[0]_mode[ble6] mode[ble6]->in[0] mode[ble6]->in[1] mode[ble6]->in[2] mode[ble6]->in[3] mode[ble6]->in[4] mode[ble6]->in[5] mode[ble6]->out[0] mode[ble6]->clk[0] svdd sgnd -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[2]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[2]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] -Xmux_1level_tapbuf_size2[2] ff[0]->Q[0] lut6[0]->out[0] mode[ble6]->out[0] sram[194]->outb sram[194]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[2], level=1, select_path_id=0. ***** -*****1***** -Xsram[194] sram->in sram[194]->out sram[194]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[194]->out) 0 -.nodeset V(sram[194]->outb) vsp -Xdirect_interc[32] mode[ble6]->in[0] lut6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[33] mode[ble6]->in[1] lut6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[34] mode[ble6]->in[2] lut6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[35] mode[ble6]->in[3] lut6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[36] mode[ble6]->in[4] lut6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[37] mode[ble6]->in[5] lut6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[38] lut6[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[39] mode[ble6]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[2]_mode[n1_lut6] mode[n1_lut6]->in[0] mode[n1_lut6]->in[1] mode[n1_lut6]->in[2] mode[n1_lut6]->in[3] mode[n1_lut6]->in[4] mode[n1_lut6]->in[5] mode[n1_lut6]->out[0] mode[n1_lut6]->clk[0] svdd sgnd -Xble6[0] ble6[0]->in[0] ble6[0]->in[1] ble6[0]->in[2] ble6[0]->in[3] ble6[0]->in[4] ble6[0]->in[5] ble6[0]->out[0] ble6[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[2]_mode[n1_lut6]_ble6[0]_mode[ble6] -Xdirect_interc[40] ble6[0]->out[0] mode[n1_lut6]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[41] mode[n1_lut6]->in[0] ble6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[42] mode[n1_lut6]->in[1] ble6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[43] mode[n1_lut6]->in[2] ble6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[44] mode[n1_lut6]->in[3] ble6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[45] mode[n1_lut6]->in[4] ble6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[46] mode[n1_lut6]->in[5] ble6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[47] mode[n1_lut6]->clk[0] ble6[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[3]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd -***** Truth Table for LUT[3], size=6. ***** -***** SRAM bits for LUT[3], size=6, num_sram=64. ***** -*****0000000000000000000000000000000000000000000000000000000000000000***** -Xsram[195] sram->in sram[195]->out sram[195]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[195]->out) 0 -.nodeset V(sram[195]->outb) vsp -Xsram[196] sram->in sram[196]->out sram[196]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[196]->out) 0 -.nodeset V(sram[196]->outb) vsp -Xsram[197] sram->in sram[197]->out sram[197]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[197]->out) 0 -.nodeset V(sram[197]->outb) vsp -Xsram[198] sram->in sram[198]->out sram[198]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[198]->out) 0 -.nodeset V(sram[198]->outb) vsp -Xsram[199] sram->in sram[199]->out sram[199]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[199]->out) 0 -.nodeset V(sram[199]->outb) vsp -Xsram[200] sram->in sram[200]->out sram[200]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[200]->out) 0 -.nodeset V(sram[200]->outb) vsp -Xsram[201] sram->in sram[201]->out sram[201]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[201]->out) 0 -.nodeset V(sram[201]->outb) vsp -Xsram[202] sram->in sram[202]->out sram[202]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[202]->out) 0 -.nodeset V(sram[202]->outb) vsp -Xsram[203] sram->in sram[203]->out sram[203]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[203]->out) 0 -.nodeset V(sram[203]->outb) vsp -Xsram[204] sram->in sram[204]->out sram[204]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[204]->out) 0 -.nodeset V(sram[204]->outb) vsp -Xsram[205] sram->in sram[205]->out sram[205]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[205]->out) 0 -.nodeset V(sram[205]->outb) vsp -Xsram[206] sram->in sram[206]->out sram[206]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[206]->out) 0 -.nodeset V(sram[206]->outb) vsp -Xsram[207] sram->in sram[207]->out sram[207]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[207]->out) 0 -.nodeset V(sram[207]->outb) vsp -Xsram[208] sram->in sram[208]->out sram[208]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[208]->out) 0 -.nodeset V(sram[208]->outb) vsp -Xsram[209] sram->in sram[209]->out sram[209]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[209]->out) 0 -.nodeset V(sram[209]->outb) vsp -Xsram[210] sram->in sram[210]->out sram[210]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[210]->out) 0 -.nodeset V(sram[210]->outb) vsp -Xsram[211] sram->in sram[211]->out sram[211]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[211]->out) 0 -.nodeset V(sram[211]->outb) vsp -Xsram[212] sram->in sram[212]->out sram[212]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[212]->out) 0 -.nodeset V(sram[212]->outb) vsp -Xsram[213] sram->in sram[213]->out sram[213]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[213]->out) 0 -.nodeset V(sram[213]->outb) vsp -Xsram[214] sram->in sram[214]->out sram[214]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[214]->out) 0 -.nodeset V(sram[214]->outb) vsp -Xsram[215] sram->in sram[215]->out sram[215]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[215]->out) 0 -.nodeset V(sram[215]->outb) vsp -Xsram[216] sram->in sram[216]->out sram[216]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[216]->out) 0 -.nodeset V(sram[216]->outb) vsp -Xsram[217] sram->in sram[217]->out sram[217]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[217]->out) 0 -.nodeset V(sram[217]->outb) vsp -Xsram[218] sram->in sram[218]->out sram[218]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[218]->out) 0 -.nodeset V(sram[218]->outb) vsp -Xsram[219] sram->in sram[219]->out sram[219]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[219]->out) 0 -.nodeset V(sram[219]->outb) vsp -Xsram[220] sram->in sram[220]->out sram[220]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[220]->out) 0 -.nodeset V(sram[220]->outb) vsp -Xsram[221] sram->in sram[221]->out sram[221]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[221]->out) 0 -.nodeset V(sram[221]->outb) vsp -Xsram[222] sram->in sram[222]->out sram[222]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[222]->out) 0 -.nodeset V(sram[222]->outb) vsp -Xsram[223] sram->in sram[223]->out sram[223]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[223]->out) 0 -.nodeset V(sram[223]->outb) vsp -Xsram[224] sram->in sram[224]->out sram[224]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[224]->out) 0 -.nodeset V(sram[224]->outb) vsp -Xsram[225] sram->in sram[225]->out sram[225]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[225]->out) 0 -.nodeset V(sram[225]->outb) vsp -Xsram[226] sram->in sram[226]->out sram[226]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[226]->out) 0 -.nodeset V(sram[226]->outb) vsp -Xsram[227] sram->in sram[227]->out sram[227]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[227]->out) 0 -.nodeset V(sram[227]->outb) vsp -Xsram[228] sram->in sram[228]->out sram[228]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[228]->out) 0 -.nodeset V(sram[228]->outb) vsp -Xsram[229] sram->in sram[229]->out sram[229]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[229]->out) 0 -.nodeset V(sram[229]->outb) vsp -Xsram[230] sram->in sram[230]->out sram[230]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[230]->out) 0 -.nodeset V(sram[230]->outb) vsp -Xsram[231] sram->in sram[231]->out sram[231]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[231]->out) 0 -.nodeset V(sram[231]->outb) vsp -Xsram[232] sram->in sram[232]->out sram[232]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[232]->out) 0 -.nodeset V(sram[232]->outb) vsp -Xsram[233] sram->in sram[233]->out sram[233]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[233]->out) 0 -.nodeset V(sram[233]->outb) vsp -Xsram[234] sram->in sram[234]->out sram[234]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[234]->out) 0 -.nodeset V(sram[234]->outb) vsp -Xsram[235] sram->in sram[235]->out sram[235]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[235]->out) 0 -.nodeset V(sram[235]->outb) vsp -Xsram[236] sram->in sram[236]->out sram[236]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[236]->out) 0 -.nodeset V(sram[236]->outb) vsp -Xsram[237] sram->in sram[237]->out sram[237]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[237]->out) 0 -.nodeset V(sram[237]->outb) vsp -Xsram[238] sram->in sram[238]->out sram[238]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[238]->out) 0 -.nodeset V(sram[238]->outb) vsp -Xsram[239] sram->in sram[239]->out sram[239]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[239]->out) 0 -.nodeset V(sram[239]->outb) vsp -Xsram[240] sram->in sram[240]->out sram[240]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[240]->out) 0 -.nodeset V(sram[240]->outb) vsp -Xsram[241] sram->in sram[241]->out sram[241]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[241]->out) 0 -.nodeset V(sram[241]->outb) vsp -Xsram[242] sram->in sram[242]->out sram[242]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[242]->out) 0 -.nodeset V(sram[242]->outb) vsp -Xsram[243] sram->in sram[243]->out sram[243]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[243]->out) 0 -.nodeset V(sram[243]->outb) vsp -Xsram[244] sram->in sram[244]->out sram[244]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[244]->out) 0 -.nodeset V(sram[244]->outb) vsp -Xsram[245] sram->in sram[245]->out sram[245]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[245]->out) 0 -.nodeset V(sram[245]->outb) vsp -Xsram[246] sram->in sram[246]->out sram[246]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[246]->out) 0 -.nodeset V(sram[246]->outb) vsp -Xsram[247] sram->in sram[247]->out sram[247]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[247]->out) 0 -.nodeset V(sram[247]->outb) vsp -Xsram[248] sram->in sram[248]->out sram[248]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[248]->out) 0 -.nodeset V(sram[248]->outb) vsp -Xsram[249] sram->in sram[249]->out sram[249]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[249]->out) 0 -.nodeset V(sram[249]->outb) vsp -Xsram[250] sram->in sram[250]->out sram[250]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[250]->out) 0 -.nodeset V(sram[250]->outb) vsp -Xsram[251] sram->in sram[251]->out sram[251]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[251]->out) 0 -.nodeset V(sram[251]->outb) vsp -Xsram[252] sram->in sram[252]->out sram[252]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[252]->out) 0 -.nodeset V(sram[252]->outb) vsp -Xsram[253] sram->in sram[253]->out sram[253]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[253]->out) 0 -.nodeset V(sram[253]->outb) vsp -Xsram[254] sram->in sram[254]->out sram[254]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[254]->out) 0 -.nodeset V(sram[254]->outb) vsp -Xsram[255] sram->in sram[255]->out sram[255]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[255]->out) 0 -.nodeset V(sram[255]->outb) vsp -Xsram[256] sram->in sram[256]->out sram[256]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[256]->out) 0 -.nodeset V(sram[256]->outb) vsp -Xsram[257] sram->in sram[257]->out sram[257]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[257]->out) 0 -.nodeset V(sram[257]->outb) vsp -Xsram[258] sram->in sram[258]->out sram[258]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[258]->out) 0 -.nodeset V(sram[258]->outb) vsp -Xlut6[3] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] sram[195]->out sram[196]->out sram[197]->out sram[198]->out sram[199]->out sram[200]->out sram[201]->out sram[202]->out sram[203]->out sram[204]->out sram[205]->out sram[206]->out sram[207]->out sram[208]->out sram[209]->out sram[210]->out sram[211]->out sram[212]->out sram[213]->out sram[214]->out sram[215]->out sram[216]->out sram[217]->out sram[218]->out sram[219]->out sram[220]->out sram[221]->out sram[222]->out sram[223]->out sram[224]->out sram[225]->out sram[226]->out sram[227]->out sram[228]->out sram[229]->out sram[230]->out sram[231]->out sram[232]->out sram[233]->out sram[234]->out sram[235]->out sram[236]->out sram[237]->out sram[238]->out sram[239]->out sram[240]->out sram[241]->out sram[242]->out sram[243]->out sram[244]->out sram[245]->out sram[246]->out sram[247]->out sram[248]->out sram[249]->out sram[250]->out sram[251]->out sram[252]->out sram[253]->out sram[254]->out sram[255]->out sram[256]->out sram[257]->out sram[258]->out gvdd_lut6[3] sgnd lut6 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[3]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[3] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[3] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[3]_mode[n1_lut6]_ble6[0]_mode[ble6] mode[ble6]->in[0] mode[ble6]->in[1] mode[ble6]->in[2] mode[ble6]->in[3] mode[ble6]->in[4] mode[ble6]->in[5] mode[ble6]->out[0] mode[ble6]->clk[0] svdd sgnd -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[3]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[3]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] -Xmux_1level_tapbuf_size2[3] ff[0]->Q[0] lut6[0]->out[0] mode[ble6]->out[0] sram[259]->outb sram[259]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[3], level=1, select_path_id=0. ***** -*****1***** -Xsram[259] sram->in sram[259]->out sram[259]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[259]->out) 0 -.nodeset V(sram[259]->outb) vsp -Xdirect_interc[48] mode[ble6]->in[0] lut6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[49] mode[ble6]->in[1] lut6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[50] mode[ble6]->in[2] lut6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[51] mode[ble6]->in[3] lut6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[52] mode[ble6]->in[4] lut6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[53] mode[ble6]->in[5] lut6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[54] lut6[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[55] mode[ble6]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[3]_mode[n1_lut6] mode[n1_lut6]->in[0] mode[n1_lut6]->in[1] mode[n1_lut6]->in[2] mode[n1_lut6]->in[3] mode[n1_lut6]->in[4] mode[n1_lut6]->in[5] mode[n1_lut6]->out[0] mode[n1_lut6]->clk[0] svdd sgnd -Xble6[0] ble6[0]->in[0] ble6[0]->in[1] ble6[0]->in[2] ble6[0]->in[3] ble6[0]->in[4] ble6[0]->in[5] ble6[0]->out[0] ble6[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[3]_mode[n1_lut6]_ble6[0]_mode[ble6] -Xdirect_interc[56] ble6[0]->out[0] mode[n1_lut6]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[57] mode[n1_lut6]->in[0] ble6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[58] mode[n1_lut6]->in[1] ble6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[59] mode[n1_lut6]->in[2] ble6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[60] mode[n1_lut6]->in[3] ble6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[61] mode[n1_lut6]->in[4] ble6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[62] mode[n1_lut6]->in[5] ble6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[63] mode[n1_lut6]->clk[0] ble6[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[4]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd -***** Truth Table for LUT[4], size=6. ***** -***** SRAM bits for LUT[4], size=6, num_sram=64. ***** -*****0000000000000000000000000000000000000000000000000000000000000000***** -Xsram[260] sram->in sram[260]->out sram[260]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[260]->out) 0 -.nodeset V(sram[260]->outb) vsp -Xsram[261] sram->in sram[261]->out sram[261]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[261]->out) 0 -.nodeset V(sram[261]->outb) vsp -Xsram[262] sram->in sram[262]->out sram[262]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[262]->out) 0 -.nodeset V(sram[262]->outb) vsp -Xsram[263] sram->in sram[263]->out sram[263]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[263]->out) 0 -.nodeset V(sram[263]->outb) vsp -Xsram[264] sram->in sram[264]->out sram[264]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[264]->out) 0 -.nodeset V(sram[264]->outb) vsp -Xsram[265] sram->in sram[265]->out sram[265]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[265]->out) 0 -.nodeset V(sram[265]->outb) vsp -Xsram[266] sram->in sram[266]->out sram[266]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[266]->out) 0 -.nodeset V(sram[266]->outb) vsp -Xsram[267] sram->in sram[267]->out sram[267]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[267]->out) 0 -.nodeset V(sram[267]->outb) vsp -Xsram[268] sram->in sram[268]->out sram[268]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[268]->out) 0 -.nodeset V(sram[268]->outb) vsp -Xsram[269] sram->in sram[269]->out sram[269]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[269]->out) 0 -.nodeset V(sram[269]->outb) vsp -Xsram[270] sram->in sram[270]->out sram[270]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[270]->out) 0 -.nodeset V(sram[270]->outb) vsp -Xsram[271] sram->in sram[271]->out sram[271]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[271]->out) 0 -.nodeset V(sram[271]->outb) vsp -Xsram[272] sram->in sram[272]->out sram[272]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[272]->out) 0 -.nodeset V(sram[272]->outb) vsp -Xsram[273] sram->in sram[273]->out sram[273]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[273]->out) 0 -.nodeset V(sram[273]->outb) vsp -Xsram[274] sram->in sram[274]->out sram[274]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[274]->out) 0 -.nodeset V(sram[274]->outb) vsp -Xsram[275] sram->in sram[275]->out sram[275]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[275]->out) 0 -.nodeset V(sram[275]->outb) vsp -Xsram[276] sram->in sram[276]->out sram[276]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[276]->out) 0 -.nodeset V(sram[276]->outb) vsp -Xsram[277] sram->in sram[277]->out sram[277]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[277]->out) 0 -.nodeset V(sram[277]->outb) vsp -Xsram[278] sram->in sram[278]->out sram[278]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[278]->out) 0 -.nodeset V(sram[278]->outb) vsp -Xsram[279] sram->in sram[279]->out sram[279]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[279]->out) 0 -.nodeset V(sram[279]->outb) vsp -Xsram[280] sram->in sram[280]->out sram[280]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[280]->out) 0 -.nodeset V(sram[280]->outb) vsp -Xsram[281] sram->in sram[281]->out sram[281]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[281]->out) 0 -.nodeset V(sram[281]->outb) vsp -Xsram[282] sram->in sram[282]->out sram[282]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[282]->out) 0 -.nodeset V(sram[282]->outb) vsp -Xsram[283] sram->in sram[283]->out sram[283]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[283]->out) 0 -.nodeset V(sram[283]->outb) vsp -Xsram[284] sram->in sram[284]->out sram[284]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[284]->out) 0 -.nodeset V(sram[284]->outb) vsp -Xsram[285] sram->in sram[285]->out sram[285]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[285]->out) 0 -.nodeset V(sram[285]->outb) vsp -Xsram[286] sram->in sram[286]->out sram[286]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[286]->out) 0 -.nodeset V(sram[286]->outb) vsp -Xsram[287] sram->in sram[287]->out sram[287]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[287]->out) 0 -.nodeset V(sram[287]->outb) vsp -Xsram[288] sram->in sram[288]->out sram[288]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[288]->out) 0 -.nodeset V(sram[288]->outb) vsp -Xsram[289] sram->in sram[289]->out sram[289]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[289]->out) 0 -.nodeset V(sram[289]->outb) vsp -Xsram[290] sram->in sram[290]->out sram[290]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[290]->out) 0 -.nodeset V(sram[290]->outb) vsp -Xsram[291] sram->in sram[291]->out sram[291]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[291]->out) 0 -.nodeset V(sram[291]->outb) vsp -Xsram[292] sram->in sram[292]->out sram[292]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[292]->out) 0 -.nodeset V(sram[292]->outb) vsp -Xsram[293] sram->in sram[293]->out sram[293]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[293]->out) 0 -.nodeset V(sram[293]->outb) vsp -Xsram[294] sram->in sram[294]->out sram[294]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[294]->out) 0 -.nodeset V(sram[294]->outb) vsp -Xsram[295] sram->in sram[295]->out sram[295]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[295]->out) 0 -.nodeset V(sram[295]->outb) vsp -Xsram[296] sram->in sram[296]->out sram[296]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[296]->out) 0 -.nodeset V(sram[296]->outb) vsp -Xsram[297] sram->in sram[297]->out sram[297]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[297]->out) 0 -.nodeset V(sram[297]->outb) vsp -Xsram[298] sram->in sram[298]->out sram[298]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[298]->out) 0 -.nodeset V(sram[298]->outb) vsp -Xsram[299] sram->in sram[299]->out sram[299]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[299]->out) 0 -.nodeset V(sram[299]->outb) vsp -Xsram[300] sram->in sram[300]->out sram[300]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[300]->out) 0 -.nodeset V(sram[300]->outb) vsp -Xsram[301] sram->in sram[301]->out sram[301]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[301]->out) 0 -.nodeset V(sram[301]->outb) vsp -Xsram[302] sram->in sram[302]->out sram[302]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[302]->out) 0 -.nodeset V(sram[302]->outb) vsp -Xsram[303] sram->in sram[303]->out sram[303]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[303]->out) 0 -.nodeset V(sram[303]->outb) vsp -Xsram[304] sram->in sram[304]->out sram[304]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[304]->out) 0 -.nodeset V(sram[304]->outb) vsp -Xsram[305] sram->in sram[305]->out sram[305]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[305]->out) 0 -.nodeset V(sram[305]->outb) vsp -Xsram[306] sram->in sram[306]->out sram[306]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[306]->out) 0 -.nodeset V(sram[306]->outb) vsp -Xsram[307] sram->in sram[307]->out sram[307]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[307]->out) 0 -.nodeset V(sram[307]->outb) vsp -Xsram[308] sram->in sram[308]->out sram[308]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[308]->out) 0 -.nodeset V(sram[308]->outb) vsp -Xsram[309] sram->in sram[309]->out sram[309]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[309]->out) 0 -.nodeset V(sram[309]->outb) vsp -Xsram[310] sram->in sram[310]->out sram[310]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[310]->out) 0 -.nodeset V(sram[310]->outb) vsp -Xsram[311] sram->in sram[311]->out sram[311]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[311]->out) 0 -.nodeset V(sram[311]->outb) vsp -Xsram[312] sram->in sram[312]->out sram[312]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[312]->out) 0 -.nodeset V(sram[312]->outb) vsp -Xsram[313] sram->in sram[313]->out sram[313]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[313]->out) 0 -.nodeset V(sram[313]->outb) vsp -Xsram[314] sram->in sram[314]->out sram[314]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[314]->out) 0 -.nodeset V(sram[314]->outb) vsp -Xsram[315] sram->in sram[315]->out sram[315]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[315]->out) 0 -.nodeset V(sram[315]->outb) vsp -Xsram[316] sram->in sram[316]->out sram[316]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[316]->out) 0 -.nodeset V(sram[316]->outb) vsp -Xsram[317] sram->in sram[317]->out sram[317]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[317]->out) 0 -.nodeset V(sram[317]->outb) vsp -Xsram[318] sram->in sram[318]->out sram[318]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[318]->out) 0 -.nodeset V(sram[318]->outb) vsp -Xsram[319] sram->in sram[319]->out sram[319]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[319]->out) 0 -.nodeset V(sram[319]->outb) vsp -Xsram[320] sram->in sram[320]->out sram[320]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[320]->out) 0 -.nodeset V(sram[320]->outb) vsp -Xsram[321] sram->in sram[321]->out sram[321]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[321]->out) 0 -.nodeset V(sram[321]->outb) vsp -Xsram[322] sram->in sram[322]->out sram[322]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[322]->out) 0 -.nodeset V(sram[322]->outb) vsp -Xsram[323] sram->in sram[323]->out sram[323]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[323]->out) 0 -.nodeset V(sram[323]->outb) vsp -Xlut6[4] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] sram[260]->out sram[261]->out sram[262]->out sram[263]->out sram[264]->out sram[265]->out sram[266]->out sram[267]->out sram[268]->out sram[269]->out sram[270]->out sram[271]->out sram[272]->out sram[273]->out sram[274]->out sram[275]->out sram[276]->out sram[277]->out sram[278]->out sram[279]->out sram[280]->out sram[281]->out sram[282]->out sram[283]->out sram[284]->out sram[285]->out sram[286]->out sram[287]->out sram[288]->out sram[289]->out sram[290]->out sram[291]->out sram[292]->out sram[293]->out sram[294]->out sram[295]->out sram[296]->out sram[297]->out sram[298]->out sram[299]->out sram[300]->out sram[301]->out sram[302]->out sram[303]->out sram[304]->out sram[305]->out sram[306]->out sram[307]->out sram[308]->out sram[309]->out sram[310]->out sram[311]->out sram[312]->out sram[313]->out sram[314]->out sram[315]->out sram[316]->out sram[317]->out sram[318]->out sram[319]->out sram[320]->out sram[321]->out sram[322]->out sram[323]->out gvdd_lut6[4] sgnd lut6 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[4]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[4] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[4] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[4]_mode[n1_lut6]_ble6[0]_mode[ble6] mode[ble6]->in[0] mode[ble6]->in[1] mode[ble6]->in[2] mode[ble6]->in[3] mode[ble6]->in[4] mode[ble6]->in[5] mode[ble6]->out[0] mode[ble6]->clk[0] svdd sgnd -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[4]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[4]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] -Xmux_1level_tapbuf_size2[4] ff[0]->Q[0] lut6[0]->out[0] mode[ble6]->out[0] sram[324]->outb sram[324]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[4], level=1, select_path_id=0. ***** -*****1***** -Xsram[324] sram->in sram[324]->out sram[324]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[324]->out) 0 -.nodeset V(sram[324]->outb) vsp -Xdirect_interc[64] mode[ble6]->in[0] lut6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[65] mode[ble6]->in[1] lut6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[66] mode[ble6]->in[2] lut6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[67] mode[ble6]->in[3] lut6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[68] mode[ble6]->in[4] lut6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[69] mode[ble6]->in[5] lut6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[70] lut6[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[71] mode[ble6]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[4]_mode[n1_lut6] mode[n1_lut6]->in[0] mode[n1_lut6]->in[1] mode[n1_lut6]->in[2] mode[n1_lut6]->in[3] mode[n1_lut6]->in[4] mode[n1_lut6]->in[5] mode[n1_lut6]->out[0] mode[n1_lut6]->clk[0] svdd sgnd -Xble6[0] ble6[0]->in[0] ble6[0]->in[1] ble6[0]->in[2] ble6[0]->in[3] ble6[0]->in[4] ble6[0]->in[5] ble6[0]->out[0] ble6[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[4]_mode[n1_lut6]_ble6[0]_mode[ble6] -Xdirect_interc[72] ble6[0]->out[0] mode[n1_lut6]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[73] mode[n1_lut6]->in[0] ble6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[74] mode[n1_lut6]->in[1] ble6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[75] mode[n1_lut6]->in[2] ble6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[76] mode[n1_lut6]->in[3] ble6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[77] mode[n1_lut6]->in[4] ble6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[78] mode[n1_lut6]->in[5] ble6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[79] mode[n1_lut6]->clk[0] ble6[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[5]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd -***** Truth Table for LUT[5], size=6. ***** -***** SRAM bits for LUT[5], size=6, num_sram=64. ***** -*****0000000000000000000000000000000000000000000000000000000000000000***** -Xsram[325] sram->in sram[325]->out sram[325]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[325]->out) 0 -.nodeset V(sram[325]->outb) vsp -Xsram[326] sram->in sram[326]->out sram[326]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[326]->out) 0 -.nodeset V(sram[326]->outb) vsp -Xsram[327] sram->in sram[327]->out sram[327]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[327]->out) 0 -.nodeset V(sram[327]->outb) vsp -Xsram[328] sram->in sram[328]->out sram[328]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[328]->out) 0 -.nodeset V(sram[328]->outb) vsp -Xsram[329] sram->in sram[329]->out sram[329]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[329]->out) 0 -.nodeset V(sram[329]->outb) vsp -Xsram[330] sram->in sram[330]->out sram[330]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[330]->out) 0 -.nodeset V(sram[330]->outb) vsp -Xsram[331] sram->in sram[331]->out sram[331]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[331]->out) 0 -.nodeset V(sram[331]->outb) vsp -Xsram[332] sram->in sram[332]->out sram[332]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[332]->out) 0 -.nodeset V(sram[332]->outb) vsp -Xsram[333] sram->in sram[333]->out sram[333]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[333]->out) 0 -.nodeset V(sram[333]->outb) vsp -Xsram[334] sram->in sram[334]->out sram[334]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[334]->out) 0 -.nodeset V(sram[334]->outb) vsp -Xsram[335] sram->in sram[335]->out sram[335]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[335]->out) 0 -.nodeset V(sram[335]->outb) vsp -Xsram[336] sram->in sram[336]->out sram[336]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[336]->out) 0 -.nodeset V(sram[336]->outb) vsp -Xsram[337] sram->in sram[337]->out sram[337]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[337]->out) 0 -.nodeset V(sram[337]->outb) vsp -Xsram[338] sram->in sram[338]->out sram[338]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[338]->out) 0 -.nodeset V(sram[338]->outb) vsp -Xsram[339] sram->in sram[339]->out sram[339]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[339]->out) 0 -.nodeset V(sram[339]->outb) vsp -Xsram[340] sram->in sram[340]->out sram[340]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[340]->out) 0 -.nodeset V(sram[340]->outb) vsp -Xsram[341] sram->in sram[341]->out sram[341]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[341]->out) 0 -.nodeset V(sram[341]->outb) vsp -Xsram[342] sram->in sram[342]->out sram[342]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[342]->out) 0 -.nodeset V(sram[342]->outb) vsp -Xsram[343] sram->in sram[343]->out sram[343]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[343]->out) 0 -.nodeset V(sram[343]->outb) vsp -Xsram[344] sram->in sram[344]->out sram[344]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[344]->out) 0 -.nodeset V(sram[344]->outb) vsp -Xsram[345] sram->in sram[345]->out sram[345]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[345]->out) 0 -.nodeset V(sram[345]->outb) vsp -Xsram[346] sram->in sram[346]->out sram[346]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[346]->out) 0 -.nodeset V(sram[346]->outb) vsp -Xsram[347] sram->in sram[347]->out sram[347]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[347]->out) 0 -.nodeset V(sram[347]->outb) vsp -Xsram[348] sram->in sram[348]->out sram[348]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[348]->out) 0 -.nodeset V(sram[348]->outb) vsp -Xsram[349] sram->in sram[349]->out sram[349]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[349]->out) 0 -.nodeset V(sram[349]->outb) vsp -Xsram[350] sram->in sram[350]->out sram[350]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[350]->out) 0 -.nodeset V(sram[350]->outb) vsp -Xsram[351] sram->in sram[351]->out sram[351]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[351]->out) 0 -.nodeset V(sram[351]->outb) vsp -Xsram[352] sram->in sram[352]->out sram[352]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[352]->out) 0 -.nodeset V(sram[352]->outb) vsp -Xsram[353] sram->in sram[353]->out sram[353]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[353]->out) 0 -.nodeset V(sram[353]->outb) vsp -Xsram[354] sram->in sram[354]->out sram[354]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[354]->out) 0 -.nodeset V(sram[354]->outb) vsp -Xsram[355] sram->in sram[355]->out sram[355]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[355]->out) 0 -.nodeset V(sram[355]->outb) vsp -Xsram[356] sram->in sram[356]->out sram[356]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[356]->out) 0 -.nodeset V(sram[356]->outb) vsp -Xsram[357] sram->in sram[357]->out sram[357]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[357]->out) 0 -.nodeset V(sram[357]->outb) vsp -Xsram[358] sram->in sram[358]->out sram[358]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[358]->out) 0 -.nodeset V(sram[358]->outb) vsp -Xsram[359] sram->in sram[359]->out sram[359]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[359]->out) 0 -.nodeset V(sram[359]->outb) vsp -Xsram[360] sram->in sram[360]->out sram[360]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[360]->out) 0 -.nodeset V(sram[360]->outb) vsp -Xsram[361] sram->in sram[361]->out sram[361]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[361]->out) 0 -.nodeset V(sram[361]->outb) vsp -Xsram[362] sram->in sram[362]->out sram[362]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[362]->out) 0 -.nodeset V(sram[362]->outb) vsp -Xsram[363] sram->in sram[363]->out sram[363]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[363]->out) 0 -.nodeset V(sram[363]->outb) vsp -Xsram[364] sram->in sram[364]->out sram[364]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[364]->out) 0 -.nodeset V(sram[364]->outb) vsp -Xsram[365] sram->in sram[365]->out sram[365]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[365]->out) 0 -.nodeset V(sram[365]->outb) vsp -Xsram[366] sram->in sram[366]->out sram[366]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[366]->out) 0 -.nodeset V(sram[366]->outb) vsp -Xsram[367] sram->in sram[367]->out sram[367]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[367]->out) 0 -.nodeset V(sram[367]->outb) vsp -Xsram[368] sram->in sram[368]->out sram[368]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[368]->out) 0 -.nodeset V(sram[368]->outb) vsp -Xsram[369] sram->in sram[369]->out sram[369]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[369]->out) 0 -.nodeset V(sram[369]->outb) vsp -Xsram[370] sram->in sram[370]->out sram[370]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[370]->out) 0 -.nodeset V(sram[370]->outb) vsp -Xsram[371] sram->in sram[371]->out sram[371]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[371]->out) 0 -.nodeset V(sram[371]->outb) vsp -Xsram[372] sram->in sram[372]->out sram[372]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[372]->out) 0 -.nodeset V(sram[372]->outb) vsp -Xsram[373] sram->in sram[373]->out sram[373]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[373]->out) 0 -.nodeset V(sram[373]->outb) vsp -Xsram[374] sram->in sram[374]->out sram[374]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[374]->out) 0 -.nodeset V(sram[374]->outb) vsp -Xsram[375] sram->in sram[375]->out sram[375]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[375]->out) 0 -.nodeset V(sram[375]->outb) vsp -Xsram[376] sram->in sram[376]->out sram[376]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[376]->out) 0 -.nodeset V(sram[376]->outb) vsp -Xsram[377] sram->in sram[377]->out sram[377]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[377]->out) 0 -.nodeset V(sram[377]->outb) vsp -Xsram[378] sram->in sram[378]->out sram[378]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[378]->out) 0 -.nodeset V(sram[378]->outb) vsp -Xsram[379] sram->in sram[379]->out sram[379]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[379]->out) 0 -.nodeset V(sram[379]->outb) vsp -Xsram[380] sram->in sram[380]->out sram[380]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[380]->out) 0 -.nodeset V(sram[380]->outb) vsp -Xsram[381] sram->in sram[381]->out sram[381]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[381]->out) 0 -.nodeset V(sram[381]->outb) vsp -Xsram[382] sram->in sram[382]->out sram[382]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[382]->out) 0 -.nodeset V(sram[382]->outb) vsp -Xsram[383] sram->in sram[383]->out sram[383]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[383]->out) 0 -.nodeset V(sram[383]->outb) vsp -Xsram[384] sram->in sram[384]->out sram[384]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[384]->out) 0 -.nodeset V(sram[384]->outb) vsp -Xsram[385] sram->in sram[385]->out sram[385]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[385]->out) 0 -.nodeset V(sram[385]->outb) vsp -Xsram[386] sram->in sram[386]->out sram[386]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[386]->out) 0 -.nodeset V(sram[386]->outb) vsp -Xsram[387] sram->in sram[387]->out sram[387]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[387]->out) 0 -.nodeset V(sram[387]->outb) vsp -Xsram[388] sram->in sram[388]->out sram[388]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[388]->out) 0 -.nodeset V(sram[388]->outb) vsp -Xlut6[5] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] sram[325]->out sram[326]->out sram[327]->out sram[328]->out sram[329]->out sram[330]->out sram[331]->out sram[332]->out sram[333]->out sram[334]->out sram[335]->out sram[336]->out sram[337]->out sram[338]->out sram[339]->out sram[340]->out sram[341]->out sram[342]->out sram[343]->out sram[344]->out sram[345]->out sram[346]->out sram[347]->out sram[348]->out sram[349]->out sram[350]->out sram[351]->out sram[352]->out sram[353]->out sram[354]->out sram[355]->out sram[356]->out sram[357]->out sram[358]->out sram[359]->out sram[360]->out sram[361]->out sram[362]->out sram[363]->out sram[364]->out sram[365]->out sram[366]->out sram[367]->out sram[368]->out sram[369]->out sram[370]->out sram[371]->out sram[372]->out sram[373]->out sram[374]->out sram[375]->out sram[376]->out sram[377]->out sram[378]->out sram[379]->out sram[380]->out sram[381]->out sram[382]->out sram[383]->out sram[384]->out sram[385]->out sram[386]->out sram[387]->out sram[388]->out gvdd_lut6[5] sgnd lut6 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[5]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[5] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[5] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[5]_mode[n1_lut6]_ble6[0]_mode[ble6] mode[ble6]->in[0] mode[ble6]->in[1] mode[ble6]->in[2] mode[ble6]->in[3] mode[ble6]->in[4] mode[ble6]->in[5] mode[ble6]->out[0] mode[ble6]->clk[0] svdd sgnd -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[5]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[5]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] -Xmux_1level_tapbuf_size2[5] ff[0]->Q[0] lut6[0]->out[0] mode[ble6]->out[0] sram[389]->outb sram[389]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[5], level=1, select_path_id=0. ***** -*****1***** -Xsram[389] sram->in sram[389]->out sram[389]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[389]->out) 0 -.nodeset V(sram[389]->outb) vsp -Xdirect_interc[80] mode[ble6]->in[0] lut6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[81] mode[ble6]->in[1] lut6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[82] mode[ble6]->in[2] lut6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[83] mode[ble6]->in[3] lut6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[84] mode[ble6]->in[4] lut6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[85] mode[ble6]->in[5] lut6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[86] lut6[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[87] mode[ble6]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[5]_mode[n1_lut6] mode[n1_lut6]->in[0] mode[n1_lut6]->in[1] mode[n1_lut6]->in[2] mode[n1_lut6]->in[3] mode[n1_lut6]->in[4] mode[n1_lut6]->in[5] mode[n1_lut6]->out[0] mode[n1_lut6]->clk[0] svdd sgnd -Xble6[0] ble6[0]->in[0] ble6[0]->in[1] ble6[0]->in[2] ble6[0]->in[3] ble6[0]->in[4] ble6[0]->in[5] ble6[0]->out[0] ble6[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[5]_mode[n1_lut6]_ble6[0]_mode[ble6] -Xdirect_interc[88] ble6[0]->out[0] mode[n1_lut6]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[89] mode[n1_lut6]->in[0] ble6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[90] mode[n1_lut6]->in[1] ble6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[91] mode[n1_lut6]->in[2] ble6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[92] mode[n1_lut6]->in[3] ble6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[93] mode[n1_lut6]->in[4] ble6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[94] mode[n1_lut6]->in[5] ble6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[95] mode[n1_lut6]->clk[0] ble6[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[6]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd -***** Truth Table for LUT[6], size=6. ***** -***** SRAM bits for LUT[6], size=6, num_sram=64. ***** -*****0000000000000000000000000000000000000000000000000000000000000000***** -Xsram[390] sram->in sram[390]->out sram[390]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[390]->out) 0 -.nodeset V(sram[390]->outb) vsp -Xsram[391] sram->in sram[391]->out sram[391]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[391]->out) 0 -.nodeset V(sram[391]->outb) vsp -Xsram[392] sram->in sram[392]->out sram[392]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[392]->out) 0 -.nodeset V(sram[392]->outb) vsp -Xsram[393] sram->in sram[393]->out sram[393]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[393]->out) 0 -.nodeset V(sram[393]->outb) vsp -Xsram[394] sram->in sram[394]->out sram[394]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[394]->out) 0 -.nodeset V(sram[394]->outb) vsp -Xsram[395] sram->in sram[395]->out sram[395]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[395]->out) 0 -.nodeset V(sram[395]->outb) vsp -Xsram[396] sram->in sram[396]->out sram[396]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[396]->out) 0 -.nodeset V(sram[396]->outb) vsp -Xsram[397] sram->in sram[397]->out sram[397]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[397]->out) 0 -.nodeset V(sram[397]->outb) vsp -Xsram[398] sram->in sram[398]->out sram[398]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[398]->out) 0 -.nodeset V(sram[398]->outb) vsp -Xsram[399] sram->in sram[399]->out sram[399]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[399]->out) 0 -.nodeset V(sram[399]->outb) vsp -Xsram[400] sram->in sram[400]->out sram[400]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[400]->out) 0 -.nodeset V(sram[400]->outb) vsp -Xsram[401] sram->in sram[401]->out sram[401]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[401]->out) 0 -.nodeset V(sram[401]->outb) vsp -Xsram[402] sram->in sram[402]->out sram[402]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[402]->out) 0 -.nodeset V(sram[402]->outb) vsp -Xsram[403] sram->in sram[403]->out sram[403]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[403]->out) 0 -.nodeset V(sram[403]->outb) vsp -Xsram[404] sram->in sram[404]->out sram[404]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[404]->out) 0 -.nodeset V(sram[404]->outb) vsp -Xsram[405] sram->in sram[405]->out sram[405]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[405]->out) 0 -.nodeset V(sram[405]->outb) vsp -Xsram[406] sram->in sram[406]->out sram[406]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[406]->out) 0 -.nodeset V(sram[406]->outb) vsp -Xsram[407] sram->in sram[407]->out sram[407]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[407]->out) 0 -.nodeset V(sram[407]->outb) vsp -Xsram[408] sram->in sram[408]->out sram[408]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[408]->out) 0 -.nodeset V(sram[408]->outb) vsp -Xsram[409] sram->in sram[409]->out sram[409]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[409]->out) 0 -.nodeset V(sram[409]->outb) vsp -Xsram[410] sram->in sram[410]->out sram[410]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[410]->out) 0 -.nodeset V(sram[410]->outb) vsp -Xsram[411] sram->in sram[411]->out sram[411]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[411]->out) 0 -.nodeset V(sram[411]->outb) vsp -Xsram[412] sram->in sram[412]->out sram[412]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[412]->out) 0 -.nodeset V(sram[412]->outb) vsp -Xsram[413] sram->in sram[413]->out sram[413]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[413]->out) 0 -.nodeset V(sram[413]->outb) vsp -Xsram[414] sram->in sram[414]->out sram[414]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[414]->out) 0 -.nodeset V(sram[414]->outb) vsp -Xsram[415] sram->in sram[415]->out sram[415]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[415]->out) 0 -.nodeset V(sram[415]->outb) vsp -Xsram[416] sram->in sram[416]->out sram[416]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[416]->out) 0 -.nodeset V(sram[416]->outb) vsp -Xsram[417] sram->in sram[417]->out sram[417]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[417]->out) 0 -.nodeset V(sram[417]->outb) vsp -Xsram[418] sram->in sram[418]->out sram[418]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[418]->out) 0 -.nodeset V(sram[418]->outb) vsp -Xsram[419] sram->in sram[419]->out sram[419]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[419]->out) 0 -.nodeset V(sram[419]->outb) vsp -Xsram[420] sram->in sram[420]->out sram[420]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[420]->out) 0 -.nodeset V(sram[420]->outb) vsp -Xsram[421] sram->in sram[421]->out sram[421]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[421]->out) 0 -.nodeset V(sram[421]->outb) vsp -Xsram[422] sram->in sram[422]->out sram[422]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[422]->out) 0 -.nodeset V(sram[422]->outb) vsp -Xsram[423] sram->in sram[423]->out sram[423]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[423]->out) 0 -.nodeset V(sram[423]->outb) vsp -Xsram[424] sram->in sram[424]->out sram[424]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[424]->out) 0 -.nodeset V(sram[424]->outb) vsp -Xsram[425] sram->in sram[425]->out sram[425]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[425]->out) 0 -.nodeset V(sram[425]->outb) vsp -Xsram[426] sram->in sram[426]->out sram[426]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[426]->out) 0 -.nodeset V(sram[426]->outb) vsp -Xsram[427] sram->in sram[427]->out sram[427]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[427]->out) 0 -.nodeset V(sram[427]->outb) vsp -Xsram[428] sram->in sram[428]->out sram[428]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[428]->out) 0 -.nodeset V(sram[428]->outb) vsp -Xsram[429] sram->in sram[429]->out sram[429]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[429]->out) 0 -.nodeset V(sram[429]->outb) vsp -Xsram[430] sram->in sram[430]->out sram[430]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[430]->out) 0 -.nodeset V(sram[430]->outb) vsp -Xsram[431] sram->in sram[431]->out sram[431]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[431]->out) 0 -.nodeset V(sram[431]->outb) vsp -Xsram[432] sram->in sram[432]->out sram[432]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[432]->out) 0 -.nodeset V(sram[432]->outb) vsp -Xsram[433] sram->in sram[433]->out sram[433]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[433]->out) 0 -.nodeset V(sram[433]->outb) vsp -Xsram[434] sram->in sram[434]->out sram[434]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[434]->out) 0 -.nodeset V(sram[434]->outb) vsp -Xsram[435] sram->in sram[435]->out sram[435]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[435]->out) 0 -.nodeset V(sram[435]->outb) vsp -Xsram[436] sram->in sram[436]->out sram[436]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[436]->out) 0 -.nodeset V(sram[436]->outb) vsp -Xsram[437] sram->in sram[437]->out sram[437]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[437]->out) 0 -.nodeset V(sram[437]->outb) vsp -Xsram[438] sram->in sram[438]->out sram[438]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[438]->out) 0 -.nodeset V(sram[438]->outb) vsp -Xsram[439] sram->in sram[439]->out sram[439]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[439]->out) 0 -.nodeset V(sram[439]->outb) vsp -Xsram[440] sram->in sram[440]->out sram[440]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[440]->out) 0 -.nodeset V(sram[440]->outb) vsp -Xsram[441] sram->in sram[441]->out sram[441]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[441]->out) 0 -.nodeset V(sram[441]->outb) vsp -Xsram[442] sram->in sram[442]->out sram[442]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[442]->out) 0 -.nodeset V(sram[442]->outb) vsp -Xsram[443] sram->in sram[443]->out sram[443]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[443]->out) 0 -.nodeset V(sram[443]->outb) vsp -Xsram[444] sram->in sram[444]->out sram[444]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[444]->out) 0 -.nodeset V(sram[444]->outb) vsp -Xsram[445] sram->in sram[445]->out sram[445]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[445]->out) 0 -.nodeset V(sram[445]->outb) vsp -Xsram[446] sram->in sram[446]->out sram[446]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[446]->out) 0 -.nodeset V(sram[446]->outb) vsp -Xsram[447] sram->in sram[447]->out sram[447]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[447]->out) 0 -.nodeset V(sram[447]->outb) vsp -Xsram[448] sram->in sram[448]->out sram[448]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[448]->out) 0 -.nodeset V(sram[448]->outb) vsp -Xsram[449] sram->in sram[449]->out sram[449]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[449]->out) 0 -.nodeset V(sram[449]->outb) vsp -Xsram[450] sram->in sram[450]->out sram[450]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[450]->out) 0 -.nodeset V(sram[450]->outb) vsp -Xsram[451] sram->in sram[451]->out sram[451]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[451]->out) 0 -.nodeset V(sram[451]->outb) vsp -Xsram[452] sram->in sram[452]->out sram[452]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[452]->out) 0 -.nodeset V(sram[452]->outb) vsp -Xsram[453] sram->in sram[453]->out sram[453]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[453]->out) 0 -.nodeset V(sram[453]->outb) vsp -Xlut6[6] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] sram[390]->out sram[391]->out sram[392]->out sram[393]->out sram[394]->out sram[395]->out sram[396]->out sram[397]->out sram[398]->out sram[399]->out sram[400]->out sram[401]->out sram[402]->out sram[403]->out sram[404]->out sram[405]->out sram[406]->out sram[407]->out sram[408]->out sram[409]->out sram[410]->out sram[411]->out sram[412]->out sram[413]->out sram[414]->out sram[415]->out sram[416]->out sram[417]->out sram[418]->out sram[419]->out sram[420]->out sram[421]->out sram[422]->out sram[423]->out sram[424]->out sram[425]->out sram[426]->out sram[427]->out sram[428]->out sram[429]->out sram[430]->out sram[431]->out sram[432]->out sram[433]->out sram[434]->out sram[435]->out sram[436]->out sram[437]->out sram[438]->out sram[439]->out sram[440]->out sram[441]->out sram[442]->out sram[443]->out sram[444]->out sram[445]->out sram[446]->out sram[447]->out sram[448]->out sram[449]->out sram[450]->out sram[451]->out sram[452]->out sram[453]->out gvdd_lut6[6] sgnd lut6 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[6]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[6] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[6] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[6]_mode[n1_lut6]_ble6[0]_mode[ble6] mode[ble6]->in[0] mode[ble6]->in[1] mode[ble6]->in[2] mode[ble6]->in[3] mode[ble6]->in[4] mode[ble6]->in[5] mode[ble6]->out[0] mode[ble6]->clk[0] svdd sgnd -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[6]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[6]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] -Xmux_1level_tapbuf_size2[6] ff[0]->Q[0] lut6[0]->out[0] mode[ble6]->out[0] sram[454]->outb sram[454]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[6], level=1, select_path_id=0. ***** -*****1***** -Xsram[454] sram->in sram[454]->out sram[454]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[454]->out) 0 -.nodeset V(sram[454]->outb) vsp -Xdirect_interc[96] mode[ble6]->in[0] lut6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[97] mode[ble6]->in[1] lut6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[98] mode[ble6]->in[2] lut6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[99] mode[ble6]->in[3] lut6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[100] mode[ble6]->in[4] lut6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[101] mode[ble6]->in[5] lut6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[102] lut6[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[103] mode[ble6]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[6]_mode[n1_lut6] mode[n1_lut6]->in[0] mode[n1_lut6]->in[1] mode[n1_lut6]->in[2] mode[n1_lut6]->in[3] mode[n1_lut6]->in[4] mode[n1_lut6]->in[5] mode[n1_lut6]->out[0] mode[n1_lut6]->clk[0] svdd sgnd -Xble6[0] ble6[0]->in[0] ble6[0]->in[1] ble6[0]->in[2] ble6[0]->in[3] ble6[0]->in[4] ble6[0]->in[5] ble6[0]->out[0] ble6[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[6]_mode[n1_lut6]_ble6[0]_mode[ble6] -Xdirect_interc[104] ble6[0]->out[0] mode[n1_lut6]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[105] mode[n1_lut6]->in[0] ble6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[106] mode[n1_lut6]->in[1] ble6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[107] mode[n1_lut6]->in[2] ble6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[108] mode[n1_lut6]->in[3] ble6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[109] mode[n1_lut6]->in[4] ble6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[110] mode[n1_lut6]->in[5] ble6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[111] mode[n1_lut6]->clk[0] ble6[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[7]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd -***** Truth Table for LUT[7], size=6. ***** -***** SRAM bits for LUT[7], size=6, num_sram=64. ***** -*****0000000000000000000000000000000000000000000000000000000000000000***** -Xsram[455] sram->in sram[455]->out sram[455]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[455]->out) 0 -.nodeset V(sram[455]->outb) vsp -Xsram[456] sram->in sram[456]->out sram[456]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[456]->out) 0 -.nodeset V(sram[456]->outb) vsp -Xsram[457] sram->in sram[457]->out sram[457]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[457]->out) 0 -.nodeset V(sram[457]->outb) vsp -Xsram[458] sram->in sram[458]->out sram[458]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[458]->out) 0 -.nodeset V(sram[458]->outb) vsp -Xsram[459] sram->in sram[459]->out sram[459]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[459]->out) 0 -.nodeset V(sram[459]->outb) vsp -Xsram[460] sram->in sram[460]->out sram[460]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[460]->out) 0 -.nodeset V(sram[460]->outb) vsp -Xsram[461] sram->in sram[461]->out sram[461]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[461]->out) 0 -.nodeset V(sram[461]->outb) vsp -Xsram[462] sram->in sram[462]->out sram[462]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[462]->out) 0 -.nodeset V(sram[462]->outb) vsp -Xsram[463] sram->in sram[463]->out sram[463]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[463]->out) 0 -.nodeset V(sram[463]->outb) vsp -Xsram[464] sram->in sram[464]->out sram[464]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[464]->out) 0 -.nodeset V(sram[464]->outb) vsp -Xsram[465] sram->in sram[465]->out sram[465]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[465]->out) 0 -.nodeset V(sram[465]->outb) vsp -Xsram[466] sram->in sram[466]->out sram[466]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[466]->out) 0 -.nodeset V(sram[466]->outb) vsp -Xsram[467] sram->in sram[467]->out sram[467]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[467]->out) 0 -.nodeset V(sram[467]->outb) vsp -Xsram[468] sram->in sram[468]->out sram[468]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[468]->out) 0 -.nodeset V(sram[468]->outb) vsp -Xsram[469] sram->in sram[469]->out sram[469]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[469]->out) 0 -.nodeset V(sram[469]->outb) vsp -Xsram[470] sram->in sram[470]->out sram[470]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[470]->out) 0 -.nodeset V(sram[470]->outb) vsp -Xsram[471] sram->in sram[471]->out sram[471]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[471]->out) 0 -.nodeset V(sram[471]->outb) vsp -Xsram[472] sram->in sram[472]->out sram[472]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[472]->out) 0 -.nodeset V(sram[472]->outb) vsp -Xsram[473] sram->in sram[473]->out sram[473]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[473]->out) 0 -.nodeset V(sram[473]->outb) vsp -Xsram[474] sram->in sram[474]->out sram[474]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[474]->out) 0 -.nodeset V(sram[474]->outb) vsp -Xsram[475] sram->in sram[475]->out sram[475]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[475]->out) 0 -.nodeset V(sram[475]->outb) vsp -Xsram[476] sram->in sram[476]->out sram[476]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[476]->out) 0 -.nodeset V(sram[476]->outb) vsp -Xsram[477] sram->in sram[477]->out sram[477]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[477]->out) 0 -.nodeset V(sram[477]->outb) vsp -Xsram[478] sram->in sram[478]->out sram[478]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[478]->out) 0 -.nodeset V(sram[478]->outb) vsp -Xsram[479] sram->in sram[479]->out sram[479]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[479]->out) 0 -.nodeset V(sram[479]->outb) vsp -Xsram[480] sram->in sram[480]->out sram[480]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[480]->out) 0 -.nodeset V(sram[480]->outb) vsp -Xsram[481] sram->in sram[481]->out sram[481]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[481]->out) 0 -.nodeset V(sram[481]->outb) vsp -Xsram[482] sram->in sram[482]->out sram[482]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[482]->out) 0 -.nodeset V(sram[482]->outb) vsp -Xsram[483] sram->in sram[483]->out sram[483]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[483]->out) 0 -.nodeset V(sram[483]->outb) vsp -Xsram[484] sram->in sram[484]->out sram[484]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[484]->out) 0 -.nodeset V(sram[484]->outb) vsp -Xsram[485] sram->in sram[485]->out sram[485]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[485]->out) 0 -.nodeset V(sram[485]->outb) vsp -Xsram[486] sram->in sram[486]->out sram[486]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[486]->out) 0 -.nodeset V(sram[486]->outb) vsp -Xsram[487] sram->in sram[487]->out sram[487]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[487]->out) 0 -.nodeset V(sram[487]->outb) vsp -Xsram[488] sram->in sram[488]->out sram[488]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[488]->out) 0 -.nodeset V(sram[488]->outb) vsp -Xsram[489] sram->in sram[489]->out sram[489]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[489]->out) 0 -.nodeset V(sram[489]->outb) vsp -Xsram[490] sram->in sram[490]->out sram[490]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[490]->out) 0 -.nodeset V(sram[490]->outb) vsp -Xsram[491] sram->in sram[491]->out sram[491]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[491]->out) 0 -.nodeset V(sram[491]->outb) vsp -Xsram[492] sram->in sram[492]->out sram[492]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[492]->out) 0 -.nodeset V(sram[492]->outb) vsp -Xsram[493] sram->in sram[493]->out sram[493]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[493]->out) 0 -.nodeset V(sram[493]->outb) vsp -Xsram[494] sram->in sram[494]->out sram[494]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[494]->out) 0 -.nodeset V(sram[494]->outb) vsp -Xsram[495] sram->in sram[495]->out sram[495]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[495]->out) 0 -.nodeset V(sram[495]->outb) vsp -Xsram[496] sram->in sram[496]->out sram[496]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[496]->out) 0 -.nodeset V(sram[496]->outb) vsp -Xsram[497] sram->in sram[497]->out sram[497]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[497]->out) 0 -.nodeset V(sram[497]->outb) vsp -Xsram[498] sram->in sram[498]->out sram[498]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[498]->out) 0 -.nodeset V(sram[498]->outb) vsp -Xsram[499] sram->in sram[499]->out sram[499]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[499]->out) 0 -.nodeset V(sram[499]->outb) vsp -Xsram[500] sram->in sram[500]->out sram[500]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[500]->out) 0 -.nodeset V(sram[500]->outb) vsp -Xsram[501] sram->in sram[501]->out sram[501]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[501]->out) 0 -.nodeset V(sram[501]->outb) vsp -Xsram[502] sram->in sram[502]->out sram[502]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[502]->out) 0 -.nodeset V(sram[502]->outb) vsp -Xsram[503] sram->in sram[503]->out sram[503]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[503]->out) 0 -.nodeset V(sram[503]->outb) vsp -Xsram[504] sram->in sram[504]->out sram[504]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[504]->out) 0 -.nodeset V(sram[504]->outb) vsp -Xsram[505] sram->in sram[505]->out sram[505]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[505]->out) 0 -.nodeset V(sram[505]->outb) vsp -Xsram[506] sram->in sram[506]->out sram[506]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[506]->out) 0 -.nodeset V(sram[506]->outb) vsp -Xsram[507] sram->in sram[507]->out sram[507]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[507]->out) 0 -.nodeset V(sram[507]->outb) vsp -Xsram[508] sram->in sram[508]->out sram[508]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[508]->out) 0 -.nodeset V(sram[508]->outb) vsp -Xsram[509] sram->in sram[509]->out sram[509]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[509]->out) 0 -.nodeset V(sram[509]->outb) vsp -Xsram[510] sram->in sram[510]->out sram[510]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[510]->out) 0 -.nodeset V(sram[510]->outb) vsp -Xsram[511] sram->in sram[511]->out sram[511]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[511]->out) 0 -.nodeset V(sram[511]->outb) vsp -Xsram[512] sram->in sram[512]->out sram[512]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[512]->out) 0 -.nodeset V(sram[512]->outb) vsp -Xsram[513] sram->in sram[513]->out sram[513]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[513]->out) 0 -.nodeset V(sram[513]->outb) vsp -Xsram[514] sram->in sram[514]->out sram[514]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[514]->out) 0 -.nodeset V(sram[514]->outb) vsp -Xsram[515] sram->in sram[515]->out sram[515]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[515]->out) 0 -.nodeset V(sram[515]->outb) vsp -Xsram[516] sram->in sram[516]->out sram[516]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[516]->out) 0 -.nodeset V(sram[516]->outb) vsp -Xsram[517] sram->in sram[517]->out sram[517]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[517]->out) 0 -.nodeset V(sram[517]->outb) vsp -Xsram[518] sram->in sram[518]->out sram[518]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[518]->out) 0 -.nodeset V(sram[518]->outb) vsp -Xlut6[7] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] sram[455]->out sram[456]->out sram[457]->out sram[458]->out sram[459]->out sram[460]->out sram[461]->out sram[462]->out sram[463]->out sram[464]->out sram[465]->out sram[466]->out sram[467]->out sram[468]->out sram[469]->out sram[470]->out sram[471]->out sram[472]->out sram[473]->out sram[474]->out sram[475]->out sram[476]->out sram[477]->out sram[478]->out sram[479]->out sram[480]->out sram[481]->out sram[482]->out sram[483]->out sram[484]->out sram[485]->out sram[486]->out sram[487]->out sram[488]->out sram[489]->out sram[490]->out sram[491]->out sram[492]->out sram[493]->out sram[494]->out sram[495]->out sram[496]->out sram[497]->out sram[498]->out sram[499]->out sram[500]->out sram[501]->out sram[502]->out sram[503]->out sram[504]->out sram[505]->out sram[506]->out sram[507]->out sram[508]->out sram[509]->out sram[510]->out sram[511]->out sram[512]->out sram[513]->out sram[514]->out sram[515]->out sram[516]->out sram[517]->out sram[518]->out gvdd_lut6[7] sgnd lut6 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[7]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[7] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[7] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[7]_mode[n1_lut6]_ble6[0]_mode[ble6] mode[ble6]->in[0] mode[ble6]->in[1] mode[ble6]->in[2] mode[ble6]->in[3] mode[ble6]->in[4] mode[ble6]->in[5] mode[ble6]->out[0] mode[ble6]->clk[0] svdd sgnd -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[7]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[7]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] -Xmux_1level_tapbuf_size2[7] ff[0]->Q[0] lut6[0]->out[0] mode[ble6]->out[0] sram[519]->outb sram[519]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[7], level=1, select_path_id=0. ***** -*****1***** -Xsram[519] sram->in sram[519]->out sram[519]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[519]->out) 0 -.nodeset V(sram[519]->outb) vsp -Xdirect_interc[112] mode[ble6]->in[0] lut6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[113] mode[ble6]->in[1] lut6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[114] mode[ble6]->in[2] lut6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[115] mode[ble6]->in[3] lut6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[116] mode[ble6]->in[4] lut6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[117] mode[ble6]->in[5] lut6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[118] lut6[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[119] mode[ble6]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[7]_mode[n1_lut6] mode[n1_lut6]->in[0] mode[n1_lut6]->in[1] mode[n1_lut6]->in[2] mode[n1_lut6]->in[3] mode[n1_lut6]->in[4] mode[n1_lut6]->in[5] mode[n1_lut6]->out[0] mode[n1_lut6]->clk[0] svdd sgnd -Xble6[0] ble6[0]->in[0] ble6[0]->in[1] ble6[0]->in[2] ble6[0]->in[3] ble6[0]->in[4] ble6[0]->in[5] ble6[0]->out[0] ble6[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[7]_mode[n1_lut6]_ble6[0]_mode[ble6] -Xdirect_interc[120] ble6[0]->out[0] mode[n1_lut6]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[121] mode[n1_lut6]->in[0] ble6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[122] mode[n1_lut6]->in[1] ble6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[123] mode[n1_lut6]->in[2] ble6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[124] mode[n1_lut6]->in[3] ble6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[125] mode[n1_lut6]->in[4] ble6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[126] mode[n1_lut6]->in[5] ble6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[127] mode[n1_lut6]->clk[0] ble6[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[8]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd -***** Truth Table for LUT[8], size=6. ***** -***** SRAM bits for LUT[8], size=6, num_sram=64. ***** -*****0000000000000000000000000000000000000000000000000000000000000000***** -Xsram[520] sram->in sram[520]->out sram[520]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[520]->out) 0 -.nodeset V(sram[520]->outb) vsp -Xsram[521] sram->in sram[521]->out sram[521]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[521]->out) 0 -.nodeset V(sram[521]->outb) vsp -Xsram[522] sram->in sram[522]->out sram[522]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[522]->out) 0 -.nodeset V(sram[522]->outb) vsp -Xsram[523] sram->in sram[523]->out sram[523]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[523]->out) 0 -.nodeset V(sram[523]->outb) vsp -Xsram[524] sram->in sram[524]->out sram[524]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[524]->out) 0 -.nodeset V(sram[524]->outb) vsp -Xsram[525] sram->in sram[525]->out sram[525]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[525]->out) 0 -.nodeset V(sram[525]->outb) vsp -Xsram[526] sram->in sram[526]->out sram[526]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[526]->out) 0 -.nodeset V(sram[526]->outb) vsp -Xsram[527] sram->in sram[527]->out sram[527]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[527]->out) 0 -.nodeset V(sram[527]->outb) vsp -Xsram[528] sram->in sram[528]->out sram[528]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[528]->out) 0 -.nodeset V(sram[528]->outb) vsp -Xsram[529] sram->in sram[529]->out sram[529]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[529]->out) 0 -.nodeset V(sram[529]->outb) vsp -Xsram[530] sram->in sram[530]->out sram[530]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[530]->out) 0 -.nodeset V(sram[530]->outb) vsp -Xsram[531] sram->in sram[531]->out sram[531]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[531]->out) 0 -.nodeset V(sram[531]->outb) vsp -Xsram[532] sram->in sram[532]->out sram[532]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[532]->out) 0 -.nodeset V(sram[532]->outb) vsp -Xsram[533] sram->in sram[533]->out sram[533]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[533]->out) 0 -.nodeset V(sram[533]->outb) vsp -Xsram[534] sram->in sram[534]->out sram[534]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[534]->out) 0 -.nodeset V(sram[534]->outb) vsp -Xsram[535] sram->in sram[535]->out sram[535]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[535]->out) 0 -.nodeset V(sram[535]->outb) vsp -Xsram[536] sram->in sram[536]->out sram[536]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[536]->out) 0 -.nodeset V(sram[536]->outb) vsp -Xsram[537] sram->in sram[537]->out sram[537]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[537]->out) 0 -.nodeset V(sram[537]->outb) vsp -Xsram[538] sram->in sram[538]->out sram[538]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[538]->out) 0 -.nodeset V(sram[538]->outb) vsp -Xsram[539] sram->in sram[539]->out sram[539]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[539]->out) 0 -.nodeset V(sram[539]->outb) vsp -Xsram[540] sram->in sram[540]->out sram[540]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[540]->out) 0 -.nodeset V(sram[540]->outb) vsp -Xsram[541] sram->in sram[541]->out sram[541]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[541]->out) 0 -.nodeset V(sram[541]->outb) vsp -Xsram[542] sram->in sram[542]->out sram[542]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[542]->out) 0 -.nodeset V(sram[542]->outb) vsp -Xsram[543] sram->in sram[543]->out sram[543]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[543]->out) 0 -.nodeset V(sram[543]->outb) vsp -Xsram[544] sram->in sram[544]->out sram[544]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[544]->out) 0 -.nodeset V(sram[544]->outb) vsp -Xsram[545] sram->in sram[545]->out sram[545]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[545]->out) 0 -.nodeset V(sram[545]->outb) vsp -Xsram[546] sram->in sram[546]->out sram[546]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[546]->out) 0 -.nodeset V(sram[546]->outb) vsp -Xsram[547] sram->in sram[547]->out sram[547]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[547]->out) 0 -.nodeset V(sram[547]->outb) vsp -Xsram[548] sram->in sram[548]->out sram[548]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[548]->out) 0 -.nodeset V(sram[548]->outb) vsp -Xsram[549] sram->in sram[549]->out sram[549]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[549]->out) 0 -.nodeset V(sram[549]->outb) vsp -Xsram[550] sram->in sram[550]->out sram[550]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[550]->out) 0 -.nodeset V(sram[550]->outb) vsp -Xsram[551] sram->in sram[551]->out sram[551]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[551]->out) 0 -.nodeset V(sram[551]->outb) vsp -Xsram[552] sram->in sram[552]->out sram[552]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[552]->out) 0 -.nodeset V(sram[552]->outb) vsp -Xsram[553] sram->in sram[553]->out sram[553]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[553]->out) 0 -.nodeset V(sram[553]->outb) vsp -Xsram[554] sram->in sram[554]->out sram[554]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[554]->out) 0 -.nodeset V(sram[554]->outb) vsp -Xsram[555] sram->in sram[555]->out sram[555]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[555]->out) 0 -.nodeset V(sram[555]->outb) vsp -Xsram[556] sram->in sram[556]->out sram[556]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[556]->out) 0 -.nodeset V(sram[556]->outb) vsp -Xsram[557] sram->in sram[557]->out sram[557]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[557]->out) 0 -.nodeset V(sram[557]->outb) vsp -Xsram[558] sram->in sram[558]->out sram[558]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[558]->out) 0 -.nodeset V(sram[558]->outb) vsp -Xsram[559] sram->in sram[559]->out sram[559]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[559]->out) 0 -.nodeset V(sram[559]->outb) vsp -Xsram[560] sram->in sram[560]->out sram[560]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[560]->out) 0 -.nodeset V(sram[560]->outb) vsp -Xsram[561] sram->in sram[561]->out sram[561]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[561]->out) 0 -.nodeset V(sram[561]->outb) vsp -Xsram[562] sram->in sram[562]->out sram[562]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[562]->out) 0 -.nodeset V(sram[562]->outb) vsp -Xsram[563] sram->in sram[563]->out sram[563]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[563]->out) 0 -.nodeset V(sram[563]->outb) vsp -Xsram[564] sram->in sram[564]->out sram[564]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[564]->out) 0 -.nodeset V(sram[564]->outb) vsp -Xsram[565] sram->in sram[565]->out sram[565]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[565]->out) 0 -.nodeset V(sram[565]->outb) vsp -Xsram[566] sram->in sram[566]->out sram[566]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[566]->out) 0 -.nodeset V(sram[566]->outb) vsp -Xsram[567] sram->in sram[567]->out sram[567]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[567]->out) 0 -.nodeset V(sram[567]->outb) vsp -Xsram[568] sram->in sram[568]->out sram[568]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[568]->out) 0 -.nodeset V(sram[568]->outb) vsp -Xsram[569] sram->in sram[569]->out sram[569]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[569]->out) 0 -.nodeset V(sram[569]->outb) vsp -Xsram[570] sram->in sram[570]->out sram[570]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[570]->out) 0 -.nodeset V(sram[570]->outb) vsp -Xsram[571] sram->in sram[571]->out sram[571]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[571]->out) 0 -.nodeset V(sram[571]->outb) vsp -Xsram[572] sram->in sram[572]->out sram[572]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[572]->out) 0 -.nodeset V(sram[572]->outb) vsp -Xsram[573] sram->in sram[573]->out sram[573]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[573]->out) 0 -.nodeset V(sram[573]->outb) vsp -Xsram[574] sram->in sram[574]->out sram[574]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[574]->out) 0 -.nodeset V(sram[574]->outb) vsp -Xsram[575] sram->in sram[575]->out sram[575]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[575]->out) 0 -.nodeset V(sram[575]->outb) vsp -Xsram[576] sram->in sram[576]->out sram[576]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[576]->out) 0 -.nodeset V(sram[576]->outb) vsp -Xsram[577] sram->in sram[577]->out sram[577]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[577]->out) 0 -.nodeset V(sram[577]->outb) vsp -Xsram[578] sram->in sram[578]->out sram[578]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[578]->out) 0 -.nodeset V(sram[578]->outb) vsp -Xsram[579] sram->in sram[579]->out sram[579]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[579]->out) 0 -.nodeset V(sram[579]->outb) vsp -Xsram[580] sram->in sram[580]->out sram[580]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[580]->out) 0 -.nodeset V(sram[580]->outb) vsp -Xsram[581] sram->in sram[581]->out sram[581]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[581]->out) 0 -.nodeset V(sram[581]->outb) vsp -Xsram[582] sram->in sram[582]->out sram[582]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[582]->out) 0 -.nodeset V(sram[582]->outb) vsp -Xsram[583] sram->in sram[583]->out sram[583]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[583]->out) 0 -.nodeset V(sram[583]->outb) vsp -Xlut6[8] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] sram[520]->out sram[521]->out sram[522]->out sram[523]->out sram[524]->out sram[525]->out sram[526]->out sram[527]->out sram[528]->out sram[529]->out sram[530]->out sram[531]->out sram[532]->out sram[533]->out sram[534]->out sram[535]->out sram[536]->out sram[537]->out sram[538]->out sram[539]->out sram[540]->out sram[541]->out sram[542]->out sram[543]->out sram[544]->out sram[545]->out sram[546]->out sram[547]->out sram[548]->out sram[549]->out sram[550]->out sram[551]->out sram[552]->out sram[553]->out sram[554]->out sram[555]->out sram[556]->out sram[557]->out sram[558]->out sram[559]->out sram[560]->out sram[561]->out sram[562]->out sram[563]->out sram[564]->out sram[565]->out sram[566]->out sram[567]->out sram[568]->out sram[569]->out sram[570]->out sram[571]->out sram[572]->out sram[573]->out sram[574]->out sram[575]->out sram[576]->out sram[577]->out sram[578]->out sram[579]->out sram[580]->out sram[581]->out sram[582]->out sram[583]->out gvdd_lut6[8] sgnd lut6 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[8]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[8] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[8] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[8]_mode[n1_lut6]_ble6[0]_mode[ble6] mode[ble6]->in[0] mode[ble6]->in[1] mode[ble6]->in[2] mode[ble6]->in[3] mode[ble6]->in[4] mode[ble6]->in[5] mode[ble6]->out[0] mode[ble6]->clk[0] svdd sgnd -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[8]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[8]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] -Xmux_1level_tapbuf_size2[8] ff[0]->Q[0] lut6[0]->out[0] mode[ble6]->out[0] sram[584]->outb sram[584]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[8], level=1, select_path_id=0. ***** -*****1***** -Xsram[584] sram->in sram[584]->out sram[584]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[584]->out) 0 -.nodeset V(sram[584]->outb) vsp -Xdirect_interc[128] mode[ble6]->in[0] lut6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[129] mode[ble6]->in[1] lut6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[130] mode[ble6]->in[2] lut6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[131] mode[ble6]->in[3] lut6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[132] mode[ble6]->in[4] lut6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[133] mode[ble6]->in[5] lut6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[134] lut6[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[135] mode[ble6]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[8]_mode[n1_lut6] mode[n1_lut6]->in[0] mode[n1_lut6]->in[1] mode[n1_lut6]->in[2] mode[n1_lut6]->in[3] mode[n1_lut6]->in[4] mode[n1_lut6]->in[5] mode[n1_lut6]->out[0] mode[n1_lut6]->clk[0] svdd sgnd -Xble6[0] ble6[0]->in[0] ble6[0]->in[1] ble6[0]->in[2] ble6[0]->in[3] ble6[0]->in[4] ble6[0]->in[5] ble6[0]->out[0] ble6[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[8]_mode[n1_lut6]_ble6[0]_mode[ble6] -Xdirect_interc[136] ble6[0]->out[0] mode[n1_lut6]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[137] mode[n1_lut6]->in[0] ble6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[138] mode[n1_lut6]->in[1] ble6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[139] mode[n1_lut6]->in[2] ble6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[140] mode[n1_lut6]->in[3] ble6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[141] mode[n1_lut6]->in[4] ble6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[142] mode[n1_lut6]->in[5] ble6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[143] mode[n1_lut6]->clk[0] ble6[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -***** Logical block mapped to this LUT: n7 ***** -.subckt grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd -***** Truth Table for LUT[9], size=6. ***** -* 0----- 1 * -***** SRAM bits for LUT[9], size=6, num_sram=64. ***** -*****0101010101010101010101010101010101010101010101010101010101010101***** -Xsram[585] sram->in sram[585]->out sram[585]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[585]->out) 0 -.nodeset V(sram[585]->outb) vsp -Xsram[586] sram->in sram[586]->out sram[586]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[586]->out) 0 -.nodeset V(sram[586]->outb) vsp -Xsram[587] sram->in sram[587]->out sram[587]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[587]->out) 0 -.nodeset V(sram[587]->outb) vsp -Xsram[588] sram->in sram[588]->out sram[588]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[588]->out) 0 -.nodeset V(sram[588]->outb) vsp -Xsram[589] sram->in sram[589]->out sram[589]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[589]->out) 0 -.nodeset V(sram[589]->outb) vsp -Xsram[590] sram->in sram[590]->out sram[590]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[590]->out) 0 -.nodeset V(sram[590]->outb) vsp -Xsram[591] sram->in sram[591]->out sram[591]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[591]->out) 0 -.nodeset V(sram[591]->outb) vsp -Xsram[592] sram->in sram[592]->out sram[592]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[592]->out) 0 -.nodeset V(sram[592]->outb) vsp -Xsram[593] sram->in sram[593]->out sram[593]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[593]->out) 0 -.nodeset V(sram[593]->outb) vsp -Xsram[594] sram->in sram[594]->out sram[594]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[594]->out) 0 -.nodeset V(sram[594]->outb) vsp -Xsram[595] sram->in sram[595]->out sram[595]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[595]->out) 0 -.nodeset V(sram[595]->outb) vsp -Xsram[596] sram->in sram[596]->out sram[596]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[596]->out) 0 -.nodeset V(sram[596]->outb) vsp -Xsram[597] sram->in sram[597]->out sram[597]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[597]->out) 0 -.nodeset V(sram[597]->outb) vsp -Xsram[598] sram->in sram[598]->out sram[598]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[598]->out) 0 -.nodeset V(sram[598]->outb) vsp -Xsram[599] sram->in sram[599]->out sram[599]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[599]->out) 0 -.nodeset V(sram[599]->outb) vsp -Xsram[600] sram->in sram[600]->out sram[600]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[600]->out) 0 -.nodeset V(sram[600]->outb) vsp -Xsram[601] sram->in sram[601]->out sram[601]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[601]->out) 0 -.nodeset V(sram[601]->outb) vsp -Xsram[602] sram->in sram[602]->out sram[602]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[602]->out) 0 -.nodeset V(sram[602]->outb) vsp -Xsram[603] sram->in sram[603]->out sram[603]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[603]->out) 0 -.nodeset V(sram[603]->outb) vsp -Xsram[604] sram->in sram[604]->out sram[604]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[604]->out) 0 -.nodeset V(sram[604]->outb) vsp -Xsram[605] sram->in sram[605]->out sram[605]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[605]->out) 0 -.nodeset V(sram[605]->outb) vsp -Xsram[606] sram->in sram[606]->out sram[606]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[606]->out) 0 -.nodeset V(sram[606]->outb) vsp -Xsram[607] sram->in sram[607]->out sram[607]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[607]->out) 0 -.nodeset V(sram[607]->outb) vsp -Xsram[608] sram->in sram[608]->out sram[608]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[608]->out) 0 -.nodeset V(sram[608]->outb) vsp -Xsram[609] sram->in sram[609]->out sram[609]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[609]->out) 0 -.nodeset V(sram[609]->outb) vsp -Xsram[610] sram->in sram[610]->out sram[610]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[610]->out) 0 -.nodeset V(sram[610]->outb) vsp -Xsram[611] sram->in sram[611]->out sram[611]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[611]->out) 0 -.nodeset V(sram[611]->outb) vsp -Xsram[612] sram->in sram[612]->out sram[612]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[612]->out) 0 -.nodeset V(sram[612]->outb) vsp -Xsram[613] sram->in sram[613]->out sram[613]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[613]->out) 0 -.nodeset V(sram[613]->outb) vsp -Xsram[614] sram->in sram[614]->out sram[614]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[614]->out) 0 -.nodeset V(sram[614]->outb) vsp -Xsram[615] sram->in sram[615]->out sram[615]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[615]->out) 0 -.nodeset V(sram[615]->outb) vsp -Xsram[616] sram->in sram[616]->out sram[616]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[616]->out) 0 -.nodeset V(sram[616]->outb) vsp -Xsram[617] sram->in sram[617]->out sram[617]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[617]->out) 0 -.nodeset V(sram[617]->outb) vsp -Xsram[618] sram->in sram[618]->out sram[618]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[618]->out) 0 -.nodeset V(sram[618]->outb) vsp -Xsram[619] sram->in sram[619]->out sram[619]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[619]->out) 0 -.nodeset V(sram[619]->outb) vsp -Xsram[620] sram->in sram[620]->out sram[620]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[620]->out) 0 -.nodeset V(sram[620]->outb) vsp -Xsram[621] sram->in sram[621]->out sram[621]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[621]->out) 0 -.nodeset V(sram[621]->outb) vsp -Xsram[622] sram->in sram[622]->out sram[622]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[622]->out) 0 -.nodeset V(sram[622]->outb) vsp -Xsram[623] sram->in sram[623]->out sram[623]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[623]->out) 0 -.nodeset V(sram[623]->outb) vsp -Xsram[624] sram->in sram[624]->out sram[624]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[624]->out) 0 -.nodeset V(sram[624]->outb) vsp -Xsram[625] sram->in sram[625]->out sram[625]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[625]->out) 0 -.nodeset V(sram[625]->outb) vsp -Xsram[626] sram->in sram[626]->out sram[626]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[626]->out) 0 -.nodeset V(sram[626]->outb) vsp -Xsram[627] sram->in sram[627]->out sram[627]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[627]->out) 0 -.nodeset V(sram[627]->outb) vsp -Xsram[628] sram->in sram[628]->out sram[628]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[628]->out) 0 -.nodeset V(sram[628]->outb) vsp -Xsram[629] sram->in sram[629]->out sram[629]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[629]->out) 0 -.nodeset V(sram[629]->outb) vsp -Xsram[630] sram->in sram[630]->out sram[630]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[630]->out) 0 -.nodeset V(sram[630]->outb) vsp -Xsram[631] sram->in sram[631]->out sram[631]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[631]->out) 0 -.nodeset V(sram[631]->outb) vsp -Xsram[632] sram->in sram[632]->out sram[632]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[632]->out) 0 -.nodeset V(sram[632]->outb) vsp -Xsram[633] sram->in sram[633]->out sram[633]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[633]->out) 0 -.nodeset V(sram[633]->outb) vsp -Xsram[634] sram->in sram[634]->out sram[634]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[634]->out) 0 -.nodeset V(sram[634]->outb) vsp -Xsram[635] sram->in sram[635]->out sram[635]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[635]->out) 0 -.nodeset V(sram[635]->outb) vsp -Xsram[636] sram->in sram[636]->out sram[636]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[636]->out) 0 -.nodeset V(sram[636]->outb) vsp -Xsram[637] sram->in sram[637]->out sram[637]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[637]->out) 0 -.nodeset V(sram[637]->outb) vsp -Xsram[638] sram->in sram[638]->out sram[638]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[638]->out) 0 -.nodeset V(sram[638]->outb) vsp -Xsram[639] sram->in sram[639]->out sram[639]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[639]->out) 0 -.nodeset V(sram[639]->outb) vsp -Xsram[640] sram->in sram[640]->out sram[640]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[640]->out) 0 -.nodeset V(sram[640]->outb) vsp -Xsram[641] sram->in sram[641]->out sram[641]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[641]->out) 0 -.nodeset V(sram[641]->outb) vsp -Xsram[642] sram->in sram[642]->out sram[642]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[642]->out) 0 -.nodeset V(sram[642]->outb) vsp -Xsram[643] sram->in sram[643]->out sram[643]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[643]->out) 0 -.nodeset V(sram[643]->outb) vsp -Xsram[644] sram->in sram[644]->out sram[644]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[644]->out) 0 -.nodeset V(sram[644]->outb) vsp -Xsram[645] sram->in sram[645]->out sram[645]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[645]->out) 0 -.nodeset V(sram[645]->outb) vsp -Xsram[646] sram->in sram[646]->out sram[646]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[646]->out) 0 -.nodeset V(sram[646]->outb) vsp -Xsram[647] sram->in sram[647]->out sram[647]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[647]->out) 0 -.nodeset V(sram[647]->outb) vsp -Xsram[648] sram->in sram[648]->out sram[648]->outb gvdd_sram_luts sgnd sram6T -.nodeset V(sram[648]->out) 0 -.nodeset V(sram[648]->outb) vsp -Xlut6[9] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] sram[585]->out sram[586]->outb sram[587]->out sram[588]->outb sram[589]->out sram[590]->outb sram[591]->out sram[592]->outb sram[593]->out sram[594]->outb sram[595]->out sram[596]->outb sram[597]->out sram[598]->outb sram[599]->out sram[600]->outb sram[601]->out sram[602]->outb sram[603]->out sram[604]->outb sram[605]->out sram[606]->outb sram[607]->out sram[608]->outb sram[609]->out sram[610]->outb sram[611]->out sram[612]->outb sram[613]->out sram[614]->outb sram[615]->out sram[616]->outb sram[617]->out sram[618]->outb sram[619]->out sram[620]->outb sram[621]->out sram[622]->outb sram[623]->out sram[624]->outb sram[625]->out sram[626]->outb sram[627]->out sram[628]->outb sram[629]->out sram[630]->outb sram[631]->out sram[632]->outb sram[633]->out sram[634]->outb sram[635]->out sram[636]->outb sram[637]->out sram[638]->outb sram[639]->out sram[640]->outb sram[641]->out sram[642]->outb sram[643]->out sram[644]->outb sram[645]->out sram[646]->outb sram[647]->out sram[648]->outb gvdd_lut6[9] sgnd lut6 -.eom -***** Logical block mapped to this FF: Q0 ***** -.subckt grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd -Xdff[9] -***** BEGIN Global ports of SPICE_MODEL(static_dff) ***** -+ Set[0] Reset[0] clk[0] -***** END Global ports of SPICE_MODEL(static_dff) ***** -+ ff[0]->D[0] ff[0]->Q[0] gvdd_dff[9] sgnd static_dff -.nodeset V(ff[0]->Q[0]) 0 -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6] mode[ble6]->in[0] mode[ble6]->in[1] mode[ble6]->in[2] mode[ble6]->in[3] mode[ble6]->in[4] mode[ble6]->in[5] mode[ble6]->out[0] mode[ble6]->clk[0] svdd sgnd -Xlut6[0] lut6[0]->in[0] lut6[0]->in[1] lut6[0]->in[2] lut6[0]->in[3] lut6[0]->in[4] lut6[0]->in[5] lut6[0]->out[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_lut6[0] -Xff[0] ff[0]->D[0] ff[0]->Q[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6]_ff[0] -Xmux_1level_tapbuf_size2[9] ff[0]->Q[0] lut6[0]->out[0] mode[ble6]->out[0] sram[649]->outb sram[649]->out gvdd_local_interc sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[9], level=1, select_path_id=0. ***** -*****1***** -Xsram[649] sram->in sram[649]->out sram[649]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[649]->out) 0 -.nodeset V(sram[649]->outb) vsp -Xdirect_interc[144] mode[ble6]->in[0] lut6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[145] mode[ble6]->in[1] lut6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[146] mode[ble6]->in[2] lut6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[147] mode[ble6]->in[3] lut6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[148] mode[ble6]->in[4] lut6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[149] mode[ble6]->in[5] lut6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[150] lut6[0]->out[0] ff[0]->D[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[151] mode[ble6]->clk[0] ff[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6] mode[n1_lut6]->in[0] mode[n1_lut6]->in[1] mode[n1_lut6]->in[2] mode[n1_lut6]->in[3] mode[n1_lut6]->in[4] mode[n1_lut6]->in[5] mode[n1_lut6]->out[0] mode[n1_lut6]->clk[0] svdd sgnd -Xble6[0] ble6[0]->in[0] ble6[0]->in[1] ble6[0]->in[2] ble6[0]->in[3] ble6[0]->in[4] ble6[0]->in[5] ble6[0]->out[0] ble6[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6]_ble6[0]_mode[ble6] -Xdirect_interc[152] ble6[0]->out[0] mode[n1_lut6]->out[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[153] mode[n1_lut6]->in[0] ble6[0]->in[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[154] mode[n1_lut6]->in[1] ble6[0]->in[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[155] mode[n1_lut6]->in[2] ble6[0]->in[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[156] mode[n1_lut6]->in[3] ble6[0]->in[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[157] mode[n1_lut6]->in[4] ble6[0]->in[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[158] mode[n1_lut6]->in[5] ble6[0]->in[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[159] mode[n1_lut6]->clk[0] ble6[0]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -.subckt grid[1][1]_clb[0]_mode[clb] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] mode[clb]->O[0] mode[clb]->O[1] mode[clb]->O[2] mode[clb]->O[3] mode[clb]->O[4] mode[clb]->O[5] mode[clb]->O[6] mode[clb]->O[7] mode[clb]->O[8] mode[clb]->O[9] mode[clb]->clk[0] svdd sgnd -Xfle[0] fle[0]->in[0] fle[0]->in[1] fle[0]->in[2] fle[0]->in[3] fle[0]->in[4] fle[0]->in[5] fle[0]->out[0] fle[0]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[0]_mode[n1_lut6] -Xfle[1] fle[1]->in[0] fle[1]->in[1] fle[1]->in[2] fle[1]->in[3] fle[1]->in[4] fle[1]->in[5] fle[1]->out[0] fle[1]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[1]_mode[n1_lut6] -Xfle[2] fle[2]->in[0] fle[2]->in[1] fle[2]->in[2] fle[2]->in[3] fle[2]->in[4] fle[2]->in[5] fle[2]->out[0] fle[2]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[2]_mode[n1_lut6] -Xfle[3] fle[3]->in[0] fle[3]->in[1] fle[3]->in[2] fle[3]->in[3] fle[3]->in[4] fle[3]->in[5] fle[3]->out[0] fle[3]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[3]_mode[n1_lut6] -Xfle[4] fle[4]->in[0] fle[4]->in[1] fle[4]->in[2] fle[4]->in[3] fle[4]->in[4] fle[4]->in[5] fle[4]->out[0] fle[4]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[4]_mode[n1_lut6] -Xfle[5] fle[5]->in[0] fle[5]->in[1] fle[5]->in[2] fle[5]->in[3] fle[5]->in[4] fle[5]->in[5] fle[5]->out[0] fle[5]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[5]_mode[n1_lut6] -Xfle[6] fle[6]->in[0] fle[6]->in[1] fle[6]->in[2] fle[6]->in[3] fle[6]->in[4] fle[6]->in[5] fle[6]->out[0] fle[6]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[6]_mode[n1_lut6] -Xfle[7] fle[7]->in[0] fle[7]->in[1] fle[7]->in[2] fle[7]->in[3] fle[7]->in[4] fle[7]->in[5] fle[7]->out[0] fle[7]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[7]_mode[n1_lut6] -Xfle[8] fle[8]->in[0] fle[8]->in[1] fle[8]->in[2] fle[8]->in[3] fle[8]->in[4] fle[8]->in[5] fle[8]->out[0] fle[8]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[8]_mode[n1_lut6] -Xfle[9] fle[9]->in[0] fle[9]->in[1] fle[9]->in[2] fle[9]->in[3] fle[9]->in[4] fle[9]->in[5] fle[9]->out[0] fle[9]->clk[0] svdd sgnd grid[1][1]_clb[0]_mode[clb]_fle[9]_mode[n1_lut6] -Xdirect_interc[160] fle[0]->out[0] mode[clb]->O[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[161] fle[1]->out[0] mode[clb]->O[1] gvdd_local_interc sgnd direct_interc -Xdirect_interc[162] fle[2]->out[0] mode[clb]->O[2] gvdd_local_interc sgnd direct_interc -Xdirect_interc[163] fle[3]->out[0] mode[clb]->O[3] gvdd_local_interc sgnd direct_interc -Xdirect_interc[164] fle[4]->out[0] mode[clb]->O[4] gvdd_local_interc sgnd direct_interc -Xdirect_interc[165] fle[5]->out[0] mode[clb]->O[5] gvdd_local_interc sgnd direct_interc -Xdirect_interc[166] fle[6]->out[0] mode[clb]->O[6] gvdd_local_interc sgnd direct_interc -Xdirect_interc[167] fle[7]->out[0] mode[clb]->O[7] gvdd_local_interc sgnd direct_interc -Xdirect_interc[168] fle[8]->out[0] mode[clb]->O[8] gvdd_local_interc sgnd direct_interc -Xdirect_interc[169] fle[9]->out[0] mode[clb]->O[9] gvdd_local_interc sgnd direct_interc -Xmux_2level_size50[0] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[0]->in[0] sram[650]->outb sram[650]->out sram[651]->out sram[651]->outb sram[652]->out sram[652]->outb sram[653]->out sram[653]->outb sram[654]->out sram[654]->outb sram[655]->out sram[655]->outb sram[656]->out sram[656]->outb sram[657]->out sram[657]->outb sram[658]->outb sram[658]->out sram[659]->out sram[659]->outb sram[660]->out sram[660]->outb sram[661]->out sram[661]->outb sram[662]->out sram[662]->outb sram[663]->out sram[663]->outb sram[664]->out sram[664]->outb sram[665]->out sram[665]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[0], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[650] sram->in sram[650]->out sram[650]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[650]->out) 0 -.nodeset V(sram[650]->outb) vsp -Xsram[651] sram->in sram[651]->out sram[651]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[651]->out) 0 -.nodeset V(sram[651]->outb) vsp -Xsram[652] sram->in sram[652]->out sram[652]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[652]->out) 0 -.nodeset V(sram[652]->outb) vsp -Xsram[653] sram->in sram[653]->out sram[653]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[653]->out) 0 -.nodeset V(sram[653]->outb) vsp -Xsram[654] sram->in sram[654]->out sram[654]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[654]->out) 0 -.nodeset V(sram[654]->outb) vsp -Xsram[655] sram->in sram[655]->out sram[655]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[655]->out) 0 -.nodeset V(sram[655]->outb) vsp -Xsram[656] sram->in sram[656]->out sram[656]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[656]->out) 0 -.nodeset V(sram[656]->outb) vsp -Xsram[657] sram->in sram[657]->out sram[657]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[657]->out) 0 -.nodeset V(sram[657]->outb) vsp -Xsram[658] sram->in sram[658]->out sram[658]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[658]->out) 0 -.nodeset V(sram[658]->outb) vsp -Xsram[659] sram->in sram[659]->out sram[659]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[659]->out) 0 -.nodeset V(sram[659]->outb) vsp -Xsram[660] sram->in sram[660]->out sram[660]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[660]->out) 0 -.nodeset V(sram[660]->outb) vsp -Xsram[661] sram->in sram[661]->out sram[661]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[661]->out) 0 -.nodeset V(sram[661]->outb) vsp -Xsram[662] sram->in sram[662]->out sram[662]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[662]->out) 0 -.nodeset V(sram[662]->outb) vsp -Xsram[663] sram->in sram[663]->out sram[663]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[663]->out) 0 -.nodeset V(sram[663]->outb) vsp -Xsram[664] sram->in sram[664]->out sram[664]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[664]->out) 0 -.nodeset V(sram[664]->outb) vsp -Xsram[665] sram->in sram[665]->out sram[665]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[665]->out) 0 -.nodeset V(sram[665]->outb) vsp -Xmux_2level_size50[1] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[0]->in[1] sram[666]->outb sram[666]->out sram[667]->out sram[667]->outb sram[668]->out sram[668]->outb sram[669]->out sram[669]->outb sram[670]->out sram[670]->outb sram[671]->out sram[671]->outb sram[672]->out sram[672]->outb sram[673]->out sram[673]->outb sram[674]->outb sram[674]->out sram[675]->out sram[675]->outb sram[676]->out sram[676]->outb sram[677]->out sram[677]->outb sram[678]->out sram[678]->outb sram[679]->out sram[679]->outb sram[680]->out sram[680]->outb sram[681]->out sram[681]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[1], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[666] sram->in sram[666]->out sram[666]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[666]->out) 0 -.nodeset V(sram[666]->outb) vsp -Xsram[667] sram->in sram[667]->out sram[667]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[667]->out) 0 -.nodeset V(sram[667]->outb) vsp -Xsram[668] sram->in sram[668]->out sram[668]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[668]->out) 0 -.nodeset V(sram[668]->outb) vsp -Xsram[669] sram->in sram[669]->out sram[669]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[669]->out) 0 -.nodeset V(sram[669]->outb) vsp -Xsram[670] sram->in sram[670]->out sram[670]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[670]->out) 0 -.nodeset V(sram[670]->outb) vsp -Xsram[671] sram->in sram[671]->out sram[671]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[671]->out) 0 -.nodeset V(sram[671]->outb) vsp -Xsram[672] sram->in sram[672]->out sram[672]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[672]->out) 0 -.nodeset V(sram[672]->outb) vsp -Xsram[673] sram->in sram[673]->out sram[673]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[673]->out) 0 -.nodeset V(sram[673]->outb) vsp -Xsram[674] sram->in sram[674]->out sram[674]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[674]->out) 0 -.nodeset V(sram[674]->outb) vsp -Xsram[675] sram->in sram[675]->out sram[675]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[675]->out) 0 -.nodeset V(sram[675]->outb) vsp -Xsram[676] sram->in sram[676]->out sram[676]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[676]->out) 0 -.nodeset V(sram[676]->outb) vsp -Xsram[677] sram->in sram[677]->out sram[677]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[677]->out) 0 -.nodeset V(sram[677]->outb) vsp -Xsram[678] sram->in sram[678]->out sram[678]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[678]->out) 0 -.nodeset V(sram[678]->outb) vsp -Xsram[679] sram->in sram[679]->out sram[679]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[679]->out) 0 -.nodeset V(sram[679]->outb) vsp -Xsram[680] sram->in sram[680]->out sram[680]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[680]->out) 0 -.nodeset V(sram[680]->outb) vsp -Xsram[681] sram->in sram[681]->out sram[681]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[681]->out) 0 -.nodeset V(sram[681]->outb) vsp -Xmux_2level_size50[2] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[0]->in[2] sram[682]->outb sram[682]->out sram[683]->out sram[683]->outb sram[684]->out sram[684]->outb sram[685]->out sram[685]->outb sram[686]->out sram[686]->outb sram[687]->out sram[687]->outb sram[688]->out sram[688]->outb sram[689]->out sram[689]->outb sram[690]->outb sram[690]->out sram[691]->out sram[691]->outb sram[692]->out sram[692]->outb sram[693]->out sram[693]->outb sram[694]->out sram[694]->outb sram[695]->out sram[695]->outb sram[696]->out sram[696]->outb sram[697]->out sram[697]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[2], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[682] sram->in sram[682]->out sram[682]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[682]->out) 0 -.nodeset V(sram[682]->outb) vsp -Xsram[683] sram->in sram[683]->out sram[683]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[683]->out) 0 -.nodeset V(sram[683]->outb) vsp -Xsram[684] sram->in sram[684]->out sram[684]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[684]->out) 0 -.nodeset V(sram[684]->outb) vsp -Xsram[685] sram->in sram[685]->out sram[685]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[685]->out) 0 -.nodeset V(sram[685]->outb) vsp -Xsram[686] sram->in sram[686]->out sram[686]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[686]->out) 0 -.nodeset V(sram[686]->outb) vsp -Xsram[687] sram->in sram[687]->out sram[687]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[687]->out) 0 -.nodeset V(sram[687]->outb) vsp -Xsram[688] sram->in sram[688]->out sram[688]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[688]->out) 0 -.nodeset V(sram[688]->outb) vsp -Xsram[689] sram->in sram[689]->out sram[689]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[689]->out) 0 -.nodeset V(sram[689]->outb) vsp -Xsram[690] sram->in sram[690]->out sram[690]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[690]->out) 0 -.nodeset V(sram[690]->outb) vsp -Xsram[691] sram->in sram[691]->out sram[691]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[691]->out) 0 -.nodeset V(sram[691]->outb) vsp -Xsram[692] sram->in sram[692]->out sram[692]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[692]->out) 0 -.nodeset V(sram[692]->outb) vsp -Xsram[693] sram->in sram[693]->out sram[693]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[693]->out) 0 -.nodeset V(sram[693]->outb) vsp -Xsram[694] sram->in sram[694]->out sram[694]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[694]->out) 0 -.nodeset V(sram[694]->outb) vsp -Xsram[695] sram->in sram[695]->out sram[695]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[695]->out) 0 -.nodeset V(sram[695]->outb) vsp -Xsram[696] sram->in sram[696]->out sram[696]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[696]->out) 0 -.nodeset V(sram[696]->outb) vsp -Xsram[697] sram->in sram[697]->out sram[697]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[697]->out) 0 -.nodeset V(sram[697]->outb) vsp -Xmux_2level_size50[3] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[0]->in[3] sram[698]->outb sram[698]->out sram[699]->out sram[699]->outb sram[700]->out sram[700]->outb sram[701]->out sram[701]->outb sram[702]->out sram[702]->outb sram[703]->out sram[703]->outb sram[704]->out sram[704]->outb sram[705]->out sram[705]->outb sram[706]->outb sram[706]->out sram[707]->out sram[707]->outb sram[708]->out sram[708]->outb sram[709]->out sram[709]->outb sram[710]->out sram[710]->outb sram[711]->out sram[711]->outb sram[712]->out sram[712]->outb sram[713]->out sram[713]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[3], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[698] sram->in sram[698]->out sram[698]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[698]->out) 0 -.nodeset V(sram[698]->outb) vsp -Xsram[699] sram->in sram[699]->out sram[699]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[699]->out) 0 -.nodeset V(sram[699]->outb) vsp -Xsram[700] sram->in sram[700]->out sram[700]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[700]->out) 0 -.nodeset V(sram[700]->outb) vsp -Xsram[701] sram->in sram[701]->out sram[701]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[701]->out) 0 -.nodeset V(sram[701]->outb) vsp -Xsram[702] sram->in sram[702]->out sram[702]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[702]->out) 0 -.nodeset V(sram[702]->outb) vsp -Xsram[703] sram->in sram[703]->out sram[703]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[703]->out) 0 -.nodeset V(sram[703]->outb) vsp -Xsram[704] sram->in sram[704]->out sram[704]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[704]->out) 0 -.nodeset V(sram[704]->outb) vsp -Xsram[705] sram->in sram[705]->out sram[705]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[705]->out) 0 -.nodeset V(sram[705]->outb) vsp -Xsram[706] sram->in sram[706]->out sram[706]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[706]->out) 0 -.nodeset V(sram[706]->outb) vsp -Xsram[707] sram->in sram[707]->out sram[707]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[707]->out) 0 -.nodeset V(sram[707]->outb) vsp -Xsram[708] sram->in sram[708]->out sram[708]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[708]->out) 0 -.nodeset V(sram[708]->outb) vsp -Xsram[709] sram->in sram[709]->out sram[709]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[709]->out) 0 -.nodeset V(sram[709]->outb) vsp -Xsram[710] sram->in sram[710]->out sram[710]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[710]->out) 0 -.nodeset V(sram[710]->outb) vsp -Xsram[711] sram->in sram[711]->out sram[711]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[711]->out) 0 -.nodeset V(sram[711]->outb) vsp -Xsram[712] sram->in sram[712]->out sram[712]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[712]->out) 0 -.nodeset V(sram[712]->outb) vsp -Xsram[713] sram->in sram[713]->out sram[713]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[713]->out) 0 -.nodeset V(sram[713]->outb) vsp -Xmux_2level_size50[4] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[0]->in[4] sram[714]->outb sram[714]->out sram[715]->out sram[715]->outb sram[716]->out sram[716]->outb sram[717]->out sram[717]->outb sram[718]->out sram[718]->outb sram[719]->out sram[719]->outb sram[720]->out sram[720]->outb sram[721]->out sram[721]->outb sram[722]->outb sram[722]->out sram[723]->out sram[723]->outb sram[724]->out sram[724]->outb sram[725]->out sram[725]->outb sram[726]->out sram[726]->outb sram[727]->out sram[727]->outb sram[728]->out sram[728]->outb sram[729]->out sram[729]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[4], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[714] sram->in sram[714]->out sram[714]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[714]->out) 0 -.nodeset V(sram[714]->outb) vsp -Xsram[715] sram->in sram[715]->out sram[715]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[715]->out) 0 -.nodeset V(sram[715]->outb) vsp -Xsram[716] sram->in sram[716]->out sram[716]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[716]->out) 0 -.nodeset V(sram[716]->outb) vsp -Xsram[717] sram->in sram[717]->out sram[717]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[717]->out) 0 -.nodeset V(sram[717]->outb) vsp -Xsram[718] sram->in sram[718]->out sram[718]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[718]->out) 0 -.nodeset V(sram[718]->outb) vsp -Xsram[719] sram->in sram[719]->out sram[719]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[719]->out) 0 -.nodeset V(sram[719]->outb) vsp -Xsram[720] sram->in sram[720]->out sram[720]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[720]->out) 0 -.nodeset V(sram[720]->outb) vsp -Xsram[721] sram->in sram[721]->out sram[721]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[721]->out) 0 -.nodeset V(sram[721]->outb) vsp -Xsram[722] sram->in sram[722]->out sram[722]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[722]->out) 0 -.nodeset V(sram[722]->outb) vsp -Xsram[723] sram->in sram[723]->out sram[723]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[723]->out) 0 -.nodeset V(sram[723]->outb) vsp -Xsram[724] sram->in sram[724]->out sram[724]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[724]->out) 0 -.nodeset V(sram[724]->outb) vsp -Xsram[725] sram->in sram[725]->out sram[725]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[725]->out) 0 -.nodeset V(sram[725]->outb) vsp -Xsram[726] sram->in sram[726]->out sram[726]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[726]->out) 0 -.nodeset V(sram[726]->outb) vsp -Xsram[727] sram->in sram[727]->out sram[727]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[727]->out) 0 -.nodeset V(sram[727]->outb) vsp -Xsram[728] sram->in sram[728]->out sram[728]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[728]->out) 0 -.nodeset V(sram[728]->outb) vsp -Xsram[729] sram->in sram[729]->out sram[729]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[729]->out) 0 -.nodeset V(sram[729]->outb) vsp -Xmux_2level_size50[5] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[0]->in[5] sram[730]->outb sram[730]->out sram[731]->out sram[731]->outb sram[732]->out sram[732]->outb sram[733]->out sram[733]->outb sram[734]->out sram[734]->outb sram[735]->out sram[735]->outb sram[736]->out sram[736]->outb sram[737]->out sram[737]->outb sram[738]->outb sram[738]->out sram[739]->out sram[739]->outb sram[740]->out sram[740]->outb sram[741]->out sram[741]->outb sram[742]->out sram[742]->outb sram[743]->out sram[743]->outb sram[744]->out sram[744]->outb sram[745]->out sram[745]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[5], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[730] sram->in sram[730]->out sram[730]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[730]->out) 0 -.nodeset V(sram[730]->outb) vsp -Xsram[731] sram->in sram[731]->out sram[731]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[731]->out) 0 -.nodeset V(sram[731]->outb) vsp -Xsram[732] sram->in sram[732]->out sram[732]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[732]->out) 0 -.nodeset V(sram[732]->outb) vsp -Xsram[733] sram->in sram[733]->out sram[733]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[733]->out) 0 -.nodeset V(sram[733]->outb) vsp -Xsram[734] sram->in sram[734]->out sram[734]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[734]->out) 0 -.nodeset V(sram[734]->outb) vsp -Xsram[735] sram->in sram[735]->out sram[735]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[735]->out) 0 -.nodeset V(sram[735]->outb) vsp -Xsram[736] sram->in sram[736]->out sram[736]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[736]->out) 0 -.nodeset V(sram[736]->outb) vsp -Xsram[737] sram->in sram[737]->out sram[737]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[737]->out) 0 -.nodeset V(sram[737]->outb) vsp -Xsram[738] sram->in sram[738]->out sram[738]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[738]->out) 0 -.nodeset V(sram[738]->outb) vsp -Xsram[739] sram->in sram[739]->out sram[739]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[739]->out) 0 -.nodeset V(sram[739]->outb) vsp -Xsram[740] sram->in sram[740]->out sram[740]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[740]->out) 0 -.nodeset V(sram[740]->outb) vsp -Xsram[741] sram->in sram[741]->out sram[741]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[741]->out) 0 -.nodeset V(sram[741]->outb) vsp -Xsram[742] sram->in sram[742]->out sram[742]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[742]->out) 0 -.nodeset V(sram[742]->outb) vsp -Xsram[743] sram->in sram[743]->out sram[743]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[743]->out) 0 -.nodeset V(sram[743]->outb) vsp -Xsram[744] sram->in sram[744]->out sram[744]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[744]->out) 0 -.nodeset V(sram[744]->outb) vsp -Xsram[745] sram->in sram[745]->out sram[745]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[745]->out) 0 -.nodeset V(sram[745]->outb) vsp -Xdirect_interc[170] mode[clb]->clk[0] fle[0]->clk[0] gvdd_local_interc sgnd direct_interc -Xmux_2level_size50[6] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[1]->in[0] sram[746]->outb sram[746]->out sram[747]->out sram[747]->outb sram[748]->out sram[748]->outb sram[749]->out sram[749]->outb sram[750]->out sram[750]->outb sram[751]->out sram[751]->outb sram[752]->out sram[752]->outb sram[753]->out sram[753]->outb sram[754]->outb sram[754]->out sram[755]->out sram[755]->outb sram[756]->out sram[756]->outb sram[757]->out sram[757]->outb sram[758]->out sram[758]->outb sram[759]->out sram[759]->outb sram[760]->out sram[760]->outb sram[761]->out sram[761]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[6], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[746] sram->in sram[746]->out sram[746]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[746]->out) 0 -.nodeset V(sram[746]->outb) vsp -Xsram[747] sram->in sram[747]->out sram[747]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[747]->out) 0 -.nodeset V(sram[747]->outb) vsp -Xsram[748] sram->in sram[748]->out sram[748]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[748]->out) 0 -.nodeset V(sram[748]->outb) vsp -Xsram[749] sram->in sram[749]->out sram[749]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[749]->out) 0 -.nodeset V(sram[749]->outb) vsp -Xsram[750] sram->in sram[750]->out sram[750]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[750]->out) 0 -.nodeset V(sram[750]->outb) vsp -Xsram[751] sram->in sram[751]->out sram[751]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[751]->out) 0 -.nodeset V(sram[751]->outb) vsp -Xsram[752] sram->in sram[752]->out sram[752]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[752]->out) 0 -.nodeset V(sram[752]->outb) vsp -Xsram[753] sram->in sram[753]->out sram[753]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[753]->out) 0 -.nodeset V(sram[753]->outb) vsp -Xsram[754] sram->in sram[754]->out sram[754]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[754]->out) 0 -.nodeset V(sram[754]->outb) vsp -Xsram[755] sram->in sram[755]->out sram[755]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[755]->out) 0 -.nodeset V(sram[755]->outb) vsp -Xsram[756] sram->in sram[756]->out sram[756]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[756]->out) 0 -.nodeset V(sram[756]->outb) vsp -Xsram[757] sram->in sram[757]->out sram[757]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[757]->out) 0 -.nodeset V(sram[757]->outb) vsp -Xsram[758] sram->in sram[758]->out sram[758]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[758]->out) 0 -.nodeset V(sram[758]->outb) vsp -Xsram[759] sram->in sram[759]->out sram[759]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[759]->out) 0 -.nodeset V(sram[759]->outb) vsp -Xsram[760] sram->in sram[760]->out sram[760]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[760]->out) 0 -.nodeset V(sram[760]->outb) vsp -Xsram[761] sram->in sram[761]->out sram[761]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[761]->out) 0 -.nodeset V(sram[761]->outb) vsp -Xmux_2level_size50[7] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[1]->in[1] sram[762]->outb sram[762]->out sram[763]->out sram[763]->outb sram[764]->out sram[764]->outb sram[765]->out sram[765]->outb sram[766]->out sram[766]->outb sram[767]->out sram[767]->outb sram[768]->out sram[768]->outb sram[769]->out sram[769]->outb sram[770]->outb sram[770]->out sram[771]->out sram[771]->outb sram[772]->out sram[772]->outb sram[773]->out sram[773]->outb sram[774]->out sram[774]->outb sram[775]->out sram[775]->outb sram[776]->out sram[776]->outb sram[777]->out sram[777]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[7], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[762] sram->in sram[762]->out sram[762]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[762]->out) 0 -.nodeset V(sram[762]->outb) vsp -Xsram[763] sram->in sram[763]->out sram[763]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[763]->out) 0 -.nodeset V(sram[763]->outb) vsp -Xsram[764] sram->in sram[764]->out sram[764]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[764]->out) 0 -.nodeset V(sram[764]->outb) vsp -Xsram[765] sram->in sram[765]->out sram[765]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[765]->out) 0 -.nodeset V(sram[765]->outb) vsp -Xsram[766] sram->in sram[766]->out sram[766]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[766]->out) 0 -.nodeset V(sram[766]->outb) vsp -Xsram[767] sram->in sram[767]->out sram[767]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[767]->out) 0 -.nodeset V(sram[767]->outb) vsp -Xsram[768] sram->in sram[768]->out sram[768]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[768]->out) 0 -.nodeset V(sram[768]->outb) vsp -Xsram[769] sram->in sram[769]->out sram[769]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[769]->out) 0 -.nodeset V(sram[769]->outb) vsp -Xsram[770] sram->in sram[770]->out sram[770]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[770]->out) 0 -.nodeset V(sram[770]->outb) vsp -Xsram[771] sram->in sram[771]->out sram[771]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[771]->out) 0 -.nodeset V(sram[771]->outb) vsp -Xsram[772] sram->in sram[772]->out sram[772]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[772]->out) 0 -.nodeset V(sram[772]->outb) vsp -Xsram[773] sram->in sram[773]->out sram[773]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[773]->out) 0 -.nodeset V(sram[773]->outb) vsp -Xsram[774] sram->in sram[774]->out sram[774]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[774]->out) 0 -.nodeset V(sram[774]->outb) vsp -Xsram[775] sram->in sram[775]->out sram[775]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[775]->out) 0 -.nodeset V(sram[775]->outb) vsp -Xsram[776] sram->in sram[776]->out sram[776]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[776]->out) 0 -.nodeset V(sram[776]->outb) vsp -Xsram[777] sram->in sram[777]->out sram[777]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[777]->out) 0 -.nodeset V(sram[777]->outb) vsp -Xmux_2level_size50[8] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[1]->in[2] sram[778]->outb sram[778]->out sram[779]->out sram[779]->outb sram[780]->out sram[780]->outb sram[781]->out sram[781]->outb sram[782]->out sram[782]->outb sram[783]->out sram[783]->outb sram[784]->out sram[784]->outb sram[785]->out sram[785]->outb sram[786]->outb sram[786]->out sram[787]->out sram[787]->outb sram[788]->out sram[788]->outb sram[789]->out sram[789]->outb sram[790]->out sram[790]->outb sram[791]->out sram[791]->outb sram[792]->out sram[792]->outb sram[793]->out sram[793]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[8], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[778] sram->in sram[778]->out sram[778]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[778]->out) 0 -.nodeset V(sram[778]->outb) vsp -Xsram[779] sram->in sram[779]->out sram[779]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[779]->out) 0 -.nodeset V(sram[779]->outb) vsp -Xsram[780] sram->in sram[780]->out sram[780]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[780]->out) 0 -.nodeset V(sram[780]->outb) vsp -Xsram[781] sram->in sram[781]->out sram[781]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[781]->out) 0 -.nodeset V(sram[781]->outb) vsp -Xsram[782] sram->in sram[782]->out sram[782]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[782]->out) 0 -.nodeset V(sram[782]->outb) vsp -Xsram[783] sram->in sram[783]->out sram[783]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[783]->out) 0 -.nodeset V(sram[783]->outb) vsp -Xsram[784] sram->in sram[784]->out sram[784]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[784]->out) 0 -.nodeset V(sram[784]->outb) vsp -Xsram[785] sram->in sram[785]->out sram[785]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[785]->out) 0 -.nodeset V(sram[785]->outb) vsp -Xsram[786] sram->in sram[786]->out sram[786]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[786]->out) 0 -.nodeset V(sram[786]->outb) vsp -Xsram[787] sram->in sram[787]->out sram[787]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[787]->out) 0 -.nodeset V(sram[787]->outb) vsp -Xsram[788] sram->in sram[788]->out sram[788]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[788]->out) 0 -.nodeset V(sram[788]->outb) vsp -Xsram[789] sram->in sram[789]->out sram[789]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[789]->out) 0 -.nodeset V(sram[789]->outb) vsp -Xsram[790] sram->in sram[790]->out sram[790]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[790]->out) 0 -.nodeset V(sram[790]->outb) vsp -Xsram[791] sram->in sram[791]->out sram[791]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[791]->out) 0 -.nodeset V(sram[791]->outb) vsp -Xsram[792] sram->in sram[792]->out sram[792]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[792]->out) 0 -.nodeset V(sram[792]->outb) vsp -Xsram[793] sram->in sram[793]->out sram[793]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[793]->out) 0 -.nodeset V(sram[793]->outb) vsp -Xmux_2level_size50[9] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[1]->in[3] sram[794]->outb sram[794]->out sram[795]->out sram[795]->outb sram[796]->out sram[796]->outb sram[797]->out sram[797]->outb sram[798]->out sram[798]->outb sram[799]->out sram[799]->outb sram[800]->out sram[800]->outb sram[801]->out sram[801]->outb sram[802]->outb sram[802]->out sram[803]->out sram[803]->outb sram[804]->out sram[804]->outb sram[805]->out sram[805]->outb sram[806]->out sram[806]->outb sram[807]->out sram[807]->outb sram[808]->out sram[808]->outb sram[809]->out sram[809]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[9], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[794] sram->in sram[794]->out sram[794]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[794]->out) 0 -.nodeset V(sram[794]->outb) vsp -Xsram[795] sram->in sram[795]->out sram[795]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[795]->out) 0 -.nodeset V(sram[795]->outb) vsp -Xsram[796] sram->in sram[796]->out sram[796]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[796]->out) 0 -.nodeset V(sram[796]->outb) vsp -Xsram[797] sram->in sram[797]->out sram[797]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[797]->out) 0 -.nodeset V(sram[797]->outb) vsp -Xsram[798] sram->in sram[798]->out sram[798]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[798]->out) 0 -.nodeset V(sram[798]->outb) vsp -Xsram[799] sram->in sram[799]->out sram[799]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[799]->out) 0 -.nodeset V(sram[799]->outb) vsp -Xsram[800] sram->in sram[800]->out sram[800]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[800]->out) 0 -.nodeset V(sram[800]->outb) vsp -Xsram[801] sram->in sram[801]->out sram[801]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[801]->out) 0 -.nodeset V(sram[801]->outb) vsp -Xsram[802] sram->in sram[802]->out sram[802]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[802]->out) 0 -.nodeset V(sram[802]->outb) vsp -Xsram[803] sram->in sram[803]->out sram[803]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[803]->out) 0 -.nodeset V(sram[803]->outb) vsp -Xsram[804] sram->in sram[804]->out sram[804]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[804]->out) 0 -.nodeset V(sram[804]->outb) vsp -Xsram[805] sram->in sram[805]->out sram[805]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[805]->out) 0 -.nodeset V(sram[805]->outb) vsp -Xsram[806] sram->in sram[806]->out sram[806]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[806]->out) 0 -.nodeset V(sram[806]->outb) vsp -Xsram[807] sram->in sram[807]->out sram[807]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[807]->out) 0 -.nodeset V(sram[807]->outb) vsp -Xsram[808] sram->in sram[808]->out sram[808]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[808]->out) 0 -.nodeset V(sram[808]->outb) vsp -Xsram[809] sram->in sram[809]->out sram[809]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[809]->out) 0 -.nodeset V(sram[809]->outb) vsp -Xmux_2level_size50[10] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[1]->in[4] sram[810]->outb sram[810]->out sram[811]->out sram[811]->outb sram[812]->out sram[812]->outb sram[813]->out sram[813]->outb sram[814]->out sram[814]->outb sram[815]->out sram[815]->outb sram[816]->out sram[816]->outb sram[817]->out sram[817]->outb sram[818]->outb sram[818]->out sram[819]->out sram[819]->outb sram[820]->out sram[820]->outb sram[821]->out sram[821]->outb sram[822]->out sram[822]->outb sram[823]->out sram[823]->outb sram[824]->out sram[824]->outb sram[825]->out sram[825]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[10], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[810] sram->in sram[810]->out sram[810]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[810]->out) 0 -.nodeset V(sram[810]->outb) vsp -Xsram[811] sram->in sram[811]->out sram[811]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[811]->out) 0 -.nodeset V(sram[811]->outb) vsp -Xsram[812] sram->in sram[812]->out sram[812]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[812]->out) 0 -.nodeset V(sram[812]->outb) vsp -Xsram[813] sram->in sram[813]->out sram[813]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[813]->out) 0 -.nodeset V(sram[813]->outb) vsp -Xsram[814] sram->in sram[814]->out sram[814]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[814]->out) 0 -.nodeset V(sram[814]->outb) vsp -Xsram[815] sram->in sram[815]->out sram[815]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[815]->out) 0 -.nodeset V(sram[815]->outb) vsp -Xsram[816] sram->in sram[816]->out sram[816]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[816]->out) 0 -.nodeset V(sram[816]->outb) vsp -Xsram[817] sram->in sram[817]->out sram[817]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[817]->out) 0 -.nodeset V(sram[817]->outb) vsp -Xsram[818] sram->in sram[818]->out sram[818]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[818]->out) 0 -.nodeset V(sram[818]->outb) vsp -Xsram[819] sram->in sram[819]->out sram[819]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[819]->out) 0 -.nodeset V(sram[819]->outb) vsp -Xsram[820] sram->in sram[820]->out sram[820]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[820]->out) 0 -.nodeset V(sram[820]->outb) vsp -Xsram[821] sram->in sram[821]->out sram[821]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[821]->out) 0 -.nodeset V(sram[821]->outb) vsp -Xsram[822] sram->in sram[822]->out sram[822]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[822]->out) 0 -.nodeset V(sram[822]->outb) vsp -Xsram[823] sram->in sram[823]->out sram[823]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[823]->out) 0 -.nodeset V(sram[823]->outb) vsp -Xsram[824] sram->in sram[824]->out sram[824]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[824]->out) 0 -.nodeset V(sram[824]->outb) vsp -Xsram[825] sram->in sram[825]->out sram[825]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[825]->out) 0 -.nodeset V(sram[825]->outb) vsp -Xmux_2level_size50[11] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[1]->in[5] sram[826]->outb sram[826]->out sram[827]->out sram[827]->outb sram[828]->out sram[828]->outb sram[829]->out sram[829]->outb sram[830]->out sram[830]->outb sram[831]->out sram[831]->outb sram[832]->out sram[832]->outb sram[833]->out sram[833]->outb sram[834]->outb sram[834]->out sram[835]->out sram[835]->outb sram[836]->out sram[836]->outb sram[837]->out sram[837]->outb sram[838]->out sram[838]->outb sram[839]->out sram[839]->outb sram[840]->out sram[840]->outb sram[841]->out sram[841]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[11], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[826] sram->in sram[826]->out sram[826]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[826]->out) 0 -.nodeset V(sram[826]->outb) vsp -Xsram[827] sram->in sram[827]->out sram[827]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[827]->out) 0 -.nodeset V(sram[827]->outb) vsp -Xsram[828] sram->in sram[828]->out sram[828]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[828]->out) 0 -.nodeset V(sram[828]->outb) vsp -Xsram[829] sram->in sram[829]->out sram[829]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[829]->out) 0 -.nodeset V(sram[829]->outb) vsp -Xsram[830] sram->in sram[830]->out sram[830]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[830]->out) 0 -.nodeset V(sram[830]->outb) vsp -Xsram[831] sram->in sram[831]->out sram[831]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[831]->out) 0 -.nodeset V(sram[831]->outb) vsp -Xsram[832] sram->in sram[832]->out sram[832]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[832]->out) 0 -.nodeset V(sram[832]->outb) vsp -Xsram[833] sram->in sram[833]->out sram[833]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[833]->out) 0 -.nodeset V(sram[833]->outb) vsp -Xsram[834] sram->in sram[834]->out sram[834]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[834]->out) 0 -.nodeset V(sram[834]->outb) vsp -Xsram[835] sram->in sram[835]->out sram[835]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[835]->out) 0 -.nodeset V(sram[835]->outb) vsp -Xsram[836] sram->in sram[836]->out sram[836]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[836]->out) 0 -.nodeset V(sram[836]->outb) vsp -Xsram[837] sram->in sram[837]->out sram[837]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[837]->out) 0 -.nodeset V(sram[837]->outb) vsp -Xsram[838] sram->in sram[838]->out sram[838]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[838]->out) 0 -.nodeset V(sram[838]->outb) vsp -Xsram[839] sram->in sram[839]->out sram[839]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[839]->out) 0 -.nodeset V(sram[839]->outb) vsp -Xsram[840] sram->in sram[840]->out sram[840]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[840]->out) 0 -.nodeset V(sram[840]->outb) vsp -Xsram[841] sram->in sram[841]->out sram[841]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[841]->out) 0 -.nodeset V(sram[841]->outb) vsp -Xdirect_interc[171] mode[clb]->clk[0] fle[1]->clk[0] gvdd_local_interc sgnd direct_interc -Xmux_2level_size50[12] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[2]->in[0] sram[842]->outb sram[842]->out sram[843]->out sram[843]->outb sram[844]->out sram[844]->outb sram[845]->out sram[845]->outb sram[846]->out sram[846]->outb sram[847]->out sram[847]->outb sram[848]->out sram[848]->outb sram[849]->out sram[849]->outb sram[850]->outb sram[850]->out sram[851]->out sram[851]->outb sram[852]->out sram[852]->outb sram[853]->out sram[853]->outb sram[854]->out sram[854]->outb sram[855]->out sram[855]->outb sram[856]->out sram[856]->outb sram[857]->out sram[857]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[12], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[842] sram->in sram[842]->out sram[842]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[842]->out) 0 -.nodeset V(sram[842]->outb) vsp -Xsram[843] sram->in sram[843]->out sram[843]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[843]->out) 0 -.nodeset V(sram[843]->outb) vsp -Xsram[844] sram->in sram[844]->out sram[844]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[844]->out) 0 -.nodeset V(sram[844]->outb) vsp -Xsram[845] sram->in sram[845]->out sram[845]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[845]->out) 0 -.nodeset V(sram[845]->outb) vsp -Xsram[846] sram->in sram[846]->out sram[846]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[846]->out) 0 -.nodeset V(sram[846]->outb) vsp -Xsram[847] sram->in sram[847]->out sram[847]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[847]->out) 0 -.nodeset V(sram[847]->outb) vsp -Xsram[848] sram->in sram[848]->out sram[848]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[848]->out) 0 -.nodeset V(sram[848]->outb) vsp -Xsram[849] sram->in sram[849]->out sram[849]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[849]->out) 0 -.nodeset V(sram[849]->outb) vsp -Xsram[850] sram->in sram[850]->out sram[850]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[850]->out) 0 -.nodeset V(sram[850]->outb) vsp -Xsram[851] sram->in sram[851]->out sram[851]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[851]->out) 0 -.nodeset V(sram[851]->outb) vsp -Xsram[852] sram->in sram[852]->out sram[852]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[852]->out) 0 -.nodeset V(sram[852]->outb) vsp -Xsram[853] sram->in sram[853]->out sram[853]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[853]->out) 0 -.nodeset V(sram[853]->outb) vsp -Xsram[854] sram->in sram[854]->out sram[854]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[854]->out) 0 -.nodeset V(sram[854]->outb) vsp -Xsram[855] sram->in sram[855]->out sram[855]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[855]->out) 0 -.nodeset V(sram[855]->outb) vsp -Xsram[856] sram->in sram[856]->out sram[856]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[856]->out) 0 -.nodeset V(sram[856]->outb) vsp -Xsram[857] sram->in sram[857]->out sram[857]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[857]->out) 0 -.nodeset V(sram[857]->outb) vsp -Xmux_2level_size50[13] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[2]->in[1] sram[858]->outb sram[858]->out sram[859]->out sram[859]->outb sram[860]->out sram[860]->outb sram[861]->out sram[861]->outb sram[862]->out sram[862]->outb sram[863]->out sram[863]->outb sram[864]->out sram[864]->outb sram[865]->out sram[865]->outb sram[866]->outb sram[866]->out sram[867]->out sram[867]->outb sram[868]->out sram[868]->outb sram[869]->out sram[869]->outb sram[870]->out sram[870]->outb sram[871]->out sram[871]->outb sram[872]->out sram[872]->outb sram[873]->out sram[873]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[13], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[858] sram->in sram[858]->out sram[858]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[858]->out) 0 -.nodeset V(sram[858]->outb) vsp -Xsram[859] sram->in sram[859]->out sram[859]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[859]->out) 0 -.nodeset V(sram[859]->outb) vsp -Xsram[860] sram->in sram[860]->out sram[860]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[860]->out) 0 -.nodeset V(sram[860]->outb) vsp -Xsram[861] sram->in sram[861]->out sram[861]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[861]->out) 0 -.nodeset V(sram[861]->outb) vsp -Xsram[862] sram->in sram[862]->out sram[862]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[862]->out) 0 -.nodeset V(sram[862]->outb) vsp -Xsram[863] sram->in sram[863]->out sram[863]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[863]->out) 0 -.nodeset V(sram[863]->outb) vsp -Xsram[864] sram->in sram[864]->out sram[864]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[864]->out) 0 -.nodeset V(sram[864]->outb) vsp -Xsram[865] sram->in sram[865]->out sram[865]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[865]->out) 0 -.nodeset V(sram[865]->outb) vsp -Xsram[866] sram->in sram[866]->out sram[866]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[866]->out) 0 -.nodeset V(sram[866]->outb) vsp -Xsram[867] sram->in sram[867]->out sram[867]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[867]->out) 0 -.nodeset V(sram[867]->outb) vsp -Xsram[868] sram->in sram[868]->out sram[868]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[868]->out) 0 -.nodeset V(sram[868]->outb) vsp -Xsram[869] sram->in sram[869]->out sram[869]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[869]->out) 0 -.nodeset V(sram[869]->outb) vsp -Xsram[870] sram->in sram[870]->out sram[870]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[870]->out) 0 -.nodeset V(sram[870]->outb) vsp -Xsram[871] sram->in sram[871]->out sram[871]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[871]->out) 0 -.nodeset V(sram[871]->outb) vsp -Xsram[872] sram->in sram[872]->out sram[872]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[872]->out) 0 -.nodeset V(sram[872]->outb) vsp -Xsram[873] sram->in sram[873]->out sram[873]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[873]->out) 0 -.nodeset V(sram[873]->outb) vsp -Xmux_2level_size50[14] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[2]->in[2] sram[874]->outb sram[874]->out sram[875]->out sram[875]->outb sram[876]->out sram[876]->outb sram[877]->out sram[877]->outb sram[878]->out sram[878]->outb sram[879]->out sram[879]->outb sram[880]->out sram[880]->outb sram[881]->out sram[881]->outb sram[882]->outb sram[882]->out sram[883]->out sram[883]->outb sram[884]->out sram[884]->outb sram[885]->out sram[885]->outb sram[886]->out sram[886]->outb sram[887]->out sram[887]->outb sram[888]->out sram[888]->outb sram[889]->out sram[889]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[14], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[874] sram->in sram[874]->out sram[874]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[874]->out) 0 -.nodeset V(sram[874]->outb) vsp -Xsram[875] sram->in sram[875]->out sram[875]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[875]->out) 0 -.nodeset V(sram[875]->outb) vsp -Xsram[876] sram->in sram[876]->out sram[876]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[876]->out) 0 -.nodeset V(sram[876]->outb) vsp -Xsram[877] sram->in sram[877]->out sram[877]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[877]->out) 0 -.nodeset V(sram[877]->outb) vsp -Xsram[878] sram->in sram[878]->out sram[878]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[878]->out) 0 -.nodeset V(sram[878]->outb) vsp -Xsram[879] sram->in sram[879]->out sram[879]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[879]->out) 0 -.nodeset V(sram[879]->outb) vsp -Xsram[880] sram->in sram[880]->out sram[880]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[880]->out) 0 -.nodeset V(sram[880]->outb) vsp -Xsram[881] sram->in sram[881]->out sram[881]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[881]->out) 0 -.nodeset V(sram[881]->outb) vsp -Xsram[882] sram->in sram[882]->out sram[882]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[882]->out) 0 -.nodeset V(sram[882]->outb) vsp -Xsram[883] sram->in sram[883]->out sram[883]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[883]->out) 0 -.nodeset V(sram[883]->outb) vsp -Xsram[884] sram->in sram[884]->out sram[884]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[884]->out) 0 -.nodeset V(sram[884]->outb) vsp -Xsram[885] sram->in sram[885]->out sram[885]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[885]->out) 0 -.nodeset V(sram[885]->outb) vsp -Xsram[886] sram->in sram[886]->out sram[886]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[886]->out) 0 -.nodeset V(sram[886]->outb) vsp -Xsram[887] sram->in sram[887]->out sram[887]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[887]->out) 0 -.nodeset V(sram[887]->outb) vsp -Xsram[888] sram->in sram[888]->out sram[888]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[888]->out) 0 -.nodeset V(sram[888]->outb) vsp -Xsram[889] sram->in sram[889]->out sram[889]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[889]->out) 0 -.nodeset V(sram[889]->outb) vsp -Xmux_2level_size50[15] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[2]->in[3] sram[890]->outb sram[890]->out sram[891]->out sram[891]->outb sram[892]->out sram[892]->outb sram[893]->out sram[893]->outb sram[894]->out sram[894]->outb sram[895]->out sram[895]->outb sram[896]->out sram[896]->outb sram[897]->out sram[897]->outb sram[898]->outb sram[898]->out sram[899]->out sram[899]->outb sram[900]->out sram[900]->outb sram[901]->out sram[901]->outb sram[902]->out sram[902]->outb sram[903]->out sram[903]->outb sram[904]->out sram[904]->outb sram[905]->out sram[905]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[15], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[890] sram->in sram[890]->out sram[890]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[890]->out) 0 -.nodeset V(sram[890]->outb) vsp -Xsram[891] sram->in sram[891]->out sram[891]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[891]->out) 0 -.nodeset V(sram[891]->outb) vsp -Xsram[892] sram->in sram[892]->out sram[892]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[892]->out) 0 -.nodeset V(sram[892]->outb) vsp -Xsram[893] sram->in sram[893]->out sram[893]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[893]->out) 0 -.nodeset V(sram[893]->outb) vsp -Xsram[894] sram->in sram[894]->out sram[894]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[894]->out) 0 -.nodeset V(sram[894]->outb) vsp -Xsram[895] sram->in sram[895]->out sram[895]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[895]->out) 0 -.nodeset V(sram[895]->outb) vsp -Xsram[896] sram->in sram[896]->out sram[896]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[896]->out) 0 -.nodeset V(sram[896]->outb) vsp -Xsram[897] sram->in sram[897]->out sram[897]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[897]->out) 0 -.nodeset V(sram[897]->outb) vsp -Xsram[898] sram->in sram[898]->out sram[898]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[898]->out) 0 -.nodeset V(sram[898]->outb) vsp -Xsram[899] sram->in sram[899]->out sram[899]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[899]->out) 0 -.nodeset V(sram[899]->outb) vsp -Xsram[900] sram->in sram[900]->out sram[900]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[900]->out) 0 -.nodeset V(sram[900]->outb) vsp -Xsram[901] sram->in sram[901]->out sram[901]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[901]->out) 0 -.nodeset V(sram[901]->outb) vsp -Xsram[902] sram->in sram[902]->out sram[902]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[902]->out) 0 -.nodeset V(sram[902]->outb) vsp -Xsram[903] sram->in sram[903]->out sram[903]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[903]->out) 0 -.nodeset V(sram[903]->outb) vsp -Xsram[904] sram->in sram[904]->out sram[904]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[904]->out) 0 -.nodeset V(sram[904]->outb) vsp -Xsram[905] sram->in sram[905]->out sram[905]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[905]->out) 0 -.nodeset V(sram[905]->outb) vsp -Xmux_2level_size50[16] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[2]->in[4] sram[906]->outb sram[906]->out sram[907]->out sram[907]->outb sram[908]->out sram[908]->outb sram[909]->out sram[909]->outb sram[910]->out sram[910]->outb sram[911]->out sram[911]->outb sram[912]->out sram[912]->outb sram[913]->out sram[913]->outb sram[914]->outb sram[914]->out sram[915]->out sram[915]->outb sram[916]->out sram[916]->outb sram[917]->out sram[917]->outb sram[918]->out sram[918]->outb sram[919]->out sram[919]->outb sram[920]->out sram[920]->outb sram[921]->out sram[921]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[16], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[906] sram->in sram[906]->out sram[906]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[906]->out) 0 -.nodeset V(sram[906]->outb) vsp -Xsram[907] sram->in sram[907]->out sram[907]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[907]->out) 0 -.nodeset V(sram[907]->outb) vsp -Xsram[908] sram->in sram[908]->out sram[908]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[908]->out) 0 -.nodeset V(sram[908]->outb) vsp -Xsram[909] sram->in sram[909]->out sram[909]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[909]->out) 0 -.nodeset V(sram[909]->outb) vsp -Xsram[910] sram->in sram[910]->out sram[910]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[910]->out) 0 -.nodeset V(sram[910]->outb) vsp -Xsram[911] sram->in sram[911]->out sram[911]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[911]->out) 0 -.nodeset V(sram[911]->outb) vsp -Xsram[912] sram->in sram[912]->out sram[912]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[912]->out) 0 -.nodeset V(sram[912]->outb) vsp -Xsram[913] sram->in sram[913]->out sram[913]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[913]->out) 0 -.nodeset V(sram[913]->outb) vsp -Xsram[914] sram->in sram[914]->out sram[914]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[914]->out) 0 -.nodeset V(sram[914]->outb) vsp -Xsram[915] sram->in sram[915]->out sram[915]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[915]->out) 0 -.nodeset V(sram[915]->outb) vsp -Xsram[916] sram->in sram[916]->out sram[916]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[916]->out) 0 -.nodeset V(sram[916]->outb) vsp -Xsram[917] sram->in sram[917]->out sram[917]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[917]->out) 0 -.nodeset V(sram[917]->outb) vsp -Xsram[918] sram->in sram[918]->out sram[918]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[918]->out) 0 -.nodeset V(sram[918]->outb) vsp -Xsram[919] sram->in sram[919]->out sram[919]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[919]->out) 0 -.nodeset V(sram[919]->outb) vsp -Xsram[920] sram->in sram[920]->out sram[920]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[920]->out) 0 -.nodeset V(sram[920]->outb) vsp -Xsram[921] sram->in sram[921]->out sram[921]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[921]->out) 0 -.nodeset V(sram[921]->outb) vsp -Xmux_2level_size50[17] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[2]->in[5] sram[922]->outb sram[922]->out sram[923]->out sram[923]->outb sram[924]->out sram[924]->outb sram[925]->out sram[925]->outb sram[926]->out sram[926]->outb sram[927]->out sram[927]->outb sram[928]->out sram[928]->outb sram[929]->out sram[929]->outb sram[930]->outb sram[930]->out sram[931]->out sram[931]->outb sram[932]->out sram[932]->outb sram[933]->out sram[933]->outb sram[934]->out sram[934]->outb sram[935]->out sram[935]->outb sram[936]->out sram[936]->outb sram[937]->out sram[937]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[17], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[922] sram->in sram[922]->out sram[922]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[922]->out) 0 -.nodeset V(sram[922]->outb) vsp -Xsram[923] sram->in sram[923]->out sram[923]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[923]->out) 0 -.nodeset V(sram[923]->outb) vsp -Xsram[924] sram->in sram[924]->out sram[924]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[924]->out) 0 -.nodeset V(sram[924]->outb) vsp -Xsram[925] sram->in sram[925]->out sram[925]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[925]->out) 0 -.nodeset V(sram[925]->outb) vsp -Xsram[926] sram->in sram[926]->out sram[926]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[926]->out) 0 -.nodeset V(sram[926]->outb) vsp -Xsram[927] sram->in sram[927]->out sram[927]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[927]->out) 0 -.nodeset V(sram[927]->outb) vsp -Xsram[928] sram->in sram[928]->out sram[928]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[928]->out) 0 -.nodeset V(sram[928]->outb) vsp -Xsram[929] sram->in sram[929]->out sram[929]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[929]->out) 0 -.nodeset V(sram[929]->outb) vsp -Xsram[930] sram->in sram[930]->out sram[930]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[930]->out) 0 -.nodeset V(sram[930]->outb) vsp -Xsram[931] sram->in sram[931]->out sram[931]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[931]->out) 0 -.nodeset V(sram[931]->outb) vsp -Xsram[932] sram->in sram[932]->out sram[932]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[932]->out) 0 -.nodeset V(sram[932]->outb) vsp -Xsram[933] sram->in sram[933]->out sram[933]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[933]->out) 0 -.nodeset V(sram[933]->outb) vsp -Xsram[934] sram->in sram[934]->out sram[934]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[934]->out) 0 -.nodeset V(sram[934]->outb) vsp -Xsram[935] sram->in sram[935]->out sram[935]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[935]->out) 0 -.nodeset V(sram[935]->outb) vsp -Xsram[936] sram->in sram[936]->out sram[936]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[936]->out) 0 -.nodeset V(sram[936]->outb) vsp -Xsram[937] sram->in sram[937]->out sram[937]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[937]->out) 0 -.nodeset V(sram[937]->outb) vsp -Xdirect_interc[172] mode[clb]->clk[0] fle[2]->clk[0] gvdd_local_interc sgnd direct_interc -Xmux_2level_size50[18] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[3]->in[0] sram[938]->outb sram[938]->out sram[939]->out sram[939]->outb sram[940]->out sram[940]->outb sram[941]->out sram[941]->outb sram[942]->out sram[942]->outb sram[943]->out sram[943]->outb sram[944]->out sram[944]->outb sram[945]->out sram[945]->outb sram[946]->outb sram[946]->out sram[947]->out sram[947]->outb sram[948]->out sram[948]->outb sram[949]->out sram[949]->outb sram[950]->out sram[950]->outb sram[951]->out sram[951]->outb sram[952]->out sram[952]->outb sram[953]->out sram[953]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[18], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[938] sram->in sram[938]->out sram[938]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[938]->out) 0 -.nodeset V(sram[938]->outb) vsp -Xsram[939] sram->in sram[939]->out sram[939]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[939]->out) 0 -.nodeset V(sram[939]->outb) vsp -Xsram[940] sram->in sram[940]->out sram[940]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[940]->out) 0 -.nodeset V(sram[940]->outb) vsp -Xsram[941] sram->in sram[941]->out sram[941]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[941]->out) 0 -.nodeset V(sram[941]->outb) vsp -Xsram[942] sram->in sram[942]->out sram[942]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[942]->out) 0 -.nodeset V(sram[942]->outb) vsp -Xsram[943] sram->in sram[943]->out sram[943]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[943]->out) 0 -.nodeset V(sram[943]->outb) vsp -Xsram[944] sram->in sram[944]->out sram[944]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[944]->out) 0 -.nodeset V(sram[944]->outb) vsp -Xsram[945] sram->in sram[945]->out sram[945]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[945]->out) 0 -.nodeset V(sram[945]->outb) vsp -Xsram[946] sram->in sram[946]->out sram[946]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[946]->out) 0 -.nodeset V(sram[946]->outb) vsp -Xsram[947] sram->in sram[947]->out sram[947]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[947]->out) 0 -.nodeset V(sram[947]->outb) vsp -Xsram[948] sram->in sram[948]->out sram[948]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[948]->out) 0 -.nodeset V(sram[948]->outb) vsp -Xsram[949] sram->in sram[949]->out sram[949]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[949]->out) 0 -.nodeset V(sram[949]->outb) vsp -Xsram[950] sram->in sram[950]->out sram[950]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[950]->out) 0 -.nodeset V(sram[950]->outb) vsp -Xsram[951] sram->in sram[951]->out sram[951]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[951]->out) 0 -.nodeset V(sram[951]->outb) vsp -Xsram[952] sram->in sram[952]->out sram[952]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[952]->out) 0 -.nodeset V(sram[952]->outb) vsp -Xsram[953] sram->in sram[953]->out sram[953]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[953]->out) 0 -.nodeset V(sram[953]->outb) vsp -Xmux_2level_size50[19] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[3]->in[1] sram[954]->outb sram[954]->out sram[955]->out sram[955]->outb sram[956]->out sram[956]->outb sram[957]->out sram[957]->outb sram[958]->out sram[958]->outb sram[959]->out sram[959]->outb sram[960]->out sram[960]->outb sram[961]->out sram[961]->outb sram[962]->outb sram[962]->out sram[963]->out sram[963]->outb sram[964]->out sram[964]->outb sram[965]->out sram[965]->outb sram[966]->out sram[966]->outb sram[967]->out sram[967]->outb sram[968]->out sram[968]->outb sram[969]->out sram[969]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[19], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[954] sram->in sram[954]->out sram[954]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[954]->out) 0 -.nodeset V(sram[954]->outb) vsp -Xsram[955] sram->in sram[955]->out sram[955]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[955]->out) 0 -.nodeset V(sram[955]->outb) vsp -Xsram[956] sram->in sram[956]->out sram[956]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[956]->out) 0 -.nodeset V(sram[956]->outb) vsp -Xsram[957] sram->in sram[957]->out sram[957]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[957]->out) 0 -.nodeset V(sram[957]->outb) vsp -Xsram[958] sram->in sram[958]->out sram[958]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[958]->out) 0 -.nodeset V(sram[958]->outb) vsp -Xsram[959] sram->in sram[959]->out sram[959]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[959]->out) 0 -.nodeset V(sram[959]->outb) vsp -Xsram[960] sram->in sram[960]->out sram[960]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[960]->out) 0 -.nodeset V(sram[960]->outb) vsp -Xsram[961] sram->in sram[961]->out sram[961]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[961]->out) 0 -.nodeset V(sram[961]->outb) vsp -Xsram[962] sram->in sram[962]->out sram[962]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[962]->out) 0 -.nodeset V(sram[962]->outb) vsp -Xsram[963] sram->in sram[963]->out sram[963]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[963]->out) 0 -.nodeset V(sram[963]->outb) vsp -Xsram[964] sram->in sram[964]->out sram[964]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[964]->out) 0 -.nodeset V(sram[964]->outb) vsp -Xsram[965] sram->in sram[965]->out sram[965]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[965]->out) 0 -.nodeset V(sram[965]->outb) vsp -Xsram[966] sram->in sram[966]->out sram[966]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[966]->out) 0 -.nodeset V(sram[966]->outb) vsp -Xsram[967] sram->in sram[967]->out sram[967]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[967]->out) 0 -.nodeset V(sram[967]->outb) vsp -Xsram[968] sram->in sram[968]->out sram[968]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[968]->out) 0 -.nodeset V(sram[968]->outb) vsp -Xsram[969] sram->in sram[969]->out sram[969]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[969]->out) 0 -.nodeset V(sram[969]->outb) vsp -Xmux_2level_size50[20] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[3]->in[2] sram[970]->outb sram[970]->out sram[971]->out sram[971]->outb sram[972]->out sram[972]->outb sram[973]->out sram[973]->outb sram[974]->out sram[974]->outb sram[975]->out sram[975]->outb sram[976]->out sram[976]->outb sram[977]->out sram[977]->outb sram[978]->outb sram[978]->out sram[979]->out sram[979]->outb sram[980]->out sram[980]->outb sram[981]->out sram[981]->outb sram[982]->out sram[982]->outb sram[983]->out sram[983]->outb sram[984]->out sram[984]->outb sram[985]->out sram[985]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[20], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[970] sram->in sram[970]->out sram[970]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[970]->out) 0 -.nodeset V(sram[970]->outb) vsp -Xsram[971] sram->in sram[971]->out sram[971]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[971]->out) 0 -.nodeset V(sram[971]->outb) vsp -Xsram[972] sram->in sram[972]->out sram[972]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[972]->out) 0 -.nodeset V(sram[972]->outb) vsp -Xsram[973] sram->in sram[973]->out sram[973]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[973]->out) 0 -.nodeset V(sram[973]->outb) vsp -Xsram[974] sram->in sram[974]->out sram[974]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[974]->out) 0 -.nodeset V(sram[974]->outb) vsp -Xsram[975] sram->in sram[975]->out sram[975]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[975]->out) 0 -.nodeset V(sram[975]->outb) vsp -Xsram[976] sram->in sram[976]->out sram[976]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[976]->out) 0 -.nodeset V(sram[976]->outb) vsp -Xsram[977] sram->in sram[977]->out sram[977]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[977]->out) 0 -.nodeset V(sram[977]->outb) vsp -Xsram[978] sram->in sram[978]->out sram[978]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[978]->out) 0 -.nodeset V(sram[978]->outb) vsp -Xsram[979] sram->in sram[979]->out sram[979]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[979]->out) 0 -.nodeset V(sram[979]->outb) vsp -Xsram[980] sram->in sram[980]->out sram[980]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[980]->out) 0 -.nodeset V(sram[980]->outb) vsp -Xsram[981] sram->in sram[981]->out sram[981]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[981]->out) 0 -.nodeset V(sram[981]->outb) vsp -Xsram[982] sram->in sram[982]->out sram[982]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[982]->out) 0 -.nodeset V(sram[982]->outb) vsp -Xsram[983] sram->in sram[983]->out sram[983]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[983]->out) 0 -.nodeset V(sram[983]->outb) vsp -Xsram[984] sram->in sram[984]->out sram[984]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[984]->out) 0 -.nodeset V(sram[984]->outb) vsp -Xsram[985] sram->in sram[985]->out sram[985]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[985]->out) 0 -.nodeset V(sram[985]->outb) vsp -Xmux_2level_size50[21] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[3]->in[3] sram[986]->outb sram[986]->out sram[987]->out sram[987]->outb sram[988]->out sram[988]->outb sram[989]->out sram[989]->outb sram[990]->out sram[990]->outb sram[991]->out sram[991]->outb sram[992]->out sram[992]->outb sram[993]->out sram[993]->outb sram[994]->outb sram[994]->out sram[995]->out sram[995]->outb sram[996]->out sram[996]->outb sram[997]->out sram[997]->outb sram[998]->out sram[998]->outb sram[999]->out sram[999]->outb sram[1000]->out sram[1000]->outb sram[1001]->out sram[1001]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[21], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[986] sram->in sram[986]->out sram[986]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[986]->out) 0 -.nodeset V(sram[986]->outb) vsp -Xsram[987] sram->in sram[987]->out sram[987]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[987]->out) 0 -.nodeset V(sram[987]->outb) vsp -Xsram[988] sram->in sram[988]->out sram[988]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[988]->out) 0 -.nodeset V(sram[988]->outb) vsp -Xsram[989] sram->in sram[989]->out sram[989]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[989]->out) 0 -.nodeset V(sram[989]->outb) vsp -Xsram[990] sram->in sram[990]->out sram[990]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[990]->out) 0 -.nodeset V(sram[990]->outb) vsp -Xsram[991] sram->in sram[991]->out sram[991]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[991]->out) 0 -.nodeset V(sram[991]->outb) vsp -Xsram[992] sram->in sram[992]->out sram[992]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[992]->out) 0 -.nodeset V(sram[992]->outb) vsp -Xsram[993] sram->in sram[993]->out sram[993]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[993]->out) 0 -.nodeset V(sram[993]->outb) vsp -Xsram[994] sram->in sram[994]->out sram[994]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[994]->out) 0 -.nodeset V(sram[994]->outb) vsp -Xsram[995] sram->in sram[995]->out sram[995]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[995]->out) 0 -.nodeset V(sram[995]->outb) vsp -Xsram[996] sram->in sram[996]->out sram[996]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[996]->out) 0 -.nodeset V(sram[996]->outb) vsp -Xsram[997] sram->in sram[997]->out sram[997]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[997]->out) 0 -.nodeset V(sram[997]->outb) vsp -Xsram[998] sram->in sram[998]->out sram[998]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[998]->out) 0 -.nodeset V(sram[998]->outb) vsp -Xsram[999] sram->in sram[999]->out sram[999]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[999]->out) 0 -.nodeset V(sram[999]->outb) vsp -Xsram[1000] sram->in sram[1000]->out sram[1000]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1000]->out) 0 -.nodeset V(sram[1000]->outb) vsp -Xsram[1001] sram->in sram[1001]->out sram[1001]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1001]->out) 0 -.nodeset V(sram[1001]->outb) vsp -Xmux_2level_size50[22] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[3]->in[4] sram[1002]->outb sram[1002]->out sram[1003]->out sram[1003]->outb sram[1004]->out sram[1004]->outb sram[1005]->out sram[1005]->outb sram[1006]->out sram[1006]->outb sram[1007]->out sram[1007]->outb sram[1008]->out sram[1008]->outb sram[1009]->out sram[1009]->outb sram[1010]->outb sram[1010]->out sram[1011]->out sram[1011]->outb sram[1012]->out sram[1012]->outb sram[1013]->out sram[1013]->outb sram[1014]->out sram[1014]->outb sram[1015]->out sram[1015]->outb sram[1016]->out sram[1016]->outb sram[1017]->out sram[1017]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[22], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1002] sram->in sram[1002]->out sram[1002]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1002]->out) 0 -.nodeset V(sram[1002]->outb) vsp -Xsram[1003] sram->in sram[1003]->out sram[1003]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1003]->out) 0 -.nodeset V(sram[1003]->outb) vsp -Xsram[1004] sram->in sram[1004]->out sram[1004]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1004]->out) 0 -.nodeset V(sram[1004]->outb) vsp -Xsram[1005] sram->in sram[1005]->out sram[1005]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1005]->out) 0 -.nodeset V(sram[1005]->outb) vsp -Xsram[1006] sram->in sram[1006]->out sram[1006]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1006]->out) 0 -.nodeset V(sram[1006]->outb) vsp -Xsram[1007] sram->in sram[1007]->out sram[1007]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1007]->out) 0 -.nodeset V(sram[1007]->outb) vsp -Xsram[1008] sram->in sram[1008]->out sram[1008]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1008]->out) 0 -.nodeset V(sram[1008]->outb) vsp -Xsram[1009] sram->in sram[1009]->out sram[1009]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1009]->out) 0 -.nodeset V(sram[1009]->outb) vsp -Xsram[1010] sram->in sram[1010]->out sram[1010]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1010]->out) 0 -.nodeset V(sram[1010]->outb) vsp -Xsram[1011] sram->in sram[1011]->out sram[1011]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1011]->out) 0 -.nodeset V(sram[1011]->outb) vsp -Xsram[1012] sram->in sram[1012]->out sram[1012]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1012]->out) 0 -.nodeset V(sram[1012]->outb) vsp -Xsram[1013] sram->in sram[1013]->out sram[1013]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1013]->out) 0 -.nodeset V(sram[1013]->outb) vsp -Xsram[1014] sram->in sram[1014]->out sram[1014]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1014]->out) 0 -.nodeset V(sram[1014]->outb) vsp -Xsram[1015] sram->in sram[1015]->out sram[1015]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1015]->out) 0 -.nodeset V(sram[1015]->outb) vsp -Xsram[1016] sram->in sram[1016]->out sram[1016]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1016]->out) 0 -.nodeset V(sram[1016]->outb) vsp -Xsram[1017] sram->in sram[1017]->out sram[1017]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1017]->out) 0 -.nodeset V(sram[1017]->outb) vsp -Xmux_2level_size50[23] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[3]->in[5] sram[1018]->outb sram[1018]->out sram[1019]->out sram[1019]->outb sram[1020]->out sram[1020]->outb sram[1021]->out sram[1021]->outb sram[1022]->out sram[1022]->outb sram[1023]->out sram[1023]->outb sram[1024]->out sram[1024]->outb sram[1025]->out sram[1025]->outb sram[1026]->outb sram[1026]->out sram[1027]->out sram[1027]->outb sram[1028]->out sram[1028]->outb sram[1029]->out sram[1029]->outb sram[1030]->out sram[1030]->outb sram[1031]->out sram[1031]->outb sram[1032]->out sram[1032]->outb sram[1033]->out sram[1033]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[23], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1018] sram->in sram[1018]->out sram[1018]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1018]->out) 0 -.nodeset V(sram[1018]->outb) vsp -Xsram[1019] sram->in sram[1019]->out sram[1019]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1019]->out) 0 -.nodeset V(sram[1019]->outb) vsp -Xsram[1020] sram->in sram[1020]->out sram[1020]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1020]->out) 0 -.nodeset V(sram[1020]->outb) vsp -Xsram[1021] sram->in sram[1021]->out sram[1021]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1021]->out) 0 -.nodeset V(sram[1021]->outb) vsp -Xsram[1022] sram->in sram[1022]->out sram[1022]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1022]->out) 0 -.nodeset V(sram[1022]->outb) vsp -Xsram[1023] sram->in sram[1023]->out sram[1023]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1023]->out) 0 -.nodeset V(sram[1023]->outb) vsp -Xsram[1024] sram->in sram[1024]->out sram[1024]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1024]->out) 0 -.nodeset V(sram[1024]->outb) vsp -Xsram[1025] sram->in sram[1025]->out sram[1025]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1025]->out) 0 -.nodeset V(sram[1025]->outb) vsp -Xsram[1026] sram->in sram[1026]->out sram[1026]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1026]->out) 0 -.nodeset V(sram[1026]->outb) vsp -Xsram[1027] sram->in sram[1027]->out sram[1027]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1027]->out) 0 -.nodeset V(sram[1027]->outb) vsp -Xsram[1028] sram->in sram[1028]->out sram[1028]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1028]->out) 0 -.nodeset V(sram[1028]->outb) vsp -Xsram[1029] sram->in sram[1029]->out sram[1029]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1029]->out) 0 -.nodeset V(sram[1029]->outb) vsp -Xsram[1030] sram->in sram[1030]->out sram[1030]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1030]->out) 0 -.nodeset V(sram[1030]->outb) vsp -Xsram[1031] sram->in sram[1031]->out sram[1031]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1031]->out) 0 -.nodeset V(sram[1031]->outb) vsp -Xsram[1032] sram->in sram[1032]->out sram[1032]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1032]->out) 0 -.nodeset V(sram[1032]->outb) vsp -Xsram[1033] sram->in sram[1033]->out sram[1033]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1033]->out) 0 -.nodeset V(sram[1033]->outb) vsp -Xdirect_interc[173] mode[clb]->clk[0] fle[3]->clk[0] gvdd_local_interc sgnd direct_interc -Xmux_2level_size50[24] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[4]->in[0] sram[1034]->outb sram[1034]->out sram[1035]->out sram[1035]->outb sram[1036]->out sram[1036]->outb sram[1037]->out sram[1037]->outb sram[1038]->out sram[1038]->outb sram[1039]->out sram[1039]->outb sram[1040]->out sram[1040]->outb sram[1041]->out sram[1041]->outb sram[1042]->outb sram[1042]->out sram[1043]->out sram[1043]->outb sram[1044]->out sram[1044]->outb sram[1045]->out sram[1045]->outb sram[1046]->out sram[1046]->outb sram[1047]->out sram[1047]->outb sram[1048]->out sram[1048]->outb sram[1049]->out sram[1049]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[24], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1034] sram->in sram[1034]->out sram[1034]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1034]->out) 0 -.nodeset V(sram[1034]->outb) vsp -Xsram[1035] sram->in sram[1035]->out sram[1035]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1035]->out) 0 -.nodeset V(sram[1035]->outb) vsp -Xsram[1036] sram->in sram[1036]->out sram[1036]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1036]->out) 0 -.nodeset V(sram[1036]->outb) vsp -Xsram[1037] sram->in sram[1037]->out sram[1037]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1037]->out) 0 -.nodeset V(sram[1037]->outb) vsp -Xsram[1038] sram->in sram[1038]->out sram[1038]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1038]->out) 0 -.nodeset V(sram[1038]->outb) vsp -Xsram[1039] sram->in sram[1039]->out sram[1039]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1039]->out) 0 -.nodeset V(sram[1039]->outb) vsp -Xsram[1040] sram->in sram[1040]->out sram[1040]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1040]->out) 0 -.nodeset V(sram[1040]->outb) vsp -Xsram[1041] sram->in sram[1041]->out sram[1041]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1041]->out) 0 -.nodeset V(sram[1041]->outb) vsp -Xsram[1042] sram->in sram[1042]->out sram[1042]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1042]->out) 0 -.nodeset V(sram[1042]->outb) vsp -Xsram[1043] sram->in sram[1043]->out sram[1043]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1043]->out) 0 -.nodeset V(sram[1043]->outb) vsp -Xsram[1044] sram->in sram[1044]->out sram[1044]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1044]->out) 0 -.nodeset V(sram[1044]->outb) vsp -Xsram[1045] sram->in sram[1045]->out sram[1045]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1045]->out) 0 -.nodeset V(sram[1045]->outb) vsp -Xsram[1046] sram->in sram[1046]->out sram[1046]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1046]->out) 0 -.nodeset V(sram[1046]->outb) vsp -Xsram[1047] sram->in sram[1047]->out sram[1047]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1047]->out) 0 -.nodeset V(sram[1047]->outb) vsp -Xsram[1048] sram->in sram[1048]->out sram[1048]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1048]->out) 0 -.nodeset V(sram[1048]->outb) vsp -Xsram[1049] sram->in sram[1049]->out sram[1049]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1049]->out) 0 -.nodeset V(sram[1049]->outb) vsp -Xmux_2level_size50[25] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[4]->in[1] sram[1050]->outb sram[1050]->out sram[1051]->out sram[1051]->outb sram[1052]->out sram[1052]->outb sram[1053]->out sram[1053]->outb sram[1054]->out sram[1054]->outb sram[1055]->out sram[1055]->outb sram[1056]->out sram[1056]->outb sram[1057]->out sram[1057]->outb sram[1058]->outb sram[1058]->out sram[1059]->out sram[1059]->outb sram[1060]->out sram[1060]->outb sram[1061]->out sram[1061]->outb sram[1062]->out sram[1062]->outb sram[1063]->out sram[1063]->outb sram[1064]->out sram[1064]->outb sram[1065]->out sram[1065]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[25], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1050] sram->in sram[1050]->out sram[1050]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1050]->out) 0 -.nodeset V(sram[1050]->outb) vsp -Xsram[1051] sram->in sram[1051]->out sram[1051]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1051]->out) 0 -.nodeset V(sram[1051]->outb) vsp -Xsram[1052] sram->in sram[1052]->out sram[1052]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1052]->out) 0 -.nodeset V(sram[1052]->outb) vsp -Xsram[1053] sram->in sram[1053]->out sram[1053]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1053]->out) 0 -.nodeset V(sram[1053]->outb) vsp -Xsram[1054] sram->in sram[1054]->out sram[1054]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1054]->out) 0 -.nodeset V(sram[1054]->outb) vsp -Xsram[1055] sram->in sram[1055]->out sram[1055]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1055]->out) 0 -.nodeset V(sram[1055]->outb) vsp -Xsram[1056] sram->in sram[1056]->out sram[1056]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1056]->out) 0 -.nodeset V(sram[1056]->outb) vsp -Xsram[1057] sram->in sram[1057]->out sram[1057]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1057]->out) 0 -.nodeset V(sram[1057]->outb) vsp -Xsram[1058] sram->in sram[1058]->out sram[1058]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1058]->out) 0 -.nodeset V(sram[1058]->outb) vsp -Xsram[1059] sram->in sram[1059]->out sram[1059]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1059]->out) 0 -.nodeset V(sram[1059]->outb) vsp -Xsram[1060] sram->in sram[1060]->out sram[1060]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1060]->out) 0 -.nodeset V(sram[1060]->outb) vsp -Xsram[1061] sram->in sram[1061]->out sram[1061]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1061]->out) 0 -.nodeset V(sram[1061]->outb) vsp -Xsram[1062] sram->in sram[1062]->out sram[1062]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1062]->out) 0 -.nodeset V(sram[1062]->outb) vsp -Xsram[1063] sram->in sram[1063]->out sram[1063]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1063]->out) 0 -.nodeset V(sram[1063]->outb) vsp -Xsram[1064] sram->in sram[1064]->out sram[1064]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1064]->out) 0 -.nodeset V(sram[1064]->outb) vsp -Xsram[1065] sram->in sram[1065]->out sram[1065]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1065]->out) 0 -.nodeset V(sram[1065]->outb) vsp -Xmux_2level_size50[26] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[4]->in[2] sram[1066]->outb sram[1066]->out sram[1067]->out sram[1067]->outb sram[1068]->out sram[1068]->outb sram[1069]->out sram[1069]->outb sram[1070]->out sram[1070]->outb sram[1071]->out sram[1071]->outb sram[1072]->out sram[1072]->outb sram[1073]->out sram[1073]->outb sram[1074]->outb sram[1074]->out sram[1075]->out sram[1075]->outb sram[1076]->out sram[1076]->outb sram[1077]->out sram[1077]->outb sram[1078]->out sram[1078]->outb sram[1079]->out sram[1079]->outb sram[1080]->out sram[1080]->outb sram[1081]->out sram[1081]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[26], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1066] sram->in sram[1066]->out sram[1066]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1066]->out) 0 -.nodeset V(sram[1066]->outb) vsp -Xsram[1067] sram->in sram[1067]->out sram[1067]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1067]->out) 0 -.nodeset V(sram[1067]->outb) vsp -Xsram[1068] sram->in sram[1068]->out sram[1068]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1068]->out) 0 -.nodeset V(sram[1068]->outb) vsp -Xsram[1069] sram->in sram[1069]->out sram[1069]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1069]->out) 0 -.nodeset V(sram[1069]->outb) vsp -Xsram[1070] sram->in sram[1070]->out sram[1070]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1070]->out) 0 -.nodeset V(sram[1070]->outb) vsp -Xsram[1071] sram->in sram[1071]->out sram[1071]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1071]->out) 0 -.nodeset V(sram[1071]->outb) vsp -Xsram[1072] sram->in sram[1072]->out sram[1072]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1072]->out) 0 -.nodeset V(sram[1072]->outb) vsp -Xsram[1073] sram->in sram[1073]->out sram[1073]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1073]->out) 0 -.nodeset V(sram[1073]->outb) vsp -Xsram[1074] sram->in sram[1074]->out sram[1074]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1074]->out) 0 -.nodeset V(sram[1074]->outb) vsp -Xsram[1075] sram->in sram[1075]->out sram[1075]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1075]->out) 0 -.nodeset V(sram[1075]->outb) vsp -Xsram[1076] sram->in sram[1076]->out sram[1076]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1076]->out) 0 -.nodeset V(sram[1076]->outb) vsp -Xsram[1077] sram->in sram[1077]->out sram[1077]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1077]->out) 0 -.nodeset V(sram[1077]->outb) vsp -Xsram[1078] sram->in sram[1078]->out sram[1078]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1078]->out) 0 -.nodeset V(sram[1078]->outb) vsp -Xsram[1079] sram->in sram[1079]->out sram[1079]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1079]->out) 0 -.nodeset V(sram[1079]->outb) vsp -Xsram[1080] sram->in sram[1080]->out sram[1080]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1080]->out) 0 -.nodeset V(sram[1080]->outb) vsp -Xsram[1081] sram->in sram[1081]->out sram[1081]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1081]->out) 0 -.nodeset V(sram[1081]->outb) vsp -Xmux_2level_size50[27] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[4]->in[3] sram[1082]->outb sram[1082]->out sram[1083]->out sram[1083]->outb sram[1084]->out sram[1084]->outb sram[1085]->out sram[1085]->outb sram[1086]->out sram[1086]->outb sram[1087]->out sram[1087]->outb sram[1088]->out sram[1088]->outb sram[1089]->out sram[1089]->outb sram[1090]->outb sram[1090]->out sram[1091]->out sram[1091]->outb sram[1092]->out sram[1092]->outb sram[1093]->out sram[1093]->outb sram[1094]->out sram[1094]->outb sram[1095]->out sram[1095]->outb sram[1096]->out sram[1096]->outb sram[1097]->out sram[1097]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[27], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1082] sram->in sram[1082]->out sram[1082]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1082]->out) 0 -.nodeset V(sram[1082]->outb) vsp -Xsram[1083] sram->in sram[1083]->out sram[1083]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1083]->out) 0 -.nodeset V(sram[1083]->outb) vsp -Xsram[1084] sram->in sram[1084]->out sram[1084]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1084]->out) 0 -.nodeset V(sram[1084]->outb) vsp -Xsram[1085] sram->in sram[1085]->out sram[1085]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1085]->out) 0 -.nodeset V(sram[1085]->outb) vsp -Xsram[1086] sram->in sram[1086]->out sram[1086]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1086]->out) 0 -.nodeset V(sram[1086]->outb) vsp -Xsram[1087] sram->in sram[1087]->out sram[1087]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1087]->out) 0 -.nodeset V(sram[1087]->outb) vsp -Xsram[1088] sram->in sram[1088]->out sram[1088]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1088]->out) 0 -.nodeset V(sram[1088]->outb) vsp -Xsram[1089] sram->in sram[1089]->out sram[1089]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1089]->out) 0 -.nodeset V(sram[1089]->outb) vsp -Xsram[1090] sram->in sram[1090]->out sram[1090]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1090]->out) 0 -.nodeset V(sram[1090]->outb) vsp -Xsram[1091] sram->in sram[1091]->out sram[1091]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1091]->out) 0 -.nodeset V(sram[1091]->outb) vsp -Xsram[1092] sram->in sram[1092]->out sram[1092]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1092]->out) 0 -.nodeset V(sram[1092]->outb) vsp -Xsram[1093] sram->in sram[1093]->out sram[1093]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1093]->out) 0 -.nodeset V(sram[1093]->outb) vsp -Xsram[1094] sram->in sram[1094]->out sram[1094]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1094]->out) 0 -.nodeset V(sram[1094]->outb) vsp -Xsram[1095] sram->in sram[1095]->out sram[1095]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1095]->out) 0 -.nodeset V(sram[1095]->outb) vsp -Xsram[1096] sram->in sram[1096]->out sram[1096]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1096]->out) 0 -.nodeset V(sram[1096]->outb) vsp -Xsram[1097] sram->in sram[1097]->out sram[1097]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1097]->out) 0 -.nodeset V(sram[1097]->outb) vsp -Xmux_2level_size50[28] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[4]->in[4] sram[1098]->outb sram[1098]->out sram[1099]->out sram[1099]->outb sram[1100]->out sram[1100]->outb sram[1101]->out sram[1101]->outb sram[1102]->out sram[1102]->outb sram[1103]->out sram[1103]->outb sram[1104]->out sram[1104]->outb sram[1105]->out sram[1105]->outb sram[1106]->outb sram[1106]->out sram[1107]->out sram[1107]->outb sram[1108]->out sram[1108]->outb sram[1109]->out sram[1109]->outb sram[1110]->out sram[1110]->outb sram[1111]->out sram[1111]->outb sram[1112]->out sram[1112]->outb sram[1113]->out sram[1113]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[28], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1098] sram->in sram[1098]->out sram[1098]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1098]->out) 0 -.nodeset V(sram[1098]->outb) vsp -Xsram[1099] sram->in sram[1099]->out sram[1099]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1099]->out) 0 -.nodeset V(sram[1099]->outb) vsp -Xsram[1100] sram->in sram[1100]->out sram[1100]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1100]->out) 0 -.nodeset V(sram[1100]->outb) vsp -Xsram[1101] sram->in sram[1101]->out sram[1101]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1101]->out) 0 -.nodeset V(sram[1101]->outb) vsp -Xsram[1102] sram->in sram[1102]->out sram[1102]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1102]->out) 0 -.nodeset V(sram[1102]->outb) vsp -Xsram[1103] sram->in sram[1103]->out sram[1103]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1103]->out) 0 -.nodeset V(sram[1103]->outb) vsp -Xsram[1104] sram->in sram[1104]->out sram[1104]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1104]->out) 0 -.nodeset V(sram[1104]->outb) vsp -Xsram[1105] sram->in sram[1105]->out sram[1105]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1105]->out) 0 -.nodeset V(sram[1105]->outb) vsp -Xsram[1106] sram->in sram[1106]->out sram[1106]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1106]->out) 0 -.nodeset V(sram[1106]->outb) vsp -Xsram[1107] sram->in sram[1107]->out sram[1107]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1107]->out) 0 -.nodeset V(sram[1107]->outb) vsp -Xsram[1108] sram->in sram[1108]->out sram[1108]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1108]->out) 0 -.nodeset V(sram[1108]->outb) vsp -Xsram[1109] sram->in sram[1109]->out sram[1109]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1109]->out) 0 -.nodeset V(sram[1109]->outb) vsp -Xsram[1110] sram->in sram[1110]->out sram[1110]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1110]->out) 0 -.nodeset V(sram[1110]->outb) vsp -Xsram[1111] sram->in sram[1111]->out sram[1111]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1111]->out) 0 -.nodeset V(sram[1111]->outb) vsp -Xsram[1112] sram->in sram[1112]->out sram[1112]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1112]->out) 0 -.nodeset V(sram[1112]->outb) vsp -Xsram[1113] sram->in sram[1113]->out sram[1113]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1113]->out) 0 -.nodeset V(sram[1113]->outb) vsp -Xmux_2level_size50[29] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[4]->in[5] sram[1114]->outb sram[1114]->out sram[1115]->out sram[1115]->outb sram[1116]->out sram[1116]->outb sram[1117]->out sram[1117]->outb sram[1118]->out sram[1118]->outb sram[1119]->out sram[1119]->outb sram[1120]->out sram[1120]->outb sram[1121]->out sram[1121]->outb sram[1122]->outb sram[1122]->out sram[1123]->out sram[1123]->outb sram[1124]->out sram[1124]->outb sram[1125]->out sram[1125]->outb sram[1126]->out sram[1126]->outb sram[1127]->out sram[1127]->outb sram[1128]->out sram[1128]->outb sram[1129]->out sram[1129]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[29], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1114] sram->in sram[1114]->out sram[1114]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1114]->out) 0 -.nodeset V(sram[1114]->outb) vsp -Xsram[1115] sram->in sram[1115]->out sram[1115]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1115]->out) 0 -.nodeset V(sram[1115]->outb) vsp -Xsram[1116] sram->in sram[1116]->out sram[1116]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1116]->out) 0 -.nodeset V(sram[1116]->outb) vsp -Xsram[1117] sram->in sram[1117]->out sram[1117]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1117]->out) 0 -.nodeset V(sram[1117]->outb) vsp -Xsram[1118] sram->in sram[1118]->out sram[1118]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1118]->out) 0 -.nodeset V(sram[1118]->outb) vsp -Xsram[1119] sram->in sram[1119]->out sram[1119]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1119]->out) 0 -.nodeset V(sram[1119]->outb) vsp -Xsram[1120] sram->in sram[1120]->out sram[1120]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1120]->out) 0 -.nodeset V(sram[1120]->outb) vsp -Xsram[1121] sram->in sram[1121]->out sram[1121]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1121]->out) 0 -.nodeset V(sram[1121]->outb) vsp -Xsram[1122] sram->in sram[1122]->out sram[1122]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1122]->out) 0 -.nodeset V(sram[1122]->outb) vsp -Xsram[1123] sram->in sram[1123]->out sram[1123]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1123]->out) 0 -.nodeset V(sram[1123]->outb) vsp -Xsram[1124] sram->in sram[1124]->out sram[1124]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1124]->out) 0 -.nodeset V(sram[1124]->outb) vsp -Xsram[1125] sram->in sram[1125]->out sram[1125]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1125]->out) 0 -.nodeset V(sram[1125]->outb) vsp -Xsram[1126] sram->in sram[1126]->out sram[1126]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1126]->out) 0 -.nodeset V(sram[1126]->outb) vsp -Xsram[1127] sram->in sram[1127]->out sram[1127]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1127]->out) 0 -.nodeset V(sram[1127]->outb) vsp -Xsram[1128] sram->in sram[1128]->out sram[1128]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1128]->out) 0 -.nodeset V(sram[1128]->outb) vsp -Xsram[1129] sram->in sram[1129]->out sram[1129]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1129]->out) 0 -.nodeset V(sram[1129]->outb) vsp -Xdirect_interc[174] mode[clb]->clk[0] fle[4]->clk[0] gvdd_local_interc sgnd direct_interc -Xmux_2level_size50[30] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[5]->in[0] sram[1130]->outb sram[1130]->out sram[1131]->out sram[1131]->outb sram[1132]->out sram[1132]->outb sram[1133]->out sram[1133]->outb sram[1134]->out sram[1134]->outb sram[1135]->out sram[1135]->outb sram[1136]->out sram[1136]->outb sram[1137]->out sram[1137]->outb sram[1138]->outb sram[1138]->out sram[1139]->out sram[1139]->outb sram[1140]->out sram[1140]->outb sram[1141]->out sram[1141]->outb sram[1142]->out sram[1142]->outb sram[1143]->out sram[1143]->outb sram[1144]->out sram[1144]->outb sram[1145]->out sram[1145]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[30], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1130] sram->in sram[1130]->out sram[1130]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1130]->out) 0 -.nodeset V(sram[1130]->outb) vsp -Xsram[1131] sram->in sram[1131]->out sram[1131]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1131]->out) 0 -.nodeset V(sram[1131]->outb) vsp -Xsram[1132] sram->in sram[1132]->out sram[1132]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1132]->out) 0 -.nodeset V(sram[1132]->outb) vsp -Xsram[1133] sram->in sram[1133]->out sram[1133]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1133]->out) 0 -.nodeset V(sram[1133]->outb) vsp -Xsram[1134] sram->in sram[1134]->out sram[1134]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1134]->out) 0 -.nodeset V(sram[1134]->outb) vsp -Xsram[1135] sram->in sram[1135]->out sram[1135]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1135]->out) 0 -.nodeset V(sram[1135]->outb) vsp -Xsram[1136] sram->in sram[1136]->out sram[1136]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1136]->out) 0 -.nodeset V(sram[1136]->outb) vsp -Xsram[1137] sram->in sram[1137]->out sram[1137]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1137]->out) 0 -.nodeset V(sram[1137]->outb) vsp -Xsram[1138] sram->in sram[1138]->out sram[1138]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1138]->out) 0 -.nodeset V(sram[1138]->outb) vsp -Xsram[1139] sram->in sram[1139]->out sram[1139]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1139]->out) 0 -.nodeset V(sram[1139]->outb) vsp -Xsram[1140] sram->in sram[1140]->out sram[1140]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1140]->out) 0 -.nodeset V(sram[1140]->outb) vsp -Xsram[1141] sram->in sram[1141]->out sram[1141]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1141]->out) 0 -.nodeset V(sram[1141]->outb) vsp -Xsram[1142] sram->in sram[1142]->out sram[1142]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1142]->out) 0 -.nodeset V(sram[1142]->outb) vsp -Xsram[1143] sram->in sram[1143]->out sram[1143]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1143]->out) 0 -.nodeset V(sram[1143]->outb) vsp -Xsram[1144] sram->in sram[1144]->out sram[1144]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1144]->out) 0 -.nodeset V(sram[1144]->outb) vsp -Xsram[1145] sram->in sram[1145]->out sram[1145]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1145]->out) 0 -.nodeset V(sram[1145]->outb) vsp -Xmux_2level_size50[31] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[5]->in[1] sram[1146]->outb sram[1146]->out sram[1147]->out sram[1147]->outb sram[1148]->out sram[1148]->outb sram[1149]->out sram[1149]->outb sram[1150]->out sram[1150]->outb sram[1151]->out sram[1151]->outb sram[1152]->out sram[1152]->outb sram[1153]->out sram[1153]->outb sram[1154]->outb sram[1154]->out sram[1155]->out sram[1155]->outb sram[1156]->out sram[1156]->outb sram[1157]->out sram[1157]->outb sram[1158]->out sram[1158]->outb sram[1159]->out sram[1159]->outb sram[1160]->out sram[1160]->outb sram[1161]->out sram[1161]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[31], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1146] sram->in sram[1146]->out sram[1146]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1146]->out) 0 -.nodeset V(sram[1146]->outb) vsp -Xsram[1147] sram->in sram[1147]->out sram[1147]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1147]->out) 0 -.nodeset V(sram[1147]->outb) vsp -Xsram[1148] sram->in sram[1148]->out sram[1148]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1148]->out) 0 -.nodeset V(sram[1148]->outb) vsp -Xsram[1149] sram->in sram[1149]->out sram[1149]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1149]->out) 0 -.nodeset V(sram[1149]->outb) vsp -Xsram[1150] sram->in sram[1150]->out sram[1150]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1150]->out) 0 -.nodeset V(sram[1150]->outb) vsp -Xsram[1151] sram->in sram[1151]->out sram[1151]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1151]->out) 0 -.nodeset V(sram[1151]->outb) vsp -Xsram[1152] sram->in sram[1152]->out sram[1152]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1152]->out) 0 -.nodeset V(sram[1152]->outb) vsp -Xsram[1153] sram->in sram[1153]->out sram[1153]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1153]->out) 0 -.nodeset V(sram[1153]->outb) vsp -Xsram[1154] sram->in sram[1154]->out sram[1154]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1154]->out) 0 -.nodeset V(sram[1154]->outb) vsp -Xsram[1155] sram->in sram[1155]->out sram[1155]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1155]->out) 0 -.nodeset V(sram[1155]->outb) vsp -Xsram[1156] sram->in sram[1156]->out sram[1156]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1156]->out) 0 -.nodeset V(sram[1156]->outb) vsp -Xsram[1157] sram->in sram[1157]->out sram[1157]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1157]->out) 0 -.nodeset V(sram[1157]->outb) vsp -Xsram[1158] sram->in sram[1158]->out sram[1158]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1158]->out) 0 -.nodeset V(sram[1158]->outb) vsp -Xsram[1159] sram->in sram[1159]->out sram[1159]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1159]->out) 0 -.nodeset V(sram[1159]->outb) vsp -Xsram[1160] sram->in sram[1160]->out sram[1160]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1160]->out) 0 -.nodeset V(sram[1160]->outb) vsp -Xsram[1161] sram->in sram[1161]->out sram[1161]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1161]->out) 0 -.nodeset V(sram[1161]->outb) vsp -Xmux_2level_size50[32] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[5]->in[2] sram[1162]->outb sram[1162]->out sram[1163]->out sram[1163]->outb sram[1164]->out sram[1164]->outb sram[1165]->out sram[1165]->outb sram[1166]->out sram[1166]->outb sram[1167]->out sram[1167]->outb sram[1168]->out sram[1168]->outb sram[1169]->out sram[1169]->outb sram[1170]->outb sram[1170]->out sram[1171]->out sram[1171]->outb sram[1172]->out sram[1172]->outb sram[1173]->out sram[1173]->outb sram[1174]->out sram[1174]->outb sram[1175]->out sram[1175]->outb sram[1176]->out sram[1176]->outb sram[1177]->out sram[1177]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[32], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1162] sram->in sram[1162]->out sram[1162]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1162]->out) 0 -.nodeset V(sram[1162]->outb) vsp -Xsram[1163] sram->in sram[1163]->out sram[1163]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1163]->out) 0 -.nodeset V(sram[1163]->outb) vsp -Xsram[1164] sram->in sram[1164]->out sram[1164]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1164]->out) 0 -.nodeset V(sram[1164]->outb) vsp -Xsram[1165] sram->in sram[1165]->out sram[1165]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1165]->out) 0 -.nodeset V(sram[1165]->outb) vsp -Xsram[1166] sram->in sram[1166]->out sram[1166]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1166]->out) 0 -.nodeset V(sram[1166]->outb) vsp -Xsram[1167] sram->in sram[1167]->out sram[1167]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1167]->out) 0 -.nodeset V(sram[1167]->outb) vsp -Xsram[1168] sram->in sram[1168]->out sram[1168]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1168]->out) 0 -.nodeset V(sram[1168]->outb) vsp -Xsram[1169] sram->in sram[1169]->out sram[1169]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1169]->out) 0 -.nodeset V(sram[1169]->outb) vsp -Xsram[1170] sram->in sram[1170]->out sram[1170]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1170]->out) 0 -.nodeset V(sram[1170]->outb) vsp -Xsram[1171] sram->in sram[1171]->out sram[1171]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1171]->out) 0 -.nodeset V(sram[1171]->outb) vsp -Xsram[1172] sram->in sram[1172]->out sram[1172]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1172]->out) 0 -.nodeset V(sram[1172]->outb) vsp -Xsram[1173] sram->in sram[1173]->out sram[1173]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1173]->out) 0 -.nodeset V(sram[1173]->outb) vsp -Xsram[1174] sram->in sram[1174]->out sram[1174]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1174]->out) 0 -.nodeset V(sram[1174]->outb) vsp -Xsram[1175] sram->in sram[1175]->out sram[1175]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1175]->out) 0 -.nodeset V(sram[1175]->outb) vsp -Xsram[1176] sram->in sram[1176]->out sram[1176]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1176]->out) 0 -.nodeset V(sram[1176]->outb) vsp -Xsram[1177] sram->in sram[1177]->out sram[1177]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1177]->out) 0 -.nodeset V(sram[1177]->outb) vsp -Xmux_2level_size50[33] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[5]->in[3] sram[1178]->outb sram[1178]->out sram[1179]->out sram[1179]->outb sram[1180]->out sram[1180]->outb sram[1181]->out sram[1181]->outb sram[1182]->out sram[1182]->outb sram[1183]->out sram[1183]->outb sram[1184]->out sram[1184]->outb sram[1185]->out sram[1185]->outb sram[1186]->outb sram[1186]->out sram[1187]->out sram[1187]->outb sram[1188]->out sram[1188]->outb sram[1189]->out sram[1189]->outb sram[1190]->out sram[1190]->outb sram[1191]->out sram[1191]->outb sram[1192]->out sram[1192]->outb sram[1193]->out sram[1193]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[33], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1178] sram->in sram[1178]->out sram[1178]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1178]->out) 0 -.nodeset V(sram[1178]->outb) vsp -Xsram[1179] sram->in sram[1179]->out sram[1179]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1179]->out) 0 -.nodeset V(sram[1179]->outb) vsp -Xsram[1180] sram->in sram[1180]->out sram[1180]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1180]->out) 0 -.nodeset V(sram[1180]->outb) vsp -Xsram[1181] sram->in sram[1181]->out sram[1181]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1181]->out) 0 -.nodeset V(sram[1181]->outb) vsp -Xsram[1182] sram->in sram[1182]->out sram[1182]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1182]->out) 0 -.nodeset V(sram[1182]->outb) vsp -Xsram[1183] sram->in sram[1183]->out sram[1183]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1183]->out) 0 -.nodeset V(sram[1183]->outb) vsp -Xsram[1184] sram->in sram[1184]->out sram[1184]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1184]->out) 0 -.nodeset V(sram[1184]->outb) vsp -Xsram[1185] sram->in sram[1185]->out sram[1185]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1185]->out) 0 -.nodeset V(sram[1185]->outb) vsp -Xsram[1186] sram->in sram[1186]->out sram[1186]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1186]->out) 0 -.nodeset V(sram[1186]->outb) vsp -Xsram[1187] sram->in sram[1187]->out sram[1187]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1187]->out) 0 -.nodeset V(sram[1187]->outb) vsp -Xsram[1188] sram->in sram[1188]->out sram[1188]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1188]->out) 0 -.nodeset V(sram[1188]->outb) vsp -Xsram[1189] sram->in sram[1189]->out sram[1189]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1189]->out) 0 -.nodeset V(sram[1189]->outb) vsp -Xsram[1190] sram->in sram[1190]->out sram[1190]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1190]->out) 0 -.nodeset V(sram[1190]->outb) vsp -Xsram[1191] sram->in sram[1191]->out sram[1191]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1191]->out) 0 -.nodeset V(sram[1191]->outb) vsp -Xsram[1192] sram->in sram[1192]->out sram[1192]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1192]->out) 0 -.nodeset V(sram[1192]->outb) vsp -Xsram[1193] sram->in sram[1193]->out sram[1193]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1193]->out) 0 -.nodeset V(sram[1193]->outb) vsp -Xmux_2level_size50[34] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[5]->in[4] sram[1194]->outb sram[1194]->out sram[1195]->out sram[1195]->outb sram[1196]->out sram[1196]->outb sram[1197]->out sram[1197]->outb sram[1198]->out sram[1198]->outb sram[1199]->out sram[1199]->outb sram[1200]->out sram[1200]->outb sram[1201]->out sram[1201]->outb sram[1202]->outb sram[1202]->out sram[1203]->out sram[1203]->outb sram[1204]->out sram[1204]->outb sram[1205]->out sram[1205]->outb sram[1206]->out sram[1206]->outb sram[1207]->out sram[1207]->outb sram[1208]->out sram[1208]->outb sram[1209]->out sram[1209]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[34], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1194] sram->in sram[1194]->out sram[1194]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1194]->out) 0 -.nodeset V(sram[1194]->outb) vsp -Xsram[1195] sram->in sram[1195]->out sram[1195]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1195]->out) 0 -.nodeset V(sram[1195]->outb) vsp -Xsram[1196] sram->in sram[1196]->out sram[1196]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1196]->out) 0 -.nodeset V(sram[1196]->outb) vsp -Xsram[1197] sram->in sram[1197]->out sram[1197]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1197]->out) 0 -.nodeset V(sram[1197]->outb) vsp -Xsram[1198] sram->in sram[1198]->out sram[1198]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1198]->out) 0 -.nodeset V(sram[1198]->outb) vsp -Xsram[1199] sram->in sram[1199]->out sram[1199]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1199]->out) 0 -.nodeset V(sram[1199]->outb) vsp -Xsram[1200] sram->in sram[1200]->out sram[1200]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1200]->out) 0 -.nodeset V(sram[1200]->outb) vsp -Xsram[1201] sram->in sram[1201]->out sram[1201]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1201]->out) 0 -.nodeset V(sram[1201]->outb) vsp -Xsram[1202] sram->in sram[1202]->out sram[1202]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1202]->out) 0 -.nodeset V(sram[1202]->outb) vsp -Xsram[1203] sram->in sram[1203]->out sram[1203]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1203]->out) 0 -.nodeset V(sram[1203]->outb) vsp -Xsram[1204] sram->in sram[1204]->out sram[1204]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1204]->out) 0 -.nodeset V(sram[1204]->outb) vsp -Xsram[1205] sram->in sram[1205]->out sram[1205]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1205]->out) 0 -.nodeset V(sram[1205]->outb) vsp -Xsram[1206] sram->in sram[1206]->out sram[1206]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1206]->out) 0 -.nodeset V(sram[1206]->outb) vsp -Xsram[1207] sram->in sram[1207]->out sram[1207]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1207]->out) 0 -.nodeset V(sram[1207]->outb) vsp -Xsram[1208] sram->in sram[1208]->out sram[1208]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1208]->out) 0 -.nodeset V(sram[1208]->outb) vsp -Xsram[1209] sram->in sram[1209]->out sram[1209]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1209]->out) 0 -.nodeset V(sram[1209]->outb) vsp -Xmux_2level_size50[35] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[5]->in[5] sram[1210]->outb sram[1210]->out sram[1211]->out sram[1211]->outb sram[1212]->out sram[1212]->outb sram[1213]->out sram[1213]->outb sram[1214]->out sram[1214]->outb sram[1215]->out sram[1215]->outb sram[1216]->out sram[1216]->outb sram[1217]->out sram[1217]->outb sram[1218]->outb sram[1218]->out sram[1219]->out sram[1219]->outb sram[1220]->out sram[1220]->outb sram[1221]->out sram[1221]->outb sram[1222]->out sram[1222]->outb sram[1223]->out sram[1223]->outb sram[1224]->out sram[1224]->outb sram[1225]->out sram[1225]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[35], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1210] sram->in sram[1210]->out sram[1210]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1210]->out) 0 -.nodeset V(sram[1210]->outb) vsp -Xsram[1211] sram->in sram[1211]->out sram[1211]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1211]->out) 0 -.nodeset V(sram[1211]->outb) vsp -Xsram[1212] sram->in sram[1212]->out sram[1212]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1212]->out) 0 -.nodeset V(sram[1212]->outb) vsp -Xsram[1213] sram->in sram[1213]->out sram[1213]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1213]->out) 0 -.nodeset V(sram[1213]->outb) vsp -Xsram[1214] sram->in sram[1214]->out sram[1214]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1214]->out) 0 -.nodeset V(sram[1214]->outb) vsp -Xsram[1215] sram->in sram[1215]->out sram[1215]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1215]->out) 0 -.nodeset V(sram[1215]->outb) vsp -Xsram[1216] sram->in sram[1216]->out sram[1216]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1216]->out) 0 -.nodeset V(sram[1216]->outb) vsp -Xsram[1217] sram->in sram[1217]->out sram[1217]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1217]->out) 0 -.nodeset V(sram[1217]->outb) vsp -Xsram[1218] sram->in sram[1218]->out sram[1218]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1218]->out) 0 -.nodeset V(sram[1218]->outb) vsp -Xsram[1219] sram->in sram[1219]->out sram[1219]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1219]->out) 0 -.nodeset V(sram[1219]->outb) vsp -Xsram[1220] sram->in sram[1220]->out sram[1220]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1220]->out) 0 -.nodeset V(sram[1220]->outb) vsp -Xsram[1221] sram->in sram[1221]->out sram[1221]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1221]->out) 0 -.nodeset V(sram[1221]->outb) vsp -Xsram[1222] sram->in sram[1222]->out sram[1222]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1222]->out) 0 -.nodeset V(sram[1222]->outb) vsp -Xsram[1223] sram->in sram[1223]->out sram[1223]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1223]->out) 0 -.nodeset V(sram[1223]->outb) vsp -Xsram[1224] sram->in sram[1224]->out sram[1224]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1224]->out) 0 -.nodeset V(sram[1224]->outb) vsp -Xsram[1225] sram->in sram[1225]->out sram[1225]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1225]->out) 0 -.nodeset V(sram[1225]->outb) vsp -Xdirect_interc[175] mode[clb]->clk[0] fle[5]->clk[0] gvdd_local_interc sgnd direct_interc -Xmux_2level_size50[36] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[6]->in[0] sram[1226]->outb sram[1226]->out sram[1227]->out sram[1227]->outb sram[1228]->out sram[1228]->outb sram[1229]->out sram[1229]->outb sram[1230]->out sram[1230]->outb sram[1231]->out sram[1231]->outb sram[1232]->out sram[1232]->outb sram[1233]->out sram[1233]->outb sram[1234]->outb sram[1234]->out sram[1235]->out sram[1235]->outb sram[1236]->out sram[1236]->outb sram[1237]->out sram[1237]->outb sram[1238]->out sram[1238]->outb sram[1239]->out sram[1239]->outb sram[1240]->out sram[1240]->outb sram[1241]->out sram[1241]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[36], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1226] sram->in sram[1226]->out sram[1226]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1226]->out) 0 -.nodeset V(sram[1226]->outb) vsp -Xsram[1227] sram->in sram[1227]->out sram[1227]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1227]->out) 0 -.nodeset V(sram[1227]->outb) vsp -Xsram[1228] sram->in sram[1228]->out sram[1228]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1228]->out) 0 -.nodeset V(sram[1228]->outb) vsp -Xsram[1229] sram->in sram[1229]->out sram[1229]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1229]->out) 0 -.nodeset V(sram[1229]->outb) vsp -Xsram[1230] sram->in sram[1230]->out sram[1230]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1230]->out) 0 -.nodeset V(sram[1230]->outb) vsp -Xsram[1231] sram->in sram[1231]->out sram[1231]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1231]->out) 0 -.nodeset V(sram[1231]->outb) vsp -Xsram[1232] sram->in sram[1232]->out sram[1232]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1232]->out) 0 -.nodeset V(sram[1232]->outb) vsp -Xsram[1233] sram->in sram[1233]->out sram[1233]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1233]->out) 0 -.nodeset V(sram[1233]->outb) vsp -Xsram[1234] sram->in sram[1234]->out sram[1234]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1234]->out) 0 -.nodeset V(sram[1234]->outb) vsp -Xsram[1235] sram->in sram[1235]->out sram[1235]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1235]->out) 0 -.nodeset V(sram[1235]->outb) vsp -Xsram[1236] sram->in sram[1236]->out sram[1236]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1236]->out) 0 -.nodeset V(sram[1236]->outb) vsp -Xsram[1237] sram->in sram[1237]->out sram[1237]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1237]->out) 0 -.nodeset V(sram[1237]->outb) vsp -Xsram[1238] sram->in sram[1238]->out sram[1238]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1238]->out) 0 -.nodeset V(sram[1238]->outb) vsp -Xsram[1239] sram->in sram[1239]->out sram[1239]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1239]->out) 0 -.nodeset V(sram[1239]->outb) vsp -Xsram[1240] sram->in sram[1240]->out sram[1240]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1240]->out) 0 -.nodeset V(sram[1240]->outb) vsp -Xsram[1241] sram->in sram[1241]->out sram[1241]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1241]->out) 0 -.nodeset V(sram[1241]->outb) vsp -Xmux_2level_size50[37] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[6]->in[1] sram[1242]->outb sram[1242]->out sram[1243]->out sram[1243]->outb sram[1244]->out sram[1244]->outb sram[1245]->out sram[1245]->outb sram[1246]->out sram[1246]->outb sram[1247]->out sram[1247]->outb sram[1248]->out sram[1248]->outb sram[1249]->out sram[1249]->outb sram[1250]->outb sram[1250]->out sram[1251]->out sram[1251]->outb sram[1252]->out sram[1252]->outb sram[1253]->out sram[1253]->outb sram[1254]->out sram[1254]->outb sram[1255]->out sram[1255]->outb sram[1256]->out sram[1256]->outb sram[1257]->out sram[1257]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[37], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1242] sram->in sram[1242]->out sram[1242]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1242]->out) 0 -.nodeset V(sram[1242]->outb) vsp -Xsram[1243] sram->in sram[1243]->out sram[1243]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1243]->out) 0 -.nodeset V(sram[1243]->outb) vsp -Xsram[1244] sram->in sram[1244]->out sram[1244]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1244]->out) 0 -.nodeset V(sram[1244]->outb) vsp -Xsram[1245] sram->in sram[1245]->out sram[1245]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1245]->out) 0 -.nodeset V(sram[1245]->outb) vsp -Xsram[1246] sram->in sram[1246]->out sram[1246]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1246]->out) 0 -.nodeset V(sram[1246]->outb) vsp -Xsram[1247] sram->in sram[1247]->out sram[1247]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1247]->out) 0 -.nodeset V(sram[1247]->outb) vsp -Xsram[1248] sram->in sram[1248]->out sram[1248]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1248]->out) 0 -.nodeset V(sram[1248]->outb) vsp -Xsram[1249] sram->in sram[1249]->out sram[1249]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1249]->out) 0 -.nodeset V(sram[1249]->outb) vsp -Xsram[1250] sram->in sram[1250]->out sram[1250]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1250]->out) 0 -.nodeset V(sram[1250]->outb) vsp -Xsram[1251] sram->in sram[1251]->out sram[1251]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1251]->out) 0 -.nodeset V(sram[1251]->outb) vsp -Xsram[1252] sram->in sram[1252]->out sram[1252]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1252]->out) 0 -.nodeset V(sram[1252]->outb) vsp -Xsram[1253] sram->in sram[1253]->out sram[1253]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1253]->out) 0 -.nodeset V(sram[1253]->outb) vsp -Xsram[1254] sram->in sram[1254]->out sram[1254]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1254]->out) 0 -.nodeset V(sram[1254]->outb) vsp -Xsram[1255] sram->in sram[1255]->out sram[1255]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1255]->out) 0 -.nodeset V(sram[1255]->outb) vsp -Xsram[1256] sram->in sram[1256]->out sram[1256]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1256]->out) 0 -.nodeset V(sram[1256]->outb) vsp -Xsram[1257] sram->in sram[1257]->out sram[1257]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1257]->out) 0 -.nodeset V(sram[1257]->outb) vsp -Xmux_2level_size50[38] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[6]->in[2] sram[1258]->outb sram[1258]->out sram[1259]->out sram[1259]->outb sram[1260]->out sram[1260]->outb sram[1261]->out sram[1261]->outb sram[1262]->out sram[1262]->outb sram[1263]->out sram[1263]->outb sram[1264]->out sram[1264]->outb sram[1265]->out sram[1265]->outb sram[1266]->outb sram[1266]->out sram[1267]->out sram[1267]->outb sram[1268]->out sram[1268]->outb sram[1269]->out sram[1269]->outb sram[1270]->out sram[1270]->outb sram[1271]->out sram[1271]->outb sram[1272]->out sram[1272]->outb sram[1273]->out sram[1273]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[38], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1258] sram->in sram[1258]->out sram[1258]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1258]->out) 0 -.nodeset V(sram[1258]->outb) vsp -Xsram[1259] sram->in sram[1259]->out sram[1259]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1259]->out) 0 -.nodeset V(sram[1259]->outb) vsp -Xsram[1260] sram->in sram[1260]->out sram[1260]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1260]->out) 0 -.nodeset V(sram[1260]->outb) vsp -Xsram[1261] sram->in sram[1261]->out sram[1261]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1261]->out) 0 -.nodeset V(sram[1261]->outb) vsp -Xsram[1262] sram->in sram[1262]->out sram[1262]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1262]->out) 0 -.nodeset V(sram[1262]->outb) vsp -Xsram[1263] sram->in sram[1263]->out sram[1263]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1263]->out) 0 -.nodeset V(sram[1263]->outb) vsp -Xsram[1264] sram->in sram[1264]->out sram[1264]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1264]->out) 0 -.nodeset V(sram[1264]->outb) vsp -Xsram[1265] sram->in sram[1265]->out sram[1265]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1265]->out) 0 -.nodeset V(sram[1265]->outb) vsp -Xsram[1266] sram->in sram[1266]->out sram[1266]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1266]->out) 0 -.nodeset V(sram[1266]->outb) vsp -Xsram[1267] sram->in sram[1267]->out sram[1267]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1267]->out) 0 -.nodeset V(sram[1267]->outb) vsp -Xsram[1268] sram->in sram[1268]->out sram[1268]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1268]->out) 0 -.nodeset V(sram[1268]->outb) vsp -Xsram[1269] sram->in sram[1269]->out sram[1269]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1269]->out) 0 -.nodeset V(sram[1269]->outb) vsp -Xsram[1270] sram->in sram[1270]->out sram[1270]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1270]->out) 0 -.nodeset V(sram[1270]->outb) vsp -Xsram[1271] sram->in sram[1271]->out sram[1271]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1271]->out) 0 -.nodeset V(sram[1271]->outb) vsp -Xsram[1272] sram->in sram[1272]->out sram[1272]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1272]->out) 0 -.nodeset V(sram[1272]->outb) vsp -Xsram[1273] sram->in sram[1273]->out sram[1273]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1273]->out) 0 -.nodeset V(sram[1273]->outb) vsp -Xmux_2level_size50[39] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[6]->in[3] sram[1274]->outb sram[1274]->out sram[1275]->out sram[1275]->outb sram[1276]->out sram[1276]->outb sram[1277]->out sram[1277]->outb sram[1278]->out sram[1278]->outb sram[1279]->out sram[1279]->outb sram[1280]->out sram[1280]->outb sram[1281]->out sram[1281]->outb sram[1282]->outb sram[1282]->out sram[1283]->out sram[1283]->outb sram[1284]->out sram[1284]->outb sram[1285]->out sram[1285]->outb sram[1286]->out sram[1286]->outb sram[1287]->out sram[1287]->outb sram[1288]->out sram[1288]->outb sram[1289]->out sram[1289]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[39], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1274] sram->in sram[1274]->out sram[1274]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1274]->out) 0 -.nodeset V(sram[1274]->outb) vsp -Xsram[1275] sram->in sram[1275]->out sram[1275]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1275]->out) 0 -.nodeset V(sram[1275]->outb) vsp -Xsram[1276] sram->in sram[1276]->out sram[1276]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1276]->out) 0 -.nodeset V(sram[1276]->outb) vsp -Xsram[1277] sram->in sram[1277]->out sram[1277]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1277]->out) 0 -.nodeset V(sram[1277]->outb) vsp -Xsram[1278] sram->in sram[1278]->out sram[1278]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1278]->out) 0 -.nodeset V(sram[1278]->outb) vsp -Xsram[1279] sram->in sram[1279]->out sram[1279]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1279]->out) 0 -.nodeset V(sram[1279]->outb) vsp -Xsram[1280] sram->in sram[1280]->out sram[1280]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1280]->out) 0 -.nodeset V(sram[1280]->outb) vsp -Xsram[1281] sram->in sram[1281]->out sram[1281]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1281]->out) 0 -.nodeset V(sram[1281]->outb) vsp -Xsram[1282] sram->in sram[1282]->out sram[1282]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1282]->out) 0 -.nodeset V(sram[1282]->outb) vsp -Xsram[1283] sram->in sram[1283]->out sram[1283]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1283]->out) 0 -.nodeset V(sram[1283]->outb) vsp -Xsram[1284] sram->in sram[1284]->out sram[1284]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1284]->out) 0 -.nodeset V(sram[1284]->outb) vsp -Xsram[1285] sram->in sram[1285]->out sram[1285]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1285]->out) 0 -.nodeset V(sram[1285]->outb) vsp -Xsram[1286] sram->in sram[1286]->out sram[1286]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1286]->out) 0 -.nodeset V(sram[1286]->outb) vsp -Xsram[1287] sram->in sram[1287]->out sram[1287]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1287]->out) 0 -.nodeset V(sram[1287]->outb) vsp -Xsram[1288] sram->in sram[1288]->out sram[1288]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1288]->out) 0 -.nodeset V(sram[1288]->outb) vsp -Xsram[1289] sram->in sram[1289]->out sram[1289]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1289]->out) 0 -.nodeset V(sram[1289]->outb) vsp -Xmux_2level_size50[40] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[6]->in[4] sram[1290]->outb sram[1290]->out sram[1291]->out sram[1291]->outb sram[1292]->out sram[1292]->outb sram[1293]->out sram[1293]->outb sram[1294]->out sram[1294]->outb sram[1295]->out sram[1295]->outb sram[1296]->out sram[1296]->outb sram[1297]->out sram[1297]->outb sram[1298]->outb sram[1298]->out sram[1299]->out sram[1299]->outb sram[1300]->out sram[1300]->outb sram[1301]->out sram[1301]->outb sram[1302]->out sram[1302]->outb sram[1303]->out sram[1303]->outb sram[1304]->out sram[1304]->outb sram[1305]->out sram[1305]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[40], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1290] sram->in sram[1290]->out sram[1290]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1290]->out) 0 -.nodeset V(sram[1290]->outb) vsp -Xsram[1291] sram->in sram[1291]->out sram[1291]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1291]->out) 0 -.nodeset V(sram[1291]->outb) vsp -Xsram[1292] sram->in sram[1292]->out sram[1292]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1292]->out) 0 -.nodeset V(sram[1292]->outb) vsp -Xsram[1293] sram->in sram[1293]->out sram[1293]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1293]->out) 0 -.nodeset V(sram[1293]->outb) vsp -Xsram[1294] sram->in sram[1294]->out sram[1294]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1294]->out) 0 -.nodeset V(sram[1294]->outb) vsp -Xsram[1295] sram->in sram[1295]->out sram[1295]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1295]->out) 0 -.nodeset V(sram[1295]->outb) vsp -Xsram[1296] sram->in sram[1296]->out sram[1296]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1296]->out) 0 -.nodeset V(sram[1296]->outb) vsp -Xsram[1297] sram->in sram[1297]->out sram[1297]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1297]->out) 0 -.nodeset V(sram[1297]->outb) vsp -Xsram[1298] sram->in sram[1298]->out sram[1298]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1298]->out) 0 -.nodeset V(sram[1298]->outb) vsp -Xsram[1299] sram->in sram[1299]->out sram[1299]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1299]->out) 0 -.nodeset V(sram[1299]->outb) vsp -Xsram[1300] sram->in sram[1300]->out sram[1300]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1300]->out) 0 -.nodeset V(sram[1300]->outb) vsp -Xsram[1301] sram->in sram[1301]->out sram[1301]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1301]->out) 0 -.nodeset V(sram[1301]->outb) vsp -Xsram[1302] sram->in sram[1302]->out sram[1302]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1302]->out) 0 -.nodeset V(sram[1302]->outb) vsp -Xsram[1303] sram->in sram[1303]->out sram[1303]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1303]->out) 0 -.nodeset V(sram[1303]->outb) vsp -Xsram[1304] sram->in sram[1304]->out sram[1304]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1304]->out) 0 -.nodeset V(sram[1304]->outb) vsp -Xsram[1305] sram->in sram[1305]->out sram[1305]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1305]->out) 0 -.nodeset V(sram[1305]->outb) vsp -Xmux_2level_size50[41] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[6]->in[5] sram[1306]->outb sram[1306]->out sram[1307]->out sram[1307]->outb sram[1308]->out sram[1308]->outb sram[1309]->out sram[1309]->outb sram[1310]->out sram[1310]->outb sram[1311]->out sram[1311]->outb sram[1312]->out sram[1312]->outb sram[1313]->out sram[1313]->outb sram[1314]->outb sram[1314]->out sram[1315]->out sram[1315]->outb sram[1316]->out sram[1316]->outb sram[1317]->out sram[1317]->outb sram[1318]->out sram[1318]->outb sram[1319]->out sram[1319]->outb sram[1320]->out sram[1320]->outb sram[1321]->out sram[1321]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[41], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1306] sram->in sram[1306]->out sram[1306]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1306]->out) 0 -.nodeset V(sram[1306]->outb) vsp -Xsram[1307] sram->in sram[1307]->out sram[1307]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1307]->out) 0 -.nodeset V(sram[1307]->outb) vsp -Xsram[1308] sram->in sram[1308]->out sram[1308]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1308]->out) 0 -.nodeset V(sram[1308]->outb) vsp -Xsram[1309] sram->in sram[1309]->out sram[1309]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1309]->out) 0 -.nodeset V(sram[1309]->outb) vsp -Xsram[1310] sram->in sram[1310]->out sram[1310]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1310]->out) 0 -.nodeset V(sram[1310]->outb) vsp -Xsram[1311] sram->in sram[1311]->out sram[1311]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1311]->out) 0 -.nodeset V(sram[1311]->outb) vsp -Xsram[1312] sram->in sram[1312]->out sram[1312]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1312]->out) 0 -.nodeset V(sram[1312]->outb) vsp -Xsram[1313] sram->in sram[1313]->out sram[1313]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1313]->out) 0 -.nodeset V(sram[1313]->outb) vsp -Xsram[1314] sram->in sram[1314]->out sram[1314]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1314]->out) 0 -.nodeset V(sram[1314]->outb) vsp -Xsram[1315] sram->in sram[1315]->out sram[1315]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1315]->out) 0 -.nodeset V(sram[1315]->outb) vsp -Xsram[1316] sram->in sram[1316]->out sram[1316]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1316]->out) 0 -.nodeset V(sram[1316]->outb) vsp -Xsram[1317] sram->in sram[1317]->out sram[1317]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1317]->out) 0 -.nodeset V(sram[1317]->outb) vsp -Xsram[1318] sram->in sram[1318]->out sram[1318]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1318]->out) 0 -.nodeset V(sram[1318]->outb) vsp -Xsram[1319] sram->in sram[1319]->out sram[1319]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1319]->out) 0 -.nodeset V(sram[1319]->outb) vsp -Xsram[1320] sram->in sram[1320]->out sram[1320]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1320]->out) 0 -.nodeset V(sram[1320]->outb) vsp -Xsram[1321] sram->in sram[1321]->out sram[1321]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1321]->out) 0 -.nodeset V(sram[1321]->outb) vsp -Xdirect_interc[176] mode[clb]->clk[0] fle[6]->clk[0] gvdd_local_interc sgnd direct_interc -Xmux_2level_size50[42] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[7]->in[0] sram[1322]->outb sram[1322]->out sram[1323]->out sram[1323]->outb sram[1324]->out sram[1324]->outb sram[1325]->out sram[1325]->outb sram[1326]->out sram[1326]->outb sram[1327]->out sram[1327]->outb sram[1328]->out sram[1328]->outb sram[1329]->out sram[1329]->outb sram[1330]->outb sram[1330]->out sram[1331]->out sram[1331]->outb sram[1332]->out sram[1332]->outb sram[1333]->out sram[1333]->outb sram[1334]->out sram[1334]->outb sram[1335]->out sram[1335]->outb sram[1336]->out sram[1336]->outb sram[1337]->out sram[1337]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[42], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1322] sram->in sram[1322]->out sram[1322]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1322]->out) 0 -.nodeset V(sram[1322]->outb) vsp -Xsram[1323] sram->in sram[1323]->out sram[1323]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1323]->out) 0 -.nodeset V(sram[1323]->outb) vsp -Xsram[1324] sram->in sram[1324]->out sram[1324]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1324]->out) 0 -.nodeset V(sram[1324]->outb) vsp -Xsram[1325] sram->in sram[1325]->out sram[1325]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1325]->out) 0 -.nodeset V(sram[1325]->outb) vsp -Xsram[1326] sram->in sram[1326]->out sram[1326]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1326]->out) 0 -.nodeset V(sram[1326]->outb) vsp -Xsram[1327] sram->in sram[1327]->out sram[1327]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1327]->out) 0 -.nodeset V(sram[1327]->outb) vsp -Xsram[1328] sram->in sram[1328]->out sram[1328]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1328]->out) 0 -.nodeset V(sram[1328]->outb) vsp -Xsram[1329] sram->in sram[1329]->out sram[1329]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1329]->out) 0 -.nodeset V(sram[1329]->outb) vsp -Xsram[1330] sram->in sram[1330]->out sram[1330]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1330]->out) 0 -.nodeset V(sram[1330]->outb) vsp -Xsram[1331] sram->in sram[1331]->out sram[1331]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1331]->out) 0 -.nodeset V(sram[1331]->outb) vsp -Xsram[1332] sram->in sram[1332]->out sram[1332]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1332]->out) 0 -.nodeset V(sram[1332]->outb) vsp -Xsram[1333] sram->in sram[1333]->out sram[1333]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1333]->out) 0 -.nodeset V(sram[1333]->outb) vsp -Xsram[1334] sram->in sram[1334]->out sram[1334]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1334]->out) 0 -.nodeset V(sram[1334]->outb) vsp -Xsram[1335] sram->in sram[1335]->out sram[1335]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1335]->out) 0 -.nodeset V(sram[1335]->outb) vsp -Xsram[1336] sram->in sram[1336]->out sram[1336]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1336]->out) 0 -.nodeset V(sram[1336]->outb) vsp -Xsram[1337] sram->in sram[1337]->out sram[1337]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1337]->out) 0 -.nodeset V(sram[1337]->outb) vsp -Xmux_2level_size50[43] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[7]->in[1] sram[1338]->outb sram[1338]->out sram[1339]->out sram[1339]->outb sram[1340]->out sram[1340]->outb sram[1341]->out sram[1341]->outb sram[1342]->out sram[1342]->outb sram[1343]->out sram[1343]->outb sram[1344]->out sram[1344]->outb sram[1345]->out sram[1345]->outb sram[1346]->outb sram[1346]->out sram[1347]->out sram[1347]->outb sram[1348]->out sram[1348]->outb sram[1349]->out sram[1349]->outb sram[1350]->out sram[1350]->outb sram[1351]->out sram[1351]->outb sram[1352]->out sram[1352]->outb sram[1353]->out sram[1353]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[43], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1338] sram->in sram[1338]->out sram[1338]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1338]->out) 0 -.nodeset V(sram[1338]->outb) vsp -Xsram[1339] sram->in sram[1339]->out sram[1339]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1339]->out) 0 -.nodeset V(sram[1339]->outb) vsp -Xsram[1340] sram->in sram[1340]->out sram[1340]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1340]->out) 0 -.nodeset V(sram[1340]->outb) vsp -Xsram[1341] sram->in sram[1341]->out sram[1341]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1341]->out) 0 -.nodeset V(sram[1341]->outb) vsp -Xsram[1342] sram->in sram[1342]->out sram[1342]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1342]->out) 0 -.nodeset V(sram[1342]->outb) vsp -Xsram[1343] sram->in sram[1343]->out sram[1343]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1343]->out) 0 -.nodeset V(sram[1343]->outb) vsp -Xsram[1344] sram->in sram[1344]->out sram[1344]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1344]->out) 0 -.nodeset V(sram[1344]->outb) vsp -Xsram[1345] sram->in sram[1345]->out sram[1345]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1345]->out) 0 -.nodeset V(sram[1345]->outb) vsp -Xsram[1346] sram->in sram[1346]->out sram[1346]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1346]->out) 0 -.nodeset V(sram[1346]->outb) vsp -Xsram[1347] sram->in sram[1347]->out sram[1347]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1347]->out) 0 -.nodeset V(sram[1347]->outb) vsp -Xsram[1348] sram->in sram[1348]->out sram[1348]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1348]->out) 0 -.nodeset V(sram[1348]->outb) vsp -Xsram[1349] sram->in sram[1349]->out sram[1349]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1349]->out) 0 -.nodeset V(sram[1349]->outb) vsp -Xsram[1350] sram->in sram[1350]->out sram[1350]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1350]->out) 0 -.nodeset V(sram[1350]->outb) vsp -Xsram[1351] sram->in sram[1351]->out sram[1351]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1351]->out) 0 -.nodeset V(sram[1351]->outb) vsp -Xsram[1352] sram->in sram[1352]->out sram[1352]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1352]->out) 0 -.nodeset V(sram[1352]->outb) vsp -Xsram[1353] sram->in sram[1353]->out sram[1353]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1353]->out) 0 -.nodeset V(sram[1353]->outb) vsp -Xmux_2level_size50[44] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[7]->in[2] sram[1354]->outb sram[1354]->out sram[1355]->out sram[1355]->outb sram[1356]->out sram[1356]->outb sram[1357]->out sram[1357]->outb sram[1358]->out sram[1358]->outb sram[1359]->out sram[1359]->outb sram[1360]->out sram[1360]->outb sram[1361]->out sram[1361]->outb sram[1362]->outb sram[1362]->out sram[1363]->out sram[1363]->outb sram[1364]->out sram[1364]->outb sram[1365]->out sram[1365]->outb sram[1366]->out sram[1366]->outb sram[1367]->out sram[1367]->outb sram[1368]->out sram[1368]->outb sram[1369]->out sram[1369]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[44], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1354] sram->in sram[1354]->out sram[1354]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1354]->out) 0 -.nodeset V(sram[1354]->outb) vsp -Xsram[1355] sram->in sram[1355]->out sram[1355]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1355]->out) 0 -.nodeset V(sram[1355]->outb) vsp -Xsram[1356] sram->in sram[1356]->out sram[1356]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1356]->out) 0 -.nodeset V(sram[1356]->outb) vsp -Xsram[1357] sram->in sram[1357]->out sram[1357]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1357]->out) 0 -.nodeset V(sram[1357]->outb) vsp -Xsram[1358] sram->in sram[1358]->out sram[1358]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1358]->out) 0 -.nodeset V(sram[1358]->outb) vsp -Xsram[1359] sram->in sram[1359]->out sram[1359]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1359]->out) 0 -.nodeset V(sram[1359]->outb) vsp -Xsram[1360] sram->in sram[1360]->out sram[1360]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1360]->out) 0 -.nodeset V(sram[1360]->outb) vsp -Xsram[1361] sram->in sram[1361]->out sram[1361]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1361]->out) 0 -.nodeset V(sram[1361]->outb) vsp -Xsram[1362] sram->in sram[1362]->out sram[1362]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1362]->out) 0 -.nodeset V(sram[1362]->outb) vsp -Xsram[1363] sram->in sram[1363]->out sram[1363]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1363]->out) 0 -.nodeset V(sram[1363]->outb) vsp -Xsram[1364] sram->in sram[1364]->out sram[1364]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1364]->out) 0 -.nodeset V(sram[1364]->outb) vsp -Xsram[1365] sram->in sram[1365]->out sram[1365]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1365]->out) 0 -.nodeset V(sram[1365]->outb) vsp -Xsram[1366] sram->in sram[1366]->out sram[1366]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1366]->out) 0 -.nodeset V(sram[1366]->outb) vsp -Xsram[1367] sram->in sram[1367]->out sram[1367]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1367]->out) 0 -.nodeset V(sram[1367]->outb) vsp -Xsram[1368] sram->in sram[1368]->out sram[1368]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1368]->out) 0 -.nodeset V(sram[1368]->outb) vsp -Xsram[1369] sram->in sram[1369]->out sram[1369]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1369]->out) 0 -.nodeset V(sram[1369]->outb) vsp -Xmux_2level_size50[45] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[7]->in[3] sram[1370]->outb sram[1370]->out sram[1371]->out sram[1371]->outb sram[1372]->out sram[1372]->outb sram[1373]->out sram[1373]->outb sram[1374]->out sram[1374]->outb sram[1375]->out sram[1375]->outb sram[1376]->out sram[1376]->outb sram[1377]->out sram[1377]->outb sram[1378]->outb sram[1378]->out sram[1379]->out sram[1379]->outb sram[1380]->out sram[1380]->outb sram[1381]->out sram[1381]->outb sram[1382]->out sram[1382]->outb sram[1383]->out sram[1383]->outb sram[1384]->out sram[1384]->outb sram[1385]->out sram[1385]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[45], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1370] sram->in sram[1370]->out sram[1370]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1370]->out) 0 -.nodeset V(sram[1370]->outb) vsp -Xsram[1371] sram->in sram[1371]->out sram[1371]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1371]->out) 0 -.nodeset V(sram[1371]->outb) vsp -Xsram[1372] sram->in sram[1372]->out sram[1372]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1372]->out) 0 -.nodeset V(sram[1372]->outb) vsp -Xsram[1373] sram->in sram[1373]->out sram[1373]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1373]->out) 0 -.nodeset V(sram[1373]->outb) vsp -Xsram[1374] sram->in sram[1374]->out sram[1374]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1374]->out) 0 -.nodeset V(sram[1374]->outb) vsp -Xsram[1375] sram->in sram[1375]->out sram[1375]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1375]->out) 0 -.nodeset V(sram[1375]->outb) vsp -Xsram[1376] sram->in sram[1376]->out sram[1376]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1376]->out) 0 -.nodeset V(sram[1376]->outb) vsp -Xsram[1377] sram->in sram[1377]->out sram[1377]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1377]->out) 0 -.nodeset V(sram[1377]->outb) vsp -Xsram[1378] sram->in sram[1378]->out sram[1378]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1378]->out) 0 -.nodeset V(sram[1378]->outb) vsp -Xsram[1379] sram->in sram[1379]->out sram[1379]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1379]->out) 0 -.nodeset V(sram[1379]->outb) vsp -Xsram[1380] sram->in sram[1380]->out sram[1380]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1380]->out) 0 -.nodeset V(sram[1380]->outb) vsp -Xsram[1381] sram->in sram[1381]->out sram[1381]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1381]->out) 0 -.nodeset V(sram[1381]->outb) vsp -Xsram[1382] sram->in sram[1382]->out sram[1382]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1382]->out) 0 -.nodeset V(sram[1382]->outb) vsp -Xsram[1383] sram->in sram[1383]->out sram[1383]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1383]->out) 0 -.nodeset V(sram[1383]->outb) vsp -Xsram[1384] sram->in sram[1384]->out sram[1384]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1384]->out) 0 -.nodeset V(sram[1384]->outb) vsp -Xsram[1385] sram->in sram[1385]->out sram[1385]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1385]->out) 0 -.nodeset V(sram[1385]->outb) vsp -Xmux_2level_size50[46] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[7]->in[4] sram[1386]->outb sram[1386]->out sram[1387]->out sram[1387]->outb sram[1388]->out sram[1388]->outb sram[1389]->out sram[1389]->outb sram[1390]->out sram[1390]->outb sram[1391]->out sram[1391]->outb sram[1392]->out sram[1392]->outb sram[1393]->out sram[1393]->outb sram[1394]->outb sram[1394]->out sram[1395]->out sram[1395]->outb sram[1396]->out sram[1396]->outb sram[1397]->out sram[1397]->outb sram[1398]->out sram[1398]->outb sram[1399]->out sram[1399]->outb sram[1400]->out sram[1400]->outb sram[1401]->out sram[1401]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[46], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1386] sram->in sram[1386]->out sram[1386]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1386]->out) 0 -.nodeset V(sram[1386]->outb) vsp -Xsram[1387] sram->in sram[1387]->out sram[1387]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1387]->out) 0 -.nodeset V(sram[1387]->outb) vsp -Xsram[1388] sram->in sram[1388]->out sram[1388]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1388]->out) 0 -.nodeset V(sram[1388]->outb) vsp -Xsram[1389] sram->in sram[1389]->out sram[1389]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1389]->out) 0 -.nodeset V(sram[1389]->outb) vsp -Xsram[1390] sram->in sram[1390]->out sram[1390]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1390]->out) 0 -.nodeset V(sram[1390]->outb) vsp -Xsram[1391] sram->in sram[1391]->out sram[1391]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1391]->out) 0 -.nodeset V(sram[1391]->outb) vsp -Xsram[1392] sram->in sram[1392]->out sram[1392]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1392]->out) 0 -.nodeset V(sram[1392]->outb) vsp -Xsram[1393] sram->in sram[1393]->out sram[1393]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1393]->out) 0 -.nodeset V(sram[1393]->outb) vsp -Xsram[1394] sram->in sram[1394]->out sram[1394]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1394]->out) 0 -.nodeset V(sram[1394]->outb) vsp -Xsram[1395] sram->in sram[1395]->out sram[1395]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1395]->out) 0 -.nodeset V(sram[1395]->outb) vsp -Xsram[1396] sram->in sram[1396]->out sram[1396]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1396]->out) 0 -.nodeset V(sram[1396]->outb) vsp -Xsram[1397] sram->in sram[1397]->out sram[1397]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1397]->out) 0 -.nodeset V(sram[1397]->outb) vsp -Xsram[1398] sram->in sram[1398]->out sram[1398]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1398]->out) 0 -.nodeset V(sram[1398]->outb) vsp -Xsram[1399] sram->in sram[1399]->out sram[1399]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1399]->out) 0 -.nodeset V(sram[1399]->outb) vsp -Xsram[1400] sram->in sram[1400]->out sram[1400]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1400]->out) 0 -.nodeset V(sram[1400]->outb) vsp -Xsram[1401] sram->in sram[1401]->out sram[1401]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1401]->out) 0 -.nodeset V(sram[1401]->outb) vsp -Xmux_2level_size50[47] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[7]->in[5] sram[1402]->outb sram[1402]->out sram[1403]->out sram[1403]->outb sram[1404]->out sram[1404]->outb sram[1405]->out sram[1405]->outb sram[1406]->out sram[1406]->outb sram[1407]->out sram[1407]->outb sram[1408]->out sram[1408]->outb sram[1409]->out sram[1409]->outb sram[1410]->outb sram[1410]->out sram[1411]->out sram[1411]->outb sram[1412]->out sram[1412]->outb sram[1413]->out sram[1413]->outb sram[1414]->out sram[1414]->outb sram[1415]->out sram[1415]->outb sram[1416]->out sram[1416]->outb sram[1417]->out sram[1417]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[47], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1402] sram->in sram[1402]->out sram[1402]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1402]->out) 0 -.nodeset V(sram[1402]->outb) vsp -Xsram[1403] sram->in sram[1403]->out sram[1403]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1403]->out) 0 -.nodeset V(sram[1403]->outb) vsp -Xsram[1404] sram->in sram[1404]->out sram[1404]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1404]->out) 0 -.nodeset V(sram[1404]->outb) vsp -Xsram[1405] sram->in sram[1405]->out sram[1405]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1405]->out) 0 -.nodeset V(sram[1405]->outb) vsp -Xsram[1406] sram->in sram[1406]->out sram[1406]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1406]->out) 0 -.nodeset V(sram[1406]->outb) vsp -Xsram[1407] sram->in sram[1407]->out sram[1407]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1407]->out) 0 -.nodeset V(sram[1407]->outb) vsp -Xsram[1408] sram->in sram[1408]->out sram[1408]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1408]->out) 0 -.nodeset V(sram[1408]->outb) vsp -Xsram[1409] sram->in sram[1409]->out sram[1409]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1409]->out) 0 -.nodeset V(sram[1409]->outb) vsp -Xsram[1410] sram->in sram[1410]->out sram[1410]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1410]->out) 0 -.nodeset V(sram[1410]->outb) vsp -Xsram[1411] sram->in sram[1411]->out sram[1411]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1411]->out) 0 -.nodeset V(sram[1411]->outb) vsp -Xsram[1412] sram->in sram[1412]->out sram[1412]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1412]->out) 0 -.nodeset V(sram[1412]->outb) vsp -Xsram[1413] sram->in sram[1413]->out sram[1413]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1413]->out) 0 -.nodeset V(sram[1413]->outb) vsp -Xsram[1414] sram->in sram[1414]->out sram[1414]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1414]->out) 0 -.nodeset V(sram[1414]->outb) vsp -Xsram[1415] sram->in sram[1415]->out sram[1415]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1415]->out) 0 -.nodeset V(sram[1415]->outb) vsp -Xsram[1416] sram->in sram[1416]->out sram[1416]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1416]->out) 0 -.nodeset V(sram[1416]->outb) vsp -Xsram[1417] sram->in sram[1417]->out sram[1417]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1417]->out) 0 -.nodeset V(sram[1417]->outb) vsp -Xdirect_interc[177] mode[clb]->clk[0] fle[7]->clk[0] gvdd_local_interc sgnd direct_interc -Xmux_2level_size50[48] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[8]->in[0] sram[1418]->outb sram[1418]->out sram[1419]->out sram[1419]->outb sram[1420]->out sram[1420]->outb sram[1421]->out sram[1421]->outb sram[1422]->out sram[1422]->outb sram[1423]->out sram[1423]->outb sram[1424]->out sram[1424]->outb sram[1425]->out sram[1425]->outb sram[1426]->outb sram[1426]->out sram[1427]->out sram[1427]->outb sram[1428]->out sram[1428]->outb sram[1429]->out sram[1429]->outb sram[1430]->out sram[1430]->outb sram[1431]->out sram[1431]->outb sram[1432]->out sram[1432]->outb sram[1433]->out sram[1433]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[48], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1418] sram->in sram[1418]->out sram[1418]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1418]->out) 0 -.nodeset V(sram[1418]->outb) vsp -Xsram[1419] sram->in sram[1419]->out sram[1419]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1419]->out) 0 -.nodeset V(sram[1419]->outb) vsp -Xsram[1420] sram->in sram[1420]->out sram[1420]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1420]->out) 0 -.nodeset V(sram[1420]->outb) vsp -Xsram[1421] sram->in sram[1421]->out sram[1421]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1421]->out) 0 -.nodeset V(sram[1421]->outb) vsp -Xsram[1422] sram->in sram[1422]->out sram[1422]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1422]->out) 0 -.nodeset V(sram[1422]->outb) vsp -Xsram[1423] sram->in sram[1423]->out sram[1423]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1423]->out) 0 -.nodeset V(sram[1423]->outb) vsp -Xsram[1424] sram->in sram[1424]->out sram[1424]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1424]->out) 0 -.nodeset V(sram[1424]->outb) vsp -Xsram[1425] sram->in sram[1425]->out sram[1425]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1425]->out) 0 -.nodeset V(sram[1425]->outb) vsp -Xsram[1426] sram->in sram[1426]->out sram[1426]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1426]->out) 0 -.nodeset V(sram[1426]->outb) vsp -Xsram[1427] sram->in sram[1427]->out sram[1427]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1427]->out) 0 -.nodeset V(sram[1427]->outb) vsp -Xsram[1428] sram->in sram[1428]->out sram[1428]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1428]->out) 0 -.nodeset V(sram[1428]->outb) vsp -Xsram[1429] sram->in sram[1429]->out sram[1429]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1429]->out) 0 -.nodeset V(sram[1429]->outb) vsp -Xsram[1430] sram->in sram[1430]->out sram[1430]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1430]->out) 0 -.nodeset V(sram[1430]->outb) vsp -Xsram[1431] sram->in sram[1431]->out sram[1431]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1431]->out) 0 -.nodeset V(sram[1431]->outb) vsp -Xsram[1432] sram->in sram[1432]->out sram[1432]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1432]->out) 0 -.nodeset V(sram[1432]->outb) vsp -Xsram[1433] sram->in sram[1433]->out sram[1433]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1433]->out) 0 -.nodeset V(sram[1433]->outb) vsp -Xmux_2level_size50[49] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[8]->in[1] sram[1434]->outb sram[1434]->out sram[1435]->out sram[1435]->outb sram[1436]->out sram[1436]->outb sram[1437]->out sram[1437]->outb sram[1438]->out sram[1438]->outb sram[1439]->out sram[1439]->outb sram[1440]->out sram[1440]->outb sram[1441]->out sram[1441]->outb sram[1442]->outb sram[1442]->out sram[1443]->out sram[1443]->outb sram[1444]->out sram[1444]->outb sram[1445]->out sram[1445]->outb sram[1446]->out sram[1446]->outb sram[1447]->out sram[1447]->outb sram[1448]->out sram[1448]->outb sram[1449]->out sram[1449]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[49], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1434] sram->in sram[1434]->out sram[1434]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1434]->out) 0 -.nodeset V(sram[1434]->outb) vsp -Xsram[1435] sram->in sram[1435]->out sram[1435]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1435]->out) 0 -.nodeset V(sram[1435]->outb) vsp -Xsram[1436] sram->in sram[1436]->out sram[1436]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1436]->out) 0 -.nodeset V(sram[1436]->outb) vsp -Xsram[1437] sram->in sram[1437]->out sram[1437]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1437]->out) 0 -.nodeset V(sram[1437]->outb) vsp -Xsram[1438] sram->in sram[1438]->out sram[1438]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1438]->out) 0 -.nodeset V(sram[1438]->outb) vsp -Xsram[1439] sram->in sram[1439]->out sram[1439]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1439]->out) 0 -.nodeset V(sram[1439]->outb) vsp -Xsram[1440] sram->in sram[1440]->out sram[1440]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1440]->out) 0 -.nodeset V(sram[1440]->outb) vsp -Xsram[1441] sram->in sram[1441]->out sram[1441]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1441]->out) 0 -.nodeset V(sram[1441]->outb) vsp -Xsram[1442] sram->in sram[1442]->out sram[1442]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1442]->out) 0 -.nodeset V(sram[1442]->outb) vsp -Xsram[1443] sram->in sram[1443]->out sram[1443]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1443]->out) 0 -.nodeset V(sram[1443]->outb) vsp -Xsram[1444] sram->in sram[1444]->out sram[1444]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1444]->out) 0 -.nodeset V(sram[1444]->outb) vsp -Xsram[1445] sram->in sram[1445]->out sram[1445]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1445]->out) 0 -.nodeset V(sram[1445]->outb) vsp -Xsram[1446] sram->in sram[1446]->out sram[1446]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1446]->out) 0 -.nodeset V(sram[1446]->outb) vsp -Xsram[1447] sram->in sram[1447]->out sram[1447]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1447]->out) 0 -.nodeset V(sram[1447]->outb) vsp -Xsram[1448] sram->in sram[1448]->out sram[1448]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1448]->out) 0 -.nodeset V(sram[1448]->outb) vsp -Xsram[1449] sram->in sram[1449]->out sram[1449]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1449]->out) 0 -.nodeset V(sram[1449]->outb) vsp -Xmux_2level_size50[50] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[8]->in[2] sram[1450]->outb sram[1450]->out sram[1451]->out sram[1451]->outb sram[1452]->out sram[1452]->outb sram[1453]->out sram[1453]->outb sram[1454]->out sram[1454]->outb sram[1455]->out sram[1455]->outb sram[1456]->out sram[1456]->outb sram[1457]->out sram[1457]->outb sram[1458]->outb sram[1458]->out sram[1459]->out sram[1459]->outb sram[1460]->out sram[1460]->outb sram[1461]->out sram[1461]->outb sram[1462]->out sram[1462]->outb sram[1463]->out sram[1463]->outb sram[1464]->out sram[1464]->outb sram[1465]->out sram[1465]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[50], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1450] sram->in sram[1450]->out sram[1450]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1450]->out) 0 -.nodeset V(sram[1450]->outb) vsp -Xsram[1451] sram->in sram[1451]->out sram[1451]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1451]->out) 0 -.nodeset V(sram[1451]->outb) vsp -Xsram[1452] sram->in sram[1452]->out sram[1452]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1452]->out) 0 -.nodeset V(sram[1452]->outb) vsp -Xsram[1453] sram->in sram[1453]->out sram[1453]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1453]->out) 0 -.nodeset V(sram[1453]->outb) vsp -Xsram[1454] sram->in sram[1454]->out sram[1454]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1454]->out) 0 -.nodeset V(sram[1454]->outb) vsp -Xsram[1455] sram->in sram[1455]->out sram[1455]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1455]->out) 0 -.nodeset V(sram[1455]->outb) vsp -Xsram[1456] sram->in sram[1456]->out sram[1456]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1456]->out) 0 -.nodeset V(sram[1456]->outb) vsp -Xsram[1457] sram->in sram[1457]->out sram[1457]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1457]->out) 0 -.nodeset V(sram[1457]->outb) vsp -Xsram[1458] sram->in sram[1458]->out sram[1458]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1458]->out) 0 -.nodeset V(sram[1458]->outb) vsp -Xsram[1459] sram->in sram[1459]->out sram[1459]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1459]->out) 0 -.nodeset V(sram[1459]->outb) vsp -Xsram[1460] sram->in sram[1460]->out sram[1460]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1460]->out) 0 -.nodeset V(sram[1460]->outb) vsp -Xsram[1461] sram->in sram[1461]->out sram[1461]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1461]->out) 0 -.nodeset V(sram[1461]->outb) vsp -Xsram[1462] sram->in sram[1462]->out sram[1462]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1462]->out) 0 -.nodeset V(sram[1462]->outb) vsp -Xsram[1463] sram->in sram[1463]->out sram[1463]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1463]->out) 0 -.nodeset V(sram[1463]->outb) vsp -Xsram[1464] sram->in sram[1464]->out sram[1464]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1464]->out) 0 -.nodeset V(sram[1464]->outb) vsp -Xsram[1465] sram->in sram[1465]->out sram[1465]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1465]->out) 0 -.nodeset V(sram[1465]->outb) vsp -Xmux_2level_size50[51] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[8]->in[3] sram[1466]->outb sram[1466]->out sram[1467]->out sram[1467]->outb sram[1468]->out sram[1468]->outb sram[1469]->out sram[1469]->outb sram[1470]->out sram[1470]->outb sram[1471]->out sram[1471]->outb sram[1472]->out sram[1472]->outb sram[1473]->out sram[1473]->outb sram[1474]->outb sram[1474]->out sram[1475]->out sram[1475]->outb sram[1476]->out sram[1476]->outb sram[1477]->out sram[1477]->outb sram[1478]->out sram[1478]->outb sram[1479]->out sram[1479]->outb sram[1480]->out sram[1480]->outb sram[1481]->out sram[1481]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[51], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1466] sram->in sram[1466]->out sram[1466]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1466]->out) 0 -.nodeset V(sram[1466]->outb) vsp -Xsram[1467] sram->in sram[1467]->out sram[1467]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1467]->out) 0 -.nodeset V(sram[1467]->outb) vsp -Xsram[1468] sram->in sram[1468]->out sram[1468]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1468]->out) 0 -.nodeset V(sram[1468]->outb) vsp -Xsram[1469] sram->in sram[1469]->out sram[1469]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1469]->out) 0 -.nodeset V(sram[1469]->outb) vsp -Xsram[1470] sram->in sram[1470]->out sram[1470]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1470]->out) 0 -.nodeset V(sram[1470]->outb) vsp -Xsram[1471] sram->in sram[1471]->out sram[1471]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1471]->out) 0 -.nodeset V(sram[1471]->outb) vsp -Xsram[1472] sram->in sram[1472]->out sram[1472]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1472]->out) 0 -.nodeset V(sram[1472]->outb) vsp -Xsram[1473] sram->in sram[1473]->out sram[1473]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1473]->out) 0 -.nodeset V(sram[1473]->outb) vsp -Xsram[1474] sram->in sram[1474]->out sram[1474]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1474]->out) 0 -.nodeset V(sram[1474]->outb) vsp -Xsram[1475] sram->in sram[1475]->out sram[1475]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1475]->out) 0 -.nodeset V(sram[1475]->outb) vsp -Xsram[1476] sram->in sram[1476]->out sram[1476]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1476]->out) 0 -.nodeset V(sram[1476]->outb) vsp -Xsram[1477] sram->in sram[1477]->out sram[1477]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1477]->out) 0 -.nodeset V(sram[1477]->outb) vsp -Xsram[1478] sram->in sram[1478]->out sram[1478]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1478]->out) 0 -.nodeset V(sram[1478]->outb) vsp -Xsram[1479] sram->in sram[1479]->out sram[1479]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1479]->out) 0 -.nodeset V(sram[1479]->outb) vsp -Xsram[1480] sram->in sram[1480]->out sram[1480]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1480]->out) 0 -.nodeset V(sram[1480]->outb) vsp -Xsram[1481] sram->in sram[1481]->out sram[1481]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1481]->out) 0 -.nodeset V(sram[1481]->outb) vsp -Xmux_2level_size50[52] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[8]->in[4] sram[1482]->outb sram[1482]->out sram[1483]->out sram[1483]->outb sram[1484]->out sram[1484]->outb sram[1485]->out sram[1485]->outb sram[1486]->out sram[1486]->outb sram[1487]->out sram[1487]->outb sram[1488]->out sram[1488]->outb sram[1489]->out sram[1489]->outb sram[1490]->outb sram[1490]->out sram[1491]->out sram[1491]->outb sram[1492]->out sram[1492]->outb sram[1493]->out sram[1493]->outb sram[1494]->out sram[1494]->outb sram[1495]->out sram[1495]->outb sram[1496]->out sram[1496]->outb sram[1497]->out sram[1497]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[52], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1482] sram->in sram[1482]->out sram[1482]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1482]->out) 0 -.nodeset V(sram[1482]->outb) vsp -Xsram[1483] sram->in sram[1483]->out sram[1483]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1483]->out) 0 -.nodeset V(sram[1483]->outb) vsp -Xsram[1484] sram->in sram[1484]->out sram[1484]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1484]->out) 0 -.nodeset V(sram[1484]->outb) vsp -Xsram[1485] sram->in sram[1485]->out sram[1485]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1485]->out) 0 -.nodeset V(sram[1485]->outb) vsp -Xsram[1486] sram->in sram[1486]->out sram[1486]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1486]->out) 0 -.nodeset V(sram[1486]->outb) vsp -Xsram[1487] sram->in sram[1487]->out sram[1487]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1487]->out) 0 -.nodeset V(sram[1487]->outb) vsp -Xsram[1488] sram->in sram[1488]->out sram[1488]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1488]->out) 0 -.nodeset V(sram[1488]->outb) vsp -Xsram[1489] sram->in sram[1489]->out sram[1489]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1489]->out) 0 -.nodeset V(sram[1489]->outb) vsp -Xsram[1490] sram->in sram[1490]->out sram[1490]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1490]->out) 0 -.nodeset V(sram[1490]->outb) vsp -Xsram[1491] sram->in sram[1491]->out sram[1491]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1491]->out) 0 -.nodeset V(sram[1491]->outb) vsp -Xsram[1492] sram->in sram[1492]->out sram[1492]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1492]->out) 0 -.nodeset V(sram[1492]->outb) vsp -Xsram[1493] sram->in sram[1493]->out sram[1493]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1493]->out) 0 -.nodeset V(sram[1493]->outb) vsp -Xsram[1494] sram->in sram[1494]->out sram[1494]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1494]->out) 0 -.nodeset V(sram[1494]->outb) vsp -Xsram[1495] sram->in sram[1495]->out sram[1495]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1495]->out) 0 -.nodeset V(sram[1495]->outb) vsp -Xsram[1496] sram->in sram[1496]->out sram[1496]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1496]->out) 0 -.nodeset V(sram[1496]->outb) vsp -Xsram[1497] sram->in sram[1497]->out sram[1497]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1497]->out) 0 -.nodeset V(sram[1497]->outb) vsp -Xmux_2level_size50[53] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[8]->in[5] sram[1498]->outb sram[1498]->out sram[1499]->out sram[1499]->outb sram[1500]->out sram[1500]->outb sram[1501]->out sram[1501]->outb sram[1502]->out sram[1502]->outb sram[1503]->out sram[1503]->outb sram[1504]->out sram[1504]->outb sram[1505]->out sram[1505]->outb sram[1506]->outb sram[1506]->out sram[1507]->out sram[1507]->outb sram[1508]->out sram[1508]->outb sram[1509]->out sram[1509]->outb sram[1510]->out sram[1510]->outb sram[1511]->out sram[1511]->outb sram[1512]->out sram[1512]->outb sram[1513]->out sram[1513]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[53], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1498] sram->in sram[1498]->out sram[1498]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1498]->out) 0 -.nodeset V(sram[1498]->outb) vsp -Xsram[1499] sram->in sram[1499]->out sram[1499]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1499]->out) 0 -.nodeset V(sram[1499]->outb) vsp -Xsram[1500] sram->in sram[1500]->out sram[1500]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1500]->out) 0 -.nodeset V(sram[1500]->outb) vsp -Xsram[1501] sram->in sram[1501]->out sram[1501]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1501]->out) 0 -.nodeset V(sram[1501]->outb) vsp -Xsram[1502] sram->in sram[1502]->out sram[1502]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1502]->out) 0 -.nodeset V(sram[1502]->outb) vsp -Xsram[1503] sram->in sram[1503]->out sram[1503]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1503]->out) 0 -.nodeset V(sram[1503]->outb) vsp -Xsram[1504] sram->in sram[1504]->out sram[1504]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1504]->out) 0 -.nodeset V(sram[1504]->outb) vsp -Xsram[1505] sram->in sram[1505]->out sram[1505]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1505]->out) 0 -.nodeset V(sram[1505]->outb) vsp -Xsram[1506] sram->in sram[1506]->out sram[1506]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1506]->out) 0 -.nodeset V(sram[1506]->outb) vsp -Xsram[1507] sram->in sram[1507]->out sram[1507]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1507]->out) 0 -.nodeset V(sram[1507]->outb) vsp -Xsram[1508] sram->in sram[1508]->out sram[1508]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1508]->out) 0 -.nodeset V(sram[1508]->outb) vsp -Xsram[1509] sram->in sram[1509]->out sram[1509]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1509]->out) 0 -.nodeset V(sram[1509]->outb) vsp -Xsram[1510] sram->in sram[1510]->out sram[1510]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1510]->out) 0 -.nodeset V(sram[1510]->outb) vsp -Xsram[1511] sram->in sram[1511]->out sram[1511]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1511]->out) 0 -.nodeset V(sram[1511]->outb) vsp -Xsram[1512] sram->in sram[1512]->out sram[1512]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1512]->out) 0 -.nodeset V(sram[1512]->outb) vsp -Xsram[1513] sram->in sram[1513]->out sram[1513]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1513]->out) 0 -.nodeset V(sram[1513]->outb) vsp -Xdirect_interc[178] mode[clb]->clk[0] fle[8]->clk[0] gvdd_local_interc sgnd direct_interc -Xmux_2level_size50[54] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[9]->in[0] sram[1514]->out sram[1514]->outb sram[1515]->out sram[1515]->outb sram[1516]->outb sram[1516]->out sram[1517]->out sram[1517]->outb sram[1518]->out sram[1518]->outb sram[1519]->out sram[1519]->outb sram[1520]->out sram[1520]->outb sram[1521]->out sram[1521]->outb sram[1522]->out sram[1522]->outb sram[1523]->out sram[1523]->outb sram[1524]->out sram[1524]->outb sram[1525]->out sram[1525]->outb sram[1526]->out sram[1526]->outb sram[1527]->out sram[1527]->outb sram[1528]->outb sram[1528]->out sram[1529]->out sram[1529]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[54], level=2, select_path_id=22. ***** -*****0010000000000010***** -Xsram[1514] sram->in sram[1514]->out sram[1514]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1514]->out) 0 -.nodeset V(sram[1514]->outb) vsp -Xsram[1515] sram->in sram[1515]->out sram[1515]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1515]->out) 0 -.nodeset V(sram[1515]->outb) vsp -Xsram[1516] sram->in sram[1516]->out sram[1516]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1516]->out) 0 -.nodeset V(sram[1516]->outb) vsp -Xsram[1517] sram->in sram[1517]->out sram[1517]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1517]->out) 0 -.nodeset V(sram[1517]->outb) vsp -Xsram[1518] sram->in sram[1518]->out sram[1518]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1518]->out) 0 -.nodeset V(sram[1518]->outb) vsp -Xsram[1519] sram->in sram[1519]->out sram[1519]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1519]->out) 0 -.nodeset V(sram[1519]->outb) vsp -Xsram[1520] sram->in sram[1520]->out sram[1520]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1520]->out) 0 -.nodeset V(sram[1520]->outb) vsp -Xsram[1521] sram->in sram[1521]->out sram[1521]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1521]->out) 0 -.nodeset V(sram[1521]->outb) vsp -Xsram[1522] sram->in sram[1522]->out sram[1522]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1522]->out) 0 -.nodeset V(sram[1522]->outb) vsp -Xsram[1523] sram->in sram[1523]->out sram[1523]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1523]->out) 0 -.nodeset V(sram[1523]->outb) vsp -Xsram[1524] sram->in sram[1524]->out sram[1524]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1524]->out) 0 -.nodeset V(sram[1524]->outb) vsp -Xsram[1525] sram->in sram[1525]->out sram[1525]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1525]->out) 0 -.nodeset V(sram[1525]->outb) vsp -Xsram[1526] sram->in sram[1526]->out sram[1526]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1526]->out) 0 -.nodeset V(sram[1526]->outb) vsp -Xsram[1527] sram->in sram[1527]->out sram[1527]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1527]->out) 0 -.nodeset V(sram[1527]->outb) vsp -Xsram[1528] sram->in sram[1528]->out sram[1528]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1528]->out) 0 -.nodeset V(sram[1528]->outb) vsp -Xsram[1529] sram->in sram[1529]->out sram[1529]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1529]->out) 0 -.nodeset V(sram[1529]->outb) vsp -Xmux_2level_size50[55] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[9]->in[1] sram[1530]->outb sram[1530]->out sram[1531]->out sram[1531]->outb sram[1532]->out sram[1532]->outb sram[1533]->out sram[1533]->outb sram[1534]->out sram[1534]->outb sram[1535]->out sram[1535]->outb sram[1536]->out sram[1536]->outb sram[1537]->out sram[1537]->outb sram[1538]->outb sram[1538]->out sram[1539]->out sram[1539]->outb sram[1540]->out sram[1540]->outb sram[1541]->out sram[1541]->outb sram[1542]->out sram[1542]->outb sram[1543]->out sram[1543]->outb sram[1544]->out sram[1544]->outb sram[1545]->out sram[1545]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[55], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1530] sram->in sram[1530]->out sram[1530]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1530]->out) 0 -.nodeset V(sram[1530]->outb) vsp -Xsram[1531] sram->in sram[1531]->out sram[1531]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1531]->out) 0 -.nodeset V(sram[1531]->outb) vsp -Xsram[1532] sram->in sram[1532]->out sram[1532]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1532]->out) 0 -.nodeset V(sram[1532]->outb) vsp -Xsram[1533] sram->in sram[1533]->out sram[1533]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1533]->out) 0 -.nodeset V(sram[1533]->outb) vsp -Xsram[1534] sram->in sram[1534]->out sram[1534]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1534]->out) 0 -.nodeset V(sram[1534]->outb) vsp -Xsram[1535] sram->in sram[1535]->out sram[1535]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1535]->out) 0 -.nodeset V(sram[1535]->outb) vsp -Xsram[1536] sram->in sram[1536]->out sram[1536]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1536]->out) 0 -.nodeset V(sram[1536]->outb) vsp -Xsram[1537] sram->in sram[1537]->out sram[1537]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1537]->out) 0 -.nodeset V(sram[1537]->outb) vsp -Xsram[1538] sram->in sram[1538]->out sram[1538]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1538]->out) 0 -.nodeset V(sram[1538]->outb) vsp -Xsram[1539] sram->in sram[1539]->out sram[1539]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1539]->out) 0 -.nodeset V(sram[1539]->outb) vsp -Xsram[1540] sram->in sram[1540]->out sram[1540]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1540]->out) 0 -.nodeset V(sram[1540]->outb) vsp -Xsram[1541] sram->in sram[1541]->out sram[1541]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1541]->out) 0 -.nodeset V(sram[1541]->outb) vsp -Xsram[1542] sram->in sram[1542]->out sram[1542]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1542]->out) 0 -.nodeset V(sram[1542]->outb) vsp -Xsram[1543] sram->in sram[1543]->out sram[1543]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1543]->out) 0 -.nodeset V(sram[1543]->outb) vsp -Xsram[1544] sram->in sram[1544]->out sram[1544]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1544]->out) 0 -.nodeset V(sram[1544]->outb) vsp -Xsram[1545] sram->in sram[1545]->out sram[1545]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1545]->out) 0 -.nodeset V(sram[1545]->outb) vsp -Xmux_2level_size50[56] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[9]->in[2] sram[1546]->outb sram[1546]->out sram[1547]->out sram[1547]->outb sram[1548]->out sram[1548]->outb sram[1549]->out sram[1549]->outb sram[1550]->out sram[1550]->outb sram[1551]->out sram[1551]->outb sram[1552]->out sram[1552]->outb sram[1553]->out sram[1553]->outb sram[1554]->outb sram[1554]->out sram[1555]->out sram[1555]->outb sram[1556]->out sram[1556]->outb sram[1557]->out sram[1557]->outb sram[1558]->out sram[1558]->outb sram[1559]->out sram[1559]->outb sram[1560]->out sram[1560]->outb sram[1561]->out sram[1561]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[56], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1546] sram->in sram[1546]->out sram[1546]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1546]->out) 0 -.nodeset V(sram[1546]->outb) vsp -Xsram[1547] sram->in sram[1547]->out sram[1547]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1547]->out) 0 -.nodeset V(sram[1547]->outb) vsp -Xsram[1548] sram->in sram[1548]->out sram[1548]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1548]->out) 0 -.nodeset V(sram[1548]->outb) vsp -Xsram[1549] sram->in sram[1549]->out sram[1549]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1549]->out) 0 -.nodeset V(sram[1549]->outb) vsp -Xsram[1550] sram->in sram[1550]->out sram[1550]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1550]->out) 0 -.nodeset V(sram[1550]->outb) vsp -Xsram[1551] sram->in sram[1551]->out sram[1551]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1551]->out) 0 -.nodeset V(sram[1551]->outb) vsp -Xsram[1552] sram->in sram[1552]->out sram[1552]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1552]->out) 0 -.nodeset V(sram[1552]->outb) vsp -Xsram[1553] sram->in sram[1553]->out sram[1553]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1553]->out) 0 -.nodeset V(sram[1553]->outb) vsp -Xsram[1554] sram->in sram[1554]->out sram[1554]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1554]->out) 0 -.nodeset V(sram[1554]->outb) vsp -Xsram[1555] sram->in sram[1555]->out sram[1555]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1555]->out) 0 -.nodeset V(sram[1555]->outb) vsp -Xsram[1556] sram->in sram[1556]->out sram[1556]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1556]->out) 0 -.nodeset V(sram[1556]->outb) vsp -Xsram[1557] sram->in sram[1557]->out sram[1557]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1557]->out) 0 -.nodeset V(sram[1557]->outb) vsp -Xsram[1558] sram->in sram[1558]->out sram[1558]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1558]->out) 0 -.nodeset V(sram[1558]->outb) vsp -Xsram[1559] sram->in sram[1559]->out sram[1559]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1559]->out) 0 -.nodeset V(sram[1559]->outb) vsp -Xsram[1560] sram->in sram[1560]->out sram[1560]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1560]->out) 0 -.nodeset V(sram[1560]->outb) vsp -Xsram[1561] sram->in sram[1561]->out sram[1561]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1561]->out) 0 -.nodeset V(sram[1561]->outb) vsp -Xmux_2level_size50[57] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[9]->in[3] sram[1562]->outb sram[1562]->out sram[1563]->out sram[1563]->outb sram[1564]->out sram[1564]->outb sram[1565]->out sram[1565]->outb sram[1566]->out sram[1566]->outb sram[1567]->out sram[1567]->outb sram[1568]->out sram[1568]->outb sram[1569]->out sram[1569]->outb sram[1570]->outb sram[1570]->out sram[1571]->out sram[1571]->outb sram[1572]->out sram[1572]->outb sram[1573]->out sram[1573]->outb sram[1574]->out sram[1574]->outb sram[1575]->out sram[1575]->outb sram[1576]->out sram[1576]->outb sram[1577]->out sram[1577]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[57], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1562] sram->in sram[1562]->out sram[1562]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1562]->out) 0 -.nodeset V(sram[1562]->outb) vsp -Xsram[1563] sram->in sram[1563]->out sram[1563]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1563]->out) 0 -.nodeset V(sram[1563]->outb) vsp -Xsram[1564] sram->in sram[1564]->out sram[1564]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1564]->out) 0 -.nodeset V(sram[1564]->outb) vsp -Xsram[1565] sram->in sram[1565]->out sram[1565]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1565]->out) 0 -.nodeset V(sram[1565]->outb) vsp -Xsram[1566] sram->in sram[1566]->out sram[1566]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1566]->out) 0 -.nodeset V(sram[1566]->outb) vsp -Xsram[1567] sram->in sram[1567]->out sram[1567]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1567]->out) 0 -.nodeset V(sram[1567]->outb) vsp -Xsram[1568] sram->in sram[1568]->out sram[1568]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1568]->out) 0 -.nodeset V(sram[1568]->outb) vsp -Xsram[1569] sram->in sram[1569]->out sram[1569]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1569]->out) 0 -.nodeset V(sram[1569]->outb) vsp -Xsram[1570] sram->in sram[1570]->out sram[1570]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1570]->out) 0 -.nodeset V(sram[1570]->outb) vsp -Xsram[1571] sram->in sram[1571]->out sram[1571]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1571]->out) 0 -.nodeset V(sram[1571]->outb) vsp -Xsram[1572] sram->in sram[1572]->out sram[1572]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1572]->out) 0 -.nodeset V(sram[1572]->outb) vsp -Xsram[1573] sram->in sram[1573]->out sram[1573]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1573]->out) 0 -.nodeset V(sram[1573]->outb) vsp -Xsram[1574] sram->in sram[1574]->out sram[1574]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1574]->out) 0 -.nodeset V(sram[1574]->outb) vsp -Xsram[1575] sram->in sram[1575]->out sram[1575]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1575]->out) 0 -.nodeset V(sram[1575]->outb) vsp -Xsram[1576] sram->in sram[1576]->out sram[1576]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1576]->out) 0 -.nodeset V(sram[1576]->outb) vsp -Xsram[1577] sram->in sram[1577]->out sram[1577]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1577]->out) 0 -.nodeset V(sram[1577]->outb) vsp -Xmux_2level_size50[58] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[9]->in[4] sram[1578]->outb sram[1578]->out sram[1579]->out sram[1579]->outb sram[1580]->out sram[1580]->outb sram[1581]->out sram[1581]->outb sram[1582]->out sram[1582]->outb sram[1583]->out sram[1583]->outb sram[1584]->out sram[1584]->outb sram[1585]->out sram[1585]->outb sram[1586]->outb sram[1586]->out sram[1587]->out sram[1587]->outb sram[1588]->out sram[1588]->outb sram[1589]->out sram[1589]->outb sram[1590]->out sram[1590]->outb sram[1591]->out sram[1591]->outb sram[1592]->out sram[1592]->outb sram[1593]->out sram[1593]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[58], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1578] sram->in sram[1578]->out sram[1578]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1578]->out) 0 -.nodeset V(sram[1578]->outb) vsp -Xsram[1579] sram->in sram[1579]->out sram[1579]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1579]->out) 0 -.nodeset V(sram[1579]->outb) vsp -Xsram[1580] sram->in sram[1580]->out sram[1580]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1580]->out) 0 -.nodeset V(sram[1580]->outb) vsp -Xsram[1581] sram->in sram[1581]->out sram[1581]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1581]->out) 0 -.nodeset V(sram[1581]->outb) vsp -Xsram[1582] sram->in sram[1582]->out sram[1582]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1582]->out) 0 -.nodeset V(sram[1582]->outb) vsp -Xsram[1583] sram->in sram[1583]->out sram[1583]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1583]->out) 0 -.nodeset V(sram[1583]->outb) vsp -Xsram[1584] sram->in sram[1584]->out sram[1584]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1584]->out) 0 -.nodeset V(sram[1584]->outb) vsp -Xsram[1585] sram->in sram[1585]->out sram[1585]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1585]->out) 0 -.nodeset V(sram[1585]->outb) vsp -Xsram[1586] sram->in sram[1586]->out sram[1586]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1586]->out) 0 -.nodeset V(sram[1586]->outb) vsp -Xsram[1587] sram->in sram[1587]->out sram[1587]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1587]->out) 0 -.nodeset V(sram[1587]->outb) vsp -Xsram[1588] sram->in sram[1588]->out sram[1588]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1588]->out) 0 -.nodeset V(sram[1588]->outb) vsp -Xsram[1589] sram->in sram[1589]->out sram[1589]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1589]->out) 0 -.nodeset V(sram[1589]->outb) vsp -Xsram[1590] sram->in sram[1590]->out sram[1590]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1590]->out) 0 -.nodeset V(sram[1590]->outb) vsp -Xsram[1591] sram->in sram[1591]->out sram[1591]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1591]->out) 0 -.nodeset V(sram[1591]->outb) vsp -Xsram[1592] sram->in sram[1592]->out sram[1592]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1592]->out) 0 -.nodeset V(sram[1592]->outb) vsp -Xsram[1593] sram->in sram[1593]->out sram[1593]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1593]->out) 0 -.nodeset V(sram[1593]->outb) vsp -Xmux_2level_size50[59] mode[clb]->I[0] mode[clb]->I[1] mode[clb]->I[2] mode[clb]->I[3] mode[clb]->I[4] mode[clb]->I[5] mode[clb]->I[6] mode[clb]->I[7] mode[clb]->I[8] mode[clb]->I[9] mode[clb]->I[10] mode[clb]->I[11] mode[clb]->I[12] mode[clb]->I[13] mode[clb]->I[14] mode[clb]->I[15] mode[clb]->I[16] mode[clb]->I[17] mode[clb]->I[18] mode[clb]->I[19] mode[clb]->I[20] mode[clb]->I[21] mode[clb]->I[22] mode[clb]->I[23] mode[clb]->I[24] mode[clb]->I[25] mode[clb]->I[26] mode[clb]->I[27] mode[clb]->I[28] mode[clb]->I[29] mode[clb]->I[30] mode[clb]->I[31] mode[clb]->I[32] mode[clb]->I[33] mode[clb]->I[34] mode[clb]->I[35] mode[clb]->I[36] mode[clb]->I[37] mode[clb]->I[38] mode[clb]->I[39] fle[0]->out[0] fle[1]->out[0] fle[2]->out[0] fle[3]->out[0] fle[4]->out[0] fle[5]->out[0] fle[6]->out[0] fle[7]->out[0] fle[8]->out[0] fle[9]->out[0] fle[9]->in[5] sram[1594]->outb sram[1594]->out sram[1595]->out sram[1595]->outb sram[1596]->out sram[1596]->outb sram[1597]->out sram[1597]->outb sram[1598]->out sram[1598]->outb sram[1599]->out sram[1599]->outb sram[1600]->out sram[1600]->outb sram[1601]->out sram[1601]->outb sram[1602]->outb sram[1602]->out sram[1603]->out sram[1603]->outb sram[1604]->out sram[1604]->outb sram[1605]->out sram[1605]->outb sram[1606]->out sram[1606]->outb sram[1607]->out sram[1607]->outb sram[1608]->out sram[1608]->outb sram[1609]->out sram[1609]->outb gvdd_local_interc sgnd mux_2level_size50 -***** SRAM bits for MUX[59], level=2, select_path_id=0. ***** -*****1000000010000000***** -Xsram[1594] sram->in sram[1594]->out sram[1594]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1594]->out) 0 -.nodeset V(sram[1594]->outb) vsp -Xsram[1595] sram->in sram[1595]->out sram[1595]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1595]->out) 0 -.nodeset V(sram[1595]->outb) vsp -Xsram[1596] sram->in sram[1596]->out sram[1596]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1596]->out) 0 -.nodeset V(sram[1596]->outb) vsp -Xsram[1597] sram->in sram[1597]->out sram[1597]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1597]->out) 0 -.nodeset V(sram[1597]->outb) vsp -Xsram[1598] sram->in sram[1598]->out sram[1598]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1598]->out) 0 -.nodeset V(sram[1598]->outb) vsp -Xsram[1599] sram->in sram[1599]->out sram[1599]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1599]->out) 0 -.nodeset V(sram[1599]->outb) vsp -Xsram[1600] sram->in sram[1600]->out sram[1600]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1600]->out) 0 -.nodeset V(sram[1600]->outb) vsp -Xsram[1601] sram->in sram[1601]->out sram[1601]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1601]->out) 0 -.nodeset V(sram[1601]->outb) vsp -Xsram[1602] sram->in sram[1602]->out sram[1602]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1602]->out) 0 -.nodeset V(sram[1602]->outb) vsp -Xsram[1603] sram->in sram[1603]->out sram[1603]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1603]->out) 0 -.nodeset V(sram[1603]->outb) vsp -Xsram[1604] sram->in sram[1604]->out sram[1604]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1604]->out) 0 -.nodeset V(sram[1604]->outb) vsp -Xsram[1605] sram->in sram[1605]->out sram[1605]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1605]->out) 0 -.nodeset V(sram[1605]->outb) vsp -Xsram[1606] sram->in sram[1606]->out sram[1606]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1606]->out) 0 -.nodeset V(sram[1606]->outb) vsp -Xsram[1607] sram->in sram[1607]->out sram[1607]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1607]->out) 0 -.nodeset V(sram[1607]->outb) vsp -Xsram[1608] sram->in sram[1608]->out sram[1608]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1608]->out) 0 -.nodeset V(sram[1608]->outb) vsp -Xsram[1609] sram->in sram[1609]->out sram[1609]->outb gvdd_sram_local_routing sgnd sram6T -.nodeset V(sram[1609]->out) 0 -.nodeset V(sram[1609]->outb) vsp -Xdirect_interc[179] mode[clb]->clk[0] fle[9]->clk[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][1], Capactity: 1 ***** -***** Top Protocol ***** -.subckt grid[1][1] -+ top_height[0]_pin[0] -+ top_height[0]_pin[4] -+ top_height[0]_pin[8] -+ top_height[0]_pin[12] -+ top_height[0]_pin[16] -+ top_height[0]_pin[20] -+ top_height[0]_pin[24] -+ top_height[0]_pin[28] -+ top_height[0]_pin[32] -+ top_height[0]_pin[36] -+ top_height[0]_pin[40] -+ top_height[0]_pin[44] -+ top_height[0]_pin[48] -+ right_height[0]_pin[1] -+ right_height[0]_pin[5] -+ right_height[0]_pin[9] -+ right_height[0]_pin[13] -+ right_height[0]_pin[17] -+ right_height[0]_pin[21] -+ right_height[0]_pin[25] -+ right_height[0]_pin[29] -+ right_height[0]_pin[33] -+ right_height[0]_pin[37] -+ right_height[0]_pin[41] -+ right_height[0]_pin[45] -+ right_height[0]_pin[49] -+ bottom_height[0]_pin[2] -+ bottom_height[0]_pin[6] -+ bottom_height[0]_pin[10] -+ bottom_height[0]_pin[14] -+ bottom_height[0]_pin[18] -+ bottom_height[0]_pin[22] -+ bottom_height[0]_pin[26] -+ bottom_height[0]_pin[30] -+ bottom_height[0]_pin[34] -+ bottom_height[0]_pin[38] -+ bottom_height[0]_pin[42] -+ bottom_height[0]_pin[46] -+ bottom_height[0]_pin[50] -+ left_height[0]_pin[3] -+ left_height[0]_pin[7] -+ left_height[0]_pin[11] -+ left_height[0]_pin[15] -+ left_height[0]_pin[19] -+ left_height[0]_pin[23] -+ left_height[0]_pin[27] -+ left_height[0]_pin[31] -+ left_height[0]_pin[35] -+ left_height[0]_pin[39] -+ left_height[0]_pin[43] -+ left_height[0]_pin[47] -+ svdd sgnd -Xgrid[1][1][0] -+ top_height[0]_pin[0] -+ right_height[0]_pin[1] -+ bottom_height[0]_pin[2] -+ left_height[0]_pin[3] -+ top_height[0]_pin[4] -+ right_height[0]_pin[5] -+ bottom_height[0]_pin[6] -+ left_height[0]_pin[7] -+ top_height[0]_pin[8] -+ right_height[0]_pin[9] -+ bottom_height[0]_pin[10] -+ left_height[0]_pin[11] -+ top_height[0]_pin[12] -+ right_height[0]_pin[13] -+ bottom_height[0]_pin[14] -+ left_height[0]_pin[15] -+ top_height[0]_pin[16] -+ right_height[0]_pin[17] -+ bottom_height[0]_pin[18] -+ left_height[0]_pin[19] -+ top_height[0]_pin[20] -+ right_height[0]_pin[21] -+ bottom_height[0]_pin[22] -+ left_height[0]_pin[23] -+ top_height[0]_pin[24] -+ right_height[0]_pin[25] -+ bottom_height[0]_pin[26] -+ left_height[0]_pin[27] -+ top_height[0]_pin[28] -+ right_height[0]_pin[29] -+ bottom_height[0]_pin[30] -+ left_height[0]_pin[31] -+ top_height[0]_pin[32] -+ right_height[0]_pin[33] -+ bottom_height[0]_pin[34] -+ left_height[0]_pin[35] -+ top_height[0]_pin[36] -+ right_height[0]_pin[37] -+ bottom_height[0]_pin[38] -+ left_height[0]_pin[39] -+ top_height[0]_pin[40] -+ right_height[0]_pin[41] -+ bottom_height[0]_pin[42] -+ left_height[0]_pin[43] -+ top_height[0]_pin[44] -+ right_height[0]_pin[45] -+ bottom_height[0]_pin[46] -+ left_height[0]_pin[47] -+ top_height[0]_pin[48] -+ right_height[0]_pin[49] -+ bottom_height[0]_pin[50] -+ svdd sgnd grid[1][1]_clb[0]_mode[clb] -.eom diff --git a/examples/spice_test_example_2/subckt/grid_1_2.sp b/examples/spice_test_example_2/subckt/grid_1_2.sp deleted file mode 100644 index 676ca9093..000000000 --- a/examples/spice_test_example_2/subckt/grid_1_2.sp +++ /dev/null @@ -1,222 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Phyiscal Logic Block [1][2] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Grid[1][2] type_descriptor: io[0] ***** -.subckt grid[1][2]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[24] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[24] sram[1634]->outb sram[1634]->out gvdd_iopad[24] sgnd iopad -***** SRAM bits for IOPAD[24] ***** -*****1***** -Xsram[1634] sram->in sram[1634]->out sram[1634]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1634]->out) 0 -.nodeset V(sram[1634]->outb) vsp -.eom -.subckt grid[1][2]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[0]_mode[io_phy]_iopad[0] -Xdirect_interc[228] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[229] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[1] ***** -.subckt grid[1][2]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[25] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[25] sram[1635]->outb sram[1635]->out gvdd_iopad[25] sgnd iopad -***** SRAM bits for IOPAD[25] ***** -*****1***** -Xsram[1635] sram->in sram[1635]->out sram[1635]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1635]->out) 0 -.nodeset V(sram[1635]->outb) vsp -.eom -.subckt grid[1][2]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[1]_mode[io_phy]_iopad[0] -Xdirect_interc[230] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[231] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[2] ***** -.subckt grid[1][2]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[26] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[26] sram[1636]->outb sram[1636]->out gvdd_iopad[26] sgnd iopad -***** SRAM bits for IOPAD[26] ***** -*****1***** -Xsram[1636] sram->in sram[1636]->out sram[1636]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1636]->out) 0 -.nodeset V(sram[1636]->outb) vsp -.eom -.subckt grid[1][2]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[2]_mode[io_phy]_iopad[0] -Xdirect_interc[232] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[233] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[3] ***** -.subckt grid[1][2]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[27] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[27] sram[1637]->outb sram[1637]->out gvdd_iopad[27] sgnd iopad -***** SRAM bits for IOPAD[27] ***** -*****1***** -Xsram[1637] sram->in sram[1637]->out sram[1637]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1637]->out) 0 -.nodeset V(sram[1637]->outb) vsp -.eom -.subckt grid[1][2]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[3]_mode[io_phy]_iopad[0] -Xdirect_interc[234] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[235] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[4] ***** -.subckt grid[1][2]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[28] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[28] sram[1638]->outb sram[1638]->out gvdd_iopad[28] sgnd iopad -***** SRAM bits for IOPAD[28] ***** -*****1***** -Xsram[1638] sram->in sram[1638]->out sram[1638]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1638]->out) 0 -.nodeset V(sram[1638]->outb) vsp -.eom -.subckt grid[1][2]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[4]_mode[io_phy]_iopad[0] -Xdirect_interc[236] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[237] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[5] ***** -.subckt grid[1][2]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[29] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[29] sram[1639]->outb sram[1639]->out gvdd_iopad[29] sgnd iopad -***** SRAM bits for IOPAD[29] ***** -*****1***** -Xsram[1639] sram->in sram[1639]->out sram[1639]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1639]->out) 0 -.nodeset V(sram[1639]->outb) vsp -.eom -.subckt grid[1][2]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[5]_mode[io_phy]_iopad[0] -Xdirect_interc[238] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[239] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[6] ***** -***** Logical block mapped to this IO: out_Q0 ***** -.subckt grid[1][2]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[30] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[30] sram[1640]->out sram[1640]->outb gvdd_iopad[30] sgnd iopad -***** SRAM bits for IOPAD[30] ***** -*****0***** -Xsram[1640] sram->in sram[1640]->out sram[1640]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1640]->out) 0 -.nodeset V(sram[1640]->outb) vsp -.eom -.subckt grid[1][2]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[6]_mode[io_phy]_iopad[0] -Xdirect_interc[240] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[241] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2] type_descriptor: io[7] ***** -.subckt grid[1][2]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[31] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[31] sram[1641]->outb sram[1641]->out gvdd_iopad[31] sgnd iopad -***** SRAM bits for IOPAD[31] ***** -*****1***** -Xsram[1641] sram->in sram[1641]->out sram[1641]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1641]->out) 0 -.nodeset V(sram[1641]->outb) vsp -.eom -.subckt grid[1][2]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[1][2]_io[7]_mode[io_phy]_iopad[0] -Xdirect_interc[242] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[243] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[1][2], Capactity: 8 ***** -***** Top Protocol ***** -.subckt grid[1][2] -+ bottom_height[0]_pin[0] -+ bottom_height[0]_pin[1] -+ bottom_height[0]_pin[2] -+ bottom_height[0]_pin[3] -+ bottom_height[0]_pin[4] -+ bottom_height[0]_pin[5] -+ bottom_height[0]_pin[6] -+ bottom_height[0]_pin[7] -+ bottom_height[0]_pin[8] -+ bottom_height[0]_pin[9] -+ bottom_height[0]_pin[10] -+ bottom_height[0]_pin[11] -+ bottom_height[0]_pin[12] -+ bottom_height[0]_pin[13] -+ bottom_height[0]_pin[14] -+ bottom_height[0]_pin[15] -+ svdd sgnd -Xgrid[1][2][0] -+ bottom_height[0]_pin[0] -+ bottom_height[0]_pin[1] -+ svdd sgnd grid[1][2]_io[0]_mode[io_phy] -Xgrid[1][2][1] -+ bottom_height[0]_pin[2] -+ bottom_height[0]_pin[3] -+ svdd sgnd grid[1][2]_io[1]_mode[io_phy] -Xgrid[1][2][2] -+ bottom_height[0]_pin[4] -+ bottom_height[0]_pin[5] -+ svdd sgnd grid[1][2]_io[2]_mode[io_phy] -Xgrid[1][2][3] -+ bottom_height[0]_pin[6] -+ bottom_height[0]_pin[7] -+ svdd sgnd grid[1][2]_io[3]_mode[io_phy] -Xgrid[1][2][4] -+ bottom_height[0]_pin[8] -+ bottom_height[0]_pin[9] -+ svdd sgnd grid[1][2]_io[4]_mode[io_phy] -Xgrid[1][2][5] -+ bottom_height[0]_pin[10] -+ bottom_height[0]_pin[11] -+ svdd sgnd grid[1][2]_io[5]_mode[io_phy] -Xgrid[1][2][6] -+ bottom_height[0]_pin[12] -+ bottom_height[0]_pin[13] -+ svdd sgnd grid[1][2]_io[6]_mode[io_phy] -Xgrid[1][2][7] -+ bottom_height[0]_pin[14] -+ bottom_height[0]_pin[15] -+ svdd sgnd grid[1][2]_io[7]_mode[io_phy] -.eom diff --git a/examples/spice_test_example_2/subckt/grid_2_1.sp b/examples/spice_test_example_2/subckt/grid_2_1.sp deleted file mode 100644 index 6afda0dcd..000000000 --- a/examples/spice_test_example_2/subckt/grid_2_1.sp +++ /dev/null @@ -1,221 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Phyiscal Logic Block [2][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Grid[2][1] type_descriptor: io[0] ***** -.subckt grid[2][1]_io[0]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[8] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[8] sram[1618]->outb sram[1618]->out gvdd_iopad[8] sgnd iopad -***** SRAM bits for IOPAD[8] ***** -*****1***** -Xsram[1618] sram->in sram[1618]->out sram[1618]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1618]->out) 0 -.nodeset V(sram[1618]->outb) vsp -.eom -.subckt grid[2][1]_io[0]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[0]_mode[io_phy]_iopad[0] -Xdirect_interc[196] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[197] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[1] ***** -.subckt grid[2][1]_io[1]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[9] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[9] sram[1619]->outb sram[1619]->out gvdd_iopad[9] sgnd iopad -***** SRAM bits for IOPAD[9] ***** -*****1***** -Xsram[1619] sram->in sram[1619]->out sram[1619]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1619]->out) 0 -.nodeset V(sram[1619]->outb) vsp -.eom -.subckt grid[2][1]_io[1]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[1]_mode[io_phy]_iopad[0] -Xdirect_interc[198] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[199] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[2] ***** -.subckt grid[2][1]_io[2]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[10] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[10] sram[1620]->outb sram[1620]->out gvdd_iopad[10] sgnd iopad -***** SRAM bits for IOPAD[10] ***** -*****1***** -Xsram[1620] sram->in sram[1620]->out sram[1620]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1620]->out) 0 -.nodeset V(sram[1620]->outb) vsp -.eom -.subckt grid[2][1]_io[2]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[2]_mode[io_phy]_iopad[0] -Xdirect_interc[200] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[201] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[3] ***** -.subckt grid[2][1]_io[3]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[11] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[11] sram[1621]->outb sram[1621]->out gvdd_iopad[11] sgnd iopad -***** SRAM bits for IOPAD[11] ***** -*****1***** -Xsram[1621] sram->in sram[1621]->out sram[1621]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1621]->out) 0 -.nodeset V(sram[1621]->outb) vsp -.eom -.subckt grid[2][1]_io[3]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[3]_mode[io_phy]_iopad[0] -Xdirect_interc[202] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[203] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[4] ***** -.subckt grid[2][1]_io[4]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[12] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[12] sram[1622]->outb sram[1622]->out gvdd_iopad[12] sgnd iopad -***** SRAM bits for IOPAD[12] ***** -*****1***** -Xsram[1622] sram->in sram[1622]->out sram[1622]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1622]->out) 0 -.nodeset V(sram[1622]->outb) vsp -.eom -.subckt grid[2][1]_io[4]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[4]_mode[io_phy]_iopad[0] -Xdirect_interc[204] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[205] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[5] ***** -.subckt grid[2][1]_io[5]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[13] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[13] sram[1623]->outb sram[1623]->out gvdd_iopad[13] sgnd iopad -***** SRAM bits for IOPAD[13] ***** -*****1***** -Xsram[1623] sram->in sram[1623]->out sram[1623]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1623]->out) 0 -.nodeset V(sram[1623]->outb) vsp -.eom -.subckt grid[2][1]_io[5]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[5]_mode[io_phy]_iopad[0] -Xdirect_interc[206] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[207] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[6] ***** -.subckt grid[2][1]_io[6]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[14] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[14] sram[1624]->outb sram[1624]->out gvdd_iopad[14] sgnd iopad -***** SRAM bits for IOPAD[14] ***** -*****1***** -Xsram[1624] sram->in sram[1624]->out sram[1624]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1624]->out) 0 -.nodeset V(sram[1624]->outb) vsp -.eom -.subckt grid[2][1]_io[6]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[6]_mode[io_phy]_iopad[0] -Xdirect_interc[208] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[209] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1] type_descriptor: io[7] ***** -.subckt grid[2][1]_io[7]_mode[io_phy]_iopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd -Xiopad[15] -***** BEGIN Global ports of SPICE_MODEL(iopad) ***** -+ zin[0] -***** END Global ports of SPICE_MODEL(iopad) ***** -+ iopad[0]->outpad[0] iopad[0]->inpad[0] gfpga_pad_iopad[15] sram[1625]->outb sram[1625]->out gvdd_iopad[15] sgnd iopad -***** SRAM bits for IOPAD[15] ***** -*****1***** -Xsram[1625] sram->in sram[1625]->out sram[1625]->outb gvdd_sram_io sgnd sram6T -.nodeset V(sram[1625]->out) 0 -.nodeset V(sram[1625]->outb) vsp -.eom -.subckt grid[2][1]_io[7]_mode[io_phy] mode[io_phy]->outpad[0] mode[io_phy]->inpad[0] svdd sgnd -Xiopad[0] iopad[0]->outpad[0] iopad[0]->inpad[0] svdd sgnd grid[2][1]_io[7]_mode[io_phy]_iopad[0] -Xdirect_interc[210] iopad[0]->inpad[0] mode[io_phy]->inpad[0] gvdd_local_interc sgnd direct_interc -Xdirect_interc[211] mode[io_phy]->outpad[0] iopad[0]->outpad[0] gvdd_local_interc sgnd direct_interc -.eom -***** END ***** - -***** Grid[2][1], Capactity: 8 ***** -***** Top Protocol ***** -.subckt grid[2][1] -+ left_height[0]_pin[0] -+ left_height[0]_pin[1] -+ left_height[0]_pin[2] -+ left_height[0]_pin[3] -+ left_height[0]_pin[4] -+ left_height[0]_pin[5] -+ left_height[0]_pin[6] -+ left_height[0]_pin[7] -+ left_height[0]_pin[8] -+ left_height[0]_pin[9] -+ left_height[0]_pin[10] -+ left_height[0]_pin[11] -+ left_height[0]_pin[12] -+ left_height[0]_pin[13] -+ left_height[0]_pin[14] -+ left_height[0]_pin[15] -+ svdd sgnd -Xgrid[2][1][0] -+ left_height[0]_pin[0] -+ left_height[0]_pin[1] -+ svdd sgnd grid[2][1]_io[0]_mode[io_phy] -Xgrid[2][1][1] -+ left_height[0]_pin[2] -+ left_height[0]_pin[3] -+ svdd sgnd grid[2][1]_io[1]_mode[io_phy] -Xgrid[2][1][2] -+ left_height[0]_pin[4] -+ left_height[0]_pin[5] -+ svdd sgnd grid[2][1]_io[2]_mode[io_phy] -Xgrid[2][1][3] -+ left_height[0]_pin[6] -+ left_height[0]_pin[7] -+ svdd sgnd grid[2][1]_io[3]_mode[io_phy] -Xgrid[2][1][4] -+ left_height[0]_pin[8] -+ left_height[0]_pin[9] -+ svdd sgnd grid[2][1]_io[4]_mode[io_phy] -Xgrid[2][1][5] -+ left_height[0]_pin[10] -+ left_height[0]_pin[11] -+ svdd sgnd grid[2][1]_io[5]_mode[io_phy] -Xgrid[2][1][6] -+ left_height[0]_pin[12] -+ left_height[0]_pin[13] -+ svdd sgnd grid[2][1]_io[6]_mode[io_phy] -Xgrid[2][1][7] -+ left_height[0]_pin[14] -+ left_height[0]_pin[15] -+ svdd sgnd grid[2][1]_io[7]_mode[io_phy] -.eom diff --git a/examples/spice_test_example_2/subckt/grid_header.sp b/examples/spice_test_example_2/subckt/grid_header.sp deleted file mode 100644 index d8e48031a..000000000 --- a/examples/spice_test_example_2/subckt/grid_header.sp +++ /dev/null @@ -1,13 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Header file * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -.include './spice_test_example_2/subckt/grid_1_2.sp' -.include './spice_test_example_2/subckt/grid_1_0.sp' -.include './spice_test_example_2/subckt/grid_2_1.sp' -.include './spice_test_example_2/subckt/grid_0_1.sp' -.include './spice_test_example_2/subckt/grid_1_1.sp' diff --git a/examples/spice_test_example_2/subckt/inv_buf_trans_gate.sp b/examples/spice_test_example_2/subckt/inv_buf_trans_gate.sp deleted file mode 100644 index 185b4e8a8..000000000 --- a/examples/spice_test_example_2/subckt/inv_buf_trans_gate.sp +++ /dev/null @@ -1,76 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Inverter, Buffer, Trans. Gate * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -* Inverter -.subckt inv in out svdd sgnd size=1 -Xn0_inv out in sgnd sgnd vpr_nmos L=nl W='size*wn' -Xp0_inv out in svdd svdd vpr_pmos L=pl W='size*beta*wp' -.eom inv - -* Powergated Inverter -.subckt pg_inv en enb in out svdd sgnd size=1 pg_size=1 -Xn0_inv out in sgnd_pg sgnd vpr_nmos L=nl W='size*wn' -Xp0_inv out in svdd_pg svdd vpr_pmos L=pl W='size*beta*wp' -Xn0_inv_pg sgnd_pg en sgnd sgnd vpr_nmos L=nl W='pg_size*wn' -Xp0_inv_pg svdd_pg enb svdd svdd vpr_pmos L=pl W='pg_size*beta*wp' -.eom inv - -* Buffer -.subckt buf in out svdd sgnd size=2 base_size=1 -Xinv0 in mid svdd sgnd inv base_size='base_size' -Xinv1 mid out svdd sgnd inv size='size*base_size' -.eom buf - -* Power-gated Buffer -.subckt pg_buf en enb in out svdd sgnd size=2 pg_size=2 -Xinv0 en enb in mid svdd sgnd pg_inv size=1 pg_size=1 -Xinv1 en enb mid out svdd sgnd pg_inv size=size pg_size=size -.eom buf - -* Transmission Gate (Complementary Pass Transistor) -.subckt cpt in out sel sel_inv svdd sgnd nmos_size=1 pmos_size=1 -Xn0_cpt in sel out sgnd vpr_nmos L=nl W='nmos_size*wn' -Xp0_cpt in sel_inv out svdd vpr_pmos L=pl W='pmos_size*wp' -.eom cpt - -.subckt tapbuf_level2_f4 in out svdd sgnd -Rinv_in in in_lvl0 0 -Xinv_lvl0_no0 in_lvl0 in_lvl1 svdd sgnd inv -Xinv_lvl1_no0 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no1 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no2 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no3 in_lvl1 in_lvl2 svdd sgnd inv -Rinv_out in_lvl2 out 0 -.eom - -.subckt tapbuf_level3_f4 in out svdd sgnd -Rinv_in in in_lvl0 0 -Xinv_lvl0_no0 in_lvl0 in_lvl1 svdd sgnd inv -Xinv_lvl1_no0 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no1 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no2 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl1_no3 in_lvl1 in_lvl2 svdd sgnd inv -Xinv_lvl2_no0 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no1 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no2 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no3 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no4 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no5 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no6 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no7 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no8 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no9 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no10 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no11 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no12 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no13 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no14 in_lvl2 in_lvl3 svdd sgnd inv -Xinv_lvl2_no15 in_lvl2 in_lvl3 svdd sgnd inv -Rinv_out in_lvl3 out 0 -.eom - diff --git a/examples/spice_test_example_2/subckt/luts.sp b/examples/spice_test_example_2/subckt/luts.sp deleted file mode 100644 index 274b1f45b..000000000 --- a/examples/spice_test_example_2/subckt/luts.sp +++ /dev/null @@ -1,30 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: LUTs * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Auto-generated LUT info: spice_model_name = lut6, size = 6 ***** -.subckt lut6 in0 in1 in2 in3 in4 in5 out sram0 sram1 sram2 sram3 sram4 sram5 sram6 sram7 sram8 sram9 sram10 sram11 sram12 sram13 sram14 sram15 sram16 sram17 sram18 sram19 sram20 sram21 sram22 sram23 sram24 sram25 sram26 sram27 sram28 sram29 sram30 sram31 sram32 sram33 sram34 sram35 sram36 sram37 sram38 sram39 sram40 sram41 sram42 sram43 sram44 sram45 sram46 sram47 sram48 sram49 sram50 sram51 sram52 sram53 sram54 sram55 sram56 sram57 sram58 sram59 sram60 sram61 sram62 sram63 svdd sgnd -Xinv0_in0_no0 in0 lut_mux_in0_inv svdd sgnd inv size='4' -Xbuf4_in0 in0 lut_mux_in0 svdd sgnd tapbuf_level2_f4 - -Xinv0_in1_no0 in1 lut_mux_in1_inv svdd sgnd inv size='4' -Xbuf4_in1 in1 lut_mux_in1 svdd sgnd tapbuf_level2_f4 - -Xinv0_in2_no0 in2 lut_mux_in2_inv svdd sgnd inv size='4' -Xbuf4_in2 in2 lut_mux_in2 svdd sgnd tapbuf_level2_f4 - -Xinv0_in3_no0 in3 lut_mux_in3_inv svdd sgnd inv size='4' -Xbuf4_in3 in3 lut_mux_in3 svdd sgnd tapbuf_level2_f4 - -Xinv0_in4_no0 in4 lut_mux_in4_inv svdd sgnd inv size='4' -Xbuf4_in4 in4 lut_mux_in4 svdd sgnd tapbuf_level2_f4 - -Xinv0_in5_no0 in5 lut_mux_in5_inv svdd sgnd inv size='4' -Xbuf4_in5 in5 lut_mux_in5 svdd sgnd tapbuf_level2_f4 - -Xlut_mux sram0 sram1 sram2 sram3 sram4 sram5 sram6 sram7 sram8 sram9 sram10 sram11 sram12 sram13 sram14 sram15 sram16 sram17 sram18 sram19 sram20 sram21 sram22 sram23 sram24 sram25 sram26 sram27 sram28 sram29 sram30 sram31 sram32 sram33 sram34 sram35 sram36 sram37 sram38 sram39 sram40 sram41 sram42 sram43 sram44 sram45 sram46 sram47 sram48 sram49 sram50 sram51 sram52 sram53 sram54 sram55 sram56 sram57 sram58 sram59 sram60 sram61 sram62 sram63 out lut_mux_in0 lut_mux_in0_inv lut_mux_in1 lut_mux_in1_inv lut_mux_in2 lut_mux_in2_inv lut_mux_in3 lut_mux_in3_inv lut_mux_in4 lut_mux_in4_inv lut_mux_in5 lut_mux_in5_inv svdd sgnd lut6_mux_size64 -.eom diff --git a/examples/spice_test_example_2/subckt/muxes.sp b/examples/spice_test_example_2/subckt/muxes.sp deleted file mode 100644 index 8cc30543c..000000000 --- a/examples/spice_test_example_2/subckt/muxes.sp +++ /dev/null @@ -1,284 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: MUXes used in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -.subckt mux_2level_tapbuf_size16_basis in0 in1 in2 in3 out sel0 sel_inv0 sel1 sel_inv1 sel2 sel_inv2 sel3 sel_inv3 svdd sgnd -Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_2level_tapbuf_pgl_nmos_size' pmos_size='mux_2level_tapbuf_pgl_pmos_size' -Xcpt_1 in1 out sel1 sel_inv1 svdd sgnd cpt nmos_size='mux_2level_tapbuf_pgl_nmos_size' pmos_size='mux_2level_tapbuf_pgl_pmos_size' -Xcpt_2 in2 out sel2 sel_inv2 svdd sgnd cpt nmos_size='mux_2level_tapbuf_pgl_nmos_size' pmos_size='mux_2level_tapbuf_pgl_pmos_size' -Xcpt_3 in3 out sel3 sel_inv3 svdd sgnd cpt nmos_size='mux_2level_tapbuf_pgl_nmos_size' pmos_size='mux_2level_tapbuf_pgl_pmos_size' -.eom - -***** CMOS MUX info: spice_model_name=mux_2level_tapbuf, size=16, structure: multi-level ***** -.subckt mux_2level_tapbuf_size16 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 in15 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 sram4 sram_inv4 sram5 sram_inv5 sram6 sram_inv6 sram7 sram_inv7 svdd sgnd -Xmux_basis_no0 mux2_l2_in0 mux2_l2_in1 mux2_l2_in2 mux2_l2_in3 mux2_l1_in0 sram4 sram_inv4 sram5 sram_inv5 sram6 sram_inv6 sram7 sram_inv7 svdd sgnd mux_2level_tapbuf_size16_basis -Xmux_basis_no1 mux2_l2_in4 mux2_l2_in5 mux2_l2_in6 mux2_l2_in7 mux2_l1_in1 sram4 sram_inv4 sram5 sram_inv5 sram6 sram_inv6 sram7 sram_inv7 svdd sgnd mux_2level_tapbuf_size16_basis -Xmux_basis_no2 mux2_l2_in8 mux2_l2_in9 mux2_l2_in10 mux2_l2_in11 mux2_l1_in2 sram4 sram_inv4 sram5 sram_inv5 sram6 sram_inv6 sram7 sram_inv7 svdd sgnd mux_2level_tapbuf_size16_basis -Xmux_basis_no3 mux2_l2_in12 mux2_l2_in13 mux2_l2_in14 mux2_l2_in15 mux2_l1_in3 sram4 sram_inv4 sram5 sram_inv5 sram6 sram_inv6 sram7 sram_inv7 svdd sgnd mux_2level_tapbuf_size16_basis -Xmux_basis_no4 mux2_l1_in0 mux2_l1_in1 mux2_l1_in2 mux2_l1_in3 mux2_l0_in0 sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 svdd sgnd mux_2level_tapbuf_size16_basis -Xinv0 in0 mux2_l2_in0 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv1 in1 mux2_l2_in1 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv2 in2 mux2_l2_in2 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv3 in3 mux2_l2_in3 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv4 in4 mux2_l2_in4 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv5 in5 mux2_l2_in5 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv6 in6 mux2_l2_in6 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv7 in7 mux2_l2_in7 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv8 in8 mux2_l2_in8 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv9 in9 mux2_l2_in9 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv10 in10 mux2_l2_in10 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv11 in11 mux2_l2_in11 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv12 in12 mux2_l2_in12 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv13 in13 mux2_l2_in13 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv14 in14 mux2_l2_in14 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xinv15 in15 mux2_l2_in15 svdd sgnd inv size='mux_2level_tapbuf_input_buf_size' -Xbuf_out mux2_l0_in0 out svdd sgnd tapbuf_level3_f4 -.eom -***** END CMOS MUX info: spice_model_name=mux_2level_tapbuf, size=16 ***** - -.subckt lut6_size64_basis in0 in1 out sel0 sel_inv0 svdd sgnd -Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='lut6_pgl_nmos_size' pmos_size='lut6_pgl_pmos_size' -Xcpt_1 in1 out sel_inv0 sel0 svdd sgnd cpt nmos_size='lut6_pgl_nmos_size' pmos_size='lut6_pgl_pmos_size' -.eom - -***** CMOS MUX info: spice_model_name= lut6_MUX, size=64 ***** -.subckt lut6_mux_size64 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 in15 in16 in17 in18 in19 in20 in21 in22 in23 in24 in25 in26 in27 in28 in29 in30 in31 in32 in33 in34 in35 in36 in37 in38 in39 in40 in41 in42 in43 in44 in45 in46 in47 in48 in49 in50 in51 in52 in53 in54 in55 in56 in57 in58 in59 in60 in61 in62 in63 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 sram4 sram_inv4 sram5 sram_inv5 svdd sgnd -Xmux_basis_no0 mux2_l6_in0 mux2_l6_in1 mux2_l5_in0 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no1 mux2_l6_in2 mux2_l6_in3 mux2_l5_in1 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no2 mux2_l6_in4 mux2_l6_in5 mux2_l5_in2 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no3 mux2_l6_in6 mux2_l6_in7 mux2_l5_in3 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no4 mux2_l6_in8 mux2_l6_in9 mux2_l5_in4 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no5 mux2_l6_in10 mux2_l6_in11 mux2_l5_in5 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no6 mux2_l6_in12 mux2_l6_in13 mux2_l5_in6 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no7 mux2_l6_in14 mux2_l6_in15 mux2_l5_in7 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no8 mux2_l6_in16 mux2_l6_in17 mux2_l5_in8 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no9 mux2_l6_in18 mux2_l6_in19 mux2_l5_in9 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no10 mux2_l6_in20 mux2_l6_in21 mux2_l5_in10 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no11 mux2_l6_in22 mux2_l6_in23 mux2_l5_in11 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no12 mux2_l6_in24 mux2_l6_in25 mux2_l5_in12 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no13 mux2_l6_in26 mux2_l6_in27 mux2_l5_in13 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no14 mux2_l6_in28 mux2_l6_in29 mux2_l5_in14 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no15 mux2_l6_in30 mux2_l6_in31 mux2_l5_in15 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no16 mux2_l6_in32 mux2_l6_in33 mux2_l5_in16 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no17 mux2_l6_in34 mux2_l6_in35 mux2_l5_in17 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no18 mux2_l6_in36 mux2_l6_in37 mux2_l5_in18 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no19 mux2_l6_in38 mux2_l6_in39 mux2_l5_in19 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no20 mux2_l6_in40 mux2_l6_in41 mux2_l5_in20 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no21 mux2_l6_in42 mux2_l6_in43 mux2_l5_in21 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no22 mux2_l6_in44 mux2_l6_in45 mux2_l5_in22 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no23 mux2_l6_in46 mux2_l6_in47 mux2_l5_in23 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no24 mux2_l6_in48 mux2_l6_in49 mux2_l5_in24 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no25 mux2_l6_in50 mux2_l6_in51 mux2_l5_in25 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no26 mux2_l6_in52 mux2_l6_in53 mux2_l5_in26 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no27 mux2_l6_in54 mux2_l6_in55 mux2_l5_in27 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no28 mux2_l6_in56 mux2_l6_in57 mux2_l5_in28 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no29 mux2_l6_in58 mux2_l6_in59 mux2_l5_in29 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no30 mux2_l6_in60 mux2_l6_in61 mux2_l5_in30 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no31 mux2_l6_in62 mux2_l6_in63 mux2_l5_in31 sram0 sram_inv0 svdd sgnd lut6_size64_basis -Xmux_basis_no32 mux2_l5_in0 mux2_l5_in1 mux2_l4_in0 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no33 mux2_l5_in2 mux2_l5_in3 mux2_l4_in1 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no34 mux2_l5_in4 mux2_l5_in5 mux2_l4_in2 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no35 mux2_l5_in6 mux2_l5_in7 mux2_l4_in3 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no36 mux2_l5_in8 mux2_l5_in9 mux2_l4_in4 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no37 mux2_l5_in10 mux2_l5_in11 mux2_l4_in5 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no38 mux2_l5_in12 mux2_l5_in13 mux2_l4_in6 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no39 mux2_l5_in14 mux2_l5_in15 mux2_l4_in7 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no40 mux2_l5_in16 mux2_l5_in17 mux2_l4_in8 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no41 mux2_l5_in18 mux2_l5_in19 mux2_l4_in9 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no42 mux2_l5_in20 mux2_l5_in21 mux2_l4_in10 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no43 mux2_l5_in22 mux2_l5_in23 mux2_l4_in11 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no44 mux2_l5_in24 mux2_l5_in25 mux2_l4_in12 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no45 mux2_l5_in26 mux2_l5_in27 mux2_l4_in13 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no46 mux2_l5_in28 mux2_l5_in29 mux2_l4_in14 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no47 mux2_l5_in30 mux2_l5_in31 mux2_l4_in15 sram1 sram_inv1 svdd sgnd lut6_size64_basis -Xmux_basis_no48 mux2_l4_in0 mux2_l4_in1 mux2_l3_in0 sram2 sram_inv2 svdd sgnd lut6_size64_basis -Xmux_basis_no49 mux2_l4_in2 mux2_l4_in3 mux2_l3_in1 sram2 sram_inv2 svdd sgnd lut6_size64_basis -Xmux_basis_no50 mux2_l4_in4 mux2_l4_in5 mux2_l3_in2 sram2 sram_inv2 svdd sgnd lut6_size64_basis -Xmux_basis_no51 mux2_l4_in6 mux2_l4_in7 mux2_l3_in3 sram2 sram_inv2 svdd sgnd lut6_size64_basis -Xmux_basis_no52 mux2_l4_in8 mux2_l4_in9 mux2_l3_in4 sram2 sram_inv2 svdd sgnd lut6_size64_basis -Xmux_basis_no53 mux2_l4_in10 mux2_l4_in11 mux2_l3_in5 sram2 sram_inv2 svdd sgnd lut6_size64_basis -Xmux_basis_no54 mux2_l4_in12 mux2_l4_in13 mux2_l3_in6 sram2 sram_inv2 svdd sgnd lut6_size64_basis -Xmux_basis_no55 mux2_l4_in14 mux2_l4_in15 mux2_l3_in7 sram2 sram_inv2 svdd sgnd lut6_size64_basis -Xmux_basis_no56 mux2_l3_in0 mux2_l3_in1 mux2_l2_in0 sram3 sram_inv3 svdd sgnd lut6_size64_basis -Xmux_basis_no57 mux2_l3_in2 mux2_l3_in3 mux2_l2_in1 sram3 sram_inv3 svdd sgnd lut6_size64_basis -Xmux_basis_no58 mux2_l3_in4 mux2_l3_in5 mux2_l2_in2 sram3 sram_inv3 svdd sgnd lut6_size64_basis -Xmux_basis_no59 mux2_l3_in6 mux2_l3_in7 mux2_l2_in3 sram3 sram_inv3 svdd sgnd lut6_size64_basis -Xmux_basis_no60 mux2_l2_in0 mux2_l2_in1 mux2_l1_in0 sram4 sram_inv4 svdd sgnd lut6_size64_basis -Xmux_basis_no61 mux2_l2_in2 mux2_l2_in3 mux2_l1_in1 sram4 sram_inv4 svdd sgnd lut6_size64_basis -Xmux_basis_no62 mux2_l1_in0 mux2_l1_in1 mux2_l0_in0 sram5 sram_inv5 svdd sgnd lut6_size64_basis -Xinv0 in0 mux2_l6_in0 svdd sgnd inv size='lut6_input_buf_size' -Xinv1 in1 mux2_l6_in1 svdd sgnd inv size='lut6_input_buf_size' -Xinv2 in2 mux2_l6_in2 svdd sgnd inv size='lut6_input_buf_size' -Xinv3 in3 mux2_l6_in3 svdd sgnd inv size='lut6_input_buf_size' -Xinv4 in4 mux2_l6_in4 svdd sgnd inv size='lut6_input_buf_size' -Xinv5 in5 mux2_l6_in5 svdd sgnd inv size='lut6_input_buf_size' -Xinv6 in6 mux2_l6_in6 svdd sgnd inv size='lut6_input_buf_size' -Xinv7 in7 mux2_l6_in7 svdd sgnd inv size='lut6_input_buf_size' -Xinv8 in8 mux2_l6_in8 svdd sgnd inv size='lut6_input_buf_size' -Xinv9 in9 mux2_l6_in9 svdd sgnd inv size='lut6_input_buf_size' -Xinv10 in10 mux2_l6_in10 svdd sgnd inv size='lut6_input_buf_size' -Xinv11 in11 mux2_l6_in11 svdd sgnd inv size='lut6_input_buf_size' -Xinv12 in12 mux2_l6_in12 svdd sgnd inv size='lut6_input_buf_size' -Xinv13 in13 mux2_l6_in13 svdd sgnd inv size='lut6_input_buf_size' -Xinv14 in14 mux2_l6_in14 svdd sgnd inv size='lut6_input_buf_size' -Xinv15 in15 mux2_l6_in15 svdd sgnd inv size='lut6_input_buf_size' -Xinv16 in16 mux2_l6_in16 svdd sgnd inv size='lut6_input_buf_size' -Xinv17 in17 mux2_l6_in17 svdd sgnd inv size='lut6_input_buf_size' -Xinv18 in18 mux2_l6_in18 svdd sgnd inv size='lut6_input_buf_size' -Xinv19 in19 mux2_l6_in19 svdd sgnd inv size='lut6_input_buf_size' -Xinv20 in20 mux2_l6_in20 svdd sgnd inv size='lut6_input_buf_size' -Xinv21 in21 mux2_l6_in21 svdd sgnd inv size='lut6_input_buf_size' -Xinv22 in22 mux2_l6_in22 svdd sgnd inv size='lut6_input_buf_size' -Xinv23 in23 mux2_l6_in23 svdd sgnd inv size='lut6_input_buf_size' -Xinv24 in24 mux2_l6_in24 svdd sgnd inv size='lut6_input_buf_size' -Xinv25 in25 mux2_l6_in25 svdd sgnd inv size='lut6_input_buf_size' -Xinv26 in26 mux2_l6_in26 svdd sgnd inv size='lut6_input_buf_size' -Xinv27 in27 mux2_l6_in27 svdd sgnd inv size='lut6_input_buf_size' -Xinv28 in28 mux2_l6_in28 svdd sgnd inv size='lut6_input_buf_size' -Xinv29 in29 mux2_l6_in29 svdd sgnd inv size='lut6_input_buf_size' -Xinv30 in30 mux2_l6_in30 svdd sgnd inv size='lut6_input_buf_size' -Xinv31 in31 mux2_l6_in31 svdd sgnd inv size='lut6_input_buf_size' -Xinv32 in32 mux2_l6_in32 svdd sgnd inv size='lut6_input_buf_size' -Xinv33 in33 mux2_l6_in33 svdd sgnd inv size='lut6_input_buf_size' -Xinv34 in34 mux2_l6_in34 svdd sgnd inv size='lut6_input_buf_size' -Xinv35 in35 mux2_l6_in35 svdd sgnd inv size='lut6_input_buf_size' -Xinv36 in36 mux2_l6_in36 svdd sgnd inv size='lut6_input_buf_size' -Xinv37 in37 mux2_l6_in37 svdd sgnd inv size='lut6_input_buf_size' -Xinv38 in38 mux2_l6_in38 svdd sgnd inv size='lut6_input_buf_size' -Xinv39 in39 mux2_l6_in39 svdd sgnd inv size='lut6_input_buf_size' -Xinv40 in40 mux2_l6_in40 svdd sgnd inv size='lut6_input_buf_size' -Xinv41 in41 mux2_l6_in41 svdd sgnd inv size='lut6_input_buf_size' -Xinv42 in42 mux2_l6_in42 svdd sgnd inv size='lut6_input_buf_size' -Xinv43 in43 mux2_l6_in43 svdd sgnd inv size='lut6_input_buf_size' -Xinv44 in44 mux2_l6_in44 svdd sgnd inv size='lut6_input_buf_size' -Xinv45 in45 mux2_l6_in45 svdd sgnd inv size='lut6_input_buf_size' -Xinv46 in46 mux2_l6_in46 svdd sgnd inv size='lut6_input_buf_size' -Xinv47 in47 mux2_l6_in47 svdd sgnd inv size='lut6_input_buf_size' -Xinv48 in48 mux2_l6_in48 svdd sgnd inv size='lut6_input_buf_size' -Xinv49 in49 mux2_l6_in49 svdd sgnd inv size='lut6_input_buf_size' -Xinv50 in50 mux2_l6_in50 svdd sgnd inv size='lut6_input_buf_size' -Xinv51 in51 mux2_l6_in51 svdd sgnd inv size='lut6_input_buf_size' -Xinv52 in52 mux2_l6_in52 svdd sgnd inv size='lut6_input_buf_size' -Xinv53 in53 mux2_l6_in53 svdd sgnd inv size='lut6_input_buf_size' -Xinv54 in54 mux2_l6_in54 svdd sgnd inv size='lut6_input_buf_size' -Xinv55 in55 mux2_l6_in55 svdd sgnd inv size='lut6_input_buf_size' -Xinv56 in56 mux2_l6_in56 svdd sgnd inv size='lut6_input_buf_size' -Xinv57 in57 mux2_l6_in57 svdd sgnd inv size='lut6_input_buf_size' -Xinv58 in58 mux2_l6_in58 svdd sgnd inv size='lut6_input_buf_size' -Xinv59 in59 mux2_l6_in59 svdd sgnd inv size='lut6_input_buf_size' -Xinv60 in60 mux2_l6_in60 svdd sgnd inv size='lut6_input_buf_size' -Xinv61 in61 mux2_l6_in61 svdd sgnd inv size='lut6_input_buf_size' -Xinv62 in62 mux2_l6_in62 svdd sgnd inv size='lut6_input_buf_size' -Xinv63 in63 mux2_l6_in63 svdd sgnd inv size='lut6_input_buf_size' -Xinv_out mux2_l0_in0 out svdd sgnd inv size='lut6_output_buf_size' -.eom -***** END CMOS MUX info: spice_model_name=lut6, size=64 ***** - -.subckt mux_2level_size50_basis in0 in1 in2 in3 in4 in5 in6 in7 out sel0 sel_inv0 sel1 sel_inv1 sel2 sel_inv2 sel3 sel_inv3 sel4 sel_inv4 sel5 sel_inv5 sel6 sel_inv6 sel7 sel_inv7 svdd sgnd -Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -Xcpt_1 in1 out sel1 sel_inv1 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -Xcpt_2 in2 out sel2 sel_inv2 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -Xcpt_3 in3 out sel3 sel_inv3 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -Xcpt_4 in4 out sel4 sel_inv4 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -Xcpt_5 in5 out sel5 sel_inv5 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -Xcpt_6 in6 out sel6 sel_inv6 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -Xcpt_7 in7 out sel7 sel_inv7 svdd sgnd cpt nmos_size='mux_2level_pgl_nmos_size' pmos_size='mux_2level_pgl_pmos_size' -.eom - -***** CMOS MUX info: spice_model_name=mux_2level, size=50, structure: multi-level ***** -.subckt mux_2level_size50 in0 in1 in2 in3 in4 in5 in6 in7 in8 in9 in10 in11 in12 in13 in14 in15 in16 in17 in18 in19 in20 in21 in22 in23 in24 in25 in26 in27 in28 in29 in30 in31 in32 in33 in34 in35 in36 in37 in38 in39 in40 in41 in42 in43 in44 in45 in46 in47 in48 in49 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 sram4 sram_inv4 sram5 sram_inv5 sram6 sram_inv6 sram7 sram_inv7 sram8 sram_inv8 sram9 sram_inv9 sram10 sram_inv10 sram11 sram_inv11 sram12 sram_inv12 sram13 sram_inv13 sram14 sram_inv14 sram15 sram_inv15 svdd sgnd -Xmux_basis_no0 mux2_l2_in0 mux2_l2_in1 mux2_l2_in2 mux2_l2_in3 mux2_l2_in4 mux2_l2_in5 mux2_l2_in6 mux2_l2_in7 mux2_l1_in0 sram8 sram_inv8 sram9 sram_inv9 sram10 sram_inv10 sram11 sram_inv11 sram12 sram_inv12 sram13 sram_inv13 sram14 sram_inv14 sram15 sram_inv15 svdd sgnd mux_2level_size50_basis -Xmux_basis_no1 mux2_l2_in8 mux2_l2_in9 mux2_l2_in10 mux2_l2_in11 mux2_l2_in12 mux2_l2_in13 mux2_l2_in14 mux2_l2_in15 mux2_l1_in1 sram8 sram_inv8 sram9 sram_inv9 sram10 sram_inv10 sram11 sram_inv11 sram12 sram_inv12 sram13 sram_inv13 sram14 sram_inv14 sram15 sram_inv15 svdd sgnd mux_2level_size50_basis -Xmux_basis_no2 mux2_l2_in16 mux2_l2_in17 mux2_l2_in18 mux2_l2_in19 mux2_l2_in20 mux2_l2_in21 mux2_l2_in22 mux2_l2_in23 mux2_l1_in2 sram8 sram_inv8 sram9 sram_inv9 sram10 sram_inv10 sram11 sram_inv11 sram12 sram_inv12 sram13 sram_inv13 sram14 sram_inv14 sram15 sram_inv15 svdd sgnd mux_2level_size50_basis -Xmux_basis_no3 mux2_l2_in24 mux2_l2_in25 mux2_l2_in26 mux2_l2_in27 mux2_l2_in28 mux2_l2_in29 mux2_l2_in30 mux2_l2_in31 mux2_l1_in3 sram8 sram_inv8 sram9 sram_inv9 sram10 sram_inv10 sram11 sram_inv11 sram12 sram_inv12 sram13 sram_inv13 sram14 sram_inv14 sram15 sram_inv15 svdd sgnd mux_2level_size50_basis -Xmux_basis_no4 mux2_l2_in32 mux2_l2_in33 mux2_l2_in34 mux2_l2_in35 mux2_l2_in36 mux2_l2_in37 mux2_l2_in38 mux2_l2_in39 mux2_l1_in4 sram8 sram_inv8 sram9 sram_inv9 sram10 sram_inv10 sram11 sram_inv11 sram12 sram_inv12 sram13 sram_inv13 sram14 sram_inv14 sram15 sram_inv15 svdd sgnd mux_2level_size50_basis -Xmux_basis_no5 mux2_l2_in40 mux2_l2_in41 mux2_l2_in42 mux2_l2_in43 mux2_l2_in44 mux2_l2_in45 mux2_l2_in46 mux2_l2_in47 mux2_l1_in5 sram8 sram_inv8 sram9 sram_inv9 sram10 sram_inv10 sram11 sram_inv11 sram12 sram_inv12 sram13 sram_inv13 sram14 sram_inv14 sram15 sram_inv15 svdd sgnd mux_2level_size50_basis -Xmux_basis_no6 mux2_l1_in0 mux2_l1_in1 mux2_l1_in2 mux2_l1_in3 mux2_l1_in4 mux2_l1_in5 mux2_l1_in6 mux2_l1_in7 mux2_l0_in0 sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 sram3 sram_inv3 sram4 sram_inv4 sram5 sram_inv5 sram6 sram_inv6 sram7 sram_inv7 svdd sgnd mux_2level_size50_basis -Xinv0 in0 mux2_l2_in0 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv1 in1 mux2_l2_in1 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv2 in2 mux2_l2_in2 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv3 in3 mux2_l2_in3 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv4 in4 mux2_l2_in4 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv5 in5 mux2_l2_in5 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv6 in6 mux2_l2_in6 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv7 in7 mux2_l2_in7 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv8 in8 mux2_l2_in8 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv9 in9 mux2_l2_in9 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv10 in10 mux2_l2_in10 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv11 in11 mux2_l2_in11 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv12 in12 mux2_l2_in12 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv13 in13 mux2_l2_in13 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv14 in14 mux2_l2_in14 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv15 in15 mux2_l2_in15 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv16 in16 mux2_l2_in16 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv17 in17 mux2_l2_in17 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv18 in18 mux2_l2_in18 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv19 in19 mux2_l2_in19 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv20 in20 mux2_l2_in20 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv21 in21 mux2_l2_in21 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv22 in22 mux2_l2_in22 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv23 in23 mux2_l2_in23 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv24 in24 mux2_l2_in24 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv25 in25 mux2_l2_in25 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv26 in26 mux2_l2_in26 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv27 in27 mux2_l2_in27 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv28 in28 mux2_l2_in28 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv29 in29 mux2_l2_in29 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv30 in30 mux2_l2_in30 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv31 in31 mux2_l2_in31 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv32 in32 mux2_l2_in32 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv33 in33 mux2_l2_in33 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv34 in34 mux2_l2_in34 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv35 in35 mux2_l2_in35 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv36 in36 mux2_l2_in36 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv37 in37 mux2_l2_in37 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv38 in38 mux2_l2_in38 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv39 in39 mux2_l2_in39 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv40 in40 mux2_l2_in40 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv41 in41 mux2_l2_in41 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv42 in42 mux2_l2_in42 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv43 in43 mux2_l2_in43 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv44 in44 mux2_l2_in44 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv45 in45 mux2_l2_in45 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv46 in46 mux2_l2_in46 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv47 in47 mux2_l2_in47 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv48 in48 mux2_l1_in6 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv49 in49 mux2_l1_in7 svdd sgnd inv size='mux_2level_input_buf_size' -Xinv_out mux2_l0_in0 out svdd sgnd inv size='mux_2level_output_buf_size' -.eom -***** END CMOS MUX info: spice_model_name=mux_2level, size=50 ***** - -.subckt mux_1level_tapbuf_size3_basis in0 in1 in2 out sel0 sel_inv0 sel1 sel_inv1 sel2 sel_inv2 svdd sgnd -Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size' -Xcpt_1 in1 out sel1 sel_inv1 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size' -Xcpt_2 in2 out sel2 sel_inv2 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size' -.eom - -***** CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=3, structure: one-level ***** -.subckt mux_1level_tapbuf_size3 in0 in1 in2 out sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 svdd sgnd -Xmux_basis_no0 mux2_l1_in0 mux2_l1_in1 mux2_l1_in2 mux2_l0_in0 sram0 sram_inv0 sram1 sram_inv1 sram2 sram_inv2 svdd sgnd mux_1level_tapbuf_size3_basis -Xinv0 in0 mux2_l1_in0 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size' -Xinv1 in1 mux2_l1_in1 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size' -Xinv2 in2 mux2_l1_in2 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size' -Xbuf_out mux2_l0_in0 out svdd sgnd tapbuf_level3_f4 -.eom -***** END CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=3 ***** - -.subckt mux_1level_tapbuf_size2_basis in0 in1 out sel0 sel_inv0 svdd sgnd -Xcpt_0 in0 out sel0 sel_inv0 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size' -Xcpt_1 in1 out sel_inv0 sel0 svdd sgnd cpt nmos_size='mux_1level_tapbuf_pgl_nmos_size' pmos_size='mux_1level_tapbuf_pgl_pmos_size' -.eom - -***** CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=2, structure: one-level ***** -.subckt mux_1level_tapbuf_size2 in0 in1 out sram0 sram_inv0 svdd sgnd -Xmux_basis_no0 mux2_l1_in0 mux2_l1_in1 mux2_l0_in0 sram0 sram_inv0 svdd sgnd mux_1level_tapbuf_size2_basis -Xinv0 in0 mux2_l1_in0 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size' -Xinv1 in1 mux2_l1_in1 svdd sgnd inv size='mux_1level_tapbuf_input_buf_size' -Xbuf_out mux2_l0_in0 out svdd sgnd tapbuf_level3_f4 -.eom -***** END CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=2 ***** - diff --git a/examples/spice_test_example_2/subckt/nmos_pmos.sp b/examples/spice_test_example_2/subckt/nmos_pmos.sp deleted file mode 100644 index 14798e493..000000000 --- a/examples/spice_test_example_2/subckt/nmos_pmos.sp +++ /dev/null @@ -1,25 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Standard and I/O NMOS and PMOS * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -* Standard NMOS -.subckt vpr_nmos drain gate source bulk L=nl W=wn -M1 drain gate source bulk nch L=L W=W -.eom vpr_nmos - -* Standard PMOS -.subckt vpr_pmos drain gate source bulk L=pl W=wp -M1 drain gate source bulk pch L=L W=W -.eom vpr_pmos -* I/O NMOS -.subckt vpr_io_nmos drain gate source bulk L=io_nl W=io_wn -M1 drain gate source bulk nch_25 L=L W=W -.eom vpr_io_nmos -* I/O PMOS -.subckt vpr_io_pmos drain gate source bulk L=io_pl W=io_wp -M1 drain gate source bulk pch_25 L=L W=W -.eom vpr_io_pmos diff --git a/examples/spice_test_example_2/subckt/routing_header.sp b/examples/spice_test_example_2/subckt/routing_header.sp deleted file mode 100644 index 92e07f666..000000000 --- a/examples/spice_test_example_2/subckt/routing_header.sp +++ /dev/null @@ -1,20 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Header file * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -.include './spice_test_example_2/subckt/cby_1_1.sp' -.include './spice_test_example_2/subckt/cby_0_1.sp' -.include './spice_test_example_2/subckt/cbx_1_1.sp' -.include './spice_test_example_2/subckt/cbx_1_0.sp' -.include './spice_test_example_2/subckt/sb_1_1.sp' -.include './spice_test_example_2/subckt/sb_1_0.sp' -.include './spice_test_example_2/subckt/sb_0_1.sp' -.include './spice_test_example_2/subckt/sb_0_0.sp' -.include './spice_test_example_2/subckt/chany_1_1.sp' -.include './spice_test_example_2/subckt/chany_0_1.sp' -.include './spice_test_example_2/subckt/chanx_1_1.sp' -.include './spice_test_example_2/subckt/chanx_1_0.sp' diff --git a/examples/spice_test_example_2/subckt/sb_0_0.sp b/examples/spice_test_example_2/subckt/sb_0_0.sp deleted file mode 100644 index 89261d945..000000000 --- a/examples/spice_test_example_2/subckt/sb_0_0.sp +++ /dev/null @@ -1,628 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Switch Block [0][0] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Switch Box[0][0] Sub-Circuit ***** -.subckt sb[0][0] -***** Inputs/outputs of top side ***** -+ chany[0][1]_out[0] chany[0][1]_in[1] chany[0][1]_out[2] chany[0][1]_in[3] chany[0][1]_out[4] chany[0][1]_in[5] chany[0][1]_out[6] chany[0][1]_in[7] chany[0][1]_out[8] chany[0][1]_in[9] chany[0][1]_out[10] chany[0][1]_in[11] chany[0][1]_out[12] chany[0][1]_in[13] chany[0][1]_out[14] chany[0][1]_in[15] chany[0][1]_out[16] chany[0][1]_in[17] chany[0][1]_out[18] chany[0][1]_in[19] chany[0][1]_out[20] chany[0][1]_in[21] chany[0][1]_out[22] chany[0][1]_in[23] chany[0][1]_out[24] chany[0][1]_in[25] chany[0][1]_out[26] chany[0][1]_in[27] chany[0][1]_out[28] chany[0][1]_in[29] chany[0][1]_out[30] chany[0][1]_in[31] chany[0][1]_out[32] chany[0][1]_in[33] chany[0][1]_out[34] chany[0][1]_in[35] chany[0][1]_out[36] chany[0][1]_in[37] chany[0][1]_out[38] chany[0][1]_in[39] chany[0][1]_out[40] chany[0][1]_in[41] chany[0][1]_out[42] chany[0][1]_in[43] chany[0][1]_out[44] chany[0][1]_in[45] chany[0][1]_out[46] chany[0][1]_in[47] chany[0][1]_out[48] chany[0][1]_in[49] chany[0][1]_out[50] chany[0][1]_in[51] chany[0][1]_out[52] chany[0][1]_in[53] chany[0][1]_out[54] chany[0][1]_in[55] chany[0][1]_out[56] chany[0][1]_in[57] chany[0][1]_out[58] chany[0][1]_in[59] chany[0][1]_out[60] chany[0][1]_in[61] chany[0][1]_out[62] chany[0][1]_in[63] chany[0][1]_out[64] chany[0][1]_in[65] chany[0][1]_out[66] chany[0][1]_in[67] chany[0][1]_out[68] chany[0][1]_in[69] chany[0][1]_out[70] chany[0][1]_in[71] chany[0][1]_out[72] chany[0][1]_in[73] chany[0][1]_out[74] chany[0][1]_in[75] chany[0][1]_out[76] chany[0][1]_in[77] chany[0][1]_out[78] chany[0][1]_in[79] chany[0][1]_out[80] chany[0][1]_in[81] chany[0][1]_out[82] chany[0][1]_in[83] chany[0][1]_out[84] chany[0][1]_in[85] chany[0][1]_out[86] chany[0][1]_in[87] chany[0][1]_out[88] chany[0][1]_in[89] chany[0][1]_out[90] chany[0][1]_in[91] chany[0][1]_out[92] chany[0][1]_in[93] chany[0][1]_out[94] chany[0][1]_in[95] chany[0][1]_out[96] chany[0][1]_in[97] chany[0][1]_out[98] chany[0][1]_in[99] -+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][47] -+ ***** Inputs/outputs of right side ***** -+ chanx[1][0]_out[0] chanx[1][0]_in[1] chanx[1][0]_out[2] chanx[1][0]_in[3] chanx[1][0]_out[4] chanx[1][0]_in[5] chanx[1][0]_out[6] chanx[1][0]_in[7] chanx[1][0]_out[8] chanx[1][0]_in[9] chanx[1][0]_out[10] chanx[1][0]_in[11] chanx[1][0]_out[12] chanx[1][0]_in[13] chanx[1][0]_out[14] chanx[1][0]_in[15] chanx[1][0]_out[16] chanx[1][0]_in[17] chanx[1][0]_out[18] chanx[1][0]_in[19] chanx[1][0]_out[20] chanx[1][0]_in[21] chanx[1][0]_out[22] chanx[1][0]_in[23] chanx[1][0]_out[24] chanx[1][0]_in[25] chanx[1][0]_out[26] chanx[1][0]_in[27] chanx[1][0]_out[28] chanx[1][0]_in[29] chanx[1][0]_out[30] chanx[1][0]_in[31] chanx[1][0]_out[32] chanx[1][0]_in[33] chanx[1][0]_out[34] chanx[1][0]_in[35] chanx[1][0]_out[36] chanx[1][0]_in[37] chanx[1][0]_out[38] chanx[1][0]_in[39] chanx[1][0]_out[40] chanx[1][0]_in[41] chanx[1][0]_out[42] chanx[1][0]_in[43] chanx[1][0]_out[44] chanx[1][0]_in[45] chanx[1][0]_out[46] chanx[1][0]_in[47] chanx[1][0]_out[48] chanx[1][0]_in[49] chanx[1][0]_out[50] chanx[1][0]_in[51] chanx[1][0]_out[52] chanx[1][0]_in[53] chanx[1][0]_out[54] chanx[1][0]_in[55] chanx[1][0]_out[56] chanx[1][0]_in[57] chanx[1][0]_out[58] chanx[1][0]_in[59] chanx[1][0]_out[60] chanx[1][0]_in[61] chanx[1][0]_out[62] chanx[1][0]_in[63] chanx[1][0]_out[64] chanx[1][0]_in[65] chanx[1][0]_out[66] chanx[1][0]_in[67] chanx[1][0]_out[68] chanx[1][0]_in[69] chanx[1][0]_out[70] chanx[1][0]_in[71] chanx[1][0]_out[72] chanx[1][0]_in[73] chanx[1][0]_out[74] chanx[1][0]_in[75] chanx[1][0]_out[76] chanx[1][0]_in[77] chanx[1][0]_out[78] chanx[1][0]_in[79] chanx[1][0]_out[80] chanx[1][0]_in[81] chanx[1][0]_out[82] chanx[1][0]_in[83] chanx[1][0]_out[84] chanx[1][0]_in[85] chanx[1][0]_out[86] chanx[1][0]_in[87] chanx[1][0]_out[88] chanx[1][0]_in[89] chanx[1][0]_out[90] chanx[1][0]_in[91] chanx[1][0]_out[92] chanx[1][0]_in[93] chanx[1][0]_out[94] chanx[1][0]_in[95] chanx[1][0]_out[96] chanx[1][0]_in[97] chanx[1][0]_out[98] chanx[1][0]_in[99] -+ grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][46] grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ ***** Inputs/outputs of bottom side ***** -+ -+ -+ ***** Inputs/outputs of left side ***** -+ -+ -+ svdd sgnd -***** top side Multiplexers ***** -Xmux_1level_tapbuf_size2[10] grid[0][1]_pin[0][1][1] chanx[1][0]_in[3] chany[0][1]_out[0] sram[1642]->outb sram[1642]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[10], level=1, select_path_id=0. ***** -*****1***** -Xsram[1642] sram->in sram[1642]->out sram[1642]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1642]->out) 0 -.nodeset V(sram[1642]->outb) vsp -Xmux_1level_tapbuf_size2[11] grid[0][1]_pin[0][1][1] chanx[1][0]_in[5] chany[0][1]_out[2] sram[1643]->outb sram[1643]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[11], level=1, select_path_id=0. ***** -*****1***** -Xsram[1643] sram->in sram[1643]->out sram[1643]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1643]->out) 0 -.nodeset V(sram[1643]->outb) vsp -Xmux_1level_tapbuf_size2[12] grid[0][1]_pin[0][1][1] chanx[1][0]_in[7] chany[0][1]_out[4] sram[1644]->outb sram[1644]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[12], level=1, select_path_id=0. ***** -*****1***** -Xsram[1644] sram->in sram[1644]->out sram[1644]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1644]->out) 0 -.nodeset V(sram[1644]->outb) vsp -Xmux_1level_tapbuf_size2[13] grid[0][1]_pin[0][1][1] chanx[1][0]_in[9] chany[0][1]_out[6] sram[1645]->outb sram[1645]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[13], level=1, select_path_id=0. ***** -*****1***** -Xsram[1645] sram->in sram[1645]->out sram[1645]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1645]->out) 0 -.nodeset V(sram[1645]->outb) vsp -Xmux_1level_tapbuf_size2[14] grid[0][1]_pin[0][1][1] chanx[1][0]_in[11] chany[0][1]_out[8] sram[1646]->outb sram[1646]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[14], level=1, select_path_id=0. ***** -*****1***** -Xsram[1646] sram->in sram[1646]->out sram[1646]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1646]->out) 0 -.nodeset V(sram[1646]->outb) vsp -Xmux_1level_tapbuf_size2[15] grid[0][1]_pin[0][1][3] chanx[1][0]_in[13] chany[0][1]_out[10] sram[1647]->outb sram[1647]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[15], level=1, select_path_id=0. ***** -*****1***** -Xsram[1647] sram->in sram[1647]->out sram[1647]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1647]->out) 0 -.nodeset V(sram[1647]->outb) vsp -Xmux_1level_tapbuf_size2[16] grid[0][1]_pin[0][1][3] chanx[1][0]_in[15] chany[0][1]_out[12] sram[1648]->outb sram[1648]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[16], level=1, select_path_id=0. ***** -*****1***** -Xsram[1648] sram->in sram[1648]->out sram[1648]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1648]->out) 0 -.nodeset V(sram[1648]->outb) vsp -Xmux_1level_tapbuf_size2[17] grid[0][1]_pin[0][1][3] chanx[1][0]_in[17] chany[0][1]_out[14] sram[1649]->outb sram[1649]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[17], level=1, select_path_id=0. ***** -*****1***** -Xsram[1649] sram->in sram[1649]->out sram[1649]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1649]->out) 0 -.nodeset V(sram[1649]->outb) vsp -Xmux_1level_tapbuf_size2[18] grid[0][1]_pin[0][1][3] chanx[1][0]_in[19] chany[0][1]_out[16] sram[1650]->outb sram[1650]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[18], level=1, select_path_id=0. ***** -*****1***** -Xsram[1650] sram->in sram[1650]->out sram[1650]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1650]->out) 0 -.nodeset V(sram[1650]->outb) vsp -Xmux_1level_tapbuf_size2[19] grid[0][1]_pin[0][1][3] chanx[1][0]_in[21] chany[0][1]_out[18] sram[1651]->outb sram[1651]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[19], level=1, select_path_id=0. ***** -*****1***** -Xsram[1651] sram->in sram[1651]->out sram[1651]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1651]->out) 0 -.nodeset V(sram[1651]->outb) vsp -Xmux_1level_tapbuf_size2[20] grid[0][1]_pin[0][1][5] chanx[1][0]_in[23] chany[0][1]_out[20] sram[1652]->outb sram[1652]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[20], level=1, select_path_id=0. ***** -*****1***** -Xsram[1652] sram->in sram[1652]->out sram[1652]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1652]->out) 0 -.nodeset V(sram[1652]->outb) vsp -Xmux_1level_tapbuf_size2[21] grid[0][1]_pin[0][1][5] chanx[1][0]_in[25] chany[0][1]_out[22] sram[1653]->outb sram[1653]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[21], level=1, select_path_id=0. ***** -*****1***** -Xsram[1653] sram->in sram[1653]->out sram[1653]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1653]->out) 0 -.nodeset V(sram[1653]->outb) vsp -Xmux_1level_tapbuf_size2[22] grid[0][1]_pin[0][1][5] chanx[1][0]_in[27] chany[0][1]_out[24] sram[1654]->outb sram[1654]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[22], level=1, select_path_id=0. ***** -*****1***** -Xsram[1654] sram->in sram[1654]->out sram[1654]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1654]->out) 0 -.nodeset V(sram[1654]->outb) vsp -Xmux_1level_tapbuf_size2[23] grid[0][1]_pin[0][1][5] chanx[1][0]_in[29] chany[0][1]_out[26] sram[1655]->outb sram[1655]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[23], level=1, select_path_id=0. ***** -*****1***** -Xsram[1655] sram->in sram[1655]->out sram[1655]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1655]->out) 0 -.nodeset V(sram[1655]->outb) vsp -Xmux_1level_tapbuf_size2[24] grid[0][1]_pin[0][1][5] chanx[1][0]_in[31] chany[0][1]_out[28] sram[1656]->outb sram[1656]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[24], level=1, select_path_id=0. ***** -*****1***** -Xsram[1656] sram->in sram[1656]->out sram[1656]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1656]->out) 0 -.nodeset V(sram[1656]->outb) vsp -Xmux_1level_tapbuf_size2[25] grid[0][1]_pin[0][1][7] chanx[1][0]_in[33] chany[0][1]_out[30] sram[1657]->outb sram[1657]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[25], level=1, select_path_id=0. ***** -*****1***** -Xsram[1657] sram->in sram[1657]->out sram[1657]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1657]->out) 0 -.nodeset V(sram[1657]->outb) vsp -Xmux_1level_tapbuf_size2[26] grid[0][1]_pin[0][1][7] chanx[1][0]_in[35] chany[0][1]_out[32] sram[1658]->outb sram[1658]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[26], level=1, select_path_id=0. ***** -*****1***** -Xsram[1658] sram->in sram[1658]->out sram[1658]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1658]->out) 0 -.nodeset V(sram[1658]->outb) vsp -Xmux_1level_tapbuf_size2[27] grid[0][1]_pin[0][1][7] chanx[1][0]_in[37] chany[0][1]_out[34] sram[1659]->outb sram[1659]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[27], level=1, select_path_id=0. ***** -*****1***** -Xsram[1659] sram->in sram[1659]->out sram[1659]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1659]->out) 0 -.nodeset V(sram[1659]->outb) vsp -Xmux_1level_tapbuf_size2[28] grid[0][1]_pin[0][1][7] chanx[1][0]_in[39] chany[0][1]_out[36] sram[1660]->outb sram[1660]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[28], level=1, select_path_id=0. ***** -*****1***** -Xsram[1660] sram->in sram[1660]->out sram[1660]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1660]->out) 0 -.nodeset V(sram[1660]->outb) vsp -Xmux_1level_tapbuf_size2[29] grid[0][1]_pin[0][1][7] chanx[1][0]_in[41] chany[0][1]_out[38] sram[1661]->outb sram[1661]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[29], level=1, select_path_id=0. ***** -*****1***** -Xsram[1661] sram->in sram[1661]->out sram[1661]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1661]->out) 0 -.nodeset V(sram[1661]->outb) vsp -Xmux_1level_tapbuf_size2[30] grid[0][1]_pin[0][1][9] chanx[1][0]_in[43] chany[0][1]_out[40] sram[1662]->outb sram[1662]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[30], level=1, select_path_id=0. ***** -*****1***** -Xsram[1662] sram->in sram[1662]->out sram[1662]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1662]->out) 0 -.nodeset V(sram[1662]->outb) vsp -Xmux_1level_tapbuf_size2[31] grid[0][1]_pin[0][1][9] chanx[1][0]_in[45] chany[0][1]_out[42] sram[1663]->outb sram[1663]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[31], level=1, select_path_id=0. ***** -*****1***** -Xsram[1663] sram->in sram[1663]->out sram[1663]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1663]->out) 0 -.nodeset V(sram[1663]->outb) vsp -Xmux_1level_tapbuf_size2[32] grid[0][1]_pin[0][1][9] chanx[1][0]_in[47] chany[0][1]_out[44] sram[1664]->outb sram[1664]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[32], level=1, select_path_id=0. ***** -*****1***** -Xsram[1664] sram->in sram[1664]->out sram[1664]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1664]->out) 0 -.nodeset V(sram[1664]->outb) vsp -Xmux_1level_tapbuf_size2[33] grid[0][1]_pin[0][1][9] chanx[1][0]_in[49] chany[0][1]_out[46] sram[1665]->outb sram[1665]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[33], level=1, select_path_id=0. ***** -*****1***** -Xsram[1665] sram->in sram[1665]->out sram[1665]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1665]->out) 0 -.nodeset V(sram[1665]->outb) vsp -Xmux_1level_tapbuf_size2[34] grid[0][1]_pin[0][1][9] chanx[1][0]_in[51] chany[0][1]_out[48] sram[1666]->outb sram[1666]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[34], level=1, select_path_id=0. ***** -*****1***** -Xsram[1666] sram->in sram[1666]->out sram[1666]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1666]->out) 0 -.nodeset V(sram[1666]->outb) vsp -Xmux_1level_tapbuf_size2[35] grid[0][1]_pin[0][1][11] chanx[1][0]_in[53] chany[0][1]_out[50] sram[1667]->outb sram[1667]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[35], level=1, select_path_id=0. ***** -*****1***** -Xsram[1667] sram->in sram[1667]->out sram[1667]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1667]->out) 0 -.nodeset V(sram[1667]->outb) vsp -Xmux_1level_tapbuf_size2[36] grid[0][1]_pin[0][1][11] chanx[1][0]_in[55] chany[0][1]_out[52] sram[1668]->outb sram[1668]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[36], level=1, select_path_id=0. ***** -*****1***** -Xsram[1668] sram->in sram[1668]->out sram[1668]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1668]->out) 0 -.nodeset V(sram[1668]->outb) vsp -Xmux_1level_tapbuf_size2[37] grid[0][1]_pin[0][1][11] chanx[1][0]_in[57] chany[0][1]_out[54] sram[1669]->outb sram[1669]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[37], level=1, select_path_id=0. ***** -*****1***** -Xsram[1669] sram->in sram[1669]->out sram[1669]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1669]->out) 0 -.nodeset V(sram[1669]->outb) vsp -Xmux_1level_tapbuf_size2[38] grid[0][1]_pin[0][1][11] chanx[1][0]_in[59] chany[0][1]_out[56] sram[1670]->outb sram[1670]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[38], level=1, select_path_id=0. ***** -*****1***** -Xsram[1670] sram->in sram[1670]->out sram[1670]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1670]->out) 0 -.nodeset V(sram[1670]->outb) vsp -Xmux_1level_tapbuf_size2[39] grid[0][1]_pin[0][1][11] chanx[1][0]_in[61] chany[0][1]_out[58] sram[1671]->outb sram[1671]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[39], level=1, select_path_id=0. ***** -*****1***** -Xsram[1671] sram->in sram[1671]->out sram[1671]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1671]->out) 0 -.nodeset V(sram[1671]->outb) vsp -Xmux_1level_tapbuf_size2[40] grid[0][1]_pin[0][1][13] chanx[1][0]_in[63] chany[0][1]_out[60] sram[1672]->outb sram[1672]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[40], level=1, select_path_id=0. ***** -*****1***** -Xsram[1672] sram->in sram[1672]->out sram[1672]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1672]->out) 0 -.nodeset V(sram[1672]->outb) vsp -Xmux_1level_tapbuf_size2[41] grid[0][1]_pin[0][1][13] chanx[1][0]_in[65] chany[0][1]_out[62] sram[1673]->outb sram[1673]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[41], level=1, select_path_id=0. ***** -*****1***** -Xsram[1673] sram->in sram[1673]->out sram[1673]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1673]->out) 0 -.nodeset V(sram[1673]->outb) vsp -Xmux_1level_tapbuf_size2[42] grid[0][1]_pin[0][1][13] chanx[1][0]_in[67] chany[0][1]_out[64] sram[1674]->outb sram[1674]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[42], level=1, select_path_id=0. ***** -*****1***** -Xsram[1674] sram->in sram[1674]->out sram[1674]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1674]->out) 0 -.nodeset V(sram[1674]->outb) vsp -Xmux_1level_tapbuf_size2[43] grid[0][1]_pin[0][1][13] chanx[1][0]_in[69] chany[0][1]_out[66] sram[1675]->outb sram[1675]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[43], level=1, select_path_id=0. ***** -*****1***** -Xsram[1675] sram->in sram[1675]->out sram[1675]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1675]->out) 0 -.nodeset V(sram[1675]->outb) vsp -Xmux_1level_tapbuf_size2[44] grid[0][1]_pin[0][1][13] chanx[1][0]_in[71] chany[0][1]_out[68] sram[1676]->outb sram[1676]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[44], level=1, select_path_id=0. ***** -*****1***** -Xsram[1676] sram->in sram[1676]->out sram[1676]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1676]->out) 0 -.nodeset V(sram[1676]->outb) vsp -Xmux_1level_tapbuf_size2[45] grid[0][1]_pin[0][1][15] chanx[1][0]_in[73] chany[0][1]_out[70] sram[1677]->outb sram[1677]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[45], level=1, select_path_id=0. ***** -*****1***** -Xsram[1677] sram->in sram[1677]->out sram[1677]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1677]->out) 0 -.nodeset V(sram[1677]->outb) vsp -Xmux_1level_tapbuf_size2[46] grid[0][1]_pin[0][1][15] chanx[1][0]_in[75] chany[0][1]_out[72] sram[1678]->outb sram[1678]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[46], level=1, select_path_id=0. ***** -*****1***** -Xsram[1678] sram->in sram[1678]->out sram[1678]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1678]->out) 0 -.nodeset V(sram[1678]->outb) vsp -Xmux_1level_tapbuf_size2[47] grid[0][1]_pin[0][1][15] chanx[1][0]_in[77] chany[0][1]_out[74] sram[1679]->outb sram[1679]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[47], level=1, select_path_id=0. ***** -*****1***** -Xsram[1679] sram->in sram[1679]->out sram[1679]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1679]->out) 0 -.nodeset V(sram[1679]->outb) vsp -Xmux_1level_tapbuf_size2[48] grid[0][1]_pin[0][1][15] chanx[1][0]_in[79] chany[0][1]_out[76] sram[1680]->out sram[1680]->outb svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[48], level=1, select_path_id=1. ***** -*****0***** -Xsram[1680] sram->in sram[1680]->out sram[1680]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1680]->out) 0 -.nodeset V(sram[1680]->outb) vsp -Xmux_1level_tapbuf_size2[49] grid[0][1]_pin[0][1][15] chanx[1][0]_in[81] chany[0][1]_out[78] sram[1681]->outb sram[1681]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[49], level=1, select_path_id=0. ***** -*****1***** -Xsram[1681] sram->in sram[1681]->out sram[1681]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1681]->out) 0 -.nodeset V(sram[1681]->outb) vsp -Xmux_1level_tapbuf_size2[50] grid[1][1]_pin[0][3][43] chanx[1][0]_in[83] chany[0][1]_out[80] sram[1682]->outb sram[1682]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[50], level=1, select_path_id=0. ***** -*****1***** -Xsram[1682] sram->in sram[1682]->out sram[1682]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1682]->out) 0 -.nodeset V(sram[1682]->outb) vsp -Xmux_1level_tapbuf_size2[51] grid[1][1]_pin[0][3][43] chanx[1][0]_in[85] chany[0][1]_out[82] sram[1683]->outb sram[1683]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[51], level=1, select_path_id=0. ***** -*****1***** -Xsram[1683] sram->in sram[1683]->out sram[1683]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1683]->out) 0 -.nodeset V(sram[1683]->outb) vsp -Xmux_1level_tapbuf_size2[52] grid[1][1]_pin[0][3][43] chanx[1][0]_in[87] chany[0][1]_out[84] sram[1684]->outb sram[1684]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[52], level=1, select_path_id=0. ***** -*****1***** -Xsram[1684] sram->in sram[1684]->out sram[1684]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1684]->out) 0 -.nodeset V(sram[1684]->outb) vsp -Xmux_1level_tapbuf_size2[53] grid[1][1]_pin[0][3][43] chanx[1][0]_in[89] chany[0][1]_out[86] sram[1685]->outb sram[1685]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[53], level=1, select_path_id=0. ***** -*****1***** -Xsram[1685] sram->in sram[1685]->out sram[1685]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1685]->out) 0 -.nodeset V(sram[1685]->outb) vsp -Xmux_1level_tapbuf_size2[54] grid[1][1]_pin[0][3][43] chanx[1][0]_in[91] chany[0][1]_out[88] sram[1686]->outb sram[1686]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[54], level=1, select_path_id=0. ***** -*****1***** -Xsram[1686] sram->in sram[1686]->out sram[1686]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1686]->out) 0 -.nodeset V(sram[1686]->outb) vsp -Xmux_1level_tapbuf_size2[55] grid[1][1]_pin[0][3][47] chanx[1][0]_in[93] chany[0][1]_out[90] sram[1687]->outb sram[1687]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[55], level=1, select_path_id=0. ***** -*****1***** -Xsram[1687] sram->in sram[1687]->out sram[1687]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1687]->out) 0 -.nodeset V(sram[1687]->outb) vsp -Xmux_1level_tapbuf_size2[56] grid[1][1]_pin[0][3][47] chanx[1][0]_in[95] chany[0][1]_out[92] sram[1688]->outb sram[1688]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[56], level=1, select_path_id=0. ***** -*****1***** -Xsram[1688] sram->in sram[1688]->out sram[1688]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1688]->out) 0 -.nodeset V(sram[1688]->outb) vsp -Xmux_1level_tapbuf_size2[57] grid[1][1]_pin[0][3][47] chanx[1][0]_in[97] chany[0][1]_out[94] sram[1689]->outb sram[1689]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[57], level=1, select_path_id=0. ***** -*****1***** -Xsram[1689] sram->in sram[1689]->out sram[1689]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1689]->out) 0 -.nodeset V(sram[1689]->outb) vsp -Xmux_1level_tapbuf_size2[58] grid[1][1]_pin[0][3][47] chanx[1][0]_in[99] chany[0][1]_out[96] sram[1690]->outb sram[1690]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[58], level=1, select_path_id=0. ***** -*****1***** -Xsram[1690] sram->in sram[1690]->out sram[1690]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1690]->out) 0 -.nodeset V(sram[1690]->outb) vsp -Xmux_1level_tapbuf_size2[59] grid[1][1]_pin[0][3][47] chanx[1][0]_in[1] chany[0][1]_out[98] sram[1691]->outb sram[1691]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[59], level=1, select_path_id=0. ***** -*****1***** -Xsram[1691] sram->in sram[1691]->out sram[1691]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1691]->out) 0 -.nodeset V(sram[1691]->outb) vsp -***** right side Multiplexers ***** -Xmux_1level_tapbuf_size2[60] grid[1][0]_pin[0][0][1] chany[0][1]_in[99] chanx[1][0]_out[0] sram[1692]->outb sram[1692]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[60], level=1, select_path_id=0. ***** -*****1***** -Xsram[1692] sram->in sram[1692]->out sram[1692]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1692]->out) 0 -.nodeset V(sram[1692]->outb) vsp -Xmux_1level_tapbuf_size2[61] grid[1][0]_pin[0][0][1] chany[0][1]_in[1] chanx[1][0]_out[2] sram[1693]->outb sram[1693]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[61], level=1, select_path_id=0. ***** -*****1***** -Xsram[1693] sram->in sram[1693]->out sram[1693]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1693]->out) 0 -.nodeset V(sram[1693]->outb) vsp -Xmux_1level_tapbuf_size2[62] grid[1][0]_pin[0][0][1] chany[0][1]_in[3] chanx[1][0]_out[4] sram[1694]->outb sram[1694]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[62], level=1, select_path_id=0. ***** -*****1***** -Xsram[1694] sram->in sram[1694]->out sram[1694]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1694]->out) 0 -.nodeset V(sram[1694]->outb) vsp -Xmux_1level_tapbuf_size2[63] grid[1][0]_pin[0][0][1] chany[0][1]_in[5] chanx[1][0]_out[6] sram[1695]->outb sram[1695]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[63], level=1, select_path_id=0. ***** -*****1***** -Xsram[1695] sram->in sram[1695]->out sram[1695]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1695]->out) 0 -.nodeset V(sram[1695]->outb) vsp -Xmux_1level_tapbuf_size2[64] grid[1][0]_pin[0][0][1] chany[0][1]_in[7] chanx[1][0]_out[8] sram[1696]->outb sram[1696]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[64], level=1, select_path_id=0. ***** -*****1***** -Xsram[1696] sram->in sram[1696]->out sram[1696]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1696]->out) 0 -.nodeset V(sram[1696]->outb) vsp -Xmux_1level_tapbuf_size2[65] grid[1][0]_pin[0][0][3] chany[0][1]_in[9] chanx[1][0]_out[10] sram[1697]->outb sram[1697]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[65], level=1, select_path_id=0. ***** -*****1***** -Xsram[1697] sram->in sram[1697]->out sram[1697]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1697]->out) 0 -.nodeset V(sram[1697]->outb) vsp -Xmux_1level_tapbuf_size2[66] grid[1][0]_pin[0][0][3] chany[0][1]_in[11] chanx[1][0]_out[12] sram[1698]->outb sram[1698]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[66], level=1, select_path_id=0. ***** -*****1***** -Xsram[1698] sram->in sram[1698]->out sram[1698]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1698]->out) 0 -.nodeset V(sram[1698]->outb) vsp -Xmux_1level_tapbuf_size2[67] grid[1][0]_pin[0][0][3] chany[0][1]_in[13] chanx[1][0]_out[14] sram[1699]->outb sram[1699]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[67], level=1, select_path_id=0. ***** -*****1***** -Xsram[1699] sram->in sram[1699]->out sram[1699]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1699]->out) 0 -.nodeset V(sram[1699]->outb) vsp -Xmux_1level_tapbuf_size2[68] grid[1][0]_pin[0][0][3] chany[0][1]_in[15] chanx[1][0]_out[16] sram[1700]->outb sram[1700]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[68], level=1, select_path_id=0. ***** -*****1***** -Xsram[1700] sram->in sram[1700]->out sram[1700]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1700]->out) 0 -.nodeset V(sram[1700]->outb) vsp -Xmux_1level_tapbuf_size2[69] grid[1][0]_pin[0][0][3] chany[0][1]_in[17] chanx[1][0]_out[18] sram[1701]->outb sram[1701]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[69], level=1, select_path_id=0. ***** -*****1***** -Xsram[1701] sram->in sram[1701]->out sram[1701]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1701]->out) 0 -.nodeset V(sram[1701]->outb) vsp -Xmux_1level_tapbuf_size2[70] grid[1][0]_pin[0][0][5] chany[0][1]_in[19] chanx[1][0]_out[20] sram[1702]->outb sram[1702]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[70], level=1, select_path_id=0. ***** -*****1***** -Xsram[1702] sram->in sram[1702]->out sram[1702]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1702]->out) 0 -.nodeset V(sram[1702]->outb) vsp -Xmux_1level_tapbuf_size2[71] grid[1][0]_pin[0][0][5] chany[0][1]_in[21] chanx[1][0]_out[22] sram[1703]->outb sram[1703]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[71], level=1, select_path_id=0. ***** -*****1***** -Xsram[1703] sram->in sram[1703]->out sram[1703]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1703]->out) 0 -.nodeset V(sram[1703]->outb) vsp -Xmux_1level_tapbuf_size2[72] grid[1][0]_pin[0][0][5] chany[0][1]_in[23] chanx[1][0]_out[24] sram[1704]->outb sram[1704]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[72], level=1, select_path_id=0. ***** -*****1***** -Xsram[1704] sram->in sram[1704]->out sram[1704]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1704]->out) 0 -.nodeset V(sram[1704]->outb) vsp -Xmux_1level_tapbuf_size2[73] grid[1][0]_pin[0][0][5] chany[0][1]_in[25] chanx[1][0]_out[26] sram[1705]->outb sram[1705]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[73], level=1, select_path_id=0. ***** -*****1***** -Xsram[1705] sram->in sram[1705]->out sram[1705]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1705]->out) 0 -.nodeset V(sram[1705]->outb) vsp -Xmux_1level_tapbuf_size2[74] grid[1][0]_pin[0][0][5] chany[0][1]_in[27] chanx[1][0]_out[28] sram[1706]->outb sram[1706]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[74], level=1, select_path_id=0. ***** -*****1***** -Xsram[1706] sram->in sram[1706]->out sram[1706]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1706]->out) 0 -.nodeset V(sram[1706]->outb) vsp -Xmux_1level_tapbuf_size2[75] grid[1][0]_pin[0][0][7] chany[0][1]_in[29] chanx[1][0]_out[30] sram[1707]->outb sram[1707]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[75], level=1, select_path_id=0. ***** -*****1***** -Xsram[1707] sram->in sram[1707]->out sram[1707]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1707]->out) 0 -.nodeset V(sram[1707]->outb) vsp -Xmux_1level_tapbuf_size2[76] grid[1][0]_pin[0][0][7] chany[0][1]_in[31] chanx[1][0]_out[32] sram[1708]->outb sram[1708]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[76], level=1, select_path_id=0. ***** -*****1***** -Xsram[1708] sram->in sram[1708]->out sram[1708]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1708]->out) 0 -.nodeset V(sram[1708]->outb) vsp -Xmux_1level_tapbuf_size2[77] grid[1][0]_pin[0][0][7] chany[0][1]_in[33] chanx[1][0]_out[34] sram[1709]->outb sram[1709]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[77], level=1, select_path_id=0. ***** -*****1***** -Xsram[1709] sram->in sram[1709]->out sram[1709]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1709]->out) 0 -.nodeset V(sram[1709]->outb) vsp -Xmux_1level_tapbuf_size2[78] grid[1][0]_pin[0][0][7] chany[0][1]_in[35] chanx[1][0]_out[36] sram[1710]->outb sram[1710]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[78], level=1, select_path_id=0. ***** -*****1***** -Xsram[1710] sram->in sram[1710]->out sram[1710]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1710]->out) 0 -.nodeset V(sram[1710]->outb) vsp -Xmux_1level_tapbuf_size2[79] grid[1][0]_pin[0][0][7] chany[0][1]_in[37] chanx[1][0]_out[38] sram[1711]->outb sram[1711]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[79], level=1, select_path_id=0. ***** -*****1***** -Xsram[1711] sram->in sram[1711]->out sram[1711]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1711]->out) 0 -.nodeset V(sram[1711]->outb) vsp -Xmux_1level_tapbuf_size2[80] grid[1][0]_pin[0][0][9] chany[0][1]_in[39] chanx[1][0]_out[40] sram[1712]->outb sram[1712]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[80], level=1, select_path_id=0. ***** -*****1***** -Xsram[1712] sram->in sram[1712]->out sram[1712]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1712]->out) 0 -.nodeset V(sram[1712]->outb) vsp -Xmux_1level_tapbuf_size2[81] grid[1][0]_pin[0][0][9] chany[0][1]_in[41] chanx[1][0]_out[42] sram[1713]->outb sram[1713]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[81], level=1, select_path_id=0. ***** -*****1***** -Xsram[1713] sram->in sram[1713]->out sram[1713]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1713]->out) 0 -.nodeset V(sram[1713]->outb) vsp -Xmux_1level_tapbuf_size2[82] grid[1][0]_pin[0][0][9] chany[0][1]_in[43] chanx[1][0]_out[44] sram[1714]->outb sram[1714]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[82], level=1, select_path_id=0. ***** -*****1***** -Xsram[1714] sram->in sram[1714]->out sram[1714]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1714]->out) 0 -.nodeset V(sram[1714]->outb) vsp -Xmux_1level_tapbuf_size2[83] grid[1][0]_pin[0][0][9] chany[0][1]_in[45] chanx[1][0]_out[46] sram[1715]->outb sram[1715]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[83], level=1, select_path_id=0. ***** -*****1***** -Xsram[1715] sram->in sram[1715]->out sram[1715]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1715]->out) 0 -.nodeset V(sram[1715]->outb) vsp -Xmux_1level_tapbuf_size2[84] grid[1][0]_pin[0][0][9] chany[0][1]_in[47] chanx[1][0]_out[48] sram[1716]->outb sram[1716]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[84], level=1, select_path_id=0. ***** -*****1***** -Xsram[1716] sram->in sram[1716]->out sram[1716]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1716]->out) 0 -.nodeset V(sram[1716]->outb) vsp -Xmux_1level_tapbuf_size2[85] grid[1][0]_pin[0][0][11] chany[0][1]_in[49] chanx[1][0]_out[50] sram[1717]->outb sram[1717]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[85], level=1, select_path_id=0. ***** -*****1***** -Xsram[1717] sram->in sram[1717]->out sram[1717]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1717]->out) 0 -.nodeset V(sram[1717]->outb) vsp -Xmux_1level_tapbuf_size2[86] grid[1][0]_pin[0][0][11] chany[0][1]_in[51] chanx[1][0]_out[52] sram[1718]->outb sram[1718]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[86], level=1, select_path_id=0. ***** -*****1***** -Xsram[1718] sram->in sram[1718]->out sram[1718]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1718]->out) 0 -.nodeset V(sram[1718]->outb) vsp -Xmux_1level_tapbuf_size2[87] grid[1][0]_pin[0][0][11] chany[0][1]_in[53] chanx[1][0]_out[54] sram[1719]->outb sram[1719]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[87], level=1, select_path_id=0. ***** -*****1***** -Xsram[1719] sram->in sram[1719]->out sram[1719]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1719]->out) 0 -.nodeset V(sram[1719]->outb) vsp -Xmux_1level_tapbuf_size2[88] grid[1][0]_pin[0][0][11] chany[0][1]_in[55] chanx[1][0]_out[56] sram[1720]->outb sram[1720]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[88], level=1, select_path_id=0. ***** -*****1***** -Xsram[1720] sram->in sram[1720]->out sram[1720]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1720]->out) 0 -.nodeset V(sram[1720]->outb) vsp -Xmux_1level_tapbuf_size2[89] grid[1][0]_pin[0][0][11] chany[0][1]_in[57] chanx[1][0]_out[58] sram[1721]->outb sram[1721]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[89], level=1, select_path_id=0. ***** -*****1***** -Xsram[1721] sram->in sram[1721]->out sram[1721]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1721]->out) 0 -.nodeset V(sram[1721]->outb) vsp -Xmux_1level_tapbuf_size2[90] grid[1][0]_pin[0][0][13] chany[0][1]_in[59] chanx[1][0]_out[60] sram[1722]->outb sram[1722]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[90], level=1, select_path_id=0. ***** -*****1***** -Xsram[1722] sram->in sram[1722]->out sram[1722]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1722]->out) 0 -.nodeset V(sram[1722]->outb) vsp -Xmux_1level_tapbuf_size2[91] grid[1][0]_pin[0][0][13] chany[0][1]_in[61] chanx[1][0]_out[62] sram[1723]->outb sram[1723]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[91], level=1, select_path_id=0. ***** -*****1***** -Xsram[1723] sram->in sram[1723]->out sram[1723]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1723]->out) 0 -.nodeset V(sram[1723]->outb) vsp -Xmux_1level_tapbuf_size2[92] grid[1][0]_pin[0][0][13] chany[0][1]_in[63] chanx[1][0]_out[64] sram[1724]->outb sram[1724]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[92], level=1, select_path_id=0. ***** -*****1***** -Xsram[1724] sram->in sram[1724]->out sram[1724]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1724]->out) 0 -.nodeset V(sram[1724]->outb) vsp -Xmux_1level_tapbuf_size2[93] grid[1][0]_pin[0][0][13] chany[0][1]_in[65] chanx[1][0]_out[66] sram[1725]->outb sram[1725]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[93], level=1, select_path_id=0. ***** -*****1***** -Xsram[1725] sram->in sram[1725]->out sram[1725]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1725]->out) 0 -.nodeset V(sram[1725]->outb) vsp -Xmux_1level_tapbuf_size2[94] grid[1][0]_pin[0][0][13] chany[0][1]_in[67] chanx[1][0]_out[68] sram[1726]->outb sram[1726]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[94], level=1, select_path_id=0. ***** -*****1***** -Xsram[1726] sram->in sram[1726]->out sram[1726]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1726]->out) 0 -.nodeset V(sram[1726]->outb) vsp -Xmux_1level_tapbuf_size2[95] grid[1][0]_pin[0][0][15] chany[0][1]_in[69] chanx[1][0]_out[70] sram[1727]->outb sram[1727]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[95], level=1, select_path_id=0. ***** -*****1***** -Xsram[1727] sram->in sram[1727]->out sram[1727]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1727]->out) 0 -.nodeset V(sram[1727]->outb) vsp -Xmux_1level_tapbuf_size2[96] grid[1][0]_pin[0][0][15] chany[0][1]_in[71] chanx[1][0]_out[72] sram[1728]->outb sram[1728]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[96], level=1, select_path_id=0. ***** -*****1***** -Xsram[1728] sram->in sram[1728]->out sram[1728]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1728]->out) 0 -.nodeset V(sram[1728]->outb) vsp -Xmux_1level_tapbuf_size2[97] grid[1][0]_pin[0][0][15] chany[0][1]_in[73] chanx[1][0]_out[74] sram[1729]->outb sram[1729]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[97], level=1, select_path_id=0. ***** -*****1***** -Xsram[1729] sram->in sram[1729]->out sram[1729]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1729]->out) 0 -.nodeset V(sram[1729]->outb) vsp -Xmux_1level_tapbuf_size2[98] grid[1][0]_pin[0][0][15] chany[0][1]_in[75] chanx[1][0]_out[76] sram[1730]->outb sram[1730]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[98], level=1, select_path_id=0. ***** -*****1***** -Xsram[1730] sram->in sram[1730]->out sram[1730]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1730]->out) 0 -.nodeset V(sram[1730]->outb) vsp -Xmux_1level_tapbuf_size2[99] grid[1][0]_pin[0][0][15] chany[0][1]_in[77] chanx[1][0]_out[78] sram[1731]->outb sram[1731]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[99], level=1, select_path_id=0. ***** -*****1***** -Xsram[1731] sram->in sram[1731]->out sram[1731]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1731]->out) 0 -.nodeset V(sram[1731]->outb) vsp -Xmux_1level_tapbuf_size2[100] grid[1][1]_pin[0][2][42] chany[0][1]_in[79] chanx[1][0]_out[80] sram[1732]->outb sram[1732]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[100], level=1, select_path_id=0. ***** -*****1***** -Xsram[1732] sram->in sram[1732]->out sram[1732]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1732]->out) 0 -.nodeset V(sram[1732]->outb) vsp -Xmux_1level_tapbuf_size2[101] grid[1][1]_pin[0][2][42] chany[0][1]_in[81] chanx[1][0]_out[82] sram[1733]->outb sram[1733]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[101], level=1, select_path_id=0. ***** -*****1***** -Xsram[1733] sram->in sram[1733]->out sram[1733]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1733]->out) 0 -.nodeset V(sram[1733]->outb) vsp -Xmux_1level_tapbuf_size2[102] grid[1][1]_pin[0][2][42] chany[0][1]_in[83] chanx[1][0]_out[84] sram[1734]->outb sram[1734]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[102], level=1, select_path_id=0. ***** -*****1***** -Xsram[1734] sram->in sram[1734]->out sram[1734]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1734]->out) 0 -.nodeset V(sram[1734]->outb) vsp -Xmux_1level_tapbuf_size2[103] grid[1][1]_pin[0][2][42] chany[0][1]_in[85] chanx[1][0]_out[86] sram[1735]->outb sram[1735]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[103], level=1, select_path_id=0. ***** -*****1***** -Xsram[1735] sram->in sram[1735]->out sram[1735]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1735]->out) 0 -.nodeset V(sram[1735]->outb) vsp -Xmux_1level_tapbuf_size2[104] grid[1][1]_pin[0][2][42] chany[0][1]_in[87] chanx[1][0]_out[88] sram[1736]->outb sram[1736]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[104], level=1, select_path_id=0. ***** -*****1***** -Xsram[1736] sram->in sram[1736]->out sram[1736]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1736]->out) 0 -.nodeset V(sram[1736]->outb) vsp -Xmux_1level_tapbuf_size2[105] grid[1][1]_pin[0][2][46] chany[0][1]_in[89] chanx[1][0]_out[90] sram[1737]->outb sram[1737]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[105], level=1, select_path_id=0. ***** -*****1***** -Xsram[1737] sram->in sram[1737]->out sram[1737]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1737]->out) 0 -.nodeset V(sram[1737]->outb) vsp -Xmux_1level_tapbuf_size2[106] grid[1][1]_pin[0][2][46] chany[0][1]_in[91] chanx[1][0]_out[92] sram[1738]->outb sram[1738]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[106], level=1, select_path_id=0. ***** -*****1***** -Xsram[1738] sram->in sram[1738]->out sram[1738]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1738]->out) 0 -.nodeset V(sram[1738]->outb) vsp -Xmux_1level_tapbuf_size2[107] grid[1][1]_pin[0][2][46] chany[0][1]_in[93] chanx[1][0]_out[94] sram[1739]->outb sram[1739]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[107], level=1, select_path_id=0. ***** -*****1***** -Xsram[1739] sram->in sram[1739]->out sram[1739]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1739]->out) 0 -.nodeset V(sram[1739]->outb) vsp -Xmux_1level_tapbuf_size2[108] grid[1][1]_pin[0][2][46] chany[0][1]_in[95] chanx[1][0]_out[96] sram[1740]->outb sram[1740]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[108], level=1, select_path_id=0. ***** -*****1***** -Xsram[1740] sram->in sram[1740]->out sram[1740]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1740]->out) 0 -.nodeset V(sram[1740]->outb) vsp -Xmux_1level_tapbuf_size2[109] grid[1][1]_pin[0][2][46] chany[0][1]_in[97] chanx[1][0]_out[98] sram[1741]->outb sram[1741]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[109], level=1, select_path_id=0. ***** -*****1***** -Xsram[1741] sram->in sram[1741]->out sram[1741]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1741]->out) 0 -.nodeset V(sram[1741]->outb) vsp -***** bottom side Multiplexers ***** -***** left side Multiplexers ***** -.eom diff --git a/examples/spice_test_example_2/subckt/sb_0_1.sp b/examples/spice_test_example_2/subckt/sb_0_1.sp deleted file mode 100644 index 874c9b913..000000000 --- a/examples/spice_test_example_2/subckt/sb_0_1.sp +++ /dev/null @@ -1,658 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Switch Block [0][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Switch Box[0][1] Sub-Circuit ***** -.subckt sb[0][1] -***** Inputs/outputs of top side ***** -+ -+ -+ ***** Inputs/outputs of right side ***** -+ chanx[1][1]_out[0] chanx[1][1]_in[1] chanx[1][1]_out[2] chanx[1][1]_in[3] chanx[1][1]_out[4] chanx[1][1]_in[5] chanx[1][1]_out[6] chanx[1][1]_in[7] chanx[1][1]_out[8] chanx[1][1]_in[9] chanx[1][1]_out[10] chanx[1][1]_in[11] chanx[1][1]_out[12] chanx[1][1]_in[13] chanx[1][1]_out[14] chanx[1][1]_in[15] chanx[1][1]_out[16] chanx[1][1]_in[17] chanx[1][1]_out[18] chanx[1][1]_in[19] chanx[1][1]_out[20] chanx[1][1]_in[21] chanx[1][1]_out[22] chanx[1][1]_in[23] chanx[1][1]_out[24] chanx[1][1]_in[25] chanx[1][1]_out[26] chanx[1][1]_in[27] chanx[1][1]_out[28] chanx[1][1]_in[29] chanx[1][1]_out[30] chanx[1][1]_in[31] chanx[1][1]_out[32] chanx[1][1]_in[33] chanx[1][1]_out[34] chanx[1][1]_in[35] chanx[1][1]_out[36] chanx[1][1]_in[37] chanx[1][1]_out[38] chanx[1][1]_in[39] chanx[1][1]_out[40] chanx[1][1]_in[41] chanx[1][1]_out[42] chanx[1][1]_in[43] chanx[1][1]_out[44] chanx[1][1]_in[45] chanx[1][1]_out[46] chanx[1][1]_in[47] chanx[1][1]_out[48] chanx[1][1]_in[49] chanx[1][1]_out[50] chanx[1][1]_in[51] chanx[1][1]_out[52] chanx[1][1]_in[53] chanx[1][1]_out[54] chanx[1][1]_in[55] chanx[1][1]_out[56] chanx[1][1]_in[57] chanx[1][1]_out[58] chanx[1][1]_in[59] chanx[1][1]_out[60] chanx[1][1]_in[61] chanx[1][1]_out[62] chanx[1][1]_in[63] chanx[1][1]_out[64] chanx[1][1]_in[65] chanx[1][1]_out[66] chanx[1][1]_in[67] chanx[1][1]_out[68] chanx[1][1]_in[69] chanx[1][1]_out[70] chanx[1][1]_in[71] chanx[1][1]_out[72] chanx[1][1]_in[73] chanx[1][1]_out[74] chanx[1][1]_in[75] chanx[1][1]_out[76] chanx[1][1]_in[77] chanx[1][1]_out[78] chanx[1][1]_in[79] chanx[1][1]_out[80] chanx[1][1]_in[81] chanx[1][1]_out[82] chanx[1][1]_in[83] chanx[1][1]_out[84] chanx[1][1]_in[85] chanx[1][1]_out[86] chanx[1][1]_in[87] chanx[1][1]_out[88] chanx[1][1]_in[89] chanx[1][1]_out[90] chanx[1][1]_in[91] chanx[1][1]_out[92] chanx[1][1]_in[93] chanx[1][1]_out[94] chanx[1][1]_in[95] chanx[1][1]_out[96] chanx[1][1]_in[97] chanx[1][1]_out[98] chanx[1][1]_in[99] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][48] -+ ***** Inputs/outputs of bottom side ***** -+ chany[0][1]_in[0] chany[0][1]_out[1] chany[0][1]_in[2] chany[0][1]_out[3] chany[0][1]_in[4] chany[0][1]_out[5] chany[0][1]_in[6] chany[0][1]_out[7] chany[0][1]_in[8] chany[0][1]_out[9] chany[0][1]_in[10] chany[0][1]_out[11] chany[0][1]_in[12] chany[0][1]_out[13] chany[0][1]_in[14] chany[0][1]_out[15] chany[0][1]_in[16] chany[0][1]_out[17] chany[0][1]_in[18] chany[0][1]_out[19] chany[0][1]_in[20] chany[0][1]_out[21] chany[0][1]_in[22] chany[0][1]_out[23] chany[0][1]_in[24] chany[0][1]_out[25] chany[0][1]_in[26] chany[0][1]_out[27] chany[0][1]_in[28] chany[0][1]_out[29] chany[0][1]_in[30] chany[0][1]_out[31] chany[0][1]_in[32] chany[0][1]_out[33] chany[0][1]_in[34] chany[0][1]_out[35] chany[0][1]_in[36] chany[0][1]_out[37] chany[0][1]_in[38] chany[0][1]_out[39] chany[0][1]_in[40] chany[0][1]_out[41] chany[0][1]_in[42] chany[0][1]_out[43] chany[0][1]_in[44] chany[0][1]_out[45] chany[0][1]_in[46] chany[0][1]_out[47] chany[0][1]_in[48] chany[0][1]_out[49] chany[0][1]_in[50] chany[0][1]_out[51] chany[0][1]_in[52] chany[0][1]_out[53] chany[0][1]_in[54] chany[0][1]_out[55] chany[0][1]_in[56] chany[0][1]_out[57] chany[0][1]_in[58] chany[0][1]_out[59] chany[0][1]_in[60] chany[0][1]_out[61] chany[0][1]_in[62] chany[0][1]_out[63] chany[0][1]_in[64] chany[0][1]_out[65] chany[0][1]_in[66] chany[0][1]_out[67] chany[0][1]_in[68] chany[0][1]_out[69] chany[0][1]_in[70] chany[0][1]_out[71] chany[0][1]_in[72] chany[0][1]_out[73] chany[0][1]_in[74] chany[0][1]_out[75] chany[0][1]_in[76] chany[0][1]_out[77] chany[0][1]_in[78] chany[0][1]_out[79] chany[0][1]_in[80] chany[0][1]_out[81] chany[0][1]_in[82] chany[0][1]_out[83] chany[0][1]_in[84] chany[0][1]_out[85] chany[0][1]_in[86] chany[0][1]_out[87] chany[0][1]_in[88] chany[0][1]_out[89] chany[0][1]_in[90] chany[0][1]_out[91] chany[0][1]_in[92] chany[0][1]_out[93] chany[0][1]_in[94] chany[0][1]_out[95] chany[0][1]_in[96] chany[0][1]_out[97] chany[0][1]_in[98] chany[0][1]_out[99] -+ grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][47] grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] -+ ***** Inputs/outputs of left side ***** -+ -+ -+ svdd sgnd -***** top side Multiplexers ***** -***** right side Multiplexers ***** -Xmux_1level_tapbuf_size3[110] grid[1][1]_pin[0][0][40] grid[1][2]_pin[0][2][15] chany[0][1]_in[96] chanx[1][1]_out[0] sram[1742]->outb sram[1742]->out sram[1743]->out sram[1743]->outb sram[1744]->out sram[1744]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[110], level=1, select_path_id=0. ***** -*****100***** -Xsram[1742] sram->in sram[1742]->out sram[1742]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1742]->out) 0 -.nodeset V(sram[1742]->outb) vsp -Xsram[1743] sram->in sram[1743]->out sram[1743]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1743]->out) 0 -.nodeset V(sram[1743]->outb) vsp -Xsram[1744] sram->in sram[1744]->out sram[1744]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1744]->out) 0 -.nodeset V(sram[1744]->outb) vsp -Xmux_1level_tapbuf_size3[111] grid[1][1]_pin[0][0][40] grid[1][2]_pin[0][2][15] chany[0][1]_in[94] chanx[1][1]_out[2] sram[1745]->outb sram[1745]->out sram[1746]->out sram[1746]->outb sram[1747]->out sram[1747]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[111], level=1, select_path_id=0. ***** -*****100***** -Xsram[1745] sram->in sram[1745]->out sram[1745]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1745]->out) 0 -.nodeset V(sram[1745]->outb) vsp -Xsram[1746] sram->in sram[1746]->out sram[1746]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1746]->out) 0 -.nodeset V(sram[1746]->outb) vsp -Xsram[1747] sram->in sram[1747]->out sram[1747]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1747]->out) 0 -.nodeset V(sram[1747]->outb) vsp -Xmux_1level_tapbuf_size3[112] grid[1][1]_pin[0][0][40] grid[1][2]_pin[0][2][15] chany[0][1]_in[92] chanx[1][1]_out[4] sram[1748]->outb sram[1748]->out sram[1749]->out sram[1749]->outb sram[1750]->out sram[1750]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[112], level=1, select_path_id=0. ***** -*****100***** -Xsram[1748] sram->in sram[1748]->out sram[1748]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1748]->out) 0 -.nodeset V(sram[1748]->outb) vsp -Xsram[1749] sram->in sram[1749]->out sram[1749]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1749]->out) 0 -.nodeset V(sram[1749]->outb) vsp -Xsram[1750] sram->in sram[1750]->out sram[1750]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1750]->out) 0 -.nodeset V(sram[1750]->outb) vsp -Xmux_1level_tapbuf_size3[113] grid[1][1]_pin[0][0][40] grid[1][2]_pin[0][2][15] chany[0][1]_in[90] chanx[1][1]_out[6] sram[1751]->outb sram[1751]->out sram[1752]->out sram[1752]->outb sram[1753]->out sram[1753]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[113], level=1, select_path_id=0. ***** -*****100***** -Xsram[1751] sram->in sram[1751]->out sram[1751]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1751]->out) 0 -.nodeset V(sram[1751]->outb) vsp -Xsram[1752] sram->in sram[1752]->out sram[1752]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1752]->out) 0 -.nodeset V(sram[1752]->outb) vsp -Xsram[1753] sram->in sram[1753]->out sram[1753]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1753]->out) 0 -.nodeset V(sram[1753]->outb) vsp -Xmux_1level_tapbuf_size3[114] grid[1][1]_pin[0][0][40] grid[1][2]_pin[0][2][15] chany[0][1]_in[88] chanx[1][1]_out[8] sram[1754]->outb sram[1754]->out sram[1755]->out sram[1755]->outb sram[1756]->out sram[1756]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[114], level=1, select_path_id=0. ***** -*****100***** -Xsram[1754] sram->in sram[1754]->out sram[1754]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1754]->out) 0 -.nodeset V(sram[1754]->outb) vsp -Xsram[1755] sram->in sram[1755]->out sram[1755]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1755]->out) 0 -.nodeset V(sram[1755]->outb) vsp -Xsram[1756] sram->in sram[1756]->out sram[1756]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1756]->out) 0 -.nodeset V(sram[1756]->outb) vsp -Xmux_1level_tapbuf_size2[115] grid[1][1]_pin[0][0][44] chany[0][1]_in[86] chanx[1][1]_out[10] sram[1757]->outb sram[1757]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[115], level=1, select_path_id=0. ***** -*****1***** -Xsram[1757] sram->in sram[1757]->out sram[1757]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1757]->out) 0 -.nodeset V(sram[1757]->outb) vsp -Xmux_1level_tapbuf_size2[116] grid[1][1]_pin[0][0][44] chany[0][1]_in[84] chanx[1][1]_out[12] sram[1758]->outb sram[1758]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[116], level=1, select_path_id=0. ***** -*****1***** -Xsram[1758] sram->in sram[1758]->out sram[1758]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1758]->out) 0 -.nodeset V(sram[1758]->outb) vsp -Xmux_1level_tapbuf_size2[117] grid[1][1]_pin[0][0][44] chany[0][1]_in[82] chanx[1][1]_out[14] sram[1759]->outb sram[1759]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[117], level=1, select_path_id=0. ***** -*****1***** -Xsram[1759] sram->in sram[1759]->out sram[1759]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1759]->out) 0 -.nodeset V(sram[1759]->outb) vsp -Xmux_1level_tapbuf_size2[118] grid[1][1]_pin[0][0][44] chany[0][1]_in[80] chanx[1][1]_out[16] sram[1760]->outb sram[1760]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[118], level=1, select_path_id=0. ***** -*****1***** -Xsram[1760] sram->in sram[1760]->out sram[1760]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1760]->out) 0 -.nodeset V(sram[1760]->outb) vsp -Xmux_1level_tapbuf_size2[119] grid[1][1]_pin[0][0][44] chany[0][1]_in[78] chanx[1][1]_out[18] sram[1761]->outb sram[1761]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[119], level=1, select_path_id=0. ***** -*****1***** -Xsram[1761] sram->in sram[1761]->out sram[1761]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1761]->out) 0 -.nodeset V(sram[1761]->outb) vsp -Xmux_1level_tapbuf_size2[120] grid[1][1]_pin[0][0][48] chany[0][1]_in[76] chanx[1][1]_out[20] sram[1762]->out sram[1762]->outb svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[120], level=1, select_path_id=1. ***** -*****0***** -Xsram[1762] sram->in sram[1762]->out sram[1762]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1762]->out) 0 -.nodeset V(sram[1762]->outb) vsp -Xmux_1level_tapbuf_size2[121] grid[1][1]_pin[0][0][48] chany[0][1]_in[74] chanx[1][1]_out[22] sram[1763]->outb sram[1763]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[121], level=1, select_path_id=0. ***** -*****1***** -Xsram[1763] sram->in sram[1763]->out sram[1763]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1763]->out) 0 -.nodeset V(sram[1763]->outb) vsp -Xmux_1level_tapbuf_size2[122] grid[1][1]_pin[0][0][48] chany[0][1]_in[72] chanx[1][1]_out[24] sram[1764]->outb sram[1764]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[122], level=1, select_path_id=0. ***** -*****1***** -Xsram[1764] sram->in sram[1764]->out sram[1764]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1764]->out) 0 -.nodeset V(sram[1764]->outb) vsp -Xmux_1level_tapbuf_size2[123] grid[1][1]_pin[0][0][48] chany[0][1]_in[70] chanx[1][1]_out[26] sram[1765]->outb sram[1765]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[123], level=1, select_path_id=0. ***** -*****1***** -Xsram[1765] sram->in sram[1765]->out sram[1765]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1765]->out) 0 -.nodeset V(sram[1765]->outb) vsp -Xmux_1level_tapbuf_size2[124] grid[1][1]_pin[0][0][48] chany[0][1]_in[68] chanx[1][1]_out[28] sram[1766]->outb sram[1766]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[124], level=1, select_path_id=0. ***** -*****1***** -Xsram[1766] sram->in sram[1766]->out sram[1766]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1766]->out) 0 -.nodeset V(sram[1766]->outb) vsp -Xmux_1level_tapbuf_size2[125] grid[1][2]_pin[0][2][1] chany[0][1]_in[66] chanx[1][1]_out[30] sram[1767]->outb sram[1767]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[125], level=1, select_path_id=0. ***** -*****1***** -Xsram[1767] sram->in sram[1767]->out sram[1767]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1767]->out) 0 -.nodeset V(sram[1767]->outb) vsp -Xmux_1level_tapbuf_size2[126] grid[1][2]_pin[0][2][1] chany[0][1]_in[64] chanx[1][1]_out[32] sram[1768]->outb sram[1768]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[126], level=1, select_path_id=0. ***** -*****1***** -Xsram[1768] sram->in sram[1768]->out sram[1768]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1768]->out) 0 -.nodeset V(sram[1768]->outb) vsp -Xmux_1level_tapbuf_size2[127] grid[1][2]_pin[0][2][1] chany[0][1]_in[62] chanx[1][1]_out[34] sram[1769]->outb sram[1769]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[127], level=1, select_path_id=0. ***** -*****1***** -Xsram[1769] sram->in sram[1769]->out sram[1769]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1769]->out) 0 -.nodeset V(sram[1769]->outb) vsp -Xmux_1level_tapbuf_size2[128] grid[1][2]_pin[0][2][1] chany[0][1]_in[60] chanx[1][1]_out[36] sram[1770]->outb sram[1770]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[128], level=1, select_path_id=0. ***** -*****1***** -Xsram[1770] sram->in sram[1770]->out sram[1770]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1770]->out) 0 -.nodeset V(sram[1770]->outb) vsp -Xmux_1level_tapbuf_size2[129] grid[1][2]_pin[0][2][1] chany[0][1]_in[58] chanx[1][1]_out[38] sram[1771]->outb sram[1771]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[129], level=1, select_path_id=0. ***** -*****1***** -Xsram[1771] sram->in sram[1771]->out sram[1771]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1771]->out) 0 -.nodeset V(sram[1771]->outb) vsp -Xmux_1level_tapbuf_size2[130] grid[1][2]_pin[0][2][3] chany[0][1]_in[56] chanx[1][1]_out[40] sram[1772]->outb sram[1772]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[130], level=1, select_path_id=0. ***** -*****1***** -Xsram[1772] sram->in sram[1772]->out sram[1772]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1772]->out) 0 -.nodeset V(sram[1772]->outb) vsp -Xmux_1level_tapbuf_size2[131] grid[1][2]_pin[0][2][3] chany[0][1]_in[54] chanx[1][1]_out[42] sram[1773]->outb sram[1773]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[131], level=1, select_path_id=0. ***** -*****1***** -Xsram[1773] sram->in sram[1773]->out sram[1773]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1773]->out) 0 -.nodeset V(sram[1773]->outb) vsp -Xmux_1level_tapbuf_size2[132] grid[1][2]_pin[0][2][3] chany[0][1]_in[52] chanx[1][1]_out[44] sram[1774]->outb sram[1774]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[132], level=1, select_path_id=0. ***** -*****1***** -Xsram[1774] sram->in sram[1774]->out sram[1774]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1774]->out) 0 -.nodeset V(sram[1774]->outb) vsp -Xmux_1level_tapbuf_size2[133] grid[1][2]_pin[0][2][3] chany[0][1]_in[50] chanx[1][1]_out[46] sram[1775]->outb sram[1775]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[133], level=1, select_path_id=0. ***** -*****1***** -Xsram[1775] sram->in sram[1775]->out sram[1775]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1775]->out) 0 -.nodeset V(sram[1775]->outb) vsp -Xmux_1level_tapbuf_size2[134] grid[1][2]_pin[0][2][3] chany[0][1]_in[48] chanx[1][1]_out[48] sram[1776]->outb sram[1776]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[134], level=1, select_path_id=0. ***** -*****1***** -Xsram[1776] sram->in sram[1776]->out sram[1776]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1776]->out) 0 -.nodeset V(sram[1776]->outb) vsp -Xmux_1level_tapbuf_size2[135] grid[1][2]_pin[0][2][5] chany[0][1]_in[46] chanx[1][1]_out[50] sram[1777]->outb sram[1777]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[135], level=1, select_path_id=0. ***** -*****1***** -Xsram[1777] sram->in sram[1777]->out sram[1777]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1777]->out) 0 -.nodeset V(sram[1777]->outb) vsp -Xmux_1level_tapbuf_size2[136] grid[1][2]_pin[0][2][5] chany[0][1]_in[44] chanx[1][1]_out[52] sram[1778]->outb sram[1778]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[136], level=1, select_path_id=0. ***** -*****1***** -Xsram[1778] sram->in sram[1778]->out sram[1778]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1778]->out) 0 -.nodeset V(sram[1778]->outb) vsp -Xmux_1level_tapbuf_size2[137] grid[1][2]_pin[0][2][5] chany[0][1]_in[42] chanx[1][1]_out[54] sram[1779]->outb sram[1779]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[137], level=1, select_path_id=0. ***** -*****1***** -Xsram[1779] sram->in sram[1779]->out sram[1779]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1779]->out) 0 -.nodeset V(sram[1779]->outb) vsp -Xmux_1level_tapbuf_size2[138] grid[1][2]_pin[0][2][5] chany[0][1]_in[40] chanx[1][1]_out[56] sram[1780]->outb sram[1780]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[138], level=1, select_path_id=0. ***** -*****1***** -Xsram[1780] sram->in sram[1780]->out sram[1780]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1780]->out) 0 -.nodeset V(sram[1780]->outb) vsp -Xmux_1level_tapbuf_size2[139] grid[1][2]_pin[0][2][5] chany[0][1]_in[38] chanx[1][1]_out[58] sram[1781]->outb sram[1781]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[139], level=1, select_path_id=0. ***** -*****1***** -Xsram[1781] sram->in sram[1781]->out sram[1781]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1781]->out) 0 -.nodeset V(sram[1781]->outb) vsp -Xmux_1level_tapbuf_size2[140] grid[1][2]_pin[0][2][7] chany[0][1]_in[36] chanx[1][1]_out[60] sram[1782]->outb sram[1782]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[140], level=1, select_path_id=0. ***** -*****1***** -Xsram[1782] sram->in sram[1782]->out sram[1782]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1782]->out) 0 -.nodeset V(sram[1782]->outb) vsp -Xmux_1level_tapbuf_size2[141] grid[1][2]_pin[0][2][7] chany[0][1]_in[34] chanx[1][1]_out[62] sram[1783]->outb sram[1783]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[141], level=1, select_path_id=0. ***** -*****1***** -Xsram[1783] sram->in sram[1783]->out sram[1783]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1783]->out) 0 -.nodeset V(sram[1783]->outb) vsp -Xmux_1level_tapbuf_size2[142] grid[1][2]_pin[0][2][7] chany[0][1]_in[32] chanx[1][1]_out[64] sram[1784]->outb sram[1784]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[142], level=1, select_path_id=0. ***** -*****1***** -Xsram[1784] sram->in sram[1784]->out sram[1784]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1784]->out) 0 -.nodeset V(sram[1784]->outb) vsp -Xmux_1level_tapbuf_size2[143] grid[1][2]_pin[0][2][7] chany[0][1]_in[30] chanx[1][1]_out[66] sram[1785]->outb sram[1785]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[143], level=1, select_path_id=0. ***** -*****1***** -Xsram[1785] sram->in sram[1785]->out sram[1785]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1785]->out) 0 -.nodeset V(sram[1785]->outb) vsp -Xmux_1level_tapbuf_size2[144] grid[1][2]_pin[0][2][7] chany[0][1]_in[28] chanx[1][1]_out[68] sram[1786]->outb sram[1786]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[144], level=1, select_path_id=0. ***** -*****1***** -Xsram[1786] sram->in sram[1786]->out sram[1786]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1786]->out) 0 -.nodeset V(sram[1786]->outb) vsp -Xmux_1level_tapbuf_size2[145] grid[1][2]_pin[0][2][9] chany[0][1]_in[26] chanx[1][1]_out[70] sram[1787]->outb sram[1787]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[145], level=1, select_path_id=0. ***** -*****1***** -Xsram[1787] sram->in sram[1787]->out sram[1787]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1787]->out) 0 -.nodeset V(sram[1787]->outb) vsp -Xmux_1level_tapbuf_size2[146] grid[1][2]_pin[0][2][9] chany[0][1]_in[24] chanx[1][1]_out[72] sram[1788]->outb sram[1788]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[146], level=1, select_path_id=0. ***** -*****1***** -Xsram[1788] sram->in sram[1788]->out sram[1788]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1788]->out) 0 -.nodeset V(sram[1788]->outb) vsp -Xmux_1level_tapbuf_size2[147] grid[1][2]_pin[0][2][9] chany[0][1]_in[22] chanx[1][1]_out[74] sram[1789]->outb sram[1789]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[147], level=1, select_path_id=0. ***** -*****1***** -Xsram[1789] sram->in sram[1789]->out sram[1789]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1789]->out) 0 -.nodeset V(sram[1789]->outb) vsp -Xmux_1level_tapbuf_size2[148] grid[1][2]_pin[0][2][9] chany[0][1]_in[20] chanx[1][1]_out[76] sram[1790]->outb sram[1790]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[148], level=1, select_path_id=0. ***** -*****1***** -Xsram[1790] sram->in sram[1790]->out sram[1790]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1790]->out) 0 -.nodeset V(sram[1790]->outb) vsp -Xmux_1level_tapbuf_size2[149] grid[1][2]_pin[0][2][9] chany[0][1]_in[18] chanx[1][1]_out[78] sram[1791]->outb sram[1791]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[149], level=1, select_path_id=0. ***** -*****1***** -Xsram[1791] sram->in sram[1791]->out sram[1791]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1791]->out) 0 -.nodeset V(sram[1791]->outb) vsp -Xmux_1level_tapbuf_size2[150] grid[1][2]_pin[0][2][11] chany[0][1]_in[16] chanx[1][1]_out[80] sram[1792]->outb sram[1792]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[150], level=1, select_path_id=0. ***** -*****1***** -Xsram[1792] sram->in sram[1792]->out sram[1792]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1792]->out) 0 -.nodeset V(sram[1792]->outb) vsp -Xmux_1level_tapbuf_size2[151] grid[1][2]_pin[0][2][11] chany[0][1]_in[14] chanx[1][1]_out[82] sram[1793]->outb sram[1793]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[151], level=1, select_path_id=0. ***** -*****1***** -Xsram[1793] sram->in sram[1793]->out sram[1793]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1793]->out) 0 -.nodeset V(sram[1793]->outb) vsp -Xmux_1level_tapbuf_size2[152] grid[1][2]_pin[0][2][11] chany[0][1]_in[12] chanx[1][1]_out[84] sram[1794]->outb sram[1794]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[152], level=1, select_path_id=0. ***** -*****1***** -Xsram[1794] sram->in sram[1794]->out sram[1794]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1794]->out) 0 -.nodeset V(sram[1794]->outb) vsp -Xmux_1level_tapbuf_size2[153] grid[1][2]_pin[0][2][11] chany[0][1]_in[10] chanx[1][1]_out[86] sram[1795]->outb sram[1795]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[153], level=1, select_path_id=0. ***** -*****1***** -Xsram[1795] sram->in sram[1795]->out sram[1795]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1795]->out) 0 -.nodeset V(sram[1795]->outb) vsp -Xmux_1level_tapbuf_size2[154] grid[1][2]_pin[0][2][11] chany[0][1]_in[8] chanx[1][1]_out[88] sram[1796]->outb sram[1796]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[154], level=1, select_path_id=0. ***** -*****1***** -Xsram[1796] sram->in sram[1796]->out sram[1796]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1796]->out) 0 -.nodeset V(sram[1796]->outb) vsp -Xmux_1level_tapbuf_size2[155] grid[1][2]_pin[0][2][13] chany[0][1]_in[6] chanx[1][1]_out[90] sram[1797]->outb sram[1797]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[155], level=1, select_path_id=0. ***** -*****1***** -Xsram[1797] sram->in sram[1797]->out sram[1797]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1797]->out) 0 -.nodeset V(sram[1797]->outb) vsp -Xmux_1level_tapbuf_size2[156] grid[1][2]_pin[0][2][13] chany[0][1]_in[4] chanx[1][1]_out[92] sram[1798]->outb sram[1798]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[156], level=1, select_path_id=0. ***** -*****1***** -Xsram[1798] sram->in sram[1798]->out sram[1798]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1798]->out) 0 -.nodeset V(sram[1798]->outb) vsp -Xmux_1level_tapbuf_size2[157] grid[1][2]_pin[0][2][13] chany[0][1]_in[2] chanx[1][1]_out[94] sram[1799]->outb sram[1799]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[157], level=1, select_path_id=0. ***** -*****1***** -Xsram[1799] sram->in sram[1799]->out sram[1799]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1799]->out) 0 -.nodeset V(sram[1799]->outb) vsp -Xmux_1level_tapbuf_size2[158] grid[1][2]_pin[0][2][13] chany[0][1]_in[0] chanx[1][1]_out[96] sram[1800]->outb sram[1800]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[158], level=1, select_path_id=0. ***** -*****1***** -Xsram[1800] sram->in sram[1800]->out sram[1800]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1800]->out) 0 -.nodeset V(sram[1800]->outb) vsp -Xmux_1level_tapbuf_size2[159] grid[1][2]_pin[0][2][13] chany[0][1]_in[98] chanx[1][1]_out[98] sram[1801]->outb sram[1801]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[159], level=1, select_path_id=0. ***** -*****1***** -Xsram[1801] sram->in sram[1801]->out sram[1801]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1801]->out) 0 -.nodeset V(sram[1801]->outb) vsp -***** bottom side Multiplexers ***** -Xmux_1level_tapbuf_size2[160] grid[0][1]_pin[0][1][1] chanx[1][1]_in[97] chany[0][1]_out[1] sram[1802]->outb sram[1802]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[160], level=1, select_path_id=0. ***** -*****1***** -Xsram[1802] sram->in sram[1802]->out sram[1802]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1802]->out) 0 -.nodeset V(sram[1802]->outb) vsp -Xmux_1level_tapbuf_size2[161] grid[0][1]_pin[0][1][1] chanx[1][1]_in[95] chany[0][1]_out[3] sram[1803]->outb sram[1803]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[161], level=1, select_path_id=0. ***** -*****1***** -Xsram[1803] sram->in sram[1803]->out sram[1803]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1803]->out) 0 -.nodeset V(sram[1803]->outb) vsp -Xmux_1level_tapbuf_size2[162] grid[0][1]_pin[0][1][1] chanx[1][1]_in[93] chany[0][1]_out[5] sram[1804]->outb sram[1804]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[162], level=1, select_path_id=0. ***** -*****1***** -Xsram[1804] sram->in sram[1804]->out sram[1804]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1804]->out) 0 -.nodeset V(sram[1804]->outb) vsp -Xmux_1level_tapbuf_size2[163] grid[0][1]_pin[0][1][1] chanx[1][1]_in[91] chany[0][1]_out[7] sram[1805]->outb sram[1805]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[163], level=1, select_path_id=0. ***** -*****1***** -Xsram[1805] sram->in sram[1805]->out sram[1805]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1805]->out) 0 -.nodeset V(sram[1805]->outb) vsp -Xmux_1level_tapbuf_size2[164] grid[0][1]_pin[0][1][1] chanx[1][1]_in[89] chany[0][1]_out[9] sram[1806]->outb sram[1806]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[164], level=1, select_path_id=0. ***** -*****1***** -Xsram[1806] sram->in sram[1806]->out sram[1806]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1806]->out) 0 -.nodeset V(sram[1806]->outb) vsp -Xmux_1level_tapbuf_size2[165] grid[0][1]_pin[0][1][3] chanx[1][1]_in[87] chany[0][1]_out[11] sram[1807]->outb sram[1807]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[165], level=1, select_path_id=0. ***** -*****1***** -Xsram[1807] sram->in sram[1807]->out sram[1807]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1807]->out) 0 -.nodeset V(sram[1807]->outb) vsp -Xmux_1level_tapbuf_size2[166] grid[0][1]_pin[0][1][3] chanx[1][1]_in[85] chany[0][1]_out[13] sram[1808]->outb sram[1808]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[166], level=1, select_path_id=0. ***** -*****1***** -Xsram[1808] sram->in sram[1808]->out sram[1808]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1808]->out) 0 -.nodeset V(sram[1808]->outb) vsp -Xmux_1level_tapbuf_size2[167] grid[0][1]_pin[0][1][3] chanx[1][1]_in[83] chany[0][1]_out[15] sram[1809]->outb sram[1809]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[167], level=1, select_path_id=0. ***** -*****1***** -Xsram[1809] sram->in sram[1809]->out sram[1809]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1809]->out) 0 -.nodeset V(sram[1809]->outb) vsp -Xmux_1level_tapbuf_size2[168] grid[0][1]_pin[0][1][3] chanx[1][1]_in[81] chany[0][1]_out[17] sram[1810]->outb sram[1810]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[168], level=1, select_path_id=0. ***** -*****1***** -Xsram[1810] sram->in sram[1810]->out sram[1810]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1810]->out) 0 -.nodeset V(sram[1810]->outb) vsp -Xmux_1level_tapbuf_size2[169] grid[0][1]_pin[0][1][3] chanx[1][1]_in[79] chany[0][1]_out[19] sram[1811]->outb sram[1811]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[169], level=1, select_path_id=0. ***** -*****1***** -Xsram[1811] sram->in sram[1811]->out sram[1811]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1811]->out) 0 -.nodeset V(sram[1811]->outb) vsp -Xmux_1level_tapbuf_size2[170] grid[0][1]_pin[0][1][5] chanx[1][1]_in[77] chany[0][1]_out[21] sram[1812]->outb sram[1812]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[170], level=1, select_path_id=0. ***** -*****1***** -Xsram[1812] sram->in sram[1812]->out sram[1812]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1812]->out) 0 -.nodeset V(sram[1812]->outb) vsp -Xmux_1level_tapbuf_size2[171] grid[0][1]_pin[0][1][5] chanx[1][1]_in[75] chany[0][1]_out[23] sram[1813]->outb sram[1813]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[171], level=1, select_path_id=0. ***** -*****1***** -Xsram[1813] sram->in sram[1813]->out sram[1813]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1813]->out) 0 -.nodeset V(sram[1813]->outb) vsp -Xmux_1level_tapbuf_size2[172] grid[0][1]_pin[0][1][5] chanx[1][1]_in[73] chany[0][1]_out[25] sram[1814]->outb sram[1814]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[172], level=1, select_path_id=0. ***** -*****1***** -Xsram[1814] sram->in sram[1814]->out sram[1814]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1814]->out) 0 -.nodeset V(sram[1814]->outb) vsp -Xmux_1level_tapbuf_size2[173] grid[0][1]_pin[0][1][5] chanx[1][1]_in[71] chany[0][1]_out[27] sram[1815]->outb sram[1815]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[173], level=1, select_path_id=0. ***** -*****1***** -Xsram[1815] sram->in sram[1815]->out sram[1815]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1815]->out) 0 -.nodeset V(sram[1815]->outb) vsp -Xmux_1level_tapbuf_size2[174] grid[0][1]_pin[0][1][5] chanx[1][1]_in[69] chany[0][1]_out[29] sram[1816]->outb sram[1816]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[174], level=1, select_path_id=0. ***** -*****1***** -Xsram[1816] sram->in sram[1816]->out sram[1816]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1816]->out) 0 -.nodeset V(sram[1816]->outb) vsp -Xmux_1level_tapbuf_size2[175] grid[0][1]_pin[0][1][7] chanx[1][1]_in[67] chany[0][1]_out[31] sram[1817]->outb sram[1817]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[175], level=1, select_path_id=0. ***** -*****1***** -Xsram[1817] sram->in sram[1817]->out sram[1817]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1817]->out) 0 -.nodeset V(sram[1817]->outb) vsp -Xmux_1level_tapbuf_size2[176] grid[0][1]_pin[0][1][7] chanx[1][1]_in[65] chany[0][1]_out[33] sram[1818]->outb sram[1818]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[176], level=1, select_path_id=0. ***** -*****1***** -Xsram[1818] sram->in sram[1818]->out sram[1818]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1818]->out) 0 -.nodeset V(sram[1818]->outb) vsp -Xmux_1level_tapbuf_size2[177] grid[0][1]_pin[0][1][7] chanx[1][1]_in[63] chany[0][1]_out[35] sram[1819]->outb sram[1819]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[177], level=1, select_path_id=0. ***** -*****1***** -Xsram[1819] sram->in sram[1819]->out sram[1819]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1819]->out) 0 -.nodeset V(sram[1819]->outb) vsp -Xmux_1level_tapbuf_size2[178] grid[0][1]_pin[0][1][7] chanx[1][1]_in[61] chany[0][1]_out[37] sram[1820]->outb sram[1820]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[178], level=1, select_path_id=0. ***** -*****1***** -Xsram[1820] sram->in sram[1820]->out sram[1820]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1820]->out) 0 -.nodeset V(sram[1820]->outb) vsp -Xmux_1level_tapbuf_size2[179] grid[0][1]_pin[0][1][7] chanx[1][1]_in[59] chany[0][1]_out[39] sram[1821]->outb sram[1821]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[179], level=1, select_path_id=0. ***** -*****1***** -Xsram[1821] sram->in sram[1821]->out sram[1821]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1821]->out) 0 -.nodeset V(sram[1821]->outb) vsp -Xmux_1level_tapbuf_size2[180] grid[0][1]_pin[0][1][9] chanx[1][1]_in[57] chany[0][1]_out[41] sram[1822]->outb sram[1822]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[180], level=1, select_path_id=0. ***** -*****1***** -Xsram[1822] sram->in sram[1822]->out sram[1822]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1822]->out) 0 -.nodeset V(sram[1822]->outb) vsp -Xmux_1level_tapbuf_size2[181] grid[0][1]_pin[0][1][9] chanx[1][1]_in[55] chany[0][1]_out[43] sram[1823]->outb sram[1823]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[181], level=1, select_path_id=0. ***** -*****1***** -Xsram[1823] sram->in sram[1823]->out sram[1823]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1823]->out) 0 -.nodeset V(sram[1823]->outb) vsp -Xmux_1level_tapbuf_size2[182] grid[0][1]_pin[0][1][9] chanx[1][1]_in[53] chany[0][1]_out[45] sram[1824]->outb sram[1824]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[182], level=1, select_path_id=0. ***** -*****1***** -Xsram[1824] sram->in sram[1824]->out sram[1824]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1824]->out) 0 -.nodeset V(sram[1824]->outb) vsp -Xmux_1level_tapbuf_size2[183] grid[0][1]_pin[0][1][9] chanx[1][1]_in[51] chany[0][1]_out[47] sram[1825]->outb sram[1825]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[183], level=1, select_path_id=0. ***** -*****1***** -Xsram[1825] sram->in sram[1825]->out sram[1825]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1825]->out) 0 -.nodeset V(sram[1825]->outb) vsp -Xmux_1level_tapbuf_size2[184] grid[0][1]_pin[0][1][9] chanx[1][1]_in[49] chany[0][1]_out[49] sram[1826]->outb sram[1826]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[184], level=1, select_path_id=0. ***** -*****1***** -Xsram[1826] sram->in sram[1826]->out sram[1826]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1826]->out) 0 -.nodeset V(sram[1826]->outb) vsp -Xmux_1level_tapbuf_size2[185] grid[0][1]_pin[0][1][11] chanx[1][1]_in[47] chany[0][1]_out[51] sram[1827]->outb sram[1827]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[185], level=1, select_path_id=0. ***** -*****1***** -Xsram[1827] sram->in sram[1827]->out sram[1827]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1827]->out) 0 -.nodeset V(sram[1827]->outb) vsp -Xmux_1level_tapbuf_size2[186] grid[0][1]_pin[0][1][11] chanx[1][1]_in[45] chany[0][1]_out[53] sram[1828]->outb sram[1828]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[186], level=1, select_path_id=0. ***** -*****1***** -Xsram[1828] sram->in sram[1828]->out sram[1828]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1828]->out) 0 -.nodeset V(sram[1828]->outb) vsp -Xmux_1level_tapbuf_size2[187] grid[0][1]_pin[0][1][11] chanx[1][1]_in[43] chany[0][1]_out[55] sram[1829]->outb sram[1829]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[187], level=1, select_path_id=0. ***** -*****1***** -Xsram[1829] sram->in sram[1829]->out sram[1829]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1829]->out) 0 -.nodeset V(sram[1829]->outb) vsp -Xmux_1level_tapbuf_size2[188] grid[0][1]_pin[0][1][11] chanx[1][1]_in[41] chany[0][1]_out[57] sram[1830]->outb sram[1830]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[188], level=1, select_path_id=0. ***** -*****1***** -Xsram[1830] sram->in sram[1830]->out sram[1830]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1830]->out) 0 -.nodeset V(sram[1830]->outb) vsp -Xmux_1level_tapbuf_size2[189] grid[0][1]_pin[0][1][11] chanx[1][1]_in[39] chany[0][1]_out[59] sram[1831]->outb sram[1831]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[189], level=1, select_path_id=0. ***** -*****1***** -Xsram[1831] sram->in sram[1831]->out sram[1831]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1831]->out) 0 -.nodeset V(sram[1831]->outb) vsp -Xmux_1level_tapbuf_size2[190] grid[0][1]_pin[0][1][13] chanx[1][1]_in[37] chany[0][1]_out[61] sram[1832]->outb sram[1832]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[190], level=1, select_path_id=0. ***** -*****1***** -Xsram[1832] sram->in sram[1832]->out sram[1832]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1832]->out) 0 -.nodeset V(sram[1832]->outb) vsp -Xmux_1level_tapbuf_size2[191] grid[0][1]_pin[0][1][13] chanx[1][1]_in[35] chany[0][1]_out[63] sram[1833]->outb sram[1833]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[191], level=1, select_path_id=0. ***** -*****1***** -Xsram[1833] sram->in sram[1833]->out sram[1833]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1833]->out) 0 -.nodeset V(sram[1833]->outb) vsp -Xmux_1level_tapbuf_size2[192] grid[0][1]_pin[0][1][13] chanx[1][1]_in[33] chany[0][1]_out[65] sram[1834]->outb sram[1834]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[192], level=1, select_path_id=0. ***** -*****1***** -Xsram[1834] sram->in sram[1834]->out sram[1834]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1834]->out) 0 -.nodeset V(sram[1834]->outb) vsp -Xmux_1level_tapbuf_size2[193] grid[0][1]_pin[0][1][13] chanx[1][1]_in[31] chany[0][1]_out[67] sram[1835]->outb sram[1835]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[193], level=1, select_path_id=0. ***** -*****1***** -Xsram[1835] sram->in sram[1835]->out sram[1835]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1835]->out) 0 -.nodeset V(sram[1835]->outb) vsp -Xmux_1level_tapbuf_size2[194] grid[0][1]_pin[0][1][13] chanx[1][1]_in[29] chany[0][1]_out[69] sram[1836]->outb sram[1836]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[194], level=1, select_path_id=0. ***** -*****1***** -Xsram[1836] sram->in sram[1836]->out sram[1836]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1836]->out) 0 -.nodeset V(sram[1836]->outb) vsp -Xmux_1level_tapbuf_size2[195] grid[0][1]_pin[0][1][15] chanx[1][1]_in[27] chany[0][1]_out[71] sram[1837]->outb sram[1837]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[195], level=1, select_path_id=0. ***** -*****1***** -Xsram[1837] sram->in sram[1837]->out sram[1837]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1837]->out) 0 -.nodeset V(sram[1837]->outb) vsp -Xmux_1level_tapbuf_size2[196] grid[0][1]_pin[0][1][15] chanx[1][1]_in[25] chany[0][1]_out[73] sram[1838]->outb sram[1838]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[196], level=1, select_path_id=0. ***** -*****1***** -Xsram[1838] sram->in sram[1838]->out sram[1838]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1838]->out) 0 -.nodeset V(sram[1838]->outb) vsp -Xmux_1level_tapbuf_size2[197] grid[0][1]_pin[0][1][15] chanx[1][1]_in[23] chany[0][1]_out[75] sram[1839]->outb sram[1839]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[197], level=1, select_path_id=0. ***** -*****1***** -Xsram[1839] sram->in sram[1839]->out sram[1839]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1839]->out) 0 -.nodeset V(sram[1839]->outb) vsp -Xmux_1level_tapbuf_size2[198] grid[0][1]_pin[0][1][15] chanx[1][1]_in[21] chany[0][1]_out[77] sram[1840]->outb sram[1840]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[198], level=1, select_path_id=0. ***** -*****1***** -Xsram[1840] sram->in sram[1840]->out sram[1840]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1840]->out) 0 -.nodeset V(sram[1840]->outb) vsp -Xmux_1level_tapbuf_size2[199] grid[0][1]_pin[0][1][15] chanx[1][1]_in[19] chany[0][1]_out[79] sram[1841]->outb sram[1841]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[199], level=1, select_path_id=0. ***** -*****1***** -Xsram[1841] sram->in sram[1841]->out sram[1841]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1841]->out) 0 -.nodeset V(sram[1841]->outb) vsp -Xmux_1level_tapbuf_size2[200] grid[1][1]_pin[0][3][43] chanx[1][1]_in[17] chany[0][1]_out[81] sram[1842]->outb sram[1842]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[200], level=1, select_path_id=0. ***** -*****1***** -Xsram[1842] sram->in sram[1842]->out sram[1842]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1842]->out) 0 -.nodeset V(sram[1842]->outb) vsp -Xmux_1level_tapbuf_size2[201] grid[1][1]_pin[0][3][43] chanx[1][1]_in[15] chany[0][1]_out[83] sram[1843]->outb sram[1843]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[201], level=1, select_path_id=0. ***** -*****1***** -Xsram[1843] sram->in sram[1843]->out sram[1843]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1843]->out) 0 -.nodeset V(sram[1843]->outb) vsp -Xmux_1level_tapbuf_size2[202] grid[1][1]_pin[0][3][43] chanx[1][1]_in[13] chany[0][1]_out[85] sram[1844]->outb sram[1844]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[202], level=1, select_path_id=0. ***** -*****1***** -Xsram[1844] sram->in sram[1844]->out sram[1844]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1844]->out) 0 -.nodeset V(sram[1844]->outb) vsp -Xmux_1level_tapbuf_size2[203] grid[1][1]_pin[0][3][43] chanx[1][1]_in[11] chany[0][1]_out[87] sram[1845]->outb sram[1845]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[203], level=1, select_path_id=0. ***** -*****1***** -Xsram[1845] sram->in sram[1845]->out sram[1845]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1845]->out) 0 -.nodeset V(sram[1845]->outb) vsp -Xmux_1level_tapbuf_size2[204] grid[1][1]_pin[0][3][43] chanx[1][1]_in[9] chany[0][1]_out[89] sram[1846]->outb sram[1846]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[204], level=1, select_path_id=0. ***** -*****1***** -Xsram[1846] sram->in sram[1846]->out sram[1846]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1846]->out) 0 -.nodeset V(sram[1846]->outb) vsp -Xmux_1level_tapbuf_size2[205] grid[1][1]_pin[0][3][47] chanx[1][1]_in[7] chany[0][1]_out[91] sram[1847]->outb sram[1847]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[205], level=1, select_path_id=0. ***** -*****1***** -Xsram[1847] sram->in sram[1847]->out sram[1847]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1847]->out) 0 -.nodeset V(sram[1847]->outb) vsp -Xmux_1level_tapbuf_size2[206] grid[1][1]_pin[0][3][47] chanx[1][1]_in[5] chany[0][1]_out[93] sram[1848]->outb sram[1848]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[206], level=1, select_path_id=0. ***** -*****1***** -Xsram[1848] sram->in sram[1848]->out sram[1848]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1848]->out) 0 -.nodeset V(sram[1848]->outb) vsp -Xmux_1level_tapbuf_size2[207] grid[1][1]_pin[0][3][47] chanx[1][1]_in[3] chany[0][1]_out[95] sram[1849]->outb sram[1849]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[207], level=1, select_path_id=0. ***** -*****1***** -Xsram[1849] sram->in sram[1849]->out sram[1849]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1849]->out) 0 -.nodeset V(sram[1849]->outb) vsp -Xmux_1level_tapbuf_size2[208] grid[1][1]_pin[0][3][47] chanx[1][1]_in[1] chany[0][1]_out[97] sram[1850]->outb sram[1850]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[208], level=1, select_path_id=0. ***** -*****1***** -Xsram[1850] sram->in sram[1850]->out sram[1850]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1850]->out) 0 -.nodeset V(sram[1850]->outb) vsp -Xmux_1level_tapbuf_size2[209] grid[1][1]_pin[0][3][47] chanx[1][1]_in[99] chany[0][1]_out[99] sram[1851]->outb sram[1851]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[209], level=1, select_path_id=0. ***** -*****1***** -Xsram[1851] sram->in sram[1851]->out sram[1851]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1851]->out) 0 -.nodeset V(sram[1851]->outb) vsp -***** left side Multiplexers ***** -.eom diff --git a/examples/spice_test_example_2/subckt/sb_1_0.sp b/examples/spice_test_example_2/subckt/sb_1_0.sp deleted file mode 100644 index 0691b0265..000000000 --- a/examples/spice_test_example_2/subckt/sb_1_0.sp +++ /dev/null @@ -1,658 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Switch Block [1][0] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Switch Box[1][0] Sub-Circuit ***** -.subckt sb[1][0] -***** Inputs/outputs of top side ***** -+ chany[1][1]_out[0] chany[1][1]_in[1] chany[1][1]_out[2] chany[1][1]_in[3] chany[1][1]_out[4] chany[1][1]_in[5] chany[1][1]_out[6] chany[1][1]_in[7] chany[1][1]_out[8] chany[1][1]_in[9] chany[1][1]_out[10] chany[1][1]_in[11] chany[1][1]_out[12] chany[1][1]_in[13] chany[1][1]_out[14] chany[1][1]_in[15] chany[1][1]_out[16] chany[1][1]_in[17] chany[1][1]_out[18] chany[1][1]_in[19] chany[1][1]_out[20] chany[1][1]_in[21] chany[1][1]_out[22] chany[1][1]_in[23] chany[1][1]_out[24] chany[1][1]_in[25] chany[1][1]_out[26] chany[1][1]_in[27] chany[1][1]_out[28] chany[1][1]_in[29] chany[1][1]_out[30] chany[1][1]_in[31] chany[1][1]_out[32] chany[1][1]_in[33] chany[1][1]_out[34] chany[1][1]_in[35] chany[1][1]_out[36] chany[1][1]_in[37] chany[1][1]_out[38] chany[1][1]_in[39] chany[1][1]_out[40] chany[1][1]_in[41] chany[1][1]_out[42] chany[1][1]_in[43] chany[1][1]_out[44] chany[1][1]_in[45] chany[1][1]_out[46] chany[1][1]_in[47] chany[1][1]_out[48] chany[1][1]_in[49] chany[1][1]_out[50] chany[1][1]_in[51] chany[1][1]_out[52] chany[1][1]_in[53] chany[1][1]_out[54] chany[1][1]_in[55] chany[1][1]_out[56] chany[1][1]_in[57] chany[1][1]_out[58] chany[1][1]_in[59] chany[1][1]_out[60] chany[1][1]_in[61] chany[1][1]_out[62] chany[1][1]_in[63] chany[1][1]_out[64] chany[1][1]_in[65] chany[1][1]_out[66] chany[1][1]_in[67] chany[1][1]_out[68] chany[1][1]_in[69] chany[1][1]_out[70] chany[1][1]_in[71] chany[1][1]_out[72] chany[1][1]_in[73] chany[1][1]_out[74] chany[1][1]_in[75] chany[1][1]_out[76] chany[1][1]_in[77] chany[1][1]_out[78] chany[1][1]_in[79] chany[1][1]_out[80] chany[1][1]_in[81] chany[1][1]_out[82] chany[1][1]_in[83] chany[1][1]_out[84] chany[1][1]_in[85] chany[1][1]_out[86] chany[1][1]_in[87] chany[1][1]_out[88] chany[1][1]_in[89] chany[1][1]_out[90] chany[1][1]_in[91] chany[1][1]_out[92] chany[1][1]_in[93] chany[1][1]_out[94] chany[1][1]_in[95] chany[1][1]_out[96] chany[1][1]_in[97] chany[1][1]_out[98] chany[1][1]_in[99] -+ grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][49] grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] -+ ***** Inputs/outputs of right side ***** -+ -+ -+ ***** Inputs/outputs of bottom side ***** -+ -+ -+ ***** Inputs/outputs of left side ***** -+ chanx[1][0]_in[0] chanx[1][0]_out[1] chanx[1][0]_in[2] chanx[1][0]_out[3] chanx[1][0]_in[4] chanx[1][0]_out[5] chanx[1][0]_in[6] chanx[1][0]_out[7] chanx[1][0]_in[8] chanx[1][0]_out[9] chanx[1][0]_in[10] chanx[1][0]_out[11] chanx[1][0]_in[12] chanx[1][0]_out[13] chanx[1][0]_in[14] chanx[1][0]_out[15] chanx[1][0]_in[16] chanx[1][0]_out[17] chanx[1][0]_in[18] chanx[1][0]_out[19] chanx[1][0]_in[20] chanx[1][0]_out[21] chanx[1][0]_in[22] chanx[1][0]_out[23] chanx[1][0]_in[24] chanx[1][0]_out[25] chanx[1][0]_in[26] chanx[1][0]_out[27] chanx[1][0]_in[28] chanx[1][0]_out[29] chanx[1][0]_in[30] chanx[1][0]_out[31] chanx[1][0]_in[32] chanx[1][0]_out[33] chanx[1][0]_in[34] chanx[1][0]_out[35] chanx[1][0]_in[36] chanx[1][0]_out[37] chanx[1][0]_in[38] chanx[1][0]_out[39] chanx[1][0]_in[40] chanx[1][0]_out[41] chanx[1][0]_in[42] chanx[1][0]_out[43] chanx[1][0]_in[44] chanx[1][0]_out[45] chanx[1][0]_in[46] chanx[1][0]_out[47] chanx[1][0]_in[48] chanx[1][0]_out[49] chanx[1][0]_in[50] chanx[1][0]_out[51] chanx[1][0]_in[52] chanx[1][0]_out[53] chanx[1][0]_in[54] chanx[1][0]_out[55] chanx[1][0]_in[56] chanx[1][0]_out[57] chanx[1][0]_in[58] chanx[1][0]_out[59] chanx[1][0]_in[60] chanx[1][0]_out[61] chanx[1][0]_in[62] chanx[1][0]_out[63] chanx[1][0]_in[64] chanx[1][0]_out[65] chanx[1][0]_in[66] chanx[1][0]_out[67] chanx[1][0]_in[68] chanx[1][0]_out[69] chanx[1][0]_in[70] chanx[1][0]_out[71] chanx[1][0]_in[72] chanx[1][0]_out[73] chanx[1][0]_in[74] chanx[1][0]_out[75] chanx[1][0]_in[76] chanx[1][0]_out[77] chanx[1][0]_in[78] chanx[1][0]_out[79] chanx[1][0]_in[80] chanx[1][0]_out[81] chanx[1][0]_in[82] chanx[1][0]_out[83] chanx[1][0]_in[84] chanx[1][0]_out[85] chanx[1][0]_in[86] chanx[1][0]_out[87] chanx[1][0]_in[88] chanx[1][0]_out[89] chanx[1][0]_in[90] chanx[1][0]_out[91] chanx[1][0]_in[92] chanx[1][0]_out[93] chanx[1][0]_in[94] chanx[1][0]_out[95] chanx[1][0]_in[96] chanx[1][0]_out[97] chanx[1][0]_in[98] chanx[1][0]_out[99] -+ grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][46] grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ svdd sgnd -***** top side Multiplexers ***** -Xmux_1level_tapbuf_size3[210] grid[1][1]_pin[0][1][41] grid[2][1]_pin[0][3][15] chanx[1][0]_in[0] chany[1][1]_out[0] sram[1852]->outb sram[1852]->out sram[1853]->out sram[1853]->outb sram[1854]->out sram[1854]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[210], level=1, select_path_id=0. ***** -*****100***** -Xsram[1852] sram->in sram[1852]->out sram[1852]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1852]->out) 0 -.nodeset V(sram[1852]->outb) vsp -Xsram[1853] sram->in sram[1853]->out sram[1853]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1853]->out) 0 -.nodeset V(sram[1853]->outb) vsp -Xsram[1854] sram->in sram[1854]->out sram[1854]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1854]->out) 0 -.nodeset V(sram[1854]->outb) vsp -Xmux_1level_tapbuf_size3[211] grid[1][1]_pin[0][1][41] grid[2][1]_pin[0][3][15] chanx[1][0]_in[98] chany[1][1]_out[2] sram[1855]->outb sram[1855]->out sram[1856]->out sram[1856]->outb sram[1857]->out sram[1857]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[211], level=1, select_path_id=0. ***** -*****100***** -Xsram[1855] sram->in sram[1855]->out sram[1855]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1855]->out) 0 -.nodeset V(sram[1855]->outb) vsp -Xsram[1856] sram->in sram[1856]->out sram[1856]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1856]->out) 0 -.nodeset V(sram[1856]->outb) vsp -Xsram[1857] sram->in sram[1857]->out sram[1857]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1857]->out) 0 -.nodeset V(sram[1857]->outb) vsp -Xmux_1level_tapbuf_size3[212] grid[1][1]_pin[0][1][41] grid[2][1]_pin[0][3][15] chanx[1][0]_in[96] chany[1][1]_out[4] sram[1858]->outb sram[1858]->out sram[1859]->out sram[1859]->outb sram[1860]->out sram[1860]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[212], level=1, select_path_id=0. ***** -*****100***** -Xsram[1858] sram->in sram[1858]->out sram[1858]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1858]->out) 0 -.nodeset V(sram[1858]->outb) vsp -Xsram[1859] sram->in sram[1859]->out sram[1859]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1859]->out) 0 -.nodeset V(sram[1859]->outb) vsp -Xsram[1860] sram->in sram[1860]->out sram[1860]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1860]->out) 0 -.nodeset V(sram[1860]->outb) vsp -Xmux_1level_tapbuf_size3[213] grid[1][1]_pin[0][1][41] grid[2][1]_pin[0][3][15] chanx[1][0]_in[94] chany[1][1]_out[6] sram[1861]->outb sram[1861]->out sram[1862]->out sram[1862]->outb sram[1863]->out sram[1863]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[213], level=1, select_path_id=0. ***** -*****100***** -Xsram[1861] sram->in sram[1861]->out sram[1861]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1861]->out) 0 -.nodeset V(sram[1861]->outb) vsp -Xsram[1862] sram->in sram[1862]->out sram[1862]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1862]->out) 0 -.nodeset V(sram[1862]->outb) vsp -Xsram[1863] sram->in sram[1863]->out sram[1863]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1863]->out) 0 -.nodeset V(sram[1863]->outb) vsp -Xmux_1level_tapbuf_size3[214] grid[1][1]_pin[0][1][41] grid[2][1]_pin[0][3][15] chanx[1][0]_in[92] chany[1][1]_out[8] sram[1864]->outb sram[1864]->out sram[1865]->out sram[1865]->outb sram[1866]->out sram[1866]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[214], level=1, select_path_id=0. ***** -*****100***** -Xsram[1864] sram->in sram[1864]->out sram[1864]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1864]->out) 0 -.nodeset V(sram[1864]->outb) vsp -Xsram[1865] sram->in sram[1865]->out sram[1865]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1865]->out) 0 -.nodeset V(sram[1865]->outb) vsp -Xsram[1866] sram->in sram[1866]->out sram[1866]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1866]->out) 0 -.nodeset V(sram[1866]->outb) vsp -Xmux_1level_tapbuf_size2[215] grid[1][1]_pin[0][1][45] chanx[1][0]_in[90] chany[1][1]_out[10] sram[1867]->outb sram[1867]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[215], level=1, select_path_id=0. ***** -*****1***** -Xsram[1867] sram->in sram[1867]->out sram[1867]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1867]->out) 0 -.nodeset V(sram[1867]->outb) vsp -Xmux_1level_tapbuf_size2[216] grid[1][1]_pin[0][1][45] chanx[1][0]_in[88] chany[1][1]_out[12] sram[1868]->outb sram[1868]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[216], level=1, select_path_id=0. ***** -*****1***** -Xsram[1868] sram->in sram[1868]->out sram[1868]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1868]->out) 0 -.nodeset V(sram[1868]->outb) vsp -Xmux_1level_tapbuf_size2[217] grid[1][1]_pin[0][1][45] chanx[1][0]_in[86] chany[1][1]_out[14] sram[1869]->outb sram[1869]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[217], level=1, select_path_id=0. ***** -*****1***** -Xsram[1869] sram->in sram[1869]->out sram[1869]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1869]->out) 0 -.nodeset V(sram[1869]->outb) vsp -Xmux_1level_tapbuf_size2[218] grid[1][1]_pin[0][1][45] chanx[1][0]_in[84] chany[1][1]_out[16] sram[1870]->outb sram[1870]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[218], level=1, select_path_id=0. ***** -*****1***** -Xsram[1870] sram->in sram[1870]->out sram[1870]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1870]->out) 0 -.nodeset V(sram[1870]->outb) vsp -Xmux_1level_tapbuf_size2[219] grid[1][1]_pin[0][1][45] chanx[1][0]_in[82] chany[1][1]_out[18] sram[1871]->outb sram[1871]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[219], level=1, select_path_id=0. ***** -*****1***** -Xsram[1871] sram->in sram[1871]->out sram[1871]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1871]->out) 0 -.nodeset V(sram[1871]->outb) vsp -Xmux_1level_tapbuf_size2[220] grid[1][1]_pin[0][1][49] chanx[1][0]_in[80] chany[1][1]_out[20] sram[1872]->outb sram[1872]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[220], level=1, select_path_id=0. ***** -*****1***** -Xsram[1872] sram->in sram[1872]->out sram[1872]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1872]->out) 0 -.nodeset V(sram[1872]->outb) vsp -Xmux_1level_tapbuf_size2[221] grid[1][1]_pin[0][1][49] chanx[1][0]_in[78] chany[1][1]_out[22] sram[1873]->outb sram[1873]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[221], level=1, select_path_id=0. ***** -*****1***** -Xsram[1873] sram->in sram[1873]->out sram[1873]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1873]->out) 0 -.nodeset V(sram[1873]->outb) vsp -Xmux_1level_tapbuf_size2[222] grid[1][1]_pin[0][1][49] chanx[1][0]_in[76] chany[1][1]_out[24] sram[1874]->outb sram[1874]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[222], level=1, select_path_id=0. ***** -*****1***** -Xsram[1874] sram->in sram[1874]->out sram[1874]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1874]->out) 0 -.nodeset V(sram[1874]->outb) vsp -Xmux_1level_tapbuf_size2[223] grid[1][1]_pin[0][1][49] chanx[1][0]_in[74] chany[1][1]_out[26] sram[1875]->outb sram[1875]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[223], level=1, select_path_id=0. ***** -*****1***** -Xsram[1875] sram->in sram[1875]->out sram[1875]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1875]->out) 0 -.nodeset V(sram[1875]->outb) vsp -Xmux_1level_tapbuf_size2[224] grid[1][1]_pin[0][1][49] chanx[1][0]_in[72] chany[1][1]_out[28] sram[1876]->outb sram[1876]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[224], level=1, select_path_id=0. ***** -*****1***** -Xsram[1876] sram->in sram[1876]->out sram[1876]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1876]->out) 0 -.nodeset V(sram[1876]->outb) vsp -Xmux_1level_tapbuf_size2[225] grid[2][1]_pin[0][3][1] chanx[1][0]_in[70] chany[1][1]_out[30] sram[1877]->outb sram[1877]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[225], level=1, select_path_id=0. ***** -*****1***** -Xsram[1877] sram->in sram[1877]->out sram[1877]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1877]->out) 0 -.nodeset V(sram[1877]->outb) vsp -Xmux_1level_tapbuf_size2[226] grid[2][1]_pin[0][3][1] chanx[1][0]_in[68] chany[1][1]_out[32] sram[1878]->outb sram[1878]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[226], level=1, select_path_id=0. ***** -*****1***** -Xsram[1878] sram->in sram[1878]->out sram[1878]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1878]->out) 0 -.nodeset V(sram[1878]->outb) vsp -Xmux_1level_tapbuf_size2[227] grid[2][1]_pin[0][3][1] chanx[1][0]_in[66] chany[1][1]_out[34] sram[1879]->outb sram[1879]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[227], level=1, select_path_id=0. ***** -*****1***** -Xsram[1879] sram->in sram[1879]->out sram[1879]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1879]->out) 0 -.nodeset V(sram[1879]->outb) vsp -Xmux_1level_tapbuf_size2[228] grid[2][1]_pin[0][3][1] chanx[1][0]_in[64] chany[1][1]_out[36] sram[1880]->outb sram[1880]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[228], level=1, select_path_id=0. ***** -*****1***** -Xsram[1880] sram->in sram[1880]->out sram[1880]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1880]->out) 0 -.nodeset V(sram[1880]->outb) vsp -Xmux_1level_tapbuf_size2[229] grid[2][1]_pin[0][3][1] chanx[1][0]_in[62] chany[1][1]_out[38] sram[1881]->outb sram[1881]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[229], level=1, select_path_id=0. ***** -*****1***** -Xsram[1881] sram->in sram[1881]->out sram[1881]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1881]->out) 0 -.nodeset V(sram[1881]->outb) vsp -Xmux_1level_tapbuf_size2[230] grid[2][1]_pin[0][3][3] chanx[1][0]_in[60] chany[1][1]_out[40] sram[1882]->outb sram[1882]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[230], level=1, select_path_id=0. ***** -*****1***** -Xsram[1882] sram->in sram[1882]->out sram[1882]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1882]->out) 0 -.nodeset V(sram[1882]->outb) vsp -Xmux_1level_tapbuf_size2[231] grid[2][1]_pin[0][3][3] chanx[1][0]_in[58] chany[1][1]_out[42] sram[1883]->outb sram[1883]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[231], level=1, select_path_id=0. ***** -*****1***** -Xsram[1883] sram->in sram[1883]->out sram[1883]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1883]->out) 0 -.nodeset V(sram[1883]->outb) vsp -Xmux_1level_tapbuf_size2[232] grid[2][1]_pin[0][3][3] chanx[1][0]_in[56] chany[1][1]_out[44] sram[1884]->outb sram[1884]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[232], level=1, select_path_id=0. ***** -*****1***** -Xsram[1884] sram->in sram[1884]->out sram[1884]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1884]->out) 0 -.nodeset V(sram[1884]->outb) vsp -Xmux_1level_tapbuf_size2[233] grid[2][1]_pin[0][3][3] chanx[1][0]_in[54] chany[1][1]_out[46] sram[1885]->outb sram[1885]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[233], level=1, select_path_id=0. ***** -*****1***** -Xsram[1885] sram->in sram[1885]->out sram[1885]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1885]->out) 0 -.nodeset V(sram[1885]->outb) vsp -Xmux_1level_tapbuf_size2[234] grid[2][1]_pin[0][3][3] chanx[1][0]_in[52] chany[1][1]_out[48] sram[1886]->outb sram[1886]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[234], level=1, select_path_id=0. ***** -*****1***** -Xsram[1886] sram->in sram[1886]->out sram[1886]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1886]->out) 0 -.nodeset V(sram[1886]->outb) vsp -Xmux_1level_tapbuf_size2[235] grid[2][1]_pin[0][3][5] chanx[1][0]_in[50] chany[1][1]_out[50] sram[1887]->outb sram[1887]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[235], level=1, select_path_id=0. ***** -*****1***** -Xsram[1887] sram->in sram[1887]->out sram[1887]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1887]->out) 0 -.nodeset V(sram[1887]->outb) vsp -Xmux_1level_tapbuf_size2[236] grid[2][1]_pin[0][3][5] chanx[1][0]_in[48] chany[1][1]_out[52] sram[1888]->outb sram[1888]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[236], level=1, select_path_id=0. ***** -*****1***** -Xsram[1888] sram->in sram[1888]->out sram[1888]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1888]->out) 0 -.nodeset V(sram[1888]->outb) vsp -Xmux_1level_tapbuf_size2[237] grid[2][1]_pin[0][3][5] chanx[1][0]_in[46] chany[1][1]_out[54] sram[1889]->outb sram[1889]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[237], level=1, select_path_id=0. ***** -*****1***** -Xsram[1889] sram->in sram[1889]->out sram[1889]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1889]->out) 0 -.nodeset V(sram[1889]->outb) vsp -Xmux_1level_tapbuf_size2[238] grid[2][1]_pin[0][3][5] chanx[1][0]_in[44] chany[1][1]_out[56] sram[1890]->outb sram[1890]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[238], level=1, select_path_id=0. ***** -*****1***** -Xsram[1890] sram->in sram[1890]->out sram[1890]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1890]->out) 0 -.nodeset V(sram[1890]->outb) vsp -Xmux_1level_tapbuf_size2[239] grid[2][1]_pin[0][3][5] chanx[1][0]_in[42] chany[1][1]_out[58] sram[1891]->outb sram[1891]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[239], level=1, select_path_id=0. ***** -*****1***** -Xsram[1891] sram->in sram[1891]->out sram[1891]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1891]->out) 0 -.nodeset V(sram[1891]->outb) vsp -Xmux_1level_tapbuf_size2[240] grid[2][1]_pin[0][3][7] chanx[1][0]_in[40] chany[1][1]_out[60] sram[1892]->outb sram[1892]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[240], level=1, select_path_id=0. ***** -*****1***** -Xsram[1892] sram->in sram[1892]->out sram[1892]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1892]->out) 0 -.nodeset V(sram[1892]->outb) vsp -Xmux_1level_tapbuf_size2[241] grid[2][1]_pin[0][3][7] chanx[1][0]_in[38] chany[1][1]_out[62] sram[1893]->outb sram[1893]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[241], level=1, select_path_id=0. ***** -*****1***** -Xsram[1893] sram->in sram[1893]->out sram[1893]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1893]->out) 0 -.nodeset V(sram[1893]->outb) vsp -Xmux_1level_tapbuf_size2[242] grid[2][1]_pin[0][3][7] chanx[1][0]_in[36] chany[1][1]_out[64] sram[1894]->outb sram[1894]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[242], level=1, select_path_id=0. ***** -*****1***** -Xsram[1894] sram->in sram[1894]->out sram[1894]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1894]->out) 0 -.nodeset V(sram[1894]->outb) vsp -Xmux_1level_tapbuf_size2[243] grid[2][1]_pin[0][3][7] chanx[1][0]_in[34] chany[1][1]_out[66] sram[1895]->outb sram[1895]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[243], level=1, select_path_id=0. ***** -*****1***** -Xsram[1895] sram->in sram[1895]->out sram[1895]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1895]->out) 0 -.nodeset V(sram[1895]->outb) vsp -Xmux_1level_tapbuf_size2[244] grid[2][1]_pin[0][3][7] chanx[1][0]_in[32] chany[1][1]_out[68] sram[1896]->outb sram[1896]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[244], level=1, select_path_id=0. ***** -*****1***** -Xsram[1896] sram->in sram[1896]->out sram[1896]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1896]->out) 0 -.nodeset V(sram[1896]->outb) vsp -Xmux_1level_tapbuf_size2[245] grid[2][1]_pin[0][3][9] chanx[1][0]_in[30] chany[1][1]_out[70] sram[1897]->outb sram[1897]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[245], level=1, select_path_id=0. ***** -*****1***** -Xsram[1897] sram->in sram[1897]->out sram[1897]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1897]->out) 0 -.nodeset V(sram[1897]->outb) vsp -Xmux_1level_tapbuf_size2[246] grid[2][1]_pin[0][3][9] chanx[1][0]_in[28] chany[1][1]_out[72] sram[1898]->outb sram[1898]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[246], level=1, select_path_id=0. ***** -*****1***** -Xsram[1898] sram->in sram[1898]->out sram[1898]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1898]->out) 0 -.nodeset V(sram[1898]->outb) vsp -Xmux_1level_tapbuf_size2[247] grid[2][1]_pin[0][3][9] chanx[1][0]_in[26] chany[1][1]_out[74] sram[1899]->outb sram[1899]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[247], level=1, select_path_id=0. ***** -*****1***** -Xsram[1899] sram->in sram[1899]->out sram[1899]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1899]->out) 0 -.nodeset V(sram[1899]->outb) vsp -Xmux_1level_tapbuf_size2[248] grid[2][1]_pin[0][3][9] chanx[1][0]_in[24] chany[1][1]_out[76] sram[1900]->outb sram[1900]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[248], level=1, select_path_id=0. ***** -*****1***** -Xsram[1900] sram->in sram[1900]->out sram[1900]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1900]->out) 0 -.nodeset V(sram[1900]->outb) vsp -Xmux_1level_tapbuf_size2[249] grid[2][1]_pin[0][3][9] chanx[1][0]_in[22] chany[1][1]_out[78] sram[1901]->outb sram[1901]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[249], level=1, select_path_id=0. ***** -*****1***** -Xsram[1901] sram->in sram[1901]->out sram[1901]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1901]->out) 0 -.nodeset V(sram[1901]->outb) vsp -Xmux_1level_tapbuf_size2[250] grid[2][1]_pin[0][3][11] chanx[1][0]_in[20] chany[1][1]_out[80] sram[1902]->outb sram[1902]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[250], level=1, select_path_id=0. ***** -*****1***** -Xsram[1902] sram->in sram[1902]->out sram[1902]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1902]->out) 0 -.nodeset V(sram[1902]->outb) vsp -Xmux_1level_tapbuf_size2[251] grid[2][1]_pin[0][3][11] chanx[1][0]_in[18] chany[1][1]_out[82] sram[1903]->outb sram[1903]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[251], level=1, select_path_id=0. ***** -*****1***** -Xsram[1903] sram->in sram[1903]->out sram[1903]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1903]->out) 0 -.nodeset V(sram[1903]->outb) vsp -Xmux_1level_tapbuf_size2[252] grid[2][1]_pin[0][3][11] chanx[1][0]_in[16] chany[1][1]_out[84] sram[1904]->outb sram[1904]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[252], level=1, select_path_id=0. ***** -*****1***** -Xsram[1904] sram->in sram[1904]->out sram[1904]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1904]->out) 0 -.nodeset V(sram[1904]->outb) vsp -Xmux_1level_tapbuf_size2[253] grid[2][1]_pin[0][3][11] chanx[1][0]_in[14] chany[1][1]_out[86] sram[1905]->outb sram[1905]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[253], level=1, select_path_id=0. ***** -*****1***** -Xsram[1905] sram->in sram[1905]->out sram[1905]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1905]->out) 0 -.nodeset V(sram[1905]->outb) vsp -Xmux_1level_tapbuf_size2[254] grid[2][1]_pin[0][3][11] chanx[1][0]_in[12] chany[1][1]_out[88] sram[1906]->outb sram[1906]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[254], level=1, select_path_id=0. ***** -*****1***** -Xsram[1906] sram->in sram[1906]->out sram[1906]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1906]->out) 0 -.nodeset V(sram[1906]->outb) vsp -Xmux_1level_tapbuf_size2[255] grid[2][1]_pin[0][3][13] chanx[1][0]_in[10] chany[1][1]_out[90] sram[1907]->outb sram[1907]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[255], level=1, select_path_id=0. ***** -*****1***** -Xsram[1907] sram->in sram[1907]->out sram[1907]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1907]->out) 0 -.nodeset V(sram[1907]->outb) vsp -Xmux_1level_tapbuf_size2[256] grid[2][1]_pin[0][3][13] chanx[1][0]_in[8] chany[1][1]_out[92] sram[1908]->outb sram[1908]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[256], level=1, select_path_id=0. ***** -*****1***** -Xsram[1908] sram->in sram[1908]->out sram[1908]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1908]->out) 0 -.nodeset V(sram[1908]->outb) vsp -Xmux_1level_tapbuf_size2[257] grid[2][1]_pin[0][3][13] chanx[1][0]_in[6] chany[1][1]_out[94] sram[1909]->outb sram[1909]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[257], level=1, select_path_id=0. ***** -*****1***** -Xsram[1909] sram->in sram[1909]->out sram[1909]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1909]->out) 0 -.nodeset V(sram[1909]->outb) vsp -Xmux_1level_tapbuf_size2[258] grid[2][1]_pin[0][3][13] chanx[1][0]_in[4] chany[1][1]_out[96] sram[1910]->outb sram[1910]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[258], level=1, select_path_id=0. ***** -*****1***** -Xsram[1910] sram->in sram[1910]->out sram[1910]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1910]->out) 0 -.nodeset V(sram[1910]->outb) vsp -Xmux_1level_tapbuf_size2[259] grid[2][1]_pin[0][3][13] chanx[1][0]_in[2] chany[1][1]_out[98] sram[1911]->outb sram[1911]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[259], level=1, select_path_id=0. ***** -*****1***** -Xsram[1911] sram->in sram[1911]->out sram[1911]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1911]->out) 0 -.nodeset V(sram[1911]->outb) vsp -***** right side Multiplexers ***** -***** bottom side Multiplexers ***** -***** left side Multiplexers ***** -Xmux_1level_tapbuf_size2[260] grid[1][0]_pin[0][0][1] chany[1][1]_in[1] chanx[1][0]_out[1] sram[1912]->outb sram[1912]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[260], level=1, select_path_id=0. ***** -*****1***** -Xsram[1912] sram->in sram[1912]->out sram[1912]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1912]->out) 0 -.nodeset V(sram[1912]->outb) vsp -Xmux_1level_tapbuf_size2[261] grid[1][0]_pin[0][0][1] chany[1][1]_in[99] chanx[1][0]_out[3] sram[1913]->outb sram[1913]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[261], level=1, select_path_id=0. ***** -*****1***** -Xsram[1913] sram->in sram[1913]->out sram[1913]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1913]->out) 0 -.nodeset V(sram[1913]->outb) vsp -Xmux_1level_tapbuf_size2[262] grid[1][0]_pin[0][0][1] chany[1][1]_in[97] chanx[1][0]_out[5] sram[1914]->outb sram[1914]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[262], level=1, select_path_id=0. ***** -*****1***** -Xsram[1914] sram->in sram[1914]->out sram[1914]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1914]->out) 0 -.nodeset V(sram[1914]->outb) vsp -Xmux_1level_tapbuf_size2[263] grid[1][0]_pin[0][0][1] chany[1][1]_in[95] chanx[1][0]_out[7] sram[1915]->outb sram[1915]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[263], level=1, select_path_id=0. ***** -*****1***** -Xsram[1915] sram->in sram[1915]->out sram[1915]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1915]->out) 0 -.nodeset V(sram[1915]->outb) vsp -Xmux_1level_tapbuf_size2[264] grid[1][0]_pin[0][0][1] chany[1][1]_in[93] chanx[1][0]_out[9] sram[1916]->outb sram[1916]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[264], level=1, select_path_id=0. ***** -*****1***** -Xsram[1916] sram->in sram[1916]->out sram[1916]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1916]->out) 0 -.nodeset V(sram[1916]->outb) vsp -Xmux_1level_tapbuf_size2[265] grid[1][0]_pin[0][0][3] chany[1][1]_in[91] chanx[1][0]_out[11] sram[1917]->outb sram[1917]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[265], level=1, select_path_id=0. ***** -*****1***** -Xsram[1917] sram->in sram[1917]->out sram[1917]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1917]->out) 0 -.nodeset V(sram[1917]->outb) vsp -Xmux_1level_tapbuf_size2[266] grid[1][0]_pin[0][0][3] chany[1][1]_in[89] chanx[1][0]_out[13] sram[1918]->outb sram[1918]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[266], level=1, select_path_id=0. ***** -*****1***** -Xsram[1918] sram->in sram[1918]->out sram[1918]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1918]->out) 0 -.nodeset V(sram[1918]->outb) vsp -Xmux_1level_tapbuf_size2[267] grid[1][0]_pin[0][0][3] chany[1][1]_in[87] chanx[1][0]_out[15] sram[1919]->outb sram[1919]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[267], level=1, select_path_id=0. ***** -*****1***** -Xsram[1919] sram->in sram[1919]->out sram[1919]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1919]->out) 0 -.nodeset V(sram[1919]->outb) vsp -Xmux_1level_tapbuf_size2[268] grid[1][0]_pin[0][0][3] chany[1][1]_in[85] chanx[1][0]_out[17] sram[1920]->outb sram[1920]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[268], level=1, select_path_id=0. ***** -*****1***** -Xsram[1920] sram->in sram[1920]->out sram[1920]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1920]->out) 0 -.nodeset V(sram[1920]->outb) vsp -Xmux_1level_tapbuf_size2[269] grid[1][0]_pin[0][0][3] chany[1][1]_in[83] chanx[1][0]_out[19] sram[1921]->outb sram[1921]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[269], level=1, select_path_id=0. ***** -*****1***** -Xsram[1921] sram->in sram[1921]->out sram[1921]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1921]->out) 0 -.nodeset V(sram[1921]->outb) vsp -Xmux_1level_tapbuf_size2[270] grid[1][0]_pin[0][0][5] chany[1][1]_in[81] chanx[1][0]_out[21] sram[1922]->outb sram[1922]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[270], level=1, select_path_id=0. ***** -*****1***** -Xsram[1922] sram->in sram[1922]->out sram[1922]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1922]->out) 0 -.nodeset V(sram[1922]->outb) vsp -Xmux_1level_tapbuf_size2[271] grid[1][0]_pin[0][0][5] chany[1][1]_in[79] chanx[1][0]_out[23] sram[1923]->outb sram[1923]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[271], level=1, select_path_id=0. ***** -*****1***** -Xsram[1923] sram->in sram[1923]->out sram[1923]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1923]->out) 0 -.nodeset V(sram[1923]->outb) vsp -Xmux_1level_tapbuf_size2[272] grid[1][0]_pin[0][0][5] chany[1][1]_in[77] chanx[1][0]_out[25] sram[1924]->outb sram[1924]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[272], level=1, select_path_id=0. ***** -*****1***** -Xsram[1924] sram->in sram[1924]->out sram[1924]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1924]->out) 0 -.nodeset V(sram[1924]->outb) vsp -Xmux_1level_tapbuf_size2[273] grid[1][0]_pin[0][0][5] chany[1][1]_in[75] chanx[1][0]_out[27] sram[1925]->outb sram[1925]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[273], level=1, select_path_id=0. ***** -*****1***** -Xsram[1925] sram->in sram[1925]->out sram[1925]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1925]->out) 0 -.nodeset V(sram[1925]->outb) vsp -Xmux_1level_tapbuf_size2[274] grid[1][0]_pin[0][0][5] chany[1][1]_in[73] chanx[1][0]_out[29] sram[1926]->outb sram[1926]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[274], level=1, select_path_id=0. ***** -*****1***** -Xsram[1926] sram->in sram[1926]->out sram[1926]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1926]->out) 0 -.nodeset V(sram[1926]->outb) vsp -Xmux_1level_tapbuf_size2[275] grid[1][0]_pin[0][0][7] chany[1][1]_in[71] chanx[1][0]_out[31] sram[1927]->outb sram[1927]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[275], level=1, select_path_id=0. ***** -*****1***** -Xsram[1927] sram->in sram[1927]->out sram[1927]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1927]->out) 0 -.nodeset V(sram[1927]->outb) vsp -Xmux_1level_tapbuf_size2[276] grid[1][0]_pin[0][0][7] chany[1][1]_in[69] chanx[1][0]_out[33] sram[1928]->outb sram[1928]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[276], level=1, select_path_id=0. ***** -*****1***** -Xsram[1928] sram->in sram[1928]->out sram[1928]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1928]->out) 0 -.nodeset V(sram[1928]->outb) vsp -Xmux_1level_tapbuf_size2[277] grid[1][0]_pin[0][0][7] chany[1][1]_in[67] chanx[1][0]_out[35] sram[1929]->outb sram[1929]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[277], level=1, select_path_id=0. ***** -*****1***** -Xsram[1929] sram->in sram[1929]->out sram[1929]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1929]->out) 0 -.nodeset V(sram[1929]->outb) vsp -Xmux_1level_tapbuf_size2[278] grid[1][0]_pin[0][0][7] chany[1][1]_in[65] chanx[1][0]_out[37] sram[1930]->outb sram[1930]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[278], level=1, select_path_id=0. ***** -*****1***** -Xsram[1930] sram->in sram[1930]->out sram[1930]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1930]->out) 0 -.nodeset V(sram[1930]->outb) vsp -Xmux_1level_tapbuf_size2[279] grid[1][0]_pin[0][0][7] chany[1][1]_in[63] chanx[1][0]_out[39] sram[1931]->outb sram[1931]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[279], level=1, select_path_id=0. ***** -*****1***** -Xsram[1931] sram->in sram[1931]->out sram[1931]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1931]->out) 0 -.nodeset V(sram[1931]->outb) vsp -Xmux_1level_tapbuf_size2[280] grid[1][0]_pin[0][0][9] chany[1][1]_in[61] chanx[1][0]_out[41] sram[1932]->outb sram[1932]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[280], level=1, select_path_id=0. ***** -*****1***** -Xsram[1932] sram->in sram[1932]->out sram[1932]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1932]->out) 0 -.nodeset V(sram[1932]->outb) vsp -Xmux_1level_tapbuf_size2[281] grid[1][0]_pin[0][0][9] chany[1][1]_in[59] chanx[1][0]_out[43] sram[1933]->outb sram[1933]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[281], level=1, select_path_id=0. ***** -*****1***** -Xsram[1933] sram->in sram[1933]->out sram[1933]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1933]->out) 0 -.nodeset V(sram[1933]->outb) vsp -Xmux_1level_tapbuf_size2[282] grid[1][0]_pin[0][0][9] chany[1][1]_in[57] chanx[1][0]_out[45] sram[1934]->outb sram[1934]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[282], level=1, select_path_id=0. ***** -*****1***** -Xsram[1934] sram->in sram[1934]->out sram[1934]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1934]->out) 0 -.nodeset V(sram[1934]->outb) vsp -Xmux_1level_tapbuf_size2[283] grid[1][0]_pin[0][0][9] chany[1][1]_in[55] chanx[1][0]_out[47] sram[1935]->outb sram[1935]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[283], level=1, select_path_id=0. ***** -*****1***** -Xsram[1935] sram->in sram[1935]->out sram[1935]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1935]->out) 0 -.nodeset V(sram[1935]->outb) vsp -Xmux_1level_tapbuf_size2[284] grid[1][0]_pin[0][0][9] chany[1][1]_in[53] chanx[1][0]_out[49] sram[1936]->outb sram[1936]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[284], level=1, select_path_id=0. ***** -*****1***** -Xsram[1936] sram->in sram[1936]->out sram[1936]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1936]->out) 0 -.nodeset V(sram[1936]->outb) vsp -Xmux_1level_tapbuf_size2[285] grid[1][0]_pin[0][0][11] chany[1][1]_in[51] chanx[1][0]_out[51] sram[1937]->outb sram[1937]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[285], level=1, select_path_id=0. ***** -*****1***** -Xsram[1937] sram->in sram[1937]->out sram[1937]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1937]->out) 0 -.nodeset V(sram[1937]->outb) vsp -Xmux_1level_tapbuf_size2[286] grid[1][0]_pin[0][0][11] chany[1][1]_in[49] chanx[1][0]_out[53] sram[1938]->outb sram[1938]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[286], level=1, select_path_id=0. ***** -*****1***** -Xsram[1938] sram->in sram[1938]->out sram[1938]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1938]->out) 0 -.nodeset V(sram[1938]->outb) vsp -Xmux_1level_tapbuf_size2[287] grid[1][0]_pin[0][0][11] chany[1][1]_in[47] chanx[1][0]_out[55] sram[1939]->outb sram[1939]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[287], level=1, select_path_id=0. ***** -*****1***** -Xsram[1939] sram->in sram[1939]->out sram[1939]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1939]->out) 0 -.nodeset V(sram[1939]->outb) vsp -Xmux_1level_tapbuf_size2[288] grid[1][0]_pin[0][0][11] chany[1][1]_in[45] chanx[1][0]_out[57] sram[1940]->outb sram[1940]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[288], level=1, select_path_id=0. ***** -*****1***** -Xsram[1940] sram->in sram[1940]->out sram[1940]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1940]->out) 0 -.nodeset V(sram[1940]->outb) vsp -Xmux_1level_tapbuf_size2[289] grid[1][0]_pin[0][0][11] chany[1][1]_in[43] chanx[1][0]_out[59] sram[1941]->outb sram[1941]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[289], level=1, select_path_id=0. ***** -*****1***** -Xsram[1941] sram->in sram[1941]->out sram[1941]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1941]->out) 0 -.nodeset V(sram[1941]->outb) vsp -Xmux_1level_tapbuf_size2[290] grid[1][0]_pin[0][0][13] chany[1][1]_in[41] chanx[1][0]_out[61] sram[1942]->outb sram[1942]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[290], level=1, select_path_id=0. ***** -*****1***** -Xsram[1942] sram->in sram[1942]->out sram[1942]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1942]->out) 0 -.nodeset V(sram[1942]->outb) vsp -Xmux_1level_tapbuf_size2[291] grid[1][0]_pin[0][0][13] chany[1][1]_in[39] chanx[1][0]_out[63] sram[1943]->outb sram[1943]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[291], level=1, select_path_id=0. ***** -*****1***** -Xsram[1943] sram->in sram[1943]->out sram[1943]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1943]->out) 0 -.nodeset V(sram[1943]->outb) vsp -Xmux_1level_tapbuf_size2[292] grid[1][0]_pin[0][0][13] chany[1][1]_in[37] chanx[1][0]_out[65] sram[1944]->outb sram[1944]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[292], level=1, select_path_id=0. ***** -*****1***** -Xsram[1944] sram->in sram[1944]->out sram[1944]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1944]->out) 0 -.nodeset V(sram[1944]->outb) vsp -Xmux_1level_tapbuf_size2[293] grid[1][0]_pin[0][0][13] chany[1][1]_in[35] chanx[1][0]_out[67] sram[1945]->outb sram[1945]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[293], level=1, select_path_id=0. ***** -*****1***** -Xsram[1945] sram->in sram[1945]->out sram[1945]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1945]->out) 0 -.nodeset V(sram[1945]->outb) vsp -Xmux_1level_tapbuf_size2[294] grid[1][0]_pin[0][0][13] chany[1][1]_in[33] chanx[1][0]_out[69] sram[1946]->outb sram[1946]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[294], level=1, select_path_id=0. ***** -*****1***** -Xsram[1946] sram->in sram[1946]->out sram[1946]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1946]->out) 0 -.nodeset V(sram[1946]->outb) vsp -Xmux_1level_tapbuf_size2[295] grid[1][0]_pin[0][0][15] chany[1][1]_in[31] chanx[1][0]_out[71] sram[1947]->outb sram[1947]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[295], level=1, select_path_id=0. ***** -*****1***** -Xsram[1947] sram->in sram[1947]->out sram[1947]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1947]->out) 0 -.nodeset V(sram[1947]->outb) vsp -Xmux_1level_tapbuf_size2[296] grid[1][0]_pin[0][0][15] chany[1][1]_in[29] chanx[1][0]_out[73] sram[1948]->outb sram[1948]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[296], level=1, select_path_id=0. ***** -*****1***** -Xsram[1948] sram->in sram[1948]->out sram[1948]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1948]->out) 0 -.nodeset V(sram[1948]->outb) vsp -Xmux_1level_tapbuf_size2[297] grid[1][0]_pin[0][0][15] chany[1][1]_in[27] chanx[1][0]_out[75] sram[1949]->outb sram[1949]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[297], level=1, select_path_id=0. ***** -*****1***** -Xsram[1949] sram->in sram[1949]->out sram[1949]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1949]->out) 0 -.nodeset V(sram[1949]->outb) vsp -Xmux_1level_tapbuf_size2[298] grid[1][0]_pin[0][0][15] chany[1][1]_in[25] chanx[1][0]_out[77] sram[1950]->outb sram[1950]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[298], level=1, select_path_id=0. ***** -*****1***** -Xsram[1950] sram->in sram[1950]->out sram[1950]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1950]->out) 0 -.nodeset V(sram[1950]->outb) vsp -Xmux_1level_tapbuf_size2[299] grid[1][0]_pin[0][0][15] chany[1][1]_in[23] chanx[1][0]_out[79] sram[1951]->out sram[1951]->outb svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[299], level=1, select_path_id=1. ***** -*****0***** -Xsram[1951] sram->in sram[1951]->out sram[1951]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1951]->out) 0 -.nodeset V(sram[1951]->outb) vsp -Xmux_1level_tapbuf_size2[300] grid[1][1]_pin[0][2][42] chany[1][1]_in[21] chanx[1][0]_out[81] sram[1952]->outb sram[1952]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[300], level=1, select_path_id=0. ***** -*****1***** -Xsram[1952] sram->in sram[1952]->out sram[1952]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1952]->out) 0 -.nodeset V(sram[1952]->outb) vsp -Xmux_1level_tapbuf_size2[301] grid[1][1]_pin[0][2][42] chany[1][1]_in[19] chanx[1][0]_out[83] sram[1953]->outb sram[1953]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[301], level=1, select_path_id=0. ***** -*****1***** -Xsram[1953] sram->in sram[1953]->out sram[1953]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1953]->out) 0 -.nodeset V(sram[1953]->outb) vsp -Xmux_1level_tapbuf_size2[302] grid[1][1]_pin[0][2][42] chany[1][1]_in[17] chanx[1][0]_out[85] sram[1954]->outb sram[1954]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[302], level=1, select_path_id=0. ***** -*****1***** -Xsram[1954] sram->in sram[1954]->out sram[1954]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1954]->out) 0 -.nodeset V(sram[1954]->outb) vsp -Xmux_1level_tapbuf_size2[303] grid[1][1]_pin[0][2][42] chany[1][1]_in[15] chanx[1][0]_out[87] sram[1955]->outb sram[1955]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[303], level=1, select_path_id=0. ***** -*****1***** -Xsram[1955] sram->in sram[1955]->out sram[1955]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1955]->out) 0 -.nodeset V(sram[1955]->outb) vsp -Xmux_1level_tapbuf_size2[304] grid[1][1]_pin[0][2][42] chany[1][1]_in[13] chanx[1][0]_out[89] sram[1956]->outb sram[1956]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[304], level=1, select_path_id=0. ***** -*****1***** -Xsram[1956] sram->in sram[1956]->out sram[1956]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1956]->out) 0 -.nodeset V(sram[1956]->outb) vsp -Xmux_1level_tapbuf_size2[305] grid[1][1]_pin[0][2][46] chany[1][1]_in[11] chanx[1][0]_out[91] sram[1957]->outb sram[1957]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[305], level=1, select_path_id=0. ***** -*****1***** -Xsram[1957] sram->in sram[1957]->out sram[1957]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1957]->out) 0 -.nodeset V(sram[1957]->outb) vsp -Xmux_1level_tapbuf_size2[306] grid[1][1]_pin[0][2][46] chany[1][1]_in[9] chanx[1][0]_out[93] sram[1958]->outb sram[1958]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[306], level=1, select_path_id=0. ***** -*****1***** -Xsram[1958] sram->in sram[1958]->out sram[1958]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1958]->out) 0 -.nodeset V(sram[1958]->outb) vsp -Xmux_1level_tapbuf_size2[307] grid[1][1]_pin[0][2][46] chany[1][1]_in[7] chanx[1][0]_out[95] sram[1959]->outb sram[1959]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[307], level=1, select_path_id=0. ***** -*****1***** -Xsram[1959] sram->in sram[1959]->out sram[1959]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1959]->out) 0 -.nodeset V(sram[1959]->outb) vsp -Xmux_1level_tapbuf_size2[308] grid[1][1]_pin[0][2][46] chany[1][1]_in[5] chanx[1][0]_out[97] sram[1960]->outb sram[1960]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[308], level=1, select_path_id=0. ***** -*****1***** -Xsram[1960] sram->in sram[1960]->out sram[1960]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1960]->out) 0 -.nodeset V(sram[1960]->outb) vsp -Xmux_1level_tapbuf_size2[309] grid[1][1]_pin[0][2][46] chany[1][1]_in[3] chanx[1][0]_out[99] sram[1961]->outb sram[1961]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[309], level=1, select_path_id=0. ***** -*****1***** -Xsram[1961] sram->in sram[1961]->out sram[1961]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1961]->out) 0 -.nodeset V(sram[1961]->outb) vsp -.eom diff --git a/examples/spice_test_example_2/subckt/sb_1_1.sp b/examples/spice_test_example_2/subckt/sb_1_1.sp deleted file mode 100644 index 7ad7a1f95..000000000 --- a/examples/spice_test_example_2/subckt/sb_1_1.sp +++ /dev/null @@ -1,688 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Switch Block [1][1] in FPGA * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -***** Switch Box[1][1] Sub-Circuit ***** -.subckt sb[1][1] -***** Inputs/outputs of top side ***** -+ -+ -+ ***** Inputs/outputs of right side ***** -+ -+ -+ ***** Inputs/outputs of bottom side ***** -+ chany[1][1]_in[0] chany[1][1]_out[1] chany[1][1]_in[2] chany[1][1]_out[3] chany[1][1]_in[4] chany[1][1]_out[5] chany[1][1]_in[6] chany[1][1]_out[7] chany[1][1]_in[8] chany[1][1]_out[9] chany[1][1]_in[10] chany[1][1]_out[11] chany[1][1]_in[12] chany[1][1]_out[13] chany[1][1]_in[14] chany[1][1]_out[15] chany[1][1]_in[16] chany[1][1]_out[17] chany[1][1]_in[18] chany[1][1]_out[19] chany[1][1]_in[20] chany[1][1]_out[21] chany[1][1]_in[22] chany[1][1]_out[23] chany[1][1]_in[24] chany[1][1]_out[25] chany[1][1]_in[26] chany[1][1]_out[27] chany[1][1]_in[28] chany[1][1]_out[29] chany[1][1]_in[30] chany[1][1]_out[31] chany[1][1]_in[32] chany[1][1]_out[33] chany[1][1]_in[34] chany[1][1]_out[35] chany[1][1]_in[36] chany[1][1]_out[37] chany[1][1]_in[38] chany[1][1]_out[39] chany[1][1]_in[40] chany[1][1]_out[41] chany[1][1]_in[42] chany[1][1]_out[43] chany[1][1]_in[44] chany[1][1]_out[45] chany[1][1]_in[46] chany[1][1]_out[47] chany[1][1]_in[48] chany[1][1]_out[49] chany[1][1]_in[50] chany[1][1]_out[51] chany[1][1]_in[52] chany[1][1]_out[53] chany[1][1]_in[54] chany[1][1]_out[55] chany[1][1]_in[56] chany[1][1]_out[57] chany[1][1]_in[58] chany[1][1]_out[59] chany[1][1]_in[60] chany[1][1]_out[61] chany[1][1]_in[62] chany[1][1]_out[63] chany[1][1]_in[64] chany[1][1]_out[65] chany[1][1]_in[66] chany[1][1]_out[67] chany[1][1]_in[68] chany[1][1]_out[69] chany[1][1]_in[70] chany[1][1]_out[71] chany[1][1]_in[72] chany[1][1]_out[73] chany[1][1]_in[74] chany[1][1]_out[75] chany[1][1]_in[76] chany[1][1]_out[77] chany[1][1]_in[78] chany[1][1]_out[79] chany[1][1]_in[80] chany[1][1]_out[81] chany[1][1]_in[82] chany[1][1]_out[83] chany[1][1]_in[84] chany[1][1]_out[85] chany[1][1]_in[86] chany[1][1]_out[87] chany[1][1]_in[88] chany[1][1]_out[89] chany[1][1]_in[90] chany[1][1]_out[91] chany[1][1]_in[92] chany[1][1]_out[93] chany[1][1]_in[94] chany[1][1]_out[95] chany[1][1]_in[96] chany[1][1]_out[97] chany[1][1]_in[98] chany[1][1]_out[99] -+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][49] -+ ***** Inputs/outputs of left side ***** -+ chanx[1][1]_in[0] chanx[1][1]_out[1] chanx[1][1]_in[2] chanx[1][1]_out[3] chanx[1][1]_in[4] chanx[1][1]_out[5] chanx[1][1]_in[6] chanx[1][1]_out[7] chanx[1][1]_in[8] chanx[1][1]_out[9] chanx[1][1]_in[10] chanx[1][1]_out[11] chanx[1][1]_in[12] chanx[1][1]_out[13] chanx[1][1]_in[14] chanx[1][1]_out[15] chanx[1][1]_in[16] chanx[1][1]_out[17] chanx[1][1]_in[18] chanx[1][1]_out[19] chanx[1][1]_in[20] chanx[1][1]_out[21] chanx[1][1]_in[22] chanx[1][1]_out[23] chanx[1][1]_in[24] chanx[1][1]_out[25] chanx[1][1]_in[26] chanx[1][1]_out[27] chanx[1][1]_in[28] chanx[1][1]_out[29] chanx[1][1]_in[30] chanx[1][1]_out[31] chanx[1][1]_in[32] chanx[1][1]_out[33] chanx[1][1]_in[34] chanx[1][1]_out[35] chanx[1][1]_in[36] chanx[1][1]_out[37] chanx[1][1]_in[38] chanx[1][1]_out[39] chanx[1][1]_in[40] chanx[1][1]_out[41] chanx[1][1]_in[42] chanx[1][1]_out[43] chanx[1][1]_in[44] chanx[1][1]_out[45] chanx[1][1]_in[46] chanx[1][1]_out[47] chanx[1][1]_in[48] chanx[1][1]_out[49] chanx[1][1]_in[50] chanx[1][1]_out[51] chanx[1][1]_in[52] chanx[1][1]_out[53] chanx[1][1]_in[54] chanx[1][1]_out[55] chanx[1][1]_in[56] chanx[1][1]_out[57] chanx[1][1]_in[58] chanx[1][1]_out[59] chanx[1][1]_in[60] chanx[1][1]_out[61] chanx[1][1]_in[62] chanx[1][1]_out[63] chanx[1][1]_in[64] chanx[1][1]_out[65] chanx[1][1]_in[66] chanx[1][1]_out[67] chanx[1][1]_in[68] chanx[1][1]_out[69] chanx[1][1]_in[70] chanx[1][1]_out[71] chanx[1][1]_in[72] chanx[1][1]_out[73] chanx[1][1]_in[74] chanx[1][1]_out[75] chanx[1][1]_in[76] chanx[1][1]_out[77] chanx[1][1]_in[78] chanx[1][1]_out[79] chanx[1][1]_in[80] chanx[1][1]_out[81] chanx[1][1]_in[82] chanx[1][1]_out[83] chanx[1][1]_in[84] chanx[1][1]_out[85] chanx[1][1]_in[86] chanx[1][1]_out[87] chanx[1][1]_in[88] chanx[1][1]_out[89] chanx[1][1]_in[90] chanx[1][1]_out[91] chanx[1][1]_in[92] chanx[1][1]_out[93] chanx[1][1]_in[94] chanx[1][1]_out[95] chanx[1][1]_in[96] chanx[1][1]_out[97] chanx[1][1]_in[98] chanx[1][1]_out[99] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][48] -+ svdd sgnd -***** top side Multiplexers ***** -***** right side Multiplexers ***** -***** bottom side Multiplexers ***** -Xmux_1level_tapbuf_size3[310] grid[1][1]_pin[0][1][41] grid[2][1]_pin[0][3][15] chanx[1][1]_in[2] chany[1][1]_out[1] sram[1962]->outb sram[1962]->out sram[1963]->out sram[1963]->outb sram[1964]->out sram[1964]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[310], level=1, select_path_id=0. ***** -*****100***** -Xsram[1962] sram->in sram[1962]->out sram[1962]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1962]->out) 0 -.nodeset V(sram[1962]->outb) vsp -Xsram[1963] sram->in sram[1963]->out sram[1963]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1963]->out) 0 -.nodeset V(sram[1963]->outb) vsp -Xsram[1964] sram->in sram[1964]->out sram[1964]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1964]->out) 0 -.nodeset V(sram[1964]->outb) vsp -Xmux_1level_tapbuf_size3[311] grid[1][1]_pin[0][1][41] grid[2][1]_pin[0][3][15] chanx[1][1]_in[4] chany[1][1]_out[3] sram[1965]->outb sram[1965]->out sram[1966]->out sram[1966]->outb sram[1967]->out sram[1967]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[311], level=1, select_path_id=0. ***** -*****100***** -Xsram[1965] sram->in sram[1965]->out sram[1965]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1965]->out) 0 -.nodeset V(sram[1965]->outb) vsp -Xsram[1966] sram->in sram[1966]->out sram[1966]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1966]->out) 0 -.nodeset V(sram[1966]->outb) vsp -Xsram[1967] sram->in sram[1967]->out sram[1967]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1967]->out) 0 -.nodeset V(sram[1967]->outb) vsp -Xmux_1level_tapbuf_size3[312] grid[1][1]_pin[0][1][41] grid[2][1]_pin[0][3][15] chanx[1][1]_in[6] chany[1][1]_out[5] sram[1968]->outb sram[1968]->out sram[1969]->out sram[1969]->outb sram[1970]->out sram[1970]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[312], level=1, select_path_id=0. ***** -*****100***** -Xsram[1968] sram->in sram[1968]->out sram[1968]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1968]->out) 0 -.nodeset V(sram[1968]->outb) vsp -Xsram[1969] sram->in sram[1969]->out sram[1969]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1969]->out) 0 -.nodeset V(sram[1969]->outb) vsp -Xsram[1970] sram->in sram[1970]->out sram[1970]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1970]->out) 0 -.nodeset V(sram[1970]->outb) vsp -Xmux_1level_tapbuf_size3[313] grid[1][1]_pin[0][1][41] grid[2][1]_pin[0][3][15] chanx[1][1]_in[8] chany[1][1]_out[7] sram[1971]->outb sram[1971]->out sram[1972]->out sram[1972]->outb sram[1973]->out sram[1973]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[313], level=1, select_path_id=0. ***** -*****100***** -Xsram[1971] sram->in sram[1971]->out sram[1971]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1971]->out) 0 -.nodeset V(sram[1971]->outb) vsp -Xsram[1972] sram->in sram[1972]->out sram[1972]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1972]->out) 0 -.nodeset V(sram[1972]->outb) vsp -Xsram[1973] sram->in sram[1973]->out sram[1973]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1973]->out) 0 -.nodeset V(sram[1973]->outb) vsp -Xmux_1level_tapbuf_size3[314] grid[1][1]_pin[0][1][41] grid[2][1]_pin[0][3][15] chanx[1][1]_in[10] chany[1][1]_out[9] sram[1974]->outb sram[1974]->out sram[1975]->out sram[1975]->outb sram[1976]->out sram[1976]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[314], level=1, select_path_id=0. ***** -*****100***** -Xsram[1974] sram->in sram[1974]->out sram[1974]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1974]->out) 0 -.nodeset V(sram[1974]->outb) vsp -Xsram[1975] sram->in sram[1975]->out sram[1975]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1975]->out) 0 -.nodeset V(sram[1975]->outb) vsp -Xsram[1976] sram->in sram[1976]->out sram[1976]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1976]->out) 0 -.nodeset V(sram[1976]->outb) vsp -Xmux_1level_tapbuf_size2[315] grid[1][1]_pin[0][1][45] chanx[1][1]_in[12] chany[1][1]_out[11] sram[1977]->outb sram[1977]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[315], level=1, select_path_id=0. ***** -*****1***** -Xsram[1977] sram->in sram[1977]->out sram[1977]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1977]->out) 0 -.nodeset V(sram[1977]->outb) vsp -Xmux_1level_tapbuf_size2[316] grid[1][1]_pin[0][1][45] chanx[1][1]_in[14] chany[1][1]_out[13] sram[1978]->outb sram[1978]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[316], level=1, select_path_id=0. ***** -*****1***** -Xsram[1978] sram->in sram[1978]->out sram[1978]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1978]->out) 0 -.nodeset V(sram[1978]->outb) vsp -Xmux_1level_tapbuf_size2[317] grid[1][1]_pin[0][1][45] chanx[1][1]_in[16] chany[1][1]_out[15] sram[1979]->outb sram[1979]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[317], level=1, select_path_id=0. ***** -*****1***** -Xsram[1979] sram->in sram[1979]->out sram[1979]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1979]->out) 0 -.nodeset V(sram[1979]->outb) vsp -Xmux_1level_tapbuf_size2[318] grid[1][1]_pin[0][1][45] chanx[1][1]_in[18] chany[1][1]_out[17] sram[1980]->outb sram[1980]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[318], level=1, select_path_id=0. ***** -*****1***** -Xsram[1980] sram->in sram[1980]->out sram[1980]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1980]->out) 0 -.nodeset V(sram[1980]->outb) vsp -Xmux_1level_tapbuf_size2[319] grid[1][1]_pin[0][1][45] chanx[1][1]_in[20] chany[1][1]_out[19] sram[1981]->outb sram[1981]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[319], level=1, select_path_id=0. ***** -*****1***** -Xsram[1981] sram->in sram[1981]->out sram[1981]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1981]->out) 0 -.nodeset V(sram[1981]->outb) vsp -Xmux_1level_tapbuf_size2[320] grid[1][1]_pin[0][1][49] chanx[1][1]_in[22] chany[1][1]_out[21] sram[1982]->outb sram[1982]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[320], level=1, select_path_id=0. ***** -*****1***** -Xsram[1982] sram->in sram[1982]->out sram[1982]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1982]->out) 0 -.nodeset V(sram[1982]->outb) vsp -Xmux_1level_tapbuf_size2[321] grid[1][1]_pin[0][1][49] chanx[1][1]_in[24] chany[1][1]_out[23] sram[1983]->outb sram[1983]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[321], level=1, select_path_id=0. ***** -*****1***** -Xsram[1983] sram->in sram[1983]->out sram[1983]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1983]->out) 0 -.nodeset V(sram[1983]->outb) vsp -Xmux_1level_tapbuf_size2[322] grid[1][1]_pin[0][1][49] chanx[1][1]_in[26] chany[1][1]_out[25] sram[1984]->outb sram[1984]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[322], level=1, select_path_id=0. ***** -*****1***** -Xsram[1984] sram->in sram[1984]->out sram[1984]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1984]->out) 0 -.nodeset V(sram[1984]->outb) vsp -Xmux_1level_tapbuf_size2[323] grid[1][1]_pin[0][1][49] chanx[1][1]_in[28] chany[1][1]_out[27] sram[1985]->outb sram[1985]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[323], level=1, select_path_id=0. ***** -*****1***** -Xsram[1985] sram->in sram[1985]->out sram[1985]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1985]->out) 0 -.nodeset V(sram[1985]->outb) vsp -Xmux_1level_tapbuf_size2[324] grid[1][1]_pin[0][1][49] chanx[1][1]_in[30] chany[1][1]_out[29] sram[1986]->outb sram[1986]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[324], level=1, select_path_id=0. ***** -*****1***** -Xsram[1986] sram->in sram[1986]->out sram[1986]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1986]->out) 0 -.nodeset V(sram[1986]->outb) vsp -Xmux_1level_tapbuf_size2[325] grid[2][1]_pin[0][3][1] chanx[1][1]_in[32] chany[1][1]_out[31] sram[1987]->outb sram[1987]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[325], level=1, select_path_id=0. ***** -*****1***** -Xsram[1987] sram->in sram[1987]->out sram[1987]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1987]->out) 0 -.nodeset V(sram[1987]->outb) vsp -Xmux_1level_tapbuf_size2[326] grid[2][1]_pin[0][3][1] chanx[1][1]_in[34] chany[1][1]_out[33] sram[1988]->outb sram[1988]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[326], level=1, select_path_id=0. ***** -*****1***** -Xsram[1988] sram->in sram[1988]->out sram[1988]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1988]->out) 0 -.nodeset V(sram[1988]->outb) vsp -Xmux_1level_tapbuf_size2[327] grid[2][1]_pin[0][3][1] chanx[1][1]_in[36] chany[1][1]_out[35] sram[1989]->outb sram[1989]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[327], level=1, select_path_id=0. ***** -*****1***** -Xsram[1989] sram->in sram[1989]->out sram[1989]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1989]->out) 0 -.nodeset V(sram[1989]->outb) vsp -Xmux_1level_tapbuf_size2[328] grid[2][1]_pin[0][3][1] chanx[1][1]_in[38] chany[1][1]_out[37] sram[1990]->outb sram[1990]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[328], level=1, select_path_id=0. ***** -*****1***** -Xsram[1990] sram->in sram[1990]->out sram[1990]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1990]->out) 0 -.nodeset V(sram[1990]->outb) vsp -Xmux_1level_tapbuf_size2[329] grid[2][1]_pin[0][3][1] chanx[1][1]_in[40] chany[1][1]_out[39] sram[1991]->outb sram[1991]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[329], level=1, select_path_id=0. ***** -*****1***** -Xsram[1991] sram->in sram[1991]->out sram[1991]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1991]->out) 0 -.nodeset V(sram[1991]->outb) vsp -Xmux_1level_tapbuf_size2[330] grid[2][1]_pin[0][3][3] chanx[1][1]_in[42] chany[1][1]_out[41] sram[1992]->outb sram[1992]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[330], level=1, select_path_id=0. ***** -*****1***** -Xsram[1992] sram->in sram[1992]->out sram[1992]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1992]->out) 0 -.nodeset V(sram[1992]->outb) vsp -Xmux_1level_tapbuf_size2[331] grid[2][1]_pin[0][3][3] chanx[1][1]_in[44] chany[1][1]_out[43] sram[1993]->outb sram[1993]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[331], level=1, select_path_id=0. ***** -*****1***** -Xsram[1993] sram->in sram[1993]->out sram[1993]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1993]->out) 0 -.nodeset V(sram[1993]->outb) vsp -Xmux_1level_tapbuf_size2[332] grid[2][1]_pin[0][3][3] chanx[1][1]_in[46] chany[1][1]_out[45] sram[1994]->outb sram[1994]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[332], level=1, select_path_id=0. ***** -*****1***** -Xsram[1994] sram->in sram[1994]->out sram[1994]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1994]->out) 0 -.nodeset V(sram[1994]->outb) vsp -Xmux_1level_tapbuf_size2[333] grid[2][1]_pin[0][3][3] chanx[1][1]_in[48] chany[1][1]_out[47] sram[1995]->outb sram[1995]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[333], level=1, select_path_id=0. ***** -*****1***** -Xsram[1995] sram->in sram[1995]->out sram[1995]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1995]->out) 0 -.nodeset V(sram[1995]->outb) vsp -Xmux_1level_tapbuf_size2[334] grid[2][1]_pin[0][3][3] chanx[1][1]_in[50] chany[1][1]_out[49] sram[1996]->outb sram[1996]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[334], level=1, select_path_id=0. ***** -*****1***** -Xsram[1996] sram->in sram[1996]->out sram[1996]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1996]->out) 0 -.nodeset V(sram[1996]->outb) vsp -Xmux_1level_tapbuf_size2[335] grid[2][1]_pin[0][3][5] chanx[1][1]_in[52] chany[1][1]_out[51] sram[1997]->outb sram[1997]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[335], level=1, select_path_id=0. ***** -*****1***** -Xsram[1997] sram->in sram[1997]->out sram[1997]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1997]->out) 0 -.nodeset V(sram[1997]->outb) vsp -Xmux_1level_tapbuf_size2[336] grid[2][1]_pin[0][3][5] chanx[1][1]_in[54] chany[1][1]_out[53] sram[1998]->outb sram[1998]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[336], level=1, select_path_id=0. ***** -*****1***** -Xsram[1998] sram->in sram[1998]->out sram[1998]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1998]->out) 0 -.nodeset V(sram[1998]->outb) vsp -Xmux_1level_tapbuf_size2[337] grid[2][1]_pin[0][3][5] chanx[1][1]_in[56] chany[1][1]_out[55] sram[1999]->outb sram[1999]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[337], level=1, select_path_id=0. ***** -*****1***** -Xsram[1999] sram->in sram[1999]->out sram[1999]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[1999]->out) 0 -.nodeset V(sram[1999]->outb) vsp -Xmux_1level_tapbuf_size2[338] grid[2][1]_pin[0][3][5] chanx[1][1]_in[58] chany[1][1]_out[57] sram[2000]->outb sram[2000]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[338], level=1, select_path_id=0. ***** -*****1***** -Xsram[2000] sram->in sram[2000]->out sram[2000]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2000]->out) 0 -.nodeset V(sram[2000]->outb) vsp -Xmux_1level_tapbuf_size2[339] grid[2][1]_pin[0][3][5] chanx[1][1]_in[60] chany[1][1]_out[59] sram[2001]->outb sram[2001]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[339], level=1, select_path_id=0. ***** -*****1***** -Xsram[2001] sram->in sram[2001]->out sram[2001]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2001]->out) 0 -.nodeset V(sram[2001]->outb) vsp -Xmux_1level_tapbuf_size2[340] grid[2][1]_pin[0][3][7] chanx[1][1]_in[62] chany[1][1]_out[61] sram[2002]->outb sram[2002]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[340], level=1, select_path_id=0. ***** -*****1***** -Xsram[2002] sram->in sram[2002]->out sram[2002]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2002]->out) 0 -.nodeset V(sram[2002]->outb) vsp -Xmux_1level_tapbuf_size2[341] grid[2][1]_pin[0][3][7] chanx[1][1]_in[64] chany[1][1]_out[63] sram[2003]->outb sram[2003]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[341], level=1, select_path_id=0. ***** -*****1***** -Xsram[2003] sram->in sram[2003]->out sram[2003]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2003]->out) 0 -.nodeset V(sram[2003]->outb) vsp -Xmux_1level_tapbuf_size2[342] grid[2][1]_pin[0][3][7] chanx[1][1]_in[66] chany[1][1]_out[65] sram[2004]->outb sram[2004]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[342], level=1, select_path_id=0. ***** -*****1***** -Xsram[2004] sram->in sram[2004]->out sram[2004]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2004]->out) 0 -.nodeset V(sram[2004]->outb) vsp -Xmux_1level_tapbuf_size2[343] grid[2][1]_pin[0][3][7] chanx[1][1]_in[68] chany[1][1]_out[67] sram[2005]->outb sram[2005]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[343], level=1, select_path_id=0. ***** -*****1***** -Xsram[2005] sram->in sram[2005]->out sram[2005]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2005]->out) 0 -.nodeset V(sram[2005]->outb) vsp -Xmux_1level_tapbuf_size2[344] grid[2][1]_pin[0][3][7] chanx[1][1]_in[70] chany[1][1]_out[69] sram[2006]->outb sram[2006]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[344], level=1, select_path_id=0. ***** -*****1***** -Xsram[2006] sram->in sram[2006]->out sram[2006]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2006]->out) 0 -.nodeset V(sram[2006]->outb) vsp -Xmux_1level_tapbuf_size2[345] grid[2][1]_pin[0][3][9] chanx[1][1]_in[72] chany[1][1]_out[71] sram[2007]->outb sram[2007]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[345], level=1, select_path_id=0. ***** -*****1***** -Xsram[2007] sram->in sram[2007]->out sram[2007]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2007]->out) 0 -.nodeset V(sram[2007]->outb) vsp -Xmux_1level_tapbuf_size2[346] grid[2][1]_pin[0][3][9] chanx[1][1]_in[74] chany[1][1]_out[73] sram[2008]->outb sram[2008]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[346], level=1, select_path_id=0. ***** -*****1***** -Xsram[2008] sram->in sram[2008]->out sram[2008]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2008]->out) 0 -.nodeset V(sram[2008]->outb) vsp -Xmux_1level_tapbuf_size2[347] grid[2][1]_pin[0][3][9] chanx[1][1]_in[76] chany[1][1]_out[75] sram[2009]->outb sram[2009]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[347], level=1, select_path_id=0. ***** -*****1***** -Xsram[2009] sram->in sram[2009]->out sram[2009]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2009]->out) 0 -.nodeset V(sram[2009]->outb) vsp -Xmux_1level_tapbuf_size2[348] grid[2][1]_pin[0][3][9] chanx[1][1]_in[78] chany[1][1]_out[77] sram[2010]->outb sram[2010]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[348], level=1, select_path_id=0. ***** -*****1***** -Xsram[2010] sram->in sram[2010]->out sram[2010]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2010]->out) 0 -.nodeset V(sram[2010]->outb) vsp -Xmux_1level_tapbuf_size2[349] grid[2][1]_pin[0][3][9] chanx[1][1]_in[80] chany[1][1]_out[79] sram[2011]->outb sram[2011]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[349], level=1, select_path_id=0. ***** -*****1***** -Xsram[2011] sram->in sram[2011]->out sram[2011]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2011]->out) 0 -.nodeset V(sram[2011]->outb) vsp -Xmux_1level_tapbuf_size2[350] grid[2][1]_pin[0][3][11] chanx[1][1]_in[82] chany[1][1]_out[81] sram[2012]->outb sram[2012]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[350], level=1, select_path_id=0. ***** -*****1***** -Xsram[2012] sram->in sram[2012]->out sram[2012]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2012]->out) 0 -.nodeset V(sram[2012]->outb) vsp -Xmux_1level_tapbuf_size2[351] grid[2][1]_pin[0][3][11] chanx[1][1]_in[84] chany[1][1]_out[83] sram[2013]->outb sram[2013]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[351], level=1, select_path_id=0. ***** -*****1***** -Xsram[2013] sram->in sram[2013]->out sram[2013]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2013]->out) 0 -.nodeset V(sram[2013]->outb) vsp -Xmux_1level_tapbuf_size2[352] grid[2][1]_pin[0][3][11] chanx[1][1]_in[86] chany[1][1]_out[85] sram[2014]->outb sram[2014]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[352], level=1, select_path_id=0. ***** -*****1***** -Xsram[2014] sram->in sram[2014]->out sram[2014]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2014]->out) 0 -.nodeset V(sram[2014]->outb) vsp -Xmux_1level_tapbuf_size2[353] grid[2][1]_pin[0][3][11] chanx[1][1]_in[88] chany[1][1]_out[87] sram[2015]->outb sram[2015]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[353], level=1, select_path_id=0. ***** -*****1***** -Xsram[2015] sram->in sram[2015]->out sram[2015]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2015]->out) 0 -.nodeset V(sram[2015]->outb) vsp -Xmux_1level_tapbuf_size2[354] grid[2][1]_pin[0][3][11] chanx[1][1]_in[90] chany[1][1]_out[89] sram[2016]->outb sram[2016]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[354], level=1, select_path_id=0. ***** -*****1***** -Xsram[2016] sram->in sram[2016]->out sram[2016]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2016]->out) 0 -.nodeset V(sram[2016]->outb) vsp -Xmux_1level_tapbuf_size2[355] grid[2][1]_pin[0][3][13] chanx[1][1]_in[92] chany[1][1]_out[91] sram[2017]->outb sram[2017]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[355], level=1, select_path_id=0. ***** -*****1***** -Xsram[2017] sram->in sram[2017]->out sram[2017]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2017]->out) 0 -.nodeset V(sram[2017]->outb) vsp -Xmux_1level_tapbuf_size2[356] grid[2][1]_pin[0][3][13] chanx[1][1]_in[94] chany[1][1]_out[93] sram[2018]->outb sram[2018]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[356], level=1, select_path_id=0. ***** -*****1***** -Xsram[2018] sram->in sram[2018]->out sram[2018]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2018]->out) 0 -.nodeset V(sram[2018]->outb) vsp -Xmux_1level_tapbuf_size2[357] grid[2][1]_pin[0][3][13] chanx[1][1]_in[96] chany[1][1]_out[95] sram[2019]->outb sram[2019]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[357], level=1, select_path_id=0. ***** -*****1***** -Xsram[2019] sram->in sram[2019]->out sram[2019]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2019]->out) 0 -.nodeset V(sram[2019]->outb) vsp -Xmux_1level_tapbuf_size2[358] grid[2][1]_pin[0][3][13] chanx[1][1]_in[98] chany[1][1]_out[97] sram[2020]->outb sram[2020]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[358], level=1, select_path_id=0. ***** -*****1***** -Xsram[2020] sram->in sram[2020]->out sram[2020]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2020]->out) 0 -.nodeset V(sram[2020]->outb) vsp -Xmux_1level_tapbuf_size2[359] grid[2][1]_pin[0][3][13] chanx[1][1]_in[0] chany[1][1]_out[99] sram[2021]->outb sram[2021]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[359], level=1, select_path_id=0. ***** -*****1***** -Xsram[2021] sram->in sram[2021]->out sram[2021]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2021]->out) 0 -.nodeset V(sram[2021]->outb) vsp -***** left side Multiplexers ***** -Xmux_1level_tapbuf_size3[360] grid[1][1]_pin[0][0][40] grid[1][2]_pin[0][2][15] chany[1][1]_in[98] chanx[1][1]_out[1] sram[2022]->outb sram[2022]->out sram[2023]->out sram[2023]->outb sram[2024]->out sram[2024]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[360], level=1, select_path_id=0. ***** -*****100***** -Xsram[2022] sram->in sram[2022]->out sram[2022]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2022]->out) 0 -.nodeset V(sram[2022]->outb) vsp -Xsram[2023] sram->in sram[2023]->out sram[2023]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2023]->out) 0 -.nodeset V(sram[2023]->outb) vsp -Xsram[2024] sram->in sram[2024]->out sram[2024]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2024]->out) 0 -.nodeset V(sram[2024]->outb) vsp -Xmux_1level_tapbuf_size3[361] grid[1][1]_pin[0][0][40] grid[1][2]_pin[0][2][15] chany[1][1]_in[0] chanx[1][1]_out[3] sram[2025]->outb sram[2025]->out sram[2026]->out sram[2026]->outb sram[2027]->out sram[2027]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[361], level=1, select_path_id=0. ***** -*****100***** -Xsram[2025] sram->in sram[2025]->out sram[2025]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2025]->out) 0 -.nodeset V(sram[2025]->outb) vsp -Xsram[2026] sram->in sram[2026]->out sram[2026]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2026]->out) 0 -.nodeset V(sram[2026]->outb) vsp -Xsram[2027] sram->in sram[2027]->out sram[2027]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2027]->out) 0 -.nodeset V(sram[2027]->outb) vsp -Xmux_1level_tapbuf_size3[362] grid[1][1]_pin[0][0][40] grid[1][2]_pin[0][2][15] chany[1][1]_in[2] chanx[1][1]_out[5] sram[2028]->outb sram[2028]->out sram[2029]->out sram[2029]->outb sram[2030]->out sram[2030]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[362], level=1, select_path_id=0. ***** -*****100***** -Xsram[2028] sram->in sram[2028]->out sram[2028]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2028]->out) 0 -.nodeset V(sram[2028]->outb) vsp -Xsram[2029] sram->in sram[2029]->out sram[2029]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2029]->out) 0 -.nodeset V(sram[2029]->outb) vsp -Xsram[2030] sram->in sram[2030]->out sram[2030]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2030]->out) 0 -.nodeset V(sram[2030]->outb) vsp -Xmux_1level_tapbuf_size3[363] grid[1][1]_pin[0][0][40] grid[1][2]_pin[0][2][15] chany[1][1]_in[4] chanx[1][1]_out[7] sram[2031]->outb sram[2031]->out sram[2032]->out sram[2032]->outb sram[2033]->out sram[2033]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[363], level=1, select_path_id=0. ***** -*****100***** -Xsram[2031] sram->in sram[2031]->out sram[2031]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2031]->out) 0 -.nodeset V(sram[2031]->outb) vsp -Xsram[2032] sram->in sram[2032]->out sram[2032]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2032]->out) 0 -.nodeset V(sram[2032]->outb) vsp -Xsram[2033] sram->in sram[2033]->out sram[2033]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2033]->out) 0 -.nodeset V(sram[2033]->outb) vsp -Xmux_1level_tapbuf_size3[364] grid[1][1]_pin[0][0][40] grid[1][2]_pin[0][2][15] chany[1][1]_in[6] chanx[1][1]_out[9] sram[2034]->outb sram[2034]->out sram[2035]->out sram[2035]->outb sram[2036]->out sram[2036]->outb svdd sgnd mux_1level_tapbuf_size3 -***** SRAM bits for MUX[364], level=1, select_path_id=0. ***** -*****100***** -Xsram[2034] sram->in sram[2034]->out sram[2034]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2034]->out) 0 -.nodeset V(sram[2034]->outb) vsp -Xsram[2035] sram->in sram[2035]->out sram[2035]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2035]->out) 0 -.nodeset V(sram[2035]->outb) vsp -Xsram[2036] sram->in sram[2036]->out sram[2036]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2036]->out) 0 -.nodeset V(sram[2036]->outb) vsp -Xmux_1level_tapbuf_size2[365] grid[1][1]_pin[0][0][44] chany[1][1]_in[8] chanx[1][1]_out[11] sram[2037]->outb sram[2037]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[365], level=1, select_path_id=0. ***** -*****1***** -Xsram[2037] sram->in sram[2037]->out sram[2037]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2037]->out) 0 -.nodeset V(sram[2037]->outb) vsp -Xmux_1level_tapbuf_size2[366] grid[1][1]_pin[0][0][44] chany[1][1]_in[10] chanx[1][1]_out[13] sram[2038]->outb sram[2038]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[366], level=1, select_path_id=0. ***** -*****1***** -Xsram[2038] sram->in sram[2038]->out sram[2038]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2038]->out) 0 -.nodeset V(sram[2038]->outb) vsp -Xmux_1level_tapbuf_size2[367] grid[1][1]_pin[0][0][44] chany[1][1]_in[12] chanx[1][1]_out[15] sram[2039]->outb sram[2039]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[367], level=1, select_path_id=0. ***** -*****1***** -Xsram[2039] sram->in sram[2039]->out sram[2039]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2039]->out) 0 -.nodeset V(sram[2039]->outb) vsp -Xmux_1level_tapbuf_size2[368] grid[1][1]_pin[0][0][44] chany[1][1]_in[14] chanx[1][1]_out[17] sram[2040]->outb sram[2040]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[368], level=1, select_path_id=0. ***** -*****1***** -Xsram[2040] sram->in sram[2040]->out sram[2040]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2040]->out) 0 -.nodeset V(sram[2040]->outb) vsp -Xmux_1level_tapbuf_size2[369] grid[1][1]_pin[0][0][44] chany[1][1]_in[16] chanx[1][1]_out[19] sram[2041]->outb sram[2041]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[369], level=1, select_path_id=0. ***** -*****1***** -Xsram[2041] sram->in sram[2041]->out sram[2041]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2041]->out) 0 -.nodeset V(sram[2041]->outb) vsp -Xmux_1level_tapbuf_size2[370] grid[1][1]_pin[0][0][48] chany[1][1]_in[18] chanx[1][1]_out[21] sram[2042]->outb sram[2042]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[370], level=1, select_path_id=0. ***** -*****1***** -Xsram[2042] sram->in sram[2042]->out sram[2042]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2042]->out) 0 -.nodeset V(sram[2042]->outb) vsp -Xmux_1level_tapbuf_size2[371] grid[1][1]_pin[0][0][48] chany[1][1]_in[20] chanx[1][1]_out[23] sram[2043]->outb sram[2043]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[371], level=1, select_path_id=0. ***** -*****1***** -Xsram[2043] sram->in sram[2043]->out sram[2043]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2043]->out) 0 -.nodeset V(sram[2043]->outb) vsp -Xmux_1level_tapbuf_size2[372] grid[1][1]_pin[0][0][48] chany[1][1]_in[22] chanx[1][1]_out[25] sram[2044]->outb sram[2044]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[372], level=1, select_path_id=0. ***** -*****1***** -Xsram[2044] sram->in sram[2044]->out sram[2044]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2044]->out) 0 -.nodeset V(sram[2044]->outb) vsp -Xmux_1level_tapbuf_size2[373] grid[1][1]_pin[0][0][48] chany[1][1]_in[24] chanx[1][1]_out[27] sram[2045]->outb sram[2045]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[373], level=1, select_path_id=0. ***** -*****1***** -Xsram[2045] sram->in sram[2045]->out sram[2045]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2045]->out) 0 -.nodeset V(sram[2045]->outb) vsp -Xmux_1level_tapbuf_size2[374] grid[1][1]_pin[0][0][48] chany[1][1]_in[26] chanx[1][1]_out[29] sram[2046]->outb sram[2046]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[374], level=1, select_path_id=0. ***** -*****1***** -Xsram[2046] sram->in sram[2046]->out sram[2046]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2046]->out) 0 -.nodeset V(sram[2046]->outb) vsp -Xmux_1level_tapbuf_size2[375] grid[1][2]_pin[0][2][1] chany[1][1]_in[28] chanx[1][1]_out[31] sram[2047]->outb sram[2047]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[375], level=1, select_path_id=0. ***** -*****1***** -Xsram[2047] sram->in sram[2047]->out sram[2047]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2047]->out) 0 -.nodeset V(sram[2047]->outb) vsp -Xmux_1level_tapbuf_size2[376] grid[1][2]_pin[0][2][1] chany[1][1]_in[30] chanx[1][1]_out[33] sram[2048]->outb sram[2048]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[376], level=1, select_path_id=0. ***** -*****1***** -Xsram[2048] sram->in sram[2048]->out sram[2048]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2048]->out) 0 -.nodeset V(sram[2048]->outb) vsp -Xmux_1level_tapbuf_size2[377] grid[1][2]_pin[0][2][1] chany[1][1]_in[32] chanx[1][1]_out[35] sram[2049]->outb sram[2049]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[377], level=1, select_path_id=0. ***** -*****1***** -Xsram[2049] sram->in sram[2049]->out sram[2049]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2049]->out) 0 -.nodeset V(sram[2049]->outb) vsp -Xmux_1level_tapbuf_size2[378] grid[1][2]_pin[0][2][1] chany[1][1]_in[34] chanx[1][1]_out[37] sram[2050]->outb sram[2050]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[378], level=1, select_path_id=0. ***** -*****1***** -Xsram[2050] sram->in sram[2050]->out sram[2050]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2050]->out) 0 -.nodeset V(sram[2050]->outb) vsp -Xmux_1level_tapbuf_size2[379] grid[1][2]_pin[0][2][1] chany[1][1]_in[36] chanx[1][1]_out[39] sram[2051]->outb sram[2051]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[379], level=1, select_path_id=0. ***** -*****1***** -Xsram[2051] sram->in sram[2051]->out sram[2051]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2051]->out) 0 -.nodeset V(sram[2051]->outb) vsp -Xmux_1level_tapbuf_size2[380] grid[1][2]_pin[0][2][3] chany[1][1]_in[38] chanx[1][1]_out[41] sram[2052]->outb sram[2052]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[380], level=1, select_path_id=0. ***** -*****1***** -Xsram[2052] sram->in sram[2052]->out sram[2052]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2052]->out) 0 -.nodeset V(sram[2052]->outb) vsp -Xmux_1level_tapbuf_size2[381] grid[1][2]_pin[0][2][3] chany[1][1]_in[40] chanx[1][1]_out[43] sram[2053]->outb sram[2053]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[381], level=1, select_path_id=0. ***** -*****1***** -Xsram[2053] sram->in sram[2053]->out sram[2053]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2053]->out) 0 -.nodeset V(sram[2053]->outb) vsp -Xmux_1level_tapbuf_size2[382] grid[1][2]_pin[0][2][3] chany[1][1]_in[42] chanx[1][1]_out[45] sram[2054]->outb sram[2054]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[382], level=1, select_path_id=0. ***** -*****1***** -Xsram[2054] sram->in sram[2054]->out sram[2054]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2054]->out) 0 -.nodeset V(sram[2054]->outb) vsp -Xmux_1level_tapbuf_size2[383] grid[1][2]_pin[0][2][3] chany[1][1]_in[44] chanx[1][1]_out[47] sram[2055]->outb sram[2055]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[383], level=1, select_path_id=0. ***** -*****1***** -Xsram[2055] sram->in sram[2055]->out sram[2055]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2055]->out) 0 -.nodeset V(sram[2055]->outb) vsp -Xmux_1level_tapbuf_size2[384] grid[1][2]_pin[0][2][3] chany[1][1]_in[46] chanx[1][1]_out[49] sram[2056]->outb sram[2056]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[384], level=1, select_path_id=0. ***** -*****1***** -Xsram[2056] sram->in sram[2056]->out sram[2056]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2056]->out) 0 -.nodeset V(sram[2056]->outb) vsp -Xmux_1level_tapbuf_size2[385] grid[1][2]_pin[0][2][5] chany[1][1]_in[48] chanx[1][1]_out[51] sram[2057]->outb sram[2057]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[385], level=1, select_path_id=0. ***** -*****1***** -Xsram[2057] sram->in sram[2057]->out sram[2057]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2057]->out) 0 -.nodeset V(sram[2057]->outb) vsp -Xmux_1level_tapbuf_size2[386] grid[1][2]_pin[0][2][5] chany[1][1]_in[50] chanx[1][1]_out[53] sram[2058]->outb sram[2058]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[386], level=1, select_path_id=0. ***** -*****1***** -Xsram[2058] sram->in sram[2058]->out sram[2058]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2058]->out) 0 -.nodeset V(sram[2058]->outb) vsp -Xmux_1level_tapbuf_size2[387] grid[1][2]_pin[0][2][5] chany[1][1]_in[52] chanx[1][1]_out[55] sram[2059]->outb sram[2059]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[387], level=1, select_path_id=0. ***** -*****1***** -Xsram[2059] sram->in sram[2059]->out sram[2059]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2059]->out) 0 -.nodeset V(sram[2059]->outb) vsp -Xmux_1level_tapbuf_size2[388] grid[1][2]_pin[0][2][5] chany[1][1]_in[54] chanx[1][1]_out[57] sram[2060]->outb sram[2060]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[388], level=1, select_path_id=0. ***** -*****1***** -Xsram[2060] sram->in sram[2060]->out sram[2060]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2060]->out) 0 -.nodeset V(sram[2060]->outb) vsp -Xmux_1level_tapbuf_size2[389] grid[1][2]_pin[0][2][5] chany[1][1]_in[56] chanx[1][1]_out[59] sram[2061]->outb sram[2061]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[389], level=1, select_path_id=0. ***** -*****1***** -Xsram[2061] sram->in sram[2061]->out sram[2061]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2061]->out) 0 -.nodeset V(sram[2061]->outb) vsp -Xmux_1level_tapbuf_size2[390] grid[1][2]_pin[0][2][7] chany[1][1]_in[58] chanx[1][1]_out[61] sram[2062]->outb sram[2062]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[390], level=1, select_path_id=0. ***** -*****1***** -Xsram[2062] sram->in sram[2062]->out sram[2062]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2062]->out) 0 -.nodeset V(sram[2062]->outb) vsp -Xmux_1level_tapbuf_size2[391] grid[1][2]_pin[0][2][7] chany[1][1]_in[60] chanx[1][1]_out[63] sram[2063]->outb sram[2063]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[391], level=1, select_path_id=0. ***** -*****1***** -Xsram[2063] sram->in sram[2063]->out sram[2063]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2063]->out) 0 -.nodeset V(sram[2063]->outb) vsp -Xmux_1level_tapbuf_size2[392] grid[1][2]_pin[0][2][7] chany[1][1]_in[62] chanx[1][1]_out[65] sram[2064]->outb sram[2064]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[392], level=1, select_path_id=0. ***** -*****1***** -Xsram[2064] sram->in sram[2064]->out sram[2064]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2064]->out) 0 -.nodeset V(sram[2064]->outb) vsp -Xmux_1level_tapbuf_size2[393] grid[1][2]_pin[0][2][7] chany[1][1]_in[64] chanx[1][1]_out[67] sram[2065]->outb sram[2065]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[393], level=1, select_path_id=0. ***** -*****1***** -Xsram[2065] sram->in sram[2065]->out sram[2065]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2065]->out) 0 -.nodeset V(sram[2065]->outb) vsp -Xmux_1level_tapbuf_size2[394] grid[1][2]_pin[0][2][7] chany[1][1]_in[66] chanx[1][1]_out[69] sram[2066]->outb sram[2066]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[394], level=1, select_path_id=0. ***** -*****1***** -Xsram[2066] sram->in sram[2066]->out sram[2066]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2066]->out) 0 -.nodeset V(sram[2066]->outb) vsp -Xmux_1level_tapbuf_size2[395] grid[1][2]_pin[0][2][9] chany[1][1]_in[68] chanx[1][1]_out[71] sram[2067]->outb sram[2067]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[395], level=1, select_path_id=0. ***** -*****1***** -Xsram[2067] sram->in sram[2067]->out sram[2067]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2067]->out) 0 -.nodeset V(sram[2067]->outb) vsp -Xmux_1level_tapbuf_size2[396] grid[1][2]_pin[0][2][9] chany[1][1]_in[70] chanx[1][1]_out[73] sram[2068]->outb sram[2068]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[396], level=1, select_path_id=0. ***** -*****1***** -Xsram[2068] sram->in sram[2068]->out sram[2068]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2068]->out) 0 -.nodeset V(sram[2068]->outb) vsp -Xmux_1level_tapbuf_size2[397] grid[1][2]_pin[0][2][9] chany[1][1]_in[72] chanx[1][1]_out[75] sram[2069]->outb sram[2069]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[397], level=1, select_path_id=0. ***** -*****1***** -Xsram[2069] sram->in sram[2069]->out sram[2069]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2069]->out) 0 -.nodeset V(sram[2069]->outb) vsp -Xmux_1level_tapbuf_size2[398] grid[1][2]_pin[0][2][9] chany[1][1]_in[74] chanx[1][1]_out[77] sram[2070]->outb sram[2070]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[398], level=1, select_path_id=0. ***** -*****1***** -Xsram[2070] sram->in sram[2070]->out sram[2070]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2070]->out) 0 -.nodeset V(sram[2070]->outb) vsp -Xmux_1level_tapbuf_size2[399] grid[1][2]_pin[0][2][9] chany[1][1]_in[76] chanx[1][1]_out[79] sram[2071]->outb sram[2071]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[399], level=1, select_path_id=0. ***** -*****1***** -Xsram[2071] sram->in sram[2071]->out sram[2071]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2071]->out) 0 -.nodeset V(sram[2071]->outb) vsp -Xmux_1level_tapbuf_size2[400] grid[1][2]_pin[0][2][11] chany[1][1]_in[78] chanx[1][1]_out[81] sram[2072]->outb sram[2072]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[400], level=1, select_path_id=0. ***** -*****1***** -Xsram[2072] sram->in sram[2072]->out sram[2072]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2072]->out) 0 -.nodeset V(sram[2072]->outb) vsp -Xmux_1level_tapbuf_size2[401] grid[1][2]_pin[0][2][11] chany[1][1]_in[80] chanx[1][1]_out[83] sram[2073]->outb sram[2073]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[401], level=1, select_path_id=0. ***** -*****1***** -Xsram[2073] sram->in sram[2073]->out sram[2073]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2073]->out) 0 -.nodeset V(sram[2073]->outb) vsp -Xmux_1level_tapbuf_size2[402] grid[1][2]_pin[0][2][11] chany[1][1]_in[82] chanx[1][1]_out[85] sram[2074]->outb sram[2074]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[402], level=1, select_path_id=0. ***** -*****1***** -Xsram[2074] sram->in sram[2074]->out sram[2074]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2074]->out) 0 -.nodeset V(sram[2074]->outb) vsp -Xmux_1level_tapbuf_size2[403] grid[1][2]_pin[0][2][11] chany[1][1]_in[84] chanx[1][1]_out[87] sram[2075]->outb sram[2075]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[403], level=1, select_path_id=0. ***** -*****1***** -Xsram[2075] sram->in sram[2075]->out sram[2075]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2075]->out) 0 -.nodeset V(sram[2075]->outb) vsp -Xmux_1level_tapbuf_size2[404] grid[1][2]_pin[0][2][11] chany[1][1]_in[86] chanx[1][1]_out[89] sram[2076]->outb sram[2076]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[404], level=1, select_path_id=0. ***** -*****1***** -Xsram[2076] sram->in sram[2076]->out sram[2076]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2076]->out) 0 -.nodeset V(sram[2076]->outb) vsp -Xmux_1level_tapbuf_size2[405] grid[1][2]_pin[0][2][13] chany[1][1]_in[88] chanx[1][1]_out[91] sram[2077]->outb sram[2077]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[405], level=1, select_path_id=0. ***** -*****1***** -Xsram[2077] sram->in sram[2077]->out sram[2077]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2077]->out) 0 -.nodeset V(sram[2077]->outb) vsp -Xmux_1level_tapbuf_size2[406] grid[1][2]_pin[0][2][13] chany[1][1]_in[90] chanx[1][1]_out[93] sram[2078]->outb sram[2078]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[406], level=1, select_path_id=0. ***** -*****1***** -Xsram[2078] sram->in sram[2078]->out sram[2078]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2078]->out) 0 -.nodeset V(sram[2078]->outb) vsp -Xmux_1level_tapbuf_size2[407] grid[1][2]_pin[0][2][13] chany[1][1]_in[92] chanx[1][1]_out[95] sram[2079]->outb sram[2079]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[407], level=1, select_path_id=0. ***** -*****1***** -Xsram[2079] sram->in sram[2079]->out sram[2079]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2079]->out) 0 -.nodeset V(sram[2079]->outb) vsp -Xmux_1level_tapbuf_size2[408] grid[1][2]_pin[0][2][13] chany[1][1]_in[94] chanx[1][1]_out[97] sram[2080]->outb sram[2080]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[408], level=1, select_path_id=0. ***** -*****1***** -Xsram[2080] sram->in sram[2080]->out sram[2080]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2080]->out) 0 -.nodeset V(sram[2080]->outb) vsp -Xmux_1level_tapbuf_size2[409] grid[1][2]_pin[0][2][13] chany[1][1]_in[96] chanx[1][1]_out[99] sram[2081]->outb sram[2081]->out svdd sgnd mux_1level_tapbuf_size2 -***** SRAM bits for MUX[409], level=1, select_path_id=0. ***** -*****1***** -Xsram[2081] sram->in sram[2081]->out sram[2081]->outb gvdd_sram_sbs sgnd sram6T -.nodeset V(sram[2081]->out) 0 -.nodeset V(sram[2081]->outb) vsp -.eom diff --git a/examples/spice_test_example_2/subckt/wires.sp b/examples/spice_test_example_2/subckt/wires.sp deleted file mode 100644 index fce9b7033..000000000 --- a/examples/spice_test_example_2/subckt/wires.sp +++ /dev/null @@ -1,50 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: Wires * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:08 2018 - * -***************************** -* Wire, spice_model_name=direct_interc -.subckt direct_interc in out svdd sgnd -Rshortcut in out 0 -.eom - -* Wire models for segments in routing -* Wire, spice_model_name=chan_segment -.subckt chan_segment_seg0 in out mid_out svdd sgnd -Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2' -Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2' -Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2' -Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2' -* Connect the output of middle point -Vmid_out_ckt pie_wire_in0_inter mid_out 0 -Rin in pie_wire_in0 0 -Rout pie_wire_in1 out 0 -.eom - -* Wire, spice_model_name=chan_segment -.subckt chan_segment_seg1 in out mid_out svdd sgnd -Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2' -Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2' -Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2' -Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2' -* Connect the output of middle point -Vmid_out_ckt pie_wire_in0_inter mid_out 0 -Rin in pie_wire_in0 0 -Rout pie_wire_in1 out 0 -.eom - -* Wire, spice_model_name=chan_segment -.subckt chan_segment_seg2 in out mid_out svdd sgnd -Clvin pie_wire_in0 sgnd 'chan_segment_wire_param_cap_val/2' -Rlv0_idx0 pie_wire_in0 pie_wire_in0_inter 'chan_segment_wire_param_res_val/2' -Rlv0_idx1 pie_wire_in0_inter pie_wire_in1 'chan_segment_wire_param_res_val/2' -Clv0_idx1 pie_wire_in1 sgnd 'chan_segment_wire_param_cap_val/2' -* Connect the output of middle point -Vmid_out_ckt pie_wire_in0_inter mid_out 0 -Rin in pie_wire_in0 0 -Rout pie_wire_in1 out 0 -.eom - diff --git a/examples/spice_test_example_2/top_tb/example_2_top.sp b/examples/spice_test_example_2/top_tb/example_2_top.sp deleted file mode 100644 index 44806aacf..000000000 --- a/examples/spice_test_example_2/top_tb/example_2_top.sp +++ /dev/null @@ -1,2663 +0,0 @@ -***************************** -* FPGA SPICE Netlist * -* Description: FPGA SPICE Netlist for Design: example_2 * -* Author: Xifan TANG * -* Organization: EPFL/IC/LSI * -* Date: Thu Nov 15 14:26:09 2018 - * -***************************** -****** Include Header file: circuit design parameters ***** -.include './spice_test_example_2/include/design_params.sp' -****** Include Header file: measurement parameters ***** -.include './spice_test_example_2/include/meas_params.sp' -****** Include Header file: stimulation parameters ***** -.include './spice_test_example_2/include/stimulate_params.sp' -****** Include subckt netlists: NMOS and PMOS ***** -.include './spice_test_example_2/subckt/nmos_pmos.sp' -****** Include subckt netlists: Inverters, Buffers ***** -.include './spice_test_example_2/subckt/inv_buf_trans_gate.sp' -****** Include subckt netlists: Multiplexers ***** -.include './spice_test_example_2/subckt/muxes.sp' -****** Include subckt netlists: Wires ***** -.include './spice_test_example_2/subckt/wires.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/ff.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/sram.sp' -.include '/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/SpiceNetlists/io.sp' -****** Include subckt netlists: Look-Up Tables (LUTs) ***** -.include './spice_test_example_2/subckt/luts.sp' -****** Include subckt netlists: Logic Blocks ***** -.include './spice_test_example_2/subckt/grid_header.sp' -****** Include subckt netlists: Routing structures (Switch Boxes, Channels, Connection Boxes) ***** -.include './spice_test_example_2/subckt/routing_header.sp' -***** Generic global ports ***** -***** VDD, GND ***** -.global gvdd -.global ggnd -***** Global set ports ***** -.global gset gset_inv -***** Global reset ports ***** -.global greset greset_inv -***** Configuration done ports ***** -.global gconfig_done gconfig_done_inv -***** Global SRAM input ***** -.global sram->in -***** Global Clock Signals ***** -.global gclock -.global gclock_inv -***** User-defined global ports ****** -.global - -***** BEGIN Global ports ***** -+ zin[0] clk[0] Reset[0] Set[0] -***** END Global ports ***** -.global gvdd_local_interc gvdd_io gvdd_hardlogic -.global gvdd_sram_local_routing -.global gvdd_sram_luts -.global gvdd_sram_cbs -.global gvdd_sram_sbs -.global gvdd_sram_io -***** Global VDD ports of Look-Up Table ***** -.global -+ gvdd_lut6[0] -+ gvdd_lut6[1] -+ gvdd_lut6[2] -+ gvdd_lut6[3] -+ gvdd_lut6[4] -+ gvdd_lut6[5] -+ gvdd_lut6[6] -+ gvdd_lut6[7] -+ gvdd_lut6[8] -+ gvdd_lut6[9] - -***** Global VDD ports of Flip-flop ***** -.global -+ gvdd_dff[0] -+ gvdd_dff[1] -+ gvdd_dff[2] -+ gvdd_dff[3] -+ gvdd_dff[4] -+ gvdd_dff[5] -+ gvdd_dff[6] -+ gvdd_dff[7] -+ gvdd_dff[8] -+ gvdd_dff[9] - -***** Global VDD ports of iopad ***** -.global -+ gvdd_iopad[0] -+ gvdd_iopad[1] -+ gvdd_iopad[2] -+ gvdd_iopad[3] -+ gvdd_iopad[4] -+ gvdd_iopad[5] -+ gvdd_iopad[6] -+ gvdd_iopad[7] -+ gvdd_iopad[8] -+ gvdd_iopad[9] -+ gvdd_iopad[10] -+ gvdd_iopad[11] -+ gvdd_iopad[12] -+ gvdd_iopad[13] -+ gvdd_iopad[14] -+ gvdd_iopad[15] -+ gvdd_iopad[16] -+ gvdd_iopad[17] -+ gvdd_iopad[18] -+ gvdd_iopad[19] -+ gvdd_iopad[20] -+ gvdd_iopad[21] -+ gvdd_iopad[22] -+ gvdd_iopad[23] -+ gvdd_iopad[24] -+ gvdd_iopad[25] -+ gvdd_iopad[26] -+ gvdd_iopad[27] -+ gvdd_iopad[28] -+ gvdd_iopad[29] -+ gvdd_iopad[30] -+ gvdd_iopad[31] - -***** Global VDD ports of hard_logic ***** -.global - -***** Global Vdds for Switch Boxes ***** -.global gvdd_sb[0][0] gvdd_sb[0][1] gvdd_sb[1][0] gvdd_sb[1][1] -***** Global Vdds for Connection Blocks - X channels ***** -.global gvdd_cbx[1][0] gvdd_cbx[1][1] -***** Global Vdds for Connection Blocks - Y channels ***** -.global gvdd_cby[0][1] gvdd_cby[1][1] -***** Global input/output ports of I/O Pads ***** -.global -+ gfpga_pad_iopad[0] -+ gfpga_pad_iopad[1] -+ gfpga_pad_iopad[2] -+ gfpga_pad_iopad[3] -+ gfpga_pad_iopad[4] -+ gfpga_pad_iopad[5] -+ gfpga_pad_iopad[6] -+ gfpga_pad_iopad[7] -+ gfpga_pad_iopad[8] -+ gfpga_pad_iopad[9] -+ gfpga_pad_iopad[10] -+ gfpga_pad_iopad[11] -+ gfpga_pad_iopad[12] -+ gfpga_pad_iopad[13] -+ gfpga_pad_iopad[14] -+ gfpga_pad_iopad[15] -+ gfpga_pad_iopad[16] -+ gfpga_pad_iopad[17] -+ gfpga_pad_iopad[18] -+ gfpga_pad_iopad[19] -+ gfpga_pad_iopad[20] -+ gfpga_pad_iopad[21] -+ gfpga_pad_iopad[22] -+ gfpga_pad_iopad[23] -+ gfpga_pad_iopad[24] -+ gfpga_pad_iopad[25] -+ gfpga_pad_iopad[26] -+ gfpga_pad_iopad[27] -+ gfpga_pad_iopad[28] -+ gfpga_pad_iopad[29] -+ gfpga_pad_iopad[30] -+ gfpga_pad_iopad[31] - -***** Link Blif Benchmark inputs to FPGA IOPADs ***** -***** Blif Benchmark inout I0 is mapped to FPGA IOPAD gfpga_pad_[17] ***** -RI0_gfpga_pad_[17] I0_gfpga_pad_[17] gfpga_pad_iopad[17] 0 -***** Blif Benchmark inout clk is mapped to FPGA IOPAD gfpga_pad_[1] ***** -Rclk_gfpga_pad_[1] clk_gfpga_pad_[1] gfpga_pad_iopad[1] 0 -***** Blif Benchmark inout out_Q0 is mapped to FPGA IOPAD gfpga_pad_[30] ***** -Rout_Q0_gfpga_pad_[30] out_Q0_gfpga_pad_[30] gfpga_pad_iopad[30] 0 -.temp 25 -.option fast -Xgrid[1][1] -+ grid[1][1]_pin[0][0][0] -+ grid[1][1]_pin[0][0][4] -+ grid[1][1]_pin[0][0][8] -+ grid[1][1]_pin[0][0][12] -+ grid[1][1]_pin[0][0][16] -+ grid[1][1]_pin[0][0][20] -+ grid[1][1]_pin[0][0][24] -+ grid[1][1]_pin[0][0][28] -+ grid[1][1]_pin[0][0][32] -+ grid[1][1]_pin[0][0][36] -+ grid[1][1]_pin[0][0][40] -+ grid[1][1]_pin[0][0][44] -+ grid[1][1]_pin[0][0][48] -+ grid[1][1]_pin[0][1][1] -+ grid[1][1]_pin[0][1][5] -+ grid[1][1]_pin[0][1][9] -+ grid[1][1]_pin[0][1][13] -+ grid[1][1]_pin[0][1][17] -+ grid[1][1]_pin[0][1][21] -+ grid[1][1]_pin[0][1][25] -+ grid[1][1]_pin[0][1][29] -+ grid[1][1]_pin[0][1][33] -+ grid[1][1]_pin[0][1][37] -+ grid[1][1]_pin[0][1][41] -+ grid[1][1]_pin[0][1][45] -+ grid[1][1]_pin[0][1][49] -+ grid[1][1]_pin[0][2][2] -+ grid[1][1]_pin[0][2][6] -+ grid[1][1]_pin[0][2][10] -+ grid[1][1]_pin[0][2][14] -+ grid[1][1]_pin[0][2][18] -+ grid[1][1]_pin[0][2][22] -+ grid[1][1]_pin[0][2][26] -+ grid[1][1]_pin[0][2][30] -+ grid[1][1]_pin[0][2][34] -+ grid[1][1]_pin[0][2][38] -+ grid[1][1]_pin[0][2][42] -+ grid[1][1]_pin[0][2][46] -+ grid[1][1]_pin[0][2][50] -+ grid[1][1]_pin[0][3][3] -+ grid[1][1]_pin[0][3][7] -+ grid[1][1]_pin[0][3][11] -+ grid[1][1]_pin[0][3][15] -+ grid[1][1]_pin[0][3][19] -+ grid[1][1]_pin[0][3][23] -+ grid[1][1]_pin[0][3][27] -+ grid[1][1]_pin[0][3][31] -+ grid[1][1]_pin[0][3][35] -+ grid[1][1]_pin[0][3][39] -+ grid[1][1]_pin[0][3][43] -+ grid[1][1]_pin[0][3][47] -+ gvdd 0 grid[1][1] -Xgrid[0][1] -+ grid[0][1]_pin[0][1][0] -+ grid[0][1]_pin[0][1][1] -+ grid[0][1]_pin[0][1][2] -+ grid[0][1]_pin[0][1][3] -+ grid[0][1]_pin[0][1][4] -+ grid[0][1]_pin[0][1][5] -+ grid[0][1]_pin[0][1][6] -+ grid[0][1]_pin[0][1][7] -+ grid[0][1]_pin[0][1][8] -+ grid[0][1]_pin[0][1][9] -+ grid[0][1]_pin[0][1][10] -+ grid[0][1]_pin[0][1][11] -+ grid[0][1]_pin[0][1][12] -+ grid[0][1]_pin[0][1][13] -+ grid[0][1]_pin[0][1][14] -+ grid[0][1]_pin[0][1][15] -+ gvdd_io 0 grid[0][1] -Xgrid[2][1] -+ grid[2][1]_pin[0][3][0] -+ grid[2][1]_pin[0][3][1] -+ grid[2][1]_pin[0][3][2] -+ grid[2][1]_pin[0][3][3] -+ grid[2][1]_pin[0][3][4] -+ grid[2][1]_pin[0][3][5] -+ grid[2][1]_pin[0][3][6] -+ grid[2][1]_pin[0][3][7] -+ grid[2][1]_pin[0][3][8] -+ grid[2][1]_pin[0][3][9] -+ grid[2][1]_pin[0][3][10] -+ grid[2][1]_pin[0][3][11] -+ grid[2][1]_pin[0][3][12] -+ grid[2][1]_pin[0][3][13] -+ grid[2][1]_pin[0][3][14] -+ grid[2][1]_pin[0][3][15] -+ gvdd_io 0 grid[2][1] -Xgrid[1][0] -+ grid[1][0]_pin[0][0][0] -+ grid[1][0]_pin[0][0][1] -+ grid[1][0]_pin[0][0][2] -+ grid[1][0]_pin[0][0][3] -+ grid[1][0]_pin[0][0][4] -+ grid[1][0]_pin[0][0][5] -+ grid[1][0]_pin[0][0][6] -+ grid[1][0]_pin[0][0][7] -+ grid[1][0]_pin[0][0][8] -+ grid[1][0]_pin[0][0][9] -+ grid[1][0]_pin[0][0][10] -+ grid[1][0]_pin[0][0][11] -+ grid[1][0]_pin[0][0][12] -+ grid[1][0]_pin[0][0][13] -+ grid[1][0]_pin[0][0][14] -+ grid[1][0]_pin[0][0][15] -+ gvdd_io 0 grid[1][0] -Xgrid[1][2] -+ grid[1][2]_pin[0][2][0] -+ grid[1][2]_pin[0][2][1] -+ grid[1][2]_pin[0][2][2] -+ grid[1][2]_pin[0][2][3] -+ grid[1][2]_pin[0][2][4] -+ grid[1][2]_pin[0][2][5] -+ grid[1][2]_pin[0][2][6] -+ grid[1][2]_pin[0][2][7] -+ grid[1][2]_pin[0][2][8] -+ grid[1][2]_pin[0][2][9] -+ grid[1][2]_pin[0][2][10] -+ grid[1][2]_pin[0][2][11] -+ grid[1][2]_pin[0][2][12] -+ grid[1][2]_pin[0][2][13] -+ grid[1][2]_pin[0][2][14] -+ grid[1][2]_pin[0][2][15] -+ gvdd_io 0 grid[1][2] -Rdangling_grid[1][1]_pin[0][2][50] grid[1][1]_pin[0][2][50] 0 0 -.nodeset V(grid[1][1]_pin[0][2][50]) 0 -Xchanx[1][0] -+ chanx[1][0]_out[0] -+ chanx[1][0]_in[1] -+ chanx[1][0]_out[2] -+ chanx[1][0]_in[3] -+ chanx[1][0]_out[4] -+ chanx[1][0]_in[5] -+ chanx[1][0]_out[6] -+ chanx[1][0]_in[7] -+ chanx[1][0]_out[8] -+ chanx[1][0]_in[9] -+ chanx[1][0]_out[10] -+ chanx[1][0]_in[11] -+ chanx[1][0]_out[12] -+ chanx[1][0]_in[13] -+ chanx[1][0]_out[14] -+ chanx[1][0]_in[15] -+ chanx[1][0]_out[16] -+ chanx[1][0]_in[17] -+ chanx[1][0]_out[18] -+ chanx[1][0]_in[19] -+ chanx[1][0]_out[20] -+ chanx[1][0]_in[21] -+ chanx[1][0]_out[22] -+ chanx[1][0]_in[23] -+ chanx[1][0]_out[24] -+ chanx[1][0]_in[25] -+ chanx[1][0]_out[26] -+ chanx[1][0]_in[27] -+ chanx[1][0]_out[28] -+ chanx[1][0]_in[29] -+ chanx[1][0]_out[30] -+ chanx[1][0]_in[31] -+ chanx[1][0]_out[32] -+ chanx[1][0]_in[33] -+ chanx[1][0]_out[34] -+ chanx[1][0]_in[35] -+ chanx[1][0]_out[36] -+ chanx[1][0]_in[37] -+ chanx[1][0]_out[38] -+ chanx[1][0]_in[39] -+ chanx[1][0]_out[40] -+ chanx[1][0]_in[41] -+ chanx[1][0]_out[42] -+ chanx[1][0]_in[43] -+ chanx[1][0]_out[44] -+ chanx[1][0]_in[45] -+ chanx[1][0]_out[46] -+ chanx[1][0]_in[47] -+ chanx[1][0]_out[48] -+ chanx[1][0]_in[49] -+ chanx[1][0]_out[50] -+ chanx[1][0]_in[51] -+ chanx[1][0]_out[52] -+ chanx[1][0]_in[53] -+ chanx[1][0]_out[54] -+ chanx[1][0]_in[55] -+ chanx[1][0]_out[56] -+ chanx[1][0]_in[57] -+ chanx[1][0]_out[58] -+ chanx[1][0]_in[59] -+ chanx[1][0]_out[60] -+ chanx[1][0]_in[61] -+ chanx[1][0]_out[62] -+ chanx[1][0]_in[63] -+ chanx[1][0]_out[64] -+ chanx[1][0]_in[65] -+ chanx[1][0]_out[66] -+ chanx[1][0]_in[67] -+ chanx[1][0]_out[68] -+ chanx[1][0]_in[69] -+ chanx[1][0]_out[70] -+ chanx[1][0]_in[71] -+ chanx[1][0]_out[72] -+ chanx[1][0]_in[73] -+ chanx[1][0]_out[74] -+ chanx[1][0]_in[75] -+ chanx[1][0]_out[76] -+ chanx[1][0]_in[77] -+ chanx[1][0]_out[78] -+ chanx[1][0]_in[79] -+ chanx[1][0]_out[80] -+ chanx[1][0]_in[81] -+ chanx[1][0]_out[82] -+ chanx[1][0]_in[83] -+ chanx[1][0]_out[84] -+ chanx[1][0]_in[85] -+ chanx[1][0]_out[86] -+ chanx[1][0]_in[87] -+ chanx[1][0]_out[88] -+ chanx[1][0]_in[89] -+ chanx[1][0]_out[90] -+ chanx[1][0]_in[91] -+ chanx[1][0]_out[92] -+ chanx[1][0]_in[93] -+ chanx[1][0]_out[94] -+ chanx[1][0]_in[95] -+ chanx[1][0]_out[96] -+ chanx[1][0]_in[97] -+ chanx[1][0]_out[98] -+ chanx[1][0]_in[99] -+ chanx[1][0]_in[0] -+ chanx[1][0]_out[1] -+ chanx[1][0]_in[2] -+ chanx[1][0]_out[3] -+ chanx[1][0]_in[4] -+ chanx[1][0]_out[5] -+ chanx[1][0]_in[6] -+ chanx[1][0]_out[7] -+ chanx[1][0]_in[8] -+ chanx[1][0]_out[9] -+ chanx[1][0]_in[10] -+ chanx[1][0]_out[11] -+ chanx[1][0]_in[12] -+ chanx[1][0]_out[13] -+ chanx[1][0]_in[14] -+ chanx[1][0]_out[15] -+ chanx[1][0]_in[16] -+ chanx[1][0]_out[17] -+ chanx[1][0]_in[18] -+ chanx[1][0]_out[19] -+ chanx[1][0]_in[20] -+ chanx[1][0]_out[21] -+ chanx[1][0]_in[22] -+ chanx[1][0]_out[23] -+ chanx[1][0]_in[24] -+ chanx[1][0]_out[25] -+ chanx[1][0]_in[26] -+ chanx[1][0]_out[27] -+ chanx[1][0]_in[28] -+ chanx[1][0]_out[29] -+ chanx[1][0]_in[30] -+ chanx[1][0]_out[31] -+ chanx[1][0]_in[32] -+ chanx[1][0]_out[33] -+ chanx[1][0]_in[34] -+ chanx[1][0]_out[35] -+ chanx[1][0]_in[36] -+ chanx[1][0]_out[37] -+ chanx[1][0]_in[38] -+ chanx[1][0]_out[39] -+ chanx[1][0]_in[40] -+ chanx[1][0]_out[41] -+ chanx[1][0]_in[42] -+ chanx[1][0]_out[43] -+ chanx[1][0]_in[44] -+ chanx[1][0]_out[45] -+ chanx[1][0]_in[46] -+ chanx[1][0]_out[47] -+ chanx[1][0]_in[48] -+ chanx[1][0]_out[49] -+ chanx[1][0]_in[50] -+ chanx[1][0]_out[51] -+ chanx[1][0]_in[52] -+ chanx[1][0]_out[53] -+ chanx[1][0]_in[54] -+ chanx[1][0]_out[55] -+ chanx[1][0]_in[56] -+ chanx[1][0]_out[57] -+ chanx[1][0]_in[58] -+ chanx[1][0]_out[59] -+ chanx[1][0]_in[60] -+ chanx[1][0]_out[61] -+ chanx[1][0]_in[62] -+ chanx[1][0]_out[63] -+ chanx[1][0]_in[64] -+ chanx[1][0]_out[65] -+ chanx[1][0]_in[66] -+ chanx[1][0]_out[67] -+ chanx[1][0]_in[68] -+ chanx[1][0]_out[69] -+ chanx[1][0]_in[70] -+ chanx[1][0]_out[71] -+ chanx[1][0]_in[72] -+ chanx[1][0]_out[73] -+ chanx[1][0]_in[74] -+ chanx[1][0]_out[75] -+ chanx[1][0]_in[76] -+ chanx[1][0]_out[77] -+ chanx[1][0]_in[78] -+ chanx[1][0]_out[79] -+ chanx[1][0]_in[80] -+ chanx[1][0]_out[81] -+ chanx[1][0]_in[82] -+ chanx[1][0]_out[83] -+ chanx[1][0]_in[84] -+ chanx[1][0]_out[85] -+ chanx[1][0]_in[86] -+ chanx[1][0]_out[87] -+ chanx[1][0]_in[88] -+ chanx[1][0]_out[89] -+ chanx[1][0]_in[90] -+ chanx[1][0]_out[91] -+ chanx[1][0]_in[92] -+ chanx[1][0]_out[93] -+ chanx[1][0]_in[94] -+ chanx[1][0]_out[95] -+ chanx[1][0]_in[96] -+ chanx[1][0]_out[97] -+ chanx[1][0]_in[98] -+ chanx[1][0]_out[99] -+ chanx[1][0]_midout[0] -+ chanx[1][0]_midout[1] -+ chanx[1][0]_midout[2] -+ chanx[1][0]_midout[3] -+ chanx[1][0]_midout[4] -+ chanx[1][0]_midout[5] -+ chanx[1][0]_midout[6] -+ chanx[1][0]_midout[7] -+ chanx[1][0]_midout[8] -+ chanx[1][0]_midout[9] -+ chanx[1][0]_midout[10] -+ chanx[1][0]_midout[11] -+ chanx[1][0]_midout[12] -+ chanx[1][0]_midout[13] -+ chanx[1][0]_midout[14] -+ chanx[1][0]_midout[15] -+ chanx[1][0]_midout[16] -+ chanx[1][0]_midout[17] -+ chanx[1][0]_midout[18] -+ chanx[1][0]_midout[19] -+ chanx[1][0]_midout[20] -+ chanx[1][0]_midout[21] -+ chanx[1][0]_midout[22] -+ chanx[1][0]_midout[23] -+ chanx[1][0]_midout[24] -+ chanx[1][0]_midout[25] -+ chanx[1][0]_midout[26] -+ chanx[1][0]_midout[27] -+ chanx[1][0]_midout[28] -+ chanx[1][0]_midout[29] -+ chanx[1][0]_midout[30] -+ chanx[1][0]_midout[31] -+ chanx[1][0]_midout[32] -+ chanx[1][0]_midout[33] -+ chanx[1][0]_midout[34] -+ chanx[1][0]_midout[35] -+ chanx[1][0]_midout[36] -+ chanx[1][0]_midout[37] -+ chanx[1][0]_midout[38] -+ chanx[1][0]_midout[39] -+ chanx[1][0]_midout[40] -+ chanx[1][0]_midout[41] -+ chanx[1][0]_midout[42] -+ chanx[1][0]_midout[43] -+ chanx[1][0]_midout[44] -+ chanx[1][0]_midout[45] -+ chanx[1][0]_midout[46] -+ chanx[1][0]_midout[47] -+ chanx[1][0]_midout[48] -+ chanx[1][0]_midout[49] -+ chanx[1][0]_midout[50] -+ chanx[1][0]_midout[51] -+ chanx[1][0]_midout[52] -+ chanx[1][0]_midout[53] -+ chanx[1][0]_midout[54] -+ chanx[1][0]_midout[55] -+ chanx[1][0]_midout[56] -+ chanx[1][0]_midout[57] -+ chanx[1][0]_midout[58] -+ chanx[1][0]_midout[59] -+ chanx[1][0]_midout[60] -+ chanx[1][0]_midout[61] -+ chanx[1][0]_midout[62] -+ chanx[1][0]_midout[63] -+ chanx[1][0]_midout[64] -+ chanx[1][0]_midout[65] -+ chanx[1][0]_midout[66] -+ chanx[1][0]_midout[67] -+ chanx[1][0]_midout[68] -+ chanx[1][0]_midout[69] -+ chanx[1][0]_midout[70] -+ chanx[1][0]_midout[71] -+ chanx[1][0]_midout[72] -+ chanx[1][0]_midout[73] -+ chanx[1][0]_midout[74] -+ chanx[1][0]_midout[75] -+ chanx[1][0]_midout[76] -+ chanx[1][0]_midout[77] -+ chanx[1][0]_midout[78] -+ chanx[1][0]_midout[79] -+ chanx[1][0]_midout[80] -+ chanx[1][0]_midout[81] -+ chanx[1][0]_midout[82] -+ chanx[1][0]_midout[83] -+ chanx[1][0]_midout[84] -+ chanx[1][0]_midout[85] -+ chanx[1][0]_midout[86] -+ chanx[1][0]_midout[87] -+ chanx[1][0]_midout[88] -+ chanx[1][0]_midout[89] -+ chanx[1][0]_midout[90] -+ chanx[1][0]_midout[91] -+ chanx[1][0]_midout[92] -+ chanx[1][0]_midout[93] -+ chanx[1][0]_midout[94] -+ chanx[1][0]_midout[95] -+ chanx[1][0]_midout[96] -+ chanx[1][0]_midout[97] -+ chanx[1][0]_midout[98] -+ chanx[1][0]_midout[99] -+ gvdd 0 chanx[1][0] -Xchanx[1][1] -+ chanx[1][1]_out[0] -+ chanx[1][1]_in[1] -+ chanx[1][1]_out[2] -+ chanx[1][1]_in[3] -+ chanx[1][1]_out[4] -+ chanx[1][1]_in[5] -+ chanx[1][1]_out[6] -+ chanx[1][1]_in[7] -+ chanx[1][1]_out[8] -+ chanx[1][1]_in[9] -+ chanx[1][1]_out[10] -+ chanx[1][1]_in[11] -+ chanx[1][1]_out[12] -+ chanx[1][1]_in[13] -+ chanx[1][1]_out[14] -+ chanx[1][1]_in[15] -+ chanx[1][1]_out[16] -+ chanx[1][1]_in[17] -+ chanx[1][1]_out[18] -+ chanx[1][1]_in[19] -+ chanx[1][1]_out[20] -+ chanx[1][1]_in[21] -+ chanx[1][1]_out[22] -+ chanx[1][1]_in[23] -+ chanx[1][1]_out[24] -+ chanx[1][1]_in[25] -+ chanx[1][1]_out[26] -+ chanx[1][1]_in[27] -+ chanx[1][1]_out[28] -+ chanx[1][1]_in[29] -+ chanx[1][1]_out[30] -+ chanx[1][1]_in[31] -+ chanx[1][1]_out[32] -+ chanx[1][1]_in[33] -+ chanx[1][1]_out[34] -+ chanx[1][1]_in[35] -+ chanx[1][1]_out[36] -+ chanx[1][1]_in[37] -+ chanx[1][1]_out[38] -+ chanx[1][1]_in[39] -+ chanx[1][1]_out[40] -+ chanx[1][1]_in[41] -+ chanx[1][1]_out[42] -+ chanx[1][1]_in[43] -+ chanx[1][1]_out[44] -+ chanx[1][1]_in[45] -+ chanx[1][1]_out[46] -+ chanx[1][1]_in[47] -+ chanx[1][1]_out[48] -+ chanx[1][1]_in[49] -+ chanx[1][1]_out[50] -+ chanx[1][1]_in[51] -+ chanx[1][1]_out[52] -+ chanx[1][1]_in[53] -+ chanx[1][1]_out[54] -+ chanx[1][1]_in[55] -+ chanx[1][1]_out[56] -+ chanx[1][1]_in[57] -+ chanx[1][1]_out[58] -+ chanx[1][1]_in[59] -+ chanx[1][1]_out[60] -+ chanx[1][1]_in[61] -+ chanx[1][1]_out[62] -+ chanx[1][1]_in[63] -+ chanx[1][1]_out[64] -+ chanx[1][1]_in[65] -+ chanx[1][1]_out[66] -+ chanx[1][1]_in[67] -+ chanx[1][1]_out[68] -+ chanx[1][1]_in[69] -+ chanx[1][1]_out[70] -+ chanx[1][1]_in[71] -+ chanx[1][1]_out[72] -+ chanx[1][1]_in[73] -+ chanx[1][1]_out[74] -+ chanx[1][1]_in[75] -+ chanx[1][1]_out[76] -+ chanx[1][1]_in[77] -+ chanx[1][1]_out[78] -+ chanx[1][1]_in[79] -+ chanx[1][1]_out[80] -+ chanx[1][1]_in[81] -+ chanx[1][1]_out[82] -+ chanx[1][1]_in[83] -+ chanx[1][1]_out[84] -+ chanx[1][1]_in[85] -+ chanx[1][1]_out[86] -+ chanx[1][1]_in[87] -+ chanx[1][1]_out[88] -+ chanx[1][1]_in[89] -+ chanx[1][1]_out[90] -+ chanx[1][1]_in[91] -+ chanx[1][1]_out[92] -+ chanx[1][1]_in[93] -+ chanx[1][1]_out[94] -+ chanx[1][1]_in[95] -+ chanx[1][1]_out[96] -+ chanx[1][1]_in[97] -+ chanx[1][1]_out[98] -+ chanx[1][1]_in[99] -+ chanx[1][1]_in[0] -+ chanx[1][1]_out[1] -+ chanx[1][1]_in[2] -+ chanx[1][1]_out[3] -+ chanx[1][1]_in[4] -+ chanx[1][1]_out[5] -+ chanx[1][1]_in[6] -+ chanx[1][1]_out[7] -+ chanx[1][1]_in[8] -+ chanx[1][1]_out[9] -+ chanx[1][1]_in[10] -+ chanx[1][1]_out[11] -+ chanx[1][1]_in[12] -+ chanx[1][1]_out[13] -+ chanx[1][1]_in[14] -+ chanx[1][1]_out[15] -+ chanx[1][1]_in[16] -+ chanx[1][1]_out[17] -+ chanx[1][1]_in[18] -+ chanx[1][1]_out[19] -+ chanx[1][1]_in[20] -+ chanx[1][1]_out[21] -+ chanx[1][1]_in[22] -+ chanx[1][1]_out[23] -+ chanx[1][1]_in[24] -+ chanx[1][1]_out[25] -+ chanx[1][1]_in[26] -+ chanx[1][1]_out[27] -+ chanx[1][1]_in[28] -+ chanx[1][1]_out[29] -+ chanx[1][1]_in[30] -+ chanx[1][1]_out[31] -+ chanx[1][1]_in[32] -+ chanx[1][1]_out[33] -+ chanx[1][1]_in[34] -+ chanx[1][1]_out[35] -+ chanx[1][1]_in[36] -+ chanx[1][1]_out[37] -+ chanx[1][1]_in[38] -+ chanx[1][1]_out[39] -+ chanx[1][1]_in[40] -+ chanx[1][1]_out[41] -+ chanx[1][1]_in[42] -+ chanx[1][1]_out[43] -+ chanx[1][1]_in[44] -+ chanx[1][1]_out[45] -+ chanx[1][1]_in[46] -+ chanx[1][1]_out[47] -+ chanx[1][1]_in[48] -+ chanx[1][1]_out[49] -+ chanx[1][1]_in[50] -+ chanx[1][1]_out[51] -+ chanx[1][1]_in[52] -+ chanx[1][1]_out[53] -+ chanx[1][1]_in[54] -+ chanx[1][1]_out[55] -+ chanx[1][1]_in[56] -+ chanx[1][1]_out[57] -+ chanx[1][1]_in[58] -+ chanx[1][1]_out[59] -+ chanx[1][1]_in[60] -+ chanx[1][1]_out[61] -+ chanx[1][1]_in[62] -+ chanx[1][1]_out[63] -+ chanx[1][1]_in[64] -+ chanx[1][1]_out[65] -+ chanx[1][1]_in[66] -+ chanx[1][1]_out[67] -+ chanx[1][1]_in[68] -+ chanx[1][1]_out[69] -+ chanx[1][1]_in[70] -+ chanx[1][1]_out[71] -+ chanx[1][1]_in[72] -+ chanx[1][1]_out[73] -+ chanx[1][1]_in[74] -+ chanx[1][1]_out[75] -+ chanx[1][1]_in[76] -+ chanx[1][1]_out[77] -+ chanx[1][1]_in[78] -+ chanx[1][1]_out[79] -+ chanx[1][1]_in[80] -+ chanx[1][1]_out[81] -+ chanx[1][1]_in[82] -+ chanx[1][1]_out[83] -+ chanx[1][1]_in[84] -+ chanx[1][1]_out[85] -+ chanx[1][1]_in[86] -+ chanx[1][1]_out[87] -+ chanx[1][1]_in[88] -+ chanx[1][1]_out[89] -+ chanx[1][1]_in[90] -+ chanx[1][1]_out[91] -+ chanx[1][1]_in[92] -+ chanx[1][1]_out[93] -+ chanx[1][1]_in[94] -+ chanx[1][1]_out[95] -+ chanx[1][1]_in[96] -+ chanx[1][1]_out[97] -+ chanx[1][1]_in[98] -+ chanx[1][1]_out[99] -+ chanx[1][1]_midout[0] -+ chanx[1][1]_midout[1] -+ chanx[1][1]_midout[2] -+ chanx[1][1]_midout[3] -+ chanx[1][1]_midout[4] -+ chanx[1][1]_midout[5] -+ chanx[1][1]_midout[6] -+ chanx[1][1]_midout[7] -+ chanx[1][1]_midout[8] -+ chanx[1][1]_midout[9] -+ chanx[1][1]_midout[10] -+ chanx[1][1]_midout[11] -+ chanx[1][1]_midout[12] -+ chanx[1][1]_midout[13] -+ chanx[1][1]_midout[14] -+ chanx[1][1]_midout[15] -+ chanx[1][1]_midout[16] -+ chanx[1][1]_midout[17] -+ chanx[1][1]_midout[18] -+ chanx[1][1]_midout[19] -+ chanx[1][1]_midout[20] -+ chanx[1][1]_midout[21] -+ chanx[1][1]_midout[22] -+ chanx[1][1]_midout[23] -+ chanx[1][1]_midout[24] -+ chanx[1][1]_midout[25] -+ chanx[1][1]_midout[26] -+ chanx[1][1]_midout[27] -+ chanx[1][1]_midout[28] -+ chanx[1][1]_midout[29] -+ chanx[1][1]_midout[30] -+ chanx[1][1]_midout[31] -+ chanx[1][1]_midout[32] -+ chanx[1][1]_midout[33] -+ chanx[1][1]_midout[34] -+ chanx[1][1]_midout[35] -+ chanx[1][1]_midout[36] -+ chanx[1][1]_midout[37] -+ chanx[1][1]_midout[38] -+ chanx[1][1]_midout[39] -+ chanx[1][1]_midout[40] -+ chanx[1][1]_midout[41] -+ chanx[1][1]_midout[42] -+ chanx[1][1]_midout[43] -+ chanx[1][1]_midout[44] -+ chanx[1][1]_midout[45] -+ chanx[1][1]_midout[46] -+ chanx[1][1]_midout[47] -+ chanx[1][1]_midout[48] -+ chanx[1][1]_midout[49] -+ chanx[1][1]_midout[50] -+ chanx[1][1]_midout[51] -+ chanx[1][1]_midout[52] -+ chanx[1][1]_midout[53] -+ chanx[1][1]_midout[54] -+ chanx[1][1]_midout[55] -+ chanx[1][1]_midout[56] -+ chanx[1][1]_midout[57] -+ chanx[1][1]_midout[58] -+ chanx[1][1]_midout[59] -+ chanx[1][1]_midout[60] -+ chanx[1][1]_midout[61] -+ chanx[1][1]_midout[62] -+ chanx[1][1]_midout[63] -+ chanx[1][1]_midout[64] -+ chanx[1][1]_midout[65] -+ chanx[1][1]_midout[66] -+ chanx[1][1]_midout[67] -+ chanx[1][1]_midout[68] -+ chanx[1][1]_midout[69] -+ chanx[1][1]_midout[70] -+ chanx[1][1]_midout[71] -+ chanx[1][1]_midout[72] -+ chanx[1][1]_midout[73] -+ chanx[1][1]_midout[74] -+ chanx[1][1]_midout[75] -+ chanx[1][1]_midout[76] -+ chanx[1][1]_midout[77] -+ chanx[1][1]_midout[78] -+ chanx[1][1]_midout[79] -+ chanx[1][1]_midout[80] -+ chanx[1][1]_midout[81] -+ chanx[1][1]_midout[82] -+ chanx[1][1]_midout[83] -+ chanx[1][1]_midout[84] -+ chanx[1][1]_midout[85] -+ chanx[1][1]_midout[86] -+ chanx[1][1]_midout[87] -+ chanx[1][1]_midout[88] -+ chanx[1][1]_midout[89] -+ chanx[1][1]_midout[90] -+ chanx[1][1]_midout[91] -+ chanx[1][1]_midout[92] -+ chanx[1][1]_midout[93] -+ chanx[1][1]_midout[94] -+ chanx[1][1]_midout[95] -+ chanx[1][1]_midout[96] -+ chanx[1][1]_midout[97] -+ chanx[1][1]_midout[98] -+ chanx[1][1]_midout[99] -+ gvdd 0 chanx[1][1] -Xchany[0][1] -+ chany[0][1]_out[0] -+ chany[0][1]_in[1] -+ chany[0][1]_out[2] -+ chany[0][1]_in[3] -+ chany[0][1]_out[4] -+ chany[0][1]_in[5] -+ chany[0][1]_out[6] -+ chany[0][1]_in[7] -+ chany[0][1]_out[8] -+ chany[0][1]_in[9] -+ chany[0][1]_out[10] -+ chany[0][1]_in[11] -+ chany[0][1]_out[12] -+ chany[0][1]_in[13] -+ chany[0][1]_out[14] -+ chany[0][1]_in[15] -+ chany[0][1]_out[16] -+ chany[0][1]_in[17] -+ chany[0][1]_out[18] -+ chany[0][1]_in[19] -+ chany[0][1]_out[20] -+ chany[0][1]_in[21] -+ chany[0][1]_out[22] -+ chany[0][1]_in[23] -+ chany[0][1]_out[24] -+ chany[0][1]_in[25] -+ chany[0][1]_out[26] -+ chany[0][1]_in[27] -+ chany[0][1]_out[28] -+ chany[0][1]_in[29] -+ chany[0][1]_out[30] -+ chany[0][1]_in[31] -+ chany[0][1]_out[32] -+ chany[0][1]_in[33] -+ chany[0][1]_out[34] -+ chany[0][1]_in[35] -+ chany[0][1]_out[36] -+ chany[0][1]_in[37] -+ chany[0][1]_out[38] -+ chany[0][1]_in[39] -+ chany[0][1]_out[40] -+ chany[0][1]_in[41] -+ chany[0][1]_out[42] -+ chany[0][1]_in[43] -+ chany[0][1]_out[44] -+ chany[0][1]_in[45] -+ chany[0][1]_out[46] -+ chany[0][1]_in[47] -+ chany[0][1]_out[48] -+ chany[0][1]_in[49] -+ chany[0][1]_out[50] -+ chany[0][1]_in[51] -+ chany[0][1]_out[52] -+ chany[0][1]_in[53] -+ chany[0][1]_out[54] -+ chany[0][1]_in[55] -+ chany[0][1]_out[56] -+ chany[0][1]_in[57] -+ chany[0][1]_out[58] -+ chany[0][1]_in[59] -+ chany[0][1]_out[60] -+ chany[0][1]_in[61] -+ chany[0][1]_out[62] -+ chany[0][1]_in[63] -+ chany[0][1]_out[64] -+ chany[0][1]_in[65] -+ chany[0][1]_out[66] -+ chany[0][1]_in[67] -+ chany[0][1]_out[68] -+ chany[0][1]_in[69] -+ chany[0][1]_out[70] -+ chany[0][1]_in[71] -+ chany[0][1]_out[72] -+ chany[0][1]_in[73] -+ chany[0][1]_out[74] -+ chany[0][1]_in[75] -+ chany[0][1]_out[76] -+ chany[0][1]_in[77] -+ chany[0][1]_out[78] -+ chany[0][1]_in[79] -+ chany[0][1]_out[80] -+ chany[0][1]_in[81] -+ chany[0][1]_out[82] -+ chany[0][1]_in[83] -+ chany[0][1]_out[84] -+ chany[0][1]_in[85] -+ chany[0][1]_out[86] -+ chany[0][1]_in[87] -+ chany[0][1]_out[88] -+ chany[0][1]_in[89] -+ chany[0][1]_out[90] -+ chany[0][1]_in[91] -+ chany[0][1]_out[92] -+ chany[0][1]_in[93] -+ chany[0][1]_out[94] -+ chany[0][1]_in[95] -+ chany[0][1]_out[96] -+ chany[0][1]_in[97] -+ chany[0][1]_out[98] -+ chany[0][1]_in[99] -+ chany[0][1]_in[0] -+ chany[0][1]_out[1] -+ chany[0][1]_in[2] -+ chany[0][1]_out[3] -+ chany[0][1]_in[4] -+ chany[0][1]_out[5] -+ chany[0][1]_in[6] -+ chany[0][1]_out[7] -+ chany[0][1]_in[8] -+ chany[0][1]_out[9] -+ chany[0][1]_in[10] -+ chany[0][1]_out[11] -+ chany[0][1]_in[12] -+ chany[0][1]_out[13] -+ chany[0][1]_in[14] -+ chany[0][1]_out[15] -+ chany[0][1]_in[16] -+ chany[0][1]_out[17] -+ chany[0][1]_in[18] -+ chany[0][1]_out[19] -+ chany[0][1]_in[20] -+ chany[0][1]_out[21] -+ chany[0][1]_in[22] -+ chany[0][1]_out[23] -+ chany[0][1]_in[24] -+ chany[0][1]_out[25] -+ chany[0][1]_in[26] -+ chany[0][1]_out[27] -+ chany[0][1]_in[28] -+ chany[0][1]_out[29] -+ chany[0][1]_in[30] -+ chany[0][1]_out[31] -+ chany[0][1]_in[32] -+ chany[0][1]_out[33] -+ chany[0][1]_in[34] -+ chany[0][1]_out[35] -+ chany[0][1]_in[36] -+ chany[0][1]_out[37] -+ chany[0][1]_in[38] -+ chany[0][1]_out[39] -+ chany[0][1]_in[40] -+ chany[0][1]_out[41] -+ chany[0][1]_in[42] -+ chany[0][1]_out[43] -+ chany[0][1]_in[44] -+ chany[0][1]_out[45] -+ chany[0][1]_in[46] -+ chany[0][1]_out[47] -+ chany[0][1]_in[48] -+ chany[0][1]_out[49] -+ chany[0][1]_in[50] -+ chany[0][1]_out[51] -+ chany[0][1]_in[52] -+ chany[0][1]_out[53] -+ chany[0][1]_in[54] -+ chany[0][1]_out[55] -+ chany[0][1]_in[56] -+ chany[0][1]_out[57] -+ chany[0][1]_in[58] -+ chany[0][1]_out[59] -+ chany[0][1]_in[60] -+ chany[0][1]_out[61] -+ chany[0][1]_in[62] -+ chany[0][1]_out[63] -+ chany[0][1]_in[64] -+ chany[0][1]_out[65] -+ chany[0][1]_in[66] -+ chany[0][1]_out[67] -+ chany[0][1]_in[68] -+ chany[0][1]_out[69] -+ chany[0][1]_in[70] -+ chany[0][1]_out[71] -+ chany[0][1]_in[72] -+ chany[0][1]_out[73] -+ chany[0][1]_in[74] -+ chany[0][1]_out[75] -+ chany[0][1]_in[76] -+ chany[0][1]_out[77] -+ chany[0][1]_in[78] -+ chany[0][1]_out[79] -+ chany[0][1]_in[80] -+ chany[0][1]_out[81] -+ chany[0][1]_in[82] -+ chany[0][1]_out[83] -+ chany[0][1]_in[84] -+ chany[0][1]_out[85] -+ chany[0][1]_in[86] -+ chany[0][1]_out[87] -+ chany[0][1]_in[88] -+ chany[0][1]_out[89] -+ chany[0][1]_in[90] -+ chany[0][1]_out[91] -+ chany[0][1]_in[92] -+ chany[0][1]_out[93] -+ chany[0][1]_in[94] -+ chany[0][1]_out[95] -+ chany[0][1]_in[96] -+ chany[0][1]_out[97] -+ chany[0][1]_in[98] -+ chany[0][1]_out[99] -+ chany[0][1]_midout[0] -+ chany[0][1]_midout[1] -+ chany[0][1]_midout[2] -+ chany[0][1]_midout[3] -+ chany[0][1]_midout[4] -+ chany[0][1]_midout[5] -+ chany[0][1]_midout[6] -+ chany[0][1]_midout[7] -+ chany[0][1]_midout[8] -+ chany[0][1]_midout[9] -+ chany[0][1]_midout[10] -+ chany[0][1]_midout[11] -+ chany[0][1]_midout[12] -+ chany[0][1]_midout[13] -+ chany[0][1]_midout[14] -+ chany[0][1]_midout[15] -+ chany[0][1]_midout[16] -+ chany[0][1]_midout[17] -+ chany[0][1]_midout[18] -+ chany[0][1]_midout[19] -+ chany[0][1]_midout[20] -+ chany[0][1]_midout[21] -+ chany[0][1]_midout[22] -+ chany[0][1]_midout[23] -+ chany[0][1]_midout[24] -+ chany[0][1]_midout[25] -+ chany[0][1]_midout[26] -+ chany[0][1]_midout[27] -+ chany[0][1]_midout[28] -+ chany[0][1]_midout[29] -+ chany[0][1]_midout[30] -+ chany[0][1]_midout[31] -+ chany[0][1]_midout[32] -+ chany[0][1]_midout[33] -+ chany[0][1]_midout[34] -+ chany[0][1]_midout[35] -+ chany[0][1]_midout[36] -+ chany[0][1]_midout[37] -+ chany[0][1]_midout[38] -+ chany[0][1]_midout[39] -+ chany[0][1]_midout[40] -+ chany[0][1]_midout[41] -+ chany[0][1]_midout[42] -+ chany[0][1]_midout[43] -+ chany[0][1]_midout[44] -+ chany[0][1]_midout[45] -+ chany[0][1]_midout[46] -+ chany[0][1]_midout[47] -+ chany[0][1]_midout[48] -+ chany[0][1]_midout[49] -+ chany[0][1]_midout[50] -+ chany[0][1]_midout[51] -+ chany[0][1]_midout[52] -+ chany[0][1]_midout[53] -+ chany[0][1]_midout[54] -+ chany[0][1]_midout[55] -+ chany[0][1]_midout[56] -+ chany[0][1]_midout[57] -+ chany[0][1]_midout[58] -+ chany[0][1]_midout[59] -+ chany[0][1]_midout[60] -+ chany[0][1]_midout[61] -+ chany[0][1]_midout[62] -+ chany[0][1]_midout[63] -+ chany[0][1]_midout[64] -+ chany[0][1]_midout[65] -+ chany[0][1]_midout[66] -+ chany[0][1]_midout[67] -+ chany[0][1]_midout[68] -+ chany[0][1]_midout[69] -+ chany[0][1]_midout[70] -+ chany[0][1]_midout[71] -+ chany[0][1]_midout[72] -+ chany[0][1]_midout[73] -+ chany[0][1]_midout[74] -+ chany[0][1]_midout[75] -+ chany[0][1]_midout[76] -+ chany[0][1]_midout[77] -+ chany[0][1]_midout[78] -+ chany[0][1]_midout[79] -+ chany[0][1]_midout[80] -+ chany[0][1]_midout[81] -+ chany[0][1]_midout[82] -+ chany[0][1]_midout[83] -+ chany[0][1]_midout[84] -+ chany[0][1]_midout[85] -+ chany[0][1]_midout[86] -+ chany[0][1]_midout[87] -+ chany[0][1]_midout[88] -+ chany[0][1]_midout[89] -+ chany[0][1]_midout[90] -+ chany[0][1]_midout[91] -+ chany[0][1]_midout[92] -+ chany[0][1]_midout[93] -+ chany[0][1]_midout[94] -+ chany[0][1]_midout[95] -+ chany[0][1]_midout[96] -+ chany[0][1]_midout[97] -+ chany[0][1]_midout[98] -+ chany[0][1]_midout[99] -+ gvdd 0 chany[0][1] -Xchany[1][1] -+ chany[1][1]_out[0] -+ chany[1][1]_in[1] -+ chany[1][1]_out[2] -+ chany[1][1]_in[3] -+ chany[1][1]_out[4] -+ chany[1][1]_in[5] -+ chany[1][1]_out[6] -+ chany[1][1]_in[7] -+ chany[1][1]_out[8] -+ chany[1][1]_in[9] -+ chany[1][1]_out[10] -+ chany[1][1]_in[11] -+ chany[1][1]_out[12] -+ chany[1][1]_in[13] -+ chany[1][1]_out[14] -+ chany[1][1]_in[15] -+ chany[1][1]_out[16] -+ chany[1][1]_in[17] -+ chany[1][1]_out[18] -+ chany[1][1]_in[19] -+ chany[1][1]_out[20] -+ chany[1][1]_in[21] -+ chany[1][1]_out[22] -+ chany[1][1]_in[23] -+ chany[1][1]_out[24] -+ chany[1][1]_in[25] -+ chany[1][1]_out[26] -+ chany[1][1]_in[27] -+ chany[1][1]_out[28] -+ chany[1][1]_in[29] -+ chany[1][1]_out[30] -+ chany[1][1]_in[31] -+ chany[1][1]_out[32] -+ chany[1][1]_in[33] -+ chany[1][1]_out[34] -+ chany[1][1]_in[35] -+ chany[1][1]_out[36] -+ chany[1][1]_in[37] -+ chany[1][1]_out[38] -+ chany[1][1]_in[39] -+ chany[1][1]_out[40] -+ chany[1][1]_in[41] -+ chany[1][1]_out[42] -+ chany[1][1]_in[43] -+ chany[1][1]_out[44] -+ chany[1][1]_in[45] -+ chany[1][1]_out[46] -+ chany[1][1]_in[47] -+ chany[1][1]_out[48] -+ chany[1][1]_in[49] -+ chany[1][1]_out[50] -+ chany[1][1]_in[51] -+ chany[1][1]_out[52] -+ chany[1][1]_in[53] -+ chany[1][1]_out[54] -+ chany[1][1]_in[55] -+ chany[1][1]_out[56] -+ chany[1][1]_in[57] -+ chany[1][1]_out[58] -+ chany[1][1]_in[59] -+ chany[1][1]_out[60] -+ chany[1][1]_in[61] -+ chany[1][1]_out[62] -+ chany[1][1]_in[63] -+ chany[1][1]_out[64] -+ chany[1][1]_in[65] -+ chany[1][1]_out[66] -+ chany[1][1]_in[67] -+ chany[1][1]_out[68] -+ chany[1][1]_in[69] -+ chany[1][1]_out[70] -+ chany[1][1]_in[71] -+ chany[1][1]_out[72] -+ chany[1][1]_in[73] -+ chany[1][1]_out[74] -+ chany[1][1]_in[75] -+ chany[1][1]_out[76] -+ chany[1][1]_in[77] -+ chany[1][1]_out[78] -+ chany[1][1]_in[79] -+ chany[1][1]_out[80] -+ chany[1][1]_in[81] -+ chany[1][1]_out[82] -+ chany[1][1]_in[83] -+ chany[1][1]_out[84] -+ chany[1][1]_in[85] -+ chany[1][1]_out[86] -+ chany[1][1]_in[87] -+ chany[1][1]_out[88] -+ chany[1][1]_in[89] -+ chany[1][1]_out[90] -+ chany[1][1]_in[91] -+ chany[1][1]_out[92] -+ chany[1][1]_in[93] -+ chany[1][1]_out[94] -+ chany[1][1]_in[95] -+ chany[1][1]_out[96] -+ chany[1][1]_in[97] -+ chany[1][1]_out[98] -+ chany[1][1]_in[99] -+ chany[1][1]_in[0] -+ chany[1][1]_out[1] -+ chany[1][1]_in[2] -+ chany[1][1]_out[3] -+ chany[1][1]_in[4] -+ chany[1][1]_out[5] -+ chany[1][1]_in[6] -+ chany[1][1]_out[7] -+ chany[1][1]_in[8] -+ chany[1][1]_out[9] -+ chany[1][1]_in[10] -+ chany[1][1]_out[11] -+ chany[1][1]_in[12] -+ chany[1][1]_out[13] -+ chany[1][1]_in[14] -+ chany[1][1]_out[15] -+ chany[1][1]_in[16] -+ chany[1][1]_out[17] -+ chany[1][1]_in[18] -+ chany[1][1]_out[19] -+ chany[1][1]_in[20] -+ chany[1][1]_out[21] -+ chany[1][1]_in[22] -+ chany[1][1]_out[23] -+ chany[1][1]_in[24] -+ chany[1][1]_out[25] -+ chany[1][1]_in[26] -+ chany[1][1]_out[27] -+ chany[1][1]_in[28] -+ chany[1][1]_out[29] -+ chany[1][1]_in[30] -+ chany[1][1]_out[31] -+ chany[1][1]_in[32] -+ chany[1][1]_out[33] -+ chany[1][1]_in[34] -+ chany[1][1]_out[35] -+ chany[1][1]_in[36] -+ chany[1][1]_out[37] -+ chany[1][1]_in[38] -+ chany[1][1]_out[39] -+ chany[1][1]_in[40] -+ chany[1][1]_out[41] -+ chany[1][1]_in[42] -+ chany[1][1]_out[43] -+ chany[1][1]_in[44] -+ chany[1][1]_out[45] -+ chany[1][1]_in[46] -+ chany[1][1]_out[47] -+ chany[1][1]_in[48] -+ chany[1][1]_out[49] -+ chany[1][1]_in[50] -+ chany[1][1]_out[51] -+ chany[1][1]_in[52] -+ chany[1][1]_out[53] -+ chany[1][1]_in[54] -+ chany[1][1]_out[55] -+ chany[1][1]_in[56] -+ chany[1][1]_out[57] -+ chany[1][1]_in[58] -+ chany[1][1]_out[59] -+ chany[1][1]_in[60] -+ chany[1][1]_out[61] -+ chany[1][1]_in[62] -+ chany[1][1]_out[63] -+ chany[1][1]_in[64] -+ chany[1][1]_out[65] -+ chany[1][1]_in[66] -+ chany[1][1]_out[67] -+ chany[1][1]_in[68] -+ chany[1][1]_out[69] -+ chany[1][1]_in[70] -+ chany[1][1]_out[71] -+ chany[1][1]_in[72] -+ chany[1][1]_out[73] -+ chany[1][1]_in[74] -+ chany[1][1]_out[75] -+ chany[1][1]_in[76] -+ chany[1][1]_out[77] -+ chany[1][1]_in[78] -+ chany[1][1]_out[79] -+ chany[1][1]_in[80] -+ chany[1][1]_out[81] -+ chany[1][1]_in[82] -+ chany[1][1]_out[83] -+ chany[1][1]_in[84] -+ chany[1][1]_out[85] -+ chany[1][1]_in[86] -+ chany[1][1]_out[87] -+ chany[1][1]_in[88] -+ chany[1][1]_out[89] -+ chany[1][1]_in[90] -+ chany[1][1]_out[91] -+ chany[1][1]_in[92] -+ chany[1][1]_out[93] -+ chany[1][1]_in[94] -+ chany[1][1]_out[95] -+ chany[1][1]_in[96] -+ chany[1][1]_out[97] -+ chany[1][1]_in[98] -+ chany[1][1]_out[99] -+ chany[1][1]_midout[0] -+ chany[1][1]_midout[1] -+ chany[1][1]_midout[2] -+ chany[1][1]_midout[3] -+ chany[1][1]_midout[4] -+ chany[1][1]_midout[5] -+ chany[1][1]_midout[6] -+ chany[1][1]_midout[7] -+ chany[1][1]_midout[8] -+ chany[1][1]_midout[9] -+ chany[1][1]_midout[10] -+ chany[1][1]_midout[11] -+ chany[1][1]_midout[12] -+ chany[1][1]_midout[13] -+ chany[1][1]_midout[14] -+ chany[1][1]_midout[15] -+ chany[1][1]_midout[16] -+ chany[1][1]_midout[17] -+ chany[1][1]_midout[18] -+ chany[1][1]_midout[19] -+ chany[1][1]_midout[20] -+ chany[1][1]_midout[21] -+ chany[1][1]_midout[22] -+ chany[1][1]_midout[23] -+ chany[1][1]_midout[24] -+ chany[1][1]_midout[25] -+ chany[1][1]_midout[26] -+ chany[1][1]_midout[27] -+ chany[1][1]_midout[28] -+ chany[1][1]_midout[29] -+ chany[1][1]_midout[30] -+ chany[1][1]_midout[31] -+ chany[1][1]_midout[32] -+ chany[1][1]_midout[33] -+ chany[1][1]_midout[34] -+ chany[1][1]_midout[35] -+ chany[1][1]_midout[36] -+ chany[1][1]_midout[37] -+ chany[1][1]_midout[38] -+ chany[1][1]_midout[39] -+ chany[1][1]_midout[40] -+ chany[1][1]_midout[41] -+ chany[1][1]_midout[42] -+ chany[1][1]_midout[43] -+ chany[1][1]_midout[44] -+ chany[1][1]_midout[45] -+ chany[1][1]_midout[46] -+ chany[1][1]_midout[47] -+ chany[1][1]_midout[48] -+ chany[1][1]_midout[49] -+ chany[1][1]_midout[50] -+ chany[1][1]_midout[51] -+ chany[1][1]_midout[52] -+ chany[1][1]_midout[53] -+ chany[1][1]_midout[54] -+ chany[1][1]_midout[55] -+ chany[1][1]_midout[56] -+ chany[1][1]_midout[57] -+ chany[1][1]_midout[58] -+ chany[1][1]_midout[59] -+ chany[1][1]_midout[60] -+ chany[1][1]_midout[61] -+ chany[1][1]_midout[62] -+ chany[1][1]_midout[63] -+ chany[1][1]_midout[64] -+ chany[1][1]_midout[65] -+ chany[1][1]_midout[66] -+ chany[1][1]_midout[67] -+ chany[1][1]_midout[68] -+ chany[1][1]_midout[69] -+ chany[1][1]_midout[70] -+ chany[1][1]_midout[71] -+ chany[1][1]_midout[72] -+ chany[1][1]_midout[73] -+ chany[1][1]_midout[74] -+ chany[1][1]_midout[75] -+ chany[1][1]_midout[76] -+ chany[1][1]_midout[77] -+ chany[1][1]_midout[78] -+ chany[1][1]_midout[79] -+ chany[1][1]_midout[80] -+ chany[1][1]_midout[81] -+ chany[1][1]_midout[82] -+ chany[1][1]_midout[83] -+ chany[1][1]_midout[84] -+ chany[1][1]_midout[85] -+ chany[1][1]_midout[86] -+ chany[1][1]_midout[87] -+ chany[1][1]_midout[88] -+ chany[1][1]_midout[89] -+ chany[1][1]_midout[90] -+ chany[1][1]_midout[91] -+ chany[1][1]_midout[92] -+ chany[1][1]_midout[93] -+ chany[1][1]_midout[94] -+ chany[1][1]_midout[95] -+ chany[1][1]_midout[96] -+ chany[1][1]_midout[97] -+ chany[1][1]_midout[98] -+ chany[1][1]_midout[99] -+ gvdd 0 chany[1][1] -Xcbx[1][0] -+ chanx[1][0]_midout[0] -+ chanx[1][0]_midout[1] -+ chanx[1][0]_midout[2] -+ chanx[1][0]_midout[3] -+ chanx[1][0]_midout[4] -+ chanx[1][0]_midout[5] -+ chanx[1][0]_midout[6] -+ chanx[1][0]_midout[7] -+ chanx[1][0]_midout[8] -+ chanx[1][0]_midout[9] -+ chanx[1][0]_midout[10] -+ chanx[1][0]_midout[11] -+ chanx[1][0]_midout[12] -+ chanx[1][0]_midout[13] -+ chanx[1][0]_midout[14] -+ chanx[1][0]_midout[15] -+ chanx[1][0]_midout[16] -+ chanx[1][0]_midout[17] -+ chanx[1][0]_midout[18] -+ chanx[1][0]_midout[19] -+ chanx[1][0]_midout[20] -+ chanx[1][0]_midout[21] -+ chanx[1][0]_midout[22] -+ chanx[1][0]_midout[23] -+ chanx[1][0]_midout[24] -+ chanx[1][0]_midout[25] -+ chanx[1][0]_midout[26] -+ chanx[1][0]_midout[27] -+ chanx[1][0]_midout[28] -+ chanx[1][0]_midout[29] -+ chanx[1][0]_midout[30] -+ chanx[1][0]_midout[31] -+ chanx[1][0]_midout[32] -+ chanx[1][0]_midout[33] -+ chanx[1][0]_midout[34] -+ chanx[1][0]_midout[35] -+ chanx[1][0]_midout[36] -+ chanx[1][0]_midout[37] -+ chanx[1][0]_midout[38] -+ chanx[1][0]_midout[39] -+ chanx[1][0]_midout[40] -+ chanx[1][0]_midout[41] -+ chanx[1][0]_midout[42] -+ chanx[1][0]_midout[43] -+ chanx[1][0]_midout[44] -+ chanx[1][0]_midout[45] -+ chanx[1][0]_midout[46] -+ chanx[1][0]_midout[47] -+ chanx[1][0]_midout[48] -+ chanx[1][0]_midout[49] -+ chanx[1][0]_midout[50] -+ chanx[1][0]_midout[51] -+ chanx[1][0]_midout[52] -+ chanx[1][0]_midout[53] -+ chanx[1][0]_midout[54] -+ chanx[1][0]_midout[55] -+ chanx[1][0]_midout[56] -+ chanx[1][0]_midout[57] -+ chanx[1][0]_midout[58] -+ chanx[1][0]_midout[59] -+ chanx[1][0]_midout[60] -+ chanx[1][0]_midout[61] -+ chanx[1][0]_midout[62] -+ chanx[1][0]_midout[63] -+ chanx[1][0]_midout[64] -+ chanx[1][0]_midout[65] -+ chanx[1][0]_midout[66] -+ chanx[1][0]_midout[67] -+ chanx[1][0]_midout[68] -+ chanx[1][0]_midout[69] -+ chanx[1][0]_midout[70] -+ chanx[1][0]_midout[71] -+ chanx[1][0]_midout[72] -+ chanx[1][0]_midout[73] -+ chanx[1][0]_midout[74] -+ chanx[1][0]_midout[75] -+ chanx[1][0]_midout[76] -+ chanx[1][0]_midout[77] -+ chanx[1][0]_midout[78] -+ chanx[1][0]_midout[79] -+ chanx[1][0]_midout[80] -+ chanx[1][0]_midout[81] -+ chanx[1][0]_midout[82] -+ chanx[1][0]_midout[83] -+ chanx[1][0]_midout[84] -+ chanx[1][0]_midout[85] -+ chanx[1][0]_midout[86] -+ chanx[1][0]_midout[87] -+ chanx[1][0]_midout[88] -+ chanx[1][0]_midout[89] -+ chanx[1][0]_midout[90] -+ chanx[1][0]_midout[91] -+ chanx[1][0]_midout[92] -+ chanx[1][0]_midout[93] -+ chanx[1][0]_midout[94] -+ chanx[1][0]_midout[95] -+ chanx[1][0]_midout[96] -+ chanx[1][0]_midout[97] -+ chanx[1][0]_midout[98] -+ chanx[1][0]_midout[99] -+ grid[1][1]_pin[0][2][2] -+ grid[1][1]_pin[0][2][6] -+ grid[1][1]_pin[0][2][10] -+ grid[1][1]_pin[0][2][14] -+ grid[1][1]_pin[0][2][18] -+ grid[1][1]_pin[0][2][22] -+ grid[1][1]_pin[0][2][26] -+ grid[1][1]_pin[0][2][30] -+ grid[1][1]_pin[0][2][34] -+ grid[1][1]_pin[0][2][38] -+ grid[1][1]_pin[0][2][50] -+ grid[1][0]_pin[0][0][0] -+ grid[1][0]_pin[0][0][2] -+ grid[1][0]_pin[0][0][4] -+ grid[1][0]_pin[0][0][6] -+ grid[1][0]_pin[0][0][8] -+ grid[1][0]_pin[0][0][10] -+ grid[1][0]_pin[0][0][12] -+ grid[1][0]_pin[0][0][14] -+ gvdd_cbx[1][0] 0 cbx[1][0] -Xcbx[1][1] -+ chanx[1][1]_midout[0] -+ chanx[1][1]_midout[1] -+ chanx[1][1]_midout[2] -+ chanx[1][1]_midout[3] -+ chanx[1][1]_midout[4] -+ chanx[1][1]_midout[5] -+ chanx[1][1]_midout[6] -+ chanx[1][1]_midout[7] -+ chanx[1][1]_midout[8] -+ chanx[1][1]_midout[9] -+ chanx[1][1]_midout[10] -+ chanx[1][1]_midout[11] -+ chanx[1][1]_midout[12] -+ chanx[1][1]_midout[13] -+ chanx[1][1]_midout[14] -+ chanx[1][1]_midout[15] -+ chanx[1][1]_midout[16] -+ chanx[1][1]_midout[17] -+ chanx[1][1]_midout[18] -+ chanx[1][1]_midout[19] -+ chanx[1][1]_midout[20] -+ chanx[1][1]_midout[21] -+ chanx[1][1]_midout[22] -+ chanx[1][1]_midout[23] -+ chanx[1][1]_midout[24] -+ chanx[1][1]_midout[25] -+ chanx[1][1]_midout[26] -+ chanx[1][1]_midout[27] -+ chanx[1][1]_midout[28] -+ chanx[1][1]_midout[29] -+ chanx[1][1]_midout[30] -+ chanx[1][1]_midout[31] -+ chanx[1][1]_midout[32] -+ chanx[1][1]_midout[33] -+ chanx[1][1]_midout[34] -+ chanx[1][1]_midout[35] -+ chanx[1][1]_midout[36] -+ chanx[1][1]_midout[37] -+ chanx[1][1]_midout[38] -+ chanx[1][1]_midout[39] -+ chanx[1][1]_midout[40] -+ chanx[1][1]_midout[41] -+ chanx[1][1]_midout[42] -+ chanx[1][1]_midout[43] -+ chanx[1][1]_midout[44] -+ chanx[1][1]_midout[45] -+ chanx[1][1]_midout[46] -+ chanx[1][1]_midout[47] -+ chanx[1][1]_midout[48] -+ chanx[1][1]_midout[49] -+ chanx[1][1]_midout[50] -+ chanx[1][1]_midout[51] -+ chanx[1][1]_midout[52] -+ chanx[1][1]_midout[53] -+ chanx[1][1]_midout[54] -+ chanx[1][1]_midout[55] -+ chanx[1][1]_midout[56] -+ chanx[1][1]_midout[57] -+ chanx[1][1]_midout[58] -+ chanx[1][1]_midout[59] -+ chanx[1][1]_midout[60] -+ chanx[1][1]_midout[61] -+ chanx[1][1]_midout[62] -+ chanx[1][1]_midout[63] -+ chanx[1][1]_midout[64] -+ chanx[1][1]_midout[65] -+ chanx[1][1]_midout[66] -+ chanx[1][1]_midout[67] -+ chanx[1][1]_midout[68] -+ chanx[1][1]_midout[69] -+ chanx[1][1]_midout[70] -+ chanx[1][1]_midout[71] -+ chanx[1][1]_midout[72] -+ chanx[1][1]_midout[73] -+ chanx[1][1]_midout[74] -+ chanx[1][1]_midout[75] -+ chanx[1][1]_midout[76] -+ chanx[1][1]_midout[77] -+ chanx[1][1]_midout[78] -+ chanx[1][1]_midout[79] -+ chanx[1][1]_midout[80] -+ chanx[1][1]_midout[81] -+ chanx[1][1]_midout[82] -+ chanx[1][1]_midout[83] -+ chanx[1][1]_midout[84] -+ chanx[1][1]_midout[85] -+ chanx[1][1]_midout[86] -+ chanx[1][1]_midout[87] -+ chanx[1][1]_midout[88] -+ chanx[1][1]_midout[89] -+ chanx[1][1]_midout[90] -+ chanx[1][1]_midout[91] -+ chanx[1][1]_midout[92] -+ chanx[1][1]_midout[93] -+ chanx[1][1]_midout[94] -+ chanx[1][1]_midout[95] -+ chanx[1][1]_midout[96] -+ chanx[1][1]_midout[97] -+ chanx[1][1]_midout[98] -+ chanx[1][1]_midout[99] -+ grid[1][2]_pin[0][2][0] -+ grid[1][2]_pin[0][2][2] -+ grid[1][2]_pin[0][2][4] -+ grid[1][2]_pin[0][2][6] -+ grid[1][2]_pin[0][2][8] -+ grid[1][2]_pin[0][2][10] -+ grid[1][2]_pin[0][2][12] -+ grid[1][2]_pin[0][2][14] -+ grid[1][1]_pin[0][0][0] -+ grid[1][1]_pin[0][0][4] -+ grid[1][1]_pin[0][0][8] -+ grid[1][1]_pin[0][0][12] -+ grid[1][1]_pin[0][0][16] -+ grid[1][1]_pin[0][0][20] -+ grid[1][1]_pin[0][0][24] -+ grid[1][1]_pin[0][0][28] -+ grid[1][1]_pin[0][0][32] -+ grid[1][1]_pin[0][0][36] -+ gvdd_cbx[1][1] 0 cbx[1][1] -Xcby[0][1] -+ chany[0][1]_midout[0] -+ chany[0][1]_midout[1] -+ chany[0][1]_midout[2] -+ chany[0][1]_midout[3] -+ chany[0][1]_midout[4] -+ chany[0][1]_midout[5] -+ chany[0][1]_midout[6] -+ chany[0][1]_midout[7] -+ chany[0][1]_midout[8] -+ chany[0][1]_midout[9] -+ chany[0][1]_midout[10] -+ chany[0][1]_midout[11] -+ chany[0][1]_midout[12] -+ chany[0][1]_midout[13] -+ chany[0][1]_midout[14] -+ chany[0][1]_midout[15] -+ chany[0][1]_midout[16] -+ chany[0][1]_midout[17] -+ chany[0][1]_midout[18] -+ chany[0][1]_midout[19] -+ chany[0][1]_midout[20] -+ chany[0][1]_midout[21] -+ chany[0][1]_midout[22] -+ chany[0][1]_midout[23] -+ chany[0][1]_midout[24] -+ chany[0][1]_midout[25] -+ chany[0][1]_midout[26] -+ chany[0][1]_midout[27] -+ chany[0][1]_midout[28] -+ chany[0][1]_midout[29] -+ chany[0][1]_midout[30] -+ chany[0][1]_midout[31] -+ chany[0][1]_midout[32] -+ chany[0][1]_midout[33] -+ chany[0][1]_midout[34] -+ chany[0][1]_midout[35] -+ chany[0][1]_midout[36] -+ chany[0][1]_midout[37] -+ chany[0][1]_midout[38] -+ chany[0][1]_midout[39] -+ chany[0][1]_midout[40] -+ chany[0][1]_midout[41] -+ chany[0][1]_midout[42] -+ chany[0][1]_midout[43] -+ chany[0][1]_midout[44] -+ chany[0][1]_midout[45] -+ chany[0][1]_midout[46] -+ chany[0][1]_midout[47] -+ chany[0][1]_midout[48] -+ chany[0][1]_midout[49] -+ chany[0][1]_midout[50] -+ chany[0][1]_midout[51] -+ chany[0][1]_midout[52] -+ chany[0][1]_midout[53] -+ chany[0][1]_midout[54] -+ chany[0][1]_midout[55] -+ chany[0][1]_midout[56] -+ chany[0][1]_midout[57] -+ chany[0][1]_midout[58] -+ chany[0][1]_midout[59] -+ chany[0][1]_midout[60] -+ chany[0][1]_midout[61] -+ chany[0][1]_midout[62] -+ chany[0][1]_midout[63] -+ chany[0][1]_midout[64] -+ chany[0][1]_midout[65] -+ chany[0][1]_midout[66] -+ chany[0][1]_midout[67] -+ chany[0][1]_midout[68] -+ chany[0][1]_midout[69] -+ chany[0][1]_midout[70] -+ chany[0][1]_midout[71] -+ chany[0][1]_midout[72] -+ chany[0][1]_midout[73] -+ chany[0][1]_midout[74] -+ chany[0][1]_midout[75] -+ chany[0][1]_midout[76] -+ chany[0][1]_midout[77] -+ chany[0][1]_midout[78] -+ chany[0][1]_midout[79] -+ chany[0][1]_midout[80] -+ chany[0][1]_midout[81] -+ chany[0][1]_midout[82] -+ chany[0][1]_midout[83] -+ chany[0][1]_midout[84] -+ chany[0][1]_midout[85] -+ chany[0][1]_midout[86] -+ chany[0][1]_midout[87] -+ chany[0][1]_midout[88] -+ chany[0][1]_midout[89] -+ chany[0][1]_midout[90] -+ chany[0][1]_midout[91] -+ chany[0][1]_midout[92] -+ chany[0][1]_midout[93] -+ chany[0][1]_midout[94] -+ chany[0][1]_midout[95] -+ chany[0][1]_midout[96] -+ chany[0][1]_midout[97] -+ chany[0][1]_midout[98] -+ chany[0][1]_midout[99] -+ grid[1][1]_pin[0][3][3] -+ grid[1][1]_pin[0][3][7] -+ grid[1][1]_pin[0][3][11] -+ grid[1][1]_pin[0][3][15] -+ grid[1][1]_pin[0][3][19] -+ grid[1][1]_pin[0][3][23] -+ grid[1][1]_pin[0][3][27] -+ grid[1][1]_pin[0][3][31] -+ grid[1][1]_pin[0][3][35] -+ grid[1][1]_pin[0][3][39] -+ grid[0][1]_pin[0][1][0] -+ grid[0][1]_pin[0][1][2] -+ grid[0][1]_pin[0][1][4] -+ grid[0][1]_pin[0][1][6] -+ grid[0][1]_pin[0][1][8] -+ grid[0][1]_pin[0][1][10] -+ grid[0][1]_pin[0][1][12] -+ grid[0][1]_pin[0][1][14] -+ gvdd_cby[0][1] 0 cby[0][1] -Xcby[1][1] -+ chany[1][1]_midout[0] -+ chany[1][1]_midout[1] -+ chany[1][1]_midout[2] -+ chany[1][1]_midout[3] -+ chany[1][1]_midout[4] -+ chany[1][1]_midout[5] -+ chany[1][1]_midout[6] -+ chany[1][1]_midout[7] -+ chany[1][1]_midout[8] -+ chany[1][1]_midout[9] -+ chany[1][1]_midout[10] -+ chany[1][1]_midout[11] -+ chany[1][1]_midout[12] -+ chany[1][1]_midout[13] -+ chany[1][1]_midout[14] -+ chany[1][1]_midout[15] -+ chany[1][1]_midout[16] -+ chany[1][1]_midout[17] -+ chany[1][1]_midout[18] -+ chany[1][1]_midout[19] -+ chany[1][1]_midout[20] -+ chany[1][1]_midout[21] -+ chany[1][1]_midout[22] -+ chany[1][1]_midout[23] -+ chany[1][1]_midout[24] -+ chany[1][1]_midout[25] -+ chany[1][1]_midout[26] -+ chany[1][1]_midout[27] -+ chany[1][1]_midout[28] -+ chany[1][1]_midout[29] -+ chany[1][1]_midout[30] -+ chany[1][1]_midout[31] -+ chany[1][1]_midout[32] -+ chany[1][1]_midout[33] -+ chany[1][1]_midout[34] -+ chany[1][1]_midout[35] -+ chany[1][1]_midout[36] -+ chany[1][1]_midout[37] -+ chany[1][1]_midout[38] -+ chany[1][1]_midout[39] -+ chany[1][1]_midout[40] -+ chany[1][1]_midout[41] -+ chany[1][1]_midout[42] -+ chany[1][1]_midout[43] -+ chany[1][1]_midout[44] -+ chany[1][1]_midout[45] -+ chany[1][1]_midout[46] -+ chany[1][1]_midout[47] -+ chany[1][1]_midout[48] -+ chany[1][1]_midout[49] -+ chany[1][1]_midout[50] -+ chany[1][1]_midout[51] -+ chany[1][1]_midout[52] -+ chany[1][1]_midout[53] -+ chany[1][1]_midout[54] -+ chany[1][1]_midout[55] -+ chany[1][1]_midout[56] -+ chany[1][1]_midout[57] -+ chany[1][1]_midout[58] -+ chany[1][1]_midout[59] -+ chany[1][1]_midout[60] -+ chany[1][1]_midout[61] -+ chany[1][1]_midout[62] -+ chany[1][1]_midout[63] -+ chany[1][1]_midout[64] -+ chany[1][1]_midout[65] -+ chany[1][1]_midout[66] -+ chany[1][1]_midout[67] -+ chany[1][1]_midout[68] -+ chany[1][1]_midout[69] -+ chany[1][1]_midout[70] -+ chany[1][1]_midout[71] -+ chany[1][1]_midout[72] -+ chany[1][1]_midout[73] -+ chany[1][1]_midout[74] -+ chany[1][1]_midout[75] -+ chany[1][1]_midout[76] -+ chany[1][1]_midout[77] -+ chany[1][1]_midout[78] -+ chany[1][1]_midout[79] -+ chany[1][1]_midout[80] -+ chany[1][1]_midout[81] -+ chany[1][1]_midout[82] -+ chany[1][1]_midout[83] -+ chany[1][1]_midout[84] -+ chany[1][1]_midout[85] -+ chany[1][1]_midout[86] -+ chany[1][1]_midout[87] -+ chany[1][1]_midout[88] -+ chany[1][1]_midout[89] -+ chany[1][1]_midout[90] -+ chany[1][1]_midout[91] -+ chany[1][1]_midout[92] -+ chany[1][1]_midout[93] -+ chany[1][1]_midout[94] -+ chany[1][1]_midout[95] -+ chany[1][1]_midout[96] -+ chany[1][1]_midout[97] -+ chany[1][1]_midout[98] -+ chany[1][1]_midout[99] -+ grid[2][1]_pin[0][3][0] -+ grid[2][1]_pin[0][3][2] -+ grid[2][1]_pin[0][3][4] -+ grid[2][1]_pin[0][3][6] -+ grid[2][1]_pin[0][3][8] -+ grid[2][1]_pin[0][3][10] -+ grid[2][1]_pin[0][3][12] -+ grid[2][1]_pin[0][3][14] -+ grid[1][1]_pin[0][1][1] -+ grid[1][1]_pin[0][1][5] -+ grid[1][1]_pin[0][1][9] -+ grid[1][1]_pin[0][1][13] -+ grid[1][1]_pin[0][1][17] -+ grid[1][1]_pin[0][1][21] -+ grid[1][1]_pin[0][1][25] -+ grid[1][1]_pin[0][1][29] -+ grid[1][1]_pin[0][1][33] -+ grid[1][1]_pin[0][1][37] -+ gvdd_cby[1][1] 0 cby[1][1] -Xsb[0][0] -+ chany[0][1]_out[0] chany[0][1]_in[1] chany[0][1]_out[2] chany[0][1]_in[3] chany[0][1]_out[4] chany[0][1]_in[5] chany[0][1]_out[6] chany[0][1]_in[7] chany[0][1]_out[8] chany[0][1]_in[9] chany[0][1]_out[10] chany[0][1]_in[11] chany[0][1]_out[12] chany[0][1]_in[13] chany[0][1]_out[14] chany[0][1]_in[15] chany[0][1]_out[16] chany[0][1]_in[17] chany[0][1]_out[18] chany[0][1]_in[19] chany[0][1]_out[20] chany[0][1]_in[21] chany[0][1]_out[22] chany[0][1]_in[23] chany[0][1]_out[24] chany[0][1]_in[25] chany[0][1]_out[26] chany[0][1]_in[27] chany[0][1]_out[28] chany[0][1]_in[29] chany[0][1]_out[30] chany[0][1]_in[31] chany[0][1]_out[32] chany[0][1]_in[33] chany[0][1]_out[34] chany[0][1]_in[35] chany[0][1]_out[36] chany[0][1]_in[37] chany[0][1]_out[38] chany[0][1]_in[39] chany[0][1]_out[40] chany[0][1]_in[41] chany[0][1]_out[42] chany[0][1]_in[43] chany[0][1]_out[44] chany[0][1]_in[45] chany[0][1]_out[46] chany[0][1]_in[47] chany[0][1]_out[48] chany[0][1]_in[49] chany[0][1]_out[50] chany[0][1]_in[51] chany[0][1]_out[52] chany[0][1]_in[53] chany[0][1]_out[54] chany[0][1]_in[55] chany[0][1]_out[56] chany[0][1]_in[57] chany[0][1]_out[58] chany[0][1]_in[59] chany[0][1]_out[60] chany[0][1]_in[61] chany[0][1]_out[62] chany[0][1]_in[63] chany[0][1]_out[64] chany[0][1]_in[65] chany[0][1]_out[66] chany[0][1]_in[67] chany[0][1]_out[68] chany[0][1]_in[69] chany[0][1]_out[70] chany[0][1]_in[71] chany[0][1]_out[72] chany[0][1]_in[73] chany[0][1]_out[74] chany[0][1]_in[75] chany[0][1]_out[76] chany[0][1]_in[77] chany[0][1]_out[78] chany[0][1]_in[79] chany[0][1]_out[80] chany[0][1]_in[81] chany[0][1]_out[82] chany[0][1]_in[83] chany[0][1]_out[84] chany[0][1]_in[85] chany[0][1]_out[86] chany[0][1]_in[87] chany[0][1]_out[88] chany[0][1]_in[89] chany[0][1]_out[90] chany[0][1]_in[91] chany[0][1]_out[92] chany[0][1]_in[93] chany[0][1]_out[94] chany[0][1]_in[95] chany[0][1]_out[96] chany[0][1]_in[97] chany[0][1]_out[98] chany[0][1]_in[99] -+ grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][47] -+ chanx[1][0]_out[0] chanx[1][0]_in[1] chanx[1][0]_out[2] chanx[1][0]_in[3] chanx[1][0]_out[4] chanx[1][0]_in[5] chanx[1][0]_out[6] chanx[1][0]_in[7] chanx[1][0]_out[8] chanx[1][0]_in[9] chanx[1][0]_out[10] chanx[1][0]_in[11] chanx[1][0]_out[12] chanx[1][0]_in[13] chanx[1][0]_out[14] chanx[1][0]_in[15] chanx[1][0]_out[16] chanx[1][0]_in[17] chanx[1][0]_out[18] chanx[1][0]_in[19] chanx[1][0]_out[20] chanx[1][0]_in[21] chanx[1][0]_out[22] chanx[1][0]_in[23] chanx[1][0]_out[24] chanx[1][0]_in[25] chanx[1][0]_out[26] chanx[1][0]_in[27] chanx[1][0]_out[28] chanx[1][0]_in[29] chanx[1][0]_out[30] chanx[1][0]_in[31] chanx[1][0]_out[32] chanx[1][0]_in[33] chanx[1][0]_out[34] chanx[1][0]_in[35] chanx[1][0]_out[36] chanx[1][0]_in[37] chanx[1][0]_out[38] chanx[1][0]_in[39] chanx[1][0]_out[40] chanx[1][0]_in[41] chanx[1][0]_out[42] chanx[1][0]_in[43] chanx[1][0]_out[44] chanx[1][0]_in[45] chanx[1][0]_out[46] chanx[1][0]_in[47] chanx[1][0]_out[48] chanx[1][0]_in[49] chanx[1][0]_out[50] chanx[1][0]_in[51] chanx[1][0]_out[52] chanx[1][0]_in[53] chanx[1][0]_out[54] chanx[1][0]_in[55] chanx[1][0]_out[56] chanx[1][0]_in[57] chanx[1][0]_out[58] chanx[1][0]_in[59] chanx[1][0]_out[60] chanx[1][0]_in[61] chanx[1][0]_out[62] chanx[1][0]_in[63] chanx[1][0]_out[64] chanx[1][0]_in[65] chanx[1][0]_out[66] chanx[1][0]_in[67] chanx[1][0]_out[68] chanx[1][0]_in[69] chanx[1][0]_out[70] chanx[1][0]_in[71] chanx[1][0]_out[72] chanx[1][0]_in[73] chanx[1][0]_out[74] chanx[1][0]_in[75] chanx[1][0]_out[76] chanx[1][0]_in[77] chanx[1][0]_out[78] chanx[1][0]_in[79] chanx[1][0]_out[80] chanx[1][0]_in[81] chanx[1][0]_out[82] chanx[1][0]_in[83] chanx[1][0]_out[84] chanx[1][0]_in[85] chanx[1][0]_out[86] chanx[1][0]_in[87] chanx[1][0]_out[88] chanx[1][0]_in[89] chanx[1][0]_out[90] chanx[1][0]_in[91] chanx[1][0]_out[92] chanx[1][0]_in[93] chanx[1][0]_out[94] chanx[1][0]_in[95] chanx[1][0]_out[96] chanx[1][0]_in[97] chanx[1][0]_out[98] chanx[1][0]_in[99] -+ grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][46] grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ -+ -+ -+ -+ gvdd_sb[0][0] 0 sb[0][0] -Xsb[0][1] -+ -+ -+ chanx[1][1]_out[0] chanx[1][1]_in[1] chanx[1][1]_out[2] chanx[1][1]_in[3] chanx[1][1]_out[4] chanx[1][1]_in[5] chanx[1][1]_out[6] chanx[1][1]_in[7] chanx[1][1]_out[8] chanx[1][1]_in[9] chanx[1][1]_out[10] chanx[1][1]_in[11] chanx[1][1]_out[12] chanx[1][1]_in[13] chanx[1][1]_out[14] chanx[1][1]_in[15] chanx[1][1]_out[16] chanx[1][1]_in[17] chanx[1][1]_out[18] chanx[1][1]_in[19] chanx[1][1]_out[20] chanx[1][1]_in[21] chanx[1][1]_out[22] chanx[1][1]_in[23] chanx[1][1]_out[24] chanx[1][1]_in[25] chanx[1][1]_out[26] chanx[1][1]_in[27] chanx[1][1]_out[28] chanx[1][1]_in[29] chanx[1][1]_out[30] chanx[1][1]_in[31] chanx[1][1]_out[32] chanx[1][1]_in[33] chanx[1][1]_out[34] chanx[1][1]_in[35] chanx[1][1]_out[36] chanx[1][1]_in[37] chanx[1][1]_out[38] chanx[1][1]_in[39] chanx[1][1]_out[40] chanx[1][1]_in[41] chanx[1][1]_out[42] chanx[1][1]_in[43] chanx[1][1]_out[44] chanx[1][1]_in[45] chanx[1][1]_out[46] chanx[1][1]_in[47] chanx[1][1]_out[48] chanx[1][1]_in[49] chanx[1][1]_out[50] chanx[1][1]_in[51] chanx[1][1]_out[52] chanx[1][1]_in[53] chanx[1][1]_out[54] chanx[1][1]_in[55] chanx[1][1]_out[56] chanx[1][1]_in[57] chanx[1][1]_out[58] chanx[1][1]_in[59] chanx[1][1]_out[60] chanx[1][1]_in[61] chanx[1][1]_out[62] chanx[1][1]_in[63] chanx[1][1]_out[64] chanx[1][1]_in[65] chanx[1][1]_out[66] chanx[1][1]_in[67] chanx[1][1]_out[68] chanx[1][1]_in[69] chanx[1][1]_out[70] chanx[1][1]_in[71] chanx[1][1]_out[72] chanx[1][1]_in[73] chanx[1][1]_out[74] chanx[1][1]_in[75] chanx[1][1]_out[76] chanx[1][1]_in[77] chanx[1][1]_out[78] chanx[1][1]_in[79] chanx[1][1]_out[80] chanx[1][1]_in[81] chanx[1][1]_out[82] chanx[1][1]_in[83] chanx[1][1]_out[84] chanx[1][1]_in[85] chanx[1][1]_out[86] chanx[1][1]_in[87] chanx[1][1]_out[88] chanx[1][1]_in[89] chanx[1][1]_out[90] chanx[1][1]_in[91] chanx[1][1]_out[92] chanx[1][1]_in[93] chanx[1][1]_out[94] chanx[1][1]_in[95] chanx[1][1]_out[96] chanx[1][1]_in[97] chanx[1][1]_out[98] chanx[1][1]_in[99] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][48] -+ chany[0][1]_in[0] chany[0][1]_out[1] chany[0][1]_in[2] chany[0][1]_out[3] chany[0][1]_in[4] chany[0][1]_out[5] chany[0][1]_in[6] chany[0][1]_out[7] chany[0][1]_in[8] chany[0][1]_out[9] chany[0][1]_in[10] chany[0][1]_out[11] chany[0][1]_in[12] chany[0][1]_out[13] chany[0][1]_in[14] chany[0][1]_out[15] chany[0][1]_in[16] chany[0][1]_out[17] chany[0][1]_in[18] chany[0][1]_out[19] chany[0][1]_in[20] chany[0][1]_out[21] chany[0][1]_in[22] chany[0][1]_out[23] chany[0][1]_in[24] chany[0][1]_out[25] chany[0][1]_in[26] chany[0][1]_out[27] chany[0][1]_in[28] chany[0][1]_out[29] chany[0][1]_in[30] chany[0][1]_out[31] chany[0][1]_in[32] chany[0][1]_out[33] chany[0][1]_in[34] chany[0][1]_out[35] chany[0][1]_in[36] chany[0][1]_out[37] chany[0][1]_in[38] chany[0][1]_out[39] chany[0][1]_in[40] chany[0][1]_out[41] chany[0][1]_in[42] chany[0][1]_out[43] chany[0][1]_in[44] chany[0][1]_out[45] chany[0][1]_in[46] chany[0][1]_out[47] chany[0][1]_in[48] chany[0][1]_out[49] chany[0][1]_in[50] chany[0][1]_out[51] chany[0][1]_in[52] chany[0][1]_out[53] chany[0][1]_in[54] chany[0][1]_out[55] chany[0][1]_in[56] chany[0][1]_out[57] chany[0][1]_in[58] chany[0][1]_out[59] chany[0][1]_in[60] chany[0][1]_out[61] chany[0][1]_in[62] chany[0][1]_out[63] chany[0][1]_in[64] chany[0][1]_out[65] chany[0][1]_in[66] chany[0][1]_out[67] chany[0][1]_in[68] chany[0][1]_out[69] chany[0][1]_in[70] chany[0][1]_out[71] chany[0][1]_in[72] chany[0][1]_out[73] chany[0][1]_in[74] chany[0][1]_out[75] chany[0][1]_in[76] chany[0][1]_out[77] chany[0][1]_in[78] chany[0][1]_out[79] chany[0][1]_in[80] chany[0][1]_out[81] chany[0][1]_in[82] chany[0][1]_out[83] chany[0][1]_in[84] chany[0][1]_out[85] chany[0][1]_in[86] chany[0][1]_out[87] chany[0][1]_in[88] chany[0][1]_out[89] chany[0][1]_in[90] chany[0][1]_out[91] chany[0][1]_in[92] chany[0][1]_out[93] chany[0][1]_in[94] chany[0][1]_out[95] chany[0][1]_in[96] chany[0][1]_out[97] chany[0][1]_in[98] chany[0][1]_out[99] -+ grid[1][1]_pin[0][3][43] grid[1][1]_pin[0][3][47] grid[0][1]_pin[0][1][1] grid[0][1]_pin[0][1][3] grid[0][1]_pin[0][1][5] grid[0][1]_pin[0][1][7] grid[0][1]_pin[0][1][9] grid[0][1]_pin[0][1][11] grid[0][1]_pin[0][1][13] grid[0][1]_pin[0][1][15] -+ -+ -+ gvdd_sb[0][1] 0 sb[0][1] -Xsb[1][0] -+ chany[1][1]_out[0] chany[1][1]_in[1] chany[1][1]_out[2] chany[1][1]_in[3] chany[1][1]_out[4] chany[1][1]_in[5] chany[1][1]_out[6] chany[1][1]_in[7] chany[1][1]_out[8] chany[1][1]_in[9] chany[1][1]_out[10] chany[1][1]_in[11] chany[1][1]_out[12] chany[1][1]_in[13] chany[1][1]_out[14] chany[1][1]_in[15] chany[1][1]_out[16] chany[1][1]_in[17] chany[1][1]_out[18] chany[1][1]_in[19] chany[1][1]_out[20] chany[1][1]_in[21] chany[1][1]_out[22] chany[1][1]_in[23] chany[1][1]_out[24] chany[1][1]_in[25] chany[1][1]_out[26] chany[1][1]_in[27] chany[1][1]_out[28] chany[1][1]_in[29] chany[1][1]_out[30] chany[1][1]_in[31] chany[1][1]_out[32] chany[1][1]_in[33] chany[1][1]_out[34] chany[1][1]_in[35] chany[1][1]_out[36] chany[1][1]_in[37] chany[1][1]_out[38] chany[1][1]_in[39] chany[1][1]_out[40] chany[1][1]_in[41] chany[1][1]_out[42] chany[1][1]_in[43] chany[1][1]_out[44] chany[1][1]_in[45] chany[1][1]_out[46] chany[1][1]_in[47] chany[1][1]_out[48] chany[1][1]_in[49] chany[1][1]_out[50] chany[1][1]_in[51] chany[1][1]_out[52] chany[1][1]_in[53] chany[1][1]_out[54] chany[1][1]_in[55] chany[1][1]_out[56] chany[1][1]_in[57] chany[1][1]_out[58] chany[1][1]_in[59] chany[1][1]_out[60] chany[1][1]_in[61] chany[1][1]_out[62] chany[1][1]_in[63] chany[1][1]_out[64] chany[1][1]_in[65] chany[1][1]_out[66] chany[1][1]_in[67] chany[1][1]_out[68] chany[1][1]_in[69] chany[1][1]_out[70] chany[1][1]_in[71] chany[1][1]_out[72] chany[1][1]_in[73] chany[1][1]_out[74] chany[1][1]_in[75] chany[1][1]_out[76] chany[1][1]_in[77] chany[1][1]_out[78] chany[1][1]_in[79] chany[1][1]_out[80] chany[1][1]_in[81] chany[1][1]_out[82] chany[1][1]_in[83] chany[1][1]_out[84] chany[1][1]_in[85] chany[1][1]_out[86] chany[1][1]_in[87] chany[1][1]_out[88] chany[1][1]_in[89] chany[1][1]_out[90] chany[1][1]_in[91] chany[1][1]_out[92] chany[1][1]_in[93] chany[1][1]_out[94] chany[1][1]_in[95] chany[1][1]_out[96] chany[1][1]_in[97] chany[1][1]_out[98] chany[1][1]_in[99] -+ grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][49] grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] -+ -+ -+ -+ -+ chanx[1][0]_in[0] chanx[1][0]_out[1] chanx[1][0]_in[2] chanx[1][0]_out[3] chanx[1][0]_in[4] chanx[1][0]_out[5] chanx[1][0]_in[6] chanx[1][0]_out[7] chanx[1][0]_in[8] chanx[1][0]_out[9] chanx[1][0]_in[10] chanx[1][0]_out[11] chanx[1][0]_in[12] chanx[1][0]_out[13] chanx[1][0]_in[14] chanx[1][0]_out[15] chanx[1][0]_in[16] chanx[1][0]_out[17] chanx[1][0]_in[18] chanx[1][0]_out[19] chanx[1][0]_in[20] chanx[1][0]_out[21] chanx[1][0]_in[22] chanx[1][0]_out[23] chanx[1][0]_in[24] chanx[1][0]_out[25] chanx[1][0]_in[26] chanx[1][0]_out[27] chanx[1][0]_in[28] chanx[1][0]_out[29] chanx[1][0]_in[30] chanx[1][0]_out[31] chanx[1][0]_in[32] chanx[1][0]_out[33] chanx[1][0]_in[34] chanx[1][0]_out[35] chanx[1][0]_in[36] chanx[1][0]_out[37] chanx[1][0]_in[38] chanx[1][0]_out[39] chanx[1][0]_in[40] chanx[1][0]_out[41] chanx[1][0]_in[42] chanx[1][0]_out[43] chanx[1][0]_in[44] chanx[1][0]_out[45] chanx[1][0]_in[46] chanx[1][0]_out[47] chanx[1][0]_in[48] chanx[1][0]_out[49] chanx[1][0]_in[50] chanx[1][0]_out[51] chanx[1][0]_in[52] chanx[1][0]_out[53] chanx[1][0]_in[54] chanx[1][0]_out[55] chanx[1][0]_in[56] chanx[1][0]_out[57] chanx[1][0]_in[58] chanx[1][0]_out[59] chanx[1][0]_in[60] chanx[1][0]_out[61] chanx[1][0]_in[62] chanx[1][0]_out[63] chanx[1][0]_in[64] chanx[1][0]_out[65] chanx[1][0]_in[66] chanx[1][0]_out[67] chanx[1][0]_in[68] chanx[1][0]_out[69] chanx[1][0]_in[70] chanx[1][0]_out[71] chanx[1][0]_in[72] chanx[1][0]_out[73] chanx[1][0]_in[74] chanx[1][0]_out[75] chanx[1][0]_in[76] chanx[1][0]_out[77] chanx[1][0]_in[78] chanx[1][0]_out[79] chanx[1][0]_in[80] chanx[1][0]_out[81] chanx[1][0]_in[82] chanx[1][0]_out[83] chanx[1][0]_in[84] chanx[1][0]_out[85] chanx[1][0]_in[86] chanx[1][0]_out[87] chanx[1][0]_in[88] chanx[1][0]_out[89] chanx[1][0]_in[90] chanx[1][0]_out[91] chanx[1][0]_in[92] chanx[1][0]_out[93] chanx[1][0]_in[94] chanx[1][0]_out[95] chanx[1][0]_in[96] chanx[1][0]_out[97] chanx[1][0]_in[98] chanx[1][0]_out[99] -+ grid[1][1]_pin[0][2][42] grid[1][1]_pin[0][2][46] grid[1][0]_pin[0][0][1] grid[1][0]_pin[0][0][3] grid[1][0]_pin[0][0][5] grid[1][0]_pin[0][0][7] grid[1][0]_pin[0][0][9] grid[1][0]_pin[0][0][11] grid[1][0]_pin[0][0][13] grid[1][0]_pin[0][0][15] -+ gvdd_sb[1][0] 0 sb[1][0] -Xsb[1][1] -+ -+ -+ -+ -+ chany[1][1]_in[0] chany[1][1]_out[1] chany[1][1]_in[2] chany[1][1]_out[3] chany[1][1]_in[4] chany[1][1]_out[5] chany[1][1]_in[6] chany[1][1]_out[7] chany[1][1]_in[8] chany[1][1]_out[9] chany[1][1]_in[10] chany[1][1]_out[11] chany[1][1]_in[12] chany[1][1]_out[13] chany[1][1]_in[14] chany[1][1]_out[15] chany[1][1]_in[16] chany[1][1]_out[17] chany[1][1]_in[18] chany[1][1]_out[19] chany[1][1]_in[20] chany[1][1]_out[21] chany[1][1]_in[22] chany[1][1]_out[23] chany[1][1]_in[24] chany[1][1]_out[25] chany[1][1]_in[26] chany[1][1]_out[27] chany[1][1]_in[28] chany[1][1]_out[29] chany[1][1]_in[30] chany[1][1]_out[31] chany[1][1]_in[32] chany[1][1]_out[33] chany[1][1]_in[34] chany[1][1]_out[35] chany[1][1]_in[36] chany[1][1]_out[37] chany[1][1]_in[38] chany[1][1]_out[39] chany[1][1]_in[40] chany[1][1]_out[41] chany[1][1]_in[42] chany[1][1]_out[43] chany[1][1]_in[44] chany[1][1]_out[45] chany[1][1]_in[46] chany[1][1]_out[47] chany[1][1]_in[48] chany[1][1]_out[49] chany[1][1]_in[50] chany[1][1]_out[51] chany[1][1]_in[52] chany[1][1]_out[53] chany[1][1]_in[54] chany[1][1]_out[55] chany[1][1]_in[56] chany[1][1]_out[57] chany[1][1]_in[58] chany[1][1]_out[59] chany[1][1]_in[60] chany[1][1]_out[61] chany[1][1]_in[62] chany[1][1]_out[63] chany[1][1]_in[64] chany[1][1]_out[65] chany[1][1]_in[66] chany[1][1]_out[67] chany[1][1]_in[68] chany[1][1]_out[69] chany[1][1]_in[70] chany[1][1]_out[71] chany[1][1]_in[72] chany[1][1]_out[73] chany[1][1]_in[74] chany[1][1]_out[75] chany[1][1]_in[76] chany[1][1]_out[77] chany[1][1]_in[78] chany[1][1]_out[79] chany[1][1]_in[80] chany[1][1]_out[81] chany[1][1]_in[82] chany[1][1]_out[83] chany[1][1]_in[84] chany[1][1]_out[85] chany[1][1]_in[86] chany[1][1]_out[87] chany[1][1]_in[88] chany[1][1]_out[89] chany[1][1]_in[90] chany[1][1]_out[91] chany[1][1]_in[92] chany[1][1]_out[93] chany[1][1]_in[94] chany[1][1]_out[95] chany[1][1]_in[96] chany[1][1]_out[97] chany[1][1]_in[98] chany[1][1]_out[99] -+ grid[2][1]_pin[0][3][1] grid[2][1]_pin[0][3][3] grid[2][1]_pin[0][3][5] grid[2][1]_pin[0][3][7] grid[2][1]_pin[0][3][9] grid[2][1]_pin[0][3][11] grid[2][1]_pin[0][3][13] grid[2][1]_pin[0][3][15] grid[1][1]_pin[0][1][41] grid[1][1]_pin[0][1][45] grid[1][1]_pin[0][1][49] -+ chanx[1][1]_in[0] chanx[1][1]_out[1] chanx[1][1]_in[2] chanx[1][1]_out[3] chanx[1][1]_in[4] chanx[1][1]_out[5] chanx[1][1]_in[6] chanx[1][1]_out[7] chanx[1][1]_in[8] chanx[1][1]_out[9] chanx[1][1]_in[10] chanx[1][1]_out[11] chanx[1][1]_in[12] chanx[1][1]_out[13] chanx[1][1]_in[14] chanx[1][1]_out[15] chanx[1][1]_in[16] chanx[1][1]_out[17] chanx[1][1]_in[18] chanx[1][1]_out[19] chanx[1][1]_in[20] chanx[1][1]_out[21] chanx[1][1]_in[22] chanx[1][1]_out[23] chanx[1][1]_in[24] chanx[1][1]_out[25] chanx[1][1]_in[26] chanx[1][1]_out[27] chanx[1][1]_in[28] chanx[1][1]_out[29] chanx[1][1]_in[30] chanx[1][1]_out[31] chanx[1][1]_in[32] chanx[1][1]_out[33] chanx[1][1]_in[34] chanx[1][1]_out[35] chanx[1][1]_in[36] chanx[1][1]_out[37] chanx[1][1]_in[38] chanx[1][1]_out[39] chanx[1][1]_in[40] chanx[1][1]_out[41] chanx[1][1]_in[42] chanx[1][1]_out[43] chanx[1][1]_in[44] chanx[1][1]_out[45] chanx[1][1]_in[46] chanx[1][1]_out[47] chanx[1][1]_in[48] chanx[1][1]_out[49] chanx[1][1]_in[50] chanx[1][1]_out[51] chanx[1][1]_in[52] chanx[1][1]_out[53] chanx[1][1]_in[54] chanx[1][1]_out[55] chanx[1][1]_in[56] chanx[1][1]_out[57] chanx[1][1]_in[58] chanx[1][1]_out[59] chanx[1][1]_in[60] chanx[1][1]_out[61] chanx[1][1]_in[62] chanx[1][1]_out[63] chanx[1][1]_in[64] chanx[1][1]_out[65] chanx[1][1]_in[66] chanx[1][1]_out[67] chanx[1][1]_in[68] chanx[1][1]_out[69] chanx[1][1]_in[70] chanx[1][1]_out[71] chanx[1][1]_in[72] chanx[1][1]_out[73] chanx[1][1]_in[74] chanx[1][1]_out[75] chanx[1][1]_in[76] chanx[1][1]_out[77] chanx[1][1]_in[78] chanx[1][1]_out[79] chanx[1][1]_in[80] chanx[1][1]_out[81] chanx[1][1]_in[82] chanx[1][1]_out[83] chanx[1][1]_in[84] chanx[1][1]_out[85] chanx[1][1]_in[86] chanx[1][1]_out[87] chanx[1][1]_in[88] chanx[1][1]_out[89] chanx[1][1]_in[90] chanx[1][1]_out[91] chanx[1][1]_in[92] chanx[1][1]_out[93] chanx[1][1]_in[94] chanx[1][1]_out[95] chanx[1][1]_in[96] chanx[1][1]_out[97] chanx[1][1]_in[98] chanx[1][1]_out[99] -+ grid[1][2]_pin[0][2][1] grid[1][2]_pin[0][2][3] grid[1][2]_pin[0][2][5] grid[1][2]_pin[0][2][7] grid[1][2]_pin[0][2][9] grid[1][2]_pin[0][2][11] grid[1][2]_pin[0][2][13] grid[1][2]_pin[0][2][15] grid[1][1]_pin[0][0][40] grid[1][1]_pin[0][0][44] grid[1][1]_pin[0][0][48] -+ gvdd_sb[1][1] 0 sb[1][1] -***** BEGIN CLB to CLB Direct Connections ***** -***** END CLB to CLB Direct Connections ***** -***** Global VDD port ***** -Vgvdd gvdd 0 vsp -***** Global GND port ***** -Vggnd ggnd 0 0 -***** Global Net for reset signal ***** -Vgreset greset 0 0 -Vgreset_inv greset_inv 0 vsp -***** Global Net for set signal ***** -Vgset gset 0 0 -Vgset_inv gset_inv 0 vsp -***** Global Net for configuration done signal ***** -Vgconfig_done gconfig_done 0 0 -Vgconfig_done_inv gconfig_done_inv 0 vsp -***** Global Clock signal ***** -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock gclock 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') - -***** pulse(vlow vhigh tdelay trise tfall pulse_width period ***** -Vgclock_inv gclock_inv 0 pulse(0 vsp 'clock_period' -+ 'clock_slew_pct_rise*clock_period' 'clock_slew_pct_fall*clock_period' -+ '0.5*(1-clock_slew_pct_rise-clock_slew_pct_fall)*clock_period' 'clock_period') -***** Connecting Global ports ***** -Rzin[0] zin[0] ggnd 0 -Rshortwireclk[0] clk[0] gclock 0 -RshortwireReset[0] Reset[0] greset 0 -RshortwireSet[0] Set[0] gset 0 -***** End Connecting Global ports ***** -***** Global Inputs for SRAMs ***** -***** Global Inputs for SRAMs ***** -Vsram->in sram->in 0 0 -.nodeset V(sram->in) 0 -***** Global VDD for SRAMs ***** -Vgvdd_sram gvdd_sram 0 vsp -***** Global VDD for I/O pads ***** -Vgvdd_io gvdd_io 0 vsp -***** Global VDD for I/O pads SRAMs ***** -Vgvdd_sram_io gvdd_sram_io 0 vsp -***** Global VDD for Local Interconnection ***** -Vgvdd_local_interc gvdd_local_interc 0 vsp -***** Global VDD for CLB to CLB direct connection ***** -Vgvdd_direct_interc gvdd_direct_interc 0 vsp -***** Global VDD for local routing SRAMs ***** -Vgvdd_sram_local_routing gvdd_sram_local_routing 0 vsp -***** Global VDD for LUTs SRAMs ***** -Vgvdd_sram_luts gvdd_sram_luts 0 vsp -***** Global VDD for Connection Boxes SRAMs ***** -Vgvdd_sram_cbs gvdd_sram_cbs 0 vsp -***** Global VDD for Switch Boxes SRAMs ***** -Vgvdd_sram_sbs gvdd_sram_sbs 0 vsp -***** Global VDD for Hard Logics ***** -***** Global VDD for Look-Up Tables (LUTs) ***** -Vgvdd_lut6[0] gvdd_lut6[0] 0 vsp -Rgvdd_lut6[0]_huge gvdd_lut6[0] 0 'vsp/10e-15' -Vgvdd_lut6[1] gvdd_lut6[1] 0 vsp -Rgvdd_lut6[1]_huge gvdd_lut6[1] 0 'vsp/10e-15' -Vgvdd_lut6[2] gvdd_lut6[2] 0 vsp -Rgvdd_lut6[2]_huge gvdd_lut6[2] 0 'vsp/10e-15' -Vgvdd_lut6[3] gvdd_lut6[3] 0 vsp -Rgvdd_lut6[3]_huge gvdd_lut6[3] 0 'vsp/10e-15' -Vgvdd_lut6[4] gvdd_lut6[4] 0 vsp -Rgvdd_lut6[4]_huge gvdd_lut6[4] 0 'vsp/10e-15' -Vgvdd_lut6[5] gvdd_lut6[5] 0 vsp -Rgvdd_lut6[5]_huge gvdd_lut6[5] 0 'vsp/10e-15' -Vgvdd_lut6[6] gvdd_lut6[6] 0 vsp -Rgvdd_lut6[6]_huge gvdd_lut6[6] 0 'vsp/10e-15' -Vgvdd_lut6[7] gvdd_lut6[7] 0 vsp -Rgvdd_lut6[7]_huge gvdd_lut6[7] 0 'vsp/10e-15' -Vgvdd_lut6[8] gvdd_lut6[8] 0 vsp -Rgvdd_lut6[8]_huge gvdd_lut6[8] 0 'vsp/10e-15' -Vgvdd_lut6[9] gvdd_lut6[9] 0 vsp -Rgvdd_lut6[9]_huge gvdd_lut6[9] 0 'vsp/10e-15' -***** Global VDD for Flip-flops (FFs) ***** -Vgvdd_dff[0] gvdd_dff[0] 0 vsp -Rgvdd_dff[0]_huge gvdd_dff[0] 0 'vsp/10e-15' -Vgvdd_dff[1] gvdd_dff[1] 0 vsp -Rgvdd_dff[1]_huge gvdd_dff[1] 0 'vsp/10e-15' -Vgvdd_dff[2] gvdd_dff[2] 0 vsp -Rgvdd_dff[2]_huge gvdd_dff[2] 0 'vsp/10e-15' -Vgvdd_dff[3] gvdd_dff[3] 0 vsp -Rgvdd_dff[3]_huge gvdd_dff[3] 0 'vsp/10e-15' -Vgvdd_dff[4] gvdd_dff[4] 0 vsp -Rgvdd_dff[4]_huge gvdd_dff[4] 0 'vsp/10e-15' -Vgvdd_dff[5] gvdd_dff[5] 0 vsp -Rgvdd_dff[5]_huge gvdd_dff[5] 0 'vsp/10e-15' -Vgvdd_dff[6] gvdd_dff[6] 0 vsp -Rgvdd_dff[6]_huge gvdd_dff[6] 0 'vsp/10e-15' -Vgvdd_dff[7] gvdd_dff[7] 0 vsp -Rgvdd_dff[7]_huge gvdd_dff[7] 0 'vsp/10e-15' -Vgvdd_dff[8] gvdd_dff[8] 0 vsp -Rgvdd_dff[8]_huge gvdd_dff[8] 0 'vsp/10e-15' -Vgvdd_dff[9] gvdd_dff[9] 0 vsp -Rgvdd_dff[9]_huge gvdd_dff[9] 0 'vsp/10e-15' -***** Global VDD for Flip-flops (FFs) ***** -Vgvdd_iopad[0] gvdd_iopad[0] 0 vsp -Rgvdd_iopad[0]_huge gvdd_iopad[0] 0 'vsp/10e-15' -Vgvdd_iopad[1] gvdd_iopad[1] 0 vsp -Rgvdd_iopad[1]_huge gvdd_iopad[1] 0 'vsp/10e-15' -Vgvdd_iopad[2] gvdd_iopad[2] 0 vsp -Rgvdd_iopad[2]_huge gvdd_iopad[2] 0 'vsp/10e-15' -Vgvdd_iopad[3] gvdd_iopad[3] 0 vsp -Rgvdd_iopad[3]_huge gvdd_iopad[3] 0 'vsp/10e-15' -Vgvdd_iopad[4] gvdd_iopad[4] 0 vsp -Rgvdd_iopad[4]_huge gvdd_iopad[4] 0 'vsp/10e-15' -Vgvdd_iopad[5] gvdd_iopad[5] 0 vsp -Rgvdd_iopad[5]_huge gvdd_iopad[5] 0 'vsp/10e-15' -Vgvdd_iopad[6] gvdd_iopad[6] 0 vsp -Rgvdd_iopad[6]_huge gvdd_iopad[6] 0 'vsp/10e-15' -Vgvdd_iopad[7] gvdd_iopad[7] 0 vsp -Rgvdd_iopad[7]_huge gvdd_iopad[7] 0 'vsp/10e-15' -Vgvdd_iopad[8] gvdd_iopad[8] 0 vsp -Rgvdd_iopad[8]_huge gvdd_iopad[8] 0 'vsp/10e-15' -Vgvdd_iopad[9] gvdd_iopad[9] 0 vsp -Rgvdd_iopad[9]_huge gvdd_iopad[9] 0 'vsp/10e-15' -Vgvdd_iopad[10] gvdd_iopad[10] 0 vsp -Rgvdd_iopad[10]_huge gvdd_iopad[10] 0 'vsp/10e-15' -Vgvdd_iopad[11] gvdd_iopad[11] 0 vsp -Rgvdd_iopad[11]_huge gvdd_iopad[11] 0 'vsp/10e-15' -Vgvdd_iopad[12] gvdd_iopad[12] 0 vsp -Rgvdd_iopad[12]_huge gvdd_iopad[12] 0 'vsp/10e-15' -Vgvdd_iopad[13] gvdd_iopad[13] 0 vsp -Rgvdd_iopad[13]_huge gvdd_iopad[13] 0 'vsp/10e-15' -Vgvdd_iopad[14] gvdd_iopad[14] 0 vsp -Rgvdd_iopad[14]_huge gvdd_iopad[14] 0 'vsp/10e-15' -Vgvdd_iopad[15] gvdd_iopad[15] 0 vsp -Rgvdd_iopad[15]_huge gvdd_iopad[15] 0 'vsp/10e-15' -Vgvdd_iopad[16] gvdd_iopad[16] 0 vsp -Rgvdd_iopad[16]_huge gvdd_iopad[16] 0 'vsp/10e-15' -Vgvdd_iopad[17] gvdd_iopad[17] 0 vsp -Rgvdd_iopad[17]_huge gvdd_iopad[17] 0 'vsp/10e-15' -Vgvdd_iopad[18] gvdd_iopad[18] 0 vsp -Rgvdd_iopad[18]_huge gvdd_iopad[18] 0 'vsp/10e-15' -Vgvdd_iopad[19] gvdd_iopad[19] 0 vsp -Rgvdd_iopad[19]_huge gvdd_iopad[19] 0 'vsp/10e-15' -Vgvdd_iopad[20] gvdd_iopad[20] 0 vsp -Rgvdd_iopad[20]_huge gvdd_iopad[20] 0 'vsp/10e-15' -Vgvdd_iopad[21] gvdd_iopad[21] 0 vsp -Rgvdd_iopad[21]_huge gvdd_iopad[21] 0 'vsp/10e-15' -Vgvdd_iopad[22] gvdd_iopad[22] 0 vsp -Rgvdd_iopad[22]_huge gvdd_iopad[22] 0 'vsp/10e-15' -Vgvdd_iopad[23] gvdd_iopad[23] 0 vsp -Rgvdd_iopad[23]_huge gvdd_iopad[23] 0 'vsp/10e-15' -Vgvdd_iopad[24] gvdd_iopad[24] 0 vsp -Rgvdd_iopad[24]_huge gvdd_iopad[24] 0 'vsp/10e-15' -Vgvdd_iopad[25] gvdd_iopad[25] 0 vsp -Rgvdd_iopad[25]_huge gvdd_iopad[25] 0 'vsp/10e-15' -Vgvdd_iopad[26] gvdd_iopad[26] 0 vsp -Rgvdd_iopad[26]_huge gvdd_iopad[26] 0 'vsp/10e-15' -Vgvdd_iopad[27] gvdd_iopad[27] 0 vsp -Rgvdd_iopad[27]_huge gvdd_iopad[27] 0 'vsp/10e-15' -Vgvdd_iopad[28] gvdd_iopad[28] 0 vsp -Rgvdd_iopad[28]_huge gvdd_iopad[28] 0 'vsp/10e-15' -Vgvdd_iopad[29] gvdd_iopad[29] 0 vsp -Rgvdd_iopad[29]_huge gvdd_iopad[29] 0 'vsp/10e-15' -Vgvdd_iopad[30] gvdd_iopad[30] 0 vsp -Rgvdd_iopad[30]_huge gvdd_iopad[30] 0 'vsp/10e-15' -Vgvdd_iopad[31] gvdd_iopad[31] 0 vsp -Rgvdd_iopad[31]_huge gvdd_iopad[31] 0 'vsp/10e-15' -***** Global VDD for Switch Boxes(SBs) ***** -Vgvdd_sb[0][0] gvdd_sb[0][0] 0 vsp -Vgvdd_sb[0][1] gvdd_sb[0][1] 0 vsp -Vgvdd_sb[1][0] gvdd_sb[1][0] 0 vsp -Vgvdd_sb[1][1] gvdd_sb[1][1] 0 vsp -***** Global VDD for Connection Boxes(CBs) ***** -Vgvdd_cbx[1][0] gvdd_cbx[1][0] 0 vsp -Vgvdd_cbx[1][1] gvdd_cbx[1][1] 0 vsp -Vgvdd_cby[0][1] gvdd_cby[0][1] 0 vsp -Vgvdd_cby[1][1] gvdd_cby[1][1] 0 vsp -Vgfpga_pad_iopad[0] gfpga_pad_iopad[0] 0 0 -Vgfpga_pad_iopad[1] gfpga_pad_iopad[1] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.4888*10.02*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '10.02*clock_period') -Vgfpga_pad_iopad[2] gfpga_pad_iopad[2] 0 0 -Vgfpga_pad_iopad[3] gfpga_pad_iopad[3] 0 0 -Vgfpga_pad_iopad[4] gfpga_pad_iopad[4] 0 0 -Vgfpga_pad_iopad[5] gfpga_pad_iopad[5] 0 0 -Vgfpga_pad_iopad[6] gfpga_pad_iopad[6] 0 0 -Vgfpga_pad_iopad[7] gfpga_pad_iopad[7] 0 0 -Vgfpga_pad_iopad[8] gfpga_pad_iopad[8] 0 0 -Vgfpga_pad_iopad[9] gfpga_pad_iopad[9] 0 0 -Vgfpga_pad_iopad[10] gfpga_pad_iopad[10] 0 0 -Vgfpga_pad_iopad[11] gfpga_pad_iopad[11] 0 0 -Vgfpga_pad_iopad[12] gfpga_pad_iopad[12] 0 0 -Vgfpga_pad_iopad[13] gfpga_pad_iopad[13] 0 0 -Vgfpga_pad_iopad[14] gfpga_pad_iopad[14] 0 0 -Vgfpga_pad_iopad[15] gfpga_pad_iopad[15] 0 0 -Vgfpga_pad_iopad[16] gfpga_pad_iopad[16] 0 0 -Vgfpga_pad_iopad[17] gfpga_pad_iopad[17] 0 -+ pulse(0 vsp 'clock_period' -+ 'input_slew_pct_rise*clock_period' 'input_slew_pct_fall*clock_period' -+ '0.5018*9.87167*(1-input_slew_pct_rise-input_slew_pct_fall)*clock_period' '9.87167*clock_period') -Vgfpga_pad_iopad[18] gfpga_pad_iopad[18] 0 0 -Vgfpga_pad_iopad[19] gfpga_pad_iopad[19] 0 0 -Vgfpga_pad_iopad[20] gfpga_pad_iopad[20] 0 0 -Vgfpga_pad_iopad[21] gfpga_pad_iopad[21] 0 0 -Vgfpga_pad_iopad[22] gfpga_pad_iopad[22] 0 0 -Vgfpga_pad_iopad[23] gfpga_pad_iopad[23] 0 0 -Vgfpga_pad_iopad[24] gfpga_pad_iopad[24] 0 0 -Vgfpga_pad_iopad[25] gfpga_pad_iopad[25] 0 0 -Vgfpga_pad_iopad[26] gfpga_pad_iopad[26] 0 0 -Vgfpga_pad_iopad[27] gfpga_pad_iopad[27] 0 0 -Vgfpga_pad_iopad[28] gfpga_pad_iopad[28] 0 0 -Vgfpga_pad_iopad[29] gfpga_pad_iopad[29] 0 0 -Vgfpga_pad_iopad[31] gfpga_pad_iopad[31] 0 0 -***** 6 Clock Simulation, accuracy=1e-13 ***** -.tran 1e-13 '6*clock_period' -***** Generic Measurements for Circuit Parameters ***** -.measure tran leakage_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from=0 to='clock_period' -.measure tran leakage_power_sram_luts avg p(Vgvdd_sram_luts) from=0 to='clock_period' -.measure tran leakage_power_sram_cbs avg p(Vgvdd_sram_cbs) from=0 to='clock_period' -.measure tran leakage_power_sram_sbs avg p(Vgvdd_sram_sbs) from=0 to='clock_period' -.measure tran leakage_power_io avg p(Vgvdd_io) from=0 to='clock_period' -.measure tran leakage_power_local_interc avg p(Vgvdd_local_interc) from=0 to='clock_period' -.measure tran leakage_power_direct_interc avg p(Vgvdd_direct_interc) from=0 to='clock_period' -.measure tran leakage_power_lut6[0] avg p(Vgvdd_lut6[0]) from=0 to='clock_period' -.measure tran leakage_power_lut6[1] avg p(Vgvdd_lut6[1]) from=0 to='clock_period' -.measure tran leakage_power_lut6[2] avg p(Vgvdd_lut6[2]) from=0 to='clock_period' -.measure tran leakage_power_lut6[3] avg p(Vgvdd_lut6[3]) from=0 to='clock_period' -.measure tran leakage_power_lut6[4] avg p(Vgvdd_lut6[4]) from=0 to='clock_period' -.measure tran leakage_power_lut6[5] avg p(Vgvdd_lut6[5]) from=0 to='clock_period' -.measure tran leakage_power_lut6[6] avg p(Vgvdd_lut6[6]) from=0 to='clock_period' -.measure tran leakage_power_lut6[7] avg p(Vgvdd_lut6[7]) from=0 to='clock_period' -.measure tran leakage_power_lut6[8] avg p(Vgvdd_lut6[8]) from=0 to='clock_period' -.measure tran leakage_power_lut6[9] avg p(Vgvdd_lut6[9]) from=0 to='clock_period' -.measure tran leakage_power_lut6[0to0] -+ param = 'leakage_power_lut6[0]' -.measure tran leakage_power_lut6[0to1] -+ param = 'leakage_power_lut6[1]+leakage_power_lut6[0to0]' -.measure tran leakage_power_lut6[0to2] -+ param = 'leakage_power_lut6[2]+leakage_power_lut6[0to1]' -.measure tran leakage_power_lut6[0to3] -+ param = 'leakage_power_lut6[3]+leakage_power_lut6[0to2]' -.measure tran leakage_power_lut6[0to4] -+ param = 'leakage_power_lut6[4]+leakage_power_lut6[0to3]' -.measure tran leakage_power_lut6[0to5] -+ param = 'leakage_power_lut6[5]+leakage_power_lut6[0to4]' -.measure tran leakage_power_lut6[0to6] -+ param = 'leakage_power_lut6[6]+leakage_power_lut6[0to5]' -.measure tran leakage_power_lut6[0to7] -+ param = 'leakage_power_lut6[7]+leakage_power_lut6[0to6]' -.measure tran leakage_power_lut6[0to8] -+ param = 'leakage_power_lut6[8]+leakage_power_lut6[0to7]' -.measure tran leakage_power_lut6[0to9] -+ param = 'leakage_power_lut6[9]+leakage_power_lut6[0to8]' -.measure tran total_leakage_power_lut6 -+ param = 'leakage_power_lut6[0to9]' -.measure tran leakage_power_dff[0] avg p(Vgvdd_dff[0]) from=0 to='clock_period' -.measure tran leakage_power_dff[1] avg p(Vgvdd_dff[1]) from=0 to='clock_period' -.measure tran leakage_power_dff[2] avg p(Vgvdd_dff[2]) from=0 to='clock_period' -.measure tran leakage_power_dff[3] avg p(Vgvdd_dff[3]) from=0 to='clock_period' -.measure tran leakage_power_dff[4] avg p(Vgvdd_dff[4]) from=0 to='clock_period' -.measure tran leakage_power_dff[5] avg p(Vgvdd_dff[5]) from=0 to='clock_period' -.measure tran leakage_power_dff[6] avg p(Vgvdd_dff[6]) from=0 to='clock_period' -.measure tran leakage_power_dff[7] avg p(Vgvdd_dff[7]) from=0 to='clock_period' -.measure tran leakage_power_dff[8] avg p(Vgvdd_dff[8]) from=0 to='clock_period' -.measure tran leakage_power_dff[9] avg p(Vgvdd_dff[9]) from=0 to='clock_period' -.measure tran leakage_power_dff[0to0] -+ param = 'leakage_power_dff[0]' -.measure tran leakage_power_dff[0to1] -+ param = 'leakage_power_dff[1]+leakage_power_dff[0to0]' -.measure tran leakage_power_dff[0to2] -+ param = 'leakage_power_dff[2]+leakage_power_dff[0to1]' -.measure tran leakage_power_dff[0to3] -+ param = 'leakage_power_dff[3]+leakage_power_dff[0to2]' -.measure tran leakage_power_dff[0to4] -+ param = 'leakage_power_dff[4]+leakage_power_dff[0to3]' -.measure tran leakage_power_dff[0to5] -+ param = 'leakage_power_dff[5]+leakage_power_dff[0to4]' -.measure tran leakage_power_dff[0to6] -+ param = 'leakage_power_dff[6]+leakage_power_dff[0to5]' -.measure tran leakage_power_dff[0to7] -+ param = 'leakage_power_dff[7]+leakage_power_dff[0to6]' -.measure tran leakage_power_dff[0to8] -+ param = 'leakage_power_dff[8]+leakage_power_dff[0to7]' -.measure tran leakage_power_dff[0to9] -+ param = 'leakage_power_dff[9]+leakage_power_dff[0to8]' -.measure tran total_leakage_power_dff -+ param = 'leakage_power_dff[0to9]' -.measure tran leakage_power_iopad[0] avg p(Vgvdd_iopad[0]) from=0 to='clock_period' -.measure tran leakage_power_iopad[1] avg p(Vgvdd_iopad[1]) from=0 to='clock_period' -.measure tran leakage_power_iopad[2] avg p(Vgvdd_iopad[2]) from=0 to='clock_period' -.measure tran leakage_power_iopad[3] avg p(Vgvdd_iopad[3]) from=0 to='clock_period' -.measure tran leakage_power_iopad[4] avg p(Vgvdd_iopad[4]) from=0 to='clock_period' -.measure tran leakage_power_iopad[5] avg p(Vgvdd_iopad[5]) from=0 to='clock_period' -.measure tran leakage_power_iopad[6] avg p(Vgvdd_iopad[6]) from=0 to='clock_period' -.measure tran leakage_power_iopad[7] avg p(Vgvdd_iopad[7]) from=0 to='clock_period' -.measure tran leakage_power_iopad[8] avg p(Vgvdd_iopad[8]) from=0 to='clock_period' -.measure tran leakage_power_iopad[9] avg p(Vgvdd_iopad[9]) from=0 to='clock_period' -.measure tran leakage_power_iopad[10] avg p(Vgvdd_iopad[10]) from=0 to='clock_period' -.measure tran leakage_power_iopad[11] avg p(Vgvdd_iopad[11]) from=0 to='clock_period' -.measure tran leakage_power_iopad[12] avg p(Vgvdd_iopad[12]) from=0 to='clock_period' -.measure tran leakage_power_iopad[13] avg p(Vgvdd_iopad[13]) from=0 to='clock_period' -.measure tran leakage_power_iopad[14] avg p(Vgvdd_iopad[14]) from=0 to='clock_period' -.measure tran leakage_power_iopad[15] avg p(Vgvdd_iopad[15]) from=0 to='clock_period' -.measure tran leakage_power_iopad[16] avg p(Vgvdd_iopad[16]) from=0 to='clock_period' -.measure tran leakage_power_iopad[17] avg p(Vgvdd_iopad[17]) from=0 to='clock_period' -.measure tran leakage_power_iopad[18] avg p(Vgvdd_iopad[18]) from=0 to='clock_period' -.measure tran leakage_power_iopad[19] avg p(Vgvdd_iopad[19]) from=0 to='clock_period' -.measure tran leakage_power_iopad[20] avg p(Vgvdd_iopad[20]) from=0 to='clock_period' -.measure tran leakage_power_iopad[21] avg p(Vgvdd_iopad[21]) from=0 to='clock_period' -.measure tran leakage_power_iopad[22] avg p(Vgvdd_iopad[22]) from=0 to='clock_period' -.measure tran leakage_power_iopad[23] avg p(Vgvdd_iopad[23]) from=0 to='clock_period' -.measure tran leakage_power_iopad[24] avg p(Vgvdd_iopad[24]) from=0 to='clock_period' -.measure tran leakage_power_iopad[25] avg p(Vgvdd_iopad[25]) from=0 to='clock_period' -.measure tran leakage_power_iopad[26] avg p(Vgvdd_iopad[26]) from=0 to='clock_period' -.measure tran leakage_power_iopad[27] avg p(Vgvdd_iopad[27]) from=0 to='clock_period' -.measure tran leakage_power_iopad[28] avg p(Vgvdd_iopad[28]) from=0 to='clock_period' -.measure tran leakage_power_iopad[29] avg p(Vgvdd_iopad[29]) from=0 to='clock_period' -.measure tran leakage_power_iopad[30] avg p(Vgvdd_iopad[30]) from=0 to='clock_period' -.measure tran leakage_power_iopad[31] avg p(Vgvdd_iopad[31]) from=0 to='clock_period' -.measure tran leakage_power_iopad[0to0] -+ param = 'leakage_power_iopad[0]' -.measure tran leakage_power_iopad[0to1] -+ param = 'leakage_power_iopad[1]+leakage_power_iopad[0to0]' -.measure tran leakage_power_iopad[0to2] -+ param = 'leakage_power_iopad[2]+leakage_power_iopad[0to1]' -.measure tran leakage_power_iopad[0to3] -+ param = 'leakage_power_iopad[3]+leakage_power_iopad[0to2]' -.measure tran leakage_power_iopad[0to4] -+ param = 'leakage_power_iopad[4]+leakage_power_iopad[0to3]' -.measure tran leakage_power_iopad[0to5] -+ param = 'leakage_power_iopad[5]+leakage_power_iopad[0to4]' -.measure tran leakage_power_iopad[0to6] -+ param = 'leakage_power_iopad[6]+leakage_power_iopad[0to5]' -.measure tran leakage_power_iopad[0to7] -+ param = 'leakage_power_iopad[7]+leakage_power_iopad[0to6]' -.measure tran leakage_power_iopad[0to8] -+ param = 'leakage_power_iopad[8]+leakage_power_iopad[0to7]' -.measure tran leakage_power_iopad[0to9] -+ param = 'leakage_power_iopad[9]+leakage_power_iopad[0to8]' -.measure tran leakage_power_iopad[0to10] -+ param = 'leakage_power_iopad[10]+leakage_power_iopad[0to9]' -.measure tran leakage_power_iopad[0to11] -+ param = 'leakage_power_iopad[11]+leakage_power_iopad[0to10]' -.measure tran leakage_power_iopad[0to12] -+ param = 'leakage_power_iopad[12]+leakage_power_iopad[0to11]' -.measure tran leakage_power_iopad[0to13] -+ param = 'leakage_power_iopad[13]+leakage_power_iopad[0to12]' -.measure tran leakage_power_iopad[0to14] -+ param = 'leakage_power_iopad[14]+leakage_power_iopad[0to13]' -.measure tran leakage_power_iopad[0to15] -+ param = 'leakage_power_iopad[15]+leakage_power_iopad[0to14]' -.measure tran leakage_power_iopad[0to16] -+ param = 'leakage_power_iopad[16]+leakage_power_iopad[0to15]' -.measure tran leakage_power_iopad[0to17] -+ param = 'leakage_power_iopad[17]+leakage_power_iopad[0to16]' -.measure tran leakage_power_iopad[0to18] -+ param = 'leakage_power_iopad[18]+leakage_power_iopad[0to17]' -.measure tran leakage_power_iopad[0to19] -+ param = 'leakage_power_iopad[19]+leakage_power_iopad[0to18]' -.measure tran leakage_power_iopad[0to20] -+ param = 'leakage_power_iopad[20]+leakage_power_iopad[0to19]' -.measure tran leakage_power_iopad[0to21] -+ param = 'leakage_power_iopad[21]+leakage_power_iopad[0to20]' -.measure tran leakage_power_iopad[0to22] -+ param = 'leakage_power_iopad[22]+leakage_power_iopad[0to21]' -.measure tran leakage_power_iopad[0to23] -+ param = 'leakage_power_iopad[23]+leakage_power_iopad[0to22]' -.measure tran leakage_power_iopad[0to24] -+ param = 'leakage_power_iopad[24]+leakage_power_iopad[0to23]' -.measure tran leakage_power_iopad[0to25] -+ param = 'leakage_power_iopad[25]+leakage_power_iopad[0to24]' -.measure tran leakage_power_iopad[0to26] -+ param = 'leakage_power_iopad[26]+leakage_power_iopad[0to25]' -.measure tran leakage_power_iopad[0to27] -+ param = 'leakage_power_iopad[27]+leakage_power_iopad[0to26]' -.measure tran leakage_power_iopad[0to28] -+ param = 'leakage_power_iopad[28]+leakage_power_iopad[0to27]' -.measure tran leakage_power_iopad[0to29] -+ param = 'leakage_power_iopad[29]+leakage_power_iopad[0to28]' -.measure tran leakage_power_iopad[0to30] -+ param = 'leakage_power_iopad[30]+leakage_power_iopad[0to29]' -.measure tran leakage_power_iopad[0to31] -+ param = 'leakage_power_iopad[31]+leakage_power_iopad[0to30]' -.measure tran total_leakage_power_iopad -+ param = 'leakage_power_iopad[0to31]' -***** Measure Leakage Power for Connection Boxes(CBs) ***** -.measure tran leakage_power_cbx[1][0] avg p(Vgvdd_cbx[1][0]) from=0 to='clock_period' -.measure tran leakage_power_cbx[1][1] avg p(Vgvdd_cbx[1][1]) from=0 to='clock_period' -.measure tran leakage_power_cby[0][1] avg p(Vgvdd_cby[0][1]) from=0 to='clock_period' -.measure tran leakage_power_cby[1][1] avg p(Vgvdd_cby[1][1]) from=0 to='clock_period' -***** Measure Total Leakage Power for Connection Boxes(CBs) ***** -.measure tran leakage_power_cbx[1to1][0to0] -+ param='leakage_power_cbx[1][0]' -.measure tran leakage_power_cbx[1to1][0to1] -+ param='leakage_power_cbx[1][1]+leakage_power_cbx[1to1][0to0]' -.measure tran leakage_power_cby[0to0][1to1] -+ param='leakage_power_cby[0][1]' -.measure tran leakage_power_cby[0to1][1to1] -+ param='leakage_power_cby[1][1]+leakage_power_cby[0to0][1to1]' -.measure tran leakage_power_cbs -+ param='leakage_power_cbx[1to1][0to1]+leakage_power_cby[0to1][1to1]' -***** Measure Leakage Power for Switch Boxes(SBs) ***** -.measure tran leakage_power_sb[0][0] avg p(Vgvdd_sb[0][0]) from=0 to='clock_period' -.measure tran leakage_power_sb[0][1] avg p(Vgvdd_sb[0][1]) from=0 to='clock_period' -.measure tran leakage_power_sb[1][0] avg p(Vgvdd_sb[1][0]) from=0 to='clock_period' -.measure tran leakage_power_sb[1][1] avg p(Vgvdd_sb[1][1]) from=0 to='clock_period' -***** Measure Total Leakage Power for Switch Boxes(SBs) ***** -.measure tran leakage_power_sb[0to0][0to0] -+ param='leakage_power_sb[0][0]' -.measure tran leakage_power_sb[0to0][0to1] -+ param='leakage_power_sb[0][1]+leakage_power_sb[0to0][0to0]' -.measure tran leakage_power_sb[0to1][0to0] -+ param='leakage_power_sb[1][0]+leakage_power_sb[0to0][0to1]' -.measure tran leakage_power_sb[0to1][0to1] -+ param='leakage_power_sb[1][1]+leakage_power_sb[0to1][0to0]' -.measure tran leakage_power_sbs -+ param='leakage_power_sb[0to1][0to1]' -.measure tran dynamic_power_sram_local_routing avg p(Vgvdd_sram_local_routing) from='clock_period' to='6*clock_period' -.measure tran energy_per_cycle_sram_local_routing - + param='dynamic_power_sram_local_routing*clock_period' -.measure tran dynamic_power_sram_luts avg p(Vgvdd_sram_luts) from='clock_period' to='6*clock_period' -.measure tran energy_per_cycle_sram_luts - + param='dynamic_power_sram_luts*clock_period' -.measure tran dynamic_power_sram_cbs avg p(Vgvdd_sram_cbs) from='clock_period' to='6*clock_period' -.measure tran energy_per_cycle_sram_cbs - + param='dynamic_power_sram_cbs*clock_period' -.measure tran dynamic_power_sram_sbs avg p(Vgvdd_sram_sbs) from='clock_period' to='6*clock_period' -.measure tran energy_per_cycle_sram_sbs - + param='dynamic_power_sram_sbs*clock_period' -.measure tran dynamic_power_iopad[0] avg p(Vgvdd_iopad[0]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[1] avg p(Vgvdd_iopad[1]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[2] avg p(Vgvdd_iopad[2]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[3] avg p(Vgvdd_iopad[3]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[4] avg p(Vgvdd_iopad[4]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[5] avg p(Vgvdd_iopad[5]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[6] avg p(Vgvdd_iopad[6]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[7] avg p(Vgvdd_iopad[7]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[8] avg p(Vgvdd_iopad[8]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[9] avg p(Vgvdd_iopad[9]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[10] avg p(Vgvdd_iopad[10]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[11] avg p(Vgvdd_iopad[11]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[12] avg p(Vgvdd_iopad[12]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[13] avg p(Vgvdd_iopad[13]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[14] avg p(Vgvdd_iopad[14]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[15] avg p(Vgvdd_iopad[15]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[16] avg p(Vgvdd_iopad[16]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[17] avg p(Vgvdd_iopad[17]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[18] avg p(Vgvdd_iopad[18]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[19] avg p(Vgvdd_iopad[19]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[20] avg p(Vgvdd_iopad[20]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[21] avg p(Vgvdd_iopad[21]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[22] avg p(Vgvdd_iopad[22]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[23] avg p(Vgvdd_iopad[23]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[24] avg p(Vgvdd_iopad[24]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[25] avg p(Vgvdd_iopad[25]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[26] avg p(Vgvdd_iopad[26]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[27] avg p(Vgvdd_iopad[27]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[28] avg p(Vgvdd_iopad[28]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[29] avg p(Vgvdd_iopad[29]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[30] avg p(Vgvdd_iopad[30]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[31] avg p(Vgvdd_iopad[31]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_iopad[0to0] -+ param = 'dynamic_power_iopad[0]' -.measure tran dynamic_power_iopad[0to1] -+ param = 'dynamic_power_iopad[1]+dynamic_power_iopad[0to0]' -.measure tran dynamic_power_iopad[0to2] -+ param = 'dynamic_power_iopad[2]+dynamic_power_iopad[0to1]' -.measure tran dynamic_power_iopad[0to3] -+ param = 'dynamic_power_iopad[3]+dynamic_power_iopad[0to2]' -.measure tran dynamic_power_iopad[0to4] -+ param = 'dynamic_power_iopad[4]+dynamic_power_iopad[0to3]' -.measure tran dynamic_power_iopad[0to5] -+ param = 'dynamic_power_iopad[5]+dynamic_power_iopad[0to4]' -.measure tran dynamic_power_iopad[0to6] -+ param = 'dynamic_power_iopad[6]+dynamic_power_iopad[0to5]' -.measure tran dynamic_power_iopad[0to7] -+ param = 'dynamic_power_iopad[7]+dynamic_power_iopad[0to6]' -.measure tran dynamic_power_iopad[0to8] -+ param = 'dynamic_power_iopad[8]+dynamic_power_iopad[0to7]' -.measure tran dynamic_power_iopad[0to9] -+ param = 'dynamic_power_iopad[9]+dynamic_power_iopad[0to8]' -.measure tran dynamic_power_iopad[0to10] -+ param = 'dynamic_power_iopad[10]+dynamic_power_iopad[0to9]' -.measure tran dynamic_power_iopad[0to11] -+ param = 'dynamic_power_iopad[11]+dynamic_power_iopad[0to10]' -.measure tran dynamic_power_iopad[0to12] -+ param = 'dynamic_power_iopad[12]+dynamic_power_iopad[0to11]' -.measure tran dynamic_power_iopad[0to13] -+ param = 'dynamic_power_iopad[13]+dynamic_power_iopad[0to12]' -.measure tran dynamic_power_iopad[0to14] -+ param = 'dynamic_power_iopad[14]+dynamic_power_iopad[0to13]' -.measure tran dynamic_power_iopad[0to15] -+ param = 'dynamic_power_iopad[15]+dynamic_power_iopad[0to14]' -.measure tran dynamic_power_iopad[0to16] -+ param = 'dynamic_power_iopad[16]+dynamic_power_iopad[0to15]' -.measure tran dynamic_power_iopad[0to17] -+ param = 'dynamic_power_iopad[17]+dynamic_power_iopad[0to16]' -.measure tran dynamic_power_iopad[0to18] -+ param = 'dynamic_power_iopad[18]+dynamic_power_iopad[0to17]' -.measure tran dynamic_power_iopad[0to19] -+ param = 'dynamic_power_iopad[19]+dynamic_power_iopad[0to18]' -.measure tran dynamic_power_iopad[0to20] -+ param = 'dynamic_power_iopad[20]+dynamic_power_iopad[0to19]' -.measure tran dynamic_power_iopad[0to21] -+ param = 'dynamic_power_iopad[21]+dynamic_power_iopad[0to20]' -.measure tran dynamic_power_iopad[0to22] -+ param = 'dynamic_power_iopad[22]+dynamic_power_iopad[0to21]' -.measure tran dynamic_power_iopad[0to23] -+ param = 'dynamic_power_iopad[23]+dynamic_power_iopad[0to22]' -.measure tran dynamic_power_iopad[0to24] -+ param = 'dynamic_power_iopad[24]+dynamic_power_iopad[0to23]' -.measure tran dynamic_power_iopad[0to25] -+ param = 'dynamic_power_iopad[25]+dynamic_power_iopad[0to24]' -.measure tran dynamic_power_iopad[0to26] -+ param = 'dynamic_power_iopad[26]+dynamic_power_iopad[0to25]' -.measure tran dynamic_power_iopad[0to27] -+ param = 'dynamic_power_iopad[27]+dynamic_power_iopad[0to26]' -.measure tran dynamic_power_iopad[0to28] -+ param = 'dynamic_power_iopad[28]+dynamic_power_iopad[0to27]' -.measure tran dynamic_power_iopad[0to29] -+ param = 'dynamic_power_iopad[29]+dynamic_power_iopad[0to28]' -.measure tran dynamic_power_iopad[0to30] -+ param = 'dynamic_power_iopad[30]+dynamic_power_iopad[0to29]' -.measure tran dynamic_power_iopad[0to31] -+ param = 'dynamic_power_iopad[31]+dynamic_power_iopad[0to30]' -.measure tran total_dynamic_power_iopad -+ param = 'dynamic_power_iopad[0to31]' -.measure tran total_energy_per_cycle_iopad -+ param = 'dynamic_power_iopad[0to31]*clock_period' -.measure tran dynamic_power_local_interc avg p(Vgvdd_local_interc) from='clock_period' to='6*clock_period' -.measure tran energy_per_cycle_local_routing - + param='dynamic_power_local_interc*clock_period' -.measure tran dynamic_power_direct_interc avg p(Vgvdd_direct_interc) from='clock_period' to='6*clock_period' -.measure tran energy_per_cycle_direct_interc - + param='dynamic_power_direct_interc*clock_period' -.measure tran dynamic_power_lut6[0] avg p(Vgvdd_lut6[0]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[1] avg p(Vgvdd_lut6[1]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[2] avg p(Vgvdd_lut6[2]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[3] avg p(Vgvdd_lut6[3]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[4] avg p(Vgvdd_lut6[4]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[5] avg p(Vgvdd_lut6[5]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[6] avg p(Vgvdd_lut6[6]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[7] avg p(Vgvdd_lut6[7]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[8] avg p(Vgvdd_lut6[8]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[9] avg p(Vgvdd_lut6[9]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_lut6[0to0] -+ param = 'dynamic_power_lut6[0]' -.measure tran dynamic_power_lut6[0to1] -+ param = 'dynamic_power_lut6[1]+dynamic_power_lut6[0to0]' -.measure tran dynamic_power_lut6[0to2] -+ param = 'dynamic_power_lut6[2]+dynamic_power_lut6[0to1]' -.measure tran dynamic_power_lut6[0to3] -+ param = 'dynamic_power_lut6[3]+dynamic_power_lut6[0to2]' -.measure tran dynamic_power_lut6[0to4] -+ param = 'dynamic_power_lut6[4]+dynamic_power_lut6[0to3]' -.measure tran dynamic_power_lut6[0to5] -+ param = 'dynamic_power_lut6[5]+dynamic_power_lut6[0to4]' -.measure tran dynamic_power_lut6[0to6] -+ param = 'dynamic_power_lut6[6]+dynamic_power_lut6[0to5]' -.measure tran dynamic_power_lut6[0to7] -+ param = 'dynamic_power_lut6[7]+dynamic_power_lut6[0to6]' -.measure tran dynamic_power_lut6[0to8] -+ param = 'dynamic_power_lut6[8]+dynamic_power_lut6[0to7]' -.measure tran dynamic_power_lut6[0to9] -+ param = 'dynamic_power_lut6[9]+dynamic_power_lut6[0to8]' -.measure tran total_dynamic_power_lut6 -+ param = 'dynamic_power_lut6[0to9]' -.measure tran total_energy_per_cycle_lut6 -+ param = 'dynamic_power_lut6[0to9]*clock_period' -.measure tran dynamic_power_dff[0] avg p(Vgvdd_dff[0]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[1] avg p(Vgvdd_dff[1]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[2] avg p(Vgvdd_dff[2]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[3] avg p(Vgvdd_dff[3]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[4] avg p(Vgvdd_dff[4]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[5] avg p(Vgvdd_dff[5]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[6] avg p(Vgvdd_dff[6]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[7] avg p(Vgvdd_dff[7]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[8] avg p(Vgvdd_dff[8]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[9] avg p(Vgvdd_dff[9]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_dff[0to0] -+ param = 'dynamic_power_dff[0]' -.measure tran dynamic_power_dff[0to1] -+ param = 'dynamic_power_dff[1]+dynamic_power_dff[0to0]' -.measure tran dynamic_power_dff[0to2] -+ param = 'dynamic_power_dff[2]+dynamic_power_dff[0to1]' -.measure tran dynamic_power_dff[0to3] -+ param = 'dynamic_power_dff[3]+dynamic_power_dff[0to2]' -.measure tran dynamic_power_dff[0to4] -+ param = 'dynamic_power_dff[4]+dynamic_power_dff[0to3]' -.measure tran dynamic_power_dff[0to5] -+ param = 'dynamic_power_dff[5]+dynamic_power_dff[0to4]' -.measure tran dynamic_power_dff[0to6] -+ param = 'dynamic_power_dff[6]+dynamic_power_dff[0to5]' -.measure tran dynamic_power_dff[0to7] -+ param = 'dynamic_power_dff[7]+dynamic_power_dff[0to6]' -.measure tran dynamic_power_dff[0to8] -+ param = 'dynamic_power_dff[8]+dynamic_power_dff[0to7]' -.measure tran dynamic_power_dff[0to9] -+ param = 'dynamic_power_dff[9]+dynamic_power_dff[0to8]' -.measure tran total_dynamic_power_dff -+ param = 'dynamic_power_dff[0to9]' -.measure tran total_energy_per_cycle_dff -+ param = 'dynamic_power_dff[0to9]*clock_period' -***** Measure Dynamic Power for Connection Boxes(CBs) ***** -.measure tran dynamic_power_cbx[1][0] avg p(Vgvdd_cbx[1][0]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_cbx[1][1] avg p(Vgvdd_cbx[1][1]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_cby[0][1] avg p(Vgvdd_cby[0][1]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_cby[1][1] avg p(Vgvdd_cby[1][1]) from='clock_period' to='6*clock_period' -***** Measure Total Dynamic Power for Connection Boxes(CBs) ***** -.measure tran dynamic_power_cbx[1to1][0to0] -+ param='dynamic_power_cbx[1][0]' -.measure tran dynamic_power_cbx[1to1][0to1] -+ param='dynamic_power_cbx[1][1]+dynamic_power_cbx[1to1][0to0]' -.measure tran dynamic_power_cby[0to0][1to1] -+ param='dynamic_power_cby[0][1]' -.measure tran dynamic_power_cby[0to1][1to1] -+ param='dynamic_power_cby[1][1]+dynamic_power_cby[0to0][1to1]' -.measure tran dynamic_power_cbs -+ param='dynamic_power_cbx[1to1][0to1]+dynamic_power_cby[0to1][1to1]' -.measure tran energy_per_cycle_cbs - + param='dynamic_power_cbs*clock_period' -***** Measure Dynamic Power for Switch Boxes(SBs) ***** -.measure tran dynamic_power_sb[0][0] avg p(Vgvdd_sb[0][0]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_sb[0][1] avg p(Vgvdd_sb[0][1]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_sb[1][0] avg p(Vgvdd_sb[1][0]) from='clock_period' to='6*clock_period' -.measure tran dynamic_power_sb[1][1] avg p(Vgvdd_sb[1][1]) from='clock_period' to='6*clock_period' -***** Measure Total Dynamic Power for Switch Boxes(SBs) ***** -.measure tran dynamic_power_sb[0to0][0to0] -+ param='dynamic_power_sb[0][0]' -.measure tran dynamic_power_sb[0to0][0to1] -+ param='dynamic_power_sb[0][1]+dynamic_power_sb[0to0][0to0]' -.measure tran dynamic_power_sb[0to1][0to0] -+ param='dynamic_power_sb[1][0]+dynamic_power_sb[0to0][0to1]' -.measure tran dynamic_power_sb[0to1][0to1] -+ param='dynamic_power_sb[1][1]+dynamic_power_sb[0to1][0to0]' -.measure tran dynamic_power_sbs -+ param='dynamic_power_sb[0to1][0to1]' -.measure tran energy_per_cycle_sbs - + param='dynamic_power_sbs*clock_period' -.end diff --git a/examples/verilog_test_example_1/example_1_top.v b/examples/verilog_test_example_1/example_1_top.v deleted file mode 100644 index 41780b584..000000000 --- a/examples/verilog_test_example_1/example_1_top.v +++ /dev/null @@ -1,1373 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: FPGA Verilog Netlist for Design: example_1 -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Include User-defined netlists ----- -// `include "/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/ff.v" -// `include "/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v" -// `include "/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/io.v" -//----- Include subckt netlists: Multiplexers ----- -// `include "./verilog_test_example_1/routing/muxes.v" -//----- Include subckt netlists: Wires ----- -// `include "./verilog_test_example_1/routing/wires.v" -//----- Include subckt netlists: Look-Up Tables (LUTs) ----- -// `include "./verilog_test_example_1/routing/luts.v" -//------ Include subckt netlists: Logic Blocks ----- -// `include "./verilog_test_example_1/routing/logic_blocks.v" -//----- Include subckt netlists: Routing structures (Switch Boxes, Channels, Connection Boxes) ----- -// `include "./verilog_test_example_1/routing/routing.v" -//----- Include subckt netlists: Decoders (controller for memeory bank) ----- -// `include "./verilog_test_example_1/routing/decoders.v" -//----- Top-level Verilog Module ----- -module example_1_top ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -inout [31:0] gfpga_pad_iopad , //---FPGA inouts -input [0:0] en_bl , //--- BL enable port -input [0:0] en_wl , //--- WL enable port -input [0:0] data_in , //--- BL data input port -input [4:0] addr_bl , //--- Address of bit lines -input [4:0] addr_wl //--- Address of word lines -); -wire [0:18] bl_bus ; //--- Array Bit lines bus -wire [0:18] wl_bus ; //--- Array Bit lines bus -wire [0:18] blb_bus ; //--- Inverted Array Bit lines bus - - wire [0:360] sram_blwl_bl; //---- Normal Bit lines - wire [0:360] sram_blwl_wl; //---- Normal Word lines - wire [0:360] sram_blwl_blb; //---- Inverted Normal Bit lines - INVTX1 INVTX1_blb_0 (bl_bus[0], blb_bus[0]); - INVTX1 INVTX1_blb_1 (bl_bus[1], blb_bus[1]); - INVTX1 INVTX1_blb_2 (bl_bus[2], blb_bus[2]); - INVTX1 INVTX1_blb_3 (bl_bus[3], blb_bus[3]); - INVTX1 INVTX1_blb_4 (bl_bus[4], blb_bus[4]); - INVTX1 INVTX1_blb_5 (bl_bus[5], blb_bus[5]); - INVTX1 INVTX1_blb_6 (bl_bus[6], blb_bus[6]); - INVTX1 INVTX1_blb_7 (bl_bus[7], blb_bus[7]); - INVTX1 INVTX1_blb_8 (bl_bus[8], blb_bus[8]); - INVTX1 INVTX1_blb_9 (bl_bus[9], blb_bus[9]); - INVTX1 INVTX1_blb_10 (bl_bus[10], blb_bus[10]); - INVTX1 INVTX1_blb_11 (bl_bus[11], blb_bus[11]); - INVTX1 INVTX1_blb_12 (bl_bus[12], blb_bus[12]); - INVTX1 INVTX1_blb_13 (bl_bus[13], blb_bus[13]); - INVTX1 INVTX1_blb_14 (bl_bus[14], blb_bus[14]); - INVTX1 INVTX1_blb_15 (bl_bus[15], blb_bus[15]); - INVTX1 INVTX1_blb_16 (bl_bus[16], blb_bus[16]); - INVTX1 INVTX1_blb_17 (bl_bus[17], blb_bus[17]); - assign sram_blwl_bl[0:18] = bl_bus[0:18]; - assign sram_blwl_blb[0:18] = blb_bus[0:18]; - assign sram_blwl_bl[19:37] = bl_bus[0:18]; - assign sram_blwl_blb[19:37] = blb_bus[0:18]; - assign sram_blwl_bl[38:56] = bl_bus[0:18]; - assign sram_blwl_blb[38:56] = blb_bus[0:18]; - assign sram_blwl_bl[57:75] = bl_bus[0:18]; - assign sram_blwl_blb[57:75] = blb_bus[0:18]; - assign sram_blwl_bl[76:94] = bl_bus[0:18]; - assign sram_blwl_blb[76:94] = blb_bus[0:18]; - assign sram_blwl_bl[95:113] = bl_bus[0:18]; - assign sram_blwl_blb[95:113] = blb_bus[0:18]; - assign sram_blwl_bl[114:132] = bl_bus[0:18]; - assign sram_blwl_blb[114:132] = blb_bus[0:18]; - assign sram_blwl_bl[133:151] = bl_bus[0:18]; - assign sram_blwl_blb[133:151] = blb_bus[0:18]; - assign sram_blwl_bl[152:170] = bl_bus[0:18]; - assign sram_blwl_blb[152:170] = blb_bus[0:18]; - assign sram_blwl_bl[171:189] = bl_bus[0:18]; - assign sram_blwl_blb[171:189] = blb_bus[0:18]; - assign sram_blwl_bl[190:208] = bl_bus[0:18]; - assign sram_blwl_blb[190:208] = blb_bus[0:18]; - assign sram_blwl_bl[209:227] = bl_bus[0:18]; - assign sram_blwl_blb[209:227] = blb_bus[0:18]; - assign sram_blwl_bl[228:246] = bl_bus[0:18]; - assign sram_blwl_blb[228:246] = blb_bus[0:18]; - assign sram_blwl_bl[247:265] = bl_bus[0:18]; - assign sram_blwl_blb[247:265] = blb_bus[0:18]; - assign sram_blwl_bl[266:284] = bl_bus[0:18]; - assign sram_blwl_blb[266:284] = blb_bus[0:18]; - assign sram_blwl_bl[285:303] = bl_bus[0:18]; - assign sram_blwl_blb[285:303] = blb_bus[0:18]; - assign sram_blwl_bl[304:322] = bl_bus[0:18]; - assign sram_blwl_blb[304:322] = blb_bus[0:18]; - assign sram_blwl_bl[323:341] = bl_bus[0:18]; - assign sram_blwl_blb[323:341] = blb_bus[0:18]; - assign sram_blwl_bl[342:360] = bl_bus[0:18]; - assign sram_blwl_blb[342:360] = blb_bus[0:18]; - assign sram_blwl_wl[0] = wl_bus[0]; - assign sram_blwl_wl[1] = wl_bus[0]; - assign sram_blwl_wl[2] = wl_bus[0]; - assign sram_blwl_wl[3] = wl_bus[0]; - assign sram_blwl_wl[4] = wl_bus[0]; - assign sram_blwl_wl[5] = wl_bus[0]; - assign sram_blwl_wl[6] = wl_bus[0]; - assign sram_blwl_wl[7] = wl_bus[0]; - assign sram_blwl_wl[8] = wl_bus[0]; - assign sram_blwl_wl[9] = wl_bus[0]; - assign sram_blwl_wl[10] = wl_bus[0]; - assign sram_blwl_wl[11] = wl_bus[0]; - assign sram_blwl_wl[12] = wl_bus[0]; - assign sram_blwl_wl[13] = wl_bus[0]; - assign sram_blwl_wl[14] = wl_bus[0]; - assign sram_blwl_wl[15] = wl_bus[0]; - assign sram_blwl_wl[16] = wl_bus[0]; - assign sram_blwl_wl[17] = wl_bus[0]; - assign sram_blwl_wl[18] = wl_bus[0]; - assign sram_blwl_wl[19] = wl_bus[1]; - assign sram_blwl_wl[20] = wl_bus[1]; - assign sram_blwl_wl[21] = wl_bus[1]; - assign sram_blwl_wl[22] = wl_bus[1]; - assign sram_blwl_wl[23] = wl_bus[1]; - assign sram_blwl_wl[24] = wl_bus[1]; - assign sram_blwl_wl[25] = wl_bus[1]; - assign sram_blwl_wl[26] = wl_bus[1]; - assign sram_blwl_wl[27] = wl_bus[1]; - assign sram_blwl_wl[28] = wl_bus[1]; - assign sram_blwl_wl[29] = wl_bus[1]; - assign sram_blwl_wl[30] = wl_bus[1]; - assign sram_blwl_wl[31] = wl_bus[1]; - assign sram_blwl_wl[32] = wl_bus[1]; - assign sram_blwl_wl[33] = wl_bus[1]; - assign sram_blwl_wl[34] = wl_bus[1]; - assign sram_blwl_wl[35] = wl_bus[1]; - assign sram_blwl_wl[36] = wl_bus[1]; - assign sram_blwl_wl[37] = wl_bus[1]; - assign sram_blwl_wl[38] = wl_bus[2]; - assign sram_blwl_wl[39] = wl_bus[2]; - assign sram_blwl_wl[40] = wl_bus[2]; - assign sram_blwl_wl[41] = wl_bus[2]; - assign sram_blwl_wl[42] = wl_bus[2]; - assign sram_blwl_wl[43] = wl_bus[2]; - assign sram_blwl_wl[44] = wl_bus[2]; - assign sram_blwl_wl[45] = wl_bus[2]; - assign sram_blwl_wl[46] = wl_bus[2]; - assign sram_blwl_wl[47] = wl_bus[2]; - assign sram_blwl_wl[48] = wl_bus[2]; - assign sram_blwl_wl[49] = wl_bus[2]; - assign sram_blwl_wl[50] = wl_bus[2]; - assign sram_blwl_wl[51] = wl_bus[2]; - assign sram_blwl_wl[52] = wl_bus[2]; - assign sram_blwl_wl[53] = wl_bus[2]; - assign sram_blwl_wl[54] = wl_bus[2]; - assign sram_blwl_wl[55] = wl_bus[2]; - assign sram_blwl_wl[56] = wl_bus[2]; - assign sram_blwl_wl[57] = wl_bus[3]; - assign sram_blwl_wl[58] = wl_bus[3]; - assign sram_blwl_wl[59] = wl_bus[3]; - assign sram_blwl_wl[60] = wl_bus[3]; - assign sram_blwl_wl[61] = wl_bus[3]; - assign sram_blwl_wl[62] = wl_bus[3]; - assign sram_blwl_wl[63] = wl_bus[3]; - assign sram_blwl_wl[64] = wl_bus[3]; - assign sram_blwl_wl[65] = wl_bus[3]; - assign sram_blwl_wl[66] = wl_bus[3]; - assign sram_blwl_wl[67] = wl_bus[3]; - assign sram_blwl_wl[68] = wl_bus[3]; - assign sram_blwl_wl[69] = wl_bus[3]; - assign sram_blwl_wl[70] = wl_bus[3]; - assign sram_blwl_wl[71] = wl_bus[3]; - assign sram_blwl_wl[72] = wl_bus[3]; - assign sram_blwl_wl[73] = wl_bus[3]; - assign sram_blwl_wl[74] = wl_bus[3]; - assign sram_blwl_wl[75] = wl_bus[3]; - assign sram_blwl_wl[76] = wl_bus[4]; - assign sram_blwl_wl[77] = wl_bus[4]; - assign sram_blwl_wl[78] = wl_bus[4]; - assign sram_blwl_wl[79] = wl_bus[4]; - assign sram_blwl_wl[80] = wl_bus[4]; - assign sram_blwl_wl[81] = wl_bus[4]; - assign sram_blwl_wl[82] = wl_bus[4]; - assign sram_blwl_wl[83] = wl_bus[4]; - assign sram_blwl_wl[84] = wl_bus[4]; - assign sram_blwl_wl[85] = wl_bus[4]; - assign sram_blwl_wl[86] = wl_bus[4]; - assign sram_blwl_wl[87] = wl_bus[4]; - assign sram_blwl_wl[88] = wl_bus[4]; - assign sram_blwl_wl[89] = wl_bus[4]; - assign sram_blwl_wl[90] = wl_bus[4]; - assign sram_blwl_wl[91] = wl_bus[4]; - assign sram_blwl_wl[92] = wl_bus[4]; - assign sram_blwl_wl[93] = wl_bus[4]; - assign sram_blwl_wl[94] = wl_bus[4]; - assign sram_blwl_wl[95] = wl_bus[5]; - assign sram_blwl_wl[96] = wl_bus[5]; - assign sram_blwl_wl[97] = wl_bus[5]; - assign sram_blwl_wl[98] = wl_bus[5]; - assign sram_blwl_wl[99] = wl_bus[5]; - assign sram_blwl_wl[100] = wl_bus[5]; - assign sram_blwl_wl[101] = wl_bus[5]; - assign sram_blwl_wl[102] = wl_bus[5]; - assign sram_blwl_wl[103] = wl_bus[5]; - assign sram_blwl_wl[104] = wl_bus[5]; - assign sram_blwl_wl[105] = wl_bus[5]; - assign sram_blwl_wl[106] = wl_bus[5]; - assign sram_blwl_wl[107] = wl_bus[5]; - assign sram_blwl_wl[108] = wl_bus[5]; - assign sram_blwl_wl[109] = wl_bus[5]; - assign sram_blwl_wl[110] = wl_bus[5]; - assign sram_blwl_wl[111] = wl_bus[5]; - assign sram_blwl_wl[112] = wl_bus[5]; - assign sram_blwl_wl[113] = wl_bus[5]; - assign sram_blwl_wl[114] = wl_bus[6]; - assign sram_blwl_wl[115] = wl_bus[6]; - assign sram_blwl_wl[116] = wl_bus[6]; - assign sram_blwl_wl[117] = wl_bus[6]; - assign sram_blwl_wl[118] = wl_bus[6]; - assign sram_blwl_wl[119] = wl_bus[6]; - assign sram_blwl_wl[120] = wl_bus[6]; - assign sram_blwl_wl[121] = wl_bus[6]; - assign sram_blwl_wl[122] = wl_bus[6]; - assign sram_blwl_wl[123] = wl_bus[6]; - assign sram_blwl_wl[124] = wl_bus[6]; - assign sram_blwl_wl[125] = wl_bus[6]; - assign sram_blwl_wl[126] = wl_bus[6]; - assign sram_blwl_wl[127] = wl_bus[6]; - assign sram_blwl_wl[128] = wl_bus[6]; - assign sram_blwl_wl[129] = wl_bus[6]; - assign sram_blwl_wl[130] = wl_bus[6]; - assign sram_blwl_wl[131] = wl_bus[6]; - assign sram_blwl_wl[132] = wl_bus[6]; - assign sram_blwl_wl[133] = wl_bus[7]; - assign sram_blwl_wl[134] = wl_bus[7]; - assign sram_blwl_wl[135] = wl_bus[7]; - assign sram_blwl_wl[136] = wl_bus[7]; - assign sram_blwl_wl[137] = wl_bus[7]; - assign sram_blwl_wl[138] = wl_bus[7]; - assign sram_blwl_wl[139] = wl_bus[7]; - assign sram_blwl_wl[140] = wl_bus[7]; - assign sram_blwl_wl[141] = wl_bus[7]; - assign sram_blwl_wl[142] = wl_bus[7]; - assign sram_blwl_wl[143] = wl_bus[7]; - assign sram_blwl_wl[144] = wl_bus[7]; - assign sram_blwl_wl[145] = wl_bus[7]; - assign sram_blwl_wl[146] = wl_bus[7]; - assign sram_blwl_wl[147] = wl_bus[7]; - assign sram_blwl_wl[148] = wl_bus[7]; - assign sram_blwl_wl[149] = wl_bus[7]; - assign sram_blwl_wl[150] = wl_bus[7]; - assign sram_blwl_wl[151] = wl_bus[7]; - assign sram_blwl_wl[152] = wl_bus[8]; - assign sram_blwl_wl[153] = wl_bus[8]; - assign sram_blwl_wl[154] = wl_bus[8]; - assign sram_blwl_wl[155] = wl_bus[8]; - assign sram_blwl_wl[156] = wl_bus[8]; - assign sram_blwl_wl[157] = wl_bus[8]; - assign sram_blwl_wl[158] = wl_bus[8]; - assign sram_blwl_wl[159] = wl_bus[8]; - assign sram_blwl_wl[160] = wl_bus[8]; - assign sram_blwl_wl[161] = wl_bus[8]; - assign sram_blwl_wl[162] = wl_bus[8]; - assign sram_blwl_wl[163] = wl_bus[8]; - assign sram_blwl_wl[164] = wl_bus[8]; - assign sram_blwl_wl[165] = wl_bus[8]; - assign sram_blwl_wl[166] = wl_bus[8]; - assign sram_blwl_wl[167] = wl_bus[8]; - assign sram_blwl_wl[168] = wl_bus[8]; - assign sram_blwl_wl[169] = wl_bus[8]; - assign sram_blwl_wl[170] = wl_bus[8]; - assign sram_blwl_wl[171] = wl_bus[9]; - assign sram_blwl_wl[172] = wl_bus[9]; - assign sram_blwl_wl[173] = wl_bus[9]; - assign sram_blwl_wl[174] = wl_bus[9]; - assign sram_blwl_wl[175] = wl_bus[9]; - assign sram_blwl_wl[176] = wl_bus[9]; - assign sram_blwl_wl[177] = wl_bus[9]; - assign sram_blwl_wl[178] = wl_bus[9]; - assign sram_blwl_wl[179] = wl_bus[9]; - assign sram_blwl_wl[180] = wl_bus[9]; - assign sram_blwl_wl[181] = wl_bus[9]; - assign sram_blwl_wl[182] = wl_bus[9]; - assign sram_blwl_wl[183] = wl_bus[9]; - assign sram_blwl_wl[184] = wl_bus[9]; - assign sram_blwl_wl[185] = wl_bus[9]; - assign sram_blwl_wl[186] = wl_bus[9]; - assign sram_blwl_wl[187] = wl_bus[9]; - assign sram_blwl_wl[188] = wl_bus[9]; - assign sram_blwl_wl[189] = wl_bus[9]; - assign sram_blwl_wl[190] = wl_bus[10]; - assign sram_blwl_wl[191] = wl_bus[10]; - assign sram_blwl_wl[192] = wl_bus[10]; - assign sram_blwl_wl[193] = wl_bus[10]; - assign sram_blwl_wl[194] = wl_bus[10]; - assign sram_blwl_wl[195] = wl_bus[10]; - assign sram_blwl_wl[196] = wl_bus[10]; - assign sram_blwl_wl[197] = wl_bus[10]; - assign sram_blwl_wl[198] = wl_bus[10]; - assign sram_blwl_wl[199] = wl_bus[10]; - assign sram_blwl_wl[200] = wl_bus[10]; - assign sram_blwl_wl[201] = wl_bus[10]; - assign sram_blwl_wl[202] = wl_bus[10]; - assign sram_blwl_wl[203] = wl_bus[10]; - assign sram_blwl_wl[204] = wl_bus[10]; - assign sram_blwl_wl[205] = wl_bus[10]; - assign sram_blwl_wl[206] = wl_bus[10]; - assign sram_blwl_wl[207] = wl_bus[10]; - assign sram_blwl_wl[208] = wl_bus[10]; - assign sram_blwl_wl[209] = wl_bus[11]; - assign sram_blwl_wl[210] = wl_bus[11]; - assign sram_blwl_wl[211] = wl_bus[11]; - assign sram_blwl_wl[212] = wl_bus[11]; - assign sram_blwl_wl[213] = wl_bus[11]; - assign sram_blwl_wl[214] = wl_bus[11]; - assign sram_blwl_wl[215] = wl_bus[11]; - assign sram_blwl_wl[216] = wl_bus[11]; - assign sram_blwl_wl[217] = wl_bus[11]; - assign sram_blwl_wl[218] = wl_bus[11]; - assign sram_blwl_wl[219] = wl_bus[11]; - assign sram_blwl_wl[220] = wl_bus[11]; - assign sram_blwl_wl[221] = wl_bus[11]; - assign sram_blwl_wl[222] = wl_bus[11]; - assign sram_blwl_wl[223] = wl_bus[11]; - assign sram_blwl_wl[224] = wl_bus[11]; - assign sram_blwl_wl[225] = wl_bus[11]; - assign sram_blwl_wl[226] = wl_bus[11]; - assign sram_blwl_wl[227] = wl_bus[11]; - assign sram_blwl_wl[228] = wl_bus[12]; - assign sram_blwl_wl[229] = wl_bus[12]; - assign sram_blwl_wl[230] = wl_bus[12]; - assign sram_blwl_wl[231] = wl_bus[12]; - assign sram_blwl_wl[232] = wl_bus[12]; - assign sram_blwl_wl[233] = wl_bus[12]; - assign sram_blwl_wl[234] = wl_bus[12]; - assign sram_blwl_wl[235] = wl_bus[12]; - assign sram_blwl_wl[236] = wl_bus[12]; - assign sram_blwl_wl[237] = wl_bus[12]; - assign sram_blwl_wl[238] = wl_bus[12]; - assign sram_blwl_wl[239] = wl_bus[12]; - assign sram_blwl_wl[240] = wl_bus[12]; - assign sram_blwl_wl[241] = wl_bus[12]; - assign sram_blwl_wl[242] = wl_bus[12]; - assign sram_blwl_wl[243] = wl_bus[12]; - assign sram_blwl_wl[244] = wl_bus[12]; - assign sram_blwl_wl[245] = wl_bus[12]; - assign sram_blwl_wl[246] = wl_bus[12]; - assign sram_blwl_wl[247] = wl_bus[13]; - assign sram_blwl_wl[248] = wl_bus[13]; - assign sram_blwl_wl[249] = wl_bus[13]; - assign sram_blwl_wl[250] = wl_bus[13]; - assign sram_blwl_wl[251] = wl_bus[13]; - assign sram_blwl_wl[252] = wl_bus[13]; - assign sram_blwl_wl[253] = wl_bus[13]; - assign sram_blwl_wl[254] = wl_bus[13]; - assign sram_blwl_wl[255] = wl_bus[13]; - assign sram_blwl_wl[256] = wl_bus[13]; - assign sram_blwl_wl[257] = wl_bus[13]; - assign sram_blwl_wl[258] = wl_bus[13]; - assign sram_blwl_wl[259] = wl_bus[13]; - assign sram_blwl_wl[260] = wl_bus[13]; - assign sram_blwl_wl[261] = wl_bus[13]; - assign sram_blwl_wl[262] = wl_bus[13]; - assign sram_blwl_wl[263] = wl_bus[13]; - assign sram_blwl_wl[264] = wl_bus[13]; - assign sram_blwl_wl[265] = wl_bus[13]; - assign sram_blwl_wl[266] = wl_bus[14]; - assign sram_blwl_wl[267] = wl_bus[14]; - assign sram_blwl_wl[268] = wl_bus[14]; - assign sram_blwl_wl[269] = wl_bus[14]; - assign sram_blwl_wl[270] = wl_bus[14]; - assign sram_blwl_wl[271] = wl_bus[14]; - assign sram_blwl_wl[272] = wl_bus[14]; - assign sram_blwl_wl[273] = wl_bus[14]; - assign sram_blwl_wl[274] = wl_bus[14]; - assign sram_blwl_wl[275] = wl_bus[14]; - assign sram_blwl_wl[276] = wl_bus[14]; - assign sram_blwl_wl[277] = wl_bus[14]; - assign sram_blwl_wl[278] = wl_bus[14]; - assign sram_blwl_wl[279] = wl_bus[14]; - assign sram_blwl_wl[280] = wl_bus[14]; - assign sram_blwl_wl[281] = wl_bus[14]; - assign sram_blwl_wl[282] = wl_bus[14]; - assign sram_blwl_wl[283] = wl_bus[14]; - assign sram_blwl_wl[284] = wl_bus[14]; - assign sram_blwl_wl[285] = wl_bus[15]; - assign sram_blwl_wl[286] = wl_bus[15]; - assign sram_blwl_wl[287] = wl_bus[15]; - assign sram_blwl_wl[288] = wl_bus[15]; - assign sram_blwl_wl[289] = wl_bus[15]; - assign sram_blwl_wl[290] = wl_bus[15]; - assign sram_blwl_wl[291] = wl_bus[15]; - assign sram_blwl_wl[292] = wl_bus[15]; - assign sram_blwl_wl[293] = wl_bus[15]; - assign sram_blwl_wl[294] = wl_bus[15]; - assign sram_blwl_wl[295] = wl_bus[15]; - assign sram_blwl_wl[296] = wl_bus[15]; - assign sram_blwl_wl[297] = wl_bus[15]; - assign sram_blwl_wl[298] = wl_bus[15]; - assign sram_blwl_wl[299] = wl_bus[15]; - assign sram_blwl_wl[300] = wl_bus[15]; - assign sram_blwl_wl[301] = wl_bus[15]; - assign sram_blwl_wl[302] = wl_bus[15]; - assign sram_blwl_wl[303] = wl_bus[15]; - assign sram_blwl_wl[304] = wl_bus[16]; - assign sram_blwl_wl[305] = wl_bus[16]; - assign sram_blwl_wl[306] = wl_bus[16]; - assign sram_blwl_wl[307] = wl_bus[16]; - assign sram_blwl_wl[308] = wl_bus[16]; - assign sram_blwl_wl[309] = wl_bus[16]; - assign sram_blwl_wl[310] = wl_bus[16]; - assign sram_blwl_wl[311] = wl_bus[16]; - assign sram_blwl_wl[312] = wl_bus[16]; - assign sram_blwl_wl[313] = wl_bus[16]; - assign sram_blwl_wl[314] = wl_bus[16]; - assign sram_blwl_wl[315] = wl_bus[16]; - assign sram_blwl_wl[316] = wl_bus[16]; - assign sram_blwl_wl[317] = wl_bus[16]; - assign sram_blwl_wl[318] = wl_bus[16]; - assign sram_blwl_wl[319] = wl_bus[16]; - assign sram_blwl_wl[320] = wl_bus[16]; - assign sram_blwl_wl[321] = wl_bus[16]; - assign sram_blwl_wl[322] = wl_bus[16]; - assign sram_blwl_wl[323] = wl_bus[17]; - assign sram_blwl_wl[324] = wl_bus[17]; - assign sram_blwl_wl[325] = wl_bus[17]; - assign sram_blwl_wl[326] = wl_bus[17]; - assign sram_blwl_wl[327] = wl_bus[17]; - assign sram_blwl_wl[328] = wl_bus[17]; - assign sram_blwl_wl[329] = wl_bus[17]; - assign sram_blwl_wl[330] = wl_bus[17]; - assign sram_blwl_wl[331] = wl_bus[17]; - assign sram_blwl_wl[332] = wl_bus[17]; - assign sram_blwl_wl[333] = wl_bus[17]; - assign sram_blwl_wl[334] = wl_bus[17]; - assign sram_blwl_wl[335] = wl_bus[17]; - assign sram_blwl_wl[336] = wl_bus[17]; - assign sram_blwl_wl[337] = wl_bus[17]; - assign sram_blwl_wl[338] = wl_bus[17]; - assign sram_blwl_wl[339] = wl_bus[17]; - assign sram_blwl_wl[340] = wl_bus[17]; - assign sram_blwl_wl[341] = wl_bus[17]; - assign sram_blwl_wl[342] = wl_bus[18]; - assign sram_blwl_wl[343] = wl_bus[18]; - assign sram_blwl_wl[344] = wl_bus[18]; - assign sram_blwl_wl[345] = wl_bus[18]; - assign sram_blwl_wl[346] = wl_bus[18]; - assign sram_blwl_wl[347] = wl_bus[18]; - assign sram_blwl_wl[348] = wl_bus[18]; - assign sram_blwl_wl[349] = wl_bus[18]; - assign sram_blwl_wl[350] = wl_bus[18]; - assign sram_blwl_wl[351] = wl_bus[18]; - assign sram_blwl_wl[352] = wl_bus[18]; - assign sram_blwl_wl[353] = wl_bus[18]; - assign sram_blwl_wl[354] = wl_bus[18]; - assign sram_blwl_wl[355] = wl_bus[18]; - assign sram_blwl_wl[356] = wl_bus[18]; - assign sram_blwl_wl[357] = wl_bus[18]; - assign sram_blwl_wl[358] = wl_bus[18]; - assign sram_blwl_wl[359] = wl_bus[18]; - assign sram_blwl_wl[360] = wl_bus[18]; -//----- BEGIN Call Grid[1][1] module ----- -grid_1__1_ grid_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - grid_1__1__pin_0__0__0_, - grid_1__1__pin_0__0__4_, - grid_1__1__pin_0__1__1_, - grid_1__1__pin_0__1__5_, - grid_1__1__pin_0__2__2_, - grid_1__1__pin_0__3__3_, -sram_blwl_bl[288:328] , -sram_blwl_wl[288:328] , -sram_blwl_blb[288:328] ); -//----- END call Grid[1][1] module ----- - -//----- BEGIN Call Grid[0][1] module ----- -grid_0__1_ grid_0__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - grid_0__1__pin_0__1__0_, - grid_0__1__pin_0__1__1_, - grid_0__1__pin_0__1__2_, - grid_0__1__pin_0__1__3_, - grid_0__1__pin_0__1__4_, - grid_0__1__pin_0__1__5_, - grid_0__1__pin_0__1__6_, - grid_0__1__pin_0__1__7_, - grid_0__1__pin_0__1__8_, - grid_0__1__pin_0__1__9_, - grid_0__1__pin_0__1__10_, - grid_0__1__pin_0__1__11_, - grid_0__1__pin_0__1__12_, - grid_0__1__pin_0__1__13_, - grid_0__1__pin_0__1__14_, - grid_0__1__pin_0__1__15_, -gfpga_pad_iopad[7:0] , -sram_blwl_bl[329:336] , -sram_blwl_wl[329:336] , -sram_blwl_blb[329:336] ); -//----- END call Grid[0][1] module ----- - -//----- BEGIN Call Grid[2][1] module ----- -grid_2__1_ grid_2__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - grid_2__1__pin_0__3__0_, - grid_2__1__pin_0__3__1_, - grid_2__1__pin_0__3__2_, - grid_2__1__pin_0__3__3_, - grid_2__1__pin_0__3__4_, - grid_2__1__pin_0__3__5_, - grid_2__1__pin_0__3__6_, - grid_2__1__pin_0__3__7_, - grid_2__1__pin_0__3__8_, - grid_2__1__pin_0__3__9_, - grid_2__1__pin_0__3__10_, - grid_2__1__pin_0__3__11_, - grid_2__1__pin_0__3__12_, - grid_2__1__pin_0__3__13_, - grid_2__1__pin_0__3__14_, - grid_2__1__pin_0__3__15_, -gfpga_pad_iopad[15:8] , -sram_blwl_bl[337:344] , -sram_blwl_wl[337:344] , -sram_blwl_blb[337:344] ); -//----- END call Grid[2][1] module ----- - -//----- BEGIN Call Grid[1][0] module ----- -grid_1__0_ grid_1__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - grid_1__0__pin_0__0__0_, - grid_1__0__pin_0__0__1_, - grid_1__0__pin_0__0__2_, - grid_1__0__pin_0__0__3_, - grid_1__0__pin_0__0__4_, - grid_1__0__pin_0__0__5_, - grid_1__0__pin_0__0__6_, - grid_1__0__pin_0__0__7_, - grid_1__0__pin_0__0__8_, - grid_1__0__pin_0__0__9_, - grid_1__0__pin_0__0__10_, - grid_1__0__pin_0__0__11_, - grid_1__0__pin_0__0__12_, - grid_1__0__pin_0__0__13_, - grid_1__0__pin_0__0__14_, - grid_1__0__pin_0__0__15_, -gfpga_pad_iopad[23:16] , -sram_blwl_bl[345:352] , -sram_blwl_wl[345:352] , -sram_blwl_blb[345:352] ); -//----- END call Grid[1][0] module ----- - -//----- BEGIN Call Grid[1][2] module ----- -grid_1__2_ grid_1__2__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - grid_1__2__pin_0__2__0_, - grid_1__2__pin_0__2__1_, - grid_1__2__pin_0__2__2_, - grid_1__2__pin_0__2__3_, - grid_1__2__pin_0__2__4_, - grid_1__2__pin_0__2__5_, - grid_1__2__pin_0__2__6_, - grid_1__2__pin_0__2__7_, - grid_1__2__pin_0__2__8_, - grid_1__2__pin_0__2__9_, - grid_1__2__pin_0__2__10_, - grid_1__2__pin_0__2__11_, - grid_1__2__pin_0__2__12_, - grid_1__2__pin_0__2__13_, - grid_1__2__pin_0__2__14_, - grid_1__2__pin_0__2__15_, -gfpga_pad_iopad[31:24] , -sram_blwl_bl[353:360] , -sram_blwl_wl[353:360] , -sram_blwl_blb[353:360] ); -//----- END call Grid[1][2] module ----- - -//----- BEGIN Call Channel-X [1][0] module ----- -chanx_1__0_ chanx_1__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -chanx_1__0__out_0_, -chanx_1__0__in_1_, -chanx_1__0__out_2_, -chanx_1__0__in_3_, -chanx_1__0__out_4_, -chanx_1__0__in_5_, -chanx_1__0__out_6_, -chanx_1__0__in_7_, -chanx_1__0__out_8_, -chanx_1__0__in_9_, -chanx_1__0__out_10_, -chanx_1__0__in_11_, -chanx_1__0__out_12_, -chanx_1__0__in_13_, -chanx_1__0__out_14_, -chanx_1__0__in_15_, -chanx_1__0__out_16_, -chanx_1__0__in_17_, -chanx_1__0__out_18_, -chanx_1__0__in_19_, -chanx_1__0__out_20_, -chanx_1__0__in_21_, -chanx_1__0__out_22_, -chanx_1__0__in_23_, -chanx_1__0__out_24_, -chanx_1__0__in_25_, -chanx_1__0__out_26_, -chanx_1__0__in_27_, -chanx_1__0__out_28_, -chanx_1__0__in_29_, -chanx_1__0__in_0_, -chanx_1__0__out_1_, -chanx_1__0__in_2_, -chanx_1__0__out_3_, -chanx_1__0__in_4_, -chanx_1__0__out_5_, -chanx_1__0__in_6_, -chanx_1__0__out_7_, -chanx_1__0__in_8_, -chanx_1__0__out_9_, -chanx_1__0__in_10_, -chanx_1__0__out_11_, -chanx_1__0__in_12_, -chanx_1__0__out_13_, -chanx_1__0__in_14_, -chanx_1__0__out_15_, -chanx_1__0__in_16_, -chanx_1__0__out_17_, -chanx_1__0__in_18_, -chanx_1__0__out_19_, -chanx_1__0__in_20_, -chanx_1__0__out_21_, -chanx_1__0__in_22_, -chanx_1__0__out_23_, -chanx_1__0__in_24_, -chanx_1__0__out_25_, -chanx_1__0__in_26_, -chanx_1__0__out_27_, -chanx_1__0__in_28_, -chanx_1__0__out_29_, -chanx_1__0__midout_0_ , -chanx_1__0__midout_1_ , -chanx_1__0__midout_2_ , -chanx_1__0__midout_3_ , -chanx_1__0__midout_4_ , -chanx_1__0__midout_5_ , -chanx_1__0__midout_6_ , -chanx_1__0__midout_7_ , -chanx_1__0__midout_8_ , -chanx_1__0__midout_9_ , -chanx_1__0__midout_10_ , -chanx_1__0__midout_11_ , -chanx_1__0__midout_12_ , -chanx_1__0__midout_13_ , -chanx_1__0__midout_14_ , -chanx_1__0__midout_15_ , -chanx_1__0__midout_16_ , -chanx_1__0__midout_17_ , -chanx_1__0__midout_18_ , -chanx_1__0__midout_19_ , -chanx_1__0__midout_20_ , -chanx_1__0__midout_21_ , -chanx_1__0__midout_22_ , -chanx_1__0__midout_23_ , -chanx_1__0__midout_24_ , -chanx_1__0__midout_25_ , -chanx_1__0__midout_26_ , -chanx_1__0__midout_27_ , -chanx_1__0__midout_28_ , -chanx_1__0__midout_29_ -); -//----- END Call Channel-X [1][0] module ----- -//----- BEGIN Call Channel-X [1][1] module ----- -chanx_1__1_ chanx_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -chanx_1__1__out_0_, -chanx_1__1__in_1_, -chanx_1__1__out_2_, -chanx_1__1__in_3_, -chanx_1__1__out_4_, -chanx_1__1__in_5_, -chanx_1__1__out_6_, -chanx_1__1__in_7_, -chanx_1__1__out_8_, -chanx_1__1__in_9_, -chanx_1__1__out_10_, -chanx_1__1__in_11_, -chanx_1__1__out_12_, -chanx_1__1__in_13_, -chanx_1__1__out_14_, -chanx_1__1__in_15_, -chanx_1__1__out_16_, -chanx_1__1__in_17_, -chanx_1__1__out_18_, -chanx_1__1__in_19_, -chanx_1__1__out_20_, -chanx_1__1__in_21_, -chanx_1__1__out_22_, -chanx_1__1__in_23_, -chanx_1__1__out_24_, -chanx_1__1__in_25_, -chanx_1__1__out_26_, -chanx_1__1__in_27_, -chanx_1__1__out_28_, -chanx_1__1__in_29_, -chanx_1__1__in_0_, -chanx_1__1__out_1_, -chanx_1__1__in_2_, -chanx_1__1__out_3_, -chanx_1__1__in_4_, -chanx_1__1__out_5_, -chanx_1__1__in_6_, -chanx_1__1__out_7_, -chanx_1__1__in_8_, -chanx_1__1__out_9_, -chanx_1__1__in_10_, -chanx_1__1__out_11_, -chanx_1__1__in_12_, -chanx_1__1__out_13_, -chanx_1__1__in_14_, -chanx_1__1__out_15_, -chanx_1__1__in_16_, -chanx_1__1__out_17_, -chanx_1__1__in_18_, -chanx_1__1__out_19_, -chanx_1__1__in_20_, -chanx_1__1__out_21_, -chanx_1__1__in_22_, -chanx_1__1__out_23_, -chanx_1__1__in_24_, -chanx_1__1__out_25_, -chanx_1__1__in_26_, -chanx_1__1__out_27_, -chanx_1__1__in_28_, -chanx_1__1__out_29_, -chanx_1__1__midout_0_ , -chanx_1__1__midout_1_ , -chanx_1__1__midout_2_ , -chanx_1__1__midout_3_ , -chanx_1__1__midout_4_ , -chanx_1__1__midout_5_ , -chanx_1__1__midout_6_ , -chanx_1__1__midout_7_ , -chanx_1__1__midout_8_ , -chanx_1__1__midout_9_ , -chanx_1__1__midout_10_ , -chanx_1__1__midout_11_ , -chanx_1__1__midout_12_ , -chanx_1__1__midout_13_ , -chanx_1__1__midout_14_ , -chanx_1__1__midout_15_ , -chanx_1__1__midout_16_ , -chanx_1__1__midout_17_ , -chanx_1__1__midout_18_ , -chanx_1__1__midout_19_ , -chanx_1__1__midout_20_ , -chanx_1__1__midout_21_ , -chanx_1__1__midout_22_ , -chanx_1__1__midout_23_ , -chanx_1__1__midout_24_ , -chanx_1__1__midout_25_ , -chanx_1__1__midout_26_ , -chanx_1__1__midout_27_ , -chanx_1__1__midout_28_ , -chanx_1__1__midout_29_ -); -//----- END Call Channel-X [1][1] module ----- -//----- BEGIN call Channel-Y [0][1] module ----- - -chany_0__1_ chany_0__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -chany_0__1__out_0_, -chany_0__1__in_1_, -chany_0__1__out_2_, -chany_0__1__in_3_, -chany_0__1__out_4_, -chany_0__1__in_5_, -chany_0__1__out_6_, -chany_0__1__in_7_, -chany_0__1__out_8_, -chany_0__1__in_9_, -chany_0__1__out_10_, -chany_0__1__in_11_, -chany_0__1__out_12_, -chany_0__1__in_13_, -chany_0__1__out_14_, -chany_0__1__in_15_, -chany_0__1__out_16_, -chany_0__1__in_17_, -chany_0__1__out_18_, -chany_0__1__in_19_, -chany_0__1__out_20_, -chany_0__1__in_21_, -chany_0__1__out_22_, -chany_0__1__in_23_, -chany_0__1__out_24_, -chany_0__1__in_25_, -chany_0__1__out_26_, -chany_0__1__in_27_, -chany_0__1__out_28_, -chany_0__1__in_29_, -chany_0__1__in_0_, -chany_0__1__out_1_, -chany_0__1__in_2_, -chany_0__1__out_3_, -chany_0__1__in_4_, -chany_0__1__out_5_, -chany_0__1__in_6_, -chany_0__1__out_7_, -chany_0__1__in_8_, -chany_0__1__out_9_, -chany_0__1__in_10_, -chany_0__1__out_11_, -chany_0__1__in_12_, -chany_0__1__out_13_, -chany_0__1__in_14_, -chany_0__1__out_15_, -chany_0__1__in_16_, -chany_0__1__out_17_, -chany_0__1__in_18_, -chany_0__1__out_19_, -chany_0__1__in_20_, -chany_0__1__out_21_, -chany_0__1__in_22_, -chany_0__1__out_23_, -chany_0__1__in_24_, -chany_0__1__out_25_, -chany_0__1__in_26_, -chany_0__1__out_27_, -chany_0__1__in_28_, -chany_0__1__out_29_, -chany_0__1__midout_0_ , -chany_0__1__midout_1_ , -chany_0__1__midout_2_ , -chany_0__1__midout_3_ , -chany_0__1__midout_4_ , -chany_0__1__midout_5_ , -chany_0__1__midout_6_ , -chany_0__1__midout_7_ , -chany_0__1__midout_8_ , -chany_0__1__midout_9_ , -chany_0__1__midout_10_ , -chany_0__1__midout_11_ , -chany_0__1__midout_12_ , -chany_0__1__midout_13_ , -chany_0__1__midout_14_ , -chany_0__1__midout_15_ , -chany_0__1__midout_16_ , -chany_0__1__midout_17_ , -chany_0__1__midout_18_ , -chany_0__1__midout_19_ , -chany_0__1__midout_20_ , -chany_0__1__midout_21_ , -chany_0__1__midout_22_ , -chany_0__1__midout_23_ , -chany_0__1__midout_24_ , -chany_0__1__midout_25_ , -chany_0__1__midout_26_ , -chany_0__1__midout_27_ , -chany_0__1__midout_28_ , -chany_0__1__midout_29_ -); -//----- END call Channel-Y [0][1] module ----- - -//----- BEGIN call Channel-Y [1][1] module ----- - -chany_1__1_ chany_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -chany_1__1__out_0_, -chany_1__1__in_1_, -chany_1__1__out_2_, -chany_1__1__in_3_, -chany_1__1__out_4_, -chany_1__1__in_5_, -chany_1__1__out_6_, -chany_1__1__in_7_, -chany_1__1__out_8_, -chany_1__1__in_9_, -chany_1__1__out_10_, -chany_1__1__in_11_, -chany_1__1__out_12_, -chany_1__1__in_13_, -chany_1__1__out_14_, -chany_1__1__in_15_, -chany_1__1__out_16_, -chany_1__1__in_17_, -chany_1__1__out_18_, -chany_1__1__in_19_, -chany_1__1__out_20_, -chany_1__1__in_21_, -chany_1__1__out_22_, -chany_1__1__in_23_, -chany_1__1__out_24_, -chany_1__1__in_25_, -chany_1__1__out_26_, -chany_1__1__in_27_, -chany_1__1__out_28_, -chany_1__1__in_29_, -chany_1__1__in_0_, -chany_1__1__out_1_, -chany_1__1__in_2_, -chany_1__1__out_3_, -chany_1__1__in_4_, -chany_1__1__out_5_, -chany_1__1__in_6_, -chany_1__1__out_7_, -chany_1__1__in_8_, -chany_1__1__out_9_, -chany_1__1__in_10_, -chany_1__1__out_11_, -chany_1__1__in_12_, -chany_1__1__out_13_, -chany_1__1__in_14_, -chany_1__1__out_15_, -chany_1__1__in_16_, -chany_1__1__out_17_, -chany_1__1__in_18_, -chany_1__1__out_19_, -chany_1__1__in_20_, -chany_1__1__out_21_, -chany_1__1__in_22_, -chany_1__1__out_23_, -chany_1__1__in_24_, -chany_1__1__out_25_, -chany_1__1__in_26_, -chany_1__1__out_27_, -chany_1__1__in_28_, -chany_1__1__out_29_, -chany_1__1__midout_0_ , -chany_1__1__midout_1_ , -chany_1__1__midout_2_ , -chany_1__1__midout_3_ , -chany_1__1__midout_4_ , -chany_1__1__midout_5_ , -chany_1__1__midout_6_ , -chany_1__1__midout_7_ , -chany_1__1__midout_8_ , -chany_1__1__midout_9_ , -chany_1__1__midout_10_ , -chany_1__1__midout_11_ , -chany_1__1__midout_12_ , -chany_1__1__midout_13_ , -chany_1__1__midout_14_ , -chany_1__1__midout_15_ , -chany_1__1__midout_16_ , -chany_1__1__midout_17_ , -chany_1__1__midout_18_ , -chany_1__1__midout_19_ , -chany_1__1__midout_20_ , -chany_1__1__midout_21_ , -chany_1__1__midout_22_ , -chany_1__1__midout_23_ , -chany_1__1__midout_24_ , -chany_1__1__midout_25_ , -chany_1__1__midout_26_ , -chany_1__1__midout_27_ , -chany_1__1__midout_28_ , -chany_1__1__midout_29_ -); -//----- END call Channel-Y [1][1] module ----- - -//----- BEGIN Call Connection Box-X direction [1][0] module ----- -cbx_1__0_ cbx_1__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- right side inputs: channel track middle outputs ----- -chanx_1__0__midout_0_, -chanx_1__0__midout_1_, -chanx_1__0__midout_2_, -chanx_1__0__midout_3_, -chanx_1__0__midout_4_, -chanx_1__0__midout_5_, -chanx_1__0__midout_6_, -chanx_1__0__midout_7_, -chanx_1__0__midout_8_, -chanx_1__0__midout_9_, -chanx_1__0__midout_10_, -chanx_1__0__midout_11_, -chanx_1__0__midout_12_, -chanx_1__0__midout_13_, -chanx_1__0__midout_14_, -chanx_1__0__midout_15_, -chanx_1__0__midout_16_, -chanx_1__0__midout_17_, -chanx_1__0__midout_18_, -chanx_1__0__midout_19_, -chanx_1__0__midout_20_, -chanx_1__0__midout_21_, -chanx_1__0__midout_22_, -chanx_1__0__midout_23_, -chanx_1__0__midout_24_, -chanx_1__0__midout_25_, -chanx_1__0__midout_26_, -chanx_1__0__midout_27_, -chanx_1__0__midout_28_, -chanx_1__0__midout_29_, -//----- top side outputs: CLB input pins ----- - grid_1__1__pin_0__2__2_, -//----- bottom side outputs: CLB input pins ----- - grid_1__0__pin_0__0__0_, - grid_1__0__pin_0__0__2_, - grid_1__0__pin_0__0__4_, - grid_1__0__pin_0__0__6_, - grid_1__0__pin_0__0__8_, - grid_1__0__pin_0__0__10_, - grid_1__0__pin_0__0__12_, - grid_1__0__pin_0__0__14_, -sram_blwl_bl[144:179] , -sram_blwl_wl[144:179] , -sram_blwl_blb[144:179] ); -//----- END call Connection Box-X direction [1][0] module ----- - -//----- BEGIN Call Connection Box-X direction [1][1] module ----- -cbx_1__1_ cbx_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- right side inputs: channel track middle outputs ----- -chanx_1__1__midout_0_, -chanx_1__1__midout_1_, -chanx_1__1__midout_2_, -chanx_1__1__midout_3_, -chanx_1__1__midout_4_, -chanx_1__1__midout_5_, -chanx_1__1__midout_6_, -chanx_1__1__midout_7_, -chanx_1__1__midout_8_, -chanx_1__1__midout_9_, -chanx_1__1__midout_10_, -chanx_1__1__midout_11_, -chanx_1__1__midout_12_, -chanx_1__1__midout_13_, -chanx_1__1__midout_14_, -chanx_1__1__midout_15_, -chanx_1__1__midout_16_, -chanx_1__1__midout_17_, -chanx_1__1__midout_18_, -chanx_1__1__midout_19_, -chanx_1__1__midout_20_, -chanx_1__1__midout_21_, -chanx_1__1__midout_22_, -chanx_1__1__midout_23_, -chanx_1__1__midout_24_, -chanx_1__1__midout_25_, -chanx_1__1__midout_26_, -chanx_1__1__midout_27_, -chanx_1__1__midout_28_, -chanx_1__1__midout_29_, -//----- top side outputs: CLB input pins ----- - grid_1__2__pin_0__2__0_, - grid_1__2__pin_0__2__2_, - grid_1__2__pin_0__2__4_, - grid_1__2__pin_0__2__6_, - grid_1__2__pin_0__2__8_, - grid_1__2__pin_0__2__10_, - grid_1__2__pin_0__2__12_, - grid_1__2__pin_0__2__14_, -//----- bottom side outputs: CLB input pins ----- - grid_1__1__pin_0__0__0_, -sram_blwl_bl[180:215] , -sram_blwl_wl[180:215] , -sram_blwl_blb[180:215] ); -//----- END call Connection Box-X direction [1][1] module ----- - -//----- BEGIN Call Connection Box-Y direction [0][1] module ----- -cby_0__1_ cby_0__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side inputs: channel track middle outputs ----- -chany_0__1__midout_0_, -chany_0__1__midout_1_, -chany_0__1__midout_2_, -chany_0__1__midout_3_, -chany_0__1__midout_4_, -chany_0__1__midout_5_, -chany_0__1__midout_6_, -chany_0__1__midout_7_, -chany_0__1__midout_8_, -chany_0__1__midout_9_, -chany_0__1__midout_10_, -chany_0__1__midout_11_, -chany_0__1__midout_12_, -chany_0__1__midout_13_, -chany_0__1__midout_14_, -chany_0__1__midout_15_, -chany_0__1__midout_16_, -chany_0__1__midout_17_, -chany_0__1__midout_18_, -chany_0__1__midout_19_, -chany_0__1__midout_20_, -chany_0__1__midout_21_, -chany_0__1__midout_22_, -chany_0__1__midout_23_, -chany_0__1__midout_24_, -chany_0__1__midout_25_, -chany_0__1__midout_26_, -chany_0__1__midout_27_, -chany_0__1__midout_28_, -chany_0__1__midout_29_, -//----- right side outputs: CLB input pins ----- - grid_1__1__pin_0__3__3_, -//----- left side outputs: CLB input pins ----- - grid_0__1__pin_0__1__0_, - grid_0__1__pin_0__1__2_, - grid_0__1__pin_0__1__4_, - grid_0__1__pin_0__1__6_, - grid_0__1__pin_0__1__8_, - grid_0__1__pin_0__1__10_, - grid_0__1__pin_0__1__12_, - grid_0__1__pin_0__1__14_, -sram_blwl_bl[216:251] , -sram_blwl_wl[216:251] , -sram_blwl_blb[216:251] ); -//----- END call Connection Box-Y direction [0][1] module ----- - -//----- BEGIN Call Connection Box-Y direction [1][1] module ----- -cby_1__1_ cby_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side inputs: channel track middle outputs ----- -chany_1__1__midout_0_, -chany_1__1__midout_1_, -chany_1__1__midout_2_, -chany_1__1__midout_3_, -chany_1__1__midout_4_, -chany_1__1__midout_5_, -chany_1__1__midout_6_, -chany_1__1__midout_7_, -chany_1__1__midout_8_, -chany_1__1__midout_9_, -chany_1__1__midout_10_, -chany_1__1__midout_11_, -chany_1__1__midout_12_, -chany_1__1__midout_13_, -chany_1__1__midout_14_, -chany_1__1__midout_15_, -chany_1__1__midout_16_, -chany_1__1__midout_17_, -chany_1__1__midout_18_, -chany_1__1__midout_19_, -chany_1__1__midout_20_, -chany_1__1__midout_21_, -chany_1__1__midout_22_, -chany_1__1__midout_23_, -chany_1__1__midout_24_, -chany_1__1__midout_25_, -chany_1__1__midout_26_, -chany_1__1__midout_27_, -chany_1__1__midout_28_, -chany_1__1__midout_29_, -//----- right side outputs: CLB input pins ----- - grid_2__1__pin_0__3__0_, - grid_2__1__pin_0__3__2_, - grid_2__1__pin_0__3__4_, - grid_2__1__pin_0__3__6_, - grid_2__1__pin_0__3__8_, - grid_2__1__pin_0__3__10_, - grid_2__1__pin_0__3__12_, - grid_2__1__pin_0__3__14_, -//----- left side outputs: CLB input pins ----- - grid_1__1__pin_0__1__1_, - grid_1__1__pin_0__1__5_, -sram_blwl_bl[252:287] , -sram_blwl_wl[252:287] , -sram_blwl_blb[252:287] ); -//----- END call Connection Box-Y direction [1][1] module ----- - -//----- BEGIN call module Switch blocks [0][0] ----- -sb_0__0_ sb_0__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side channel ports----- -chany_0__1__out_0_, chany_0__1__in_1_, chany_0__1__out_2_, chany_0__1__in_3_, chany_0__1__out_4_, chany_0__1__in_5_, chany_0__1__out_6_, chany_0__1__in_7_, chany_0__1__out_8_, chany_0__1__in_9_, chany_0__1__out_10_, chany_0__1__in_11_, chany_0__1__out_12_, chany_0__1__in_13_, chany_0__1__out_14_, chany_0__1__in_15_, chany_0__1__out_16_, chany_0__1__in_17_, chany_0__1__out_18_, chany_0__1__in_19_, chany_0__1__out_20_, chany_0__1__in_21_, chany_0__1__out_22_, chany_0__1__in_23_, chany_0__1__out_24_, chany_0__1__in_25_, chany_0__1__out_26_, chany_0__1__in_27_, chany_0__1__out_28_, chany_0__1__in_29_, -//----- top side inputs: CLB output pins ----- - grid_0__1__pin_0__1__1_, grid_0__1__pin_0__1__3_, grid_0__1__pin_0__1__5_, grid_0__1__pin_0__1__7_, grid_0__1__pin_0__1__9_, grid_0__1__pin_0__1__11_, grid_0__1__pin_0__1__13_, grid_0__1__pin_0__1__15_, -//----- right side channel ports----- -chanx_1__0__out_0_, chanx_1__0__in_1_, chanx_1__0__out_2_, chanx_1__0__in_3_, chanx_1__0__out_4_, chanx_1__0__in_5_, chanx_1__0__out_6_, chanx_1__0__in_7_, chanx_1__0__out_8_, chanx_1__0__in_9_, chanx_1__0__out_10_, chanx_1__0__in_11_, chanx_1__0__out_12_, chanx_1__0__in_13_, chanx_1__0__out_14_, chanx_1__0__in_15_, chanx_1__0__out_16_, chanx_1__0__in_17_, chanx_1__0__out_18_, chanx_1__0__in_19_, chanx_1__0__out_20_, chanx_1__0__in_21_, chanx_1__0__out_22_, chanx_1__0__in_23_, chanx_1__0__out_24_, chanx_1__0__in_25_, chanx_1__0__out_26_, chanx_1__0__in_27_, chanx_1__0__out_28_, chanx_1__0__in_29_, -//----- right side inputs: CLB output pins ----- - grid_1__0__pin_0__0__1_, grid_1__0__pin_0__0__3_, grid_1__0__pin_0__0__5_, grid_1__0__pin_0__0__7_, grid_1__0__pin_0__0__9_, grid_1__0__pin_0__0__11_, grid_1__0__pin_0__0__13_, grid_1__0__pin_0__0__15_, -//----- bottom side channel ports----- - -//----- bottom side inputs: CLB output pins ----- - -//----- left side channel ports----- - -//----- left side inputs: CLB output pins ----- - -sram_blwl_bl[0:33] , -sram_blwl_wl[0:33] , -sram_blwl_blb[0:33] ); -//----- END call module Switch blocks [0][0] ----- - -//----- BEGIN call module Switch blocks [0][1] ----- -sb_0__1_ sb_0__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side channel ports----- - -//----- top side inputs: CLB output pins ----- - -//----- right side channel ports----- -chanx_1__1__out_0_, chanx_1__1__in_1_, chanx_1__1__out_2_, chanx_1__1__in_3_, chanx_1__1__out_4_, chanx_1__1__in_5_, chanx_1__1__out_6_, chanx_1__1__in_7_, chanx_1__1__out_8_, chanx_1__1__in_9_, chanx_1__1__out_10_, chanx_1__1__in_11_, chanx_1__1__out_12_, chanx_1__1__in_13_, chanx_1__1__out_14_, chanx_1__1__in_15_, chanx_1__1__out_16_, chanx_1__1__in_17_, chanx_1__1__out_18_, chanx_1__1__in_19_, chanx_1__1__out_20_, chanx_1__1__in_21_, chanx_1__1__out_22_, chanx_1__1__in_23_, chanx_1__1__out_24_, chanx_1__1__in_25_, chanx_1__1__out_26_, chanx_1__1__in_27_, chanx_1__1__out_28_, chanx_1__1__in_29_, -//----- right side inputs: CLB output pins ----- - grid_1__2__pin_0__2__1_, grid_1__2__pin_0__2__3_, grid_1__2__pin_0__2__5_, grid_1__2__pin_0__2__7_, grid_1__2__pin_0__2__9_, grid_1__2__pin_0__2__11_, grid_1__2__pin_0__2__13_, grid_1__2__pin_0__2__15_, grid_1__1__pin_0__0__4_, -//----- bottom side channel ports----- -chany_0__1__in_0_, chany_0__1__out_1_, chany_0__1__in_2_, chany_0__1__out_3_, chany_0__1__in_4_, chany_0__1__out_5_, chany_0__1__in_6_, chany_0__1__out_7_, chany_0__1__in_8_, chany_0__1__out_9_, chany_0__1__in_10_, chany_0__1__out_11_, chany_0__1__in_12_, chany_0__1__out_13_, chany_0__1__in_14_, chany_0__1__out_15_, chany_0__1__in_16_, chany_0__1__out_17_, chany_0__1__in_18_, chany_0__1__out_19_, chany_0__1__in_20_, chany_0__1__out_21_, chany_0__1__in_22_, chany_0__1__out_23_, chany_0__1__in_24_, chany_0__1__out_25_, chany_0__1__in_26_, chany_0__1__out_27_, chany_0__1__in_28_, chany_0__1__out_29_, -//----- bottom side inputs: CLB output pins ----- - grid_0__1__pin_0__1__1_, grid_0__1__pin_0__1__3_, grid_0__1__pin_0__1__5_, grid_0__1__pin_0__1__7_, grid_0__1__pin_0__1__9_, grid_0__1__pin_0__1__11_, grid_0__1__pin_0__1__13_, grid_0__1__pin_0__1__15_, -//----- left side channel ports----- - -//----- left side inputs: CLB output pins ----- - -sram_blwl_bl[34:71] , -sram_blwl_wl[34:71] , -sram_blwl_blb[34:71] ); -//----- END call module Switch blocks [0][1] ----- - -//----- BEGIN call module Switch blocks [1][0] ----- -sb_1__0_ sb_1__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side channel ports----- -chany_1__1__out_0_, chany_1__1__in_1_, chany_1__1__out_2_, chany_1__1__in_3_, chany_1__1__out_4_, chany_1__1__in_5_, chany_1__1__out_6_, chany_1__1__in_7_, chany_1__1__out_8_, chany_1__1__in_9_, chany_1__1__out_10_, chany_1__1__in_11_, chany_1__1__out_12_, chany_1__1__in_13_, chany_1__1__out_14_, chany_1__1__in_15_, chany_1__1__out_16_, chany_1__1__in_17_, chany_1__1__out_18_, chany_1__1__in_19_, chany_1__1__out_20_, chany_1__1__in_21_, chany_1__1__out_22_, chany_1__1__in_23_, chany_1__1__out_24_, chany_1__1__in_25_, chany_1__1__out_26_, chany_1__1__in_27_, chany_1__1__out_28_, chany_1__1__in_29_, -//----- top side inputs: CLB output pins ----- - grid_2__1__pin_0__3__1_, grid_2__1__pin_0__3__3_, grid_2__1__pin_0__3__5_, grid_2__1__pin_0__3__7_, grid_2__1__pin_0__3__9_, grid_2__1__pin_0__3__11_, grid_2__1__pin_0__3__13_, grid_2__1__pin_0__3__15_, -//----- right side channel ports----- - -//----- right side inputs: CLB output pins ----- - -//----- bottom side channel ports----- - -//----- bottom side inputs: CLB output pins ----- - -//----- left side channel ports----- -chanx_1__0__in_0_, chanx_1__0__out_1_, chanx_1__0__in_2_, chanx_1__0__out_3_, chanx_1__0__in_4_, chanx_1__0__out_5_, chanx_1__0__in_6_, chanx_1__0__out_7_, chanx_1__0__in_8_, chanx_1__0__out_9_, chanx_1__0__in_10_, chanx_1__0__out_11_, chanx_1__0__in_12_, chanx_1__0__out_13_, chanx_1__0__in_14_, chanx_1__0__out_15_, chanx_1__0__in_16_, chanx_1__0__out_17_, chanx_1__0__in_18_, chanx_1__0__out_19_, chanx_1__0__in_20_, chanx_1__0__out_21_, chanx_1__0__in_22_, chanx_1__0__out_23_, chanx_1__0__in_24_, chanx_1__0__out_25_, chanx_1__0__in_26_, chanx_1__0__out_27_, chanx_1__0__in_28_, chanx_1__0__out_29_, -//----- left side inputs: CLB output pins ----- - grid_1__0__pin_0__0__1_, grid_1__0__pin_0__0__3_, grid_1__0__pin_0__0__5_, grid_1__0__pin_0__0__7_, grid_1__0__pin_0__0__9_, grid_1__0__pin_0__0__11_, grid_1__0__pin_0__0__13_, grid_1__0__pin_0__0__15_, -sram_blwl_bl[72:105] , -sram_blwl_wl[72:105] , -sram_blwl_blb[72:105] ); -//----- END call module Switch blocks [1][0] ----- - -//----- BEGIN call module Switch blocks [1][1] ----- -sb_1__1_ sb_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side channel ports----- - -//----- top side inputs: CLB output pins ----- - -//----- right side channel ports----- - -//----- right side inputs: CLB output pins ----- - -//----- bottom side channel ports----- -chany_1__1__in_0_, chany_1__1__out_1_, chany_1__1__in_2_, chany_1__1__out_3_, chany_1__1__in_4_, chany_1__1__out_5_, chany_1__1__in_6_, chany_1__1__out_7_, chany_1__1__in_8_, chany_1__1__out_9_, chany_1__1__in_10_, chany_1__1__out_11_, chany_1__1__in_12_, chany_1__1__out_13_, chany_1__1__in_14_, chany_1__1__out_15_, chany_1__1__in_16_, chany_1__1__out_17_, chany_1__1__in_18_, chany_1__1__out_19_, chany_1__1__in_20_, chany_1__1__out_21_, chany_1__1__in_22_, chany_1__1__out_23_, chany_1__1__in_24_, chany_1__1__out_25_, chany_1__1__in_26_, chany_1__1__out_27_, chany_1__1__in_28_, chany_1__1__out_29_, -//----- bottom side inputs: CLB output pins ----- - grid_2__1__pin_0__3__1_, grid_2__1__pin_0__3__3_, grid_2__1__pin_0__3__5_, grid_2__1__pin_0__3__7_, grid_2__1__pin_0__3__9_, grid_2__1__pin_0__3__11_, grid_2__1__pin_0__3__13_, grid_2__1__pin_0__3__15_, -//----- left side channel ports----- -chanx_1__1__in_0_, chanx_1__1__out_1_, chanx_1__1__in_2_, chanx_1__1__out_3_, chanx_1__1__in_4_, chanx_1__1__out_5_, chanx_1__1__in_6_, chanx_1__1__out_7_, chanx_1__1__in_8_, chanx_1__1__out_9_, chanx_1__1__in_10_, chanx_1__1__out_11_, chanx_1__1__in_12_, chanx_1__1__out_13_, chanx_1__1__in_14_, chanx_1__1__out_15_, chanx_1__1__in_16_, chanx_1__1__out_17_, chanx_1__1__in_18_, chanx_1__1__out_19_, chanx_1__1__in_20_, chanx_1__1__out_21_, chanx_1__1__in_22_, chanx_1__1__out_23_, chanx_1__1__in_24_, chanx_1__1__out_25_, chanx_1__1__in_26_, chanx_1__1__out_27_, chanx_1__1__in_28_, chanx_1__1__out_29_, -//----- left side inputs: CLB output pins ----- - grid_1__2__pin_0__2__1_, grid_1__2__pin_0__2__3_, grid_1__2__pin_0__2__5_, grid_1__2__pin_0__2__7_, grid_1__2__pin_0__2__9_, grid_1__2__pin_0__2__11_, grid_1__2__pin_0__2__13_, grid_1__2__pin_0__2__15_, grid_1__1__pin_0__0__4_, -sram_blwl_bl[106:143] , -sram_blwl_wl[106:143] , -sram_blwl_blb[106:143] ); -//----- END call module Switch blocks [1][1] ----- - -//----- BEGIN CLB to CLB Direct Connections ----- -//----- END CLB to CLB Direct Connections ----- -//----- BEGIN call decoders for memory bank controller ----- -bl_decoder5to19 mem_bank_bl_decoder (en_bl, addr_bl[4:0], data_in, bl_bus[0:18]); -wl_decoder5to19 mem_bank_wl_decoder (en_wl, addr_wl[4:0], wl_bus[0:18]); -//----- END call decoders for memory bank controller ----- - -endmodule diff --git a/examples/verilog_test_example_1/lb/grid_0_1.v b/examples/verilog_test_example_1/lb/grid_0_1.v deleted file mode 100644 index 7cfdb0585..000000000 --- a/examples/verilog_test_example_1/lb/grid_0_1.v +++ /dev/null @@ -1,694 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Physical Logic Block [0][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Grid[0][1] type_descriptor: io[0] ----- -//----- IO Verilog module: grid_0__1__io_0__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_0__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [0:0] gfpga_pad_iopad -, -input [329:329] sram_blwl_bl , -input [329:329] sram_blwl_wl , -input [329:329] sram_blwl_blb ); -wire [329:329] sram_blwl_out ; -wire [329:329] sram_blwl_outb ; -wire [329:329] sram_blwl_329_configbus0; -wire [329:329] sram_blwl_329_configbus1; -wire [329:329] sram_blwl_329_configbus0_b; -assign sram_blwl_329_configbus0[329:329] = sram_blwl_bl[329:329] ; -assign sram_blwl_329_configbus1[329:329] = sram_blwl_wl[329:329] ; -assign sram_blwl_329_configbus0_b[329:329] = sram_blwl_blb[329:329] ; -iopad iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[0], sram_blwl_out[329:329] , sram_blwl_outb[329:329] ); -sram6T_blwl sram_blwl_329_ (sram_blwl_out[329], sram_blwl_out[329], sram_blwl_outb[329], sram_blwl_329_configbus0[329:329], sram_blwl_329_configbus1[329:329] , sram_blwl_329_configbus0_b[329:329] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_0__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_0__mode_io_phy_ ----- -module grid_0__1__io_0__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [0:0] gfpga_pad_iopad , -input [329:329] sram_blwl_bl , -input [329:329] sram_blwl_wl , -input [329:329] sram_blwl_blb ); -grid_0__1__io_0__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[0:0] , -sram_blwl_bl[329:329] , -sram_blwl_wl[329:329] , -sram_blwl_blb[329:329] ); -direct_interc direct_interc_14_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_15_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_0__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[1] ----- -//----- IO Verilog module: grid_0__1__io_1__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_1__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [1:1] gfpga_pad_iopad -, -input [330:330] sram_blwl_bl , -input [330:330] sram_blwl_wl , -input [330:330] sram_blwl_blb ); -wire [330:330] sram_blwl_out ; -wire [330:330] sram_blwl_outb ; -wire [330:330] sram_blwl_330_configbus0; -wire [330:330] sram_blwl_330_configbus1; -wire [330:330] sram_blwl_330_configbus0_b; -assign sram_blwl_330_configbus0[330:330] = sram_blwl_bl[330:330] ; -assign sram_blwl_330_configbus1[330:330] = sram_blwl_wl[330:330] ; -assign sram_blwl_330_configbus0_b[330:330] = sram_blwl_blb[330:330] ; -iopad iopad_1_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[1], sram_blwl_out[330:330] , sram_blwl_outb[330:330] ); -sram6T_blwl sram_blwl_330_ (sram_blwl_out[330], sram_blwl_out[330], sram_blwl_outb[330], sram_blwl_330_configbus0[330:330], sram_blwl_330_configbus1[330:330] , sram_blwl_330_configbus0_b[330:330] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_1__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_1__mode_io_phy_ ----- -module grid_0__1__io_1__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [1:1] gfpga_pad_iopad , -input [330:330] sram_blwl_bl , -input [330:330] sram_blwl_wl , -input [330:330] sram_blwl_blb ); -grid_0__1__io_1__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[1:1] , -sram_blwl_bl[330:330] , -sram_blwl_wl[330:330] , -sram_blwl_blb[330:330] ); -direct_interc direct_interc_16_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_17_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_1__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[2] ----- -//----- IO Verilog module: grid_0__1__io_2__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_2__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [2:2] gfpga_pad_iopad -, -input [331:331] sram_blwl_bl , -input [331:331] sram_blwl_wl , -input [331:331] sram_blwl_blb ); -wire [331:331] sram_blwl_out ; -wire [331:331] sram_blwl_outb ; -wire [331:331] sram_blwl_331_configbus0; -wire [331:331] sram_blwl_331_configbus1; -wire [331:331] sram_blwl_331_configbus0_b; -assign sram_blwl_331_configbus0[331:331] = sram_blwl_bl[331:331] ; -assign sram_blwl_331_configbus1[331:331] = sram_blwl_wl[331:331] ; -assign sram_blwl_331_configbus0_b[331:331] = sram_blwl_blb[331:331] ; -iopad iopad_2_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[2], sram_blwl_out[331:331] , sram_blwl_outb[331:331] ); -sram6T_blwl sram_blwl_331_ (sram_blwl_out[331], sram_blwl_out[331], sram_blwl_outb[331], sram_blwl_331_configbus0[331:331], sram_blwl_331_configbus1[331:331] , sram_blwl_331_configbus0_b[331:331] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_2__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_2__mode_io_phy_ ----- -module grid_0__1__io_2__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [2:2] gfpga_pad_iopad , -input [331:331] sram_blwl_bl , -input [331:331] sram_blwl_wl , -input [331:331] sram_blwl_blb ); -grid_0__1__io_2__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[2:2] , -sram_blwl_bl[331:331] , -sram_blwl_wl[331:331] , -sram_blwl_blb[331:331] ); -direct_interc direct_interc_18_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_19_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_2__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[3] ----- -//----- IO Verilog module: grid_0__1__io_3__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_3__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [3:3] gfpga_pad_iopad -, -input [332:332] sram_blwl_bl , -input [332:332] sram_blwl_wl , -input [332:332] sram_blwl_blb ); -wire [332:332] sram_blwl_out ; -wire [332:332] sram_blwl_outb ; -wire [332:332] sram_blwl_332_configbus0; -wire [332:332] sram_blwl_332_configbus1; -wire [332:332] sram_blwl_332_configbus0_b; -assign sram_blwl_332_configbus0[332:332] = sram_blwl_bl[332:332] ; -assign sram_blwl_332_configbus1[332:332] = sram_blwl_wl[332:332] ; -assign sram_blwl_332_configbus0_b[332:332] = sram_blwl_blb[332:332] ; -iopad iopad_3_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[3], sram_blwl_out[332:332] , sram_blwl_outb[332:332] ); -sram6T_blwl sram_blwl_332_ (sram_blwl_out[332], sram_blwl_out[332], sram_blwl_outb[332], sram_blwl_332_configbus0[332:332], sram_blwl_332_configbus1[332:332] , sram_blwl_332_configbus0_b[332:332] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_3__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_3__mode_io_phy_ ----- -module grid_0__1__io_3__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [3:3] gfpga_pad_iopad , -input [332:332] sram_blwl_bl , -input [332:332] sram_blwl_wl , -input [332:332] sram_blwl_blb ); -grid_0__1__io_3__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[3:3] , -sram_blwl_bl[332:332] , -sram_blwl_wl[332:332] , -sram_blwl_blb[332:332] ); -direct_interc direct_interc_20_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_21_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_3__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[4] ----- -//----- IO Verilog module: grid_0__1__io_4__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_4__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [4:4] gfpga_pad_iopad -, -input [333:333] sram_blwl_bl , -input [333:333] sram_blwl_wl , -input [333:333] sram_blwl_blb ); -wire [333:333] sram_blwl_out ; -wire [333:333] sram_blwl_outb ; -wire [333:333] sram_blwl_333_configbus0; -wire [333:333] sram_blwl_333_configbus1; -wire [333:333] sram_blwl_333_configbus0_b; -assign sram_blwl_333_configbus0[333:333] = sram_blwl_bl[333:333] ; -assign sram_blwl_333_configbus1[333:333] = sram_blwl_wl[333:333] ; -assign sram_blwl_333_configbus0_b[333:333] = sram_blwl_blb[333:333] ; -iopad iopad_4_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[4], sram_blwl_out[333:333] , sram_blwl_outb[333:333] ); -sram6T_blwl sram_blwl_333_ (sram_blwl_out[333], sram_blwl_out[333], sram_blwl_outb[333], sram_blwl_333_configbus0[333:333], sram_blwl_333_configbus1[333:333] , sram_blwl_333_configbus0_b[333:333] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_4__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_4__mode_io_phy_ ----- -module grid_0__1__io_4__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [4:4] gfpga_pad_iopad , -input [333:333] sram_blwl_bl , -input [333:333] sram_blwl_wl , -input [333:333] sram_blwl_blb ); -grid_0__1__io_4__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[4:4] , -sram_blwl_bl[333:333] , -sram_blwl_wl[333:333] , -sram_blwl_blb[333:333] ); -direct_interc direct_interc_22_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_23_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_4__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[5] ----- -//----- IO Verilog module: grid_0__1__io_5__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_5__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [5:5] gfpga_pad_iopad -, -input [334:334] sram_blwl_bl , -input [334:334] sram_blwl_wl , -input [334:334] sram_blwl_blb ); -wire [334:334] sram_blwl_out ; -wire [334:334] sram_blwl_outb ; -wire [334:334] sram_blwl_334_configbus0; -wire [334:334] sram_blwl_334_configbus1; -wire [334:334] sram_blwl_334_configbus0_b; -assign sram_blwl_334_configbus0[334:334] = sram_blwl_bl[334:334] ; -assign sram_blwl_334_configbus1[334:334] = sram_blwl_wl[334:334] ; -assign sram_blwl_334_configbus0_b[334:334] = sram_blwl_blb[334:334] ; -iopad iopad_5_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[5], sram_blwl_out[334:334] , sram_blwl_outb[334:334] ); -sram6T_blwl sram_blwl_334_ (sram_blwl_out[334], sram_blwl_out[334], sram_blwl_outb[334], sram_blwl_334_configbus0[334:334], sram_blwl_334_configbus1[334:334] , sram_blwl_334_configbus0_b[334:334] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_5__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_5__mode_io_phy_ ----- -module grid_0__1__io_5__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [5:5] gfpga_pad_iopad , -input [334:334] sram_blwl_bl , -input [334:334] sram_blwl_wl , -input [334:334] sram_blwl_blb ); -grid_0__1__io_5__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[5:5] , -sram_blwl_bl[334:334] , -sram_blwl_wl[334:334] , -sram_blwl_blb[334:334] ); -direct_interc direct_interc_24_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_25_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_5__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[6] ----- -//----- IO Verilog module: grid_0__1__io_6__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_6__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [6:6] gfpga_pad_iopad -, -input [335:335] sram_blwl_bl , -input [335:335] sram_blwl_wl , -input [335:335] sram_blwl_blb ); -wire [335:335] sram_blwl_out ; -wire [335:335] sram_blwl_outb ; -wire [335:335] sram_blwl_335_configbus0; -wire [335:335] sram_blwl_335_configbus1; -wire [335:335] sram_blwl_335_configbus0_b; -assign sram_blwl_335_configbus0[335:335] = sram_blwl_bl[335:335] ; -assign sram_blwl_335_configbus1[335:335] = sram_blwl_wl[335:335] ; -assign sram_blwl_335_configbus0_b[335:335] = sram_blwl_blb[335:335] ; -iopad iopad_6_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[6], sram_blwl_out[335:335] , sram_blwl_outb[335:335] ); -sram6T_blwl sram_blwl_335_ (sram_blwl_out[335], sram_blwl_out[335], sram_blwl_outb[335], sram_blwl_335_configbus0[335:335], sram_blwl_335_configbus1[335:335] , sram_blwl_335_configbus0_b[335:335] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_6__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_6__mode_io_phy_ ----- -module grid_0__1__io_6__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [6:6] gfpga_pad_iopad , -input [335:335] sram_blwl_bl , -input [335:335] sram_blwl_wl , -input [335:335] sram_blwl_blb ); -grid_0__1__io_6__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[6:6] , -sram_blwl_bl[335:335] , -sram_blwl_wl[335:335] , -sram_blwl_blb[335:335] ); -direct_interc direct_interc_26_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_27_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_6__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[7] ----- -//----- IO Verilog module: grid_0__1__io_7__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_7__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [7:7] gfpga_pad_iopad -, -input [336:336] sram_blwl_bl , -input [336:336] sram_blwl_wl , -input [336:336] sram_blwl_blb ); -wire [336:336] sram_blwl_out ; -wire [336:336] sram_blwl_outb ; -wire [336:336] sram_blwl_336_configbus0; -wire [336:336] sram_blwl_336_configbus1; -wire [336:336] sram_blwl_336_configbus0_b; -assign sram_blwl_336_configbus0[336:336] = sram_blwl_bl[336:336] ; -assign sram_blwl_336_configbus1[336:336] = sram_blwl_wl[336:336] ; -assign sram_blwl_336_configbus0_b[336:336] = sram_blwl_blb[336:336] ; -iopad iopad_7_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[7], sram_blwl_out[336:336] , sram_blwl_outb[336:336] ); -sram6T_blwl sram_blwl_336_ (sram_blwl_out[336], sram_blwl_out[336], sram_blwl_outb[336], sram_blwl_336_configbus0[336:336], sram_blwl_336_configbus1[336:336] , sram_blwl_336_configbus0_b[336:336] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_7__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_7__mode_io_phy_ ----- -module grid_0__1__io_7__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [7:7] gfpga_pad_iopad , -input [336:336] sram_blwl_bl , -input [336:336] sram_blwl_wl , -input [336:336] sram_blwl_blb ); -grid_0__1__io_7__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[7:7] , -sram_blwl_bl[336:336] , -sram_blwl_wl[336:336] , -sram_blwl_blb[336:336] ); -direct_interc direct_interc_28_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_29_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_7__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1], Capactity: 8 ----- -//----- Top Protocol ----- -module grid_0__1_( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input right_height_0__pin_0_, -output right_height_0__pin_1_, -input right_height_0__pin_2_, -output right_height_0__pin_3_, -input right_height_0__pin_4_, -output right_height_0__pin_5_, -input right_height_0__pin_6_, -output right_height_0__pin_7_, -input right_height_0__pin_8_, -output right_height_0__pin_9_, -input right_height_0__pin_10_, -output right_height_0__pin_11_, -input right_height_0__pin_12_, -output right_height_0__pin_13_, -input right_height_0__pin_14_, -output right_height_0__pin_15_, -input [7:0] gfpga_pad_iopad , -input [329:336] sram_blwl_bl , -input [329:336] sram_blwl_wl , -input [329:336] sram_blwl_blb ); -grid_0__1__io_0__mode_io_phy_ grid_0__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_0_, -right_height_0__pin_1_ -//---- IOPAD ---- -, -gfpga_pad_iopad[0:0] , -//---- SRAM ---- -sram_blwl_bl[329:329] , -sram_blwl_wl[329:329] , -sram_blwl_blb[329:329] ); -grid_0__1__io_1__mode_io_phy_ grid_0__1__1_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_2_, -right_height_0__pin_3_ -//---- IOPAD ---- -, -gfpga_pad_iopad[1:1] , -//---- SRAM ---- -sram_blwl_bl[330:330] , -sram_blwl_wl[330:330] , -sram_blwl_blb[330:330] ); -grid_0__1__io_2__mode_io_phy_ grid_0__1__2_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_4_, -right_height_0__pin_5_ -//---- IOPAD ---- -, -gfpga_pad_iopad[2:2] , -//---- SRAM ---- -sram_blwl_bl[331:331] , -sram_blwl_wl[331:331] , -sram_blwl_blb[331:331] ); -grid_0__1__io_3__mode_io_phy_ grid_0__1__3_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_6_, -right_height_0__pin_7_ -//---- IOPAD ---- -, -gfpga_pad_iopad[3:3] , -//---- SRAM ---- -sram_blwl_bl[332:332] , -sram_blwl_wl[332:332] , -sram_blwl_blb[332:332] ); -grid_0__1__io_4__mode_io_phy_ grid_0__1__4_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_8_, -right_height_0__pin_9_ -//---- IOPAD ---- -, -gfpga_pad_iopad[4:4] , -//---- SRAM ---- -sram_blwl_bl[333:333] , -sram_blwl_wl[333:333] , -sram_blwl_blb[333:333] ); -grid_0__1__io_5__mode_io_phy_ grid_0__1__5_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_10_, -right_height_0__pin_11_ -//---- IOPAD ---- -, -gfpga_pad_iopad[5:5] , -//---- SRAM ---- -sram_blwl_bl[334:334] , -sram_blwl_wl[334:334] , -sram_blwl_blb[334:334] ); -grid_0__1__io_6__mode_io_phy_ grid_0__1__6_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_12_, -right_height_0__pin_13_ -//---- IOPAD ---- -, -gfpga_pad_iopad[6:6] , -//---- SRAM ---- -sram_blwl_bl[335:335] , -sram_blwl_wl[335:335] , -sram_blwl_blb[335:335] ); -grid_0__1__io_7__mode_io_phy_ grid_0__1__7_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_14_, -right_height_0__pin_15_ -//---- IOPAD ---- -, -gfpga_pad_iopad[7:7] , -//---- SRAM ---- -sram_blwl_bl[336:336] , -sram_blwl_wl[336:336] , -sram_blwl_blb[336:336] ); -endmodule -//----- END Top Protocol ----- -//----- END Grid[0][1], Capactity: 8 ----- - diff --git a/examples/verilog_test_example_1/lb/grid_1_0.v b/examples/verilog_test_example_1/lb/grid_1_0.v deleted file mode 100644 index 9305876b7..000000000 --- a/examples/verilog_test_example_1/lb/grid_1_0.v +++ /dev/null @@ -1,694 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Physical Logic Block [1][0] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Grid[1][0] type_descriptor: io[0] ----- -//----- IO Verilog module: grid_1__0__io_0__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_0__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [16:16] gfpga_pad_iopad -, -input [345:345] sram_blwl_bl , -input [345:345] sram_blwl_wl , -input [345:345] sram_blwl_blb ); -wire [345:345] sram_blwl_out ; -wire [345:345] sram_blwl_outb ; -wire [345:345] sram_blwl_345_configbus0; -wire [345:345] sram_blwl_345_configbus1; -wire [345:345] sram_blwl_345_configbus0_b; -assign sram_blwl_345_configbus0[345:345] = sram_blwl_bl[345:345] ; -assign sram_blwl_345_configbus1[345:345] = sram_blwl_wl[345:345] ; -assign sram_blwl_345_configbus0_b[345:345] = sram_blwl_blb[345:345] ; -iopad iopad_16_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[16], sram_blwl_out[345:345] , sram_blwl_outb[345:345] ); -sram6T_blwl sram_blwl_345_ (sram_blwl_out[345], sram_blwl_out[345], sram_blwl_outb[345], sram_blwl_345_configbus0[345:345], sram_blwl_345_configbus1[345:345] , sram_blwl_345_configbus0_b[345:345] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_0__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_0__mode_io_phy_ ----- -module grid_1__0__io_0__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [16:16] gfpga_pad_iopad , -input [345:345] sram_blwl_bl , -input [345:345] sram_blwl_wl , -input [345:345] sram_blwl_blb ); -grid_1__0__io_0__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[16:16] , -sram_blwl_bl[345:345] , -sram_blwl_wl[345:345] , -sram_blwl_blb[345:345] ); -direct_interc direct_interc_46_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_47_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_0__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[1] ----- -//----- IO Verilog module: grid_1__0__io_1__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_1__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [17:17] gfpga_pad_iopad -, -input [346:346] sram_blwl_bl , -input [346:346] sram_blwl_wl , -input [346:346] sram_blwl_blb ); -wire [346:346] sram_blwl_out ; -wire [346:346] sram_blwl_outb ; -wire [346:346] sram_blwl_346_configbus0; -wire [346:346] sram_blwl_346_configbus1; -wire [346:346] sram_blwl_346_configbus0_b; -assign sram_blwl_346_configbus0[346:346] = sram_blwl_bl[346:346] ; -assign sram_blwl_346_configbus1[346:346] = sram_blwl_wl[346:346] ; -assign sram_blwl_346_configbus0_b[346:346] = sram_blwl_blb[346:346] ; -iopad iopad_17_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[17], sram_blwl_out[346:346] , sram_blwl_outb[346:346] ); -sram6T_blwl sram_blwl_346_ (sram_blwl_out[346], sram_blwl_out[346], sram_blwl_outb[346], sram_blwl_346_configbus0[346:346], sram_blwl_346_configbus1[346:346] , sram_blwl_346_configbus0_b[346:346] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_1__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_1__mode_io_phy_ ----- -module grid_1__0__io_1__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [17:17] gfpga_pad_iopad , -input [346:346] sram_blwl_bl , -input [346:346] sram_blwl_wl , -input [346:346] sram_blwl_blb ); -grid_1__0__io_1__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[17:17] , -sram_blwl_bl[346:346] , -sram_blwl_wl[346:346] , -sram_blwl_blb[346:346] ); -direct_interc direct_interc_48_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_49_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_1__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[2] ----- -//----- IO Verilog module: grid_1__0__io_2__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_2__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [18:18] gfpga_pad_iopad -, -input [347:347] sram_blwl_bl , -input [347:347] sram_blwl_wl , -input [347:347] sram_blwl_blb ); -wire [347:347] sram_blwl_out ; -wire [347:347] sram_blwl_outb ; -wire [347:347] sram_blwl_347_configbus0; -wire [347:347] sram_blwl_347_configbus1; -wire [347:347] sram_blwl_347_configbus0_b; -assign sram_blwl_347_configbus0[347:347] = sram_blwl_bl[347:347] ; -assign sram_blwl_347_configbus1[347:347] = sram_blwl_wl[347:347] ; -assign sram_blwl_347_configbus0_b[347:347] = sram_blwl_blb[347:347] ; -iopad iopad_18_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[18], sram_blwl_out[347:347] , sram_blwl_outb[347:347] ); -sram6T_blwl sram_blwl_347_ (sram_blwl_out[347], sram_blwl_out[347], sram_blwl_outb[347], sram_blwl_347_configbus0[347:347], sram_blwl_347_configbus1[347:347] , sram_blwl_347_configbus0_b[347:347] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_2__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_2__mode_io_phy_ ----- -module grid_1__0__io_2__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [18:18] gfpga_pad_iopad , -input [347:347] sram_blwl_bl , -input [347:347] sram_blwl_wl , -input [347:347] sram_blwl_blb ); -grid_1__0__io_2__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[18:18] , -sram_blwl_bl[347:347] , -sram_blwl_wl[347:347] , -sram_blwl_blb[347:347] ); -direct_interc direct_interc_50_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_51_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_2__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[3] ----- -//----- IO Verilog module: grid_1__0__io_3__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_3__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [19:19] gfpga_pad_iopad -, -input [348:348] sram_blwl_bl , -input [348:348] sram_blwl_wl , -input [348:348] sram_blwl_blb ); -wire [348:348] sram_blwl_out ; -wire [348:348] sram_blwl_outb ; -wire [348:348] sram_blwl_348_configbus0; -wire [348:348] sram_blwl_348_configbus1; -wire [348:348] sram_blwl_348_configbus0_b; -assign sram_blwl_348_configbus0[348:348] = sram_blwl_bl[348:348] ; -assign sram_blwl_348_configbus1[348:348] = sram_blwl_wl[348:348] ; -assign sram_blwl_348_configbus0_b[348:348] = sram_blwl_blb[348:348] ; -iopad iopad_19_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[19], sram_blwl_out[348:348] , sram_blwl_outb[348:348] ); -sram6T_blwl sram_blwl_348_ (sram_blwl_out[348], sram_blwl_out[348], sram_blwl_outb[348], sram_blwl_348_configbus0[348:348], sram_blwl_348_configbus1[348:348] , sram_blwl_348_configbus0_b[348:348] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_3__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_3__mode_io_phy_ ----- -module grid_1__0__io_3__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [19:19] gfpga_pad_iopad , -input [348:348] sram_blwl_bl , -input [348:348] sram_blwl_wl , -input [348:348] sram_blwl_blb ); -grid_1__0__io_3__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[19:19] , -sram_blwl_bl[348:348] , -sram_blwl_wl[348:348] , -sram_blwl_blb[348:348] ); -direct_interc direct_interc_52_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_53_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_3__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[4] ----- -//----- IO Verilog module: grid_1__0__io_4__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_4__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [20:20] gfpga_pad_iopad -, -input [349:349] sram_blwl_bl , -input [349:349] sram_blwl_wl , -input [349:349] sram_blwl_blb ); -wire [349:349] sram_blwl_out ; -wire [349:349] sram_blwl_outb ; -wire [349:349] sram_blwl_349_configbus0; -wire [349:349] sram_blwl_349_configbus1; -wire [349:349] sram_blwl_349_configbus0_b; -assign sram_blwl_349_configbus0[349:349] = sram_blwl_bl[349:349] ; -assign sram_blwl_349_configbus1[349:349] = sram_blwl_wl[349:349] ; -assign sram_blwl_349_configbus0_b[349:349] = sram_blwl_blb[349:349] ; -iopad iopad_20_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[20], sram_blwl_out[349:349] , sram_blwl_outb[349:349] ); -sram6T_blwl sram_blwl_349_ (sram_blwl_out[349], sram_blwl_out[349], sram_blwl_outb[349], sram_blwl_349_configbus0[349:349], sram_blwl_349_configbus1[349:349] , sram_blwl_349_configbus0_b[349:349] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_4__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_4__mode_io_phy_ ----- -module grid_1__0__io_4__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [20:20] gfpga_pad_iopad , -input [349:349] sram_blwl_bl , -input [349:349] sram_blwl_wl , -input [349:349] sram_blwl_blb ); -grid_1__0__io_4__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[20:20] , -sram_blwl_bl[349:349] , -sram_blwl_wl[349:349] , -sram_blwl_blb[349:349] ); -direct_interc direct_interc_54_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_55_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_4__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[5] ----- -//----- IO Verilog module: grid_1__0__io_5__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_5__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [21:21] gfpga_pad_iopad -, -input [350:350] sram_blwl_bl , -input [350:350] sram_blwl_wl , -input [350:350] sram_blwl_blb ); -wire [350:350] sram_blwl_out ; -wire [350:350] sram_blwl_outb ; -wire [350:350] sram_blwl_350_configbus0; -wire [350:350] sram_blwl_350_configbus1; -wire [350:350] sram_blwl_350_configbus0_b; -assign sram_blwl_350_configbus0[350:350] = sram_blwl_bl[350:350] ; -assign sram_blwl_350_configbus1[350:350] = sram_blwl_wl[350:350] ; -assign sram_blwl_350_configbus0_b[350:350] = sram_blwl_blb[350:350] ; -iopad iopad_21_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[21], sram_blwl_out[350:350] , sram_blwl_outb[350:350] ); -sram6T_blwl sram_blwl_350_ (sram_blwl_out[350], sram_blwl_out[350], sram_blwl_outb[350], sram_blwl_350_configbus0[350:350], sram_blwl_350_configbus1[350:350] , sram_blwl_350_configbus0_b[350:350] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_5__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_5__mode_io_phy_ ----- -module grid_1__0__io_5__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [21:21] gfpga_pad_iopad , -input [350:350] sram_blwl_bl , -input [350:350] sram_blwl_wl , -input [350:350] sram_blwl_blb ); -grid_1__0__io_5__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[21:21] , -sram_blwl_bl[350:350] , -sram_blwl_wl[350:350] , -sram_blwl_blb[350:350] ); -direct_interc direct_interc_56_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_57_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_5__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[6] ----- -//----- IO Verilog module: grid_1__0__io_6__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_6__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [22:22] gfpga_pad_iopad -, -input [351:351] sram_blwl_bl , -input [351:351] sram_blwl_wl , -input [351:351] sram_blwl_blb ); -wire [351:351] sram_blwl_out ; -wire [351:351] sram_blwl_outb ; -wire [351:351] sram_blwl_351_configbus0; -wire [351:351] sram_blwl_351_configbus1; -wire [351:351] sram_blwl_351_configbus0_b; -assign sram_blwl_351_configbus0[351:351] = sram_blwl_bl[351:351] ; -assign sram_blwl_351_configbus1[351:351] = sram_blwl_wl[351:351] ; -assign sram_blwl_351_configbus0_b[351:351] = sram_blwl_blb[351:351] ; -iopad iopad_22_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[22], sram_blwl_out[351:351] , sram_blwl_outb[351:351] ); -sram6T_blwl sram_blwl_351_ (sram_blwl_out[351], sram_blwl_out[351], sram_blwl_outb[351], sram_blwl_351_configbus0[351:351], sram_blwl_351_configbus1[351:351] , sram_blwl_351_configbus0_b[351:351] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_6__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_6__mode_io_phy_ ----- -module grid_1__0__io_6__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [22:22] gfpga_pad_iopad , -input [351:351] sram_blwl_bl , -input [351:351] sram_blwl_wl , -input [351:351] sram_blwl_blb ); -grid_1__0__io_6__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[22:22] , -sram_blwl_bl[351:351] , -sram_blwl_wl[351:351] , -sram_blwl_blb[351:351] ); -direct_interc direct_interc_58_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_59_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_6__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[7] ----- -//----- IO Verilog module: grid_1__0__io_7__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_7__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [23:23] gfpga_pad_iopad -, -input [352:352] sram_blwl_bl , -input [352:352] sram_blwl_wl , -input [352:352] sram_blwl_blb ); -wire [352:352] sram_blwl_out ; -wire [352:352] sram_blwl_outb ; -wire [352:352] sram_blwl_352_configbus0; -wire [352:352] sram_blwl_352_configbus1; -wire [352:352] sram_blwl_352_configbus0_b; -assign sram_blwl_352_configbus0[352:352] = sram_blwl_bl[352:352] ; -assign sram_blwl_352_configbus1[352:352] = sram_blwl_wl[352:352] ; -assign sram_blwl_352_configbus0_b[352:352] = sram_blwl_blb[352:352] ; -iopad iopad_23_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[23], sram_blwl_out[352:352] , sram_blwl_outb[352:352] ); -sram6T_blwl sram_blwl_352_ (sram_blwl_out[352], sram_blwl_out[352], sram_blwl_outb[352], sram_blwl_352_configbus0[352:352], sram_blwl_352_configbus1[352:352] , sram_blwl_352_configbus0_b[352:352] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_7__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_7__mode_io_phy_ ----- -module grid_1__0__io_7__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [23:23] gfpga_pad_iopad , -input [352:352] sram_blwl_bl , -input [352:352] sram_blwl_wl , -input [352:352] sram_blwl_blb ); -grid_1__0__io_7__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[23:23] , -sram_blwl_bl[352:352] , -sram_blwl_wl[352:352] , -sram_blwl_blb[352:352] ); -direct_interc direct_interc_60_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_61_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_7__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0], Capactity: 8 ----- -//----- Top Protocol ----- -module grid_1__0_( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input top_height_0__pin_0_, -output top_height_0__pin_1_, -input top_height_0__pin_2_, -output top_height_0__pin_3_, -input top_height_0__pin_4_, -output top_height_0__pin_5_, -input top_height_0__pin_6_, -output top_height_0__pin_7_, -input top_height_0__pin_8_, -output top_height_0__pin_9_, -input top_height_0__pin_10_, -output top_height_0__pin_11_, -input top_height_0__pin_12_, -output top_height_0__pin_13_, -input top_height_0__pin_14_, -output top_height_0__pin_15_, -input [23:16] gfpga_pad_iopad , -input [345:352] sram_blwl_bl , -input [345:352] sram_blwl_wl , -input [345:352] sram_blwl_blb ); -grid_1__0__io_0__mode_io_phy_ grid_1__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_0_, -top_height_0__pin_1_ -//---- IOPAD ---- -, -gfpga_pad_iopad[16:16] , -//---- SRAM ---- -sram_blwl_bl[345:345] , -sram_blwl_wl[345:345] , -sram_blwl_blb[345:345] ); -grid_1__0__io_1__mode_io_phy_ grid_1__0__1_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_2_, -top_height_0__pin_3_ -//---- IOPAD ---- -, -gfpga_pad_iopad[17:17] , -//---- SRAM ---- -sram_blwl_bl[346:346] , -sram_blwl_wl[346:346] , -sram_blwl_blb[346:346] ); -grid_1__0__io_2__mode_io_phy_ grid_1__0__2_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_4_, -top_height_0__pin_5_ -//---- IOPAD ---- -, -gfpga_pad_iopad[18:18] , -//---- SRAM ---- -sram_blwl_bl[347:347] , -sram_blwl_wl[347:347] , -sram_blwl_blb[347:347] ); -grid_1__0__io_3__mode_io_phy_ grid_1__0__3_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_6_, -top_height_0__pin_7_ -//---- IOPAD ---- -, -gfpga_pad_iopad[19:19] , -//---- SRAM ---- -sram_blwl_bl[348:348] , -sram_blwl_wl[348:348] , -sram_blwl_blb[348:348] ); -grid_1__0__io_4__mode_io_phy_ grid_1__0__4_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_8_, -top_height_0__pin_9_ -//---- IOPAD ---- -, -gfpga_pad_iopad[20:20] , -//---- SRAM ---- -sram_blwl_bl[349:349] , -sram_blwl_wl[349:349] , -sram_blwl_blb[349:349] ); -grid_1__0__io_5__mode_io_phy_ grid_1__0__5_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_10_, -top_height_0__pin_11_ -//---- IOPAD ---- -, -gfpga_pad_iopad[21:21] , -//---- SRAM ---- -sram_blwl_bl[350:350] , -sram_blwl_wl[350:350] , -sram_blwl_blb[350:350] ); -grid_1__0__io_6__mode_io_phy_ grid_1__0__6_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_12_, -top_height_0__pin_13_ -//---- IOPAD ---- -, -gfpga_pad_iopad[22:22] , -//---- SRAM ---- -sram_blwl_bl[351:351] , -sram_blwl_wl[351:351] , -sram_blwl_blb[351:351] ); -grid_1__0__io_7__mode_io_phy_ grid_1__0__7_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_14_, -top_height_0__pin_15_ -//---- IOPAD ---- -, -gfpga_pad_iopad[23:23] , -//---- SRAM ---- -sram_blwl_bl[352:352] , -sram_blwl_wl[352:352] , -sram_blwl_blb[352:352] ); -endmodule -//----- END Top Protocol ----- -//----- END Grid[1][0], Capactity: 8 ----- - diff --git a/examples/verilog_test_example_1/lb/grid_1_1.v b/examples/verilog_test_example_1/lb/grid_1_1.v deleted file mode 100644 index ade8d0c74..000000000 --- a/examples/verilog_test_example_1/lb/grid_1_1.v +++ /dev/null @@ -1,452 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Logic Block [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Grid[1][1] type_descriptor: clb[0] ----- -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4__lut4_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4__lut4_0_ ( -input wire lut4_0___in_0_, -input wire lut4_0___in_1_, -input wire lut4_0___in_2_, -input wire lut4_0___in_3_, -output wire lut4_0___out_0_, -input [288:303] sram_blwl_bl , -input [288:303] sram_blwl_wl , -input [288:303] sram_blwl_blb ); -wire [0:3] lut4_0___in; -assign lut4_0___in[0] = lut4_0___in_0_; -assign lut4_0___in[1] = lut4_0___in_1_; -assign lut4_0___in[2] = lut4_0___in_2_; -assign lut4_0___in[3] = lut4_0___in_3_; -wire [0:0] lut4_0___out; -assign lut4_0___out_0_ = lut4_0___out[0]; -wire [288:303] sram_blwl_out ; -wire [288:303] sram_blwl_outb ; -lut4 lut4_0_ ( -//----- Input and output ports ----- - lut4_0___in[0:3] , lut4_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[288:303] , sram_blwl_outb[288:303] ); -//----- Truth Table for LUT node (n7). ----- -//----- Truth Table for LUT[0], size=4. ----- -// 0--- 1 -//----- SRAM bits for LUT[0], size=4, num_sram=16. ----- -//-----0101010101010101----- -wire [288:288] sram_blwl_288_configbus0; -wire [288:288] sram_blwl_288_configbus1; -wire [288:288] sram_blwl_288_configbus0_b; -assign sram_blwl_288_configbus0[288:288] = sram_blwl_bl[288:288] ; -assign sram_blwl_288_configbus1[288:288] = sram_blwl_wl[288:288] ; -assign sram_blwl_288_configbus0_b[288:288] = sram_blwl_blb[288:288] ; -sram6T_blwl sram_blwl_288_ (sram_blwl_out[288], sram_blwl_out[288], sram_blwl_outb[288], sram_blwl_288_configbus0[288:288], sram_blwl_288_configbus1[288:288] , sram_blwl_288_configbus0_b[288:288] ); -wire [289:289] sram_blwl_289_configbus0; -wire [289:289] sram_blwl_289_configbus1; -wire [289:289] sram_blwl_289_configbus0_b; -assign sram_blwl_289_configbus0[289:289] = sram_blwl_bl[289:289] ; -assign sram_blwl_289_configbus1[289:289] = sram_blwl_wl[289:289] ; -assign sram_blwl_289_configbus0_b[289:289] = sram_blwl_blb[289:289] ; -sram6T_blwl sram_blwl_289_ (sram_blwl_out[289], sram_blwl_out[289], sram_blwl_outb[289], sram_blwl_289_configbus0[289:289], sram_blwl_289_configbus1[289:289] , sram_blwl_289_configbus0_b[289:289] ); -wire [290:290] sram_blwl_290_configbus0; -wire [290:290] sram_blwl_290_configbus1; -wire [290:290] sram_blwl_290_configbus0_b; -assign sram_blwl_290_configbus0[290:290] = sram_blwl_bl[290:290] ; -assign sram_blwl_290_configbus1[290:290] = sram_blwl_wl[290:290] ; -assign sram_blwl_290_configbus0_b[290:290] = sram_blwl_blb[290:290] ; -sram6T_blwl sram_blwl_290_ (sram_blwl_out[290], sram_blwl_out[290], sram_blwl_outb[290], sram_blwl_290_configbus0[290:290], sram_blwl_290_configbus1[290:290] , sram_blwl_290_configbus0_b[290:290] ); -wire [291:291] sram_blwl_291_configbus0; -wire [291:291] sram_blwl_291_configbus1; -wire [291:291] sram_blwl_291_configbus0_b; -assign sram_blwl_291_configbus0[291:291] = sram_blwl_bl[291:291] ; -assign sram_blwl_291_configbus1[291:291] = sram_blwl_wl[291:291] ; -assign sram_blwl_291_configbus0_b[291:291] = sram_blwl_blb[291:291] ; -sram6T_blwl sram_blwl_291_ (sram_blwl_out[291], sram_blwl_out[291], sram_blwl_outb[291], sram_blwl_291_configbus0[291:291], sram_blwl_291_configbus1[291:291] , sram_blwl_291_configbus0_b[291:291] ); -wire [292:292] sram_blwl_292_configbus0; -wire [292:292] sram_blwl_292_configbus1; -wire [292:292] sram_blwl_292_configbus0_b; -assign sram_blwl_292_configbus0[292:292] = sram_blwl_bl[292:292] ; -assign sram_blwl_292_configbus1[292:292] = sram_blwl_wl[292:292] ; -assign sram_blwl_292_configbus0_b[292:292] = sram_blwl_blb[292:292] ; -sram6T_blwl sram_blwl_292_ (sram_blwl_out[292], sram_blwl_out[292], sram_blwl_outb[292], sram_blwl_292_configbus0[292:292], sram_blwl_292_configbus1[292:292] , sram_blwl_292_configbus0_b[292:292] ); -wire [293:293] sram_blwl_293_configbus0; -wire [293:293] sram_blwl_293_configbus1; -wire [293:293] sram_blwl_293_configbus0_b; -assign sram_blwl_293_configbus0[293:293] = sram_blwl_bl[293:293] ; -assign sram_blwl_293_configbus1[293:293] = sram_blwl_wl[293:293] ; -assign sram_blwl_293_configbus0_b[293:293] = sram_blwl_blb[293:293] ; -sram6T_blwl sram_blwl_293_ (sram_blwl_out[293], sram_blwl_out[293], sram_blwl_outb[293], sram_blwl_293_configbus0[293:293], sram_blwl_293_configbus1[293:293] , sram_blwl_293_configbus0_b[293:293] ); -wire [294:294] sram_blwl_294_configbus0; -wire [294:294] sram_blwl_294_configbus1; -wire [294:294] sram_blwl_294_configbus0_b; -assign sram_blwl_294_configbus0[294:294] = sram_blwl_bl[294:294] ; -assign sram_blwl_294_configbus1[294:294] = sram_blwl_wl[294:294] ; -assign sram_blwl_294_configbus0_b[294:294] = sram_blwl_blb[294:294] ; -sram6T_blwl sram_blwl_294_ (sram_blwl_out[294], sram_blwl_out[294], sram_blwl_outb[294], sram_blwl_294_configbus0[294:294], sram_blwl_294_configbus1[294:294] , sram_blwl_294_configbus0_b[294:294] ); -wire [295:295] sram_blwl_295_configbus0; -wire [295:295] sram_blwl_295_configbus1; -wire [295:295] sram_blwl_295_configbus0_b; -assign sram_blwl_295_configbus0[295:295] = sram_blwl_bl[295:295] ; -assign sram_blwl_295_configbus1[295:295] = sram_blwl_wl[295:295] ; -assign sram_blwl_295_configbus0_b[295:295] = sram_blwl_blb[295:295] ; -sram6T_blwl sram_blwl_295_ (sram_blwl_out[295], sram_blwl_out[295], sram_blwl_outb[295], sram_blwl_295_configbus0[295:295], sram_blwl_295_configbus1[295:295] , sram_blwl_295_configbus0_b[295:295] ); -wire [296:296] sram_blwl_296_configbus0; -wire [296:296] sram_blwl_296_configbus1; -wire [296:296] sram_blwl_296_configbus0_b; -assign sram_blwl_296_configbus0[296:296] = sram_blwl_bl[296:296] ; -assign sram_blwl_296_configbus1[296:296] = sram_blwl_wl[296:296] ; -assign sram_blwl_296_configbus0_b[296:296] = sram_blwl_blb[296:296] ; -sram6T_blwl sram_blwl_296_ (sram_blwl_out[296], sram_blwl_out[296], sram_blwl_outb[296], sram_blwl_296_configbus0[296:296], sram_blwl_296_configbus1[296:296] , sram_blwl_296_configbus0_b[296:296] ); -wire [297:297] sram_blwl_297_configbus0; -wire [297:297] sram_blwl_297_configbus1; -wire [297:297] sram_blwl_297_configbus0_b; -assign sram_blwl_297_configbus0[297:297] = sram_blwl_bl[297:297] ; -assign sram_blwl_297_configbus1[297:297] = sram_blwl_wl[297:297] ; -assign sram_blwl_297_configbus0_b[297:297] = sram_blwl_blb[297:297] ; -sram6T_blwl sram_blwl_297_ (sram_blwl_out[297], sram_blwl_out[297], sram_blwl_outb[297], sram_blwl_297_configbus0[297:297], sram_blwl_297_configbus1[297:297] , sram_blwl_297_configbus0_b[297:297] ); -wire [298:298] sram_blwl_298_configbus0; -wire [298:298] sram_blwl_298_configbus1; -wire [298:298] sram_blwl_298_configbus0_b; -assign sram_blwl_298_configbus0[298:298] = sram_blwl_bl[298:298] ; -assign sram_blwl_298_configbus1[298:298] = sram_blwl_wl[298:298] ; -assign sram_blwl_298_configbus0_b[298:298] = sram_blwl_blb[298:298] ; -sram6T_blwl sram_blwl_298_ (sram_blwl_out[298], sram_blwl_out[298], sram_blwl_outb[298], sram_blwl_298_configbus0[298:298], sram_blwl_298_configbus1[298:298] , sram_blwl_298_configbus0_b[298:298] ); -wire [299:299] sram_blwl_299_configbus0; -wire [299:299] sram_blwl_299_configbus1; -wire [299:299] sram_blwl_299_configbus0_b; -assign sram_blwl_299_configbus0[299:299] = sram_blwl_bl[299:299] ; -assign sram_blwl_299_configbus1[299:299] = sram_blwl_wl[299:299] ; -assign sram_blwl_299_configbus0_b[299:299] = sram_blwl_blb[299:299] ; -sram6T_blwl sram_blwl_299_ (sram_blwl_out[299], sram_blwl_out[299], sram_blwl_outb[299], sram_blwl_299_configbus0[299:299], sram_blwl_299_configbus1[299:299] , sram_blwl_299_configbus0_b[299:299] ); -wire [300:300] sram_blwl_300_configbus0; -wire [300:300] sram_blwl_300_configbus1; -wire [300:300] sram_blwl_300_configbus0_b; -assign sram_blwl_300_configbus0[300:300] = sram_blwl_bl[300:300] ; -assign sram_blwl_300_configbus1[300:300] = sram_blwl_wl[300:300] ; -assign sram_blwl_300_configbus0_b[300:300] = sram_blwl_blb[300:300] ; -sram6T_blwl sram_blwl_300_ (sram_blwl_out[300], sram_blwl_out[300], sram_blwl_outb[300], sram_blwl_300_configbus0[300:300], sram_blwl_300_configbus1[300:300] , sram_blwl_300_configbus0_b[300:300] ); -wire [301:301] sram_blwl_301_configbus0; -wire [301:301] sram_blwl_301_configbus1; -wire [301:301] sram_blwl_301_configbus0_b; -assign sram_blwl_301_configbus0[301:301] = sram_blwl_bl[301:301] ; -assign sram_blwl_301_configbus1[301:301] = sram_blwl_wl[301:301] ; -assign sram_blwl_301_configbus0_b[301:301] = sram_blwl_blb[301:301] ; -sram6T_blwl sram_blwl_301_ (sram_blwl_out[301], sram_blwl_out[301], sram_blwl_outb[301], sram_blwl_301_configbus0[301:301], sram_blwl_301_configbus1[301:301] , sram_blwl_301_configbus0_b[301:301] ); -wire [302:302] sram_blwl_302_configbus0; -wire [302:302] sram_blwl_302_configbus1; -wire [302:302] sram_blwl_302_configbus0_b; -assign sram_blwl_302_configbus0[302:302] = sram_blwl_bl[302:302] ; -assign sram_blwl_302_configbus1[302:302] = sram_blwl_wl[302:302] ; -assign sram_blwl_302_configbus0_b[302:302] = sram_blwl_blb[302:302] ; -sram6T_blwl sram_blwl_302_ (sram_blwl_out[302], sram_blwl_out[302], sram_blwl_outb[302], sram_blwl_302_configbus0[302:302], sram_blwl_302_configbus1[302:302] , sram_blwl_302_configbus0_b[302:302] ); -wire [303:303] sram_blwl_303_configbus0; -wire [303:303] sram_blwl_303_configbus1; -wire [303:303] sram_blwl_303_configbus0_b; -assign sram_blwl_303_configbus0[303:303] = sram_blwl_bl[303:303] ; -assign sram_blwl_303_configbus1[303:303] = sram_blwl_wl[303:303] ; -assign sram_blwl_303_configbus0_b[303:303] = sram_blwl_blb[303:303] ; -sram6T_blwl sram_blwl_303_ (sram_blwl_out[303], sram_blwl_out[303], sram_blwl_outb[303], sram_blwl_303_configbus0[303:303], sram_blwl_303_configbus1[303:303] , sram_blwl_303_configbus0_b[303:303] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4__lut4_0_ ----- - -//----- Flip-flop Verilog module: Q0 ----- -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4__ff_0_ ----- - -//----- Programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4_ ----- -module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble4___in_0_, -input wire mode_ble4___in_1_, -input wire mode_ble4___in_2_, -input wire mode_ble4___in_3_, -output wire mode_ble4___out_0_, -input wire mode_ble4___clk_0_, -input [288:304] sram_blwl_bl , -input [288:304] sram_blwl_wl , -input [288:304] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4__lut4_0_ lut4_0_ ( - lut4_0___in_0_, lut4_0___in_1_, lut4_0___in_2_, lut4_0___in_3_, lut4_0___out_0_, -sram_blwl_bl[288:303] , -sram_blwl_wl[288:303] , -sram_blwl_blb[288:303] ); -grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_120_ ; -assign in_bus_mux_1level_tapbuf_size2_120_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_120_[1] = lut4_0___out_0_ ; -wire [304:304] mux_1level_tapbuf_size2_120_configbus0; -wire [304:304] mux_1level_tapbuf_size2_120_configbus1; -wire [304:304] mux_1level_tapbuf_size2_120_sram_blwl_out ; -wire [304:304] mux_1level_tapbuf_size2_120_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_120_configbus0[304:304] = sram_blwl_bl[304:304] ; -assign mux_1level_tapbuf_size2_120_configbus1[304:304] = sram_blwl_wl[304:304] ; -wire [304:304] mux_1level_tapbuf_size2_120_configbus0_b; -assign mux_1level_tapbuf_size2_120_configbus0_b[304:304] = sram_blwl_blb[304:304] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_120_ (in_bus_mux_1level_tapbuf_size2_120_, mode_ble4___out_0_, mux_1level_tapbuf_size2_120_sram_blwl_out[304:304] , -mux_1level_tapbuf_size2_120_sram_blwl_outb[304:304] ); -//----- SRAM bits for MUX[120], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_304_ (mux_1level_tapbuf_size2_120_sram_blwl_out[304:304] ,mux_1level_tapbuf_size2_120_sram_blwl_out[304:304] ,mux_1level_tapbuf_size2_120_sram_blwl_outb[304:304] ,mux_1level_tapbuf_size2_120_configbus0[304:304], mux_1level_tapbuf_size2_120_configbus1[304:304] , mux_1level_tapbuf_size2_120_configbus0_b[304:304] ); -direct_interc direct_interc_0_ (mode_ble4___in_0_, lut4_0___in_0_ ); -direct_interc direct_interc_1_ (mode_ble4___in_1_, lut4_0___in_1_ ); -direct_interc direct_interc_2_ (mode_ble4___in_2_, lut4_0___in_2_ ); -direct_interc direct_interc_3_ (mode_ble4___in_3_, lut4_0___in_3_ ); -direct_interc direct_interc_4_ (lut4_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_5_ (mode_ble4___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4_ ----- - -//----- Programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4_ ----- -module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut4___in_0_, -input wire mode_n1_lut4___in_1_, -input wire mode_n1_lut4___in_2_, -input wire mode_n1_lut4___in_3_, -output wire mode_n1_lut4___out_0_, -input wire mode_n1_lut4___clk_0_, -input [288:304] sram_blwl_bl , -input [288:304] sram_blwl_wl , -input [288:304] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4__ble4_0__mode_ble4_ ble4_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble4_0___in_0_, ble4_0___in_1_, ble4_0___in_2_, ble4_0___in_3_, ble4_0___out_0_, ble4_0___clk_0_, -sram_blwl_bl[288:304] , -sram_blwl_wl[288:304] , -sram_blwl_blb[288:304] ); -direct_interc direct_interc_6_ (ble4_0___out_0_, mode_n1_lut4___out_0_ ); -direct_interc direct_interc_7_ (mode_n1_lut4___in_0_, ble4_0___in_0_ ); -direct_interc direct_interc_8_ (mode_n1_lut4___in_1_, ble4_0___in_1_ ); -direct_interc direct_interc_9_ (mode_n1_lut4___in_2_, ble4_0___in_2_ ); -direct_interc direct_interc_10_ (mode_n1_lut4___in_3_, ble4_0___in_3_ ); -direct_interc direct_interc_11_ (mode_n1_lut4___clk_0_, ble4_0___clk_0_ ); -endmodule -//----- END Programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4_ ----- - -//----- Programmable logic block Verilog module grid_1__1__clb_0__mode_clb_ ----- -module grid_1__1__clb_0__mode_clb_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_clb___I_0_, -input wire mode_clb___I_1_, -input wire mode_clb___I_2_, -input wire mode_clb___I_3_, -output wire mode_clb___O_0_, -input wire mode_clb___clk_0_, -input [288:328] sram_blwl_bl , -input [288:328] sram_blwl_wl , -input [288:328] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut4_ fle_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_0___in_0_, fle_0___in_1_, fle_0___in_2_, fle_0___in_3_, fle_0___out_0_, fle_0___clk_0_, -sram_blwl_bl[288:304] , -sram_blwl_wl[288:304] , -sram_blwl_blb[288:304] ); -direct_interc direct_interc_12_ (fle_0___out_0_, mode_clb___O_0_ ); -wire [0:4] in_bus_mux_2level_size5_0_ ; -assign in_bus_mux_2level_size5_0_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size5_0_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size5_0_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size5_0_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size5_0_[4] = fle_0___out_0_ ; -wire [305:310] mux_2level_size5_0_configbus0; -wire [305:310] mux_2level_size5_0_configbus1; -wire [305:310] mux_2level_size5_0_sram_blwl_out ; -wire [305:310] mux_2level_size5_0_sram_blwl_outb ; -assign mux_2level_size5_0_configbus0[305:310] = sram_blwl_bl[305:310] ; -assign mux_2level_size5_0_configbus1[305:310] = sram_blwl_wl[305:310] ; -wire [305:310] mux_2level_size5_0_configbus0_b; -assign mux_2level_size5_0_configbus0_b[305:310] = sram_blwl_blb[305:310] ; -mux_2level_size5 mux_2level_size5_0_ (in_bus_mux_2level_size5_0_, fle_0___in_0_, mux_2level_size5_0_sram_blwl_out[305:310] , -mux_2level_size5_0_sram_blwl_outb[305:310] ); -//----- SRAM bits for MUX[0], level=2, select_path_id=3. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----010100----- -sram6T_blwl sram_blwl_305_ (mux_2level_size5_0_sram_blwl_out[305:305] ,mux_2level_size5_0_sram_blwl_out[305:305] ,mux_2level_size5_0_sram_blwl_outb[305:305] ,mux_2level_size5_0_configbus0[305:305], mux_2level_size5_0_configbus1[305:305] , mux_2level_size5_0_configbus0_b[305:305] ); -sram6T_blwl sram_blwl_306_ (mux_2level_size5_0_sram_blwl_out[306:306] ,mux_2level_size5_0_sram_blwl_out[306:306] ,mux_2level_size5_0_sram_blwl_outb[306:306] ,mux_2level_size5_0_configbus0[306:306], mux_2level_size5_0_configbus1[306:306] , mux_2level_size5_0_configbus0_b[306:306] ); -sram6T_blwl sram_blwl_307_ (mux_2level_size5_0_sram_blwl_out[307:307] ,mux_2level_size5_0_sram_blwl_out[307:307] ,mux_2level_size5_0_sram_blwl_outb[307:307] ,mux_2level_size5_0_configbus0[307:307], mux_2level_size5_0_configbus1[307:307] , mux_2level_size5_0_configbus0_b[307:307] ); -sram6T_blwl sram_blwl_308_ (mux_2level_size5_0_sram_blwl_out[308:308] ,mux_2level_size5_0_sram_blwl_out[308:308] ,mux_2level_size5_0_sram_blwl_outb[308:308] ,mux_2level_size5_0_configbus0[308:308], mux_2level_size5_0_configbus1[308:308] , mux_2level_size5_0_configbus0_b[308:308] ); -sram6T_blwl sram_blwl_309_ (mux_2level_size5_0_sram_blwl_out[309:309] ,mux_2level_size5_0_sram_blwl_out[309:309] ,mux_2level_size5_0_sram_blwl_outb[309:309] ,mux_2level_size5_0_configbus0[309:309], mux_2level_size5_0_configbus1[309:309] , mux_2level_size5_0_configbus0_b[309:309] ); -sram6T_blwl sram_blwl_310_ (mux_2level_size5_0_sram_blwl_out[310:310] ,mux_2level_size5_0_sram_blwl_out[310:310] ,mux_2level_size5_0_sram_blwl_outb[310:310] ,mux_2level_size5_0_configbus0[310:310], mux_2level_size5_0_configbus1[310:310] , mux_2level_size5_0_configbus0_b[310:310] ); -wire [0:4] in_bus_mux_2level_size5_1_ ; -assign in_bus_mux_2level_size5_1_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size5_1_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size5_1_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size5_1_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size5_1_[4] = fle_0___out_0_ ; -wire [311:316] mux_2level_size5_1_configbus0; -wire [311:316] mux_2level_size5_1_configbus1; -wire [311:316] mux_2level_size5_1_sram_blwl_out ; -wire [311:316] mux_2level_size5_1_sram_blwl_outb ; -assign mux_2level_size5_1_configbus0[311:316] = sram_blwl_bl[311:316] ; -assign mux_2level_size5_1_configbus1[311:316] = sram_blwl_wl[311:316] ; -wire [311:316] mux_2level_size5_1_configbus0_b; -assign mux_2level_size5_1_configbus0_b[311:316] = sram_blwl_blb[311:316] ; -mux_2level_size5 mux_2level_size5_1_ (in_bus_mux_2level_size5_1_, fle_0___in_1_, mux_2level_size5_1_sram_blwl_out[311:316] , -mux_2level_size5_1_sram_blwl_outb[311:316] ); -//----- SRAM bits for MUX[1], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100100----- -sram6T_blwl sram_blwl_311_ (mux_2level_size5_1_sram_blwl_out[311:311] ,mux_2level_size5_1_sram_blwl_out[311:311] ,mux_2level_size5_1_sram_blwl_outb[311:311] ,mux_2level_size5_1_configbus0[311:311], mux_2level_size5_1_configbus1[311:311] , mux_2level_size5_1_configbus0_b[311:311] ); -sram6T_blwl sram_blwl_312_ (mux_2level_size5_1_sram_blwl_out[312:312] ,mux_2level_size5_1_sram_blwl_out[312:312] ,mux_2level_size5_1_sram_blwl_outb[312:312] ,mux_2level_size5_1_configbus0[312:312], mux_2level_size5_1_configbus1[312:312] , mux_2level_size5_1_configbus0_b[312:312] ); -sram6T_blwl sram_blwl_313_ (mux_2level_size5_1_sram_blwl_out[313:313] ,mux_2level_size5_1_sram_blwl_out[313:313] ,mux_2level_size5_1_sram_blwl_outb[313:313] ,mux_2level_size5_1_configbus0[313:313], mux_2level_size5_1_configbus1[313:313] , mux_2level_size5_1_configbus0_b[313:313] ); -sram6T_blwl sram_blwl_314_ (mux_2level_size5_1_sram_blwl_out[314:314] ,mux_2level_size5_1_sram_blwl_out[314:314] ,mux_2level_size5_1_sram_blwl_outb[314:314] ,mux_2level_size5_1_configbus0[314:314], mux_2level_size5_1_configbus1[314:314] , mux_2level_size5_1_configbus0_b[314:314] ); -sram6T_blwl sram_blwl_315_ (mux_2level_size5_1_sram_blwl_out[315:315] ,mux_2level_size5_1_sram_blwl_out[315:315] ,mux_2level_size5_1_sram_blwl_outb[315:315] ,mux_2level_size5_1_configbus0[315:315], mux_2level_size5_1_configbus1[315:315] , mux_2level_size5_1_configbus0_b[315:315] ); -sram6T_blwl sram_blwl_316_ (mux_2level_size5_1_sram_blwl_out[316:316] ,mux_2level_size5_1_sram_blwl_out[316:316] ,mux_2level_size5_1_sram_blwl_outb[316:316] ,mux_2level_size5_1_configbus0[316:316], mux_2level_size5_1_configbus1[316:316] , mux_2level_size5_1_configbus0_b[316:316] ); -wire [0:4] in_bus_mux_2level_size5_2_ ; -assign in_bus_mux_2level_size5_2_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size5_2_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size5_2_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size5_2_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size5_2_[4] = fle_0___out_0_ ; -wire [317:322] mux_2level_size5_2_configbus0; -wire [317:322] mux_2level_size5_2_configbus1; -wire [317:322] mux_2level_size5_2_sram_blwl_out ; -wire [317:322] mux_2level_size5_2_sram_blwl_outb ; -assign mux_2level_size5_2_configbus0[317:322] = sram_blwl_bl[317:322] ; -assign mux_2level_size5_2_configbus1[317:322] = sram_blwl_wl[317:322] ; -wire [317:322] mux_2level_size5_2_configbus0_b; -assign mux_2level_size5_2_configbus0_b[317:322] = sram_blwl_blb[317:322] ; -mux_2level_size5 mux_2level_size5_2_ (in_bus_mux_2level_size5_2_, fle_0___in_2_, mux_2level_size5_2_sram_blwl_out[317:322] , -mux_2level_size5_2_sram_blwl_outb[317:322] ); -//----- SRAM bits for MUX[2], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100100----- -sram6T_blwl sram_blwl_317_ (mux_2level_size5_2_sram_blwl_out[317:317] ,mux_2level_size5_2_sram_blwl_out[317:317] ,mux_2level_size5_2_sram_blwl_outb[317:317] ,mux_2level_size5_2_configbus0[317:317], mux_2level_size5_2_configbus1[317:317] , mux_2level_size5_2_configbus0_b[317:317] ); -sram6T_blwl sram_blwl_318_ (mux_2level_size5_2_sram_blwl_out[318:318] ,mux_2level_size5_2_sram_blwl_out[318:318] ,mux_2level_size5_2_sram_blwl_outb[318:318] ,mux_2level_size5_2_configbus0[318:318], mux_2level_size5_2_configbus1[318:318] , mux_2level_size5_2_configbus0_b[318:318] ); -sram6T_blwl sram_blwl_319_ (mux_2level_size5_2_sram_blwl_out[319:319] ,mux_2level_size5_2_sram_blwl_out[319:319] ,mux_2level_size5_2_sram_blwl_outb[319:319] ,mux_2level_size5_2_configbus0[319:319], mux_2level_size5_2_configbus1[319:319] , mux_2level_size5_2_configbus0_b[319:319] ); -sram6T_blwl sram_blwl_320_ (mux_2level_size5_2_sram_blwl_out[320:320] ,mux_2level_size5_2_sram_blwl_out[320:320] ,mux_2level_size5_2_sram_blwl_outb[320:320] ,mux_2level_size5_2_configbus0[320:320], mux_2level_size5_2_configbus1[320:320] , mux_2level_size5_2_configbus0_b[320:320] ); -sram6T_blwl sram_blwl_321_ (mux_2level_size5_2_sram_blwl_out[321:321] ,mux_2level_size5_2_sram_blwl_out[321:321] ,mux_2level_size5_2_sram_blwl_outb[321:321] ,mux_2level_size5_2_configbus0[321:321], mux_2level_size5_2_configbus1[321:321] , mux_2level_size5_2_configbus0_b[321:321] ); -sram6T_blwl sram_blwl_322_ (mux_2level_size5_2_sram_blwl_out[322:322] ,mux_2level_size5_2_sram_blwl_out[322:322] ,mux_2level_size5_2_sram_blwl_outb[322:322] ,mux_2level_size5_2_configbus0[322:322], mux_2level_size5_2_configbus1[322:322] , mux_2level_size5_2_configbus0_b[322:322] ); -wire [0:4] in_bus_mux_2level_size5_3_ ; -assign in_bus_mux_2level_size5_3_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size5_3_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size5_3_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size5_3_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size5_3_[4] = fle_0___out_0_ ; -wire [323:328] mux_2level_size5_3_configbus0; -wire [323:328] mux_2level_size5_3_configbus1; -wire [323:328] mux_2level_size5_3_sram_blwl_out ; -wire [323:328] mux_2level_size5_3_sram_blwl_outb ; -assign mux_2level_size5_3_configbus0[323:328] = sram_blwl_bl[323:328] ; -assign mux_2level_size5_3_configbus1[323:328] = sram_blwl_wl[323:328] ; -wire [323:328] mux_2level_size5_3_configbus0_b; -assign mux_2level_size5_3_configbus0_b[323:328] = sram_blwl_blb[323:328] ; -mux_2level_size5 mux_2level_size5_3_ (in_bus_mux_2level_size5_3_, fle_0___in_3_, mux_2level_size5_3_sram_blwl_out[323:328] , -mux_2level_size5_3_sram_blwl_outb[323:328] ); -//----- SRAM bits for MUX[3], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100100----- -sram6T_blwl sram_blwl_323_ (mux_2level_size5_3_sram_blwl_out[323:323] ,mux_2level_size5_3_sram_blwl_out[323:323] ,mux_2level_size5_3_sram_blwl_outb[323:323] ,mux_2level_size5_3_configbus0[323:323], mux_2level_size5_3_configbus1[323:323] , mux_2level_size5_3_configbus0_b[323:323] ); -sram6T_blwl sram_blwl_324_ (mux_2level_size5_3_sram_blwl_out[324:324] ,mux_2level_size5_3_sram_blwl_out[324:324] ,mux_2level_size5_3_sram_blwl_outb[324:324] ,mux_2level_size5_3_configbus0[324:324], mux_2level_size5_3_configbus1[324:324] , mux_2level_size5_3_configbus0_b[324:324] ); -sram6T_blwl sram_blwl_325_ (mux_2level_size5_3_sram_blwl_out[325:325] ,mux_2level_size5_3_sram_blwl_out[325:325] ,mux_2level_size5_3_sram_blwl_outb[325:325] ,mux_2level_size5_3_configbus0[325:325], mux_2level_size5_3_configbus1[325:325] , mux_2level_size5_3_configbus0_b[325:325] ); -sram6T_blwl sram_blwl_326_ (mux_2level_size5_3_sram_blwl_out[326:326] ,mux_2level_size5_3_sram_blwl_out[326:326] ,mux_2level_size5_3_sram_blwl_outb[326:326] ,mux_2level_size5_3_configbus0[326:326], mux_2level_size5_3_configbus1[326:326] , mux_2level_size5_3_configbus0_b[326:326] ); -sram6T_blwl sram_blwl_327_ (mux_2level_size5_3_sram_blwl_out[327:327] ,mux_2level_size5_3_sram_blwl_out[327:327] ,mux_2level_size5_3_sram_blwl_outb[327:327] ,mux_2level_size5_3_configbus0[327:327], mux_2level_size5_3_configbus1[327:327] , mux_2level_size5_3_configbus0_b[327:327] ); -sram6T_blwl sram_blwl_328_ (mux_2level_size5_3_sram_blwl_out[328:328] ,mux_2level_size5_3_sram_blwl_out[328:328] ,mux_2level_size5_3_sram_blwl_outb[328:328] ,mux_2level_size5_3_configbus0[328:328], mux_2level_size5_3_configbus1[328:328] , mux_2level_size5_3_configbus0_b[328:328] ); -direct_interc direct_interc_13_ (mode_clb___clk_0_, fle_0___clk_0_ ); -endmodule -//----- END Programmable logic block Verilog module grid_1__1__clb_0__mode_clb_ ----- - -//----- END ----- - -//----- Grid[1][1], Capactity: 1 ----- -//----- Top Protocol ----- -module grid_1__1_( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input top_height_0__pin_0_, -output top_height_0__pin_4_, -input right_height_0__pin_1_, -input right_height_0__pin_5_, -input bottom_height_0__pin_2_, -input left_height_0__pin_3_, -input [288:328] sram_blwl_bl , -input [288:328] sram_blwl_wl , -input [288:328] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb_ grid_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_0_ , -right_height_0__pin_1_ , -bottom_height_0__pin_2_ , -left_height_0__pin_3_ , -top_height_0__pin_4_ , -right_height_0__pin_5_ -//---- IOPAD ---- -, -//---- SRAM ---- -sram_blwl_bl[288:328] , -sram_blwl_wl[288:328] , -sram_blwl_blb[288:328] ); -endmodule -//----- END Top Protocol ----- -//----- END Grid[1][1], Capactity: 1 ----- - diff --git a/examples/verilog_test_example_1/lb/grid_1_2.v b/examples/verilog_test_example_1/lb/grid_1_2.v deleted file mode 100644 index 8e85aa17d..000000000 --- a/examples/verilog_test_example_1/lb/grid_1_2.v +++ /dev/null @@ -1,694 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Physical Logic Block [1][2] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Grid[1][2] type_descriptor: io[0] ----- -//----- IO Verilog module: grid_1__2__io_0__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_0__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [24:24] gfpga_pad_iopad -, -input [353:353] sram_blwl_bl , -input [353:353] sram_blwl_wl , -input [353:353] sram_blwl_blb ); -wire [353:353] sram_blwl_out ; -wire [353:353] sram_blwl_outb ; -wire [353:353] sram_blwl_353_configbus0; -wire [353:353] sram_blwl_353_configbus1; -wire [353:353] sram_blwl_353_configbus0_b; -assign sram_blwl_353_configbus0[353:353] = sram_blwl_bl[353:353] ; -assign sram_blwl_353_configbus1[353:353] = sram_blwl_wl[353:353] ; -assign sram_blwl_353_configbus0_b[353:353] = sram_blwl_blb[353:353] ; -iopad iopad_24_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[24], sram_blwl_out[353:353] , sram_blwl_outb[353:353] ); -sram6T_blwl sram_blwl_353_ (sram_blwl_out[353], sram_blwl_out[353], sram_blwl_outb[353], sram_blwl_353_configbus0[353:353], sram_blwl_353_configbus1[353:353] , sram_blwl_353_configbus0_b[353:353] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_0__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_0__mode_io_phy_ ----- -module grid_1__2__io_0__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [24:24] gfpga_pad_iopad , -input [353:353] sram_blwl_bl , -input [353:353] sram_blwl_wl , -input [353:353] sram_blwl_blb ); -grid_1__2__io_0__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[24:24] , -sram_blwl_bl[353:353] , -sram_blwl_wl[353:353] , -sram_blwl_blb[353:353] ); -direct_interc direct_interc_62_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_63_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_0__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[1] ----- -//----- IO Verilog module: grid_1__2__io_1__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_1__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [25:25] gfpga_pad_iopad -, -input [354:354] sram_blwl_bl , -input [354:354] sram_blwl_wl , -input [354:354] sram_blwl_blb ); -wire [354:354] sram_blwl_out ; -wire [354:354] sram_blwl_outb ; -wire [354:354] sram_blwl_354_configbus0; -wire [354:354] sram_blwl_354_configbus1; -wire [354:354] sram_blwl_354_configbus0_b; -assign sram_blwl_354_configbus0[354:354] = sram_blwl_bl[354:354] ; -assign sram_blwl_354_configbus1[354:354] = sram_blwl_wl[354:354] ; -assign sram_blwl_354_configbus0_b[354:354] = sram_blwl_blb[354:354] ; -iopad iopad_25_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[25], sram_blwl_out[354:354] , sram_blwl_outb[354:354] ); -sram6T_blwl sram_blwl_354_ (sram_blwl_out[354], sram_blwl_out[354], sram_blwl_outb[354], sram_blwl_354_configbus0[354:354], sram_blwl_354_configbus1[354:354] , sram_blwl_354_configbus0_b[354:354] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_1__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_1__mode_io_phy_ ----- -module grid_1__2__io_1__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [25:25] gfpga_pad_iopad , -input [354:354] sram_blwl_bl , -input [354:354] sram_blwl_wl , -input [354:354] sram_blwl_blb ); -grid_1__2__io_1__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[25:25] , -sram_blwl_bl[354:354] , -sram_blwl_wl[354:354] , -sram_blwl_blb[354:354] ); -direct_interc direct_interc_64_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_65_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_1__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[2] ----- -//----- IO Verilog module: grid_1__2__io_2__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_2__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [26:26] gfpga_pad_iopad -, -input [355:355] sram_blwl_bl , -input [355:355] sram_blwl_wl , -input [355:355] sram_blwl_blb ); -wire [355:355] sram_blwl_out ; -wire [355:355] sram_blwl_outb ; -wire [355:355] sram_blwl_355_configbus0; -wire [355:355] sram_blwl_355_configbus1; -wire [355:355] sram_blwl_355_configbus0_b; -assign sram_blwl_355_configbus0[355:355] = sram_blwl_bl[355:355] ; -assign sram_blwl_355_configbus1[355:355] = sram_blwl_wl[355:355] ; -assign sram_blwl_355_configbus0_b[355:355] = sram_blwl_blb[355:355] ; -iopad iopad_26_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[26], sram_blwl_out[355:355] , sram_blwl_outb[355:355] ); -sram6T_blwl sram_blwl_355_ (sram_blwl_out[355], sram_blwl_out[355], sram_blwl_outb[355], sram_blwl_355_configbus0[355:355], sram_blwl_355_configbus1[355:355] , sram_blwl_355_configbus0_b[355:355] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_2__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_2__mode_io_phy_ ----- -module grid_1__2__io_2__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [26:26] gfpga_pad_iopad , -input [355:355] sram_blwl_bl , -input [355:355] sram_blwl_wl , -input [355:355] sram_blwl_blb ); -grid_1__2__io_2__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[26:26] , -sram_blwl_bl[355:355] , -sram_blwl_wl[355:355] , -sram_blwl_blb[355:355] ); -direct_interc direct_interc_66_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_67_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_2__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[3] ----- -//----- IO Verilog module: grid_1__2__io_3__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_3__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [27:27] gfpga_pad_iopad -, -input [356:356] sram_blwl_bl , -input [356:356] sram_blwl_wl , -input [356:356] sram_blwl_blb ); -wire [356:356] sram_blwl_out ; -wire [356:356] sram_blwl_outb ; -wire [356:356] sram_blwl_356_configbus0; -wire [356:356] sram_blwl_356_configbus1; -wire [356:356] sram_blwl_356_configbus0_b; -assign sram_blwl_356_configbus0[356:356] = sram_blwl_bl[356:356] ; -assign sram_blwl_356_configbus1[356:356] = sram_blwl_wl[356:356] ; -assign sram_blwl_356_configbus0_b[356:356] = sram_blwl_blb[356:356] ; -iopad iopad_27_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[27], sram_blwl_out[356:356] , sram_blwl_outb[356:356] ); -sram6T_blwl sram_blwl_356_ (sram_blwl_out[356], sram_blwl_out[356], sram_blwl_outb[356], sram_blwl_356_configbus0[356:356], sram_blwl_356_configbus1[356:356] , sram_blwl_356_configbus0_b[356:356] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_3__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_3__mode_io_phy_ ----- -module grid_1__2__io_3__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [27:27] gfpga_pad_iopad , -input [356:356] sram_blwl_bl , -input [356:356] sram_blwl_wl , -input [356:356] sram_blwl_blb ); -grid_1__2__io_3__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[27:27] , -sram_blwl_bl[356:356] , -sram_blwl_wl[356:356] , -sram_blwl_blb[356:356] ); -direct_interc direct_interc_68_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_69_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_3__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[4] ----- -//----- IO Verilog module: grid_1__2__io_4__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_4__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [28:28] gfpga_pad_iopad -, -input [357:357] sram_blwl_bl , -input [357:357] sram_blwl_wl , -input [357:357] sram_blwl_blb ); -wire [357:357] sram_blwl_out ; -wire [357:357] sram_blwl_outb ; -wire [357:357] sram_blwl_357_configbus0; -wire [357:357] sram_blwl_357_configbus1; -wire [357:357] sram_blwl_357_configbus0_b; -assign sram_blwl_357_configbus0[357:357] = sram_blwl_bl[357:357] ; -assign sram_blwl_357_configbus1[357:357] = sram_blwl_wl[357:357] ; -assign sram_blwl_357_configbus0_b[357:357] = sram_blwl_blb[357:357] ; -iopad iopad_28_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[28], sram_blwl_out[357:357] , sram_blwl_outb[357:357] ); -sram6T_blwl sram_blwl_357_ (sram_blwl_out[357], sram_blwl_out[357], sram_blwl_outb[357], sram_blwl_357_configbus0[357:357], sram_blwl_357_configbus1[357:357] , sram_blwl_357_configbus0_b[357:357] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_4__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_4__mode_io_phy_ ----- -module grid_1__2__io_4__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [28:28] gfpga_pad_iopad , -input [357:357] sram_blwl_bl , -input [357:357] sram_blwl_wl , -input [357:357] sram_blwl_blb ); -grid_1__2__io_4__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[28:28] , -sram_blwl_bl[357:357] , -sram_blwl_wl[357:357] , -sram_blwl_blb[357:357] ); -direct_interc direct_interc_70_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_71_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_4__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[5] ----- -//----- IO Verilog module: grid_1__2__io_5__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_5__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [29:29] gfpga_pad_iopad -, -input [358:358] sram_blwl_bl , -input [358:358] sram_blwl_wl , -input [358:358] sram_blwl_blb ); -wire [358:358] sram_blwl_out ; -wire [358:358] sram_blwl_outb ; -wire [358:358] sram_blwl_358_configbus0; -wire [358:358] sram_blwl_358_configbus1; -wire [358:358] sram_blwl_358_configbus0_b; -assign sram_blwl_358_configbus0[358:358] = sram_blwl_bl[358:358] ; -assign sram_blwl_358_configbus1[358:358] = sram_blwl_wl[358:358] ; -assign sram_blwl_358_configbus0_b[358:358] = sram_blwl_blb[358:358] ; -iopad iopad_29_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[29], sram_blwl_out[358:358] , sram_blwl_outb[358:358] ); -sram6T_blwl sram_blwl_358_ (sram_blwl_out[358], sram_blwl_out[358], sram_blwl_outb[358], sram_blwl_358_configbus0[358:358], sram_blwl_358_configbus1[358:358] , sram_blwl_358_configbus0_b[358:358] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_5__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_5__mode_io_phy_ ----- -module grid_1__2__io_5__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [29:29] gfpga_pad_iopad , -input [358:358] sram_blwl_bl , -input [358:358] sram_blwl_wl , -input [358:358] sram_blwl_blb ); -grid_1__2__io_5__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[29:29] , -sram_blwl_bl[358:358] , -sram_blwl_wl[358:358] , -sram_blwl_blb[358:358] ); -direct_interc direct_interc_72_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_73_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_5__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[6] ----- -//----- IO Verilog module: grid_1__2__io_6__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_6__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [30:30] gfpga_pad_iopad -, -input [359:359] sram_blwl_bl , -input [359:359] sram_blwl_wl , -input [359:359] sram_blwl_blb ); -wire [359:359] sram_blwl_out ; -wire [359:359] sram_blwl_outb ; -wire [359:359] sram_blwl_359_configbus0; -wire [359:359] sram_blwl_359_configbus1; -wire [359:359] sram_blwl_359_configbus0_b; -assign sram_blwl_359_configbus0[359:359] = sram_blwl_bl[359:359] ; -assign sram_blwl_359_configbus1[359:359] = sram_blwl_wl[359:359] ; -assign sram_blwl_359_configbus0_b[359:359] = sram_blwl_blb[359:359] ; -iopad iopad_30_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[30], sram_blwl_out[359:359] , sram_blwl_outb[359:359] ); -sram6T_blwl sram_blwl_359_ (sram_blwl_out[359], sram_blwl_out[359], sram_blwl_outb[359], sram_blwl_359_configbus0[359:359], sram_blwl_359_configbus1[359:359] , sram_blwl_359_configbus0_b[359:359] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_6__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_6__mode_io_phy_ ----- -module grid_1__2__io_6__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [30:30] gfpga_pad_iopad , -input [359:359] sram_blwl_bl , -input [359:359] sram_blwl_wl , -input [359:359] sram_blwl_blb ); -grid_1__2__io_6__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[30:30] , -sram_blwl_bl[359:359] , -sram_blwl_wl[359:359] , -sram_blwl_blb[359:359] ); -direct_interc direct_interc_74_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_75_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_6__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[7] ----- -//----- IO Verilog module: grid_1__2__io_7__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_7__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [31:31] gfpga_pad_iopad -, -input [360:360] sram_blwl_bl , -input [360:360] sram_blwl_wl , -input [360:360] sram_blwl_blb ); -wire [360:360] sram_blwl_out ; -wire [360:360] sram_blwl_outb ; -wire [360:360] sram_blwl_360_configbus0; -wire [360:360] sram_blwl_360_configbus1; -wire [360:360] sram_blwl_360_configbus0_b; -assign sram_blwl_360_configbus0[360:360] = sram_blwl_bl[360:360] ; -assign sram_blwl_360_configbus1[360:360] = sram_blwl_wl[360:360] ; -assign sram_blwl_360_configbus0_b[360:360] = sram_blwl_blb[360:360] ; -iopad iopad_31_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[31], sram_blwl_out[360:360] , sram_blwl_outb[360:360] ); -sram6T_blwl sram_blwl_360_ (sram_blwl_out[360], sram_blwl_out[360], sram_blwl_outb[360], sram_blwl_360_configbus0[360:360], sram_blwl_360_configbus1[360:360] , sram_blwl_360_configbus0_b[360:360] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_7__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_7__mode_io_phy_ ----- -module grid_1__2__io_7__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [31:31] gfpga_pad_iopad , -input [360:360] sram_blwl_bl , -input [360:360] sram_blwl_wl , -input [360:360] sram_blwl_blb ); -grid_1__2__io_7__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[31:31] , -sram_blwl_bl[360:360] , -sram_blwl_wl[360:360] , -sram_blwl_blb[360:360] ); -direct_interc direct_interc_76_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_77_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_7__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2], Capactity: 8 ----- -//----- Top Protocol ----- -module grid_1__2_( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input bottom_height_0__pin_0_, -output bottom_height_0__pin_1_, -input bottom_height_0__pin_2_, -output bottom_height_0__pin_3_, -input bottom_height_0__pin_4_, -output bottom_height_0__pin_5_, -input bottom_height_0__pin_6_, -output bottom_height_0__pin_7_, -input bottom_height_0__pin_8_, -output bottom_height_0__pin_9_, -input bottom_height_0__pin_10_, -output bottom_height_0__pin_11_, -input bottom_height_0__pin_12_, -output bottom_height_0__pin_13_, -input bottom_height_0__pin_14_, -output bottom_height_0__pin_15_, -input [31:24] gfpga_pad_iopad , -input [353:360] sram_blwl_bl , -input [353:360] sram_blwl_wl , -input [353:360] sram_blwl_blb ); -grid_1__2__io_0__mode_io_phy_ grid_1__2__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_0_, -bottom_height_0__pin_1_ -//---- IOPAD ---- -, -gfpga_pad_iopad[24:24] , -//---- SRAM ---- -sram_blwl_bl[353:353] , -sram_blwl_wl[353:353] , -sram_blwl_blb[353:353] ); -grid_1__2__io_1__mode_io_phy_ grid_1__2__1_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_2_, -bottom_height_0__pin_3_ -//---- IOPAD ---- -, -gfpga_pad_iopad[25:25] , -//---- SRAM ---- -sram_blwl_bl[354:354] , -sram_blwl_wl[354:354] , -sram_blwl_blb[354:354] ); -grid_1__2__io_2__mode_io_phy_ grid_1__2__2_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_4_, -bottom_height_0__pin_5_ -//---- IOPAD ---- -, -gfpga_pad_iopad[26:26] , -//---- SRAM ---- -sram_blwl_bl[355:355] , -sram_blwl_wl[355:355] , -sram_blwl_blb[355:355] ); -grid_1__2__io_3__mode_io_phy_ grid_1__2__3_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_6_, -bottom_height_0__pin_7_ -//---- IOPAD ---- -, -gfpga_pad_iopad[27:27] , -//---- SRAM ---- -sram_blwl_bl[356:356] , -sram_blwl_wl[356:356] , -sram_blwl_blb[356:356] ); -grid_1__2__io_4__mode_io_phy_ grid_1__2__4_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_8_, -bottom_height_0__pin_9_ -//---- IOPAD ---- -, -gfpga_pad_iopad[28:28] , -//---- SRAM ---- -sram_blwl_bl[357:357] , -sram_blwl_wl[357:357] , -sram_blwl_blb[357:357] ); -grid_1__2__io_5__mode_io_phy_ grid_1__2__5_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_10_, -bottom_height_0__pin_11_ -//---- IOPAD ---- -, -gfpga_pad_iopad[29:29] , -//---- SRAM ---- -sram_blwl_bl[358:358] , -sram_blwl_wl[358:358] , -sram_blwl_blb[358:358] ); -grid_1__2__io_6__mode_io_phy_ grid_1__2__6_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_12_, -bottom_height_0__pin_13_ -//---- IOPAD ---- -, -gfpga_pad_iopad[30:30] , -//---- SRAM ---- -sram_blwl_bl[359:359] , -sram_blwl_wl[359:359] , -sram_blwl_blb[359:359] ); -grid_1__2__io_7__mode_io_phy_ grid_1__2__7_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_14_, -bottom_height_0__pin_15_ -//---- IOPAD ---- -, -gfpga_pad_iopad[31:31] , -//---- SRAM ---- -sram_blwl_bl[360:360] , -sram_blwl_wl[360:360] , -sram_blwl_blb[360:360] ); -endmodule -//----- END Top Protocol ----- -//----- END Grid[1][2], Capactity: 8 ----- - diff --git a/examples/verilog_test_example_1/lb/grid_2_1.v b/examples/verilog_test_example_1/lb/grid_2_1.v deleted file mode 100644 index d01f195e8..000000000 --- a/examples/verilog_test_example_1/lb/grid_2_1.v +++ /dev/null @@ -1,694 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Physical Logic Block [2][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Grid[2][1] type_descriptor: io[0] ----- -//----- IO Verilog module: grid_2__1__io_0__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_0__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [8:8] gfpga_pad_iopad -, -input [337:337] sram_blwl_bl , -input [337:337] sram_blwl_wl , -input [337:337] sram_blwl_blb ); -wire [337:337] sram_blwl_out ; -wire [337:337] sram_blwl_outb ; -wire [337:337] sram_blwl_337_configbus0; -wire [337:337] sram_blwl_337_configbus1; -wire [337:337] sram_blwl_337_configbus0_b; -assign sram_blwl_337_configbus0[337:337] = sram_blwl_bl[337:337] ; -assign sram_blwl_337_configbus1[337:337] = sram_blwl_wl[337:337] ; -assign sram_blwl_337_configbus0_b[337:337] = sram_blwl_blb[337:337] ; -iopad iopad_8_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[8], sram_blwl_out[337:337] , sram_blwl_outb[337:337] ); -sram6T_blwl sram_blwl_337_ (sram_blwl_out[337], sram_blwl_out[337], sram_blwl_outb[337], sram_blwl_337_configbus0[337:337], sram_blwl_337_configbus1[337:337] , sram_blwl_337_configbus0_b[337:337] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_0__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_0__mode_io_phy_ ----- -module grid_2__1__io_0__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [8:8] gfpga_pad_iopad , -input [337:337] sram_blwl_bl , -input [337:337] sram_blwl_wl , -input [337:337] sram_blwl_blb ); -grid_2__1__io_0__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[8:8] , -sram_blwl_bl[337:337] , -sram_blwl_wl[337:337] , -sram_blwl_blb[337:337] ); -direct_interc direct_interc_30_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_31_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_0__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[1] ----- -//----- IO Verilog module: grid_2__1__io_1__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_1__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [9:9] gfpga_pad_iopad -, -input [338:338] sram_blwl_bl , -input [338:338] sram_blwl_wl , -input [338:338] sram_blwl_blb ); -wire [338:338] sram_blwl_out ; -wire [338:338] sram_blwl_outb ; -wire [338:338] sram_blwl_338_configbus0; -wire [338:338] sram_blwl_338_configbus1; -wire [338:338] sram_blwl_338_configbus0_b; -assign sram_blwl_338_configbus0[338:338] = sram_blwl_bl[338:338] ; -assign sram_blwl_338_configbus1[338:338] = sram_blwl_wl[338:338] ; -assign sram_blwl_338_configbus0_b[338:338] = sram_blwl_blb[338:338] ; -iopad iopad_9_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[9], sram_blwl_out[338:338] , sram_blwl_outb[338:338] ); -sram6T_blwl sram_blwl_338_ (sram_blwl_out[338], sram_blwl_out[338], sram_blwl_outb[338], sram_blwl_338_configbus0[338:338], sram_blwl_338_configbus1[338:338] , sram_blwl_338_configbus0_b[338:338] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_1__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_1__mode_io_phy_ ----- -module grid_2__1__io_1__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [9:9] gfpga_pad_iopad , -input [338:338] sram_blwl_bl , -input [338:338] sram_blwl_wl , -input [338:338] sram_blwl_blb ); -grid_2__1__io_1__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[9:9] , -sram_blwl_bl[338:338] , -sram_blwl_wl[338:338] , -sram_blwl_blb[338:338] ); -direct_interc direct_interc_32_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_33_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_1__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[2] ----- -//----- IO Verilog module: grid_2__1__io_2__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_2__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [10:10] gfpga_pad_iopad -, -input [339:339] sram_blwl_bl , -input [339:339] sram_blwl_wl , -input [339:339] sram_blwl_blb ); -wire [339:339] sram_blwl_out ; -wire [339:339] sram_blwl_outb ; -wire [339:339] sram_blwl_339_configbus0; -wire [339:339] sram_blwl_339_configbus1; -wire [339:339] sram_blwl_339_configbus0_b; -assign sram_blwl_339_configbus0[339:339] = sram_blwl_bl[339:339] ; -assign sram_blwl_339_configbus1[339:339] = sram_blwl_wl[339:339] ; -assign sram_blwl_339_configbus0_b[339:339] = sram_blwl_blb[339:339] ; -iopad iopad_10_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[10], sram_blwl_out[339:339] , sram_blwl_outb[339:339] ); -sram6T_blwl sram_blwl_339_ (sram_blwl_out[339], sram_blwl_out[339], sram_blwl_outb[339], sram_blwl_339_configbus0[339:339], sram_blwl_339_configbus1[339:339] , sram_blwl_339_configbus0_b[339:339] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_2__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_2__mode_io_phy_ ----- -module grid_2__1__io_2__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [10:10] gfpga_pad_iopad , -input [339:339] sram_blwl_bl , -input [339:339] sram_blwl_wl , -input [339:339] sram_blwl_blb ); -grid_2__1__io_2__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[10:10] , -sram_blwl_bl[339:339] , -sram_blwl_wl[339:339] , -sram_blwl_blb[339:339] ); -direct_interc direct_interc_34_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_35_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_2__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[3] ----- -//----- IO Verilog module: grid_2__1__io_3__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_3__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [11:11] gfpga_pad_iopad -, -input [340:340] sram_blwl_bl , -input [340:340] sram_blwl_wl , -input [340:340] sram_blwl_blb ); -wire [340:340] sram_blwl_out ; -wire [340:340] sram_blwl_outb ; -wire [340:340] sram_blwl_340_configbus0; -wire [340:340] sram_blwl_340_configbus1; -wire [340:340] sram_blwl_340_configbus0_b; -assign sram_blwl_340_configbus0[340:340] = sram_blwl_bl[340:340] ; -assign sram_blwl_340_configbus1[340:340] = sram_blwl_wl[340:340] ; -assign sram_blwl_340_configbus0_b[340:340] = sram_blwl_blb[340:340] ; -iopad iopad_11_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[11], sram_blwl_out[340:340] , sram_blwl_outb[340:340] ); -sram6T_blwl sram_blwl_340_ (sram_blwl_out[340], sram_blwl_out[340], sram_blwl_outb[340], sram_blwl_340_configbus0[340:340], sram_blwl_340_configbus1[340:340] , sram_blwl_340_configbus0_b[340:340] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_3__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_3__mode_io_phy_ ----- -module grid_2__1__io_3__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [11:11] gfpga_pad_iopad , -input [340:340] sram_blwl_bl , -input [340:340] sram_blwl_wl , -input [340:340] sram_blwl_blb ); -grid_2__1__io_3__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[11:11] , -sram_blwl_bl[340:340] , -sram_blwl_wl[340:340] , -sram_blwl_blb[340:340] ); -direct_interc direct_interc_36_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_37_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_3__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[4] ----- -//----- IO Verilog module: grid_2__1__io_4__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_4__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [12:12] gfpga_pad_iopad -, -input [341:341] sram_blwl_bl , -input [341:341] sram_blwl_wl , -input [341:341] sram_blwl_blb ); -wire [341:341] sram_blwl_out ; -wire [341:341] sram_blwl_outb ; -wire [341:341] sram_blwl_341_configbus0; -wire [341:341] sram_blwl_341_configbus1; -wire [341:341] sram_blwl_341_configbus0_b; -assign sram_blwl_341_configbus0[341:341] = sram_blwl_bl[341:341] ; -assign sram_blwl_341_configbus1[341:341] = sram_blwl_wl[341:341] ; -assign sram_blwl_341_configbus0_b[341:341] = sram_blwl_blb[341:341] ; -iopad iopad_12_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[12], sram_blwl_out[341:341] , sram_blwl_outb[341:341] ); -sram6T_blwl sram_blwl_341_ (sram_blwl_out[341], sram_blwl_out[341], sram_blwl_outb[341], sram_blwl_341_configbus0[341:341], sram_blwl_341_configbus1[341:341] , sram_blwl_341_configbus0_b[341:341] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_4__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_4__mode_io_phy_ ----- -module grid_2__1__io_4__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [12:12] gfpga_pad_iopad , -input [341:341] sram_blwl_bl , -input [341:341] sram_blwl_wl , -input [341:341] sram_blwl_blb ); -grid_2__1__io_4__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[12:12] , -sram_blwl_bl[341:341] , -sram_blwl_wl[341:341] , -sram_blwl_blb[341:341] ); -direct_interc direct_interc_38_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_39_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_4__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[5] ----- -//----- IO Verilog module: grid_2__1__io_5__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_5__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [13:13] gfpga_pad_iopad -, -input [342:342] sram_blwl_bl , -input [342:342] sram_blwl_wl , -input [342:342] sram_blwl_blb ); -wire [342:342] sram_blwl_out ; -wire [342:342] sram_blwl_outb ; -wire [342:342] sram_blwl_342_configbus0; -wire [342:342] sram_blwl_342_configbus1; -wire [342:342] sram_blwl_342_configbus0_b; -assign sram_blwl_342_configbus0[342:342] = sram_blwl_bl[342:342] ; -assign sram_blwl_342_configbus1[342:342] = sram_blwl_wl[342:342] ; -assign sram_blwl_342_configbus0_b[342:342] = sram_blwl_blb[342:342] ; -iopad iopad_13_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[13], sram_blwl_out[342:342] , sram_blwl_outb[342:342] ); -sram6T_blwl sram_blwl_342_ (sram_blwl_out[342], sram_blwl_out[342], sram_blwl_outb[342], sram_blwl_342_configbus0[342:342], sram_blwl_342_configbus1[342:342] , sram_blwl_342_configbus0_b[342:342] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_5__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_5__mode_io_phy_ ----- -module grid_2__1__io_5__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [13:13] gfpga_pad_iopad , -input [342:342] sram_blwl_bl , -input [342:342] sram_blwl_wl , -input [342:342] sram_blwl_blb ); -grid_2__1__io_5__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[13:13] , -sram_blwl_bl[342:342] , -sram_blwl_wl[342:342] , -sram_blwl_blb[342:342] ); -direct_interc direct_interc_40_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_41_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_5__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[6] ----- -//----- IO Verilog module: grid_2__1__io_6__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_6__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [14:14] gfpga_pad_iopad -, -input [343:343] sram_blwl_bl , -input [343:343] sram_blwl_wl , -input [343:343] sram_blwl_blb ); -wire [343:343] sram_blwl_out ; -wire [343:343] sram_blwl_outb ; -wire [343:343] sram_blwl_343_configbus0; -wire [343:343] sram_blwl_343_configbus1; -wire [343:343] sram_blwl_343_configbus0_b; -assign sram_blwl_343_configbus0[343:343] = sram_blwl_bl[343:343] ; -assign sram_blwl_343_configbus1[343:343] = sram_blwl_wl[343:343] ; -assign sram_blwl_343_configbus0_b[343:343] = sram_blwl_blb[343:343] ; -iopad iopad_14_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[14], sram_blwl_out[343:343] , sram_blwl_outb[343:343] ); -sram6T_blwl sram_blwl_343_ (sram_blwl_out[343], sram_blwl_out[343], sram_blwl_outb[343], sram_blwl_343_configbus0[343:343], sram_blwl_343_configbus1[343:343] , sram_blwl_343_configbus0_b[343:343] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_6__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_6__mode_io_phy_ ----- -module grid_2__1__io_6__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [14:14] gfpga_pad_iopad , -input [343:343] sram_blwl_bl , -input [343:343] sram_blwl_wl , -input [343:343] sram_blwl_blb ); -grid_2__1__io_6__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[14:14] , -sram_blwl_bl[343:343] , -sram_blwl_wl[343:343] , -sram_blwl_blb[343:343] ); -direct_interc direct_interc_42_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_43_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_6__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[7] ----- -//----- IO Verilog module: grid_2__1__io_7__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_7__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [15:15] gfpga_pad_iopad -, -input [344:344] sram_blwl_bl , -input [344:344] sram_blwl_wl , -input [344:344] sram_blwl_blb ); -wire [344:344] sram_blwl_out ; -wire [344:344] sram_blwl_outb ; -wire [344:344] sram_blwl_344_configbus0; -wire [344:344] sram_blwl_344_configbus1; -wire [344:344] sram_blwl_344_configbus0_b; -assign sram_blwl_344_configbus0[344:344] = sram_blwl_bl[344:344] ; -assign sram_blwl_344_configbus1[344:344] = sram_blwl_wl[344:344] ; -assign sram_blwl_344_configbus0_b[344:344] = sram_blwl_blb[344:344] ; -iopad iopad_15_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[15], sram_blwl_out[344:344] , sram_blwl_outb[344:344] ); -sram6T_blwl sram_blwl_344_ (sram_blwl_out[344], sram_blwl_out[344], sram_blwl_outb[344], sram_blwl_344_configbus0[344:344], sram_blwl_344_configbus1[344:344] , sram_blwl_344_configbus0_b[344:344] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_7__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_7__mode_io_phy_ ----- -module grid_2__1__io_7__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [15:15] gfpga_pad_iopad , -input [344:344] sram_blwl_bl , -input [344:344] sram_blwl_wl , -input [344:344] sram_blwl_blb ); -grid_2__1__io_7__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[15:15] , -sram_blwl_bl[344:344] , -sram_blwl_wl[344:344] , -sram_blwl_blb[344:344] ); -direct_interc direct_interc_44_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_45_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_7__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1], Capactity: 8 ----- -//----- Top Protocol ----- -module grid_2__1_( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input left_height_0__pin_0_, -output left_height_0__pin_1_, -input left_height_0__pin_2_, -output left_height_0__pin_3_, -input left_height_0__pin_4_, -output left_height_0__pin_5_, -input left_height_0__pin_6_, -output left_height_0__pin_7_, -input left_height_0__pin_8_, -output left_height_0__pin_9_, -input left_height_0__pin_10_, -output left_height_0__pin_11_, -input left_height_0__pin_12_, -output left_height_0__pin_13_, -input left_height_0__pin_14_, -output left_height_0__pin_15_, -input [15:8] gfpga_pad_iopad , -input [337:344] sram_blwl_bl , -input [337:344] sram_blwl_wl , -input [337:344] sram_blwl_blb ); -grid_2__1__io_0__mode_io_phy_ grid_2__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_0_, -left_height_0__pin_1_ -//---- IOPAD ---- -, -gfpga_pad_iopad[8:8] , -//---- SRAM ---- -sram_blwl_bl[337:337] , -sram_blwl_wl[337:337] , -sram_blwl_blb[337:337] ); -grid_2__1__io_1__mode_io_phy_ grid_2__1__1_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_2_, -left_height_0__pin_3_ -//---- IOPAD ---- -, -gfpga_pad_iopad[9:9] , -//---- SRAM ---- -sram_blwl_bl[338:338] , -sram_blwl_wl[338:338] , -sram_blwl_blb[338:338] ); -grid_2__1__io_2__mode_io_phy_ grid_2__1__2_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_4_, -left_height_0__pin_5_ -//---- IOPAD ---- -, -gfpga_pad_iopad[10:10] , -//---- SRAM ---- -sram_blwl_bl[339:339] , -sram_blwl_wl[339:339] , -sram_blwl_blb[339:339] ); -grid_2__1__io_3__mode_io_phy_ grid_2__1__3_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_6_, -left_height_0__pin_7_ -//---- IOPAD ---- -, -gfpga_pad_iopad[11:11] , -//---- SRAM ---- -sram_blwl_bl[340:340] , -sram_blwl_wl[340:340] , -sram_blwl_blb[340:340] ); -grid_2__1__io_4__mode_io_phy_ grid_2__1__4_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_8_, -left_height_0__pin_9_ -//---- IOPAD ---- -, -gfpga_pad_iopad[12:12] , -//---- SRAM ---- -sram_blwl_bl[341:341] , -sram_blwl_wl[341:341] , -sram_blwl_blb[341:341] ); -grid_2__1__io_5__mode_io_phy_ grid_2__1__5_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_10_, -left_height_0__pin_11_ -//---- IOPAD ---- -, -gfpga_pad_iopad[13:13] , -//---- SRAM ---- -sram_blwl_bl[342:342] , -sram_blwl_wl[342:342] , -sram_blwl_blb[342:342] ); -grid_2__1__io_6__mode_io_phy_ grid_2__1__6_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_12_, -left_height_0__pin_13_ -//---- IOPAD ---- -, -gfpga_pad_iopad[14:14] , -//---- SRAM ---- -sram_blwl_bl[343:343] , -sram_blwl_wl[343:343] , -sram_blwl_blb[343:343] ); -grid_2__1__io_7__mode_io_phy_ grid_2__1__7_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_14_, -left_height_0__pin_15_ -//---- IOPAD ---- -, -gfpga_pad_iopad[15:15] , -//---- SRAM ---- -sram_blwl_bl[344:344] , -sram_blwl_wl[344:344] , -sram_blwl_blb[344:344] ); -endmodule -//----- END Top Protocol ----- -//----- END Grid[2][1], Capactity: 8 ----- - diff --git a/examples/verilog_test_example_1/lb/logic_blocks.v b/examples/verilog_test_example_1/lb/logic_blocks.v deleted file mode 100644 index 2402aed3b..000000000 --- a/examples/verilog_test_example_1/lb/logic_blocks.v +++ /dev/null @@ -1,16 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Header file -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -`include "./verilog_test_example_1/lb/grid_1_2.v" -`include "./verilog_test_example_1/lb/grid_1_0.v" -`include "./verilog_test_example_1/lb/grid_2_1.v" -`include "./verilog_test_example_1/lb/grid_0_1.v" -`include "./verilog_test_example_1/lb/grid_1_1.v" diff --git a/examples/verilog_test_example_1/routing/cbx_1_0.v b/examples/verilog_test_example_1/routing/cbx_1_0.v deleted file mode 100644 index bd5e71849..000000000 --- a/examples/verilog_test_example_1/routing/cbx_1_0.v +++ /dev/null @@ -1,302 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Connection Block - X direction [1][0] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Connection Box -X direction [1][0] ----- -module cbx_1__0_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input chanx_1__0__midout_0_, - -input chanx_1__0__midout_1_, - -input chanx_1__0__midout_2_, - -input chanx_1__0__midout_3_, - -input chanx_1__0__midout_4_, - -input chanx_1__0__midout_5_, - -input chanx_1__0__midout_6_, - -input chanx_1__0__midout_7_, - -input chanx_1__0__midout_8_, - -input chanx_1__0__midout_9_, - -input chanx_1__0__midout_10_, - -input chanx_1__0__midout_11_, - -input chanx_1__0__midout_12_, - -input chanx_1__0__midout_13_, - -input chanx_1__0__midout_14_, - -input chanx_1__0__midout_15_, - -input chanx_1__0__midout_16_, - -input chanx_1__0__midout_17_, - -input chanx_1__0__midout_18_, - -input chanx_1__0__midout_19_, - -input chanx_1__0__midout_20_, - -input chanx_1__0__midout_21_, - -input chanx_1__0__midout_22_, - -input chanx_1__0__midout_23_, - -input chanx_1__0__midout_24_, - -input chanx_1__0__midout_25_, - -input chanx_1__0__midout_26_, - -input chanx_1__0__midout_27_, - -input chanx_1__0__midout_28_, - -input chanx_1__0__midout_29_, - -output grid_1__1__pin_0__2__2_, - -output grid_1__0__pin_0__0__0_, - -output grid_1__0__pin_0__0__2_, - -output grid_1__0__pin_0__0__4_, - -output grid_1__0__pin_0__0__6_, - -output grid_1__0__pin_0__0__8_, - -output grid_1__0__pin_0__0__10_, - -output grid_1__0__pin_0__0__12_, - -output grid_1__0__pin_0__0__14_, - -input [144:179] sram_blwl_bl , -input [144:179] sram_blwl_wl , -input [144:179] sram_blwl_blb ); -wire [0:3] mux_2level_tapbuf_size4_0_inbus; -assign mux_2level_tapbuf_size4_0_inbus[0] = chanx_1__0__midout_6_; -assign mux_2level_tapbuf_size4_0_inbus[1] = chanx_1__0__midout_7_; -assign mux_2level_tapbuf_size4_0_inbus[2] = chanx_1__0__midout_22_; -assign mux_2level_tapbuf_size4_0_inbus[3] = chanx_1__0__midout_23_; -wire [144:147] mux_2level_tapbuf_size4_0_configbus0; -wire [144:147] mux_2level_tapbuf_size4_0_configbus1; -wire [144:147] mux_2level_tapbuf_size4_0_sram_blwl_out ; -wire [144:147] mux_2level_tapbuf_size4_0_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_0_configbus0[144:147] = sram_blwl_bl[144:147] ; -assign mux_2level_tapbuf_size4_0_configbus1[144:147] = sram_blwl_wl[144:147] ; -wire [144:147] mux_2level_tapbuf_size4_0_configbus0_b; -assign mux_2level_tapbuf_size4_0_configbus0_b[144:147] = sram_blwl_blb[144:147] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_0_ (mux_2level_tapbuf_size4_0_inbus, grid_1__1__pin_0__2__2_, mux_2level_tapbuf_size4_0_sram_blwl_out[144:147] , -mux_2level_tapbuf_size4_0_sram_blwl_outb[144:147] ); -//----- SRAM bits for MUX[0], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_144_ (mux_2level_tapbuf_size4_0_sram_blwl_out[144:144] ,mux_2level_tapbuf_size4_0_sram_blwl_out[144:144] ,mux_2level_tapbuf_size4_0_sram_blwl_outb[144:144] ,mux_2level_tapbuf_size4_0_configbus0[144:144], mux_2level_tapbuf_size4_0_configbus1[144:144] , mux_2level_tapbuf_size4_0_configbus0_b[144:144] ); -sram6T_blwl sram_blwl_145_ (mux_2level_tapbuf_size4_0_sram_blwl_out[145:145] ,mux_2level_tapbuf_size4_0_sram_blwl_out[145:145] ,mux_2level_tapbuf_size4_0_sram_blwl_outb[145:145] ,mux_2level_tapbuf_size4_0_configbus0[145:145], mux_2level_tapbuf_size4_0_configbus1[145:145] , mux_2level_tapbuf_size4_0_configbus0_b[145:145] ); -sram6T_blwl sram_blwl_146_ (mux_2level_tapbuf_size4_0_sram_blwl_out[146:146] ,mux_2level_tapbuf_size4_0_sram_blwl_out[146:146] ,mux_2level_tapbuf_size4_0_sram_blwl_outb[146:146] ,mux_2level_tapbuf_size4_0_configbus0[146:146], mux_2level_tapbuf_size4_0_configbus1[146:146] , mux_2level_tapbuf_size4_0_configbus0_b[146:146] ); -sram6T_blwl sram_blwl_147_ (mux_2level_tapbuf_size4_0_sram_blwl_out[147:147] ,mux_2level_tapbuf_size4_0_sram_blwl_out[147:147] ,mux_2level_tapbuf_size4_0_sram_blwl_outb[147:147] ,mux_2level_tapbuf_size4_0_configbus0[147:147], mux_2level_tapbuf_size4_0_configbus1[147:147] , mux_2level_tapbuf_size4_0_configbus0_b[147:147] ); -wire [0:3] mux_2level_tapbuf_size4_1_inbus; -assign mux_2level_tapbuf_size4_1_inbus[0] = chanx_1__0__midout_0_; -assign mux_2level_tapbuf_size4_1_inbus[1] = chanx_1__0__midout_1_; -assign mux_2level_tapbuf_size4_1_inbus[2] = chanx_1__0__midout_14_; -assign mux_2level_tapbuf_size4_1_inbus[3] = chanx_1__0__midout_15_; -wire [148:151] mux_2level_tapbuf_size4_1_configbus0; -wire [148:151] mux_2level_tapbuf_size4_1_configbus1; -wire [148:151] mux_2level_tapbuf_size4_1_sram_blwl_out ; -wire [148:151] mux_2level_tapbuf_size4_1_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_1_configbus0[148:151] = sram_blwl_bl[148:151] ; -assign mux_2level_tapbuf_size4_1_configbus1[148:151] = sram_blwl_wl[148:151] ; -wire [148:151] mux_2level_tapbuf_size4_1_configbus0_b; -assign mux_2level_tapbuf_size4_1_configbus0_b[148:151] = sram_blwl_blb[148:151] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_1_ (mux_2level_tapbuf_size4_1_inbus, grid_1__0__pin_0__0__0_, mux_2level_tapbuf_size4_1_sram_blwl_out[148:151] , -mux_2level_tapbuf_size4_1_sram_blwl_outb[148:151] ); -//----- SRAM bits for MUX[1], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_148_ (mux_2level_tapbuf_size4_1_sram_blwl_out[148:148] ,mux_2level_tapbuf_size4_1_sram_blwl_out[148:148] ,mux_2level_tapbuf_size4_1_sram_blwl_outb[148:148] ,mux_2level_tapbuf_size4_1_configbus0[148:148], mux_2level_tapbuf_size4_1_configbus1[148:148] , mux_2level_tapbuf_size4_1_configbus0_b[148:148] ); -sram6T_blwl sram_blwl_149_ (mux_2level_tapbuf_size4_1_sram_blwl_out[149:149] ,mux_2level_tapbuf_size4_1_sram_blwl_out[149:149] ,mux_2level_tapbuf_size4_1_sram_blwl_outb[149:149] ,mux_2level_tapbuf_size4_1_configbus0[149:149], mux_2level_tapbuf_size4_1_configbus1[149:149] , mux_2level_tapbuf_size4_1_configbus0_b[149:149] ); -sram6T_blwl sram_blwl_150_ (mux_2level_tapbuf_size4_1_sram_blwl_out[150:150] ,mux_2level_tapbuf_size4_1_sram_blwl_out[150:150] ,mux_2level_tapbuf_size4_1_sram_blwl_outb[150:150] ,mux_2level_tapbuf_size4_1_configbus0[150:150], mux_2level_tapbuf_size4_1_configbus1[150:150] , mux_2level_tapbuf_size4_1_configbus0_b[150:150] ); -sram6T_blwl sram_blwl_151_ (mux_2level_tapbuf_size4_1_sram_blwl_out[151:151] ,mux_2level_tapbuf_size4_1_sram_blwl_out[151:151] ,mux_2level_tapbuf_size4_1_sram_blwl_outb[151:151] ,mux_2level_tapbuf_size4_1_configbus0[151:151], mux_2level_tapbuf_size4_1_configbus1[151:151] , mux_2level_tapbuf_size4_1_configbus0_b[151:151] ); -wire [0:3] mux_2level_tapbuf_size4_2_inbus; -assign mux_2level_tapbuf_size4_2_inbus[0] = chanx_1__0__midout_0_; -assign mux_2level_tapbuf_size4_2_inbus[1] = chanx_1__0__midout_1_; -assign mux_2level_tapbuf_size4_2_inbus[2] = chanx_1__0__midout_16_; -assign mux_2level_tapbuf_size4_2_inbus[3] = chanx_1__0__midout_17_; -wire [152:155] mux_2level_tapbuf_size4_2_configbus0; -wire [152:155] mux_2level_tapbuf_size4_2_configbus1; -wire [152:155] mux_2level_tapbuf_size4_2_sram_blwl_out ; -wire [152:155] mux_2level_tapbuf_size4_2_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_2_configbus0[152:155] = sram_blwl_bl[152:155] ; -assign mux_2level_tapbuf_size4_2_configbus1[152:155] = sram_blwl_wl[152:155] ; -wire [152:155] mux_2level_tapbuf_size4_2_configbus0_b; -assign mux_2level_tapbuf_size4_2_configbus0_b[152:155] = sram_blwl_blb[152:155] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_2_ (mux_2level_tapbuf_size4_2_inbus, grid_1__0__pin_0__0__2_, mux_2level_tapbuf_size4_2_sram_blwl_out[152:155] , -mux_2level_tapbuf_size4_2_sram_blwl_outb[152:155] ); -//----- SRAM bits for MUX[2], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_152_ (mux_2level_tapbuf_size4_2_sram_blwl_out[152:152] ,mux_2level_tapbuf_size4_2_sram_blwl_out[152:152] ,mux_2level_tapbuf_size4_2_sram_blwl_outb[152:152] ,mux_2level_tapbuf_size4_2_configbus0[152:152], mux_2level_tapbuf_size4_2_configbus1[152:152] , mux_2level_tapbuf_size4_2_configbus0_b[152:152] ); -sram6T_blwl sram_blwl_153_ (mux_2level_tapbuf_size4_2_sram_blwl_out[153:153] ,mux_2level_tapbuf_size4_2_sram_blwl_out[153:153] ,mux_2level_tapbuf_size4_2_sram_blwl_outb[153:153] ,mux_2level_tapbuf_size4_2_configbus0[153:153], mux_2level_tapbuf_size4_2_configbus1[153:153] , mux_2level_tapbuf_size4_2_configbus0_b[153:153] ); -sram6T_blwl sram_blwl_154_ (mux_2level_tapbuf_size4_2_sram_blwl_out[154:154] ,mux_2level_tapbuf_size4_2_sram_blwl_out[154:154] ,mux_2level_tapbuf_size4_2_sram_blwl_outb[154:154] ,mux_2level_tapbuf_size4_2_configbus0[154:154], mux_2level_tapbuf_size4_2_configbus1[154:154] , mux_2level_tapbuf_size4_2_configbus0_b[154:154] ); -sram6T_blwl sram_blwl_155_ (mux_2level_tapbuf_size4_2_sram_blwl_out[155:155] ,mux_2level_tapbuf_size4_2_sram_blwl_out[155:155] ,mux_2level_tapbuf_size4_2_sram_blwl_outb[155:155] ,mux_2level_tapbuf_size4_2_configbus0[155:155], mux_2level_tapbuf_size4_2_configbus1[155:155] , mux_2level_tapbuf_size4_2_configbus0_b[155:155] ); -wire [0:3] mux_2level_tapbuf_size4_3_inbus; -assign mux_2level_tapbuf_size4_3_inbus[0] = chanx_1__0__midout_2_; -assign mux_2level_tapbuf_size4_3_inbus[1] = chanx_1__0__midout_3_; -assign mux_2level_tapbuf_size4_3_inbus[2] = chanx_1__0__midout_18_; -assign mux_2level_tapbuf_size4_3_inbus[3] = chanx_1__0__midout_19_; -wire [156:159] mux_2level_tapbuf_size4_3_configbus0; -wire [156:159] mux_2level_tapbuf_size4_3_configbus1; -wire [156:159] mux_2level_tapbuf_size4_3_sram_blwl_out ; -wire [156:159] mux_2level_tapbuf_size4_3_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_3_configbus0[156:159] = sram_blwl_bl[156:159] ; -assign mux_2level_tapbuf_size4_3_configbus1[156:159] = sram_blwl_wl[156:159] ; -wire [156:159] mux_2level_tapbuf_size4_3_configbus0_b; -assign mux_2level_tapbuf_size4_3_configbus0_b[156:159] = sram_blwl_blb[156:159] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_3_ (mux_2level_tapbuf_size4_3_inbus, grid_1__0__pin_0__0__4_, mux_2level_tapbuf_size4_3_sram_blwl_out[156:159] , -mux_2level_tapbuf_size4_3_sram_blwl_outb[156:159] ); -//----- SRAM bits for MUX[3], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_156_ (mux_2level_tapbuf_size4_3_sram_blwl_out[156:156] ,mux_2level_tapbuf_size4_3_sram_blwl_out[156:156] ,mux_2level_tapbuf_size4_3_sram_blwl_outb[156:156] ,mux_2level_tapbuf_size4_3_configbus0[156:156], mux_2level_tapbuf_size4_3_configbus1[156:156] , mux_2level_tapbuf_size4_3_configbus0_b[156:156] ); -sram6T_blwl sram_blwl_157_ (mux_2level_tapbuf_size4_3_sram_blwl_out[157:157] ,mux_2level_tapbuf_size4_3_sram_blwl_out[157:157] ,mux_2level_tapbuf_size4_3_sram_blwl_outb[157:157] ,mux_2level_tapbuf_size4_3_configbus0[157:157], mux_2level_tapbuf_size4_3_configbus1[157:157] , mux_2level_tapbuf_size4_3_configbus0_b[157:157] ); -sram6T_blwl sram_blwl_158_ (mux_2level_tapbuf_size4_3_sram_blwl_out[158:158] ,mux_2level_tapbuf_size4_3_sram_blwl_out[158:158] ,mux_2level_tapbuf_size4_3_sram_blwl_outb[158:158] ,mux_2level_tapbuf_size4_3_configbus0[158:158], mux_2level_tapbuf_size4_3_configbus1[158:158] , mux_2level_tapbuf_size4_3_configbus0_b[158:158] ); -sram6T_blwl sram_blwl_159_ (mux_2level_tapbuf_size4_3_sram_blwl_out[159:159] ,mux_2level_tapbuf_size4_3_sram_blwl_out[159:159] ,mux_2level_tapbuf_size4_3_sram_blwl_outb[159:159] ,mux_2level_tapbuf_size4_3_configbus0[159:159], mux_2level_tapbuf_size4_3_configbus1[159:159] , mux_2level_tapbuf_size4_3_configbus0_b[159:159] ); -wire [0:3] mux_2level_tapbuf_size4_4_inbus; -assign mux_2level_tapbuf_size4_4_inbus[0] = chanx_1__0__midout_4_; -assign mux_2level_tapbuf_size4_4_inbus[1] = chanx_1__0__midout_5_; -assign mux_2level_tapbuf_size4_4_inbus[2] = chanx_1__0__midout_20_; -assign mux_2level_tapbuf_size4_4_inbus[3] = chanx_1__0__midout_21_; -wire [160:163] mux_2level_tapbuf_size4_4_configbus0; -wire [160:163] mux_2level_tapbuf_size4_4_configbus1; -wire [160:163] mux_2level_tapbuf_size4_4_sram_blwl_out ; -wire [160:163] mux_2level_tapbuf_size4_4_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_4_configbus0[160:163] = sram_blwl_bl[160:163] ; -assign mux_2level_tapbuf_size4_4_configbus1[160:163] = sram_blwl_wl[160:163] ; -wire [160:163] mux_2level_tapbuf_size4_4_configbus0_b; -assign mux_2level_tapbuf_size4_4_configbus0_b[160:163] = sram_blwl_blb[160:163] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_4_ (mux_2level_tapbuf_size4_4_inbus, grid_1__0__pin_0__0__6_, mux_2level_tapbuf_size4_4_sram_blwl_out[160:163] , -mux_2level_tapbuf_size4_4_sram_blwl_outb[160:163] ); -//----- SRAM bits for MUX[4], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_160_ (mux_2level_tapbuf_size4_4_sram_blwl_out[160:160] ,mux_2level_tapbuf_size4_4_sram_blwl_out[160:160] ,mux_2level_tapbuf_size4_4_sram_blwl_outb[160:160] ,mux_2level_tapbuf_size4_4_configbus0[160:160], mux_2level_tapbuf_size4_4_configbus1[160:160] , mux_2level_tapbuf_size4_4_configbus0_b[160:160] ); -sram6T_blwl sram_blwl_161_ (mux_2level_tapbuf_size4_4_sram_blwl_out[161:161] ,mux_2level_tapbuf_size4_4_sram_blwl_out[161:161] ,mux_2level_tapbuf_size4_4_sram_blwl_outb[161:161] ,mux_2level_tapbuf_size4_4_configbus0[161:161], mux_2level_tapbuf_size4_4_configbus1[161:161] , mux_2level_tapbuf_size4_4_configbus0_b[161:161] ); -sram6T_blwl sram_blwl_162_ (mux_2level_tapbuf_size4_4_sram_blwl_out[162:162] ,mux_2level_tapbuf_size4_4_sram_blwl_out[162:162] ,mux_2level_tapbuf_size4_4_sram_blwl_outb[162:162] ,mux_2level_tapbuf_size4_4_configbus0[162:162], mux_2level_tapbuf_size4_4_configbus1[162:162] , mux_2level_tapbuf_size4_4_configbus0_b[162:162] ); -sram6T_blwl sram_blwl_163_ (mux_2level_tapbuf_size4_4_sram_blwl_out[163:163] ,mux_2level_tapbuf_size4_4_sram_blwl_out[163:163] ,mux_2level_tapbuf_size4_4_sram_blwl_outb[163:163] ,mux_2level_tapbuf_size4_4_configbus0[163:163], mux_2level_tapbuf_size4_4_configbus1[163:163] , mux_2level_tapbuf_size4_4_configbus0_b[163:163] ); -wire [0:3] mux_2level_tapbuf_size4_5_inbus; -assign mux_2level_tapbuf_size4_5_inbus[0] = chanx_1__0__midout_6_; -assign mux_2level_tapbuf_size4_5_inbus[1] = chanx_1__0__midout_7_; -assign mux_2level_tapbuf_size4_5_inbus[2] = chanx_1__0__midout_22_; -assign mux_2level_tapbuf_size4_5_inbus[3] = chanx_1__0__midout_23_; -wire [164:167] mux_2level_tapbuf_size4_5_configbus0; -wire [164:167] mux_2level_tapbuf_size4_5_configbus1; -wire [164:167] mux_2level_tapbuf_size4_5_sram_blwl_out ; -wire [164:167] mux_2level_tapbuf_size4_5_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_5_configbus0[164:167] = sram_blwl_bl[164:167] ; -assign mux_2level_tapbuf_size4_5_configbus1[164:167] = sram_blwl_wl[164:167] ; -wire [164:167] mux_2level_tapbuf_size4_5_configbus0_b; -assign mux_2level_tapbuf_size4_5_configbus0_b[164:167] = sram_blwl_blb[164:167] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_5_ (mux_2level_tapbuf_size4_5_inbus, grid_1__0__pin_0__0__8_, mux_2level_tapbuf_size4_5_sram_blwl_out[164:167] , -mux_2level_tapbuf_size4_5_sram_blwl_outb[164:167] ); -//----- SRAM bits for MUX[5], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_164_ (mux_2level_tapbuf_size4_5_sram_blwl_out[164:164] ,mux_2level_tapbuf_size4_5_sram_blwl_out[164:164] ,mux_2level_tapbuf_size4_5_sram_blwl_outb[164:164] ,mux_2level_tapbuf_size4_5_configbus0[164:164], mux_2level_tapbuf_size4_5_configbus1[164:164] , mux_2level_tapbuf_size4_5_configbus0_b[164:164] ); -sram6T_blwl sram_blwl_165_ (mux_2level_tapbuf_size4_5_sram_blwl_out[165:165] ,mux_2level_tapbuf_size4_5_sram_blwl_out[165:165] ,mux_2level_tapbuf_size4_5_sram_blwl_outb[165:165] ,mux_2level_tapbuf_size4_5_configbus0[165:165], mux_2level_tapbuf_size4_5_configbus1[165:165] , mux_2level_tapbuf_size4_5_configbus0_b[165:165] ); -sram6T_blwl sram_blwl_166_ (mux_2level_tapbuf_size4_5_sram_blwl_out[166:166] ,mux_2level_tapbuf_size4_5_sram_blwl_out[166:166] ,mux_2level_tapbuf_size4_5_sram_blwl_outb[166:166] ,mux_2level_tapbuf_size4_5_configbus0[166:166], mux_2level_tapbuf_size4_5_configbus1[166:166] , mux_2level_tapbuf_size4_5_configbus0_b[166:166] ); -sram6T_blwl sram_blwl_167_ (mux_2level_tapbuf_size4_5_sram_blwl_out[167:167] ,mux_2level_tapbuf_size4_5_sram_blwl_out[167:167] ,mux_2level_tapbuf_size4_5_sram_blwl_outb[167:167] ,mux_2level_tapbuf_size4_5_configbus0[167:167], mux_2level_tapbuf_size4_5_configbus1[167:167] , mux_2level_tapbuf_size4_5_configbus0_b[167:167] ); -wire [0:3] mux_2level_tapbuf_size4_6_inbus; -assign mux_2level_tapbuf_size4_6_inbus[0] = chanx_1__0__midout_8_; -assign mux_2level_tapbuf_size4_6_inbus[1] = chanx_1__0__midout_9_; -assign mux_2level_tapbuf_size4_6_inbus[2] = chanx_1__0__midout_24_; -assign mux_2level_tapbuf_size4_6_inbus[3] = chanx_1__0__midout_25_; -wire [168:171] mux_2level_tapbuf_size4_6_configbus0; -wire [168:171] mux_2level_tapbuf_size4_6_configbus1; -wire [168:171] mux_2level_tapbuf_size4_6_sram_blwl_out ; -wire [168:171] mux_2level_tapbuf_size4_6_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_6_configbus0[168:171] = sram_blwl_bl[168:171] ; -assign mux_2level_tapbuf_size4_6_configbus1[168:171] = sram_blwl_wl[168:171] ; -wire [168:171] mux_2level_tapbuf_size4_6_configbus0_b; -assign mux_2level_tapbuf_size4_6_configbus0_b[168:171] = sram_blwl_blb[168:171] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_6_ (mux_2level_tapbuf_size4_6_inbus, grid_1__0__pin_0__0__10_, mux_2level_tapbuf_size4_6_sram_blwl_out[168:171] , -mux_2level_tapbuf_size4_6_sram_blwl_outb[168:171] ); -//----- SRAM bits for MUX[6], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_168_ (mux_2level_tapbuf_size4_6_sram_blwl_out[168:168] ,mux_2level_tapbuf_size4_6_sram_blwl_out[168:168] ,mux_2level_tapbuf_size4_6_sram_blwl_outb[168:168] ,mux_2level_tapbuf_size4_6_configbus0[168:168], mux_2level_tapbuf_size4_6_configbus1[168:168] , mux_2level_tapbuf_size4_6_configbus0_b[168:168] ); -sram6T_blwl sram_blwl_169_ (mux_2level_tapbuf_size4_6_sram_blwl_out[169:169] ,mux_2level_tapbuf_size4_6_sram_blwl_out[169:169] ,mux_2level_tapbuf_size4_6_sram_blwl_outb[169:169] ,mux_2level_tapbuf_size4_6_configbus0[169:169], mux_2level_tapbuf_size4_6_configbus1[169:169] , mux_2level_tapbuf_size4_6_configbus0_b[169:169] ); -sram6T_blwl sram_blwl_170_ (mux_2level_tapbuf_size4_6_sram_blwl_out[170:170] ,mux_2level_tapbuf_size4_6_sram_blwl_out[170:170] ,mux_2level_tapbuf_size4_6_sram_blwl_outb[170:170] ,mux_2level_tapbuf_size4_6_configbus0[170:170], mux_2level_tapbuf_size4_6_configbus1[170:170] , mux_2level_tapbuf_size4_6_configbus0_b[170:170] ); -sram6T_blwl sram_blwl_171_ (mux_2level_tapbuf_size4_6_sram_blwl_out[171:171] ,mux_2level_tapbuf_size4_6_sram_blwl_out[171:171] ,mux_2level_tapbuf_size4_6_sram_blwl_outb[171:171] ,mux_2level_tapbuf_size4_6_configbus0[171:171], mux_2level_tapbuf_size4_6_configbus1[171:171] , mux_2level_tapbuf_size4_6_configbus0_b[171:171] ); -wire [0:3] mux_2level_tapbuf_size4_7_inbus; -assign mux_2level_tapbuf_size4_7_inbus[0] = chanx_1__0__midout_10_; -assign mux_2level_tapbuf_size4_7_inbus[1] = chanx_1__0__midout_11_; -assign mux_2level_tapbuf_size4_7_inbus[2] = chanx_1__0__midout_26_; -assign mux_2level_tapbuf_size4_7_inbus[3] = chanx_1__0__midout_27_; -wire [172:175] mux_2level_tapbuf_size4_7_configbus0; -wire [172:175] mux_2level_tapbuf_size4_7_configbus1; -wire [172:175] mux_2level_tapbuf_size4_7_sram_blwl_out ; -wire [172:175] mux_2level_tapbuf_size4_7_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_7_configbus0[172:175] = sram_blwl_bl[172:175] ; -assign mux_2level_tapbuf_size4_7_configbus1[172:175] = sram_blwl_wl[172:175] ; -wire [172:175] mux_2level_tapbuf_size4_7_configbus0_b; -assign mux_2level_tapbuf_size4_7_configbus0_b[172:175] = sram_blwl_blb[172:175] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_7_ (mux_2level_tapbuf_size4_7_inbus, grid_1__0__pin_0__0__12_, mux_2level_tapbuf_size4_7_sram_blwl_out[172:175] , -mux_2level_tapbuf_size4_7_sram_blwl_outb[172:175] ); -//----- SRAM bits for MUX[7], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_172_ (mux_2level_tapbuf_size4_7_sram_blwl_out[172:172] ,mux_2level_tapbuf_size4_7_sram_blwl_out[172:172] ,mux_2level_tapbuf_size4_7_sram_blwl_outb[172:172] ,mux_2level_tapbuf_size4_7_configbus0[172:172], mux_2level_tapbuf_size4_7_configbus1[172:172] , mux_2level_tapbuf_size4_7_configbus0_b[172:172] ); -sram6T_blwl sram_blwl_173_ (mux_2level_tapbuf_size4_7_sram_blwl_out[173:173] ,mux_2level_tapbuf_size4_7_sram_blwl_out[173:173] ,mux_2level_tapbuf_size4_7_sram_blwl_outb[173:173] ,mux_2level_tapbuf_size4_7_configbus0[173:173], mux_2level_tapbuf_size4_7_configbus1[173:173] , mux_2level_tapbuf_size4_7_configbus0_b[173:173] ); -sram6T_blwl sram_blwl_174_ (mux_2level_tapbuf_size4_7_sram_blwl_out[174:174] ,mux_2level_tapbuf_size4_7_sram_blwl_out[174:174] ,mux_2level_tapbuf_size4_7_sram_blwl_outb[174:174] ,mux_2level_tapbuf_size4_7_configbus0[174:174], mux_2level_tapbuf_size4_7_configbus1[174:174] , mux_2level_tapbuf_size4_7_configbus0_b[174:174] ); -sram6T_blwl sram_blwl_175_ (mux_2level_tapbuf_size4_7_sram_blwl_out[175:175] ,mux_2level_tapbuf_size4_7_sram_blwl_out[175:175] ,mux_2level_tapbuf_size4_7_sram_blwl_outb[175:175] ,mux_2level_tapbuf_size4_7_configbus0[175:175], mux_2level_tapbuf_size4_7_configbus1[175:175] , mux_2level_tapbuf_size4_7_configbus0_b[175:175] ); -wire [0:3] mux_2level_tapbuf_size4_8_inbus; -assign mux_2level_tapbuf_size4_8_inbus[0] = chanx_1__0__midout_12_; -assign mux_2level_tapbuf_size4_8_inbus[1] = chanx_1__0__midout_13_; -assign mux_2level_tapbuf_size4_8_inbus[2] = chanx_1__0__midout_28_; -assign mux_2level_tapbuf_size4_8_inbus[3] = chanx_1__0__midout_29_; -wire [176:179] mux_2level_tapbuf_size4_8_configbus0; -wire [176:179] mux_2level_tapbuf_size4_8_configbus1; -wire [176:179] mux_2level_tapbuf_size4_8_sram_blwl_out ; -wire [176:179] mux_2level_tapbuf_size4_8_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_8_configbus0[176:179] = sram_blwl_bl[176:179] ; -assign mux_2level_tapbuf_size4_8_configbus1[176:179] = sram_blwl_wl[176:179] ; -wire [176:179] mux_2level_tapbuf_size4_8_configbus0_b; -assign mux_2level_tapbuf_size4_8_configbus0_b[176:179] = sram_blwl_blb[176:179] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_8_ (mux_2level_tapbuf_size4_8_inbus, grid_1__0__pin_0__0__14_, mux_2level_tapbuf_size4_8_sram_blwl_out[176:179] , -mux_2level_tapbuf_size4_8_sram_blwl_outb[176:179] ); -//----- SRAM bits for MUX[8], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_176_ (mux_2level_tapbuf_size4_8_sram_blwl_out[176:176] ,mux_2level_tapbuf_size4_8_sram_blwl_out[176:176] ,mux_2level_tapbuf_size4_8_sram_blwl_outb[176:176] ,mux_2level_tapbuf_size4_8_configbus0[176:176], mux_2level_tapbuf_size4_8_configbus1[176:176] , mux_2level_tapbuf_size4_8_configbus0_b[176:176] ); -sram6T_blwl sram_blwl_177_ (mux_2level_tapbuf_size4_8_sram_blwl_out[177:177] ,mux_2level_tapbuf_size4_8_sram_blwl_out[177:177] ,mux_2level_tapbuf_size4_8_sram_blwl_outb[177:177] ,mux_2level_tapbuf_size4_8_configbus0[177:177], mux_2level_tapbuf_size4_8_configbus1[177:177] , mux_2level_tapbuf_size4_8_configbus0_b[177:177] ); -sram6T_blwl sram_blwl_178_ (mux_2level_tapbuf_size4_8_sram_blwl_out[178:178] ,mux_2level_tapbuf_size4_8_sram_blwl_out[178:178] ,mux_2level_tapbuf_size4_8_sram_blwl_outb[178:178] ,mux_2level_tapbuf_size4_8_configbus0[178:178], mux_2level_tapbuf_size4_8_configbus1[178:178] , mux_2level_tapbuf_size4_8_configbus0_b[178:178] ); -sram6T_blwl sram_blwl_179_ (mux_2level_tapbuf_size4_8_sram_blwl_out[179:179] ,mux_2level_tapbuf_size4_8_sram_blwl_out[179:179] ,mux_2level_tapbuf_size4_8_sram_blwl_outb[179:179] ,mux_2level_tapbuf_size4_8_configbus0[179:179], mux_2level_tapbuf_size4_8_configbus1[179:179] , mux_2level_tapbuf_size4_8_configbus0_b[179:179] ); -endmodule -//----- END Verilog Module of Connection Box -X direction [1][0] ----- - diff --git a/examples/verilog_test_example_1/routing/cbx_1_1.v b/examples/verilog_test_example_1/routing/cbx_1_1.v deleted file mode 100644 index e92065657..000000000 --- a/examples/verilog_test_example_1/routing/cbx_1_1.v +++ /dev/null @@ -1,302 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Connection Block - X direction [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Connection Box -X direction [1][1] ----- -module cbx_1__1_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input chanx_1__1__midout_0_, - -input chanx_1__1__midout_1_, - -input chanx_1__1__midout_2_, - -input chanx_1__1__midout_3_, - -input chanx_1__1__midout_4_, - -input chanx_1__1__midout_5_, - -input chanx_1__1__midout_6_, - -input chanx_1__1__midout_7_, - -input chanx_1__1__midout_8_, - -input chanx_1__1__midout_9_, - -input chanx_1__1__midout_10_, - -input chanx_1__1__midout_11_, - -input chanx_1__1__midout_12_, - -input chanx_1__1__midout_13_, - -input chanx_1__1__midout_14_, - -input chanx_1__1__midout_15_, - -input chanx_1__1__midout_16_, - -input chanx_1__1__midout_17_, - -input chanx_1__1__midout_18_, - -input chanx_1__1__midout_19_, - -input chanx_1__1__midout_20_, - -input chanx_1__1__midout_21_, - -input chanx_1__1__midout_22_, - -input chanx_1__1__midout_23_, - -input chanx_1__1__midout_24_, - -input chanx_1__1__midout_25_, - -input chanx_1__1__midout_26_, - -input chanx_1__1__midout_27_, - -input chanx_1__1__midout_28_, - -input chanx_1__1__midout_29_, - -output grid_1__2__pin_0__2__0_, - -output grid_1__2__pin_0__2__2_, - -output grid_1__2__pin_0__2__4_, - -output grid_1__2__pin_0__2__6_, - -output grid_1__2__pin_0__2__8_, - -output grid_1__2__pin_0__2__10_, - -output grid_1__2__pin_0__2__12_, - -output grid_1__2__pin_0__2__14_, - -output grid_1__1__pin_0__0__0_, - -input [180:215] sram_blwl_bl , -input [180:215] sram_blwl_wl , -input [180:215] sram_blwl_blb ); -wire [0:3] mux_2level_tapbuf_size4_9_inbus; -assign mux_2level_tapbuf_size4_9_inbus[0] = chanx_1__1__midout_6_; -assign mux_2level_tapbuf_size4_9_inbus[1] = chanx_1__1__midout_7_; -assign mux_2level_tapbuf_size4_9_inbus[2] = chanx_1__1__midout_12_; -assign mux_2level_tapbuf_size4_9_inbus[3] = chanx_1__1__midout_13_; -wire [180:183] mux_2level_tapbuf_size4_9_configbus0; -wire [180:183] mux_2level_tapbuf_size4_9_configbus1; -wire [180:183] mux_2level_tapbuf_size4_9_sram_blwl_out ; -wire [180:183] mux_2level_tapbuf_size4_9_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_9_configbus0[180:183] = sram_blwl_bl[180:183] ; -assign mux_2level_tapbuf_size4_9_configbus1[180:183] = sram_blwl_wl[180:183] ; -wire [180:183] mux_2level_tapbuf_size4_9_configbus0_b; -assign mux_2level_tapbuf_size4_9_configbus0_b[180:183] = sram_blwl_blb[180:183] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_9_ (mux_2level_tapbuf_size4_9_inbus, grid_1__2__pin_0__2__0_, mux_2level_tapbuf_size4_9_sram_blwl_out[180:183] , -mux_2level_tapbuf_size4_9_sram_blwl_outb[180:183] ); -//----- SRAM bits for MUX[9], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_180_ (mux_2level_tapbuf_size4_9_sram_blwl_out[180:180] ,mux_2level_tapbuf_size4_9_sram_blwl_out[180:180] ,mux_2level_tapbuf_size4_9_sram_blwl_outb[180:180] ,mux_2level_tapbuf_size4_9_configbus0[180:180], mux_2level_tapbuf_size4_9_configbus1[180:180] , mux_2level_tapbuf_size4_9_configbus0_b[180:180] ); -sram6T_blwl sram_blwl_181_ (mux_2level_tapbuf_size4_9_sram_blwl_out[181:181] ,mux_2level_tapbuf_size4_9_sram_blwl_out[181:181] ,mux_2level_tapbuf_size4_9_sram_blwl_outb[181:181] ,mux_2level_tapbuf_size4_9_configbus0[181:181], mux_2level_tapbuf_size4_9_configbus1[181:181] , mux_2level_tapbuf_size4_9_configbus0_b[181:181] ); -sram6T_blwl sram_blwl_182_ (mux_2level_tapbuf_size4_9_sram_blwl_out[182:182] ,mux_2level_tapbuf_size4_9_sram_blwl_out[182:182] ,mux_2level_tapbuf_size4_9_sram_blwl_outb[182:182] ,mux_2level_tapbuf_size4_9_configbus0[182:182], mux_2level_tapbuf_size4_9_configbus1[182:182] , mux_2level_tapbuf_size4_9_configbus0_b[182:182] ); -sram6T_blwl sram_blwl_183_ (mux_2level_tapbuf_size4_9_sram_blwl_out[183:183] ,mux_2level_tapbuf_size4_9_sram_blwl_out[183:183] ,mux_2level_tapbuf_size4_9_sram_blwl_outb[183:183] ,mux_2level_tapbuf_size4_9_configbus0[183:183], mux_2level_tapbuf_size4_9_configbus1[183:183] , mux_2level_tapbuf_size4_9_configbus0_b[183:183] ); -wire [0:3] mux_2level_tapbuf_size4_10_inbus; -assign mux_2level_tapbuf_size4_10_inbus[0] = chanx_1__1__midout_0_; -assign mux_2level_tapbuf_size4_10_inbus[1] = chanx_1__1__midout_1_; -assign mux_2level_tapbuf_size4_10_inbus[2] = chanx_1__1__midout_18_; -assign mux_2level_tapbuf_size4_10_inbus[3] = chanx_1__1__midout_19_; -wire [184:187] mux_2level_tapbuf_size4_10_configbus0; -wire [184:187] mux_2level_tapbuf_size4_10_configbus1; -wire [184:187] mux_2level_tapbuf_size4_10_sram_blwl_out ; -wire [184:187] mux_2level_tapbuf_size4_10_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_10_configbus0[184:187] = sram_blwl_bl[184:187] ; -assign mux_2level_tapbuf_size4_10_configbus1[184:187] = sram_blwl_wl[184:187] ; -wire [184:187] mux_2level_tapbuf_size4_10_configbus0_b; -assign mux_2level_tapbuf_size4_10_configbus0_b[184:187] = sram_blwl_blb[184:187] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_10_ (mux_2level_tapbuf_size4_10_inbus, grid_1__2__pin_0__2__2_, mux_2level_tapbuf_size4_10_sram_blwl_out[184:187] , -mux_2level_tapbuf_size4_10_sram_blwl_outb[184:187] ); -//----- SRAM bits for MUX[10], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_184_ (mux_2level_tapbuf_size4_10_sram_blwl_out[184:184] ,mux_2level_tapbuf_size4_10_sram_blwl_out[184:184] ,mux_2level_tapbuf_size4_10_sram_blwl_outb[184:184] ,mux_2level_tapbuf_size4_10_configbus0[184:184], mux_2level_tapbuf_size4_10_configbus1[184:184] , mux_2level_tapbuf_size4_10_configbus0_b[184:184] ); -sram6T_blwl sram_blwl_185_ (mux_2level_tapbuf_size4_10_sram_blwl_out[185:185] ,mux_2level_tapbuf_size4_10_sram_blwl_out[185:185] ,mux_2level_tapbuf_size4_10_sram_blwl_outb[185:185] ,mux_2level_tapbuf_size4_10_configbus0[185:185], mux_2level_tapbuf_size4_10_configbus1[185:185] , mux_2level_tapbuf_size4_10_configbus0_b[185:185] ); -sram6T_blwl sram_blwl_186_ (mux_2level_tapbuf_size4_10_sram_blwl_out[186:186] ,mux_2level_tapbuf_size4_10_sram_blwl_out[186:186] ,mux_2level_tapbuf_size4_10_sram_blwl_outb[186:186] ,mux_2level_tapbuf_size4_10_configbus0[186:186], mux_2level_tapbuf_size4_10_configbus1[186:186] , mux_2level_tapbuf_size4_10_configbus0_b[186:186] ); -sram6T_blwl sram_blwl_187_ (mux_2level_tapbuf_size4_10_sram_blwl_out[187:187] ,mux_2level_tapbuf_size4_10_sram_blwl_out[187:187] ,mux_2level_tapbuf_size4_10_sram_blwl_outb[187:187] ,mux_2level_tapbuf_size4_10_configbus0[187:187], mux_2level_tapbuf_size4_10_configbus1[187:187] , mux_2level_tapbuf_size4_10_configbus0_b[187:187] ); -wire [0:3] mux_2level_tapbuf_size4_11_inbus; -assign mux_2level_tapbuf_size4_11_inbus[0] = chanx_1__1__midout_2_; -assign mux_2level_tapbuf_size4_11_inbus[1] = chanx_1__1__midout_3_; -assign mux_2level_tapbuf_size4_11_inbus[2] = chanx_1__1__midout_16_; -assign mux_2level_tapbuf_size4_11_inbus[3] = chanx_1__1__midout_17_; -wire [188:191] mux_2level_tapbuf_size4_11_configbus0; -wire [188:191] mux_2level_tapbuf_size4_11_configbus1; -wire [188:191] mux_2level_tapbuf_size4_11_sram_blwl_out ; -wire [188:191] mux_2level_tapbuf_size4_11_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_11_configbus0[188:191] = sram_blwl_bl[188:191] ; -assign mux_2level_tapbuf_size4_11_configbus1[188:191] = sram_blwl_wl[188:191] ; -wire [188:191] mux_2level_tapbuf_size4_11_configbus0_b; -assign mux_2level_tapbuf_size4_11_configbus0_b[188:191] = sram_blwl_blb[188:191] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_11_ (mux_2level_tapbuf_size4_11_inbus, grid_1__2__pin_0__2__4_, mux_2level_tapbuf_size4_11_sram_blwl_out[188:191] , -mux_2level_tapbuf_size4_11_sram_blwl_outb[188:191] ); -//----- SRAM bits for MUX[11], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_188_ (mux_2level_tapbuf_size4_11_sram_blwl_out[188:188] ,mux_2level_tapbuf_size4_11_sram_blwl_out[188:188] ,mux_2level_tapbuf_size4_11_sram_blwl_outb[188:188] ,mux_2level_tapbuf_size4_11_configbus0[188:188], mux_2level_tapbuf_size4_11_configbus1[188:188] , mux_2level_tapbuf_size4_11_configbus0_b[188:188] ); -sram6T_blwl sram_blwl_189_ (mux_2level_tapbuf_size4_11_sram_blwl_out[189:189] ,mux_2level_tapbuf_size4_11_sram_blwl_out[189:189] ,mux_2level_tapbuf_size4_11_sram_blwl_outb[189:189] ,mux_2level_tapbuf_size4_11_configbus0[189:189], mux_2level_tapbuf_size4_11_configbus1[189:189] , mux_2level_tapbuf_size4_11_configbus0_b[189:189] ); -sram6T_blwl sram_blwl_190_ (mux_2level_tapbuf_size4_11_sram_blwl_out[190:190] ,mux_2level_tapbuf_size4_11_sram_blwl_out[190:190] ,mux_2level_tapbuf_size4_11_sram_blwl_outb[190:190] ,mux_2level_tapbuf_size4_11_configbus0[190:190], mux_2level_tapbuf_size4_11_configbus1[190:190] , mux_2level_tapbuf_size4_11_configbus0_b[190:190] ); -sram6T_blwl sram_blwl_191_ (mux_2level_tapbuf_size4_11_sram_blwl_out[191:191] ,mux_2level_tapbuf_size4_11_sram_blwl_out[191:191] ,mux_2level_tapbuf_size4_11_sram_blwl_outb[191:191] ,mux_2level_tapbuf_size4_11_configbus0[191:191], mux_2level_tapbuf_size4_11_configbus1[191:191] , mux_2level_tapbuf_size4_11_configbus0_b[191:191] ); -wire [0:3] mux_2level_tapbuf_size4_12_inbus; -assign mux_2level_tapbuf_size4_12_inbus[0] = chanx_1__1__midout_4_; -assign mux_2level_tapbuf_size4_12_inbus[1] = chanx_1__1__midout_5_; -assign mux_2level_tapbuf_size4_12_inbus[2] = chanx_1__1__midout_20_; -assign mux_2level_tapbuf_size4_12_inbus[3] = chanx_1__1__midout_21_; -wire [192:195] mux_2level_tapbuf_size4_12_configbus0; -wire [192:195] mux_2level_tapbuf_size4_12_configbus1; -wire [192:195] mux_2level_tapbuf_size4_12_sram_blwl_out ; -wire [192:195] mux_2level_tapbuf_size4_12_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_12_configbus0[192:195] = sram_blwl_bl[192:195] ; -assign mux_2level_tapbuf_size4_12_configbus1[192:195] = sram_blwl_wl[192:195] ; -wire [192:195] mux_2level_tapbuf_size4_12_configbus0_b; -assign mux_2level_tapbuf_size4_12_configbus0_b[192:195] = sram_blwl_blb[192:195] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_12_ (mux_2level_tapbuf_size4_12_inbus, grid_1__2__pin_0__2__6_, mux_2level_tapbuf_size4_12_sram_blwl_out[192:195] , -mux_2level_tapbuf_size4_12_sram_blwl_outb[192:195] ); -//----- SRAM bits for MUX[12], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_192_ (mux_2level_tapbuf_size4_12_sram_blwl_out[192:192] ,mux_2level_tapbuf_size4_12_sram_blwl_out[192:192] ,mux_2level_tapbuf_size4_12_sram_blwl_outb[192:192] ,mux_2level_tapbuf_size4_12_configbus0[192:192], mux_2level_tapbuf_size4_12_configbus1[192:192] , mux_2level_tapbuf_size4_12_configbus0_b[192:192] ); -sram6T_blwl sram_blwl_193_ (mux_2level_tapbuf_size4_12_sram_blwl_out[193:193] ,mux_2level_tapbuf_size4_12_sram_blwl_out[193:193] ,mux_2level_tapbuf_size4_12_sram_blwl_outb[193:193] ,mux_2level_tapbuf_size4_12_configbus0[193:193], mux_2level_tapbuf_size4_12_configbus1[193:193] , mux_2level_tapbuf_size4_12_configbus0_b[193:193] ); -sram6T_blwl sram_blwl_194_ (mux_2level_tapbuf_size4_12_sram_blwl_out[194:194] ,mux_2level_tapbuf_size4_12_sram_blwl_out[194:194] ,mux_2level_tapbuf_size4_12_sram_blwl_outb[194:194] ,mux_2level_tapbuf_size4_12_configbus0[194:194], mux_2level_tapbuf_size4_12_configbus1[194:194] , mux_2level_tapbuf_size4_12_configbus0_b[194:194] ); -sram6T_blwl sram_blwl_195_ (mux_2level_tapbuf_size4_12_sram_blwl_out[195:195] ,mux_2level_tapbuf_size4_12_sram_blwl_out[195:195] ,mux_2level_tapbuf_size4_12_sram_blwl_outb[195:195] ,mux_2level_tapbuf_size4_12_configbus0[195:195], mux_2level_tapbuf_size4_12_configbus1[195:195] , mux_2level_tapbuf_size4_12_configbus0_b[195:195] ); -wire [0:3] mux_2level_tapbuf_size4_13_inbus; -assign mux_2level_tapbuf_size4_13_inbus[0] = chanx_1__1__midout_10_; -assign mux_2level_tapbuf_size4_13_inbus[1] = chanx_1__1__midout_11_; -assign mux_2level_tapbuf_size4_13_inbus[2] = chanx_1__1__midout_22_; -assign mux_2level_tapbuf_size4_13_inbus[3] = chanx_1__1__midout_23_; -wire [196:199] mux_2level_tapbuf_size4_13_configbus0; -wire [196:199] mux_2level_tapbuf_size4_13_configbus1; -wire [196:199] mux_2level_tapbuf_size4_13_sram_blwl_out ; -wire [196:199] mux_2level_tapbuf_size4_13_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_13_configbus0[196:199] = sram_blwl_bl[196:199] ; -assign mux_2level_tapbuf_size4_13_configbus1[196:199] = sram_blwl_wl[196:199] ; -wire [196:199] mux_2level_tapbuf_size4_13_configbus0_b; -assign mux_2level_tapbuf_size4_13_configbus0_b[196:199] = sram_blwl_blb[196:199] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_13_ (mux_2level_tapbuf_size4_13_inbus, grid_1__2__pin_0__2__8_, mux_2level_tapbuf_size4_13_sram_blwl_out[196:199] , -mux_2level_tapbuf_size4_13_sram_blwl_outb[196:199] ); -//----- SRAM bits for MUX[13], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_196_ (mux_2level_tapbuf_size4_13_sram_blwl_out[196:196] ,mux_2level_tapbuf_size4_13_sram_blwl_out[196:196] ,mux_2level_tapbuf_size4_13_sram_blwl_outb[196:196] ,mux_2level_tapbuf_size4_13_configbus0[196:196], mux_2level_tapbuf_size4_13_configbus1[196:196] , mux_2level_tapbuf_size4_13_configbus0_b[196:196] ); -sram6T_blwl sram_blwl_197_ (mux_2level_tapbuf_size4_13_sram_blwl_out[197:197] ,mux_2level_tapbuf_size4_13_sram_blwl_out[197:197] ,mux_2level_tapbuf_size4_13_sram_blwl_outb[197:197] ,mux_2level_tapbuf_size4_13_configbus0[197:197], mux_2level_tapbuf_size4_13_configbus1[197:197] , mux_2level_tapbuf_size4_13_configbus0_b[197:197] ); -sram6T_blwl sram_blwl_198_ (mux_2level_tapbuf_size4_13_sram_blwl_out[198:198] ,mux_2level_tapbuf_size4_13_sram_blwl_out[198:198] ,mux_2level_tapbuf_size4_13_sram_blwl_outb[198:198] ,mux_2level_tapbuf_size4_13_configbus0[198:198], mux_2level_tapbuf_size4_13_configbus1[198:198] , mux_2level_tapbuf_size4_13_configbus0_b[198:198] ); -sram6T_blwl sram_blwl_199_ (mux_2level_tapbuf_size4_13_sram_blwl_out[199:199] ,mux_2level_tapbuf_size4_13_sram_blwl_out[199:199] ,mux_2level_tapbuf_size4_13_sram_blwl_outb[199:199] ,mux_2level_tapbuf_size4_13_configbus0[199:199], mux_2level_tapbuf_size4_13_configbus1[199:199] , mux_2level_tapbuf_size4_13_configbus0_b[199:199] ); -wire [0:3] mux_2level_tapbuf_size4_14_inbus; -assign mux_2level_tapbuf_size4_14_inbus[0] = chanx_1__1__midout_8_; -assign mux_2level_tapbuf_size4_14_inbus[1] = chanx_1__1__midout_9_; -assign mux_2level_tapbuf_size4_14_inbus[2] = chanx_1__1__midout_24_; -assign mux_2level_tapbuf_size4_14_inbus[3] = chanx_1__1__midout_25_; -wire [200:203] mux_2level_tapbuf_size4_14_configbus0; -wire [200:203] mux_2level_tapbuf_size4_14_configbus1; -wire [200:203] mux_2level_tapbuf_size4_14_sram_blwl_out ; -wire [200:203] mux_2level_tapbuf_size4_14_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_14_configbus0[200:203] = sram_blwl_bl[200:203] ; -assign mux_2level_tapbuf_size4_14_configbus1[200:203] = sram_blwl_wl[200:203] ; -wire [200:203] mux_2level_tapbuf_size4_14_configbus0_b; -assign mux_2level_tapbuf_size4_14_configbus0_b[200:203] = sram_blwl_blb[200:203] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_14_ (mux_2level_tapbuf_size4_14_inbus, grid_1__2__pin_0__2__10_, mux_2level_tapbuf_size4_14_sram_blwl_out[200:203] , -mux_2level_tapbuf_size4_14_sram_blwl_outb[200:203] ); -//----- SRAM bits for MUX[14], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_200_ (mux_2level_tapbuf_size4_14_sram_blwl_out[200:200] ,mux_2level_tapbuf_size4_14_sram_blwl_out[200:200] ,mux_2level_tapbuf_size4_14_sram_blwl_outb[200:200] ,mux_2level_tapbuf_size4_14_configbus0[200:200], mux_2level_tapbuf_size4_14_configbus1[200:200] , mux_2level_tapbuf_size4_14_configbus0_b[200:200] ); -sram6T_blwl sram_blwl_201_ (mux_2level_tapbuf_size4_14_sram_blwl_out[201:201] ,mux_2level_tapbuf_size4_14_sram_blwl_out[201:201] ,mux_2level_tapbuf_size4_14_sram_blwl_outb[201:201] ,mux_2level_tapbuf_size4_14_configbus0[201:201], mux_2level_tapbuf_size4_14_configbus1[201:201] , mux_2level_tapbuf_size4_14_configbus0_b[201:201] ); -sram6T_blwl sram_blwl_202_ (mux_2level_tapbuf_size4_14_sram_blwl_out[202:202] ,mux_2level_tapbuf_size4_14_sram_blwl_out[202:202] ,mux_2level_tapbuf_size4_14_sram_blwl_outb[202:202] ,mux_2level_tapbuf_size4_14_configbus0[202:202], mux_2level_tapbuf_size4_14_configbus1[202:202] , mux_2level_tapbuf_size4_14_configbus0_b[202:202] ); -sram6T_blwl sram_blwl_203_ (mux_2level_tapbuf_size4_14_sram_blwl_out[203:203] ,mux_2level_tapbuf_size4_14_sram_blwl_out[203:203] ,mux_2level_tapbuf_size4_14_sram_blwl_outb[203:203] ,mux_2level_tapbuf_size4_14_configbus0[203:203], mux_2level_tapbuf_size4_14_configbus1[203:203] , mux_2level_tapbuf_size4_14_configbus0_b[203:203] ); -wire [0:3] mux_2level_tapbuf_size4_15_inbus; -assign mux_2level_tapbuf_size4_15_inbus[0] = chanx_1__1__midout_14_; -assign mux_2level_tapbuf_size4_15_inbus[1] = chanx_1__1__midout_15_; -assign mux_2level_tapbuf_size4_15_inbus[2] = chanx_1__1__midout_26_; -assign mux_2level_tapbuf_size4_15_inbus[3] = chanx_1__1__midout_27_; -wire [204:207] mux_2level_tapbuf_size4_15_configbus0; -wire [204:207] mux_2level_tapbuf_size4_15_configbus1; -wire [204:207] mux_2level_tapbuf_size4_15_sram_blwl_out ; -wire [204:207] mux_2level_tapbuf_size4_15_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_15_configbus0[204:207] = sram_blwl_bl[204:207] ; -assign mux_2level_tapbuf_size4_15_configbus1[204:207] = sram_blwl_wl[204:207] ; -wire [204:207] mux_2level_tapbuf_size4_15_configbus0_b; -assign mux_2level_tapbuf_size4_15_configbus0_b[204:207] = sram_blwl_blb[204:207] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_15_ (mux_2level_tapbuf_size4_15_inbus, grid_1__2__pin_0__2__12_, mux_2level_tapbuf_size4_15_sram_blwl_out[204:207] , -mux_2level_tapbuf_size4_15_sram_blwl_outb[204:207] ); -//----- SRAM bits for MUX[15], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_204_ (mux_2level_tapbuf_size4_15_sram_blwl_out[204:204] ,mux_2level_tapbuf_size4_15_sram_blwl_out[204:204] ,mux_2level_tapbuf_size4_15_sram_blwl_outb[204:204] ,mux_2level_tapbuf_size4_15_configbus0[204:204], mux_2level_tapbuf_size4_15_configbus1[204:204] , mux_2level_tapbuf_size4_15_configbus0_b[204:204] ); -sram6T_blwl sram_blwl_205_ (mux_2level_tapbuf_size4_15_sram_blwl_out[205:205] ,mux_2level_tapbuf_size4_15_sram_blwl_out[205:205] ,mux_2level_tapbuf_size4_15_sram_blwl_outb[205:205] ,mux_2level_tapbuf_size4_15_configbus0[205:205], mux_2level_tapbuf_size4_15_configbus1[205:205] , mux_2level_tapbuf_size4_15_configbus0_b[205:205] ); -sram6T_blwl sram_blwl_206_ (mux_2level_tapbuf_size4_15_sram_blwl_out[206:206] ,mux_2level_tapbuf_size4_15_sram_blwl_out[206:206] ,mux_2level_tapbuf_size4_15_sram_blwl_outb[206:206] ,mux_2level_tapbuf_size4_15_configbus0[206:206], mux_2level_tapbuf_size4_15_configbus1[206:206] , mux_2level_tapbuf_size4_15_configbus0_b[206:206] ); -sram6T_blwl sram_blwl_207_ (mux_2level_tapbuf_size4_15_sram_blwl_out[207:207] ,mux_2level_tapbuf_size4_15_sram_blwl_out[207:207] ,mux_2level_tapbuf_size4_15_sram_blwl_outb[207:207] ,mux_2level_tapbuf_size4_15_configbus0[207:207], mux_2level_tapbuf_size4_15_configbus1[207:207] , mux_2level_tapbuf_size4_15_configbus0_b[207:207] ); -wire [0:3] mux_2level_tapbuf_size4_16_inbus; -assign mux_2level_tapbuf_size4_16_inbus[0] = chanx_1__1__midout_12_; -assign mux_2level_tapbuf_size4_16_inbus[1] = chanx_1__1__midout_13_; -assign mux_2level_tapbuf_size4_16_inbus[2] = chanx_1__1__midout_28_; -assign mux_2level_tapbuf_size4_16_inbus[3] = chanx_1__1__midout_29_; -wire [208:211] mux_2level_tapbuf_size4_16_configbus0; -wire [208:211] mux_2level_tapbuf_size4_16_configbus1; -wire [208:211] mux_2level_tapbuf_size4_16_sram_blwl_out ; -wire [208:211] mux_2level_tapbuf_size4_16_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_16_configbus0[208:211] = sram_blwl_bl[208:211] ; -assign mux_2level_tapbuf_size4_16_configbus1[208:211] = sram_blwl_wl[208:211] ; -wire [208:211] mux_2level_tapbuf_size4_16_configbus0_b; -assign mux_2level_tapbuf_size4_16_configbus0_b[208:211] = sram_blwl_blb[208:211] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_16_ (mux_2level_tapbuf_size4_16_inbus, grid_1__2__pin_0__2__14_, mux_2level_tapbuf_size4_16_sram_blwl_out[208:211] , -mux_2level_tapbuf_size4_16_sram_blwl_outb[208:211] ); -//----- SRAM bits for MUX[16], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_208_ (mux_2level_tapbuf_size4_16_sram_blwl_out[208:208] ,mux_2level_tapbuf_size4_16_sram_blwl_out[208:208] ,mux_2level_tapbuf_size4_16_sram_blwl_outb[208:208] ,mux_2level_tapbuf_size4_16_configbus0[208:208], mux_2level_tapbuf_size4_16_configbus1[208:208] , mux_2level_tapbuf_size4_16_configbus0_b[208:208] ); -sram6T_blwl sram_blwl_209_ (mux_2level_tapbuf_size4_16_sram_blwl_out[209:209] ,mux_2level_tapbuf_size4_16_sram_blwl_out[209:209] ,mux_2level_tapbuf_size4_16_sram_blwl_outb[209:209] ,mux_2level_tapbuf_size4_16_configbus0[209:209], mux_2level_tapbuf_size4_16_configbus1[209:209] , mux_2level_tapbuf_size4_16_configbus0_b[209:209] ); -sram6T_blwl sram_blwl_210_ (mux_2level_tapbuf_size4_16_sram_blwl_out[210:210] ,mux_2level_tapbuf_size4_16_sram_blwl_out[210:210] ,mux_2level_tapbuf_size4_16_sram_blwl_outb[210:210] ,mux_2level_tapbuf_size4_16_configbus0[210:210], mux_2level_tapbuf_size4_16_configbus1[210:210] , mux_2level_tapbuf_size4_16_configbus0_b[210:210] ); -sram6T_blwl sram_blwl_211_ (mux_2level_tapbuf_size4_16_sram_blwl_out[211:211] ,mux_2level_tapbuf_size4_16_sram_blwl_out[211:211] ,mux_2level_tapbuf_size4_16_sram_blwl_outb[211:211] ,mux_2level_tapbuf_size4_16_configbus0[211:211], mux_2level_tapbuf_size4_16_configbus1[211:211] , mux_2level_tapbuf_size4_16_configbus0_b[211:211] ); -wire [0:3] mux_2level_tapbuf_size4_17_inbus; -assign mux_2level_tapbuf_size4_17_inbus[0] = chanx_1__1__midout_6_; -assign mux_2level_tapbuf_size4_17_inbus[1] = chanx_1__1__midout_7_; -assign mux_2level_tapbuf_size4_17_inbus[2] = chanx_1__1__midout_12_; -assign mux_2level_tapbuf_size4_17_inbus[3] = chanx_1__1__midout_13_; -wire [212:215] mux_2level_tapbuf_size4_17_configbus0; -wire [212:215] mux_2level_tapbuf_size4_17_configbus1; -wire [212:215] mux_2level_tapbuf_size4_17_sram_blwl_out ; -wire [212:215] mux_2level_tapbuf_size4_17_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_17_configbus0[212:215] = sram_blwl_bl[212:215] ; -assign mux_2level_tapbuf_size4_17_configbus1[212:215] = sram_blwl_wl[212:215] ; -wire [212:215] mux_2level_tapbuf_size4_17_configbus0_b; -assign mux_2level_tapbuf_size4_17_configbus0_b[212:215] = sram_blwl_blb[212:215] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_17_ (mux_2level_tapbuf_size4_17_inbus, grid_1__1__pin_0__0__0_, mux_2level_tapbuf_size4_17_sram_blwl_out[212:215] , -mux_2level_tapbuf_size4_17_sram_blwl_outb[212:215] ); -//----- SRAM bits for MUX[17], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_212_ (mux_2level_tapbuf_size4_17_sram_blwl_out[212:212] ,mux_2level_tapbuf_size4_17_sram_blwl_out[212:212] ,mux_2level_tapbuf_size4_17_sram_blwl_outb[212:212] ,mux_2level_tapbuf_size4_17_configbus0[212:212], mux_2level_tapbuf_size4_17_configbus1[212:212] , mux_2level_tapbuf_size4_17_configbus0_b[212:212] ); -sram6T_blwl sram_blwl_213_ (mux_2level_tapbuf_size4_17_sram_blwl_out[213:213] ,mux_2level_tapbuf_size4_17_sram_blwl_out[213:213] ,mux_2level_tapbuf_size4_17_sram_blwl_outb[213:213] ,mux_2level_tapbuf_size4_17_configbus0[213:213], mux_2level_tapbuf_size4_17_configbus1[213:213] , mux_2level_tapbuf_size4_17_configbus0_b[213:213] ); -sram6T_blwl sram_blwl_214_ (mux_2level_tapbuf_size4_17_sram_blwl_out[214:214] ,mux_2level_tapbuf_size4_17_sram_blwl_out[214:214] ,mux_2level_tapbuf_size4_17_sram_blwl_outb[214:214] ,mux_2level_tapbuf_size4_17_configbus0[214:214], mux_2level_tapbuf_size4_17_configbus1[214:214] , mux_2level_tapbuf_size4_17_configbus0_b[214:214] ); -sram6T_blwl sram_blwl_215_ (mux_2level_tapbuf_size4_17_sram_blwl_out[215:215] ,mux_2level_tapbuf_size4_17_sram_blwl_out[215:215] ,mux_2level_tapbuf_size4_17_sram_blwl_outb[215:215] ,mux_2level_tapbuf_size4_17_configbus0[215:215], mux_2level_tapbuf_size4_17_configbus1[215:215] , mux_2level_tapbuf_size4_17_configbus0_b[215:215] ); -endmodule -//----- END Verilog Module of Connection Box -X direction [1][1] ----- - diff --git a/examples/verilog_test_example_1/routing/cby_0_1.v b/examples/verilog_test_example_1/routing/cby_0_1.v deleted file mode 100644 index f4a56689a..000000000 --- a/examples/verilog_test_example_1/routing/cby_0_1.v +++ /dev/null @@ -1,302 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Connection Block - Y direction [0][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Connection Box -Y direction [0][1] ----- -module cby_0__1_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input chany_0__1__midout_0_, - -input chany_0__1__midout_1_, - -input chany_0__1__midout_2_, - -input chany_0__1__midout_3_, - -input chany_0__1__midout_4_, - -input chany_0__1__midout_5_, - -input chany_0__1__midout_6_, - -input chany_0__1__midout_7_, - -input chany_0__1__midout_8_, - -input chany_0__1__midout_9_, - -input chany_0__1__midout_10_, - -input chany_0__1__midout_11_, - -input chany_0__1__midout_12_, - -input chany_0__1__midout_13_, - -input chany_0__1__midout_14_, - -input chany_0__1__midout_15_, - -input chany_0__1__midout_16_, - -input chany_0__1__midout_17_, - -input chany_0__1__midout_18_, - -input chany_0__1__midout_19_, - -input chany_0__1__midout_20_, - -input chany_0__1__midout_21_, - -input chany_0__1__midout_22_, - -input chany_0__1__midout_23_, - -input chany_0__1__midout_24_, - -input chany_0__1__midout_25_, - -input chany_0__1__midout_26_, - -input chany_0__1__midout_27_, - -input chany_0__1__midout_28_, - -input chany_0__1__midout_29_, - -output grid_1__1__pin_0__3__3_, - -output grid_0__1__pin_0__1__0_, - -output grid_0__1__pin_0__1__2_, - -output grid_0__1__pin_0__1__4_, - -output grid_0__1__pin_0__1__6_, - -output grid_0__1__pin_0__1__8_, - -output grid_0__1__pin_0__1__10_, - -output grid_0__1__pin_0__1__12_, - -output grid_0__1__pin_0__1__14_, - -input [216:251] sram_blwl_bl , -input [216:251] sram_blwl_wl , -input [216:251] sram_blwl_blb ); -wire [0:3] mux_2level_tapbuf_size4_18_inbus; -assign mux_2level_tapbuf_size4_18_inbus[0] = chany_0__1__midout_10_; -assign mux_2level_tapbuf_size4_18_inbus[1] = chany_0__1__midout_11_; -assign mux_2level_tapbuf_size4_18_inbus[2] = chany_0__1__midout_26_; -assign mux_2level_tapbuf_size4_18_inbus[3] = chany_0__1__midout_27_; -wire [216:219] mux_2level_tapbuf_size4_18_configbus0; -wire [216:219] mux_2level_tapbuf_size4_18_configbus1; -wire [216:219] mux_2level_tapbuf_size4_18_sram_blwl_out ; -wire [216:219] mux_2level_tapbuf_size4_18_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_18_configbus0[216:219] = sram_blwl_bl[216:219] ; -assign mux_2level_tapbuf_size4_18_configbus1[216:219] = sram_blwl_wl[216:219] ; -wire [216:219] mux_2level_tapbuf_size4_18_configbus0_b; -assign mux_2level_tapbuf_size4_18_configbus0_b[216:219] = sram_blwl_blb[216:219] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_18_ (mux_2level_tapbuf_size4_18_inbus, grid_1__1__pin_0__3__3_, mux_2level_tapbuf_size4_18_sram_blwl_out[216:219] , -mux_2level_tapbuf_size4_18_sram_blwl_outb[216:219] ); -//----- SRAM bits for MUX[18], level=2, select_path_id=3. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----0101----- -sram6T_blwl sram_blwl_216_ (mux_2level_tapbuf_size4_18_sram_blwl_out[216:216] ,mux_2level_tapbuf_size4_18_sram_blwl_out[216:216] ,mux_2level_tapbuf_size4_18_sram_blwl_outb[216:216] ,mux_2level_tapbuf_size4_18_configbus0[216:216], mux_2level_tapbuf_size4_18_configbus1[216:216] , mux_2level_tapbuf_size4_18_configbus0_b[216:216] ); -sram6T_blwl sram_blwl_217_ (mux_2level_tapbuf_size4_18_sram_blwl_out[217:217] ,mux_2level_tapbuf_size4_18_sram_blwl_out[217:217] ,mux_2level_tapbuf_size4_18_sram_blwl_outb[217:217] ,mux_2level_tapbuf_size4_18_configbus0[217:217], mux_2level_tapbuf_size4_18_configbus1[217:217] , mux_2level_tapbuf_size4_18_configbus0_b[217:217] ); -sram6T_blwl sram_blwl_218_ (mux_2level_tapbuf_size4_18_sram_blwl_out[218:218] ,mux_2level_tapbuf_size4_18_sram_blwl_out[218:218] ,mux_2level_tapbuf_size4_18_sram_blwl_outb[218:218] ,mux_2level_tapbuf_size4_18_configbus0[218:218], mux_2level_tapbuf_size4_18_configbus1[218:218] , mux_2level_tapbuf_size4_18_configbus0_b[218:218] ); -sram6T_blwl sram_blwl_219_ (mux_2level_tapbuf_size4_18_sram_blwl_out[219:219] ,mux_2level_tapbuf_size4_18_sram_blwl_out[219:219] ,mux_2level_tapbuf_size4_18_sram_blwl_outb[219:219] ,mux_2level_tapbuf_size4_18_configbus0[219:219], mux_2level_tapbuf_size4_18_configbus1[219:219] , mux_2level_tapbuf_size4_18_configbus0_b[219:219] ); -wire [0:3] mux_2level_tapbuf_size4_19_inbus; -assign mux_2level_tapbuf_size4_19_inbus[0] = chany_0__1__midout_0_; -assign mux_2level_tapbuf_size4_19_inbus[1] = chany_0__1__midout_1_; -assign mux_2level_tapbuf_size4_19_inbus[2] = chany_0__1__midout_14_; -assign mux_2level_tapbuf_size4_19_inbus[3] = chany_0__1__midout_15_; -wire [220:223] mux_2level_tapbuf_size4_19_configbus0; -wire [220:223] mux_2level_tapbuf_size4_19_configbus1; -wire [220:223] mux_2level_tapbuf_size4_19_sram_blwl_out ; -wire [220:223] mux_2level_tapbuf_size4_19_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_19_configbus0[220:223] = sram_blwl_bl[220:223] ; -assign mux_2level_tapbuf_size4_19_configbus1[220:223] = sram_blwl_wl[220:223] ; -wire [220:223] mux_2level_tapbuf_size4_19_configbus0_b; -assign mux_2level_tapbuf_size4_19_configbus0_b[220:223] = sram_blwl_blb[220:223] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_19_ (mux_2level_tapbuf_size4_19_inbus, grid_0__1__pin_0__1__0_, mux_2level_tapbuf_size4_19_sram_blwl_out[220:223] , -mux_2level_tapbuf_size4_19_sram_blwl_outb[220:223] ); -//----- SRAM bits for MUX[19], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_220_ (mux_2level_tapbuf_size4_19_sram_blwl_out[220:220] ,mux_2level_tapbuf_size4_19_sram_blwl_out[220:220] ,mux_2level_tapbuf_size4_19_sram_blwl_outb[220:220] ,mux_2level_tapbuf_size4_19_configbus0[220:220], mux_2level_tapbuf_size4_19_configbus1[220:220] , mux_2level_tapbuf_size4_19_configbus0_b[220:220] ); -sram6T_blwl sram_blwl_221_ (mux_2level_tapbuf_size4_19_sram_blwl_out[221:221] ,mux_2level_tapbuf_size4_19_sram_blwl_out[221:221] ,mux_2level_tapbuf_size4_19_sram_blwl_outb[221:221] ,mux_2level_tapbuf_size4_19_configbus0[221:221], mux_2level_tapbuf_size4_19_configbus1[221:221] , mux_2level_tapbuf_size4_19_configbus0_b[221:221] ); -sram6T_blwl sram_blwl_222_ (mux_2level_tapbuf_size4_19_sram_blwl_out[222:222] ,mux_2level_tapbuf_size4_19_sram_blwl_out[222:222] ,mux_2level_tapbuf_size4_19_sram_blwl_outb[222:222] ,mux_2level_tapbuf_size4_19_configbus0[222:222], mux_2level_tapbuf_size4_19_configbus1[222:222] , mux_2level_tapbuf_size4_19_configbus0_b[222:222] ); -sram6T_blwl sram_blwl_223_ (mux_2level_tapbuf_size4_19_sram_blwl_out[223:223] ,mux_2level_tapbuf_size4_19_sram_blwl_out[223:223] ,mux_2level_tapbuf_size4_19_sram_blwl_outb[223:223] ,mux_2level_tapbuf_size4_19_configbus0[223:223], mux_2level_tapbuf_size4_19_configbus1[223:223] , mux_2level_tapbuf_size4_19_configbus0_b[223:223] ); -wire [0:3] mux_2level_tapbuf_size4_20_inbus; -assign mux_2level_tapbuf_size4_20_inbus[0] = chany_0__1__midout_2_; -assign mux_2level_tapbuf_size4_20_inbus[1] = chany_0__1__midout_3_; -assign mux_2level_tapbuf_size4_20_inbus[2] = chany_0__1__midout_16_; -assign mux_2level_tapbuf_size4_20_inbus[3] = chany_0__1__midout_17_; -wire [224:227] mux_2level_tapbuf_size4_20_configbus0; -wire [224:227] mux_2level_tapbuf_size4_20_configbus1; -wire [224:227] mux_2level_tapbuf_size4_20_sram_blwl_out ; -wire [224:227] mux_2level_tapbuf_size4_20_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_20_configbus0[224:227] = sram_blwl_bl[224:227] ; -assign mux_2level_tapbuf_size4_20_configbus1[224:227] = sram_blwl_wl[224:227] ; -wire [224:227] mux_2level_tapbuf_size4_20_configbus0_b; -assign mux_2level_tapbuf_size4_20_configbus0_b[224:227] = sram_blwl_blb[224:227] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_20_ (mux_2level_tapbuf_size4_20_inbus, grid_0__1__pin_0__1__2_, mux_2level_tapbuf_size4_20_sram_blwl_out[224:227] , -mux_2level_tapbuf_size4_20_sram_blwl_outb[224:227] ); -//----- SRAM bits for MUX[20], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_224_ (mux_2level_tapbuf_size4_20_sram_blwl_out[224:224] ,mux_2level_tapbuf_size4_20_sram_blwl_out[224:224] ,mux_2level_tapbuf_size4_20_sram_blwl_outb[224:224] ,mux_2level_tapbuf_size4_20_configbus0[224:224], mux_2level_tapbuf_size4_20_configbus1[224:224] , mux_2level_tapbuf_size4_20_configbus0_b[224:224] ); -sram6T_blwl sram_blwl_225_ (mux_2level_tapbuf_size4_20_sram_blwl_out[225:225] ,mux_2level_tapbuf_size4_20_sram_blwl_out[225:225] ,mux_2level_tapbuf_size4_20_sram_blwl_outb[225:225] ,mux_2level_tapbuf_size4_20_configbus0[225:225], mux_2level_tapbuf_size4_20_configbus1[225:225] , mux_2level_tapbuf_size4_20_configbus0_b[225:225] ); -sram6T_blwl sram_blwl_226_ (mux_2level_tapbuf_size4_20_sram_blwl_out[226:226] ,mux_2level_tapbuf_size4_20_sram_blwl_out[226:226] ,mux_2level_tapbuf_size4_20_sram_blwl_outb[226:226] ,mux_2level_tapbuf_size4_20_configbus0[226:226], mux_2level_tapbuf_size4_20_configbus1[226:226] , mux_2level_tapbuf_size4_20_configbus0_b[226:226] ); -sram6T_blwl sram_blwl_227_ (mux_2level_tapbuf_size4_20_sram_blwl_out[227:227] ,mux_2level_tapbuf_size4_20_sram_blwl_out[227:227] ,mux_2level_tapbuf_size4_20_sram_blwl_outb[227:227] ,mux_2level_tapbuf_size4_20_configbus0[227:227], mux_2level_tapbuf_size4_20_configbus1[227:227] , mux_2level_tapbuf_size4_20_configbus0_b[227:227] ); -wire [0:3] mux_2level_tapbuf_size4_21_inbus; -assign mux_2level_tapbuf_size4_21_inbus[0] = chany_0__1__midout_4_; -assign mux_2level_tapbuf_size4_21_inbus[1] = chany_0__1__midout_5_; -assign mux_2level_tapbuf_size4_21_inbus[2] = chany_0__1__midout_18_; -assign mux_2level_tapbuf_size4_21_inbus[3] = chany_0__1__midout_19_; -wire [228:231] mux_2level_tapbuf_size4_21_configbus0; -wire [228:231] mux_2level_tapbuf_size4_21_configbus1; -wire [228:231] mux_2level_tapbuf_size4_21_sram_blwl_out ; -wire [228:231] mux_2level_tapbuf_size4_21_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_21_configbus0[228:231] = sram_blwl_bl[228:231] ; -assign mux_2level_tapbuf_size4_21_configbus1[228:231] = sram_blwl_wl[228:231] ; -wire [228:231] mux_2level_tapbuf_size4_21_configbus0_b; -assign mux_2level_tapbuf_size4_21_configbus0_b[228:231] = sram_blwl_blb[228:231] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_21_ (mux_2level_tapbuf_size4_21_inbus, grid_0__1__pin_0__1__4_, mux_2level_tapbuf_size4_21_sram_blwl_out[228:231] , -mux_2level_tapbuf_size4_21_sram_blwl_outb[228:231] ); -//----- SRAM bits for MUX[21], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_228_ (mux_2level_tapbuf_size4_21_sram_blwl_out[228:228] ,mux_2level_tapbuf_size4_21_sram_blwl_out[228:228] ,mux_2level_tapbuf_size4_21_sram_blwl_outb[228:228] ,mux_2level_tapbuf_size4_21_configbus0[228:228], mux_2level_tapbuf_size4_21_configbus1[228:228] , mux_2level_tapbuf_size4_21_configbus0_b[228:228] ); -sram6T_blwl sram_blwl_229_ (mux_2level_tapbuf_size4_21_sram_blwl_out[229:229] ,mux_2level_tapbuf_size4_21_sram_blwl_out[229:229] ,mux_2level_tapbuf_size4_21_sram_blwl_outb[229:229] ,mux_2level_tapbuf_size4_21_configbus0[229:229], mux_2level_tapbuf_size4_21_configbus1[229:229] , mux_2level_tapbuf_size4_21_configbus0_b[229:229] ); -sram6T_blwl sram_blwl_230_ (mux_2level_tapbuf_size4_21_sram_blwl_out[230:230] ,mux_2level_tapbuf_size4_21_sram_blwl_out[230:230] ,mux_2level_tapbuf_size4_21_sram_blwl_outb[230:230] ,mux_2level_tapbuf_size4_21_configbus0[230:230], mux_2level_tapbuf_size4_21_configbus1[230:230] , mux_2level_tapbuf_size4_21_configbus0_b[230:230] ); -sram6T_blwl sram_blwl_231_ (mux_2level_tapbuf_size4_21_sram_blwl_out[231:231] ,mux_2level_tapbuf_size4_21_sram_blwl_out[231:231] ,mux_2level_tapbuf_size4_21_sram_blwl_outb[231:231] ,mux_2level_tapbuf_size4_21_configbus0[231:231], mux_2level_tapbuf_size4_21_configbus1[231:231] , mux_2level_tapbuf_size4_21_configbus0_b[231:231] ); -wire [0:3] mux_2level_tapbuf_size4_22_inbus; -assign mux_2level_tapbuf_size4_22_inbus[0] = chany_0__1__midout_6_; -assign mux_2level_tapbuf_size4_22_inbus[1] = chany_0__1__midout_7_; -assign mux_2level_tapbuf_size4_22_inbus[2] = chany_0__1__midout_20_; -assign mux_2level_tapbuf_size4_22_inbus[3] = chany_0__1__midout_21_; -wire [232:235] mux_2level_tapbuf_size4_22_configbus0; -wire [232:235] mux_2level_tapbuf_size4_22_configbus1; -wire [232:235] mux_2level_tapbuf_size4_22_sram_blwl_out ; -wire [232:235] mux_2level_tapbuf_size4_22_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_22_configbus0[232:235] = sram_blwl_bl[232:235] ; -assign mux_2level_tapbuf_size4_22_configbus1[232:235] = sram_blwl_wl[232:235] ; -wire [232:235] mux_2level_tapbuf_size4_22_configbus0_b; -assign mux_2level_tapbuf_size4_22_configbus0_b[232:235] = sram_blwl_blb[232:235] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_22_ (mux_2level_tapbuf_size4_22_inbus, grid_0__1__pin_0__1__6_, mux_2level_tapbuf_size4_22_sram_blwl_out[232:235] , -mux_2level_tapbuf_size4_22_sram_blwl_outb[232:235] ); -//----- SRAM bits for MUX[22], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_232_ (mux_2level_tapbuf_size4_22_sram_blwl_out[232:232] ,mux_2level_tapbuf_size4_22_sram_blwl_out[232:232] ,mux_2level_tapbuf_size4_22_sram_blwl_outb[232:232] ,mux_2level_tapbuf_size4_22_configbus0[232:232], mux_2level_tapbuf_size4_22_configbus1[232:232] , mux_2level_tapbuf_size4_22_configbus0_b[232:232] ); -sram6T_blwl sram_blwl_233_ (mux_2level_tapbuf_size4_22_sram_blwl_out[233:233] ,mux_2level_tapbuf_size4_22_sram_blwl_out[233:233] ,mux_2level_tapbuf_size4_22_sram_blwl_outb[233:233] ,mux_2level_tapbuf_size4_22_configbus0[233:233], mux_2level_tapbuf_size4_22_configbus1[233:233] , mux_2level_tapbuf_size4_22_configbus0_b[233:233] ); -sram6T_blwl sram_blwl_234_ (mux_2level_tapbuf_size4_22_sram_blwl_out[234:234] ,mux_2level_tapbuf_size4_22_sram_blwl_out[234:234] ,mux_2level_tapbuf_size4_22_sram_blwl_outb[234:234] ,mux_2level_tapbuf_size4_22_configbus0[234:234], mux_2level_tapbuf_size4_22_configbus1[234:234] , mux_2level_tapbuf_size4_22_configbus0_b[234:234] ); -sram6T_blwl sram_blwl_235_ (mux_2level_tapbuf_size4_22_sram_blwl_out[235:235] ,mux_2level_tapbuf_size4_22_sram_blwl_out[235:235] ,mux_2level_tapbuf_size4_22_sram_blwl_outb[235:235] ,mux_2level_tapbuf_size4_22_configbus0[235:235], mux_2level_tapbuf_size4_22_configbus1[235:235] , mux_2level_tapbuf_size4_22_configbus0_b[235:235] ); -wire [0:3] mux_2level_tapbuf_size4_23_inbus; -assign mux_2level_tapbuf_size4_23_inbus[0] = chany_0__1__midout_6_; -assign mux_2level_tapbuf_size4_23_inbus[1] = chany_0__1__midout_7_; -assign mux_2level_tapbuf_size4_23_inbus[2] = chany_0__1__midout_22_; -assign mux_2level_tapbuf_size4_23_inbus[3] = chany_0__1__midout_23_; -wire [236:239] mux_2level_tapbuf_size4_23_configbus0; -wire [236:239] mux_2level_tapbuf_size4_23_configbus1; -wire [236:239] mux_2level_tapbuf_size4_23_sram_blwl_out ; -wire [236:239] mux_2level_tapbuf_size4_23_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_23_configbus0[236:239] = sram_blwl_bl[236:239] ; -assign mux_2level_tapbuf_size4_23_configbus1[236:239] = sram_blwl_wl[236:239] ; -wire [236:239] mux_2level_tapbuf_size4_23_configbus0_b; -assign mux_2level_tapbuf_size4_23_configbus0_b[236:239] = sram_blwl_blb[236:239] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_23_ (mux_2level_tapbuf_size4_23_inbus, grid_0__1__pin_0__1__8_, mux_2level_tapbuf_size4_23_sram_blwl_out[236:239] , -mux_2level_tapbuf_size4_23_sram_blwl_outb[236:239] ); -//----- SRAM bits for MUX[23], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_236_ (mux_2level_tapbuf_size4_23_sram_blwl_out[236:236] ,mux_2level_tapbuf_size4_23_sram_blwl_out[236:236] ,mux_2level_tapbuf_size4_23_sram_blwl_outb[236:236] ,mux_2level_tapbuf_size4_23_configbus0[236:236], mux_2level_tapbuf_size4_23_configbus1[236:236] , mux_2level_tapbuf_size4_23_configbus0_b[236:236] ); -sram6T_blwl sram_blwl_237_ (mux_2level_tapbuf_size4_23_sram_blwl_out[237:237] ,mux_2level_tapbuf_size4_23_sram_blwl_out[237:237] ,mux_2level_tapbuf_size4_23_sram_blwl_outb[237:237] ,mux_2level_tapbuf_size4_23_configbus0[237:237], mux_2level_tapbuf_size4_23_configbus1[237:237] , mux_2level_tapbuf_size4_23_configbus0_b[237:237] ); -sram6T_blwl sram_blwl_238_ (mux_2level_tapbuf_size4_23_sram_blwl_out[238:238] ,mux_2level_tapbuf_size4_23_sram_blwl_out[238:238] ,mux_2level_tapbuf_size4_23_sram_blwl_outb[238:238] ,mux_2level_tapbuf_size4_23_configbus0[238:238], mux_2level_tapbuf_size4_23_configbus1[238:238] , mux_2level_tapbuf_size4_23_configbus0_b[238:238] ); -sram6T_blwl sram_blwl_239_ (mux_2level_tapbuf_size4_23_sram_blwl_out[239:239] ,mux_2level_tapbuf_size4_23_sram_blwl_out[239:239] ,mux_2level_tapbuf_size4_23_sram_blwl_outb[239:239] ,mux_2level_tapbuf_size4_23_configbus0[239:239], mux_2level_tapbuf_size4_23_configbus1[239:239] , mux_2level_tapbuf_size4_23_configbus0_b[239:239] ); -wire [0:3] mux_2level_tapbuf_size4_24_inbus; -assign mux_2level_tapbuf_size4_24_inbus[0] = chany_0__1__midout_8_; -assign mux_2level_tapbuf_size4_24_inbus[1] = chany_0__1__midout_9_; -assign mux_2level_tapbuf_size4_24_inbus[2] = chany_0__1__midout_24_; -assign mux_2level_tapbuf_size4_24_inbus[3] = chany_0__1__midout_25_; -wire [240:243] mux_2level_tapbuf_size4_24_configbus0; -wire [240:243] mux_2level_tapbuf_size4_24_configbus1; -wire [240:243] mux_2level_tapbuf_size4_24_sram_blwl_out ; -wire [240:243] mux_2level_tapbuf_size4_24_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_24_configbus0[240:243] = sram_blwl_bl[240:243] ; -assign mux_2level_tapbuf_size4_24_configbus1[240:243] = sram_blwl_wl[240:243] ; -wire [240:243] mux_2level_tapbuf_size4_24_configbus0_b; -assign mux_2level_tapbuf_size4_24_configbus0_b[240:243] = sram_blwl_blb[240:243] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_24_ (mux_2level_tapbuf_size4_24_inbus, grid_0__1__pin_0__1__10_, mux_2level_tapbuf_size4_24_sram_blwl_out[240:243] , -mux_2level_tapbuf_size4_24_sram_blwl_outb[240:243] ); -//----- SRAM bits for MUX[24], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_240_ (mux_2level_tapbuf_size4_24_sram_blwl_out[240:240] ,mux_2level_tapbuf_size4_24_sram_blwl_out[240:240] ,mux_2level_tapbuf_size4_24_sram_blwl_outb[240:240] ,mux_2level_tapbuf_size4_24_configbus0[240:240], mux_2level_tapbuf_size4_24_configbus1[240:240] , mux_2level_tapbuf_size4_24_configbus0_b[240:240] ); -sram6T_blwl sram_blwl_241_ (mux_2level_tapbuf_size4_24_sram_blwl_out[241:241] ,mux_2level_tapbuf_size4_24_sram_blwl_out[241:241] ,mux_2level_tapbuf_size4_24_sram_blwl_outb[241:241] ,mux_2level_tapbuf_size4_24_configbus0[241:241], mux_2level_tapbuf_size4_24_configbus1[241:241] , mux_2level_tapbuf_size4_24_configbus0_b[241:241] ); -sram6T_blwl sram_blwl_242_ (mux_2level_tapbuf_size4_24_sram_blwl_out[242:242] ,mux_2level_tapbuf_size4_24_sram_blwl_out[242:242] ,mux_2level_tapbuf_size4_24_sram_blwl_outb[242:242] ,mux_2level_tapbuf_size4_24_configbus0[242:242], mux_2level_tapbuf_size4_24_configbus1[242:242] , mux_2level_tapbuf_size4_24_configbus0_b[242:242] ); -sram6T_blwl sram_blwl_243_ (mux_2level_tapbuf_size4_24_sram_blwl_out[243:243] ,mux_2level_tapbuf_size4_24_sram_blwl_out[243:243] ,mux_2level_tapbuf_size4_24_sram_blwl_outb[243:243] ,mux_2level_tapbuf_size4_24_configbus0[243:243], mux_2level_tapbuf_size4_24_configbus1[243:243] , mux_2level_tapbuf_size4_24_configbus0_b[243:243] ); -wire [0:3] mux_2level_tapbuf_size4_25_inbus; -assign mux_2level_tapbuf_size4_25_inbus[0] = chany_0__1__midout_10_; -assign mux_2level_tapbuf_size4_25_inbus[1] = chany_0__1__midout_11_; -assign mux_2level_tapbuf_size4_25_inbus[2] = chany_0__1__midout_26_; -assign mux_2level_tapbuf_size4_25_inbus[3] = chany_0__1__midout_27_; -wire [244:247] mux_2level_tapbuf_size4_25_configbus0; -wire [244:247] mux_2level_tapbuf_size4_25_configbus1; -wire [244:247] mux_2level_tapbuf_size4_25_sram_blwl_out ; -wire [244:247] mux_2level_tapbuf_size4_25_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_25_configbus0[244:247] = sram_blwl_bl[244:247] ; -assign mux_2level_tapbuf_size4_25_configbus1[244:247] = sram_blwl_wl[244:247] ; -wire [244:247] mux_2level_tapbuf_size4_25_configbus0_b; -assign mux_2level_tapbuf_size4_25_configbus0_b[244:247] = sram_blwl_blb[244:247] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_25_ (mux_2level_tapbuf_size4_25_inbus, grid_0__1__pin_0__1__12_, mux_2level_tapbuf_size4_25_sram_blwl_out[244:247] , -mux_2level_tapbuf_size4_25_sram_blwl_outb[244:247] ); -//----- SRAM bits for MUX[25], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_244_ (mux_2level_tapbuf_size4_25_sram_blwl_out[244:244] ,mux_2level_tapbuf_size4_25_sram_blwl_out[244:244] ,mux_2level_tapbuf_size4_25_sram_blwl_outb[244:244] ,mux_2level_tapbuf_size4_25_configbus0[244:244], mux_2level_tapbuf_size4_25_configbus1[244:244] , mux_2level_tapbuf_size4_25_configbus0_b[244:244] ); -sram6T_blwl sram_blwl_245_ (mux_2level_tapbuf_size4_25_sram_blwl_out[245:245] ,mux_2level_tapbuf_size4_25_sram_blwl_out[245:245] ,mux_2level_tapbuf_size4_25_sram_blwl_outb[245:245] ,mux_2level_tapbuf_size4_25_configbus0[245:245], mux_2level_tapbuf_size4_25_configbus1[245:245] , mux_2level_tapbuf_size4_25_configbus0_b[245:245] ); -sram6T_blwl sram_blwl_246_ (mux_2level_tapbuf_size4_25_sram_blwl_out[246:246] ,mux_2level_tapbuf_size4_25_sram_blwl_out[246:246] ,mux_2level_tapbuf_size4_25_sram_blwl_outb[246:246] ,mux_2level_tapbuf_size4_25_configbus0[246:246], mux_2level_tapbuf_size4_25_configbus1[246:246] , mux_2level_tapbuf_size4_25_configbus0_b[246:246] ); -sram6T_blwl sram_blwl_247_ (mux_2level_tapbuf_size4_25_sram_blwl_out[247:247] ,mux_2level_tapbuf_size4_25_sram_blwl_out[247:247] ,mux_2level_tapbuf_size4_25_sram_blwl_outb[247:247] ,mux_2level_tapbuf_size4_25_configbus0[247:247], mux_2level_tapbuf_size4_25_configbus1[247:247] , mux_2level_tapbuf_size4_25_configbus0_b[247:247] ); -wire [0:3] mux_2level_tapbuf_size4_26_inbus; -assign mux_2level_tapbuf_size4_26_inbus[0] = chany_0__1__midout_12_; -assign mux_2level_tapbuf_size4_26_inbus[1] = chany_0__1__midout_13_; -assign mux_2level_tapbuf_size4_26_inbus[2] = chany_0__1__midout_28_; -assign mux_2level_tapbuf_size4_26_inbus[3] = chany_0__1__midout_29_; -wire [248:251] mux_2level_tapbuf_size4_26_configbus0; -wire [248:251] mux_2level_tapbuf_size4_26_configbus1; -wire [248:251] mux_2level_tapbuf_size4_26_sram_blwl_out ; -wire [248:251] mux_2level_tapbuf_size4_26_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_26_configbus0[248:251] = sram_blwl_bl[248:251] ; -assign mux_2level_tapbuf_size4_26_configbus1[248:251] = sram_blwl_wl[248:251] ; -wire [248:251] mux_2level_tapbuf_size4_26_configbus0_b; -assign mux_2level_tapbuf_size4_26_configbus0_b[248:251] = sram_blwl_blb[248:251] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_26_ (mux_2level_tapbuf_size4_26_inbus, grid_0__1__pin_0__1__14_, mux_2level_tapbuf_size4_26_sram_blwl_out[248:251] , -mux_2level_tapbuf_size4_26_sram_blwl_outb[248:251] ); -//----- SRAM bits for MUX[26], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_248_ (mux_2level_tapbuf_size4_26_sram_blwl_out[248:248] ,mux_2level_tapbuf_size4_26_sram_blwl_out[248:248] ,mux_2level_tapbuf_size4_26_sram_blwl_outb[248:248] ,mux_2level_tapbuf_size4_26_configbus0[248:248], mux_2level_tapbuf_size4_26_configbus1[248:248] , mux_2level_tapbuf_size4_26_configbus0_b[248:248] ); -sram6T_blwl sram_blwl_249_ (mux_2level_tapbuf_size4_26_sram_blwl_out[249:249] ,mux_2level_tapbuf_size4_26_sram_blwl_out[249:249] ,mux_2level_tapbuf_size4_26_sram_blwl_outb[249:249] ,mux_2level_tapbuf_size4_26_configbus0[249:249], mux_2level_tapbuf_size4_26_configbus1[249:249] , mux_2level_tapbuf_size4_26_configbus0_b[249:249] ); -sram6T_blwl sram_blwl_250_ (mux_2level_tapbuf_size4_26_sram_blwl_out[250:250] ,mux_2level_tapbuf_size4_26_sram_blwl_out[250:250] ,mux_2level_tapbuf_size4_26_sram_blwl_outb[250:250] ,mux_2level_tapbuf_size4_26_configbus0[250:250], mux_2level_tapbuf_size4_26_configbus1[250:250] , mux_2level_tapbuf_size4_26_configbus0_b[250:250] ); -sram6T_blwl sram_blwl_251_ (mux_2level_tapbuf_size4_26_sram_blwl_out[251:251] ,mux_2level_tapbuf_size4_26_sram_blwl_out[251:251] ,mux_2level_tapbuf_size4_26_sram_blwl_outb[251:251] ,mux_2level_tapbuf_size4_26_configbus0[251:251], mux_2level_tapbuf_size4_26_configbus1[251:251] , mux_2level_tapbuf_size4_26_configbus0_b[251:251] ); -endmodule -//----- END Verilog Module of Connection Box -Y direction [0][1] ----- - diff --git a/examples/verilog_test_example_1/routing/cby_1_1.v b/examples/verilog_test_example_1/routing/cby_1_1.v deleted file mode 100644 index b0e1dc7ae..000000000 --- a/examples/verilog_test_example_1/routing/cby_1_1.v +++ /dev/null @@ -1,304 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Connection Block - Y direction [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Connection Box -Y direction [1][1] ----- -module cby_1__1_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input chany_1__1__midout_0_, - -input chany_1__1__midout_1_, - -input chany_1__1__midout_2_, - -input chany_1__1__midout_3_, - -input chany_1__1__midout_4_, - -input chany_1__1__midout_5_, - -input chany_1__1__midout_6_, - -input chany_1__1__midout_7_, - -input chany_1__1__midout_8_, - -input chany_1__1__midout_9_, - -input chany_1__1__midout_10_, - -input chany_1__1__midout_11_, - -input chany_1__1__midout_12_, - -input chany_1__1__midout_13_, - -input chany_1__1__midout_14_, - -input chany_1__1__midout_15_, - -input chany_1__1__midout_16_, - -input chany_1__1__midout_17_, - -input chany_1__1__midout_18_, - -input chany_1__1__midout_19_, - -input chany_1__1__midout_20_, - -input chany_1__1__midout_21_, - -input chany_1__1__midout_22_, - -input chany_1__1__midout_23_, - -input chany_1__1__midout_24_, - -input chany_1__1__midout_25_, - -input chany_1__1__midout_26_, - -input chany_1__1__midout_27_, - -input chany_1__1__midout_28_, - -input chany_1__1__midout_29_, - -output grid_2__1__pin_0__3__0_, - -output grid_2__1__pin_0__3__2_, - -output grid_2__1__pin_0__3__4_, - -output grid_2__1__pin_0__3__6_, - -output grid_2__1__pin_0__3__8_, - -output grid_2__1__pin_0__3__10_, - -output grid_2__1__pin_0__3__12_, - -output grid_2__1__pin_0__3__14_, - -output grid_1__1__pin_0__1__1_, - -output grid_1__1__pin_0__1__5_, - -input [252:287] sram_blwl_bl , -input [252:287] sram_blwl_wl , -input [252:287] sram_blwl_blb ); -wire [0:3] mux_2level_tapbuf_size4_27_inbus; -assign mux_2level_tapbuf_size4_27_inbus[0] = chany_1__1__midout_6_; -assign mux_2level_tapbuf_size4_27_inbus[1] = chany_1__1__midout_7_; -assign mux_2level_tapbuf_size4_27_inbus[2] = chany_1__1__midout_18_; -assign mux_2level_tapbuf_size4_27_inbus[3] = chany_1__1__midout_19_; -wire [252:255] mux_2level_tapbuf_size4_27_configbus0; -wire [252:255] mux_2level_tapbuf_size4_27_configbus1; -wire [252:255] mux_2level_tapbuf_size4_27_sram_blwl_out ; -wire [252:255] mux_2level_tapbuf_size4_27_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_27_configbus0[252:255] = sram_blwl_bl[252:255] ; -assign mux_2level_tapbuf_size4_27_configbus1[252:255] = sram_blwl_wl[252:255] ; -wire [252:255] mux_2level_tapbuf_size4_27_configbus0_b; -assign mux_2level_tapbuf_size4_27_configbus0_b[252:255] = sram_blwl_blb[252:255] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_27_ (mux_2level_tapbuf_size4_27_inbus, grid_2__1__pin_0__3__0_, mux_2level_tapbuf_size4_27_sram_blwl_out[252:255] , -mux_2level_tapbuf_size4_27_sram_blwl_outb[252:255] ); -//----- SRAM bits for MUX[27], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_252_ (mux_2level_tapbuf_size4_27_sram_blwl_out[252:252] ,mux_2level_tapbuf_size4_27_sram_blwl_out[252:252] ,mux_2level_tapbuf_size4_27_sram_blwl_outb[252:252] ,mux_2level_tapbuf_size4_27_configbus0[252:252], mux_2level_tapbuf_size4_27_configbus1[252:252] , mux_2level_tapbuf_size4_27_configbus0_b[252:252] ); -sram6T_blwl sram_blwl_253_ (mux_2level_tapbuf_size4_27_sram_blwl_out[253:253] ,mux_2level_tapbuf_size4_27_sram_blwl_out[253:253] ,mux_2level_tapbuf_size4_27_sram_blwl_outb[253:253] ,mux_2level_tapbuf_size4_27_configbus0[253:253], mux_2level_tapbuf_size4_27_configbus1[253:253] , mux_2level_tapbuf_size4_27_configbus0_b[253:253] ); -sram6T_blwl sram_blwl_254_ (mux_2level_tapbuf_size4_27_sram_blwl_out[254:254] ,mux_2level_tapbuf_size4_27_sram_blwl_out[254:254] ,mux_2level_tapbuf_size4_27_sram_blwl_outb[254:254] ,mux_2level_tapbuf_size4_27_configbus0[254:254], mux_2level_tapbuf_size4_27_configbus1[254:254] , mux_2level_tapbuf_size4_27_configbus0_b[254:254] ); -sram6T_blwl sram_blwl_255_ (mux_2level_tapbuf_size4_27_sram_blwl_out[255:255] ,mux_2level_tapbuf_size4_27_sram_blwl_out[255:255] ,mux_2level_tapbuf_size4_27_sram_blwl_outb[255:255] ,mux_2level_tapbuf_size4_27_configbus0[255:255], mux_2level_tapbuf_size4_27_configbus1[255:255] , mux_2level_tapbuf_size4_27_configbus0_b[255:255] ); -wire [0:3] mux_2level_tapbuf_size4_28_inbus; -assign mux_2level_tapbuf_size4_28_inbus[0] = chany_1__1__midout_0_; -assign mux_2level_tapbuf_size4_28_inbus[1] = chany_1__1__midout_1_; -assign mux_2level_tapbuf_size4_28_inbus[2] = chany_1__1__midout_16_; -assign mux_2level_tapbuf_size4_28_inbus[3] = chany_1__1__midout_17_; -wire [256:259] mux_2level_tapbuf_size4_28_configbus0; -wire [256:259] mux_2level_tapbuf_size4_28_configbus1; -wire [256:259] mux_2level_tapbuf_size4_28_sram_blwl_out ; -wire [256:259] mux_2level_tapbuf_size4_28_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_28_configbus0[256:259] = sram_blwl_bl[256:259] ; -assign mux_2level_tapbuf_size4_28_configbus1[256:259] = sram_blwl_wl[256:259] ; -wire [256:259] mux_2level_tapbuf_size4_28_configbus0_b; -assign mux_2level_tapbuf_size4_28_configbus0_b[256:259] = sram_blwl_blb[256:259] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_28_ (mux_2level_tapbuf_size4_28_inbus, grid_2__1__pin_0__3__2_, mux_2level_tapbuf_size4_28_sram_blwl_out[256:259] , -mux_2level_tapbuf_size4_28_sram_blwl_outb[256:259] ); -//----- SRAM bits for MUX[28], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_256_ (mux_2level_tapbuf_size4_28_sram_blwl_out[256:256] ,mux_2level_tapbuf_size4_28_sram_blwl_out[256:256] ,mux_2level_tapbuf_size4_28_sram_blwl_outb[256:256] ,mux_2level_tapbuf_size4_28_configbus0[256:256], mux_2level_tapbuf_size4_28_configbus1[256:256] , mux_2level_tapbuf_size4_28_configbus0_b[256:256] ); -sram6T_blwl sram_blwl_257_ (mux_2level_tapbuf_size4_28_sram_blwl_out[257:257] ,mux_2level_tapbuf_size4_28_sram_blwl_out[257:257] ,mux_2level_tapbuf_size4_28_sram_blwl_outb[257:257] ,mux_2level_tapbuf_size4_28_configbus0[257:257], mux_2level_tapbuf_size4_28_configbus1[257:257] , mux_2level_tapbuf_size4_28_configbus0_b[257:257] ); -sram6T_blwl sram_blwl_258_ (mux_2level_tapbuf_size4_28_sram_blwl_out[258:258] ,mux_2level_tapbuf_size4_28_sram_blwl_out[258:258] ,mux_2level_tapbuf_size4_28_sram_blwl_outb[258:258] ,mux_2level_tapbuf_size4_28_configbus0[258:258], mux_2level_tapbuf_size4_28_configbus1[258:258] , mux_2level_tapbuf_size4_28_configbus0_b[258:258] ); -sram6T_blwl sram_blwl_259_ (mux_2level_tapbuf_size4_28_sram_blwl_out[259:259] ,mux_2level_tapbuf_size4_28_sram_blwl_out[259:259] ,mux_2level_tapbuf_size4_28_sram_blwl_outb[259:259] ,mux_2level_tapbuf_size4_28_configbus0[259:259], mux_2level_tapbuf_size4_28_configbus1[259:259] , mux_2level_tapbuf_size4_28_configbus0_b[259:259] ); -wire [0:3] mux_2level_tapbuf_size4_29_inbus; -assign mux_2level_tapbuf_size4_29_inbus[0] = chany_1__1__midout_2_; -assign mux_2level_tapbuf_size4_29_inbus[1] = chany_1__1__midout_3_; -assign mux_2level_tapbuf_size4_29_inbus[2] = chany_1__1__midout_20_; -assign mux_2level_tapbuf_size4_29_inbus[3] = chany_1__1__midout_21_; -wire [260:263] mux_2level_tapbuf_size4_29_configbus0; -wire [260:263] mux_2level_tapbuf_size4_29_configbus1; -wire [260:263] mux_2level_tapbuf_size4_29_sram_blwl_out ; -wire [260:263] mux_2level_tapbuf_size4_29_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_29_configbus0[260:263] = sram_blwl_bl[260:263] ; -assign mux_2level_tapbuf_size4_29_configbus1[260:263] = sram_blwl_wl[260:263] ; -wire [260:263] mux_2level_tapbuf_size4_29_configbus0_b; -assign mux_2level_tapbuf_size4_29_configbus0_b[260:263] = sram_blwl_blb[260:263] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_29_ (mux_2level_tapbuf_size4_29_inbus, grid_2__1__pin_0__3__4_, mux_2level_tapbuf_size4_29_sram_blwl_out[260:263] , -mux_2level_tapbuf_size4_29_sram_blwl_outb[260:263] ); -//----- SRAM bits for MUX[29], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_260_ (mux_2level_tapbuf_size4_29_sram_blwl_out[260:260] ,mux_2level_tapbuf_size4_29_sram_blwl_out[260:260] ,mux_2level_tapbuf_size4_29_sram_blwl_outb[260:260] ,mux_2level_tapbuf_size4_29_configbus0[260:260], mux_2level_tapbuf_size4_29_configbus1[260:260] , mux_2level_tapbuf_size4_29_configbus0_b[260:260] ); -sram6T_blwl sram_blwl_261_ (mux_2level_tapbuf_size4_29_sram_blwl_out[261:261] ,mux_2level_tapbuf_size4_29_sram_blwl_out[261:261] ,mux_2level_tapbuf_size4_29_sram_blwl_outb[261:261] ,mux_2level_tapbuf_size4_29_configbus0[261:261], mux_2level_tapbuf_size4_29_configbus1[261:261] , mux_2level_tapbuf_size4_29_configbus0_b[261:261] ); -sram6T_blwl sram_blwl_262_ (mux_2level_tapbuf_size4_29_sram_blwl_out[262:262] ,mux_2level_tapbuf_size4_29_sram_blwl_out[262:262] ,mux_2level_tapbuf_size4_29_sram_blwl_outb[262:262] ,mux_2level_tapbuf_size4_29_configbus0[262:262], mux_2level_tapbuf_size4_29_configbus1[262:262] , mux_2level_tapbuf_size4_29_configbus0_b[262:262] ); -sram6T_blwl sram_blwl_263_ (mux_2level_tapbuf_size4_29_sram_blwl_out[263:263] ,mux_2level_tapbuf_size4_29_sram_blwl_out[263:263] ,mux_2level_tapbuf_size4_29_sram_blwl_outb[263:263] ,mux_2level_tapbuf_size4_29_configbus0[263:263], mux_2level_tapbuf_size4_29_configbus1[263:263] , mux_2level_tapbuf_size4_29_configbus0_b[263:263] ); -wire [0:3] mux_2level_tapbuf_size4_30_inbus; -assign mux_2level_tapbuf_size4_30_inbus[0] = chany_1__1__midout_4_; -assign mux_2level_tapbuf_size4_30_inbus[1] = chany_1__1__midout_5_; -assign mux_2level_tapbuf_size4_30_inbus[2] = chany_1__1__midout_22_; -assign mux_2level_tapbuf_size4_30_inbus[3] = chany_1__1__midout_23_; -wire [264:267] mux_2level_tapbuf_size4_30_configbus0; -wire [264:267] mux_2level_tapbuf_size4_30_configbus1; -wire [264:267] mux_2level_tapbuf_size4_30_sram_blwl_out ; -wire [264:267] mux_2level_tapbuf_size4_30_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_30_configbus0[264:267] = sram_blwl_bl[264:267] ; -assign mux_2level_tapbuf_size4_30_configbus1[264:267] = sram_blwl_wl[264:267] ; -wire [264:267] mux_2level_tapbuf_size4_30_configbus0_b; -assign mux_2level_tapbuf_size4_30_configbus0_b[264:267] = sram_blwl_blb[264:267] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_30_ (mux_2level_tapbuf_size4_30_inbus, grid_2__1__pin_0__3__6_, mux_2level_tapbuf_size4_30_sram_blwl_out[264:267] , -mux_2level_tapbuf_size4_30_sram_blwl_outb[264:267] ); -//----- SRAM bits for MUX[30], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_264_ (mux_2level_tapbuf_size4_30_sram_blwl_out[264:264] ,mux_2level_tapbuf_size4_30_sram_blwl_out[264:264] ,mux_2level_tapbuf_size4_30_sram_blwl_outb[264:264] ,mux_2level_tapbuf_size4_30_configbus0[264:264], mux_2level_tapbuf_size4_30_configbus1[264:264] , mux_2level_tapbuf_size4_30_configbus0_b[264:264] ); -sram6T_blwl sram_blwl_265_ (mux_2level_tapbuf_size4_30_sram_blwl_out[265:265] ,mux_2level_tapbuf_size4_30_sram_blwl_out[265:265] ,mux_2level_tapbuf_size4_30_sram_blwl_outb[265:265] ,mux_2level_tapbuf_size4_30_configbus0[265:265], mux_2level_tapbuf_size4_30_configbus1[265:265] , mux_2level_tapbuf_size4_30_configbus0_b[265:265] ); -sram6T_blwl sram_blwl_266_ (mux_2level_tapbuf_size4_30_sram_blwl_out[266:266] ,mux_2level_tapbuf_size4_30_sram_blwl_out[266:266] ,mux_2level_tapbuf_size4_30_sram_blwl_outb[266:266] ,mux_2level_tapbuf_size4_30_configbus0[266:266], mux_2level_tapbuf_size4_30_configbus1[266:266] , mux_2level_tapbuf_size4_30_configbus0_b[266:266] ); -sram6T_blwl sram_blwl_267_ (mux_2level_tapbuf_size4_30_sram_blwl_out[267:267] ,mux_2level_tapbuf_size4_30_sram_blwl_out[267:267] ,mux_2level_tapbuf_size4_30_sram_blwl_outb[267:267] ,mux_2level_tapbuf_size4_30_configbus0[267:267], mux_2level_tapbuf_size4_30_configbus1[267:267] , mux_2level_tapbuf_size4_30_configbus0_b[267:267] ); -wire [0:3] mux_2level_tapbuf_size4_31_inbus; -assign mux_2level_tapbuf_size4_31_inbus[0] = chany_1__1__midout_10_; -assign mux_2level_tapbuf_size4_31_inbus[1] = chany_1__1__midout_11_; -assign mux_2level_tapbuf_size4_31_inbus[2] = chany_1__1__midout_22_; -assign mux_2level_tapbuf_size4_31_inbus[3] = chany_1__1__midout_23_; -wire [268:271] mux_2level_tapbuf_size4_31_configbus0; -wire [268:271] mux_2level_tapbuf_size4_31_configbus1; -wire [268:271] mux_2level_tapbuf_size4_31_sram_blwl_out ; -wire [268:271] mux_2level_tapbuf_size4_31_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_31_configbus0[268:271] = sram_blwl_bl[268:271] ; -assign mux_2level_tapbuf_size4_31_configbus1[268:271] = sram_blwl_wl[268:271] ; -wire [268:271] mux_2level_tapbuf_size4_31_configbus0_b; -assign mux_2level_tapbuf_size4_31_configbus0_b[268:271] = sram_blwl_blb[268:271] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_31_ (mux_2level_tapbuf_size4_31_inbus, grid_2__1__pin_0__3__8_, mux_2level_tapbuf_size4_31_sram_blwl_out[268:271] , -mux_2level_tapbuf_size4_31_sram_blwl_outb[268:271] ); -//----- SRAM bits for MUX[31], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_268_ (mux_2level_tapbuf_size4_31_sram_blwl_out[268:268] ,mux_2level_tapbuf_size4_31_sram_blwl_out[268:268] ,mux_2level_tapbuf_size4_31_sram_blwl_outb[268:268] ,mux_2level_tapbuf_size4_31_configbus0[268:268], mux_2level_tapbuf_size4_31_configbus1[268:268] , mux_2level_tapbuf_size4_31_configbus0_b[268:268] ); -sram6T_blwl sram_blwl_269_ (mux_2level_tapbuf_size4_31_sram_blwl_out[269:269] ,mux_2level_tapbuf_size4_31_sram_blwl_out[269:269] ,mux_2level_tapbuf_size4_31_sram_blwl_outb[269:269] ,mux_2level_tapbuf_size4_31_configbus0[269:269], mux_2level_tapbuf_size4_31_configbus1[269:269] , mux_2level_tapbuf_size4_31_configbus0_b[269:269] ); -sram6T_blwl sram_blwl_270_ (mux_2level_tapbuf_size4_31_sram_blwl_out[270:270] ,mux_2level_tapbuf_size4_31_sram_blwl_out[270:270] ,mux_2level_tapbuf_size4_31_sram_blwl_outb[270:270] ,mux_2level_tapbuf_size4_31_configbus0[270:270], mux_2level_tapbuf_size4_31_configbus1[270:270] , mux_2level_tapbuf_size4_31_configbus0_b[270:270] ); -sram6T_blwl sram_blwl_271_ (mux_2level_tapbuf_size4_31_sram_blwl_out[271:271] ,mux_2level_tapbuf_size4_31_sram_blwl_out[271:271] ,mux_2level_tapbuf_size4_31_sram_blwl_outb[271:271] ,mux_2level_tapbuf_size4_31_configbus0[271:271], mux_2level_tapbuf_size4_31_configbus1[271:271] , mux_2level_tapbuf_size4_31_configbus0_b[271:271] ); -wire [0:3] mux_2level_tapbuf_size4_32_inbus; -assign mux_2level_tapbuf_size4_32_inbus[0] = chany_1__1__midout_8_; -assign mux_2level_tapbuf_size4_32_inbus[1] = chany_1__1__midout_9_; -assign mux_2level_tapbuf_size4_32_inbus[2] = chany_1__1__midout_24_; -assign mux_2level_tapbuf_size4_32_inbus[3] = chany_1__1__midout_25_; -wire [272:275] mux_2level_tapbuf_size4_32_configbus0; -wire [272:275] mux_2level_tapbuf_size4_32_configbus1; -wire [272:275] mux_2level_tapbuf_size4_32_sram_blwl_out ; -wire [272:275] mux_2level_tapbuf_size4_32_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_32_configbus0[272:275] = sram_blwl_bl[272:275] ; -assign mux_2level_tapbuf_size4_32_configbus1[272:275] = sram_blwl_wl[272:275] ; -wire [272:275] mux_2level_tapbuf_size4_32_configbus0_b; -assign mux_2level_tapbuf_size4_32_configbus0_b[272:275] = sram_blwl_blb[272:275] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_32_ (mux_2level_tapbuf_size4_32_inbus, grid_2__1__pin_0__3__10_, mux_2level_tapbuf_size4_32_sram_blwl_out[272:275] , -mux_2level_tapbuf_size4_32_sram_blwl_outb[272:275] ); -//----- SRAM bits for MUX[32], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_272_ (mux_2level_tapbuf_size4_32_sram_blwl_out[272:272] ,mux_2level_tapbuf_size4_32_sram_blwl_out[272:272] ,mux_2level_tapbuf_size4_32_sram_blwl_outb[272:272] ,mux_2level_tapbuf_size4_32_configbus0[272:272], mux_2level_tapbuf_size4_32_configbus1[272:272] , mux_2level_tapbuf_size4_32_configbus0_b[272:272] ); -sram6T_blwl sram_blwl_273_ (mux_2level_tapbuf_size4_32_sram_blwl_out[273:273] ,mux_2level_tapbuf_size4_32_sram_blwl_out[273:273] ,mux_2level_tapbuf_size4_32_sram_blwl_outb[273:273] ,mux_2level_tapbuf_size4_32_configbus0[273:273], mux_2level_tapbuf_size4_32_configbus1[273:273] , mux_2level_tapbuf_size4_32_configbus0_b[273:273] ); -sram6T_blwl sram_blwl_274_ (mux_2level_tapbuf_size4_32_sram_blwl_out[274:274] ,mux_2level_tapbuf_size4_32_sram_blwl_out[274:274] ,mux_2level_tapbuf_size4_32_sram_blwl_outb[274:274] ,mux_2level_tapbuf_size4_32_configbus0[274:274], mux_2level_tapbuf_size4_32_configbus1[274:274] , mux_2level_tapbuf_size4_32_configbus0_b[274:274] ); -sram6T_blwl sram_blwl_275_ (mux_2level_tapbuf_size4_32_sram_blwl_out[275:275] ,mux_2level_tapbuf_size4_32_sram_blwl_out[275:275] ,mux_2level_tapbuf_size4_32_sram_blwl_outb[275:275] ,mux_2level_tapbuf_size4_32_configbus0[275:275], mux_2level_tapbuf_size4_32_configbus1[275:275] , mux_2level_tapbuf_size4_32_configbus0_b[275:275] ); -wire [0:3] mux_2level_tapbuf_size4_33_inbus; -assign mux_2level_tapbuf_size4_33_inbus[0] = chany_1__1__midout_14_; -assign mux_2level_tapbuf_size4_33_inbus[1] = chany_1__1__midout_15_; -assign mux_2level_tapbuf_size4_33_inbus[2] = chany_1__1__midout_26_; -assign mux_2level_tapbuf_size4_33_inbus[3] = chany_1__1__midout_27_; -wire [276:279] mux_2level_tapbuf_size4_33_configbus0; -wire [276:279] mux_2level_tapbuf_size4_33_configbus1; -wire [276:279] mux_2level_tapbuf_size4_33_sram_blwl_out ; -wire [276:279] mux_2level_tapbuf_size4_33_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_33_configbus0[276:279] = sram_blwl_bl[276:279] ; -assign mux_2level_tapbuf_size4_33_configbus1[276:279] = sram_blwl_wl[276:279] ; -wire [276:279] mux_2level_tapbuf_size4_33_configbus0_b; -assign mux_2level_tapbuf_size4_33_configbus0_b[276:279] = sram_blwl_blb[276:279] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_33_ (mux_2level_tapbuf_size4_33_inbus, grid_2__1__pin_0__3__12_, mux_2level_tapbuf_size4_33_sram_blwl_out[276:279] , -mux_2level_tapbuf_size4_33_sram_blwl_outb[276:279] ); -//----- SRAM bits for MUX[33], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_276_ (mux_2level_tapbuf_size4_33_sram_blwl_out[276:276] ,mux_2level_tapbuf_size4_33_sram_blwl_out[276:276] ,mux_2level_tapbuf_size4_33_sram_blwl_outb[276:276] ,mux_2level_tapbuf_size4_33_configbus0[276:276], mux_2level_tapbuf_size4_33_configbus1[276:276] , mux_2level_tapbuf_size4_33_configbus0_b[276:276] ); -sram6T_blwl sram_blwl_277_ (mux_2level_tapbuf_size4_33_sram_blwl_out[277:277] ,mux_2level_tapbuf_size4_33_sram_blwl_out[277:277] ,mux_2level_tapbuf_size4_33_sram_blwl_outb[277:277] ,mux_2level_tapbuf_size4_33_configbus0[277:277], mux_2level_tapbuf_size4_33_configbus1[277:277] , mux_2level_tapbuf_size4_33_configbus0_b[277:277] ); -sram6T_blwl sram_blwl_278_ (mux_2level_tapbuf_size4_33_sram_blwl_out[278:278] ,mux_2level_tapbuf_size4_33_sram_blwl_out[278:278] ,mux_2level_tapbuf_size4_33_sram_blwl_outb[278:278] ,mux_2level_tapbuf_size4_33_configbus0[278:278], mux_2level_tapbuf_size4_33_configbus1[278:278] , mux_2level_tapbuf_size4_33_configbus0_b[278:278] ); -sram6T_blwl sram_blwl_279_ (mux_2level_tapbuf_size4_33_sram_blwl_out[279:279] ,mux_2level_tapbuf_size4_33_sram_blwl_out[279:279] ,mux_2level_tapbuf_size4_33_sram_blwl_outb[279:279] ,mux_2level_tapbuf_size4_33_configbus0[279:279], mux_2level_tapbuf_size4_33_configbus1[279:279] , mux_2level_tapbuf_size4_33_configbus0_b[279:279] ); -wire [0:3] mux_2level_tapbuf_size4_34_inbus; -assign mux_2level_tapbuf_size4_34_inbus[0] = chany_1__1__midout_12_; -assign mux_2level_tapbuf_size4_34_inbus[1] = chany_1__1__midout_13_; -assign mux_2level_tapbuf_size4_34_inbus[2] = chany_1__1__midout_28_; -assign mux_2level_tapbuf_size4_34_inbus[3] = chany_1__1__midout_29_; -wire [280:283] mux_2level_tapbuf_size4_34_configbus0; -wire [280:283] mux_2level_tapbuf_size4_34_configbus1; -wire [280:283] mux_2level_tapbuf_size4_34_sram_blwl_out ; -wire [280:283] mux_2level_tapbuf_size4_34_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_34_configbus0[280:283] = sram_blwl_bl[280:283] ; -assign mux_2level_tapbuf_size4_34_configbus1[280:283] = sram_blwl_wl[280:283] ; -wire [280:283] mux_2level_tapbuf_size4_34_configbus0_b; -assign mux_2level_tapbuf_size4_34_configbus0_b[280:283] = sram_blwl_blb[280:283] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_34_ (mux_2level_tapbuf_size4_34_inbus, grid_2__1__pin_0__3__14_, mux_2level_tapbuf_size4_34_sram_blwl_out[280:283] , -mux_2level_tapbuf_size4_34_sram_blwl_outb[280:283] ); -//----- SRAM bits for MUX[34], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_280_ (mux_2level_tapbuf_size4_34_sram_blwl_out[280:280] ,mux_2level_tapbuf_size4_34_sram_blwl_out[280:280] ,mux_2level_tapbuf_size4_34_sram_blwl_outb[280:280] ,mux_2level_tapbuf_size4_34_configbus0[280:280], mux_2level_tapbuf_size4_34_configbus1[280:280] , mux_2level_tapbuf_size4_34_configbus0_b[280:280] ); -sram6T_blwl sram_blwl_281_ (mux_2level_tapbuf_size4_34_sram_blwl_out[281:281] ,mux_2level_tapbuf_size4_34_sram_blwl_out[281:281] ,mux_2level_tapbuf_size4_34_sram_blwl_outb[281:281] ,mux_2level_tapbuf_size4_34_configbus0[281:281], mux_2level_tapbuf_size4_34_configbus1[281:281] , mux_2level_tapbuf_size4_34_configbus0_b[281:281] ); -sram6T_blwl sram_blwl_282_ (mux_2level_tapbuf_size4_34_sram_blwl_out[282:282] ,mux_2level_tapbuf_size4_34_sram_blwl_out[282:282] ,mux_2level_tapbuf_size4_34_sram_blwl_outb[282:282] ,mux_2level_tapbuf_size4_34_configbus0[282:282], mux_2level_tapbuf_size4_34_configbus1[282:282] , mux_2level_tapbuf_size4_34_configbus0_b[282:282] ); -sram6T_blwl sram_blwl_283_ (mux_2level_tapbuf_size4_34_sram_blwl_out[283:283] ,mux_2level_tapbuf_size4_34_sram_blwl_out[283:283] ,mux_2level_tapbuf_size4_34_sram_blwl_outb[283:283] ,mux_2level_tapbuf_size4_34_configbus0[283:283], mux_2level_tapbuf_size4_34_configbus1[283:283] , mux_2level_tapbuf_size4_34_configbus0_b[283:283] ); -wire [0:3] mux_2level_tapbuf_size4_35_inbus; -assign mux_2level_tapbuf_size4_35_inbus[0] = chany_1__1__midout_0_; -assign mux_2level_tapbuf_size4_35_inbus[1] = chany_1__1__midout_1_; -assign mux_2level_tapbuf_size4_35_inbus[2] = chany_1__1__midout_16_; -assign mux_2level_tapbuf_size4_35_inbus[3] = chany_1__1__midout_17_; -wire [284:287] mux_2level_tapbuf_size4_35_configbus0; -wire [284:287] mux_2level_tapbuf_size4_35_configbus1; -wire [284:287] mux_2level_tapbuf_size4_35_sram_blwl_out ; -wire [284:287] mux_2level_tapbuf_size4_35_sram_blwl_outb ; -assign mux_2level_tapbuf_size4_35_configbus0[284:287] = sram_blwl_bl[284:287] ; -assign mux_2level_tapbuf_size4_35_configbus1[284:287] = sram_blwl_wl[284:287] ; -wire [284:287] mux_2level_tapbuf_size4_35_configbus0_b; -assign mux_2level_tapbuf_size4_35_configbus0_b[284:287] = sram_blwl_blb[284:287] ; -mux_2level_tapbuf_size4 mux_2level_tapbuf_size4_35_ (mux_2level_tapbuf_size4_35_inbus, grid_1__1__pin_0__1__1_, mux_2level_tapbuf_size4_35_sram_blwl_out[284:287] , -mux_2level_tapbuf_size4_35_sram_blwl_outb[284:287] ); -//----- SRAM bits for MUX[35], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1010----- -sram6T_blwl sram_blwl_284_ (mux_2level_tapbuf_size4_35_sram_blwl_out[284:284] ,mux_2level_tapbuf_size4_35_sram_blwl_out[284:284] ,mux_2level_tapbuf_size4_35_sram_blwl_outb[284:284] ,mux_2level_tapbuf_size4_35_configbus0[284:284], mux_2level_tapbuf_size4_35_configbus1[284:284] , mux_2level_tapbuf_size4_35_configbus0_b[284:284] ); -sram6T_blwl sram_blwl_285_ (mux_2level_tapbuf_size4_35_sram_blwl_out[285:285] ,mux_2level_tapbuf_size4_35_sram_blwl_out[285:285] ,mux_2level_tapbuf_size4_35_sram_blwl_outb[285:285] ,mux_2level_tapbuf_size4_35_configbus0[285:285], mux_2level_tapbuf_size4_35_configbus1[285:285] , mux_2level_tapbuf_size4_35_configbus0_b[285:285] ); -sram6T_blwl sram_blwl_286_ (mux_2level_tapbuf_size4_35_sram_blwl_out[286:286] ,mux_2level_tapbuf_size4_35_sram_blwl_out[286:286] ,mux_2level_tapbuf_size4_35_sram_blwl_outb[286:286] ,mux_2level_tapbuf_size4_35_configbus0[286:286], mux_2level_tapbuf_size4_35_configbus1[286:286] , mux_2level_tapbuf_size4_35_configbus0_b[286:286] ); -sram6T_blwl sram_blwl_287_ (mux_2level_tapbuf_size4_35_sram_blwl_out[287:287] ,mux_2level_tapbuf_size4_35_sram_blwl_out[287:287] ,mux_2level_tapbuf_size4_35_sram_blwl_outb[287:287] ,mux_2level_tapbuf_size4_35_configbus0[287:287], mux_2level_tapbuf_size4_35_configbus1[287:287] , mux_2level_tapbuf_size4_35_configbus0_b[287:287] ); -endmodule -//----- END Verilog Module of Connection Box -Y direction [1][1] ----- - diff --git a/examples/verilog_test_example_1/routing/chanx_1_0.v b/examples/verilog_test_example_1/routing/chanx_1_0.v deleted file mode 100644 index 675c69f8d..000000000 --- a/examples/verilog_test_example_1/routing/chanx_1_0.v +++ /dev/null @@ -1,175 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Routing Channel - X direction [1][0] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Channel X [1][0] ----- -module chanx_1__0_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, - input in0, //--- track 0 input - output out1, //--- track 1 output - input in2, //--- track 2 input - output out3, //--- track 3 output - input in4, //--- track 4 input - output out5, //--- track 5 output - input in6, //--- track 6 input - output out7, //--- track 7 output - input in8, //--- track 8 input - output out9, //--- track 9 output - input in10, //--- track 10 input - output out11, //--- track 11 output - input in12, //--- track 12 input - output out13, //--- track 13 output - input in14, //--- track 14 input - output out15, //--- track 15 output - input in16, //--- track 16 input - output out17, //--- track 17 output - input in18, //--- track 18 input - output out19, //--- track 19 output - input in20, //--- track 20 input - output out21, //--- track 21 output - input in22, //--- track 22 input - output out23, //--- track 23 output - input in24, //--- track 24 input - output out25, //--- track 25 output - input in26, //--- track 26 input - output out27, //--- track 27 output - input in28, //--- track 28 input - output out29, //--- track 29 output - output out0, //--- track 0 output - input in1, //--- track 1 input - output out2, //--- track 2 output - input in3, //--- track 3 input - output out4, //--- track 4 output - input in5, //--- track 5 input - output out6, //--- track 6 output - input in7, //--- track 7 input - output out8, //--- track 8 output - input in9, //--- track 9 input - output out10, //--- track 10 output - input in11, //--- track 11 input - output out12, //--- track 12 output - input in13, //--- track 13 input - output out14, //--- track 14 output - input in15, //--- track 15 input - output out16, //--- track 16 output - input in17, //--- track 17 input - output out18, //--- track 18 output - input in19, //--- track 19 input - output out20, //--- track 20 output - input in21, //--- track 21 input - output out22, //--- track 22 output - input in23, //--- track 23 input - output out24, //--- track 24 output - input in25, //--- track 25 input - output out26, //--- track 26 output - input in27, //--- track 27 input - output out28, //--- track 28 output - input in29, //--- track 29 input - output mid_out0, // Middle output 0 to logic blocks - output mid_out1, // Middle output 1 to logic blocks - output mid_out2, // Middle output 2 to logic blocks - output mid_out3, // Middle output 3 to logic blocks - output mid_out4, // Middle output 4 to logic blocks - output mid_out5, // Middle output 5 to logic blocks - output mid_out6, // Middle output 6 to logic blocks - output mid_out7, // Middle output 7 to logic blocks - output mid_out8, // Middle output 8 to logic blocks - output mid_out9, // Middle output 9 to logic blocks - output mid_out10, // Middle output 10 to logic blocks - output mid_out11, // Middle output 11 to logic blocks - output mid_out12, // Middle output 12 to logic blocks - output mid_out13, // Middle output 13 to logic blocks - output mid_out14, // Middle output 14 to logic blocks - output mid_out15, // Middle output 15 to logic blocks - output mid_out16, // Middle output 16 to logic blocks - output mid_out17, // Middle output 17 to logic blocks - output mid_out18, // Middle output 18 to logic blocks - output mid_out19, // Middle output 19 to logic blocks - output mid_out20, // Middle output 20 to logic blocks - output mid_out21, // Middle output 21 to logic blocks - output mid_out22, // Middle output 22 to logic blocks - output mid_out23, // Middle output 23 to logic blocks - output mid_out24, // Middle output 24 to logic blocks - output mid_out25, // Middle output 25 to logic blocks - output mid_out26, // Middle output 26 to logic blocks - output mid_out27, // Middle output 27 to logic blocks - output mid_out28, // Middle output 28 to logic blocks - output mid_out29 // Middle output 29 to logic blocks - ); -assign out0 = in0; -assign mid_out0 = in0; -assign out1 = in1; -assign mid_out1 = in1; -assign out2 = in2; -assign mid_out2 = in2; -assign out3 = in3; -assign mid_out3 = in3; -assign out4 = in4; -assign mid_out4 = in4; -assign out5 = in5; -assign mid_out5 = in5; -assign out6 = in6; -assign mid_out6 = in6; -assign out7 = in7; -assign mid_out7 = in7; -assign out8 = in8; -assign mid_out8 = in8; -assign out9 = in9; -assign mid_out9 = in9; -assign out10 = in10; -assign mid_out10 = in10; -assign out11 = in11; -assign mid_out11 = in11; -assign out12 = in12; -assign mid_out12 = in12; -assign out13 = in13; -assign mid_out13 = in13; -assign out14 = in14; -assign mid_out14 = in14; -assign out15 = in15; -assign mid_out15 = in15; -assign out16 = in16; -assign mid_out16 = in16; -assign out17 = in17; -assign mid_out17 = in17; -assign out18 = in18; -assign mid_out18 = in18; -assign out19 = in19; -assign mid_out19 = in19; -assign out20 = in20; -assign mid_out20 = in20; -assign out21 = in21; -assign mid_out21 = in21; -assign out22 = in22; -assign mid_out22 = in22; -assign out23 = in23; -assign mid_out23 = in23; -assign out24 = in24; -assign mid_out24 = in24; -assign out25 = in25; -assign mid_out25 = in25; -assign out26 = in26; -assign mid_out26 = in26; -assign out27 = in27; -assign mid_out27 = in27; -assign out28 = in28; -assign mid_out28 = in28; -assign out29 = in29; -assign mid_out29 = in29; -endmodule -//----- END Verilog Module of Channel X [1][0] ----- - diff --git a/examples/verilog_test_example_1/routing/chanx_1_1.v b/examples/verilog_test_example_1/routing/chanx_1_1.v deleted file mode 100644 index 45513c1c4..000000000 --- a/examples/verilog_test_example_1/routing/chanx_1_1.v +++ /dev/null @@ -1,175 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Routing Channel - X direction [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Channel X [1][1] ----- -module chanx_1__1_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, - input in0, //--- track 0 input - output out1, //--- track 1 output - input in2, //--- track 2 input - output out3, //--- track 3 output - input in4, //--- track 4 input - output out5, //--- track 5 output - input in6, //--- track 6 input - output out7, //--- track 7 output - input in8, //--- track 8 input - output out9, //--- track 9 output - input in10, //--- track 10 input - output out11, //--- track 11 output - input in12, //--- track 12 input - output out13, //--- track 13 output - input in14, //--- track 14 input - output out15, //--- track 15 output - input in16, //--- track 16 input - output out17, //--- track 17 output - input in18, //--- track 18 input - output out19, //--- track 19 output - input in20, //--- track 20 input - output out21, //--- track 21 output - input in22, //--- track 22 input - output out23, //--- track 23 output - input in24, //--- track 24 input - output out25, //--- track 25 output - input in26, //--- track 26 input - output out27, //--- track 27 output - input in28, //--- track 28 input - output out29, //--- track 29 output - output out0, //--- track 0 output - input in1, //--- track 1 input - output out2, //--- track 2 output - input in3, //--- track 3 input - output out4, //--- track 4 output - input in5, //--- track 5 input - output out6, //--- track 6 output - input in7, //--- track 7 input - output out8, //--- track 8 output - input in9, //--- track 9 input - output out10, //--- track 10 output - input in11, //--- track 11 input - output out12, //--- track 12 output - input in13, //--- track 13 input - output out14, //--- track 14 output - input in15, //--- track 15 input - output out16, //--- track 16 output - input in17, //--- track 17 input - output out18, //--- track 18 output - input in19, //--- track 19 input - output out20, //--- track 20 output - input in21, //--- track 21 input - output out22, //--- track 22 output - input in23, //--- track 23 input - output out24, //--- track 24 output - input in25, //--- track 25 input - output out26, //--- track 26 output - input in27, //--- track 27 input - output out28, //--- track 28 output - input in29, //--- track 29 input - output mid_out0, // Middle output 0 to logic blocks - output mid_out1, // Middle output 1 to logic blocks - output mid_out2, // Middle output 2 to logic blocks - output mid_out3, // Middle output 3 to logic blocks - output mid_out4, // Middle output 4 to logic blocks - output mid_out5, // Middle output 5 to logic blocks - output mid_out6, // Middle output 6 to logic blocks - output mid_out7, // Middle output 7 to logic blocks - output mid_out8, // Middle output 8 to logic blocks - output mid_out9, // Middle output 9 to logic blocks - output mid_out10, // Middle output 10 to logic blocks - output mid_out11, // Middle output 11 to logic blocks - output mid_out12, // Middle output 12 to logic blocks - output mid_out13, // Middle output 13 to logic blocks - output mid_out14, // Middle output 14 to logic blocks - output mid_out15, // Middle output 15 to logic blocks - output mid_out16, // Middle output 16 to logic blocks - output mid_out17, // Middle output 17 to logic blocks - output mid_out18, // Middle output 18 to logic blocks - output mid_out19, // Middle output 19 to logic blocks - output mid_out20, // Middle output 20 to logic blocks - output mid_out21, // Middle output 21 to logic blocks - output mid_out22, // Middle output 22 to logic blocks - output mid_out23, // Middle output 23 to logic blocks - output mid_out24, // Middle output 24 to logic blocks - output mid_out25, // Middle output 25 to logic blocks - output mid_out26, // Middle output 26 to logic blocks - output mid_out27, // Middle output 27 to logic blocks - output mid_out28, // Middle output 28 to logic blocks - output mid_out29 // Middle output 29 to logic blocks - ); -assign out0 = in0; -assign mid_out0 = in0; -assign out1 = in1; -assign mid_out1 = in1; -assign out2 = in2; -assign mid_out2 = in2; -assign out3 = in3; -assign mid_out3 = in3; -assign out4 = in4; -assign mid_out4 = in4; -assign out5 = in5; -assign mid_out5 = in5; -assign out6 = in6; -assign mid_out6 = in6; -assign out7 = in7; -assign mid_out7 = in7; -assign out8 = in8; -assign mid_out8 = in8; -assign out9 = in9; -assign mid_out9 = in9; -assign out10 = in10; -assign mid_out10 = in10; -assign out11 = in11; -assign mid_out11 = in11; -assign out12 = in12; -assign mid_out12 = in12; -assign out13 = in13; -assign mid_out13 = in13; -assign out14 = in14; -assign mid_out14 = in14; -assign out15 = in15; -assign mid_out15 = in15; -assign out16 = in16; -assign mid_out16 = in16; -assign out17 = in17; -assign mid_out17 = in17; -assign out18 = in18; -assign mid_out18 = in18; -assign out19 = in19; -assign mid_out19 = in19; -assign out20 = in20; -assign mid_out20 = in20; -assign out21 = in21; -assign mid_out21 = in21; -assign out22 = in22; -assign mid_out22 = in22; -assign out23 = in23; -assign mid_out23 = in23; -assign out24 = in24; -assign mid_out24 = in24; -assign out25 = in25; -assign mid_out25 = in25; -assign out26 = in26; -assign mid_out26 = in26; -assign out27 = in27; -assign mid_out27 = in27; -assign out28 = in28; -assign mid_out28 = in28; -assign out29 = in29; -assign mid_out29 = in29; -endmodule -//----- END Verilog Module of Channel X [1][1] ----- - diff --git a/examples/verilog_test_example_1/routing/chany_0_1.v b/examples/verilog_test_example_1/routing/chany_0_1.v deleted file mode 100644 index 936f919d4..000000000 --- a/examples/verilog_test_example_1/routing/chany_0_1.v +++ /dev/null @@ -1,175 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Routing Channel - Y direction [0][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module Channel Y [0][1] ----- -module chany_0__1_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, - input in0, //--- track 0 input - output out1, //--- track 1 output - input in2, //--- track 2 input - output out3, //--- track 3 output - input in4, //--- track 4 input - output out5, //--- track 5 output - input in6, //--- track 6 input - output out7, //--- track 7 output - input in8, //--- track 8 input - output out9, //--- track 9 output - input in10, //--- track 10 input - output out11, //--- track 11 output - input in12, //--- track 12 input - output out13, //--- track 13 output - input in14, //--- track 14 input - output out15, //--- track 15 output - input in16, //--- track 16 input - output out17, //--- track 17 output - input in18, //--- track 18 input - output out19, //--- track 19 output - input in20, //--- track 20 input - output out21, //--- track 21 output - input in22, //--- track 22 input - output out23, //--- track 23 output - input in24, //--- track 24 input - output out25, //--- track 25 output - input in26, //--- track 26 input - output out27, //--- track 27 output - input in28, //--- track 28 input - output out29, //--- track 29 output - output out0, //--- track 0 output - input in1, //--- track 1 input - output out2, //--- track 2 output - input in3, //--- track 3 input - output out4, //--- track 4 output - input in5, //--- track 5 input - output out6, //--- track 6 output - input in7, //--- track 7 input - output out8, //--- track 8 output - input in9, //--- track 9 input - output out10, //--- track 10 output - input in11, //--- track 11 input - output out12, //--- track 12 output - input in13, //--- track 13 input - output out14, //--- track 14 output - input in15, //--- track 15 input - output out16, //--- track 16 output - input in17, //--- track 17 input - output out18, //--- track 18 output - input in19, //--- track 19 input - output out20, //--- track 20 output - input in21, //--- track 21 input - output out22, //--- track 22 output - input in23, //--- track 23 input - output out24, //--- track 24 output - input in25, //--- track 25 input - output out26, //--- track 26 output - input in27, //--- track 27 input - output out28, //--- track 28 output - input in29, //--- track 29 input - output mid_out0, // Middle output 0 to logic blocks - output mid_out1, // Middle output 1 to logic blocks - output mid_out2, // Middle output 2 to logic blocks - output mid_out3, // Middle output 3 to logic blocks - output mid_out4, // Middle output 4 to logic blocks - output mid_out5, // Middle output 5 to logic blocks - output mid_out6, // Middle output 6 to logic blocks - output mid_out7, // Middle output 7 to logic blocks - output mid_out8, // Middle output 8 to logic blocks - output mid_out9, // Middle output 9 to logic blocks - output mid_out10, // Middle output 10 to logic blocks - output mid_out11, // Middle output 11 to logic blocks - output mid_out12, // Middle output 12 to logic blocks - output mid_out13, // Middle output 13 to logic blocks - output mid_out14, // Middle output 14 to logic blocks - output mid_out15, // Middle output 15 to logic blocks - output mid_out16, // Middle output 16 to logic blocks - output mid_out17, // Middle output 17 to logic blocks - output mid_out18, // Middle output 18 to logic blocks - output mid_out19, // Middle output 19 to logic blocks - output mid_out20, // Middle output 20 to logic blocks - output mid_out21, // Middle output 21 to logic blocks - output mid_out22, // Middle output 22 to logic blocks - output mid_out23, // Middle output 23 to logic blocks - output mid_out24, // Middle output 24 to logic blocks - output mid_out25, // Middle output 25 to logic blocks - output mid_out26, // Middle output 26 to logic blocks - output mid_out27, // Middle output 27 to logic blocks - output mid_out28, // Middle output 28 to logic blocks - output mid_out29 // Middle output 29 to logic blocks - ); -assign out0 = in0; -assign mid_out0 = in0; -assign out1 = in1; -assign mid_out1 = in1; -assign out2 = in2; -assign mid_out2 = in2; -assign out3 = in3; -assign mid_out3 = in3; -assign out4 = in4; -assign mid_out4 = in4; -assign out5 = in5; -assign mid_out5 = in5; -assign out6 = in6; -assign mid_out6 = in6; -assign out7 = in7; -assign mid_out7 = in7; -assign out8 = in8; -assign mid_out8 = in8; -assign out9 = in9; -assign mid_out9 = in9; -assign out10 = in10; -assign mid_out10 = in10; -assign out11 = in11; -assign mid_out11 = in11; -assign out12 = in12; -assign mid_out12 = in12; -assign out13 = in13; -assign mid_out13 = in13; -assign out14 = in14; -assign mid_out14 = in14; -assign out15 = in15; -assign mid_out15 = in15; -assign out16 = in16; -assign mid_out16 = in16; -assign out17 = in17; -assign mid_out17 = in17; -assign out18 = in18; -assign mid_out18 = in18; -assign out19 = in19; -assign mid_out19 = in19; -assign out20 = in20; -assign mid_out20 = in20; -assign out21 = in21; -assign mid_out21 = in21; -assign out22 = in22; -assign mid_out22 = in22; -assign out23 = in23; -assign mid_out23 = in23; -assign out24 = in24; -assign mid_out24 = in24; -assign out25 = in25; -assign mid_out25 = in25; -assign out26 = in26; -assign mid_out26 = in26; -assign out27 = in27; -assign mid_out27 = in27; -assign out28 = in28; -assign mid_out28 = in28; -assign out29 = in29; -assign mid_out29 = in29; -endmodule -//----- END Verilog Module of Channel Y [0][1] ----- - diff --git a/examples/verilog_test_example_1/routing/chany_1_1.v b/examples/verilog_test_example_1/routing/chany_1_1.v deleted file mode 100644 index 44789628a..000000000 --- a/examples/verilog_test_example_1/routing/chany_1_1.v +++ /dev/null @@ -1,175 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Routing Channel - Y direction [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module Channel Y [1][1] ----- -module chany_1__1_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, - input in0, //--- track 0 input - output out1, //--- track 1 output - input in2, //--- track 2 input - output out3, //--- track 3 output - input in4, //--- track 4 input - output out5, //--- track 5 output - input in6, //--- track 6 input - output out7, //--- track 7 output - input in8, //--- track 8 input - output out9, //--- track 9 output - input in10, //--- track 10 input - output out11, //--- track 11 output - input in12, //--- track 12 input - output out13, //--- track 13 output - input in14, //--- track 14 input - output out15, //--- track 15 output - input in16, //--- track 16 input - output out17, //--- track 17 output - input in18, //--- track 18 input - output out19, //--- track 19 output - input in20, //--- track 20 input - output out21, //--- track 21 output - input in22, //--- track 22 input - output out23, //--- track 23 output - input in24, //--- track 24 input - output out25, //--- track 25 output - input in26, //--- track 26 input - output out27, //--- track 27 output - input in28, //--- track 28 input - output out29, //--- track 29 output - output out0, //--- track 0 output - input in1, //--- track 1 input - output out2, //--- track 2 output - input in3, //--- track 3 input - output out4, //--- track 4 output - input in5, //--- track 5 input - output out6, //--- track 6 output - input in7, //--- track 7 input - output out8, //--- track 8 output - input in9, //--- track 9 input - output out10, //--- track 10 output - input in11, //--- track 11 input - output out12, //--- track 12 output - input in13, //--- track 13 input - output out14, //--- track 14 output - input in15, //--- track 15 input - output out16, //--- track 16 output - input in17, //--- track 17 input - output out18, //--- track 18 output - input in19, //--- track 19 input - output out20, //--- track 20 output - input in21, //--- track 21 input - output out22, //--- track 22 output - input in23, //--- track 23 input - output out24, //--- track 24 output - input in25, //--- track 25 input - output out26, //--- track 26 output - input in27, //--- track 27 input - output out28, //--- track 28 output - input in29, //--- track 29 input - output mid_out0, // Middle output 0 to logic blocks - output mid_out1, // Middle output 1 to logic blocks - output mid_out2, // Middle output 2 to logic blocks - output mid_out3, // Middle output 3 to logic blocks - output mid_out4, // Middle output 4 to logic blocks - output mid_out5, // Middle output 5 to logic blocks - output mid_out6, // Middle output 6 to logic blocks - output mid_out7, // Middle output 7 to logic blocks - output mid_out8, // Middle output 8 to logic blocks - output mid_out9, // Middle output 9 to logic blocks - output mid_out10, // Middle output 10 to logic blocks - output mid_out11, // Middle output 11 to logic blocks - output mid_out12, // Middle output 12 to logic blocks - output mid_out13, // Middle output 13 to logic blocks - output mid_out14, // Middle output 14 to logic blocks - output mid_out15, // Middle output 15 to logic blocks - output mid_out16, // Middle output 16 to logic blocks - output mid_out17, // Middle output 17 to logic blocks - output mid_out18, // Middle output 18 to logic blocks - output mid_out19, // Middle output 19 to logic blocks - output mid_out20, // Middle output 20 to logic blocks - output mid_out21, // Middle output 21 to logic blocks - output mid_out22, // Middle output 22 to logic blocks - output mid_out23, // Middle output 23 to logic blocks - output mid_out24, // Middle output 24 to logic blocks - output mid_out25, // Middle output 25 to logic blocks - output mid_out26, // Middle output 26 to logic blocks - output mid_out27, // Middle output 27 to logic blocks - output mid_out28, // Middle output 28 to logic blocks - output mid_out29 // Middle output 29 to logic blocks - ); -assign out0 = in0; -assign mid_out0 = in0; -assign out1 = in1; -assign mid_out1 = in1; -assign out2 = in2; -assign mid_out2 = in2; -assign out3 = in3; -assign mid_out3 = in3; -assign out4 = in4; -assign mid_out4 = in4; -assign out5 = in5; -assign mid_out5 = in5; -assign out6 = in6; -assign mid_out6 = in6; -assign out7 = in7; -assign mid_out7 = in7; -assign out8 = in8; -assign mid_out8 = in8; -assign out9 = in9; -assign mid_out9 = in9; -assign out10 = in10; -assign mid_out10 = in10; -assign out11 = in11; -assign mid_out11 = in11; -assign out12 = in12; -assign mid_out12 = in12; -assign out13 = in13; -assign mid_out13 = in13; -assign out14 = in14; -assign mid_out14 = in14; -assign out15 = in15; -assign mid_out15 = in15; -assign out16 = in16; -assign mid_out16 = in16; -assign out17 = in17; -assign mid_out17 = in17; -assign out18 = in18; -assign mid_out18 = in18; -assign out19 = in19; -assign mid_out19 = in19; -assign out20 = in20; -assign mid_out20 = in20; -assign out21 = in21; -assign mid_out21 = in21; -assign out22 = in22; -assign mid_out22 = in22; -assign out23 = in23; -assign mid_out23 = in23; -assign out24 = in24; -assign mid_out24 = in24; -assign out25 = in25; -assign mid_out25 = in25; -assign out26 = in26; -assign mid_out26 = in26; -assign out27 = in27; -assign mid_out27 = in27; -assign out28 = in28; -assign mid_out28 = in28; -assign out29 = in29; -assign mid_out29 = in29; -endmodule -//----- END Verilog Module of Channel Y [1][1] ----- - diff --git a/examples/verilog_test_example_1/routing/routing.v b/examples/verilog_test_example_1/routing/routing.v deleted file mode 100644 index f227fa42a..000000000 --- a/examples/verilog_test_example_1/routing/routing.v +++ /dev/null @@ -1,23 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Header file -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -`include "./verilog_test_example_1/routing/cby_1_1.v" -`include "./verilog_test_example_1/routing/cby_0_1.v" -`include "./verilog_test_example_1/routing/cbx_1_1.v" -`include "./verilog_test_example_1/routing/cbx_1_0.v" -`include "./verilog_test_example_1/routing/sb_1_1.v" -`include "./verilog_test_example_1/routing/sb_1_0.v" -`include "./verilog_test_example_1/routing/sb_0_1.v" -`include "./verilog_test_example_1/routing/sb_0_0.v" -`include "./verilog_test_example_1/routing/chany_1_1.v" -`include "./verilog_test_example_1/routing/chany_0_1.v" -`include "./verilog_test_example_1/routing/chanx_1_1.v" -`include "./verilog_test_example_1/routing/chanx_1_0.v" diff --git a/examples/verilog_test_example_1/routing/sb_0_0.v b/examples/verilog_test_example_1/routing/sb_0_0.v deleted file mode 100644 index caf58ca9e..000000000 --- a/examples/verilog_test_example_1/routing/sb_0_0.v +++ /dev/null @@ -1,627 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Switch Block [0][0] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Switch Box[0][0] ----- -module sb_0__0_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -//----- Inputs/outputs of top side ----- - output chany_0__1__out_0_, - input chany_0__1__in_1_, - output chany_0__1__out_2_, - input chany_0__1__in_3_, - output chany_0__1__out_4_, - input chany_0__1__in_5_, - output chany_0__1__out_6_, - input chany_0__1__in_7_, - output chany_0__1__out_8_, - input chany_0__1__in_9_, - output chany_0__1__out_10_, - input chany_0__1__in_11_, - output chany_0__1__out_12_, - input chany_0__1__in_13_, - output chany_0__1__out_14_, - input chany_0__1__in_15_, - output chany_0__1__out_16_, - input chany_0__1__in_17_, - output chany_0__1__out_18_, - input chany_0__1__in_19_, - output chany_0__1__out_20_, - input chany_0__1__in_21_, - output chany_0__1__out_22_, - input chany_0__1__in_23_, - output chany_0__1__out_24_, - input chany_0__1__in_25_, - output chany_0__1__out_26_, - input chany_0__1__in_27_, - output chany_0__1__out_28_, - input chany_0__1__in_29_, -input grid_0__1__pin_0__1__1_, -input grid_0__1__pin_0__1__3_, -input grid_0__1__pin_0__1__5_, -input grid_0__1__pin_0__1__7_, -input grid_0__1__pin_0__1__9_, -input grid_0__1__pin_0__1__11_, -input grid_0__1__pin_0__1__13_, -input grid_0__1__pin_0__1__15_, -//----- Inputs/outputs of right side ----- - output chanx_1__0__out_0_, - input chanx_1__0__in_1_, - output chanx_1__0__out_2_, - input chanx_1__0__in_3_, - output chanx_1__0__out_4_, - input chanx_1__0__in_5_, - output chanx_1__0__out_6_, - input chanx_1__0__in_7_, - output chanx_1__0__out_8_, - input chanx_1__0__in_9_, - output chanx_1__0__out_10_, - input chanx_1__0__in_11_, - output chanx_1__0__out_12_, - input chanx_1__0__in_13_, - output chanx_1__0__out_14_, - input chanx_1__0__in_15_, - output chanx_1__0__out_16_, - input chanx_1__0__in_17_, - output chanx_1__0__out_18_, - input chanx_1__0__in_19_, - output chanx_1__0__out_20_, - input chanx_1__0__in_21_, - output chanx_1__0__out_22_, - input chanx_1__0__in_23_, - output chanx_1__0__out_24_, - input chanx_1__0__in_25_, - output chanx_1__0__out_26_, - input chanx_1__0__in_27_, - output chanx_1__0__out_28_, - input chanx_1__0__in_29_, -input grid_1__0__pin_0__0__1_, -input grid_1__0__pin_0__0__3_, -input grid_1__0__pin_0__0__5_, -input grid_1__0__pin_0__0__7_, -input grid_1__0__pin_0__0__9_, -input grid_1__0__pin_0__0__11_, -input grid_1__0__pin_0__0__13_, -input grid_1__0__pin_0__0__15_, -//----- Inputs/outputs of bottom side ----- -//----- Inputs/outputs of left side ----- -input [0:33] sram_blwl_bl , -input [0:33] sram_blwl_wl , -input [0:33] sram_blwl_blb ); -//----- top side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_0_inbus; -assign mux_1level_tapbuf_size3_0_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size3_0_inbus[1] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size3_0_inbus[2] = chanx_1__0__in_3_ ; -wire [0:2] mux_1level_tapbuf_size3_0_configbus0; -wire [0:2] mux_1level_tapbuf_size3_0_configbus1; -wire [0:2] mux_1level_tapbuf_size3_0_sram_blwl_out ; -wire [0:2] mux_1level_tapbuf_size3_0_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_0_configbus0[0:2] = sram_blwl_bl[0:2] ; -assign mux_1level_tapbuf_size3_0_configbus1[0:2] = sram_blwl_wl[0:2] ; -wire [0:2] mux_1level_tapbuf_size3_0_configbus0_b; -assign mux_1level_tapbuf_size3_0_configbus0_b[0:2] = sram_blwl_blb[0:2] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_0_ (mux_1level_tapbuf_size3_0_inbus, chany_0__1__out_0_ , mux_1level_tapbuf_size3_0_sram_blwl_out[0:2] , -mux_1level_tapbuf_size3_0_sram_blwl_outb[0:2] ); -//----- SRAM bits for MUX[0], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_0_ (mux_1level_tapbuf_size3_0_sram_blwl_out[0:0] ,mux_1level_tapbuf_size3_0_sram_blwl_out[0:0] ,mux_1level_tapbuf_size3_0_sram_blwl_outb[0:0] ,mux_1level_tapbuf_size3_0_configbus0[0:0], mux_1level_tapbuf_size3_0_configbus1[0:0] , mux_1level_tapbuf_size3_0_configbus0_b[0:0] ); -sram6T_blwl sram_blwl_1_ (mux_1level_tapbuf_size3_0_sram_blwl_out[1:1] ,mux_1level_tapbuf_size3_0_sram_blwl_out[1:1] ,mux_1level_tapbuf_size3_0_sram_blwl_outb[1:1] ,mux_1level_tapbuf_size3_0_configbus0[1:1], mux_1level_tapbuf_size3_0_configbus1[1:1] , mux_1level_tapbuf_size3_0_configbus0_b[1:1] ); -sram6T_blwl sram_blwl_2_ (mux_1level_tapbuf_size3_0_sram_blwl_out[2:2] ,mux_1level_tapbuf_size3_0_sram_blwl_out[2:2] ,mux_1level_tapbuf_size3_0_sram_blwl_outb[2:2] ,mux_1level_tapbuf_size3_0_configbus0[2:2], mux_1level_tapbuf_size3_0_configbus1[2:2] , mux_1level_tapbuf_size3_0_configbus0_b[2:2] ); -wire [0:1] mux_1level_tapbuf_size2_1_inbus; -assign mux_1level_tapbuf_size2_1_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_1_inbus[1] = chanx_1__0__in_5_ ; -wire [3:3] mux_1level_tapbuf_size2_1_configbus0; -wire [3:3] mux_1level_tapbuf_size2_1_configbus1; -wire [3:3] mux_1level_tapbuf_size2_1_sram_blwl_out ; -wire [3:3] mux_1level_tapbuf_size2_1_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_1_configbus0[3:3] = sram_blwl_bl[3:3] ; -assign mux_1level_tapbuf_size2_1_configbus1[3:3] = sram_blwl_wl[3:3] ; -wire [3:3] mux_1level_tapbuf_size2_1_configbus0_b; -assign mux_1level_tapbuf_size2_1_configbus0_b[3:3] = sram_blwl_blb[3:3] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_1_ (mux_1level_tapbuf_size2_1_inbus, chany_0__1__out_2_ , mux_1level_tapbuf_size2_1_sram_blwl_out[3:3] , -mux_1level_tapbuf_size2_1_sram_blwl_outb[3:3] ); -//----- SRAM bits for MUX[1], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_3_ (mux_1level_tapbuf_size2_1_sram_blwl_out[3:3] ,mux_1level_tapbuf_size2_1_sram_blwl_out[3:3] ,mux_1level_tapbuf_size2_1_sram_blwl_outb[3:3] ,mux_1level_tapbuf_size2_1_configbus0[3:3], mux_1level_tapbuf_size2_1_configbus1[3:3] , mux_1level_tapbuf_size2_1_configbus0_b[3:3] ); -wire [0:1] mux_1level_tapbuf_size2_2_inbus; -assign mux_1level_tapbuf_size2_2_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_2_inbus[1] = chanx_1__0__in_7_ ; -wire [4:4] mux_1level_tapbuf_size2_2_configbus0; -wire [4:4] mux_1level_tapbuf_size2_2_configbus1; -wire [4:4] mux_1level_tapbuf_size2_2_sram_blwl_out ; -wire [4:4] mux_1level_tapbuf_size2_2_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_2_configbus0[4:4] = sram_blwl_bl[4:4] ; -assign mux_1level_tapbuf_size2_2_configbus1[4:4] = sram_blwl_wl[4:4] ; -wire [4:4] mux_1level_tapbuf_size2_2_configbus0_b; -assign mux_1level_tapbuf_size2_2_configbus0_b[4:4] = sram_blwl_blb[4:4] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_2_ (mux_1level_tapbuf_size2_2_inbus, chany_0__1__out_4_ , mux_1level_tapbuf_size2_2_sram_blwl_out[4:4] , -mux_1level_tapbuf_size2_2_sram_blwl_outb[4:4] ); -//----- SRAM bits for MUX[2], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_4_ (mux_1level_tapbuf_size2_2_sram_blwl_out[4:4] ,mux_1level_tapbuf_size2_2_sram_blwl_out[4:4] ,mux_1level_tapbuf_size2_2_sram_blwl_outb[4:4] ,mux_1level_tapbuf_size2_2_configbus0[4:4], mux_1level_tapbuf_size2_2_configbus1[4:4] , mux_1level_tapbuf_size2_2_configbus0_b[4:4] ); -wire [0:1] mux_1level_tapbuf_size2_3_inbus; -assign mux_1level_tapbuf_size2_3_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_3_inbus[1] = chanx_1__0__in_9_ ; -wire [5:5] mux_1level_tapbuf_size2_3_configbus0; -wire [5:5] mux_1level_tapbuf_size2_3_configbus1; -wire [5:5] mux_1level_tapbuf_size2_3_sram_blwl_out ; -wire [5:5] mux_1level_tapbuf_size2_3_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_3_configbus0[5:5] = sram_blwl_bl[5:5] ; -assign mux_1level_tapbuf_size2_3_configbus1[5:5] = sram_blwl_wl[5:5] ; -wire [5:5] mux_1level_tapbuf_size2_3_configbus0_b; -assign mux_1level_tapbuf_size2_3_configbus0_b[5:5] = sram_blwl_blb[5:5] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_3_ (mux_1level_tapbuf_size2_3_inbus, chany_0__1__out_6_ , mux_1level_tapbuf_size2_3_sram_blwl_out[5:5] , -mux_1level_tapbuf_size2_3_sram_blwl_outb[5:5] ); -//----- SRAM bits for MUX[3], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_5_ (mux_1level_tapbuf_size2_3_sram_blwl_out[5:5] ,mux_1level_tapbuf_size2_3_sram_blwl_out[5:5] ,mux_1level_tapbuf_size2_3_sram_blwl_outb[5:5] ,mux_1level_tapbuf_size2_3_configbus0[5:5], mux_1level_tapbuf_size2_3_configbus1[5:5] , mux_1level_tapbuf_size2_3_configbus0_b[5:5] ); -wire [0:1] mux_1level_tapbuf_size2_4_inbus; -assign mux_1level_tapbuf_size2_4_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_4_inbus[1] = chanx_1__0__in_11_ ; -wire [6:6] mux_1level_tapbuf_size2_4_configbus0; -wire [6:6] mux_1level_tapbuf_size2_4_configbus1; -wire [6:6] mux_1level_tapbuf_size2_4_sram_blwl_out ; -wire [6:6] mux_1level_tapbuf_size2_4_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_4_configbus0[6:6] = sram_blwl_bl[6:6] ; -assign mux_1level_tapbuf_size2_4_configbus1[6:6] = sram_blwl_wl[6:6] ; -wire [6:6] mux_1level_tapbuf_size2_4_configbus0_b; -assign mux_1level_tapbuf_size2_4_configbus0_b[6:6] = sram_blwl_blb[6:6] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_4_ (mux_1level_tapbuf_size2_4_inbus, chany_0__1__out_8_ , mux_1level_tapbuf_size2_4_sram_blwl_out[6:6] , -mux_1level_tapbuf_size2_4_sram_blwl_outb[6:6] ); -//----- SRAM bits for MUX[4], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_6_ (mux_1level_tapbuf_size2_4_sram_blwl_out[6:6] ,mux_1level_tapbuf_size2_4_sram_blwl_out[6:6] ,mux_1level_tapbuf_size2_4_sram_blwl_outb[6:6] ,mux_1level_tapbuf_size2_4_configbus0[6:6], mux_1level_tapbuf_size2_4_configbus1[6:6] , mux_1level_tapbuf_size2_4_configbus0_b[6:6] ); -wire [0:1] mux_1level_tapbuf_size2_5_inbus; -assign mux_1level_tapbuf_size2_5_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_5_inbus[1] = chanx_1__0__in_13_ ; -wire [7:7] mux_1level_tapbuf_size2_5_configbus0; -wire [7:7] mux_1level_tapbuf_size2_5_configbus1; -wire [7:7] mux_1level_tapbuf_size2_5_sram_blwl_out ; -wire [7:7] mux_1level_tapbuf_size2_5_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_5_configbus0[7:7] = sram_blwl_bl[7:7] ; -assign mux_1level_tapbuf_size2_5_configbus1[7:7] = sram_blwl_wl[7:7] ; -wire [7:7] mux_1level_tapbuf_size2_5_configbus0_b; -assign mux_1level_tapbuf_size2_5_configbus0_b[7:7] = sram_blwl_blb[7:7] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_5_ (mux_1level_tapbuf_size2_5_inbus, chany_0__1__out_10_ , mux_1level_tapbuf_size2_5_sram_blwl_out[7:7] , -mux_1level_tapbuf_size2_5_sram_blwl_outb[7:7] ); -//----- SRAM bits for MUX[5], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_7_ (mux_1level_tapbuf_size2_5_sram_blwl_out[7:7] ,mux_1level_tapbuf_size2_5_sram_blwl_out[7:7] ,mux_1level_tapbuf_size2_5_sram_blwl_outb[7:7] ,mux_1level_tapbuf_size2_5_configbus0[7:7], mux_1level_tapbuf_size2_5_configbus1[7:7] , mux_1level_tapbuf_size2_5_configbus0_b[7:7] ); -wire [0:1] mux_1level_tapbuf_size2_6_inbus; -assign mux_1level_tapbuf_size2_6_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_6_inbus[1] = chanx_1__0__in_15_ ; -wire [8:8] mux_1level_tapbuf_size2_6_configbus0; -wire [8:8] mux_1level_tapbuf_size2_6_configbus1; -wire [8:8] mux_1level_tapbuf_size2_6_sram_blwl_out ; -wire [8:8] mux_1level_tapbuf_size2_6_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_6_configbus0[8:8] = sram_blwl_bl[8:8] ; -assign mux_1level_tapbuf_size2_6_configbus1[8:8] = sram_blwl_wl[8:8] ; -wire [8:8] mux_1level_tapbuf_size2_6_configbus0_b; -assign mux_1level_tapbuf_size2_6_configbus0_b[8:8] = sram_blwl_blb[8:8] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_6_ (mux_1level_tapbuf_size2_6_inbus, chany_0__1__out_12_ , mux_1level_tapbuf_size2_6_sram_blwl_out[8:8] , -mux_1level_tapbuf_size2_6_sram_blwl_outb[8:8] ); -//----- SRAM bits for MUX[6], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_8_ (mux_1level_tapbuf_size2_6_sram_blwl_out[8:8] ,mux_1level_tapbuf_size2_6_sram_blwl_out[8:8] ,mux_1level_tapbuf_size2_6_sram_blwl_outb[8:8] ,mux_1level_tapbuf_size2_6_configbus0[8:8], mux_1level_tapbuf_size2_6_configbus1[8:8] , mux_1level_tapbuf_size2_6_configbus0_b[8:8] ); -wire [0:1] mux_1level_tapbuf_size2_7_inbus; -assign mux_1level_tapbuf_size2_7_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_7_inbus[1] = chanx_1__0__in_17_ ; -wire [9:9] mux_1level_tapbuf_size2_7_configbus0; -wire [9:9] mux_1level_tapbuf_size2_7_configbus1; -wire [9:9] mux_1level_tapbuf_size2_7_sram_blwl_out ; -wire [9:9] mux_1level_tapbuf_size2_7_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_7_configbus0[9:9] = sram_blwl_bl[9:9] ; -assign mux_1level_tapbuf_size2_7_configbus1[9:9] = sram_blwl_wl[9:9] ; -wire [9:9] mux_1level_tapbuf_size2_7_configbus0_b; -assign mux_1level_tapbuf_size2_7_configbus0_b[9:9] = sram_blwl_blb[9:9] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_7_ (mux_1level_tapbuf_size2_7_inbus, chany_0__1__out_14_ , mux_1level_tapbuf_size2_7_sram_blwl_out[9:9] , -mux_1level_tapbuf_size2_7_sram_blwl_outb[9:9] ); -//----- SRAM bits for MUX[7], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_9_ (mux_1level_tapbuf_size2_7_sram_blwl_out[9:9] ,mux_1level_tapbuf_size2_7_sram_blwl_out[9:9] ,mux_1level_tapbuf_size2_7_sram_blwl_outb[9:9] ,mux_1level_tapbuf_size2_7_configbus0[9:9], mux_1level_tapbuf_size2_7_configbus1[9:9] , mux_1level_tapbuf_size2_7_configbus0_b[9:9] ); -wire [0:1] mux_1level_tapbuf_size2_8_inbus; -assign mux_1level_tapbuf_size2_8_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_8_inbus[1] = chanx_1__0__in_19_ ; -wire [10:10] mux_1level_tapbuf_size2_8_configbus0; -wire [10:10] mux_1level_tapbuf_size2_8_configbus1; -wire [10:10] mux_1level_tapbuf_size2_8_sram_blwl_out ; -wire [10:10] mux_1level_tapbuf_size2_8_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_8_configbus0[10:10] = sram_blwl_bl[10:10] ; -assign mux_1level_tapbuf_size2_8_configbus1[10:10] = sram_blwl_wl[10:10] ; -wire [10:10] mux_1level_tapbuf_size2_8_configbus0_b; -assign mux_1level_tapbuf_size2_8_configbus0_b[10:10] = sram_blwl_blb[10:10] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_8_ (mux_1level_tapbuf_size2_8_inbus, chany_0__1__out_16_ , mux_1level_tapbuf_size2_8_sram_blwl_out[10:10] , -mux_1level_tapbuf_size2_8_sram_blwl_outb[10:10] ); -//----- SRAM bits for MUX[8], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_10_ (mux_1level_tapbuf_size2_8_sram_blwl_out[10:10] ,mux_1level_tapbuf_size2_8_sram_blwl_out[10:10] ,mux_1level_tapbuf_size2_8_sram_blwl_outb[10:10] ,mux_1level_tapbuf_size2_8_configbus0[10:10], mux_1level_tapbuf_size2_8_configbus1[10:10] , mux_1level_tapbuf_size2_8_configbus0_b[10:10] ); -wire [0:1] mux_1level_tapbuf_size2_9_inbus; -assign mux_1level_tapbuf_size2_9_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_9_inbus[1] = chanx_1__0__in_21_ ; -wire [11:11] mux_1level_tapbuf_size2_9_configbus0; -wire [11:11] mux_1level_tapbuf_size2_9_configbus1; -wire [11:11] mux_1level_tapbuf_size2_9_sram_blwl_out ; -wire [11:11] mux_1level_tapbuf_size2_9_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_9_configbus0[11:11] = sram_blwl_bl[11:11] ; -assign mux_1level_tapbuf_size2_9_configbus1[11:11] = sram_blwl_wl[11:11] ; -wire [11:11] mux_1level_tapbuf_size2_9_configbus0_b; -assign mux_1level_tapbuf_size2_9_configbus0_b[11:11] = sram_blwl_blb[11:11] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_9_ (mux_1level_tapbuf_size2_9_inbus, chany_0__1__out_18_ , mux_1level_tapbuf_size2_9_sram_blwl_out[11:11] , -mux_1level_tapbuf_size2_9_sram_blwl_outb[11:11] ); -//----- SRAM bits for MUX[9], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_11_ (mux_1level_tapbuf_size2_9_sram_blwl_out[11:11] ,mux_1level_tapbuf_size2_9_sram_blwl_out[11:11] ,mux_1level_tapbuf_size2_9_sram_blwl_outb[11:11] ,mux_1level_tapbuf_size2_9_configbus0[11:11], mux_1level_tapbuf_size2_9_configbus1[11:11] , mux_1level_tapbuf_size2_9_configbus0_b[11:11] ); -wire [0:1] mux_1level_tapbuf_size2_10_inbus; -assign mux_1level_tapbuf_size2_10_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_10_inbus[1] = chanx_1__0__in_23_ ; -wire [12:12] mux_1level_tapbuf_size2_10_configbus0; -wire [12:12] mux_1level_tapbuf_size2_10_configbus1; -wire [12:12] mux_1level_tapbuf_size2_10_sram_blwl_out ; -wire [12:12] mux_1level_tapbuf_size2_10_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_10_configbus0[12:12] = sram_blwl_bl[12:12] ; -assign mux_1level_tapbuf_size2_10_configbus1[12:12] = sram_blwl_wl[12:12] ; -wire [12:12] mux_1level_tapbuf_size2_10_configbus0_b; -assign mux_1level_tapbuf_size2_10_configbus0_b[12:12] = sram_blwl_blb[12:12] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_10_ (mux_1level_tapbuf_size2_10_inbus, chany_0__1__out_20_ , mux_1level_tapbuf_size2_10_sram_blwl_out[12:12] , -mux_1level_tapbuf_size2_10_sram_blwl_outb[12:12] ); -//----- SRAM bits for MUX[10], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_12_ (mux_1level_tapbuf_size2_10_sram_blwl_out[12:12] ,mux_1level_tapbuf_size2_10_sram_blwl_out[12:12] ,mux_1level_tapbuf_size2_10_sram_blwl_outb[12:12] ,mux_1level_tapbuf_size2_10_configbus0[12:12], mux_1level_tapbuf_size2_10_configbus1[12:12] , mux_1level_tapbuf_size2_10_configbus0_b[12:12] ); -wire [0:1] mux_1level_tapbuf_size2_11_inbus; -assign mux_1level_tapbuf_size2_11_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_11_inbus[1] = chanx_1__0__in_25_ ; -wire [13:13] mux_1level_tapbuf_size2_11_configbus0; -wire [13:13] mux_1level_tapbuf_size2_11_configbus1; -wire [13:13] mux_1level_tapbuf_size2_11_sram_blwl_out ; -wire [13:13] mux_1level_tapbuf_size2_11_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_11_configbus0[13:13] = sram_blwl_bl[13:13] ; -assign mux_1level_tapbuf_size2_11_configbus1[13:13] = sram_blwl_wl[13:13] ; -wire [13:13] mux_1level_tapbuf_size2_11_configbus0_b; -assign mux_1level_tapbuf_size2_11_configbus0_b[13:13] = sram_blwl_blb[13:13] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_11_ (mux_1level_tapbuf_size2_11_inbus, chany_0__1__out_22_ , mux_1level_tapbuf_size2_11_sram_blwl_out[13:13] , -mux_1level_tapbuf_size2_11_sram_blwl_outb[13:13] ); -//----- SRAM bits for MUX[11], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_13_ (mux_1level_tapbuf_size2_11_sram_blwl_out[13:13] ,mux_1level_tapbuf_size2_11_sram_blwl_out[13:13] ,mux_1level_tapbuf_size2_11_sram_blwl_outb[13:13] ,mux_1level_tapbuf_size2_11_configbus0[13:13], mux_1level_tapbuf_size2_11_configbus1[13:13] , mux_1level_tapbuf_size2_11_configbus0_b[13:13] ); -wire [0:1] mux_1level_tapbuf_size2_12_inbus; -assign mux_1level_tapbuf_size2_12_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_12_inbus[1] = chanx_1__0__in_27_ ; -wire [14:14] mux_1level_tapbuf_size2_12_configbus0; -wire [14:14] mux_1level_tapbuf_size2_12_configbus1; -wire [14:14] mux_1level_tapbuf_size2_12_sram_blwl_out ; -wire [14:14] mux_1level_tapbuf_size2_12_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_12_configbus0[14:14] = sram_blwl_bl[14:14] ; -assign mux_1level_tapbuf_size2_12_configbus1[14:14] = sram_blwl_wl[14:14] ; -wire [14:14] mux_1level_tapbuf_size2_12_configbus0_b; -assign mux_1level_tapbuf_size2_12_configbus0_b[14:14] = sram_blwl_blb[14:14] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_12_ (mux_1level_tapbuf_size2_12_inbus, chany_0__1__out_24_ , mux_1level_tapbuf_size2_12_sram_blwl_out[14:14] , -mux_1level_tapbuf_size2_12_sram_blwl_outb[14:14] ); -//----- SRAM bits for MUX[12], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_14_ (mux_1level_tapbuf_size2_12_sram_blwl_out[14:14] ,mux_1level_tapbuf_size2_12_sram_blwl_out[14:14] ,mux_1level_tapbuf_size2_12_sram_blwl_outb[14:14] ,mux_1level_tapbuf_size2_12_configbus0[14:14], mux_1level_tapbuf_size2_12_configbus1[14:14] , mux_1level_tapbuf_size2_12_configbus0_b[14:14] ); -wire [0:1] mux_1level_tapbuf_size2_13_inbus; -assign mux_1level_tapbuf_size2_13_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_13_inbus[1] = chanx_1__0__in_29_ ; -wire [15:15] mux_1level_tapbuf_size2_13_configbus0; -wire [15:15] mux_1level_tapbuf_size2_13_configbus1; -wire [15:15] mux_1level_tapbuf_size2_13_sram_blwl_out ; -wire [15:15] mux_1level_tapbuf_size2_13_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_13_configbus0[15:15] = sram_blwl_bl[15:15] ; -assign mux_1level_tapbuf_size2_13_configbus1[15:15] = sram_blwl_wl[15:15] ; -wire [15:15] mux_1level_tapbuf_size2_13_configbus0_b; -assign mux_1level_tapbuf_size2_13_configbus0_b[15:15] = sram_blwl_blb[15:15] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_13_ (mux_1level_tapbuf_size2_13_inbus, chany_0__1__out_26_ , mux_1level_tapbuf_size2_13_sram_blwl_out[15:15] , -mux_1level_tapbuf_size2_13_sram_blwl_outb[15:15] ); -//----- SRAM bits for MUX[13], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_15_ (mux_1level_tapbuf_size2_13_sram_blwl_out[15:15] ,mux_1level_tapbuf_size2_13_sram_blwl_out[15:15] ,mux_1level_tapbuf_size2_13_sram_blwl_outb[15:15] ,mux_1level_tapbuf_size2_13_configbus0[15:15], mux_1level_tapbuf_size2_13_configbus1[15:15] , mux_1level_tapbuf_size2_13_configbus0_b[15:15] ); -wire [0:1] mux_1level_tapbuf_size2_14_inbus; -assign mux_1level_tapbuf_size2_14_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_14_inbus[1] = chanx_1__0__in_1_ ; -wire [16:16] mux_1level_tapbuf_size2_14_configbus0; -wire [16:16] mux_1level_tapbuf_size2_14_configbus1; -wire [16:16] mux_1level_tapbuf_size2_14_sram_blwl_out ; -wire [16:16] mux_1level_tapbuf_size2_14_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_14_configbus0[16:16] = sram_blwl_bl[16:16] ; -assign mux_1level_tapbuf_size2_14_configbus1[16:16] = sram_blwl_wl[16:16] ; -wire [16:16] mux_1level_tapbuf_size2_14_configbus0_b; -assign mux_1level_tapbuf_size2_14_configbus0_b[16:16] = sram_blwl_blb[16:16] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_14_ (mux_1level_tapbuf_size2_14_inbus, chany_0__1__out_28_ , mux_1level_tapbuf_size2_14_sram_blwl_out[16:16] , -mux_1level_tapbuf_size2_14_sram_blwl_outb[16:16] ); -//----- SRAM bits for MUX[14], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_16_ (mux_1level_tapbuf_size2_14_sram_blwl_out[16:16] ,mux_1level_tapbuf_size2_14_sram_blwl_out[16:16] ,mux_1level_tapbuf_size2_14_sram_blwl_outb[16:16] ,mux_1level_tapbuf_size2_14_configbus0[16:16], mux_1level_tapbuf_size2_14_configbus1[16:16] , mux_1level_tapbuf_size2_14_configbus0_b[16:16] ); -//----- right side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_15_inbus; -assign mux_1level_tapbuf_size3_15_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size3_15_inbus[1] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size3_15_inbus[2] = chany_0__1__in_29_ ; -wire [17:19] mux_1level_tapbuf_size3_15_configbus0; -wire [17:19] mux_1level_tapbuf_size3_15_configbus1; -wire [17:19] mux_1level_tapbuf_size3_15_sram_blwl_out ; -wire [17:19] mux_1level_tapbuf_size3_15_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_15_configbus0[17:19] = sram_blwl_bl[17:19] ; -assign mux_1level_tapbuf_size3_15_configbus1[17:19] = sram_blwl_wl[17:19] ; -wire [17:19] mux_1level_tapbuf_size3_15_configbus0_b; -assign mux_1level_tapbuf_size3_15_configbus0_b[17:19] = sram_blwl_blb[17:19] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_15_ (mux_1level_tapbuf_size3_15_inbus, chanx_1__0__out_0_ , mux_1level_tapbuf_size3_15_sram_blwl_out[17:19] , -mux_1level_tapbuf_size3_15_sram_blwl_outb[17:19] ); -//----- SRAM bits for MUX[15], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_17_ (mux_1level_tapbuf_size3_15_sram_blwl_out[17:17] ,mux_1level_tapbuf_size3_15_sram_blwl_out[17:17] ,mux_1level_tapbuf_size3_15_sram_blwl_outb[17:17] ,mux_1level_tapbuf_size3_15_configbus0[17:17], mux_1level_tapbuf_size3_15_configbus1[17:17] , mux_1level_tapbuf_size3_15_configbus0_b[17:17] ); -sram6T_blwl sram_blwl_18_ (mux_1level_tapbuf_size3_15_sram_blwl_out[18:18] ,mux_1level_tapbuf_size3_15_sram_blwl_out[18:18] ,mux_1level_tapbuf_size3_15_sram_blwl_outb[18:18] ,mux_1level_tapbuf_size3_15_configbus0[18:18], mux_1level_tapbuf_size3_15_configbus1[18:18] , mux_1level_tapbuf_size3_15_configbus0_b[18:18] ); -sram6T_blwl sram_blwl_19_ (mux_1level_tapbuf_size3_15_sram_blwl_out[19:19] ,mux_1level_tapbuf_size3_15_sram_blwl_out[19:19] ,mux_1level_tapbuf_size3_15_sram_blwl_outb[19:19] ,mux_1level_tapbuf_size3_15_configbus0[19:19], mux_1level_tapbuf_size3_15_configbus1[19:19] , mux_1level_tapbuf_size3_15_configbus0_b[19:19] ); -wire [0:1] mux_1level_tapbuf_size2_16_inbus; -assign mux_1level_tapbuf_size2_16_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_16_inbus[1] = chany_0__1__in_1_ ; -wire [20:20] mux_1level_tapbuf_size2_16_configbus0; -wire [20:20] mux_1level_tapbuf_size2_16_configbus1; -wire [20:20] mux_1level_tapbuf_size2_16_sram_blwl_out ; -wire [20:20] mux_1level_tapbuf_size2_16_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_16_configbus0[20:20] = sram_blwl_bl[20:20] ; -assign mux_1level_tapbuf_size2_16_configbus1[20:20] = sram_blwl_wl[20:20] ; -wire [20:20] mux_1level_tapbuf_size2_16_configbus0_b; -assign mux_1level_tapbuf_size2_16_configbus0_b[20:20] = sram_blwl_blb[20:20] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_16_ (mux_1level_tapbuf_size2_16_inbus, chanx_1__0__out_2_ , mux_1level_tapbuf_size2_16_sram_blwl_out[20:20] , -mux_1level_tapbuf_size2_16_sram_blwl_outb[20:20] ); -//----- SRAM bits for MUX[16], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_20_ (mux_1level_tapbuf_size2_16_sram_blwl_out[20:20] ,mux_1level_tapbuf_size2_16_sram_blwl_out[20:20] ,mux_1level_tapbuf_size2_16_sram_blwl_outb[20:20] ,mux_1level_tapbuf_size2_16_configbus0[20:20], mux_1level_tapbuf_size2_16_configbus1[20:20] , mux_1level_tapbuf_size2_16_configbus0_b[20:20] ); -wire [0:1] mux_1level_tapbuf_size2_17_inbus; -assign mux_1level_tapbuf_size2_17_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_17_inbus[1] = chany_0__1__in_3_ ; -wire [21:21] mux_1level_tapbuf_size2_17_configbus0; -wire [21:21] mux_1level_tapbuf_size2_17_configbus1; -wire [21:21] mux_1level_tapbuf_size2_17_sram_blwl_out ; -wire [21:21] mux_1level_tapbuf_size2_17_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_17_configbus0[21:21] = sram_blwl_bl[21:21] ; -assign mux_1level_tapbuf_size2_17_configbus1[21:21] = sram_blwl_wl[21:21] ; -wire [21:21] mux_1level_tapbuf_size2_17_configbus0_b; -assign mux_1level_tapbuf_size2_17_configbus0_b[21:21] = sram_blwl_blb[21:21] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_17_ (mux_1level_tapbuf_size2_17_inbus, chanx_1__0__out_4_ , mux_1level_tapbuf_size2_17_sram_blwl_out[21:21] , -mux_1level_tapbuf_size2_17_sram_blwl_outb[21:21] ); -//----- SRAM bits for MUX[17], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_21_ (mux_1level_tapbuf_size2_17_sram_blwl_out[21:21] ,mux_1level_tapbuf_size2_17_sram_blwl_out[21:21] ,mux_1level_tapbuf_size2_17_sram_blwl_outb[21:21] ,mux_1level_tapbuf_size2_17_configbus0[21:21], mux_1level_tapbuf_size2_17_configbus1[21:21] , mux_1level_tapbuf_size2_17_configbus0_b[21:21] ); -wire [0:1] mux_1level_tapbuf_size2_18_inbus; -assign mux_1level_tapbuf_size2_18_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_18_inbus[1] = chany_0__1__in_5_ ; -wire [22:22] mux_1level_tapbuf_size2_18_configbus0; -wire [22:22] mux_1level_tapbuf_size2_18_configbus1; -wire [22:22] mux_1level_tapbuf_size2_18_sram_blwl_out ; -wire [22:22] mux_1level_tapbuf_size2_18_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_18_configbus0[22:22] = sram_blwl_bl[22:22] ; -assign mux_1level_tapbuf_size2_18_configbus1[22:22] = sram_blwl_wl[22:22] ; -wire [22:22] mux_1level_tapbuf_size2_18_configbus0_b; -assign mux_1level_tapbuf_size2_18_configbus0_b[22:22] = sram_blwl_blb[22:22] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_18_ (mux_1level_tapbuf_size2_18_inbus, chanx_1__0__out_6_ , mux_1level_tapbuf_size2_18_sram_blwl_out[22:22] , -mux_1level_tapbuf_size2_18_sram_blwl_outb[22:22] ); -//----- SRAM bits for MUX[18], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_22_ (mux_1level_tapbuf_size2_18_sram_blwl_out[22:22] ,mux_1level_tapbuf_size2_18_sram_blwl_out[22:22] ,mux_1level_tapbuf_size2_18_sram_blwl_outb[22:22] ,mux_1level_tapbuf_size2_18_configbus0[22:22], mux_1level_tapbuf_size2_18_configbus1[22:22] , mux_1level_tapbuf_size2_18_configbus0_b[22:22] ); -wire [0:1] mux_1level_tapbuf_size2_19_inbus; -assign mux_1level_tapbuf_size2_19_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_19_inbus[1] = chany_0__1__in_7_ ; -wire [23:23] mux_1level_tapbuf_size2_19_configbus0; -wire [23:23] mux_1level_tapbuf_size2_19_configbus1; -wire [23:23] mux_1level_tapbuf_size2_19_sram_blwl_out ; -wire [23:23] mux_1level_tapbuf_size2_19_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_19_configbus0[23:23] = sram_blwl_bl[23:23] ; -assign mux_1level_tapbuf_size2_19_configbus1[23:23] = sram_blwl_wl[23:23] ; -wire [23:23] mux_1level_tapbuf_size2_19_configbus0_b; -assign mux_1level_tapbuf_size2_19_configbus0_b[23:23] = sram_blwl_blb[23:23] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_19_ (mux_1level_tapbuf_size2_19_inbus, chanx_1__0__out_8_ , mux_1level_tapbuf_size2_19_sram_blwl_out[23:23] , -mux_1level_tapbuf_size2_19_sram_blwl_outb[23:23] ); -//----- SRAM bits for MUX[19], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_23_ (mux_1level_tapbuf_size2_19_sram_blwl_out[23:23] ,mux_1level_tapbuf_size2_19_sram_blwl_out[23:23] ,mux_1level_tapbuf_size2_19_sram_blwl_outb[23:23] ,mux_1level_tapbuf_size2_19_configbus0[23:23], mux_1level_tapbuf_size2_19_configbus1[23:23] , mux_1level_tapbuf_size2_19_configbus0_b[23:23] ); -wire [0:1] mux_1level_tapbuf_size2_20_inbus; -assign mux_1level_tapbuf_size2_20_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_20_inbus[1] = chany_0__1__in_9_ ; -wire [24:24] mux_1level_tapbuf_size2_20_configbus0; -wire [24:24] mux_1level_tapbuf_size2_20_configbus1; -wire [24:24] mux_1level_tapbuf_size2_20_sram_blwl_out ; -wire [24:24] mux_1level_tapbuf_size2_20_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_20_configbus0[24:24] = sram_blwl_bl[24:24] ; -assign mux_1level_tapbuf_size2_20_configbus1[24:24] = sram_blwl_wl[24:24] ; -wire [24:24] mux_1level_tapbuf_size2_20_configbus0_b; -assign mux_1level_tapbuf_size2_20_configbus0_b[24:24] = sram_blwl_blb[24:24] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_20_ (mux_1level_tapbuf_size2_20_inbus, chanx_1__0__out_10_ , mux_1level_tapbuf_size2_20_sram_blwl_out[24:24] , -mux_1level_tapbuf_size2_20_sram_blwl_outb[24:24] ); -//----- SRAM bits for MUX[20], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_24_ (mux_1level_tapbuf_size2_20_sram_blwl_out[24:24] ,mux_1level_tapbuf_size2_20_sram_blwl_out[24:24] ,mux_1level_tapbuf_size2_20_sram_blwl_outb[24:24] ,mux_1level_tapbuf_size2_20_configbus0[24:24], mux_1level_tapbuf_size2_20_configbus1[24:24] , mux_1level_tapbuf_size2_20_configbus0_b[24:24] ); -wire [0:1] mux_1level_tapbuf_size2_21_inbus; -assign mux_1level_tapbuf_size2_21_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_21_inbus[1] = chany_0__1__in_11_ ; -wire [25:25] mux_1level_tapbuf_size2_21_configbus0; -wire [25:25] mux_1level_tapbuf_size2_21_configbus1; -wire [25:25] mux_1level_tapbuf_size2_21_sram_blwl_out ; -wire [25:25] mux_1level_tapbuf_size2_21_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_21_configbus0[25:25] = sram_blwl_bl[25:25] ; -assign mux_1level_tapbuf_size2_21_configbus1[25:25] = sram_blwl_wl[25:25] ; -wire [25:25] mux_1level_tapbuf_size2_21_configbus0_b; -assign mux_1level_tapbuf_size2_21_configbus0_b[25:25] = sram_blwl_blb[25:25] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_21_ (mux_1level_tapbuf_size2_21_inbus, chanx_1__0__out_12_ , mux_1level_tapbuf_size2_21_sram_blwl_out[25:25] , -mux_1level_tapbuf_size2_21_sram_blwl_outb[25:25] ); -//----- SRAM bits for MUX[21], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_25_ (mux_1level_tapbuf_size2_21_sram_blwl_out[25:25] ,mux_1level_tapbuf_size2_21_sram_blwl_out[25:25] ,mux_1level_tapbuf_size2_21_sram_blwl_outb[25:25] ,mux_1level_tapbuf_size2_21_configbus0[25:25], mux_1level_tapbuf_size2_21_configbus1[25:25] , mux_1level_tapbuf_size2_21_configbus0_b[25:25] ); -wire [0:1] mux_1level_tapbuf_size2_22_inbus; -assign mux_1level_tapbuf_size2_22_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_22_inbus[1] = chany_0__1__in_13_ ; -wire [26:26] mux_1level_tapbuf_size2_22_configbus0; -wire [26:26] mux_1level_tapbuf_size2_22_configbus1; -wire [26:26] mux_1level_tapbuf_size2_22_sram_blwl_out ; -wire [26:26] mux_1level_tapbuf_size2_22_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_22_configbus0[26:26] = sram_blwl_bl[26:26] ; -assign mux_1level_tapbuf_size2_22_configbus1[26:26] = sram_blwl_wl[26:26] ; -wire [26:26] mux_1level_tapbuf_size2_22_configbus0_b; -assign mux_1level_tapbuf_size2_22_configbus0_b[26:26] = sram_blwl_blb[26:26] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_22_ (mux_1level_tapbuf_size2_22_inbus, chanx_1__0__out_14_ , mux_1level_tapbuf_size2_22_sram_blwl_out[26:26] , -mux_1level_tapbuf_size2_22_sram_blwl_outb[26:26] ); -//----- SRAM bits for MUX[22], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_26_ (mux_1level_tapbuf_size2_22_sram_blwl_out[26:26] ,mux_1level_tapbuf_size2_22_sram_blwl_out[26:26] ,mux_1level_tapbuf_size2_22_sram_blwl_outb[26:26] ,mux_1level_tapbuf_size2_22_configbus0[26:26], mux_1level_tapbuf_size2_22_configbus1[26:26] , mux_1level_tapbuf_size2_22_configbus0_b[26:26] ); -wire [0:1] mux_1level_tapbuf_size2_23_inbus; -assign mux_1level_tapbuf_size2_23_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_23_inbus[1] = chany_0__1__in_15_ ; -wire [27:27] mux_1level_tapbuf_size2_23_configbus0; -wire [27:27] mux_1level_tapbuf_size2_23_configbus1; -wire [27:27] mux_1level_tapbuf_size2_23_sram_blwl_out ; -wire [27:27] mux_1level_tapbuf_size2_23_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_23_configbus0[27:27] = sram_blwl_bl[27:27] ; -assign mux_1level_tapbuf_size2_23_configbus1[27:27] = sram_blwl_wl[27:27] ; -wire [27:27] mux_1level_tapbuf_size2_23_configbus0_b; -assign mux_1level_tapbuf_size2_23_configbus0_b[27:27] = sram_blwl_blb[27:27] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_23_ (mux_1level_tapbuf_size2_23_inbus, chanx_1__0__out_16_ , mux_1level_tapbuf_size2_23_sram_blwl_out[27:27] , -mux_1level_tapbuf_size2_23_sram_blwl_outb[27:27] ); -//----- SRAM bits for MUX[23], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_27_ (mux_1level_tapbuf_size2_23_sram_blwl_out[27:27] ,mux_1level_tapbuf_size2_23_sram_blwl_out[27:27] ,mux_1level_tapbuf_size2_23_sram_blwl_outb[27:27] ,mux_1level_tapbuf_size2_23_configbus0[27:27], mux_1level_tapbuf_size2_23_configbus1[27:27] , mux_1level_tapbuf_size2_23_configbus0_b[27:27] ); -wire [0:1] mux_1level_tapbuf_size2_24_inbus; -assign mux_1level_tapbuf_size2_24_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_24_inbus[1] = chany_0__1__in_17_ ; -wire [28:28] mux_1level_tapbuf_size2_24_configbus0; -wire [28:28] mux_1level_tapbuf_size2_24_configbus1; -wire [28:28] mux_1level_tapbuf_size2_24_sram_blwl_out ; -wire [28:28] mux_1level_tapbuf_size2_24_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_24_configbus0[28:28] = sram_blwl_bl[28:28] ; -assign mux_1level_tapbuf_size2_24_configbus1[28:28] = sram_blwl_wl[28:28] ; -wire [28:28] mux_1level_tapbuf_size2_24_configbus0_b; -assign mux_1level_tapbuf_size2_24_configbus0_b[28:28] = sram_blwl_blb[28:28] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_24_ (mux_1level_tapbuf_size2_24_inbus, chanx_1__0__out_18_ , mux_1level_tapbuf_size2_24_sram_blwl_out[28:28] , -mux_1level_tapbuf_size2_24_sram_blwl_outb[28:28] ); -//----- SRAM bits for MUX[24], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_28_ (mux_1level_tapbuf_size2_24_sram_blwl_out[28:28] ,mux_1level_tapbuf_size2_24_sram_blwl_out[28:28] ,mux_1level_tapbuf_size2_24_sram_blwl_outb[28:28] ,mux_1level_tapbuf_size2_24_configbus0[28:28], mux_1level_tapbuf_size2_24_configbus1[28:28] , mux_1level_tapbuf_size2_24_configbus0_b[28:28] ); -wire [0:1] mux_1level_tapbuf_size2_25_inbus; -assign mux_1level_tapbuf_size2_25_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_25_inbus[1] = chany_0__1__in_19_ ; -wire [29:29] mux_1level_tapbuf_size2_25_configbus0; -wire [29:29] mux_1level_tapbuf_size2_25_configbus1; -wire [29:29] mux_1level_tapbuf_size2_25_sram_blwl_out ; -wire [29:29] mux_1level_tapbuf_size2_25_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_25_configbus0[29:29] = sram_blwl_bl[29:29] ; -assign mux_1level_tapbuf_size2_25_configbus1[29:29] = sram_blwl_wl[29:29] ; -wire [29:29] mux_1level_tapbuf_size2_25_configbus0_b; -assign mux_1level_tapbuf_size2_25_configbus0_b[29:29] = sram_blwl_blb[29:29] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_25_ (mux_1level_tapbuf_size2_25_inbus, chanx_1__0__out_20_ , mux_1level_tapbuf_size2_25_sram_blwl_out[29:29] , -mux_1level_tapbuf_size2_25_sram_blwl_outb[29:29] ); -//----- SRAM bits for MUX[25], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_29_ (mux_1level_tapbuf_size2_25_sram_blwl_out[29:29] ,mux_1level_tapbuf_size2_25_sram_blwl_out[29:29] ,mux_1level_tapbuf_size2_25_sram_blwl_outb[29:29] ,mux_1level_tapbuf_size2_25_configbus0[29:29], mux_1level_tapbuf_size2_25_configbus1[29:29] , mux_1level_tapbuf_size2_25_configbus0_b[29:29] ); -wire [0:1] mux_1level_tapbuf_size2_26_inbus; -assign mux_1level_tapbuf_size2_26_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_26_inbus[1] = chany_0__1__in_21_ ; -wire [30:30] mux_1level_tapbuf_size2_26_configbus0; -wire [30:30] mux_1level_tapbuf_size2_26_configbus1; -wire [30:30] mux_1level_tapbuf_size2_26_sram_blwl_out ; -wire [30:30] mux_1level_tapbuf_size2_26_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_26_configbus0[30:30] = sram_blwl_bl[30:30] ; -assign mux_1level_tapbuf_size2_26_configbus1[30:30] = sram_blwl_wl[30:30] ; -wire [30:30] mux_1level_tapbuf_size2_26_configbus0_b; -assign mux_1level_tapbuf_size2_26_configbus0_b[30:30] = sram_blwl_blb[30:30] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_26_ (mux_1level_tapbuf_size2_26_inbus, chanx_1__0__out_22_ , mux_1level_tapbuf_size2_26_sram_blwl_out[30:30] , -mux_1level_tapbuf_size2_26_sram_blwl_outb[30:30] ); -//----- SRAM bits for MUX[26], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_30_ (mux_1level_tapbuf_size2_26_sram_blwl_out[30:30] ,mux_1level_tapbuf_size2_26_sram_blwl_out[30:30] ,mux_1level_tapbuf_size2_26_sram_blwl_outb[30:30] ,mux_1level_tapbuf_size2_26_configbus0[30:30], mux_1level_tapbuf_size2_26_configbus1[30:30] , mux_1level_tapbuf_size2_26_configbus0_b[30:30] ); -wire [0:1] mux_1level_tapbuf_size2_27_inbus; -assign mux_1level_tapbuf_size2_27_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_27_inbus[1] = chany_0__1__in_23_ ; -wire [31:31] mux_1level_tapbuf_size2_27_configbus0; -wire [31:31] mux_1level_tapbuf_size2_27_configbus1; -wire [31:31] mux_1level_tapbuf_size2_27_sram_blwl_out ; -wire [31:31] mux_1level_tapbuf_size2_27_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_27_configbus0[31:31] = sram_blwl_bl[31:31] ; -assign mux_1level_tapbuf_size2_27_configbus1[31:31] = sram_blwl_wl[31:31] ; -wire [31:31] mux_1level_tapbuf_size2_27_configbus0_b; -assign mux_1level_tapbuf_size2_27_configbus0_b[31:31] = sram_blwl_blb[31:31] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_27_ (mux_1level_tapbuf_size2_27_inbus, chanx_1__0__out_24_ , mux_1level_tapbuf_size2_27_sram_blwl_out[31:31] , -mux_1level_tapbuf_size2_27_sram_blwl_outb[31:31] ); -//----- SRAM bits for MUX[27], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_31_ (mux_1level_tapbuf_size2_27_sram_blwl_out[31:31] ,mux_1level_tapbuf_size2_27_sram_blwl_out[31:31] ,mux_1level_tapbuf_size2_27_sram_blwl_outb[31:31] ,mux_1level_tapbuf_size2_27_configbus0[31:31], mux_1level_tapbuf_size2_27_configbus1[31:31] , mux_1level_tapbuf_size2_27_configbus0_b[31:31] ); -wire [0:1] mux_1level_tapbuf_size2_28_inbus; -assign mux_1level_tapbuf_size2_28_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_28_inbus[1] = chany_0__1__in_25_ ; -wire [32:32] mux_1level_tapbuf_size2_28_configbus0; -wire [32:32] mux_1level_tapbuf_size2_28_configbus1; -wire [32:32] mux_1level_tapbuf_size2_28_sram_blwl_out ; -wire [32:32] mux_1level_tapbuf_size2_28_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_28_configbus0[32:32] = sram_blwl_bl[32:32] ; -assign mux_1level_tapbuf_size2_28_configbus1[32:32] = sram_blwl_wl[32:32] ; -wire [32:32] mux_1level_tapbuf_size2_28_configbus0_b; -assign mux_1level_tapbuf_size2_28_configbus0_b[32:32] = sram_blwl_blb[32:32] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_28_ (mux_1level_tapbuf_size2_28_inbus, chanx_1__0__out_26_ , mux_1level_tapbuf_size2_28_sram_blwl_out[32:32] , -mux_1level_tapbuf_size2_28_sram_blwl_outb[32:32] ); -//----- SRAM bits for MUX[28], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_32_ (mux_1level_tapbuf_size2_28_sram_blwl_out[32:32] ,mux_1level_tapbuf_size2_28_sram_blwl_out[32:32] ,mux_1level_tapbuf_size2_28_sram_blwl_outb[32:32] ,mux_1level_tapbuf_size2_28_configbus0[32:32], mux_1level_tapbuf_size2_28_configbus1[32:32] , mux_1level_tapbuf_size2_28_configbus0_b[32:32] ); -wire [0:1] mux_1level_tapbuf_size2_29_inbus; -assign mux_1level_tapbuf_size2_29_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_29_inbus[1] = chany_0__1__in_27_ ; -wire [33:33] mux_1level_tapbuf_size2_29_configbus0; -wire [33:33] mux_1level_tapbuf_size2_29_configbus1; -wire [33:33] mux_1level_tapbuf_size2_29_sram_blwl_out ; -wire [33:33] mux_1level_tapbuf_size2_29_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_29_configbus0[33:33] = sram_blwl_bl[33:33] ; -assign mux_1level_tapbuf_size2_29_configbus1[33:33] = sram_blwl_wl[33:33] ; -wire [33:33] mux_1level_tapbuf_size2_29_configbus0_b; -assign mux_1level_tapbuf_size2_29_configbus0_b[33:33] = sram_blwl_blb[33:33] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_29_ (mux_1level_tapbuf_size2_29_inbus, chanx_1__0__out_28_ , mux_1level_tapbuf_size2_29_sram_blwl_out[33:33] , -mux_1level_tapbuf_size2_29_sram_blwl_outb[33:33] ); -//----- SRAM bits for MUX[29], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_33_ (mux_1level_tapbuf_size2_29_sram_blwl_out[33:33] ,mux_1level_tapbuf_size2_29_sram_blwl_out[33:33] ,mux_1level_tapbuf_size2_29_sram_blwl_outb[33:33] ,mux_1level_tapbuf_size2_29_configbus0[33:33], mux_1level_tapbuf_size2_29_configbus1[33:33] , mux_1level_tapbuf_size2_29_configbus0_b[33:33] ); -//----- bottom side Multiplexers ----- -//----- left side Multiplexers ----- -endmodule -//----- END Verilog Module of Switch Box[0][0] ----- - diff --git a/examples/verilog_test_example_1/routing/sb_0_1.v b/examples/verilog_test_example_1/routing/sb_0_1.v deleted file mode 100644 index f2fc97c04..000000000 --- a/examples/verilog_test_example_1/routing/sb_0_1.v +++ /dev/null @@ -1,634 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Switch Block [0][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Switch Box[0][1] ----- -module sb_0__1_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -//----- Inputs/outputs of top side ----- -//----- Inputs/outputs of right side ----- - output chanx_1__1__out_0_, - input chanx_1__1__in_1_, - output chanx_1__1__out_2_, - input chanx_1__1__in_3_, - output chanx_1__1__out_4_, - input chanx_1__1__in_5_, - output chanx_1__1__out_6_, - input chanx_1__1__in_7_, - output chanx_1__1__out_8_, - input chanx_1__1__in_9_, - output chanx_1__1__out_10_, - input chanx_1__1__in_11_, - output chanx_1__1__out_12_, - input chanx_1__1__in_13_, - output chanx_1__1__out_14_, - input chanx_1__1__in_15_, - output chanx_1__1__out_16_, - input chanx_1__1__in_17_, - output chanx_1__1__out_18_, - input chanx_1__1__in_19_, - output chanx_1__1__out_20_, - input chanx_1__1__in_21_, - output chanx_1__1__out_22_, - input chanx_1__1__in_23_, - output chanx_1__1__out_24_, - input chanx_1__1__in_25_, - output chanx_1__1__out_26_, - input chanx_1__1__in_27_, - output chanx_1__1__out_28_, - input chanx_1__1__in_29_, -input grid_1__2__pin_0__2__1_, -input grid_1__2__pin_0__2__3_, -input grid_1__2__pin_0__2__5_, -input grid_1__2__pin_0__2__7_, -input grid_1__2__pin_0__2__9_, -input grid_1__2__pin_0__2__11_, -input grid_1__2__pin_0__2__13_, -input grid_1__2__pin_0__2__15_, -input grid_1__1__pin_0__0__4_, -//----- Inputs/outputs of bottom side ----- - input chany_0__1__in_0_, - output chany_0__1__out_1_, - input chany_0__1__in_2_, - output chany_0__1__out_3_, - input chany_0__1__in_4_, - output chany_0__1__out_5_, - input chany_0__1__in_6_, - output chany_0__1__out_7_, - input chany_0__1__in_8_, - output chany_0__1__out_9_, - input chany_0__1__in_10_, - output chany_0__1__out_11_, - input chany_0__1__in_12_, - output chany_0__1__out_13_, - input chany_0__1__in_14_, - output chany_0__1__out_15_, - input chany_0__1__in_16_, - output chany_0__1__out_17_, - input chany_0__1__in_18_, - output chany_0__1__out_19_, - input chany_0__1__in_20_, - output chany_0__1__out_21_, - input chany_0__1__in_22_, - output chany_0__1__out_23_, - input chany_0__1__in_24_, - output chany_0__1__out_25_, - input chany_0__1__in_26_, - output chany_0__1__out_27_, - input chany_0__1__in_28_, - output chany_0__1__out_29_, -input grid_0__1__pin_0__1__1_, -input grid_0__1__pin_0__1__3_, -input grid_0__1__pin_0__1__5_, -input grid_0__1__pin_0__1__7_, -input grid_0__1__pin_0__1__9_, -input grid_0__1__pin_0__1__11_, -input grid_0__1__pin_0__1__13_, -input grid_0__1__pin_0__1__15_, -//----- Inputs/outputs of left side ----- -input [34:71] sram_blwl_bl , -input [34:71] sram_blwl_wl , -input [34:71] sram_blwl_blb ); -//----- top side Multiplexers ----- -//----- right side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_30_inbus; -assign mux_1level_tapbuf_size3_30_inbus[0] = grid_1__1__pin_0__0__4_; -assign mux_1level_tapbuf_size3_30_inbus[1] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size3_30_inbus[2] = chany_0__1__in_26_ ; -wire [34:36] mux_1level_tapbuf_size3_30_configbus0; -wire [34:36] mux_1level_tapbuf_size3_30_configbus1; -wire [34:36] mux_1level_tapbuf_size3_30_sram_blwl_out ; -wire [34:36] mux_1level_tapbuf_size3_30_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_30_configbus0[34:36] = sram_blwl_bl[34:36] ; -assign mux_1level_tapbuf_size3_30_configbus1[34:36] = sram_blwl_wl[34:36] ; -wire [34:36] mux_1level_tapbuf_size3_30_configbus0_b; -assign mux_1level_tapbuf_size3_30_configbus0_b[34:36] = sram_blwl_blb[34:36] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_30_ (mux_1level_tapbuf_size3_30_inbus, chanx_1__1__out_0_ , mux_1level_tapbuf_size3_30_sram_blwl_out[34:36] , -mux_1level_tapbuf_size3_30_sram_blwl_outb[34:36] ); -//----- SRAM bits for MUX[30], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_34_ (mux_1level_tapbuf_size3_30_sram_blwl_out[34:34] ,mux_1level_tapbuf_size3_30_sram_blwl_out[34:34] ,mux_1level_tapbuf_size3_30_sram_blwl_outb[34:34] ,mux_1level_tapbuf_size3_30_configbus0[34:34], mux_1level_tapbuf_size3_30_configbus1[34:34] , mux_1level_tapbuf_size3_30_configbus0_b[34:34] ); -sram6T_blwl sram_blwl_35_ (mux_1level_tapbuf_size3_30_sram_blwl_out[35:35] ,mux_1level_tapbuf_size3_30_sram_blwl_out[35:35] ,mux_1level_tapbuf_size3_30_sram_blwl_outb[35:35] ,mux_1level_tapbuf_size3_30_configbus0[35:35], mux_1level_tapbuf_size3_30_configbus1[35:35] , mux_1level_tapbuf_size3_30_configbus0_b[35:35] ); -sram6T_blwl sram_blwl_36_ (mux_1level_tapbuf_size3_30_sram_blwl_out[36:36] ,mux_1level_tapbuf_size3_30_sram_blwl_out[36:36] ,mux_1level_tapbuf_size3_30_sram_blwl_outb[36:36] ,mux_1level_tapbuf_size3_30_configbus0[36:36], mux_1level_tapbuf_size3_30_configbus1[36:36] , mux_1level_tapbuf_size3_30_configbus0_b[36:36] ); -wire [0:2] mux_1level_tapbuf_size3_31_inbus; -assign mux_1level_tapbuf_size3_31_inbus[0] = grid_1__1__pin_0__0__4_; -assign mux_1level_tapbuf_size3_31_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_31_inbus[2] = chany_0__1__in_24_ ; -wire [37:39] mux_1level_tapbuf_size3_31_configbus0; -wire [37:39] mux_1level_tapbuf_size3_31_configbus1; -wire [37:39] mux_1level_tapbuf_size3_31_sram_blwl_out ; -wire [37:39] mux_1level_tapbuf_size3_31_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_31_configbus0[37:39] = sram_blwl_bl[37:39] ; -assign mux_1level_tapbuf_size3_31_configbus1[37:39] = sram_blwl_wl[37:39] ; -wire [37:39] mux_1level_tapbuf_size3_31_configbus0_b; -assign mux_1level_tapbuf_size3_31_configbus0_b[37:39] = sram_blwl_blb[37:39] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_31_ (mux_1level_tapbuf_size3_31_inbus, chanx_1__1__out_2_ , mux_1level_tapbuf_size3_31_sram_blwl_out[37:39] , -mux_1level_tapbuf_size3_31_sram_blwl_outb[37:39] ); -//----- SRAM bits for MUX[31], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_37_ (mux_1level_tapbuf_size3_31_sram_blwl_out[37:37] ,mux_1level_tapbuf_size3_31_sram_blwl_out[37:37] ,mux_1level_tapbuf_size3_31_sram_blwl_outb[37:37] ,mux_1level_tapbuf_size3_31_configbus0[37:37], mux_1level_tapbuf_size3_31_configbus1[37:37] , mux_1level_tapbuf_size3_31_configbus0_b[37:37] ); -sram6T_blwl sram_blwl_38_ (mux_1level_tapbuf_size3_31_sram_blwl_out[38:38] ,mux_1level_tapbuf_size3_31_sram_blwl_out[38:38] ,mux_1level_tapbuf_size3_31_sram_blwl_outb[38:38] ,mux_1level_tapbuf_size3_31_configbus0[38:38], mux_1level_tapbuf_size3_31_configbus1[38:38] , mux_1level_tapbuf_size3_31_configbus0_b[38:38] ); -sram6T_blwl sram_blwl_39_ (mux_1level_tapbuf_size3_31_sram_blwl_out[39:39] ,mux_1level_tapbuf_size3_31_sram_blwl_out[39:39] ,mux_1level_tapbuf_size3_31_sram_blwl_outb[39:39] ,mux_1level_tapbuf_size3_31_configbus0[39:39], mux_1level_tapbuf_size3_31_configbus1[39:39] , mux_1level_tapbuf_size3_31_configbus0_b[39:39] ); -wire [0:2] mux_1level_tapbuf_size3_32_inbus; -assign mux_1level_tapbuf_size3_32_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size3_32_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_32_inbus[2] = chany_0__1__in_22_ ; -wire [40:42] mux_1level_tapbuf_size3_32_configbus0; -wire [40:42] mux_1level_tapbuf_size3_32_configbus1; -wire [40:42] mux_1level_tapbuf_size3_32_sram_blwl_out ; -wire [40:42] mux_1level_tapbuf_size3_32_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_32_configbus0[40:42] = sram_blwl_bl[40:42] ; -assign mux_1level_tapbuf_size3_32_configbus1[40:42] = sram_blwl_wl[40:42] ; -wire [40:42] mux_1level_tapbuf_size3_32_configbus0_b; -assign mux_1level_tapbuf_size3_32_configbus0_b[40:42] = sram_blwl_blb[40:42] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_32_ (mux_1level_tapbuf_size3_32_inbus, chanx_1__1__out_4_ , mux_1level_tapbuf_size3_32_sram_blwl_out[40:42] , -mux_1level_tapbuf_size3_32_sram_blwl_outb[40:42] ); -//----- SRAM bits for MUX[32], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_40_ (mux_1level_tapbuf_size3_32_sram_blwl_out[40:40] ,mux_1level_tapbuf_size3_32_sram_blwl_out[40:40] ,mux_1level_tapbuf_size3_32_sram_blwl_outb[40:40] ,mux_1level_tapbuf_size3_32_configbus0[40:40], mux_1level_tapbuf_size3_32_configbus1[40:40] , mux_1level_tapbuf_size3_32_configbus0_b[40:40] ); -sram6T_blwl sram_blwl_41_ (mux_1level_tapbuf_size3_32_sram_blwl_out[41:41] ,mux_1level_tapbuf_size3_32_sram_blwl_out[41:41] ,mux_1level_tapbuf_size3_32_sram_blwl_outb[41:41] ,mux_1level_tapbuf_size3_32_configbus0[41:41], mux_1level_tapbuf_size3_32_configbus1[41:41] , mux_1level_tapbuf_size3_32_configbus0_b[41:41] ); -sram6T_blwl sram_blwl_42_ (mux_1level_tapbuf_size3_32_sram_blwl_out[42:42] ,mux_1level_tapbuf_size3_32_sram_blwl_out[42:42] ,mux_1level_tapbuf_size3_32_sram_blwl_outb[42:42] ,mux_1level_tapbuf_size3_32_configbus0[42:42], mux_1level_tapbuf_size3_32_configbus1[42:42] , mux_1level_tapbuf_size3_32_configbus0_b[42:42] ); -wire [0:1] mux_1level_tapbuf_size2_33_inbus; -assign mux_1level_tapbuf_size2_33_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_33_inbus[1] = chany_0__1__in_20_ ; -wire [43:43] mux_1level_tapbuf_size2_33_configbus0; -wire [43:43] mux_1level_tapbuf_size2_33_configbus1; -wire [43:43] mux_1level_tapbuf_size2_33_sram_blwl_out ; -wire [43:43] mux_1level_tapbuf_size2_33_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_33_configbus0[43:43] = sram_blwl_bl[43:43] ; -assign mux_1level_tapbuf_size2_33_configbus1[43:43] = sram_blwl_wl[43:43] ; -wire [43:43] mux_1level_tapbuf_size2_33_configbus0_b; -assign mux_1level_tapbuf_size2_33_configbus0_b[43:43] = sram_blwl_blb[43:43] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_33_ (mux_1level_tapbuf_size2_33_inbus, chanx_1__1__out_6_ , mux_1level_tapbuf_size2_33_sram_blwl_out[43:43] , -mux_1level_tapbuf_size2_33_sram_blwl_outb[43:43] ); -//----- SRAM bits for MUX[33], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_43_ (mux_1level_tapbuf_size2_33_sram_blwl_out[43:43] ,mux_1level_tapbuf_size2_33_sram_blwl_out[43:43] ,mux_1level_tapbuf_size2_33_sram_blwl_outb[43:43] ,mux_1level_tapbuf_size2_33_configbus0[43:43], mux_1level_tapbuf_size2_33_configbus1[43:43] , mux_1level_tapbuf_size2_33_configbus0_b[43:43] ); -wire [0:1] mux_1level_tapbuf_size2_34_inbus; -assign mux_1level_tapbuf_size2_34_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_34_inbus[1] = chany_0__1__in_18_ ; -wire [44:44] mux_1level_tapbuf_size2_34_configbus0; -wire [44:44] mux_1level_tapbuf_size2_34_configbus1; -wire [44:44] mux_1level_tapbuf_size2_34_sram_blwl_out ; -wire [44:44] mux_1level_tapbuf_size2_34_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_34_configbus0[44:44] = sram_blwl_bl[44:44] ; -assign mux_1level_tapbuf_size2_34_configbus1[44:44] = sram_blwl_wl[44:44] ; -wire [44:44] mux_1level_tapbuf_size2_34_configbus0_b; -assign mux_1level_tapbuf_size2_34_configbus0_b[44:44] = sram_blwl_blb[44:44] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_34_ (mux_1level_tapbuf_size2_34_inbus, chanx_1__1__out_8_ , mux_1level_tapbuf_size2_34_sram_blwl_out[44:44] , -mux_1level_tapbuf_size2_34_sram_blwl_outb[44:44] ); -//----- SRAM bits for MUX[34], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_44_ (mux_1level_tapbuf_size2_34_sram_blwl_out[44:44] ,mux_1level_tapbuf_size2_34_sram_blwl_out[44:44] ,mux_1level_tapbuf_size2_34_sram_blwl_outb[44:44] ,mux_1level_tapbuf_size2_34_configbus0[44:44], mux_1level_tapbuf_size2_34_configbus1[44:44] , mux_1level_tapbuf_size2_34_configbus0_b[44:44] ); -wire [0:1] mux_1level_tapbuf_size2_35_inbus; -assign mux_1level_tapbuf_size2_35_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_35_inbus[1] = chany_0__1__in_16_ ; -wire [45:45] mux_1level_tapbuf_size2_35_configbus0; -wire [45:45] mux_1level_tapbuf_size2_35_configbus1; -wire [45:45] mux_1level_tapbuf_size2_35_sram_blwl_out ; -wire [45:45] mux_1level_tapbuf_size2_35_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_35_configbus0[45:45] = sram_blwl_bl[45:45] ; -assign mux_1level_tapbuf_size2_35_configbus1[45:45] = sram_blwl_wl[45:45] ; -wire [45:45] mux_1level_tapbuf_size2_35_configbus0_b; -assign mux_1level_tapbuf_size2_35_configbus0_b[45:45] = sram_blwl_blb[45:45] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_35_ (mux_1level_tapbuf_size2_35_inbus, chanx_1__1__out_10_ , mux_1level_tapbuf_size2_35_sram_blwl_out[45:45] , -mux_1level_tapbuf_size2_35_sram_blwl_outb[45:45] ); -//----- SRAM bits for MUX[35], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_45_ (mux_1level_tapbuf_size2_35_sram_blwl_out[45:45] ,mux_1level_tapbuf_size2_35_sram_blwl_out[45:45] ,mux_1level_tapbuf_size2_35_sram_blwl_outb[45:45] ,mux_1level_tapbuf_size2_35_configbus0[45:45], mux_1level_tapbuf_size2_35_configbus1[45:45] , mux_1level_tapbuf_size2_35_configbus0_b[45:45] ); -wire [0:1] mux_1level_tapbuf_size2_36_inbus; -assign mux_1level_tapbuf_size2_36_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_36_inbus[1] = chany_0__1__in_14_ ; -wire [46:46] mux_1level_tapbuf_size2_36_configbus0; -wire [46:46] mux_1level_tapbuf_size2_36_configbus1; -wire [46:46] mux_1level_tapbuf_size2_36_sram_blwl_out ; -wire [46:46] mux_1level_tapbuf_size2_36_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_36_configbus0[46:46] = sram_blwl_bl[46:46] ; -assign mux_1level_tapbuf_size2_36_configbus1[46:46] = sram_blwl_wl[46:46] ; -wire [46:46] mux_1level_tapbuf_size2_36_configbus0_b; -assign mux_1level_tapbuf_size2_36_configbus0_b[46:46] = sram_blwl_blb[46:46] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_36_ (mux_1level_tapbuf_size2_36_inbus, chanx_1__1__out_12_ , mux_1level_tapbuf_size2_36_sram_blwl_out[46:46] , -mux_1level_tapbuf_size2_36_sram_blwl_outb[46:46] ); -//----- SRAM bits for MUX[36], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_46_ (mux_1level_tapbuf_size2_36_sram_blwl_out[46:46] ,mux_1level_tapbuf_size2_36_sram_blwl_out[46:46] ,mux_1level_tapbuf_size2_36_sram_blwl_outb[46:46] ,mux_1level_tapbuf_size2_36_configbus0[46:46], mux_1level_tapbuf_size2_36_configbus1[46:46] , mux_1level_tapbuf_size2_36_configbus0_b[46:46] ); -wire [0:1] mux_1level_tapbuf_size2_37_inbus; -assign mux_1level_tapbuf_size2_37_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_37_inbus[1] = chany_0__1__in_12_ ; -wire [47:47] mux_1level_tapbuf_size2_37_configbus0; -wire [47:47] mux_1level_tapbuf_size2_37_configbus1; -wire [47:47] mux_1level_tapbuf_size2_37_sram_blwl_out ; -wire [47:47] mux_1level_tapbuf_size2_37_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_37_configbus0[47:47] = sram_blwl_bl[47:47] ; -assign mux_1level_tapbuf_size2_37_configbus1[47:47] = sram_blwl_wl[47:47] ; -wire [47:47] mux_1level_tapbuf_size2_37_configbus0_b; -assign mux_1level_tapbuf_size2_37_configbus0_b[47:47] = sram_blwl_blb[47:47] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_37_ (mux_1level_tapbuf_size2_37_inbus, chanx_1__1__out_14_ , mux_1level_tapbuf_size2_37_sram_blwl_out[47:47] , -mux_1level_tapbuf_size2_37_sram_blwl_outb[47:47] ); -//----- SRAM bits for MUX[37], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_47_ (mux_1level_tapbuf_size2_37_sram_blwl_out[47:47] ,mux_1level_tapbuf_size2_37_sram_blwl_out[47:47] ,mux_1level_tapbuf_size2_37_sram_blwl_outb[47:47] ,mux_1level_tapbuf_size2_37_configbus0[47:47], mux_1level_tapbuf_size2_37_configbus1[47:47] , mux_1level_tapbuf_size2_37_configbus0_b[47:47] ); -wire [0:1] mux_1level_tapbuf_size2_38_inbus; -assign mux_1level_tapbuf_size2_38_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_38_inbus[1] = chany_0__1__in_10_ ; -wire [48:48] mux_1level_tapbuf_size2_38_configbus0; -wire [48:48] mux_1level_tapbuf_size2_38_configbus1; -wire [48:48] mux_1level_tapbuf_size2_38_sram_blwl_out ; -wire [48:48] mux_1level_tapbuf_size2_38_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_38_configbus0[48:48] = sram_blwl_bl[48:48] ; -assign mux_1level_tapbuf_size2_38_configbus1[48:48] = sram_blwl_wl[48:48] ; -wire [48:48] mux_1level_tapbuf_size2_38_configbus0_b; -assign mux_1level_tapbuf_size2_38_configbus0_b[48:48] = sram_blwl_blb[48:48] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_38_ (mux_1level_tapbuf_size2_38_inbus, chanx_1__1__out_16_ , mux_1level_tapbuf_size2_38_sram_blwl_out[48:48] , -mux_1level_tapbuf_size2_38_sram_blwl_outb[48:48] ); -//----- SRAM bits for MUX[38], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_48_ (mux_1level_tapbuf_size2_38_sram_blwl_out[48:48] ,mux_1level_tapbuf_size2_38_sram_blwl_out[48:48] ,mux_1level_tapbuf_size2_38_sram_blwl_outb[48:48] ,mux_1level_tapbuf_size2_38_configbus0[48:48], mux_1level_tapbuf_size2_38_configbus1[48:48] , mux_1level_tapbuf_size2_38_configbus0_b[48:48] ); -wire [0:1] mux_1level_tapbuf_size2_39_inbus; -assign mux_1level_tapbuf_size2_39_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_39_inbus[1] = chany_0__1__in_8_ ; -wire [49:49] mux_1level_tapbuf_size2_39_configbus0; -wire [49:49] mux_1level_tapbuf_size2_39_configbus1; -wire [49:49] mux_1level_tapbuf_size2_39_sram_blwl_out ; -wire [49:49] mux_1level_tapbuf_size2_39_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_39_configbus0[49:49] = sram_blwl_bl[49:49] ; -assign mux_1level_tapbuf_size2_39_configbus1[49:49] = sram_blwl_wl[49:49] ; -wire [49:49] mux_1level_tapbuf_size2_39_configbus0_b; -assign mux_1level_tapbuf_size2_39_configbus0_b[49:49] = sram_blwl_blb[49:49] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_39_ (mux_1level_tapbuf_size2_39_inbus, chanx_1__1__out_18_ , mux_1level_tapbuf_size2_39_sram_blwl_out[49:49] , -mux_1level_tapbuf_size2_39_sram_blwl_outb[49:49] ); -//----- SRAM bits for MUX[39], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_49_ (mux_1level_tapbuf_size2_39_sram_blwl_out[49:49] ,mux_1level_tapbuf_size2_39_sram_blwl_out[49:49] ,mux_1level_tapbuf_size2_39_sram_blwl_outb[49:49] ,mux_1level_tapbuf_size2_39_configbus0[49:49], mux_1level_tapbuf_size2_39_configbus1[49:49] , mux_1level_tapbuf_size2_39_configbus0_b[49:49] ); -wire [0:1] mux_1level_tapbuf_size2_40_inbus; -assign mux_1level_tapbuf_size2_40_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_40_inbus[1] = chany_0__1__in_6_ ; -wire [50:50] mux_1level_tapbuf_size2_40_configbus0; -wire [50:50] mux_1level_tapbuf_size2_40_configbus1; -wire [50:50] mux_1level_tapbuf_size2_40_sram_blwl_out ; -wire [50:50] mux_1level_tapbuf_size2_40_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_40_configbus0[50:50] = sram_blwl_bl[50:50] ; -assign mux_1level_tapbuf_size2_40_configbus1[50:50] = sram_blwl_wl[50:50] ; -wire [50:50] mux_1level_tapbuf_size2_40_configbus0_b; -assign mux_1level_tapbuf_size2_40_configbus0_b[50:50] = sram_blwl_blb[50:50] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_40_ (mux_1level_tapbuf_size2_40_inbus, chanx_1__1__out_20_ , mux_1level_tapbuf_size2_40_sram_blwl_out[50:50] , -mux_1level_tapbuf_size2_40_sram_blwl_outb[50:50] ); -//----- SRAM bits for MUX[40], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_50_ (mux_1level_tapbuf_size2_40_sram_blwl_out[50:50] ,mux_1level_tapbuf_size2_40_sram_blwl_out[50:50] ,mux_1level_tapbuf_size2_40_sram_blwl_outb[50:50] ,mux_1level_tapbuf_size2_40_configbus0[50:50], mux_1level_tapbuf_size2_40_configbus1[50:50] , mux_1level_tapbuf_size2_40_configbus0_b[50:50] ); -wire [0:1] mux_1level_tapbuf_size2_41_inbus; -assign mux_1level_tapbuf_size2_41_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_41_inbus[1] = chany_0__1__in_4_ ; -wire [51:51] mux_1level_tapbuf_size2_41_configbus0; -wire [51:51] mux_1level_tapbuf_size2_41_configbus1; -wire [51:51] mux_1level_tapbuf_size2_41_sram_blwl_out ; -wire [51:51] mux_1level_tapbuf_size2_41_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_41_configbus0[51:51] = sram_blwl_bl[51:51] ; -assign mux_1level_tapbuf_size2_41_configbus1[51:51] = sram_blwl_wl[51:51] ; -wire [51:51] mux_1level_tapbuf_size2_41_configbus0_b; -assign mux_1level_tapbuf_size2_41_configbus0_b[51:51] = sram_blwl_blb[51:51] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_41_ (mux_1level_tapbuf_size2_41_inbus, chanx_1__1__out_22_ , mux_1level_tapbuf_size2_41_sram_blwl_out[51:51] , -mux_1level_tapbuf_size2_41_sram_blwl_outb[51:51] ); -//----- SRAM bits for MUX[41], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_51_ (mux_1level_tapbuf_size2_41_sram_blwl_out[51:51] ,mux_1level_tapbuf_size2_41_sram_blwl_out[51:51] ,mux_1level_tapbuf_size2_41_sram_blwl_outb[51:51] ,mux_1level_tapbuf_size2_41_configbus0[51:51], mux_1level_tapbuf_size2_41_configbus1[51:51] , mux_1level_tapbuf_size2_41_configbus0_b[51:51] ); -wire [0:1] mux_1level_tapbuf_size2_42_inbus; -assign mux_1level_tapbuf_size2_42_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_42_inbus[1] = chany_0__1__in_2_ ; -wire [52:52] mux_1level_tapbuf_size2_42_configbus0; -wire [52:52] mux_1level_tapbuf_size2_42_configbus1; -wire [52:52] mux_1level_tapbuf_size2_42_sram_blwl_out ; -wire [52:52] mux_1level_tapbuf_size2_42_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_42_configbus0[52:52] = sram_blwl_bl[52:52] ; -assign mux_1level_tapbuf_size2_42_configbus1[52:52] = sram_blwl_wl[52:52] ; -wire [52:52] mux_1level_tapbuf_size2_42_configbus0_b; -assign mux_1level_tapbuf_size2_42_configbus0_b[52:52] = sram_blwl_blb[52:52] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_42_ (mux_1level_tapbuf_size2_42_inbus, chanx_1__1__out_24_ , mux_1level_tapbuf_size2_42_sram_blwl_out[52:52] , -mux_1level_tapbuf_size2_42_sram_blwl_outb[52:52] ); -//----- SRAM bits for MUX[42], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_52_ (mux_1level_tapbuf_size2_42_sram_blwl_out[52:52] ,mux_1level_tapbuf_size2_42_sram_blwl_out[52:52] ,mux_1level_tapbuf_size2_42_sram_blwl_outb[52:52] ,mux_1level_tapbuf_size2_42_configbus0[52:52], mux_1level_tapbuf_size2_42_configbus1[52:52] , mux_1level_tapbuf_size2_42_configbus0_b[52:52] ); -wire [0:1] mux_1level_tapbuf_size2_43_inbus; -assign mux_1level_tapbuf_size2_43_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_43_inbus[1] = chany_0__1__in_0_ ; -wire [53:53] mux_1level_tapbuf_size2_43_configbus0; -wire [53:53] mux_1level_tapbuf_size2_43_configbus1; -wire [53:53] mux_1level_tapbuf_size2_43_sram_blwl_out ; -wire [53:53] mux_1level_tapbuf_size2_43_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_43_configbus0[53:53] = sram_blwl_bl[53:53] ; -assign mux_1level_tapbuf_size2_43_configbus1[53:53] = sram_blwl_wl[53:53] ; -wire [53:53] mux_1level_tapbuf_size2_43_configbus0_b; -assign mux_1level_tapbuf_size2_43_configbus0_b[53:53] = sram_blwl_blb[53:53] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_43_ (mux_1level_tapbuf_size2_43_inbus, chanx_1__1__out_26_ , mux_1level_tapbuf_size2_43_sram_blwl_out[53:53] , -mux_1level_tapbuf_size2_43_sram_blwl_outb[53:53] ); -//----- SRAM bits for MUX[43], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_53_ (mux_1level_tapbuf_size2_43_sram_blwl_out[53:53] ,mux_1level_tapbuf_size2_43_sram_blwl_out[53:53] ,mux_1level_tapbuf_size2_43_sram_blwl_outb[53:53] ,mux_1level_tapbuf_size2_43_configbus0[53:53], mux_1level_tapbuf_size2_43_configbus1[53:53] , mux_1level_tapbuf_size2_43_configbus0_b[53:53] ); -wire [0:1] mux_1level_tapbuf_size2_44_inbus; -assign mux_1level_tapbuf_size2_44_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_44_inbus[1] = chany_0__1__in_28_ ; -wire [54:54] mux_1level_tapbuf_size2_44_configbus0; -wire [54:54] mux_1level_tapbuf_size2_44_configbus1; -wire [54:54] mux_1level_tapbuf_size2_44_sram_blwl_out ; -wire [54:54] mux_1level_tapbuf_size2_44_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_44_configbus0[54:54] = sram_blwl_bl[54:54] ; -assign mux_1level_tapbuf_size2_44_configbus1[54:54] = sram_blwl_wl[54:54] ; -wire [54:54] mux_1level_tapbuf_size2_44_configbus0_b; -assign mux_1level_tapbuf_size2_44_configbus0_b[54:54] = sram_blwl_blb[54:54] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_44_ (mux_1level_tapbuf_size2_44_inbus, chanx_1__1__out_28_ , mux_1level_tapbuf_size2_44_sram_blwl_out[54:54] , -mux_1level_tapbuf_size2_44_sram_blwl_outb[54:54] ); -//----- SRAM bits for MUX[44], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_54_ (mux_1level_tapbuf_size2_44_sram_blwl_out[54:54] ,mux_1level_tapbuf_size2_44_sram_blwl_out[54:54] ,mux_1level_tapbuf_size2_44_sram_blwl_outb[54:54] ,mux_1level_tapbuf_size2_44_configbus0[54:54], mux_1level_tapbuf_size2_44_configbus1[54:54] , mux_1level_tapbuf_size2_44_configbus0_b[54:54] ); -//----- bottom side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_45_inbus; -assign mux_1level_tapbuf_size3_45_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size3_45_inbus[1] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size3_45_inbus[2] = chanx_1__1__in_27_ ; -wire [55:57] mux_1level_tapbuf_size3_45_configbus0; -wire [55:57] mux_1level_tapbuf_size3_45_configbus1; -wire [55:57] mux_1level_tapbuf_size3_45_sram_blwl_out ; -wire [55:57] mux_1level_tapbuf_size3_45_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_45_configbus0[55:57] = sram_blwl_bl[55:57] ; -assign mux_1level_tapbuf_size3_45_configbus1[55:57] = sram_blwl_wl[55:57] ; -wire [55:57] mux_1level_tapbuf_size3_45_configbus0_b; -assign mux_1level_tapbuf_size3_45_configbus0_b[55:57] = sram_blwl_blb[55:57] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_45_ (mux_1level_tapbuf_size3_45_inbus, chany_0__1__out_1_ , mux_1level_tapbuf_size3_45_sram_blwl_out[55:57] , -mux_1level_tapbuf_size3_45_sram_blwl_outb[55:57] ); -//----- SRAM bits for MUX[45], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_55_ (mux_1level_tapbuf_size3_45_sram_blwl_out[55:55] ,mux_1level_tapbuf_size3_45_sram_blwl_out[55:55] ,mux_1level_tapbuf_size3_45_sram_blwl_outb[55:55] ,mux_1level_tapbuf_size3_45_configbus0[55:55], mux_1level_tapbuf_size3_45_configbus1[55:55] , mux_1level_tapbuf_size3_45_configbus0_b[55:55] ); -sram6T_blwl sram_blwl_56_ (mux_1level_tapbuf_size3_45_sram_blwl_out[56:56] ,mux_1level_tapbuf_size3_45_sram_blwl_out[56:56] ,mux_1level_tapbuf_size3_45_sram_blwl_outb[56:56] ,mux_1level_tapbuf_size3_45_configbus0[56:56], mux_1level_tapbuf_size3_45_configbus1[56:56] , mux_1level_tapbuf_size3_45_configbus0_b[56:56] ); -sram6T_blwl sram_blwl_57_ (mux_1level_tapbuf_size3_45_sram_blwl_out[57:57] ,mux_1level_tapbuf_size3_45_sram_blwl_out[57:57] ,mux_1level_tapbuf_size3_45_sram_blwl_outb[57:57] ,mux_1level_tapbuf_size3_45_configbus0[57:57], mux_1level_tapbuf_size3_45_configbus1[57:57] , mux_1level_tapbuf_size3_45_configbus0_b[57:57] ); -wire [0:1] mux_1level_tapbuf_size2_46_inbus; -assign mux_1level_tapbuf_size2_46_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_46_inbus[1] = chanx_1__1__in_25_ ; -wire [58:58] mux_1level_tapbuf_size2_46_configbus0; -wire [58:58] mux_1level_tapbuf_size2_46_configbus1; -wire [58:58] mux_1level_tapbuf_size2_46_sram_blwl_out ; -wire [58:58] mux_1level_tapbuf_size2_46_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_46_configbus0[58:58] = sram_blwl_bl[58:58] ; -assign mux_1level_tapbuf_size2_46_configbus1[58:58] = sram_blwl_wl[58:58] ; -wire [58:58] mux_1level_tapbuf_size2_46_configbus0_b; -assign mux_1level_tapbuf_size2_46_configbus0_b[58:58] = sram_blwl_blb[58:58] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_46_ (mux_1level_tapbuf_size2_46_inbus, chany_0__1__out_3_ , mux_1level_tapbuf_size2_46_sram_blwl_out[58:58] , -mux_1level_tapbuf_size2_46_sram_blwl_outb[58:58] ); -//----- SRAM bits for MUX[46], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_58_ (mux_1level_tapbuf_size2_46_sram_blwl_out[58:58] ,mux_1level_tapbuf_size2_46_sram_blwl_out[58:58] ,mux_1level_tapbuf_size2_46_sram_blwl_outb[58:58] ,mux_1level_tapbuf_size2_46_configbus0[58:58], mux_1level_tapbuf_size2_46_configbus1[58:58] , mux_1level_tapbuf_size2_46_configbus0_b[58:58] ); -wire [0:1] mux_1level_tapbuf_size2_47_inbus; -assign mux_1level_tapbuf_size2_47_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_47_inbus[1] = chanx_1__1__in_23_ ; -wire [59:59] mux_1level_tapbuf_size2_47_configbus0; -wire [59:59] mux_1level_tapbuf_size2_47_configbus1; -wire [59:59] mux_1level_tapbuf_size2_47_sram_blwl_out ; -wire [59:59] mux_1level_tapbuf_size2_47_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_47_configbus0[59:59] = sram_blwl_bl[59:59] ; -assign mux_1level_tapbuf_size2_47_configbus1[59:59] = sram_blwl_wl[59:59] ; -wire [59:59] mux_1level_tapbuf_size2_47_configbus0_b; -assign mux_1level_tapbuf_size2_47_configbus0_b[59:59] = sram_blwl_blb[59:59] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_47_ (mux_1level_tapbuf_size2_47_inbus, chany_0__1__out_5_ , mux_1level_tapbuf_size2_47_sram_blwl_out[59:59] , -mux_1level_tapbuf_size2_47_sram_blwl_outb[59:59] ); -//----- SRAM bits for MUX[47], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_59_ (mux_1level_tapbuf_size2_47_sram_blwl_out[59:59] ,mux_1level_tapbuf_size2_47_sram_blwl_out[59:59] ,mux_1level_tapbuf_size2_47_sram_blwl_outb[59:59] ,mux_1level_tapbuf_size2_47_configbus0[59:59], mux_1level_tapbuf_size2_47_configbus1[59:59] , mux_1level_tapbuf_size2_47_configbus0_b[59:59] ); -wire [0:1] mux_1level_tapbuf_size2_48_inbus; -assign mux_1level_tapbuf_size2_48_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_48_inbus[1] = chanx_1__1__in_21_ ; -wire [60:60] mux_1level_tapbuf_size2_48_configbus0; -wire [60:60] mux_1level_tapbuf_size2_48_configbus1; -wire [60:60] mux_1level_tapbuf_size2_48_sram_blwl_out ; -wire [60:60] mux_1level_tapbuf_size2_48_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_48_configbus0[60:60] = sram_blwl_bl[60:60] ; -assign mux_1level_tapbuf_size2_48_configbus1[60:60] = sram_blwl_wl[60:60] ; -wire [60:60] mux_1level_tapbuf_size2_48_configbus0_b; -assign mux_1level_tapbuf_size2_48_configbus0_b[60:60] = sram_blwl_blb[60:60] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_48_ (mux_1level_tapbuf_size2_48_inbus, chany_0__1__out_7_ , mux_1level_tapbuf_size2_48_sram_blwl_out[60:60] , -mux_1level_tapbuf_size2_48_sram_blwl_outb[60:60] ); -//----- SRAM bits for MUX[48], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_60_ (mux_1level_tapbuf_size2_48_sram_blwl_out[60:60] ,mux_1level_tapbuf_size2_48_sram_blwl_out[60:60] ,mux_1level_tapbuf_size2_48_sram_blwl_outb[60:60] ,mux_1level_tapbuf_size2_48_configbus0[60:60], mux_1level_tapbuf_size2_48_configbus1[60:60] , mux_1level_tapbuf_size2_48_configbus0_b[60:60] ); -wire [0:1] mux_1level_tapbuf_size2_49_inbus; -assign mux_1level_tapbuf_size2_49_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_49_inbus[1] = chanx_1__1__in_19_ ; -wire [61:61] mux_1level_tapbuf_size2_49_configbus0; -wire [61:61] mux_1level_tapbuf_size2_49_configbus1; -wire [61:61] mux_1level_tapbuf_size2_49_sram_blwl_out ; -wire [61:61] mux_1level_tapbuf_size2_49_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_49_configbus0[61:61] = sram_blwl_bl[61:61] ; -assign mux_1level_tapbuf_size2_49_configbus1[61:61] = sram_blwl_wl[61:61] ; -wire [61:61] mux_1level_tapbuf_size2_49_configbus0_b; -assign mux_1level_tapbuf_size2_49_configbus0_b[61:61] = sram_blwl_blb[61:61] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_49_ (mux_1level_tapbuf_size2_49_inbus, chany_0__1__out_9_ , mux_1level_tapbuf_size2_49_sram_blwl_out[61:61] , -mux_1level_tapbuf_size2_49_sram_blwl_outb[61:61] ); -//----- SRAM bits for MUX[49], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_61_ (mux_1level_tapbuf_size2_49_sram_blwl_out[61:61] ,mux_1level_tapbuf_size2_49_sram_blwl_out[61:61] ,mux_1level_tapbuf_size2_49_sram_blwl_outb[61:61] ,mux_1level_tapbuf_size2_49_configbus0[61:61], mux_1level_tapbuf_size2_49_configbus1[61:61] , mux_1level_tapbuf_size2_49_configbus0_b[61:61] ); -wire [0:1] mux_1level_tapbuf_size2_50_inbus; -assign mux_1level_tapbuf_size2_50_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_50_inbus[1] = chanx_1__1__in_17_ ; -wire [62:62] mux_1level_tapbuf_size2_50_configbus0; -wire [62:62] mux_1level_tapbuf_size2_50_configbus1; -wire [62:62] mux_1level_tapbuf_size2_50_sram_blwl_out ; -wire [62:62] mux_1level_tapbuf_size2_50_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_50_configbus0[62:62] = sram_blwl_bl[62:62] ; -assign mux_1level_tapbuf_size2_50_configbus1[62:62] = sram_blwl_wl[62:62] ; -wire [62:62] mux_1level_tapbuf_size2_50_configbus0_b; -assign mux_1level_tapbuf_size2_50_configbus0_b[62:62] = sram_blwl_blb[62:62] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_50_ (mux_1level_tapbuf_size2_50_inbus, chany_0__1__out_11_ , mux_1level_tapbuf_size2_50_sram_blwl_out[62:62] , -mux_1level_tapbuf_size2_50_sram_blwl_outb[62:62] ); -//----- SRAM bits for MUX[50], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_62_ (mux_1level_tapbuf_size2_50_sram_blwl_out[62:62] ,mux_1level_tapbuf_size2_50_sram_blwl_out[62:62] ,mux_1level_tapbuf_size2_50_sram_blwl_outb[62:62] ,mux_1level_tapbuf_size2_50_configbus0[62:62], mux_1level_tapbuf_size2_50_configbus1[62:62] , mux_1level_tapbuf_size2_50_configbus0_b[62:62] ); -wire [0:1] mux_1level_tapbuf_size2_51_inbus; -assign mux_1level_tapbuf_size2_51_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_51_inbus[1] = chanx_1__1__in_15_ ; -wire [63:63] mux_1level_tapbuf_size2_51_configbus0; -wire [63:63] mux_1level_tapbuf_size2_51_configbus1; -wire [63:63] mux_1level_tapbuf_size2_51_sram_blwl_out ; -wire [63:63] mux_1level_tapbuf_size2_51_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_51_configbus0[63:63] = sram_blwl_bl[63:63] ; -assign mux_1level_tapbuf_size2_51_configbus1[63:63] = sram_blwl_wl[63:63] ; -wire [63:63] mux_1level_tapbuf_size2_51_configbus0_b; -assign mux_1level_tapbuf_size2_51_configbus0_b[63:63] = sram_blwl_blb[63:63] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_51_ (mux_1level_tapbuf_size2_51_inbus, chany_0__1__out_13_ , mux_1level_tapbuf_size2_51_sram_blwl_out[63:63] , -mux_1level_tapbuf_size2_51_sram_blwl_outb[63:63] ); -//----- SRAM bits for MUX[51], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_63_ (mux_1level_tapbuf_size2_51_sram_blwl_out[63:63] ,mux_1level_tapbuf_size2_51_sram_blwl_out[63:63] ,mux_1level_tapbuf_size2_51_sram_blwl_outb[63:63] ,mux_1level_tapbuf_size2_51_configbus0[63:63], mux_1level_tapbuf_size2_51_configbus1[63:63] , mux_1level_tapbuf_size2_51_configbus0_b[63:63] ); -wire [0:1] mux_1level_tapbuf_size2_52_inbus; -assign mux_1level_tapbuf_size2_52_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_52_inbus[1] = chanx_1__1__in_13_ ; -wire [64:64] mux_1level_tapbuf_size2_52_configbus0; -wire [64:64] mux_1level_tapbuf_size2_52_configbus1; -wire [64:64] mux_1level_tapbuf_size2_52_sram_blwl_out ; -wire [64:64] mux_1level_tapbuf_size2_52_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_52_configbus0[64:64] = sram_blwl_bl[64:64] ; -assign mux_1level_tapbuf_size2_52_configbus1[64:64] = sram_blwl_wl[64:64] ; -wire [64:64] mux_1level_tapbuf_size2_52_configbus0_b; -assign mux_1level_tapbuf_size2_52_configbus0_b[64:64] = sram_blwl_blb[64:64] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_52_ (mux_1level_tapbuf_size2_52_inbus, chany_0__1__out_15_ , mux_1level_tapbuf_size2_52_sram_blwl_out[64:64] , -mux_1level_tapbuf_size2_52_sram_blwl_outb[64:64] ); -//----- SRAM bits for MUX[52], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_64_ (mux_1level_tapbuf_size2_52_sram_blwl_out[64:64] ,mux_1level_tapbuf_size2_52_sram_blwl_out[64:64] ,mux_1level_tapbuf_size2_52_sram_blwl_outb[64:64] ,mux_1level_tapbuf_size2_52_configbus0[64:64], mux_1level_tapbuf_size2_52_configbus1[64:64] , mux_1level_tapbuf_size2_52_configbus0_b[64:64] ); -wire [0:1] mux_1level_tapbuf_size2_53_inbus; -assign mux_1level_tapbuf_size2_53_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_53_inbus[1] = chanx_1__1__in_11_ ; -wire [65:65] mux_1level_tapbuf_size2_53_configbus0; -wire [65:65] mux_1level_tapbuf_size2_53_configbus1; -wire [65:65] mux_1level_tapbuf_size2_53_sram_blwl_out ; -wire [65:65] mux_1level_tapbuf_size2_53_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_53_configbus0[65:65] = sram_blwl_bl[65:65] ; -assign mux_1level_tapbuf_size2_53_configbus1[65:65] = sram_blwl_wl[65:65] ; -wire [65:65] mux_1level_tapbuf_size2_53_configbus0_b; -assign mux_1level_tapbuf_size2_53_configbus0_b[65:65] = sram_blwl_blb[65:65] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_53_ (mux_1level_tapbuf_size2_53_inbus, chany_0__1__out_17_ , mux_1level_tapbuf_size2_53_sram_blwl_out[65:65] , -mux_1level_tapbuf_size2_53_sram_blwl_outb[65:65] ); -//----- SRAM bits for MUX[53], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_65_ (mux_1level_tapbuf_size2_53_sram_blwl_out[65:65] ,mux_1level_tapbuf_size2_53_sram_blwl_out[65:65] ,mux_1level_tapbuf_size2_53_sram_blwl_outb[65:65] ,mux_1level_tapbuf_size2_53_configbus0[65:65], mux_1level_tapbuf_size2_53_configbus1[65:65] , mux_1level_tapbuf_size2_53_configbus0_b[65:65] ); -wire [0:1] mux_1level_tapbuf_size2_54_inbus; -assign mux_1level_tapbuf_size2_54_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_54_inbus[1] = chanx_1__1__in_9_ ; -wire [66:66] mux_1level_tapbuf_size2_54_configbus0; -wire [66:66] mux_1level_tapbuf_size2_54_configbus1; -wire [66:66] mux_1level_tapbuf_size2_54_sram_blwl_out ; -wire [66:66] mux_1level_tapbuf_size2_54_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_54_configbus0[66:66] = sram_blwl_bl[66:66] ; -assign mux_1level_tapbuf_size2_54_configbus1[66:66] = sram_blwl_wl[66:66] ; -wire [66:66] mux_1level_tapbuf_size2_54_configbus0_b; -assign mux_1level_tapbuf_size2_54_configbus0_b[66:66] = sram_blwl_blb[66:66] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_54_ (mux_1level_tapbuf_size2_54_inbus, chany_0__1__out_19_ , mux_1level_tapbuf_size2_54_sram_blwl_out[66:66] , -mux_1level_tapbuf_size2_54_sram_blwl_outb[66:66] ); -//----- SRAM bits for MUX[54], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_66_ (mux_1level_tapbuf_size2_54_sram_blwl_out[66:66] ,mux_1level_tapbuf_size2_54_sram_blwl_out[66:66] ,mux_1level_tapbuf_size2_54_sram_blwl_outb[66:66] ,mux_1level_tapbuf_size2_54_configbus0[66:66], mux_1level_tapbuf_size2_54_configbus1[66:66] , mux_1level_tapbuf_size2_54_configbus0_b[66:66] ); -wire [0:1] mux_1level_tapbuf_size2_55_inbus; -assign mux_1level_tapbuf_size2_55_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_55_inbus[1] = chanx_1__1__in_7_ ; -wire [67:67] mux_1level_tapbuf_size2_55_configbus0; -wire [67:67] mux_1level_tapbuf_size2_55_configbus1; -wire [67:67] mux_1level_tapbuf_size2_55_sram_blwl_out ; -wire [67:67] mux_1level_tapbuf_size2_55_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_55_configbus0[67:67] = sram_blwl_bl[67:67] ; -assign mux_1level_tapbuf_size2_55_configbus1[67:67] = sram_blwl_wl[67:67] ; -wire [67:67] mux_1level_tapbuf_size2_55_configbus0_b; -assign mux_1level_tapbuf_size2_55_configbus0_b[67:67] = sram_blwl_blb[67:67] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_55_ (mux_1level_tapbuf_size2_55_inbus, chany_0__1__out_21_ , mux_1level_tapbuf_size2_55_sram_blwl_out[67:67] , -mux_1level_tapbuf_size2_55_sram_blwl_outb[67:67] ); -//----- SRAM bits for MUX[55], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_67_ (mux_1level_tapbuf_size2_55_sram_blwl_out[67:67] ,mux_1level_tapbuf_size2_55_sram_blwl_out[67:67] ,mux_1level_tapbuf_size2_55_sram_blwl_outb[67:67] ,mux_1level_tapbuf_size2_55_configbus0[67:67], mux_1level_tapbuf_size2_55_configbus1[67:67] , mux_1level_tapbuf_size2_55_configbus0_b[67:67] ); -wire [0:1] mux_1level_tapbuf_size2_56_inbus; -assign mux_1level_tapbuf_size2_56_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_56_inbus[1] = chanx_1__1__in_5_ ; -wire [68:68] mux_1level_tapbuf_size2_56_configbus0; -wire [68:68] mux_1level_tapbuf_size2_56_configbus1; -wire [68:68] mux_1level_tapbuf_size2_56_sram_blwl_out ; -wire [68:68] mux_1level_tapbuf_size2_56_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_56_configbus0[68:68] = sram_blwl_bl[68:68] ; -assign mux_1level_tapbuf_size2_56_configbus1[68:68] = sram_blwl_wl[68:68] ; -wire [68:68] mux_1level_tapbuf_size2_56_configbus0_b; -assign mux_1level_tapbuf_size2_56_configbus0_b[68:68] = sram_blwl_blb[68:68] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_56_ (mux_1level_tapbuf_size2_56_inbus, chany_0__1__out_23_ , mux_1level_tapbuf_size2_56_sram_blwl_out[68:68] , -mux_1level_tapbuf_size2_56_sram_blwl_outb[68:68] ); -//----- SRAM bits for MUX[56], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_68_ (mux_1level_tapbuf_size2_56_sram_blwl_out[68:68] ,mux_1level_tapbuf_size2_56_sram_blwl_out[68:68] ,mux_1level_tapbuf_size2_56_sram_blwl_outb[68:68] ,mux_1level_tapbuf_size2_56_configbus0[68:68], mux_1level_tapbuf_size2_56_configbus1[68:68] , mux_1level_tapbuf_size2_56_configbus0_b[68:68] ); -wire [0:1] mux_1level_tapbuf_size2_57_inbus; -assign mux_1level_tapbuf_size2_57_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_57_inbus[1] = chanx_1__1__in_3_ ; -wire [69:69] mux_1level_tapbuf_size2_57_configbus0; -wire [69:69] mux_1level_tapbuf_size2_57_configbus1; -wire [69:69] mux_1level_tapbuf_size2_57_sram_blwl_out ; -wire [69:69] mux_1level_tapbuf_size2_57_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_57_configbus0[69:69] = sram_blwl_bl[69:69] ; -assign mux_1level_tapbuf_size2_57_configbus1[69:69] = sram_blwl_wl[69:69] ; -wire [69:69] mux_1level_tapbuf_size2_57_configbus0_b; -assign mux_1level_tapbuf_size2_57_configbus0_b[69:69] = sram_blwl_blb[69:69] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_57_ (mux_1level_tapbuf_size2_57_inbus, chany_0__1__out_25_ , mux_1level_tapbuf_size2_57_sram_blwl_out[69:69] , -mux_1level_tapbuf_size2_57_sram_blwl_outb[69:69] ); -//----- SRAM bits for MUX[57], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_69_ (mux_1level_tapbuf_size2_57_sram_blwl_out[69:69] ,mux_1level_tapbuf_size2_57_sram_blwl_out[69:69] ,mux_1level_tapbuf_size2_57_sram_blwl_outb[69:69] ,mux_1level_tapbuf_size2_57_configbus0[69:69], mux_1level_tapbuf_size2_57_configbus1[69:69] , mux_1level_tapbuf_size2_57_configbus0_b[69:69] ); -wire [0:1] mux_1level_tapbuf_size2_58_inbus; -assign mux_1level_tapbuf_size2_58_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_58_inbus[1] = chanx_1__1__in_1_ ; -wire [70:70] mux_1level_tapbuf_size2_58_configbus0; -wire [70:70] mux_1level_tapbuf_size2_58_configbus1; -wire [70:70] mux_1level_tapbuf_size2_58_sram_blwl_out ; -wire [70:70] mux_1level_tapbuf_size2_58_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_58_configbus0[70:70] = sram_blwl_bl[70:70] ; -assign mux_1level_tapbuf_size2_58_configbus1[70:70] = sram_blwl_wl[70:70] ; -wire [70:70] mux_1level_tapbuf_size2_58_configbus0_b; -assign mux_1level_tapbuf_size2_58_configbus0_b[70:70] = sram_blwl_blb[70:70] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_58_ (mux_1level_tapbuf_size2_58_inbus, chany_0__1__out_27_ , mux_1level_tapbuf_size2_58_sram_blwl_out[70:70] , -mux_1level_tapbuf_size2_58_sram_blwl_outb[70:70] ); -//----- SRAM bits for MUX[58], level=1, select_path_id=1. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----0----- -sram6T_blwl sram_blwl_70_ (mux_1level_tapbuf_size2_58_sram_blwl_out[70:70] ,mux_1level_tapbuf_size2_58_sram_blwl_out[70:70] ,mux_1level_tapbuf_size2_58_sram_blwl_outb[70:70] ,mux_1level_tapbuf_size2_58_configbus0[70:70], mux_1level_tapbuf_size2_58_configbus1[70:70] , mux_1level_tapbuf_size2_58_configbus0_b[70:70] ); -wire [0:1] mux_1level_tapbuf_size2_59_inbus; -assign mux_1level_tapbuf_size2_59_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_59_inbus[1] = chanx_1__1__in_29_ ; -wire [71:71] mux_1level_tapbuf_size2_59_configbus0; -wire [71:71] mux_1level_tapbuf_size2_59_configbus1; -wire [71:71] mux_1level_tapbuf_size2_59_sram_blwl_out ; -wire [71:71] mux_1level_tapbuf_size2_59_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_59_configbus0[71:71] = sram_blwl_bl[71:71] ; -assign mux_1level_tapbuf_size2_59_configbus1[71:71] = sram_blwl_wl[71:71] ; -wire [71:71] mux_1level_tapbuf_size2_59_configbus0_b; -assign mux_1level_tapbuf_size2_59_configbus0_b[71:71] = sram_blwl_blb[71:71] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_59_ (mux_1level_tapbuf_size2_59_inbus, chany_0__1__out_29_ , mux_1level_tapbuf_size2_59_sram_blwl_out[71:71] , -mux_1level_tapbuf_size2_59_sram_blwl_outb[71:71] ); -//----- SRAM bits for MUX[59], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_71_ (mux_1level_tapbuf_size2_59_sram_blwl_out[71:71] ,mux_1level_tapbuf_size2_59_sram_blwl_out[71:71] ,mux_1level_tapbuf_size2_59_sram_blwl_outb[71:71] ,mux_1level_tapbuf_size2_59_configbus0[71:71], mux_1level_tapbuf_size2_59_configbus1[71:71] , mux_1level_tapbuf_size2_59_configbus0_b[71:71] ); -//----- left side Multiplexers ----- -endmodule -//----- END Verilog Module of Switch Box[0][1] ----- - diff --git a/examples/verilog_test_example_1/routing/sb_1_0.v b/examples/verilog_test_example_1/routing/sb_1_0.v deleted file mode 100644 index d84137bec..000000000 --- a/examples/verilog_test_example_1/routing/sb_1_0.v +++ /dev/null @@ -1,627 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Switch Block [1][0] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Switch Box[1][0] ----- -module sb_1__0_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -//----- Inputs/outputs of top side ----- - output chany_1__1__out_0_, - input chany_1__1__in_1_, - output chany_1__1__out_2_, - input chany_1__1__in_3_, - output chany_1__1__out_4_, - input chany_1__1__in_5_, - output chany_1__1__out_6_, - input chany_1__1__in_7_, - output chany_1__1__out_8_, - input chany_1__1__in_9_, - output chany_1__1__out_10_, - input chany_1__1__in_11_, - output chany_1__1__out_12_, - input chany_1__1__in_13_, - output chany_1__1__out_14_, - input chany_1__1__in_15_, - output chany_1__1__out_16_, - input chany_1__1__in_17_, - output chany_1__1__out_18_, - input chany_1__1__in_19_, - output chany_1__1__out_20_, - input chany_1__1__in_21_, - output chany_1__1__out_22_, - input chany_1__1__in_23_, - output chany_1__1__out_24_, - input chany_1__1__in_25_, - output chany_1__1__out_26_, - input chany_1__1__in_27_, - output chany_1__1__out_28_, - input chany_1__1__in_29_, -input grid_2__1__pin_0__3__1_, -input grid_2__1__pin_0__3__3_, -input grid_2__1__pin_0__3__5_, -input grid_2__1__pin_0__3__7_, -input grid_2__1__pin_0__3__9_, -input grid_2__1__pin_0__3__11_, -input grid_2__1__pin_0__3__13_, -input grid_2__1__pin_0__3__15_, -//----- Inputs/outputs of right side ----- -//----- Inputs/outputs of bottom side ----- -//----- Inputs/outputs of left side ----- - input chanx_1__0__in_0_, - output chanx_1__0__out_1_, - input chanx_1__0__in_2_, - output chanx_1__0__out_3_, - input chanx_1__0__in_4_, - output chanx_1__0__out_5_, - input chanx_1__0__in_6_, - output chanx_1__0__out_7_, - input chanx_1__0__in_8_, - output chanx_1__0__out_9_, - input chanx_1__0__in_10_, - output chanx_1__0__out_11_, - input chanx_1__0__in_12_, - output chanx_1__0__out_13_, - input chanx_1__0__in_14_, - output chanx_1__0__out_15_, - input chanx_1__0__in_16_, - output chanx_1__0__out_17_, - input chanx_1__0__in_18_, - output chanx_1__0__out_19_, - input chanx_1__0__in_20_, - output chanx_1__0__out_21_, - input chanx_1__0__in_22_, - output chanx_1__0__out_23_, - input chanx_1__0__in_24_, - output chanx_1__0__out_25_, - input chanx_1__0__in_26_, - output chanx_1__0__out_27_, - input chanx_1__0__in_28_, - output chanx_1__0__out_29_, -input grid_1__0__pin_0__0__1_, -input grid_1__0__pin_0__0__3_, -input grid_1__0__pin_0__0__5_, -input grid_1__0__pin_0__0__7_, -input grid_1__0__pin_0__0__9_, -input grid_1__0__pin_0__0__11_, -input grid_1__0__pin_0__0__13_, -input grid_1__0__pin_0__0__15_, -input [72:105] sram_blwl_bl , -input [72:105] sram_blwl_wl , -input [72:105] sram_blwl_blb ); -//----- top side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_60_inbus; -assign mux_1level_tapbuf_size3_60_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size3_60_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_60_inbus[2] = chanx_1__0__in_0_ ; -wire [72:74] mux_1level_tapbuf_size3_60_configbus0; -wire [72:74] mux_1level_tapbuf_size3_60_configbus1; -wire [72:74] mux_1level_tapbuf_size3_60_sram_blwl_out ; -wire [72:74] mux_1level_tapbuf_size3_60_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_60_configbus0[72:74] = sram_blwl_bl[72:74] ; -assign mux_1level_tapbuf_size3_60_configbus1[72:74] = sram_blwl_wl[72:74] ; -wire [72:74] mux_1level_tapbuf_size3_60_configbus0_b; -assign mux_1level_tapbuf_size3_60_configbus0_b[72:74] = sram_blwl_blb[72:74] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_60_ (mux_1level_tapbuf_size3_60_inbus, chany_1__1__out_0_ , mux_1level_tapbuf_size3_60_sram_blwl_out[72:74] , -mux_1level_tapbuf_size3_60_sram_blwl_outb[72:74] ); -//----- SRAM bits for MUX[60], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_72_ (mux_1level_tapbuf_size3_60_sram_blwl_out[72:72] ,mux_1level_tapbuf_size3_60_sram_blwl_out[72:72] ,mux_1level_tapbuf_size3_60_sram_blwl_outb[72:72] ,mux_1level_tapbuf_size3_60_configbus0[72:72], mux_1level_tapbuf_size3_60_configbus1[72:72] , mux_1level_tapbuf_size3_60_configbus0_b[72:72] ); -sram6T_blwl sram_blwl_73_ (mux_1level_tapbuf_size3_60_sram_blwl_out[73:73] ,mux_1level_tapbuf_size3_60_sram_blwl_out[73:73] ,mux_1level_tapbuf_size3_60_sram_blwl_outb[73:73] ,mux_1level_tapbuf_size3_60_configbus0[73:73], mux_1level_tapbuf_size3_60_configbus1[73:73] , mux_1level_tapbuf_size3_60_configbus0_b[73:73] ); -sram6T_blwl sram_blwl_74_ (mux_1level_tapbuf_size3_60_sram_blwl_out[74:74] ,mux_1level_tapbuf_size3_60_sram_blwl_out[74:74] ,mux_1level_tapbuf_size3_60_sram_blwl_outb[74:74] ,mux_1level_tapbuf_size3_60_configbus0[74:74], mux_1level_tapbuf_size3_60_configbus1[74:74] , mux_1level_tapbuf_size3_60_configbus0_b[74:74] ); -wire [0:1] mux_1level_tapbuf_size2_61_inbus; -assign mux_1level_tapbuf_size2_61_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_61_inbus[1] = chanx_1__0__in_28_ ; -wire [75:75] mux_1level_tapbuf_size2_61_configbus0; -wire [75:75] mux_1level_tapbuf_size2_61_configbus1; -wire [75:75] mux_1level_tapbuf_size2_61_sram_blwl_out ; -wire [75:75] mux_1level_tapbuf_size2_61_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_61_configbus0[75:75] = sram_blwl_bl[75:75] ; -assign mux_1level_tapbuf_size2_61_configbus1[75:75] = sram_blwl_wl[75:75] ; -wire [75:75] mux_1level_tapbuf_size2_61_configbus0_b; -assign mux_1level_tapbuf_size2_61_configbus0_b[75:75] = sram_blwl_blb[75:75] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_61_ (mux_1level_tapbuf_size2_61_inbus, chany_1__1__out_2_ , mux_1level_tapbuf_size2_61_sram_blwl_out[75:75] , -mux_1level_tapbuf_size2_61_sram_blwl_outb[75:75] ); -//----- SRAM bits for MUX[61], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_75_ (mux_1level_tapbuf_size2_61_sram_blwl_out[75:75] ,mux_1level_tapbuf_size2_61_sram_blwl_out[75:75] ,mux_1level_tapbuf_size2_61_sram_blwl_outb[75:75] ,mux_1level_tapbuf_size2_61_configbus0[75:75], mux_1level_tapbuf_size2_61_configbus1[75:75] , mux_1level_tapbuf_size2_61_configbus0_b[75:75] ); -wire [0:1] mux_1level_tapbuf_size2_62_inbus; -assign mux_1level_tapbuf_size2_62_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_62_inbus[1] = chanx_1__0__in_26_ ; -wire [76:76] mux_1level_tapbuf_size2_62_configbus0; -wire [76:76] mux_1level_tapbuf_size2_62_configbus1; -wire [76:76] mux_1level_tapbuf_size2_62_sram_blwl_out ; -wire [76:76] mux_1level_tapbuf_size2_62_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_62_configbus0[76:76] = sram_blwl_bl[76:76] ; -assign mux_1level_tapbuf_size2_62_configbus1[76:76] = sram_blwl_wl[76:76] ; -wire [76:76] mux_1level_tapbuf_size2_62_configbus0_b; -assign mux_1level_tapbuf_size2_62_configbus0_b[76:76] = sram_blwl_blb[76:76] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_62_ (mux_1level_tapbuf_size2_62_inbus, chany_1__1__out_4_ , mux_1level_tapbuf_size2_62_sram_blwl_out[76:76] , -mux_1level_tapbuf_size2_62_sram_blwl_outb[76:76] ); -//----- SRAM bits for MUX[62], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_76_ (mux_1level_tapbuf_size2_62_sram_blwl_out[76:76] ,mux_1level_tapbuf_size2_62_sram_blwl_out[76:76] ,mux_1level_tapbuf_size2_62_sram_blwl_outb[76:76] ,mux_1level_tapbuf_size2_62_configbus0[76:76], mux_1level_tapbuf_size2_62_configbus1[76:76] , mux_1level_tapbuf_size2_62_configbus0_b[76:76] ); -wire [0:1] mux_1level_tapbuf_size2_63_inbus; -assign mux_1level_tapbuf_size2_63_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_63_inbus[1] = chanx_1__0__in_24_ ; -wire [77:77] mux_1level_tapbuf_size2_63_configbus0; -wire [77:77] mux_1level_tapbuf_size2_63_configbus1; -wire [77:77] mux_1level_tapbuf_size2_63_sram_blwl_out ; -wire [77:77] mux_1level_tapbuf_size2_63_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_63_configbus0[77:77] = sram_blwl_bl[77:77] ; -assign mux_1level_tapbuf_size2_63_configbus1[77:77] = sram_blwl_wl[77:77] ; -wire [77:77] mux_1level_tapbuf_size2_63_configbus0_b; -assign mux_1level_tapbuf_size2_63_configbus0_b[77:77] = sram_blwl_blb[77:77] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_63_ (mux_1level_tapbuf_size2_63_inbus, chany_1__1__out_6_ , mux_1level_tapbuf_size2_63_sram_blwl_out[77:77] , -mux_1level_tapbuf_size2_63_sram_blwl_outb[77:77] ); -//----- SRAM bits for MUX[63], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_77_ (mux_1level_tapbuf_size2_63_sram_blwl_out[77:77] ,mux_1level_tapbuf_size2_63_sram_blwl_out[77:77] ,mux_1level_tapbuf_size2_63_sram_blwl_outb[77:77] ,mux_1level_tapbuf_size2_63_configbus0[77:77], mux_1level_tapbuf_size2_63_configbus1[77:77] , mux_1level_tapbuf_size2_63_configbus0_b[77:77] ); -wire [0:1] mux_1level_tapbuf_size2_64_inbus; -assign mux_1level_tapbuf_size2_64_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_64_inbus[1] = chanx_1__0__in_22_ ; -wire [78:78] mux_1level_tapbuf_size2_64_configbus0; -wire [78:78] mux_1level_tapbuf_size2_64_configbus1; -wire [78:78] mux_1level_tapbuf_size2_64_sram_blwl_out ; -wire [78:78] mux_1level_tapbuf_size2_64_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_64_configbus0[78:78] = sram_blwl_bl[78:78] ; -assign mux_1level_tapbuf_size2_64_configbus1[78:78] = sram_blwl_wl[78:78] ; -wire [78:78] mux_1level_tapbuf_size2_64_configbus0_b; -assign mux_1level_tapbuf_size2_64_configbus0_b[78:78] = sram_blwl_blb[78:78] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_64_ (mux_1level_tapbuf_size2_64_inbus, chany_1__1__out_8_ , mux_1level_tapbuf_size2_64_sram_blwl_out[78:78] , -mux_1level_tapbuf_size2_64_sram_blwl_outb[78:78] ); -//----- SRAM bits for MUX[64], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_78_ (mux_1level_tapbuf_size2_64_sram_blwl_out[78:78] ,mux_1level_tapbuf_size2_64_sram_blwl_out[78:78] ,mux_1level_tapbuf_size2_64_sram_blwl_outb[78:78] ,mux_1level_tapbuf_size2_64_configbus0[78:78], mux_1level_tapbuf_size2_64_configbus1[78:78] , mux_1level_tapbuf_size2_64_configbus0_b[78:78] ); -wire [0:1] mux_1level_tapbuf_size2_65_inbus; -assign mux_1level_tapbuf_size2_65_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_65_inbus[1] = chanx_1__0__in_20_ ; -wire [79:79] mux_1level_tapbuf_size2_65_configbus0; -wire [79:79] mux_1level_tapbuf_size2_65_configbus1; -wire [79:79] mux_1level_tapbuf_size2_65_sram_blwl_out ; -wire [79:79] mux_1level_tapbuf_size2_65_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_65_configbus0[79:79] = sram_blwl_bl[79:79] ; -assign mux_1level_tapbuf_size2_65_configbus1[79:79] = sram_blwl_wl[79:79] ; -wire [79:79] mux_1level_tapbuf_size2_65_configbus0_b; -assign mux_1level_tapbuf_size2_65_configbus0_b[79:79] = sram_blwl_blb[79:79] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_65_ (mux_1level_tapbuf_size2_65_inbus, chany_1__1__out_10_ , mux_1level_tapbuf_size2_65_sram_blwl_out[79:79] , -mux_1level_tapbuf_size2_65_sram_blwl_outb[79:79] ); -//----- SRAM bits for MUX[65], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_79_ (mux_1level_tapbuf_size2_65_sram_blwl_out[79:79] ,mux_1level_tapbuf_size2_65_sram_blwl_out[79:79] ,mux_1level_tapbuf_size2_65_sram_blwl_outb[79:79] ,mux_1level_tapbuf_size2_65_configbus0[79:79], mux_1level_tapbuf_size2_65_configbus1[79:79] , mux_1level_tapbuf_size2_65_configbus0_b[79:79] ); -wire [0:1] mux_1level_tapbuf_size2_66_inbus; -assign mux_1level_tapbuf_size2_66_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_66_inbus[1] = chanx_1__0__in_18_ ; -wire [80:80] mux_1level_tapbuf_size2_66_configbus0; -wire [80:80] mux_1level_tapbuf_size2_66_configbus1; -wire [80:80] mux_1level_tapbuf_size2_66_sram_blwl_out ; -wire [80:80] mux_1level_tapbuf_size2_66_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_66_configbus0[80:80] = sram_blwl_bl[80:80] ; -assign mux_1level_tapbuf_size2_66_configbus1[80:80] = sram_blwl_wl[80:80] ; -wire [80:80] mux_1level_tapbuf_size2_66_configbus0_b; -assign mux_1level_tapbuf_size2_66_configbus0_b[80:80] = sram_blwl_blb[80:80] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_66_ (mux_1level_tapbuf_size2_66_inbus, chany_1__1__out_12_ , mux_1level_tapbuf_size2_66_sram_blwl_out[80:80] , -mux_1level_tapbuf_size2_66_sram_blwl_outb[80:80] ); -//----- SRAM bits for MUX[66], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_80_ (mux_1level_tapbuf_size2_66_sram_blwl_out[80:80] ,mux_1level_tapbuf_size2_66_sram_blwl_out[80:80] ,mux_1level_tapbuf_size2_66_sram_blwl_outb[80:80] ,mux_1level_tapbuf_size2_66_configbus0[80:80], mux_1level_tapbuf_size2_66_configbus1[80:80] , mux_1level_tapbuf_size2_66_configbus0_b[80:80] ); -wire [0:1] mux_1level_tapbuf_size2_67_inbus; -assign mux_1level_tapbuf_size2_67_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_67_inbus[1] = chanx_1__0__in_16_ ; -wire [81:81] mux_1level_tapbuf_size2_67_configbus0; -wire [81:81] mux_1level_tapbuf_size2_67_configbus1; -wire [81:81] mux_1level_tapbuf_size2_67_sram_blwl_out ; -wire [81:81] mux_1level_tapbuf_size2_67_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_67_configbus0[81:81] = sram_blwl_bl[81:81] ; -assign mux_1level_tapbuf_size2_67_configbus1[81:81] = sram_blwl_wl[81:81] ; -wire [81:81] mux_1level_tapbuf_size2_67_configbus0_b; -assign mux_1level_tapbuf_size2_67_configbus0_b[81:81] = sram_blwl_blb[81:81] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_67_ (mux_1level_tapbuf_size2_67_inbus, chany_1__1__out_14_ , mux_1level_tapbuf_size2_67_sram_blwl_out[81:81] , -mux_1level_tapbuf_size2_67_sram_blwl_outb[81:81] ); -//----- SRAM bits for MUX[67], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_81_ (mux_1level_tapbuf_size2_67_sram_blwl_out[81:81] ,mux_1level_tapbuf_size2_67_sram_blwl_out[81:81] ,mux_1level_tapbuf_size2_67_sram_blwl_outb[81:81] ,mux_1level_tapbuf_size2_67_configbus0[81:81], mux_1level_tapbuf_size2_67_configbus1[81:81] , mux_1level_tapbuf_size2_67_configbus0_b[81:81] ); -wire [0:1] mux_1level_tapbuf_size2_68_inbus; -assign mux_1level_tapbuf_size2_68_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_68_inbus[1] = chanx_1__0__in_14_ ; -wire [82:82] mux_1level_tapbuf_size2_68_configbus0; -wire [82:82] mux_1level_tapbuf_size2_68_configbus1; -wire [82:82] mux_1level_tapbuf_size2_68_sram_blwl_out ; -wire [82:82] mux_1level_tapbuf_size2_68_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_68_configbus0[82:82] = sram_blwl_bl[82:82] ; -assign mux_1level_tapbuf_size2_68_configbus1[82:82] = sram_blwl_wl[82:82] ; -wire [82:82] mux_1level_tapbuf_size2_68_configbus0_b; -assign mux_1level_tapbuf_size2_68_configbus0_b[82:82] = sram_blwl_blb[82:82] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_68_ (mux_1level_tapbuf_size2_68_inbus, chany_1__1__out_16_ , mux_1level_tapbuf_size2_68_sram_blwl_out[82:82] , -mux_1level_tapbuf_size2_68_sram_blwl_outb[82:82] ); -//----- SRAM bits for MUX[68], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_82_ (mux_1level_tapbuf_size2_68_sram_blwl_out[82:82] ,mux_1level_tapbuf_size2_68_sram_blwl_out[82:82] ,mux_1level_tapbuf_size2_68_sram_blwl_outb[82:82] ,mux_1level_tapbuf_size2_68_configbus0[82:82], mux_1level_tapbuf_size2_68_configbus1[82:82] , mux_1level_tapbuf_size2_68_configbus0_b[82:82] ); -wire [0:1] mux_1level_tapbuf_size2_69_inbus; -assign mux_1level_tapbuf_size2_69_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_69_inbus[1] = chanx_1__0__in_12_ ; -wire [83:83] mux_1level_tapbuf_size2_69_configbus0; -wire [83:83] mux_1level_tapbuf_size2_69_configbus1; -wire [83:83] mux_1level_tapbuf_size2_69_sram_blwl_out ; -wire [83:83] mux_1level_tapbuf_size2_69_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_69_configbus0[83:83] = sram_blwl_bl[83:83] ; -assign mux_1level_tapbuf_size2_69_configbus1[83:83] = sram_blwl_wl[83:83] ; -wire [83:83] mux_1level_tapbuf_size2_69_configbus0_b; -assign mux_1level_tapbuf_size2_69_configbus0_b[83:83] = sram_blwl_blb[83:83] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_69_ (mux_1level_tapbuf_size2_69_inbus, chany_1__1__out_18_ , mux_1level_tapbuf_size2_69_sram_blwl_out[83:83] , -mux_1level_tapbuf_size2_69_sram_blwl_outb[83:83] ); -//----- SRAM bits for MUX[69], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_83_ (mux_1level_tapbuf_size2_69_sram_blwl_out[83:83] ,mux_1level_tapbuf_size2_69_sram_blwl_out[83:83] ,mux_1level_tapbuf_size2_69_sram_blwl_outb[83:83] ,mux_1level_tapbuf_size2_69_configbus0[83:83], mux_1level_tapbuf_size2_69_configbus1[83:83] , mux_1level_tapbuf_size2_69_configbus0_b[83:83] ); -wire [0:1] mux_1level_tapbuf_size2_70_inbus; -assign mux_1level_tapbuf_size2_70_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_70_inbus[1] = chanx_1__0__in_10_ ; -wire [84:84] mux_1level_tapbuf_size2_70_configbus0; -wire [84:84] mux_1level_tapbuf_size2_70_configbus1; -wire [84:84] mux_1level_tapbuf_size2_70_sram_blwl_out ; -wire [84:84] mux_1level_tapbuf_size2_70_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_70_configbus0[84:84] = sram_blwl_bl[84:84] ; -assign mux_1level_tapbuf_size2_70_configbus1[84:84] = sram_blwl_wl[84:84] ; -wire [84:84] mux_1level_tapbuf_size2_70_configbus0_b; -assign mux_1level_tapbuf_size2_70_configbus0_b[84:84] = sram_blwl_blb[84:84] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_70_ (mux_1level_tapbuf_size2_70_inbus, chany_1__1__out_20_ , mux_1level_tapbuf_size2_70_sram_blwl_out[84:84] , -mux_1level_tapbuf_size2_70_sram_blwl_outb[84:84] ); -//----- SRAM bits for MUX[70], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_84_ (mux_1level_tapbuf_size2_70_sram_blwl_out[84:84] ,mux_1level_tapbuf_size2_70_sram_blwl_out[84:84] ,mux_1level_tapbuf_size2_70_sram_blwl_outb[84:84] ,mux_1level_tapbuf_size2_70_configbus0[84:84], mux_1level_tapbuf_size2_70_configbus1[84:84] , mux_1level_tapbuf_size2_70_configbus0_b[84:84] ); -wire [0:1] mux_1level_tapbuf_size2_71_inbus; -assign mux_1level_tapbuf_size2_71_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_71_inbus[1] = chanx_1__0__in_8_ ; -wire [85:85] mux_1level_tapbuf_size2_71_configbus0; -wire [85:85] mux_1level_tapbuf_size2_71_configbus1; -wire [85:85] mux_1level_tapbuf_size2_71_sram_blwl_out ; -wire [85:85] mux_1level_tapbuf_size2_71_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_71_configbus0[85:85] = sram_blwl_bl[85:85] ; -assign mux_1level_tapbuf_size2_71_configbus1[85:85] = sram_blwl_wl[85:85] ; -wire [85:85] mux_1level_tapbuf_size2_71_configbus0_b; -assign mux_1level_tapbuf_size2_71_configbus0_b[85:85] = sram_blwl_blb[85:85] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_71_ (mux_1level_tapbuf_size2_71_inbus, chany_1__1__out_22_ , mux_1level_tapbuf_size2_71_sram_blwl_out[85:85] , -mux_1level_tapbuf_size2_71_sram_blwl_outb[85:85] ); -//----- SRAM bits for MUX[71], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_85_ (mux_1level_tapbuf_size2_71_sram_blwl_out[85:85] ,mux_1level_tapbuf_size2_71_sram_blwl_out[85:85] ,mux_1level_tapbuf_size2_71_sram_blwl_outb[85:85] ,mux_1level_tapbuf_size2_71_configbus0[85:85], mux_1level_tapbuf_size2_71_configbus1[85:85] , mux_1level_tapbuf_size2_71_configbus0_b[85:85] ); -wire [0:1] mux_1level_tapbuf_size2_72_inbus; -assign mux_1level_tapbuf_size2_72_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_72_inbus[1] = chanx_1__0__in_6_ ; -wire [86:86] mux_1level_tapbuf_size2_72_configbus0; -wire [86:86] mux_1level_tapbuf_size2_72_configbus1; -wire [86:86] mux_1level_tapbuf_size2_72_sram_blwl_out ; -wire [86:86] mux_1level_tapbuf_size2_72_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_72_configbus0[86:86] = sram_blwl_bl[86:86] ; -assign mux_1level_tapbuf_size2_72_configbus1[86:86] = sram_blwl_wl[86:86] ; -wire [86:86] mux_1level_tapbuf_size2_72_configbus0_b; -assign mux_1level_tapbuf_size2_72_configbus0_b[86:86] = sram_blwl_blb[86:86] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_72_ (mux_1level_tapbuf_size2_72_inbus, chany_1__1__out_24_ , mux_1level_tapbuf_size2_72_sram_blwl_out[86:86] , -mux_1level_tapbuf_size2_72_sram_blwl_outb[86:86] ); -//----- SRAM bits for MUX[72], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_86_ (mux_1level_tapbuf_size2_72_sram_blwl_out[86:86] ,mux_1level_tapbuf_size2_72_sram_blwl_out[86:86] ,mux_1level_tapbuf_size2_72_sram_blwl_outb[86:86] ,mux_1level_tapbuf_size2_72_configbus0[86:86], mux_1level_tapbuf_size2_72_configbus1[86:86] , mux_1level_tapbuf_size2_72_configbus0_b[86:86] ); -wire [0:1] mux_1level_tapbuf_size2_73_inbus; -assign mux_1level_tapbuf_size2_73_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_73_inbus[1] = chanx_1__0__in_4_ ; -wire [87:87] mux_1level_tapbuf_size2_73_configbus0; -wire [87:87] mux_1level_tapbuf_size2_73_configbus1; -wire [87:87] mux_1level_tapbuf_size2_73_sram_blwl_out ; -wire [87:87] mux_1level_tapbuf_size2_73_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_73_configbus0[87:87] = sram_blwl_bl[87:87] ; -assign mux_1level_tapbuf_size2_73_configbus1[87:87] = sram_blwl_wl[87:87] ; -wire [87:87] mux_1level_tapbuf_size2_73_configbus0_b; -assign mux_1level_tapbuf_size2_73_configbus0_b[87:87] = sram_blwl_blb[87:87] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_73_ (mux_1level_tapbuf_size2_73_inbus, chany_1__1__out_26_ , mux_1level_tapbuf_size2_73_sram_blwl_out[87:87] , -mux_1level_tapbuf_size2_73_sram_blwl_outb[87:87] ); -//----- SRAM bits for MUX[73], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_87_ (mux_1level_tapbuf_size2_73_sram_blwl_out[87:87] ,mux_1level_tapbuf_size2_73_sram_blwl_out[87:87] ,mux_1level_tapbuf_size2_73_sram_blwl_outb[87:87] ,mux_1level_tapbuf_size2_73_configbus0[87:87], mux_1level_tapbuf_size2_73_configbus1[87:87] , mux_1level_tapbuf_size2_73_configbus0_b[87:87] ); -wire [0:1] mux_1level_tapbuf_size2_74_inbus; -assign mux_1level_tapbuf_size2_74_inbus[0] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size2_74_inbus[1] = chanx_1__0__in_2_ ; -wire [88:88] mux_1level_tapbuf_size2_74_configbus0; -wire [88:88] mux_1level_tapbuf_size2_74_configbus1; -wire [88:88] mux_1level_tapbuf_size2_74_sram_blwl_out ; -wire [88:88] mux_1level_tapbuf_size2_74_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_74_configbus0[88:88] = sram_blwl_bl[88:88] ; -assign mux_1level_tapbuf_size2_74_configbus1[88:88] = sram_blwl_wl[88:88] ; -wire [88:88] mux_1level_tapbuf_size2_74_configbus0_b; -assign mux_1level_tapbuf_size2_74_configbus0_b[88:88] = sram_blwl_blb[88:88] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_74_ (mux_1level_tapbuf_size2_74_inbus, chany_1__1__out_28_ , mux_1level_tapbuf_size2_74_sram_blwl_out[88:88] , -mux_1level_tapbuf_size2_74_sram_blwl_outb[88:88] ); -//----- SRAM bits for MUX[74], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_88_ (mux_1level_tapbuf_size2_74_sram_blwl_out[88:88] ,mux_1level_tapbuf_size2_74_sram_blwl_out[88:88] ,mux_1level_tapbuf_size2_74_sram_blwl_outb[88:88] ,mux_1level_tapbuf_size2_74_configbus0[88:88], mux_1level_tapbuf_size2_74_configbus1[88:88] , mux_1level_tapbuf_size2_74_configbus0_b[88:88] ); -//----- right side Multiplexers ----- -//----- bottom side Multiplexers ----- -//----- left side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_75_inbus; -assign mux_1level_tapbuf_size3_75_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size3_75_inbus[1] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size3_75_inbus[2] = chany_1__1__in_1_ ; -wire [89:91] mux_1level_tapbuf_size3_75_configbus0; -wire [89:91] mux_1level_tapbuf_size3_75_configbus1; -wire [89:91] mux_1level_tapbuf_size3_75_sram_blwl_out ; -wire [89:91] mux_1level_tapbuf_size3_75_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_75_configbus0[89:91] = sram_blwl_bl[89:91] ; -assign mux_1level_tapbuf_size3_75_configbus1[89:91] = sram_blwl_wl[89:91] ; -wire [89:91] mux_1level_tapbuf_size3_75_configbus0_b; -assign mux_1level_tapbuf_size3_75_configbus0_b[89:91] = sram_blwl_blb[89:91] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_75_ (mux_1level_tapbuf_size3_75_inbus, chanx_1__0__out_1_ , mux_1level_tapbuf_size3_75_sram_blwl_out[89:91] , -mux_1level_tapbuf_size3_75_sram_blwl_outb[89:91] ); -//----- SRAM bits for MUX[75], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_89_ (mux_1level_tapbuf_size3_75_sram_blwl_out[89:89] ,mux_1level_tapbuf_size3_75_sram_blwl_out[89:89] ,mux_1level_tapbuf_size3_75_sram_blwl_outb[89:89] ,mux_1level_tapbuf_size3_75_configbus0[89:89], mux_1level_tapbuf_size3_75_configbus1[89:89] , mux_1level_tapbuf_size3_75_configbus0_b[89:89] ); -sram6T_blwl sram_blwl_90_ (mux_1level_tapbuf_size3_75_sram_blwl_out[90:90] ,mux_1level_tapbuf_size3_75_sram_blwl_out[90:90] ,mux_1level_tapbuf_size3_75_sram_blwl_outb[90:90] ,mux_1level_tapbuf_size3_75_configbus0[90:90], mux_1level_tapbuf_size3_75_configbus1[90:90] , mux_1level_tapbuf_size3_75_configbus0_b[90:90] ); -sram6T_blwl sram_blwl_91_ (mux_1level_tapbuf_size3_75_sram_blwl_out[91:91] ,mux_1level_tapbuf_size3_75_sram_blwl_out[91:91] ,mux_1level_tapbuf_size3_75_sram_blwl_outb[91:91] ,mux_1level_tapbuf_size3_75_configbus0[91:91], mux_1level_tapbuf_size3_75_configbus1[91:91] , mux_1level_tapbuf_size3_75_configbus0_b[91:91] ); -wire [0:1] mux_1level_tapbuf_size2_76_inbus; -assign mux_1level_tapbuf_size2_76_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_76_inbus[1] = chany_1__1__in_29_ ; -wire [92:92] mux_1level_tapbuf_size2_76_configbus0; -wire [92:92] mux_1level_tapbuf_size2_76_configbus1; -wire [92:92] mux_1level_tapbuf_size2_76_sram_blwl_out ; -wire [92:92] mux_1level_tapbuf_size2_76_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_76_configbus0[92:92] = sram_blwl_bl[92:92] ; -assign mux_1level_tapbuf_size2_76_configbus1[92:92] = sram_blwl_wl[92:92] ; -wire [92:92] mux_1level_tapbuf_size2_76_configbus0_b; -assign mux_1level_tapbuf_size2_76_configbus0_b[92:92] = sram_blwl_blb[92:92] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_76_ (mux_1level_tapbuf_size2_76_inbus, chanx_1__0__out_3_ , mux_1level_tapbuf_size2_76_sram_blwl_out[92:92] , -mux_1level_tapbuf_size2_76_sram_blwl_outb[92:92] ); -//----- SRAM bits for MUX[76], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_92_ (mux_1level_tapbuf_size2_76_sram_blwl_out[92:92] ,mux_1level_tapbuf_size2_76_sram_blwl_out[92:92] ,mux_1level_tapbuf_size2_76_sram_blwl_outb[92:92] ,mux_1level_tapbuf_size2_76_configbus0[92:92], mux_1level_tapbuf_size2_76_configbus1[92:92] , mux_1level_tapbuf_size2_76_configbus0_b[92:92] ); -wire [0:1] mux_1level_tapbuf_size2_77_inbus; -assign mux_1level_tapbuf_size2_77_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_77_inbus[1] = chany_1__1__in_27_ ; -wire [93:93] mux_1level_tapbuf_size2_77_configbus0; -wire [93:93] mux_1level_tapbuf_size2_77_configbus1; -wire [93:93] mux_1level_tapbuf_size2_77_sram_blwl_out ; -wire [93:93] mux_1level_tapbuf_size2_77_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_77_configbus0[93:93] = sram_blwl_bl[93:93] ; -assign mux_1level_tapbuf_size2_77_configbus1[93:93] = sram_blwl_wl[93:93] ; -wire [93:93] mux_1level_tapbuf_size2_77_configbus0_b; -assign mux_1level_tapbuf_size2_77_configbus0_b[93:93] = sram_blwl_blb[93:93] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_77_ (mux_1level_tapbuf_size2_77_inbus, chanx_1__0__out_5_ , mux_1level_tapbuf_size2_77_sram_blwl_out[93:93] , -mux_1level_tapbuf_size2_77_sram_blwl_outb[93:93] ); -//----- SRAM bits for MUX[77], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_93_ (mux_1level_tapbuf_size2_77_sram_blwl_out[93:93] ,mux_1level_tapbuf_size2_77_sram_blwl_out[93:93] ,mux_1level_tapbuf_size2_77_sram_blwl_outb[93:93] ,mux_1level_tapbuf_size2_77_configbus0[93:93], mux_1level_tapbuf_size2_77_configbus1[93:93] , mux_1level_tapbuf_size2_77_configbus0_b[93:93] ); -wire [0:1] mux_1level_tapbuf_size2_78_inbus; -assign mux_1level_tapbuf_size2_78_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_78_inbus[1] = chany_1__1__in_25_ ; -wire [94:94] mux_1level_tapbuf_size2_78_configbus0; -wire [94:94] mux_1level_tapbuf_size2_78_configbus1; -wire [94:94] mux_1level_tapbuf_size2_78_sram_blwl_out ; -wire [94:94] mux_1level_tapbuf_size2_78_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_78_configbus0[94:94] = sram_blwl_bl[94:94] ; -assign mux_1level_tapbuf_size2_78_configbus1[94:94] = sram_blwl_wl[94:94] ; -wire [94:94] mux_1level_tapbuf_size2_78_configbus0_b; -assign mux_1level_tapbuf_size2_78_configbus0_b[94:94] = sram_blwl_blb[94:94] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_78_ (mux_1level_tapbuf_size2_78_inbus, chanx_1__0__out_7_ , mux_1level_tapbuf_size2_78_sram_blwl_out[94:94] , -mux_1level_tapbuf_size2_78_sram_blwl_outb[94:94] ); -//----- SRAM bits for MUX[78], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_94_ (mux_1level_tapbuf_size2_78_sram_blwl_out[94:94] ,mux_1level_tapbuf_size2_78_sram_blwl_out[94:94] ,mux_1level_tapbuf_size2_78_sram_blwl_outb[94:94] ,mux_1level_tapbuf_size2_78_configbus0[94:94], mux_1level_tapbuf_size2_78_configbus1[94:94] , mux_1level_tapbuf_size2_78_configbus0_b[94:94] ); -wire [0:1] mux_1level_tapbuf_size2_79_inbus; -assign mux_1level_tapbuf_size2_79_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_79_inbus[1] = chany_1__1__in_23_ ; -wire [95:95] mux_1level_tapbuf_size2_79_configbus0; -wire [95:95] mux_1level_tapbuf_size2_79_configbus1; -wire [95:95] mux_1level_tapbuf_size2_79_sram_blwl_out ; -wire [95:95] mux_1level_tapbuf_size2_79_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_79_configbus0[95:95] = sram_blwl_bl[95:95] ; -assign mux_1level_tapbuf_size2_79_configbus1[95:95] = sram_blwl_wl[95:95] ; -wire [95:95] mux_1level_tapbuf_size2_79_configbus0_b; -assign mux_1level_tapbuf_size2_79_configbus0_b[95:95] = sram_blwl_blb[95:95] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_79_ (mux_1level_tapbuf_size2_79_inbus, chanx_1__0__out_9_ , mux_1level_tapbuf_size2_79_sram_blwl_out[95:95] , -mux_1level_tapbuf_size2_79_sram_blwl_outb[95:95] ); -//----- SRAM bits for MUX[79], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_95_ (mux_1level_tapbuf_size2_79_sram_blwl_out[95:95] ,mux_1level_tapbuf_size2_79_sram_blwl_out[95:95] ,mux_1level_tapbuf_size2_79_sram_blwl_outb[95:95] ,mux_1level_tapbuf_size2_79_configbus0[95:95], mux_1level_tapbuf_size2_79_configbus1[95:95] , mux_1level_tapbuf_size2_79_configbus0_b[95:95] ); -wire [0:1] mux_1level_tapbuf_size2_80_inbus; -assign mux_1level_tapbuf_size2_80_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_80_inbus[1] = chany_1__1__in_21_ ; -wire [96:96] mux_1level_tapbuf_size2_80_configbus0; -wire [96:96] mux_1level_tapbuf_size2_80_configbus1; -wire [96:96] mux_1level_tapbuf_size2_80_sram_blwl_out ; -wire [96:96] mux_1level_tapbuf_size2_80_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_80_configbus0[96:96] = sram_blwl_bl[96:96] ; -assign mux_1level_tapbuf_size2_80_configbus1[96:96] = sram_blwl_wl[96:96] ; -wire [96:96] mux_1level_tapbuf_size2_80_configbus0_b; -assign mux_1level_tapbuf_size2_80_configbus0_b[96:96] = sram_blwl_blb[96:96] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_80_ (mux_1level_tapbuf_size2_80_inbus, chanx_1__0__out_11_ , mux_1level_tapbuf_size2_80_sram_blwl_out[96:96] , -mux_1level_tapbuf_size2_80_sram_blwl_outb[96:96] ); -//----- SRAM bits for MUX[80], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_96_ (mux_1level_tapbuf_size2_80_sram_blwl_out[96:96] ,mux_1level_tapbuf_size2_80_sram_blwl_out[96:96] ,mux_1level_tapbuf_size2_80_sram_blwl_outb[96:96] ,mux_1level_tapbuf_size2_80_configbus0[96:96], mux_1level_tapbuf_size2_80_configbus1[96:96] , mux_1level_tapbuf_size2_80_configbus0_b[96:96] ); -wire [0:1] mux_1level_tapbuf_size2_81_inbus; -assign mux_1level_tapbuf_size2_81_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_81_inbus[1] = chany_1__1__in_19_ ; -wire [97:97] mux_1level_tapbuf_size2_81_configbus0; -wire [97:97] mux_1level_tapbuf_size2_81_configbus1; -wire [97:97] mux_1level_tapbuf_size2_81_sram_blwl_out ; -wire [97:97] mux_1level_tapbuf_size2_81_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_81_configbus0[97:97] = sram_blwl_bl[97:97] ; -assign mux_1level_tapbuf_size2_81_configbus1[97:97] = sram_blwl_wl[97:97] ; -wire [97:97] mux_1level_tapbuf_size2_81_configbus0_b; -assign mux_1level_tapbuf_size2_81_configbus0_b[97:97] = sram_blwl_blb[97:97] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_81_ (mux_1level_tapbuf_size2_81_inbus, chanx_1__0__out_13_ , mux_1level_tapbuf_size2_81_sram_blwl_out[97:97] , -mux_1level_tapbuf_size2_81_sram_blwl_outb[97:97] ); -//----- SRAM bits for MUX[81], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_97_ (mux_1level_tapbuf_size2_81_sram_blwl_out[97:97] ,mux_1level_tapbuf_size2_81_sram_blwl_out[97:97] ,mux_1level_tapbuf_size2_81_sram_blwl_outb[97:97] ,mux_1level_tapbuf_size2_81_configbus0[97:97], mux_1level_tapbuf_size2_81_configbus1[97:97] , mux_1level_tapbuf_size2_81_configbus0_b[97:97] ); -wire [0:1] mux_1level_tapbuf_size2_82_inbus; -assign mux_1level_tapbuf_size2_82_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_82_inbus[1] = chany_1__1__in_17_ ; -wire [98:98] mux_1level_tapbuf_size2_82_configbus0; -wire [98:98] mux_1level_tapbuf_size2_82_configbus1; -wire [98:98] mux_1level_tapbuf_size2_82_sram_blwl_out ; -wire [98:98] mux_1level_tapbuf_size2_82_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_82_configbus0[98:98] = sram_blwl_bl[98:98] ; -assign mux_1level_tapbuf_size2_82_configbus1[98:98] = sram_blwl_wl[98:98] ; -wire [98:98] mux_1level_tapbuf_size2_82_configbus0_b; -assign mux_1level_tapbuf_size2_82_configbus0_b[98:98] = sram_blwl_blb[98:98] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_82_ (mux_1level_tapbuf_size2_82_inbus, chanx_1__0__out_15_ , mux_1level_tapbuf_size2_82_sram_blwl_out[98:98] , -mux_1level_tapbuf_size2_82_sram_blwl_outb[98:98] ); -//----- SRAM bits for MUX[82], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_98_ (mux_1level_tapbuf_size2_82_sram_blwl_out[98:98] ,mux_1level_tapbuf_size2_82_sram_blwl_out[98:98] ,mux_1level_tapbuf_size2_82_sram_blwl_outb[98:98] ,mux_1level_tapbuf_size2_82_configbus0[98:98], mux_1level_tapbuf_size2_82_configbus1[98:98] , mux_1level_tapbuf_size2_82_configbus0_b[98:98] ); -wire [0:1] mux_1level_tapbuf_size2_83_inbus; -assign mux_1level_tapbuf_size2_83_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_83_inbus[1] = chany_1__1__in_15_ ; -wire [99:99] mux_1level_tapbuf_size2_83_configbus0; -wire [99:99] mux_1level_tapbuf_size2_83_configbus1; -wire [99:99] mux_1level_tapbuf_size2_83_sram_blwl_out ; -wire [99:99] mux_1level_tapbuf_size2_83_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_83_configbus0[99:99] = sram_blwl_bl[99:99] ; -assign mux_1level_tapbuf_size2_83_configbus1[99:99] = sram_blwl_wl[99:99] ; -wire [99:99] mux_1level_tapbuf_size2_83_configbus0_b; -assign mux_1level_tapbuf_size2_83_configbus0_b[99:99] = sram_blwl_blb[99:99] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_83_ (mux_1level_tapbuf_size2_83_inbus, chanx_1__0__out_17_ , mux_1level_tapbuf_size2_83_sram_blwl_out[99:99] , -mux_1level_tapbuf_size2_83_sram_blwl_outb[99:99] ); -//----- SRAM bits for MUX[83], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_99_ (mux_1level_tapbuf_size2_83_sram_blwl_out[99:99] ,mux_1level_tapbuf_size2_83_sram_blwl_out[99:99] ,mux_1level_tapbuf_size2_83_sram_blwl_outb[99:99] ,mux_1level_tapbuf_size2_83_configbus0[99:99], mux_1level_tapbuf_size2_83_configbus1[99:99] , mux_1level_tapbuf_size2_83_configbus0_b[99:99] ); -wire [0:1] mux_1level_tapbuf_size2_84_inbus; -assign mux_1level_tapbuf_size2_84_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_84_inbus[1] = chany_1__1__in_13_ ; -wire [100:100] mux_1level_tapbuf_size2_84_configbus0; -wire [100:100] mux_1level_tapbuf_size2_84_configbus1; -wire [100:100] mux_1level_tapbuf_size2_84_sram_blwl_out ; -wire [100:100] mux_1level_tapbuf_size2_84_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_84_configbus0[100:100] = sram_blwl_bl[100:100] ; -assign mux_1level_tapbuf_size2_84_configbus1[100:100] = sram_blwl_wl[100:100] ; -wire [100:100] mux_1level_tapbuf_size2_84_configbus0_b; -assign mux_1level_tapbuf_size2_84_configbus0_b[100:100] = sram_blwl_blb[100:100] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_84_ (mux_1level_tapbuf_size2_84_inbus, chanx_1__0__out_19_ , mux_1level_tapbuf_size2_84_sram_blwl_out[100:100] , -mux_1level_tapbuf_size2_84_sram_blwl_outb[100:100] ); -//----- SRAM bits for MUX[84], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_100_ (mux_1level_tapbuf_size2_84_sram_blwl_out[100:100] ,mux_1level_tapbuf_size2_84_sram_blwl_out[100:100] ,mux_1level_tapbuf_size2_84_sram_blwl_outb[100:100] ,mux_1level_tapbuf_size2_84_configbus0[100:100], mux_1level_tapbuf_size2_84_configbus1[100:100] , mux_1level_tapbuf_size2_84_configbus0_b[100:100] ); -wire [0:1] mux_1level_tapbuf_size2_85_inbus; -assign mux_1level_tapbuf_size2_85_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_85_inbus[1] = chany_1__1__in_11_ ; -wire [101:101] mux_1level_tapbuf_size2_85_configbus0; -wire [101:101] mux_1level_tapbuf_size2_85_configbus1; -wire [101:101] mux_1level_tapbuf_size2_85_sram_blwl_out ; -wire [101:101] mux_1level_tapbuf_size2_85_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_85_configbus0[101:101] = sram_blwl_bl[101:101] ; -assign mux_1level_tapbuf_size2_85_configbus1[101:101] = sram_blwl_wl[101:101] ; -wire [101:101] mux_1level_tapbuf_size2_85_configbus0_b; -assign mux_1level_tapbuf_size2_85_configbus0_b[101:101] = sram_blwl_blb[101:101] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_85_ (mux_1level_tapbuf_size2_85_inbus, chanx_1__0__out_21_ , mux_1level_tapbuf_size2_85_sram_blwl_out[101:101] , -mux_1level_tapbuf_size2_85_sram_blwl_outb[101:101] ); -//----- SRAM bits for MUX[85], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_101_ (mux_1level_tapbuf_size2_85_sram_blwl_out[101:101] ,mux_1level_tapbuf_size2_85_sram_blwl_out[101:101] ,mux_1level_tapbuf_size2_85_sram_blwl_outb[101:101] ,mux_1level_tapbuf_size2_85_configbus0[101:101], mux_1level_tapbuf_size2_85_configbus1[101:101] , mux_1level_tapbuf_size2_85_configbus0_b[101:101] ); -wire [0:1] mux_1level_tapbuf_size2_86_inbus; -assign mux_1level_tapbuf_size2_86_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_86_inbus[1] = chany_1__1__in_9_ ; -wire [102:102] mux_1level_tapbuf_size2_86_configbus0; -wire [102:102] mux_1level_tapbuf_size2_86_configbus1; -wire [102:102] mux_1level_tapbuf_size2_86_sram_blwl_out ; -wire [102:102] mux_1level_tapbuf_size2_86_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_86_configbus0[102:102] = sram_blwl_bl[102:102] ; -assign mux_1level_tapbuf_size2_86_configbus1[102:102] = sram_blwl_wl[102:102] ; -wire [102:102] mux_1level_tapbuf_size2_86_configbus0_b; -assign mux_1level_tapbuf_size2_86_configbus0_b[102:102] = sram_blwl_blb[102:102] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_86_ (mux_1level_tapbuf_size2_86_inbus, chanx_1__0__out_23_ , mux_1level_tapbuf_size2_86_sram_blwl_out[102:102] , -mux_1level_tapbuf_size2_86_sram_blwl_outb[102:102] ); -//----- SRAM bits for MUX[86], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_102_ (mux_1level_tapbuf_size2_86_sram_blwl_out[102:102] ,mux_1level_tapbuf_size2_86_sram_blwl_out[102:102] ,mux_1level_tapbuf_size2_86_sram_blwl_outb[102:102] ,mux_1level_tapbuf_size2_86_configbus0[102:102], mux_1level_tapbuf_size2_86_configbus1[102:102] , mux_1level_tapbuf_size2_86_configbus0_b[102:102] ); -wire [0:1] mux_1level_tapbuf_size2_87_inbus; -assign mux_1level_tapbuf_size2_87_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_87_inbus[1] = chany_1__1__in_7_ ; -wire [103:103] mux_1level_tapbuf_size2_87_configbus0; -wire [103:103] mux_1level_tapbuf_size2_87_configbus1; -wire [103:103] mux_1level_tapbuf_size2_87_sram_blwl_out ; -wire [103:103] mux_1level_tapbuf_size2_87_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_87_configbus0[103:103] = sram_blwl_bl[103:103] ; -assign mux_1level_tapbuf_size2_87_configbus1[103:103] = sram_blwl_wl[103:103] ; -wire [103:103] mux_1level_tapbuf_size2_87_configbus0_b; -assign mux_1level_tapbuf_size2_87_configbus0_b[103:103] = sram_blwl_blb[103:103] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_87_ (mux_1level_tapbuf_size2_87_inbus, chanx_1__0__out_25_ , mux_1level_tapbuf_size2_87_sram_blwl_out[103:103] , -mux_1level_tapbuf_size2_87_sram_blwl_outb[103:103] ); -//----- SRAM bits for MUX[87], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_103_ (mux_1level_tapbuf_size2_87_sram_blwl_out[103:103] ,mux_1level_tapbuf_size2_87_sram_blwl_out[103:103] ,mux_1level_tapbuf_size2_87_sram_blwl_outb[103:103] ,mux_1level_tapbuf_size2_87_configbus0[103:103], mux_1level_tapbuf_size2_87_configbus1[103:103] , mux_1level_tapbuf_size2_87_configbus0_b[103:103] ); -wire [0:1] mux_1level_tapbuf_size2_88_inbus; -assign mux_1level_tapbuf_size2_88_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_88_inbus[1] = chany_1__1__in_5_ ; -wire [104:104] mux_1level_tapbuf_size2_88_configbus0; -wire [104:104] mux_1level_tapbuf_size2_88_configbus1; -wire [104:104] mux_1level_tapbuf_size2_88_sram_blwl_out ; -wire [104:104] mux_1level_tapbuf_size2_88_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_88_configbus0[104:104] = sram_blwl_bl[104:104] ; -assign mux_1level_tapbuf_size2_88_configbus1[104:104] = sram_blwl_wl[104:104] ; -wire [104:104] mux_1level_tapbuf_size2_88_configbus0_b; -assign mux_1level_tapbuf_size2_88_configbus0_b[104:104] = sram_blwl_blb[104:104] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_88_ (mux_1level_tapbuf_size2_88_inbus, chanx_1__0__out_27_ , mux_1level_tapbuf_size2_88_sram_blwl_out[104:104] , -mux_1level_tapbuf_size2_88_sram_blwl_outb[104:104] ); -//----- SRAM bits for MUX[88], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_104_ (mux_1level_tapbuf_size2_88_sram_blwl_out[104:104] ,mux_1level_tapbuf_size2_88_sram_blwl_out[104:104] ,mux_1level_tapbuf_size2_88_sram_blwl_outb[104:104] ,mux_1level_tapbuf_size2_88_configbus0[104:104], mux_1level_tapbuf_size2_88_configbus1[104:104] , mux_1level_tapbuf_size2_88_configbus0_b[104:104] ); -wire [0:1] mux_1level_tapbuf_size2_89_inbus; -assign mux_1level_tapbuf_size2_89_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_89_inbus[1] = chany_1__1__in_3_ ; -wire [105:105] mux_1level_tapbuf_size2_89_configbus0; -wire [105:105] mux_1level_tapbuf_size2_89_configbus1; -wire [105:105] mux_1level_tapbuf_size2_89_sram_blwl_out ; -wire [105:105] mux_1level_tapbuf_size2_89_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_89_configbus0[105:105] = sram_blwl_bl[105:105] ; -assign mux_1level_tapbuf_size2_89_configbus1[105:105] = sram_blwl_wl[105:105] ; -wire [105:105] mux_1level_tapbuf_size2_89_configbus0_b; -assign mux_1level_tapbuf_size2_89_configbus0_b[105:105] = sram_blwl_blb[105:105] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_89_ (mux_1level_tapbuf_size2_89_inbus, chanx_1__0__out_29_ , mux_1level_tapbuf_size2_89_sram_blwl_out[105:105] , -mux_1level_tapbuf_size2_89_sram_blwl_outb[105:105] ); -//----- SRAM bits for MUX[89], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_105_ (mux_1level_tapbuf_size2_89_sram_blwl_out[105:105] ,mux_1level_tapbuf_size2_89_sram_blwl_out[105:105] ,mux_1level_tapbuf_size2_89_sram_blwl_outb[105:105] ,mux_1level_tapbuf_size2_89_configbus0[105:105], mux_1level_tapbuf_size2_89_configbus1[105:105] , mux_1level_tapbuf_size2_89_configbus0_b[105:105] ); -endmodule -//----- END Verilog Module of Switch Box[1][0] ----- - diff --git a/examples/verilog_test_example_1/routing/sb_1_1.v b/examples/verilog_test_example_1/routing/sb_1_1.v deleted file mode 100644 index fd67e7bb8..000000000 --- a/examples/verilog_test_example_1/routing/sb_1_1.v +++ /dev/null @@ -1,634 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Switch Block [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Switch Box[1][1] ----- -module sb_1__1_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -//----- Inputs/outputs of top side ----- -//----- Inputs/outputs of right side ----- -//----- Inputs/outputs of bottom side ----- - input chany_1__1__in_0_, - output chany_1__1__out_1_, - input chany_1__1__in_2_, - output chany_1__1__out_3_, - input chany_1__1__in_4_, - output chany_1__1__out_5_, - input chany_1__1__in_6_, - output chany_1__1__out_7_, - input chany_1__1__in_8_, - output chany_1__1__out_9_, - input chany_1__1__in_10_, - output chany_1__1__out_11_, - input chany_1__1__in_12_, - output chany_1__1__out_13_, - input chany_1__1__in_14_, - output chany_1__1__out_15_, - input chany_1__1__in_16_, - output chany_1__1__out_17_, - input chany_1__1__in_18_, - output chany_1__1__out_19_, - input chany_1__1__in_20_, - output chany_1__1__out_21_, - input chany_1__1__in_22_, - output chany_1__1__out_23_, - input chany_1__1__in_24_, - output chany_1__1__out_25_, - input chany_1__1__in_26_, - output chany_1__1__out_27_, - input chany_1__1__in_28_, - output chany_1__1__out_29_, -input grid_2__1__pin_0__3__1_, -input grid_2__1__pin_0__3__3_, -input grid_2__1__pin_0__3__5_, -input grid_2__1__pin_0__3__7_, -input grid_2__1__pin_0__3__9_, -input grid_2__1__pin_0__3__11_, -input grid_2__1__pin_0__3__13_, -input grid_2__1__pin_0__3__15_, -//----- Inputs/outputs of left side ----- - input chanx_1__1__in_0_, - output chanx_1__1__out_1_, - input chanx_1__1__in_2_, - output chanx_1__1__out_3_, - input chanx_1__1__in_4_, - output chanx_1__1__out_5_, - input chanx_1__1__in_6_, - output chanx_1__1__out_7_, - input chanx_1__1__in_8_, - output chanx_1__1__out_9_, - input chanx_1__1__in_10_, - output chanx_1__1__out_11_, - input chanx_1__1__in_12_, - output chanx_1__1__out_13_, - input chanx_1__1__in_14_, - output chanx_1__1__out_15_, - input chanx_1__1__in_16_, - output chanx_1__1__out_17_, - input chanx_1__1__in_18_, - output chanx_1__1__out_19_, - input chanx_1__1__in_20_, - output chanx_1__1__out_21_, - input chanx_1__1__in_22_, - output chanx_1__1__out_23_, - input chanx_1__1__in_24_, - output chanx_1__1__out_25_, - input chanx_1__1__in_26_, - output chanx_1__1__out_27_, - input chanx_1__1__in_28_, - output chanx_1__1__out_29_, -input grid_1__2__pin_0__2__1_, -input grid_1__2__pin_0__2__3_, -input grid_1__2__pin_0__2__5_, -input grid_1__2__pin_0__2__7_, -input grid_1__2__pin_0__2__9_, -input grid_1__2__pin_0__2__11_, -input grid_1__2__pin_0__2__13_, -input grid_1__2__pin_0__2__15_, -input grid_1__1__pin_0__0__4_, -input [106:143] sram_blwl_bl , -input [106:143] sram_blwl_wl , -input [106:143] sram_blwl_blb ); -//----- top side Multiplexers ----- -//----- right side Multiplexers ----- -//----- bottom side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_90_inbus; -assign mux_1level_tapbuf_size3_90_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size3_90_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_90_inbus[2] = chanx_1__1__in_2_ ; -wire [106:108] mux_1level_tapbuf_size3_90_configbus0; -wire [106:108] mux_1level_tapbuf_size3_90_configbus1; -wire [106:108] mux_1level_tapbuf_size3_90_sram_blwl_out ; -wire [106:108] mux_1level_tapbuf_size3_90_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_90_configbus0[106:108] = sram_blwl_bl[106:108] ; -assign mux_1level_tapbuf_size3_90_configbus1[106:108] = sram_blwl_wl[106:108] ; -wire [106:108] mux_1level_tapbuf_size3_90_configbus0_b; -assign mux_1level_tapbuf_size3_90_configbus0_b[106:108] = sram_blwl_blb[106:108] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_90_ (mux_1level_tapbuf_size3_90_inbus, chany_1__1__out_1_ , mux_1level_tapbuf_size3_90_sram_blwl_out[106:108] , -mux_1level_tapbuf_size3_90_sram_blwl_outb[106:108] ); -//----- SRAM bits for MUX[90], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_106_ (mux_1level_tapbuf_size3_90_sram_blwl_out[106:106] ,mux_1level_tapbuf_size3_90_sram_blwl_out[106:106] ,mux_1level_tapbuf_size3_90_sram_blwl_outb[106:106] ,mux_1level_tapbuf_size3_90_configbus0[106:106], mux_1level_tapbuf_size3_90_configbus1[106:106] , mux_1level_tapbuf_size3_90_configbus0_b[106:106] ); -sram6T_blwl sram_blwl_107_ (mux_1level_tapbuf_size3_90_sram_blwl_out[107:107] ,mux_1level_tapbuf_size3_90_sram_blwl_out[107:107] ,mux_1level_tapbuf_size3_90_sram_blwl_outb[107:107] ,mux_1level_tapbuf_size3_90_configbus0[107:107], mux_1level_tapbuf_size3_90_configbus1[107:107] , mux_1level_tapbuf_size3_90_configbus0_b[107:107] ); -sram6T_blwl sram_blwl_108_ (mux_1level_tapbuf_size3_90_sram_blwl_out[108:108] ,mux_1level_tapbuf_size3_90_sram_blwl_out[108:108] ,mux_1level_tapbuf_size3_90_sram_blwl_outb[108:108] ,mux_1level_tapbuf_size3_90_configbus0[108:108], mux_1level_tapbuf_size3_90_configbus1[108:108] , mux_1level_tapbuf_size3_90_configbus0_b[108:108] ); -wire [0:1] mux_1level_tapbuf_size2_91_inbus; -assign mux_1level_tapbuf_size2_91_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_91_inbus[1] = chanx_1__1__in_4_ ; -wire [109:109] mux_1level_tapbuf_size2_91_configbus0; -wire [109:109] mux_1level_tapbuf_size2_91_configbus1; -wire [109:109] mux_1level_tapbuf_size2_91_sram_blwl_out ; -wire [109:109] mux_1level_tapbuf_size2_91_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_91_configbus0[109:109] = sram_blwl_bl[109:109] ; -assign mux_1level_tapbuf_size2_91_configbus1[109:109] = sram_blwl_wl[109:109] ; -wire [109:109] mux_1level_tapbuf_size2_91_configbus0_b; -assign mux_1level_tapbuf_size2_91_configbus0_b[109:109] = sram_blwl_blb[109:109] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_91_ (mux_1level_tapbuf_size2_91_inbus, chany_1__1__out_3_ , mux_1level_tapbuf_size2_91_sram_blwl_out[109:109] , -mux_1level_tapbuf_size2_91_sram_blwl_outb[109:109] ); -//----- SRAM bits for MUX[91], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_109_ (mux_1level_tapbuf_size2_91_sram_blwl_out[109:109] ,mux_1level_tapbuf_size2_91_sram_blwl_out[109:109] ,mux_1level_tapbuf_size2_91_sram_blwl_outb[109:109] ,mux_1level_tapbuf_size2_91_configbus0[109:109], mux_1level_tapbuf_size2_91_configbus1[109:109] , mux_1level_tapbuf_size2_91_configbus0_b[109:109] ); -wire [0:1] mux_1level_tapbuf_size2_92_inbus; -assign mux_1level_tapbuf_size2_92_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_92_inbus[1] = chanx_1__1__in_6_ ; -wire [110:110] mux_1level_tapbuf_size2_92_configbus0; -wire [110:110] mux_1level_tapbuf_size2_92_configbus1; -wire [110:110] mux_1level_tapbuf_size2_92_sram_blwl_out ; -wire [110:110] mux_1level_tapbuf_size2_92_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_92_configbus0[110:110] = sram_blwl_bl[110:110] ; -assign mux_1level_tapbuf_size2_92_configbus1[110:110] = sram_blwl_wl[110:110] ; -wire [110:110] mux_1level_tapbuf_size2_92_configbus0_b; -assign mux_1level_tapbuf_size2_92_configbus0_b[110:110] = sram_blwl_blb[110:110] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_92_ (mux_1level_tapbuf_size2_92_inbus, chany_1__1__out_5_ , mux_1level_tapbuf_size2_92_sram_blwl_out[110:110] , -mux_1level_tapbuf_size2_92_sram_blwl_outb[110:110] ); -//----- SRAM bits for MUX[92], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_110_ (mux_1level_tapbuf_size2_92_sram_blwl_out[110:110] ,mux_1level_tapbuf_size2_92_sram_blwl_out[110:110] ,mux_1level_tapbuf_size2_92_sram_blwl_outb[110:110] ,mux_1level_tapbuf_size2_92_configbus0[110:110], mux_1level_tapbuf_size2_92_configbus1[110:110] , mux_1level_tapbuf_size2_92_configbus0_b[110:110] ); -wire [0:1] mux_1level_tapbuf_size2_93_inbus; -assign mux_1level_tapbuf_size2_93_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_93_inbus[1] = chanx_1__1__in_8_ ; -wire [111:111] mux_1level_tapbuf_size2_93_configbus0; -wire [111:111] mux_1level_tapbuf_size2_93_configbus1; -wire [111:111] mux_1level_tapbuf_size2_93_sram_blwl_out ; -wire [111:111] mux_1level_tapbuf_size2_93_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_93_configbus0[111:111] = sram_blwl_bl[111:111] ; -assign mux_1level_tapbuf_size2_93_configbus1[111:111] = sram_blwl_wl[111:111] ; -wire [111:111] mux_1level_tapbuf_size2_93_configbus0_b; -assign mux_1level_tapbuf_size2_93_configbus0_b[111:111] = sram_blwl_blb[111:111] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_93_ (mux_1level_tapbuf_size2_93_inbus, chany_1__1__out_7_ , mux_1level_tapbuf_size2_93_sram_blwl_out[111:111] , -mux_1level_tapbuf_size2_93_sram_blwl_outb[111:111] ); -//----- SRAM bits for MUX[93], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_111_ (mux_1level_tapbuf_size2_93_sram_blwl_out[111:111] ,mux_1level_tapbuf_size2_93_sram_blwl_out[111:111] ,mux_1level_tapbuf_size2_93_sram_blwl_outb[111:111] ,mux_1level_tapbuf_size2_93_configbus0[111:111], mux_1level_tapbuf_size2_93_configbus1[111:111] , mux_1level_tapbuf_size2_93_configbus0_b[111:111] ); -wire [0:1] mux_1level_tapbuf_size2_94_inbus; -assign mux_1level_tapbuf_size2_94_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_94_inbus[1] = chanx_1__1__in_10_ ; -wire [112:112] mux_1level_tapbuf_size2_94_configbus0; -wire [112:112] mux_1level_tapbuf_size2_94_configbus1; -wire [112:112] mux_1level_tapbuf_size2_94_sram_blwl_out ; -wire [112:112] mux_1level_tapbuf_size2_94_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_94_configbus0[112:112] = sram_blwl_bl[112:112] ; -assign mux_1level_tapbuf_size2_94_configbus1[112:112] = sram_blwl_wl[112:112] ; -wire [112:112] mux_1level_tapbuf_size2_94_configbus0_b; -assign mux_1level_tapbuf_size2_94_configbus0_b[112:112] = sram_blwl_blb[112:112] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_94_ (mux_1level_tapbuf_size2_94_inbus, chany_1__1__out_9_ , mux_1level_tapbuf_size2_94_sram_blwl_out[112:112] , -mux_1level_tapbuf_size2_94_sram_blwl_outb[112:112] ); -//----- SRAM bits for MUX[94], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_112_ (mux_1level_tapbuf_size2_94_sram_blwl_out[112:112] ,mux_1level_tapbuf_size2_94_sram_blwl_out[112:112] ,mux_1level_tapbuf_size2_94_sram_blwl_outb[112:112] ,mux_1level_tapbuf_size2_94_configbus0[112:112], mux_1level_tapbuf_size2_94_configbus1[112:112] , mux_1level_tapbuf_size2_94_configbus0_b[112:112] ); -wire [0:1] mux_1level_tapbuf_size2_95_inbus; -assign mux_1level_tapbuf_size2_95_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_95_inbus[1] = chanx_1__1__in_12_ ; -wire [113:113] mux_1level_tapbuf_size2_95_configbus0; -wire [113:113] mux_1level_tapbuf_size2_95_configbus1; -wire [113:113] mux_1level_tapbuf_size2_95_sram_blwl_out ; -wire [113:113] mux_1level_tapbuf_size2_95_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_95_configbus0[113:113] = sram_blwl_bl[113:113] ; -assign mux_1level_tapbuf_size2_95_configbus1[113:113] = sram_blwl_wl[113:113] ; -wire [113:113] mux_1level_tapbuf_size2_95_configbus0_b; -assign mux_1level_tapbuf_size2_95_configbus0_b[113:113] = sram_blwl_blb[113:113] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_95_ (mux_1level_tapbuf_size2_95_inbus, chany_1__1__out_11_ , mux_1level_tapbuf_size2_95_sram_blwl_out[113:113] , -mux_1level_tapbuf_size2_95_sram_blwl_outb[113:113] ); -//----- SRAM bits for MUX[95], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_113_ (mux_1level_tapbuf_size2_95_sram_blwl_out[113:113] ,mux_1level_tapbuf_size2_95_sram_blwl_out[113:113] ,mux_1level_tapbuf_size2_95_sram_blwl_outb[113:113] ,mux_1level_tapbuf_size2_95_configbus0[113:113], mux_1level_tapbuf_size2_95_configbus1[113:113] , mux_1level_tapbuf_size2_95_configbus0_b[113:113] ); -wire [0:1] mux_1level_tapbuf_size2_96_inbus; -assign mux_1level_tapbuf_size2_96_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_96_inbus[1] = chanx_1__1__in_14_ ; -wire [114:114] mux_1level_tapbuf_size2_96_configbus0; -wire [114:114] mux_1level_tapbuf_size2_96_configbus1; -wire [114:114] mux_1level_tapbuf_size2_96_sram_blwl_out ; -wire [114:114] mux_1level_tapbuf_size2_96_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_96_configbus0[114:114] = sram_blwl_bl[114:114] ; -assign mux_1level_tapbuf_size2_96_configbus1[114:114] = sram_blwl_wl[114:114] ; -wire [114:114] mux_1level_tapbuf_size2_96_configbus0_b; -assign mux_1level_tapbuf_size2_96_configbus0_b[114:114] = sram_blwl_blb[114:114] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_96_ (mux_1level_tapbuf_size2_96_inbus, chany_1__1__out_13_ , mux_1level_tapbuf_size2_96_sram_blwl_out[114:114] , -mux_1level_tapbuf_size2_96_sram_blwl_outb[114:114] ); -//----- SRAM bits for MUX[96], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_114_ (mux_1level_tapbuf_size2_96_sram_blwl_out[114:114] ,mux_1level_tapbuf_size2_96_sram_blwl_out[114:114] ,mux_1level_tapbuf_size2_96_sram_blwl_outb[114:114] ,mux_1level_tapbuf_size2_96_configbus0[114:114], mux_1level_tapbuf_size2_96_configbus1[114:114] , mux_1level_tapbuf_size2_96_configbus0_b[114:114] ); -wire [0:1] mux_1level_tapbuf_size2_97_inbus; -assign mux_1level_tapbuf_size2_97_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_97_inbus[1] = chanx_1__1__in_16_ ; -wire [115:115] mux_1level_tapbuf_size2_97_configbus0; -wire [115:115] mux_1level_tapbuf_size2_97_configbus1; -wire [115:115] mux_1level_tapbuf_size2_97_sram_blwl_out ; -wire [115:115] mux_1level_tapbuf_size2_97_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_97_configbus0[115:115] = sram_blwl_bl[115:115] ; -assign mux_1level_tapbuf_size2_97_configbus1[115:115] = sram_blwl_wl[115:115] ; -wire [115:115] mux_1level_tapbuf_size2_97_configbus0_b; -assign mux_1level_tapbuf_size2_97_configbus0_b[115:115] = sram_blwl_blb[115:115] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_97_ (mux_1level_tapbuf_size2_97_inbus, chany_1__1__out_15_ , mux_1level_tapbuf_size2_97_sram_blwl_out[115:115] , -mux_1level_tapbuf_size2_97_sram_blwl_outb[115:115] ); -//----- SRAM bits for MUX[97], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_115_ (mux_1level_tapbuf_size2_97_sram_blwl_out[115:115] ,mux_1level_tapbuf_size2_97_sram_blwl_out[115:115] ,mux_1level_tapbuf_size2_97_sram_blwl_outb[115:115] ,mux_1level_tapbuf_size2_97_configbus0[115:115], mux_1level_tapbuf_size2_97_configbus1[115:115] , mux_1level_tapbuf_size2_97_configbus0_b[115:115] ); -wire [0:1] mux_1level_tapbuf_size2_98_inbus; -assign mux_1level_tapbuf_size2_98_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_98_inbus[1] = chanx_1__1__in_18_ ; -wire [116:116] mux_1level_tapbuf_size2_98_configbus0; -wire [116:116] mux_1level_tapbuf_size2_98_configbus1; -wire [116:116] mux_1level_tapbuf_size2_98_sram_blwl_out ; -wire [116:116] mux_1level_tapbuf_size2_98_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_98_configbus0[116:116] = sram_blwl_bl[116:116] ; -assign mux_1level_tapbuf_size2_98_configbus1[116:116] = sram_blwl_wl[116:116] ; -wire [116:116] mux_1level_tapbuf_size2_98_configbus0_b; -assign mux_1level_tapbuf_size2_98_configbus0_b[116:116] = sram_blwl_blb[116:116] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_98_ (mux_1level_tapbuf_size2_98_inbus, chany_1__1__out_17_ , mux_1level_tapbuf_size2_98_sram_blwl_out[116:116] , -mux_1level_tapbuf_size2_98_sram_blwl_outb[116:116] ); -//----- SRAM bits for MUX[98], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_116_ (mux_1level_tapbuf_size2_98_sram_blwl_out[116:116] ,mux_1level_tapbuf_size2_98_sram_blwl_out[116:116] ,mux_1level_tapbuf_size2_98_sram_blwl_outb[116:116] ,mux_1level_tapbuf_size2_98_configbus0[116:116], mux_1level_tapbuf_size2_98_configbus1[116:116] , mux_1level_tapbuf_size2_98_configbus0_b[116:116] ); -wire [0:1] mux_1level_tapbuf_size2_99_inbus; -assign mux_1level_tapbuf_size2_99_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_99_inbus[1] = chanx_1__1__in_20_ ; -wire [117:117] mux_1level_tapbuf_size2_99_configbus0; -wire [117:117] mux_1level_tapbuf_size2_99_configbus1; -wire [117:117] mux_1level_tapbuf_size2_99_sram_blwl_out ; -wire [117:117] mux_1level_tapbuf_size2_99_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_99_configbus0[117:117] = sram_blwl_bl[117:117] ; -assign mux_1level_tapbuf_size2_99_configbus1[117:117] = sram_blwl_wl[117:117] ; -wire [117:117] mux_1level_tapbuf_size2_99_configbus0_b; -assign mux_1level_tapbuf_size2_99_configbus0_b[117:117] = sram_blwl_blb[117:117] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_99_ (mux_1level_tapbuf_size2_99_inbus, chany_1__1__out_19_ , mux_1level_tapbuf_size2_99_sram_blwl_out[117:117] , -mux_1level_tapbuf_size2_99_sram_blwl_outb[117:117] ); -//----- SRAM bits for MUX[99], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_117_ (mux_1level_tapbuf_size2_99_sram_blwl_out[117:117] ,mux_1level_tapbuf_size2_99_sram_blwl_out[117:117] ,mux_1level_tapbuf_size2_99_sram_blwl_outb[117:117] ,mux_1level_tapbuf_size2_99_configbus0[117:117], mux_1level_tapbuf_size2_99_configbus1[117:117] , mux_1level_tapbuf_size2_99_configbus0_b[117:117] ); -wire [0:1] mux_1level_tapbuf_size2_100_inbus; -assign mux_1level_tapbuf_size2_100_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_100_inbus[1] = chanx_1__1__in_22_ ; -wire [118:118] mux_1level_tapbuf_size2_100_configbus0; -wire [118:118] mux_1level_tapbuf_size2_100_configbus1; -wire [118:118] mux_1level_tapbuf_size2_100_sram_blwl_out ; -wire [118:118] mux_1level_tapbuf_size2_100_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_100_configbus0[118:118] = sram_blwl_bl[118:118] ; -assign mux_1level_tapbuf_size2_100_configbus1[118:118] = sram_blwl_wl[118:118] ; -wire [118:118] mux_1level_tapbuf_size2_100_configbus0_b; -assign mux_1level_tapbuf_size2_100_configbus0_b[118:118] = sram_blwl_blb[118:118] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_100_ (mux_1level_tapbuf_size2_100_inbus, chany_1__1__out_21_ , mux_1level_tapbuf_size2_100_sram_blwl_out[118:118] , -mux_1level_tapbuf_size2_100_sram_blwl_outb[118:118] ); -//----- SRAM bits for MUX[100], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_118_ (mux_1level_tapbuf_size2_100_sram_blwl_out[118:118] ,mux_1level_tapbuf_size2_100_sram_blwl_out[118:118] ,mux_1level_tapbuf_size2_100_sram_blwl_outb[118:118] ,mux_1level_tapbuf_size2_100_configbus0[118:118], mux_1level_tapbuf_size2_100_configbus1[118:118] , mux_1level_tapbuf_size2_100_configbus0_b[118:118] ); -wire [0:1] mux_1level_tapbuf_size2_101_inbus; -assign mux_1level_tapbuf_size2_101_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_101_inbus[1] = chanx_1__1__in_24_ ; -wire [119:119] mux_1level_tapbuf_size2_101_configbus0; -wire [119:119] mux_1level_tapbuf_size2_101_configbus1; -wire [119:119] mux_1level_tapbuf_size2_101_sram_blwl_out ; -wire [119:119] mux_1level_tapbuf_size2_101_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_101_configbus0[119:119] = sram_blwl_bl[119:119] ; -assign mux_1level_tapbuf_size2_101_configbus1[119:119] = sram_blwl_wl[119:119] ; -wire [119:119] mux_1level_tapbuf_size2_101_configbus0_b; -assign mux_1level_tapbuf_size2_101_configbus0_b[119:119] = sram_blwl_blb[119:119] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_101_ (mux_1level_tapbuf_size2_101_inbus, chany_1__1__out_23_ , mux_1level_tapbuf_size2_101_sram_blwl_out[119:119] , -mux_1level_tapbuf_size2_101_sram_blwl_outb[119:119] ); -//----- SRAM bits for MUX[101], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_119_ (mux_1level_tapbuf_size2_101_sram_blwl_out[119:119] ,mux_1level_tapbuf_size2_101_sram_blwl_out[119:119] ,mux_1level_tapbuf_size2_101_sram_blwl_outb[119:119] ,mux_1level_tapbuf_size2_101_configbus0[119:119], mux_1level_tapbuf_size2_101_configbus1[119:119] , mux_1level_tapbuf_size2_101_configbus0_b[119:119] ); -wire [0:1] mux_1level_tapbuf_size2_102_inbus; -assign mux_1level_tapbuf_size2_102_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_102_inbus[1] = chanx_1__1__in_26_ ; -wire [120:120] mux_1level_tapbuf_size2_102_configbus0; -wire [120:120] mux_1level_tapbuf_size2_102_configbus1; -wire [120:120] mux_1level_tapbuf_size2_102_sram_blwl_out ; -wire [120:120] mux_1level_tapbuf_size2_102_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_102_configbus0[120:120] = sram_blwl_bl[120:120] ; -assign mux_1level_tapbuf_size2_102_configbus1[120:120] = sram_blwl_wl[120:120] ; -wire [120:120] mux_1level_tapbuf_size2_102_configbus0_b; -assign mux_1level_tapbuf_size2_102_configbus0_b[120:120] = sram_blwl_blb[120:120] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_102_ (mux_1level_tapbuf_size2_102_inbus, chany_1__1__out_25_ , mux_1level_tapbuf_size2_102_sram_blwl_out[120:120] , -mux_1level_tapbuf_size2_102_sram_blwl_outb[120:120] ); -//----- SRAM bits for MUX[102], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_120_ (mux_1level_tapbuf_size2_102_sram_blwl_out[120:120] ,mux_1level_tapbuf_size2_102_sram_blwl_out[120:120] ,mux_1level_tapbuf_size2_102_sram_blwl_outb[120:120] ,mux_1level_tapbuf_size2_102_configbus0[120:120], mux_1level_tapbuf_size2_102_configbus1[120:120] , mux_1level_tapbuf_size2_102_configbus0_b[120:120] ); -wire [0:1] mux_1level_tapbuf_size2_103_inbus; -assign mux_1level_tapbuf_size2_103_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_103_inbus[1] = chanx_1__1__in_28_ ; -wire [121:121] mux_1level_tapbuf_size2_103_configbus0; -wire [121:121] mux_1level_tapbuf_size2_103_configbus1; -wire [121:121] mux_1level_tapbuf_size2_103_sram_blwl_out ; -wire [121:121] mux_1level_tapbuf_size2_103_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_103_configbus0[121:121] = sram_blwl_bl[121:121] ; -assign mux_1level_tapbuf_size2_103_configbus1[121:121] = sram_blwl_wl[121:121] ; -wire [121:121] mux_1level_tapbuf_size2_103_configbus0_b; -assign mux_1level_tapbuf_size2_103_configbus0_b[121:121] = sram_blwl_blb[121:121] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_103_ (mux_1level_tapbuf_size2_103_inbus, chany_1__1__out_27_ , mux_1level_tapbuf_size2_103_sram_blwl_out[121:121] , -mux_1level_tapbuf_size2_103_sram_blwl_outb[121:121] ); -//----- SRAM bits for MUX[103], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_121_ (mux_1level_tapbuf_size2_103_sram_blwl_out[121:121] ,mux_1level_tapbuf_size2_103_sram_blwl_out[121:121] ,mux_1level_tapbuf_size2_103_sram_blwl_outb[121:121] ,mux_1level_tapbuf_size2_103_configbus0[121:121], mux_1level_tapbuf_size2_103_configbus1[121:121] , mux_1level_tapbuf_size2_103_configbus0_b[121:121] ); -wire [0:1] mux_1level_tapbuf_size2_104_inbus; -assign mux_1level_tapbuf_size2_104_inbus[0] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size2_104_inbus[1] = chanx_1__1__in_0_ ; -wire [122:122] mux_1level_tapbuf_size2_104_configbus0; -wire [122:122] mux_1level_tapbuf_size2_104_configbus1; -wire [122:122] mux_1level_tapbuf_size2_104_sram_blwl_out ; -wire [122:122] mux_1level_tapbuf_size2_104_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_104_configbus0[122:122] = sram_blwl_bl[122:122] ; -assign mux_1level_tapbuf_size2_104_configbus1[122:122] = sram_blwl_wl[122:122] ; -wire [122:122] mux_1level_tapbuf_size2_104_configbus0_b; -assign mux_1level_tapbuf_size2_104_configbus0_b[122:122] = sram_blwl_blb[122:122] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_104_ (mux_1level_tapbuf_size2_104_inbus, chany_1__1__out_29_ , mux_1level_tapbuf_size2_104_sram_blwl_out[122:122] , -mux_1level_tapbuf_size2_104_sram_blwl_outb[122:122] ); -//----- SRAM bits for MUX[104], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_122_ (mux_1level_tapbuf_size2_104_sram_blwl_out[122:122] ,mux_1level_tapbuf_size2_104_sram_blwl_out[122:122] ,mux_1level_tapbuf_size2_104_sram_blwl_outb[122:122] ,mux_1level_tapbuf_size2_104_configbus0[122:122], mux_1level_tapbuf_size2_104_configbus1[122:122] , mux_1level_tapbuf_size2_104_configbus0_b[122:122] ); -//----- left side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_105_inbus; -assign mux_1level_tapbuf_size3_105_inbus[0] = grid_1__1__pin_0__0__4_; -assign mux_1level_tapbuf_size3_105_inbus[1] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size3_105_inbus[2] = chany_1__1__in_28_ ; -wire [123:125] mux_1level_tapbuf_size3_105_configbus0; -wire [123:125] mux_1level_tapbuf_size3_105_configbus1; -wire [123:125] mux_1level_tapbuf_size3_105_sram_blwl_out ; -wire [123:125] mux_1level_tapbuf_size3_105_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_105_configbus0[123:125] = sram_blwl_bl[123:125] ; -assign mux_1level_tapbuf_size3_105_configbus1[123:125] = sram_blwl_wl[123:125] ; -wire [123:125] mux_1level_tapbuf_size3_105_configbus0_b; -assign mux_1level_tapbuf_size3_105_configbus0_b[123:125] = sram_blwl_blb[123:125] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_105_ (mux_1level_tapbuf_size3_105_inbus, chanx_1__1__out_1_ , mux_1level_tapbuf_size3_105_sram_blwl_out[123:125] , -mux_1level_tapbuf_size3_105_sram_blwl_outb[123:125] ); -//----- SRAM bits for MUX[105], level=1, select_path_id=1. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----010----- -sram6T_blwl sram_blwl_123_ (mux_1level_tapbuf_size3_105_sram_blwl_out[123:123] ,mux_1level_tapbuf_size3_105_sram_blwl_out[123:123] ,mux_1level_tapbuf_size3_105_sram_blwl_outb[123:123] ,mux_1level_tapbuf_size3_105_configbus0[123:123], mux_1level_tapbuf_size3_105_configbus1[123:123] , mux_1level_tapbuf_size3_105_configbus0_b[123:123] ); -sram6T_blwl sram_blwl_124_ (mux_1level_tapbuf_size3_105_sram_blwl_out[124:124] ,mux_1level_tapbuf_size3_105_sram_blwl_out[124:124] ,mux_1level_tapbuf_size3_105_sram_blwl_outb[124:124] ,mux_1level_tapbuf_size3_105_configbus0[124:124], mux_1level_tapbuf_size3_105_configbus1[124:124] , mux_1level_tapbuf_size3_105_configbus0_b[124:124] ); -sram6T_blwl sram_blwl_125_ (mux_1level_tapbuf_size3_105_sram_blwl_out[125:125] ,mux_1level_tapbuf_size3_105_sram_blwl_out[125:125] ,mux_1level_tapbuf_size3_105_sram_blwl_outb[125:125] ,mux_1level_tapbuf_size3_105_configbus0[125:125], mux_1level_tapbuf_size3_105_configbus1[125:125] , mux_1level_tapbuf_size3_105_configbus0_b[125:125] ); -wire [0:2] mux_1level_tapbuf_size3_106_inbus; -assign mux_1level_tapbuf_size3_106_inbus[0] = grid_1__1__pin_0__0__4_; -assign mux_1level_tapbuf_size3_106_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_106_inbus[2] = chany_1__1__in_0_ ; -wire [126:128] mux_1level_tapbuf_size3_106_configbus0; -wire [126:128] mux_1level_tapbuf_size3_106_configbus1; -wire [126:128] mux_1level_tapbuf_size3_106_sram_blwl_out ; -wire [126:128] mux_1level_tapbuf_size3_106_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_106_configbus0[126:128] = sram_blwl_bl[126:128] ; -assign mux_1level_tapbuf_size3_106_configbus1[126:128] = sram_blwl_wl[126:128] ; -wire [126:128] mux_1level_tapbuf_size3_106_configbus0_b; -assign mux_1level_tapbuf_size3_106_configbus0_b[126:128] = sram_blwl_blb[126:128] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_106_ (mux_1level_tapbuf_size3_106_inbus, chanx_1__1__out_3_ , mux_1level_tapbuf_size3_106_sram_blwl_out[126:128] , -mux_1level_tapbuf_size3_106_sram_blwl_outb[126:128] ); -//----- SRAM bits for MUX[106], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_126_ (mux_1level_tapbuf_size3_106_sram_blwl_out[126:126] ,mux_1level_tapbuf_size3_106_sram_blwl_out[126:126] ,mux_1level_tapbuf_size3_106_sram_blwl_outb[126:126] ,mux_1level_tapbuf_size3_106_configbus0[126:126], mux_1level_tapbuf_size3_106_configbus1[126:126] , mux_1level_tapbuf_size3_106_configbus0_b[126:126] ); -sram6T_blwl sram_blwl_127_ (mux_1level_tapbuf_size3_106_sram_blwl_out[127:127] ,mux_1level_tapbuf_size3_106_sram_blwl_out[127:127] ,mux_1level_tapbuf_size3_106_sram_blwl_outb[127:127] ,mux_1level_tapbuf_size3_106_configbus0[127:127], mux_1level_tapbuf_size3_106_configbus1[127:127] , mux_1level_tapbuf_size3_106_configbus0_b[127:127] ); -sram6T_blwl sram_blwl_128_ (mux_1level_tapbuf_size3_106_sram_blwl_out[128:128] ,mux_1level_tapbuf_size3_106_sram_blwl_out[128:128] ,mux_1level_tapbuf_size3_106_sram_blwl_outb[128:128] ,mux_1level_tapbuf_size3_106_configbus0[128:128], mux_1level_tapbuf_size3_106_configbus1[128:128] , mux_1level_tapbuf_size3_106_configbus0_b[128:128] ); -wire [0:2] mux_1level_tapbuf_size3_107_inbus; -assign mux_1level_tapbuf_size3_107_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size3_107_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_107_inbus[2] = chany_1__1__in_2_ ; -wire [129:131] mux_1level_tapbuf_size3_107_configbus0; -wire [129:131] mux_1level_tapbuf_size3_107_configbus1; -wire [129:131] mux_1level_tapbuf_size3_107_sram_blwl_out ; -wire [129:131] mux_1level_tapbuf_size3_107_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_107_configbus0[129:131] = sram_blwl_bl[129:131] ; -assign mux_1level_tapbuf_size3_107_configbus1[129:131] = sram_blwl_wl[129:131] ; -wire [129:131] mux_1level_tapbuf_size3_107_configbus0_b; -assign mux_1level_tapbuf_size3_107_configbus0_b[129:131] = sram_blwl_blb[129:131] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_107_ (mux_1level_tapbuf_size3_107_inbus, chanx_1__1__out_5_ , mux_1level_tapbuf_size3_107_sram_blwl_out[129:131] , -mux_1level_tapbuf_size3_107_sram_blwl_outb[129:131] ); -//----- SRAM bits for MUX[107], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_129_ (mux_1level_tapbuf_size3_107_sram_blwl_out[129:129] ,mux_1level_tapbuf_size3_107_sram_blwl_out[129:129] ,mux_1level_tapbuf_size3_107_sram_blwl_outb[129:129] ,mux_1level_tapbuf_size3_107_configbus0[129:129], mux_1level_tapbuf_size3_107_configbus1[129:129] , mux_1level_tapbuf_size3_107_configbus0_b[129:129] ); -sram6T_blwl sram_blwl_130_ (mux_1level_tapbuf_size3_107_sram_blwl_out[130:130] ,mux_1level_tapbuf_size3_107_sram_blwl_out[130:130] ,mux_1level_tapbuf_size3_107_sram_blwl_outb[130:130] ,mux_1level_tapbuf_size3_107_configbus0[130:130], mux_1level_tapbuf_size3_107_configbus1[130:130] , mux_1level_tapbuf_size3_107_configbus0_b[130:130] ); -sram6T_blwl sram_blwl_131_ (mux_1level_tapbuf_size3_107_sram_blwl_out[131:131] ,mux_1level_tapbuf_size3_107_sram_blwl_out[131:131] ,mux_1level_tapbuf_size3_107_sram_blwl_outb[131:131] ,mux_1level_tapbuf_size3_107_configbus0[131:131], mux_1level_tapbuf_size3_107_configbus1[131:131] , mux_1level_tapbuf_size3_107_configbus0_b[131:131] ); -wire [0:1] mux_1level_tapbuf_size2_108_inbus; -assign mux_1level_tapbuf_size2_108_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_108_inbus[1] = chany_1__1__in_4_ ; -wire [132:132] mux_1level_tapbuf_size2_108_configbus0; -wire [132:132] mux_1level_tapbuf_size2_108_configbus1; -wire [132:132] mux_1level_tapbuf_size2_108_sram_blwl_out ; -wire [132:132] mux_1level_tapbuf_size2_108_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_108_configbus0[132:132] = sram_blwl_bl[132:132] ; -assign mux_1level_tapbuf_size2_108_configbus1[132:132] = sram_blwl_wl[132:132] ; -wire [132:132] mux_1level_tapbuf_size2_108_configbus0_b; -assign mux_1level_tapbuf_size2_108_configbus0_b[132:132] = sram_blwl_blb[132:132] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_108_ (mux_1level_tapbuf_size2_108_inbus, chanx_1__1__out_7_ , mux_1level_tapbuf_size2_108_sram_blwl_out[132:132] , -mux_1level_tapbuf_size2_108_sram_blwl_outb[132:132] ); -//----- SRAM bits for MUX[108], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_132_ (mux_1level_tapbuf_size2_108_sram_blwl_out[132:132] ,mux_1level_tapbuf_size2_108_sram_blwl_out[132:132] ,mux_1level_tapbuf_size2_108_sram_blwl_outb[132:132] ,mux_1level_tapbuf_size2_108_configbus0[132:132], mux_1level_tapbuf_size2_108_configbus1[132:132] , mux_1level_tapbuf_size2_108_configbus0_b[132:132] ); -wire [0:1] mux_1level_tapbuf_size2_109_inbus; -assign mux_1level_tapbuf_size2_109_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_109_inbus[1] = chany_1__1__in_6_ ; -wire [133:133] mux_1level_tapbuf_size2_109_configbus0; -wire [133:133] mux_1level_tapbuf_size2_109_configbus1; -wire [133:133] mux_1level_tapbuf_size2_109_sram_blwl_out ; -wire [133:133] mux_1level_tapbuf_size2_109_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_109_configbus0[133:133] = sram_blwl_bl[133:133] ; -assign mux_1level_tapbuf_size2_109_configbus1[133:133] = sram_blwl_wl[133:133] ; -wire [133:133] mux_1level_tapbuf_size2_109_configbus0_b; -assign mux_1level_tapbuf_size2_109_configbus0_b[133:133] = sram_blwl_blb[133:133] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_109_ (mux_1level_tapbuf_size2_109_inbus, chanx_1__1__out_9_ , mux_1level_tapbuf_size2_109_sram_blwl_out[133:133] , -mux_1level_tapbuf_size2_109_sram_blwl_outb[133:133] ); -//----- SRAM bits for MUX[109], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_133_ (mux_1level_tapbuf_size2_109_sram_blwl_out[133:133] ,mux_1level_tapbuf_size2_109_sram_blwl_out[133:133] ,mux_1level_tapbuf_size2_109_sram_blwl_outb[133:133] ,mux_1level_tapbuf_size2_109_configbus0[133:133], mux_1level_tapbuf_size2_109_configbus1[133:133] , mux_1level_tapbuf_size2_109_configbus0_b[133:133] ); -wire [0:1] mux_1level_tapbuf_size2_110_inbus; -assign mux_1level_tapbuf_size2_110_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_110_inbus[1] = chany_1__1__in_8_ ; -wire [134:134] mux_1level_tapbuf_size2_110_configbus0; -wire [134:134] mux_1level_tapbuf_size2_110_configbus1; -wire [134:134] mux_1level_tapbuf_size2_110_sram_blwl_out ; -wire [134:134] mux_1level_tapbuf_size2_110_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_110_configbus0[134:134] = sram_blwl_bl[134:134] ; -assign mux_1level_tapbuf_size2_110_configbus1[134:134] = sram_blwl_wl[134:134] ; -wire [134:134] mux_1level_tapbuf_size2_110_configbus0_b; -assign mux_1level_tapbuf_size2_110_configbus0_b[134:134] = sram_blwl_blb[134:134] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_110_ (mux_1level_tapbuf_size2_110_inbus, chanx_1__1__out_11_ , mux_1level_tapbuf_size2_110_sram_blwl_out[134:134] , -mux_1level_tapbuf_size2_110_sram_blwl_outb[134:134] ); -//----- SRAM bits for MUX[110], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_134_ (mux_1level_tapbuf_size2_110_sram_blwl_out[134:134] ,mux_1level_tapbuf_size2_110_sram_blwl_out[134:134] ,mux_1level_tapbuf_size2_110_sram_blwl_outb[134:134] ,mux_1level_tapbuf_size2_110_configbus0[134:134], mux_1level_tapbuf_size2_110_configbus1[134:134] , mux_1level_tapbuf_size2_110_configbus0_b[134:134] ); -wire [0:1] mux_1level_tapbuf_size2_111_inbus; -assign mux_1level_tapbuf_size2_111_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_111_inbus[1] = chany_1__1__in_10_ ; -wire [135:135] mux_1level_tapbuf_size2_111_configbus0; -wire [135:135] mux_1level_tapbuf_size2_111_configbus1; -wire [135:135] mux_1level_tapbuf_size2_111_sram_blwl_out ; -wire [135:135] mux_1level_tapbuf_size2_111_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_111_configbus0[135:135] = sram_blwl_bl[135:135] ; -assign mux_1level_tapbuf_size2_111_configbus1[135:135] = sram_blwl_wl[135:135] ; -wire [135:135] mux_1level_tapbuf_size2_111_configbus0_b; -assign mux_1level_tapbuf_size2_111_configbus0_b[135:135] = sram_blwl_blb[135:135] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_111_ (mux_1level_tapbuf_size2_111_inbus, chanx_1__1__out_13_ , mux_1level_tapbuf_size2_111_sram_blwl_out[135:135] , -mux_1level_tapbuf_size2_111_sram_blwl_outb[135:135] ); -//----- SRAM bits for MUX[111], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_135_ (mux_1level_tapbuf_size2_111_sram_blwl_out[135:135] ,mux_1level_tapbuf_size2_111_sram_blwl_out[135:135] ,mux_1level_tapbuf_size2_111_sram_blwl_outb[135:135] ,mux_1level_tapbuf_size2_111_configbus0[135:135], mux_1level_tapbuf_size2_111_configbus1[135:135] , mux_1level_tapbuf_size2_111_configbus0_b[135:135] ); -wire [0:1] mux_1level_tapbuf_size2_112_inbus; -assign mux_1level_tapbuf_size2_112_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_112_inbus[1] = chany_1__1__in_12_ ; -wire [136:136] mux_1level_tapbuf_size2_112_configbus0; -wire [136:136] mux_1level_tapbuf_size2_112_configbus1; -wire [136:136] mux_1level_tapbuf_size2_112_sram_blwl_out ; -wire [136:136] mux_1level_tapbuf_size2_112_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_112_configbus0[136:136] = sram_blwl_bl[136:136] ; -assign mux_1level_tapbuf_size2_112_configbus1[136:136] = sram_blwl_wl[136:136] ; -wire [136:136] mux_1level_tapbuf_size2_112_configbus0_b; -assign mux_1level_tapbuf_size2_112_configbus0_b[136:136] = sram_blwl_blb[136:136] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_112_ (mux_1level_tapbuf_size2_112_inbus, chanx_1__1__out_15_ , mux_1level_tapbuf_size2_112_sram_blwl_out[136:136] , -mux_1level_tapbuf_size2_112_sram_blwl_outb[136:136] ); -//----- SRAM bits for MUX[112], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_136_ (mux_1level_tapbuf_size2_112_sram_blwl_out[136:136] ,mux_1level_tapbuf_size2_112_sram_blwl_out[136:136] ,mux_1level_tapbuf_size2_112_sram_blwl_outb[136:136] ,mux_1level_tapbuf_size2_112_configbus0[136:136], mux_1level_tapbuf_size2_112_configbus1[136:136] , mux_1level_tapbuf_size2_112_configbus0_b[136:136] ); -wire [0:1] mux_1level_tapbuf_size2_113_inbus; -assign mux_1level_tapbuf_size2_113_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_113_inbus[1] = chany_1__1__in_14_ ; -wire [137:137] mux_1level_tapbuf_size2_113_configbus0; -wire [137:137] mux_1level_tapbuf_size2_113_configbus1; -wire [137:137] mux_1level_tapbuf_size2_113_sram_blwl_out ; -wire [137:137] mux_1level_tapbuf_size2_113_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_113_configbus0[137:137] = sram_blwl_bl[137:137] ; -assign mux_1level_tapbuf_size2_113_configbus1[137:137] = sram_blwl_wl[137:137] ; -wire [137:137] mux_1level_tapbuf_size2_113_configbus0_b; -assign mux_1level_tapbuf_size2_113_configbus0_b[137:137] = sram_blwl_blb[137:137] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_113_ (mux_1level_tapbuf_size2_113_inbus, chanx_1__1__out_17_ , mux_1level_tapbuf_size2_113_sram_blwl_out[137:137] , -mux_1level_tapbuf_size2_113_sram_blwl_outb[137:137] ); -//----- SRAM bits for MUX[113], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_137_ (mux_1level_tapbuf_size2_113_sram_blwl_out[137:137] ,mux_1level_tapbuf_size2_113_sram_blwl_out[137:137] ,mux_1level_tapbuf_size2_113_sram_blwl_outb[137:137] ,mux_1level_tapbuf_size2_113_configbus0[137:137], mux_1level_tapbuf_size2_113_configbus1[137:137] , mux_1level_tapbuf_size2_113_configbus0_b[137:137] ); -wire [0:1] mux_1level_tapbuf_size2_114_inbus; -assign mux_1level_tapbuf_size2_114_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_114_inbus[1] = chany_1__1__in_16_ ; -wire [138:138] mux_1level_tapbuf_size2_114_configbus0; -wire [138:138] mux_1level_tapbuf_size2_114_configbus1; -wire [138:138] mux_1level_tapbuf_size2_114_sram_blwl_out ; -wire [138:138] mux_1level_tapbuf_size2_114_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_114_configbus0[138:138] = sram_blwl_bl[138:138] ; -assign mux_1level_tapbuf_size2_114_configbus1[138:138] = sram_blwl_wl[138:138] ; -wire [138:138] mux_1level_tapbuf_size2_114_configbus0_b; -assign mux_1level_tapbuf_size2_114_configbus0_b[138:138] = sram_blwl_blb[138:138] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_114_ (mux_1level_tapbuf_size2_114_inbus, chanx_1__1__out_19_ , mux_1level_tapbuf_size2_114_sram_blwl_out[138:138] , -mux_1level_tapbuf_size2_114_sram_blwl_outb[138:138] ); -//----- SRAM bits for MUX[114], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_138_ (mux_1level_tapbuf_size2_114_sram_blwl_out[138:138] ,mux_1level_tapbuf_size2_114_sram_blwl_out[138:138] ,mux_1level_tapbuf_size2_114_sram_blwl_outb[138:138] ,mux_1level_tapbuf_size2_114_configbus0[138:138], mux_1level_tapbuf_size2_114_configbus1[138:138] , mux_1level_tapbuf_size2_114_configbus0_b[138:138] ); -wire [0:1] mux_1level_tapbuf_size2_115_inbus; -assign mux_1level_tapbuf_size2_115_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_115_inbus[1] = chany_1__1__in_18_ ; -wire [139:139] mux_1level_tapbuf_size2_115_configbus0; -wire [139:139] mux_1level_tapbuf_size2_115_configbus1; -wire [139:139] mux_1level_tapbuf_size2_115_sram_blwl_out ; -wire [139:139] mux_1level_tapbuf_size2_115_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_115_configbus0[139:139] = sram_blwl_bl[139:139] ; -assign mux_1level_tapbuf_size2_115_configbus1[139:139] = sram_blwl_wl[139:139] ; -wire [139:139] mux_1level_tapbuf_size2_115_configbus0_b; -assign mux_1level_tapbuf_size2_115_configbus0_b[139:139] = sram_blwl_blb[139:139] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_115_ (mux_1level_tapbuf_size2_115_inbus, chanx_1__1__out_21_ , mux_1level_tapbuf_size2_115_sram_blwl_out[139:139] , -mux_1level_tapbuf_size2_115_sram_blwl_outb[139:139] ); -//----- SRAM bits for MUX[115], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_139_ (mux_1level_tapbuf_size2_115_sram_blwl_out[139:139] ,mux_1level_tapbuf_size2_115_sram_blwl_out[139:139] ,mux_1level_tapbuf_size2_115_sram_blwl_outb[139:139] ,mux_1level_tapbuf_size2_115_configbus0[139:139], mux_1level_tapbuf_size2_115_configbus1[139:139] , mux_1level_tapbuf_size2_115_configbus0_b[139:139] ); -wire [0:1] mux_1level_tapbuf_size2_116_inbus; -assign mux_1level_tapbuf_size2_116_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_116_inbus[1] = chany_1__1__in_20_ ; -wire [140:140] mux_1level_tapbuf_size2_116_configbus0; -wire [140:140] mux_1level_tapbuf_size2_116_configbus1; -wire [140:140] mux_1level_tapbuf_size2_116_sram_blwl_out ; -wire [140:140] mux_1level_tapbuf_size2_116_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_116_configbus0[140:140] = sram_blwl_bl[140:140] ; -assign mux_1level_tapbuf_size2_116_configbus1[140:140] = sram_blwl_wl[140:140] ; -wire [140:140] mux_1level_tapbuf_size2_116_configbus0_b; -assign mux_1level_tapbuf_size2_116_configbus0_b[140:140] = sram_blwl_blb[140:140] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_116_ (mux_1level_tapbuf_size2_116_inbus, chanx_1__1__out_23_ , mux_1level_tapbuf_size2_116_sram_blwl_out[140:140] , -mux_1level_tapbuf_size2_116_sram_blwl_outb[140:140] ); -//----- SRAM bits for MUX[116], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_140_ (mux_1level_tapbuf_size2_116_sram_blwl_out[140:140] ,mux_1level_tapbuf_size2_116_sram_blwl_out[140:140] ,mux_1level_tapbuf_size2_116_sram_blwl_outb[140:140] ,mux_1level_tapbuf_size2_116_configbus0[140:140], mux_1level_tapbuf_size2_116_configbus1[140:140] , mux_1level_tapbuf_size2_116_configbus0_b[140:140] ); -wire [0:1] mux_1level_tapbuf_size2_117_inbus; -assign mux_1level_tapbuf_size2_117_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_117_inbus[1] = chany_1__1__in_22_ ; -wire [141:141] mux_1level_tapbuf_size2_117_configbus0; -wire [141:141] mux_1level_tapbuf_size2_117_configbus1; -wire [141:141] mux_1level_tapbuf_size2_117_sram_blwl_out ; -wire [141:141] mux_1level_tapbuf_size2_117_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_117_configbus0[141:141] = sram_blwl_bl[141:141] ; -assign mux_1level_tapbuf_size2_117_configbus1[141:141] = sram_blwl_wl[141:141] ; -wire [141:141] mux_1level_tapbuf_size2_117_configbus0_b; -assign mux_1level_tapbuf_size2_117_configbus0_b[141:141] = sram_blwl_blb[141:141] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_117_ (mux_1level_tapbuf_size2_117_inbus, chanx_1__1__out_25_ , mux_1level_tapbuf_size2_117_sram_blwl_out[141:141] , -mux_1level_tapbuf_size2_117_sram_blwl_outb[141:141] ); -//----- SRAM bits for MUX[117], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_141_ (mux_1level_tapbuf_size2_117_sram_blwl_out[141:141] ,mux_1level_tapbuf_size2_117_sram_blwl_out[141:141] ,mux_1level_tapbuf_size2_117_sram_blwl_outb[141:141] ,mux_1level_tapbuf_size2_117_configbus0[141:141], mux_1level_tapbuf_size2_117_configbus1[141:141] , mux_1level_tapbuf_size2_117_configbus0_b[141:141] ); -wire [0:1] mux_1level_tapbuf_size2_118_inbus; -assign mux_1level_tapbuf_size2_118_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_118_inbus[1] = chany_1__1__in_24_ ; -wire [142:142] mux_1level_tapbuf_size2_118_configbus0; -wire [142:142] mux_1level_tapbuf_size2_118_configbus1; -wire [142:142] mux_1level_tapbuf_size2_118_sram_blwl_out ; -wire [142:142] mux_1level_tapbuf_size2_118_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_118_configbus0[142:142] = sram_blwl_bl[142:142] ; -assign mux_1level_tapbuf_size2_118_configbus1[142:142] = sram_blwl_wl[142:142] ; -wire [142:142] mux_1level_tapbuf_size2_118_configbus0_b; -assign mux_1level_tapbuf_size2_118_configbus0_b[142:142] = sram_blwl_blb[142:142] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_118_ (mux_1level_tapbuf_size2_118_inbus, chanx_1__1__out_27_ , mux_1level_tapbuf_size2_118_sram_blwl_out[142:142] , -mux_1level_tapbuf_size2_118_sram_blwl_outb[142:142] ); -//----- SRAM bits for MUX[118], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_142_ (mux_1level_tapbuf_size2_118_sram_blwl_out[142:142] ,mux_1level_tapbuf_size2_118_sram_blwl_out[142:142] ,mux_1level_tapbuf_size2_118_sram_blwl_outb[142:142] ,mux_1level_tapbuf_size2_118_configbus0[142:142], mux_1level_tapbuf_size2_118_configbus1[142:142] , mux_1level_tapbuf_size2_118_configbus0_b[142:142] ); -wire [0:1] mux_1level_tapbuf_size2_119_inbus; -assign mux_1level_tapbuf_size2_119_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_119_inbus[1] = chany_1__1__in_26_ ; -wire [143:143] mux_1level_tapbuf_size2_119_configbus0; -wire [143:143] mux_1level_tapbuf_size2_119_configbus1; -wire [143:143] mux_1level_tapbuf_size2_119_sram_blwl_out ; -wire [143:143] mux_1level_tapbuf_size2_119_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_119_configbus0[143:143] = sram_blwl_bl[143:143] ; -assign mux_1level_tapbuf_size2_119_configbus1[143:143] = sram_blwl_wl[143:143] ; -wire [143:143] mux_1level_tapbuf_size2_119_configbus0_b; -assign mux_1level_tapbuf_size2_119_configbus0_b[143:143] = sram_blwl_blb[143:143] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_119_ (mux_1level_tapbuf_size2_119_inbus, chanx_1__1__out_29_ , mux_1level_tapbuf_size2_119_sram_blwl_out[143:143] , -mux_1level_tapbuf_size2_119_sram_blwl_outb[143:143] ); -//----- SRAM bits for MUX[119], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_143_ (mux_1level_tapbuf_size2_119_sram_blwl_out[143:143] ,mux_1level_tapbuf_size2_119_sram_blwl_out[143:143] ,mux_1level_tapbuf_size2_119_sram_blwl_outb[143:143] ,mux_1level_tapbuf_size2_119_configbus0[143:143], mux_1level_tapbuf_size2_119_configbus1[143:143] , mux_1level_tapbuf_size2_119_configbus0_b[143:143] ); -endmodule -//----- END Verilog Module of Switch Box[1][1] ----- - diff --git a/examples/verilog_test_example_1/sub_module/decoders.v b/examples/verilog_test_example_1/sub_module/decoders.v deleted file mode 100644 index ddcaef07d..000000000 --- a/examples/verilog_test_example_1/sub_module/decoders.v +++ /dev/null @@ -1,40 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog Decoders -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- BL Decoder convert 5 bits to binary 19 bits ----- -module bl_decoder5to19 ( -input wire enable, -input wire [4:0] addr_in, -input wire data_in, -output reg [0:18] addr_out -); -always@(addr_out,addr_in,enable, data_in) -begin - addr_out = 19'bz; - if (1'b1 == enable) begin - addr_out[addr_in] = data_in; - end -end -endmodule -//----- WL Decoder convert 5 bits to binary 19 bits ----- -module wl_decoder5to19 ( -input wire enable, -input wire [4:0] addr_in, -output reg [0:18] addr_out -); -always@(addr_out,addr_in,enable) -begin - addr_out = 19'b0; - if (1'b1 == enable) begin - addr_out[addr_in] = 1'b1; - end -end -endmodule diff --git a/examples/verilog_test_example_1/sub_module/inv_buf_passgate.v b/examples/verilog_test_example_1/sub_module/inv_buf_passgate.v deleted file mode 100644 index 5c638ad0c..000000000 --- a/examples/verilog_test_example_1/sub_module/inv_buf_passgate.v +++ /dev/null @@ -1,45 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Essential gates -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog module for INVTX1 ----- -module INVTX1 ( -input in, -output out -); -assign out = ~in; -endmodule - -//----- Verilog module for buf4 ----- -module buf4 ( -input in, -output out -); -assign out = in; -endmodule - -//----- Verilog module for tap_buf4 ----- -module tap_buf4 ( -input in, -output out -); -assign out = ~in; -endmodule - -//----- Verilog module for TGATE ----- -module TGATE ( -input in, -input sel, -input selb, -output out -); -assign out = sel? in : 1'bz; -endmodule - diff --git a/examples/verilog_test_example_1/sub_module/luts.v b/examples/verilog_test_example_1/sub_module/luts.v deleted file mode 100644 index d11f32123..000000000 --- a/examples/verilog_test_example_1/sub_module/luts.v +++ /dev/null @@ -1,23 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Look-Up Tables -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//-----LUT module, verilog_model_name=lut4 ----- -module lut4 (input wire [0:3] in, -output wire [0:0] out, -input wire [0:15] sram_out, -input wire [0:15] sram_outb -); - wire [0:3] in_b; - assign in_b = ~ in; - lut4_mux lut4_mux_0_ ( sram_out, out, in, in_b); -endmodule -//-----END LUT module, verilog_model_name=lut4 ----- - diff --git a/examples/verilog_test_example_1/sub_module/muxes.v b/examples/verilog_test_example_1/sub_module/muxes.v deleted file mode 100644 index cac6a58be..000000000 --- a/examples/verilog_test_example_1/sub_module/muxes.v +++ /dev/null @@ -1,211 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: MUXes used in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//---- Structural Verilog for CMOS MUX basis module: mux_2level_tapbuf_size4_basis ----- -module mux_2level_tapbuf_size4_basis ( -input [0:1] in, -output out, -input [0:1] mem, -input [0:1] mem_inv); -//---- Structure-level description ----- - TGATE TGATE_0 (in[0], mem[0], mem_inv[0], out); - TGATE TGATE_1 (in[1], mem[1], mem_inv[1], out); -endmodule -//---- END Structural Verilog CMOS MUX basis module: mux_2level_tapbuf_size4_basis ----- - -//----- CMOS MUX info: spice_model_name=mux_2level_tapbuf, size=4, structure: multi-level ----- -module mux_2level_tapbuf_size4 (input wire [0:3] in, -output wire out, -input wire [0:3] sram, -input wire [0:3] sram_inv -); -wire [0:3] mux2_l2_in; -wire [0:1] mux2_l1_in; -wire [0:0] mux2_l0_in; -mux_2level_tapbuf_size4_basis mux_basis_no0 (mux2_l2_in[0:1], mux2_l1_in[0], sram[2:3], sram_inv[2:3] ); - -mux_2level_tapbuf_size4_basis mux_basis_no1 (mux2_l2_in[2:3], mux2_l1_in[1], sram[2:3], sram_inv[2:3] ); - -mux_2level_tapbuf_size4_basis mux_basis_no2 (mux2_l1_in[0:1], mux2_l0_in[0], sram[0:1], sram_inv[0:1] ); - -INVTX1 inv0 (in[0], mux2_l2_in[0]); -INVTX1 inv1 (in[1], mux2_l2_in[1]); -INVTX1 inv2 (in[2], mux2_l2_in[2]); -INVTX1 inv3 (in[3], mux2_l2_in[3]); -tap_buf4 buf_out (mux2_l0_in[0], out ); -endmodule -//----- END CMOS MUX info: spice_model_name=mux_2level_tapbuf, size=4 ----- - - -//---- Structural Verilog for CMOS MUX basis module: lut4_size16_basis ----- -module lut4_size16_basis ( -input [0:1] in, -output out, -input [0:0] mem, -input [0:0] mem_inv); -//---- Structure-level description ----- - TGATE TGATE_0 (in[0], mem[0], mem_inv[0], out); - TGATE TGATE_1 (in[1], mem_inv[0], mem[0], out); -endmodule -//---- END Structural Verilog CMOS MUX basis module: lut4_size16_basis ----- - -//------ CMOS MUX info: spice_model_name= lut4_MUX, size=16 ----- -module lut4_mux( -input wire [0:15] in, -output wire out, -input wire [0:3] sram, -input wire [0:3] sram_inv -); -wire [0:15] mux2_l4_in; -wire [0:7] mux2_l3_in; -wire [0:3] mux2_l2_in; -wire [0:1] mux2_l1_in; -wire [0:0] mux2_l0_in; -lut4_size16_basis mux_basis_no0 (mux2_l4_in[0:1], mux2_l3_in[0], sram[0], sram_inv[0]); -lut4_size16_basis mux_basis_no1 (mux2_l4_in[2:3], mux2_l3_in[1], sram[0], sram_inv[0]); -lut4_size16_basis mux_basis_no2 (mux2_l4_in[4:5], mux2_l3_in[2], sram[0], sram_inv[0]); -lut4_size16_basis mux_basis_no3 (mux2_l4_in[6:7], mux2_l3_in[3], sram[0], sram_inv[0]); -lut4_size16_basis mux_basis_no4 (mux2_l4_in[8:9], mux2_l3_in[4], sram[0], sram_inv[0]); -lut4_size16_basis mux_basis_no5 (mux2_l4_in[10:11], mux2_l3_in[5], sram[0], sram_inv[0]); -lut4_size16_basis mux_basis_no6 (mux2_l4_in[12:13], mux2_l3_in[6], sram[0], sram_inv[0]); -lut4_size16_basis mux_basis_no7 (mux2_l4_in[14:15], mux2_l3_in[7], sram[0], sram_inv[0]); -lut4_size16_basis mux_basis_no8 (mux2_l3_in[0:1], mux2_l2_in[0], sram[1], sram_inv[1]); -lut4_size16_basis mux_basis_no9 (mux2_l3_in[2:3], mux2_l2_in[1], sram[1], sram_inv[1]); -lut4_size16_basis mux_basis_no10 (mux2_l3_in[4:5], mux2_l2_in[2], sram[1], sram_inv[1]); -lut4_size16_basis mux_basis_no11 (mux2_l3_in[6:7], mux2_l2_in[3], sram[1], sram_inv[1]); -lut4_size16_basis mux_basis_no12 (mux2_l2_in[0:1], mux2_l1_in[0], sram[2], sram_inv[2]); -lut4_size16_basis mux_basis_no13 (mux2_l2_in[2:3], mux2_l1_in[1], sram[2], sram_inv[2]); -lut4_size16_basis mux_basis_no14 (mux2_l1_in[0:1], mux2_l0_in[0], sram[3], sram_inv[3]); -INVTX1 inv0 (in[0], mux2_l4_in[0]); -INVTX1 inv1 (in[1], mux2_l4_in[1]); -INVTX1 inv2 (in[2], mux2_l4_in[2]); -INVTX1 inv3 (in[3], mux2_l4_in[3]); -INVTX1 inv4 (in[4], mux2_l4_in[4]); -INVTX1 inv5 (in[5], mux2_l4_in[5]); -INVTX1 inv6 (in[6], mux2_l4_in[6]); -INVTX1 inv7 (in[7], mux2_l4_in[7]); -INVTX1 inv8 (in[8], mux2_l4_in[8]); -INVTX1 inv9 (in[9], mux2_l4_in[9]); -INVTX1 inv10 (in[10], mux2_l4_in[10]); -INVTX1 inv11 (in[11], mux2_l4_in[11]); -INVTX1 inv12 (in[12], mux2_l4_in[12]); -INVTX1 inv13 (in[13], mux2_l4_in[13]); -INVTX1 inv14 (in[14], mux2_l4_in[14]); -INVTX1 inv15 (in[15], mux2_l4_in[15]); -INVTX1 inv_out (mux2_l0_in[0], out ); -endmodule -//----- END CMOS MUX info: spice_model_name=lut4, size=16 ----- - - -//---- Structural Verilog for CMOS MUX basis module: mux_2level_size5_basis ----- -module mux_2level_size5_basis ( -input [0:2] in, -output out, -input [0:2] mem, -input [0:2] mem_inv); -//---- Structure-level description ----- - TGATE TGATE_0 (in[0], mem[0], mem_inv[0], out); - TGATE TGATE_1 (in[1], mem[1], mem_inv[1], out); - TGATE TGATE_2 (in[2], mem[2], mem_inv[2], out); -endmodule -//---- END Structural Verilog CMOS MUX basis module: mux_2level_size5_basis ----- - -//----- CMOS MUX info: spice_model_name=mux_2level, size=5, structure: multi-level ----- -module mux_2level_size5 (input wire [0:4] in, -output wire out, -input wire [0:5] sram, -input wire [0:5] sram_inv -); -wire [0:2] mux2_l2_in; -wire [0:2] mux2_l1_in; -wire [0:0] mux2_l0_in; -mux_2level_size5_basis mux_basis_no0 (mux2_l2_in[0:2], mux2_l1_in[0], sram[3:5], sram_inv[3:5] ); - -mux_2level_size5_basis mux_basis_no1 (mux2_l1_in[0:2], mux2_l0_in[0], sram[0:2], sram_inv[0:2] ); - -INVTX1 inv0 (in[0], mux2_l2_in[0]); -INVTX1 inv1 (in[1], mux2_l2_in[1]); -INVTX1 inv2 (in[2], mux2_l2_in[2]); -INVTX1 inv3 (in[3], mux2_l1_in[1]); -INVTX1 inv4 (in[4], mux2_l1_in[2]); -INVTX1 inv_out (mux2_l0_in[0], out ); -endmodule -//----- END CMOS MUX info: spice_model_name=mux_2level, size=5 ----- - - -//---- Structural Verilog for CMOS MUX basis module: mux_1level_tapbuf_size2_basis ----- -module mux_1level_tapbuf_size2_basis ( -input [0:1] in, -output out, -input [0:0] mem, -input [0:0] mem_inv); -//---- Structure-level description ----- - TGATE TGATE_0 (in[0], mem[0], mem_inv[0], out); - TGATE TGATE_1 (in[1], mem_inv[0], mem[0], out); -endmodule -//---- END Structural Verilog CMOS MUX basis module: mux_1level_tapbuf_size2_basis ----- - -//----- CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=2, structure: one-level ----- -module mux_1level_tapbuf_size2 (input wire [0:1] in, -output wire out, -input wire [0:0] sram, -input wire [0:0] sram_inv -); -wire [0:1] mux2_l1_in; -wire [0:0] mux2_l0_in; -mux_1level_tapbuf_size2_basis mux_basis ( -//----- MUX inputs ----- -mux2_l1_in[0:1], mux2_l0_in[0], -//----- SRAM ports ----- -sram[0:0], sram_inv[0:0] -); -INVTX1 inv0 (in[0], mux2_l1_in[0]); -INVTX1 inv1 (in[1], mux2_l1_in[1]); -tap_buf4 buf_out (mux2_l0_in[0], out ); -endmodule -//----- END CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=2 ----- - - -//---- Structural Verilog for CMOS MUX basis module: mux_1level_tapbuf_size3_basis ----- -module mux_1level_tapbuf_size3_basis ( -input [0:2] in, -output out, -input [0:2] mem, -input [0:2] mem_inv); -//---- Structure-level description ----- - TGATE TGATE_0 (in[0], mem[0], mem_inv[0], out); - TGATE TGATE_1 (in[1], mem[1], mem_inv[1], out); - TGATE TGATE_2 (in[2], mem[2], mem_inv[2], out); -endmodule -//---- END Structural Verilog CMOS MUX basis module: mux_1level_tapbuf_size3_basis ----- - -//----- CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=3, structure: one-level ----- -module mux_1level_tapbuf_size3 (input wire [0:2] in, -output wire out, -input wire [0:2] sram, -input wire [0:2] sram_inv -); -wire [0:2] mux2_l1_in; -wire [0:0] mux2_l0_in; -mux_1level_tapbuf_size3_basis mux_basis ( -//----- MUX inputs ----- -mux2_l1_in[0:2], mux2_l0_in[0], -//----- SRAM ports ----- -sram[0:2], sram_inv[0:2] -); -INVTX1 inv0 (in[0], mux2_l1_in[0]); -INVTX1 inv1 (in[1], mux2_l1_in[1]); -INVTX1 inv2 (in[2], mux2_l1_in[2]); -tap_buf4 buf_out (mux2_l0_in[0], out ); -endmodule -//----- END CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=3 ----- - - diff --git a/examples/verilog_test_example_1/sub_module/wires.v b/examples/verilog_test_example_1/sub_module/wires.v deleted file mode 100644 index 592b9461a..000000000 --- a/examples/verilog_test_example_1/sub_module/wires.v +++ /dev/null @@ -1,43 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Wires -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:04 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//-----Wire module, verilog_model_name=direct_interc ----- -module direct_interc ( -input wire in, output wire out); - assign out = in; -endmodule -//-----END Wire module, verilog_model_name=direct_interc ----- - -//----- Wire models for segments in routing ----- -//-----Wire module, verilog_model_name=chan_segment ----- -module chan_segment_seg0 ( -input wire in, output wire out, output wire mid_out); - assign out = in; - assign mid_out = in; -endmodule -//-----END Wire module, verilog_model_name=chan_segment ----- - -//-----Wire module, verilog_model_name=chan_segment ----- -module chan_segment_seg1 ( -input wire in, output wire out, output wire mid_out); - assign out = in; - assign mid_out = in; -endmodule -//-----END Wire module, verilog_model_name=chan_segment ----- - -//-----Wire module, verilog_model_name=chan_segment ----- -module chan_segment_seg2 ( -input wire in, output wire out, output wire mid_out); - assign out = in; - assign mid_out = in; -endmodule -//-----END Wire module, verilog_model_name=chan_segment ----- - diff --git a/examples/verilog_test_example_2/example_2_top.v b/examples/verilog_test_example_2/example_2_top.v deleted file mode 100644 index 6b8f4c7aa..000000000 --- a/examples/verilog_test_example_2/example_2_top.v +++ /dev/null @@ -1,4970 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: FPGA Verilog Netlist for Design: example_2 -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Include User-defined netlists ----- -// `include "/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/ff.v" -// `include "/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/sram.v" -// `include "/research/ece/lnis/USERS/tang/tangxifan-eda-tools/branches/vpr7_rram/vpr/VerilogNetlists/io.v" -//----- Include subckt netlists: Multiplexers ----- -// `include "./verilog_test_example_2/routing/muxes.v" -//----- Include subckt netlists: Wires ----- -// `include "./verilog_test_example_2/routing/wires.v" -//----- Include subckt netlists: Look-Up Tables (LUTs) ----- -// `include "./verilog_test_example_2/routing/luts.v" -//------ Include subckt netlists: Logic Blocks ----- -// `include "./verilog_test_example_2/routing/logic_blocks.v" -//----- Include subckt netlists: Routing structures (Switch Boxes, Channels, Connection Boxes) ----- -// `include "./verilog_test_example_2/routing/routing.v" -//----- Include subckt netlists: Decoders (controller for memeory bank) ----- -// `include "./verilog_test_example_2/routing/decoders.v" -//----- Top-level Verilog Module ----- -module example_2_top ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -inout [31:0] gfpga_pad_iopad , //---FPGA inouts -input [0:0] en_bl , //--- BL enable port -input [0:0] en_wl , //--- WL enable port -input [0:0] data_in , //--- BL data input port -input [5:0] addr_bl , //--- Address of bit lines -input [5:0] addr_wl //--- Address of word lines -); -wire [0:51] bl_bus ; //--- Array Bit lines bus -wire [0:51] wl_bus ; //--- Array Bit lines bus -wire [0:51] blb_bus ; //--- Inverted Array Bit lines bus - - wire [0:2657] sram_blwl_bl; //---- Normal Bit lines - wire [0:2657] sram_blwl_wl; //---- Normal Word lines - wire [0:2657] sram_blwl_blb; //---- Inverted Normal Bit lines - INVTX1 INVTX1_blb_0 (bl_bus[0], blb_bus[0]); - INVTX1 INVTX1_blb_1 (bl_bus[1], blb_bus[1]); - INVTX1 INVTX1_blb_2 (bl_bus[2], blb_bus[2]); - INVTX1 INVTX1_blb_3 (bl_bus[3], blb_bus[3]); - INVTX1 INVTX1_blb_4 (bl_bus[4], blb_bus[4]); - INVTX1 INVTX1_blb_5 (bl_bus[5], blb_bus[5]); - INVTX1 INVTX1_blb_6 (bl_bus[6], blb_bus[6]); - INVTX1 INVTX1_blb_7 (bl_bus[7], blb_bus[7]); - INVTX1 INVTX1_blb_8 (bl_bus[8], blb_bus[8]); - INVTX1 INVTX1_blb_9 (bl_bus[9], blb_bus[9]); - INVTX1 INVTX1_blb_10 (bl_bus[10], blb_bus[10]); - INVTX1 INVTX1_blb_11 (bl_bus[11], blb_bus[11]); - INVTX1 INVTX1_blb_12 (bl_bus[12], blb_bus[12]); - INVTX1 INVTX1_blb_13 (bl_bus[13], blb_bus[13]); - INVTX1 INVTX1_blb_14 (bl_bus[14], blb_bus[14]); - INVTX1 INVTX1_blb_15 (bl_bus[15], blb_bus[15]); - INVTX1 INVTX1_blb_16 (bl_bus[16], blb_bus[16]); - INVTX1 INVTX1_blb_17 (bl_bus[17], blb_bus[17]); - INVTX1 INVTX1_blb_18 (bl_bus[18], blb_bus[18]); - INVTX1 INVTX1_blb_19 (bl_bus[19], blb_bus[19]); - INVTX1 INVTX1_blb_20 (bl_bus[20], blb_bus[20]); - INVTX1 INVTX1_blb_21 (bl_bus[21], blb_bus[21]); - INVTX1 INVTX1_blb_22 (bl_bus[22], blb_bus[22]); - INVTX1 INVTX1_blb_23 (bl_bus[23], blb_bus[23]); - INVTX1 INVTX1_blb_24 (bl_bus[24], blb_bus[24]); - INVTX1 INVTX1_blb_25 (bl_bus[25], blb_bus[25]); - INVTX1 INVTX1_blb_26 (bl_bus[26], blb_bus[26]); - INVTX1 INVTX1_blb_27 (bl_bus[27], blb_bus[27]); - INVTX1 INVTX1_blb_28 (bl_bus[28], blb_bus[28]); - INVTX1 INVTX1_blb_29 (bl_bus[29], blb_bus[29]); - INVTX1 INVTX1_blb_30 (bl_bus[30], blb_bus[30]); - INVTX1 INVTX1_blb_31 (bl_bus[31], blb_bus[31]); - INVTX1 INVTX1_blb_32 (bl_bus[32], blb_bus[32]); - INVTX1 INVTX1_blb_33 (bl_bus[33], blb_bus[33]); - INVTX1 INVTX1_blb_34 (bl_bus[34], blb_bus[34]); - INVTX1 INVTX1_blb_35 (bl_bus[35], blb_bus[35]); - INVTX1 INVTX1_blb_36 (bl_bus[36], blb_bus[36]); - INVTX1 INVTX1_blb_37 (bl_bus[37], blb_bus[37]); - INVTX1 INVTX1_blb_38 (bl_bus[38], blb_bus[38]); - INVTX1 INVTX1_blb_39 (bl_bus[39], blb_bus[39]); - INVTX1 INVTX1_blb_40 (bl_bus[40], blb_bus[40]); - INVTX1 INVTX1_blb_41 (bl_bus[41], blb_bus[41]); - INVTX1 INVTX1_blb_42 (bl_bus[42], blb_bus[42]); - INVTX1 INVTX1_blb_43 (bl_bus[43], blb_bus[43]); - INVTX1 INVTX1_blb_44 (bl_bus[44], blb_bus[44]); - INVTX1 INVTX1_blb_45 (bl_bus[45], blb_bus[45]); - INVTX1 INVTX1_blb_46 (bl_bus[46], blb_bus[46]); - INVTX1 INVTX1_blb_47 (bl_bus[47], blb_bus[47]); - INVTX1 INVTX1_blb_48 (bl_bus[48], blb_bus[48]); - INVTX1 INVTX1_blb_49 (bl_bus[49], blb_bus[49]); - INVTX1 INVTX1_blb_50 (bl_bus[50], blb_bus[50]); - assign sram_blwl_bl[0:51] = bl_bus[0:51]; - assign sram_blwl_blb[0:51] = blb_bus[0:51]; - assign sram_blwl_bl[52:103] = bl_bus[0:51]; - assign sram_blwl_blb[52:103] = blb_bus[0:51]; - assign sram_blwl_bl[104:155] = bl_bus[0:51]; - assign sram_blwl_blb[104:155] = blb_bus[0:51]; - assign sram_blwl_bl[156:207] = bl_bus[0:51]; - assign sram_blwl_blb[156:207] = blb_bus[0:51]; - assign sram_blwl_bl[208:259] = bl_bus[0:51]; - assign sram_blwl_blb[208:259] = blb_bus[0:51]; - assign sram_blwl_bl[260:311] = bl_bus[0:51]; - assign sram_blwl_blb[260:311] = blb_bus[0:51]; - assign sram_blwl_bl[312:363] = bl_bus[0:51]; - assign sram_blwl_blb[312:363] = blb_bus[0:51]; - assign sram_blwl_bl[364:415] = bl_bus[0:51]; - assign sram_blwl_blb[364:415] = blb_bus[0:51]; - assign sram_blwl_bl[416:467] = bl_bus[0:51]; - assign sram_blwl_blb[416:467] = blb_bus[0:51]; - assign sram_blwl_bl[468:519] = bl_bus[0:51]; - assign sram_blwl_blb[468:519] = blb_bus[0:51]; - assign sram_blwl_bl[520:571] = bl_bus[0:51]; - assign sram_blwl_blb[520:571] = blb_bus[0:51]; - assign sram_blwl_bl[572:623] = bl_bus[0:51]; - assign sram_blwl_blb[572:623] = blb_bus[0:51]; - assign sram_blwl_bl[624:675] = bl_bus[0:51]; - assign sram_blwl_blb[624:675] = blb_bus[0:51]; - assign sram_blwl_bl[676:727] = bl_bus[0:51]; - assign sram_blwl_blb[676:727] = blb_bus[0:51]; - assign sram_blwl_bl[728:779] = bl_bus[0:51]; - assign sram_blwl_blb[728:779] = blb_bus[0:51]; - assign sram_blwl_bl[780:831] = bl_bus[0:51]; - assign sram_blwl_blb[780:831] = blb_bus[0:51]; - assign sram_blwl_bl[832:883] = bl_bus[0:51]; - assign sram_blwl_blb[832:883] = blb_bus[0:51]; - assign sram_blwl_bl[884:935] = bl_bus[0:51]; - assign sram_blwl_blb[884:935] = blb_bus[0:51]; - assign sram_blwl_bl[936:987] = bl_bus[0:51]; - assign sram_blwl_blb[936:987] = blb_bus[0:51]; - assign sram_blwl_bl[988:1039] = bl_bus[0:51]; - assign sram_blwl_blb[988:1039] = blb_bus[0:51]; - assign sram_blwl_bl[1040:1091] = bl_bus[0:51]; - assign sram_blwl_blb[1040:1091] = blb_bus[0:51]; - assign sram_blwl_bl[1092:1143] = bl_bus[0:51]; - assign sram_blwl_blb[1092:1143] = blb_bus[0:51]; - assign sram_blwl_bl[1144:1195] = bl_bus[0:51]; - assign sram_blwl_blb[1144:1195] = blb_bus[0:51]; - assign sram_blwl_bl[1196:1247] = bl_bus[0:51]; - assign sram_blwl_blb[1196:1247] = blb_bus[0:51]; - assign sram_blwl_bl[1248:1299] = bl_bus[0:51]; - assign sram_blwl_blb[1248:1299] = blb_bus[0:51]; - assign sram_blwl_bl[1300:1351] = bl_bus[0:51]; - assign sram_blwl_blb[1300:1351] = blb_bus[0:51]; - assign sram_blwl_bl[1352:1403] = bl_bus[0:51]; - assign sram_blwl_blb[1352:1403] = blb_bus[0:51]; - assign sram_blwl_bl[1404:1455] = bl_bus[0:51]; - assign sram_blwl_blb[1404:1455] = blb_bus[0:51]; - assign sram_blwl_bl[1456:1507] = bl_bus[0:51]; - assign sram_blwl_blb[1456:1507] = blb_bus[0:51]; - assign sram_blwl_bl[1508:1559] = bl_bus[0:51]; - assign sram_blwl_blb[1508:1559] = blb_bus[0:51]; - assign sram_blwl_bl[1560:1611] = bl_bus[0:51]; - assign sram_blwl_blb[1560:1611] = blb_bus[0:51]; - assign sram_blwl_bl[1612:1663] = bl_bus[0:51]; - assign sram_blwl_blb[1612:1663] = blb_bus[0:51]; - assign sram_blwl_bl[1664:1715] = bl_bus[0:51]; - assign sram_blwl_blb[1664:1715] = blb_bus[0:51]; - assign sram_blwl_bl[1716:1767] = bl_bus[0:51]; - assign sram_blwl_blb[1716:1767] = blb_bus[0:51]; - assign sram_blwl_bl[1768:1819] = bl_bus[0:51]; - assign sram_blwl_blb[1768:1819] = blb_bus[0:51]; - assign sram_blwl_bl[1820:1871] = bl_bus[0:51]; - assign sram_blwl_blb[1820:1871] = blb_bus[0:51]; - assign sram_blwl_bl[1872:1923] = bl_bus[0:51]; - assign sram_blwl_blb[1872:1923] = blb_bus[0:51]; - assign sram_blwl_bl[1924:1975] = bl_bus[0:51]; - assign sram_blwl_blb[1924:1975] = blb_bus[0:51]; - assign sram_blwl_bl[1976:2027] = bl_bus[0:51]; - assign sram_blwl_blb[1976:2027] = blb_bus[0:51]; - assign sram_blwl_bl[2028:2079] = bl_bus[0:51]; - assign sram_blwl_blb[2028:2079] = blb_bus[0:51]; - assign sram_blwl_bl[2080:2131] = bl_bus[0:51]; - assign sram_blwl_blb[2080:2131] = blb_bus[0:51]; - assign sram_blwl_bl[2132:2183] = bl_bus[0:51]; - assign sram_blwl_blb[2132:2183] = blb_bus[0:51]; - assign sram_blwl_bl[2184:2235] = bl_bus[0:51]; - assign sram_blwl_blb[2184:2235] = blb_bus[0:51]; - assign sram_blwl_bl[2236:2287] = bl_bus[0:51]; - assign sram_blwl_blb[2236:2287] = blb_bus[0:51]; - assign sram_blwl_bl[2288:2339] = bl_bus[0:51]; - assign sram_blwl_blb[2288:2339] = blb_bus[0:51]; - assign sram_blwl_bl[2340:2391] = bl_bus[0:51]; - assign sram_blwl_blb[2340:2391] = blb_bus[0:51]; - assign sram_blwl_bl[2392:2443] = bl_bus[0:51]; - assign sram_blwl_blb[2392:2443] = blb_bus[0:51]; - assign sram_blwl_bl[2444:2495] = bl_bus[0:51]; - assign sram_blwl_blb[2444:2495] = blb_bus[0:51]; - assign sram_blwl_bl[2496:2547] = bl_bus[0:51]; - assign sram_blwl_blb[2496:2547] = blb_bus[0:51]; - assign sram_blwl_bl[2548:2599] = bl_bus[0:51]; - assign sram_blwl_blb[2548:2599] = blb_bus[0:51]; - assign sram_blwl_bl[2600:2651] = bl_bus[0:51]; - assign sram_blwl_blb[2600:2651] = blb_bus[0:51]; - assign sram_blwl_bl[2652:2657] = bl_bus[0:5]; - assign sram_blwl_blb[2652:2657] = blb_bus[0:5]; - assign sram_blwl_wl[0] = wl_bus[0]; - assign sram_blwl_wl[1] = wl_bus[0]; - assign sram_blwl_wl[2] = wl_bus[0]; - assign sram_blwl_wl[3] = wl_bus[0]; - assign sram_blwl_wl[4] = wl_bus[0]; - assign sram_blwl_wl[5] = wl_bus[0]; - assign sram_blwl_wl[6] = wl_bus[0]; - assign sram_blwl_wl[7] = wl_bus[0]; - assign sram_blwl_wl[8] = wl_bus[0]; - assign sram_blwl_wl[9] = wl_bus[0]; - assign sram_blwl_wl[10] = wl_bus[0]; - assign sram_blwl_wl[11] = wl_bus[0]; - assign sram_blwl_wl[12] = wl_bus[0]; - assign sram_blwl_wl[13] = wl_bus[0]; - assign sram_blwl_wl[14] = wl_bus[0]; - assign sram_blwl_wl[15] = wl_bus[0]; - assign sram_blwl_wl[16] = wl_bus[0]; - assign sram_blwl_wl[17] = wl_bus[0]; - assign sram_blwl_wl[18] = wl_bus[0]; - assign sram_blwl_wl[19] = wl_bus[0]; - assign sram_blwl_wl[20] = wl_bus[0]; - assign sram_blwl_wl[21] = wl_bus[0]; - assign sram_blwl_wl[22] = wl_bus[0]; - assign sram_blwl_wl[23] = wl_bus[0]; - assign sram_blwl_wl[24] = wl_bus[0]; - assign sram_blwl_wl[25] = wl_bus[0]; - assign sram_blwl_wl[26] = wl_bus[0]; - assign sram_blwl_wl[27] = wl_bus[0]; - assign sram_blwl_wl[28] = wl_bus[0]; - assign sram_blwl_wl[29] = wl_bus[0]; - assign sram_blwl_wl[30] = wl_bus[0]; - assign sram_blwl_wl[31] = wl_bus[0]; - assign sram_blwl_wl[32] = wl_bus[0]; - assign sram_blwl_wl[33] = wl_bus[0]; - assign sram_blwl_wl[34] = wl_bus[0]; - assign sram_blwl_wl[35] = wl_bus[0]; - assign sram_blwl_wl[36] = wl_bus[0]; - assign sram_blwl_wl[37] = wl_bus[0]; - assign sram_blwl_wl[38] = wl_bus[0]; - assign sram_blwl_wl[39] = wl_bus[0]; - assign sram_blwl_wl[40] = wl_bus[0]; - assign sram_blwl_wl[41] = wl_bus[0]; - assign sram_blwl_wl[42] = wl_bus[0]; - assign sram_blwl_wl[43] = wl_bus[0]; - assign sram_blwl_wl[44] = wl_bus[0]; - assign sram_blwl_wl[45] = wl_bus[0]; - assign sram_blwl_wl[46] = wl_bus[0]; - assign sram_blwl_wl[47] = wl_bus[0]; - assign sram_blwl_wl[48] = wl_bus[0]; - assign sram_blwl_wl[49] = wl_bus[0]; - assign sram_blwl_wl[50] = wl_bus[0]; - assign sram_blwl_wl[51] = wl_bus[0]; - assign sram_blwl_wl[52] = wl_bus[1]; - assign sram_blwl_wl[53] = wl_bus[1]; - assign sram_blwl_wl[54] = wl_bus[1]; - assign sram_blwl_wl[55] = wl_bus[1]; - assign sram_blwl_wl[56] = wl_bus[1]; - assign sram_blwl_wl[57] = wl_bus[1]; - assign sram_blwl_wl[58] = wl_bus[1]; - assign sram_blwl_wl[59] = wl_bus[1]; - assign sram_blwl_wl[60] = wl_bus[1]; - assign sram_blwl_wl[61] = wl_bus[1]; - assign sram_blwl_wl[62] = wl_bus[1]; - assign sram_blwl_wl[63] = wl_bus[1]; - assign sram_blwl_wl[64] = wl_bus[1]; - assign sram_blwl_wl[65] = wl_bus[1]; - assign sram_blwl_wl[66] = wl_bus[1]; - assign sram_blwl_wl[67] = wl_bus[1]; - assign sram_blwl_wl[68] = wl_bus[1]; - assign sram_blwl_wl[69] = wl_bus[1]; - assign sram_blwl_wl[70] = wl_bus[1]; - assign sram_blwl_wl[71] = wl_bus[1]; - assign sram_blwl_wl[72] = wl_bus[1]; - assign sram_blwl_wl[73] = wl_bus[1]; - assign sram_blwl_wl[74] = wl_bus[1]; - assign sram_blwl_wl[75] = wl_bus[1]; - assign sram_blwl_wl[76] = wl_bus[1]; - assign sram_blwl_wl[77] = wl_bus[1]; - assign sram_blwl_wl[78] = wl_bus[1]; - assign sram_blwl_wl[79] = wl_bus[1]; - assign sram_blwl_wl[80] = wl_bus[1]; - assign sram_blwl_wl[81] = wl_bus[1]; - assign sram_blwl_wl[82] = wl_bus[1]; - assign sram_blwl_wl[83] = wl_bus[1]; - assign sram_blwl_wl[84] = wl_bus[1]; - assign sram_blwl_wl[85] = wl_bus[1]; - assign sram_blwl_wl[86] = wl_bus[1]; - assign sram_blwl_wl[87] = wl_bus[1]; - assign sram_blwl_wl[88] = wl_bus[1]; - assign sram_blwl_wl[89] = wl_bus[1]; - assign sram_blwl_wl[90] = wl_bus[1]; - assign sram_blwl_wl[91] = wl_bus[1]; - assign sram_blwl_wl[92] = wl_bus[1]; - assign sram_blwl_wl[93] = wl_bus[1]; - assign sram_blwl_wl[94] = wl_bus[1]; - assign sram_blwl_wl[95] = wl_bus[1]; - assign sram_blwl_wl[96] = wl_bus[1]; - assign sram_blwl_wl[97] = wl_bus[1]; - assign sram_blwl_wl[98] = wl_bus[1]; - assign sram_blwl_wl[99] = wl_bus[1]; - assign sram_blwl_wl[100] = wl_bus[1]; - assign sram_blwl_wl[101] = wl_bus[1]; - assign sram_blwl_wl[102] = wl_bus[1]; - assign sram_blwl_wl[103] = wl_bus[1]; - assign sram_blwl_wl[104] = wl_bus[2]; - assign sram_blwl_wl[105] = wl_bus[2]; - assign sram_blwl_wl[106] = wl_bus[2]; - assign sram_blwl_wl[107] = wl_bus[2]; - assign sram_blwl_wl[108] = wl_bus[2]; - assign sram_blwl_wl[109] = wl_bus[2]; - assign sram_blwl_wl[110] = wl_bus[2]; - assign sram_blwl_wl[111] = wl_bus[2]; - assign sram_blwl_wl[112] = wl_bus[2]; - assign sram_blwl_wl[113] = wl_bus[2]; - assign sram_blwl_wl[114] = wl_bus[2]; - assign sram_blwl_wl[115] = wl_bus[2]; - assign sram_blwl_wl[116] = wl_bus[2]; - assign sram_blwl_wl[117] = wl_bus[2]; - assign sram_blwl_wl[118] = wl_bus[2]; - assign sram_blwl_wl[119] = wl_bus[2]; - assign sram_blwl_wl[120] = wl_bus[2]; - assign sram_blwl_wl[121] = wl_bus[2]; - assign sram_blwl_wl[122] = wl_bus[2]; - assign sram_blwl_wl[123] = wl_bus[2]; - assign sram_blwl_wl[124] = wl_bus[2]; - assign sram_blwl_wl[125] = wl_bus[2]; - assign sram_blwl_wl[126] = wl_bus[2]; - assign sram_blwl_wl[127] = wl_bus[2]; - assign sram_blwl_wl[128] = wl_bus[2]; - assign sram_blwl_wl[129] = wl_bus[2]; - assign sram_blwl_wl[130] = wl_bus[2]; - assign sram_blwl_wl[131] = wl_bus[2]; - assign sram_blwl_wl[132] = wl_bus[2]; - assign sram_blwl_wl[133] = wl_bus[2]; - assign sram_blwl_wl[134] = wl_bus[2]; - assign sram_blwl_wl[135] = wl_bus[2]; - assign sram_blwl_wl[136] = wl_bus[2]; - assign sram_blwl_wl[137] = wl_bus[2]; - assign sram_blwl_wl[138] = wl_bus[2]; - assign sram_blwl_wl[139] = wl_bus[2]; - assign sram_blwl_wl[140] = wl_bus[2]; - assign sram_blwl_wl[141] = wl_bus[2]; - assign sram_blwl_wl[142] = wl_bus[2]; - assign sram_blwl_wl[143] = wl_bus[2]; - assign sram_blwl_wl[144] = wl_bus[2]; - assign sram_blwl_wl[145] = wl_bus[2]; - assign sram_blwl_wl[146] = wl_bus[2]; - assign sram_blwl_wl[147] = wl_bus[2]; - assign sram_blwl_wl[148] = wl_bus[2]; - assign sram_blwl_wl[149] = wl_bus[2]; - assign sram_blwl_wl[150] = wl_bus[2]; - assign sram_blwl_wl[151] = wl_bus[2]; - assign sram_blwl_wl[152] = wl_bus[2]; - assign sram_blwl_wl[153] = wl_bus[2]; - assign sram_blwl_wl[154] = wl_bus[2]; - assign sram_blwl_wl[155] = wl_bus[2]; - assign sram_blwl_wl[156] = wl_bus[3]; - assign sram_blwl_wl[157] = wl_bus[3]; - assign sram_blwl_wl[158] = wl_bus[3]; - assign sram_blwl_wl[159] = wl_bus[3]; - assign sram_blwl_wl[160] = wl_bus[3]; - assign sram_blwl_wl[161] = wl_bus[3]; - assign sram_blwl_wl[162] = wl_bus[3]; - assign sram_blwl_wl[163] = wl_bus[3]; - assign sram_blwl_wl[164] = wl_bus[3]; - assign sram_blwl_wl[165] = wl_bus[3]; - assign sram_blwl_wl[166] = wl_bus[3]; - assign sram_blwl_wl[167] = wl_bus[3]; - assign sram_blwl_wl[168] = wl_bus[3]; - assign sram_blwl_wl[169] = wl_bus[3]; - assign sram_blwl_wl[170] = wl_bus[3]; - assign sram_blwl_wl[171] = wl_bus[3]; - assign sram_blwl_wl[172] = wl_bus[3]; - assign sram_blwl_wl[173] = wl_bus[3]; - assign sram_blwl_wl[174] = wl_bus[3]; - assign sram_blwl_wl[175] = wl_bus[3]; - assign sram_blwl_wl[176] = wl_bus[3]; - assign sram_blwl_wl[177] = wl_bus[3]; - assign sram_blwl_wl[178] = wl_bus[3]; - assign sram_blwl_wl[179] = wl_bus[3]; - assign sram_blwl_wl[180] = wl_bus[3]; - assign sram_blwl_wl[181] = wl_bus[3]; - assign sram_blwl_wl[182] = wl_bus[3]; - assign sram_blwl_wl[183] = wl_bus[3]; - assign sram_blwl_wl[184] = wl_bus[3]; - assign sram_blwl_wl[185] = wl_bus[3]; - assign sram_blwl_wl[186] = wl_bus[3]; - assign sram_blwl_wl[187] = wl_bus[3]; - assign sram_blwl_wl[188] = wl_bus[3]; - assign sram_blwl_wl[189] = wl_bus[3]; - assign sram_blwl_wl[190] = wl_bus[3]; - assign sram_blwl_wl[191] = wl_bus[3]; - assign sram_blwl_wl[192] = wl_bus[3]; - assign sram_blwl_wl[193] = wl_bus[3]; - assign sram_blwl_wl[194] = wl_bus[3]; - assign sram_blwl_wl[195] = wl_bus[3]; - assign sram_blwl_wl[196] = wl_bus[3]; - assign sram_blwl_wl[197] = wl_bus[3]; - assign sram_blwl_wl[198] = wl_bus[3]; - assign sram_blwl_wl[199] = wl_bus[3]; - assign sram_blwl_wl[200] = wl_bus[3]; - assign sram_blwl_wl[201] = wl_bus[3]; - assign sram_blwl_wl[202] = wl_bus[3]; - assign sram_blwl_wl[203] = wl_bus[3]; - assign sram_blwl_wl[204] = wl_bus[3]; - assign sram_blwl_wl[205] = wl_bus[3]; - assign sram_blwl_wl[206] = wl_bus[3]; - assign sram_blwl_wl[207] = wl_bus[3]; - assign sram_blwl_wl[208] = wl_bus[4]; - assign sram_blwl_wl[209] = wl_bus[4]; - assign sram_blwl_wl[210] = wl_bus[4]; - assign sram_blwl_wl[211] = wl_bus[4]; - assign sram_blwl_wl[212] = wl_bus[4]; - assign sram_blwl_wl[213] = wl_bus[4]; - assign sram_blwl_wl[214] = wl_bus[4]; - assign sram_blwl_wl[215] = wl_bus[4]; - assign sram_blwl_wl[216] = wl_bus[4]; - assign sram_blwl_wl[217] = wl_bus[4]; - assign sram_blwl_wl[218] = wl_bus[4]; - assign sram_blwl_wl[219] = wl_bus[4]; - assign sram_blwl_wl[220] = wl_bus[4]; - assign sram_blwl_wl[221] = wl_bus[4]; - assign sram_blwl_wl[222] = wl_bus[4]; - assign sram_blwl_wl[223] = wl_bus[4]; - assign sram_blwl_wl[224] = wl_bus[4]; - assign sram_blwl_wl[225] = wl_bus[4]; - assign sram_blwl_wl[226] = wl_bus[4]; - assign sram_blwl_wl[227] = wl_bus[4]; - assign sram_blwl_wl[228] = wl_bus[4]; - assign sram_blwl_wl[229] = wl_bus[4]; - assign sram_blwl_wl[230] = wl_bus[4]; - assign sram_blwl_wl[231] = wl_bus[4]; - assign sram_blwl_wl[232] = wl_bus[4]; - assign sram_blwl_wl[233] = wl_bus[4]; - assign sram_blwl_wl[234] = wl_bus[4]; - assign sram_blwl_wl[235] = wl_bus[4]; - assign sram_blwl_wl[236] = wl_bus[4]; - assign sram_blwl_wl[237] = wl_bus[4]; - assign sram_blwl_wl[238] = wl_bus[4]; - assign sram_blwl_wl[239] = wl_bus[4]; - assign sram_blwl_wl[240] = wl_bus[4]; - assign sram_blwl_wl[241] = wl_bus[4]; - assign sram_blwl_wl[242] = wl_bus[4]; - assign sram_blwl_wl[243] = wl_bus[4]; - assign sram_blwl_wl[244] = wl_bus[4]; - assign sram_blwl_wl[245] = wl_bus[4]; - assign sram_blwl_wl[246] = wl_bus[4]; - assign sram_blwl_wl[247] = wl_bus[4]; - assign sram_blwl_wl[248] = wl_bus[4]; - assign sram_blwl_wl[249] = wl_bus[4]; - assign sram_blwl_wl[250] = wl_bus[4]; - assign sram_blwl_wl[251] = wl_bus[4]; - assign sram_blwl_wl[252] = wl_bus[4]; - assign sram_blwl_wl[253] = wl_bus[4]; - assign sram_blwl_wl[254] = wl_bus[4]; - assign sram_blwl_wl[255] = wl_bus[4]; - assign sram_blwl_wl[256] = wl_bus[4]; - assign sram_blwl_wl[257] = wl_bus[4]; - assign sram_blwl_wl[258] = wl_bus[4]; - assign sram_blwl_wl[259] = wl_bus[4]; - assign sram_blwl_wl[260] = wl_bus[5]; - assign sram_blwl_wl[261] = wl_bus[5]; - assign sram_blwl_wl[262] = wl_bus[5]; - assign sram_blwl_wl[263] = wl_bus[5]; - assign sram_blwl_wl[264] = wl_bus[5]; - assign sram_blwl_wl[265] = wl_bus[5]; - assign sram_blwl_wl[266] = wl_bus[5]; - assign sram_blwl_wl[267] = wl_bus[5]; - assign sram_blwl_wl[268] = wl_bus[5]; - assign sram_blwl_wl[269] = wl_bus[5]; - assign sram_blwl_wl[270] = wl_bus[5]; - assign sram_blwl_wl[271] = wl_bus[5]; - assign sram_blwl_wl[272] = wl_bus[5]; - assign sram_blwl_wl[273] = wl_bus[5]; - assign sram_blwl_wl[274] = wl_bus[5]; - assign sram_blwl_wl[275] = wl_bus[5]; - assign sram_blwl_wl[276] = wl_bus[5]; - assign sram_blwl_wl[277] = wl_bus[5]; - assign sram_blwl_wl[278] = wl_bus[5]; - assign sram_blwl_wl[279] = wl_bus[5]; - assign sram_blwl_wl[280] = wl_bus[5]; - assign sram_blwl_wl[281] = wl_bus[5]; - assign sram_blwl_wl[282] = wl_bus[5]; - assign sram_blwl_wl[283] = wl_bus[5]; - assign sram_blwl_wl[284] = wl_bus[5]; - assign sram_blwl_wl[285] = wl_bus[5]; - assign sram_blwl_wl[286] = wl_bus[5]; - assign sram_blwl_wl[287] = wl_bus[5]; - assign sram_blwl_wl[288] = wl_bus[5]; - assign sram_blwl_wl[289] = wl_bus[5]; - assign sram_blwl_wl[290] = wl_bus[5]; - assign sram_blwl_wl[291] = wl_bus[5]; - assign sram_blwl_wl[292] = wl_bus[5]; - assign sram_blwl_wl[293] = wl_bus[5]; - assign sram_blwl_wl[294] = wl_bus[5]; - assign sram_blwl_wl[295] = wl_bus[5]; - assign sram_blwl_wl[296] = wl_bus[5]; - assign sram_blwl_wl[297] = wl_bus[5]; - assign sram_blwl_wl[298] = wl_bus[5]; - assign sram_blwl_wl[299] = wl_bus[5]; - assign sram_blwl_wl[300] = wl_bus[5]; - assign sram_blwl_wl[301] = wl_bus[5]; - assign sram_blwl_wl[302] = wl_bus[5]; - assign sram_blwl_wl[303] = wl_bus[5]; - assign sram_blwl_wl[304] = wl_bus[5]; - assign sram_blwl_wl[305] = wl_bus[5]; - assign sram_blwl_wl[306] = wl_bus[5]; - assign sram_blwl_wl[307] = wl_bus[5]; - assign sram_blwl_wl[308] = wl_bus[5]; - assign sram_blwl_wl[309] = wl_bus[5]; - assign sram_blwl_wl[310] = wl_bus[5]; - assign sram_blwl_wl[311] = wl_bus[5]; - assign sram_blwl_wl[312] = wl_bus[6]; - assign sram_blwl_wl[313] = wl_bus[6]; - assign sram_blwl_wl[314] = wl_bus[6]; - assign sram_blwl_wl[315] = wl_bus[6]; - assign sram_blwl_wl[316] = wl_bus[6]; - assign sram_blwl_wl[317] = wl_bus[6]; - assign sram_blwl_wl[318] = wl_bus[6]; - assign sram_blwl_wl[319] = wl_bus[6]; - assign sram_blwl_wl[320] = wl_bus[6]; - assign sram_blwl_wl[321] = wl_bus[6]; - assign sram_blwl_wl[322] = wl_bus[6]; - assign sram_blwl_wl[323] = wl_bus[6]; - assign sram_blwl_wl[324] = wl_bus[6]; - assign sram_blwl_wl[325] = wl_bus[6]; - assign sram_blwl_wl[326] = wl_bus[6]; - assign sram_blwl_wl[327] = wl_bus[6]; - assign sram_blwl_wl[328] = wl_bus[6]; - assign sram_blwl_wl[329] = wl_bus[6]; - assign sram_blwl_wl[330] = wl_bus[6]; - assign sram_blwl_wl[331] = wl_bus[6]; - assign sram_blwl_wl[332] = wl_bus[6]; - assign sram_blwl_wl[333] = wl_bus[6]; - assign sram_blwl_wl[334] = wl_bus[6]; - assign sram_blwl_wl[335] = wl_bus[6]; - assign sram_blwl_wl[336] = wl_bus[6]; - assign sram_blwl_wl[337] = wl_bus[6]; - assign sram_blwl_wl[338] = wl_bus[6]; - assign sram_blwl_wl[339] = wl_bus[6]; - assign sram_blwl_wl[340] = wl_bus[6]; - assign sram_blwl_wl[341] = wl_bus[6]; - assign sram_blwl_wl[342] = wl_bus[6]; - assign sram_blwl_wl[343] = wl_bus[6]; - assign sram_blwl_wl[344] = wl_bus[6]; - assign sram_blwl_wl[345] = wl_bus[6]; - assign sram_blwl_wl[346] = wl_bus[6]; - assign sram_blwl_wl[347] = wl_bus[6]; - assign sram_blwl_wl[348] = wl_bus[6]; - assign sram_blwl_wl[349] = wl_bus[6]; - assign sram_blwl_wl[350] = wl_bus[6]; - assign sram_blwl_wl[351] = wl_bus[6]; - assign sram_blwl_wl[352] = wl_bus[6]; - assign sram_blwl_wl[353] = wl_bus[6]; - assign sram_blwl_wl[354] = wl_bus[6]; - assign sram_blwl_wl[355] = wl_bus[6]; - assign sram_blwl_wl[356] = wl_bus[6]; - assign sram_blwl_wl[357] = wl_bus[6]; - assign sram_blwl_wl[358] = wl_bus[6]; - assign sram_blwl_wl[359] = wl_bus[6]; - assign sram_blwl_wl[360] = wl_bus[6]; - assign sram_blwl_wl[361] = wl_bus[6]; - assign sram_blwl_wl[362] = wl_bus[6]; - assign sram_blwl_wl[363] = wl_bus[6]; - assign sram_blwl_wl[364] = wl_bus[7]; - assign sram_blwl_wl[365] = wl_bus[7]; - assign sram_blwl_wl[366] = wl_bus[7]; - assign sram_blwl_wl[367] = wl_bus[7]; - assign sram_blwl_wl[368] = wl_bus[7]; - assign sram_blwl_wl[369] = wl_bus[7]; - assign sram_blwl_wl[370] = wl_bus[7]; - assign sram_blwl_wl[371] = wl_bus[7]; - assign sram_blwl_wl[372] = wl_bus[7]; - assign sram_blwl_wl[373] = wl_bus[7]; - assign sram_blwl_wl[374] = wl_bus[7]; - assign sram_blwl_wl[375] = wl_bus[7]; - assign sram_blwl_wl[376] = wl_bus[7]; - assign sram_blwl_wl[377] = wl_bus[7]; - assign sram_blwl_wl[378] = wl_bus[7]; - assign sram_blwl_wl[379] = wl_bus[7]; - assign sram_blwl_wl[380] = wl_bus[7]; - assign sram_blwl_wl[381] = wl_bus[7]; - assign sram_blwl_wl[382] = wl_bus[7]; - assign sram_blwl_wl[383] = wl_bus[7]; - assign sram_blwl_wl[384] = wl_bus[7]; - assign sram_blwl_wl[385] = wl_bus[7]; - assign sram_blwl_wl[386] = wl_bus[7]; - assign sram_blwl_wl[387] = wl_bus[7]; - assign sram_blwl_wl[388] = wl_bus[7]; - assign sram_blwl_wl[389] = wl_bus[7]; - assign sram_blwl_wl[390] = wl_bus[7]; - assign sram_blwl_wl[391] = wl_bus[7]; - assign sram_blwl_wl[392] = wl_bus[7]; - assign sram_blwl_wl[393] = wl_bus[7]; - assign sram_blwl_wl[394] = wl_bus[7]; - assign sram_blwl_wl[395] = wl_bus[7]; - assign sram_blwl_wl[396] = wl_bus[7]; - assign sram_blwl_wl[397] = wl_bus[7]; - assign sram_blwl_wl[398] = wl_bus[7]; - assign sram_blwl_wl[399] = wl_bus[7]; - assign sram_blwl_wl[400] = wl_bus[7]; - assign sram_blwl_wl[401] = wl_bus[7]; - assign sram_blwl_wl[402] = wl_bus[7]; - assign sram_blwl_wl[403] = wl_bus[7]; - assign sram_blwl_wl[404] = wl_bus[7]; - assign sram_blwl_wl[405] = wl_bus[7]; - assign sram_blwl_wl[406] = wl_bus[7]; - assign sram_blwl_wl[407] = wl_bus[7]; - assign sram_blwl_wl[408] = wl_bus[7]; - assign sram_blwl_wl[409] = wl_bus[7]; - assign sram_blwl_wl[410] = wl_bus[7]; - assign sram_blwl_wl[411] = wl_bus[7]; - assign sram_blwl_wl[412] = wl_bus[7]; - assign sram_blwl_wl[413] = wl_bus[7]; - assign sram_blwl_wl[414] = wl_bus[7]; - assign sram_blwl_wl[415] = wl_bus[7]; - assign sram_blwl_wl[416] = wl_bus[8]; - assign sram_blwl_wl[417] = wl_bus[8]; - assign sram_blwl_wl[418] = wl_bus[8]; - assign sram_blwl_wl[419] = wl_bus[8]; - assign sram_blwl_wl[420] = wl_bus[8]; - assign sram_blwl_wl[421] = wl_bus[8]; - assign sram_blwl_wl[422] = wl_bus[8]; - assign sram_blwl_wl[423] = wl_bus[8]; - assign sram_blwl_wl[424] = wl_bus[8]; - assign sram_blwl_wl[425] = wl_bus[8]; - assign sram_blwl_wl[426] = wl_bus[8]; - assign sram_blwl_wl[427] = wl_bus[8]; - assign sram_blwl_wl[428] = wl_bus[8]; - assign sram_blwl_wl[429] = wl_bus[8]; - assign sram_blwl_wl[430] = wl_bus[8]; - assign sram_blwl_wl[431] = wl_bus[8]; - assign sram_blwl_wl[432] = wl_bus[8]; - assign sram_blwl_wl[433] = wl_bus[8]; - assign sram_blwl_wl[434] = wl_bus[8]; - assign sram_blwl_wl[435] = wl_bus[8]; - assign sram_blwl_wl[436] = wl_bus[8]; - assign sram_blwl_wl[437] = wl_bus[8]; - assign sram_blwl_wl[438] = wl_bus[8]; - assign sram_blwl_wl[439] = wl_bus[8]; - assign sram_blwl_wl[440] = wl_bus[8]; - assign sram_blwl_wl[441] = wl_bus[8]; - assign sram_blwl_wl[442] = wl_bus[8]; - assign sram_blwl_wl[443] = wl_bus[8]; - assign sram_blwl_wl[444] = wl_bus[8]; - assign sram_blwl_wl[445] = wl_bus[8]; - assign sram_blwl_wl[446] = wl_bus[8]; - assign sram_blwl_wl[447] = wl_bus[8]; - assign sram_blwl_wl[448] = wl_bus[8]; - assign sram_blwl_wl[449] = wl_bus[8]; - assign sram_blwl_wl[450] = wl_bus[8]; - assign sram_blwl_wl[451] = wl_bus[8]; - assign sram_blwl_wl[452] = wl_bus[8]; - assign sram_blwl_wl[453] = wl_bus[8]; - assign sram_blwl_wl[454] = wl_bus[8]; - assign sram_blwl_wl[455] = wl_bus[8]; - assign sram_blwl_wl[456] = wl_bus[8]; - assign sram_blwl_wl[457] = wl_bus[8]; - assign sram_blwl_wl[458] = wl_bus[8]; - assign sram_blwl_wl[459] = wl_bus[8]; - assign sram_blwl_wl[460] = wl_bus[8]; - assign sram_blwl_wl[461] = wl_bus[8]; - assign sram_blwl_wl[462] = wl_bus[8]; - assign sram_blwl_wl[463] = wl_bus[8]; - assign sram_blwl_wl[464] = wl_bus[8]; - assign sram_blwl_wl[465] = wl_bus[8]; - assign sram_blwl_wl[466] = wl_bus[8]; - assign sram_blwl_wl[467] = wl_bus[8]; - assign sram_blwl_wl[468] = wl_bus[9]; - assign sram_blwl_wl[469] = wl_bus[9]; - assign sram_blwl_wl[470] = wl_bus[9]; - assign sram_blwl_wl[471] = wl_bus[9]; - assign sram_blwl_wl[472] = wl_bus[9]; - assign sram_blwl_wl[473] = wl_bus[9]; - assign sram_blwl_wl[474] = wl_bus[9]; - assign sram_blwl_wl[475] = wl_bus[9]; - assign sram_blwl_wl[476] = wl_bus[9]; - assign sram_blwl_wl[477] = wl_bus[9]; - assign sram_blwl_wl[478] = wl_bus[9]; - assign sram_blwl_wl[479] = wl_bus[9]; - assign sram_blwl_wl[480] = wl_bus[9]; - assign sram_blwl_wl[481] = wl_bus[9]; - assign sram_blwl_wl[482] = wl_bus[9]; - assign sram_blwl_wl[483] = wl_bus[9]; - assign sram_blwl_wl[484] = wl_bus[9]; - assign sram_blwl_wl[485] = wl_bus[9]; - assign sram_blwl_wl[486] = wl_bus[9]; - assign sram_blwl_wl[487] = wl_bus[9]; - assign sram_blwl_wl[488] = wl_bus[9]; - assign sram_blwl_wl[489] = wl_bus[9]; - assign sram_blwl_wl[490] = wl_bus[9]; - assign sram_blwl_wl[491] = wl_bus[9]; - assign sram_blwl_wl[492] = wl_bus[9]; - assign sram_blwl_wl[493] = wl_bus[9]; - assign sram_blwl_wl[494] = wl_bus[9]; - assign sram_blwl_wl[495] = wl_bus[9]; - assign sram_blwl_wl[496] = wl_bus[9]; - assign sram_blwl_wl[497] = wl_bus[9]; - assign sram_blwl_wl[498] = wl_bus[9]; - assign sram_blwl_wl[499] = wl_bus[9]; - assign sram_blwl_wl[500] = wl_bus[9]; - assign sram_blwl_wl[501] = wl_bus[9]; - assign sram_blwl_wl[502] = wl_bus[9]; - assign sram_blwl_wl[503] = wl_bus[9]; - assign sram_blwl_wl[504] = wl_bus[9]; - assign sram_blwl_wl[505] = wl_bus[9]; - assign sram_blwl_wl[506] = wl_bus[9]; - assign sram_blwl_wl[507] = wl_bus[9]; - assign sram_blwl_wl[508] = wl_bus[9]; - assign sram_blwl_wl[509] = wl_bus[9]; - assign sram_blwl_wl[510] = wl_bus[9]; - assign sram_blwl_wl[511] = wl_bus[9]; - assign sram_blwl_wl[512] = wl_bus[9]; - assign sram_blwl_wl[513] = wl_bus[9]; - assign sram_blwl_wl[514] = wl_bus[9]; - assign sram_blwl_wl[515] = wl_bus[9]; - assign sram_blwl_wl[516] = wl_bus[9]; - assign sram_blwl_wl[517] = wl_bus[9]; - assign sram_blwl_wl[518] = wl_bus[9]; - assign sram_blwl_wl[519] = wl_bus[9]; - assign sram_blwl_wl[520] = wl_bus[10]; - assign sram_blwl_wl[521] = wl_bus[10]; - assign sram_blwl_wl[522] = wl_bus[10]; - assign sram_blwl_wl[523] = wl_bus[10]; - assign sram_blwl_wl[524] = wl_bus[10]; - assign sram_blwl_wl[525] = wl_bus[10]; - assign sram_blwl_wl[526] = wl_bus[10]; - assign sram_blwl_wl[527] = wl_bus[10]; - assign sram_blwl_wl[528] = wl_bus[10]; - assign sram_blwl_wl[529] = wl_bus[10]; - assign sram_blwl_wl[530] = wl_bus[10]; - assign sram_blwl_wl[531] = wl_bus[10]; - assign sram_blwl_wl[532] = wl_bus[10]; - assign sram_blwl_wl[533] = wl_bus[10]; - assign sram_blwl_wl[534] = wl_bus[10]; - assign sram_blwl_wl[535] = wl_bus[10]; - assign sram_blwl_wl[536] = wl_bus[10]; - assign sram_blwl_wl[537] = wl_bus[10]; - assign sram_blwl_wl[538] = wl_bus[10]; - assign sram_blwl_wl[539] = wl_bus[10]; - assign sram_blwl_wl[540] = wl_bus[10]; - assign sram_blwl_wl[541] = wl_bus[10]; - assign sram_blwl_wl[542] = wl_bus[10]; - assign sram_blwl_wl[543] = wl_bus[10]; - assign sram_blwl_wl[544] = wl_bus[10]; - assign sram_blwl_wl[545] = wl_bus[10]; - assign sram_blwl_wl[546] = wl_bus[10]; - assign sram_blwl_wl[547] = wl_bus[10]; - assign sram_blwl_wl[548] = wl_bus[10]; - assign sram_blwl_wl[549] = wl_bus[10]; - assign sram_blwl_wl[550] = wl_bus[10]; - assign sram_blwl_wl[551] = wl_bus[10]; - assign sram_blwl_wl[552] = wl_bus[10]; - assign sram_blwl_wl[553] = wl_bus[10]; - assign sram_blwl_wl[554] = wl_bus[10]; - assign sram_blwl_wl[555] = wl_bus[10]; - assign sram_blwl_wl[556] = wl_bus[10]; - assign sram_blwl_wl[557] = wl_bus[10]; - assign sram_blwl_wl[558] = wl_bus[10]; - assign sram_blwl_wl[559] = wl_bus[10]; - assign sram_blwl_wl[560] = wl_bus[10]; - assign sram_blwl_wl[561] = wl_bus[10]; - assign sram_blwl_wl[562] = wl_bus[10]; - assign sram_blwl_wl[563] = wl_bus[10]; - assign sram_blwl_wl[564] = wl_bus[10]; - assign sram_blwl_wl[565] = wl_bus[10]; - assign sram_blwl_wl[566] = wl_bus[10]; - assign sram_blwl_wl[567] = wl_bus[10]; - assign sram_blwl_wl[568] = wl_bus[10]; - assign sram_blwl_wl[569] = wl_bus[10]; - assign sram_blwl_wl[570] = wl_bus[10]; - assign sram_blwl_wl[571] = wl_bus[10]; - assign sram_blwl_wl[572] = wl_bus[11]; - assign sram_blwl_wl[573] = wl_bus[11]; - assign sram_blwl_wl[574] = wl_bus[11]; - assign sram_blwl_wl[575] = wl_bus[11]; - assign sram_blwl_wl[576] = wl_bus[11]; - assign sram_blwl_wl[577] = wl_bus[11]; - assign sram_blwl_wl[578] = wl_bus[11]; - assign sram_blwl_wl[579] = wl_bus[11]; - assign sram_blwl_wl[580] = wl_bus[11]; - assign sram_blwl_wl[581] = wl_bus[11]; - assign sram_blwl_wl[582] = wl_bus[11]; - assign sram_blwl_wl[583] = wl_bus[11]; - assign sram_blwl_wl[584] = wl_bus[11]; - assign sram_blwl_wl[585] = wl_bus[11]; - assign sram_blwl_wl[586] = wl_bus[11]; - assign sram_blwl_wl[587] = wl_bus[11]; - assign sram_blwl_wl[588] = wl_bus[11]; - assign sram_blwl_wl[589] = wl_bus[11]; - assign sram_blwl_wl[590] = wl_bus[11]; - assign sram_blwl_wl[591] = wl_bus[11]; - assign sram_blwl_wl[592] = wl_bus[11]; - assign sram_blwl_wl[593] = wl_bus[11]; - assign sram_blwl_wl[594] = wl_bus[11]; - assign sram_blwl_wl[595] = wl_bus[11]; - assign sram_blwl_wl[596] = wl_bus[11]; - assign sram_blwl_wl[597] = wl_bus[11]; - assign sram_blwl_wl[598] = wl_bus[11]; - assign sram_blwl_wl[599] = wl_bus[11]; - assign sram_blwl_wl[600] = wl_bus[11]; - assign sram_blwl_wl[601] = wl_bus[11]; - assign sram_blwl_wl[602] = wl_bus[11]; - assign sram_blwl_wl[603] = wl_bus[11]; - assign sram_blwl_wl[604] = wl_bus[11]; - assign sram_blwl_wl[605] = wl_bus[11]; - assign sram_blwl_wl[606] = wl_bus[11]; - assign sram_blwl_wl[607] = wl_bus[11]; - assign sram_blwl_wl[608] = wl_bus[11]; - assign sram_blwl_wl[609] = wl_bus[11]; - assign sram_blwl_wl[610] = wl_bus[11]; - assign sram_blwl_wl[611] = wl_bus[11]; - assign sram_blwl_wl[612] = wl_bus[11]; - assign sram_blwl_wl[613] = wl_bus[11]; - assign sram_blwl_wl[614] = wl_bus[11]; - assign sram_blwl_wl[615] = wl_bus[11]; - assign sram_blwl_wl[616] = wl_bus[11]; - assign sram_blwl_wl[617] = wl_bus[11]; - assign sram_blwl_wl[618] = wl_bus[11]; - assign sram_blwl_wl[619] = wl_bus[11]; - assign sram_blwl_wl[620] = wl_bus[11]; - assign sram_blwl_wl[621] = wl_bus[11]; - assign sram_blwl_wl[622] = wl_bus[11]; - assign sram_blwl_wl[623] = wl_bus[11]; - assign sram_blwl_wl[624] = wl_bus[12]; - assign sram_blwl_wl[625] = wl_bus[12]; - assign sram_blwl_wl[626] = wl_bus[12]; - assign sram_blwl_wl[627] = wl_bus[12]; - assign sram_blwl_wl[628] = wl_bus[12]; - assign sram_blwl_wl[629] = wl_bus[12]; - assign sram_blwl_wl[630] = wl_bus[12]; - assign sram_blwl_wl[631] = wl_bus[12]; - assign sram_blwl_wl[632] = wl_bus[12]; - assign sram_blwl_wl[633] = wl_bus[12]; - assign sram_blwl_wl[634] = wl_bus[12]; - assign sram_blwl_wl[635] = wl_bus[12]; - assign sram_blwl_wl[636] = wl_bus[12]; - assign sram_blwl_wl[637] = wl_bus[12]; - assign sram_blwl_wl[638] = wl_bus[12]; - assign sram_blwl_wl[639] = wl_bus[12]; - assign sram_blwl_wl[640] = wl_bus[12]; - assign sram_blwl_wl[641] = wl_bus[12]; - assign sram_blwl_wl[642] = wl_bus[12]; - assign sram_blwl_wl[643] = wl_bus[12]; - assign sram_blwl_wl[644] = wl_bus[12]; - assign sram_blwl_wl[645] = wl_bus[12]; - assign sram_blwl_wl[646] = wl_bus[12]; - assign sram_blwl_wl[647] = wl_bus[12]; - assign sram_blwl_wl[648] = wl_bus[12]; - assign sram_blwl_wl[649] = wl_bus[12]; - assign sram_blwl_wl[650] = wl_bus[12]; - assign sram_blwl_wl[651] = wl_bus[12]; - assign sram_blwl_wl[652] = wl_bus[12]; - assign sram_blwl_wl[653] = wl_bus[12]; - assign sram_blwl_wl[654] = wl_bus[12]; - assign sram_blwl_wl[655] = wl_bus[12]; - assign sram_blwl_wl[656] = wl_bus[12]; - assign sram_blwl_wl[657] = wl_bus[12]; - assign sram_blwl_wl[658] = wl_bus[12]; - assign sram_blwl_wl[659] = wl_bus[12]; - assign sram_blwl_wl[660] = wl_bus[12]; - assign sram_blwl_wl[661] = wl_bus[12]; - assign sram_blwl_wl[662] = wl_bus[12]; - assign sram_blwl_wl[663] = wl_bus[12]; - assign sram_blwl_wl[664] = wl_bus[12]; - assign sram_blwl_wl[665] = wl_bus[12]; - assign sram_blwl_wl[666] = wl_bus[12]; - assign sram_blwl_wl[667] = wl_bus[12]; - assign sram_blwl_wl[668] = wl_bus[12]; - assign sram_blwl_wl[669] = wl_bus[12]; - assign sram_blwl_wl[670] = wl_bus[12]; - assign sram_blwl_wl[671] = wl_bus[12]; - assign sram_blwl_wl[672] = wl_bus[12]; - assign sram_blwl_wl[673] = wl_bus[12]; - assign sram_blwl_wl[674] = wl_bus[12]; - assign sram_blwl_wl[675] = wl_bus[12]; - assign sram_blwl_wl[676] = wl_bus[13]; - assign sram_blwl_wl[677] = wl_bus[13]; - assign sram_blwl_wl[678] = wl_bus[13]; - assign sram_blwl_wl[679] = wl_bus[13]; - assign sram_blwl_wl[680] = wl_bus[13]; - assign sram_blwl_wl[681] = wl_bus[13]; - assign sram_blwl_wl[682] = wl_bus[13]; - assign sram_blwl_wl[683] = wl_bus[13]; - assign sram_blwl_wl[684] = wl_bus[13]; - assign sram_blwl_wl[685] = wl_bus[13]; - assign sram_blwl_wl[686] = wl_bus[13]; - assign sram_blwl_wl[687] = wl_bus[13]; - assign sram_blwl_wl[688] = wl_bus[13]; - assign sram_blwl_wl[689] = wl_bus[13]; - assign sram_blwl_wl[690] = wl_bus[13]; - assign sram_blwl_wl[691] = wl_bus[13]; - assign sram_blwl_wl[692] = wl_bus[13]; - assign sram_blwl_wl[693] = wl_bus[13]; - assign sram_blwl_wl[694] = wl_bus[13]; - assign sram_blwl_wl[695] = wl_bus[13]; - assign sram_blwl_wl[696] = wl_bus[13]; - assign sram_blwl_wl[697] = wl_bus[13]; - assign sram_blwl_wl[698] = wl_bus[13]; - assign sram_blwl_wl[699] = wl_bus[13]; - assign sram_blwl_wl[700] = wl_bus[13]; - assign sram_blwl_wl[701] = wl_bus[13]; - assign sram_blwl_wl[702] = wl_bus[13]; - assign sram_blwl_wl[703] = wl_bus[13]; - assign sram_blwl_wl[704] = wl_bus[13]; - assign sram_blwl_wl[705] = wl_bus[13]; - assign sram_blwl_wl[706] = wl_bus[13]; - assign sram_blwl_wl[707] = wl_bus[13]; - assign sram_blwl_wl[708] = wl_bus[13]; - assign sram_blwl_wl[709] = wl_bus[13]; - assign sram_blwl_wl[710] = wl_bus[13]; - assign sram_blwl_wl[711] = wl_bus[13]; - assign sram_blwl_wl[712] = wl_bus[13]; - assign sram_blwl_wl[713] = wl_bus[13]; - assign sram_blwl_wl[714] = wl_bus[13]; - assign sram_blwl_wl[715] = wl_bus[13]; - assign sram_blwl_wl[716] = wl_bus[13]; - assign sram_blwl_wl[717] = wl_bus[13]; - assign sram_blwl_wl[718] = wl_bus[13]; - assign sram_blwl_wl[719] = wl_bus[13]; - assign sram_blwl_wl[720] = wl_bus[13]; - assign sram_blwl_wl[721] = wl_bus[13]; - assign sram_blwl_wl[722] = wl_bus[13]; - assign sram_blwl_wl[723] = wl_bus[13]; - assign sram_blwl_wl[724] = wl_bus[13]; - assign sram_blwl_wl[725] = wl_bus[13]; - assign sram_blwl_wl[726] = wl_bus[13]; - assign sram_blwl_wl[727] = wl_bus[13]; - assign sram_blwl_wl[728] = wl_bus[14]; - assign sram_blwl_wl[729] = wl_bus[14]; - assign sram_blwl_wl[730] = wl_bus[14]; - assign sram_blwl_wl[731] = wl_bus[14]; - assign sram_blwl_wl[732] = wl_bus[14]; - assign sram_blwl_wl[733] = wl_bus[14]; - assign sram_blwl_wl[734] = wl_bus[14]; - assign sram_blwl_wl[735] = wl_bus[14]; - assign sram_blwl_wl[736] = wl_bus[14]; - assign sram_blwl_wl[737] = wl_bus[14]; - assign sram_blwl_wl[738] = wl_bus[14]; - assign sram_blwl_wl[739] = wl_bus[14]; - assign sram_blwl_wl[740] = wl_bus[14]; - assign sram_blwl_wl[741] = wl_bus[14]; - assign sram_blwl_wl[742] = wl_bus[14]; - assign sram_blwl_wl[743] = wl_bus[14]; - assign sram_blwl_wl[744] = wl_bus[14]; - assign sram_blwl_wl[745] = wl_bus[14]; - assign sram_blwl_wl[746] = wl_bus[14]; - assign sram_blwl_wl[747] = wl_bus[14]; - assign sram_blwl_wl[748] = wl_bus[14]; - assign sram_blwl_wl[749] = wl_bus[14]; - assign sram_blwl_wl[750] = wl_bus[14]; - assign sram_blwl_wl[751] = wl_bus[14]; - assign sram_blwl_wl[752] = wl_bus[14]; - assign sram_blwl_wl[753] = wl_bus[14]; - assign sram_blwl_wl[754] = wl_bus[14]; - assign sram_blwl_wl[755] = wl_bus[14]; - assign sram_blwl_wl[756] = wl_bus[14]; - assign sram_blwl_wl[757] = wl_bus[14]; - assign sram_blwl_wl[758] = wl_bus[14]; - assign sram_blwl_wl[759] = wl_bus[14]; - assign sram_blwl_wl[760] = wl_bus[14]; - assign sram_blwl_wl[761] = wl_bus[14]; - assign sram_blwl_wl[762] = wl_bus[14]; - assign sram_blwl_wl[763] = wl_bus[14]; - assign sram_blwl_wl[764] = wl_bus[14]; - assign sram_blwl_wl[765] = wl_bus[14]; - assign sram_blwl_wl[766] = wl_bus[14]; - assign sram_blwl_wl[767] = wl_bus[14]; - assign sram_blwl_wl[768] = wl_bus[14]; - assign sram_blwl_wl[769] = wl_bus[14]; - assign sram_blwl_wl[770] = wl_bus[14]; - assign sram_blwl_wl[771] = wl_bus[14]; - assign sram_blwl_wl[772] = wl_bus[14]; - assign sram_blwl_wl[773] = wl_bus[14]; - assign sram_blwl_wl[774] = wl_bus[14]; - assign sram_blwl_wl[775] = wl_bus[14]; - assign sram_blwl_wl[776] = wl_bus[14]; - assign sram_blwl_wl[777] = wl_bus[14]; - assign sram_blwl_wl[778] = wl_bus[14]; - assign sram_blwl_wl[779] = wl_bus[14]; - assign sram_blwl_wl[780] = wl_bus[15]; - assign sram_blwl_wl[781] = wl_bus[15]; - assign sram_blwl_wl[782] = wl_bus[15]; - assign sram_blwl_wl[783] = wl_bus[15]; - assign sram_blwl_wl[784] = wl_bus[15]; - assign sram_blwl_wl[785] = wl_bus[15]; - assign sram_blwl_wl[786] = wl_bus[15]; - assign sram_blwl_wl[787] = wl_bus[15]; - assign sram_blwl_wl[788] = wl_bus[15]; - assign sram_blwl_wl[789] = wl_bus[15]; - assign sram_blwl_wl[790] = wl_bus[15]; - assign sram_blwl_wl[791] = wl_bus[15]; - assign sram_blwl_wl[792] = wl_bus[15]; - assign sram_blwl_wl[793] = wl_bus[15]; - assign sram_blwl_wl[794] = wl_bus[15]; - assign sram_blwl_wl[795] = wl_bus[15]; - assign sram_blwl_wl[796] = wl_bus[15]; - assign sram_blwl_wl[797] = wl_bus[15]; - assign sram_blwl_wl[798] = wl_bus[15]; - assign sram_blwl_wl[799] = wl_bus[15]; - assign sram_blwl_wl[800] = wl_bus[15]; - assign sram_blwl_wl[801] = wl_bus[15]; - assign sram_blwl_wl[802] = wl_bus[15]; - assign sram_blwl_wl[803] = wl_bus[15]; - assign sram_blwl_wl[804] = wl_bus[15]; - assign sram_blwl_wl[805] = wl_bus[15]; - assign sram_blwl_wl[806] = wl_bus[15]; - assign sram_blwl_wl[807] = wl_bus[15]; - assign sram_blwl_wl[808] = wl_bus[15]; - assign sram_blwl_wl[809] = wl_bus[15]; - assign sram_blwl_wl[810] = wl_bus[15]; - assign sram_blwl_wl[811] = wl_bus[15]; - assign sram_blwl_wl[812] = wl_bus[15]; - assign sram_blwl_wl[813] = wl_bus[15]; - assign sram_blwl_wl[814] = wl_bus[15]; - assign sram_blwl_wl[815] = wl_bus[15]; - assign sram_blwl_wl[816] = wl_bus[15]; - assign sram_blwl_wl[817] = wl_bus[15]; - assign sram_blwl_wl[818] = wl_bus[15]; - assign sram_blwl_wl[819] = wl_bus[15]; - assign sram_blwl_wl[820] = wl_bus[15]; - assign sram_blwl_wl[821] = wl_bus[15]; - assign sram_blwl_wl[822] = wl_bus[15]; - assign sram_blwl_wl[823] = wl_bus[15]; - assign sram_blwl_wl[824] = wl_bus[15]; - assign sram_blwl_wl[825] = wl_bus[15]; - assign sram_blwl_wl[826] = wl_bus[15]; - assign sram_blwl_wl[827] = wl_bus[15]; - assign sram_blwl_wl[828] = wl_bus[15]; - assign sram_blwl_wl[829] = wl_bus[15]; - assign sram_blwl_wl[830] = wl_bus[15]; - assign sram_blwl_wl[831] = wl_bus[15]; - assign sram_blwl_wl[832] = wl_bus[16]; - assign sram_blwl_wl[833] = wl_bus[16]; - assign sram_blwl_wl[834] = wl_bus[16]; - assign sram_blwl_wl[835] = wl_bus[16]; - assign sram_blwl_wl[836] = wl_bus[16]; - assign sram_blwl_wl[837] = wl_bus[16]; - assign sram_blwl_wl[838] = wl_bus[16]; - assign sram_blwl_wl[839] = wl_bus[16]; - assign sram_blwl_wl[840] = wl_bus[16]; - assign sram_blwl_wl[841] = wl_bus[16]; - assign sram_blwl_wl[842] = wl_bus[16]; - assign sram_blwl_wl[843] = wl_bus[16]; - assign sram_blwl_wl[844] = wl_bus[16]; - assign sram_blwl_wl[845] = wl_bus[16]; - assign sram_blwl_wl[846] = wl_bus[16]; - assign sram_blwl_wl[847] = wl_bus[16]; - assign sram_blwl_wl[848] = wl_bus[16]; - assign sram_blwl_wl[849] = wl_bus[16]; - assign sram_blwl_wl[850] = wl_bus[16]; - assign sram_blwl_wl[851] = wl_bus[16]; - assign sram_blwl_wl[852] = wl_bus[16]; - assign sram_blwl_wl[853] = wl_bus[16]; - assign sram_blwl_wl[854] = wl_bus[16]; - assign sram_blwl_wl[855] = wl_bus[16]; - assign sram_blwl_wl[856] = wl_bus[16]; - assign sram_blwl_wl[857] = wl_bus[16]; - assign sram_blwl_wl[858] = wl_bus[16]; - assign sram_blwl_wl[859] = wl_bus[16]; - assign sram_blwl_wl[860] = wl_bus[16]; - assign sram_blwl_wl[861] = wl_bus[16]; - assign sram_blwl_wl[862] = wl_bus[16]; - assign sram_blwl_wl[863] = wl_bus[16]; - assign sram_blwl_wl[864] = wl_bus[16]; - assign sram_blwl_wl[865] = wl_bus[16]; - assign sram_blwl_wl[866] = wl_bus[16]; - assign sram_blwl_wl[867] = wl_bus[16]; - assign sram_blwl_wl[868] = wl_bus[16]; - assign sram_blwl_wl[869] = wl_bus[16]; - assign sram_blwl_wl[870] = wl_bus[16]; - assign sram_blwl_wl[871] = wl_bus[16]; - assign sram_blwl_wl[872] = wl_bus[16]; - assign sram_blwl_wl[873] = wl_bus[16]; - assign sram_blwl_wl[874] = wl_bus[16]; - assign sram_blwl_wl[875] = wl_bus[16]; - assign sram_blwl_wl[876] = wl_bus[16]; - assign sram_blwl_wl[877] = wl_bus[16]; - assign sram_blwl_wl[878] = wl_bus[16]; - assign sram_blwl_wl[879] = wl_bus[16]; - assign sram_blwl_wl[880] = wl_bus[16]; - assign sram_blwl_wl[881] = wl_bus[16]; - assign sram_blwl_wl[882] = wl_bus[16]; - assign sram_blwl_wl[883] = wl_bus[16]; - assign sram_blwl_wl[884] = wl_bus[17]; - assign sram_blwl_wl[885] = wl_bus[17]; - assign sram_blwl_wl[886] = wl_bus[17]; - assign sram_blwl_wl[887] = wl_bus[17]; - assign sram_blwl_wl[888] = wl_bus[17]; - assign sram_blwl_wl[889] = wl_bus[17]; - assign sram_blwl_wl[890] = wl_bus[17]; - assign sram_blwl_wl[891] = wl_bus[17]; - assign sram_blwl_wl[892] = wl_bus[17]; - assign sram_blwl_wl[893] = wl_bus[17]; - assign sram_blwl_wl[894] = wl_bus[17]; - assign sram_blwl_wl[895] = wl_bus[17]; - assign sram_blwl_wl[896] = wl_bus[17]; - assign sram_blwl_wl[897] = wl_bus[17]; - assign sram_blwl_wl[898] = wl_bus[17]; - assign sram_blwl_wl[899] = wl_bus[17]; - assign sram_blwl_wl[900] = wl_bus[17]; - assign sram_blwl_wl[901] = wl_bus[17]; - assign sram_blwl_wl[902] = wl_bus[17]; - assign sram_blwl_wl[903] = wl_bus[17]; - assign sram_blwl_wl[904] = wl_bus[17]; - assign sram_blwl_wl[905] = wl_bus[17]; - assign sram_blwl_wl[906] = wl_bus[17]; - assign sram_blwl_wl[907] = wl_bus[17]; - assign sram_blwl_wl[908] = wl_bus[17]; - assign sram_blwl_wl[909] = wl_bus[17]; - assign sram_blwl_wl[910] = wl_bus[17]; - assign sram_blwl_wl[911] = wl_bus[17]; - assign sram_blwl_wl[912] = wl_bus[17]; - assign sram_blwl_wl[913] = wl_bus[17]; - assign sram_blwl_wl[914] = wl_bus[17]; - assign sram_blwl_wl[915] = wl_bus[17]; - assign sram_blwl_wl[916] = wl_bus[17]; - assign sram_blwl_wl[917] = wl_bus[17]; - assign sram_blwl_wl[918] = wl_bus[17]; - assign sram_blwl_wl[919] = wl_bus[17]; - assign sram_blwl_wl[920] = wl_bus[17]; - assign sram_blwl_wl[921] = wl_bus[17]; - assign sram_blwl_wl[922] = wl_bus[17]; - assign sram_blwl_wl[923] = wl_bus[17]; - assign sram_blwl_wl[924] = wl_bus[17]; - assign sram_blwl_wl[925] = wl_bus[17]; - assign sram_blwl_wl[926] = wl_bus[17]; - assign sram_blwl_wl[927] = wl_bus[17]; - assign sram_blwl_wl[928] = wl_bus[17]; - assign sram_blwl_wl[929] = wl_bus[17]; - assign sram_blwl_wl[930] = wl_bus[17]; - assign sram_blwl_wl[931] = wl_bus[17]; - assign sram_blwl_wl[932] = wl_bus[17]; - assign sram_blwl_wl[933] = wl_bus[17]; - assign sram_blwl_wl[934] = wl_bus[17]; - assign sram_blwl_wl[935] = wl_bus[17]; - assign sram_blwl_wl[936] = wl_bus[18]; - assign sram_blwl_wl[937] = wl_bus[18]; - assign sram_blwl_wl[938] = wl_bus[18]; - assign sram_blwl_wl[939] = wl_bus[18]; - assign sram_blwl_wl[940] = wl_bus[18]; - assign sram_blwl_wl[941] = wl_bus[18]; - assign sram_blwl_wl[942] = wl_bus[18]; - assign sram_blwl_wl[943] = wl_bus[18]; - assign sram_blwl_wl[944] = wl_bus[18]; - assign sram_blwl_wl[945] = wl_bus[18]; - assign sram_blwl_wl[946] = wl_bus[18]; - assign sram_blwl_wl[947] = wl_bus[18]; - assign sram_blwl_wl[948] = wl_bus[18]; - assign sram_blwl_wl[949] = wl_bus[18]; - assign sram_blwl_wl[950] = wl_bus[18]; - assign sram_blwl_wl[951] = wl_bus[18]; - assign sram_blwl_wl[952] = wl_bus[18]; - assign sram_blwl_wl[953] = wl_bus[18]; - assign sram_blwl_wl[954] = wl_bus[18]; - assign sram_blwl_wl[955] = wl_bus[18]; - assign sram_blwl_wl[956] = wl_bus[18]; - assign sram_blwl_wl[957] = wl_bus[18]; - assign sram_blwl_wl[958] = wl_bus[18]; - assign sram_blwl_wl[959] = wl_bus[18]; - assign sram_blwl_wl[960] = wl_bus[18]; - assign sram_blwl_wl[961] = wl_bus[18]; - assign sram_blwl_wl[962] = wl_bus[18]; - assign sram_blwl_wl[963] = wl_bus[18]; - assign sram_blwl_wl[964] = wl_bus[18]; - assign sram_blwl_wl[965] = wl_bus[18]; - assign sram_blwl_wl[966] = wl_bus[18]; - assign sram_blwl_wl[967] = wl_bus[18]; - assign sram_blwl_wl[968] = wl_bus[18]; - assign sram_blwl_wl[969] = wl_bus[18]; - assign sram_blwl_wl[970] = wl_bus[18]; - assign sram_blwl_wl[971] = wl_bus[18]; - assign sram_blwl_wl[972] = wl_bus[18]; - assign sram_blwl_wl[973] = wl_bus[18]; - assign sram_blwl_wl[974] = wl_bus[18]; - assign sram_blwl_wl[975] = wl_bus[18]; - assign sram_blwl_wl[976] = wl_bus[18]; - assign sram_blwl_wl[977] = wl_bus[18]; - assign sram_blwl_wl[978] = wl_bus[18]; - assign sram_blwl_wl[979] = wl_bus[18]; - assign sram_blwl_wl[980] = wl_bus[18]; - assign sram_blwl_wl[981] = wl_bus[18]; - assign sram_blwl_wl[982] = wl_bus[18]; - assign sram_blwl_wl[983] = wl_bus[18]; - assign sram_blwl_wl[984] = wl_bus[18]; - assign sram_blwl_wl[985] = wl_bus[18]; - assign sram_blwl_wl[986] = wl_bus[18]; - assign sram_blwl_wl[987] = wl_bus[18]; - assign sram_blwl_wl[988] = wl_bus[19]; - assign sram_blwl_wl[989] = wl_bus[19]; - assign sram_blwl_wl[990] = wl_bus[19]; - assign sram_blwl_wl[991] = wl_bus[19]; - assign sram_blwl_wl[992] = wl_bus[19]; - assign sram_blwl_wl[993] = wl_bus[19]; - assign sram_blwl_wl[994] = wl_bus[19]; - assign sram_blwl_wl[995] = wl_bus[19]; - assign sram_blwl_wl[996] = wl_bus[19]; - assign sram_blwl_wl[997] = wl_bus[19]; - assign sram_blwl_wl[998] = wl_bus[19]; - assign sram_blwl_wl[999] = wl_bus[19]; - assign sram_blwl_wl[1000] = wl_bus[19]; - assign sram_blwl_wl[1001] = wl_bus[19]; - assign sram_blwl_wl[1002] = wl_bus[19]; - assign sram_blwl_wl[1003] = wl_bus[19]; - assign sram_blwl_wl[1004] = wl_bus[19]; - assign sram_blwl_wl[1005] = wl_bus[19]; - assign sram_blwl_wl[1006] = wl_bus[19]; - assign sram_blwl_wl[1007] = wl_bus[19]; - assign sram_blwl_wl[1008] = wl_bus[19]; - assign sram_blwl_wl[1009] = wl_bus[19]; - assign sram_blwl_wl[1010] = wl_bus[19]; - assign sram_blwl_wl[1011] = wl_bus[19]; - assign sram_blwl_wl[1012] = wl_bus[19]; - assign sram_blwl_wl[1013] = wl_bus[19]; - assign sram_blwl_wl[1014] = wl_bus[19]; - assign sram_blwl_wl[1015] = wl_bus[19]; - assign sram_blwl_wl[1016] = wl_bus[19]; - assign sram_blwl_wl[1017] = wl_bus[19]; - assign sram_blwl_wl[1018] = wl_bus[19]; - assign sram_blwl_wl[1019] = wl_bus[19]; - assign sram_blwl_wl[1020] = wl_bus[19]; - assign sram_blwl_wl[1021] = wl_bus[19]; - assign sram_blwl_wl[1022] = wl_bus[19]; - assign sram_blwl_wl[1023] = wl_bus[19]; - assign sram_blwl_wl[1024] = wl_bus[19]; - assign sram_blwl_wl[1025] = wl_bus[19]; - assign sram_blwl_wl[1026] = wl_bus[19]; - assign sram_blwl_wl[1027] = wl_bus[19]; - assign sram_blwl_wl[1028] = wl_bus[19]; - assign sram_blwl_wl[1029] = wl_bus[19]; - assign sram_blwl_wl[1030] = wl_bus[19]; - assign sram_blwl_wl[1031] = wl_bus[19]; - assign sram_blwl_wl[1032] = wl_bus[19]; - assign sram_blwl_wl[1033] = wl_bus[19]; - assign sram_blwl_wl[1034] = wl_bus[19]; - assign sram_blwl_wl[1035] = wl_bus[19]; - assign sram_blwl_wl[1036] = wl_bus[19]; - assign sram_blwl_wl[1037] = wl_bus[19]; - assign sram_blwl_wl[1038] = wl_bus[19]; - assign sram_blwl_wl[1039] = wl_bus[19]; - assign sram_blwl_wl[1040] = wl_bus[20]; - assign sram_blwl_wl[1041] = wl_bus[20]; - assign sram_blwl_wl[1042] = wl_bus[20]; - assign sram_blwl_wl[1043] = wl_bus[20]; - assign sram_blwl_wl[1044] = wl_bus[20]; - assign sram_blwl_wl[1045] = wl_bus[20]; - assign sram_blwl_wl[1046] = wl_bus[20]; - assign sram_blwl_wl[1047] = wl_bus[20]; - assign sram_blwl_wl[1048] = wl_bus[20]; - assign sram_blwl_wl[1049] = wl_bus[20]; - assign sram_blwl_wl[1050] = wl_bus[20]; - assign sram_blwl_wl[1051] = wl_bus[20]; - assign sram_blwl_wl[1052] = wl_bus[20]; - assign sram_blwl_wl[1053] = wl_bus[20]; - assign sram_blwl_wl[1054] = wl_bus[20]; - assign sram_blwl_wl[1055] = wl_bus[20]; - assign sram_blwl_wl[1056] = wl_bus[20]; - assign sram_blwl_wl[1057] = wl_bus[20]; - assign sram_blwl_wl[1058] = wl_bus[20]; - assign sram_blwl_wl[1059] = wl_bus[20]; - assign sram_blwl_wl[1060] = wl_bus[20]; - assign sram_blwl_wl[1061] = wl_bus[20]; - assign sram_blwl_wl[1062] = wl_bus[20]; - assign sram_blwl_wl[1063] = wl_bus[20]; - assign sram_blwl_wl[1064] = wl_bus[20]; - assign sram_blwl_wl[1065] = wl_bus[20]; - assign sram_blwl_wl[1066] = wl_bus[20]; - assign sram_blwl_wl[1067] = wl_bus[20]; - assign sram_blwl_wl[1068] = wl_bus[20]; - assign sram_blwl_wl[1069] = wl_bus[20]; - assign sram_blwl_wl[1070] = wl_bus[20]; - assign sram_blwl_wl[1071] = wl_bus[20]; - assign sram_blwl_wl[1072] = wl_bus[20]; - assign sram_blwl_wl[1073] = wl_bus[20]; - assign sram_blwl_wl[1074] = wl_bus[20]; - assign sram_blwl_wl[1075] = wl_bus[20]; - assign sram_blwl_wl[1076] = wl_bus[20]; - assign sram_blwl_wl[1077] = wl_bus[20]; - assign sram_blwl_wl[1078] = wl_bus[20]; - assign sram_blwl_wl[1079] = wl_bus[20]; - assign sram_blwl_wl[1080] = wl_bus[20]; - assign sram_blwl_wl[1081] = wl_bus[20]; - assign sram_blwl_wl[1082] = wl_bus[20]; - assign sram_blwl_wl[1083] = wl_bus[20]; - assign sram_blwl_wl[1084] = wl_bus[20]; - assign sram_blwl_wl[1085] = wl_bus[20]; - assign sram_blwl_wl[1086] = wl_bus[20]; - assign sram_blwl_wl[1087] = wl_bus[20]; - assign sram_blwl_wl[1088] = wl_bus[20]; - assign sram_blwl_wl[1089] = wl_bus[20]; - assign sram_blwl_wl[1090] = wl_bus[20]; - assign sram_blwl_wl[1091] = wl_bus[20]; - assign sram_blwl_wl[1092] = wl_bus[21]; - assign sram_blwl_wl[1093] = wl_bus[21]; - assign sram_blwl_wl[1094] = wl_bus[21]; - assign sram_blwl_wl[1095] = wl_bus[21]; - assign sram_blwl_wl[1096] = wl_bus[21]; - assign sram_blwl_wl[1097] = wl_bus[21]; - assign sram_blwl_wl[1098] = wl_bus[21]; - assign sram_blwl_wl[1099] = wl_bus[21]; - assign sram_blwl_wl[1100] = wl_bus[21]; - assign sram_blwl_wl[1101] = wl_bus[21]; - assign sram_blwl_wl[1102] = wl_bus[21]; - assign sram_blwl_wl[1103] = wl_bus[21]; - assign sram_blwl_wl[1104] = wl_bus[21]; - assign sram_blwl_wl[1105] = wl_bus[21]; - assign sram_blwl_wl[1106] = wl_bus[21]; - assign sram_blwl_wl[1107] = wl_bus[21]; - assign sram_blwl_wl[1108] = wl_bus[21]; - assign sram_blwl_wl[1109] = wl_bus[21]; - assign sram_blwl_wl[1110] = wl_bus[21]; - assign sram_blwl_wl[1111] = wl_bus[21]; - assign sram_blwl_wl[1112] = wl_bus[21]; - assign sram_blwl_wl[1113] = wl_bus[21]; - assign sram_blwl_wl[1114] = wl_bus[21]; - assign sram_blwl_wl[1115] = wl_bus[21]; - assign sram_blwl_wl[1116] = wl_bus[21]; - assign sram_blwl_wl[1117] = wl_bus[21]; - assign sram_blwl_wl[1118] = wl_bus[21]; - assign sram_blwl_wl[1119] = wl_bus[21]; - assign sram_blwl_wl[1120] = wl_bus[21]; - assign sram_blwl_wl[1121] = wl_bus[21]; - assign sram_blwl_wl[1122] = wl_bus[21]; - assign sram_blwl_wl[1123] = wl_bus[21]; - assign sram_blwl_wl[1124] = wl_bus[21]; - assign sram_blwl_wl[1125] = wl_bus[21]; - assign sram_blwl_wl[1126] = wl_bus[21]; - assign sram_blwl_wl[1127] = wl_bus[21]; - assign sram_blwl_wl[1128] = wl_bus[21]; - assign sram_blwl_wl[1129] = wl_bus[21]; - assign sram_blwl_wl[1130] = wl_bus[21]; - assign sram_blwl_wl[1131] = wl_bus[21]; - assign sram_blwl_wl[1132] = wl_bus[21]; - assign sram_blwl_wl[1133] = wl_bus[21]; - assign sram_blwl_wl[1134] = wl_bus[21]; - assign sram_blwl_wl[1135] = wl_bus[21]; - assign sram_blwl_wl[1136] = wl_bus[21]; - assign sram_blwl_wl[1137] = wl_bus[21]; - assign sram_blwl_wl[1138] = wl_bus[21]; - assign sram_blwl_wl[1139] = wl_bus[21]; - assign sram_blwl_wl[1140] = wl_bus[21]; - assign sram_blwl_wl[1141] = wl_bus[21]; - assign sram_blwl_wl[1142] = wl_bus[21]; - assign sram_blwl_wl[1143] = wl_bus[21]; - assign sram_blwl_wl[1144] = wl_bus[22]; - assign sram_blwl_wl[1145] = wl_bus[22]; - assign sram_blwl_wl[1146] = wl_bus[22]; - assign sram_blwl_wl[1147] = wl_bus[22]; - assign sram_blwl_wl[1148] = wl_bus[22]; - assign sram_blwl_wl[1149] = wl_bus[22]; - assign sram_blwl_wl[1150] = wl_bus[22]; - assign sram_blwl_wl[1151] = wl_bus[22]; - assign sram_blwl_wl[1152] = wl_bus[22]; - assign sram_blwl_wl[1153] = wl_bus[22]; - assign sram_blwl_wl[1154] = wl_bus[22]; - assign sram_blwl_wl[1155] = wl_bus[22]; - assign sram_blwl_wl[1156] = wl_bus[22]; - assign sram_blwl_wl[1157] = wl_bus[22]; - assign sram_blwl_wl[1158] = wl_bus[22]; - assign sram_blwl_wl[1159] = wl_bus[22]; - assign sram_blwl_wl[1160] = wl_bus[22]; - assign sram_blwl_wl[1161] = wl_bus[22]; - assign sram_blwl_wl[1162] = wl_bus[22]; - assign sram_blwl_wl[1163] = wl_bus[22]; - assign sram_blwl_wl[1164] = wl_bus[22]; - assign sram_blwl_wl[1165] = wl_bus[22]; - assign sram_blwl_wl[1166] = wl_bus[22]; - assign sram_blwl_wl[1167] = wl_bus[22]; - assign sram_blwl_wl[1168] = wl_bus[22]; - assign sram_blwl_wl[1169] = wl_bus[22]; - assign sram_blwl_wl[1170] = wl_bus[22]; - assign sram_blwl_wl[1171] = wl_bus[22]; - assign sram_blwl_wl[1172] = wl_bus[22]; - assign sram_blwl_wl[1173] = wl_bus[22]; - assign sram_blwl_wl[1174] = wl_bus[22]; - assign sram_blwl_wl[1175] = wl_bus[22]; - assign sram_blwl_wl[1176] = wl_bus[22]; - assign sram_blwl_wl[1177] = wl_bus[22]; - assign sram_blwl_wl[1178] = wl_bus[22]; - assign sram_blwl_wl[1179] = wl_bus[22]; - assign sram_blwl_wl[1180] = wl_bus[22]; - assign sram_blwl_wl[1181] = wl_bus[22]; - assign sram_blwl_wl[1182] = wl_bus[22]; - assign sram_blwl_wl[1183] = wl_bus[22]; - assign sram_blwl_wl[1184] = wl_bus[22]; - assign sram_blwl_wl[1185] = wl_bus[22]; - assign sram_blwl_wl[1186] = wl_bus[22]; - assign sram_blwl_wl[1187] = wl_bus[22]; - assign sram_blwl_wl[1188] = wl_bus[22]; - assign sram_blwl_wl[1189] = wl_bus[22]; - assign sram_blwl_wl[1190] = wl_bus[22]; - assign sram_blwl_wl[1191] = wl_bus[22]; - assign sram_blwl_wl[1192] = wl_bus[22]; - assign sram_blwl_wl[1193] = wl_bus[22]; - assign sram_blwl_wl[1194] = wl_bus[22]; - assign sram_blwl_wl[1195] = wl_bus[22]; - assign sram_blwl_wl[1196] = wl_bus[23]; - assign sram_blwl_wl[1197] = wl_bus[23]; - assign sram_blwl_wl[1198] = wl_bus[23]; - assign sram_blwl_wl[1199] = wl_bus[23]; - assign sram_blwl_wl[1200] = wl_bus[23]; - assign sram_blwl_wl[1201] = wl_bus[23]; - assign sram_blwl_wl[1202] = wl_bus[23]; - assign sram_blwl_wl[1203] = wl_bus[23]; - assign sram_blwl_wl[1204] = wl_bus[23]; - assign sram_blwl_wl[1205] = wl_bus[23]; - assign sram_blwl_wl[1206] = wl_bus[23]; - assign sram_blwl_wl[1207] = wl_bus[23]; - assign sram_blwl_wl[1208] = wl_bus[23]; - assign sram_blwl_wl[1209] = wl_bus[23]; - assign sram_blwl_wl[1210] = wl_bus[23]; - assign sram_blwl_wl[1211] = wl_bus[23]; - assign sram_blwl_wl[1212] = wl_bus[23]; - assign sram_blwl_wl[1213] = wl_bus[23]; - assign sram_blwl_wl[1214] = wl_bus[23]; - assign sram_blwl_wl[1215] = wl_bus[23]; - assign sram_blwl_wl[1216] = wl_bus[23]; - assign sram_blwl_wl[1217] = wl_bus[23]; - assign sram_blwl_wl[1218] = wl_bus[23]; - assign sram_blwl_wl[1219] = wl_bus[23]; - assign sram_blwl_wl[1220] = wl_bus[23]; - assign sram_blwl_wl[1221] = wl_bus[23]; - assign sram_blwl_wl[1222] = wl_bus[23]; - assign sram_blwl_wl[1223] = wl_bus[23]; - assign sram_blwl_wl[1224] = wl_bus[23]; - assign sram_blwl_wl[1225] = wl_bus[23]; - assign sram_blwl_wl[1226] = wl_bus[23]; - assign sram_blwl_wl[1227] = wl_bus[23]; - assign sram_blwl_wl[1228] = wl_bus[23]; - assign sram_blwl_wl[1229] = wl_bus[23]; - assign sram_blwl_wl[1230] = wl_bus[23]; - assign sram_blwl_wl[1231] = wl_bus[23]; - assign sram_blwl_wl[1232] = wl_bus[23]; - assign sram_blwl_wl[1233] = wl_bus[23]; - assign sram_blwl_wl[1234] = wl_bus[23]; - assign sram_blwl_wl[1235] = wl_bus[23]; - assign sram_blwl_wl[1236] = wl_bus[23]; - assign sram_blwl_wl[1237] = wl_bus[23]; - assign sram_blwl_wl[1238] = wl_bus[23]; - assign sram_blwl_wl[1239] = wl_bus[23]; - assign sram_blwl_wl[1240] = wl_bus[23]; - assign sram_blwl_wl[1241] = wl_bus[23]; - assign sram_blwl_wl[1242] = wl_bus[23]; - assign sram_blwl_wl[1243] = wl_bus[23]; - assign sram_blwl_wl[1244] = wl_bus[23]; - assign sram_blwl_wl[1245] = wl_bus[23]; - assign sram_blwl_wl[1246] = wl_bus[23]; - assign sram_blwl_wl[1247] = wl_bus[23]; - assign sram_blwl_wl[1248] = wl_bus[24]; - assign sram_blwl_wl[1249] = wl_bus[24]; - assign sram_blwl_wl[1250] = wl_bus[24]; - assign sram_blwl_wl[1251] = wl_bus[24]; - assign sram_blwl_wl[1252] = wl_bus[24]; - assign sram_blwl_wl[1253] = wl_bus[24]; - assign sram_blwl_wl[1254] = wl_bus[24]; - assign sram_blwl_wl[1255] = wl_bus[24]; - assign sram_blwl_wl[1256] = wl_bus[24]; - assign sram_blwl_wl[1257] = wl_bus[24]; - assign sram_blwl_wl[1258] = wl_bus[24]; - assign sram_blwl_wl[1259] = wl_bus[24]; - assign sram_blwl_wl[1260] = wl_bus[24]; - assign sram_blwl_wl[1261] = wl_bus[24]; - assign sram_blwl_wl[1262] = wl_bus[24]; - assign sram_blwl_wl[1263] = wl_bus[24]; - assign sram_blwl_wl[1264] = wl_bus[24]; - assign sram_blwl_wl[1265] = wl_bus[24]; - assign sram_blwl_wl[1266] = wl_bus[24]; - assign sram_blwl_wl[1267] = wl_bus[24]; - assign sram_blwl_wl[1268] = wl_bus[24]; - assign sram_blwl_wl[1269] = wl_bus[24]; - assign sram_blwl_wl[1270] = wl_bus[24]; - assign sram_blwl_wl[1271] = wl_bus[24]; - assign sram_blwl_wl[1272] = wl_bus[24]; - assign sram_blwl_wl[1273] = wl_bus[24]; - assign sram_blwl_wl[1274] = wl_bus[24]; - assign sram_blwl_wl[1275] = wl_bus[24]; - assign sram_blwl_wl[1276] = wl_bus[24]; - assign sram_blwl_wl[1277] = wl_bus[24]; - assign sram_blwl_wl[1278] = wl_bus[24]; - assign sram_blwl_wl[1279] = wl_bus[24]; - assign sram_blwl_wl[1280] = wl_bus[24]; - assign sram_blwl_wl[1281] = wl_bus[24]; - assign sram_blwl_wl[1282] = wl_bus[24]; - assign sram_blwl_wl[1283] = wl_bus[24]; - assign sram_blwl_wl[1284] = wl_bus[24]; - assign sram_blwl_wl[1285] = wl_bus[24]; - assign sram_blwl_wl[1286] = wl_bus[24]; - assign sram_blwl_wl[1287] = wl_bus[24]; - assign sram_blwl_wl[1288] = wl_bus[24]; - assign sram_blwl_wl[1289] = wl_bus[24]; - assign sram_blwl_wl[1290] = wl_bus[24]; - assign sram_blwl_wl[1291] = wl_bus[24]; - assign sram_blwl_wl[1292] = wl_bus[24]; - assign sram_blwl_wl[1293] = wl_bus[24]; - assign sram_blwl_wl[1294] = wl_bus[24]; - assign sram_blwl_wl[1295] = wl_bus[24]; - assign sram_blwl_wl[1296] = wl_bus[24]; - assign sram_blwl_wl[1297] = wl_bus[24]; - assign sram_blwl_wl[1298] = wl_bus[24]; - assign sram_blwl_wl[1299] = wl_bus[24]; - assign sram_blwl_wl[1300] = wl_bus[25]; - assign sram_blwl_wl[1301] = wl_bus[25]; - assign sram_blwl_wl[1302] = wl_bus[25]; - assign sram_blwl_wl[1303] = wl_bus[25]; - assign sram_blwl_wl[1304] = wl_bus[25]; - assign sram_blwl_wl[1305] = wl_bus[25]; - assign sram_blwl_wl[1306] = wl_bus[25]; - assign sram_blwl_wl[1307] = wl_bus[25]; - assign sram_blwl_wl[1308] = wl_bus[25]; - assign sram_blwl_wl[1309] = wl_bus[25]; - assign sram_blwl_wl[1310] = wl_bus[25]; - assign sram_blwl_wl[1311] = wl_bus[25]; - assign sram_blwl_wl[1312] = wl_bus[25]; - assign sram_blwl_wl[1313] = wl_bus[25]; - assign sram_blwl_wl[1314] = wl_bus[25]; - assign sram_blwl_wl[1315] = wl_bus[25]; - assign sram_blwl_wl[1316] = wl_bus[25]; - assign sram_blwl_wl[1317] = wl_bus[25]; - assign sram_blwl_wl[1318] = wl_bus[25]; - assign sram_blwl_wl[1319] = wl_bus[25]; - assign sram_blwl_wl[1320] = wl_bus[25]; - assign sram_blwl_wl[1321] = wl_bus[25]; - assign sram_blwl_wl[1322] = wl_bus[25]; - assign sram_blwl_wl[1323] = wl_bus[25]; - assign sram_blwl_wl[1324] = wl_bus[25]; - assign sram_blwl_wl[1325] = wl_bus[25]; - assign sram_blwl_wl[1326] = wl_bus[25]; - assign sram_blwl_wl[1327] = wl_bus[25]; - assign sram_blwl_wl[1328] = wl_bus[25]; - assign sram_blwl_wl[1329] = wl_bus[25]; - assign sram_blwl_wl[1330] = wl_bus[25]; - assign sram_blwl_wl[1331] = wl_bus[25]; - assign sram_blwl_wl[1332] = wl_bus[25]; - assign sram_blwl_wl[1333] = wl_bus[25]; - assign sram_blwl_wl[1334] = wl_bus[25]; - assign sram_blwl_wl[1335] = wl_bus[25]; - assign sram_blwl_wl[1336] = wl_bus[25]; - assign sram_blwl_wl[1337] = wl_bus[25]; - assign sram_blwl_wl[1338] = wl_bus[25]; - assign sram_blwl_wl[1339] = wl_bus[25]; - assign sram_blwl_wl[1340] = wl_bus[25]; - assign sram_blwl_wl[1341] = wl_bus[25]; - assign sram_blwl_wl[1342] = wl_bus[25]; - assign sram_blwl_wl[1343] = wl_bus[25]; - assign sram_blwl_wl[1344] = wl_bus[25]; - assign sram_blwl_wl[1345] = wl_bus[25]; - assign sram_blwl_wl[1346] = wl_bus[25]; - assign sram_blwl_wl[1347] = wl_bus[25]; - assign sram_blwl_wl[1348] = wl_bus[25]; - assign sram_blwl_wl[1349] = wl_bus[25]; - assign sram_blwl_wl[1350] = wl_bus[25]; - assign sram_blwl_wl[1351] = wl_bus[25]; - assign sram_blwl_wl[1352] = wl_bus[26]; - assign sram_blwl_wl[1353] = wl_bus[26]; - assign sram_blwl_wl[1354] = wl_bus[26]; - assign sram_blwl_wl[1355] = wl_bus[26]; - assign sram_blwl_wl[1356] = wl_bus[26]; - assign sram_blwl_wl[1357] = wl_bus[26]; - assign sram_blwl_wl[1358] = wl_bus[26]; - assign sram_blwl_wl[1359] = wl_bus[26]; - assign sram_blwl_wl[1360] = wl_bus[26]; - assign sram_blwl_wl[1361] = wl_bus[26]; - assign sram_blwl_wl[1362] = wl_bus[26]; - assign sram_blwl_wl[1363] = wl_bus[26]; - assign sram_blwl_wl[1364] = wl_bus[26]; - assign sram_blwl_wl[1365] = wl_bus[26]; - assign sram_blwl_wl[1366] = wl_bus[26]; - assign sram_blwl_wl[1367] = wl_bus[26]; - assign sram_blwl_wl[1368] = wl_bus[26]; - assign sram_blwl_wl[1369] = wl_bus[26]; - assign sram_blwl_wl[1370] = wl_bus[26]; - assign sram_blwl_wl[1371] = wl_bus[26]; - assign sram_blwl_wl[1372] = wl_bus[26]; - assign sram_blwl_wl[1373] = wl_bus[26]; - assign sram_blwl_wl[1374] = wl_bus[26]; - assign sram_blwl_wl[1375] = wl_bus[26]; - assign sram_blwl_wl[1376] = wl_bus[26]; - assign sram_blwl_wl[1377] = wl_bus[26]; - assign sram_blwl_wl[1378] = wl_bus[26]; - assign sram_blwl_wl[1379] = wl_bus[26]; - assign sram_blwl_wl[1380] = wl_bus[26]; - assign sram_blwl_wl[1381] = wl_bus[26]; - assign sram_blwl_wl[1382] = wl_bus[26]; - assign sram_blwl_wl[1383] = wl_bus[26]; - assign sram_blwl_wl[1384] = wl_bus[26]; - assign sram_blwl_wl[1385] = wl_bus[26]; - assign sram_blwl_wl[1386] = wl_bus[26]; - assign sram_blwl_wl[1387] = wl_bus[26]; - assign sram_blwl_wl[1388] = wl_bus[26]; - assign sram_blwl_wl[1389] = wl_bus[26]; - assign sram_blwl_wl[1390] = wl_bus[26]; - assign sram_blwl_wl[1391] = wl_bus[26]; - assign sram_blwl_wl[1392] = wl_bus[26]; - assign sram_blwl_wl[1393] = wl_bus[26]; - assign sram_blwl_wl[1394] = wl_bus[26]; - assign sram_blwl_wl[1395] = wl_bus[26]; - assign sram_blwl_wl[1396] = wl_bus[26]; - assign sram_blwl_wl[1397] = wl_bus[26]; - assign sram_blwl_wl[1398] = wl_bus[26]; - assign sram_blwl_wl[1399] = wl_bus[26]; - assign sram_blwl_wl[1400] = wl_bus[26]; - assign sram_blwl_wl[1401] = wl_bus[26]; - assign sram_blwl_wl[1402] = wl_bus[26]; - assign sram_blwl_wl[1403] = wl_bus[26]; - assign sram_blwl_wl[1404] = wl_bus[27]; - assign sram_blwl_wl[1405] = wl_bus[27]; - assign sram_blwl_wl[1406] = wl_bus[27]; - assign sram_blwl_wl[1407] = wl_bus[27]; - assign sram_blwl_wl[1408] = wl_bus[27]; - assign sram_blwl_wl[1409] = wl_bus[27]; - assign sram_blwl_wl[1410] = wl_bus[27]; - assign sram_blwl_wl[1411] = wl_bus[27]; - assign sram_blwl_wl[1412] = wl_bus[27]; - assign sram_blwl_wl[1413] = wl_bus[27]; - assign sram_blwl_wl[1414] = wl_bus[27]; - assign sram_blwl_wl[1415] = wl_bus[27]; - assign sram_blwl_wl[1416] = wl_bus[27]; - assign sram_blwl_wl[1417] = wl_bus[27]; - assign sram_blwl_wl[1418] = wl_bus[27]; - assign sram_blwl_wl[1419] = wl_bus[27]; - assign sram_blwl_wl[1420] = wl_bus[27]; - assign sram_blwl_wl[1421] = wl_bus[27]; - assign sram_blwl_wl[1422] = wl_bus[27]; - assign sram_blwl_wl[1423] = wl_bus[27]; - assign sram_blwl_wl[1424] = wl_bus[27]; - assign sram_blwl_wl[1425] = wl_bus[27]; - assign sram_blwl_wl[1426] = wl_bus[27]; - assign sram_blwl_wl[1427] = wl_bus[27]; - assign sram_blwl_wl[1428] = wl_bus[27]; - assign sram_blwl_wl[1429] = wl_bus[27]; - assign sram_blwl_wl[1430] = wl_bus[27]; - assign sram_blwl_wl[1431] = wl_bus[27]; - assign sram_blwl_wl[1432] = wl_bus[27]; - assign sram_blwl_wl[1433] = wl_bus[27]; - assign sram_blwl_wl[1434] = wl_bus[27]; - assign sram_blwl_wl[1435] = wl_bus[27]; - assign sram_blwl_wl[1436] = wl_bus[27]; - assign sram_blwl_wl[1437] = wl_bus[27]; - assign sram_blwl_wl[1438] = wl_bus[27]; - assign sram_blwl_wl[1439] = wl_bus[27]; - assign sram_blwl_wl[1440] = wl_bus[27]; - assign sram_blwl_wl[1441] = wl_bus[27]; - assign sram_blwl_wl[1442] = wl_bus[27]; - assign sram_blwl_wl[1443] = wl_bus[27]; - assign sram_blwl_wl[1444] = wl_bus[27]; - assign sram_blwl_wl[1445] = wl_bus[27]; - assign sram_blwl_wl[1446] = wl_bus[27]; - assign sram_blwl_wl[1447] = wl_bus[27]; - assign sram_blwl_wl[1448] = wl_bus[27]; - assign sram_blwl_wl[1449] = wl_bus[27]; - assign sram_blwl_wl[1450] = wl_bus[27]; - assign sram_blwl_wl[1451] = wl_bus[27]; - assign sram_blwl_wl[1452] = wl_bus[27]; - assign sram_blwl_wl[1453] = wl_bus[27]; - assign sram_blwl_wl[1454] = wl_bus[27]; - assign sram_blwl_wl[1455] = wl_bus[27]; - assign sram_blwl_wl[1456] = wl_bus[28]; - assign sram_blwl_wl[1457] = wl_bus[28]; - assign sram_blwl_wl[1458] = wl_bus[28]; - assign sram_blwl_wl[1459] = wl_bus[28]; - assign sram_blwl_wl[1460] = wl_bus[28]; - assign sram_blwl_wl[1461] = wl_bus[28]; - assign sram_blwl_wl[1462] = wl_bus[28]; - assign sram_blwl_wl[1463] = wl_bus[28]; - assign sram_blwl_wl[1464] = wl_bus[28]; - assign sram_blwl_wl[1465] = wl_bus[28]; - assign sram_blwl_wl[1466] = wl_bus[28]; - assign sram_blwl_wl[1467] = wl_bus[28]; - assign sram_blwl_wl[1468] = wl_bus[28]; - assign sram_blwl_wl[1469] = wl_bus[28]; - assign sram_blwl_wl[1470] = wl_bus[28]; - assign sram_blwl_wl[1471] = wl_bus[28]; - assign sram_blwl_wl[1472] = wl_bus[28]; - assign sram_blwl_wl[1473] = wl_bus[28]; - assign sram_blwl_wl[1474] = wl_bus[28]; - assign sram_blwl_wl[1475] = wl_bus[28]; - assign sram_blwl_wl[1476] = wl_bus[28]; - assign sram_blwl_wl[1477] = wl_bus[28]; - assign sram_blwl_wl[1478] = wl_bus[28]; - assign sram_blwl_wl[1479] = wl_bus[28]; - assign sram_blwl_wl[1480] = wl_bus[28]; - assign sram_blwl_wl[1481] = wl_bus[28]; - assign sram_blwl_wl[1482] = wl_bus[28]; - assign sram_blwl_wl[1483] = wl_bus[28]; - assign sram_blwl_wl[1484] = wl_bus[28]; - assign sram_blwl_wl[1485] = wl_bus[28]; - assign sram_blwl_wl[1486] = wl_bus[28]; - assign sram_blwl_wl[1487] = wl_bus[28]; - assign sram_blwl_wl[1488] = wl_bus[28]; - assign sram_blwl_wl[1489] = wl_bus[28]; - assign sram_blwl_wl[1490] = wl_bus[28]; - assign sram_blwl_wl[1491] = wl_bus[28]; - assign sram_blwl_wl[1492] = wl_bus[28]; - assign sram_blwl_wl[1493] = wl_bus[28]; - assign sram_blwl_wl[1494] = wl_bus[28]; - assign sram_blwl_wl[1495] = wl_bus[28]; - assign sram_blwl_wl[1496] = wl_bus[28]; - assign sram_blwl_wl[1497] = wl_bus[28]; - assign sram_blwl_wl[1498] = wl_bus[28]; - assign sram_blwl_wl[1499] = wl_bus[28]; - assign sram_blwl_wl[1500] = wl_bus[28]; - assign sram_blwl_wl[1501] = wl_bus[28]; - assign sram_blwl_wl[1502] = wl_bus[28]; - assign sram_blwl_wl[1503] = wl_bus[28]; - assign sram_blwl_wl[1504] = wl_bus[28]; - assign sram_blwl_wl[1505] = wl_bus[28]; - assign sram_blwl_wl[1506] = wl_bus[28]; - assign sram_blwl_wl[1507] = wl_bus[28]; - assign sram_blwl_wl[1508] = wl_bus[29]; - assign sram_blwl_wl[1509] = wl_bus[29]; - assign sram_blwl_wl[1510] = wl_bus[29]; - assign sram_blwl_wl[1511] = wl_bus[29]; - assign sram_blwl_wl[1512] = wl_bus[29]; - assign sram_blwl_wl[1513] = wl_bus[29]; - assign sram_blwl_wl[1514] = wl_bus[29]; - assign sram_blwl_wl[1515] = wl_bus[29]; - assign sram_blwl_wl[1516] = wl_bus[29]; - assign sram_blwl_wl[1517] = wl_bus[29]; - assign sram_blwl_wl[1518] = wl_bus[29]; - assign sram_blwl_wl[1519] = wl_bus[29]; - assign sram_blwl_wl[1520] = wl_bus[29]; - assign sram_blwl_wl[1521] = wl_bus[29]; - assign sram_blwl_wl[1522] = wl_bus[29]; - assign sram_blwl_wl[1523] = wl_bus[29]; - assign sram_blwl_wl[1524] = wl_bus[29]; - assign sram_blwl_wl[1525] = wl_bus[29]; - assign sram_blwl_wl[1526] = wl_bus[29]; - assign sram_blwl_wl[1527] = wl_bus[29]; - assign sram_blwl_wl[1528] = wl_bus[29]; - assign sram_blwl_wl[1529] = wl_bus[29]; - assign sram_blwl_wl[1530] = wl_bus[29]; - assign sram_blwl_wl[1531] = wl_bus[29]; - assign sram_blwl_wl[1532] = wl_bus[29]; - assign sram_blwl_wl[1533] = wl_bus[29]; - assign sram_blwl_wl[1534] = wl_bus[29]; - assign sram_blwl_wl[1535] = wl_bus[29]; - assign sram_blwl_wl[1536] = wl_bus[29]; - assign sram_blwl_wl[1537] = wl_bus[29]; - assign sram_blwl_wl[1538] = wl_bus[29]; - assign sram_blwl_wl[1539] = wl_bus[29]; - assign sram_blwl_wl[1540] = wl_bus[29]; - assign sram_blwl_wl[1541] = wl_bus[29]; - assign sram_blwl_wl[1542] = wl_bus[29]; - assign sram_blwl_wl[1543] = wl_bus[29]; - assign sram_blwl_wl[1544] = wl_bus[29]; - assign sram_blwl_wl[1545] = wl_bus[29]; - assign sram_blwl_wl[1546] = wl_bus[29]; - assign sram_blwl_wl[1547] = wl_bus[29]; - assign sram_blwl_wl[1548] = wl_bus[29]; - assign sram_blwl_wl[1549] = wl_bus[29]; - assign sram_blwl_wl[1550] = wl_bus[29]; - assign sram_blwl_wl[1551] = wl_bus[29]; - assign sram_blwl_wl[1552] = wl_bus[29]; - assign sram_blwl_wl[1553] = wl_bus[29]; - assign sram_blwl_wl[1554] = wl_bus[29]; - assign sram_blwl_wl[1555] = wl_bus[29]; - assign sram_blwl_wl[1556] = wl_bus[29]; - assign sram_blwl_wl[1557] = wl_bus[29]; - assign sram_blwl_wl[1558] = wl_bus[29]; - assign sram_blwl_wl[1559] = wl_bus[29]; - assign sram_blwl_wl[1560] = wl_bus[30]; - assign sram_blwl_wl[1561] = wl_bus[30]; - assign sram_blwl_wl[1562] = wl_bus[30]; - assign sram_blwl_wl[1563] = wl_bus[30]; - assign sram_blwl_wl[1564] = wl_bus[30]; - assign sram_blwl_wl[1565] = wl_bus[30]; - assign sram_blwl_wl[1566] = wl_bus[30]; - assign sram_blwl_wl[1567] = wl_bus[30]; - assign sram_blwl_wl[1568] = wl_bus[30]; - assign sram_blwl_wl[1569] = wl_bus[30]; - assign sram_blwl_wl[1570] = wl_bus[30]; - assign sram_blwl_wl[1571] = wl_bus[30]; - assign sram_blwl_wl[1572] = wl_bus[30]; - assign sram_blwl_wl[1573] = wl_bus[30]; - assign sram_blwl_wl[1574] = wl_bus[30]; - assign sram_blwl_wl[1575] = wl_bus[30]; - assign sram_blwl_wl[1576] = wl_bus[30]; - assign sram_blwl_wl[1577] = wl_bus[30]; - assign sram_blwl_wl[1578] = wl_bus[30]; - assign sram_blwl_wl[1579] = wl_bus[30]; - assign sram_blwl_wl[1580] = wl_bus[30]; - assign sram_blwl_wl[1581] = wl_bus[30]; - assign sram_blwl_wl[1582] = wl_bus[30]; - assign sram_blwl_wl[1583] = wl_bus[30]; - assign sram_blwl_wl[1584] = wl_bus[30]; - assign sram_blwl_wl[1585] = wl_bus[30]; - assign sram_blwl_wl[1586] = wl_bus[30]; - assign sram_blwl_wl[1587] = wl_bus[30]; - assign sram_blwl_wl[1588] = wl_bus[30]; - assign sram_blwl_wl[1589] = wl_bus[30]; - assign sram_blwl_wl[1590] = wl_bus[30]; - assign sram_blwl_wl[1591] = wl_bus[30]; - assign sram_blwl_wl[1592] = wl_bus[30]; - assign sram_blwl_wl[1593] = wl_bus[30]; - assign sram_blwl_wl[1594] = wl_bus[30]; - assign sram_blwl_wl[1595] = wl_bus[30]; - assign sram_blwl_wl[1596] = wl_bus[30]; - assign sram_blwl_wl[1597] = wl_bus[30]; - assign sram_blwl_wl[1598] = wl_bus[30]; - assign sram_blwl_wl[1599] = wl_bus[30]; - assign sram_blwl_wl[1600] = wl_bus[30]; - assign sram_blwl_wl[1601] = wl_bus[30]; - assign sram_blwl_wl[1602] = wl_bus[30]; - assign sram_blwl_wl[1603] = wl_bus[30]; - assign sram_blwl_wl[1604] = wl_bus[30]; - assign sram_blwl_wl[1605] = wl_bus[30]; - assign sram_blwl_wl[1606] = wl_bus[30]; - assign sram_blwl_wl[1607] = wl_bus[30]; - assign sram_blwl_wl[1608] = wl_bus[30]; - assign sram_blwl_wl[1609] = wl_bus[30]; - assign sram_blwl_wl[1610] = wl_bus[30]; - assign sram_blwl_wl[1611] = wl_bus[30]; - assign sram_blwl_wl[1612] = wl_bus[31]; - assign sram_blwl_wl[1613] = wl_bus[31]; - assign sram_blwl_wl[1614] = wl_bus[31]; - assign sram_blwl_wl[1615] = wl_bus[31]; - assign sram_blwl_wl[1616] = wl_bus[31]; - assign sram_blwl_wl[1617] = wl_bus[31]; - assign sram_blwl_wl[1618] = wl_bus[31]; - assign sram_blwl_wl[1619] = wl_bus[31]; - assign sram_blwl_wl[1620] = wl_bus[31]; - assign sram_blwl_wl[1621] = wl_bus[31]; - assign sram_blwl_wl[1622] = wl_bus[31]; - assign sram_blwl_wl[1623] = wl_bus[31]; - assign sram_blwl_wl[1624] = wl_bus[31]; - assign sram_blwl_wl[1625] = wl_bus[31]; - assign sram_blwl_wl[1626] = wl_bus[31]; - assign sram_blwl_wl[1627] = wl_bus[31]; - assign sram_blwl_wl[1628] = wl_bus[31]; - assign sram_blwl_wl[1629] = wl_bus[31]; - assign sram_blwl_wl[1630] = wl_bus[31]; - assign sram_blwl_wl[1631] = wl_bus[31]; - assign sram_blwl_wl[1632] = wl_bus[31]; - assign sram_blwl_wl[1633] = wl_bus[31]; - assign sram_blwl_wl[1634] = wl_bus[31]; - assign sram_blwl_wl[1635] = wl_bus[31]; - assign sram_blwl_wl[1636] = wl_bus[31]; - assign sram_blwl_wl[1637] = wl_bus[31]; - assign sram_blwl_wl[1638] = wl_bus[31]; - assign sram_blwl_wl[1639] = wl_bus[31]; - assign sram_blwl_wl[1640] = wl_bus[31]; - assign sram_blwl_wl[1641] = wl_bus[31]; - assign sram_blwl_wl[1642] = wl_bus[31]; - assign sram_blwl_wl[1643] = wl_bus[31]; - assign sram_blwl_wl[1644] = wl_bus[31]; - assign sram_blwl_wl[1645] = wl_bus[31]; - assign sram_blwl_wl[1646] = wl_bus[31]; - assign sram_blwl_wl[1647] = wl_bus[31]; - assign sram_blwl_wl[1648] = wl_bus[31]; - assign sram_blwl_wl[1649] = wl_bus[31]; - assign sram_blwl_wl[1650] = wl_bus[31]; - assign sram_blwl_wl[1651] = wl_bus[31]; - assign sram_blwl_wl[1652] = wl_bus[31]; - assign sram_blwl_wl[1653] = wl_bus[31]; - assign sram_blwl_wl[1654] = wl_bus[31]; - assign sram_blwl_wl[1655] = wl_bus[31]; - assign sram_blwl_wl[1656] = wl_bus[31]; - assign sram_blwl_wl[1657] = wl_bus[31]; - assign sram_blwl_wl[1658] = wl_bus[31]; - assign sram_blwl_wl[1659] = wl_bus[31]; - assign sram_blwl_wl[1660] = wl_bus[31]; - assign sram_blwl_wl[1661] = wl_bus[31]; - assign sram_blwl_wl[1662] = wl_bus[31]; - assign sram_blwl_wl[1663] = wl_bus[31]; - assign sram_blwl_wl[1664] = wl_bus[32]; - assign sram_blwl_wl[1665] = wl_bus[32]; - assign sram_blwl_wl[1666] = wl_bus[32]; - assign sram_blwl_wl[1667] = wl_bus[32]; - assign sram_blwl_wl[1668] = wl_bus[32]; - assign sram_blwl_wl[1669] = wl_bus[32]; - assign sram_blwl_wl[1670] = wl_bus[32]; - assign sram_blwl_wl[1671] = wl_bus[32]; - assign sram_blwl_wl[1672] = wl_bus[32]; - assign sram_blwl_wl[1673] = wl_bus[32]; - assign sram_blwl_wl[1674] = wl_bus[32]; - assign sram_blwl_wl[1675] = wl_bus[32]; - assign sram_blwl_wl[1676] = wl_bus[32]; - assign sram_blwl_wl[1677] = wl_bus[32]; - assign sram_blwl_wl[1678] = wl_bus[32]; - assign sram_blwl_wl[1679] = wl_bus[32]; - assign sram_blwl_wl[1680] = wl_bus[32]; - assign sram_blwl_wl[1681] = wl_bus[32]; - assign sram_blwl_wl[1682] = wl_bus[32]; - assign sram_blwl_wl[1683] = wl_bus[32]; - assign sram_blwl_wl[1684] = wl_bus[32]; - assign sram_blwl_wl[1685] = wl_bus[32]; - assign sram_blwl_wl[1686] = wl_bus[32]; - assign sram_blwl_wl[1687] = wl_bus[32]; - assign sram_blwl_wl[1688] = wl_bus[32]; - assign sram_blwl_wl[1689] = wl_bus[32]; - assign sram_blwl_wl[1690] = wl_bus[32]; - assign sram_blwl_wl[1691] = wl_bus[32]; - assign sram_blwl_wl[1692] = wl_bus[32]; - assign sram_blwl_wl[1693] = wl_bus[32]; - assign sram_blwl_wl[1694] = wl_bus[32]; - assign sram_blwl_wl[1695] = wl_bus[32]; - assign sram_blwl_wl[1696] = wl_bus[32]; - assign sram_blwl_wl[1697] = wl_bus[32]; - assign sram_blwl_wl[1698] = wl_bus[32]; - assign sram_blwl_wl[1699] = wl_bus[32]; - assign sram_blwl_wl[1700] = wl_bus[32]; - assign sram_blwl_wl[1701] = wl_bus[32]; - assign sram_blwl_wl[1702] = wl_bus[32]; - assign sram_blwl_wl[1703] = wl_bus[32]; - assign sram_blwl_wl[1704] = wl_bus[32]; - assign sram_blwl_wl[1705] = wl_bus[32]; - assign sram_blwl_wl[1706] = wl_bus[32]; - assign sram_blwl_wl[1707] = wl_bus[32]; - assign sram_blwl_wl[1708] = wl_bus[32]; - assign sram_blwl_wl[1709] = wl_bus[32]; - assign sram_blwl_wl[1710] = wl_bus[32]; - assign sram_blwl_wl[1711] = wl_bus[32]; - assign sram_blwl_wl[1712] = wl_bus[32]; - assign sram_blwl_wl[1713] = wl_bus[32]; - assign sram_blwl_wl[1714] = wl_bus[32]; - assign sram_blwl_wl[1715] = wl_bus[32]; - assign sram_blwl_wl[1716] = wl_bus[33]; - assign sram_blwl_wl[1717] = wl_bus[33]; - assign sram_blwl_wl[1718] = wl_bus[33]; - assign sram_blwl_wl[1719] = wl_bus[33]; - assign sram_blwl_wl[1720] = wl_bus[33]; - assign sram_blwl_wl[1721] = wl_bus[33]; - assign sram_blwl_wl[1722] = wl_bus[33]; - assign sram_blwl_wl[1723] = wl_bus[33]; - assign sram_blwl_wl[1724] = wl_bus[33]; - assign sram_blwl_wl[1725] = wl_bus[33]; - assign sram_blwl_wl[1726] = wl_bus[33]; - assign sram_blwl_wl[1727] = wl_bus[33]; - assign sram_blwl_wl[1728] = wl_bus[33]; - assign sram_blwl_wl[1729] = wl_bus[33]; - assign sram_blwl_wl[1730] = wl_bus[33]; - assign sram_blwl_wl[1731] = wl_bus[33]; - assign sram_blwl_wl[1732] = wl_bus[33]; - assign sram_blwl_wl[1733] = wl_bus[33]; - assign sram_blwl_wl[1734] = wl_bus[33]; - assign sram_blwl_wl[1735] = wl_bus[33]; - assign sram_blwl_wl[1736] = wl_bus[33]; - assign sram_blwl_wl[1737] = wl_bus[33]; - assign sram_blwl_wl[1738] = wl_bus[33]; - assign sram_blwl_wl[1739] = wl_bus[33]; - assign sram_blwl_wl[1740] = wl_bus[33]; - assign sram_blwl_wl[1741] = wl_bus[33]; - assign sram_blwl_wl[1742] = wl_bus[33]; - assign sram_blwl_wl[1743] = wl_bus[33]; - assign sram_blwl_wl[1744] = wl_bus[33]; - assign sram_blwl_wl[1745] = wl_bus[33]; - assign sram_blwl_wl[1746] = wl_bus[33]; - assign sram_blwl_wl[1747] = wl_bus[33]; - assign sram_blwl_wl[1748] = wl_bus[33]; - assign sram_blwl_wl[1749] = wl_bus[33]; - assign sram_blwl_wl[1750] = wl_bus[33]; - assign sram_blwl_wl[1751] = wl_bus[33]; - assign sram_blwl_wl[1752] = wl_bus[33]; - assign sram_blwl_wl[1753] = wl_bus[33]; - assign sram_blwl_wl[1754] = wl_bus[33]; - assign sram_blwl_wl[1755] = wl_bus[33]; - assign sram_blwl_wl[1756] = wl_bus[33]; - assign sram_blwl_wl[1757] = wl_bus[33]; - assign sram_blwl_wl[1758] = wl_bus[33]; - assign sram_blwl_wl[1759] = wl_bus[33]; - assign sram_blwl_wl[1760] = wl_bus[33]; - assign sram_blwl_wl[1761] = wl_bus[33]; - assign sram_blwl_wl[1762] = wl_bus[33]; - assign sram_blwl_wl[1763] = wl_bus[33]; - assign sram_blwl_wl[1764] = wl_bus[33]; - assign sram_blwl_wl[1765] = wl_bus[33]; - assign sram_blwl_wl[1766] = wl_bus[33]; - assign sram_blwl_wl[1767] = wl_bus[33]; - assign sram_blwl_wl[1768] = wl_bus[34]; - assign sram_blwl_wl[1769] = wl_bus[34]; - assign sram_blwl_wl[1770] = wl_bus[34]; - assign sram_blwl_wl[1771] = wl_bus[34]; - assign sram_blwl_wl[1772] = wl_bus[34]; - assign sram_blwl_wl[1773] = wl_bus[34]; - assign sram_blwl_wl[1774] = wl_bus[34]; - assign sram_blwl_wl[1775] = wl_bus[34]; - assign sram_blwl_wl[1776] = wl_bus[34]; - assign sram_blwl_wl[1777] = wl_bus[34]; - assign sram_blwl_wl[1778] = wl_bus[34]; - assign sram_blwl_wl[1779] = wl_bus[34]; - assign sram_blwl_wl[1780] = wl_bus[34]; - assign sram_blwl_wl[1781] = wl_bus[34]; - assign sram_blwl_wl[1782] = wl_bus[34]; - assign sram_blwl_wl[1783] = wl_bus[34]; - assign sram_blwl_wl[1784] = wl_bus[34]; - assign sram_blwl_wl[1785] = wl_bus[34]; - assign sram_blwl_wl[1786] = wl_bus[34]; - assign sram_blwl_wl[1787] = wl_bus[34]; - assign sram_blwl_wl[1788] = wl_bus[34]; - assign sram_blwl_wl[1789] = wl_bus[34]; - assign sram_blwl_wl[1790] = wl_bus[34]; - assign sram_blwl_wl[1791] = wl_bus[34]; - assign sram_blwl_wl[1792] = wl_bus[34]; - assign sram_blwl_wl[1793] = wl_bus[34]; - assign sram_blwl_wl[1794] = wl_bus[34]; - assign sram_blwl_wl[1795] = wl_bus[34]; - assign sram_blwl_wl[1796] = wl_bus[34]; - assign sram_blwl_wl[1797] = wl_bus[34]; - assign sram_blwl_wl[1798] = wl_bus[34]; - assign sram_blwl_wl[1799] = wl_bus[34]; - assign sram_blwl_wl[1800] = wl_bus[34]; - assign sram_blwl_wl[1801] = wl_bus[34]; - assign sram_blwl_wl[1802] = wl_bus[34]; - assign sram_blwl_wl[1803] = wl_bus[34]; - assign sram_blwl_wl[1804] = wl_bus[34]; - assign sram_blwl_wl[1805] = wl_bus[34]; - assign sram_blwl_wl[1806] = wl_bus[34]; - assign sram_blwl_wl[1807] = wl_bus[34]; - assign sram_blwl_wl[1808] = wl_bus[34]; - assign sram_blwl_wl[1809] = wl_bus[34]; - assign sram_blwl_wl[1810] = wl_bus[34]; - assign sram_blwl_wl[1811] = wl_bus[34]; - assign sram_blwl_wl[1812] = wl_bus[34]; - assign sram_blwl_wl[1813] = wl_bus[34]; - assign sram_blwl_wl[1814] = wl_bus[34]; - assign sram_blwl_wl[1815] = wl_bus[34]; - assign sram_blwl_wl[1816] = wl_bus[34]; - assign sram_blwl_wl[1817] = wl_bus[34]; - assign sram_blwl_wl[1818] = wl_bus[34]; - assign sram_blwl_wl[1819] = wl_bus[34]; - assign sram_blwl_wl[1820] = wl_bus[35]; - assign sram_blwl_wl[1821] = wl_bus[35]; - assign sram_blwl_wl[1822] = wl_bus[35]; - assign sram_blwl_wl[1823] = wl_bus[35]; - assign sram_blwl_wl[1824] = wl_bus[35]; - assign sram_blwl_wl[1825] = wl_bus[35]; - assign sram_blwl_wl[1826] = wl_bus[35]; - assign sram_blwl_wl[1827] = wl_bus[35]; - assign sram_blwl_wl[1828] = wl_bus[35]; - assign sram_blwl_wl[1829] = wl_bus[35]; - assign sram_blwl_wl[1830] = wl_bus[35]; - assign sram_blwl_wl[1831] = wl_bus[35]; - assign sram_blwl_wl[1832] = wl_bus[35]; - assign sram_blwl_wl[1833] = wl_bus[35]; - assign sram_blwl_wl[1834] = wl_bus[35]; - assign sram_blwl_wl[1835] = wl_bus[35]; - assign sram_blwl_wl[1836] = wl_bus[35]; - assign sram_blwl_wl[1837] = wl_bus[35]; - assign sram_blwl_wl[1838] = wl_bus[35]; - assign sram_blwl_wl[1839] = wl_bus[35]; - assign sram_blwl_wl[1840] = wl_bus[35]; - assign sram_blwl_wl[1841] = wl_bus[35]; - assign sram_blwl_wl[1842] = wl_bus[35]; - assign sram_blwl_wl[1843] = wl_bus[35]; - assign sram_blwl_wl[1844] = wl_bus[35]; - assign sram_blwl_wl[1845] = wl_bus[35]; - assign sram_blwl_wl[1846] = wl_bus[35]; - assign sram_blwl_wl[1847] = wl_bus[35]; - assign sram_blwl_wl[1848] = wl_bus[35]; - assign sram_blwl_wl[1849] = wl_bus[35]; - assign sram_blwl_wl[1850] = wl_bus[35]; - assign sram_blwl_wl[1851] = wl_bus[35]; - assign sram_blwl_wl[1852] = wl_bus[35]; - assign sram_blwl_wl[1853] = wl_bus[35]; - assign sram_blwl_wl[1854] = wl_bus[35]; - assign sram_blwl_wl[1855] = wl_bus[35]; - assign sram_blwl_wl[1856] = wl_bus[35]; - assign sram_blwl_wl[1857] = wl_bus[35]; - assign sram_blwl_wl[1858] = wl_bus[35]; - assign sram_blwl_wl[1859] = wl_bus[35]; - assign sram_blwl_wl[1860] = wl_bus[35]; - assign sram_blwl_wl[1861] = wl_bus[35]; - assign sram_blwl_wl[1862] = wl_bus[35]; - assign sram_blwl_wl[1863] = wl_bus[35]; - assign sram_blwl_wl[1864] = wl_bus[35]; - assign sram_blwl_wl[1865] = wl_bus[35]; - assign sram_blwl_wl[1866] = wl_bus[35]; - assign sram_blwl_wl[1867] = wl_bus[35]; - assign sram_blwl_wl[1868] = wl_bus[35]; - assign sram_blwl_wl[1869] = wl_bus[35]; - assign sram_blwl_wl[1870] = wl_bus[35]; - assign sram_blwl_wl[1871] = wl_bus[35]; - assign sram_blwl_wl[1872] = wl_bus[36]; - assign sram_blwl_wl[1873] = wl_bus[36]; - assign sram_blwl_wl[1874] = wl_bus[36]; - assign sram_blwl_wl[1875] = wl_bus[36]; - assign sram_blwl_wl[1876] = wl_bus[36]; - assign sram_blwl_wl[1877] = wl_bus[36]; - assign sram_blwl_wl[1878] = wl_bus[36]; - assign sram_blwl_wl[1879] = wl_bus[36]; - assign sram_blwl_wl[1880] = wl_bus[36]; - assign sram_blwl_wl[1881] = wl_bus[36]; - assign sram_blwl_wl[1882] = wl_bus[36]; - assign sram_blwl_wl[1883] = wl_bus[36]; - assign sram_blwl_wl[1884] = wl_bus[36]; - assign sram_blwl_wl[1885] = wl_bus[36]; - assign sram_blwl_wl[1886] = wl_bus[36]; - assign sram_blwl_wl[1887] = wl_bus[36]; - assign sram_blwl_wl[1888] = wl_bus[36]; - assign sram_blwl_wl[1889] = wl_bus[36]; - assign sram_blwl_wl[1890] = wl_bus[36]; - assign sram_blwl_wl[1891] = wl_bus[36]; - assign sram_blwl_wl[1892] = wl_bus[36]; - assign sram_blwl_wl[1893] = wl_bus[36]; - assign sram_blwl_wl[1894] = wl_bus[36]; - assign sram_blwl_wl[1895] = wl_bus[36]; - assign sram_blwl_wl[1896] = wl_bus[36]; - assign sram_blwl_wl[1897] = wl_bus[36]; - assign sram_blwl_wl[1898] = wl_bus[36]; - assign sram_blwl_wl[1899] = wl_bus[36]; - assign sram_blwl_wl[1900] = wl_bus[36]; - assign sram_blwl_wl[1901] = wl_bus[36]; - assign sram_blwl_wl[1902] = wl_bus[36]; - assign sram_blwl_wl[1903] = wl_bus[36]; - assign sram_blwl_wl[1904] = wl_bus[36]; - assign sram_blwl_wl[1905] = wl_bus[36]; - assign sram_blwl_wl[1906] = wl_bus[36]; - assign sram_blwl_wl[1907] = wl_bus[36]; - assign sram_blwl_wl[1908] = wl_bus[36]; - assign sram_blwl_wl[1909] = wl_bus[36]; - assign sram_blwl_wl[1910] = wl_bus[36]; - assign sram_blwl_wl[1911] = wl_bus[36]; - assign sram_blwl_wl[1912] = wl_bus[36]; - assign sram_blwl_wl[1913] = wl_bus[36]; - assign sram_blwl_wl[1914] = wl_bus[36]; - assign sram_blwl_wl[1915] = wl_bus[36]; - assign sram_blwl_wl[1916] = wl_bus[36]; - assign sram_blwl_wl[1917] = wl_bus[36]; - assign sram_blwl_wl[1918] = wl_bus[36]; - assign sram_blwl_wl[1919] = wl_bus[36]; - assign sram_blwl_wl[1920] = wl_bus[36]; - assign sram_blwl_wl[1921] = wl_bus[36]; - assign sram_blwl_wl[1922] = wl_bus[36]; - assign sram_blwl_wl[1923] = wl_bus[36]; - assign sram_blwl_wl[1924] = wl_bus[37]; - assign sram_blwl_wl[1925] = wl_bus[37]; - assign sram_blwl_wl[1926] = wl_bus[37]; - assign sram_blwl_wl[1927] = wl_bus[37]; - assign sram_blwl_wl[1928] = wl_bus[37]; - assign sram_blwl_wl[1929] = wl_bus[37]; - assign sram_blwl_wl[1930] = wl_bus[37]; - assign sram_blwl_wl[1931] = wl_bus[37]; - assign sram_blwl_wl[1932] = wl_bus[37]; - assign sram_blwl_wl[1933] = wl_bus[37]; - assign sram_blwl_wl[1934] = wl_bus[37]; - assign sram_blwl_wl[1935] = wl_bus[37]; - assign sram_blwl_wl[1936] = wl_bus[37]; - assign sram_blwl_wl[1937] = wl_bus[37]; - assign sram_blwl_wl[1938] = wl_bus[37]; - assign sram_blwl_wl[1939] = wl_bus[37]; - assign sram_blwl_wl[1940] = wl_bus[37]; - assign sram_blwl_wl[1941] = wl_bus[37]; - assign sram_blwl_wl[1942] = wl_bus[37]; - assign sram_blwl_wl[1943] = wl_bus[37]; - assign sram_blwl_wl[1944] = wl_bus[37]; - assign sram_blwl_wl[1945] = wl_bus[37]; - assign sram_blwl_wl[1946] = wl_bus[37]; - assign sram_blwl_wl[1947] = wl_bus[37]; - assign sram_blwl_wl[1948] = wl_bus[37]; - assign sram_blwl_wl[1949] = wl_bus[37]; - assign sram_blwl_wl[1950] = wl_bus[37]; - assign sram_blwl_wl[1951] = wl_bus[37]; - assign sram_blwl_wl[1952] = wl_bus[37]; - assign sram_blwl_wl[1953] = wl_bus[37]; - assign sram_blwl_wl[1954] = wl_bus[37]; - assign sram_blwl_wl[1955] = wl_bus[37]; - assign sram_blwl_wl[1956] = wl_bus[37]; - assign sram_blwl_wl[1957] = wl_bus[37]; - assign sram_blwl_wl[1958] = wl_bus[37]; - assign sram_blwl_wl[1959] = wl_bus[37]; - assign sram_blwl_wl[1960] = wl_bus[37]; - assign sram_blwl_wl[1961] = wl_bus[37]; - assign sram_blwl_wl[1962] = wl_bus[37]; - assign sram_blwl_wl[1963] = wl_bus[37]; - assign sram_blwl_wl[1964] = wl_bus[37]; - assign sram_blwl_wl[1965] = wl_bus[37]; - assign sram_blwl_wl[1966] = wl_bus[37]; - assign sram_blwl_wl[1967] = wl_bus[37]; - assign sram_blwl_wl[1968] = wl_bus[37]; - assign sram_blwl_wl[1969] = wl_bus[37]; - assign sram_blwl_wl[1970] = wl_bus[37]; - assign sram_blwl_wl[1971] = wl_bus[37]; - assign sram_blwl_wl[1972] = wl_bus[37]; - assign sram_blwl_wl[1973] = wl_bus[37]; - assign sram_blwl_wl[1974] = wl_bus[37]; - assign sram_blwl_wl[1975] = wl_bus[37]; - assign sram_blwl_wl[1976] = wl_bus[38]; - assign sram_blwl_wl[1977] = wl_bus[38]; - assign sram_blwl_wl[1978] = wl_bus[38]; - assign sram_blwl_wl[1979] = wl_bus[38]; - assign sram_blwl_wl[1980] = wl_bus[38]; - assign sram_blwl_wl[1981] = wl_bus[38]; - assign sram_blwl_wl[1982] = wl_bus[38]; - assign sram_blwl_wl[1983] = wl_bus[38]; - assign sram_blwl_wl[1984] = wl_bus[38]; - assign sram_blwl_wl[1985] = wl_bus[38]; - assign sram_blwl_wl[1986] = wl_bus[38]; - assign sram_blwl_wl[1987] = wl_bus[38]; - assign sram_blwl_wl[1988] = wl_bus[38]; - assign sram_blwl_wl[1989] = wl_bus[38]; - assign sram_blwl_wl[1990] = wl_bus[38]; - assign sram_blwl_wl[1991] = wl_bus[38]; - assign sram_blwl_wl[1992] = wl_bus[38]; - assign sram_blwl_wl[1993] = wl_bus[38]; - assign sram_blwl_wl[1994] = wl_bus[38]; - assign sram_blwl_wl[1995] = wl_bus[38]; - assign sram_blwl_wl[1996] = wl_bus[38]; - assign sram_blwl_wl[1997] = wl_bus[38]; - assign sram_blwl_wl[1998] = wl_bus[38]; - assign sram_blwl_wl[1999] = wl_bus[38]; - assign sram_blwl_wl[2000] = wl_bus[38]; - assign sram_blwl_wl[2001] = wl_bus[38]; - assign sram_blwl_wl[2002] = wl_bus[38]; - assign sram_blwl_wl[2003] = wl_bus[38]; - assign sram_blwl_wl[2004] = wl_bus[38]; - assign sram_blwl_wl[2005] = wl_bus[38]; - assign sram_blwl_wl[2006] = wl_bus[38]; - assign sram_blwl_wl[2007] = wl_bus[38]; - assign sram_blwl_wl[2008] = wl_bus[38]; - assign sram_blwl_wl[2009] = wl_bus[38]; - assign sram_blwl_wl[2010] = wl_bus[38]; - assign sram_blwl_wl[2011] = wl_bus[38]; - assign sram_blwl_wl[2012] = wl_bus[38]; - assign sram_blwl_wl[2013] = wl_bus[38]; - assign sram_blwl_wl[2014] = wl_bus[38]; - assign sram_blwl_wl[2015] = wl_bus[38]; - assign sram_blwl_wl[2016] = wl_bus[38]; - assign sram_blwl_wl[2017] = wl_bus[38]; - assign sram_blwl_wl[2018] = wl_bus[38]; - assign sram_blwl_wl[2019] = wl_bus[38]; - assign sram_blwl_wl[2020] = wl_bus[38]; - assign sram_blwl_wl[2021] = wl_bus[38]; - assign sram_blwl_wl[2022] = wl_bus[38]; - assign sram_blwl_wl[2023] = wl_bus[38]; - assign sram_blwl_wl[2024] = wl_bus[38]; - assign sram_blwl_wl[2025] = wl_bus[38]; - assign sram_blwl_wl[2026] = wl_bus[38]; - assign sram_blwl_wl[2027] = wl_bus[38]; - assign sram_blwl_wl[2028] = wl_bus[39]; - assign sram_blwl_wl[2029] = wl_bus[39]; - assign sram_blwl_wl[2030] = wl_bus[39]; - assign sram_blwl_wl[2031] = wl_bus[39]; - assign sram_blwl_wl[2032] = wl_bus[39]; - assign sram_blwl_wl[2033] = wl_bus[39]; - assign sram_blwl_wl[2034] = wl_bus[39]; - assign sram_blwl_wl[2035] = wl_bus[39]; - assign sram_blwl_wl[2036] = wl_bus[39]; - assign sram_blwl_wl[2037] = wl_bus[39]; - assign sram_blwl_wl[2038] = wl_bus[39]; - assign sram_blwl_wl[2039] = wl_bus[39]; - assign sram_blwl_wl[2040] = wl_bus[39]; - assign sram_blwl_wl[2041] = wl_bus[39]; - assign sram_blwl_wl[2042] = wl_bus[39]; - assign sram_blwl_wl[2043] = wl_bus[39]; - assign sram_blwl_wl[2044] = wl_bus[39]; - assign sram_blwl_wl[2045] = wl_bus[39]; - assign sram_blwl_wl[2046] = wl_bus[39]; - assign sram_blwl_wl[2047] = wl_bus[39]; - assign sram_blwl_wl[2048] = wl_bus[39]; - assign sram_blwl_wl[2049] = wl_bus[39]; - assign sram_blwl_wl[2050] = wl_bus[39]; - assign sram_blwl_wl[2051] = wl_bus[39]; - assign sram_blwl_wl[2052] = wl_bus[39]; - assign sram_blwl_wl[2053] = wl_bus[39]; - assign sram_blwl_wl[2054] = wl_bus[39]; - assign sram_blwl_wl[2055] = wl_bus[39]; - assign sram_blwl_wl[2056] = wl_bus[39]; - assign sram_blwl_wl[2057] = wl_bus[39]; - assign sram_blwl_wl[2058] = wl_bus[39]; - assign sram_blwl_wl[2059] = wl_bus[39]; - assign sram_blwl_wl[2060] = wl_bus[39]; - assign sram_blwl_wl[2061] = wl_bus[39]; - assign sram_blwl_wl[2062] = wl_bus[39]; - assign sram_blwl_wl[2063] = wl_bus[39]; - assign sram_blwl_wl[2064] = wl_bus[39]; - assign sram_blwl_wl[2065] = wl_bus[39]; - assign sram_blwl_wl[2066] = wl_bus[39]; - assign sram_blwl_wl[2067] = wl_bus[39]; - assign sram_blwl_wl[2068] = wl_bus[39]; - assign sram_blwl_wl[2069] = wl_bus[39]; - assign sram_blwl_wl[2070] = wl_bus[39]; - assign sram_blwl_wl[2071] = wl_bus[39]; - assign sram_blwl_wl[2072] = wl_bus[39]; - assign sram_blwl_wl[2073] = wl_bus[39]; - assign sram_blwl_wl[2074] = wl_bus[39]; - assign sram_blwl_wl[2075] = wl_bus[39]; - assign sram_blwl_wl[2076] = wl_bus[39]; - assign sram_blwl_wl[2077] = wl_bus[39]; - assign sram_blwl_wl[2078] = wl_bus[39]; - assign sram_blwl_wl[2079] = wl_bus[39]; - assign sram_blwl_wl[2080] = wl_bus[40]; - assign sram_blwl_wl[2081] = wl_bus[40]; - assign sram_blwl_wl[2082] = wl_bus[40]; - assign sram_blwl_wl[2083] = wl_bus[40]; - assign sram_blwl_wl[2084] = wl_bus[40]; - assign sram_blwl_wl[2085] = wl_bus[40]; - assign sram_blwl_wl[2086] = wl_bus[40]; - assign sram_blwl_wl[2087] = wl_bus[40]; - assign sram_blwl_wl[2088] = wl_bus[40]; - assign sram_blwl_wl[2089] = wl_bus[40]; - assign sram_blwl_wl[2090] = wl_bus[40]; - assign sram_blwl_wl[2091] = wl_bus[40]; - assign sram_blwl_wl[2092] = wl_bus[40]; - assign sram_blwl_wl[2093] = wl_bus[40]; - assign sram_blwl_wl[2094] = wl_bus[40]; - assign sram_blwl_wl[2095] = wl_bus[40]; - assign sram_blwl_wl[2096] = wl_bus[40]; - assign sram_blwl_wl[2097] = wl_bus[40]; - assign sram_blwl_wl[2098] = wl_bus[40]; - assign sram_blwl_wl[2099] = wl_bus[40]; - assign sram_blwl_wl[2100] = wl_bus[40]; - assign sram_blwl_wl[2101] = wl_bus[40]; - assign sram_blwl_wl[2102] = wl_bus[40]; - assign sram_blwl_wl[2103] = wl_bus[40]; - assign sram_blwl_wl[2104] = wl_bus[40]; - assign sram_blwl_wl[2105] = wl_bus[40]; - assign sram_blwl_wl[2106] = wl_bus[40]; - assign sram_blwl_wl[2107] = wl_bus[40]; - assign sram_blwl_wl[2108] = wl_bus[40]; - assign sram_blwl_wl[2109] = wl_bus[40]; - assign sram_blwl_wl[2110] = wl_bus[40]; - assign sram_blwl_wl[2111] = wl_bus[40]; - assign sram_blwl_wl[2112] = wl_bus[40]; - assign sram_blwl_wl[2113] = wl_bus[40]; - assign sram_blwl_wl[2114] = wl_bus[40]; - assign sram_blwl_wl[2115] = wl_bus[40]; - assign sram_blwl_wl[2116] = wl_bus[40]; - assign sram_blwl_wl[2117] = wl_bus[40]; - assign sram_blwl_wl[2118] = wl_bus[40]; - assign sram_blwl_wl[2119] = wl_bus[40]; - assign sram_blwl_wl[2120] = wl_bus[40]; - assign sram_blwl_wl[2121] = wl_bus[40]; - assign sram_blwl_wl[2122] = wl_bus[40]; - assign sram_blwl_wl[2123] = wl_bus[40]; - assign sram_blwl_wl[2124] = wl_bus[40]; - assign sram_blwl_wl[2125] = wl_bus[40]; - assign sram_blwl_wl[2126] = wl_bus[40]; - assign sram_blwl_wl[2127] = wl_bus[40]; - assign sram_blwl_wl[2128] = wl_bus[40]; - assign sram_blwl_wl[2129] = wl_bus[40]; - assign sram_blwl_wl[2130] = wl_bus[40]; - assign sram_blwl_wl[2131] = wl_bus[40]; - assign sram_blwl_wl[2132] = wl_bus[41]; - assign sram_blwl_wl[2133] = wl_bus[41]; - assign sram_blwl_wl[2134] = wl_bus[41]; - assign sram_blwl_wl[2135] = wl_bus[41]; - assign sram_blwl_wl[2136] = wl_bus[41]; - assign sram_blwl_wl[2137] = wl_bus[41]; - assign sram_blwl_wl[2138] = wl_bus[41]; - assign sram_blwl_wl[2139] = wl_bus[41]; - assign sram_blwl_wl[2140] = wl_bus[41]; - assign sram_blwl_wl[2141] = wl_bus[41]; - assign sram_blwl_wl[2142] = wl_bus[41]; - assign sram_blwl_wl[2143] = wl_bus[41]; - assign sram_blwl_wl[2144] = wl_bus[41]; - assign sram_blwl_wl[2145] = wl_bus[41]; - assign sram_blwl_wl[2146] = wl_bus[41]; - assign sram_blwl_wl[2147] = wl_bus[41]; - assign sram_blwl_wl[2148] = wl_bus[41]; - assign sram_blwl_wl[2149] = wl_bus[41]; - assign sram_blwl_wl[2150] = wl_bus[41]; - assign sram_blwl_wl[2151] = wl_bus[41]; - assign sram_blwl_wl[2152] = wl_bus[41]; - assign sram_blwl_wl[2153] = wl_bus[41]; - assign sram_blwl_wl[2154] = wl_bus[41]; - assign sram_blwl_wl[2155] = wl_bus[41]; - assign sram_blwl_wl[2156] = wl_bus[41]; - assign sram_blwl_wl[2157] = wl_bus[41]; - assign sram_blwl_wl[2158] = wl_bus[41]; - assign sram_blwl_wl[2159] = wl_bus[41]; - assign sram_blwl_wl[2160] = wl_bus[41]; - assign sram_blwl_wl[2161] = wl_bus[41]; - assign sram_blwl_wl[2162] = wl_bus[41]; - assign sram_blwl_wl[2163] = wl_bus[41]; - assign sram_blwl_wl[2164] = wl_bus[41]; - assign sram_blwl_wl[2165] = wl_bus[41]; - assign sram_blwl_wl[2166] = wl_bus[41]; - assign sram_blwl_wl[2167] = wl_bus[41]; - assign sram_blwl_wl[2168] = wl_bus[41]; - assign sram_blwl_wl[2169] = wl_bus[41]; - assign sram_blwl_wl[2170] = wl_bus[41]; - assign sram_blwl_wl[2171] = wl_bus[41]; - assign sram_blwl_wl[2172] = wl_bus[41]; - assign sram_blwl_wl[2173] = wl_bus[41]; - assign sram_blwl_wl[2174] = wl_bus[41]; - assign sram_blwl_wl[2175] = wl_bus[41]; - assign sram_blwl_wl[2176] = wl_bus[41]; - assign sram_blwl_wl[2177] = wl_bus[41]; - assign sram_blwl_wl[2178] = wl_bus[41]; - assign sram_blwl_wl[2179] = wl_bus[41]; - assign sram_blwl_wl[2180] = wl_bus[41]; - assign sram_blwl_wl[2181] = wl_bus[41]; - assign sram_blwl_wl[2182] = wl_bus[41]; - assign sram_blwl_wl[2183] = wl_bus[41]; - assign sram_blwl_wl[2184] = wl_bus[42]; - assign sram_blwl_wl[2185] = wl_bus[42]; - assign sram_blwl_wl[2186] = wl_bus[42]; - assign sram_blwl_wl[2187] = wl_bus[42]; - assign sram_blwl_wl[2188] = wl_bus[42]; - assign sram_blwl_wl[2189] = wl_bus[42]; - assign sram_blwl_wl[2190] = wl_bus[42]; - assign sram_blwl_wl[2191] = wl_bus[42]; - assign sram_blwl_wl[2192] = wl_bus[42]; - assign sram_blwl_wl[2193] = wl_bus[42]; - assign sram_blwl_wl[2194] = wl_bus[42]; - assign sram_blwl_wl[2195] = wl_bus[42]; - assign sram_blwl_wl[2196] = wl_bus[42]; - assign sram_blwl_wl[2197] = wl_bus[42]; - assign sram_blwl_wl[2198] = wl_bus[42]; - assign sram_blwl_wl[2199] = wl_bus[42]; - assign sram_blwl_wl[2200] = wl_bus[42]; - assign sram_blwl_wl[2201] = wl_bus[42]; - assign sram_blwl_wl[2202] = wl_bus[42]; - assign sram_blwl_wl[2203] = wl_bus[42]; - assign sram_blwl_wl[2204] = wl_bus[42]; - assign sram_blwl_wl[2205] = wl_bus[42]; - assign sram_blwl_wl[2206] = wl_bus[42]; - assign sram_blwl_wl[2207] = wl_bus[42]; - assign sram_blwl_wl[2208] = wl_bus[42]; - assign sram_blwl_wl[2209] = wl_bus[42]; - assign sram_blwl_wl[2210] = wl_bus[42]; - assign sram_blwl_wl[2211] = wl_bus[42]; - assign sram_blwl_wl[2212] = wl_bus[42]; - assign sram_blwl_wl[2213] = wl_bus[42]; - assign sram_blwl_wl[2214] = wl_bus[42]; - assign sram_blwl_wl[2215] = wl_bus[42]; - assign sram_blwl_wl[2216] = wl_bus[42]; - assign sram_blwl_wl[2217] = wl_bus[42]; - assign sram_blwl_wl[2218] = wl_bus[42]; - assign sram_blwl_wl[2219] = wl_bus[42]; - assign sram_blwl_wl[2220] = wl_bus[42]; - assign sram_blwl_wl[2221] = wl_bus[42]; - assign sram_blwl_wl[2222] = wl_bus[42]; - assign sram_blwl_wl[2223] = wl_bus[42]; - assign sram_blwl_wl[2224] = wl_bus[42]; - assign sram_blwl_wl[2225] = wl_bus[42]; - assign sram_blwl_wl[2226] = wl_bus[42]; - assign sram_blwl_wl[2227] = wl_bus[42]; - assign sram_blwl_wl[2228] = wl_bus[42]; - assign sram_blwl_wl[2229] = wl_bus[42]; - assign sram_blwl_wl[2230] = wl_bus[42]; - assign sram_blwl_wl[2231] = wl_bus[42]; - assign sram_blwl_wl[2232] = wl_bus[42]; - assign sram_blwl_wl[2233] = wl_bus[42]; - assign sram_blwl_wl[2234] = wl_bus[42]; - assign sram_blwl_wl[2235] = wl_bus[42]; - assign sram_blwl_wl[2236] = wl_bus[43]; - assign sram_blwl_wl[2237] = wl_bus[43]; - assign sram_blwl_wl[2238] = wl_bus[43]; - assign sram_blwl_wl[2239] = wl_bus[43]; - assign sram_blwl_wl[2240] = wl_bus[43]; - assign sram_blwl_wl[2241] = wl_bus[43]; - assign sram_blwl_wl[2242] = wl_bus[43]; - assign sram_blwl_wl[2243] = wl_bus[43]; - assign sram_blwl_wl[2244] = wl_bus[43]; - assign sram_blwl_wl[2245] = wl_bus[43]; - assign sram_blwl_wl[2246] = wl_bus[43]; - assign sram_blwl_wl[2247] = wl_bus[43]; - assign sram_blwl_wl[2248] = wl_bus[43]; - assign sram_blwl_wl[2249] = wl_bus[43]; - assign sram_blwl_wl[2250] = wl_bus[43]; - assign sram_blwl_wl[2251] = wl_bus[43]; - assign sram_blwl_wl[2252] = wl_bus[43]; - assign sram_blwl_wl[2253] = wl_bus[43]; - assign sram_blwl_wl[2254] = wl_bus[43]; - assign sram_blwl_wl[2255] = wl_bus[43]; - assign sram_blwl_wl[2256] = wl_bus[43]; - assign sram_blwl_wl[2257] = wl_bus[43]; - assign sram_blwl_wl[2258] = wl_bus[43]; - assign sram_blwl_wl[2259] = wl_bus[43]; - assign sram_blwl_wl[2260] = wl_bus[43]; - assign sram_blwl_wl[2261] = wl_bus[43]; - assign sram_blwl_wl[2262] = wl_bus[43]; - assign sram_blwl_wl[2263] = wl_bus[43]; - assign sram_blwl_wl[2264] = wl_bus[43]; - assign sram_blwl_wl[2265] = wl_bus[43]; - assign sram_blwl_wl[2266] = wl_bus[43]; - assign sram_blwl_wl[2267] = wl_bus[43]; - assign sram_blwl_wl[2268] = wl_bus[43]; - assign sram_blwl_wl[2269] = wl_bus[43]; - assign sram_blwl_wl[2270] = wl_bus[43]; - assign sram_blwl_wl[2271] = wl_bus[43]; - assign sram_blwl_wl[2272] = wl_bus[43]; - assign sram_blwl_wl[2273] = wl_bus[43]; - assign sram_blwl_wl[2274] = wl_bus[43]; - assign sram_blwl_wl[2275] = wl_bus[43]; - assign sram_blwl_wl[2276] = wl_bus[43]; - assign sram_blwl_wl[2277] = wl_bus[43]; - assign sram_blwl_wl[2278] = wl_bus[43]; - assign sram_blwl_wl[2279] = wl_bus[43]; - assign sram_blwl_wl[2280] = wl_bus[43]; - assign sram_blwl_wl[2281] = wl_bus[43]; - assign sram_blwl_wl[2282] = wl_bus[43]; - assign sram_blwl_wl[2283] = wl_bus[43]; - assign sram_blwl_wl[2284] = wl_bus[43]; - assign sram_blwl_wl[2285] = wl_bus[43]; - assign sram_blwl_wl[2286] = wl_bus[43]; - assign sram_blwl_wl[2287] = wl_bus[43]; - assign sram_blwl_wl[2288] = wl_bus[44]; - assign sram_blwl_wl[2289] = wl_bus[44]; - assign sram_blwl_wl[2290] = wl_bus[44]; - assign sram_blwl_wl[2291] = wl_bus[44]; - assign sram_blwl_wl[2292] = wl_bus[44]; - assign sram_blwl_wl[2293] = wl_bus[44]; - assign sram_blwl_wl[2294] = wl_bus[44]; - assign sram_blwl_wl[2295] = wl_bus[44]; - assign sram_blwl_wl[2296] = wl_bus[44]; - assign sram_blwl_wl[2297] = wl_bus[44]; - assign sram_blwl_wl[2298] = wl_bus[44]; - assign sram_blwl_wl[2299] = wl_bus[44]; - assign sram_blwl_wl[2300] = wl_bus[44]; - assign sram_blwl_wl[2301] = wl_bus[44]; - assign sram_blwl_wl[2302] = wl_bus[44]; - assign sram_blwl_wl[2303] = wl_bus[44]; - assign sram_blwl_wl[2304] = wl_bus[44]; - assign sram_blwl_wl[2305] = wl_bus[44]; - assign sram_blwl_wl[2306] = wl_bus[44]; - assign sram_blwl_wl[2307] = wl_bus[44]; - assign sram_blwl_wl[2308] = wl_bus[44]; - assign sram_blwl_wl[2309] = wl_bus[44]; - assign sram_blwl_wl[2310] = wl_bus[44]; - assign sram_blwl_wl[2311] = wl_bus[44]; - assign sram_blwl_wl[2312] = wl_bus[44]; - assign sram_blwl_wl[2313] = wl_bus[44]; - assign sram_blwl_wl[2314] = wl_bus[44]; - assign sram_blwl_wl[2315] = wl_bus[44]; - assign sram_blwl_wl[2316] = wl_bus[44]; - assign sram_blwl_wl[2317] = wl_bus[44]; - assign sram_blwl_wl[2318] = wl_bus[44]; - assign sram_blwl_wl[2319] = wl_bus[44]; - assign sram_blwl_wl[2320] = wl_bus[44]; - assign sram_blwl_wl[2321] = wl_bus[44]; - assign sram_blwl_wl[2322] = wl_bus[44]; - assign sram_blwl_wl[2323] = wl_bus[44]; - assign sram_blwl_wl[2324] = wl_bus[44]; - assign sram_blwl_wl[2325] = wl_bus[44]; - assign sram_blwl_wl[2326] = wl_bus[44]; - assign sram_blwl_wl[2327] = wl_bus[44]; - assign sram_blwl_wl[2328] = wl_bus[44]; - assign sram_blwl_wl[2329] = wl_bus[44]; - assign sram_blwl_wl[2330] = wl_bus[44]; - assign sram_blwl_wl[2331] = wl_bus[44]; - assign sram_blwl_wl[2332] = wl_bus[44]; - assign sram_blwl_wl[2333] = wl_bus[44]; - assign sram_blwl_wl[2334] = wl_bus[44]; - assign sram_blwl_wl[2335] = wl_bus[44]; - assign sram_blwl_wl[2336] = wl_bus[44]; - assign sram_blwl_wl[2337] = wl_bus[44]; - assign sram_blwl_wl[2338] = wl_bus[44]; - assign sram_blwl_wl[2339] = wl_bus[44]; - assign sram_blwl_wl[2340] = wl_bus[45]; - assign sram_blwl_wl[2341] = wl_bus[45]; - assign sram_blwl_wl[2342] = wl_bus[45]; - assign sram_blwl_wl[2343] = wl_bus[45]; - assign sram_blwl_wl[2344] = wl_bus[45]; - assign sram_blwl_wl[2345] = wl_bus[45]; - assign sram_blwl_wl[2346] = wl_bus[45]; - assign sram_blwl_wl[2347] = wl_bus[45]; - assign sram_blwl_wl[2348] = wl_bus[45]; - assign sram_blwl_wl[2349] = wl_bus[45]; - assign sram_blwl_wl[2350] = wl_bus[45]; - assign sram_blwl_wl[2351] = wl_bus[45]; - assign sram_blwl_wl[2352] = wl_bus[45]; - assign sram_blwl_wl[2353] = wl_bus[45]; - assign sram_blwl_wl[2354] = wl_bus[45]; - assign sram_blwl_wl[2355] = wl_bus[45]; - assign sram_blwl_wl[2356] = wl_bus[45]; - assign sram_blwl_wl[2357] = wl_bus[45]; - assign sram_blwl_wl[2358] = wl_bus[45]; - assign sram_blwl_wl[2359] = wl_bus[45]; - assign sram_blwl_wl[2360] = wl_bus[45]; - assign sram_blwl_wl[2361] = wl_bus[45]; - assign sram_blwl_wl[2362] = wl_bus[45]; - assign sram_blwl_wl[2363] = wl_bus[45]; - assign sram_blwl_wl[2364] = wl_bus[45]; - assign sram_blwl_wl[2365] = wl_bus[45]; - assign sram_blwl_wl[2366] = wl_bus[45]; - assign sram_blwl_wl[2367] = wl_bus[45]; - assign sram_blwl_wl[2368] = wl_bus[45]; - assign sram_blwl_wl[2369] = wl_bus[45]; - assign sram_blwl_wl[2370] = wl_bus[45]; - assign sram_blwl_wl[2371] = wl_bus[45]; - assign sram_blwl_wl[2372] = wl_bus[45]; - assign sram_blwl_wl[2373] = wl_bus[45]; - assign sram_blwl_wl[2374] = wl_bus[45]; - assign sram_blwl_wl[2375] = wl_bus[45]; - assign sram_blwl_wl[2376] = wl_bus[45]; - assign sram_blwl_wl[2377] = wl_bus[45]; - assign sram_blwl_wl[2378] = wl_bus[45]; - assign sram_blwl_wl[2379] = wl_bus[45]; - assign sram_blwl_wl[2380] = wl_bus[45]; - assign sram_blwl_wl[2381] = wl_bus[45]; - assign sram_blwl_wl[2382] = wl_bus[45]; - assign sram_blwl_wl[2383] = wl_bus[45]; - assign sram_blwl_wl[2384] = wl_bus[45]; - assign sram_blwl_wl[2385] = wl_bus[45]; - assign sram_blwl_wl[2386] = wl_bus[45]; - assign sram_blwl_wl[2387] = wl_bus[45]; - assign sram_blwl_wl[2388] = wl_bus[45]; - assign sram_blwl_wl[2389] = wl_bus[45]; - assign sram_blwl_wl[2390] = wl_bus[45]; - assign sram_blwl_wl[2391] = wl_bus[45]; - assign sram_blwl_wl[2392] = wl_bus[46]; - assign sram_blwl_wl[2393] = wl_bus[46]; - assign sram_blwl_wl[2394] = wl_bus[46]; - assign sram_blwl_wl[2395] = wl_bus[46]; - assign sram_blwl_wl[2396] = wl_bus[46]; - assign sram_blwl_wl[2397] = wl_bus[46]; - assign sram_blwl_wl[2398] = wl_bus[46]; - assign sram_blwl_wl[2399] = wl_bus[46]; - assign sram_blwl_wl[2400] = wl_bus[46]; - assign sram_blwl_wl[2401] = wl_bus[46]; - assign sram_blwl_wl[2402] = wl_bus[46]; - assign sram_blwl_wl[2403] = wl_bus[46]; - assign sram_blwl_wl[2404] = wl_bus[46]; - assign sram_blwl_wl[2405] = wl_bus[46]; - assign sram_blwl_wl[2406] = wl_bus[46]; - assign sram_blwl_wl[2407] = wl_bus[46]; - assign sram_blwl_wl[2408] = wl_bus[46]; - assign sram_blwl_wl[2409] = wl_bus[46]; - assign sram_blwl_wl[2410] = wl_bus[46]; - assign sram_blwl_wl[2411] = wl_bus[46]; - assign sram_blwl_wl[2412] = wl_bus[46]; - assign sram_blwl_wl[2413] = wl_bus[46]; - assign sram_blwl_wl[2414] = wl_bus[46]; - assign sram_blwl_wl[2415] = wl_bus[46]; - assign sram_blwl_wl[2416] = wl_bus[46]; - assign sram_blwl_wl[2417] = wl_bus[46]; - assign sram_blwl_wl[2418] = wl_bus[46]; - assign sram_blwl_wl[2419] = wl_bus[46]; - assign sram_blwl_wl[2420] = wl_bus[46]; - assign sram_blwl_wl[2421] = wl_bus[46]; - assign sram_blwl_wl[2422] = wl_bus[46]; - assign sram_blwl_wl[2423] = wl_bus[46]; - assign sram_blwl_wl[2424] = wl_bus[46]; - assign sram_blwl_wl[2425] = wl_bus[46]; - assign sram_blwl_wl[2426] = wl_bus[46]; - assign sram_blwl_wl[2427] = wl_bus[46]; - assign sram_blwl_wl[2428] = wl_bus[46]; - assign sram_blwl_wl[2429] = wl_bus[46]; - assign sram_blwl_wl[2430] = wl_bus[46]; - assign sram_blwl_wl[2431] = wl_bus[46]; - assign sram_blwl_wl[2432] = wl_bus[46]; - assign sram_blwl_wl[2433] = wl_bus[46]; - assign sram_blwl_wl[2434] = wl_bus[46]; - assign sram_blwl_wl[2435] = wl_bus[46]; - assign sram_blwl_wl[2436] = wl_bus[46]; - assign sram_blwl_wl[2437] = wl_bus[46]; - assign sram_blwl_wl[2438] = wl_bus[46]; - assign sram_blwl_wl[2439] = wl_bus[46]; - assign sram_blwl_wl[2440] = wl_bus[46]; - assign sram_blwl_wl[2441] = wl_bus[46]; - assign sram_blwl_wl[2442] = wl_bus[46]; - assign sram_blwl_wl[2443] = wl_bus[46]; - assign sram_blwl_wl[2444] = wl_bus[47]; - assign sram_blwl_wl[2445] = wl_bus[47]; - assign sram_blwl_wl[2446] = wl_bus[47]; - assign sram_blwl_wl[2447] = wl_bus[47]; - assign sram_blwl_wl[2448] = wl_bus[47]; - assign sram_blwl_wl[2449] = wl_bus[47]; - assign sram_blwl_wl[2450] = wl_bus[47]; - assign sram_blwl_wl[2451] = wl_bus[47]; - assign sram_blwl_wl[2452] = wl_bus[47]; - assign sram_blwl_wl[2453] = wl_bus[47]; - assign sram_blwl_wl[2454] = wl_bus[47]; - assign sram_blwl_wl[2455] = wl_bus[47]; - assign sram_blwl_wl[2456] = wl_bus[47]; - assign sram_blwl_wl[2457] = wl_bus[47]; - assign sram_blwl_wl[2458] = wl_bus[47]; - assign sram_blwl_wl[2459] = wl_bus[47]; - assign sram_blwl_wl[2460] = wl_bus[47]; - assign sram_blwl_wl[2461] = wl_bus[47]; - assign sram_blwl_wl[2462] = wl_bus[47]; - assign sram_blwl_wl[2463] = wl_bus[47]; - assign sram_blwl_wl[2464] = wl_bus[47]; - assign sram_blwl_wl[2465] = wl_bus[47]; - assign sram_blwl_wl[2466] = wl_bus[47]; - assign sram_blwl_wl[2467] = wl_bus[47]; - assign sram_blwl_wl[2468] = wl_bus[47]; - assign sram_blwl_wl[2469] = wl_bus[47]; - assign sram_blwl_wl[2470] = wl_bus[47]; - assign sram_blwl_wl[2471] = wl_bus[47]; - assign sram_blwl_wl[2472] = wl_bus[47]; - assign sram_blwl_wl[2473] = wl_bus[47]; - assign sram_blwl_wl[2474] = wl_bus[47]; - assign sram_blwl_wl[2475] = wl_bus[47]; - assign sram_blwl_wl[2476] = wl_bus[47]; - assign sram_blwl_wl[2477] = wl_bus[47]; - assign sram_blwl_wl[2478] = wl_bus[47]; - assign sram_blwl_wl[2479] = wl_bus[47]; - assign sram_blwl_wl[2480] = wl_bus[47]; - assign sram_blwl_wl[2481] = wl_bus[47]; - assign sram_blwl_wl[2482] = wl_bus[47]; - assign sram_blwl_wl[2483] = wl_bus[47]; - assign sram_blwl_wl[2484] = wl_bus[47]; - assign sram_blwl_wl[2485] = wl_bus[47]; - assign sram_blwl_wl[2486] = wl_bus[47]; - assign sram_blwl_wl[2487] = wl_bus[47]; - assign sram_blwl_wl[2488] = wl_bus[47]; - assign sram_blwl_wl[2489] = wl_bus[47]; - assign sram_blwl_wl[2490] = wl_bus[47]; - assign sram_blwl_wl[2491] = wl_bus[47]; - assign sram_blwl_wl[2492] = wl_bus[47]; - assign sram_blwl_wl[2493] = wl_bus[47]; - assign sram_blwl_wl[2494] = wl_bus[47]; - assign sram_blwl_wl[2495] = wl_bus[47]; - assign sram_blwl_wl[2496] = wl_bus[48]; - assign sram_blwl_wl[2497] = wl_bus[48]; - assign sram_blwl_wl[2498] = wl_bus[48]; - assign sram_blwl_wl[2499] = wl_bus[48]; - assign sram_blwl_wl[2500] = wl_bus[48]; - assign sram_blwl_wl[2501] = wl_bus[48]; - assign sram_blwl_wl[2502] = wl_bus[48]; - assign sram_blwl_wl[2503] = wl_bus[48]; - assign sram_blwl_wl[2504] = wl_bus[48]; - assign sram_blwl_wl[2505] = wl_bus[48]; - assign sram_blwl_wl[2506] = wl_bus[48]; - assign sram_blwl_wl[2507] = wl_bus[48]; - assign sram_blwl_wl[2508] = wl_bus[48]; - assign sram_blwl_wl[2509] = wl_bus[48]; - assign sram_blwl_wl[2510] = wl_bus[48]; - assign sram_blwl_wl[2511] = wl_bus[48]; - assign sram_blwl_wl[2512] = wl_bus[48]; - assign sram_blwl_wl[2513] = wl_bus[48]; - assign sram_blwl_wl[2514] = wl_bus[48]; - assign sram_blwl_wl[2515] = wl_bus[48]; - assign sram_blwl_wl[2516] = wl_bus[48]; - assign sram_blwl_wl[2517] = wl_bus[48]; - assign sram_blwl_wl[2518] = wl_bus[48]; - assign sram_blwl_wl[2519] = wl_bus[48]; - assign sram_blwl_wl[2520] = wl_bus[48]; - assign sram_blwl_wl[2521] = wl_bus[48]; - assign sram_blwl_wl[2522] = wl_bus[48]; - assign sram_blwl_wl[2523] = wl_bus[48]; - assign sram_blwl_wl[2524] = wl_bus[48]; - assign sram_blwl_wl[2525] = wl_bus[48]; - assign sram_blwl_wl[2526] = wl_bus[48]; - assign sram_blwl_wl[2527] = wl_bus[48]; - assign sram_blwl_wl[2528] = wl_bus[48]; - assign sram_blwl_wl[2529] = wl_bus[48]; - assign sram_blwl_wl[2530] = wl_bus[48]; - assign sram_blwl_wl[2531] = wl_bus[48]; - assign sram_blwl_wl[2532] = wl_bus[48]; - assign sram_blwl_wl[2533] = wl_bus[48]; - assign sram_blwl_wl[2534] = wl_bus[48]; - assign sram_blwl_wl[2535] = wl_bus[48]; - assign sram_blwl_wl[2536] = wl_bus[48]; - assign sram_blwl_wl[2537] = wl_bus[48]; - assign sram_blwl_wl[2538] = wl_bus[48]; - assign sram_blwl_wl[2539] = wl_bus[48]; - assign sram_blwl_wl[2540] = wl_bus[48]; - assign sram_blwl_wl[2541] = wl_bus[48]; - assign sram_blwl_wl[2542] = wl_bus[48]; - assign sram_blwl_wl[2543] = wl_bus[48]; - assign sram_blwl_wl[2544] = wl_bus[48]; - assign sram_blwl_wl[2545] = wl_bus[48]; - assign sram_blwl_wl[2546] = wl_bus[48]; - assign sram_blwl_wl[2547] = wl_bus[48]; - assign sram_blwl_wl[2548] = wl_bus[49]; - assign sram_blwl_wl[2549] = wl_bus[49]; - assign sram_blwl_wl[2550] = wl_bus[49]; - assign sram_blwl_wl[2551] = wl_bus[49]; - assign sram_blwl_wl[2552] = wl_bus[49]; - assign sram_blwl_wl[2553] = wl_bus[49]; - assign sram_blwl_wl[2554] = wl_bus[49]; - assign sram_blwl_wl[2555] = wl_bus[49]; - assign sram_blwl_wl[2556] = wl_bus[49]; - assign sram_blwl_wl[2557] = wl_bus[49]; - assign sram_blwl_wl[2558] = wl_bus[49]; - assign sram_blwl_wl[2559] = wl_bus[49]; - assign sram_blwl_wl[2560] = wl_bus[49]; - assign sram_blwl_wl[2561] = wl_bus[49]; - assign sram_blwl_wl[2562] = wl_bus[49]; - assign sram_blwl_wl[2563] = wl_bus[49]; - assign sram_blwl_wl[2564] = wl_bus[49]; - assign sram_blwl_wl[2565] = wl_bus[49]; - assign sram_blwl_wl[2566] = wl_bus[49]; - assign sram_blwl_wl[2567] = wl_bus[49]; - assign sram_blwl_wl[2568] = wl_bus[49]; - assign sram_blwl_wl[2569] = wl_bus[49]; - assign sram_blwl_wl[2570] = wl_bus[49]; - assign sram_blwl_wl[2571] = wl_bus[49]; - assign sram_blwl_wl[2572] = wl_bus[49]; - assign sram_blwl_wl[2573] = wl_bus[49]; - assign sram_blwl_wl[2574] = wl_bus[49]; - assign sram_blwl_wl[2575] = wl_bus[49]; - assign sram_blwl_wl[2576] = wl_bus[49]; - assign sram_blwl_wl[2577] = wl_bus[49]; - assign sram_blwl_wl[2578] = wl_bus[49]; - assign sram_blwl_wl[2579] = wl_bus[49]; - assign sram_blwl_wl[2580] = wl_bus[49]; - assign sram_blwl_wl[2581] = wl_bus[49]; - assign sram_blwl_wl[2582] = wl_bus[49]; - assign sram_blwl_wl[2583] = wl_bus[49]; - assign sram_blwl_wl[2584] = wl_bus[49]; - assign sram_blwl_wl[2585] = wl_bus[49]; - assign sram_blwl_wl[2586] = wl_bus[49]; - assign sram_blwl_wl[2587] = wl_bus[49]; - assign sram_blwl_wl[2588] = wl_bus[49]; - assign sram_blwl_wl[2589] = wl_bus[49]; - assign sram_blwl_wl[2590] = wl_bus[49]; - assign sram_blwl_wl[2591] = wl_bus[49]; - assign sram_blwl_wl[2592] = wl_bus[49]; - assign sram_blwl_wl[2593] = wl_bus[49]; - assign sram_blwl_wl[2594] = wl_bus[49]; - assign sram_blwl_wl[2595] = wl_bus[49]; - assign sram_blwl_wl[2596] = wl_bus[49]; - assign sram_blwl_wl[2597] = wl_bus[49]; - assign sram_blwl_wl[2598] = wl_bus[49]; - assign sram_blwl_wl[2599] = wl_bus[49]; - assign sram_blwl_wl[2600] = wl_bus[50]; - assign sram_blwl_wl[2601] = wl_bus[50]; - assign sram_blwl_wl[2602] = wl_bus[50]; - assign sram_blwl_wl[2603] = wl_bus[50]; - assign sram_blwl_wl[2604] = wl_bus[50]; - assign sram_blwl_wl[2605] = wl_bus[50]; - assign sram_blwl_wl[2606] = wl_bus[50]; - assign sram_blwl_wl[2607] = wl_bus[50]; - assign sram_blwl_wl[2608] = wl_bus[50]; - assign sram_blwl_wl[2609] = wl_bus[50]; - assign sram_blwl_wl[2610] = wl_bus[50]; - assign sram_blwl_wl[2611] = wl_bus[50]; - assign sram_blwl_wl[2612] = wl_bus[50]; - assign sram_blwl_wl[2613] = wl_bus[50]; - assign sram_blwl_wl[2614] = wl_bus[50]; - assign sram_blwl_wl[2615] = wl_bus[50]; - assign sram_blwl_wl[2616] = wl_bus[50]; - assign sram_blwl_wl[2617] = wl_bus[50]; - assign sram_blwl_wl[2618] = wl_bus[50]; - assign sram_blwl_wl[2619] = wl_bus[50]; - assign sram_blwl_wl[2620] = wl_bus[50]; - assign sram_blwl_wl[2621] = wl_bus[50]; - assign sram_blwl_wl[2622] = wl_bus[50]; - assign sram_blwl_wl[2623] = wl_bus[50]; - assign sram_blwl_wl[2624] = wl_bus[50]; - assign sram_blwl_wl[2625] = wl_bus[50]; - assign sram_blwl_wl[2626] = wl_bus[50]; - assign sram_blwl_wl[2627] = wl_bus[50]; - assign sram_blwl_wl[2628] = wl_bus[50]; - assign sram_blwl_wl[2629] = wl_bus[50]; - assign sram_blwl_wl[2630] = wl_bus[50]; - assign sram_blwl_wl[2631] = wl_bus[50]; - assign sram_blwl_wl[2632] = wl_bus[50]; - assign sram_blwl_wl[2633] = wl_bus[50]; - assign sram_blwl_wl[2634] = wl_bus[50]; - assign sram_blwl_wl[2635] = wl_bus[50]; - assign sram_blwl_wl[2636] = wl_bus[50]; - assign sram_blwl_wl[2637] = wl_bus[50]; - assign sram_blwl_wl[2638] = wl_bus[50]; - assign sram_blwl_wl[2639] = wl_bus[50]; - assign sram_blwl_wl[2640] = wl_bus[50]; - assign sram_blwl_wl[2641] = wl_bus[50]; - assign sram_blwl_wl[2642] = wl_bus[50]; - assign sram_blwl_wl[2643] = wl_bus[50]; - assign sram_blwl_wl[2644] = wl_bus[50]; - assign sram_blwl_wl[2645] = wl_bus[50]; - assign sram_blwl_wl[2646] = wl_bus[50]; - assign sram_blwl_wl[2647] = wl_bus[50]; - assign sram_blwl_wl[2648] = wl_bus[50]; - assign sram_blwl_wl[2649] = wl_bus[50]; - assign sram_blwl_wl[2650] = wl_bus[50]; - assign sram_blwl_wl[2651] = wl_bus[50]; - assign sram_blwl_wl[2652] = wl_bus[51]; - assign sram_blwl_wl[2653] = wl_bus[51]; - assign sram_blwl_wl[2654] = wl_bus[51]; - assign sram_blwl_wl[2655] = wl_bus[51]; - assign sram_blwl_wl[2656] = wl_bus[51]; - assign sram_blwl_wl[2657] = wl_bus[51]; -//----- BEGIN Call Grid[1][1] module ----- -grid_1__1_ grid_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - grid_1__1__pin_0__0__0_, - grid_1__1__pin_0__0__4_, - grid_1__1__pin_0__0__8_, - grid_1__1__pin_0__0__12_, - grid_1__1__pin_0__0__16_, - grid_1__1__pin_0__0__20_, - grid_1__1__pin_0__0__24_, - grid_1__1__pin_0__0__28_, - grid_1__1__pin_0__0__32_, - grid_1__1__pin_0__0__36_, - grid_1__1__pin_0__0__40_, - grid_1__1__pin_0__0__44_, - grid_1__1__pin_0__0__48_, - grid_1__1__pin_0__1__1_, - grid_1__1__pin_0__1__5_, - grid_1__1__pin_0__1__9_, - grid_1__1__pin_0__1__13_, - grid_1__1__pin_0__1__17_, - grid_1__1__pin_0__1__21_, - grid_1__1__pin_0__1__25_, - grid_1__1__pin_0__1__29_, - grid_1__1__pin_0__1__33_, - grid_1__1__pin_0__1__37_, - grid_1__1__pin_0__1__41_, - grid_1__1__pin_0__1__45_, - grid_1__1__pin_0__1__49_, - grid_1__1__pin_0__2__2_, - grid_1__1__pin_0__2__6_, - grid_1__1__pin_0__2__10_, - grid_1__1__pin_0__2__14_, - grid_1__1__pin_0__2__18_, - grid_1__1__pin_0__2__22_, - grid_1__1__pin_0__2__26_, - grid_1__1__pin_0__2__30_, - grid_1__1__pin_0__2__34_, - grid_1__1__pin_0__2__38_, - grid_1__1__pin_0__2__42_, - grid_1__1__pin_0__2__46_, - grid_1__1__pin_0__2__50_, - grid_1__1__pin_0__3__3_, - grid_1__1__pin_0__3__7_, - grid_1__1__pin_0__3__11_, - grid_1__1__pin_0__3__15_, - grid_1__1__pin_0__3__19_, - grid_1__1__pin_0__3__23_, - grid_1__1__pin_0__3__27_, - grid_1__1__pin_0__3__31_, - grid_1__1__pin_0__3__35_, - grid_1__1__pin_0__3__39_, - grid_1__1__pin_0__3__43_, - grid_1__1__pin_0__3__47_, -sram_blwl_bl[1016:2625] , -sram_blwl_wl[1016:2625] , -sram_blwl_blb[1016:2625] ); -//----- END call Grid[1][1] module ----- - -//----- BEGIN Call Grid[0][1] module ----- -grid_0__1_ grid_0__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - grid_0__1__pin_0__1__0_, - grid_0__1__pin_0__1__1_, - grid_0__1__pin_0__1__2_, - grid_0__1__pin_0__1__3_, - grid_0__1__pin_0__1__4_, - grid_0__1__pin_0__1__5_, - grid_0__1__pin_0__1__6_, - grid_0__1__pin_0__1__7_, - grid_0__1__pin_0__1__8_, - grid_0__1__pin_0__1__9_, - grid_0__1__pin_0__1__10_, - grid_0__1__pin_0__1__11_, - grid_0__1__pin_0__1__12_, - grid_0__1__pin_0__1__13_, - grid_0__1__pin_0__1__14_, - grid_0__1__pin_0__1__15_, -gfpga_pad_iopad[7:0] , -sram_blwl_bl[2626:2633] , -sram_blwl_wl[2626:2633] , -sram_blwl_blb[2626:2633] ); -//----- END call Grid[0][1] module ----- - -//----- BEGIN Call Grid[2][1] module ----- -grid_2__1_ grid_2__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - grid_2__1__pin_0__3__0_, - grid_2__1__pin_0__3__1_, - grid_2__1__pin_0__3__2_, - grid_2__1__pin_0__3__3_, - grid_2__1__pin_0__3__4_, - grid_2__1__pin_0__3__5_, - grid_2__1__pin_0__3__6_, - grid_2__1__pin_0__3__7_, - grid_2__1__pin_0__3__8_, - grid_2__1__pin_0__3__9_, - grid_2__1__pin_0__3__10_, - grid_2__1__pin_0__3__11_, - grid_2__1__pin_0__3__12_, - grid_2__1__pin_0__3__13_, - grid_2__1__pin_0__3__14_, - grid_2__1__pin_0__3__15_, -gfpga_pad_iopad[15:8] , -sram_blwl_bl[2634:2641] , -sram_blwl_wl[2634:2641] , -sram_blwl_blb[2634:2641] ); -//----- END call Grid[2][1] module ----- - -//----- BEGIN Call Grid[1][0] module ----- -grid_1__0_ grid_1__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - grid_1__0__pin_0__0__0_, - grid_1__0__pin_0__0__1_, - grid_1__0__pin_0__0__2_, - grid_1__0__pin_0__0__3_, - grid_1__0__pin_0__0__4_, - grid_1__0__pin_0__0__5_, - grid_1__0__pin_0__0__6_, - grid_1__0__pin_0__0__7_, - grid_1__0__pin_0__0__8_, - grid_1__0__pin_0__0__9_, - grid_1__0__pin_0__0__10_, - grid_1__0__pin_0__0__11_, - grid_1__0__pin_0__0__12_, - grid_1__0__pin_0__0__13_, - grid_1__0__pin_0__0__14_, - grid_1__0__pin_0__0__15_, -gfpga_pad_iopad[23:16] , -sram_blwl_bl[2642:2649] , -sram_blwl_wl[2642:2649] , -sram_blwl_blb[2642:2649] ); -//----- END call Grid[1][0] module ----- - -//----- BEGIN Call Grid[1][2] module ----- -grid_1__2_ grid_1__2__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - grid_1__2__pin_0__2__0_, - grid_1__2__pin_0__2__1_, - grid_1__2__pin_0__2__2_, - grid_1__2__pin_0__2__3_, - grid_1__2__pin_0__2__4_, - grid_1__2__pin_0__2__5_, - grid_1__2__pin_0__2__6_, - grid_1__2__pin_0__2__7_, - grid_1__2__pin_0__2__8_, - grid_1__2__pin_0__2__9_, - grid_1__2__pin_0__2__10_, - grid_1__2__pin_0__2__11_, - grid_1__2__pin_0__2__12_, - grid_1__2__pin_0__2__13_, - grid_1__2__pin_0__2__14_, - grid_1__2__pin_0__2__15_, -gfpga_pad_iopad[31:24] , -sram_blwl_bl[2650:2657] , -sram_blwl_wl[2650:2657] , -sram_blwl_blb[2650:2657] ); -//----- END call Grid[1][2] module ----- - -//----- BEGIN Call Channel-X [1][0] module ----- -chanx_1__0_ chanx_1__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -chanx_1__0__out_0_, -chanx_1__0__in_1_, -chanx_1__0__out_2_, -chanx_1__0__in_3_, -chanx_1__0__out_4_, -chanx_1__0__in_5_, -chanx_1__0__out_6_, -chanx_1__0__in_7_, -chanx_1__0__out_8_, -chanx_1__0__in_9_, -chanx_1__0__out_10_, -chanx_1__0__in_11_, -chanx_1__0__out_12_, -chanx_1__0__in_13_, -chanx_1__0__out_14_, -chanx_1__0__in_15_, -chanx_1__0__out_16_, -chanx_1__0__in_17_, -chanx_1__0__out_18_, -chanx_1__0__in_19_, -chanx_1__0__out_20_, -chanx_1__0__in_21_, -chanx_1__0__out_22_, -chanx_1__0__in_23_, -chanx_1__0__out_24_, -chanx_1__0__in_25_, -chanx_1__0__out_26_, -chanx_1__0__in_27_, -chanx_1__0__out_28_, -chanx_1__0__in_29_, -chanx_1__0__out_30_, -chanx_1__0__in_31_, -chanx_1__0__out_32_, -chanx_1__0__in_33_, -chanx_1__0__out_34_, -chanx_1__0__in_35_, -chanx_1__0__out_36_, -chanx_1__0__in_37_, -chanx_1__0__out_38_, -chanx_1__0__in_39_, -chanx_1__0__out_40_, -chanx_1__0__in_41_, -chanx_1__0__out_42_, -chanx_1__0__in_43_, -chanx_1__0__out_44_, -chanx_1__0__in_45_, -chanx_1__0__out_46_, -chanx_1__0__in_47_, -chanx_1__0__out_48_, -chanx_1__0__in_49_, -chanx_1__0__out_50_, -chanx_1__0__in_51_, -chanx_1__0__out_52_, -chanx_1__0__in_53_, -chanx_1__0__out_54_, -chanx_1__0__in_55_, -chanx_1__0__out_56_, -chanx_1__0__in_57_, -chanx_1__0__out_58_, -chanx_1__0__in_59_, -chanx_1__0__out_60_, -chanx_1__0__in_61_, -chanx_1__0__out_62_, -chanx_1__0__in_63_, -chanx_1__0__out_64_, -chanx_1__0__in_65_, -chanx_1__0__out_66_, -chanx_1__0__in_67_, -chanx_1__0__out_68_, -chanx_1__0__in_69_, -chanx_1__0__out_70_, -chanx_1__0__in_71_, -chanx_1__0__out_72_, -chanx_1__0__in_73_, -chanx_1__0__out_74_, -chanx_1__0__in_75_, -chanx_1__0__out_76_, -chanx_1__0__in_77_, -chanx_1__0__out_78_, -chanx_1__0__in_79_, -chanx_1__0__out_80_, -chanx_1__0__in_81_, -chanx_1__0__out_82_, -chanx_1__0__in_83_, -chanx_1__0__out_84_, -chanx_1__0__in_85_, -chanx_1__0__out_86_, -chanx_1__0__in_87_, -chanx_1__0__out_88_, -chanx_1__0__in_89_, -chanx_1__0__out_90_, -chanx_1__0__in_91_, -chanx_1__0__out_92_, -chanx_1__0__in_93_, -chanx_1__0__out_94_, -chanx_1__0__in_95_, -chanx_1__0__out_96_, -chanx_1__0__in_97_, -chanx_1__0__out_98_, -chanx_1__0__in_99_, -chanx_1__0__in_0_, -chanx_1__0__out_1_, -chanx_1__0__in_2_, -chanx_1__0__out_3_, -chanx_1__0__in_4_, -chanx_1__0__out_5_, -chanx_1__0__in_6_, -chanx_1__0__out_7_, -chanx_1__0__in_8_, -chanx_1__0__out_9_, -chanx_1__0__in_10_, -chanx_1__0__out_11_, -chanx_1__0__in_12_, -chanx_1__0__out_13_, -chanx_1__0__in_14_, -chanx_1__0__out_15_, -chanx_1__0__in_16_, -chanx_1__0__out_17_, -chanx_1__0__in_18_, -chanx_1__0__out_19_, -chanx_1__0__in_20_, -chanx_1__0__out_21_, -chanx_1__0__in_22_, -chanx_1__0__out_23_, -chanx_1__0__in_24_, -chanx_1__0__out_25_, -chanx_1__0__in_26_, -chanx_1__0__out_27_, -chanx_1__0__in_28_, -chanx_1__0__out_29_, -chanx_1__0__in_30_, -chanx_1__0__out_31_, -chanx_1__0__in_32_, -chanx_1__0__out_33_, -chanx_1__0__in_34_, -chanx_1__0__out_35_, -chanx_1__0__in_36_, -chanx_1__0__out_37_, -chanx_1__0__in_38_, -chanx_1__0__out_39_, -chanx_1__0__in_40_, -chanx_1__0__out_41_, -chanx_1__0__in_42_, -chanx_1__0__out_43_, -chanx_1__0__in_44_, -chanx_1__0__out_45_, -chanx_1__0__in_46_, -chanx_1__0__out_47_, -chanx_1__0__in_48_, -chanx_1__0__out_49_, -chanx_1__0__in_50_, -chanx_1__0__out_51_, -chanx_1__0__in_52_, -chanx_1__0__out_53_, -chanx_1__0__in_54_, -chanx_1__0__out_55_, -chanx_1__0__in_56_, -chanx_1__0__out_57_, -chanx_1__0__in_58_, -chanx_1__0__out_59_, -chanx_1__0__in_60_, -chanx_1__0__out_61_, -chanx_1__0__in_62_, -chanx_1__0__out_63_, -chanx_1__0__in_64_, -chanx_1__0__out_65_, -chanx_1__0__in_66_, -chanx_1__0__out_67_, -chanx_1__0__in_68_, -chanx_1__0__out_69_, -chanx_1__0__in_70_, -chanx_1__0__out_71_, -chanx_1__0__in_72_, -chanx_1__0__out_73_, -chanx_1__0__in_74_, -chanx_1__0__out_75_, -chanx_1__0__in_76_, -chanx_1__0__out_77_, -chanx_1__0__in_78_, -chanx_1__0__out_79_, -chanx_1__0__in_80_, -chanx_1__0__out_81_, -chanx_1__0__in_82_, -chanx_1__0__out_83_, -chanx_1__0__in_84_, -chanx_1__0__out_85_, -chanx_1__0__in_86_, -chanx_1__0__out_87_, -chanx_1__0__in_88_, -chanx_1__0__out_89_, -chanx_1__0__in_90_, -chanx_1__0__out_91_, -chanx_1__0__in_92_, -chanx_1__0__out_93_, -chanx_1__0__in_94_, -chanx_1__0__out_95_, -chanx_1__0__in_96_, -chanx_1__0__out_97_, -chanx_1__0__in_98_, -chanx_1__0__out_99_, -chanx_1__0__midout_0_ , -chanx_1__0__midout_1_ , -chanx_1__0__midout_2_ , -chanx_1__0__midout_3_ , -chanx_1__0__midout_4_ , -chanx_1__0__midout_5_ , -chanx_1__0__midout_6_ , -chanx_1__0__midout_7_ , -chanx_1__0__midout_8_ , -chanx_1__0__midout_9_ , -chanx_1__0__midout_10_ , -chanx_1__0__midout_11_ , -chanx_1__0__midout_12_ , -chanx_1__0__midout_13_ , -chanx_1__0__midout_14_ , -chanx_1__0__midout_15_ , -chanx_1__0__midout_16_ , -chanx_1__0__midout_17_ , -chanx_1__0__midout_18_ , -chanx_1__0__midout_19_ , -chanx_1__0__midout_20_ , -chanx_1__0__midout_21_ , -chanx_1__0__midout_22_ , -chanx_1__0__midout_23_ , -chanx_1__0__midout_24_ , -chanx_1__0__midout_25_ , -chanx_1__0__midout_26_ , -chanx_1__0__midout_27_ , -chanx_1__0__midout_28_ , -chanx_1__0__midout_29_ , -chanx_1__0__midout_30_ , -chanx_1__0__midout_31_ , -chanx_1__0__midout_32_ , -chanx_1__0__midout_33_ , -chanx_1__0__midout_34_ , -chanx_1__0__midout_35_ , -chanx_1__0__midout_36_ , -chanx_1__0__midout_37_ , -chanx_1__0__midout_38_ , -chanx_1__0__midout_39_ , -chanx_1__0__midout_40_ , -chanx_1__0__midout_41_ , -chanx_1__0__midout_42_ , -chanx_1__0__midout_43_ , -chanx_1__0__midout_44_ , -chanx_1__0__midout_45_ , -chanx_1__0__midout_46_ , -chanx_1__0__midout_47_ , -chanx_1__0__midout_48_ , -chanx_1__0__midout_49_ , -chanx_1__0__midout_50_ , -chanx_1__0__midout_51_ , -chanx_1__0__midout_52_ , -chanx_1__0__midout_53_ , -chanx_1__0__midout_54_ , -chanx_1__0__midout_55_ , -chanx_1__0__midout_56_ , -chanx_1__0__midout_57_ , -chanx_1__0__midout_58_ , -chanx_1__0__midout_59_ , -chanx_1__0__midout_60_ , -chanx_1__0__midout_61_ , -chanx_1__0__midout_62_ , -chanx_1__0__midout_63_ , -chanx_1__0__midout_64_ , -chanx_1__0__midout_65_ , -chanx_1__0__midout_66_ , -chanx_1__0__midout_67_ , -chanx_1__0__midout_68_ , -chanx_1__0__midout_69_ , -chanx_1__0__midout_70_ , -chanx_1__0__midout_71_ , -chanx_1__0__midout_72_ , -chanx_1__0__midout_73_ , -chanx_1__0__midout_74_ , -chanx_1__0__midout_75_ , -chanx_1__0__midout_76_ , -chanx_1__0__midout_77_ , -chanx_1__0__midout_78_ , -chanx_1__0__midout_79_ , -chanx_1__0__midout_80_ , -chanx_1__0__midout_81_ , -chanx_1__0__midout_82_ , -chanx_1__0__midout_83_ , -chanx_1__0__midout_84_ , -chanx_1__0__midout_85_ , -chanx_1__0__midout_86_ , -chanx_1__0__midout_87_ , -chanx_1__0__midout_88_ , -chanx_1__0__midout_89_ , -chanx_1__0__midout_90_ , -chanx_1__0__midout_91_ , -chanx_1__0__midout_92_ , -chanx_1__0__midout_93_ , -chanx_1__0__midout_94_ , -chanx_1__0__midout_95_ , -chanx_1__0__midout_96_ , -chanx_1__0__midout_97_ , -chanx_1__0__midout_98_ , -chanx_1__0__midout_99_ -); -//----- END Call Channel-X [1][0] module ----- -//----- BEGIN Call Channel-X [1][1] module ----- -chanx_1__1_ chanx_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -chanx_1__1__out_0_, -chanx_1__1__in_1_, -chanx_1__1__out_2_, -chanx_1__1__in_3_, -chanx_1__1__out_4_, -chanx_1__1__in_5_, -chanx_1__1__out_6_, -chanx_1__1__in_7_, -chanx_1__1__out_8_, -chanx_1__1__in_9_, -chanx_1__1__out_10_, -chanx_1__1__in_11_, -chanx_1__1__out_12_, -chanx_1__1__in_13_, -chanx_1__1__out_14_, -chanx_1__1__in_15_, -chanx_1__1__out_16_, -chanx_1__1__in_17_, -chanx_1__1__out_18_, -chanx_1__1__in_19_, -chanx_1__1__out_20_, -chanx_1__1__in_21_, -chanx_1__1__out_22_, -chanx_1__1__in_23_, -chanx_1__1__out_24_, -chanx_1__1__in_25_, -chanx_1__1__out_26_, -chanx_1__1__in_27_, -chanx_1__1__out_28_, -chanx_1__1__in_29_, -chanx_1__1__out_30_, -chanx_1__1__in_31_, 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-chany_0__1__midout_7_ , -chany_0__1__midout_8_ , -chany_0__1__midout_9_ , -chany_0__1__midout_10_ , -chany_0__1__midout_11_ , -chany_0__1__midout_12_ , -chany_0__1__midout_13_ , -chany_0__1__midout_14_ , -chany_0__1__midout_15_ , -chany_0__1__midout_16_ , -chany_0__1__midout_17_ , -chany_0__1__midout_18_ , -chany_0__1__midout_19_ , -chany_0__1__midout_20_ , -chany_0__1__midout_21_ , -chany_0__1__midout_22_ , -chany_0__1__midout_23_ , -chany_0__1__midout_24_ , -chany_0__1__midout_25_ , -chany_0__1__midout_26_ , -chany_0__1__midout_27_ , -chany_0__1__midout_28_ , -chany_0__1__midout_29_ , -chany_0__1__midout_30_ , -chany_0__1__midout_31_ , -chany_0__1__midout_32_ , -chany_0__1__midout_33_ , -chany_0__1__midout_34_ , -chany_0__1__midout_35_ , -chany_0__1__midout_36_ , -chany_0__1__midout_37_ , -chany_0__1__midout_38_ , -chany_0__1__midout_39_ , -chany_0__1__midout_40_ , -chany_0__1__midout_41_ , -chany_0__1__midout_42_ , -chany_0__1__midout_43_ , -chany_0__1__midout_44_ , -chany_0__1__midout_45_ , -chany_0__1__midout_46_ , -chany_0__1__midout_47_ , -chany_0__1__midout_48_ , -chany_0__1__midout_49_ , -chany_0__1__midout_50_ , -chany_0__1__midout_51_ , -chany_0__1__midout_52_ , -chany_0__1__midout_53_ , -chany_0__1__midout_54_ , -chany_0__1__midout_55_ , -chany_0__1__midout_56_ , -chany_0__1__midout_57_ , -chany_0__1__midout_58_ , -chany_0__1__midout_59_ , -chany_0__1__midout_60_ , -chany_0__1__midout_61_ , -chany_0__1__midout_62_ , -chany_0__1__midout_63_ , -chany_0__1__midout_64_ , -chany_0__1__midout_65_ , -chany_0__1__midout_66_ , -chany_0__1__midout_67_ , -chany_0__1__midout_68_ , -chany_0__1__midout_69_ , -chany_0__1__midout_70_ , -chany_0__1__midout_71_ , -chany_0__1__midout_72_ , -chany_0__1__midout_73_ , -chany_0__1__midout_74_ , -chany_0__1__midout_75_ , -chany_0__1__midout_76_ , -chany_0__1__midout_77_ , -chany_0__1__midout_78_ , -chany_0__1__midout_79_ , -chany_0__1__midout_80_ , -chany_0__1__midout_81_ , -chany_0__1__midout_82_ , -chany_0__1__midout_83_ , -chany_0__1__midout_84_ , -chany_0__1__midout_85_ , -chany_0__1__midout_86_ , -chany_0__1__midout_87_ , -chany_0__1__midout_88_ , -chany_0__1__midout_89_ , -chany_0__1__midout_90_ , -chany_0__1__midout_91_ , -chany_0__1__midout_92_ , -chany_0__1__midout_93_ , -chany_0__1__midout_94_ , -chany_0__1__midout_95_ , -chany_0__1__midout_96_ , -chany_0__1__midout_97_ , -chany_0__1__midout_98_ , -chany_0__1__midout_99_ -); -//----- END call Channel-Y [0][1] module ----- - -//----- BEGIN call Channel-Y [1][1] module ----- - -chany_1__1_ chany_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -chany_1__1__out_0_, -chany_1__1__in_1_, -chany_1__1__out_2_, -chany_1__1__in_3_, -chany_1__1__out_4_, -chany_1__1__in_5_, -chany_1__1__out_6_, -chany_1__1__in_7_, -chany_1__1__out_8_, -chany_1__1__in_9_, -chany_1__1__out_10_, -chany_1__1__in_11_, -chany_1__1__out_12_, -chany_1__1__in_13_, -chany_1__1__out_14_, -chany_1__1__in_15_, -chany_1__1__out_16_, -chany_1__1__in_17_, -chany_1__1__out_18_, -chany_1__1__in_19_, -chany_1__1__out_20_, -chany_1__1__in_21_, -chany_1__1__out_22_, -chany_1__1__in_23_, -chany_1__1__out_24_, -chany_1__1__in_25_, -chany_1__1__out_26_, -chany_1__1__in_27_, -chany_1__1__out_28_, -chany_1__1__in_29_, -chany_1__1__out_30_, -chany_1__1__in_31_, -chany_1__1__out_32_, -chany_1__1__in_33_, -chany_1__1__out_34_, -chany_1__1__in_35_, -chany_1__1__out_36_, -chany_1__1__in_37_, -chany_1__1__out_38_, -chany_1__1__in_39_, -chany_1__1__out_40_, -chany_1__1__in_41_, -chany_1__1__out_42_, -chany_1__1__in_43_, -chany_1__1__out_44_, -chany_1__1__in_45_, -chany_1__1__out_46_, -chany_1__1__in_47_, -chany_1__1__out_48_, -chany_1__1__in_49_, -chany_1__1__out_50_, -chany_1__1__in_51_, -chany_1__1__out_52_, -chany_1__1__in_53_, -chany_1__1__out_54_, -chany_1__1__in_55_, -chany_1__1__out_56_, -chany_1__1__in_57_, -chany_1__1__out_58_, -chany_1__1__in_59_, -chany_1__1__out_60_, -chany_1__1__in_61_, -chany_1__1__out_62_, -chany_1__1__in_63_, -chany_1__1__out_64_, -chany_1__1__in_65_, -chany_1__1__out_66_, -chany_1__1__in_67_, -chany_1__1__out_68_, -chany_1__1__in_69_, -chany_1__1__out_70_, -chany_1__1__in_71_, -chany_1__1__out_72_, -chany_1__1__in_73_, -chany_1__1__out_74_, -chany_1__1__in_75_, -chany_1__1__out_76_, -chany_1__1__in_77_, -chany_1__1__out_78_, -chany_1__1__in_79_, -chany_1__1__out_80_, -chany_1__1__in_81_, -chany_1__1__out_82_, -chany_1__1__in_83_, -chany_1__1__out_84_, -chany_1__1__in_85_, -chany_1__1__out_86_, -chany_1__1__in_87_, -chany_1__1__out_88_, -chany_1__1__in_89_, -chany_1__1__out_90_, -chany_1__1__in_91_, -chany_1__1__out_92_, -chany_1__1__in_93_, -chany_1__1__out_94_, -chany_1__1__in_95_, -chany_1__1__out_96_, -chany_1__1__in_97_, -chany_1__1__out_98_, -chany_1__1__in_99_, -chany_1__1__in_0_, -chany_1__1__out_1_, -chany_1__1__in_2_, -chany_1__1__out_3_, -chany_1__1__in_4_, -chany_1__1__out_5_, -chany_1__1__in_6_, -chany_1__1__out_7_, -chany_1__1__in_8_, -chany_1__1__out_9_, -chany_1__1__in_10_, -chany_1__1__out_11_, -chany_1__1__in_12_, -chany_1__1__out_13_, -chany_1__1__in_14_, -chany_1__1__out_15_, -chany_1__1__in_16_, -chany_1__1__out_17_, -chany_1__1__in_18_, -chany_1__1__out_19_, -chany_1__1__in_20_, -chany_1__1__out_21_, -chany_1__1__in_22_, -chany_1__1__out_23_, -chany_1__1__in_24_, -chany_1__1__out_25_, -chany_1__1__in_26_, -chany_1__1__out_27_, -chany_1__1__in_28_, -chany_1__1__out_29_, -chany_1__1__in_30_, -chany_1__1__out_31_, -chany_1__1__in_32_, -chany_1__1__out_33_, -chany_1__1__in_34_, -chany_1__1__out_35_, -chany_1__1__in_36_, -chany_1__1__out_37_, -chany_1__1__in_38_, -chany_1__1__out_39_, -chany_1__1__in_40_, -chany_1__1__out_41_, -chany_1__1__in_42_, -chany_1__1__out_43_, -chany_1__1__in_44_, -chany_1__1__out_45_, -chany_1__1__in_46_, -chany_1__1__out_47_, -chany_1__1__in_48_, -chany_1__1__out_49_, -chany_1__1__in_50_, -chany_1__1__out_51_, -chany_1__1__in_52_, -chany_1__1__out_53_, -chany_1__1__in_54_, -chany_1__1__out_55_, -chany_1__1__in_56_, -chany_1__1__out_57_, -chany_1__1__in_58_, -chany_1__1__out_59_, -chany_1__1__in_60_, -chany_1__1__out_61_, -chany_1__1__in_62_, -chany_1__1__out_63_, -chany_1__1__in_64_, -chany_1__1__out_65_, -chany_1__1__in_66_, -chany_1__1__out_67_, -chany_1__1__in_68_, -chany_1__1__out_69_, -chany_1__1__in_70_, -chany_1__1__out_71_, -chany_1__1__in_72_, -chany_1__1__out_73_, -chany_1__1__in_74_, -chany_1__1__out_75_, -chany_1__1__in_76_, -chany_1__1__out_77_, -chany_1__1__in_78_, -chany_1__1__out_79_, -chany_1__1__in_80_, -chany_1__1__out_81_, -chany_1__1__in_82_, -chany_1__1__out_83_, -chany_1__1__in_84_, -chany_1__1__out_85_, -chany_1__1__in_86_, -chany_1__1__out_87_, -chany_1__1__in_88_, -chany_1__1__out_89_, -chany_1__1__in_90_, -chany_1__1__out_91_, -chany_1__1__in_92_, -chany_1__1__out_93_, -chany_1__1__in_94_, -chany_1__1__out_95_, -chany_1__1__in_96_, -chany_1__1__out_97_, -chany_1__1__in_98_, -chany_1__1__out_99_, -chany_1__1__midout_0_ , -chany_1__1__midout_1_ , -chany_1__1__midout_2_ , -chany_1__1__midout_3_ , -chany_1__1__midout_4_ , -chany_1__1__midout_5_ , -chany_1__1__midout_6_ , -chany_1__1__midout_7_ , -chany_1__1__midout_8_ , -chany_1__1__midout_9_ , -chany_1__1__midout_10_ , -chany_1__1__midout_11_ , -chany_1__1__midout_12_ , -chany_1__1__midout_13_ , -chany_1__1__midout_14_ , -chany_1__1__midout_15_ , -chany_1__1__midout_16_ , -chany_1__1__midout_17_ , -chany_1__1__midout_18_ , -chany_1__1__midout_19_ , -chany_1__1__midout_20_ , -chany_1__1__midout_21_ , -chany_1__1__midout_22_ , -chany_1__1__midout_23_ , -chany_1__1__midout_24_ , -chany_1__1__midout_25_ , -chany_1__1__midout_26_ , -chany_1__1__midout_27_ , -chany_1__1__midout_28_ , -chany_1__1__midout_29_ , -chany_1__1__midout_30_ , -chany_1__1__midout_31_ , -chany_1__1__midout_32_ , -chany_1__1__midout_33_ , -chany_1__1__midout_34_ , -chany_1__1__midout_35_ , -chany_1__1__midout_36_ , -chany_1__1__midout_37_ , -chany_1__1__midout_38_ , -chany_1__1__midout_39_ , -chany_1__1__midout_40_ , -chany_1__1__midout_41_ , -chany_1__1__midout_42_ , -chany_1__1__midout_43_ , -chany_1__1__midout_44_ , -chany_1__1__midout_45_ , -chany_1__1__midout_46_ , -chany_1__1__midout_47_ , -chany_1__1__midout_48_ , -chany_1__1__midout_49_ , -chany_1__1__midout_50_ , -chany_1__1__midout_51_ , -chany_1__1__midout_52_ , -chany_1__1__midout_53_ , -chany_1__1__midout_54_ , -chany_1__1__midout_55_ , -chany_1__1__midout_56_ , -chany_1__1__midout_57_ , -chany_1__1__midout_58_ , -chany_1__1__midout_59_ , -chany_1__1__midout_60_ , -chany_1__1__midout_61_ , -chany_1__1__midout_62_ , -chany_1__1__midout_63_ , -chany_1__1__midout_64_ , -chany_1__1__midout_65_ , -chany_1__1__midout_66_ , -chany_1__1__midout_67_ , -chany_1__1__midout_68_ , -chany_1__1__midout_69_ , -chany_1__1__midout_70_ , -chany_1__1__midout_71_ , -chany_1__1__midout_72_ , -chany_1__1__midout_73_ , -chany_1__1__midout_74_ , -chany_1__1__midout_75_ , -chany_1__1__midout_76_ , -chany_1__1__midout_77_ , -chany_1__1__midout_78_ , -chany_1__1__midout_79_ , -chany_1__1__midout_80_ , -chany_1__1__midout_81_ , -chany_1__1__midout_82_ , -chany_1__1__midout_83_ , -chany_1__1__midout_84_ , -chany_1__1__midout_85_ , -chany_1__1__midout_86_ , -chany_1__1__midout_87_ , -chany_1__1__midout_88_ , -chany_1__1__midout_89_ , -chany_1__1__midout_90_ , -chany_1__1__midout_91_ , -chany_1__1__midout_92_ , -chany_1__1__midout_93_ , -chany_1__1__midout_94_ , -chany_1__1__midout_95_ , -chany_1__1__midout_96_ , -chany_1__1__midout_97_ , -chany_1__1__midout_98_ , -chany_1__1__midout_99_ -); -//----- END call Channel-Y [1][1] module ----- - -//----- BEGIN Call Connection Box-X direction [1][0] module ----- -cbx_1__0_ cbx_1__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- right side inputs: channel track middle outputs ----- -chanx_1__0__midout_0_, -chanx_1__0__midout_1_, -chanx_1__0__midout_2_, -chanx_1__0__midout_3_, -chanx_1__0__midout_4_, -chanx_1__0__midout_5_, -chanx_1__0__midout_6_, -chanx_1__0__midout_7_, -chanx_1__0__midout_8_, -chanx_1__0__midout_9_, -chanx_1__0__midout_10_, -chanx_1__0__midout_11_, -chanx_1__0__midout_12_, -chanx_1__0__midout_13_, -chanx_1__0__midout_14_, -chanx_1__0__midout_15_, -chanx_1__0__midout_16_, -chanx_1__0__midout_17_, -chanx_1__0__midout_18_, -chanx_1__0__midout_19_, -chanx_1__0__midout_20_, -chanx_1__0__midout_21_, -chanx_1__0__midout_22_, -chanx_1__0__midout_23_, -chanx_1__0__midout_24_, -chanx_1__0__midout_25_, -chanx_1__0__midout_26_, -chanx_1__0__midout_27_, -chanx_1__0__midout_28_, -chanx_1__0__midout_29_, -chanx_1__0__midout_30_, -chanx_1__0__midout_31_, -chanx_1__0__midout_32_, -chanx_1__0__midout_33_, -chanx_1__0__midout_34_, -chanx_1__0__midout_35_, -chanx_1__0__midout_36_, -chanx_1__0__midout_37_, -chanx_1__0__midout_38_, -chanx_1__0__midout_39_, -chanx_1__0__midout_40_, -chanx_1__0__midout_41_, -chanx_1__0__midout_42_, -chanx_1__0__midout_43_, -chanx_1__0__midout_44_, -chanx_1__0__midout_45_, -chanx_1__0__midout_46_, -chanx_1__0__midout_47_, -chanx_1__0__midout_48_, -chanx_1__0__midout_49_, -chanx_1__0__midout_50_, -chanx_1__0__midout_51_, -chanx_1__0__midout_52_, -chanx_1__0__midout_53_, -chanx_1__0__midout_54_, -chanx_1__0__midout_55_, -chanx_1__0__midout_56_, -chanx_1__0__midout_57_, -chanx_1__0__midout_58_, -chanx_1__0__midout_59_, -chanx_1__0__midout_60_, -chanx_1__0__midout_61_, -chanx_1__0__midout_62_, -chanx_1__0__midout_63_, -chanx_1__0__midout_64_, -chanx_1__0__midout_65_, -chanx_1__0__midout_66_, -chanx_1__0__midout_67_, -chanx_1__0__midout_68_, -chanx_1__0__midout_69_, -chanx_1__0__midout_70_, -chanx_1__0__midout_71_, -chanx_1__0__midout_72_, -chanx_1__0__midout_73_, -chanx_1__0__midout_74_, -chanx_1__0__midout_75_, -chanx_1__0__midout_76_, -chanx_1__0__midout_77_, -chanx_1__0__midout_78_, -chanx_1__0__midout_79_, -chanx_1__0__midout_80_, -chanx_1__0__midout_81_, -chanx_1__0__midout_82_, -chanx_1__0__midout_83_, -chanx_1__0__midout_84_, -chanx_1__0__midout_85_, -chanx_1__0__midout_86_, -chanx_1__0__midout_87_, -chanx_1__0__midout_88_, -chanx_1__0__midout_89_, -chanx_1__0__midout_90_, -chanx_1__0__midout_91_, -chanx_1__0__midout_92_, -chanx_1__0__midout_93_, -chanx_1__0__midout_94_, -chanx_1__0__midout_95_, -chanx_1__0__midout_96_, -chanx_1__0__midout_97_, -chanx_1__0__midout_98_, -chanx_1__0__midout_99_, -//----- top side outputs: CLB input pins ----- - grid_1__1__pin_0__2__2_, - grid_1__1__pin_0__2__6_, - grid_1__1__pin_0__2__10_, - grid_1__1__pin_0__2__14_, - grid_1__1__pin_0__2__18_, - grid_1__1__pin_0__2__22_, - grid_1__1__pin_0__2__26_, - grid_1__1__pin_0__2__30_, - grid_1__1__pin_0__2__34_, - grid_1__1__pin_0__2__38_, - grid_1__1__pin_0__2__50_, -//----- bottom side outputs: CLB input pins ----- - grid_1__0__pin_0__0__0_, - grid_1__0__pin_0__0__2_, - grid_1__0__pin_0__0__4_, - grid_1__0__pin_0__0__6_, - grid_1__0__pin_0__0__8_, - grid_1__0__pin_0__0__10_, - grid_1__0__pin_0__0__12_, - grid_1__0__pin_0__0__14_, -sram_blwl_bl[440:583] , -sram_blwl_wl[440:583] , -sram_blwl_blb[440:583] ); -//----- END call Connection Box-X direction [1][0] module ----- - -//----- BEGIN Call Connection Box-X direction [1][1] module ----- -cbx_1__1_ cbx_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- right side inputs: channel track middle outputs ----- -chanx_1__1__midout_0_, -chanx_1__1__midout_1_, -chanx_1__1__midout_2_, -chanx_1__1__midout_3_, -chanx_1__1__midout_4_, -chanx_1__1__midout_5_, -chanx_1__1__midout_6_, -chanx_1__1__midout_7_, -chanx_1__1__midout_8_, -chanx_1__1__midout_9_, -chanx_1__1__midout_10_, -chanx_1__1__midout_11_, -chanx_1__1__midout_12_, -chanx_1__1__midout_13_, -chanx_1__1__midout_14_, -chanx_1__1__midout_15_, -chanx_1__1__midout_16_, -chanx_1__1__midout_17_, -chanx_1__1__midout_18_, -chanx_1__1__midout_19_, -chanx_1__1__midout_20_, -chanx_1__1__midout_21_, -chanx_1__1__midout_22_, -chanx_1__1__midout_23_, -chanx_1__1__midout_24_, -chanx_1__1__midout_25_, -chanx_1__1__midout_26_, -chanx_1__1__midout_27_, -chanx_1__1__midout_28_, -chanx_1__1__midout_29_, -chanx_1__1__midout_30_, -chanx_1__1__midout_31_, -chanx_1__1__midout_32_, -chanx_1__1__midout_33_, -chanx_1__1__midout_34_, -chanx_1__1__midout_35_, -chanx_1__1__midout_36_, -chanx_1__1__midout_37_, -chanx_1__1__midout_38_, -chanx_1__1__midout_39_, -chanx_1__1__midout_40_, -chanx_1__1__midout_41_, -chanx_1__1__midout_42_, -chanx_1__1__midout_43_, -chanx_1__1__midout_44_, -chanx_1__1__midout_45_, -chanx_1__1__midout_46_, -chanx_1__1__midout_47_, -chanx_1__1__midout_48_, -chanx_1__1__midout_49_, -chanx_1__1__midout_50_, -chanx_1__1__midout_51_, -chanx_1__1__midout_52_, -chanx_1__1__midout_53_, -chanx_1__1__midout_54_, -chanx_1__1__midout_55_, -chanx_1__1__midout_56_, -chanx_1__1__midout_57_, -chanx_1__1__midout_58_, -chanx_1__1__midout_59_, -chanx_1__1__midout_60_, -chanx_1__1__midout_61_, -chanx_1__1__midout_62_, -chanx_1__1__midout_63_, -chanx_1__1__midout_64_, -chanx_1__1__midout_65_, -chanx_1__1__midout_66_, -chanx_1__1__midout_67_, -chanx_1__1__midout_68_, -chanx_1__1__midout_69_, -chanx_1__1__midout_70_, -chanx_1__1__midout_71_, -chanx_1__1__midout_72_, -chanx_1__1__midout_73_, -chanx_1__1__midout_74_, -chanx_1__1__midout_75_, -chanx_1__1__midout_76_, -chanx_1__1__midout_77_, -chanx_1__1__midout_78_, -chanx_1__1__midout_79_, -chanx_1__1__midout_80_, -chanx_1__1__midout_81_, -chanx_1__1__midout_82_, -chanx_1__1__midout_83_, -chanx_1__1__midout_84_, -chanx_1__1__midout_85_, -chanx_1__1__midout_86_, -chanx_1__1__midout_87_, -chanx_1__1__midout_88_, -chanx_1__1__midout_89_, -chanx_1__1__midout_90_, -chanx_1__1__midout_91_, -chanx_1__1__midout_92_, -chanx_1__1__midout_93_, -chanx_1__1__midout_94_, -chanx_1__1__midout_95_, -chanx_1__1__midout_96_, -chanx_1__1__midout_97_, -chanx_1__1__midout_98_, -chanx_1__1__midout_99_, -//----- top side outputs: CLB input pins ----- - grid_1__2__pin_0__2__0_, - grid_1__2__pin_0__2__2_, - grid_1__2__pin_0__2__4_, - grid_1__2__pin_0__2__6_, - grid_1__2__pin_0__2__8_, - grid_1__2__pin_0__2__10_, - grid_1__2__pin_0__2__12_, - grid_1__2__pin_0__2__14_, -//----- bottom side outputs: CLB input pins ----- - grid_1__1__pin_0__0__0_, - grid_1__1__pin_0__0__4_, - grid_1__1__pin_0__0__8_, - grid_1__1__pin_0__0__12_, - grid_1__1__pin_0__0__16_, - grid_1__1__pin_0__0__20_, - grid_1__1__pin_0__0__24_, - grid_1__1__pin_0__0__28_, - grid_1__1__pin_0__0__32_, - grid_1__1__pin_0__0__36_, -sram_blwl_bl[584:727] , -sram_blwl_wl[584:727] , -sram_blwl_blb[584:727] ); -//----- END call Connection Box-X direction [1][1] module ----- - -//----- BEGIN Call Connection Box-Y direction [0][1] module ----- -cby_0__1_ cby_0__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side inputs: channel track middle outputs ----- -chany_0__1__midout_0_, -chany_0__1__midout_1_, -chany_0__1__midout_2_, -chany_0__1__midout_3_, -chany_0__1__midout_4_, -chany_0__1__midout_5_, -chany_0__1__midout_6_, -chany_0__1__midout_7_, -chany_0__1__midout_8_, -chany_0__1__midout_9_, -chany_0__1__midout_10_, -chany_0__1__midout_11_, -chany_0__1__midout_12_, -chany_0__1__midout_13_, -chany_0__1__midout_14_, -chany_0__1__midout_15_, -chany_0__1__midout_16_, -chany_0__1__midout_17_, -chany_0__1__midout_18_, -chany_0__1__midout_19_, -chany_0__1__midout_20_, -chany_0__1__midout_21_, -chany_0__1__midout_22_, -chany_0__1__midout_23_, -chany_0__1__midout_24_, -chany_0__1__midout_25_, -chany_0__1__midout_26_, -chany_0__1__midout_27_, -chany_0__1__midout_28_, -chany_0__1__midout_29_, -chany_0__1__midout_30_, -chany_0__1__midout_31_, -chany_0__1__midout_32_, -chany_0__1__midout_33_, -chany_0__1__midout_34_, -chany_0__1__midout_35_, -chany_0__1__midout_36_, -chany_0__1__midout_37_, -chany_0__1__midout_38_, -chany_0__1__midout_39_, -chany_0__1__midout_40_, -chany_0__1__midout_41_, -chany_0__1__midout_42_, -chany_0__1__midout_43_, -chany_0__1__midout_44_, -chany_0__1__midout_45_, -chany_0__1__midout_46_, -chany_0__1__midout_47_, -chany_0__1__midout_48_, -chany_0__1__midout_49_, -chany_0__1__midout_50_, -chany_0__1__midout_51_, -chany_0__1__midout_52_, -chany_0__1__midout_53_, -chany_0__1__midout_54_, -chany_0__1__midout_55_, -chany_0__1__midout_56_, -chany_0__1__midout_57_, -chany_0__1__midout_58_, -chany_0__1__midout_59_, -chany_0__1__midout_60_, -chany_0__1__midout_61_, -chany_0__1__midout_62_, -chany_0__1__midout_63_, -chany_0__1__midout_64_, -chany_0__1__midout_65_, -chany_0__1__midout_66_, -chany_0__1__midout_67_, -chany_0__1__midout_68_, -chany_0__1__midout_69_, -chany_0__1__midout_70_, -chany_0__1__midout_71_, -chany_0__1__midout_72_, -chany_0__1__midout_73_, -chany_0__1__midout_74_, -chany_0__1__midout_75_, -chany_0__1__midout_76_, -chany_0__1__midout_77_, -chany_0__1__midout_78_, -chany_0__1__midout_79_, -chany_0__1__midout_80_, -chany_0__1__midout_81_, -chany_0__1__midout_82_, -chany_0__1__midout_83_, -chany_0__1__midout_84_, -chany_0__1__midout_85_, -chany_0__1__midout_86_, -chany_0__1__midout_87_, -chany_0__1__midout_88_, -chany_0__1__midout_89_, -chany_0__1__midout_90_, -chany_0__1__midout_91_, -chany_0__1__midout_92_, -chany_0__1__midout_93_, -chany_0__1__midout_94_, -chany_0__1__midout_95_, -chany_0__1__midout_96_, -chany_0__1__midout_97_, -chany_0__1__midout_98_, -chany_0__1__midout_99_, -//----- right side outputs: CLB input pins ----- - grid_1__1__pin_0__3__3_, - grid_1__1__pin_0__3__7_, - grid_1__1__pin_0__3__11_, - grid_1__1__pin_0__3__15_, - grid_1__1__pin_0__3__19_, - grid_1__1__pin_0__3__23_, - grid_1__1__pin_0__3__27_, - grid_1__1__pin_0__3__31_, - grid_1__1__pin_0__3__35_, - grid_1__1__pin_0__3__39_, -//----- left side outputs: CLB input pins ----- - grid_0__1__pin_0__1__0_, - grid_0__1__pin_0__1__2_, - grid_0__1__pin_0__1__4_, - grid_0__1__pin_0__1__6_, - grid_0__1__pin_0__1__8_, - grid_0__1__pin_0__1__10_, - grid_0__1__pin_0__1__12_, - grid_0__1__pin_0__1__14_, -sram_blwl_bl[728:871] , -sram_blwl_wl[728:871] , -sram_blwl_blb[728:871] ); -//----- END call Connection Box-Y direction [0][1] module ----- - -//----- BEGIN Call Connection Box-Y direction [1][1] module ----- -cby_1__1_ cby_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side inputs: channel track middle outputs ----- -chany_1__1__midout_0_, -chany_1__1__midout_1_, -chany_1__1__midout_2_, -chany_1__1__midout_3_, -chany_1__1__midout_4_, -chany_1__1__midout_5_, -chany_1__1__midout_6_, -chany_1__1__midout_7_, -chany_1__1__midout_8_, -chany_1__1__midout_9_, -chany_1__1__midout_10_, -chany_1__1__midout_11_, -chany_1__1__midout_12_, -chany_1__1__midout_13_, -chany_1__1__midout_14_, -chany_1__1__midout_15_, -chany_1__1__midout_16_, -chany_1__1__midout_17_, -chany_1__1__midout_18_, -chany_1__1__midout_19_, -chany_1__1__midout_20_, -chany_1__1__midout_21_, -chany_1__1__midout_22_, -chany_1__1__midout_23_, -chany_1__1__midout_24_, -chany_1__1__midout_25_, -chany_1__1__midout_26_, -chany_1__1__midout_27_, -chany_1__1__midout_28_, -chany_1__1__midout_29_, -chany_1__1__midout_30_, -chany_1__1__midout_31_, -chany_1__1__midout_32_, -chany_1__1__midout_33_, -chany_1__1__midout_34_, -chany_1__1__midout_35_, -chany_1__1__midout_36_, -chany_1__1__midout_37_, -chany_1__1__midout_38_, -chany_1__1__midout_39_, -chany_1__1__midout_40_, -chany_1__1__midout_41_, -chany_1__1__midout_42_, -chany_1__1__midout_43_, -chany_1__1__midout_44_, -chany_1__1__midout_45_, -chany_1__1__midout_46_, -chany_1__1__midout_47_, -chany_1__1__midout_48_, -chany_1__1__midout_49_, -chany_1__1__midout_50_, -chany_1__1__midout_51_, -chany_1__1__midout_52_, -chany_1__1__midout_53_, -chany_1__1__midout_54_, -chany_1__1__midout_55_, -chany_1__1__midout_56_, -chany_1__1__midout_57_, -chany_1__1__midout_58_, -chany_1__1__midout_59_, -chany_1__1__midout_60_, -chany_1__1__midout_61_, -chany_1__1__midout_62_, -chany_1__1__midout_63_, -chany_1__1__midout_64_, -chany_1__1__midout_65_, -chany_1__1__midout_66_, -chany_1__1__midout_67_, -chany_1__1__midout_68_, -chany_1__1__midout_69_, -chany_1__1__midout_70_, -chany_1__1__midout_71_, -chany_1__1__midout_72_, -chany_1__1__midout_73_, -chany_1__1__midout_74_, -chany_1__1__midout_75_, -chany_1__1__midout_76_, -chany_1__1__midout_77_, -chany_1__1__midout_78_, -chany_1__1__midout_79_, -chany_1__1__midout_80_, -chany_1__1__midout_81_, -chany_1__1__midout_82_, -chany_1__1__midout_83_, -chany_1__1__midout_84_, -chany_1__1__midout_85_, -chany_1__1__midout_86_, -chany_1__1__midout_87_, -chany_1__1__midout_88_, -chany_1__1__midout_89_, -chany_1__1__midout_90_, -chany_1__1__midout_91_, -chany_1__1__midout_92_, -chany_1__1__midout_93_, -chany_1__1__midout_94_, -chany_1__1__midout_95_, -chany_1__1__midout_96_, -chany_1__1__midout_97_, -chany_1__1__midout_98_, -chany_1__1__midout_99_, -//----- right side outputs: CLB input pins ----- - grid_2__1__pin_0__3__0_, - grid_2__1__pin_0__3__2_, - grid_2__1__pin_0__3__4_, - grid_2__1__pin_0__3__6_, - grid_2__1__pin_0__3__8_, - grid_2__1__pin_0__3__10_, - grid_2__1__pin_0__3__12_, - grid_2__1__pin_0__3__14_, -//----- left side outputs: CLB input pins ----- - grid_1__1__pin_0__1__1_, - grid_1__1__pin_0__1__5_, - grid_1__1__pin_0__1__9_, - grid_1__1__pin_0__1__13_, - grid_1__1__pin_0__1__17_, - grid_1__1__pin_0__1__21_, - grid_1__1__pin_0__1__25_, - grid_1__1__pin_0__1__29_, - grid_1__1__pin_0__1__33_, - grid_1__1__pin_0__1__37_, -sram_blwl_bl[872:1015] , -sram_blwl_wl[872:1015] , -sram_blwl_blb[872:1015] ); -//----- END call Connection Box-Y direction [1][1] module ----- - -//----- BEGIN call module Switch blocks [0][0] ----- -sb_0__0_ sb_0__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side channel ports----- -chany_0__1__out_0_, chany_0__1__in_1_, chany_0__1__out_2_, chany_0__1__in_3_, chany_0__1__out_4_, chany_0__1__in_5_, chany_0__1__out_6_, chany_0__1__in_7_, chany_0__1__out_8_, chany_0__1__in_9_, chany_0__1__out_10_, chany_0__1__in_11_, chany_0__1__out_12_, chany_0__1__in_13_, chany_0__1__out_14_, chany_0__1__in_15_, chany_0__1__out_16_, chany_0__1__in_17_, chany_0__1__out_18_, chany_0__1__in_19_, chany_0__1__out_20_, chany_0__1__in_21_, chany_0__1__out_22_, chany_0__1__in_23_, chany_0__1__out_24_, chany_0__1__in_25_, chany_0__1__out_26_, chany_0__1__in_27_, chany_0__1__out_28_, chany_0__1__in_29_, chany_0__1__out_30_, chany_0__1__in_31_, chany_0__1__out_32_, chany_0__1__in_33_, chany_0__1__out_34_, chany_0__1__in_35_, chany_0__1__out_36_, chany_0__1__in_37_, chany_0__1__out_38_, chany_0__1__in_39_, chany_0__1__out_40_, chany_0__1__in_41_, chany_0__1__out_42_, chany_0__1__in_43_, chany_0__1__out_44_, chany_0__1__in_45_, chany_0__1__out_46_, chany_0__1__in_47_, chany_0__1__out_48_, chany_0__1__in_49_, chany_0__1__out_50_, chany_0__1__in_51_, chany_0__1__out_52_, chany_0__1__in_53_, chany_0__1__out_54_, chany_0__1__in_55_, chany_0__1__out_56_, chany_0__1__in_57_, chany_0__1__out_58_, chany_0__1__in_59_, chany_0__1__out_60_, chany_0__1__in_61_, chany_0__1__out_62_, chany_0__1__in_63_, chany_0__1__out_64_, chany_0__1__in_65_, chany_0__1__out_66_, chany_0__1__in_67_, chany_0__1__out_68_, chany_0__1__in_69_, chany_0__1__out_70_, chany_0__1__in_71_, chany_0__1__out_72_, chany_0__1__in_73_, chany_0__1__out_74_, chany_0__1__in_75_, chany_0__1__out_76_, chany_0__1__in_77_, chany_0__1__out_78_, chany_0__1__in_79_, chany_0__1__out_80_, chany_0__1__in_81_, chany_0__1__out_82_, chany_0__1__in_83_, chany_0__1__out_84_, chany_0__1__in_85_, chany_0__1__out_86_, chany_0__1__in_87_, chany_0__1__out_88_, chany_0__1__in_89_, chany_0__1__out_90_, chany_0__1__in_91_, chany_0__1__out_92_, chany_0__1__in_93_, chany_0__1__out_94_, chany_0__1__in_95_, chany_0__1__out_96_, chany_0__1__in_97_, chany_0__1__out_98_, chany_0__1__in_99_, -//----- top side inputs: CLB output pins ----- - grid_0__1__pin_0__1__1_, grid_0__1__pin_0__1__3_, grid_0__1__pin_0__1__5_, grid_0__1__pin_0__1__7_, grid_0__1__pin_0__1__9_, grid_0__1__pin_0__1__11_, grid_0__1__pin_0__1__13_, grid_0__1__pin_0__1__15_, grid_1__1__pin_0__3__43_, grid_1__1__pin_0__3__47_, -//----- right side channel ports----- -chanx_1__0__out_0_, chanx_1__0__in_1_, chanx_1__0__out_2_, chanx_1__0__in_3_, chanx_1__0__out_4_, chanx_1__0__in_5_, chanx_1__0__out_6_, chanx_1__0__in_7_, chanx_1__0__out_8_, chanx_1__0__in_9_, chanx_1__0__out_10_, chanx_1__0__in_11_, chanx_1__0__out_12_, chanx_1__0__in_13_, chanx_1__0__out_14_, chanx_1__0__in_15_, chanx_1__0__out_16_, chanx_1__0__in_17_, chanx_1__0__out_18_, chanx_1__0__in_19_, chanx_1__0__out_20_, chanx_1__0__in_21_, chanx_1__0__out_22_, chanx_1__0__in_23_, chanx_1__0__out_24_, chanx_1__0__in_25_, chanx_1__0__out_26_, chanx_1__0__in_27_, chanx_1__0__out_28_, chanx_1__0__in_29_, chanx_1__0__out_30_, chanx_1__0__in_31_, chanx_1__0__out_32_, chanx_1__0__in_33_, chanx_1__0__out_34_, chanx_1__0__in_35_, chanx_1__0__out_36_, chanx_1__0__in_37_, chanx_1__0__out_38_, chanx_1__0__in_39_, chanx_1__0__out_40_, chanx_1__0__in_41_, chanx_1__0__out_42_, chanx_1__0__in_43_, chanx_1__0__out_44_, chanx_1__0__in_45_, chanx_1__0__out_46_, chanx_1__0__in_47_, chanx_1__0__out_48_, chanx_1__0__in_49_, chanx_1__0__out_50_, chanx_1__0__in_51_, chanx_1__0__out_52_, chanx_1__0__in_53_, chanx_1__0__out_54_, chanx_1__0__in_55_, chanx_1__0__out_56_, chanx_1__0__in_57_, chanx_1__0__out_58_, chanx_1__0__in_59_, chanx_1__0__out_60_, chanx_1__0__in_61_, chanx_1__0__out_62_, chanx_1__0__in_63_, chanx_1__0__out_64_, chanx_1__0__in_65_, chanx_1__0__out_66_, chanx_1__0__in_67_, chanx_1__0__out_68_, chanx_1__0__in_69_, chanx_1__0__out_70_, chanx_1__0__in_71_, chanx_1__0__out_72_, chanx_1__0__in_73_, chanx_1__0__out_74_, chanx_1__0__in_75_, chanx_1__0__out_76_, chanx_1__0__in_77_, chanx_1__0__out_78_, chanx_1__0__in_79_, chanx_1__0__out_80_, chanx_1__0__in_81_, chanx_1__0__out_82_, chanx_1__0__in_83_, chanx_1__0__out_84_, chanx_1__0__in_85_, chanx_1__0__out_86_, chanx_1__0__in_87_, chanx_1__0__out_88_, chanx_1__0__in_89_, chanx_1__0__out_90_, chanx_1__0__in_91_, chanx_1__0__out_92_, chanx_1__0__in_93_, chanx_1__0__out_94_, chanx_1__0__in_95_, chanx_1__0__out_96_, chanx_1__0__in_97_, chanx_1__0__out_98_, chanx_1__0__in_99_, -//----- right side inputs: CLB output pins ----- - grid_1__1__pin_0__2__42_, grid_1__1__pin_0__2__46_, grid_1__0__pin_0__0__1_, grid_1__0__pin_0__0__3_, grid_1__0__pin_0__0__5_, grid_1__0__pin_0__0__7_, grid_1__0__pin_0__0__9_, grid_1__0__pin_0__0__11_, grid_1__0__pin_0__0__13_, grid_1__0__pin_0__0__15_, -//----- bottom side channel ports----- - -//----- bottom side inputs: CLB output pins ----- - -//----- left side channel ports----- - -//----- left side inputs: CLB output pins ----- - -sram_blwl_bl[0:99] , -sram_blwl_wl[0:99] , -sram_blwl_blb[0:99] ); -//----- END call module Switch blocks [0][0] ----- - -//----- BEGIN call module Switch blocks [0][1] ----- -sb_0__1_ sb_0__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side channel ports----- - -//----- top side inputs: CLB output pins ----- - -//----- right side channel ports----- -chanx_1__1__out_0_, chanx_1__1__in_1_, chanx_1__1__out_2_, chanx_1__1__in_3_, chanx_1__1__out_4_, chanx_1__1__in_5_, chanx_1__1__out_6_, chanx_1__1__in_7_, chanx_1__1__out_8_, chanx_1__1__in_9_, chanx_1__1__out_10_, chanx_1__1__in_11_, chanx_1__1__out_12_, chanx_1__1__in_13_, chanx_1__1__out_14_, chanx_1__1__in_15_, chanx_1__1__out_16_, chanx_1__1__in_17_, chanx_1__1__out_18_, chanx_1__1__in_19_, chanx_1__1__out_20_, chanx_1__1__in_21_, chanx_1__1__out_22_, chanx_1__1__in_23_, chanx_1__1__out_24_, chanx_1__1__in_25_, chanx_1__1__out_26_, chanx_1__1__in_27_, chanx_1__1__out_28_, chanx_1__1__in_29_, chanx_1__1__out_30_, chanx_1__1__in_31_, chanx_1__1__out_32_, chanx_1__1__in_33_, chanx_1__1__out_34_, chanx_1__1__in_35_, chanx_1__1__out_36_, chanx_1__1__in_37_, chanx_1__1__out_38_, chanx_1__1__in_39_, chanx_1__1__out_40_, chanx_1__1__in_41_, chanx_1__1__out_42_, chanx_1__1__in_43_, chanx_1__1__out_44_, chanx_1__1__in_45_, chanx_1__1__out_46_, chanx_1__1__in_47_, chanx_1__1__out_48_, chanx_1__1__in_49_, chanx_1__1__out_50_, chanx_1__1__in_51_, chanx_1__1__out_52_, chanx_1__1__in_53_, chanx_1__1__out_54_, chanx_1__1__in_55_, chanx_1__1__out_56_, chanx_1__1__in_57_, chanx_1__1__out_58_, chanx_1__1__in_59_, chanx_1__1__out_60_, chanx_1__1__in_61_, chanx_1__1__out_62_, chanx_1__1__in_63_, chanx_1__1__out_64_, chanx_1__1__in_65_, chanx_1__1__out_66_, chanx_1__1__in_67_, chanx_1__1__out_68_, chanx_1__1__in_69_, chanx_1__1__out_70_, chanx_1__1__in_71_, chanx_1__1__out_72_, chanx_1__1__in_73_, chanx_1__1__out_74_, chanx_1__1__in_75_, chanx_1__1__out_76_, chanx_1__1__in_77_, chanx_1__1__out_78_, chanx_1__1__in_79_, chanx_1__1__out_80_, chanx_1__1__in_81_, chanx_1__1__out_82_, chanx_1__1__in_83_, chanx_1__1__out_84_, chanx_1__1__in_85_, chanx_1__1__out_86_, chanx_1__1__in_87_, chanx_1__1__out_88_, chanx_1__1__in_89_, chanx_1__1__out_90_, chanx_1__1__in_91_, chanx_1__1__out_92_, chanx_1__1__in_93_, chanx_1__1__out_94_, chanx_1__1__in_95_, chanx_1__1__out_96_, chanx_1__1__in_97_, chanx_1__1__out_98_, chanx_1__1__in_99_, -//----- right side inputs: CLB output pins ----- - grid_1__2__pin_0__2__1_, grid_1__2__pin_0__2__3_, grid_1__2__pin_0__2__5_, grid_1__2__pin_0__2__7_, grid_1__2__pin_0__2__9_, grid_1__2__pin_0__2__11_, grid_1__2__pin_0__2__13_, grid_1__2__pin_0__2__15_, grid_1__1__pin_0__0__40_, grid_1__1__pin_0__0__44_, grid_1__1__pin_0__0__48_, -//----- bottom side channel ports----- -chany_0__1__in_0_, chany_0__1__out_1_, chany_0__1__in_2_, chany_0__1__out_3_, chany_0__1__in_4_, chany_0__1__out_5_, chany_0__1__in_6_, chany_0__1__out_7_, chany_0__1__in_8_, chany_0__1__out_9_, chany_0__1__in_10_, chany_0__1__out_11_, chany_0__1__in_12_, chany_0__1__out_13_, chany_0__1__in_14_, chany_0__1__out_15_, chany_0__1__in_16_, chany_0__1__out_17_, chany_0__1__in_18_, chany_0__1__out_19_, chany_0__1__in_20_, chany_0__1__out_21_, chany_0__1__in_22_, chany_0__1__out_23_, chany_0__1__in_24_, chany_0__1__out_25_, chany_0__1__in_26_, chany_0__1__out_27_, chany_0__1__in_28_, chany_0__1__out_29_, chany_0__1__in_30_, chany_0__1__out_31_, chany_0__1__in_32_, chany_0__1__out_33_, chany_0__1__in_34_, chany_0__1__out_35_, chany_0__1__in_36_, chany_0__1__out_37_, chany_0__1__in_38_, chany_0__1__out_39_, chany_0__1__in_40_, chany_0__1__out_41_, chany_0__1__in_42_, chany_0__1__out_43_, chany_0__1__in_44_, chany_0__1__out_45_, chany_0__1__in_46_, chany_0__1__out_47_, chany_0__1__in_48_, chany_0__1__out_49_, chany_0__1__in_50_, chany_0__1__out_51_, chany_0__1__in_52_, chany_0__1__out_53_, chany_0__1__in_54_, chany_0__1__out_55_, chany_0__1__in_56_, chany_0__1__out_57_, chany_0__1__in_58_, chany_0__1__out_59_, chany_0__1__in_60_, chany_0__1__out_61_, chany_0__1__in_62_, chany_0__1__out_63_, chany_0__1__in_64_, chany_0__1__out_65_, chany_0__1__in_66_, chany_0__1__out_67_, chany_0__1__in_68_, chany_0__1__out_69_, chany_0__1__in_70_, chany_0__1__out_71_, chany_0__1__in_72_, chany_0__1__out_73_, chany_0__1__in_74_, chany_0__1__out_75_, chany_0__1__in_76_, chany_0__1__out_77_, chany_0__1__in_78_, chany_0__1__out_79_, chany_0__1__in_80_, chany_0__1__out_81_, chany_0__1__in_82_, chany_0__1__out_83_, chany_0__1__in_84_, chany_0__1__out_85_, chany_0__1__in_86_, chany_0__1__out_87_, chany_0__1__in_88_, chany_0__1__out_89_, chany_0__1__in_90_, chany_0__1__out_91_, chany_0__1__in_92_, chany_0__1__out_93_, chany_0__1__in_94_, chany_0__1__out_95_, chany_0__1__in_96_, chany_0__1__out_97_, chany_0__1__in_98_, chany_0__1__out_99_, -//----- bottom side inputs: CLB output pins ----- - grid_1__1__pin_0__3__43_, grid_1__1__pin_0__3__47_, grid_0__1__pin_0__1__1_, grid_0__1__pin_0__1__3_, grid_0__1__pin_0__1__5_, grid_0__1__pin_0__1__7_, grid_0__1__pin_0__1__9_, grid_0__1__pin_0__1__11_, grid_0__1__pin_0__1__13_, grid_0__1__pin_0__1__15_, -//----- left side channel ports----- - -//----- left side inputs: CLB output pins ----- - -sram_blwl_bl[100:209] , -sram_blwl_wl[100:209] , -sram_blwl_blb[100:209] ); -//----- END call module Switch blocks [0][1] ----- - -//----- BEGIN call module Switch blocks [1][0] ----- -sb_1__0_ sb_1__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side channel ports----- -chany_1__1__out_0_, chany_1__1__in_1_, chany_1__1__out_2_, chany_1__1__in_3_, chany_1__1__out_4_, chany_1__1__in_5_, chany_1__1__out_6_, chany_1__1__in_7_, chany_1__1__out_8_, chany_1__1__in_9_, chany_1__1__out_10_, chany_1__1__in_11_, chany_1__1__out_12_, chany_1__1__in_13_, chany_1__1__out_14_, chany_1__1__in_15_, chany_1__1__out_16_, chany_1__1__in_17_, chany_1__1__out_18_, chany_1__1__in_19_, chany_1__1__out_20_, chany_1__1__in_21_, chany_1__1__out_22_, chany_1__1__in_23_, chany_1__1__out_24_, chany_1__1__in_25_, chany_1__1__out_26_, chany_1__1__in_27_, chany_1__1__out_28_, chany_1__1__in_29_, chany_1__1__out_30_, chany_1__1__in_31_, chany_1__1__out_32_, chany_1__1__in_33_, chany_1__1__out_34_, chany_1__1__in_35_, chany_1__1__out_36_, chany_1__1__in_37_, chany_1__1__out_38_, chany_1__1__in_39_, chany_1__1__out_40_, chany_1__1__in_41_, chany_1__1__out_42_, chany_1__1__in_43_, chany_1__1__out_44_, chany_1__1__in_45_, chany_1__1__out_46_, chany_1__1__in_47_, chany_1__1__out_48_, chany_1__1__in_49_, chany_1__1__out_50_, chany_1__1__in_51_, chany_1__1__out_52_, chany_1__1__in_53_, chany_1__1__out_54_, chany_1__1__in_55_, chany_1__1__out_56_, chany_1__1__in_57_, chany_1__1__out_58_, chany_1__1__in_59_, chany_1__1__out_60_, chany_1__1__in_61_, chany_1__1__out_62_, chany_1__1__in_63_, chany_1__1__out_64_, chany_1__1__in_65_, chany_1__1__out_66_, chany_1__1__in_67_, chany_1__1__out_68_, chany_1__1__in_69_, chany_1__1__out_70_, chany_1__1__in_71_, chany_1__1__out_72_, chany_1__1__in_73_, chany_1__1__out_74_, chany_1__1__in_75_, chany_1__1__out_76_, chany_1__1__in_77_, chany_1__1__out_78_, chany_1__1__in_79_, chany_1__1__out_80_, chany_1__1__in_81_, chany_1__1__out_82_, chany_1__1__in_83_, chany_1__1__out_84_, chany_1__1__in_85_, chany_1__1__out_86_, chany_1__1__in_87_, chany_1__1__out_88_, chany_1__1__in_89_, chany_1__1__out_90_, chany_1__1__in_91_, chany_1__1__out_92_, chany_1__1__in_93_, chany_1__1__out_94_, chany_1__1__in_95_, chany_1__1__out_96_, chany_1__1__in_97_, chany_1__1__out_98_, chany_1__1__in_99_, -//----- top side inputs: CLB output pins ----- - grid_1__1__pin_0__1__41_, grid_1__1__pin_0__1__45_, grid_1__1__pin_0__1__49_, grid_2__1__pin_0__3__1_, grid_2__1__pin_0__3__3_, grid_2__1__pin_0__3__5_, grid_2__1__pin_0__3__7_, grid_2__1__pin_0__3__9_, grid_2__1__pin_0__3__11_, grid_2__1__pin_0__3__13_, grid_2__1__pin_0__3__15_, -//----- right side channel ports----- - -//----- right side inputs: CLB output pins ----- - -//----- bottom side channel ports----- - -//----- bottom side inputs: CLB output pins ----- - -//----- left side channel ports----- -chanx_1__0__in_0_, chanx_1__0__out_1_, chanx_1__0__in_2_, chanx_1__0__out_3_, chanx_1__0__in_4_, chanx_1__0__out_5_, chanx_1__0__in_6_, chanx_1__0__out_7_, chanx_1__0__in_8_, chanx_1__0__out_9_, chanx_1__0__in_10_, chanx_1__0__out_11_, chanx_1__0__in_12_, chanx_1__0__out_13_, chanx_1__0__in_14_, chanx_1__0__out_15_, chanx_1__0__in_16_, chanx_1__0__out_17_, chanx_1__0__in_18_, chanx_1__0__out_19_, chanx_1__0__in_20_, chanx_1__0__out_21_, chanx_1__0__in_22_, chanx_1__0__out_23_, chanx_1__0__in_24_, chanx_1__0__out_25_, chanx_1__0__in_26_, chanx_1__0__out_27_, chanx_1__0__in_28_, chanx_1__0__out_29_, chanx_1__0__in_30_, chanx_1__0__out_31_, chanx_1__0__in_32_, chanx_1__0__out_33_, chanx_1__0__in_34_, chanx_1__0__out_35_, chanx_1__0__in_36_, chanx_1__0__out_37_, chanx_1__0__in_38_, chanx_1__0__out_39_, chanx_1__0__in_40_, chanx_1__0__out_41_, chanx_1__0__in_42_, chanx_1__0__out_43_, chanx_1__0__in_44_, chanx_1__0__out_45_, chanx_1__0__in_46_, chanx_1__0__out_47_, chanx_1__0__in_48_, chanx_1__0__out_49_, chanx_1__0__in_50_, chanx_1__0__out_51_, chanx_1__0__in_52_, chanx_1__0__out_53_, chanx_1__0__in_54_, chanx_1__0__out_55_, chanx_1__0__in_56_, chanx_1__0__out_57_, chanx_1__0__in_58_, chanx_1__0__out_59_, chanx_1__0__in_60_, chanx_1__0__out_61_, chanx_1__0__in_62_, chanx_1__0__out_63_, chanx_1__0__in_64_, chanx_1__0__out_65_, chanx_1__0__in_66_, chanx_1__0__out_67_, chanx_1__0__in_68_, chanx_1__0__out_69_, chanx_1__0__in_70_, chanx_1__0__out_71_, chanx_1__0__in_72_, chanx_1__0__out_73_, chanx_1__0__in_74_, chanx_1__0__out_75_, chanx_1__0__in_76_, chanx_1__0__out_77_, chanx_1__0__in_78_, chanx_1__0__out_79_, chanx_1__0__in_80_, chanx_1__0__out_81_, chanx_1__0__in_82_, chanx_1__0__out_83_, chanx_1__0__in_84_, chanx_1__0__out_85_, chanx_1__0__in_86_, chanx_1__0__out_87_, chanx_1__0__in_88_, chanx_1__0__out_89_, chanx_1__0__in_90_, chanx_1__0__out_91_, chanx_1__0__in_92_, chanx_1__0__out_93_, chanx_1__0__in_94_, chanx_1__0__out_95_, chanx_1__0__in_96_, chanx_1__0__out_97_, chanx_1__0__in_98_, chanx_1__0__out_99_, -//----- left side inputs: CLB output pins ----- - grid_1__1__pin_0__2__42_, grid_1__1__pin_0__2__46_, grid_1__0__pin_0__0__1_, grid_1__0__pin_0__0__3_, grid_1__0__pin_0__0__5_, grid_1__0__pin_0__0__7_, grid_1__0__pin_0__0__9_, grid_1__0__pin_0__0__11_, grid_1__0__pin_0__0__13_, grid_1__0__pin_0__0__15_, -sram_blwl_bl[210:319] , -sram_blwl_wl[210:319] , -sram_blwl_blb[210:319] ); -//----- END call module Switch blocks [1][0] ----- - -//----- BEGIN call module Switch blocks [1][1] ----- -sb_1__1_ sb_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -//----- top side channel ports----- - -//----- top side inputs: CLB output pins ----- - -//----- right side channel ports----- - -//----- right side inputs: CLB output pins ----- - -//----- bottom side channel ports----- -chany_1__1__in_0_, chany_1__1__out_1_, chany_1__1__in_2_, chany_1__1__out_3_, chany_1__1__in_4_, chany_1__1__out_5_, chany_1__1__in_6_, chany_1__1__out_7_, chany_1__1__in_8_, chany_1__1__out_9_, chany_1__1__in_10_, chany_1__1__out_11_, chany_1__1__in_12_, chany_1__1__out_13_, chany_1__1__in_14_, chany_1__1__out_15_, chany_1__1__in_16_, chany_1__1__out_17_, chany_1__1__in_18_, chany_1__1__out_19_, chany_1__1__in_20_, chany_1__1__out_21_, chany_1__1__in_22_, chany_1__1__out_23_, chany_1__1__in_24_, chany_1__1__out_25_, chany_1__1__in_26_, chany_1__1__out_27_, chany_1__1__in_28_, chany_1__1__out_29_, chany_1__1__in_30_, chany_1__1__out_31_, chany_1__1__in_32_, chany_1__1__out_33_, chany_1__1__in_34_, chany_1__1__out_35_, chany_1__1__in_36_, chany_1__1__out_37_, chany_1__1__in_38_, chany_1__1__out_39_, chany_1__1__in_40_, chany_1__1__out_41_, chany_1__1__in_42_, chany_1__1__out_43_, chany_1__1__in_44_, chany_1__1__out_45_, chany_1__1__in_46_, chany_1__1__out_47_, chany_1__1__in_48_, chany_1__1__out_49_, chany_1__1__in_50_, chany_1__1__out_51_, chany_1__1__in_52_, chany_1__1__out_53_, chany_1__1__in_54_, chany_1__1__out_55_, chany_1__1__in_56_, chany_1__1__out_57_, chany_1__1__in_58_, chany_1__1__out_59_, chany_1__1__in_60_, chany_1__1__out_61_, chany_1__1__in_62_, chany_1__1__out_63_, chany_1__1__in_64_, chany_1__1__out_65_, chany_1__1__in_66_, chany_1__1__out_67_, chany_1__1__in_68_, chany_1__1__out_69_, chany_1__1__in_70_, chany_1__1__out_71_, chany_1__1__in_72_, chany_1__1__out_73_, chany_1__1__in_74_, chany_1__1__out_75_, chany_1__1__in_76_, chany_1__1__out_77_, chany_1__1__in_78_, chany_1__1__out_79_, chany_1__1__in_80_, chany_1__1__out_81_, chany_1__1__in_82_, chany_1__1__out_83_, chany_1__1__in_84_, chany_1__1__out_85_, chany_1__1__in_86_, chany_1__1__out_87_, chany_1__1__in_88_, chany_1__1__out_89_, chany_1__1__in_90_, chany_1__1__out_91_, chany_1__1__in_92_, chany_1__1__out_93_, chany_1__1__in_94_, chany_1__1__out_95_, chany_1__1__in_96_, chany_1__1__out_97_, chany_1__1__in_98_, chany_1__1__out_99_, -//----- bottom side inputs: CLB output pins ----- - grid_2__1__pin_0__3__1_, grid_2__1__pin_0__3__3_, grid_2__1__pin_0__3__5_, grid_2__1__pin_0__3__7_, grid_2__1__pin_0__3__9_, grid_2__1__pin_0__3__11_, grid_2__1__pin_0__3__13_, grid_2__1__pin_0__3__15_, grid_1__1__pin_0__1__41_, grid_1__1__pin_0__1__45_, grid_1__1__pin_0__1__49_, -//----- left side channel ports----- -chanx_1__1__in_0_, chanx_1__1__out_1_, chanx_1__1__in_2_, chanx_1__1__out_3_, chanx_1__1__in_4_, chanx_1__1__out_5_, chanx_1__1__in_6_, chanx_1__1__out_7_, chanx_1__1__in_8_, chanx_1__1__out_9_, chanx_1__1__in_10_, chanx_1__1__out_11_, chanx_1__1__in_12_, chanx_1__1__out_13_, chanx_1__1__in_14_, chanx_1__1__out_15_, chanx_1__1__in_16_, chanx_1__1__out_17_, chanx_1__1__in_18_, chanx_1__1__out_19_, chanx_1__1__in_20_, chanx_1__1__out_21_, chanx_1__1__in_22_, chanx_1__1__out_23_, chanx_1__1__in_24_, chanx_1__1__out_25_, chanx_1__1__in_26_, chanx_1__1__out_27_, chanx_1__1__in_28_, chanx_1__1__out_29_, chanx_1__1__in_30_, chanx_1__1__out_31_, chanx_1__1__in_32_, chanx_1__1__out_33_, chanx_1__1__in_34_, chanx_1__1__out_35_, chanx_1__1__in_36_, chanx_1__1__out_37_, chanx_1__1__in_38_, chanx_1__1__out_39_, chanx_1__1__in_40_, chanx_1__1__out_41_, chanx_1__1__in_42_, chanx_1__1__out_43_, chanx_1__1__in_44_, chanx_1__1__out_45_, chanx_1__1__in_46_, chanx_1__1__out_47_, chanx_1__1__in_48_, chanx_1__1__out_49_, chanx_1__1__in_50_, chanx_1__1__out_51_, chanx_1__1__in_52_, chanx_1__1__out_53_, chanx_1__1__in_54_, chanx_1__1__out_55_, chanx_1__1__in_56_, chanx_1__1__out_57_, chanx_1__1__in_58_, chanx_1__1__out_59_, chanx_1__1__in_60_, chanx_1__1__out_61_, chanx_1__1__in_62_, chanx_1__1__out_63_, chanx_1__1__in_64_, chanx_1__1__out_65_, chanx_1__1__in_66_, chanx_1__1__out_67_, chanx_1__1__in_68_, chanx_1__1__out_69_, chanx_1__1__in_70_, chanx_1__1__out_71_, chanx_1__1__in_72_, chanx_1__1__out_73_, chanx_1__1__in_74_, chanx_1__1__out_75_, chanx_1__1__in_76_, chanx_1__1__out_77_, chanx_1__1__in_78_, chanx_1__1__out_79_, chanx_1__1__in_80_, chanx_1__1__out_81_, chanx_1__1__in_82_, chanx_1__1__out_83_, chanx_1__1__in_84_, chanx_1__1__out_85_, chanx_1__1__in_86_, chanx_1__1__out_87_, chanx_1__1__in_88_, chanx_1__1__out_89_, chanx_1__1__in_90_, chanx_1__1__out_91_, chanx_1__1__in_92_, chanx_1__1__out_93_, chanx_1__1__in_94_, chanx_1__1__out_95_, chanx_1__1__in_96_, chanx_1__1__out_97_, chanx_1__1__in_98_, chanx_1__1__out_99_, -//----- left side inputs: CLB output pins ----- - grid_1__2__pin_0__2__1_, grid_1__2__pin_0__2__3_, grid_1__2__pin_0__2__5_, grid_1__2__pin_0__2__7_, grid_1__2__pin_0__2__9_, grid_1__2__pin_0__2__11_, grid_1__2__pin_0__2__13_, grid_1__2__pin_0__2__15_, grid_1__1__pin_0__0__40_, grid_1__1__pin_0__0__44_, grid_1__1__pin_0__0__48_, -sram_blwl_bl[320:439] , -sram_blwl_wl[320:439] , -sram_blwl_blb[320:439] ); -//----- END call module Switch blocks [1][1] ----- - -//----- BEGIN CLB to CLB Direct Connections ----- -//----- END CLB to CLB Direct Connections ----- -//----- BEGIN call decoders for memory bank controller ----- -bl_decoder6to52 mem_bank_bl_decoder (en_bl, addr_bl[5:0], data_in, bl_bus[0:51]); -wl_decoder6to52 mem_bank_wl_decoder (en_wl, addr_wl[5:0], wl_bus[0:51]); -//----- END call decoders for memory bank controller ----- - -endmodule diff --git a/examples/verilog_test_example_2/lb/grid_0_1.v b/examples/verilog_test_example_2/lb/grid_0_1.v deleted file mode 100644 index 5d0752795..000000000 --- a/examples/verilog_test_example_2/lb/grid_0_1.v +++ /dev/null @@ -1,694 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Physical Logic Block [0][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Grid[0][1] type_descriptor: io[0] ----- -//----- IO Verilog module: grid_0__1__io_0__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_0__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [0:0] gfpga_pad_iopad -, -input [2626:2626] sram_blwl_bl , -input [2626:2626] sram_blwl_wl , -input [2626:2626] sram_blwl_blb ); -wire [2626:2626] sram_blwl_out ; -wire [2626:2626] sram_blwl_outb ; -wire [2626:2626] sram_blwl_2626_configbus0; -wire [2626:2626] sram_blwl_2626_configbus1; -wire [2626:2626] sram_blwl_2626_configbus0_b; -assign sram_blwl_2626_configbus0[2626:2626] = sram_blwl_bl[2626:2626] ; -assign sram_blwl_2626_configbus1[2626:2626] = sram_blwl_wl[2626:2626] ; -assign sram_blwl_2626_configbus0_b[2626:2626] = sram_blwl_blb[2626:2626] ; -iopad iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[0], sram_blwl_out[2626:2626] , sram_blwl_outb[2626:2626] ); -sram6T_blwl sram_blwl_2626_ (sram_blwl_out[2626], sram_blwl_out[2626], sram_blwl_outb[2626], sram_blwl_2626_configbus0[2626:2626], sram_blwl_2626_configbus1[2626:2626] , sram_blwl_2626_configbus0_b[2626:2626] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_0__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_0__mode_io_phy_ ----- -module grid_0__1__io_0__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [0:0] gfpga_pad_iopad , -input [2626:2626] sram_blwl_bl , -input [2626:2626] sram_blwl_wl , -input [2626:2626] sram_blwl_blb ); -grid_0__1__io_0__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[0:0] , -sram_blwl_bl[2626:2626] , -sram_blwl_wl[2626:2626] , -sram_blwl_blb[2626:2626] ); -direct_interc direct_interc_180_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_181_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_0__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[1] ----- -//----- IO Verilog module: grid_0__1__io_1__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_1__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [1:1] gfpga_pad_iopad -, -input [2627:2627] sram_blwl_bl , -input [2627:2627] sram_blwl_wl , -input [2627:2627] sram_blwl_blb ); -wire [2627:2627] sram_blwl_out ; -wire [2627:2627] sram_blwl_outb ; -wire [2627:2627] sram_blwl_2627_configbus0; -wire [2627:2627] sram_blwl_2627_configbus1; -wire [2627:2627] sram_blwl_2627_configbus0_b; -assign sram_blwl_2627_configbus0[2627:2627] = sram_blwl_bl[2627:2627] ; -assign sram_blwl_2627_configbus1[2627:2627] = sram_blwl_wl[2627:2627] ; -assign sram_blwl_2627_configbus0_b[2627:2627] = sram_blwl_blb[2627:2627] ; -iopad iopad_1_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[1], sram_blwl_out[2627:2627] , sram_blwl_outb[2627:2627] ); -sram6T_blwl sram_blwl_2627_ (sram_blwl_out[2627], sram_blwl_out[2627], sram_blwl_outb[2627], sram_blwl_2627_configbus0[2627:2627], sram_blwl_2627_configbus1[2627:2627] , sram_blwl_2627_configbus0_b[2627:2627] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_1__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_1__mode_io_phy_ ----- -module grid_0__1__io_1__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [1:1] gfpga_pad_iopad , -input [2627:2627] sram_blwl_bl , -input [2627:2627] sram_blwl_wl , -input [2627:2627] sram_blwl_blb ); -grid_0__1__io_1__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[1:1] , -sram_blwl_bl[2627:2627] , -sram_blwl_wl[2627:2627] , -sram_blwl_blb[2627:2627] ); -direct_interc direct_interc_182_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_183_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_1__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[2] ----- -//----- IO Verilog module: grid_0__1__io_2__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_2__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [2:2] gfpga_pad_iopad -, -input [2628:2628] sram_blwl_bl , -input [2628:2628] sram_blwl_wl , -input [2628:2628] sram_blwl_blb ); -wire [2628:2628] sram_blwl_out ; -wire [2628:2628] sram_blwl_outb ; -wire [2628:2628] sram_blwl_2628_configbus0; -wire [2628:2628] sram_blwl_2628_configbus1; -wire [2628:2628] sram_blwl_2628_configbus0_b; -assign sram_blwl_2628_configbus0[2628:2628] = sram_blwl_bl[2628:2628] ; -assign sram_blwl_2628_configbus1[2628:2628] = sram_blwl_wl[2628:2628] ; -assign sram_blwl_2628_configbus0_b[2628:2628] = sram_blwl_blb[2628:2628] ; -iopad iopad_2_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[2], sram_blwl_out[2628:2628] , sram_blwl_outb[2628:2628] ); -sram6T_blwl sram_blwl_2628_ (sram_blwl_out[2628], sram_blwl_out[2628], sram_blwl_outb[2628], sram_blwl_2628_configbus0[2628:2628], sram_blwl_2628_configbus1[2628:2628] , sram_blwl_2628_configbus0_b[2628:2628] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_2__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_2__mode_io_phy_ ----- -module grid_0__1__io_2__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [2:2] gfpga_pad_iopad , -input [2628:2628] sram_blwl_bl , -input [2628:2628] sram_blwl_wl , -input [2628:2628] sram_blwl_blb ); -grid_0__1__io_2__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[2:2] , -sram_blwl_bl[2628:2628] , -sram_blwl_wl[2628:2628] , -sram_blwl_blb[2628:2628] ); -direct_interc direct_interc_184_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_185_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_2__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[3] ----- -//----- IO Verilog module: grid_0__1__io_3__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_3__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [3:3] gfpga_pad_iopad -, -input [2629:2629] sram_blwl_bl , -input [2629:2629] sram_blwl_wl , -input [2629:2629] sram_blwl_blb ); -wire [2629:2629] sram_blwl_out ; -wire [2629:2629] sram_blwl_outb ; -wire [2629:2629] sram_blwl_2629_configbus0; -wire [2629:2629] sram_blwl_2629_configbus1; -wire [2629:2629] sram_blwl_2629_configbus0_b; -assign sram_blwl_2629_configbus0[2629:2629] = sram_blwl_bl[2629:2629] ; -assign sram_blwl_2629_configbus1[2629:2629] = sram_blwl_wl[2629:2629] ; -assign sram_blwl_2629_configbus0_b[2629:2629] = sram_blwl_blb[2629:2629] ; -iopad iopad_3_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[3], sram_blwl_out[2629:2629] , sram_blwl_outb[2629:2629] ); -sram6T_blwl sram_blwl_2629_ (sram_blwl_out[2629], sram_blwl_out[2629], sram_blwl_outb[2629], sram_blwl_2629_configbus0[2629:2629], sram_blwl_2629_configbus1[2629:2629] , sram_blwl_2629_configbus0_b[2629:2629] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_3__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_3__mode_io_phy_ ----- -module grid_0__1__io_3__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [3:3] gfpga_pad_iopad , -input [2629:2629] sram_blwl_bl , -input [2629:2629] sram_blwl_wl , -input [2629:2629] sram_blwl_blb ); -grid_0__1__io_3__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[3:3] , -sram_blwl_bl[2629:2629] , -sram_blwl_wl[2629:2629] , -sram_blwl_blb[2629:2629] ); -direct_interc direct_interc_186_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_187_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_3__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[4] ----- -//----- IO Verilog module: grid_0__1__io_4__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_4__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [4:4] gfpga_pad_iopad -, -input [2630:2630] sram_blwl_bl , -input [2630:2630] sram_blwl_wl , -input [2630:2630] sram_blwl_blb ); -wire [2630:2630] sram_blwl_out ; -wire [2630:2630] sram_blwl_outb ; -wire [2630:2630] sram_blwl_2630_configbus0; -wire [2630:2630] sram_blwl_2630_configbus1; -wire [2630:2630] sram_blwl_2630_configbus0_b; -assign sram_blwl_2630_configbus0[2630:2630] = sram_blwl_bl[2630:2630] ; -assign sram_blwl_2630_configbus1[2630:2630] = sram_blwl_wl[2630:2630] ; -assign sram_blwl_2630_configbus0_b[2630:2630] = sram_blwl_blb[2630:2630] ; -iopad iopad_4_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[4], sram_blwl_out[2630:2630] , sram_blwl_outb[2630:2630] ); -sram6T_blwl sram_blwl_2630_ (sram_blwl_out[2630], sram_blwl_out[2630], sram_blwl_outb[2630], sram_blwl_2630_configbus0[2630:2630], sram_blwl_2630_configbus1[2630:2630] , sram_blwl_2630_configbus0_b[2630:2630] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_4__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_4__mode_io_phy_ ----- -module grid_0__1__io_4__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [4:4] gfpga_pad_iopad , -input [2630:2630] sram_blwl_bl , -input [2630:2630] sram_blwl_wl , -input [2630:2630] sram_blwl_blb ); -grid_0__1__io_4__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[4:4] , -sram_blwl_bl[2630:2630] , -sram_blwl_wl[2630:2630] , -sram_blwl_blb[2630:2630] ); -direct_interc direct_interc_188_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_189_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_4__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[5] ----- -//----- IO Verilog module: grid_0__1__io_5__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_5__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [5:5] gfpga_pad_iopad -, -input [2631:2631] sram_blwl_bl , -input [2631:2631] sram_blwl_wl , -input [2631:2631] sram_blwl_blb ); -wire [2631:2631] sram_blwl_out ; -wire [2631:2631] sram_blwl_outb ; -wire [2631:2631] sram_blwl_2631_configbus0; -wire [2631:2631] sram_blwl_2631_configbus1; -wire [2631:2631] sram_blwl_2631_configbus0_b; -assign sram_blwl_2631_configbus0[2631:2631] = sram_blwl_bl[2631:2631] ; -assign sram_blwl_2631_configbus1[2631:2631] = sram_blwl_wl[2631:2631] ; -assign sram_blwl_2631_configbus0_b[2631:2631] = sram_blwl_blb[2631:2631] ; -iopad iopad_5_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[5], sram_blwl_out[2631:2631] , sram_blwl_outb[2631:2631] ); -sram6T_blwl sram_blwl_2631_ (sram_blwl_out[2631], sram_blwl_out[2631], sram_blwl_outb[2631], sram_blwl_2631_configbus0[2631:2631], sram_blwl_2631_configbus1[2631:2631] , sram_blwl_2631_configbus0_b[2631:2631] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_5__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_5__mode_io_phy_ ----- -module grid_0__1__io_5__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [5:5] gfpga_pad_iopad , -input [2631:2631] sram_blwl_bl , -input [2631:2631] sram_blwl_wl , -input [2631:2631] sram_blwl_blb ); -grid_0__1__io_5__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[5:5] , -sram_blwl_bl[2631:2631] , -sram_blwl_wl[2631:2631] , -sram_blwl_blb[2631:2631] ); -direct_interc direct_interc_190_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_191_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_5__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[6] ----- -//----- IO Verilog module: grid_0__1__io_6__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_6__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [6:6] gfpga_pad_iopad -, -input [2632:2632] sram_blwl_bl , -input [2632:2632] sram_blwl_wl , -input [2632:2632] sram_blwl_blb ); -wire [2632:2632] sram_blwl_out ; -wire [2632:2632] sram_blwl_outb ; -wire [2632:2632] sram_blwl_2632_configbus0; -wire [2632:2632] sram_blwl_2632_configbus1; -wire [2632:2632] sram_blwl_2632_configbus0_b; -assign sram_blwl_2632_configbus0[2632:2632] = sram_blwl_bl[2632:2632] ; -assign sram_blwl_2632_configbus1[2632:2632] = sram_blwl_wl[2632:2632] ; -assign sram_blwl_2632_configbus0_b[2632:2632] = sram_blwl_blb[2632:2632] ; -iopad iopad_6_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[6], sram_blwl_out[2632:2632] , sram_blwl_outb[2632:2632] ); -sram6T_blwl sram_blwl_2632_ (sram_blwl_out[2632], sram_blwl_out[2632], sram_blwl_outb[2632], sram_blwl_2632_configbus0[2632:2632], sram_blwl_2632_configbus1[2632:2632] , sram_blwl_2632_configbus0_b[2632:2632] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_6__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_6__mode_io_phy_ ----- -module grid_0__1__io_6__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [6:6] gfpga_pad_iopad , -input [2632:2632] sram_blwl_bl , -input [2632:2632] sram_blwl_wl , -input [2632:2632] sram_blwl_blb ); -grid_0__1__io_6__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[6:6] , -sram_blwl_bl[2632:2632] , -sram_blwl_wl[2632:2632] , -sram_blwl_blb[2632:2632] ); -direct_interc direct_interc_192_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_193_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_6__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1] type_descriptor: io[7] ----- -//----- IO Verilog module: grid_0__1__io_7__mode_io_phy__iopad_0_ ----- -module grid_0__1__io_7__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [7:7] gfpga_pad_iopad -, -input [2633:2633] sram_blwl_bl , -input [2633:2633] sram_blwl_wl , -input [2633:2633] sram_blwl_blb ); -wire [2633:2633] sram_blwl_out ; -wire [2633:2633] sram_blwl_outb ; -wire [2633:2633] sram_blwl_2633_configbus0; -wire [2633:2633] sram_blwl_2633_configbus1; -wire [2633:2633] sram_blwl_2633_configbus0_b; -assign sram_blwl_2633_configbus0[2633:2633] = sram_blwl_bl[2633:2633] ; -assign sram_blwl_2633_configbus1[2633:2633] = sram_blwl_wl[2633:2633] ; -assign sram_blwl_2633_configbus0_b[2633:2633] = sram_blwl_blb[2633:2633] ; -iopad iopad_7_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[7], sram_blwl_out[2633:2633] , sram_blwl_outb[2633:2633] ); -sram6T_blwl sram_blwl_2633_ (sram_blwl_out[2633], sram_blwl_out[2633], sram_blwl_outb[2633], sram_blwl_2633_configbus0[2633:2633], sram_blwl_2633_configbus1[2633:2633] , sram_blwl_2633_configbus0_b[2633:2633] ); -endmodule -//----- END IO Verilog module: grid_0__1__io_7__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_0__1__io_7__mode_io_phy_ ----- -module grid_0__1__io_7__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [7:7] gfpga_pad_iopad , -input [2633:2633] sram_blwl_bl , -input [2633:2633] sram_blwl_wl , -input [2633:2633] sram_blwl_blb ); -grid_0__1__io_7__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[7:7] , -sram_blwl_bl[2633:2633] , -sram_blwl_wl[2633:2633] , -sram_blwl_blb[2633:2633] ); -direct_interc direct_interc_194_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_195_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_0__1__io_7__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[0][1], Capactity: 8 ----- -//----- Top Protocol ----- -module grid_0__1_( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input right_height_0__pin_0_, -output right_height_0__pin_1_, -input right_height_0__pin_2_, -output right_height_0__pin_3_, -input right_height_0__pin_4_, -output right_height_0__pin_5_, -input right_height_0__pin_6_, -output right_height_0__pin_7_, -input right_height_0__pin_8_, -output right_height_0__pin_9_, -input right_height_0__pin_10_, -output right_height_0__pin_11_, -input right_height_0__pin_12_, -output right_height_0__pin_13_, -input right_height_0__pin_14_, -output right_height_0__pin_15_, -input [7:0] gfpga_pad_iopad , -input [2626:2633] sram_blwl_bl , -input [2626:2633] sram_blwl_wl , -input [2626:2633] sram_blwl_blb ); -grid_0__1__io_0__mode_io_phy_ grid_0__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_0_, -right_height_0__pin_1_ -//---- IOPAD ---- -, -gfpga_pad_iopad[0:0] , -//---- SRAM ---- -sram_blwl_bl[2626:2626] , -sram_blwl_wl[2626:2626] , -sram_blwl_blb[2626:2626] ); -grid_0__1__io_1__mode_io_phy_ grid_0__1__1_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_2_, -right_height_0__pin_3_ -//---- IOPAD ---- -, -gfpga_pad_iopad[1:1] , -//---- SRAM ---- -sram_blwl_bl[2627:2627] , -sram_blwl_wl[2627:2627] , -sram_blwl_blb[2627:2627] ); -grid_0__1__io_2__mode_io_phy_ grid_0__1__2_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_4_, -right_height_0__pin_5_ -//---- IOPAD ---- -, -gfpga_pad_iopad[2:2] , -//---- SRAM ---- -sram_blwl_bl[2628:2628] , -sram_blwl_wl[2628:2628] , -sram_blwl_blb[2628:2628] ); -grid_0__1__io_3__mode_io_phy_ grid_0__1__3_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_6_, -right_height_0__pin_7_ -//---- IOPAD ---- -, -gfpga_pad_iopad[3:3] , -//---- SRAM ---- -sram_blwl_bl[2629:2629] , -sram_blwl_wl[2629:2629] , -sram_blwl_blb[2629:2629] ); -grid_0__1__io_4__mode_io_phy_ grid_0__1__4_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_8_, -right_height_0__pin_9_ -//---- IOPAD ---- -, -gfpga_pad_iopad[4:4] , -//---- SRAM ---- -sram_blwl_bl[2630:2630] , -sram_blwl_wl[2630:2630] , -sram_blwl_blb[2630:2630] ); -grid_0__1__io_5__mode_io_phy_ grid_0__1__5_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_10_, -right_height_0__pin_11_ -//---- IOPAD ---- -, -gfpga_pad_iopad[5:5] , -//---- SRAM ---- -sram_blwl_bl[2631:2631] , -sram_blwl_wl[2631:2631] , -sram_blwl_blb[2631:2631] ); -grid_0__1__io_6__mode_io_phy_ grid_0__1__6_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_12_, -right_height_0__pin_13_ -//---- IOPAD ---- -, -gfpga_pad_iopad[6:6] , -//---- SRAM ---- -sram_blwl_bl[2632:2632] , -sram_blwl_wl[2632:2632] , -sram_blwl_blb[2632:2632] ); -grid_0__1__io_7__mode_io_phy_ grid_0__1__7_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -right_height_0__pin_14_, -right_height_0__pin_15_ -//---- IOPAD ---- -, -gfpga_pad_iopad[7:7] , -//---- SRAM ---- -sram_blwl_bl[2633:2633] , -sram_blwl_wl[2633:2633] , -sram_blwl_blb[2633:2633] ); -endmodule -//----- END Top Protocol ----- -//----- END Grid[0][1], Capactity: 8 ----- - diff --git a/examples/verilog_test_example_2/lb/grid_1_0.v b/examples/verilog_test_example_2/lb/grid_1_0.v deleted file mode 100644 index 5a91209e2..000000000 --- a/examples/verilog_test_example_2/lb/grid_1_0.v +++ /dev/null @@ -1,694 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Physical Logic Block [1][0] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Grid[1][0] type_descriptor: io[0] ----- -//----- IO Verilog module: grid_1__0__io_0__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_0__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [16:16] gfpga_pad_iopad -, -input [2642:2642] sram_blwl_bl , -input [2642:2642] sram_blwl_wl , -input [2642:2642] sram_blwl_blb ); -wire [2642:2642] sram_blwl_out ; -wire [2642:2642] sram_blwl_outb ; -wire [2642:2642] sram_blwl_2642_configbus0; -wire [2642:2642] sram_blwl_2642_configbus1; -wire [2642:2642] sram_blwl_2642_configbus0_b; -assign sram_blwl_2642_configbus0[2642:2642] = sram_blwl_bl[2642:2642] ; -assign sram_blwl_2642_configbus1[2642:2642] = sram_blwl_wl[2642:2642] ; -assign sram_blwl_2642_configbus0_b[2642:2642] = sram_blwl_blb[2642:2642] ; -iopad iopad_16_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[16], sram_blwl_out[2642:2642] , sram_blwl_outb[2642:2642] ); -sram6T_blwl sram_blwl_2642_ (sram_blwl_out[2642], sram_blwl_out[2642], sram_blwl_outb[2642], sram_blwl_2642_configbus0[2642:2642], sram_blwl_2642_configbus1[2642:2642] , sram_blwl_2642_configbus0_b[2642:2642] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_0__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_0__mode_io_phy_ ----- -module grid_1__0__io_0__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [16:16] gfpga_pad_iopad , -input [2642:2642] sram_blwl_bl , -input [2642:2642] sram_blwl_wl , -input [2642:2642] sram_blwl_blb ); -grid_1__0__io_0__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[16:16] , -sram_blwl_bl[2642:2642] , -sram_blwl_wl[2642:2642] , -sram_blwl_blb[2642:2642] ); -direct_interc direct_interc_212_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_213_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_0__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[1] ----- -//----- IO Verilog module: grid_1__0__io_1__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_1__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [17:17] gfpga_pad_iopad -, -input [2643:2643] sram_blwl_bl , -input [2643:2643] sram_blwl_wl , -input [2643:2643] sram_blwl_blb ); -wire [2643:2643] sram_blwl_out ; -wire [2643:2643] sram_blwl_outb ; -wire [2643:2643] sram_blwl_2643_configbus0; -wire [2643:2643] sram_blwl_2643_configbus1; -wire [2643:2643] sram_blwl_2643_configbus0_b; -assign sram_blwl_2643_configbus0[2643:2643] = sram_blwl_bl[2643:2643] ; -assign sram_blwl_2643_configbus1[2643:2643] = sram_blwl_wl[2643:2643] ; -assign sram_blwl_2643_configbus0_b[2643:2643] = sram_blwl_blb[2643:2643] ; -iopad iopad_17_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[17], sram_blwl_out[2643:2643] , sram_blwl_outb[2643:2643] ); -sram6T_blwl sram_blwl_2643_ (sram_blwl_out[2643], sram_blwl_out[2643], sram_blwl_outb[2643], sram_blwl_2643_configbus0[2643:2643], sram_blwl_2643_configbus1[2643:2643] , sram_blwl_2643_configbus0_b[2643:2643] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_1__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_1__mode_io_phy_ ----- -module grid_1__0__io_1__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [17:17] gfpga_pad_iopad , -input [2643:2643] sram_blwl_bl , -input [2643:2643] sram_blwl_wl , -input [2643:2643] sram_blwl_blb ); -grid_1__0__io_1__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[17:17] , -sram_blwl_bl[2643:2643] , -sram_blwl_wl[2643:2643] , -sram_blwl_blb[2643:2643] ); -direct_interc direct_interc_214_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_215_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_1__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[2] ----- -//----- IO Verilog module: grid_1__0__io_2__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_2__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [18:18] gfpga_pad_iopad -, -input [2644:2644] sram_blwl_bl , -input [2644:2644] sram_blwl_wl , -input [2644:2644] sram_blwl_blb ); -wire [2644:2644] sram_blwl_out ; -wire [2644:2644] sram_blwl_outb ; -wire [2644:2644] sram_blwl_2644_configbus0; -wire [2644:2644] sram_blwl_2644_configbus1; -wire [2644:2644] sram_blwl_2644_configbus0_b; -assign sram_blwl_2644_configbus0[2644:2644] = sram_blwl_bl[2644:2644] ; -assign sram_blwl_2644_configbus1[2644:2644] = sram_blwl_wl[2644:2644] ; -assign sram_blwl_2644_configbus0_b[2644:2644] = sram_blwl_blb[2644:2644] ; -iopad iopad_18_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[18], sram_blwl_out[2644:2644] , sram_blwl_outb[2644:2644] ); -sram6T_blwl sram_blwl_2644_ (sram_blwl_out[2644], sram_blwl_out[2644], sram_blwl_outb[2644], sram_blwl_2644_configbus0[2644:2644], sram_blwl_2644_configbus1[2644:2644] , sram_blwl_2644_configbus0_b[2644:2644] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_2__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_2__mode_io_phy_ ----- -module grid_1__0__io_2__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [18:18] gfpga_pad_iopad , -input [2644:2644] sram_blwl_bl , -input [2644:2644] sram_blwl_wl , -input [2644:2644] sram_blwl_blb ); -grid_1__0__io_2__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[18:18] , -sram_blwl_bl[2644:2644] , -sram_blwl_wl[2644:2644] , -sram_blwl_blb[2644:2644] ); -direct_interc direct_interc_216_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_217_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_2__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[3] ----- -//----- IO Verilog module: grid_1__0__io_3__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_3__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [19:19] gfpga_pad_iopad -, -input [2645:2645] sram_blwl_bl , -input [2645:2645] sram_blwl_wl , -input [2645:2645] sram_blwl_blb ); -wire [2645:2645] sram_blwl_out ; -wire [2645:2645] sram_blwl_outb ; -wire [2645:2645] sram_blwl_2645_configbus0; -wire [2645:2645] sram_blwl_2645_configbus1; -wire [2645:2645] sram_blwl_2645_configbus0_b; -assign sram_blwl_2645_configbus0[2645:2645] = sram_blwl_bl[2645:2645] ; -assign sram_blwl_2645_configbus1[2645:2645] = sram_blwl_wl[2645:2645] ; -assign sram_blwl_2645_configbus0_b[2645:2645] = sram_blwl_blb[2645:2645] ; -iopad iopad_19_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[19], sram_blwl_out[2645:2645] , sram_blwl_outb[2645:2645] ); -sram6T_blwl sram_blwl_2645_ (sram_blwl_out[2645], sram_blwl_out[2645], sram_blwl_outb[2645], sram_blwl_2645_configbus0[2645:2645], sram_blwl_2645_configbus1[2645:2645] , sram_blwl_2645_configbus0_b[2645:2645] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_3__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_3__mode_io_phy_ ----- -module grid_1__0__io_3__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [19:19] gfpga_pad_iopad , -input [2645:2645] sram_blwl_bl , -input [2645:2645] sram_blwl_wl , -input [2645:2645] sram_blwl_blb ); -grid_1__0__io_3__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[19:19] , -sram_blwl_bl[2645:2645] , -sram_blwl_wl[2645:2645] , -sram_blwl_blb[2645:2645] ); -direct_interc direct_interc_218_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_219_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_3__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[4] ----- -//----- IO Verilog module: grid_1__0__io_4__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_4__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [20:20] gfpga_pad_iopad -, -input [2646:2646] sram_blwl_bl , -input [2646:2646] sram_blwl_wl , -input [2646:2646] sram_blwl_blb ); -wire [2646:2646] sram_blwl_out ; -wire [2646:2646] sram_blwl_outb ; -wire [2646:2646] sram_blwl_2646_configbus0; -wire [2646:2646] sram_blwl_2646_configbus1; -wire [2646:2646] sram_blwl_2646_configbus0_b; -assign sram_blwl_2646_configbus0[2646:2646] = sram_blwl_bl[2646:2646] ; -assign sram_blwl_2646_configbus1[2646:2646] = sram_blwl_wl[2646:2646] ; -assign sram_blwl_2646_configbus0_b[2646:2646] = sram_blwl_blb[2646:2646] ; -iopad iopad_20_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[20], sram_blwl_out[2646:2646] , sram_blwl_outb[2646:2646] ); -sram6T_blwl sram_blwl_2646_ (sram_blwl_out[2646], sram_blwl_out[2646], sram_blwl_outb[2646], sram_blwl_2646_configbus0[2646:2646], sram_blwl_2646_configbus1[2646:2646] , sram_blwl_2646_configbus0_b[2646:2646] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_4__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_4__mode_io_phy_ ----- -module grid_1__0__io_4__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [20:20] gfpga_pad_iopad , -input [2646:2646] sram_blwl_bl , -input [2646:2646] sram_blwl_wl , -input [2646:2646] sram_blwl_blb ); -grid_1__0__io_4__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[20:20] , -sram_blwl_bl[2646:2646] , -sram_blwl_wl[2646:2646] , -sram_blwl_blb[2646:2646] ); -direct_interc direct_interc_220_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_221_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_4__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[5] ----- -//----- IO Verilog module: grid_1__0__io_5__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_5__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [21:21] gfpga_pad_iopad -, -input [2647:2647] sram_blwl_bl , -input [2647:2647] sram_blwl_wl , -input [2647:2647] sram_blwl_blb ); -wire [2647:2647] sram_blwl_out ; -wire [2647:2647] sram_blwl_outb ; -wire [2647:2647] sram_blwl_2647_configbus0; -wire [2647:2647] sram_blwl_2647_configbus1; -wire [2647:2647] sram_blwl_2647_configbus0_b; -assign sram_blwl_2647_configbus0[2647:2647] = sram_blwl_bl[2647:2647] ; -assign sram_blwl_2647_configbus1[2647:2647] = sram_blwl_wl[2647:2647] ; -assign sram_blwl_2647_configbus0_b[2647:2647] = sram_blwl_blb[2647:2647] ; -iopad iopad_21_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[21], sram_blwl_out[2647:2647] , sram_blwl_outb[2647:2647] ); -sram6T_blwl sram_blwl_2647_ (sram_blwl_out[2647], sram_blwl_out[2647], sram_blwl_outb[2647], sram_blwl_2647_configbus0[2647:2647], sram_blwl_2647_configbus1[2647:2647] , sram_blwl_2647_configbus0_b[2647:2647] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_5__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_5__mode_io_phy_ ----- -module grid_1__0__io_5__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [21:21] gfpga_pad_iopad , -input [2647:2647] sram_blwl_bl , -input [2647:2647] sram_blwl_wl , -input [2647:2647] sram_blwl_blb ); -grid_1__0__io_5__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[21:21] , -sram_blwl_bl[2647:2647] , -sram_blwl_wl[2647:2647] , -sram_blwl_blb[2647:2647] ); -direct_interc direct_interc_222_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_223_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_5__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[6] ----- -//----- IO Verilog module: grid_1__0__io_6__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_6__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [22:22] gfpga_pad_iopad -, -input [2648:2648] sram_blwl_bl , -input [2648:2648] sram_blwl_wl , -input [2648:2648] sram_blwl_blb ); -wire [2648:2648] sram_blwl_out ; -wire [2648:2648] sram_blwl_outb ; -wire [2648:2648] sram_blwl_2648_configbus0; -wire [2648:2648] sram_blwl_2648_configbus1; -wire [2648:2648] sram_blwl_2648_configbus0_b; -assign sram_blwl_2648_configbus0[2648:2648] = sram_blwl_bl[2648:2648] ; -assign sram_blwl_2648_configbus1[2648:2648] = sram_blwl_wl[2648:2648] ; -assign sram_blwl_2648_configbus0_b[2648:2648] = sram_blwl_blb[2648:2648] ; -iopad iopad_22_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[22], sram_blwl_out[2648:2648] , sram_blwl_outb[2648:2648] ); -sram6T_blwl sram_blwl_2648_ (sram_blwl_out[2648], sram_blwl_out[2648], sram_blwl_outb[2648], sram_blwl_2648_configbus0[2648:2648], sram_blwl_2648_configbus1[2648:2648] , sram_blwl_2648_configbus0_b[2648:2648] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_6__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_6__mode_io_phy_ ----- -module grid_1__0__io_6__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [22:22] gfpga_pad_iopad , -input [2648:2648] sram_blwl_bl , -input [2648:2648] sram_blwl_wl , -input [2648:2648] sram_blwl_blb ); -grid_1__0__io_6__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[22:22] , -sram_blwl_bl[2648:2648] , -sram_blwl_wl[2648:2648] , -sram_blwl_blb[2648:2648] ); -direct_interc direct_interc_224_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_225_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_6__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0] type_descriptor: io[7] ----- -//----- IO Verilog module: grid_1__0__io_7__mode_io_phy__iopad_0_ ----- -module grid_1__0__io_7__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [23:23] gfpga_pad_iopad -, -input [2649:2649] sram_blwl_bl , -input [2649:2649] sram_blwl_wl , -input [2649:2649] sram_blwl_blb ); -wire [2649:2649] sram_blwl_out ; -wire [2649:2649] sram_blwl_outb ; -wire [2649:2649] sram_blwl_2649_configbus0; -wire [2649:2649] sram_blwl_2649_configbus1; -wire [2649:2649] sram_blwl_2649_configbus0_b; -assign sram_blwl_2649_configbus0[2649:2649] = sram_blwl_bl[2649:2649] ; -assign sram_blwl_2649_configbus1[2649:2649] = sram_blwl_wl[2649:2649] ; -assign sram_blwl_2649_configbus0_b[2649:2649] = sram_blwl_blb[2649:2649] ; -iopad iopad_23_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[23], sram_blwl_out[2649:2649] , sram_blwl_outb[2649:2649] ); -sram6T_blwl sram_blwl_2649_ (sram_blwl_out[2649], sram_blwl_out[2649], sram_blwl_outb[2649], sram_blwl_2649_configbus0[2649:2649], sram_blwl_2649_configbus1[2649:2649] , sram_blwl_2649_configbus0_b[2649:2649] ); -endmodule -//----- END IO Verilog module: grid_1__0__io_7__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__0__io_7__mode_io_phy_ ----- -module grid_1__0__io_7__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [23:23] gfpga_pad_iopad , -input [2649:2649] sram_blwl_bl , -input [2649:2649] sram_blwl_wl , -input [2649:2649] sram_blwl_blb ); -grid_1__0__io_7__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[23:23] , -sram_blwl_bl[2649:2649] , -sram_blwl_wl[2649:2649] , -sram_blwl_blb[2649:2649] ); -direct_interc direct_interc_226_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_227_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__0__io_7__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][0], Capactity: 8 ----- -//----- Top Protocol ----- -module grid_1__0_( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input top_height_0__pin_0_, -output top_height_0__pin_1_, -input top_height_0__pin_2_, -output top_height_0__pin_3_, -input top_height_0__pin_4_, -output top_height_0__pin_5_, -input top_height_0__pin_6_, -output top_height_0__pin_7_, -input top_height_0__pin_8_, -output top_height_0__pin_9_, -input top_height_0__pin_10_, -output top_height_0__pin_11_, -input top_height_0__pin_12_, -output top_height_0__pin_13_, -input top_height_0__pin_14_, -output top_height_0__pin_15_, -input [23:16] gfpga_pad_iopad , -input [2642:2649] sram_blwl_bl , -input [2642:2649] sram_blwl_wl , -input [2642:2649] sram_blwl_blb ); -grid_1__0__io_0__mode_io_phy_ grid_1__0__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_0_, -top_height_0__pin_1_ -//---- IOPAD ---- -, -gfpga_pad_iopad[16:16] , -//---- SRAM ---- -sram_blwl_bl[2642:2642] , -sram_blwl_wl[2642:2642] , -sram_blwl_blb[2642:2642] ); -grid_1__0__io_1__mode_io_phy_ grid_1__0__1_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_2_, -top_height_0__pin_3_ -//---- IOPAD ---- -, -gfpga_pad_iopad[17:17] , -//---- SRAM ---- -sram_blwl_bl[2643:2643] , -sram_blwl_wl[2643:2643] , -sram_blwl_blb[2643:2643] ); -grid_1__0__io_2__mode_io_phy_ grid_1__0__2_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_4_, -top_height_0__pin_5_ -//---- IOPAD ---- -, -gfpga_pad_iopad[18:18] , -//---- SRAM ---- -sram_blwl_bl[2644:2644] , -sram_blwl_wl[2644:2644] , -sram_blwl_blb[2644:2644] ); -grid_1__0__io_3__mode_io_phy_ grid_1__0__3_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_6_, -top_height_0__pin_7_ -//---- IOPAD ---- -, -gfpga_pad_iopad[19:19] , -//---- SRAM ---- -sram_blwl_bl[2645:2645] , -sram_blwl_wl[2645:2645] , -sram_blwl_blb[2645:2645] ); -grid_1__0__io_4__mode_io_phy_ grid_1__0__4_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_8_, -top_height_0__pin_9_ -//---- IOPAD ---- -, -gfpga_pad_iopad[20:20] , -//---- SRAM ---- -sram_blwl_bl[2646:2646] , -sram_blwl_wl[2646:2646] , -sram_blwl_blb[2646:2646] ); -grid_1__0__io_5__mode_io_phy_ grid_1__0__5_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_10_, -top_height_0__pin_11_ -//---- IOPAD ---- -, -gfpga_pad_iopad[21:21] , -//---- SRAM ---- -sram_blwl_bl[2647:2647] , -sram_blwl_wl[2647:2647] , -sram_blwl_blb[2647:2647] ); -grid_1__0__io_6__mode_io_phy_ grid_1__0__6_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_12_, -top_height_0__pin_13_ -//---- IOPAD ---- -, -gfpga_pad_iopad[22:22] , -//---- SRAM ---- -sram_blwl_bl[2648:2648] , -sram_blwl_wl[2648:2648] , -sram_blwl_blb[2648:2648] ); -grid_1__0__io_7__mode_io_phy_ grid_1__0__7_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_14_, -top_height_0__pin_15_ -//---- IOPAD ---- -, -gfpga_pad_iopad[23:23] , -//---- SRAM ---- -sram_blwl_bl[2649:2649] , -sram_blwl_wl[2649:2649] , -sram_blwl_blb[2649:2649] ); -endmodule -//----- END Top Protocol ----- -//----- END Grid[1][0], Capactity: 8 ----- - diff --git a/examples/verilog_test_example_2/lb/grid_1_1.v b/examples/verilog_test_example_2/lb/grid_1_1.v deleted file mode 100644 index 7ccfc2bfb..000000000 --- a/examples/verilog_test_example_2/lb/grid_1_1.v +++ /dev/null @@ -1,11197 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Logic Block [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Grid[1][1] type_descriptor: clb[0] ----- -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ( -input wire lut6_0___in_0_, -input wire lut6_0___in_1_, -input wire lut6_0___in_2_, -input wire lut6_0___in_3_, -input wire lut6_0___in_4_, -input wire lut6_0___in_5_, -output wire lut6_0___out_0_, -input [1016:1079] sram_blwl_bl , -input [1016:1079] sram_blwl_wl , -input [1016:1079] sram_blwl_blb ); -wire [0:5] lut6_0___in; -assign lut6_0___in[0] = lut6_0___in_0_; -assign lut6_0___in[1] = lut6_0___in_1_; -assign lut6_0___in[2] = lut6_0___in_2_; -assign lut6_0___in[3] = lut6_0___in_3_; -assign lut6_0___in[4] = lut6_0___in_4_; -assign lut6_0___in[5] = lut6_0___in_5_; -wire [0:0] lut6_0___out; -assign lut6_0___out_0_ = lut6_0___out[0]; -wire [1016:1079] sram_blwl_out ; -wire [1016:1079] sram_blwl_outb ; -lut6 lut6_0_ ( -//----- Input and output ports ----- - lut6_0___in[0:5] , lut6_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[1016:1079] , sram_blwl_outb[1016:1079] ); -//----- Truth Table for LUT[0], size=6. ----- -//----- SRAM bits for LUT[0], size=6, num_sram=64. ----- -//-----0000000000000000000000000000000000000000000000000000000000000000----- -wire [1016:1016] sram_blwl_1016_configbus0; -wire [1016:1016] sram_blwl_1016_configbus1; -wire [1016:1016] sram_blwl_1016_configbus0_b; -assign sram_blwl_1016_configbus0[1016:1016] = sram_blwl_bl[1016:1016] ; -assign sram_blwl_1016_configbus1[1016:1016] = sram_blwl_wl[1016:1016] ; -assign sram_blwl_1016_configbus0_b[1016:1016] = sram_blwl_blb[1016:1016] ; -sram6T_blwl sram_blwl_1016_ (sram_blwl_out[1016], sram_blwl_out[1016], sram_blwl_outb[1016], sram_blwl_1016_configbus0[1016:1016], sram_blwl_1016_configbus1[1016:1016] , sram_blwl_1016_configbus0_b[1016:1016] ); -wire [1017:1017] sram_blwl_1017_configbus0; -wire [1017:1017] sram_blwl_1017_configbus1; -wire [1017:1017] sram_blwl_1017_configbus0_b; -assign sram_blwl_1017_configbus0[1017:1017] = sram_blwl_bl[1017:1017] ; -assign sram_blwl_1017_configbus1[1017:1017] = sram_blwl_wl[1017:1017] ; -assign sram_blwl_1017_configbus0_b[1017:1017] = sram_blwl_blb[1017:1017] ; -sram6T_blwl sram_blwl_1017_ (sram_blwl_out[1017], sram_blwl_out[1017], sram_blwl_outb[1017], sram_blwl_1017_configbus0[1017:1017], sram_blwl_1017_configbus1[1017:1017] , sram_blwl_1017_configbus0_b[1017:1017] ); -wire [1018:1018] sram_blwl_1018_configbus0; -wire [1018:1018] sram_blwl_1018_configbus1; -wire [1018:1018] sram_blwl_1018_configbus0_b; -assign sram_blwl_1018_configbus0[1018:1018] = sram_blwl_bl[1018:1018] ; -assign sram_blwl_1018_configbus1[1018:1018] = sram_blwl_wl[1018:1018] ; -assign sram_blwl_1018_configbus0_b[1018:1018] = sram_blwl_blb[1018:1018] ; -sram6T_blwl sram_blwl_1018_ (sram_blwl_out[1018], sram_blwl_out[1018], sram_blwl_outb[1018], sram_blwl_1018_configbus0[1018:1018], sram_blwl_1018_configbus1[1018:1018] , sram_blwl_1018_configbus0_b[1018:1018] ); -wire [1019:1019] sram_blwl_1019_configbus0; -wire [1019:1019] sram_blwl_1019_configbus1; -wire [1019:1019] sram_blwl_1019_configbus0_b; -assign sram_blwl_1019_configbus0[1019:1019] = sram_blwl_bl[1019:1019] ; -assign sram_blwl_1019_configbus1[1019:1019] = sram_blwl_wl[1019:1019] ; -assign sram_blwl_1019_configbus0_b[1019:1019] = sram_blwl_blb[1019:1019] ; -sram6T_blwl sram_blwl_1019_ (sram_blwl_out[1019], sram_blwl_out[1019], sram_blwl_outb[1019], sram_blwl_1019_configbus0[1019:1019], sram_blwl_1019_configbus1[1019:1019] , sram_blwl_1019_configbus0_b[1019:1019] ); -wire [1020:1020] sram_blwl_1020_configbus0; -wire [1020:1020] sram_blwl_1020_configbus1; -wire [1020:1020] sram_blwl_1020_configbus0_b; -assign sram_blwl_1020_configbus0[1020:1020] = sram_blwl_bl[1020:1020] ; -assign sram_blwl_1020_configbus1[1020:1020] = sram_blwl_wl[1020:1020] ; -assign sram_blwl_1020_configbus0_b[1020:1020] = sram_blwl_blb[1020:1020] ; -sram6T_blwl sram_blwl_1020_ (sram_blwl_out[1020], sram_blwl_out[1020], sram_blwl_outb[1020], sram_blwl_1020_configbus0[1020:1020], sram_blwl_1020_configbus1[1020:1020] , sram_blwl_1020_configbus0_b[1020:1020] ); -wire [1021:1021] sram_blwl_1021_configbus0; -wire [1021:1021] sram_blwl_1021_configbus1; -wire [1021:1021] sram_blwl_1021_configbus0_b; -assign sram_blwl_1021_configbus0[1021:1021] = sram_blwl_bl[1021:1021] ; -assign sram_blwl_1021_configbus1[1021:1021] = sram_blwl_wl[1021:1021] ; -assign sram_blwl_1021_configbus0_b[1021:1021] = sram_blwl_blb[1021:1021] ; -sram6T_blwl sram_blwl_1021_ (sram_blwl_out[1021], sram_blwl_out[1021], sram_blwl_outb[1021], sram_blwl_1021_configbus0[1021:1021], sram_blwl_1021_configbus1[1021:1021] , sram_blwl_1021_configbus0_b[1021:1021] ); -wire [1022:1022] sram_blwl_1022_configbus0; -wire [1022:1022] sram_blwl_1022_configbus1; -wire [1022:1022] sram_blwl_1022_configbus0_b; -assign sram_blwl_1022_configbus0[1022:1022] = sram_blwl_bl[1022:1022] ; -assign sram_blwl_1022_configbus1[1022:1022] = sram_blwl_wl[1022:1022] ; -assign sram_blwl_1022_configbus0_b[1022:1022] = sram_blwl_blb[1022:1022] ; -sram6T_blwl sram_blwl_1022_ (sram_blwl_out[1022], sram_blwl_out[1022], sram_blwl_outb[1022], sram_blwl_1022_configbus0[1022:1022], sram_blwl_1022_configbus1[1022:1022] , sram_blwl_1022_configbus0_b[1022:1022] ); -wire [1023:1023] sram_blwl_1023_configbus0; -wire [1023:1023] sram_blwl_1023_configbus1; -wire [1023:1023] sram_blwl_1023_configbus0_b; -assign sram_blwl_1023_configbus0[1023:1023] = sram_blwl_bl[1023:1023] ; -assign sram_blwl_1023_configbus1[1023:1023] = sram_blwl_wl[1023:1023] ; -assign sram_blwl_1023_configbus0_b[1023:1023] = sram_blwl_blb[1023:1023] ; -sram6T_blwl sram_blwl_1023_ (sram_blwl_out[1023], sram_blwl_out[1023], sram_blwl_outb[1023], sram_blwl_1023_configbus0[1023:1023], sram_blwl_1023_configbus1[1023:1023] , sram_blwl_1023_configbus0_b[1023:1023] ); -wire [1024:1024] sram_blwl_1024_configbus0; -wire [1024:1024] sram_blwl_1024_configbus1; -wire [1024:1024] sram_blwl_1024_configbus0_b; -assign sram_blwl_1024_configbus0[1024:1024] = sram_blwl_bl[1024:1024] ; -assign sram_blwl_1024_configbus1[1024:1024] = sram_blwl_wl[1024:1024] ; -assign sram_blwl_1024_configbus0_b[1024:1024] = sram_blwl_blb[1024:1024] ; -sram6T_blwl sram_blwl_1024_ (sram_blwl_out[1024], sram_blwl_out[1024], sram_blwl_outb[1024], sram_blwl_1024_configbus0[1024:1024], sram_blwl_1024_configbus1[1024:1024] , sram_blwl_1024_configbus0_b[1024:1024] ); -wire [1025:1025] sram_blwl_1025_configbus0; -wire [1025:1025] sram_blwl_1025_configbus1; -wire [1025:1025] sram_blwl_1025_configbus0_b; -assign sram_blwl_1025_configbus0[1025:1025] = sram_blwl_bl[1025:1025] ; -assign sram_blwl_1025_configbus1[1025:1025] = sram_blwl_wl[1025:1025] ; -assign sram_blwl_1025_configbus0_b[1025:1025] = sram_blwl_blb[1025:1025] ; -sram6T_blwl sram_blwl_1025_ (sram_blwl_out[1025], sram_blwl_out[1025], sram_blwl_outb[1025], sram_blwl_1025_configbus0[1025:1025], sram_blwl_1025_configbus1[1025:1025] , sram_blwl_1025_configbus0_b[1025:1025] ); -wire [1026:1026] sram_blwl_1026_configbus0; -wire [1026:1026] sram_blwl_1026_configbus1; -wire [1026:1026] sram_blwl_1026_configbus0_b; -assign sram_blwl_1026_configbus0[1026:1026] = sram_blwl_bl[1026:1026] ; -assign sram_blwl_1026_configbus1[1026:1026] = sram_blwl_wl[1026:1026] ; -assign sram_blwl_1026_configbus0_b[1026:1026] = sram_blwl_blb[1026:1026] ; -sram6T_blwl sram_blwl_1026_ (sram_blwl_out[1026], sram_blwl_out[1026], sram_blwl_outb[1026], sram_blwl_1026_configbus0[1026:1026], sram_blwl_1026_configbus1[1026:1026] , sram_blwl_1026_configbus0_b[1026:1026] ); -wire [1027:1027] sram_blwl_1027_configbus0; -wire [1027:1027] sram_blwl_1027_configbus1; -wire [1027:1027] sram_blwl_1027_configbus0_b; -assign sram_blwl_1027_configbus0[1027:1027] = sram_blwl_bl[1027:1027] ; -assign sram_blwl_1027_configbus1[1027:1027] = sram_blwl_wl[1027:1027] ; -assign sram_blwl_1027_configbus0_b[1027:1027] = sram_blwl_blb[1027:1027] ; -sram6T_blwl sram_blwl_1027_ (sram_blwl_out[1027], sram_blwl_out[1027], sram_blwl_outb[1027], sram_blwl_1027_configbus0[1027:1027], sram_blwl_1027_configbus1[1027:1027] , sram_blwl_1027_configbus0_b[1027:1027] ); -wire [1028:1028] sram_blwl_1028_configbus0; -wire [1028:1028] sram_blwl_1028_configbus1; -wire [1028:1028] sram_blwl_1028_configbus0_b; -assign sram_blwl_1028_configbus0[1028:1028] = sram_blwl_bl[1028:1028] ; -assign sram_blwl_1028_configbus1[1028:1028] = sram_blwl_wl[1028:1028] ; -assign sram_blwl_1028_configbus0_b[1028:1028] = sram_blwl_blb[1028:1028] ; -sram6T_blwl sram_blwl_1028_ (sram_blwl_out[1028], sram_blwl_out[1028], sram_blwl_outb[1028], sram_blwl_1028_configbus0[1028:1028], sram_blwl_1028_configbus1[1028:1028] , sram_blwl_1028_configbus0_b[1028:1028] ); -wire [1029:1029] sram_blwl_1029_configbus0; -wire [1029:1029] sram_blwl_1029_configbus1; -wire [1029:1029] sram_blwl_1029_configbus0_b; -assign sram_blwl_1029_configbus0[1029:1029] = sram_blwl_bl[1029:1029] ; -assign sram_blwl_1029_configbus1[1029:1029] = sram_blwl_wl[1029:1029] ; -assign sram_blwl_1029_configbus0_b[1029:1029] = sram_blwl_blb[1029:1029] ; -sram6T_blwl sram_blwl_1029_ (sram_blwl_out[1029], sram_blwl_out[1029], sram_blwl_outb[1029], sram_blwl_1029_configbus0[1029:1029], sram_blwl_1029_configbus1[1029:1029] , sram_blwl_1029_configbus0_b[1029:1029] ); -wire [1030:1030] sram_blwl_1030_configbus0; -wire [1030:1030] sram_blwl_1030_configbus1; -wire [1030:1030] sram_blwl_1030_configbus0_b; -assign sram_blwl_1030_configbus0[1030:1030] = sram_blwl_bl[1030:1030] ; -assign sram_blwl_1030_configbus1[1030:1030] = sram_blwl_wl[1030:1030] ; -assign sram_blwl_1030_configbus0_b[1030:1030] = sram_blwl_blb[1030:1030] ; -sram6T_blwl sram_blwl_1030_ (sram_blwl_out[1030], sram_blwl_out[1030], sram_blwl_outb[1030], sram_blwl_1030_configbus0[1030:1030], sram_blwl_1030_configbus1[1030:1030] , sram_blwl_1030_configbus0_b[1030:1030] ); -wire [1031:1031] sram_blwl_1031_configbus0; -wire [1031:1031] sram_blwl_1031_configbus1; -wire [1031:1031] sram_blwl_1031_configbus0_b; -assign sram_blwl_1031_configbus0[1031:1031] = sram_blwl_bl[1031:1031] ; -assign sram_blwl_1031_configbus1[1031:1031] = sram_blwl_wl[1031:1031] ; -assign sram_blwl_1031_configbus0_b[1031:1031] = sram_blwl_blb[1031:1031] ; -sram6T_blwl sram_blwl_1031_ (sram_blwl_out[1031], sram_blwl_out[1031], sram_blwl_outb[1031], sram_blwl_1031_configbus0[1031:1031], sram_blwl_1031_configbus1[1031:1031] , sram_blwl_1031_configbus0_b[1031:1031] ); -wire [1032:1032] sram_blwl_1032_configbus0; -wire [1032:1032] sram_blwl_1032_configbus1; -wire [1032:1032] sram_blwl_1032_configbus0_b; -assign sram_blwl_1032_configbus0[1032:1032] = sram_blwl_bl[1032:1032] ; -assign sram_blwl_1032_configbus1[1032:1032] = sram_blwl_wl[1032:1032] ; -assign sram_blwl_1032_configbus0_b[1032:1032] = sram_blwl_blb[1032:1032] ; -sram6T_blwl sram_blwl_1032_ (sram_blwl_out[1032], sram_blwl_out[1032], sram_blwl_outb[1032], sram_blwl_1032_configbus0[1032:1032], sram_blwl_1032_configbus1[1032:1032] , sram_blwl_1032_configbus0_b[1032:1032] ); -wire [1033:1033] sram_blwl_1033_configbus0; -wire [1033:1033] sram_blwl_1033_configbus1; -wire [1033:1033] sram_blwl_1033_configbus0_b; -assign sram_blwl_1033_configbus0[1033:1033] = sram_blwl_bl[1033:1033] ; -assign sram_blwl_1033_configbus1[1033:1033] = sram_blwl_wl[1033:1033] ; -assign sram_blwl_1033_configbus0_b[1033:1033] = sram_blwl_blb[1033:1033] ; -sram6T_blwl sram_blwl_1033_ (sram_blwl_out[1033], sram_blwl_out[1033], sram_blwl_outb[1033], sram_blwl_1033_configbus0[1033:1033], sram_blwl_1033_configbus1[1033:1033] , sram_blwl_1033_configbus0_b[1033:1033] ); -wire [1034:1034] sram_blwl_1034_configbus0; -wire [1034:1034] sram_blwl_1034_configbus1; -wire [1034:1034] sram_blwl_1034_configbus0_b; -assign sram_blwl_1034_configbus0[1034:1034] = sram_blwl_bl[1034:1034] ; -assign sram_blwl_1034_configbus1[1034:1034] = sram_blwl_wl[1034:1034] ; -assign sram_blwl_1034_configbus0_b[1034:1034] = sram_blwl_blb[1034:1034] ; -sram6T_blwl sram_blwl_1034_ (sram_blwl_out[1034], sram_blwl_out[1034], sram_blwl_outb[1034], sram_blwl_1034_configbus0[1034:1034], sram_blwl_1034_configbus1[1034:1034] , sram_blwl_1034_configbus0_b[1034:1034] ); -wire [1035:1035] sram_blwl_1035_configbus0; -wire [1035:1035] sram_blwl_1035_configbus1; -wire [1035:1035] sram_blwl_1035_configbus0_b; -assign sram_blwl_1035_configbus0[1035:1035] = sram_blwl_bl[1035:1035] ; -assign sram_blwl_1035_configbus1[1035:1035] = sram_blwl_wl[1035:1035] ; -assign sram_blwl_1035_configbus0_b[1035:1035] = sram_blwl_blb[1035:1035] ; -sram6T_blwl sram_blwl_1035_ (sram_blwl_out[1035], sram_blwl_out[1035], sram_blwl_outb[1035], sram_blwl_1035_configbus0[1035:1035], sram_blwl_1035_configbus1[1035:1035] , sram_blwl_1035_configbus0_b[1035:1035] ); -wire [1036:1036] sram_blwl_1036_configbus0; -wire [1036:1036] sram_blwl_1036_configbus1; -wire [1036:1036] sram_blwl_1036_configbus0_b; -assign sram_blwl_1036_configbus0[1036:1036] = sram_blwl_bl[1036:1036] ; -assign sram_blwl_1036_configbus1[1036:1036] = sram_blwl_wl[1036:1036] ; -assign sram_blwl_1036_configbus0_b[1036:1036] = sram_blwl_blb[1036:1036] ; -sram6T_blwl sram_blwl_1036_ (sram_blwl_out[1036], sram_blwl_out[1036], sram_blwl_outb[1036], sram_blwl_1036_configbus0[1036:1036], sram_blwl_1036_configbus1[1036:1036] , sram_blwl_1036_configbus0_b[1036:1036] ); -wire [1037:1037] sram_blwl_1037_configbus0; -wire [1037:1037] sram_blwl_1037_configbus1; -wire [1037:1037] sram_blwl_1037_configbus0_b; -assign sram_blwl_1037_configbus0[1037:1037] = sram_blwl_bl[1037:1037] ; -assign sram_blwl_1037_configbus1[1037:1037] = sram_blwl_wl[1037:1037] ; -assign sram_blwl_1037_configbus0_b[1037:1037] = sram_blwl_blb[1037:1037] ; -sram6T_blwl sram_blwl_1037_ (sram_blwl_out[1037], sram_blwl_out[1037], sram_blwl_outb[1037], sram_blwl_1037_configbus0[1037:1037], sram_blwl_1037_configbus1[1037:1037] , sram_blwl_1037_configbus0_b[1037:1037] ); -wire [1038:1038] sram_blwl_1038_configbus0; -wire [1038:1038] sram_blwl_1038_configbus1; -wire [1038:1038] sram_blwl_1038_configbus0_b; -assign sram_blwl_1038_configbus0[1038:1038] = sram_blwl_bl[1038:1038] ; -assign sram_blwl_1038_configbus1[1038:1038] = sram_blwl_wl[1038:1038] ; -assign sram_blwl_1038_configbus0_b[1038:1038] = sram_blwl_blb[1038:1038] ; -sram6T_blwl sram_blwl_1038_ (sram_blwl_out[1038], sram_blwl_out[1038], sram_blwl_outb[1038], sram_blwl_1038_configbus0[1038:1038], sram_blwl_1038_configbus1[1038:1038] , sram_blwl_1038_configbus0_b[1038:1038] ); -wire [1039:1039] sram_blwl_1039_configbus0; -wire [1039:1039] sram_blwl_1039_configbus1; -wire [1039:1039] sram_blwl_1039_configbus0_b; -assign sram_blwl_1039_configbus0[1039:1039] = sram_blwl_bl[1039:1039] ; -assign sram_blwl_1039_configbus1[1039:1039] = sram_blwl_wl[1039:1039] ; -assign sram_blwl_1039_configbus0_b[1039:1039] = sram_blwl_blb[1039:1039] ; -sram6T_blwl sram_blwl_1039_ (sram_blwl_out[1039], sram_blwl_out[1039], sram_blwl_outb[1039], sram_blwl_1039_configbus0[1039:1039], sram_blwl_1039_configbus1[1039:1039] , sram_blwl_1039_configbus0_b[1039:1039] ); -wire [1040:1040] sram_blwl_1040_configbus0; -wire [1040:1040] sram_blwl_1040_configbus1; -wire [1040:1040] sram_blwl_1040_configbus0_b; -assign sram_blwl_1040_configbus0[1040:1040] = sram_blwl_bl[1040:1040] ; -assign sram_blwl_1040_configbus1[1040:1040] = sram_blwl_wl[1040:1040] ; -assign sram_blwl_1040_configbus0_b[1040:1040] = sram_blwl_blb[1040:1040] ; -sram6T_blwl sram_blwl_1040_ (sram_blwl_out[1040], sram_blwl_out[1040], sram_blwl_outb[1040], sram_blwl_1040_configbus0[1040:1040], sram_blwl_1040_configbus1[1040:1040] , sram_blwl_1040_configbus0_b[1040:1040] ); -wire [1041:1041] sram_blwl_1041_configbus0; -wire [1041:1041] sram_blwl_1041_configbus1; -wire [1041:1041] sram_blwl_1041_configbus0_b; -assign sram_blwl_1041_configbus0[1041:1041] = sram_blwl_bl[1041:1041] ; -assign sram_blwl_1041_configbus1[1041:1041] = sram_blwl_wl[1041:1041] ; -assign sram_blwl_1041_configbus0_b[1041:1041] = sram_blwl_blb[1041:1041] ; -sram6T_blwl sram_blwl_1041_ (sram_blwl_out[1041], sram_blwl_out[1041], sram_blwl_outb[1041], sram_blwl_1041_configbus0[1041:1041], sram_blwl_1041_configbus1[1041:1041] , sram_blwl_1041_configbus0_b[1041:1041] ); -wire [1042:1042] sram_blwl_1042_configbus0; -wire [1042:1042] sram_blwl_1042_configbus1; -wire [1042:1042] sram_blwl_1042_configbus0_b; -assign sram_blwl_1042_configbus0[1042:1042] = sram_blwl_bl[1042:1042] ; -assign sram_blwl_1042_configbus1[1042:1042] = sram_blwl_wl[1042:1042] ; -assign sram_blwl_1042_configbus0_b[1042:1042] = sram_blwl_blb[1042:1042] ; -sram6T_blwl sram_blwl_1042_ (sram_blwl_out[1042], sram_blwl_out[1042], sram_blwl_outb[1042], sram_blwl_1042_configbus0[1042:1042], sram_blwl_1042_configbus1[1042:1042] , sram_blwl_1042_configbus0_b[1042:1042] ); -wire [1043:1043] sram_blwl_1043_configbus0; -wire [1043:1043] sram_blwl_1043_configbus1; -wire [1043:1043] sram_blwl_1043_configbus0_b; -assign sram_blwl_1043_configbus0[1043:1043] = sram_blwl_bl[1043:1043] ; -assign sram_blwl_1043_configbus1[1043:1043] = sram_blwl_wl[1043:1043] ; -assign sram_blwl_1043_configbus0_b[1043:1043] = sram_blwl_blb[1043:1043] ; -sram6T_blwl sram_blwl_1043_ (sram_blwl_out[1043], sram_blwl_out[1043], sram_blwl_outb[1043], sram_blwl_1043_configbus0[1043:1043], sram_blwl_1043_configbus1[1043:1043] , sram_blwl_1043_configbus0_b[1043:1043] ); -wire [1044:1044] sram_blwl_1044_configbus0; -wire [1044:1044] sram_blwl_1044_configbus1; -wire [1044:1044] sram_blwl_1044_configbus0_b; -assign sram_blwl_1044_configbus0[1044:1044] = sram_blwl_bl[1044:1044] ; -assign sram_blwl_1044_configbus1[1044:1044] = sram_blwl_wl[1044:1044] ; -assign sram_blwl_1044_configbus0_b[1044:1044] = sram_blwl_blb[1044:1044] ; -sram6T_blwl sram_blwl_1044_ (sram_blwl_out[1044], sram_blwl_out[1044], sram_blwl_outb[1044], sram_blwl_1044_configbus0[1044:1044], sram_blwl_1044_configbus1[1044:1044] , sram_blwl_1044_configbus0_b[1044:1044] ); -wire [1045:1045] sram_blwl_1045_configbus0; -wire [1045:1045] sram_blwl_1045_configbus1; -wire [1045:1045] sram_blwl_1045_configbus0_b; -assign sram_blwl_1045_configbus0[1045:1045] = sram_blwl_bl[1045:1045] ; -assign sram_blwl_1045_configbus1[1045:1045] = sram_blwl_wl[1045:1045] ; -assign sram_blwl_1045_configbus0_b[1045:1045] = sram_blwl_blb[1045:1045] ; -sram6T_blwl sram_blwl_1045_ (sram_blwl_out[1045], sram_blwl_out[1045], sram_blwl_outb[1045], sram_blwl_1045_configbus0[1045:1045], sram_blwl_1045_configbus1[1045:1045] , sram_blwl_1045_configbus0_b[1045:1045] ); -wire [1046:1046] sram_blwl_1046_configbus0; -wire [1046:1046] sram_blwl_1046_configbus1; -wire [1046:1046] sram_blwl_1046_configbus0_b; -assign sram_blwl_1046_configbus0[1046:1046] = sram_blwl_bl[1046:1046] ; -assign sram_blwl_1046_configbus1[1046:1046] = sram_blwl_wl[1046:1046] ; -assign sram_blwl_1046_configbus0_b[1046:1046] = sram_blwl_blb[1046:1046] ; -sram6T_blwl sram_blwl_1046_ (sram_blwl_out[1046], sram_blwl_out[1046], sram_blwl_outb[1046], sram_blwl_1046_configbus0[1046:1046], sram_blwl_1046_configbus1[1046:1046] , sram_blwl_1046_configbus0_b[1046:1046] ); -wire [1047:1047] sram_blwl_1047_configbus0; -wire [1047:1047] sram_blwl_1047_configbus1; -wire [1047:1047] sram_blwl_1047_configbus0_b; -assign sram_blwl_1047_configbus0[1047:1047] = sram_blwl_bl[1047:1047] ; -assign sram_blwl_1047_configbus1[1047:1047] = sram_blwl_wl[1047:1047] ; -assign sram_blwl_1047_configbus0_b[1047:1047] = sram_blwl_blb[1047:1047] ; -sram6T_blwl sram_blwl_1047_ (sram_blwl_out[1047], sram_blwl_out[1047], sram_blwl_outb[1047], sram_blwl_1047_configbus0[1047:1047], sram_blwl_1047_configbus1[1047:1047] , sram_blwl_1047_configbus0_b[1047:1047] ); -wire [1048:1048] sram_blwl_1048_configbus0; -wire [1048:1048] sram_blwl_1048_configbus1; -wire [1048:1048] sram_blwl_1048_configbus0_b; -assign sram_blwl_1048_configbus0[1048:1048] = sram_blwl_bl[1048:1048] ; -assign sram_blwl_1048_configbus1[1048:1048] = sram_blwl_wl[1048:1048] ; -assign sram_blwl_1048_configbus0_b[1048:1048] = sram_blwl_blb[1048:1048] ; -sram6T_blwl sram_blwl_1048_ (sram_blwl_out[1048], sram_blwl_out[1048], sram_blwl_outb[1048], sram_blwl_1048_configbus0[1048:1048], sram_blwl_1048_configbus1[1048:1048] , sram_blwl_1048_configbus0_b[1048:1048] ); -wire [1049:1049] sram_blwl_1049_configbus0; -wire [1049:1049] sram_blwl_1049_configbus1; -wire [1049:1049] sram_blwl_1049_configbus0_b; -assign sram_blwl_1049_configbus0[1049:1049] = sram_blwl_bl[1049:1049] ; -assign sram_blwl_1049_configbus1[1049:1049] = sram_blwl_wl[1049:1049] ; -assign sram_blwl_1049_configbus0_b[1049:1049] = sram_blwl_blb[1049:1049] ; -sram6T_blwl sram_blwl_1049_ (sram_blwl_out[1049], sram_blwl_out[1049], sram_blwl_outb[1049], sram_blwl_1049_configbus0[1049:1049], sram_blwl_1049_configbus1[1049:1049] , sram_blwl_1049_configbus0_b[1049:1049] ); -wire [1050:1050] sram_blwl_1050_configbus0; -wire [1050:1050] sram_blwl_1050_configbus1; -wire [1050:1050] sram_blwl_1050_configbus0_b; -assign sram_blwl_1050_configbus0[1050:1050] = sram_blwl_bl[1050:1050] ; -assign sram_blwl_1050_configbus1[1050:1050] = sram_blwl_wl[1050:1050] ; -assign sram_blwl_1050_configbus0_b[1050:1050] = sram_blwl_blb[1050:1050] ; -sram6T_blwl sram_blwl_1050_ (sram_blwl_out[1050], sram_blwl_out[1050], sram_blwl_outb[1050], sram_blwl_1050_configbus0[1050:1050], sram_blwl_1050_configbus1[1050:1050] , sram_blwl_1050_configbus0_b[1050:1050] ); -wire [1051:1051] sram_blwl_1051_configbus0; -wire [1051:1051] sram_blwl_1051_configbus1; -wire [1051:1051] sram_blwl_1051_configbus0_b; -assign sram_blwl_1051_configbus0[1051:1051] = sram_blwl_bl[1051:1051] ; -assign sram_blwl_1051_configbus1[1051:1051] = sram_blwl_wl[1051:1051] ; -assign sram_blwl_1051_configbus0_b[1051:1051] = sram_blwl_blb[1051:1051] ; -sram6T_blwl sram_blwl_1051_ (sram_blwl_out[1051], sram_blwl_out[1051], sram_blwl_outb[1051], sram_blwl_1051_configbus0[1051:1051], sram_blwl_1051_configbus1[1051:1051] , sram_blwl_1051_configbus0_b[1051:1051] ); -wire [1052:1052] sram_blwl_1052_configbus0; -wire [1052:1052] sram_blwl_1052_configbus1; -wire [1052:1052] sram_blwl_1052_configbus0_b; -assign sram_blwl_1052_configbus0[1052:1052] = sram_blwl_bl[1052:1052] ; -assign sram_blwl_1052_configbus1[1052:1052] = sram_blwl_wl[1052:1052] ; -assign sram_blwl_1052_configbus0_b[1052:1052] = sram_blwl_blb[1052:1052] ; -sram6T_blwl sram_blwl_1052_ (sram_blwl_out[1052], sram_blwl_out[1052], sram_blwl_outb[1052], sram_blwl_1052_configbus0[1052:1052], sram_blwl_1052_configbus1[1052:1052] , sram_blwl_1052_configbus0_b[1052:1052] ); -wire [1053:1053] sram_blwl_1053_configbus0; -wire [1053:1053] sram_blwl_1053_configbus1; -wire [1053:1053] sram_blwl_1053_configbus0_b; -assign sram_blwl_1053_configbus0[1053:1053] = sram_blwl_bl[1053:1053] ; -assign sram_blwl_1053_configbus1[1053:1053] = sram_blwl_wl[1053:1053] ; -assign sram_blwl_1053_configbus0_b[1053:1053] = sram_blwl_blb[1053:1053] ; -sram6T_blwl sram_blwl_1053_ (sram_blwl_out[1053], sram_blwl_out[1053], sram_blwl_outb[1053], sram_blwl_1053_configbus0[1053:1053], sram_blwl_1053_configbus1[1053:1053] , sram_blwl_1053_configbus0_b[1053:1053] ); -wire [1054:1054] sram_blwl_1054_configbus0; -wire [1054:1054] sram_blwl_1054_configbus1; -wire [1054:1054] sram_blwl_1054_configbus0_b; -assign sram_blwl_1054_configbus0[1054:1054] = sram_blwl_bl[1054:1054] ; -assign sram_blwl_1054_configbus1[1054:1054] = sram_blwl_wl[1054:1054] ; -assign sram_blwl_1054_configbus0_b[1054:1054] = sram_blwl_blb[1054:1054] ; -sram6T_blwl sram_blwl_1054_ (sram_blwl_out[1054], sram_blwl_out[1054], sram_blwl_outb[1054], sram_blwl_1054_configbus0[1054:1054], sram_blwl_1054_configbus1[1054:1054] , sram_blwl_1054_configbus0_b[1054:1054] ); -wire [1055:1055] sram_blwl_1055_configbus0; -wire [1055:1055] sram_blwl_1055_configbus1; -wire [1055:1055] sram_blwl_1055_configbus0_b; -assign sram_blwl_1055_configbus0[1055:1055] = sram_blwl_bl[1055:1055] ; -assign sram_blwl_1055_configbus1[1055:1055] = sram_blwl_wl[1055:1055] ; -assign sram_blwl_1055_configbus0_b[1055:1055] = sram_blwl_blb[1055:1055] ; -sram6T_blwl sram_blwl_1055_ (sram_blwl_out[1055], sram_blwl_out[1055], sram_blwl_outb[1055], sram_blwl_1055_configbus0[1055:1055], sram_blwl_1055_configbus1[1055:1055] , sram_blwl_1055_configbus0_b[1055:1055] ); -wire [1056:1056] sram_blwl_1056_configbus0; -wire [1056:1056] sram_blwl_1056_configbus1; -wire [1056:1056] sram_blwl_1056_configbus0_b; -assign sram_blwl_1056_configbus0[1056:1056] = sram_blwl_bl[1056:1056] ; -assign sram_blwl_1056_configbus1[1056:1056] = sram_blwl_wl[1056:1056] ; -assign sram_blwl_1056_configbus0_b[1056:1056] = sram_blwl_blb[1056:1056] ; -sram6T_blwl sram_blwl_1056_ (sram_blwl_out[1056], sram_blwl_out[1056], sram_blwl_outb[1056], sram_blwl_1056_configbus0[1056:1056], sram_blwl_1056_configbus1[1056:1056] , sram_blwl_1056_configbus0_b[1056:1056] ); -wire [1057:1057] sram_blwl_1057_configbus0; -wire [1057:1057] sram_blwl_1057_configbus1; -wire [1057:1057] sram_blwl_1057_configbus0_b; -assign sram_blwl_1057_configbus0[1057:1057] = sram_blwl_bl[1057:1057] ; -assign sram_blwl_1057_configbus1[1057:1057] = sram_blwl_wl[1057:1057] ; -assign sram_blwl_1057_configbus0_b[1057:1057] = sram_blwl_blb[1057:1057] ; -sram6T_blwl sram_blwl_1057_ (sram_blwl_out[1057], sram_blwl_out[1057], sram_blwl_outb[1057], sram_blwl_1057_configbus0[1057:1057], sram_blwl_1057_configbus1[1057:1057] , sram_blwl_1057_configbus0_b[1057:1057] ); -wire [1058:1058] sram_blwl_1058_configbus0; -wire [1058:1058] sram_blwl_1058_configbus1; -wire [1058:1058] sram_blwl_1058_configbus0_b; -assign sram_blwl_1058_configbus0[1058:1058] = sram_blwl_bl[1058:1058] ; -assign sram_blwl_1058_configbus1[1058:1058] = sram_blwl_wl[1058:1058] ; -assign sram_blwl_1058_configbus0_b[1058:1058] = sram_blwl_blb[1058:1058] ; -sram6T_blwl sram_blwl_1058_ (sram_blwl_out[1058], sram_blwl_out[1058], sram_blwl_outb[1058], sram_blwl_1058_configbus0[1058:1058], sram_blwl_1058_configbus1[1058:1058] , sram_blwl_1058_configbus0_b[1058:1058] ); -wire [1059:1059] sram_blwl_1059_configbus0; -wire [1059:1059] sram_blwl_1059_configbus1; -wire [1059:1059] sram_blwl_1059_configbus0_b; -assign sram_blwl_1059_configbus0[1059:1059] = sram_blwl_bl[1059:1059] ; -assign sram_blwl_1059_configbus1[1059:1059] = sram_blwl_wl[1059:1059] ; -assign sram_blwl_1059_configbus0_b[1059:1059] = sram_blwl_blb[1059:1059] ; -sram6T_blwl sram_blwl_1059_ (sram_blwl_out[1059], sram_blwl_out[1059], sram_blwl_outb[1059], sram_blwl_1059_configbus0[1059:1059], sram_blwl_1059_configbus1[1059:1059] , sram_blwl_1059_configbus0_b[1059:1059] ); -wire [1060:1060] sram_blwl_1060_configbus0; -wire [1060:1060] sram_blwl_1060_configbus1; -wire [1060:1060] sram_blwl_1060_configbus0_b; -assign sram_blwl_1060_configbus0[1060:1060] = sram_blwl_bl[1060:1060] ; -assign sram_blwl_1060_configbus1[1060:1060] = sram_blwl_wl[1060:1060] ; -assign sram_blwl_1060_configbus0_b[1060:1060] = sram_blwl_blb[1060:1060] ; -sram6T_blwl sram_blwl_1060_ (sram_blwl_out[1060], sram_blwl_out[1060], sram_blwl_outb[1060], sram_blwl_1060_configbus0[1060:1060], sram_blwl_1060_configbus1[1060:1060] , sram_blwl_1060_configbus0_b[1060:1060] ); -wire [1061:1061] sram_blwl_1061_configbus0; -wire [1061:1061] sram_blwl_1061_configbus1; -wire [1061:1061] sram_blwl_1061_configbus0_b; -assign sram_blwl_1061_configbus0[1061:1061] = sram_blwl_bl[1061:1061] ; -assign sram_blwl_1061_configbus1[1061:1061] = sram_blwl_wl[1061:1061] ; -assign sram_blwl_1061_configbus0_b[1061:1061] = sram_blwl_blb[1061:1061] ; -sram6T_blwl sram_blwl_1061_ (sram_blwl_out[1061], sram_blwl_out[1061], sram_blwl_outb[1061], sram_blwl_1061_configbus0[1061:1061], sram_blwl_1061_configbus1[1061:1061] , sram_blwl_1061_configbus0_b[1061:1061] ); -wire [1062:1062] sram_blwl_1062_configbus0; -wire [1062:1062] sram_blwl_1062_configbus1; -wire [1062:1062] sram_blwl_1062_configbus0_b; -assign sram_blwl_1062_configbus0[1062:1062] = sram_blwl_bl[1062:1062] ; -assign sram_blwl_1062_configbus1[1062:1062] = sram_blwl_wl[1062:1062] ; -assign sram_blwl_1062_configbus0_b[1062:1062] = sram_blwl_blb[1062:1062] ; -sram6T_blwl sram_blwl_1062_ (sram_blwl_out[1062], sram_blwl_out[1062], sram_blwl_outb[1062], sram_blwl_1062_configbus0[1062:1062], sram_blwl_1062_configbus1[1062:1062] , sram_blwl_1062_configbus0_b[1062:1062] ); -wire [1063:1063] sram_blwl_1063_configbus0; -wire [1063:1063] sram_blwl_1063_configbus1; -wire [1063:1063] sram_blwl_1063_configbus0_b; -assign sram_blwl_1063_configbus0[1063:1063] = sram_blwl_bl[1063:1063] ; -assign sram_blwl_1063_configbus1[1063:1063] = sram_blwl_wl[1063:1063] ; -assign sram_blwl_1063_configbus0_b[1063:1063] = sram_blwl_blb[1063:1063] ; -sram6T_blwl sram_blwl_1063_ (sram_blwl_out[1063], sram_blwl_out[1063], sram_blwl_outb[1063], sram_blwl_1063_configbus0[1063:1063], sram_blwl_1063_configbus1[1063:1063] , sram_blwl_1063_configbus0_b[1063:1063] ); -wire [1064:1064] sram_blwl_1064_configbus0; -wire [1064:1064] sram_blwl_1064_configbus1; -wire [1064:1064] sram_blwl_1064_configbus0_b; -assign sram_blwl_1064_configbus0[1064:1064] = sram_blwl_bl[1064:1064] ; -assign sram_blwl_1064_configbus1[1064:1064] = sram_blwl_wl[1064:1064] ; -assign sram_blwl_1064_configbus0_b[1064:1064] = sram_blwl_blb[1064:1064] ; -sram6T_blwl sram_blwl_1064_ (sram_blwl_out[1064], sram_blwl_out[1064], sram_blwl_outb[1064], sram_blwl_1064_configbus0[1064:1064], sram_blwl_1064_configbus1[1064:1064] , sram_blwl_1064_configbus0_b[1064:1064] ); -wire [1065:1065] sram_blwl_1065_configbus0; -wire [1065:1065] sram_blwl_1065_configbus1; -wire [1065:1065] sram_blwl_1065_configbus0_b; -assign sram_blwl_1065_configbus0[1065:1065] = sram_blwl_bl[1065:1065] ; -assign sram_blwl_1065_configbus1[1065:1065] = sram_blwl_wl[1065:1065] ; -assign sram_blwl_1065_configbus0_b[1065:1065] = sram_blwl_blb[1065:1065] ; -sram6T_blwl sram_blwl_1065_ (sram_blwl_out[1065], sram_blwl_out[1065], sram_blwl_outb[1065], sram_blwl_1065_configbus0[1065:1065], sram_blwl_1065_configbus1[1065:1065] , sram_blwl_1065_configbus0_b[1065:1065] ); -wire [1066:1066] sram_blwl_1066_configbus0; -wire [1066:1066] sram_blwl_1066_configbus1; -wire [1066:1066] sram_blwl_1066_configbus0_b; -assign sram_blwl_1066_configbus0[1066:1066] = sram_blwl_bl[1066:1066] ; -assign sram_blwl_1066_configbus1[1066:1066] = sram_blwl_wl[1066:1066] ; -assign sram_blwl_1066_configbus0_b[1066:1066] = sram_blwl_blb[1066:1066] ; -sram6T_blwl sram_blwl_1066_ (sram_blwl_out[1066], sram_blwl_out[1066], sram_blwl_outb[1066], sram_blwl_1066_configbus0[1066:1066], sram_blwl_1066_configbus1[1066:1066] , sram_blwl_1066_configbus0_b[1066:1066] ); -wire [1067:1067] sram_blwl_1067_configbus0; -wire [1067:1067] sram_blwl_1067_configbus1; -wire [1067:1067] sram_blwl_1067_configbus0_b; -assign sram_blwl_1067_configbus0[1067:1067] = sram_blwl_bl[1067:1067] ; -assign sram_blwl_1067_configbus1[1067:1067] = sram_blwl_wl[1067:1067] ; -assign sram_blwl_1067_configbus0_b[1067:1067] = sram_blwl_blb[1067:1067] ; -sram6T_blwl sram_blwl_1067_ (sram_blwl_out[1067], sram_blwl_out[1067], sram_blwl_outb[1067], sram_blwl_1067_configbus0[1067:1067], sram_blwl_1067_configbus1[1067:1067] , sram_blwl_1067_configbus0_b[1067:1067] ); -wire [1068:1068] sram_blwl_1068_configbus0; -wire [1068:1068] sram_blwl_1068_configbus1; -wire [1068:1068] sram_blwl_1068_configbus0_b; -assign sram_blwl_1068_configbus0[1068:1068] = sram_blwl_bl[1068:1068] ; -assign sram_blwl_1068_configbus1[1068:1068] = sram_blwl_wl[1068:1068] ; -assign sram_blwl_1068_configbus0_b[1068:1068] = sram_blwl_blb[1068:1068] ; -sram6T_blwl sram_blwl_1068_ (sram_blwl_out[1068], sram_blwl_out[1068], sram_blwl_outb[1068], sram_blwl_1068_configbus0[1068:1068], sram_blwl_1068_configbus1[1068:1068] , sram_blwl_1068_configbus0_b[1068:1068] ); -wire [1069:1069] sram_blwl_1069_configbus0; -wire [1069:1069] sram_blwl_1069_configbus1; -wire [1069:1069] sram_blwl_1069_configbus0_b; -assign sram_blwl_1069_configbus0[1069:1069] = sram_blwl_bl[1069:1069] ; -assign sram_blwl_1069_configbus1[1069:1069] = sram_blwl_wl[1069:1069] ; -assign sram_blwl_1069_configbus0_b[1069:1069] = sram_blwl_blb[1069:1069] ; -sram6T_blwl sram_blwl_1069_ (sram_blwl_out[1069], sram_blwl_out[1069], sram_blwl_outb[1069], sram_blwl_1069_configbus0[1069:1069], sram_blwl_1069_configbus1[1069:1069] , sram_blwl_1069_configbus0_b[1069:1069] ); -wire [1070:1070] sram_blwl_1070_configbus0; -wire [1070:1070] sram_blwl_1070_configbus1; -wire [1070:1070] sram_blwl_1070_configbus0_b; -assign sram_blwl_1070_configbus0[1070:1070] = sram_blwl_bl[1070:1070] ; -assign sram_blwl_1070_configbus1[1070:1070] = sram_blwl_wl[1070:1070] ; -assign sram_blwl_1070_configbus0_b[1070:1070] = sram_blwl_blb[1070:1070] ; -sram6T_blwl sram_blwl_1070_ (sram_blwl_out[1070], sram_blwl_out[1070], sram_blwl_outb[1070], sram_blwl_1070_configbus0[1070:1070], sram_blwl_1070_configbus1[1070:1070] , sram_blwl_1070_configbus0_b[1070:1070] ); -wire [1071:1071] sram_blwl_1071_configbus0; -wire [1071:1071] sram_blwl_1071_configbus1; -wire [1071:1071] sram_blwl_1071_configbus0_b; -assign sram_blwl_1071_configbus0[1071:1071] = sram_blwl_bl[1071:1071] ; -assign sram_blwl_1071_configbus1[1071:1071] = sram_blwl_wl[1071:1071] ; -assign sram_blwl_1071_configbus0_b[1071:1071] = sram_blwl_blb[1071:1071] ; -sram6T_blwl sram_blwl_1071_ (sram_blwl_out[1071], sram_blwl_out[1071], sram_blwl_outb[1071], sram_blwl_1071_configbus0[1071:1071], sram_blwl_1071_configbus1[1071:1071] , sram_blwl_1071_configbus0_b[1071:1071] ); -wire [1072:1072] sram_blwl_1072_configbus0; -wire [1072:1072] sram_blwl_1072_configbus1; -wire [1072:1072] sram_blwl_1072_configbus0_b; -assign sram_blwl_1072_configbus0[1072:1072] = sram_blwl_bl[1072:1072] ; -assign sram_blwl_1072_configbus1[1072:1072] = sram_blwl_wl[1072:1072] ; -assign sram_blwl_1072_configbus0_b[1072:1072] = sram_blwl_blb[1072:1072] ; -sram6T_blwl sram_blwl_1072_ (sram_blwl_out[1072], sram_blwl_out[1072], sram_blwl_outb[1072], sram_blwl_1072_configbus0[1072:1072], sram_blwl_1072_configbus1[1072:1072] , sram_blwl_1072_configbus0_b[1072:1072] ); -wire [1073:1073] sram_blwl_1073_configbus0; -wire [1073:1073] sram_blwl_1073_configbus1; -wire [1073:1073] sram_blwl_1073_configbus0_b; -assign sram_blwl_1073_configbus0[1073:1073] = sram_blwl_bl[1073:1073] ; -assign sram_blwl_1073_configbus1[1073:1073] = sram_blwl_wl[1073:1073] ; -assign sram_blwl_1073_configbus0_b[1073:1073] = sram_blwl_blb[1073:1073] ; -sram6T_blwl sram_blwl_1073_ (sram_blwl_out[1073], sram_blwl_out[1073], sram_blwl_outb[1073], sram_blwl_1073_configbus0[1073:1073], sram_blwl_1073_configbus1[1073:1073] , sram_blwl_1073_configbus0_b[1073:1073] ); -wire [1074:1074] sram_blwl_1074_configbus0; -wire [1074:1074] sram_blwl_1074_configbus1; -wire [1074:1074] sram_blwl_1074_configbus0_b; -assign sram_blwl_1074_configbus0[1074:1074] = sram_blwl_bl[1074:1074] ; -assign sram_blwl_1074_configbus1[1074:1074] = sram_blwl_wl[1074:1074] ; -assign sram_blwl_1074_configbus0_b[1074:1074] = sram_blwl_blb[1074:1074] ; -sram6T_blwl sram_blwl_1074_ (sram_blwl_out[1074], sram_blwl_out[1074], sram_blwl_outb[1074], sram_blwl_1074_configbus0[1074:1074], sram_blwl_1074_configbus1[1074:1074] , sram_blwl_1074_configbus0_b[1074:1074] ); -wire [1075:1075] sram_blwl_1075_configbus0; -wire [1075:1075] sram_blwl_1075_configbus1; -wire [1075:1075] sram_blwl_1075_configbus0_b; -assign sram_blwl_1075_configbus0[1075:1075] = sram_blwl_bl[1075:1075] ; -assign sram_blwl_1075_configbus1[1075:1075] = sram_blwl_wl[1075:1075] ; -assign sram_blwl_1075_configbus0_b[1075:1075] = sram_blwl_blb[1075:1075] ; -sram6T_blwl sram_blwl_1075_ (sram_blwl_out[1075], sram_blwl_out[1075], sram_blwl_outb[1075], sram_blwl_1075_configbus0[1075:1075], sram_blwl_1075_configbus1[1075:1075] , sram_blwl_1075_configbus0_b[1075:1075] ); -wire [1076:1076] sram_blwl_1076_configbus0; -wire [1076:1076] sram_blwl_1076_configbus1; -wire [1076:1076] sram_blwl_1076_configbus0_b; -assign sram_blwl_1076_configbus0[1076:1076] = sram_blwl_bl[1076:1076] ; -assign sram_blwl_1076_configbus1[1076:1076] = sram_blwl_wl[1076:1076] ; -assign sram_blwl_1076_configbus0_b[1076:1076] = sram_blwl_blb[1076:1076] ; -sram6T_blwl sram_blwl_1076_ (sram_blwl_out[1076], sram_blwl_out[1076], sram_blwl_outb[1076], sram_blwl_1076_configbus0[1076:1076], sram_blwl_1076_configbus1[1076:1076] , sram_blwl_1076_configbus0_b[1076:1076] ); -wire [1077:1077] sram_blwl_1077_configbus0; -wire [1077:1077] sram_blwl_1077_configbus1; -wire [1077:1077] sram_blwl_1077_configbus0_b; -assign sram_blwl_1077_configbus0[1077:1077] = sram_blwl_bl[1077:1077] ; -assign sram_blwl_1077_configbus1[1077:1077] = sram_blwl_wl[1077:1077] ; -assign sram_blwl_1077_configbus0_b[1077:1077] = sram_blwl_blb[1077:1077] ; -sram6T_blwl sram_blwl_1077_ (sram_blwl_out[1077], sram_blwl_out[1077], sram_blwl_outb[1077], sram_blwl_1077_configbus0[1077:1077], sram_blwl_1077_configbus1[1077:1077] , sram_blwl_1077_configbus0_b[1077:1077] ); -wire [1078:1078] sram_blwl_1078_configbus0; -wire [1078:1078] sram_blwl_1078_configbus1; -wire [1078:1078] sram_blwl_1078_configbus0_b; -assign sram_blwl_1078_configbus0[1078:1078] = sram_blwl_bl[1078:1078] ; -assign sram_blwl_1078_configbus1[1078:1078] = sram_blwl_wl[1078:1078] ; -assign sram_blwl_1078_configbus0_b[1078:1078] = sram_blwl_blb[1078:1078] ; -sram6T_blwl sram_blwl_1078_ (sram_blwl_out[1078], sram_blwl_out[1078], sram_blwl_outb[1078], sram_blwl_1078_configbus0[1078:1078], sram_blwl_1078_configbus1[1078:1078] , sram_blwl_1078_configbus0_b[1078:1078] ); -wire [1079:1079] sram_blwl_1079_configbus0; -wire [1079:1079] sram_blwl_1079_configbus1; -wire [1079:1079] sram_blwl_1079_configbus0_b; -assign sram_blwl_1079_configbus0[1079:1079] = sram_blwl_bl[1079:1079] ; -assign sram_blwl_1079_configbus1[1079:1079] = sram_blwl_wl[1079:1079] ; -assign sram_blwl_1079_configbus0_b[1079:1079] = sram_blwl_blb[1079:1079] ; -sram6T_blwl sram_blwl_1079_ (sram_blwl_out[1079], sram_blwl_out[1079], sram_blwl_outb[1079], sram_blwl_1079_configbus0[1079:1079], sram_blwl_1079_configbus1[1079:1079] , sram_blwl_1079_configbus0_b[1079:1079] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- - -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6_ ----- -module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble6___in_0_, -input wire mode_ble6___in_1_, -input wire mode_ble6___in_2_, -input wire mode_ble6___in_3_, -input wire mode_ble6___in_4_, -input wire mode_ble6___in_5_, -output wire mode_ble6___out_0_, -input wire mode_ble6___clk_0_, -input [1016:1080] sram_blwl_bl , -input [1016:1080] sram_blwl_wl , -input [1016:1080] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ lut6_0_ ( - lut6_0___in_0_, lut6_0___in_1_, lut6_0___in_2_, lut6_0___in_3_, lut6_0___in_4_, lut6_0___in_5_, lut6_0___out_0_, -sram_blwl_bl[1016:1079] , -sram_blwl_wl[1016:1079] , -sram_blwl_blb[1016:1079] ); -grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_400_ ; -assign in_bus_mux_1level_tapbuf_size2_400_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_400_[1] = lut6_0___out_0_ ; -wire [1080:1080] mux_1level_tapbuf_size2_400_configbus0; -wire [1080:1080] mux_1level_tapbuf_size2_400_configbus1; -wire [1080:1080] mux_1level_tapbuf_size2_400_sram_blwl_out ; -wire [1080:1080] mux_1level_tapbuf_size2_400_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_400_configbus0[1080:1080] = sram_blwl_bl[1080:1080] ; -assign mux_1level_tapbuf_size2_400_configbus1[1080:1080] = sram_blwl_wl[1080:1080] ; -wire [1080:1080] mux_1level_tapbuf_size2_400_configbus0_b; -assign mux_1level_tapbuf_size2_400_configbus0_b[1080:1080] = sram_blwl_blb[1080:1080] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_400_ (in_bus_mux_1level_tapbuf_size2_400_, mode_ble6___out_0_, mux_1level_tapbuf_size2_400_sram_blwl_out[1080:1080] , -mux_1level_tapbuf_size2_400_sram_blwl_outb[1080:1080] ); -//----- SRAM bits for MUX[400], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1080_ (mux_1level_tapbuf_size2_400_sram_blwl_out[1080:1080] ,mux_1level_tapbuf_size2_400_sram_blwl_out[1080:1080] ,mux_1level_tapbuf_size2_400_sram_blwl_outb[1080:1080] ,mux_1level_tapbuf_size2_400_configbus0[1080:1080], mux_1level_tapbuf_size2_400_configbus1[1080:1080] , mux_1level_tapbuf_size2_400_configbus0_b[1080:1080] ); -direct_interc direct_interc_0_ (mode_ble6___in_0_, lut6_0___in_0_ ); -direct_interc direct_interc_1_ (mode_ble6___in_1_, lut6_0___in_1_ ); -direct_interc direct_interc_2_ (mode_ble6___in_2_, lut6_0___in_2_ ); -direct_interc direct_interc_3_ (mode_ble6___in_3_, lut6_0___in_3_ ); -direct_interc direct_interc_4_ (mode_ble6___in_4_, lut6_0___in_4_ ); -direct_interc direct_interc_5_ (mode_ble6___in_5_, lut6_0___in_5_ ); -direct_interc direct_interc_6_ (lut6_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_7_ (mode_ble6___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6_ ----- -module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut6___in_0_, -input wire mode_n1_lut6___in_1_, -input wire mode_n1_lut6___in_2_, -input wire mode_n1_lut6___in_3_, -input wire mode_n1_lut6___in_4_, -input wire mode_n1_lut6___in_5_, -output wire mode_n1_lut6___out_0_, -input wire mode_n1_lut6___clk_0_, -input [1016:1080] sram_blwl_bl , -input [1016:1080] sram_blwl_wl , -input [1016:1080] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6__ble6_0__mode_ble6_ ble6_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble6_0___in_0_, ble6_0___in_1_, ble6_0___in_2_, ble6_0___in_3_, ble6_0___in_4_, ble6_0___in_5_, ble6_0___out_0_, ble6_0___clk_0_, -sram_blwl_bl[1016:1080] , -sram_blwl_wl[1016:1080] , -sram_blwl_blb[1016:1080] ); -direct_interc direct_interc_8_ (ble6_0___out_0_, mode_n1_lut6___out_0_ ); -direct_interc direct_interc_9_ (mode_n1_lut6___in_0_, ble6_0___in_0_ ); -direct_interc direct_interc_10_ (mode_n1_lut6___in_1_, ble6_0___in_1_ ); -direct_interc direct_interc_11_ (mode_n1_lut6___in_2_, ble6_0___in_2_ ); -direct_interc direct_interc_12_ (mode_n1_lut6___in_3_, ble6_0___in_3_ ); -direct_interc direct_interc_13_ (mode_n1_lut6___in_4_, ble6_0___in_4_ ); -direct_interc direct_interc_14_ (mode_n1_lut6___in_5_, ble6_0___in_5_ ); -direct_interc direct_interc_15_ (mode_n1_lut6___clk_0_, ble6_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6_ ----- - -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ( -input wire lut6_0___in_0_, -input wire lut6_0___in_1_, -input wire lut6_0___in_2_, -input wire lut6_0___in_3_, -input wire lut6_0___in_4_, -input wire lut6_0___in_5_, -output wire lut6_0___out_0_, -input [1081:1144] sram_blwl_bl , -input [1081:1144] sram_blwl_wl , -input [1081:1144] sram_blwl_blb ); -wire [0:5] lut6_0___in; -assign lut6_0___in[0] = lut6_0___in_0_; -assign lut6_0___in[1] = lut6_0___in_1_; -assign lut6_0___in[2] = lut6_0___in_2_; -assign lut6_0___in[3] = lut6_0___in_3_; -assign lut6_0___in[4] = lut6_0___in_4_; -assign lut6_0___in[5] = lut6_0___in_5_; -wire [0:0] lut6_0___out; -assign lut6_0___out_0_ = lut6_0___out[0]; -wire [1081:1144] sram_blwl_out ; -wire [1081:1144] sram_blwl_outb ; -lut6 lut6_1_ ( -//----- Input and output ports ----- - lut6_0___in[0:5] , lut6_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[1081:1144] , sram_blwl_outb[1081:1144] ); -//----- Truth Table for LUT[1], size=6. ----- -//----- SRAM bits for LUT[1], size=6, num_sram=64. ----- -//-----0000000000000000000000000000000000000000000000000000000000000000----- -wire [1081:1081] sram_blwl_1081_configbus0; -wire [1081:1081] sram_blwl_1081_configbus1; -wire [1081:1081] sram_blwl_1081_configbus0_b; -assign sram_blwl_1081_configbus0[1081:1081] = sram_blwl_bl[1081:1081] ; -assign sram_blwl_1081_configbus1[1081:1081] = sram_blwl_wl[1081:1081] ; -assign sram_blwl_1081_configbus0_b[1081:1081] = sram_blwl_blb[1081:1081] ; -sram6T_blwl sram_blwl_1081_ (sram_blwl_out[1081], sram_blwl_out[1081], sram_blwl_outb[1081], sram_blwl_1081_configbus0[1081:1081], sram_blwl_1081_configbus1[1081:1081] , sram_blwl_1081_configbus0_b[1081:1081] ); -wire [1082:1082] sram_blwl_1082_configbus0; -wire [1082:1082] sram_blwl_1082_configbus1; -wire [1082:1082] sram_blwl_1082_configbus0_b; -assign sram_blwl_1082_configbus0[1082:1082] = sram_blwl_bl[1082:1082] ; -assign sram_blwl_1082_configbus1[1082:1082] = sram_blwl_wl[1082:1082] ; -assign sram_blwl_1082_configbus0_b[1082:1082] = sram_blwl_blb[1082:1082] ; -sram6T_blwl sram_blwl_1082_ (sram_blwl_out[1082], sram_blwl_out[1082], sram_blwl_outb[1082], sram_blwl_1082_configbus0[1082:1082], sram_blwl_1082_configbus1[1082:1082] , sram_blwl_1082_configbus0_b[1082:1082] ); -wire [1083:1083] sram_blwl_1083_configbus0; -wire [1083:1083] sram_blwl_1083_configbus1; -wire [1083:1083] sram_blwl_1083_configbus0_b; -assign sram_blwl_1083_configbus0[1083:1083] = sram_blwl_bl[1083:1083] ; -assign sram_blwl_1083_configbus1[1083:1083] = sram_blwl_wl[1083:1083] ; -assign sram_blwl_1083_configbus0_b[1083:1083] = sram_blwl_blb[1083:1083] ; -sram6T_blwl sram_blwl_1083_ (sram_blwl_out[1083], sram_blwl_out[1083], sram_blwl_outb[1083], sram_blwl_1083_configbus0[1083:1083], sram_blwl_1083_configbus1[1083:1083] , sram_blwl_1083_configbus0_b[1083:1083] ); -wire [1084:1084] sram_blwl_1084_configbus0; -wire [1084:1084] sram_blwl_1084_configbus1; -wire [1084:1084] sram_blwl_1084_configbus0_b; -assign sram_blwl_1084_configbus0[1084:1084] = sram_blwl_bl[1084:1084] ; -assign sram_blwl_1084_configbus1[1084:1084] = sram_blwl_wl[1084:1084] ; -assign sram_blwl_1084_configbus0_b[1084:1084] = sram_blwl_blb[1084:1084] ; -sram6T_blwl sram_blwl_1084_ (sram_blwl_out[1084], sram_blwl_out[1084], sram_blwl_outb[1084], sram_blwl_1084_configbus0[1084:1084], sram_blwl_1084_configbus1[1084:1084] , sram_blwl_1084_configbus0_b[1084:1084] ); -wire [1085:1085] sram_blwl_1085_configbus0; -wire [1085:1085] sram_blwl_1085_configbus1; -wire [1085:1085] sram_blwl_1085_configbus0_b; -assign sram_blwl_1085_configbus0[1085:1085] = sram_blwl_bl[1085:1085] ; -assign sram_blwl_1085_configbus1[1085:1085] = sram_blwl_wl[1085:1085] ; -assign sram_blwl_1085_configbus0_b[1085:1085] = sram_blwl_blb[1085:1085] ; -sram6T_blwl sram_blwl_1085_ (sram_blwl_out[1085], sram_blwl_out[1085], sram_blwl_outb[1085], sram_blwl_1085_configbus0[1085:1085], sram_blwl_1085_configbus1[1085:1085] , sram_blwl_1085_configbus0_b[1085:1085] ); -wire [1086:1086] sram_blwl_1086_configbus0; -wire [1086:1086] sram_blwl_1086_configbus1; -wire [1086:1086] sram_blwl_1086_configbus0_b; -assign sram_blwl_1086_configbus0[1086:1086] = sram_blwl_bl[1086:1086] ; -assign sram_blwl_1086_configbus1[1086:1086] = sram_blwl_wl[1086:1086] ; -assign sram_blwl_1086_configbus0_b[1086:1086] = sram_blwl_blb[1086:1086] ; -sram6T_blwl sram_blwl_1086_ (sram_blwl_out[1086], sram_blwl_out[1086], sram_blwl_outb[1086], sram_blwl_1086_configbus0[1086:1086], sram_blwl_1086_configbus1[1086:1086] , sram_blwl_1086_configbus0_b[1086:1086] ); -wire [1087:1087] sram_blwl_1087_configbus0; -wire [1087:1087] sram_blwl_1087_configbus1; -wire [1087:1087] sram_blwl_1087_configbus0_b; -assign sram_blwl_1087_configbus0[1087:1087] = sram_blwl_bl[1087:1087] ; -assign sram_blwl_1087_configbus1[1087:1087] = sram_blwl_wl[1087:1087] ; -assign sram_blwl_1087_configbus0_b[1087:1087] = sram_blwl_blb[1087:1087] ; -sram6T_blwl sram_blwl_1087_ (sram_blwl_out[1087], sram_blwl_out[1087], sram_blwl_outb[1087], sram_blwl_1087_configbus0[1087:1087], sram_blwl_1087_configbus1[1087:1087] , sram_blwl_1087_configbus0_b[1087:1087] ); -wire [1088:1088] sram_blwl_1088_configbus0; -wire [1088:1088] sram_blwl_1088_configbus1; -wire [1088:1088] sram_blwl_1088_configbus0_b; -assign sram_blwl_1088_configbus0[1088:1088] = sram_blwl_bl[1088:1088] ; -assign sram_blwl_1088_configbus1[1088:1088] = sram_blwl_wl[1088:1088] ; -assign sram_blwl_1088_configbus0_b[1088:1088] = sram_blwl_blb[1088:1088] ; -sram6T_blwl sram_blwl_1088_ (sram_blwl_out[1088], sram_blwl_out[1088], sram_blwl_outb[1088], sram_blwl_1088_configbus0[1088:1088], sram_blwl_1088_configbus1[1088:1088] , sram_blwl_1088_configbus0_b[1088:1088] ); -wire [1089:1089] sram_blwl_1089_configbus0; -wire [1089:1089] sram_blwl_1089_configbus1; -wire [1089:1089] sram_blwl_1089_configbus0_b; -assign sram_blwl_1089_configbus0[1089:1089] = sram_blwl_bl[1089:1089] ; -assign sram_blwl_1089_configbus1[1089:1089] = sram_blwl_wl[1089:1089] ; -assign sram_blwl_1089_configbus0_b[1089:1089] = sram_blwl_blb[1089:1089] ; -sram6T_blwl sram_blwl_1089_ (sram_blwl_out[1089], sram_blwl_out[1089], sram_blwl_outb[1089], sram_blwl_1089_configbus0[1089:1089], sram_blwl_1089_configbus1[1089:1089] , sram_blwl_1089_configbus0_b[1089:1089] ); -wire [1090:1090] sram_blwl_1090_configbus0; -wire [1090:1090] sram_blwl_1090_configbus1; -wire [1090:1090] sram_blwl_1090_configbus0_b; -assign sram_blwl_1090_configbus0[1090:1090] = sram_blwl_bl[1090:1090] ; -assign sram_blwl_1090_configbus1[1090:1090] = sram_blwl_wl[1090:1090] ; -assign sram_blwl_1090_configbus0_b[1090:1090] = sram_blwl_blb[1090:1090] ; -sram6T_blwl sram_blwl_1090_ (sram_blwl_out[1090], sram_blwl_out[1090], sram_blwl_outb[1090], sram_blwl_1090_configbus0[1090:1090], sram_blwl_1090_configbus1[1090:1090] , sram_blwl_1090_configbus0_b[1090:1090] ); -wire [1091:1091] sram_blwl_1091_configbus0; -wire [1091:1091] sram_blwl_1091_configbus1; -wire [1091:1091] sram_blwl_1091_configbus0_b; -assign sram_blwl_1091_configbus0[1091:1091] = sram_blwl_bl[1091:1091] ; -assign sram_blwl_1091_configbus1[1091:1091] = sram_blwl_wl[1091:1091] ; -assign sram_blwl_1091_configbus0_b[1091:1091] = sram_blwl_blb[1091:1091] ; -sram6T_blwl sram_blwl_1091_ (sram_blwl_out[1091], sram_blwl_out[1091], sram_blwl_outb[1091], sram_blwl_1091_configbus0[1091:1091], sram_blwl_1091_configbus1[1091:1091] , sram_blwl_1091_configbus0_b[1091:1091] ); -wire [1092:1092] sram_blwl_1092_configbus0; -wire [1092:1092] sram_blwl_1092_configbus1; -wire [1092:1092] sram_blwl_1092_configbus0_b; -assign sram_blwl_1092_configbus0[1092:1092] = sram_blwl_bl[1092:1092] ; -assign sram_blwl_1092_configbus1[1092:1092] = sram_blwl_wl[1092:1092] ; -assign sram_blwl_1092_configbus0_b[1092:1092] = sram_blwl_blb[1092:1092] ; -sram6T_blwl sram_blwl_1092_ (sram_blwl_out[1092], sram_blwl_out[1092], sram_blwl_outb[1092], sram_blwl_1092_configbus0[1092:1092], sram_blwl_1092_configbus1[1092:1092] , sram_blwl_1092_configbus0_b[1092:1092] ); -wire [1093:1093] sram_blwl_1093_configbus0; -wire [1093:1093] sram_blwl_1093_configbus1; -wire [1093:1093] sram_blwl_1093_configbus0_b; -assign sram_blwl_1093_configbus0[1093:1093] = sram_blwl_bl[1093:1093] ; -assign sram_blwl_1093_configbus1[1093:1093] = sram_blwl_wl[1093:1093] ; -assign sram_blwl_1093_configbus0_b[1093:1093] = sram_blwl_blb[1093:1093] ; -sram6T_blwl sram_blwl_1093_ (sram_blwl_out[1093], sram_blwl_out[1093], sram_blwl_outb[1093], sram_blwl_1093_configbus0[1093:1093], sram_blwl_1093_configbus1[1093:1093] , sram_blwl_1093_configbus0_b[1093:1093] ); -wire [1094:1094] sram_blwl_1094_configbus0; -wire [1094:1094] sram_blwl_1094_configbus1; -wire [1094:1094] sram_blwl_1094_configbus0_b; -assign sram_blwl_1094_configbus0[1094:1094] = sram_blwl_bl[1094:1094] ; -assign sram_blwl_1094_configbus1[1094:1094] = sram_blwl_wl[1094:1094] ; -assign sram_blwl_1094_configbus0_b[1094:1094] = sram_blwl_blb[1094:1094] ; -sram6T_blwl sram_blwl_1094_ (sram_blwl_out[1094], sram_blwl_out[1094], sram_blwl_outb[1094], sram_blwl_1094_configbus0[1094:1094], sram_blwl_1094_configbus1[1094:1094] , sram_blwl_1094_configbus0_b[1094:1094] ); -wire [1095:1095] sram_blwl_1095_configbus0; -wire [1095:1095] sram_blwl_1095_configbus1; -wire [1095:1095] sram_blwl_1095_configbus0_b; -assign sram_blwl_1095_configbus0[1095:1095] = sram_blwl_bl[1095:1095] ; -assign sram_blwl_1095_configbus1[1095:1095] = sram_blwl_wl[1095:1095] ; -assign sram_blwl_1095_configbus0_b[1095:1095] = sram_blwl_blb[1095:1095] ; -sram6T_blwl sram_blwl_1095_ (sram_blwl_out[1095], sram_blwl_out[1095], sram_blwl_outb[1095], sram_blwl_1095_configbus0[1095:1095], sram_blwl_1095_configbus1[1095:1095] , sram_blwl_1095_configbus0_b[1095:1095] ); -wire [1096:1096] sram_blwl_1096_configbus0; -wire [1096:1096] sram_blwl_1096_configbus1; -wire [1096:1096] sram_blwl_1096_configbus0_b; -assign sram_blwl_1096_configbus0[1096:1096] = sram_blwl_bl[1096:1096] ; -assign sram_blwl_1096_configbus1[1096:1096] = sram_blwl_wl[1096:1096] ; -assign sram_blwl_1096_configbus0_b[1096:1096] = sram_blwl_blb[1096:1096] ; -sram6T_blwl sram_blwl_1096_ (sram_blwl_out[1096], sram_blwl_out[1096], sram_blwl_outb[1096], sram_blwl_1096_configbus0[1096:1096], sram_blwl_1096_configbus1[1096:1096] , sram_blwl_1096_configbus0_b[1096:1096] ); -wire [1097:1097] sram_blwl_1097_configbus0; -wire [1097:1097] sram_blwl_1097_configbus1; -wire [1097:1097] sram_blwl_1097_configbus0_b; -assign sram_blwl_1097_configbus0[1097:1097] = sram_blwl_bl[1097:1097] ; -assign sram_blwl_1097_configbus1[1097:1097] = sram_blwl_wl[1097:1097] ; -assign sram_blwl_1097_configbus0_b[1097:1097] = sram_blwl_blb[1097:1097] ; -sram6T_blwl sram_blwl_1097_ (sram_blwl_out[1097], sram_blwl_out[1097], sram_blwl_outb[1097], sram_blwl_1097_configbus0[1097:1097], sram_blwl_1097_configbus1[1097:1097] , sram_blwl_1097_configbus0_b[1097:1097] ); -wire [1098:1098] sram_blwl_1098_configbus0; -wire [1098:1098] sram_blwl_1098_configbus1; -wire [1098:1098] sram_blwl_1098_configbus0_b; -assign sram_blwl_1098_configbus0[1098:1098] = sram_blwl_bl[1098:1098] ; -assign sram_blwl_1098_configbus1[1098:1098] = sram_blwl_wl[1098:1098] ; -assign sram_blwl_1098_configbus0_b[1098:1098] = sram_blwl_blb[1098:1098] ; -sram6T_blwl sram_blwl_1098_ (sram_blwl_out[1098], sram_blwl_out[1098], sram_blwl_outb[1098], sram_blwl_1098_configbus0[1098:1098], sram_blwl_1098_configbus1[1098:1098] , sram_blwl_1098_configbus0_b[1098:1098] ); -wire [1099:1099] sram_blwl_1099_configbus0; -wire [1099:1099] sram_blwl_1099_configbus1; -wire [1099:1099] sram_blwl_1099_configbus0_b; -assign sram_blwl_1099_configbus0[1099:1099] = sram_blwl_bl[1099:1099] ; -assign sram_blwl_1099_configbus1[1099:1099] = sram_blwl_wl[1099:1099] ; -assign sram_blwl_1099_configbus0_b[1099:1099] = sram_blwl_blb[1099:1099] ; -sram6T_blwl sram_blwl_1099_ (sram_blwl_out[1099], sram_blwl_out[1099], sram_blwl_outb[1099], sram_blwl_1099_configbus0[1099:1099], sram_blwl_1099_configbus1[1099:1099] , sram_blwl_1099_configbus0_b[1099:1099] ); -wire [1100:1100] sram_blwl_1100_configbus0; -wire [1100:1100] sram_blwl_1100_configbus1; -wire [1100:1100] sram_blwl_1100_configbus0_b; -assign sram_blwl_1100_configbus0[1100:1100] = sram_blwl_bl[1100:1100] ; -assign sram_blwl_1100_configbus1[1100:1100] = sram_blwl_wl[1100:1100] ; -assign sram_blwl_1100_configbus0_b[1100:1100] = sram_blwl_blb[1100:1100] ; -sram6T_blwl sram_blwl_1100_ (sram_blwl_out[1100], sram_blwl_out[1100], sram_blwl_outb[1100], sram_blwl_1100_configbus0[1100:1100], sram_blwl_1100_configbus1[1100:1100] , sram_blwl_1100_configbus0_b[1100:1100] ); -wire [1101:1101] sram_blwl_1101_configbus0; -wire [1101:1101] sram_blwl_1101_configbus1; -wire [1101:1101] sram_blwl_1101_configbus0_b; -assign sram_blwl_1101_configbus0[1101:1101] = sram_blwl_bl[1101:1101] ; -assign sram_blwl_1101_configbus1[1101:1101] = sram_blwl_wl[1101:1101] ; -assign sram_blwl_1101_configbus0_b[1101:1101] = sram_blwl_blb[1101:1101] ; -sram6T_blwl sram_blwl_1101_ (sram_blwl_out[1101], sram_blwl_out[1101], sram_blwl_outb[1101], sram_blwl_1101_configbus0[1101:1101], sram_blwl_1101_configbus1[1101:1101] , sram_blwl_1101_configbus0_b[1101:1101] ); -wire [1102:1102] sram_blwl_1102_configbus0; -wire [1102:1102] sram_blwl_1102_configbus1; -wire [1102:1102] sram_blwl_1102_configbus0_b; -assign sram_blwl_1102_configbus0[1102:1102] = sram_blwl_bl[1102:1102] ; -assign sram_blwl_1102_configbus1[1102:1102] = sram_blwl_wl[1102:1102] ; -assign sram_blwl_1102_configbus0_b[1102:1102] = sram_blwl_blb[1102:1102] ; -sram6T_blwl sram_blwl_1102_ (sram_blwl_out[1102], sram_blwl_out[1102], sram_blwl_outb[1102], sram_blwl_1102_configbus0[1102:1102], sram_blwl_1102_configbus1[1102:1102] , sram_blwl_1102_configbus0_b[1102:1102] ); -wire [1103:1103] sram_blwl_1103_configbus0; -wire [1103:1103] sram_blwl_1103_configbus1; -wire [1103:1103] sram_blwl_1103_configbus0_b; -assign sram_blwl_1103_configbus0[1103:1103] = sram_blwl_bl[1103:1103] ; -assign sram_blwl_1103_configbus1[1103:1103] = sram_blwl_wl[1103:1103] ; -assign sram_blwl_1103_configbus0_b[1103:1103] = sram_blwl_blb[1103:1103] ; -sram6T_blwl sram_blwl_1103_ (sram_blwl_out[1103], sram_blwl_out[1103], sram_blwl_outb[1103], sram_blwl_1103_configbus0[1103:1103], sram_blwl_1103_configbus1[1103:1103] , sram_blwl_1103_configbus0_b[1103:1103] ); -wire [1104:1104] sram_blwl_1104_configbus0; -wire [1104:1104] sram_blwl_1104_configbus1; -wire [1104:1104] sram_blwl_1104_configbus0_b; -assign sram_blwl_1104_configbus0[1104:1104] = sram_blwl_bl[1104:1104] ; -assign sram_blwl_1104_configbus1[1104:1104] = sram_blwl_wl[1104:1104] ; -assign sram_blwl_1104_configbus0_b[1104:1104] = sram_blwl_blb[1104:1104] ; -sram6T_blwl sram_blwl_1104_ (sram_blwl_out[1104], sram_blwl_out[1104], sram_blwl_outb[1104], sram_blwl_1104_configbus0[1104:1104], sram_blwl_1104_configbus1[1104:1104] , sram_blwl_1104_configbus0_b[1104:1104] ); -wire [1105:1105] sram_blwl_1105_configbus0; -wire [1105:1105] sram_blwl_1105_configbus1; -wire [1105:1105] sram_blwl_1105_configbus0_b; -assign sram_blwl_1105_configbus0[1105:1105] = sram_blwl_bl[1105:1105] ; -assign sram_blwl_1105_configbus1[1105:1105] = sram_blwl_wl[1105:1105] ; -assign sram_blwl_1105_configbus0_b[1105:1105] = sram_blwl_blb[1105:1105] ; -sram6T_blwl sram_blwl_1105_ (sram_blwl_out[1105], sram_blwl_out[1105], sram_blwl_outb[1105], sram_blwl_1105_configbus0[1105:1105], sram_blwl_1105_configbus1[1105:1105] , sram_blwl_1105_configbus0_b[1105:1105] ); -wire [1106:1106] sram_blwl_1106_configbus0; -wire [1106:1106] sram_blwl_1106_configbus1; -wire [1106:1106] sram_blwl_1106_configbus0_b; -assign sram_blwl_1106_configbus0[1106:1106] = sram_blwl_bl[1106:1106] ; -assign sram_blwl_1106_configbus1[1106:1106] = sram_blwl_wl[1106:1106] ; -assign sram_blwl_1106_configbus0_b[1106:1106] = sram_blwl_blb[1106:1106] ; -sram6T_blwl sram_blwl_1106_ (sram_blwl_out[1106], sram_blwl_out[1106], sram_blwl_outb[1106], sram_blwl_1106_configbus0[1106:1106], sram_blwl_1106_configbus1[1106:1106] , sram_blwl_1106_configbus0_b[1106:1106] ); -wire [1107:1107] sram_blwl_1107_configbus0; -wire [1107:1107] sram_blwl_1107_configbus1; -wire [1107:1107] sram_blwl_1107_configbus0_b; -assign sram_blwl_1107_configbus0[1107:1107] = sram_blwl_bl[1107:1107] ; -assign sram_blwl_1107_configbus1[1107:1107] = sram_blwl_wl[1107:1107] ; -assign sram_blwl_1107_configbus0_b[1107:1107] = sram_blwl_blb[1107:1107] ; -sram6T_blwl sram_blwl_1107_ (sram_blwl_out[1107], sram_blwl_out[1107], sram_blwl_outb[1107], sram_blwl_1107_configbus0[1107:1107], sram_blwl_1107_configbus1[1107:1107] , sram_blwl_1107_configbus0_b[1107:1107] ); -wire [1108:1108] sram_blwl_1108_configbus0; -wire [1108:1108] sram_blwl_1108_configbus1; -wire [1108:1108] sram_blwl_1108_configbus0_b; -assign sram_blwl_1108_configbus0[1108:1108] = sram_blwl_bl[1108:1108] ; -assign sram_blwl_1108_configbus1[1108:1108] = sram_blwl_wl[1108:1108] ; -assign sram_blwl_1108_configbus0_b[1108:1108] = sram_blwl_blb[1108:1108] ; -sram6T_blwl sram_blwl_1108_ (sram_blwl_out[1108], sram_blwl_out[1108], sram_blwl_outb[1108], sram_blwl_1108_configbus0[1108:1108], sram_blwl_1108_configbus1[1108:1108] , sram_blwl_1108_configbus0_b[1108:1108] ); -wire [1109:1109] sram_blwl_1109_configbus0; -wire [1109:1109] sram_blwl_1109_configbus1; -wire [1109:1109] sram_blwl_1109_configbus0_b; -assign sram_blwl_1109_configbus0[1109:1109] = sram_blwl_bl[1109:1109] ; -assign sram_blwl_1109_configbus1[1109:1109] = sram_blwl_wl[1109:1109] ; -assign sram_blwl_1109_configbus0_b[1109:1109] = sram_blwl_blb[1109:1109] ; -sram6T_blwl sram_blwl_1109_ (sram_blwl_out[1109], sram_blwl_out[1109], sram_blwl_outb[1109], sram_blwl_1109_configbus0[1109:1109], sram_blwl_1109_configbus1[1109:1109] , sram_blwl_1109_configbus0_b[1109:1109] ); -wire [1110:1110] sram_blwl_1110_configbus0; -wire [1110:1110] sram_blwl_1110_configbus1; -wire [1110:1110] sram_blwl_1110_configbus0_b; -assign sram_blwl_1110_configbus0[1110:1110] = sram_blwl_bl[1110:1110] ; -assign sram_blwl_1110_configbus1[1110:1110] = sram_blwl_wl[1110:1110] ; -assign sram_blwl_1110_configbus0_b[1110:1110] = sram_blwl_blb[1110:1110] ; -sram6T_blwl sram_blwl_1110_ (sram_blwl_out[1110], sram_blwl_out[1110], sram_blwl_outb[1110], sram_blwl_1110_configbus0[1110:1110], sram_blwl_1110_configbus1[1110:1110] , sram_blwl_1110_configbus0_b[1110:1110] ); -wire [1111:1111] sram_blwl_1111_configbus0; -wire [1111:1111] sram_blwl_1111_configbus1; -wire [1111:1111] sram_blwl_1111_configbus0_b; -assign sram_blwl_1111_configbus0[1111:1111] = sram_blwl_bl[1111:1111] ; -assign sram_blwl_1111_configbus1[1111:1111] = sram_blwl_wl[1111:1111] ; -assign sram_blwl_1111_configbus0_b[1111:1111] = sram_blwl_blb[1111:1111] ; -sram6T_blwl sram_blwl_1111_ (sram_blwl_out[1111], sram_blwl_out[1111], sram_blwl_outb[1111], sram_blwl_1111_configbus0[1111:1111], sram_blwl_1111_configbus1[1111:1111] , sram_blwl_1111_configbus0_b[1111:1111] ); -wire [1112:1112] sram_blwl_1112_configbus0; -wire [1112:1112] sram_blwl_1112_configbus1; -wire [1112:1112] sram_blwl_1112_configbus0_b; -assign sram_blwl_1112_configbus0[1112:1112] = sram_blwl_bl[1112:1112] ; -assign sram_blwl_1112_configbus1[1112:1112] = sram_blwl_wl[1112:1112] ; -assign sram_blwl_1112_configbus0_b[1112:1112] = sram_blwl_blb[1112:1112] ; -sram6T_blwl sram_blwl_1112_ (sram_blwl_out[1112], sram_blwl_out[1112], sram_blwl_outb[1112], sram_blwl_1112_configbus0[1112:1112], sram_blwl_1112_configbus1[1112:1112] , sram_blwl_1112_configbus0_b[1112:1112] ); -wire [1113:1113] sram_blwl_1113_configbus0; -wire [1113:1113] sram_blwl_1113_configbus1; -wire [1113:1113] sram_blwl_1113_configbus0_b; -assign sram_blwl_1113_configbus0[1113:1113] = sram_blwl_bl[1113:1113] ; -assign sram_blwl_1113_configbus1[1113:1113] = sram_blwl_wl[1113:1113] ; -assign sram_blwl_1113_configbus0_b[1113:1113] = sram_blwl_blb[1113:1113] ; -sram6T_blwl sram_blwl_1113_ (sram_blwl_out[1113], sram_blwl_out[1113], sram_blwl_outb[1113], sram_blwl_1113_configbus0[1113:1113], sram_blwl_1113_configbus1[1113:1113] , sram_blwl_1113_configbus0_b[1113:1113] ); -wire [1114:1114] sram_blwl_1114_configbus0; -wire [1114:1114] sram_blwl_1114_configbus1; -wire [1114:1114] sram_blwl_1114_configbus0_b; -assign sram_blwl_1114_configbus0[1114:1114] = sram_blwl_bl[1114:1114] ; -assign sram_blwl_1114_configbus1[1114:1114] = sram_blwl_wl[1114:1114] ; -assign sram_blwl_1114_configbus0_b[1114:1114] = sram_blwl_blb[1114:1114] ; -sram6T_blwl sram_blwl_1114_ (sram_blwl_out[1114], sram_blwl_out[1114], sram_blwl_outb[1114], sram_blwl_1114_configbus0[1114:1114], sram_blwl_1114_configbus1[1114:1114] , sram_blwl_1114_configbus0_b[1114:1114] ); -wire [1115:1115] sram_blwl_1115_configbus0; -wire [1115:1115] sram_blwl_1115_configbus1; -wire [1115:1115] sram_blwl_1115_configbus0_b; -assign sram_blwl_1115_configbus0[1115:1115] = sram_blwl_bl[1115:1115] ; -assign sram_blwl_1115_configbus1[1115:1115] = sram_blwl_wl[1115:1115] ; -assign sram_blwl_1115_configbus0_b[1115:1115] = sram_blwl_blb[1115:1115] ; -sram6T_blwl sram_blwl_1115_ (sram_blwl_out[1115], sram_blwl_out[1115], sram_blwl_outb[1115], sram_blwl_1115_configbus0[1115:1115], sram_blwl_1115_configbus1[1115:1115] , sram_blwl_1115_configbus0_b[1115:1115] ); -wire [1116:1116] sram_blwl_1116_configbus0; -wire [1116:1116] sram_blwl_1116_configbus1; -wire [1116:1116] sram_blwl_1116_configbus0_b; -assign sram_blwl_1116_configbus0[1116:1116] = sram_blwl_bl[1116:1116] ; -assign sram_blwl_1116_configbus1[1116:1116] = sram_blwl_wl[1116:1116] ; -assign sram_blwl_1116_configbus0_b[1116:1116] = sram_blwl_blb[1116:1116] ; -sram6T_blwl sram_blwl_1116_ (sram_blwl_out[1116], sram_blwl_out[1116], sram_blwl_outb[1116], sram_blwl_1116_configbus0[1116:1116], sram_blwl_1116_configbus1[1116:1116] , sram_blwl_1116_configbus0_b[1116:1116] ); -wire [1117:1117] sram_blwl_1117_configbus0; -wire [1117:1117] sram_blwl_1117_configbus1; -wire [1117:1117] sram_blwl_1117_configbus0_b; -assign sram_blwl_1117_configbus0[1117:1117] = sram_blwl_bl[1117:1117] ; -assign sram_blwl_1117_configbus1[1117:1117] = sram_blwl_wl[1117:1117] ; -assign sram_blwl_1117_configbus0_b[1117:1117] = sram_blwl_blb[1117:1117] ; -sram6T_blwl sram_blwl_1117_ (sram_blwl_out[1117], sram_blwl_out[1117], sram_blwl_outb[1117], sram_blwl_1117_configbus0[1117:1117], sram_blwl_1117_configbus1[1117:1117] , sram_blwl_1117_configbus0_b[1117:1117] ); -wire [1118:1118] sram_blwl_1118_configbus0; -wire [1118:1118] sram_blwl_1118_configbus1; -wire [1118:1118] sram_blwl_1118_configbus0_b; -assign sram_blwl_1118_configbus0[1118:1118] = sram_blwl_bl[1118:1118] ; -assign sram_blwl_1118_configbus1[1118:1118] = sram_blwl_wl[1118:1118] ; -assign sram_blwl_1118_configbus0_b[1118:1118] = sram_blwl_blb[1118:1118] ; -sram6T_blwl sram_blwl_1118_ (sram_blwl_out[1118], sram_blwl_out[1118], sram_blwl_outb[1118], sram_blwl_1118_configbus0[1118:1118], sram_blwl_1118_configbus1[1118:1118] , sram_blwl_1118_configbus0_b[1118:1118] ); -wire [1119:1119] sram_blwl_1119_configbus0; -wire [1119:1119] sram_blwl_1119_configbus1; -wire [1119:1119] sram_blwl_1119_configbus0_b; -assign sram_blwl_1119_configbus0[1119:1119] = sram_blwl_bl[1119:1119] ; -assign sram_blwl_1119_configbus1[1119:1119] = sram_blwl_wl[1119:1119] ; -assign sram_blwl_1119_configbus0_b[1119:1119] = sram_blwl_blb[1119:1119] ; -sram6T_blwl sram_blwl_1119_ (sram_blwl_out[1119], sram_blwl_out[1119], sram_blwl_outb[1119], sram_blwl_1119_configbus0[1119:1119], sram_blwl_1119_configbus1[1119:1119] , sram_blwl_1119_configbus0_b[1119:1119] ); -wire [1120:1120] sram_blwl_1120_configbus0; -wire [1120:1120] sram_blwl_1120_configbus1; -wire [1120:1120] sram_blwl_1120_configbus0_b; -assign sram_blwl_1120_configbus0[1120:1120] = sram_blwl_bl[1120:1120] ; -assign sram_blwl_1120_configbus1[1120:1120] = sram_blwl_wl[1120:1120] ; -assign sram_blwl_1120_configbus0_b[1120:1120] = sram_blwl_blb[1120:1120] ; -sram6T_blwl sram_blwl_1120_ (sram_blwl_out[1120], sram_blwl_out[1120], sram_blwl_outb[1120], sram_blwl_1120_configbus0[1120:1120], sram_blwl_1120_configbus1[1120:1120] , sram_blwl_1120_configbus0_b[1120:1120] ); -wire [1121:1121] sram_blwl_1121_configbus0; -wire [1121:1121] sram_blwl_1121_configbus1; -wire [1121:1121] sram_blwl_1121_configbus0_b; -assign sram_blwl_1121_configbus0[1121:1121] = sram_blwl_bl[1121:1121] ; -assign sram_blwl_1121_configbus1[1121:1121] = sram_blwl_wl[1121:1121] ; -assign sram_blwl_1121_configbus0_b[1121:1121] = sram_blwl_blb[1121:1121] ; -sram6T_blwl sram_blwl_1121_ (sram_blwl_out[1121], sram_blwl_out[1121], sram_blwl_outb[1121], sram_blwl_1121_configbus0[1121:1121], sram_blwl_1121_configbus1[1121:1121] , sram_blwl_1121_configbus0_b[1121:1121] ); -wire [1122:1122] sram_blwl_1122_configbus0; -wire [1122:1122] sram_blwl_1122_configbus1; -wire [1122:1122] sram_blwl_1122_configbus0_b; -assign sram_blwl_1122_configbus0[1122:1122] = sram_blwl_bl[1122:1122] ; -assign sram_blwl_1122_configbus1[1122:1122] = sram_blwl_wl[1122:1122] ; -assign sram_blwl_1122_configbus0_b[1122:1122] = sram_blwl_blb[1122:1122] ; -sram6T_blwl sram_blwl_1122_ (sram_blwl_out[1122], sram_blwl_out[1122], sram_blwl_outb[1122], sram_blwl_1122_configbus0[1122:1122], sram_blwl_1122_configbus1[1122:1122] , sram_blwl_1122_configbus0_b[1122:1122] ); -wire [1123:1123] sram_blwl_1123_configbus0; -wire [1123:1123] sram_blwl_1123_configbus1; -wire [1123:1123] sram_blwl_1123_configbus0_b; -assign sram_blwl_1123_configbus0[1123:1123] = sram_blwl_bl[1123:1123] ; -assign sram_blwl_1123_configbus1[1123:1123] = sram_blwl_wl[1123:1123] ; -assign sram_blwl_1123_configbus0_b[1123:1123] = sram_blwl_blb[1123:1123] ; -sram6T_blwl sram_blwl_1123_ (sram_blwl_out[1123], sram_blwl_out[1123], sram_blwl_outb[1123], sram_blwl_1123_configbus0[1123:1123], sram_blwl_1123_configbus1[1123:1123] , sram_blwl_1123_configbus0_b[1123:1123] ); -wire [1124:1124] sram_blwl_1124_configbus0; -wire [1124:1124] sram_blwl_1124_configbus1; -wire [1124:1124] sram_blwl_1124_configbus0_b; -assign sram_blwl_1124_configbus0[1124:1124] = sram_blwl_bl[1124:1124] ; -assign sram_blwl_1124_configbus1[1124:1124] = sram_blwl_wl[1124:1124] ; -assign sram_blwl_1124_configbus0_b[1124:1124] = sram_blwl_blb[1124:1124] ; -sram6T_blwl sram_blwl_1124_ (sram_blwl_out[1124], sram_blwl_out[1124], sram_blwl_outb[1124], sram_blwl_1124_configbus0[1124:1124], sram_blwl_1124_configbus1[1124:1124] , sram_blwl_1124_configbus0_b[1124:1124] ); -wire [1125:1125] sram_blwl_1125_configbus0; -wire [1125:1125] sram_blwl_1125_configbus1; -wire [1125:1125] sram_blwl_1125_configbus0_b; -assign sram_blwl_1125_configbus0[1125:1125] = sram_blwl_bl[1125:1125] ; -assign sram_blwl_1125_configbus1[1125:1125] = sram_blwl_wl[1125:1125] ; -assign sram_blwl_1125_configbus0_b[1125:1125] = sram_blwl_blb[1125:1125] ; -sram6T_blwl sram_blwl_1125_ (sram_blwl_out[1125], sram_blwl_out[1125], sram_blwl_outb[1125], sram_blwl_1125_configbus0[1125:1125], sram_blwl_1125_configbus1[1125:1125] , sram_blwl_1125_configbus0_b[1125:1125] ); -wire [1126:1126] sram_blwl_1126_configbus0; -wire [1126:1126] sram_blwl_1126_configbus1; -wire [1126:1126] sram_blwl_1126_configbus0_b; -assign sram_blwl_1126_configbus0[1126:1126] = sram_blwl_bl[1126:1126] ; -assign sram_blwl_1126_configbus1[1126:1126] = sram_blwl_wl[1126:1126] ; -assign sram_blwl_1126_configbus0_b[1126:1126] = sram_blwl_blb[1126:1126] ; -sram6T_blwl sram_blwl_1126_ (sram_blwl_out[1126], sram_blwl_out[1126], sram_blwl_outb[1126], sram_blwl_1126_configbus0[1126:1126], sram_blwl_1126_configbus1[1126:1126] , sram_blwl_1126_configbus0_b[1126:1126] ); -wire [1127:1127] sram_blwl_1127_configbus0; -wire [1127:1127] sram_blwl_1127_configbus1; -wire [1127:1127] sram_blwl_1127_configbus0_b; -assign sram_blwl_1127_configbus0[1127:1127] = sram_blwl_bl[1127:1127] ; -assign sram_blwl_1127_configbus1[1127:1127] = sram_blwl_wl[1127:1127] ; -assign sram_blwl_1127_configbus0_b[1127:1127] = sram_blwl_blb[1127:1127] ; -sram6T_blwl sram_blwl_1127_ (sram_blwl_out[1127], sram_blwl_out[1127], sram_blwl_outb[1127], sram_blwl_1127_configbus0[1127:1127], sram_blwl_1127_configbus1[1127:1127] , sram_blwl_1127_configbus0_b[1127:1127] ); -wire [1128:1128] sram_blwl_1128_configbus0; -wire [1128:1128] sram_blwl_1128_configbus1; -wire [1128:1128] sram_blwl_1128_configbus0_b; -assign sram_blwl_1128_configbus0[1128:1128] = sram_blwl_bl[1128:1128] ; -assign sram_blwl_1128_configbus1[1128:1128] = sram_blwl_wl[1128:1128] ; -assign sram_blwl_1128_configbus0_b[1128:1128] = sram_blwl_blb[1128:1128] ; -sram6T_blwl sram_blwl_1128_ (sram_blwl_out[1128], sram_blwl_out[1128], sram_blwl_outb[1128], sram_blwl_1128_configbus0[1128:1128], sram_blwl_1128_configbus1[1128:1128] , sram_blwl_1128_configbus0_b[1128:1128] ); -wire [1129:1129] sram_blwl_1129_configbus0; -wire [1129:1129] sram_blwl_1129_configbus1; -wire [1129:1129] sram_blwl_1129_configbus0_b; -assign sram_blwl_1129_configbus0[1129:1129] = sram_blwl_bl[1129:1129] ; -assign sram_blwl_1129_configbus1[1129:1129] = sram_blwl_wl[1129:1129] ; -assign sram_blwl_1129_configbus0_b[1129:1129] = sram_blwl_blb[1129:1129] ; -sram6T_blwl sram_blwl_1129_ (sram_blwl_out[1129], sram_blwl_out[1129], sram_blwl_outb[1129], sram_blwl_1129_configbus0[1129:1129], sram_blwl_1129_configbus1[1129:1129] , sram_blwl_1129_configbus0_b[1129:1129] ); -wire [1130:1130] sram_blwl_1130_configbus0; -wire [1130:1130] sram_blwl_1130_configbus1; -wire [1130:1130] sram_blwl_1130_configbus0_b; -assign sram_blwl_1130_configbus0[1130:1130] = sram_blwl_bl[1130:1130] ; -assign sram_blwl_1130_configbus1[1130:1130] = sram_blwl_wl[1130:1130] ; -assign sram_blwl_1130_configbus0_b[1130:1130] = sram_blwl_blb[1130:1130] ; -sram6T_blwl sram_blwl_1130_ (sram_blwl_out[1130], sram_blwl_out[1130], sram_blwl_outb[1130], sram_blwl_1130_configbus0[1130:1130], sram_blwl_1130_configbus1[1130:1130] , sram_blwl_1130_configbus0_b[1130:1130] ); -wire [1131:1131] sram_blwl_1131_configbus0; -wire [1131:1131] sram_blwl_1131_configbus1; -wire [1131:1131] sram_blwl_1131_configbus0_b; -assign sram_blwl_1131_configbus0[1131:1131] = sram_blwl_bl[1131:1131] ; -assign sram_blwl_1131_configbus1[1131:1131] = sram_blwl_wl[1131:1131] ; -assign sram_blwl_1131_configbus0_b[1131:1131] = sram_blwl_blb[1131:1131] ; -sram6T_blwl sram_blwl_1131_ (sram_blwl_out[1131], sram_blwl_out[1131], sram_blwl_outb[1131], sram_blwl_1131_configbus0[1131:1131], sram_blwl_1131_configbus1[1131:1131] , sram_blwl_1131_configbus0_b[1131:1131] ); -wire [1132:1132] sram_blwl_1132_configbus0; -wire [1132:1132] sram_blwl_1132_configbus1; -wire [1132:1132] sram_blwl_1132_configbus0_b; -assign sram_blwl_1132_configbus0[1132:1132] = sram_blwl_bl[1132:1132] ; -assign sram_blwl_1132_configbus1[1132:1132] = sram_blwl_wl[1132:1132] ; -assign sram_blwl_1132_configbus0_b[1132:1132] = sram_blwl_blb[1132:1132] ; -sram6T_blwl sram_blwl_1132_ (sram_blwl_out[1132], sram_blwl_out[1132], sram_blwl_outb[1132], sram_blwl_1132_configbus0[1132:1132], sram_blwl_1132_configbus1[1132:1132] , sram_blwl_1132_configbus0_b[1132:1132] ); -wire [1133:1133] sram_blwl_1133_configbus0; -wire [1133:1133] sram_blwl_1133_configbus1; -wire [1133:1133] sram_blwl_1133_configbus0_b; -assign sram_blwl_1133_configbus0[1133:1133] = sram_blwl_bl[1133:1133] ; -assign sram_blwl_1133_configbus1[1133:1133] = sram_blwl_wl[1133:1133] ; -assign sram_blwl_1133_configbus0_b[1133:1133] = sram_blwl_blb[1133:1133] ; -sram6T_blwl sram_blwl_1133_ (sram_blwl_out[1133], sram_blwl_out[1133], sram_blwl_outb[1133], sram_blwl_1133_configbus0[1133:1133], sram_blwl_1133_configbus1[1133:1133] , sram_blwl_1133_configbus0_b[1133:1133] ); -wire [1134:1134] sram_blwl_1134_configbus0; -wire [1134:1134] sram_blwl_1134_configbus1; -wire [1134:1134] sram_blwl_1134_configbus0_b; -assign sram_blwl_1134_configbus0[1134:1134] = sram_blwl_bl[1134:1134] ; -assign sram_blwl_1134_configbus1[1134:1134] = sram_blwl_wl[1134:1134] ; -assign sram_blwl_1134_configbus0_b[1134:1134] = sram_blwl_blb[1134:1134] ; -sram6T_blwl sram_blwl_1134_ (sram_blwl_out[1134], sram_blwl_out[1134], sram_blwl_outb[1134], sram_blwl_1134_configbus0[1134:1134], sram_blwl_1134_configbus1[1134:1134] , sram_blwl_1134_configbus0_b[1134:1134] ); -wire [1135:1135] sram_blwl_1135_configbus0; -wire [1135:1135] sram_blwl_1135_configbus1; -wire [1135:1135] sram_blwl_1135_configbus0_b; -assign sram_blwl_1135_configbus0[1135:1135] = sram_blwl_bl[1135:1135] ; -assign sram_blwl_1135_configbus1[1135:1135] = sram_blwl_wl[1135:1135] ; -assign sram_blwl_1135_configbus0_b[1135:1135] = sram_blwl_blb[1135:1135] ; -sram6T_blwl sram_blwl_1135_ (sram_blwl_out[1135], sram_blwl_out[1135], sram_blwl_outb[1135], sram_blwl_1135_configbus0[1135:1135], sram_blwl_1135_configbus1[1135:1135] , sram_blwl_1135_configbus0_b[1135:1135] ); -wire [1136:1136] sram_blwl_1136_configbus0; -wire [1136:1136] sram_blwl_1136_configbus1; -wire [1136:1136] sram_blwl_1136_configbus0_b; -assign sram_blwl_1136_configbus0[1136:1136] = sram_blwl_bl[1136:1136] ; -assign sram_blwl_1136_configbus1[1136:1136] = sram_blwl_wl[1136:1136] ; -assign sram_blwl_1136_configbus0_b[1136:1136] = sram_blwl_blb[1136:1136] ; -sram6T_blwl sram_blwl_1136_ (sram_blwl_out[1136], sram_blwl_out[1136], sram_blwl_outb[1136], sram_blwl_1136_configbus0[1136:1136], sram_blwl_1136_configbus1[1136:1136] , sram_blwl_1136_configbus0_b[1136:1136] ); -wire [1137:1137] sram_blwl_1137_configbus0; -wire [1137:1137] sram_blwl_1137_configbus1; -wire [1137:1137] sram_blwl_1137_configbus0_b; -assign sram_blwl_1137_configbus0[1137:1137] = sram_blwl_bl[1137:1137] ; -assign sram_blwl_1137_configbus1[1137:1137] = sram_blwl_wl[1137:1137] ; -assign sram_blwl_1137_configbus0_b[1137:1137] = sram_blwl_blb[1137:1137] ; -sram6T_blwl sram_blwl_1137_ (sram_blwl_out[1137], sram_blwl_out[1137], sram_blwl_outb[1137], sram_blwl_1137_configbus0[1137:1137], sram_blwl_1137_configbus1[1137:1137] , sram_blwl_1137_configbus0_b[1137:1137] ); -wire [1138:1138] sram_blwl_1138_configbus0; -wire [1138:1138] sram_blwl_1138_configbus1; -wire [1138:1138] sram_blwl_1138_configbus0_b; -assign sram_blwl_1138_configbus0[1138:1138] = sram_blwl_bl[1138:1138] ; -assign sram_blwl_1138_configbus1[1138:1138] = sram_blwl_wl[1138:1138] ; -assign sram_blwl_1138_configbus0_b[1138:1138] = sram_blwl_blb[1138:1138] ; -sram6T_blwl sram_blwl_1138_ (sram_blwl_out[1138], sram_blwl_out[1138], sram_blwl_outb[1138], sram_blwl_1138_configbus0[1138:1138], sram_blwl_1138_configbus1[1138:1138] , sram_blwl_1138_configbus0_b[1138:1138] ); -wire [1139:1139] sram_blwl_1139_configbus0; -wire [1139:1139] sram_blwl_1139_configbus1; -wire [1139:1139] sram_blwl_1139_configbus0_b; -assign sram_blwl_1139_configbus0[1139:1139] = sram_blwl_bl[1139:1139] ; -assign sram_blwl_1139_configbus1[1139:1139] = sram_blwl_wl[1139:1139] ; -assign sram_blwl_1139_configbus0_b[1139:1139] = sram_blwl_blb[1139:1139] ; -sram6T_blwl sram_blwl_1139_ (sram_blwl_out[1139], sram_blwl_out[1139], sram_blwl_outb[1139], sram_blwl_1139_configbus0[1139:1139], sram_blwl_1139_configbus1[1139:1139] , sram_blwl_1139_configbus0_b[1139:1139] ); -wire [1140:1140] sram_blwl_1140_configbus0; -wire [1140:1140] sram_blwl_1140_configbus1; -wire [1140:1140] sram_blwl_1140_configbus0_b; -assign sram_blwl_1140_configbus0[1140:1140] = sram_blwl_bl[1140:1140] ; -assign sram_blwl_1140_configbus1[1140:1140] = sram_blwl_wl[1140:1140] ; -assign sram_blwl_1140_configbus0_b[1140:1140] = sram_blwl_blb[1140:1140] ; -sram6T_blwl sram_blwl_1140_ (sram_blwl_out[1140], sram_blwl_out[1140], sram_blwl_outb[1140], sram_blwl_1140_configbus0[1140:1140], sram_blwl_1140_configbus1[1140:1140] , sram_blwl_1140_configbus0_b[1140:1140] ); -wire [1141:1141] sram_blwl_1141_configbus0; -wire [1141:1141] sram_blwl_1141_configbus1; -wire [1141:1141] sram_blwl_1141_configbus0_b; -assign sram_blwl_1141_configbus0[1141:1141] = sram_blwl_bl[1141:1141] ; -assign sram_blwl_1141_configbus1[1141:1141] = sram_blwl_wl[1141:1141] ; -assign sram_blwl_1141_configbus0_b[1141:1141] = sram_blwl_blb[1141:1141] ; -sram6T_blwl sram_blwl_1141_ (sram_blwl_out[1141], sram_blwl_out[1141], sram_blwl_outb[1141], sram_blwl_1141_configbus0[1141:1141], sram_blwl_1141_configbus1[1141:1141] , sram_blwl_1141_configbus0_b[1141:1141] ); -wire [1142:1142] sram_blwl_1142_configbus0; -wire [1142:1142] sram_blwl_1142_configbus1; -wire [1142:1142] sram_blwl_1142_configbus0_b; -assign sram_blwl_1142_configbus0[1142:1142] = sram_blwl_bl[1142:1142] ; -assign sram_blwl_1142_configbus1[1142:1142] = sram_blwl_wl[1142:1142] ; -assign sram_blwl_1142_configbus0_b[1142:1142] = sram_blwl_blb[1142:1142] ; -sram6T_blwl sram_blwl_1142_ (sram_blwl_out[1142], sram_blwl_out[1142], sram_blwl_outb[1142], sram_blwl_1142_configbus0[1142:1142], sram_blwl_1142_configbus1[1142:1142] , sram_blwl_1142_configbus0_b[1142:1142] ); -wire [1143:1143] sram_blwl_1143_configbus0; -wire [1143:1143] sram_blwl_1143_configbus1; -wire [1143:1143] sram_blwl_1143_configbus0_b; -assign sram_blwl_1143_configbus0[1143:1143] = sram_blwl_bl[1143:1143] ; -assign sram_blwl_1143_configbus1[1143:1143] = sram_blwl_wl[1143:1143] ; -assign sram_blwl_1143_configbus0_b[1143:1143] = sram_blwl_blb[1143:1143] ; -sram6T_blwl sram_blwl_1143_ (sram_blwl_out[1143], sram_blwl_out[1143], sram_blwl_outb[1143], sram_blwl_1143_configbus0[1143:1143], sram_blwl_1143_configbus1[1143:1143] , sram_blwl_1143_configbus0_b[1143:1143] ); -wire [1144:1144] sram_blwl_1144_configbus0; -wire [1144:1144] sram_blwl_1144_configbus1; -wire [1144:1144] sram_blwl_1144_configbus0_b; -assign sram_blwl_1144_configbus0[1144:1144] = sram_blwl_bl[1144:1144] ; -assign sram_blwl_1144_configbus1[1144:1144] = sram_blwl_wl[1144:1144] ; -assign sram_blwl_1144_configbus0_b[1144:1144] = sram_blwl_blb[1144:1144] ; -sram6T_blwl sram_blwl_1144_ (sram_blwl_out[1144], sram_blwl_out[1144], sram_blwl_outb[1144], sram_blwl_1144_configbus0[1144:1144], sram_blwl_1144_configbus1[1144:1144] , sram_blwl_1144_configbus0_b[1144:1144] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- - -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_1_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6_ ----- -module grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble6___in_0_, -input wire mode_ble6___in_1_, -input wire mode_ble6___in_2_, -input wire mode_ble6___in_3_, -input wire mode_ble6___in_4_, -input wire mode_ble6___in_5_, -output wire mode_ble6___out_0_, -input wire mode_ble6___clk_0_, -input [1081:1145] sram_blwl_bl , -input [1081:1145] sram_blwl_wl , -input [1081:1145] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ lut6_0_ ( - lut6_0___in_0_, lut6_0___in_1_, lut6_0___in_2_, lut6_0___in_3_, lut6_0___in_4_, lut6_0___in_5_, lut6_0___out_0_, -sram_blwl_bl[1081:1144] , -sram_blwl_wl[1081:1144] , -sram_blwl_blb[1081:1144] ); -grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_401_ ; -assign in_bus_mux_1level_tapbuf_size2_401_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_401_[1] = lut6_0___out_0_ ; -wire [1145:1145] mux_1level_tapbuf_size2_401_configbus0; -wire [1145:1145] mux_1level_tapbuf_size2_401_configbus1; -wire [1145:1145] mux_1level_tapbuf_size2_401_sram_blwl_out ; -wire [1145:1145] mux_1level_tapbuf_size2_401_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_401_configbus0[1145:1145] = sram_blwl_bl[1145:1145] ; -assign mux_1level_tapbuf_size2_401_configbus1[1145:1145] = sram_blwl_wl[1145:1145] ; -wire [1145:1145] mux_1level_tapbuf_size2_401_configbus0_b; -assign mux_1level_tapbuf_size2_401_configbus0_b[1145:1145] = sram_blwl_blb[1145:1145] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_401_ (in_bus_mux_1level_tapbuf_size2_401_, mode_ble6___out_0_, mux_1level_tapbuf_size2_401_sram_blwl_out[1145:1145] , -mux_1level_tapbuf_size2_401_sram_blwl_outb[1145:1145] ); -//----- SRAM bits for MUX[401], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1145_ (mux_1level_tapbuf_size2_401_sram_blwl_out[1145:1145] ,mux_1level_tapbuf_size2_401_sram_blwl_out[1145:1145] ,mux_1level_tapbuf_size2_401_sram_blwl_outb[1145:1145] ,mux_1level_tapbuf_size2_401_configbus0[1145:1145], mux_1level_tapbuf_size2_401_configbus1[1145:1145] , mux_1level_tapbuf_size2_401_configbus0_b[1145:1145] ); -direct_interc direct_interc_16_ (mode_ble6___in_0_, lut6_0___in_0_ ); -direct_interc direct_interc_17_ (mode_ble6___in_1_, lut6_0___in_1_ ); -direct_interc direct_interc_18_ (mode_ble6___in_2_, lut6_0___in_2_ ); -direct_interc direct_interc_19_ (mode_ble6___in_3_, lut6_0___in_3_ ); -direct_interc direct_interc_20_ (mode_ble6___in_4_, lut6_0___in_4_ ); -direct_interc direct_interc_21_ (mode_ble6___in_5_, lut6_0___in_5_ ); -direct_interc direct_interc_22_ (lut6_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_23_ (mode_ble6___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6_ ----- -module grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut6___in_0_, -input wire mode_n1_lut6___in_1_, -input wire mode_n1_lut6___in_2_, -input wire mode_n1_lut6___in_3_, -input wire mode_n1_lut6___in_4_, -input wire mode_n1_lut6___in_5_, -output wire mode_n1_lut6___out_0_, -input wire mode_n1_lut6___clk_0_, -input [1081:1145] sram_blwl_bl , -input [1081:1145] sram_blwl_wl , -input [1081:1145] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6__ble6_0__mode_ble6_ ble6_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble6_0___in_0_, ble6_0___in_1_, ble6_0___in_2_, ble6_0___in_3_, ble6_0___in_4_, ble6_0___in_5_, ble6_0___out_0_, ble6_0___clk_0_, -sram_blwl_bl[1081:1145] , -sram_blwl_wl[1081:1145] , -sram_blwl_blb[1081:1145] ); -direct_interc direct_interc_24_ (ble6_0___out_0_, mode_n1_lut6___out_0_ ); -direct_interc direct_interc_25_ (mode_n1_lut6___in_0_, ble6_0___in_0_ ); -direct_interc direct_interc_26_ (mode_n1_lut6___in_1_, ble6_0___in_1_ ); -direct_interc direct_interc_27_ (mode_n1_lut6___in_2_, ble6_0___in_2_ ); -direct_interc direct_interc_28_ (mode_n1_lut6___in_3_, ble6_0___in_3_ ); -direct_interc direct_interc_29_ (mode_n1_lut6___in_4_, ble6_0___in_4_ ); -direct_interc direct_interc_30_ (mode_n1_lut6___in_5_, ble6_0___in_5_ ); -direct_interc direct_interc_31_ (mode_n1_lut6___clk_0_, ble6_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6_ ----- - -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ( -input wire lut6_0___in_0_, -input wire lut6_0___in_1_, -input wire lut6_0___in_2_, -input wire lut6_0___in_3_, -input wire lut6_0___in_4_, -input wire lut6_0___in_5_, -output wire lut6_0___out_0_, -input [1146:1209] sram_blwl_bl , -input [1146:1209] sram_blwl_wl , -input [1146:1209] sram_blwl_blb ); -wire [0:5] lut6_0___in; -assign lut6_0___in[0] = lut6_0___in_0_; -assign lut6_0___in[1] = lut6_0___in_1_; -assign lut6_0___in[2] = lut6_0___in_2_; -assign lut6_0___in[3] = lut6_0___in_3_; -assign lut6_0___in[4] = lut6_0___in_4_; -assign lut6_0___in[5] = lut6_0___in_5_; -wire [0:0] lut6_0___out; -assign lut6_0___out_0_ = lut6_0___out[0]; -wire [1146:1209] sram_blwl_out ; -wire [1146:1209] sram_blwl_outb ; -lut6 lut6_2_ ( -//----- Input and output ports ----- - lut6_0___in[0:5] , lut6_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[1146:1209] , sram_blwl_outb[1146:1209] ); -//----- Truth Table for LUT[2], size=6. ----- -//----- SRAM bits for LUT[2], size=6, num_sram=64. ----- -//-----0000000000000000000000000000000000000000000000000000000000000000----- -wire [1146:1146] sram_blwl_1146_configbus0; -wire [1146:1146] sram_blwl_1146_configbus1; -wire [1146:1146] sram_blwl_1146_configbus0_b; -assign sram_blwl_1146_configbus0[1146:1146] = sram_blwl_bl[1146:1146] ; -assign sram_blwl_1146_configbus1[1146:1146] = sram_blwl_wl[1146:1146] ; -assign sram_blwl_1146_configbus0_b[1146:1146] = sram_blwl_blb[1146:1146] ; -sram6T_blwl sram_blwl_1146_ (sram_blwl_out[1146], sram_blwl_out[1146], sram_blwl_outb[1146], sram_blwl_1146_configbus0[1146:1146], sram_blwl_1146_configbus1[1146:1146] , sram_blwl_1146_configbus0_b[1146:1146] ); -wire [1147:1147] sram_blwl_1147_configbus0; -wire [1147:1147] sram_blwl_1147_configbus1; -wire [1147:1147] sram_blwl_1147_configbus0_b; -assign sram_blwl_1147_configbus0[1147:1147] = sram_blwl_bl[1147:1147] ; -assign sram_blwl_1147_configbus1[1147:1147] = sram_blwl_wl[1147:1147] ; -assign sram_blwl_1147_configbus0_b[1147:1147] = sram_blwl_blb[1147:1147] ; -sram6T_blwl sram_blwl_1147_ (sram_blwl_out[1147], sram_blwl_out[1147], sram_blwl_outb[1147], sram_blwl_1147_configbus0[1147:1147], sram_blwl_1147_configbus1[1147:1147] , sram_blwl_1147_configbus0_b[1147:1147] ); -wire [1148:1148] sram_blwl_1148_configbus0; -wire [1148:1148] sram_blwl_1148_configbus1; -wire [1148:1148] sram_blwl_1148_configbus0_b; -assign sram_blwl_1148_configbus0[1148:1148] = sram_blwl_bl[1148:1148] ; -assign sram_blwl_1148_configbus1[1148:1148] = sram_blwl_wl[1148:1148] ; -assign sram_blwl_1148_configbus0_b[1148:1148] = sram_blwl_blb[1148:1148] ; -sram6T_blwl sram_blwl_1148_ (sram_blwl_out[1148], sram_blwl_out[1148], sram_blwl_outb[1148], sram_blwl_1148_configbus0[1148:1148], sram_blwl_1148_configbus1[1148:1148] , sram_blwl_1148_configbus0_b[1148:1148] ); -wire [1149:1149] sram_blwl_1149_configbus0; -wire [1149:1149] sram_blwl_1149_configbus1; -wire [1149:1149] sram_blwl_1149_configbus0_b; -assign sram_blwl_1149_configbus0[1149:1149] = sram_blwl_bl[1149:1149] ; -assign sram_blwl_1149_configbus1[1149:1149] = sram_blwl_wl[1149:1149] ; -assign sram_blwl_1149_configbus0_b[1149:1149] = sram_blwl_blb[1149:1149] ; -sram6T_blwl sram_blwl_1149_ (sram_blwl_out[1149], sram_blwl_out[1149], sram_blwl_outb[1149], sram_blwl_1149_configbus0[1149:1149], sram_blwl_1149_configbus1[1149:1149] , sram_blwl_1149_configbus0_b[1149:1149] ); -wire [1150:1150] sram_blwl_1150_configbus0; -wire [1150:1150] sram_blwl_1150_configbus1; -wire [1150:1150] sram_blwl_1150_configbus0_b; -assign sram_blwl_1150_configbus0[1150:1150] = sram_blwl_bl[1150:1150] ; -assign sram_blwl_1150_configbus1[1150:1150] = sram_blwl_wl[1150:1150] ; -assign sram_blwl_1150_configbus0_b[1150:1150] = sram_blwl_blb[1150:1150] ; -sram6T_blwl sram_blwl_1150_ (sram_blwl_out[1150], sram_blwl_out[1150], sram_blwl_outb[1150], sram_blwl_1150_configbus0[1150:1150], sram_blwl_1150_configbus1[1150:1150] , sram_blwl_1150_configbus0_b[1150:1150] ); -wire [1151:1151] sram_blwl_1151_configbus0; -wire [1151:1151] sram_blwl_1151_configbus1; -wire [1151:1151] sram_blwl_1151_configbus0_b; -assign sram_blwl_1151_configbus0[1151:1151] = sram_blwl_bl[1151:1151] ; -assign sram_blwl_1151_configbus1[1151:1151] = sram_blwl_wl[1151:1151] ; -assign sram_blwl_1151_configbus0_b[1151:1151] = sram_blwl_blb[1151:1151] ; -sram6T_blwl sram_blwl_1151_ (sram_blwl_out[1151], sram_blwl_out[1151], sram_blwl_outb[1151], sram_blwl_1151_configbus0[1151:1151], sram_blwl_1151_configbus1[1151:1151] , sram_blwl_1151_configbus0_b[1151:1151] ); -wire [1152:1152] sram_blwl_1152_configbus0; -wire [1152:1152] sram_blwl_1152_configbus1; -wire [1152:1152] sram_blwl_1152_configbus0_b; -assign sram_blwl_1152_configbus0[1152:1152] = sram_blwl_bl[1152:1152] ; -assign sram_blwl_1152_configbus1[1152:1152] = sram_blwl_wl[1152:1152] ; -assign sram_blwl_1152_configbus0_b[1152:1152] = sram_blwl_blb[1152:1152] ; -sram6T_blwl sram_blwl_1152_ (sram_blwl_out[1152], sram_blwl_out[1152], sram_blwl_outb[1152], sram_blwl_1152_configbus0[1152:1152], sram_blwl_1152_configbus1[1152:1152] , sram_blwl_1152_configbus0_b[1152:1152] ); -wire [1153:1153] sram_blwl_1153_configbus0; -wire [1153:1153] sram_blwl_1153_configbus1; -wire [1153:1153] sram_blwl_1153_configbus0_b; -assign sram_blwl_1153_configbus0[1153:1153] = sram_blwl_bl[1153:1153] ; -assign sram_blwl_1153_configbus1[1153:1153] = sram_blwl_wl[1153:1153] ; -assign sram_blwl_1153_configbus0_b[1153:1153] = sram_blwl_blb[1153:1153] ; -sram6T_blwl sram_blwl_1153_ (sram_blwl_out[1153], sram_blwl_out[1153], sram_blwl_outb[1153], sram_blwl_1153_configbus0[1153:1153], sram_blwl_1153_configbus1[1153:1153] , sram_blwl_1153_configbus0_b[1153:1153] ); -wire [1154:1154] sram_blwl_1154_configbus0; -wire [1154:1154] sram_blwl_1154_configbus1; -wire [1154:1154] sram_blwl_1154_configbus0_b; -assign sram_blwl_1154_configbus0[1154:1154] = sram_blwl_bl[1154:1154] ; -assign sram_blwl_1154_configbus1[1154:1154] = sram_blwl_wl[1154:1154] ; -assign sram_blwl_1154_configbus0_b[1154:1154] = sram_blwl_blb[1154:1154] ; -sram6T_blwl sram_blwl_1154_ (sram_blwl_out[1154], sram_blwl_out[1154], sram_blwl_outb[1154], sram_blwl_1154_configbus0[1154:1154], sram_blwl_1154_configbus1[1154:1154] , sram_blwl_1154_configbus0_b[1154:1154] ); -wire [1155:1155] sram_blwl_1155_configbus0; -wire [1155:1155] sram_blwl_1155_configbus1; -wire [1155:1155] sram_blwl_1155_configbus0_b; -assign sram_blwl_1155_configbus0[1155:1155] = sram_blwl_bl[1155:1155] ; -assign sram_blwl_1155_configbus1[1155:1155] = sram_blwl_wl[1155:1155] ; -assign sram_blwl_1155_configbus0_b[1155:1155] = sram_blwl_blb[1155:1155] ; -sram6T_blwl sram_blwl_1155_ (sram_blwl_out[1155], sram_blwl_out[1155], sram_blwl_outb[1155], sram_blwl_1155_configbus0[1155:1155], sram_blwl_1155_configbus1[1155:1155] , sram_blwl_1155_configbus0_b[1155:1155] ); -wire [1156:1156] sram_blwl_1156_configbus0; -wire [1156:1156] sram_blwl_1156_configbus1; -wire [1156:1156] sram_blwl_1156_configbus0_b; -assign sram_blwl_1156_configbus0[1156:1156] = sram_blwl_bl[1156:1156] ; -assign sram_blwl_1156_configbus1[1156:1156] = sram_blwl_wl[1156:1156] ; -assign sram_blwl_1156_configbus0_b[1156:1156] = sram_blwl_blb[1156:1156] ; -sram6T_blwl sram_blwl_1156_ (sram_blwl_out[1156], sram_blwl_out[1156], sram_blwl_outb[1156], sram_blwl_1156_configbus0[1156:1156], sram_blwl_1156_configbus1[1156:1156] , sram_blwl_1156_configbus0_b[1156:1156] ); -wire [1157:1157] sram_blwl_1157_configbus0; -wire [1157:1157] sram_blwl_1157_configbus1; -wire [1157:1157] sram_blwl_1157_configbus0_b; -assign sram_blwl_1157_configbus0[1157:1157] = sram_blwl_bl[1157:1157] ; -assign sram_blwl_1157_configbus1[1157:1157] = sram_blwl_wl[1157:1157] ; -assign sram_blwl_1157_configbus0_b[1157:1157] = sram_blwl_blb[1157:1157] ; -sram6T_blwl sram_blwl_1157_ (sram_blwl_out[1157], sram_blwl_out[1157], sram_blwl_outb[1157], sram_blwl_1157_configbus0[1157:1157], sram_blwl_1157_configbus1[1157:1157] , sram_blwl_1157_configbus0_b[1157:1157] ); -wire [1158:1158] sram_blwl_1158_configbus0; -wire [1158:1158] sram_blwl_1158_configbus1; -wire [1158:1158] sram_blwl_1158_configbus0_b; -assign sram_blwl_1158_configbus0[1158:1158] = sram_blwl_bl[1158:1158] ; -assign sram_blwl_1158_configbus1[1158:1158] = sram_blwl_wl[1158:1158] ; -assign sram_blwl_1158_configbus0_b[1158:1158] = sram_blwl_blb[1158:1158] ; -sram6T_blwl sram_blwl_1158_ (sram_blwl_out[1158], sram_blwl_out[1158], sram_blwl_outb[1158], sram_blwl_1158_configbus0[1158:1158], sram_blwl_1158_configbus1[1158:1158] , sram_blwl_1158_configbus0_b[1158:1158] ); -wire [1159:1159] sram_blwl_1159_configbus0; -wire [1159:1159] sram_blwl_1159_configbus1; -wire [1159:1159] sram_blwl_1159_configbus0_b; -assign sram_blwl_1159_configbus0[1159:1159] = sram_blwl_bl[1159:1159] ; -assign sram_blwl_1159_configbus1[1159:1159] = sram_blwl_wl[1159:1159] ; -assign sram_blwl_1159_configbus0_b[1159:1159] = sram_blwl_blb[1159:1159] ; -sram6T_blwl sram_blwl_1159_ (sram_blwl_out[1159], sram_blwl_out[1159], sram_blwl_outb[1159], sram_blwl_1159_configbus0[1159:1159], sram_blwl_1159_configbus1[1159:1159] , sram_blwl_1159_configbus0_b[1159:1159] ); -wire [1160:1160] sram_blwl_1160_configbus0; -wire [1160:1160] sram_blwl_1160_configbus1; -wire [1160:1160] sram_blwl_1160_configbus0_b; -assign sram_blwl_1160_configbus0[1160:1160] = sram_blwl_bl[1160:1160] ; -assign sram_blwl_1160_configbus1[1160:1160] = sram_blwl_wl[1160:1160] ; -assign sram_blwl_1160_configbus0_b[1160:1160] = sram_blwl_blb[1160:1160] ; -sram6T_blwl sram_blwl_1160_ (sram_blwl_out[1160], sram_blwl_out[1160], sram_blwl_outb[1160], sram_blwl_1160_configbus0[1160:1160], sram_blwl_1160_configbus1[1160:1160] , sram_blwl_1160_configbus0_b[1160:1160] ); -wire [1161:1161] sram_blwl_1161_configbus0; -wire [1161:1161] sram_blwl_1161_configbus1; -wire [1161:1161] sram_blwl_1161_configbus0_b; -assign sram_blwl_1161_configbus0[1161:1161] = sram_blwl_bl[1161:1161] ; -assign sram_blwl_1161_configbus1[1161:1161] = sram_blwl_wl[1161:1161] ; -assign sram_blwl_1161_configbus0_b[1161:1161] = sram_blwl_blb[1161:1161] ; -sram6T_blwl sram_blwl_1161_ (sram_blwl_out[1161], sram_blwl_out[1161], sram_blwl_outb[1161], sram_blwl_1161_configbus0[1161:1161], sram_blwl_1161_configbus1[1161:1161] , sram_blwl_1161_configbus0_b[1161:1161] ); -wire [1162:1162] sram_blwl_1162_configbus0; -wire [1162:1162] sram_blwl_1162_configbus1; -wire [1162:1162] sram_blwl_1162_configbus0_b; -assign sram_blwl_1162_configbus0[1162:1162] = sram_blwl_bl[1162:1162] ; -assign sram_blwl_1162_configbus1[1162:1162] = sram_blwl_wl[1162:1162] ; -assign sram_blwl_1162_configbus0_b[1162:1162] = sram_blwl_blb[1162:1162] ; -sram6T_blwl sram_blwl_1162_ (sram_blwl_out[1162], sram_blwl_out[1162], sram_blwl_outb[1162], sram_blwl_1162_configbus0[1162:1162], sram_blwl_1162_configbus1[1162:1162] , sram_blwl_1162_configbus0_b[1162:1162] ); -wire [1163:1163] sram_blwl_1163_configbus0; -wire [1163:1163] sram_blwl_1163_configbus1; -wire [1163:1163] sram_blwl_1163_configbus0_b; -assign sram_blwl_1163_configbus0[1163:1163] = sram_blwl_bl[1163:1163] ; -assign sram_blwl_1163_configbus1[1163:1163] = sram_blwl_wl[1163:1163] ; -assign sram_blwl_1163_configbus0_b[1163:1163] = sram_blwl_blb[1163:1163] ; -sram6T_blwl sram_blwl_1163_ (sram_blwl_out[1163], sram_blwl_out[1163], sram_blwl_outb[1163], sram_blwl_1163_configbus0[1163:1163], sram_blwl_1163_configbus1[1163:1163] , sram_blwl_1163_configbus0_b[1163:1163] ); -wire [1164:1164] sram_blwl_1164_configbus0; -wire [1164:1164] sram_blwl_1164_configbus1; -wire [1164:1164] sram_blwl_1164_configbus0_b; -assign sram_blwl_1164_configbus0[1164:1164] = sram_blwl_bl[1164:1164] ; -assign sram_blwl_1164_configbus1[1164:1164] = sram_blwl_wl[1164:1164] ; -assign sram_blwl_1164_configbus0_b[1164:1164] = sram_blwl_blb[1164:1164] ; -sram6T_blwl sram_blwl_1164_ (sram_blwl_out[1164], sram_blwl_out[1164], sram_blwl_outb[1164], sram_blwl_1164_configbus0[1164:1164], sram_blwl_1164_configbus1[1164:1164] , sram_blwl_1164_configbus0_b[1164:1164] ); -wire [1165:1165] sram_blwl_1165_configbus0; -wire [1165:1165] sram_blwl_1165_configbus1; -wire [1165:1165] sram_blwl_1165_configbus0_b; -assign sram_blwl_1165_configbus0[1165:1165] = sram_blwl_bl[1165:1165] ; -assign sram_blwl_1165_configbus1[1165:1165] = sram_blwl_wl[1165:1165] ; -assign sram_blwl_1165_configbus0_b[1165:1165] = sram_blwl_blb[1165:1165] ; -sram6T_blwl sram_blwl_1165_ (sram_blwl_out[1165], sram_blwl_out[1165], sram_blwl_outb[1165], sram_blwl_1165_configbus0[1165:1165], sram_blwl_1165_configbus1[1165:1165] , sram_blwl_1165_configbus0_b[1165:1165] ); -wire [1166:1166] sram_blwl_1166_configbus0; -wire [1166:1166] sram_blwl_1166_configbus1; -wire [1166:1166] sram_blwl_1166_configbus0_b; -assign sram_blwl_1166_configbus0[1166:1166] = sram_blwl_bl[1166:1166] ; -assign sram_blwl_1166_configbus1[1166:1166] = sram_blwl_wl[1166:1166] ; -assign sram_blwl_1166_configbus0_b[1166:1166] = sram_blwl_blb[1166:1166] ; -sram6T_blwl sram_blwl_1166_ (sram_blwl_out[1166], sram_blwl_out[1166], sram_blwl_outb[1166], sram_blwl_1166_configbus0[1166:1166], sram_blwl_1166_configbus1[1166:1166] , sram_blwl_1166_configbus0_b[1166:1166] ); -wire [1167:1167] sram_blwl_1167_configbus0; -wire [1167:1167] sram_blwl_1167_configbus1; -wire [1167:1167] sram_blwl_1167_configbus0_b; -assign sram_blwl_1167_configbus0[1167:1167] = sram_blwl_bl[1167:1167] ; -assign sram_blwl_1167_configbus1[1167:1167] = sram_blwl_wl[1167:1167] ; -assign sram_blwl_1167_configbus0_b[1167:1167] = sram_blwl_blb[1167:1167] ; -sram6T_blwl sram_blwl_1167_ (sram_blwl_out[1167], sram_blwl_out[1167], sram_blwl_outb[1167], sram_blwl_1167_configbus0[1167:1167], sram_blwl_1167_configbus1[1167:1167] , sram_blwl_1167_configbus0_b[1167:1167] ); -wire [1168:1168] sram_blwl_1168_configbus0; -wire [1168:1168] sram_blwl_1168_configbus1; -wire [1168:1168] sram_blwl_1168_configbus0_b; -assign sram_blwl_1168_configbus0[1168:1168] = sram_blwl_bl[1168:1168] ; -assign sram_blwl_1168_configbus1[1168:1168] = sram_blwl_wl[1168:1168] ; -assign sram_blwl_1168_configbus0_b[1168:1168] = sram_blwl_blb[1168:1168] ; -sram6T_blwl sram_blwl_1168_ (sram_blwl_out[1168], sram_blwl_out[1168], sram_blwl_outb[1168], sram_blwl_1168_configbus0[1168:1168], sram_blwl_1168_configbus1[1168:1168] , sram_blwl_1168_configbus0_b[1168:1168] ); -wire [1169:1169] sram_blwl_1169_configbus0; -wire [1169:1169] sram_blwl_1169_configbus1; -wire [1169:1169] sram_blwl_1169_configbus0_b; -assign sram_blwl_1169_configbus0[1169:1169] = sram_blwl_bl[1169:1169] ; -assign sram_blwl_1169_configbus1[1169:1169] = sram_blwl_wl[1169:1169] ; -assign sram_blwl_1169_configbus0_b[1169:1169] = sram_blwl_blb[1169:1169] ; -sram6T_blwl sram_blwl_1169_ (sram_blwl_out[1169], sram_blwl_out[1169], sram_blwl_outb[1169], sram_blwl_1169_configbus0[1169:1169], sram_blwl_1169_configbus1[1169:1169] , sram_blwl_1169_configbus0_b[1169:1169] ); -wire [1170:1170] sram_blwl_1170_configbus0; -wire [1170:1170] sram_blwl_1170_configbus1; -wire [1170:1170] sram_blwl_1170_configbus0_b; -assign sram_blwl_1170_configbus0[1170:1170] = sram_blwl_bl[1170:1170] ; -assign sram_blwl_1170_configbus1[1170:1170] = sram_blwl_wl[1170:1170] ; -assign sram_blwl_1170_configbus0_b[1170:1170] = sram_blwl_blb[1170:1170] ; -sram6T_blwl sram_blwl_1170_ (sram_blwl_out[1170], sram_blwl_out[1170], sram_blwl_outb[1170], sram_blwl_1170_configbus0[1170:1170], sram_blwl_1170_configbus1[1170:1170] , sram_blwl_1170_configbus0_b[1170:1170] ); -wire [1171:1171] sram_blwl_1171_configbus0; -wire [1171:1171] sram_blwl_1171_configbus1; -wire [1171:1171] sram_blwl_1171_configbus0_b; -assign sram_blwl_1171_configbus0[1171:1171] = sram_blwl_bl[1171:1171] ; -assign sram_blwl_1171_configbus1[1171:1171] = sram_blwl_wl[1171:1171] ; -assign sram_blwl_1171_configbus0_b[1171:1171] = sram_blwl_blb[1171:1171] ; -sram6T_blwl sram_blwl_1171_ (sram_blwl_out[1171], sram_blwl_out[1171], sram_blwl_outb[1171], sram_blwl_1171_configbus0[1171:1171], sram_blwl_1171_configbus1[1171:1171] , sram_blwl_1171_configbus0_b[1171:1171] ); -wire [1172:1172] sram_blwl_1172_configbus0; -wire [1172:1172] sram_blwl_1172_configbus1; -wire [1172:1172] sram_blwl_1172_configbus0_b; -assign sram_blwl_1172_configbus0[1172:1172] = sram_blwl_bl[1172:1172] ; -assign sram_blwl_1172_configbus1[1172:1172] = sram_blwl_wl[1172:1172] ; -assign sram_blwl_1172_configbus0_b[1172:1172] = sram_blwl_blb[1172:1172] ; -sram6T_blwl sram_blwl_1172_ (sram_blwl_out[1172], sram_blwl_out[1172], sram_blwl_outb[1172], sram_blwl_1172_configbus0[1172:1172], sram_blwl_1172_configbus1[1172:1172] , sram_blwl_1172_configbus0_b[1172:1172] ); -wire [1173:1173] sram_blwl_1173_configbus0; -wire [1173:1173] sram_blwl_1173_configbus1; -wire [1173:1173] sram_blwl_1173_configbus0_b; -assign sram_blwl_1173_configbus0[1173:1173] = sram_blwl_bl[1173:1173] ; -assign sram_blwl_1173_configbus1[1173:1173] = sram_blwl_wl[1173:1173] ; -assign sram_blwl_1173_configbus0_b[1173:1173] = sram_blwl_blb[1173:1173] ; -sram6T_blwl sram_blwl_1173_ (sram_blwl_out[1173], sram_blwl_out[1173], sram_blwl_outb[1173], sram_blwl_1173_configbus0[1173:1173], sram_blwl_1173_configbus1[1173:1173] , sram_blwl_1173_configbus0_b[1173:1173] ); -wire [1174:1174] sram_blwl_1174_configbus0; -wire [1174:1174] sram_blwl_1174_configbus1; -wire [1174:1174] sram_blwl_1174_configbus0_b; -assign sram_blwl_1174_configbus0[1174:1174] = sram_blwl_bl[1174:1174] ; -assign sram_blwl_1174_configbus1[1174:1174] = sram_blwl_wl[1174:1174] ; -assign sram_blwl_1174_configbus0_b[1174:1174] = sram_blwl_blb[1174:1174] ; -sram6T_blwl sram_blwl_1174_ (sram_blwl_out[1174], sram_blwl_out[1174], sram_blwl_outb[1174], sram_blwl_1174_configbus0[1174:1174], sram_blwl_1174_configbus1[1174:1174] , sram_blwl_1174_configbus0_b[1174:1174] ); -wire [1175:1175] sram_blwl_1175_configbus0; -wire [1175:1175] sram_blwl_1175_configbus1; -wire [1175:1175] sram_blwl_1175_configbus0_b; -assign sram_blwl_1175_configbus0[1175:1175] = sram_blwl_bl[1175:1175] ; -assign sram_blwl_1175_configbus1[1175:1175] = sram_blwl_wl[1175:1175] ; -assign sram_blwl_1175_configbus0_b[1175:1175] = sram_blwl_blb[1175:1175] ; -sram6T_blwl sram_blwl_1175_ (sram_blwl_out[1175], sram_blwl_out[1175], sram_blwl_outb[1175], sram_blwl_1175_configbus0[1175:1175], sram_blwl_1175_configbus1[1175:1175] , sram_blwl_1175_configbus0_b[1175:1175] ); -wire [1176:1176] sram_blwl_1176_configbus0; -wire [1176:1176] sram_blwl_1176_configbus1; -wire [1176:1176] sram_blwl_1176_configbus0_b; -assign sram_blwl_1176_configbus0[1176:1176] = sram_blwl_bl[1176:1176] ; -assign sram_blwl_1176_configbus1[1176:1176] = sram_blwl_wl[1176:1176] ; -assign sram_blwl_1176_configbus0_b[1176:1176] = sram_blwl_blb[1176:1176] ; -sram6T_blwl sram_blwl_1176_ (sram_blwl_out[1176], sram_blwl_out[1176], sram_blwl_outb[1176], sram_blwl_1176_configbus0[1176:1176], sram_blwl_1176_configbus1[1176:1176] , sram_blwl_1176_configbus0_b[1176:1176] ); -wire [1177:1177] sram_blwl_1177_configbus0; -wire [1177:1177] sram_blwl_1177_configbus1; -wire [1177:1177] sram_blwl_1177_configbus0_b; -assign sram_blwl_1177_configbus0[1177:1177] = sram_blwl_bl[1177:1177] ; -assign sram_blwl_1177_configbus1[1177:1177] = sram_blwl_wl[1177:1177] ; -assign sram_blwl_1177_configbus0_b[1177:1177] = sram_blwl_blb[1177:1177] ; -sram6T_blwl sram_blwl_1177_ (sram_blwl_out[1177], sram_blwl_out[1177], sram_blwl_outb[1177], sram_blwl_1177_configbus0[1177:1177], sram_blwl_1177_configbus1[1177:1177] , sram_blwl_1177_configbus0_b[1177:1177] ); -wire [1178:1178] sram_blwl_1178_configbus0; -wire [1178:1178] sram_blwl_1178_configbus1; -wire [1178:1178] sram_blwl_1178_configbus0_b; -assign sram_blwl_1178_configbus0[1178:1178] = sram_blwl_bl[1178:1178] ; -assign sram_blwl_1178_configbus1[1178:1178] = sram_blwl_wl[1178:1178] ; -assign sram_blwl_1178_configbus0_b[1178:1178] = sram_blwl_blb[1178:1178] ; -sram6T_blwl sram_blwl_1178_ (sram_blwl_out[1178], sram_blwl_out[1178], sram_blwl_outb[1178], sram_blwl_1178_configbus0[1178:1178], sram_blwl_1178_configbus1[1178:1178] , sram_blwl_1178_configbus0_b[1178:1178] ); -wire [1179:1179] sram_blwl_1179_configbus0; -wire [1179:1179] sram_blwl_1179_configbus1; -wire [1179:1179] sram_blwl_1179_configbus0_b; -assign sram_blwl_1179_configbus0[1179:1179] = sram_blwl_bl[1179:1179] ; -assign sram_blwl_1179_configbus1[1179:1179] = sram_blwl_wl[1179:1179] ; -assign sram_blwl_1179_configbus0_b[1179:1179] = sram_blwl_blb[1179:1179] ; -sram6T_blwl sram_blwl_1179_ (sram_blwl_out[1179], sram_blwl_out[1179], sram_blwl_outb[1179], sram_blwl_1179_configbus0[1179:1179], sram_blwl_1179_configbus1[1179:1179] , sram_blwl_1179_configbus0_b[1179:1179] ); -wire [1180:1180] sram_blwl_1180_configbus0; -wire [1180:1180] sram_blwl_1180_configbus1; -wire [1180:1180] sram_blwl_1180_configbus0_b; -assign sram_blwl_1180_configbus0[1180:1180] = sram_blwl_bl[1180:1180] ; -assign sram_blwl_1180_configbus1[1180:1180] = sram_blwl_wl[1180:1180] ; -assign sram_blwl_1180_configbus0_b[1180:1180] = sram_blwl_blb[1180:1180] ; -sram6T_blwl sram_blwl_1180_ (sram_blwl_out[1180], sram_blwl_out[1180], sram_blwl_outb[1180], sram_blwl_1180_configbus0[1180:1180], sram_blwl_1180_configbus1[1180:1180] , sram_blwl_1180_configbus0_b[1180:1180] ); -wire [1181:1181] sram_blwl_1181_configbus0; -wire [1181:1181] sram_blwl_1181_configbus1; -wire [1181:1181] sram_blwl_1181_configbus0_b; -assign sram_blwl_1181_configbus0[1181:1181] = sram_blwl_bl[1181:1181] ; -assign sram_blwl_1181_configbus1[1181:1181] = sram_blwl_wl[1181:1181] ; -assign sram_blwl_1181_configbus0_b[1181:1181] = sram_blwl_blb[1181:1181] ; -sram6T_blwl sram_blwl_1181_ (sram_blwl_out[1181], sram_blwl_out[1181], sram_blwl_outb[1181], sram_blwl_1181_configbus0[1181:1181], sram_blwl_1181_configbus1[1181:1181] , sram_blwl_1181_configbus0_b[1181:1181] ); -wire [1182:1182] sram_blwl_1182_configbus0; -wire [1182:1182] sram_blwl_1182_configbus1; -wire [1182:1182] sram_blwl_1182_configbus0_b; -assign sram_blwl_1182_configbus0[1182:1182] = sram_blwl_bl[1182:1182] ; -assign sram_blwl_1182_configbus1[1182:1182] = sram_blwl_wl[1182:1182] ; -assign sram_blwl_1182_configbus0_b[1182:1182] = sram_blwl_blb[1182:1182] ; -sram6T_blwl sram_blwl_1182_ (sram_blwl_out[1182], sram_blwl_out[1182], sram_blwl_outb[1182], sram_blwl_1182_configbus0[1182:1182], sram_blwl_1182_configbus1[1182:1182] , sram_blwl_1182_configbus0_b[1182:1182] ); -wire [1183:1183] sram_blwl_1183_configbus0; -wire [1183:1183] sram_blwl_1183_configbus1; -wire [1183:1183] sram_blwl_1183_configbus0_b; -assign sram_blwl_1183_configbus0[1183:1183] = sram_blwl_bl[1183:1183] ; -assign sram_blwl_1183_configbus1[1183:1183] = sram_blwl_wl[1183:1183] ; -assign sram_blwl_1183_configbus0_b[1183:1183] = sram_blwl_blb[1183:1183] ; -sram6T_blwl sram_blwl_1183_ (sram_blwl_out[1183], sram_blwl_out[1183], sram_blwl_outb[1183], sram_blwl_1183_configbus0[1183:1183], sram_blwl_1183_configbus1[1183:1183] , sram_blwl_1183_configbus0_b[1183:1183] ); -wire [1184:1184] sram_blwl_1184_configbus0; -wire [1184:1184] sram_blwl_1184_configbus1; -wire [1184:1184] sram_blwl_1184_configbus0_b; -assign sram_blwl_1184_configbus0[1184:1184] = sram_blwl_bl[1184:1184] ; -assign sram_blwl_1184_configbus1[1184:1184] = sram_blwl_wl[1184:1184] ; -assign sram_blwl_1184_configbus0_b[1184:1184] = sram_blwl_blb[1184:1184] ; -sram6T_blwl sram_blwl_1184_ (sram_blwl_out[1184], sram_blwl_out[1184], sram_blwl_outb[1184], sram_blwl_1184_configbus0[1184:1184], sram_blwl_1184_configbus1[1184:1184] , sram_blwl_1184_configbus0_b[1184:1184] ); -wire [1185:1185] sram_blwl_1185_configbus0; -wire [1185:1185] sram_blwl_1185_configbus1; -wire [1185:1185] sram_blwl_1185_configbus0_b; -assign sram_blwl_1185_configbus0[1185:1185] = sram_blwl_bl[1185:1185] ; -assign sram_blwl_1185_configbus1[1185:1185] = sram_blwl_wl[1185:1185] ; -assign sram_blwl_1185_configbus0_b[1185:1185] = sram_blwl_blb[1185:1185] ; -sram6T_blwl sram_blwl_1185_ (sram_blwl_out[1185], sram_blwl_out[1185], sram_blwl_outb[1185], sram_blwl_1185_configbus0[1185:1185], sram_blwl_1185_configbus1[1185:1185] , sram_blwl_1185_configbus0_b[1185:1185] ); -wire [1186:1186] sram_blwl_1186_configbus0; -wire [1186:1186] sram_blwl_1186_configbus1; -wire [1186:1186] sram_blwl_1186_configbus0_b; -assign sram_blwl_1186_configbus0[1186:1186] = sram_blwl_bl[1186:1186] ; -assign sram_blwl_1186_configbus1[1186:1186] = sram_blwl_wl[1186:1186] ; -assign sram_blwl_1186_configbus0_b[1186:1186] = sram_blwl_blb[1186:1186] ; -sram6T_blwl sram_blwl_1186_ (sram_blwl_out[1186], sram_blwl_out[1186], sram_blwl_outb[1186], sram_blwl_1186_configbus0[1186:1186], sram_blwl_1186_configbus1[1186:1186] , sram_blwl_1186_configbus0_b[1186:1186] ); -wire [1187:1187] sram_blwl_1187_configbus0; -wire [1187:1187] sram_blwl_1187_configbus1; -wire [1187:1187] sram_blwl_1187_configbus0_b; -assign sram_blwl_1187_configbus0[1187:1187] = sram_blwl_bl[1187:1187] ; -assign sram_blwl_1187_configbus1[1187:1187] = sram_blwl_wl[1187:1187] ; -assign sram_blwl_1187_configbus0_b[1187:1187] = sram_blwl_blb[1187:1187] ; -sram6T_blwl sram_blwl_1187_ (sram_blwl_out[1187], sram_blwl_out[1187], sram_blwl_outb[1187], sram_blwl_1187_configbus0[1187:1187], sram_blwl_1187_configbus1[1187:1187] , sram_blwl_1187_configbus0_b[1187:1187] ); -wire [1188:1188] sram_blwl_1188_configbus0; -wire [1188:1188] sram_blwl_1188_configbus1; -wire [1188:1188] sram_blwl_1188_configbus0_b; -assign sram_blwl_1188_configbus0[1188:1188] = sram_blwl_bl[1188:1188] ; -assign sram_blwl_1188_configbus1[1188:1188] = sram_blwl_wl[1188:1188] ; -assign sram_blwl_1188_configbus0_b[1188:1188] = sram_blwl_blb[1188:1188] ; -sram6T_blwl sram_blwl_1188_ (sram_blwl_out[1188], sram_blwl_out[1188], sram_blwl_outb[1188], sram_blwl_1188_configbus0[1188:1188], sram_blwl_1188_configbus1[1188:1188] , sram_blwl_1188_configbus0_b[1188:1188] ); -wire [1189:1189] sram_blwl_1189_configbus0; -wire [1189:1189] sram_blwl_1189_configbus1; -wire [1189:1189] sram_blwl_1189_configbus0_b; -assign sram_blwl_1189_configbus0[1189:1189] = sram_blwl_bl[1189:1189] ; -assign sram_blwl_1189_configbus1[1189:1189] = sram_blwl_wl[1189:1189] ; -assign sram_blwl_1189_configbus0_b[1189:1189] = sram_blwl_blb[1189:1189] ; -sram6T_blwl sram_blwl_1189_ (sram_blwl_out[1189], sram_blwl_out[1189], sram_blwl_outb[1189], sram_blwl_1189_configbus0[1189:1189], sram_blwl_1189_configbus1[1189:1189] , sram_blwl_1189_configbus0_b[1189:1189] ); -wire [1190:1190] sram_blwl_1190_configbus0; -wire [1190:1190] sram_blwl_1190_configbus1; -wire [1190:1190] sram_blwl_1190_configbus0_b; -assign sram_blwl_1190_configbus0[1190:1190] = sram_blwl_bl[1190:1190] ; -assign sram_blwl_1190_configbus1[1190:1190] = sram_blwl_wl[1190:1190] ; -assign sram_blwl_1190_configbus0_b[1190:1190] = sram_blwl_blb[1190:1190] ; -sram6T_blwl sram_blwl_1190_ (sram_blwl_out[1190], sram_blwl_out[1190], sram_blwl_outb[1190], sram_blwl_1190_configbus0[1190:1190], sram_blwl_1190_configbus1[1190:1190] , sram_blwl_1190_configbus0_b[1190:1190] ); -wire [1191:1191] sram_blwl_1191_configbus0; -wire [1191:1191] sram_blwl_1191_configbus1; -wire [1191:1191] sram_blwl_1191_configbus0_b; -assign sram_blwl_1191_configbus0[1191:1191] = sram_blwl_bl[1191:1191] ; -assign sram_blwl_1191_configbus1[1191:1191] = sram_blwl_wl[1191:1191] ; -assign sram_blwl_1191_configbus0_b[1191:1191] = sram_blwl_blb[1191:1191] ; -sram6T_blwl sram_blwl_1191_ (sram_blwl_out[1191], sram_blwl_out[1191], sram_blwl_outb[1191], sram_blwl_1191_configbus0[1191:1191], sram_blwl_1191_configbus1[1191:1191] , sram_blwl_1191_configbus0_b[1191:1191] ); -wire [1192:1192] sram_blwl_1192_configbus0; -wire [1192:1192] sram_blwl_1192_configbus1; -wire [1192:1192] sram_blwl_1192_configbus0_b; -assign sram_blwl_1192_configbus0[1192:1192] = sram_blwl_bl[1192:1192] ; -assign sram_blwl_1192_configbus1[1192:1192] = sram_blwl_wl[1192:1192] ; -assign sram_blwl_1192_configbus0_b[1192:1192] = sram_blwl_blb[1192:1192] ; -sram6T_blwl sram_blwl_1192_ (sram_blwl_out[1192], sram_blwl_out[1192], sram_blwl_outb[1192], sram_blwl_1192_configbus0[1192:1192], sram_blwl_1192_configbus1[1192:1192] , sram_blwl_1192_configbus0_b[1192:1192] ); -wire [1193:1193] sram_blwl_1193_configbus0; -wire [1193:1193] sram_blwl_1193_configbus1; -wire [1193:1193] sram_blwl_1193_configbus0_b; -assign sram_blwl_1193_configbus0[1193:1193] = sram_blwl_bl[1193:1193] ; -assign sram_blwl_1193_configbus1[1193:1193] = sram_blwl_wl[1193:1193] ; -assign sram_blwl_1193_configbus0_b[1193:1193] = sram_blwl_blb[1193:1193] ; -sram6T_blwl sram_blwl_1193_ (sram_blwl_out[1193], sram_blwl_out[1193], sram_blwl_outb[1193], sram_blwl_1193_configbus0[1193:1193], sram_blwl_1193_configbus1[1193:1193] , sram_blwl_1193_configbus0_b[1193:1193] ); -wire [1194:1194] sram_blwl_1194_configbus0; -wire [1194:1194] sram_blwl_1194_configbus1; -wire [1194:1194] sram_blwl_1194_configbus0_b; -assign sram_blwl_1194_configbus0[1194:1194] = sram_blwl_bl[1194:1194] ; -assign sram_blwl_1194_configbus1[1194:1194] = sram_blwl_wl[1194:1194] ; -assign sram_blwl_1194_configbus0_b[1194:1194] = sram_blwl_blb[1194:1194] ; -sram6T_blwl sram_blwl_1194_ (sram_blwl_out[1194], sram_blwl_out[1194], sram_blwl_outb[1194], sram_blwl_1194_configbus0[1194:1194], sram_blwl_1194_configbus1[1194:1194] , sram_blwl_1194_configbus0_b[1194:1194] ); -wire [1195:1195] sram_blwl_1195_configbus0; -wire [1195:1195] sram_blwl_1195_configbus1; -wire [1195:1195] sram_blwl_1195_configbus0_b; -assign sram_blwl_1195_configbus0[1195:1195] = sram_blwl_bl[1195:1195] ; -assign sram_blwl_1195_configbus1[1195:1195] = sram_blwl_wl[1195:1195] ; -assign sram_blwl_1195_configbus0_b[1195:1195] = sram_blwl_blb[1195:1195] ; -sram6T_blwl sram_blwl_1195_ (sram_blwl_out[1195], sram_blwl_out[1195], sram_blwl_outb[1195], sram_blwl_1195_configbus0[1195:1195], sram_blwl_1195_configbus1[1195:1195] , sram_blwl_1195_configbus0_b[1195:1195] ); -wire [1196:1196] sram_blwl_1196_configbus0; -wire [1196:1196] sram_blwl_1196_configbus1; -wire [1196:1196] sram_blwl_1196_configbus0_b; -assign sram_blwl_1196_configbus0[1196:1196] = sram_blwl_bl[1196:1196] ; -assign sram_blwl_1196_configbus1[1196:1196] = sram_blwl_wl[1196:1196] ; -assign sram_blwl_1196_configbus0_b[1196:1196] = sram_blwl_blb[1196:1196] ; -sram6T_blwl sram_blwl_1196_ (sram_blwl_out[1196], sram_blwl_out[1196], sram_blwl_outb[1196], sram_blwl_1196_configbus0[1196:1196], sram_blwl_1196_configbus1[1196:1196] , sram_blwl_1196_configbus0_b[1196:1196] ); -wire [1197:1197] sram_blwl_1197_configbus0; -wire [1197:1197] sram_blwl_1197_configbus1; -wire [1197:1197] sram_blwl_1197_configbus0_b; -assign sram_blwl_1197_configbus0[1197:1197] = sram_blwl_bl[1197:1197] ; -assign sram_blwl_1197_configbus1[1197:1197] = sram_blwl_wl[1197:1197] ; -assign sram_blwl_1197_configbus0_b[1197:1197] = sram_blwl_blb[1197:1197] ; -sram6T_blwl sram_blwl_1197_ (sram_blwl_out[1197], sram_blwl_out[1197], sram_blwl_outb[1197], sram_blwl_1197_configbus0[1197:1197], sram_blwl_1197_configbus1[1197:1197] , sram_blwl_1197_configbus0_b[1197:1197] ); -wire [1198:1198] sram_blwl_1198_configbus0; -wire [1198:1198] sram_blwl_1198_configbus1; -wire [1198:1198] sram_blwl_1198_configbus0_b; -assign sram_blwl_1198_configbus0[1198:1198] = sram_blwl_bl[1198:1198] ; -assign sram_blwl_1198_configbus1[1198:1198] = sram_blwl_wl[1198:1198] ; -assign sram_blwl_1198_configbus0_b[1198:1198] = sram_blwl_blb[1198:1198] ; -sram6T_blwl sram_blwl_1198_ (sram_blwl_out[1198], sram_blwl_out[1198], sram_blwl_outb[1198], sram_blwl_1198_configbus0[1198:1198], sram_blwl_1198_configbus1[1198:1198] , sram_blwl_1198_configbus0_b[1198:1198] ); -wire [1199:1199] sram_blwl_1199_configbus0; -wire [1199:1199] sram_blwl_1199_configbus1; -wire [1199:1199] sram_blwl_1199_configbus0_b; -assign sram_blwl_1199_configbus0[1199:1199] = sram_blwl_bl[1199:1199] ; -assign sram_blwl_1199_configbus1[1199:1199] = sram_blwl_wl[1199:1199] ; -assign sram_blwl_1199_configbus0_b[1199:1199] = sram_blwl_blb[1199:1199] ; -sram6T_blwl sram_blwl_1199_ (sram_blwl_out[1199], sram_blwl_out[1199], sram_blwl_outb[1199], sram_blwl_1199_configbus0[1199:1199], sram_blwl_1199_configbus1[1199:1199] , sram_blwl_1199_configbus0_b[1199:1199] ); -wire [1200:1200] sram_blwl_1200_configbus0; -wire [1200:1200] sram_blwl_1200_configbus1; -wire [1200:1200] sram_blwl_1200_configbus0_b; -assign sram_blwl_1200_configbus0[1200:1200] = sram_blwl_bl[1200:1200] ; -assign sram_blwl_1200_configbus1[1200:1200] = sram_blwl_wl[1200:1200] ; -assign sram_blwl_1200_configbus0_b[1200:1200] = sram_blwl_blb[1200:1200] ; -sram6T_blwl sram_blwl_1200_ (sram_blwl_out[1200], sram_blwl_out[1200], sram_blwl_outb[1200], sram_blwl_1200_configbus0[1200:1200], sram_blwl_1200_configbus1[1200:1200] , sram_blwl_1200_configbus0_b[1200:1200] ); -wire [1201:1201] sram_blwl_1201_configbus0; -wire [1201:1201] sram_blwl_1201_configbus1; -wire [1201:1201] sram_blwl_1201_configbus0_b; -assign sram_blwl_1201_configbus0[1201:1201] = sram_blwl_bl[1201:1201] ; -assign sram_blwl_1201_configbus1[1201:1201] = sram_blwl_wl[1201:1201] ; -assign sram_blwl_1201_configbus0_b[1201:1201] = sram_blwl_blb[1201:1201] ; -sram6T_blwl sram_blwl_1201_ (sram_blwl_out[1201], sram_blwl_out[1201], sram_blwl_outb[1201], sram_blwl_1201_configbus0[1201:1201], sram_blwl_1201_configbus1[1201:1201] , sram_blwl_1201_configbus0_b[1201:1201] ); -wire [1202:1202] sram_blwl_1202_configbus0; -wire [1202:1202] sram_blwl_1202_configbus1; -wire [1202:1202] sram_blwl_1202_configbus0_b; -assign sram_blwl_1202_configbus0[1202:1202] = sram_blwl_bl[1202:1202] ; -assign sram_blwl_1202_configbus1[1202:1202] = sram_blwl_wl[1202:1202] ; -assign sram_blwl_1202_configbus0_b[1202:1202] = sram_blwl_blb[1202:1202] ; -sram6T_blwl sram_blwl_1202_ (sram_blwl_out[1202], sram_blwl_out[1202], sram_blwl_outb[1202], sram_blwl_1202_configbus0[1202:1202], sram_blwl_1202_configbus1[1202:1202] , sram_blwl_1202_configbus0_b[1202:1202] ); -wire [1203:1203] sram_blwl_1203_configbus0; -wire [1203:1203] sram_blwl_1203_configbus1; -wire [1203:1203] sram_blwl_1203_configbus0_b; -assign sram_blwl_1203_configbus0[1203:1203] = sram_blwl_bl[1203:1203] ; -assign sram_blwl_1203_configbus1[1203:1203] = sram_blwl_wl[1203:1203] ; -assign sram_blwl_1203_configbus0_b[1203:1203] = sram_blwl_blb[1203:1203] ; -sram6T_blwl sram_blwl_1203_ (sram_blwl_out[1203], sram_blwl_out[1203], sram_blwl_outb[1203], sram_blwl_1203_configbus0[1203:1203], sram_blwl_1203_configbus1[1203:1203] , sram_blwl_1203_configbus0_b[1203:1203] ); -wire [1204:1204] sram_blwl_1204_configbus0; -wire [1204:1204] sram_blwl_1204_configbus1; -wire [1204:1204] sram_blwl_1204_configbus0_b; -assign sram_blwl_1204_configbus0[1204:1204] = sram_blwl_bl[1204:1204] ; -assign sram_blwl_1204_configbus1[1204:1204] = sram_blwl_wl[1204:1204] ; -assign sram_blwl_1204_configbus0_b[1204:1204] = sram_blwl_blb[1204:1204] ; -sram6T_blwl sram_blwl_1204_ (sram_blwl_out[1204], sram_blwl_out[1204], sram_blwl_outb[1204], sram_blwl_1204_configbus0[1204:1204], sram_blwl_1204_configbus1[1204:1204] , sram_blwl_1204_configbus0_b[1204:1204] ); -wire [1205:1205] sram_blwl_1205_configbus0; -wire [1205:1205] sram_blwl_1205_configbus1; -wire [1205:1205] sram_blwl_1205_configbus0_b; -assign sram_blwl_1205_configbus0[1205:1205] = sram_blwl_bl[1205:1205] ; -assign sram_blwl_1205_configbus1[1205:1205] = sram_blwl_wl[1205:1205] ; -assign sram_blwl_1205_configbus0_b[1205:1205] = sram_blwl_blb[1205:1205] ; -sram6T_blwl sram_blwl_1205_ (sram_blwl_out[1205], sram_blwl_out[1205], sram_blwl_outb[1205], sram_blwl_1205_configbus0[1205:1205], sram_blwl_1205_configbus1[1205:1205] , sram_blwl_1205_configbus0_b[1205:1205] ); -wire [1206:1206] sram_blwl_1206_configbus0; -wire [1206:1206] sram_blwl_1206_configbus1; -wire [1206:1206] sram_blwl_1206_configbus0_b; -assign sram_blwl_1206_configbus0[1206:1206] = sram_blwl_bl[1206:1206] ; -assign sram_blwl_1206_configbus1[1206:1206] = sram_blwl_wl[1206:1206] ; -assign sram_blwl_1206_configbus0_b[1206:1206] = sram_blwl_blb[1206:1206] ; -sram6T_blwl sram_blwl_1206_ (sram_blwl_out[1206], sram_blwl_out[1206], sram_blwl_outb[1206], sram_blwl_1206_configbus0[1206:1206], sram_blwl_1206_configbus1[1206:1206] , sram_blwl_1206_configbus0_b[1206:1206] ); -wire [1207:1207] sram_blwl_1207_configbus0; -wire [1207:1207] sram_blwl_1207_configbus1; -wire [1207:1207] sram_blwl_1207_configbus0_b; -assign sram_blwl_1207_configbus0[1207:1207] = sram_blwl_bl[1207:1207] ; -assign sram_blwl_1207_configbus1[1207:1207] = sram_blwl_wl[1207:1207] ; -assign sram_blwl_1207_configbus0_b[1207:1207] = sram_blwl_blb[1207:1207] ; -sram6T_blwl sram_blwl_1207_ (sram_blwl_out[1207], sram_blwl_out[1207], sram_blwl_outb[1207], sram_blwl_1207_configbus0[1207:1207], sram_blwl_1207_configbus1[1207:1207] , sram_blwl_1207_configbus0_b[1207:1207] ); -wire [1208:1208] sram_blwl_1208_configbus0; -wire [1208:1208] sram_blwl_1208_configbus1; -wire [1208:1208] sram_blwl_1208_configbus0_b; -assign sram_blwl_1208_configbus0[1208:1208] = sram_blwl_bl[1208:1208] ; -assign sram_blwl_1208_configbus1[1208:1208] = sram_blwl_wl[1208:1208] ; -assign sram_blwl_1208_configbus0_b[1208:1208] = sram_blwl_blb[1208:1208] ; -sram6T_blwl sram_blwl_1208_ (sram_blwl_out[1208], sram_blwl_out[1208], sram_blwl_outb[1208], sram_blwl_1208_configbus0[1208:1208], sram_blwl_1208_configbus1[1208:1208] , sram_blwl_1208_configbus0_b[1208:1208] ); -wire [1209:1209] sram_blwl_1209_configbus0; -wire [1209:1209] sram_blwl_1209_configbus1; -wire [1209:1209] sram_blwl_1209_configbus0_b; -assign sram_blwl_1209_configbus0[1209:1209] = sram_blwl_bl[1209:1209] ; -assign sram_blwl_1209_configbus1[1209:1209] = sram_blwl_wl[1209:1209] ; -assign sram_blwl_1209_configbus0_b[1209:1209] = sram_blwl_blb[1209:1209] ; -sram6T_blwl sram_blwl_1209_ (sram_blwl_out[1209], sram_blwl_out[1209], sram_blwl_outb[1209], sram_blwl_1209_configbus0[1209:1209], sram_blwl_1209_configbus1[1209:1209] , sram_blwl_1209_configbus0_b[1209:1209] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- - -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_2_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6_ ----- -module grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble6___in_0_, -input wire mode_ble6___in_1_, -input wire mode_ble6___in_2_, -input wire mode_ble6___in_3_, -input wire mode_ble6___in_4_, -input wire mode_ble6___in_5_, -output wire mode_ble6___out_0_, -input wire mode_ble6___clk_0_, -input [1146:1210] sram_blwl_bl , -input [1146:1210] sram_blwl_wl , -input [1146:1210] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ lut6_0_ ( - lut6_0___in_0_, lut6_0___in_1_, lut6_0___in_2_, lut6_0___in_3_, lut6_0___in_4_, lut6_0___in_5_, lut6_0___out_0_, -sram_blwl_bl[1146:1209] , -sram_blwl_wl[1146:1209] , -sram_blwl_blb[1146:1209] ); -grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_402_ ; -assign in_bus_mux_1level_tapbuf_size2_402_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_402_[1] = lut6_0___out_0_ ; -wire [1210:1210] mux_1level_tapbuf_size2_402_configbus0; -wire [1210:1210] mux_1level_tapbuf_size2_402_configbus1; -wire [1210:1210] mux_1level_tapbuf_size2_402_sram_blwl_out ; -wire [1210:1210] mux_1level_tapbuf_size2_402_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_402_configbus0[1210:1210] = sram_blwl_bl[1210:1210] ; -assign mux_1level_tapbuf_size2_402_configbus1[1210:1210] = sram_blwl_wl[1210:1210] ; -wire [1210:1210] mux_1level_tapbuf_size2_402_configbus0_b; -assign mux_1level_tapbuf_size2_402_configbus0_b[1210:1210] = sram_blwl_blb[1210:1210] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_402_ (in_bus_mux_1level_tapbuf_size2_402_, mode_ble6___out_0_, mux_1level_tapbuf_size2_402_sram_blwl_out[1210:1210] , -mux_1level_tapbuf_size2_402_sram_blwl_outb[1210:1210] ); -//----- SRAM bits for MUX[402], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1210_ (mux_1level_tapbuf_size2_402_sram_blwl_out[1210:1210] ,mux_1level_tapbuf_size2_402_sram_blwl_out[1210:1210] ,mux_1level_tapbuf_size2_402_sram_blwl_outb[1210:1210] ,mux_1level_tapbuf_size2_402_configbus0[1210:1210], mux_1level_tapbuf_size2_402_configbus1[1210:1210] , mux_1level_tapbuf_size2_402_configbus0_b[1210:1210] ); -direct_interc direct_interc_32_ (mode_ble6___in_0_, lut6_0___in_0_ ); -direct_interc direct_interc_33_ (mode_ble6___in_1_, lut6_0___in_1_ ); -direct_interc direct_interc_34_ (mode_ble6___in_2_, lut6_0___in_2_ ); -direct_interc direct_interc_35_ (mode_ble6___in_3_, lut6_0___in_3_ ); -direct_interc direct_interc_36_ (mode_ble6___in_4_, lut6_0___in_4_ ); -direct_interc direct_interc_37_ (mode_ble6___in_5_, lut6_0___in_5_ ); -direct_interc direct_interc_38_ (lut6_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_39_ (mode_ble6___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6_ ----- -module grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut6___in_0_, -input wire mode_n1_lut6___in_1_, -input wire mode_n1_lut6___in_2_, -input wire mode_n1_lut6___in_3_, -input wire mode_n1_lut6___in_4_, -input wire mode_n1_lut6___in_5_, -output wire mode_n1_lut6___out_0_, -input wire mode_n1_lut6___clk_0_, -input [1146:1210] sram_blwl_bl , -input [1146:1210] sram_blwl_wl , -input [1146:1210] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6__ble6_0__mode_ble6_ ble6_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble6_0___in_0_, ble6_0___in_1_, ble6_0___in_2_, ble6_0___in_3_, ble6_0___in_4_, ble6_0___in_5_, ble6_0___out_0_, ble6_0___clk_0_, -sram_blwl_bl[1146:1210] , -sram_blwl_wl[1146:1210] , -sram_blwl_blb[1146:1210] ); -direct_interc direct_interc_40_ (ble6_0___out_0_, mode_n1_lut6___out_0_ ); -direct_interc direct_interc_41_ (mode_n1_lut6___in_0_, ble6_0___in_0_ ); -direct_interc direct_interc_42_ (mode_n1_lut6___in_1_, ble6_0___in_1_ ); -direct_interc direct_interc_43_ (mode_n1_lut6___in_2_, ble6_0___in_2_ ); -direct_interc direct_interc_44_ (mode_n1_lut6___in_3_, ble6_0___in_3_ ); -direct_interc direct_interc_45_ (mode_n1_lut6___in_4_, ble6_0___in_4_ ); -direct_interc direct_interc_46_ (mode_n1_lut6___in_5_, ble6_0___in_5_ ); -direct_interc direct_interc_47_ (mode_n1_lut6___clk_0_, ble6_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6_ ----- - -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ( -input wire lut6_0___in_0_, -input wire lut6_0___in_1_, -input wire lut6_0___in_2_, -input wire lut6_0___in_3_, -input wire lut6_0___in_4_, -input wire lut6_0___in_5_, -output wire lut6_0___out_0_, -input [1211:1274] sram_blwl_bl , -input [1211:1274] sram_blwl_wl , -input [1211:1274] sram_blwl_blb ); -wire [0:5] lut6_0___in; -assign lut6_0___in[0] = lut6_0___in_0_; -assign lut6_0___in[1] = lut6_0___in_1_; -assign lut6_0___in[2] = lut6_0___in_2_; -assign lut6_0___in[3] = lut6_0___in_3_; -assign lut6_0___in[4] = lut6_0___in_4_; -assign lut6_0___in[5] = lut6_0___in_5_; -wire [0:0] lut6_0___out; -assign lut6_0___out_0_ = lut6_0___out[0]; -wire [1211:1274] sram_blwl_out ; -wire [1211:1274] sram_blwl_outb ; -lut6 lut6_3_ ( -//----- Input and output ports ----- - lut6_0___in[0:5] , lut6_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[1211:1274] , sram_blwl_outb[1211:1274] ); -//----- Truth Table for LUT[3], size=6. ----- -//----- SRAM bits for LUT[3], size=6, num_sram=64. ----- -//-----0000000000000000000000000000000000000000000000000000000000000000----- -wire [1211:1211] sram_blwl_1211_configbus0; -wire [1211:1211] sram_blwl_1211_configbus1; -wire [1211:1211] sram_blwl_1211_configbus0_b; -assign sram_blwl_1211_configbus0[1211:1211] = sram_blwl_bl[1211:1211] ; -assign sram_blwl_1211_configbus1[1211:1211] = sram_blwl_wl[1211:1211] ; -assign sram_blwl_1211_configbus0_b[1211:1211] = sram_blwl_blb[1211:1211] ; -sram6T_blwl sram_blwl_1211_ (sram_blwl_out[1211], sram_blwl_out[1211], sram_blwl_outb[1211], sram_blwl_1211_configbus0[1211:1211], sram_blwl_1211_configbus1[1211:1211] , sram_blwl_1211_configbus0_b[1211:1211] ); -wire [1212:1212] sram_blwl_1212_configbus0; -wire [1212:1212] sram_blwl_1212_configbus1; -wire [1212:1212] sram_blwl_1212_configbus0_b; -assign sram_blwl_1212_configbus0[1212:1212] = sram_blwl_bl[1212:1212] ; -assign sram_blwl_1212_configbus1[1212:1212] = sram_blwl_wl[1212:1212] ; -assign sram_blwl_1212_configbus0_b[1212:1212] = sram_blwl_blb[1212:1212] ; -sram6T_blwl sram_blwl_1212_ (sram_blwl_out[1212], sram_blwl_out[1212], sram_blwl_outb[1212], sram_blwl_1212_configbus0[1212:1212], sram_blwl_1212_configbus1[1212:1212] , sram_blwl_1212_configbus0_b[1212:1212] ); -wire [1213:1213] sram_blwl_1213_configbus0; -wire [1213:1213] sram_blwl_1213_configbus1; -wire [1213:1213] sram_blwl_1213_configbus0_b; -assign sram_blwl_1213_configbus0[1213:1213] = sram_blwl_bl[1213:1213] ; -assign sram_blwl_1213_configbus1[1213:1213] = sram_blwl_wl[1213:1213] ; -assign sram_blwl_1213_configbus0_b[1213:1213] = sram_blwl_blb[1213:1213] ; -sram6T_blwl sram_blwl_1213_ (sram_blwl_out[1213], sram_blwl_out[1213], sram_blwl_outb[1213], sram_blwl_1213_configbus0[1213:1213], sram_blwl_1213_configbus1[1213:1213] , sram_blwl_1213_configbus0_b[1213:1213] ); -wire [1214:1214] sram_blwl_1214_configbus0; -wire [1214:1214] sram_blwl_1214_configbus1; -wire [1214:1214] sram_blwl_1214_configbus0_b; -assign sram_blwl_1214_configbus0[1214:1214] = sram_blwl_bl[1214:1214] ; -assign sram_blwl_1214_configbus1[1214:1214] = sram_blwl_wl[1214:1214] ; -assign sram_blwl_1214_configbus0_b[1214:1214] = sram_blwl_blb[1214:1214] ; -sram6T_blwl sram_blwl_1214_ (sram_blwl_out[1214], sram_blwl_out[1214], sram_blwl_outb[1214], sram_blwl_1214_configbus0[1214:1214], sram_blwl_1214_configbus1[1214:1214] , sram_blwl_1214_configbus0_b[1214:1214] ); -wire [1215:1215] sram_blwl_1215_configbus0; -wire [1215:1215] sram_blwl_1215_configbus1; -wire [1215:1215] sram_blwl_1215_configbus0_b; -assign sram_blwl_1215_configbus0[1215:1215] = sram_blwl_bl[1215:1215] ; -assign sram_blwl_1215_configbus1[1215:1215] = sram_blwl_wl[1215:1215] ; -assign sram_blwl_1215_configbus0_b[1215:1215] = sram_blwl_blb[1215:1215] ; -sram6T_blwl sram_blwl_1215_ (sram_blwl_out[1215], sram_blwl_out[1215], sram_blwl_outb[1215], sram_blwl_1215_configbus0[1215:1215], sram_blwl_1215_configbus1[1215:1215] , sram_blwl_1215_configbus0_b[1215:1215] ); -wire [1216:1216] sram_blwl_1216_configbus0; -wire [1216:1216] sram_blwl_1216_configbus1; -wire [1216:1216] sram_blwl_1216_configbus0_b; -assign sram_blwl_1216_configbus0[1216:1216] = sram_blwl_bl[1216:1216] ; -assign sram_blwl_1216_configbus1[1216:1216] = sram_blwl_wl[1216:1216] ; -assign sram_blwl_1216_configbus0_b[1216:1216] = sram_blwl_blb[1216:1216] ; -sram6T_blwl sram_blwl_1216_ (sram_blwl_out[1216], sram_blwl_out[1216], sram_blwl_outb[1216], sram_blwl_1216_configbus0[1216:1216], sram_blwl_1216_configbus1[1216:1216] , sram_blwl_1216_configbus0_b[1216:1216] ); -wire [1217:1217] sram_blwl_1217_configbus0; -wire [1217:1217] sram_blwl_1217_configbus1; -wire [1217:1217] sram_blwl_1217_configbus0_b; -assign sram_blwl_1217_configbus0[1217:1217] = sram_blwl_bl[1217:1217] ; -assign sram_blwl_1217_configbus1[1217:1217] = sram_blwl_wl[1217:1217] ; -assign sram_blwl_1217_configbus0_b[1217:1217] = sram_blwl_blb[1217:1217] ; -sram6T_blwl sram_blwl_1217_ (sram_blwl_out[1217], sram_blwl_out[1217], sram_blwl_outb[1217], sram_blwl_1217_configbus0[1217:1217], sram_blwl_1217_configbus1[1217:1217] , sram_blwl_1217_configbus0_b[1217:1217] ); -wire [1218:1218] sram_blwl_1218_configbus0; -wire [1218:1218] sram_blwl_1218_configbus1; -wire [1218:1218] sram_blwl_1218_configbus0_b; -assign sram_blwl_1218_configbus0[1218:1218] = sram_blwl_bl[1218:1218] ; -assign sram_blwl_1218_configbus1[1218:1218] = sram_blwl_wl[1218:1218] ; -assign sram_blwl_1218_configbus0_b[1218:1218] = sram_blwl_blb[1218:1218] ; -sram6T_blwl sram_blwl_1218_ (sram_blwl_out[1218], sram_blwl_out[1218], sram_blwl_outb[1218], sram_blwl_1218_configbus0[1218:1218], sram_blwl_1218_configbus1[1218:1218] , sram_blwl_1218_configbus0_b[1218:1218] ); -wire [1219:1219] sram_blwl_1219_configbus0; -wire [1219:1219] sram_blwl_1219_configbus1; -wire [1219:1219] sram_blwl_1219_configbus0_b; -assign sram_blwl_1219_configbus0[1219:1219] = sram_blwl_bl[1219:1219] ; -assign sram_blwl_1219_configbus1[1219:1219] = sram_blwl_wl[1219:1219] ; -assign sram_blwl_1219_configbus0_b[1219:1219] = sram_blwl_blb[1219:1219] ; -sram6T_blwl sram_blwl_1219_ (sram_blwl_out[1219], sram_blwl_out[1219], sram_blwl_outb[1219], sram_blwl_1219_configbus0[1219:1219], sram_blwl_1219_configbus1[1219:1219] , sram_blwl_1219_configbus0_b[1219:1219] ); -wire [1220:1220] sram_blwl_1220_configbus0; -wire [1220:1220] sram_blwl_1220_configbus1; -wire [1220:1220] sram_blwl_1220_configbus0_b; -assign sram_blwl_1220_configbus0[1220:1220] = sram_blwl_bl[1220:1220] ; -assign sram_blwl_1220_configbus1[1220:1220] = sram_blwl_wl[1220:1220] ; -assign sram_blwl_1220_configbus0_b[1220:1220] = sram_blwl_blb[1220:1220] ; -sram6T_blwl sram_blwl_1220_ (sram_blwl_out[1220], sram_blwl_out[1220], sram_blwl_outb[1220], sram_blwl_1220_configbus0[1220:1220], sram_blwl_1220_configbus1[1220:1220] , sram_blwl_1220_configbus0_b[1220:1220] ); -wire [1221:1221] sram_blwl_1221_configbus0; -wire [1221:1221] sram_blwl_1221_configbus1; -wire [1221:1221] sram_blwl_1221_configbus0_b; -assign sram_blwl_1221_configbus0[1221:1221] = sram_blwl_bl[1221:1221] ; -assign sram_blwl_1221_configbus1[1221:1221] = sram_blwl_wl[1221:1221] ; -assign sram_blwl_1221_configbus0_b[1221:1221] = sram_blwl_blb[1221:1221] ; -sram6T_blwl sram_blwl_1221_ (sram_blwl_out[1221], sram_blwl_out[1221], sram_blwl_outb[1221], sram_blwl_1221_configbus0[1221:1221], sram_blwl_1221_configbus1[1221:1221] , sram_blwl_1221_configbus0_b[1221:1221] ); -wire [1222:1222] sram_blwl_1222_configbus0; -wire [1222:1222] sram_blwl_1222_configbus1; -wire [1222:1222] sram_blwl_1222_configbus0_b; -assign sram_blwl_1222_configbus0[1222:1222] = sram_blwl_bl[1222:1222] ; -assign sram_blwl_1222_configbus1[1222:1222] = sram_blwl_wl[1222:1222] ; -assign sram_blwl_1222_configbus0_b[1222:1222] = sram_blwl_blb[1222:1222] ; -sram6T_blwl sram_blwl_1222_ (sram_blwl_out[1222], sram_blwl_out[1222], sram_blwl_outb[1222], sram_blwl_1222_configbus0[1222:1222], sram_blwl_1222_configbus1[1222:1222] , sram_blwl_1222_configbus0_b[1222:1222] ); -wire [1223:1223] sram_blwl_1223_configbus0; -wire [1223:1223] sram_blwl_1223_configbus1; -wire [1223:1223] sram_blwl_1223_configbus0_b; -assign sram_blwl_1223_configbus0[1223:1223] = sram_blwl_bl[1223:1223] ; -assign sram_blwl_1223_configbus1[1223:1223] = sram_blwl_wl[1223:1223] ; -assign sram_blwl_1223_configbus0_b[1223:1223] = sram_blwl_blb[1223:1223] ; -sram6T_blwl sram_blwl_1223_ (sram_blwl_out[1223], sram_blwl_out[1223], sram_blwl_outb[1223], sram_blwl_1223_configbus0[1223:1223], sram_blwl_1223_configbus1[1223:1223] , sram_blwl_1223_configbus0_b[1223:1223] ); -wire [1224:1224] sram_blwl_1224_configbus0; -wire [1224:1224] sram_blwl_1224_configbus1; -wire [1224:1224] sram_blwl_1224_configbus0_b; -assign sram_blwl_1224_configbus0[1224:1224] = sram_blwl_bl[1224:1224] ; -assign sram_blwl_1224_configbus1[1224:1224] = sram_blwl_wl[1224:1224] ; -assign sram_blwl_1224_configbus0_b[1224:1224] = sram_blwl_blb[1224:1224] ; -sram6T_blwl sram_blwl_1224_ (sram_blwl_out[1224], sram_blwl_out[1224], sram_blwl_outb[1224], sram_blwl_1224_configbus0[1224:1224], sram_blwl_1224_configbus1[1224:1224] , sram_blwl_1224_configbus0_b[1224:1224] ); -wire [1225:1225] sram_blwl_1225_configbus0; -wire [1225:1225] sram_blwl_1225_configbus1; -wire [1225:1225] sram_blwl_1225_configbus0_b; -assign sram_blwl_1225_configbus0[1225:1225] = sram_blwl_bl[1225:1225] ; -assign sram_blwl_1225_configbus1[1225:1225] = sram_blwl_wl[1225:1225] ; -assign sram_blwl_1225_configbus0_b[1225:1225] = sram_blwl_blb[1225:1225] ; -sram6T_blwl sram_blwl_1225_ (sram_blwl_out[1225], sram_blwl_out[1225], sram_blwl_outb[1225], sram_blwl_1225_configbus0[1225:1225], sram_blwl_1225_configbus1[1225:1225] , sram_blwl_1225_configbus0_b[1225:1225] ); -wire [1226:1226] sram_blwl_1226_configbus0; -wire [1226:1226] sram_blwl_1226_configbus1; -wire [1226:1226] sram_blwl_1226_configbus0_b; -assign sram_blwl_1226_configbus0[1226:1226] = sram_blwl_bl[1226:1226] ; -assign sram_blwl_1226_configbus1[1226:1226] = sram_blwl_wl[1226:1226] ; -assign sram_blwl_1226_configbus0_b[1226:1226] = sram_blwl_blb[1226:1226] ; -sram6T_blwl sram_blwl_1226_ (sram_blwl_out[1226], sram_blwl_out[1226], sram_blwl_outb[1226], sram_blwl_1226_configbus0[1226:1226], sram_blwl_1226_configbus1[1226:1226] , sram_blwl_1226_configbus0_b[1226:1226] ); -wire [1227:1227] sram_blwl_1227_configbus0; -wire [1227:1227] sram_blwl_1227_configbus1; -wire [1227:1227] sram_blwl_1227_configbus0_b; -assign sram_blwl_1227_configbus0[1227:1227] = sram_blwl_bl[1227:1227] ; -assign sram_blwl_1227_configbus1[1227:1227] = sram_blwl_wl[1227:1227] ; -assign sram_blwl_1227_configbus0_b[1227:1227] = sram_blwl_blb[1227:1227] ; -sram6T_blwl sram_blwl_1227_ (sram_blwl_out[1227], sram_blwl_out[1227], sram_blwl_outb[1227], sram_blwl_1227_configbus0[1227:1227], sram_blwl_1227_configbus1[1227:1227] , sram_blwl_1227_configbus0_b[1227:1227] ); -wire [1228:1228] sram_blwl_1228_configbus0; -wire [1228:1228] sram_blwl_1228_configbus1; -wire [1228:1228] sram_blwl_1228_configbus0_b; -assign sram_blwl_1228_configbus0[1228:1228] = sram_blwl_bl[1228:1228] ; -assign sram_blwl_1228_configbus1[1228:1228] = sram_blwl_wl[1228:1228] ; -assign sram_blwl_1228_configbus0_b[1228:1228] = sram_blwl_blb[1228:1228] ; -sram6T_blwl sram_blwl_1228_ (sram_blwl_out[1228], sram_blwl_out[1228], sram_blwl_outb[1228], sram_blwl_1228_configbus0[1228:1228], sram_blwl_1228_configbus1[1228:1228] , sram_blwl_1228_configbus0_b[1228:1228] ); -wire [1229:1229] sram_blwl_1229_configbus0; -wire [1229:1229] sram_blwl_1229_configbus1; -wire [1229:1229] sram_blwl_1229_configbus0_b; -assign sram_blwl_1229_configbus0[1229:1229] = sram_blwl_bl[1229:1229] ; -assign sram_blwl_1229_configbus1[1229:1229] = sram_blwl_wl[1229:1229] ; -assign sram_blwl_1229_configbus0_b[1229:1229] = sram_blwl_blb[1229:1229] ; -sram6T_blwl sram_blwl_1229_ (sram_blwl_out[1229], sram_blwl_out[1229], sram_blwl_outb[1229], sram_blwl_1229_configbus0[1229:1229], sram_blwl_1229_configbus1[1229:1229] , sram_blwl_1229_configbus0_b[1229:1229] ); -wire [1230:1230] sram_blwl_1230_configbus0; -wire [1230:1230] sram_blwl_1230_configbus1; -wire [1230:1230] sram_blwl_1230_configbus0_b; -assign sram_blwl_1230_configbus0[1230:1230] = sram_blwl_bl[1230:1230] ; -assign sram_blwl_1230_configbus1[1230:1230] = sram_blwl_wl[1230:1230] ; -assign sram_blwl_1230_configbus0_b[1230:1230] = sram_blwl_blb[1230:1230] ; -sram6T_blwl sram_blwl_1230_ (sram_blwl_out[1230], sram_blwl_out[1230], sram_blwl_outb[1230], sram_blwl_1230_configbus0[1230:1230], sram_blwl_1230_configbus1[1230:1230] , sram_blwl_1230_configbus0_b[1230:1230] ); -wire [1231:1231] sram_blwl_1231_configbus0; -wire [1231:1231] sram_blwl_1231_configbus1; -wire [1231:1231] sram_blwl_1231_configbus0_b; -assign sram_blwl_1231_configbus0[1231:1231] = sram_blwl_bl[1231:1231] ; -assign sram_blwl_1231_configbus1[1231:1231] = sram_blwl_wl[1231:1231] ; -assign sram_blwl_1231_configbus0_b[1231:1231] = sram_blwl_blb[1231:1231] ; -sram6T_blwl sram_blwl_1231_ (sram_blwl_out[1231], sram_blwl_out[1231], sram_blwl_outb[1231], sram_blwl_1231_configbus0[1231:1231], sram_blwl_1231_configbus1[1231:1231] , sram_blwl_1231_configbus0_b[1231:1231] ); -wire [1232:1232] sram_blwl_1232_configbus0; -wire [1232:1232] sram_blwl_1232_configbus1; -wire [1232:1232] sram_blwl_1232_configbus0_b; -assign sram_blwl_1232_configbus0[1232:1232] = sram_blwl_bl[1232:1232] ; -assign sram_blwl_1232_configbus1[1232:1232] = sram_blwl_wl[1232:1232] ; -assign sram_blwl_1232_configbus0_b[1232:1232] = sram_blwl_blb[1232:1232] ; -sram6T_blwl sram_blwl_1232_ (sram_blwl_out[1232], sram_blwl_out[1232], sram_blwl_outb[1232], sram_blwl_1232_configbus0[1232:1232], sram_blwl_1232_configbus1[1232:1232] , sram_blwl_1232_configbus0_b[1232:1232] ); -wire [1233:1233] sram_blwl_1233_configbus0; -wire [1233:1233] sram_blwl_1233_configbus1; -wire [1233:1233] sram_blwl_1233_configbus0_b; -assign sram_blwl_1233_configbus0[1233:1233] = sram_blwl_bl[1233:1233] ; -assign sram_blwl_1233_configbus1[1233:1233] = sram_blwl_wl[1233:1233] ; -assign sram_blwl_1233_configbus0_b[1233:1233] = sram_blwl_blb[1233:1233] ; -sram6T_blwl sram_blwl_1233_ (sram_blwl_out[1233], sram_blwl_out[1233], sram_blwl_outb[1233], sram_blwl_1233_configbus0[1233:1233], sram_blwl_1233_configbus1[1233:1233] , sram_blwl_1233_configbus0_b[1233:1233] ); -wire [1234:1234] sram_blwl_1234_configbus0; -wire [1234:1234] sram_blwl_1234_configbus1; -wire [1234:1234] sram_blwl_1234_configbus0_b; -assign sram_blwl_1234_configbus0[1234:1234] = sram_blwl_bl[1234:1234] ; -assign sram_blwl_1234_configbus1[1234:1234] = sram_blwl_wl[1234:1234] ; -assign sram_blwl_1234_configbus0_b[1234:1234] = sram_blwl_blb[1234:1234] ; -sram6T_blwl sram_blwl_1234_ (sram_blwl_out[1234], sram_blwl_out[1234], sram_blwl_outb[1234], sram_blwl_1234_configbus0[1234:1234], sram_blwl_1234_configbus1[1234:1234] , sram_blwl_1234_configbus0_b[1234:1234] ); -wire [1235:1235] sram_blwl_1235_configbus0; -wire [1235:1235] sram_blwl_1235_configbus1; -wire [1235:1235] sram_blwl_1235_configbus0_b; -assign sram_blwl_1235_configbus0[1235:1235] = sram_blwl_bl[1235:1235] ; -assign sram_blwl_1235_configbus1[1235:1235] = sram_blwl_wl[1235:1235] ; -assign sram_blwl_1235_configbus0_b[1235:1235] = sram_blwl_blb[1235:1235] ; -sram6T_blwl sram_blwl_1235_ (sram_blwl_out[1235], sram_blwl_out[1235], sram_blwl_outb[1235], sram_blwl_1235_configbus0[1235:1235], sram_blwl_1235_configbus1[1235:1235] , sram_blwl_1235_configbus0_b[1235:1235] ); -wire [1236:1236] sram_blwl_1236_configbus0; -wire [1236:1236] sram_blwl_1236_configbus1; -wire [1236:1236] sram_blwl_1236_configbus0_b; -assign sram_blwl_1236_configbus0[1236:1236] = sram_blwl_bl[1236:1236] ; -assign sram_blwl_1236_configbus1[1236:1236] = sram_blwl_wl[1236:1236] ; -assign sram_blwl_1236_configbus0_b[1236:1236] = sram_blwl_blb[1236:1236] ; -sram6T_blwl sram_blwl_1236_ (sram_blwl_out[1236], sram_blwl_out[1236], sram_blwl_outb[1236], sram_blwl_1236_configbus0[1236:1236], sram_blwl_1236_configbus1[1236:1236] , sram_blwl_1236_configbus0_b[1236:1236] ); -wire [1237:1237] sram_blwl_1237_configbus0; -wire [1237:1237] sram_blwl_1237_configbus1; -wire [1237:1237] sram_blwl_1237_configbus0_b; -assign sram_blwl_1237_configbus0[1237:1237] = sram_blwl_bl[1237:1237] ; -assign sram_blwl_1237_configbus1[1237:1237] = sram_blwl_wl[1237:1237] ; -assign sram_blwl_1237_configbus0_b[1237:1237] = sram_blwl_blb[1237:1237] ; -sram6T_blwl sram_blwl_1237_ (sram_blwl_out[1237], sram_blwl_out[1237], sram_blwl_outb[1237], sram_blwl_1237_configbus0[1237:1237], sram_blwl_1237_configbus1[1237:1237] , sram_blwl_1237_configbus0_b[1237:1237] ); -wire [1238:1238] sram_blwl_1238_configbus0; -wire [1238:1238] sram_blwl_1238_configbus1; -wire [1238:1238] sram_blwl_1238_configbus0_b; -assign sram_blwl_1238_configbus0[1238:1238] = sram_blwl_bl[1238:1238] ; -assign sram_blwl_1238_configbus1[1238:1238] = sram_blwl_wl[1238:1238] ; -assign sram_blwl_1238_configbus0_b[1238:1238] = sram_blwl_blb[1238:1238] ; -sram6T_blwl sram_blwl_1238_ (sram_blwl_out[1238], sram_blwl_out[1238], sram_blwl_outb[1238], sram_blwl_1238_configbus0[1238:1238], sram_blwl_1238_configbus1[1238:1238] , sram_blwl_1238_configbus0_b[1238:1238] ); -wire [1239:1239] sram_blwl_1239_configbus0; -wire [1239:1239] sram_blwl_1239_configbus1; -wire [1239:1239] sram_blwl_1239_configbus0_b; -assign sram_blwl_1239_configbus0[1239:1239] = sram_blwl_bl[1239:1239] ; -assign sram_blwl_1239_configbus1[1239:1239] = sram_blwl_wl[1239:1239] ; -assign sram_blwl_1239_configbus0_b[1239:1239] = sram_blwl_blb[1239:1239] ; -sram6T_blwl sram_blwl_1239_ (sram_blwl_out[1239], sram_blwl_out[1239], sram_blwl_outb[1239], sram_blwl_1239_configbus0[1239:1239], sram_blwl_1239_configbus1[1239:1239] , sram_blwl_1239_configbus0_b[1239:1239] ); -wire [1240:1240] sram_blwl_1240_configbus0; -wire [1240:1240] sram_blwl_1240_configbus1; -wire [1240:1240] sram_blwl_1240_configbus0_b; -assign sram_blwl_1240_configbus0[1240:1240] = sram_blwl_bl[1240:1240] ; -assign sram_blwl_1240_configbus1[1240:1240] = sram_blwl_wl[1240:1240] ; -assign sram_blwl_1240_configbus0_b[1240:1240] = sram_blwl_blb[1240:1240] ; -sram6T_blwl sram_blwl_1240_ (sram_blwl_out[1240], sram_blwl_out[1240], sram_blwl_outb[1240], sram_blwl_1240_configbus0[1240:1240], sram_blwl_1240_configbus1[1240:1240] , sram_blwl_1240_configbus0_b[1240:1240] ); -wire [1241:1241] sram_blwl_1241_configbus0; -wire [1241:1241] sram_blwl_1241_configbus1; -wire [1241:1241] sram_blwl_1241_configbus0_b; -assign sram_blwl_1241_configbus0[1241:1241] = sram_blwl_bl[1241:1241] ; -assign sram_blwl_1241_configbus1[1241:1241] = sram_blwl_wl[1241:1241] ; -assign sram_blwl_1241_configbus0_b[1241:1241] = sram_blwl_blb[1241:1241] ; -sram6T_blwl sram_blwl_1241_ (sram_blwl_out[1241], sram_blwl_out[1241], sram_blwl_outb[1241], sram_blwl_1241_configbus0[1241:1241], sram_blwl_1241_configbus1[1241:1241] , sram_blwl_1241_configbus0_b[1241:1241] ); -wire [1242:1242] sram_blwl_1242_configbus0; -wire [1242:1242] sram_blwl_1242_configbus1; -wire [1242:1242] sram_blwl_1242_configbus0_b; -assign sram_blwl_1242_configbus0[1242:1242] = sram_blwl_bl[1242:1242] ; -assign sram_blwl_1242_configbus1[1242:1242] = sram_blwl_wl[1242:1242] ; -assign sram_blwl_1242_configbus0_b[1242:1242] = sram_blwl_blb[1242:1242] ; -sram6T_blwl sram_blwl_1242_ (sram_blwl_out[1242], sram_blwl_out[1242], sram_blwl_outb[1242], sram_blwl_1242_configbus0[1242:1242], sram_blwl_1242_configbus1[1242:1242] , sram_blwl_1242_configbus0_b[1242:1242] ); -wire [1243:1243] sram_blwl_1243_configbus0; -wire [1243:1243] sram_blwl_1243_configbus1; -wire [1243:1243] sram_blwl_1243_configbus0_b; -assign sram_blwl_1243_configbus0[1243:1243] = sram_blwl_bl[1243:1243] ; -assign sram_blwl_1243_configbus1[1243:1243] = sram_blwl_wl[1243:1243] ; -assign sram_blwl_1243_configbus0_b[1243:1243] = sram_blwl_blb[1243:1243] ; -sram6T_blwl sram_blwl_1243_ (sram_blwl_out[1243], sram_blwl_out[1243], sram_blwl_outb[1243], sram_blwl_1243_configbus0[1243:1243], sram_blwl_1243_configbus1[1243:1243] , sram_blwl_1243_configbus0_b[1243:1243] ); -wire [1244:1244] sram_blwl_1244_configbus0; -wire [1244:1244] sram_blwl_1244_configbus1; -wire [1244:1244] sram_blwl_1244_configbus0_b; -assign sram_blwl_1244_configbus0[1244:1244] = sram_blwl_bl[1244:1244] ; -assign sram_blwl_1244_configbus1[1244:1244] = sram_blwl_wl[1244:1244] ; -assign sram_blwl_1244_configbus0_b[1244:1244] = sram_blwl_blb[1244:1244] ; -sram6T_blwl sram_blwl_1244_ (sram_blwl_out[1244], sram_blwl_out[1244], sram_blwl_outb[1244], sram_blwl_1244_configbus0[1244:1244], sram_blwl_1244_configbus1[1244:1244] , sram_blwl_1244_configbus0_b[1244:1244] ); -wire [1245:1245] sram_blwl_1245_configbus0; -wire [1245:1245] sram_blwl_1245_configbus1; -wire [1245:1245] sram_blwl_1245_configbus0_b; -assign sram_blwl_1245_configbus0[1245:1245] = sram_blwl_bl[1245:1245] ; -assign sram_blwl_1245_configbus1[1245:1245] = sram_blwl_wl[1245:1245] ; -assign sram_blwl_1245_configbus0_b[1245:1245] = sram_blwl_blb[1245:1245] ; -sram6T_blwl sram_blwl_1245_ (sram_blwl_out[1245], sram_blwl_out[1245], sram_blwl_outb[1245], sram_blwl_1245_configbus0[1245:1245], sram_blwl_1245_configbus1[1245:1245] , sram_blwl_1245_configbus0_b[1245:1245] ); -wire [1246:1246] sram_blwl_1246_configbus0; -wire [1246:1246] sram_blwl_1246_configbus1; -wire [1246:1246] sram_blwl_1246_configbus0_b; -assign sram_blwl_1246_configbus0[1246:1246] = sram_blwl_bl[1246:1246] ; -assign sram_blwl_1246_configbus1[1246:1246] = sram_blwl_wl[1246:1246] ; -assign sram_blwl_1246_configbus0_b[1246:1246] = sram_blwl_blb[1246:1246] ; -sram6T_blwl sram_blwl_1246_ (sram_blwl_out[1246], sram_blwl_out[1246], sram_blwl_outb[1246], sram_blwl_1246_configbus0[1246:1246], sram_blwl_1246_configbus1[1246:1246] , sram_blwl_1246_configbus0_b[1246:1246] ); -wire [1247:1247] sram_blwl_1247_configbus0; -wire [1247:1247] sram_blwl_1247_configbus1; -wire [1247:1247] sram_blwl_1247_configbus0_b; -assign sram_blwl_1247_configbus0[1247:1247] = sram_blwl_bl[1247:1247] ; -assign sram_blwl_1247_configbus1[1247:1247] = sram_blwl_wl[1247:1247] ; -assign sram_blwl_1247_configbus0_b[1247:1247] = sram_blwl_blb[1247:1247] ; -sram6T_blwl sram_blwl_1247_ (sram_blwl_out[1247], sram_blwl_out[1247], sram_blwl_outb[1247], sram_blwl_1247_configbus0[1247:1247], sram_blwl_1247_configbus1[1247:1247] , sram_blwl_1247_configbus0_b[1247:1247] ); -wire [1248:1248] sram_blwl_1248_configbus0; -wire [1248:1248] sram_blwl_1248_configbus1; -wire [1248:1248] sram_blwl_1248_configbus0_b; -assign sram_blwl_1248_configbus0[1248:1248] = sram_blwl_bl[1248:1248] ; -assign sram_blwl_1248_configbus1[1248:1248] = sram_blwl_wl[1248:1248] ; -assign sram_blwl_1248_configbus0_b[1248:1248] = sram_blwl_blb[1248:1248] ; -sram6T_blwl sram_blwl_1248_ (sram_blwl_out[1248], sram_blwl_out[1248], sram_blwl_outb[1248], sram_blwl_1248_configbus0[1248:1248], sram_blwl_1248_configbus1[1248:1248] , sram_blwl_1248_configbus0_b[1248:1248] ); -wire [1249:1249] sram_blwl_1249_configbus0; -wire [1249:1249] sram_blwl_1249_configbus1; -wire [1249:1249] sram_blwl_1249_configbus0_b; -assign sram_blwl_1249_configbus0[1249:1249] = sram_blwl_bl[1249:1249] ; -assign sram_blwl_1249_configbus1[1249:1249] = sram_blwl_wl[1249:1249] ; -assign sram_blwl_1249_configbus0_b[1249:1249] = sram_blwl_blb[1249:1249] ; -sram6T_blwl sram_blwl_1249_ (sram_blwl_out[1249], sram_blwl_out[1249], sram_blwl_outb[1249], sram_blwl_1249_configbus0[1249:1249], sram_blwl_1249_configbus1[1249:1249] , sram_blwl_1249_configbus0_b[1249:1249] ); -wire [1250:1250] sram_blwl_1250_configbus0; -wire [1250:1250] sram_blwl_1250_configbus1; -wire [1250:1250] sram_blwl_1250_configbus0_b; -assign sram_blwl_1250_configbus0[1250:1250] = sram_blwl_bl[1250:1250] ; -assign sram_blwl_1250_configbus1[1250:1250] = sram_blwl_wl[1250:1250] ; -assign sram_blwl_1250_configbus0_b[1250:1250] = sram_blwl_blb[1250:1250] ; -sram6T_blwl sram_blwl_1250_ (sram_blwl_out[1250], sram_blwl_out[1250], sram_blwl_outb[1250], sram_blwl_1250_configbus0[1250:1250], sram_blwl_1250_configbus1[1250:1250] , sram_blwl_1250_configbus0_b[1250:1250] ); -wire [1251:1251] sram_blwl_1251_configbus0; -wire [1251:1251] sram_blwl_1251_configbus1; -wire [1251:1251] sram_blwl_1251_configbus0_b; -assign sram_blwl_1251_configbus0[1251:1251] = sram_blwl_bl[1251:1251] ; -assign sram_blwl_1251_configbus1[1251:1251] = sram_blwl_wl[1251:1251] ; -assign sram_blwl_1251_configbus0_b[1251:1251] = sram_blwl_blb[1251:1251] ; -sram6T_blwl sram_blwl_1251_ (sram_blwl_out[1251], sram_blwl_out[1251], sram_blwl_outb[1251], sram_blwl_1251_configbus0[1251:1251], sram_blwl_1251_configbus1[1251:1251] , sram_blwl_1251_configbus0_b[1251:1251] ); -wire [1252:1252] sram_blwl_1252_configbus0; -wire [1252:1252] sram_blwl_1252_configbus1; -wire [1252:1252] sram_blwl_1252_configbus0_b; -assign sram_blwl_1252_configbus0[1252:1252] = sram_blwl_bl[1252:1252] ; -assign sram_blwl_1252_configbus1[1252:1252] = sram_blwl_wl[1252:1252] ; -assign sram_blwl_1252_configbus0_b[1252:1252] = sram_blwl_blb[1252:1252] ; -sram6T_blwl sram_blwl_1252_ (sram_blwl_out[1252], sram_blwl_out[1252], sram_blwl_outb[1252], sram_blwl_1252_configbus0[1252:1252], sram_blwl_1252_configbus1[1252:1252] , sram_blwl_1252_configbus0_b[1252:1252] ); -wire [1253:1253] sram_blwl_1253_configbus0; -wire [1253:1253] sram_blwl_1253_configbus1; -wire [1253:1253] sram_blwl_1253_configbus0_b; -assign sram_blwl_1253_configbus0[1253:1253] = sram_blwl_bl[1253:1253] ; -assign sram_blwl_1253_configbus1[1253:1253] = sram_blwl_wl[1253:1253] ; -assign sram_blwl_1253_configbus0_b[1253:1253] = sram_blwl_blb[1253:1253] ; -sram6T_blwl sram_blwl_1253_ (sram_blwl_out[1253], sram_blwl_out[1253], sram_blwl_outb[1253], sram_blwl_1253_configbus0[1253:1253], sram_blwl_1253_configbus1[1253:1253] , sram_blwl_1253_configbus0_b[1253:1253] ); -wire [1254:1254] sram_blwl_1254_configbus0; -wire [1254:1254] sram_blwl_1254_configbus1; -wire [1254:1254] sram_blwl_1254_configbus0_b; -assign sram_blwl_1254_configbus0[1254:1254] = sram_blwl_bl[1254:1254] ; -assign sram_blwl_1254_configbus1[1254:1254] = sram_blwl_wl[1254:1254] ; -assign sram_blwl_1254_configbus0_b[1254:1254] = sram_blwl_blb[1254:1254] ; -sram6T_blwl sram_blwl_1254_ (sram_blwl_out[1254], sram_blwl_out[1254], sram_blwl_outb[1254], sram_blwl_1254_configbus0[1254:1254], sram_blwl_1254_configbus1[1254:1254] , sram_blwl_1254_configbus0_b[1254:1254] ); -wire [1255:1255] sram_blwl_1255_configbus0; -wire [1255:1255] sram_blwl_1255_configbus1; -wire [1255:1255] sram_blwl_1255_configbus0_b; -assign sram_blwl_1255_configbus0[1255:1255] = sram_blwl_bl[1255:1255] ; -assign sram_blwl_1255_configbus1[1255:1255] = sram_blwl_wl[1255:1255] ; -assign sram_blwl_1255_configbus0_b[1255:1255] = sram_blwl_blb[1255:1255] ; -sram6T_blwl sram_blwl_1255_ (sram_blwl_out[1255], sram_blwl_out[1255], sram_blwl_outb[1255], sram_blwl_1255_configbus0[1255:1255], sram_blwl_1255_configbus1[1255:1255] , sram_blwl_1255_configbus0_b[1255:1255] ); -wire [1256:1256] sram_blwl_1256_configbus0; -wire [1256:1256] sram_blwl_1256_configbus1; -wire [1256:1256] sram_blwl_1256_configbus0_b; -assign sram_blwl_1256_configbus0[1256:1256] = sram_blwl_bl[1256:1256] ; -assign sram_blwl_1256_configbus1[1256:1256] = sram_blwl_wl[1256:1256] ; -assign sram_blwl_1256_configbus0_b[1256:1256] = sram_blwl_blb[1256:1256] ; -sram6T_blwl sram_blwl_1256_ (sram_blwl_out[1256], sram_blwl_out[1256], sram_blwl_outb[1256], sram_blwl_1256_configbus0[1256:1256], sram_blwl_1256_configbus1[1256:1256] , sram_blwl_1256_configbus0_b[1256:1256] ); -wire [1257:1257] sram_blwl_1257_configbus0; -wire [1257:1257] sram_blwl_1257_configbus1; -wire [1257:1257] sram_blwl_1257_configbus0_b; -assign sram_blwl_1257_configbus0[1257:1257] = sram_blwl_bl[1257:1257] ; -assign sram_blwl_1257_configbus1[1257:1257] = sram_blwl_wl[1257:1257] ; -assign sram_blwl_1257_configbus0_b[1257:1257] = sram_blwl_blb[1257:1257] ; -sram6T_blwl sram_blwl_1257_ (sram_blwl_out[1257], sram_blwl_out[1257], sram_blwl_outb[1257], sram_blwl_1257_configbus0[1257:1257], sram_blwl_1257_configbus1[1257:1257] , sram_blwl_1257_configbus0_b[1257:1257] ); -wire [1258:1258] sram_blwl_1258_configbus0; -wire [1258:1258] sram_blwl_1258_configbus1; -wire [1258:1258] sram_blwl_1258_configbus0_b; -assign sram_blwl_1258_configbus0[1258:1258] = sram_blwl_bl[1258:1258] ; -assign sram_blwl_1258_configbus1[1258:1258] = sram_blwl_wl[1258:1258] ; -assign sram_blwl_1258_configbus0_b[1258:1258] = sram_blwl_blb[1258:1258] ; -sram6T_blwl sram_blwl_1258_ (sram_blwl_out[1258], sram_blwl_out[1258], sram_blwl_outb[1258], sram_blwl_1258_configbus0[1258:1258], sram_blwl_1258_configbus1[1258:1258] , sram_blwl_1258_configbus0_b[1258:1258] ); -wire [1259:1259] sram_blwl_1259_configbus0; -wire [1259:1259] sram_blwl_1259_configbus1; -wire [1259:1259] sram_blwl_1259_configbus0_b; -assign sram_blwl_1259_configbus0[1259:1259] = sram_blwl_bl[1259:1259] ; -assign sram_blwl_1259_configbus1[1259:1259] = sram_blwl_wl[1259:1259] ; -assign sram_blwl_1259_configbus0_b[1259:1259] = sram_blwl_blb[1259:1259] ; -sram6T_blwl sram_blwl_1259_ (sram_blwl_out[1259], sram_blwl_out[1259], sram_blwl_outb[1259], sram_blwl_1259_configbus0[1259:1259], sram_blwl_1259_configbus1[1259:1259] , sram_blwl_1259_configbus0_b[1259:1259] ); -wire [1260:1260] sram_blwl_1260_configbus0; -wire [1260:1260] sram_blwl_1260_configbus1; -wire [1260:1260] sram_blwl_1260_configbus0_b; -assign sram_blwl_1260_configbus0[1260:1260] = sram_blwl_bl[1260:1260] ; -assign sram_blwl_1260_configbus1[1260:1260] = sram_blwl_wl[1260:1260] ; -assign sram_blwl_1260_configbus0_b[1260:1260] = sram_blwl_blb[1260:1260] ; -sram6T_blwl sram_blwl_1260_ (sram_blwl_out[1260], sram_blwl_out[1260], sram_blwl_outb[1260], sram_blwl_1260_configbus0[1260:1260], sram_blwl_1260_configbus1[1260:1260] , sram_blwl_1260_configbus0_b[1260:1260] ); -wire [1261:1261] sram_blwl_1261_configbus0; -wire [1261:1261] sram_blwl_1261_configbus1; -wire [1261:1261] sram_blwl_1261_configbus0_b; -assign sram_blwl_1261_configbus0[1261:1261] = sram_blwl_bl[1261:1261] ; -assign sram_blwl_1261_configbus1[1261:1261] = sram_blwl_wl[1261:1261] ; -assign sram_blwl_1261_configbus0_b[1261:1261] = sram_blwl_blb[1261:1261] ; -sram6T_blwl sram_blwl_1261_ (sram_blwl_out[1261], sram_blwl_out[1261], sram_blwl_outb[1261], sram_blwl_1261_configbus0[1261:1261], sram_blwl_1261_configbus1[1261:1261] , sram_blwl_1261_configbus0_b[1261:1261] ); -wire [1262:1262] sram_blwl_1262_configbus0; -wire [1262:1262] sram_blwl_1262_configbus1; -wire [1262:1262] sram_blwl_1262_configbus0_b; -assign sram_blwl_1262_configbus0[1262:1262] = sram_blwl_bl[1262:1262] ; -assign sram_blwl_1262_configbus1[1262:1262] = sram_blwl_wl[1262:1262] ; -assign sram_blwl_1262_configbus0_b[1262:1262] = sram_blwl_blb[1262:1262] ; -sram6T_blwl sram_blwl_1262_ (sram_blwl_out[1262], sram_blwl_out[1262], sram_blwl_outb[1262], sram_blwl_1262_configbus0[1262:1262], sram_blwl_1262_configbus1[1262:1262] , sram_blwl_1262_configbus0_b[1262:1262] ); -wire [1263:1263] sram_blwl_1263_configbus0; -wire [1263:1263] sram_blwl_1263_configbus1; -wire [1263:1263] sram_blwl_1263_configbus0_b; -assign sram_blwl_1263_configbus0[1263:1263] = sram_blwl_bl[1263:1263] ; -assign sram_blwl_1263_configbus1[1263:1263] = sram_blwl_wl[1263:1263] ; -assign sram_blwl_1263_configbus0_b[1263:1263] = sram_blwl_blb[1263:1263] ; -sram6T_blwl sram_blwl_1263_ (sram_blwl_out[1263], sram_blwl_out[1263], sram_blwl_outb[1263], sram_blwl_1263_configbus0[1263:1263], sram_blwl_1263_configbus1[1263:1263] , sram_blwl_1263_configbus0_b[1263:1263] ); -wire [1264:1264] sram_blwl_1264_configbus0; -wire [1264:1264] sram_blwl_1264_configbus1; -wire [1264:1264] sram_blwl_1264_configbus0_b; -assign sram_blwl_1264_configbus0[1264:1264] = sram_blwl_bl[1264:1264] ; -assign sram_blwl_1264_configbus1[1264:1264] = sram_blwl_wl[1264:1264] ; -assign sram_blwl_1264_configbus0_b[1264:1264] = sram_blwl_blb[1264:1264] ; -sram6T_blwl sram_blwl_1264_ (sram_blwl_out[1264], sram_blwl_out[1264], sram_blwl_outb[1264], sram_blwl_1264_configbus0[1264:1264], sram_blwl_1264_configbus1[1264:1264] , sram_blwl_1264_configbus0_b[1264:1264] ); -wire [1265:1265] sram_blwl_1265_configbus0; -wire [1265:1265] sram_blwl_1265_configbus1; -wire [1265:1265] sram_blwl_1265_configbus0_b; -assign sram_blwl_1265_configbus0[1265:1265] = sram_blwl_bl[1265:1265] ; -assign sram_blwl_1265_configbus1[1265:1265] = sram_blwl_wl[1265:1265] ; -assign sram_blwl_1265_configbus0_b[1265:1265] = sram_blwl_blb[1265:1265] ; -sram6T_blwl sram_blwl_1265_ (sram_blwl_out[1265], sram_blwl_out[1265], sram_blwl_outb[1265], sram_blwl_1265_configbus0[1265:1265], sram_blwl_1265_configbus1[1265:1265] , sram_blwl_1265_configbus0_b[1265:1265] ); -wire [1266:1266] sram_blwl_1266_configbus0; -wire [1266:1266] sram_blwl_1266_configbus1; -wire [1266:1266] sram_blwl_1266_configbus0_b; -assign sram_blwl_1266_configbus0[1266:1266] = sram_blwl_bl[1266:1266] ; -assign sram_blwl_1266_configbus1[1266:1266] = sram_blwl_wl[1266:1266] ; -assign sram_blwl_1266_configbus0_b[1266:1266] = sram_blwl_blb[1266:1266] ; -sram6T_blwl sram_blwl_1266_ (sram_blwl_out[1266], sram_blwl_out[1266], sram_blwl_outb[1266], sram_blwl_1266_configbus0[1266:1266], sram_blwl_1266_configbus1[1266:1266] , sram_blwl_1266_configbus0_b[1266:1266] ); -wire [1267:1267] sram_blwl_1267_configbus0; -wire [1267:1267] sram_blwl_1267_configbus1; -wire [1267:1267] sram_blwl_1267_configbus0_b; -assign sram_blwl_1267_configbus0[1267:1267] = sram_blwl_bl[1267:1267] ; -assign sram_blwl_1267_configbus1[1267:1267] = sram_blwl_wl[1267:1267] ; -assign sram_blwl_1267_configbus0_b[1267:1267] = sram_blwl_blb[1267:1267] ; -sram6T_blwl sram_blwl_1267_ (sram_blwl_out[1267], sram_blwl_out[1267], sram_blwl_outb[1267], sram_blwl_1267_configbus0[1267:1267], sram_blwl_1267_configbus1[1267:1267] , sram_blwl_1267_configbus0_b[1267:1267] ); -wire [1268:1268] sram_blwl_1268_configbus0; -wire [1268:1268] sram_blwl_1268_configbus1; -wire [1268:1268] sram_blwl_1268_configbus0_b; -assign sram_blwl_1268_configbus0[1268:1268] = sram_blwl_bl[1268:1268] ; -assign sram_blwl_1268_configbus1[1268:1268] = sram_blwl_wl[1268:1268] ; -assign sram_blwl_1268_configbus0_b[1268:1268] = sram_blwl_blb[1268:1268] ; -sram6T_blwl sram_blwl_1268_ (sram_blwl_out[1268], sram_blwl_out[1268], sram_blwl_outb[1268], sram_blwl_1268_configbus0[1268:1268], sram_blwl_1268_configbus1[1268:1268] , sram_blwl_1268_configbus0_b[1268:1268] ); -wire [1269:1269] sram_blwl_1269_configbus0; -wire [1269:1269] sram_blwl_1269_configbus1; -wire [1269:1269] sram_blwl_1269_configbus0_b; -assign sram_blwl_1269_configbus0[1269:1269] = sram_blwl_bl[1269:1269] ; -assign sram_blwl_1269_configbus1[1269:1269] = sram_blwl_wl[1269:1269] ; -assign sram_blwl_1269_configbus0_b[1269:1269] = sram_blwl_blb[1269:1269] ; -sram6T_blwl sram_blwl_1269_ (sram_blwl_out[1269], sram_blwl_out[1269], sram_blwl_outb[1269], sram_blwl_1269_configbus0[1269:1269], sram_blwl_1269_configbus1[1269:1269] , sram_blwl_1269_configbus0_b[1269:1269] ); -wire [1270:1270] sram_blwl_1270_configbus0; -wire [1270:1270] sram_blwl_1270_configbus1; -wire [1270:1270] sram_blwl_1270_configbus0_b; -assign sram_blwl_1270_configbus0[1270:1270] = sram_blwl_bl[1270:1270] ; -assign sram_blwl_1270_configbus1[1270:1270] = sram_blwl_wl[1270:1270] ; -assign sram_blwl_1270_configbus0_b[1270:1270] = sram_blwl_blb[1270:1270] ; -sram6T_blwl sram_blwl_1270_ (sram_blwl_out[1270], sram_blwl_out[1270], sram_blwl_outb[1270], sram_blwl_1270_configbus0[1270:1270], sram_blwl_1270_configbus1[1270:1270] , sram_blwl_1270_configbus0_b[1270:1270] ); -wire [1271:1271] sram_blwl_1271_configbus0; -wire [1271:1271] sram_blwl_1271_configbus1; -wire [1271:1271] sram_blwl_1271_configbus0_b; -assign sram_blwl_1271_configbus0[1271:1271] = sram_blwl_bl[1271:1271] ; -assign sram_blwl_1271_configbus1[1271:1271] = sram_blwl_wl[1271:1271] ; -assign sram_blwl_1271_configbus0_b[1271:1271] = sram_blwl_blb[1271:1271] ; -sram6T_blwl sram_blwl_1271_ (sram_blwl_out[1271], sram_blwl_out[1271], sram_blwl_outb[1271], sram_blwl_1271_configbus0[1271:1271], sram_blwl_1271_configbus1[1271:1271] , sram_blwl_1271_configbus0_b[1271:1271] ); -wire [1272:1272] sram_blwl_1272_configbus0; -wire [1272:1272] sram_blwl_1272_configbus1; -wire [1272:1272] sram_blwl_1272_configbus0_b; -assign sram_blwl_1272_configbus0[1272:1272] = sram_blwl_bl[1272:1272] ; -assign sram_blwl_1272_configbus1[1272:1272] = sram_blwl_wl[1272:1272] ; -assign sram_blwl_1272_configbus0_b[1272:1272] = sram_blwl_blb[1272:1272] ; -sram6T_blwl sram_blwl_1272_ (sram_blwl_out[1272], sram_blwl_out[1272], sram_blwl_outb[1272], sram_blwl_1272_configbus0[1272:1272], sram_blwl_1272_configbus1[1272:1272] , sram_blwl_1272_configbus0_b[1272:1272] ); -wire [1273:1273] sram_blwl_1273_configbus0; -wire [1273:1273] sram_blwl_1273_configbus1; -wire [1273:1273] sram_blwl_1273_configbus0_b; -assign sram_blwl_1273_configbus0[1273:1273] = sram_blwl_bl[1273:1273] ; -assign sram_blwl_1273_configbus1[1273:1273] = sram_blwl_wl[1273:1273] ; -assign sram_blwl_1273_configbus0_b[1273:1273] = sram_blwl_blb[1273:1273] ; -sram6T_blwl sram_blwl_1273_ (sram_blwl_out[1273], sram_blwl_out[1273], sram_blwl_outb[1273], sram_blwl_1273_configbus0[1273:1273], sram_blwl_1273_configbus1[1273:1273] , sram_blwl_1273_configbus0_b[1273:1273] ); -wire [1274:1274] sram_blwl_1274_configbus0; -wire [1274:1274] sram_blwl_1274_configbus1; -wire [1274:1274] sram_blwl_1274_configbus0_b; -assign sram_blwl_1274_configbus0[1274:1274] = sram_blwl_bl[1274:1274] ; -assign sram_blwl_1274_configbus1[1274:1274] = sram_blwl_wl[1274:1274] ; -assign sram_blwl_1274_configbus0_b[1274:1274] = sram_blwl_blb[1274:1274] ; -sram6T_blwl sram_blwl_1274_ (sram_blwl_out[1274], sram_blwl_out[1274], sram_blwl_outb[1274], sram_blwl_1274_configbus0[1274:1274], sram_blwl_1274_configbus1[1274:1274] , sram_blwl_1274_configbus0_b[1274:1274] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- - -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_3_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6_ ----- -module grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble6___in_0_, -input wire mode_ble6___in_1_, -input wire mode_ble6___in_2_, -input wire mode_ble6___in_3_, -input wire mode_ble6___in_4_, -input wire mode_ble6___in_5_, -output wire mode_ble6___out_0_, -input wire mode_ble6___clk_0_, -input [1211:1275] sram_blwl_bl , -input [1211:1275] sram_blwl_wl , -input [1211:1275] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ lut6_0_ ( - lut6_0___in_0_, lut6_0___in_1_, lut6_0___in_2_, lut6_0___in_3_, lut6_0___in_4_, lut6_0___in_5_, lut6_0___out_0_, -sram_blwl_bl[1211:1274] , -sram_blwl_wl[1211:1274] , -sram_blwl_blb[1211:1274] ); -grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_403_ ; -assign in_bus_mux_1level_tapbuf_size2_403_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_403_[1] = lut6_0___out_0_ ; -wire [1275:1275] mux_1level_tapbuf_size2_403_configbus0; -wire [1275:1275] mux_1level_tapbuf_size2_403_configbus1; -wire [1275:1275] mux_1level_tapbuf_size2_403_sram_blwl_out ; -wire [1275:1275] mux_1level_tapbuf_size2_403_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_403_configbus0[1275:1275] = sram_blwl_bl[1275:1275] ; -assign mux_1level_tapbuf_size2_403_configbus1[1275:1275] = sram_blwl_wl[1275:1275] ; -wire [1275:1275] mux_1level_tapbuf_size2_403_configbus0_b; -assign mux_1level_tapbuf_size2_403_configbus0_b[1275:1275] = sram_blwl_blb[1275:1275] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_403_ (in_bus_mux_1level_tapbuf_size2_403_, mode_ble6___out_0_, mux_1level_tapbuf_size2_403_sram_blwl_out[1275:1275] , -mux_1level_tapbuf_size2_403_sram_blwl_outb[1275:1275] ); -//----- SRAM bits for MUX[403], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1275_ (mux_1level_tapbuf_size2_403_sram_blwl_out[1275:1275] ,mux_1level_tapbuf_size2_403_sram_blwl_out[1275:1275] ,mux_1level_tapbuf_size2_403_sram_blwl_outb[1275:1275] ,mux_1level_tapbuf_size2_403_configbus0[1275:1275], mux_1level_tapbuf_size2_403_configbus1[1275:1275] , mux_1level_tapbuf_size2_403_configbus0_b[1275:1275] ); -direct_interc direct_interc_48_ (mode_ble6___in_0_, lut6_0___in_0_ ); -direct_interc direct_interc_49_ (mode_ble6___in_1_, lut6_0___in_1_ ); -direct_interc direct_interc_50_ (mode_ble6___in_2_, lut6_0___in_2_ ); -direct_interc direct_interc_51_ (mode_ble6___in_3_, lut6_0___in_3_ ); -direct_interc direct_interc_52_ (mode_ble6___in_4_, lut6_0___in_4_ ); -direct_interc direct_interc_53_ (mode_ble6___in_5_, lut6_0___in_5_ ); -direct_interc direct_interc_54_ (lut6_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_55_ (mode_ble6___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6_ ----- -module grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut6___in_0_, -input wire mode_n1_lut6___in_1_, -input wire mode_n1_lut6___in_2_, -input wire mode_n1_lut6___in_3_, -input wire mode_n1_lut6___in_4_, -input wire mode_n1_lut6___in_5_, -output wire mode_n1_lut6___out_0_, -input wire mode_n1_lut6___clk_0_, -input [1211:1275] sram_blwl_bl , -input [1211:1275] sram_blwl_wl , -input [1211:1275] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6__ble6_0__mode_ble6_ ble6_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble6_0___in_0_, ble6_0___in_1_, ble6_0___in_2_, ble6_0___in_3_, ble6_0___in_4_, ble6_0___in_5_, ble6_0___out_0_, ble6_0___clk_0_, -sram_blwl_bl[1211:1275] , -sram_blwl_wl[1211:1275] , -sram_blwl_blb[1211:1275] ); -direct_interc direct_interc_56_ (ble6_0___out_0_, mode_n1_lut6___out_0_ ); -direct_interc direct_interc_57_ (mode_n1_lut6___in_0_, ble6_0___in_0_ ); -direct_interc direct_interc_58_ (mode_n1_lut6___in_1_, ble6_0___in_1_ ); -direct_interc direct_interc_59_ (mode_n1_lut6___in_2_, ble6_0___in_2_ ); -direct_interc direct_interc_60_ (mode_n1_lut6___in_3_, ble6_0___in_3_ ); -direct_interc direct_interc_61_ (mode_n1_lut6___in_4_, ble6_0___in_4_ ); -direct_interc direct_interc_62_ (mode_n1_lut6___in_5_, ble6_0___in_5_ ); -direct_interc direct_interc_63_ (mode_n1_lut6___clk_0_, ble6_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6_ ----- - -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ( -input wire lut6_0___in_0_, -input wire lut6_0___in_1_, -input wire lut6_0___in_2_, -input wire lut6_0___in_3_, -input wire lut6_0___in_4_, -input wire lut6_0___in_5_, -output wire lut6_0___out_0_, -input [1276:1339] sram_blwl_bl , -input [1276:1339] sram_blwl_wl , -input [1276:1339] sram_blwl_blb ); -wire [0:5] lut6_0___in; -assign lut6_0___in[0] = lut6_0___in_0_; -assign lut6_0___in[1] = lut6_0___in_1_; -assign lut6_0___in[2] = lut6_0___in_2_; -assign lut6_0___in[3] = lut6_0___in_3_; -assign lut6_0___in[4] = lut6_0___in_4_; -assign lut6_0___in[5] = lut6_0___in_5_; -wire [0:0] lut6_0___out; -assign lut6_0___out_0_ = lut6_0___out[0]; -wire [1276:1339] sram_blwl_out ; -wire [1276:1339] sram_blwl_outb ; -lut6 lut6_4_ ( -//----- Input and output ports ----- - lut6_0___in[0:5] , lut6_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[1276:1339] , sram_blwl_outb[1276:1339] ); -//----- Truth Table for LUT[4], size=6. ----- -//----- SRAM bits for LUT[4], size=6, num_sram=64. ----- -//-----0000000000000000000000000000000000000000000000000000000000000000----- -wire [1276:1276] sram_blwl_1276_configbus0; -wire [1276:1276] sram_blwl_1276_configbus1; -wire [1276:1276] sram_blwl_1276_configbus0_b; -assign sram_blwl_1276_configbus0[1276:1276] = sram_blwl_bl[1276:1276] ; -assign sram_blwl_1276_configbus1[1276:1276] = sram_blwl_wl[1276:1276] ; -assign sram_blwl_1276_configbus0_b[1276:1276] = sram_blwl_blb[1276:1276] ; -sram6T_blwl sram_blwl_1276_ (sram_blwl_out[1276], sram_blwl_out[1276], sram_blwl_outb[1276], sram_blwl_1276_configbus0[1276:1276], sram_blwl_1276_configbus1[1276:1276] , sram_blwl_1276_configbus0_b[1276:1276] ); -wire [1277:1277] sram_blwl_1277_configbus0; -wire [1277:1277] sram_blwl_1277_configbus1; -wire [1277:1277] sram_blwl_1277_configbus0_b; -assign sram_blwl_1277_configbus0[1277:1277] = sram_blwl_bl[1277:1277] ; -assign sram_blwl_1277_configbus1[1277:1277] = sram_blwl_wl[1277:1277] ; -assign sram_blwl_1277_configbus0_b[1277:1277] = sram_blwl_blb[1277:1277] ; -sram6T_blwl sram_blwl_1277_ (sram_blwl_out[1277], sram_blwl_out[1277], sram_blwl_outb[1277], sram_blwl_1277_configbus0[1277:1277], sram_blwl_1277_configbus1[1277:1277] , sram_blwl_1277_configbus0_b[1277:1277] ); -wire [1278:1278] sram_blwl_1278_configbus0; -wire [1278:1278] sram_blwl_1278_configbus1; -wire [1278:1278] sram_blwl_1278_configbus0_b; -assign sram_blwl_1278_configbus0[1278:1278] = sram_blwl_bl[1278:1278] ; -assign sram_blwl_1278_configbus1[1278:1278] = sram_blwl_wl[1278:1278] ; -assign sram_blwl_1278_configbus0_b[1278:1278] = sram_blwl_blb[1278:1278] ; -sram6T_blwl sram_blwl_1278_ (sram_blwl_out[1278], sram_blwl_out[1278], sram_blwl_outb[1278], sram_blwl_1278_configbus0[1278:1278], sram_blwl_1278_configbus1[1278:1278] , sram_blwl_1278_configbus0_b[1278:1278] ); -wire [1279:1279] sram_blwl_1279_configbus0; -wire [1279:1279] sram_blwl_1279_configbus1; -wire [1279:1279] sram_blwl_1279_configbus0_b; -assign sram_blwl_1279_configbus0[1279:1279] = sram_blwl_bl[1279:1279] ; -assign sram_blwl_1279_configbus1[1279:1279] = sram_blwl_wl[1279:1279] ; -assign sram_blwl_1279_configbus0_b[1279:1279] = sram_blwl_blb[1279:1279] ; -sram6T_blwl sram_blwl_1279_ (sram_blwl_out[1279], sram_blwl_out[1279], sram_blwl_outb[1279], sram_blwl_1279_configbus0[1279:1279], sram_blwl_1279_configbus1[1279:1279] , sram_blwl_1279_configbus0_b[1279:1279] ); -wire [1280:1280] sram_blwl_1280_configbus0; -wire [1280:1280] sram_blwl_1280_configbus1; -wire [1280:1280] sram_blwl_1280_configbus0_b; -assign sram_blwl_1280_configbus0[1280:1280] = sram_blwl_bl[1280:1280] ; -assign sram_blwl_1280_configbus1[1280:1280] = sram_blwl_wl[1280:1280] ; -assign sram_blwl_1280_configbus0_b[1280:1280] = sram_blwl_blb[1280:1280] ; -sram6T_blwl sram_blwl_1280_ (sram_blwl_out[1280], sram_blwl_out[1280], sram_blwl_outb[1280], sram_blwl_1280_configbus0[1280:1280], sram_blwl_1280_configbus1[1280:1280] , sram_blwl_1280_configbus0_b[1280:1280] ); -wire [1281:1281] sram_blwl_1281_configbus0; -wire [1281:1281] sram_blwl_1281_configbus1; -wire [1281:1281] sram_blwl_1281_configbus0_b; -assign sram_blwl_1281_configbus0[1281:1281] = sram_blwl_bl[1281:1281] ; -assign sram_blwl_1281_configbus1[1281:1281] = sram_blwl_wl[1281:1281] ; -assign sram_blwl_1281_configbus0_b[1281:1281] = sram_blwl_blb[1281:1281] ; -sram6T_blwl sram_blwl_1281_ (sram_blwl_out[1281], sram_blwl_out[1281], sram_blwl_outb[1281], sram_blwl_1281_configbus0[1281:1281], sram_blwl_1281_configbus1[1281:1281] , sram_blwl_1281_configbus0_b[1281:1281] ); -wire [1282:1282] sram_blwl_1282_configbus0; -wire [1282:1282] sram_blwl_1282_configbus1; -wire [1282:1282] sram_blwl_1282_configbus0_b; -assign sram_blwl_1282_configbus0[1282:1282] = sram_blwl_bl[1282:1282] ; -assign sram_blwl_1282_configbus1[1282:1282] = sram_blwl_wl[1282:1282] ; -assign sram_blwl_1282_configbus0_b[1282:1282] = sram_blwl_blb[1282:1282] ; -sram6T_blwl sram_blwl_1282_ (sram_blwl_out[1282], sram_blwl_out[1282], sram_blwl_outb[1282], sram_blwl_1282_configbus0[1282:1282], sram_blwl_1282_configbus1[1282:1282] , sram_blwl_1282_configbus0_b[1282:1282] ); -wire [1283:1283] sram_blwl_1283_configbus0; -wire [1283:1283] sram_blwl_1283_configbus1; -wire [1283:1283] sram_blwl_1283_configbus0_b; -assign sram_blwl_1283_configbus0[1283:1283] = sram_blwl_bl[1283:1283] ; -assign sram_blwl_1283_configbus1[1283:1283] = sram_blwl_wl[1283:1283] ; -assign sram_blwl_1283_configbus0_b[1283:1283] = sram_blwl_blb[1283:1283] ; -sram6T_blwl sram_blwl_1283_ (sram_blwl_out[1283], sram_blwl_out[1283], sram_blwl_outb[1283], sram_blwl_1283_configbus0[1283:1283], sram_blwl_1283_configbus1[1283:1283] , sram_blwl_1283_configbus0_b[1283:1283] ); -wire [1284:1284] sram_blwl_1284_configbus0; -wire [1284:1284] sram_blwl_1284_configbus1; -wire [1284:1284] sram_blwl_1284_configbus0_b; -assign sram_blwl_1284_configbus0[1284:1284] = sram_blwl_bl[1284:1284] ; -assign sram_blwl_1284_configbus1[1284:1284] = sram_blwl_wl[1284:1284] ; -assign sram_blwl_1284_configbus0_b[1284:1284] = sram_blwl_blb[1284:1284] ; -sram6T_blwl sram_blwl_1284_ (sram_blwl_out[1284], sram_blwl_out[1284], sram_blwl_outb[1284], sram_blwl_1284_configbus0[1284:1284], sram_blwl_1284_configbus1[1284:1284] , sram_blwl_1284_configbus0_b[1284:1284] ); -wire [1285:1285] sram_blwl_1285_configbus0; -wire [1285:1285] sram_blwl_1285_configbus1; -wire [1285:1285] sram_blwl_1285_configbus0_b; -assign sram_blwl_1285_configbus0[1285:1285] = sram_blwl_bl[1285:1285] ; -assign sram_blwl_1285_configbus1[1285:1285] = sram_blwl_wl[1285:1285] ; -assign sram_blwl_1285_configbus0_b[1285:1285] = sram_blwl_blb[1285:1285] ; -sram6T_blwl sram_blwl_1285_ (sram_blwl_out[1285], sram_blwl_out[1285], sram_blwl_outb[1285], sram_blwl_1285_configbus0[1285:1285], sram_blwl_1285_configbus1[1285:1285] , sram_blwl_1285_configbus0_b[1285:1285] ); -wire [1286:1286] sram_blwl_1286_configbus0; -wire [1286:1286] sram_blwl_1286_configbus1; -wire [1286:1286] sram_blwl_1286_configbus0_b; -assign sram_blwl_1286_configbus0[1286:1286] = sram_blwl_bl[1286:1286] ; -assign sram_blwl_1286_configbus1[1286:1286] = sram_blwl_wl[1286:1286] ; -assign sram_blwl_1286_configbus0_b[1286:1286] = sram_blwl_blb[1286:1286] ; -sram6T_blwl sram_blwl_1286_ (sram_blwl_out[1286], sram_blwl_out[1286], sram_blwl_outb[1286], sram_blwl_1286_configbus0[1286:1286], sram_blwl_1286_configbus1[1286:1286] , sram_blwl_1286_configbus0_b[1286:1286] ); -wire [1287:1287] sram_blwl_1287_configbus0; -wire [1287:1287] sram_blwl_1287_configbus1; -wire [1287:1287] sram_blwl_1287_configbus0_b; -assign sram_blwl_1287_configbus0[1287:1287] = sram_blwl_bl[1287:1287] ; -assign sram_blwl_1287_configbus1[1287:1287] = sram_blwl_wl[1287:1287] ; -assign sram_blwl_1287_configbus0_b[1287:1287] = sram_blwl_blb[1287:1287] ; -sram6T_blwl sram_blwl_1287_ (sram_blwl_out[1287], sram_blwl_out[1287], sram_blwl_outb[1287], sram_blwl_1287_configbus0[1287:1287], sram_blwl_1287_configbus1[1287:1287] , sram_blwl_1287_configbus0_b[1287:1287] ); -wire [1288:1288] sram_blwl_1288_configbus0; -wire [1288:1288] sram_blwl_1288_configbus1; -wire [1288:1288] sram_blwl_1288_configbus0_b; -assign sram_blwl_1288_configbus0[1288:1288] = sram_blwl_bl[1288:1288] ; -assign sram_blwl_1288_configbus1[1288:1288] = sram_blwl_wl[1288:1288] ; -assign sram_blwl_1288_configbus0_b[1288:1288] = sram_blwl_blb[1288:1288] ; -sram6T_blwl sram_blwl_1288_ (sram_blwl_out[1288], sram_blwl_out[1288], sram_blwl_outb[1288], sram_blwl_1288_configbus0[1288:1288], sram_blwl_1288_configbus1[1288:1288] , sram_blwl_1288_configbus0_b[1288:1288] ); -wire [1289:1289] sram_blwl_1289_configbus0; -wire [1289:1289] sram_blwl_1289_configbus1; -wire [1289:1289] sram_blwl_1289_configbus0_b; -assign sram_blwl_1289_configbus0[1289:1289] = sram_blwl_bl[1289:1289] ; -assign sram_blwl_1289_configbus1[1289:1289] = sram_blwl_wl[1289:1289] ; -assign sram_blwl_1289_configbus0_b[1289:1289] = sram_blwl_blb[1289:1289] ; -sram6T_blwl sram_blwl_1289_ (sram_blwl_out[1289], sram_blwl_out[1289], sram_blwl_outb[1289], sram_blwl_1289_configbus0[1289:1289], sram_blwl_1289_configbus1[1289:1289] , sram_blwl_1289_configbus0_b[1289:1289] ); -wire [1290:1290] sram_blwl_1290_configbus0; -wire [1290:1290] sram_blwl_1290_configbus1; -wire [1290:1290] sram_blwl_1290_configbus0_b; -assign sram_blwl_1290_configbus0[1290:1290] = sram_blwl_bl[1290:1290] ; -assign sram_blwl_1290_configbus1[1290:1290] = sram_blwl_wl[1290:1290] ; -assign sram_blwl_1290_configbus0_b[1290:1290] = sram_blwl_blb[1290:1290] ; -sram6T_blwl sram_blwl_1290_ (sram_blwl_out[1290], sram_blwl_out[1290], sram_blwl_outb[1290], sram_blwl_1290_configbus0[1290:1290], sram_blwl_1290_configbus1[1290:1290] , sram_blwl_1290_configbus0_b[1290:1290] ); -wire [1291:1291] sram_blwl_1291_configbus0; -wire [1291:1291] sram_blwl_1291_configbus1; -wire [1291:1291] sram_blwl_1291_configbus0_b; -assign sram_blwl_1291_configbus0[1291:1291] = sram_blwl_bl[1291:1291] ; -assign sram_blwl_1291_configbus1[1291:1291] = sram_blwl_wl[1291:1291] ; -assign sram_blwl_1291_configbus0_b[1291:1291] = sram_blwl_blb[1291:1291] ; -sram6T_blwl sram_blwl_1291_ (sram_blwl_out[1291], sram_blwl_out[1291], sram_blwl_outb[1291], sram_blwl_1291_configbus0[1291:1291], sram_blwl_1291_configbus1[1291:1291] , sram_blwl_1291_configbus0_b[1291:1291] ); -wire [1292:1292] sram_blwl_1292_configbus0; -wire [1292:1292] sram_blwl_1292_configbus1; -wire [1292:1292] sram_blwl_1292_configbus0_b; -assign sram_blwl_1292_configbus0[1292:1292] = sram_blwl_bl[1292:1292] ; -assign sram_blwl_1292_configbus1[1292:1292] = sram_blwl_wl[1292:1292] ; -assign sram_blwl_1292_configbus0_b[1292:1292] = sram_blwl_blb[1292:1292] ; -sram6T_blwl sram_blwl_1292_ (sram_blwl_out[1292], sram_blwl_out[1292], sram_blwl_outb[1292], sram_blwl_1292_configbus0[1292:1292], sram_blwl_1292_configbus1[1292:1292] , sram_blwl_1292_configbus0_b[1292:1292] ); -wire [1293:1293] sram_blwl_1293_configbus0; -wire [1293:1293] sram_blwl_1293_configbus1; -wire [1293:1293] sram_blwl_1293_configbus0_b; -assign sram_blwl_1293_configbus0[1293:1293] = sram_blwl_bl[1293:1293] ; -assign sram_blwl_1293_configbus1[1293:1293] = sram_blwl_wl[1293:1293] ; -assign sram_blwl_1293_configbus0_b[1293:1293] = sram_blwl_blb[1293:1293] ; -sram6T_blwl sram_blwl_1293_ (sram_blwl_out[1293], sram_blwl_out[1293], sram_blwl_outb[1293], sram_blwl_1293_configbus0[1293:1293], sram_blwl_1293_configbus1[1293:1293] , sram_blwl_1293_configbus0_b[1293:1293] ); -wire [1294:1294] sram_blwl_1294_configbus0; -wire [1294:1294] sram_blwl_1294_configbus1; -wire [1294:1294] sram_blwl_1294_configbus0_b; -assign sram_blwl_1294_configbus0[1294:1294] = sram_blwl_bl[1294:1294] ; -assign sram_blwl_1294_configbus1[1294:1294] = sram_blwl_wl[1294:1294] ; -assign sram_blwl_1294_configbus0_b[1294:1294] = sram_blwl_blb[1294:1294] ; -sram6T_blwl sram_blwl_1294_ (sram_blwl_out[1294], sram_blwl_out[1294], sram_blwl_outb[1294], sram_blwl_1294_configbus0[1294:1294], sram_blwl_1294_configbus1[1294:1294] , sram_blwl_1294_configbus0_b[1294:1294] ); -wire [1295:1295] sram_blwl_1295_configbus0; -wire [1295:1295] sram_blwl_1295_configbus1; -wire [1295:1295] sram_blwl_1295_configbus0_b; -assign sram_blwl_1295_configbus0[1295:1295] = sram_blwl_bl[1295:1295] ; -assign sram_blwl_1295_configbus1[1295:1295] = sram_blwl_wl[1295:1295] ; -assign sram_blwl_1295_configbus0_b[1295:1295] = sram_blwl_blb[1295:1295] ; -sram6T_blwl sram_blwl_1295_ (sram_blwl_out[1295], sram_blwl_out[1295], sram_blwl_outb[1295], sram_blwl_1295_configbus0[1295:1295], sram_blwl_1295_configbus1[1295:1295] , sram_blwl_1295_configbus0_b[1295:1295] ); -wire [1296:1296] sram_blwl_1296_configbus0; -wire [1296:1296] sram_blwl_1296_configbus1; -wire [1296:1296] sram_blwl_1296_configbus0_b; -assign sram_blwl_1296_configbus0[1296:1296] = sram_blwl_bl[1296:1296] ; -assign sram_blwl_1296_configbus1[1296:1296] = sram_blwl_wl[1296:1296] ; -assign sram_blwl_1296_configbus0_b[1296:1296] = sram_blwl_blb[1296:1296] ; -sram6T_blwl sram_blwl_1296_ (sram_blwl_out[1296], sram_blwl_out[1296], sram_blwl_outb[1296], sram_blwl_1296_configbus0[1296:1296], sram_blwl_1296_configbus1[1296:1296] , sram_blwl_1296_configbus0_b[1296:1296] ); -wire [1297:1297] sram_blwl_1297_configbus0; -wire [1297:1297] sram_blwl_1297_configbus1; -wire [1297:1297] sram_blwl_1297_configbus0_b; -assign sram_blwl_1297_configbus0[1297:1297] = sram_blwl_bl[1297:1297] ; -assign sram_blwl_1297_configbus1[1297:1297] = sram_blwl_wl[1297:1297] ; -assign sram_blwl_1297_configbus0_b[1297:1297] = sram_blwl_blb[1297:1297] ; -sram6T_blwl sram_blwl_1297_ (sram_blwl_out[1297], sram_blwl_out[1297], sram_blwl_outb[1297], sram_blwl_1297_configbus0[1297:1297], sram_blwl_1297_configbus1[1297:1297] , sram_blwl_1297_configbus0_b[1297:1297] ); -wire [1298:1298] sram_blwl_1298_configbus0; -wire [1298:1298] sram_blwl_1298_configbus1; -wire [1298:1298] sram_blwl_1298_configbus0_b; -assign sram_blwl_1298_configbus0[1298:1298] = sram_blwl_bl[1298:1298] ; -assign sram_blwl_1298_configbus1[1298:1298] = sram_blwl_wl[1298:1298] ; -assign sram_blwl_1298_configbus0_b[1298:1298] = sram_blwl_blb[1298:1298] ; -sram6T_blwl sram_blwl_1298_ (sram_blwl_out[1298], sram_blwl_out[1298], sram_blwl_outb[1298], sram_blwl_1298_configbus0[1298:1298], sram_blwl_1298_configbus1[1298:1298] , sram_blwl_1298_configbus0_b[1298:1298] ); -wire [1299:1299] sram_blwl_1299_configbus0; -wire [1299:1299] sram_blwl_1299_configbus1; -wire [1299:1299] sram_blwl_1299_configbus0_b; -assign sram_blwl_1299_configbus0[1299:1299] = sram_blwl_bl[1299:1299] ; -assign sram_blwl_1299_configbus1[1299:1299] = sram_blwl_wl[1299:1299] ; -assign sram_blwl_1299_configbus0_b[1299:1299] = sram_blwl_blb[1299:1299] ; -sram6T_blwl sram_blwl_1299_ (sram_blwl_out[1299], sram_blwl_out[1299], sram_blwl_outb[1299], sram_blwl_1299_configbus0[1299:1299], sram_blwl_1299_configbus1[1299:1299] , sram_blwl_1299_configbus0_b[1299:1299] ); -wire [1300:1300] sram_blwl_1300_configbus0; -wire [1300:1300] sram_blwl_1300_configbus1; -wire [1300:1300] sram_blwl_1300_configbus0_b; -assign sram_blwl_1300_configbus0[1300:1300] = sram_blwl_bl[1300:1300] ; -assign sram_blwl_1300_configbus1[1300:1300] = sram_blwl_wl[1300:1300] ; -assign sram_blwl_1300_configbus0_b[1300:1300] = sram_blwl_blb[1300:1300] ; -sram6T_blwl sram_blwl_1300_ (sram_blwl_out[1300], sram_blwl_out[1300], sram_blwl_outb[1300], sram_blwl_1300_configbus0[1300:1300], sram_blwl_1300_configbus1[1300:1300] , sram_blwl_1300_configbus0_b[1300:1300] ); -wire [1301:1301] sram_blwl_1301_configbus0; -wire [1301:1301] sram_blwl_1301_configbus1; -wire [1301:1301] sram_blwl_1301_configbus0_b; -assign sram_blwl_1301_configbus0[1301:1301] = sram_blwl_bl[1301:1301] ; -assign sram_blwl_1301_configbus1[1301:1301] = sram_blwl_wl[1301:1301] ; -assign sram_blwl_1301_configbus0_b[1301:1301] = sram_blwl_blb[1301:1301] ; -sram6T_blwl sram_blwl_1301_ (sram_blwl_out[1301], sram_blwl_out[1301], sram_blwl_outb[1301], sram_blwl_1301_configbus0[1301:1301], sram_blwl_1301_configbus1[1301:1301] , sram_blwl_1301_configbus0_b[1301:1301] ); -wire [1302:1302] sram_blwl_1302_configbus0; -wire [1302:1302] sram_blwl_1302_configbus1; -wire [1302:1302] sram_blwl_1302_configbus0_b; -assign sram_blwl_1302_configbus0[1302:1302] = sram_blwl_bl[1302:1302] ; -assign sram_blwl_1302_configbus1[1302:1302] = sram_blwl_wl[1302:1302] ; -assign sram_blwl_1302_configbus0_b[1302:1302] = sram_blwl_blb[1302:1302] ; -sram6T_blwl sram_blwl_1302_ (sram_blwl_out[1302], sram_blwl_out[1302], sram_blwl_outb[1302], sram_blwl_1302_configbus0[1302:1302], sram_blwl_1302_configbus1[1302:1302] , sram_blwl_1302_configbus0_b[1302:1302] ); -wire [1303:1303] sram_blwl_1303_configbus0; -wire [1303:1303] sram_blwl_1303_configbus1; -wire [1303:1303] sram_blwl_1303_configbus0_b; -assign sram_blwl_1303_configbus0[1303:1303] = sram_blwl_bl[1303:1303] ; -assign sram_blwl_1303_configbus1[1303:1303] = sram_blwl_wl[1303:1303] ; -assign sram_blwl_1303_configbus0_b[1303:1303] = sram_blwl_blb[1303:1303] ; -sram6T_blwl sram_blwl_1303_ (sram_blwl_out[1303], sram_blwl_out[1303], sram_blwl_outb[1303], sram_blwl_1303_configbus0[1303:1303], sram_blwl_1303_configbus1[1303:1303] , sram_blwl_1303_configbus0_b[1303:1303] ); -wire [1304:1304] sram_blwl_1304_configbus0; -wire [1304:1304] sram_blwl_1304_configbus1; -wire [1304:1304] sram_blwl_1304_configbus0_b; -assign sram_blwl_1304_configbus0[1304:1304] = sram_blwl_bl[1304:1304] ; -assign sram_blwl_1304_configbus1[1304:1304] = sram_blwl_wl[1304:1304] ; -assign sram_blwl_1304_configbus0_b[1304:1304] = sram_blwl_blb[1304:1304] ; -sram6T_blwl sram_blwl_1304_ (sram_blwl_out[1304], sram_blwl_out[1304], sram_blwl_outb[1304], sram_blwl_1304_configbus0[1304:1304], sram_blwl_1304_configbus1[1304:1304] , sram_blwl_1304_configbus0_b[1304:1304] ); -wire [1305:1305] sram_blwl_1305_configbus0; -wire [1305:1305] sram_blwl_1305_configbus1; -wire [1305:1305] sram_blwl_1305_configbus0_b; -assign sram_blwl_1305_configbus0[1305:1305] = sram_blwl_bl[1305:1305] ; -assign sram_blwl_1305_configbus1[1305:1305] = sram_blwl_wl[1305:1305] ; -assign sram_blwl_1305_configbus0_b[1305:1305] = sram_blwl_blb[1305:1305] ; -sram6T_blwl sram_blwl_1305_ (sram_blwl_out[1305], sram_blwl_out[1305], sram_blwl_outb[1305], sram_blwl_1305_configbus0[1305:1305], sram_blwl_1305_configbus1[1305:1305] , sram_blwl_1305_configbus0_b[1305:1305] ); -wire [1306:1306] sram_blwl_1306_configbus0; -wire [1306:1306] sram_blwl_1306_configbus1; -wire [1306:1306] sram_blwl_1306_configbus0_b; -assign sram_blwl_1306_configbus0[1306:1306] = sram_blwl_bl[1306:1306] ; -assign sram_blwl_1306_configbus1[1306:1306] = sram_blwl_wl[1306:1306] ; -assign sram_blwl_1306_configbus0_b[1306:1306] = sram_blwl_blb[1306:1306] ; -sram6T_blwl sram_blwl_1306_ (sram_blwl_out[1306], sram_blwl_out[1306], sram_blwl_outb[1306], sram_blwl_1306_configbus0[1306:1306], sram_blwl_1306_configbus1[1306:1306] , sram_blwl_1306_configbus0_b[1306:1306] ); -wire [1307:1307] sram_blwl_1307_configbus0; -wire [1307:1307] sram_blwl_1307_configbus1; -wire [1307:1307] sram_blwl_1307_configbus0_b; -assign sram_blwl_1307_configbus0[1307:1307] = sram_blwl_bl[1307:1307] ; -assign sram_blwl_1307_configbus1[1307:1307] = sram_blwl_wl[1307:1307] ; -assign sram_blwl_1307_configbus0_b[1307:1307] = sram_blwl_blb[1307:1307] ; -sram6T_blwl sram_blwl_1307_ (sram_blwl_out[1307], sram_blwl_out[1307], sram_blwl_outb[1307], sram_blwl_1307_configbus0[1307:1307], sram_blwl_1307_configbus1[1307:1307] , sram_blwl_1307_configbus0_b[1307:1307] ); -wire [1308:1308] sram_blwl_1308_configbus0; -wire [1308:1308] sram_blwl_1308_configbus1; -wire [1308:1308] sram_blwl_1308_configbus0_b; -assign sram_blwl_1308_configbus0[1308:1308] = sram_blwl_bl[1308:1308] ; -assign sram_blwl_1308_configbus1[1308:1308] = sram_blwl_wl[1308:1308] ; -assign sram_blwl_1308_configbus0_b[1308:1308] = sram_blwl_blb[1308:1308] ; -sram6T_blwl sram_blwl_1308_ (sram_blwl_out[1308], sram_blwl_out[1308], sram_blwl_outb[1308], sram_blwl_1308_configbus0[1308:1308], sram_blwl_1308_configbus1[1308:1308] , sram_blwl_1308_configbus0_b[1308:1308] ); -wire [1309:1309] sram_blwl_1309_configbus0; -wire [1309:1309] sram_blwl_1309_configbus1; -wire [1309:1309] sram_blwl_1309_configbus0_b; -assign sram_blwl_1309_configbus0[1309:1309] = sram_blwl_bl[1309:1309] ; -assign sram_blwl_1309_configbus1[1309:1309] = sram_blwl_wl[1309:1309] ; -assign sram_blwl_1309_configbus0_b[1309:1309] = sram_blwl_blb[1309:1309] ; -sram6T_blwl sram_blwl_1309_ (sram_blwl_out[1309], sram_blwl_out[1309], sram_blwl_outb[1309], sram_blwl_1309_configbus0[1309:1309], sram_blwl_1309_configbus1[1309:1309] , sram_blwl_1309_configbus0_b[1309:1309] ); -wire [1310:1310] sram_blwl_1310_configbus0; -wire [1310:1310] sram_blwl_1310_configbus1; -wire [1310:1310] sram_blwl_1310_configbus0_b; -assign sram_blwl_1310_configbus0[1310:1310] = sram_blwl_bl[1310:1310] ; -assign sram_blwl_1310_configbus1[1310:1310] = sram_blwl_wl[1310:1310] ; -assign sram_blwl_1310_configbus0_b[1310:1310] = sram_blwl_blb[1310:1310] ; -sram6T_blwl sram_blwl_1310_ (sram_blwl_out[1310], sram_blwl_out[1310], sram_blwl_outb[1310], sram_blwl_1310_configbus0[1310:1310], sram_blwl_1310_configbus1[1310:1310] , sram_blwl_1310_configbus0_b[1310:1310] ); -wire [1311:1311] sram_blwl_1311_configbus0; -wire [1311:1311] sram_blwl_1311_configbus1; -wire [1311:1311] sram_blwl_1311_configbus0_b; -assign sram_blwl_1311_configbus0[1311:1311] = sram_blwl_bl[1311:1311] ; -assign sram_blwl_1311_configbus1[1311:1311] = sram_blwl_wl[1311:1311] ; -assign sram_blwl_1311_configbus0_b[1311:1311] = sram_blwl_blb[1311:1311] ; -sram6T_blwl sram_blwl_1311_ (sram_blwl_out[1311], sram_blwl_out[1311], sram_blwl_outb[1311], sram_blwl_1311_configbus0[1311:1311], sram_blwl_1311_configbus1[1311:1311] , sram_blwl_1311_configbus0_b[1311:1311] ); -wire [1312:1312] sram_blwl_1312_configbus0; -wire [1312:1312] sram_blwl_1312_configbus1; -wire [1312:1312] sram_blwl_1312_configbus0_b; -assign sram_blwl_1312_configbus0[1312:1312] = sram_blwl_bl[1312:1312] ; -assign sram_blwl_1312_configbus1[1312:1312] = sram_blwl_wl[1312:1312] ; -assign sram_blwl_1312_configbus0_b[1312:1312] = sram_blwl_blb[1312:1312] ; -sram6T_blwl sram_blwl_1312_ (sram_blwl_out[1312], sram_blwl_out[1312], sram_blwl_outb[1312], sram_blwl_1312_configbus0[1312:1312], sram_blwl_1312_configbus1[1312:1312] , sram_blwl_1312_configbus0_b[1312:1312] ); -wire [1313:1313] sram_blwl_1313_configbus0; -wire [1313:1313] sram_blwl_1313_configbus1; -wire [1313:1313] sram_blwl_1313_configbus0_b; -assign sram_blwl_1313_configbus0[1313:1313] = sram_blwl_bl[1313:1313] ; -assign sram_blwl_1313_configbus1[1313:1313] = sram_blwl_wl[1313:1313] ; -assign sram_blwl_1313_configbus0_b[1313:1313] = sram_blwl_blb[1313:1313] ; -sram6T_blwl sram_blwl_1313_ (sram_blwl_out[1313], sram_blwl_out[1313], sram_blwl_outb[1313], sram_blwl_1313_configbus0[1313:1313], sram_blwl_1313_configbus1[1313:1313] , sram_blwl_1313_configbus0_b[1313:1313] ); -wire [1314:1314] sram_blwl_1314_configbus0; -wire [1314:1314] sram_blwl_1314_configbus1; -wire [1314:1314] sram_blwl_1314_configbus0_b; -assign sram_blwl_1314_configbus0[1314:1314] = sram_blwl_bl[1314:1314] ; -assign sram_blwl_1314_configbus1[1314:1314] = sram_blwl_wl[1314:1314] ; -assign sram_blwl_1314_configbus0_b[1314:1314] = sram_blwl_blb[1314:1314] ; -sram6T_blwl sram_blwl_1314_ (sram_blwl_out[1314], sram_blwl_out[1314], sram_blwl_outb[1314], sram_blwl_1314_configbus0[1314:1314], sram_blwl_1314_configbus1[1314:1314] , sram_blwl_1314_configbus0_b[1314:1314] ); -wire [1315:1315] sram_blwl_1315_configbus0; -wire [1315:1315] sram_blwl_1315_configbus1; -wire [1315:1315] sram_blwl_1315_configbus0_b; -assign sram_blwl_1315_configbus0[1315:1315] = sram_blwl_bl[1315:1315] ; -assign sram_blwl_1315_configbus1[1315:1315] = sram_blwl_wl[1315:1315] ; -assign sram_blwl_1315_configbus0_b[1315:1315] = sram_blwl_blb[1315:1315] ; -sram6T_blwl sram_blwl_1315_ (sram_blwl_out[1315], sram_blwl_out[1315], sram_blwl_outb[1315], sram_blwl_1315_configbus0[1315:1315], sram_blwl_1315_configbus1[1315:1315] , sram_blwl_1315_configbus0_b[1315:1315] ); -wire [1316:1316] sram_blwl_1316_configbus0; -wire [1316:1316] sram_blwl_1316_configbus1; -wire [1316:1316] sram_blwl_1316_configbus0_b; -assign sram_blwl_1316_configbus0[1316:1316] = sram_blwl_bl[1316:1316] ; -assign sram_blwl_1316_configbus1[1316:1316] = sram_blwl_wl[1316:1316] ; -assign sram_blwl_1316_configbus0_b[1316:1316] = sram_blwl_blb[1316:1316] ; -sram6T_blwl sram_blwl_1316_ (sram_blwl_out[1316], sram_blwl_out[1316], sram_blwl_outb[1316], sram_blwl_1316_configbus0[1316:1316], sram_blwl_1316_configbus1[1316:1316] , sram_blwl_1316_configbus0_b[1316:1316] ); -wire [1317:1317] sram_blwl_1317_configbus0; -wire [1317:1317] sram_blwl_1317_configbus1; -wire [1317:1317] sram_blwl_1317_configbus0_b; -assign sram_blwl_1317_configbus0[1317:1317] = sram_blwl_bl[1317:1317] ; -assign sram_blwl_1317_configbus1[1317:1317] = sram_blwl_wl[1317:1317] ; -assign sram_blwl_1317_configbus0_b[1317:1317] = sram_blwl_blb[1317:1317] ; -sram6T_blwl sram_blwl_1317_ (sram_blwl_out[1317], sram_blwl_out[1317], sram_blwl_outb[1317], sram_blwl_1317_configbus0[1317:1317], sram_blwl_1317_configbus1[1317:1317] , sram_blwl_1317_configbus0_b[1317:1317] ); -wire [1318:1318] sram_blwl_1318_configbus0; -wire [1318:1318] sram_blwl_1318_configbus1; -wire [1318:1318] sram_blwl_1318_configbus0_b; -assign sram_blwl_1318_configbus0[1318:1318] = sram_blwl_bl[1318:1318] ; -assign sram_blwl_1318_configbus1[1318:1318] = sram_blwl_wl[1318:1318] ; -assign sram_blwl_1318_configbus0_b[1318:1318] = sram_blwl_blb[1318:1318] ; -sram6T_blwl sram_blwl_1318_ (sram_blwl_out[1318], sram_blwl_out[1318], sram_blwl_outb[1318], sram_blwl_1318_configbus0[1318:1318], sram_blwl_1318_configbus1[1318:1318] , sram_blwl_1318_configbus0_b[1318:1318] ); -wire [1319:1319] sram_blwl_1319_configbus0; -wire [1319:1319] sram_blwl_1319_configbus1; -wire [1319:1319] sram_blwl_1319_configbus0_b; -assign sram_blwl_1319_configbus0[1319:1319] = sram_blwl_bl[1319:1319] ; -assign sram_blwl_1319_configbus1[1319:1319] = sram_blwl_wl[1319:1319] ; -assign sram_blwl_1319_configbus0_b[1319:1319] = sram_blwl_blb[1319:1319] ; -sram6T_blwl sram_blwl_1319_ (sram_blwl_out[1319], sram_blwl_out[1319], sram_blwl_outb[1319], sram_blwl_1319_configbus0[1319:1319], sram_blwl_1319_configbus1[1319:1319] , sram_blwl_1319_configbus0_b[1319:1319] ); -wire [1320:1320] sram_blwl_1320_configbus0; -wire [1320:1320] sram_blwl_1320_configbus1; -wire [1320:1320] sram_blwl_1320_configbus0_b; -assign sram_blwl_1320_configbus0[1320:1320] = sram_blwl_bl[1320:1320] ; -assign sram_blwl_1320_configbus1[1320:1320] = sram_blwl_wl[1320:1320] ; -assign sram_blwl_1320_configbus0_b[1320:1320] = sram_blwl_blb[1320:1320] ; -sram6T_blwl sram_blwl_1320_ (sram_blwl_out[1320], sram_blwl_out[1320], sram_blwl_outb[1320], sram_blwl_1320_configbus0[1320:1320], sram_blwl_1320_configbus1[1320:1320] , sram_blwl_1320_configbus0_b[1320:1320] ); -wire [1321:1321] sram_blwl_1321_configbus0; -wire [1321:1321] sram_blwl_1321_configbus1; -wire [1321:1321] sram_blwl_1321_configbus0_b; -assign sram_blwl_1321_configbus0[1321:1321] = sram_blwl_bl[1321:1321] ; -assign sram_blwl_1321_configbus1[1321:1321] = sram_blwl_wl[1321:1321] ; -assign sram_blwl_1321_configbus0_b[1321:1321] = sram_blwl_blb[1321:1321] ; -sram6T_blwl sram_blwl_1321_ (sram_blwl_out[1321], sram_blwl_out[1321], sram_blwl_outb[1321], sram_blwl_1321_configbus0[1321:1321], sram_blwl_1321_configbus1[1321:1321] , sram_blwl_1321_configbus0_b[1321:1321] ); -wire [1322:1322] sram_blwl_1322_configbus0; -wire [1322:1322] sram_blwl_1322_configbus1; -wire [1322:1322] sram_blwl_1322_configbus0_b; -assign sram_blwl_1322_configbus0[1322:1322] = sram_blwl_bl[1322:1322] ; -assign sram_blwl_1322_configbus1[1322:1322] = sram_blwl_wl[1322:1322] ; -assign sram_blwl_1322_configbus0_b[1322:1322] = sram_blwl_blb[1322:1322] ; -sram6T_blwl sram_blwl_1322_ (sram_blwl_out[1322], sram_blwl_out[1322], sram_blwl_outb[1322], sram_blwl_1322_configbus0[1322:1322], sram_blwl_1322_configbus1[1322:1322] , sram_blwl_1322_configbus0_b[1322:1322] ); -wire [1323:1323] sram_blwl_1323_configbus0; -wire [1323:1323] sram_blwl_1323_configbus1; -wire [1323:1323] sram_blwl_1323_configbus0_b; -assign sram_blwl_1323_configbus0[1323:1323] = sram_blwl_bl[1323:1323] ; -assign sram_blwl_1323_configbus1[1323:1323] = sram_blwl_wl[1323:1323] ; -assign sram_blwl_1323_configbus0_b[1323:1323] = sram_blwl_blb[1323:1323] ; -sram6T_blwl sram_blwl_1323_ (sram_blwl_out[1323], sram_blwl_out[1323], sram_blwl_outb[1323], sram_blwl_1323_configbus0[1323:1323], sram_blwl_1323_configbus1[1323:1323] , sram_blwl_1323_configbus0_b[1323:1323] ); -wire [1324:1324] sram_blwl_1324_configbus0; -wire [1324:1324] sram_blwl_1324_configbus1; -wire [1324:1324] sram_blwl_1324_configbus0_b; -assign sram_blwl_1324_configbus0[1324:1324] = sram_blwl_bl[1324:1324] ; -assign sram_blwl_1324_configbus1[1324:1324] = sram_blwl_wl[1324:1324] ; -assign sram_blwl_1324_configbus0_b[1324:1324] = sram_blwl_blb[1324:1324] ; -sram6T_blwl sram_blwl_1324_ (sram_blwl_out[1324], sram_blwl_out[1324], sram_blwl_outb[1324], sram_blwl_1324_configbus0[1324:1324], sram_blwl_1324_configbus1[1324:1324] , sram_blwl_1324_configbus0_b[1324:1324] ); -wire [1325:1325] sram_blwl_1325_configbus0; -wire [1325:1325] sram_blwl_1325_configbus1; -wire [1325:1325] sram_blwl_1325_configbus0_b; -assign sram_blwl_1325_configbus0[1325:1325] = sram_blwl_bl[1325:1325] ; -assign sram_blwl_1325_configbus1[1325:1325] = sram_blwl_wl[1325:1325] ; -assign sram_blwl_1325_configbus0_b[1325:1325] = sram_blwl_blb[1325:1325] ; -sram6T_blwl sram_blwl_1325_ (sram_blwl_out[1325], sram_blwl_out[1325], sram_blwl_outb[1325], sram_blwl_1325_configbus0[1325:1325], sram_blwl_1325_configbus1[1325:1325] , sram_blwl_1325_configbus0_b[1325:1325] ); -wire [1326:1326] sram_blwl_1326_configbus0; -wire [1326:1326] sram_blwl_1326_configbus1; -wire [1326:1326] sram_blwl_1326_configbus0_b; -assign sram_blwl_1326_configbus0[1326:1326] = sram_blwl_bl[1326:1326] ; -assign sram_blwl_1326_configbus1[1326:1326] = sram_blwl_wl[1326:1326] ; -assign sram_blwl_1326_configbus0_b[1326:1326] = sram_blwl_blb[1326:1326] ; -sram6T_blwl sram_blwl_1326_ (sram_blwl_out[1326], sram_blwl_out[1326], sram_blwl_outb[1326], sram_blwl_1326_configbus0[1326:1326], sram_blwl_1326_configbus1[1326:1326] , sram_blwl_1326_configbus0_b[1326:1326] ); -wire [1327:1327] sram_blwl_1327_configbus0; -wire [1327:1327] sram_blwl_1327_configbus1; -wire [1327:1327] sram_blwl_1327_configbus0_b; -assign sram_blwl_1327_configbus0[1327:1327] = sram_blwl_bl[1327:1327] ; -assign sram_blwl_1327_configbus1[1327:1327] = sram_blwl_wl[1327:1327] ; -assign sram_blwl_1327_configbus0_b[1327:1327] = sram_blwl_blb[1327:1327] ; -sram6T_blwl sram_blwl_1327_ (sram_blwl_out[1327], sram_blwl_out[1327], sram_blwl_outb[1327], sram_blwl_1327_configbus0[1327:1327], sram_blwl_1327_configbus1[1327:1327] , sram_blwl_1327_configbus0_b[1327:1327] ); -wire [1328:1328] sram_blwl_1328_configbus0; -wire [1328:1328] sram_blwl_1328_configbus1; -wire [1328:1328] sram_blwl_1328_configbus0_b; -assign sram_blwl_1328_configbus0[1328:1328] = sram_blwl_bl[1328:1328] ; -assign sram_blwl_1328_configbus1[1328:1328] = sram_blwl_wl[1328:1328] ; -assign sram_blwl_1328_configbus0_b[1328:1328] = sram_blwl_blb[1328:1328] ; -sram6T_blwl sram_blwl_1328_ (sram_blwl_out[1328], sram_blwl_out[1328], sram_blwl_outb[1328], sram_blwl_1328_configbus0[1328:1328], sram_blwl_1328_configbus1[1328:1328] , sram_blwl_1328_configbus0_b[1328:1328] ); -wire [1329:1329] sram_blwl_1329_configbus0; -wire [1329:1329] sram_blwl_1329_configbus1; -wire [1329:1329] sram_blwl_1329_configbus0_b; -assign sram_blwl_1329_configbus0[1329:1329] = sram_blwl_bl[1329:1329] ; -assign sram_blwl_1329_configbus1[1329:1329] = sram_blwl_wl[1329:1329] ; -assign sram_blwl_1329_configbus0_b[1329:1329] = sram_blwl_blb[1329:1329] ; -sram6T_blwl sram_blwl_1329_ (sram_blwl_out[1329], sram_blwl_out[1329], sram_blwl_outb[1329], sram_blwl_1329_configbus0[1329:1329], sram_blwl_1329_configbus1[1329:1329] , sram_blwl_1329_configbus0_b[1329:1329] ); -wire [1330:1330] sram_blwl_1330_configbus0; -wire [1330:1330] sram_blwl_1330_configbus1; -wire [1330:1330] sram_blwl_1330_configbus0_b; -assign sram_blwl_1330_configbus0[1330:1330] = sram_blwl_bl[1330:1330] ; -assign sram_blwl_1330_configbus1[1330:1330] = sram_blwl_wl[1330:1330] ; -assign sram_blwl_1330_configbus0_b[1330:1330] = sram_blwl_blb[1330:1330] ; -sram6T_blwl sram_blwl_1330_ (sram_blwl_out[1330], sram_blwl_out[1330], sram_blwl_outb[1330], sram_blwl_1330_configbus0[1330:1330], sram_blwl_1330_configbus1[1330:1330] , sram_blwl_1330_configbus0_b[1330:1330] ); -wire [1331:1331] sram_blwl_1331_configbus0; -wire [1331:1331] sram_blwl_1331_configbus1; -wire [1331:1331] sram_blwl_1331_configbus0_b; -assign sram_blwl_1331_configbus0[1331:1331] = sram_blwl_bl[1331:1331] ; -assign sram_blwl_1331_configbus1[1331:1331] = sram_blwl_wl[1331:1331] ; -assign sram_blwl_1331_configbus0_b[1331:1331] = sram_blwl_blb[1331:1331] ; -sram6T_blwl sram_blwl_1331_ (sram_blwl_out[1331], sram_blwl_out[1331], sram_blwl_outb[1331], sram_blwl_1331_configbus0[1331:1331], sram_blwl_1331_configbus1[1331:1331] , sram_blwl_1331_configbus0_b[1331:1331] ); -wire [1332:1332] sram_blwl_1332_configbus0; -wire [1332:1332] sram_blwl_1332_configbus1; -wire [1332:1332] sram_blwl_1332_configbus0_b; -assign sram_blwl_1332_configbus0[1332:1332] = sram_blwl_bl[1332:1332] ; -assign sram_blwl_1332_configbus1[1332:1332] = sram_blwl_wl[1332:1332] ; -assign sram_blwl_1332_configbus0_b[1332:1332] = sram_blwl_blb[1332:1332] ; -sram6T_blwl sram_blwl_1332_ (sram_blwl_out[1332], sram_blwl_out[1332], sram_blwl_outb[1332], sram_blwl_1332_configbus0[1332:1332], sram_blwl_1332_configbus1[1332:1332] , sram_blwl_1332_configbus0_b[1332:1332] ); -wire [1333:1333] sram_blwl_1333_configbus0; -wire [1333:1333] sram_blwl_1333_configbus1; -wire [1333:1333] sram_blwl_1333_configbus0_b; -assign sram_blwl_1333_configbus0[1333:1333] = sram_blwl_bl[1333:1333] ; -assign sram_blwl_1333_configbus1[1333:1333] = sram_blwl_wl[1333:1333] ; -assign sram_blwl_1333_configbus0_b[1333:1333] = sram_blwl_blb[1333:1333] ; -sram6T_blwl sram_blwl_1333_ (sram_blwl_out[1333], sram_blwl_out[1333], sram_blwl_outb[1333], sram_blwl_1333_configbus0[1333:1333], sram_blwl_1333_configbus1[1333:1333] , sram_blwl_1333_configbus0_b[1333:1333] ); -wire [1334:1334] sram_blwl_1334_configbus0; -wire [1334:1334] sram_blwl_1334_configbus1; -wire [1334:1334] sram_blwl_1334_configbus0_b; -assign sram_blwl_1334_configbus0[1334:1334] = sram_blwl_bl[1334:1334] ; -assign sram_blwl_1334_configbus1[1334:1334] = sram_blwl_wl[1334:1334] ; -assign sram_blwl_1334_configbus0_b[1334:1334] = sram_blwl_blb[1334:1334] ; -sram6T_blwl sram_blwl_1334_ (sram_blwl_out[1334], sram_blwl_out[1334], sram_blwl_outb[1334], sram_blwl_1334_configbus0[1334:1334], sram_blwl_1334_configbus1[1334:1334] , sram_blwl_1334_configbus0_b[1334:1334] ); -wire [1335:1335] sram_blwl_1335_configbus0; -wire [1335:1335] sram_blwl_1335_configbus1; -wire [1335:1335] sram_blwl_1335_configbus0_b; -assign sram_blwl_1335_configbus0[1335:1335] = sram_blwl_bl[1335:1335] ; -assign sram_blwl_1335_configbus1[1335:1335] = sram_blwl_wl[1335:1335] ; -assign sram_blwl_1335_configbus0_b[1335:1335] = sram_blwl_blb[1335:1335] ; -sram6T_blwl sram_blwl_1335_ (sram_blwl_out[1335], sram_blwl_out[1335], sram_blwl_outb[1335], sram_blwl_1335_configbus0[1335:1335], sram_blwl_1335_configbus1[1335:1335] , sram_blwl_1335_configbus0_b[1335:1335] ); -wire [1336:1336] sram_blwl_1336_configbus0; -wire [1336:1336] sram_blwl_1336_configbus1; -wire [1336:1336] sram_blwl_1336_configbus0_b; -assign sram_blwl_1336_configbus0[1336:1336] = sram_blwl_bl[1336:1336] ; -assign sram_blwl_1336_configbus1[1336:1336] = sram_blwl_wl[1336:1336] ; -assign sram_blwl_1336_configbus0_b[1336:1336] = sram_blwl_blb[1336:1336] ; -sram6T_blwl sram_blwl_1336_ (sram_blwl_out[1336], sram_blwl_out[1336], sram_blwl_outb[1336], sram_blwl_1336_configbus0[1336:1336], sram_blwl_1336_configbus1[1336:1336] , sram_blwl_1336_configbus0_b[1336:1336] ); -wire [1337:1337] sram_blwl_1337_configbus0; -wire [1337:1337] sram_blwl_1337_configbus1; -wire [1337:1337] sram_blwl_1337_configbus0_b; -assign sram_blwl_1337_configbus0[1337:1337] = sram_blwl_bl[1337:1337] ; -assign sram_blwl_1337_configbus1[1337:1337] = sram_blwl_wl[1337:1337] ; -assign sram_blwl_1337_configbus0_b[1337:1337] = sram_blwl_blb[1337:1337] ; -sram6T_blwl sram_blwl_1337_ (sram_blwl_out[1337], sram_blwl_out[1337], sram_blwl_outb[1337], sram_blwl_1337_configbus0[1337:1337], sram_blwl_1337_configbus1[1337:1337] , sram_blwl_1337_configbus0_b[1337:1337] ); -wire [1338:1338] sram_blwl_1338_configbus0; -wire [1338:1338] sram_blwl_1338_configbus1; -wire [1338:1338] sram_blwl_1338_configbus0_b; -assign sram_blwl_1338_configbus0[1338:1338] = sram_blwl_bl[1338:1338] ; -assign sram_blwl_1338_configbus1[1338:1338] = sram_blwl_wl[1338:1338] ; -assign sram_blwl_1338_configbus0_b[1338:1338] = sram_blwl_blb[1338:1338] ; -sram6T_blwl sram_blwl_1338_ (sram_blwl_out[1338], sram_blwl_out[1338], sram_blwl_outb[1338], sram_blwl_1338_configbus0[1338:1338], sram_blwl_1338_configbus1[1338:1338] , sram_blwl_1338_configbus0_b[1338:1338] ); -wire [1339:1339] sram_blwl_1339_configbus0; -wire [1339:1339] sram_blwl_1339_configbus1; -wire [1339:1339] sram_blwl_1339_configbus0_b; -assign sram_blwl_1339_configbus0[1339:1339] = sram_blwl_bl[1339:1339] ; -assign sram_blwl_1339_configbus1[1339:1339] = sram_blwl_wl[1339:1339] ; -assign sram_blwl_1339_configbus0_b[1339:1339] = sram_blwl_blb[1339:1339] ; -sram6T_blwl sram_blwl_1339_ (sram_blwl_out[1339], sram_blwl_out[1339], sram_blwl_outb[1339], sram_blwl_1339_configbus0[1339:1339], sram_blwl_1339_configbus1[1339:1339] , sram_blwl_1339_configbus0_b[1339:1339] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- - -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_4_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6_ ----- -module grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble6___in_0_, -input wire mode_ble6___in_1_, -input wire mode_ble6___in_2_, -input wire mode_ble6___in_3_, -input wire mode_ble6___in_4_, -input wire mode_ble6___in_5_, -output wire mode_ble6___out_0_, -input wire mode_ble6___clk_0_, -input [1276:1340] sram_blwl_bl , -input [1276:1340] sram_blwl_wl , -input [1276:1340] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ lut6_0_ ( - lut6_0___in_0_, lut6_0___in_1_, lut6_0___in_2_, lut6_0___in_3_, lut6_0___in_4_, lut6_0___in_5_, lut6_0___out_0_, -sram_blwl_bl[1276:1339] , -sram_blwl_wl[1276:1339] , -sram_blwl_blb[1276:1339] ); -grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_404_ ; -assign in_bus_mux_1level_tapbuf_size2_404_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_404_[1] = lut6_0___out_0_ ; -wire [1340:1340] mux_1level_tapbuf_size2_404_configbus0; -wire [1340:1340] mux_1level_tapbuf_size2_404_configbus1; -wire [1340:1340] mux_1level_tapbuf_size2_404_sram_blwl_out ; -wire [1340:1340] mux_1level_tapbuf_size2_404_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_404_configbus0[1340:1340] = sram_blwl_bl[1340:1340] ; -assign mux_1level_tapbuf_size2_404_configbus1[1340:1340] = sram_blwl_wl[1340:1340] ; -wire [1340:1340] mux_1level_tapbuf_size2_404_configbus0_b; -assign mux_1level_tapbuf_size2_404_configbus0_b[1340:1340] = sram_blwl_blb[1340:1340] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_404_ (in_bus_mux_1level_tapbuf_size2_404_, mode_ble6___out_0_, mux_1level_tapbuf_size2_404_sram_blwl_out[1340:1340] , -mux_1level_tapbuf_size2_404_sram_blwl_outb[1340:1340] ); -//----- SRAM bits for MUX[404], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1340_ (mux_1level_tapbuf_size2_404_sram_blwl_out[1340:1340] ,mux_1level_tapbuf_size2_404_sram_blwl_out[1340:1340] ,mux_1level_tapbuf_size2_404_sram_blwl_outb[1340:1340] ,mux_1level_tapbuf_size2_404_configbus0[1340:1340], mux_1level_tapbuf_size2_404_configbus1[1340:1340] , mux_1level_tapbuf_size2_404_configbus0_b[1340:1340] ); -direct_interc direct_interc_64_ (mode_ble6___in_0_, lut6_0___in_0_ ); -direct_interc direct_interc_65_ (mode_ble6___in_1_, lut6_0___in_1_ ); -direct_interc direct_interc_66_ (mode_ble6___in_2_, lut6_0___in_2_ ); -direct_interc direct_interc_67_ (mode_ble6___in_3_, lut6_0___in_3_ ); -direct_interc direct_interc_68_ (mode_ble6___in_4_, lut6_0___in_4_ ); -direct_interc direct_interc_69_ (mode_ble6___in_5_, lut6_0___in_5_ ); -direct_interc direct_interc_70_ (lut6_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_71_ (mode_ble6___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6_ ----- -module grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut6___in_0_, -input wire mode_n1_lut6___in_1_, -input wire mode_n1_lut6___in_2_, -input wire mode_n1_lut6___in_3_, -input wire mode_n1_lut6___in_4_, -input wire mode_n1_lut6___in_5_, -output wire mode_n1_lut6___out_0_, -input wire mode_n1_lut6___clk_0_, -input [1276:1340] sram_blwl_bl , -input [1276:1340] sram_blwl_wl , -input [1276:1340] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6__ble6_0__mode_ble6_ ble6_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble6_0___in_0_, ble6_0___in_1_, ble6_0___in_2_, ble6_0___in_3_, ble6_0___in_4_, ble6_0___in_5_, ble6_0___out_0_, ble6_0___clk_0_, -sram_blwl_bl[1276:1340] , -sram_blwl_wl[1276:1340] , -sram_blwl_blb[1276:1340] ); -direct_interc direct_interc_72_ (ble6_0___out_0_, mode_n1_lut6___out_0_ ); -direct_interc direct_interc_73_ (mode_n1_lut6___in_0_, ble6_0___in_0_ ); -direct_interc direct_interc_74_ (mode_n1_lut6___in_1_, ble6_0___in_1_ ); -direct_interc direct_interc_75_ (mode_n1_lut6___in_2_, ble6_0___in_2_ ); -direct_interc direct_interc_76_ (mode_n1_lut6___in_3_, ble6_0___in_3_ ); -direct_interc direct_interc_77_ (mode_n1_lut6___in_4_, ble6_0___in_4_ ); -direct_interc direct_interc_78_ (mode_n1_lut6___in_5_, ble6_0___in_5_ ); -direct_interc direct_interc_79_ (mode_n1_lut6___clk_0_, ble6_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6_ ----- - -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ( -input wire lut6_0___in_0_, -input wire lut6_0___in_1_, -input wire lut6_0___in_2_, -input wire lut6_0___in_3_, -input wire lut6_0___in_4_, -input wire lut6_0___in_5_, -output wire lut6_0___out_0_, -input [1341:1404] sram_blwl_bl , -input [1341:1404] sram_blwl_wl , -input [1341:1404] sram_blwl_blb ); -wire [0:5] lut6_0___in; -assign lut6_0___in[0] = lut6_0___in_0_; -assign lut6_0___in[1] = lut6_0___in_1_; -assign lut6_0___in[2] = lut6_0___in_2_; -assign lut6_0___in[3] = lut6_0___in_3_; -assign lut6_0___in[4] = lut6_0___in_4_; -assign lut6_0___in[5] = lut6_0___in_5_; -wire [0:0] lut6_0___out; -assign lut6_0___out_0_ = lut6_0___out[0]; -wire [1341:1404] sram_blwl_out ; -wire [1341:1404] sram_blwl_outb ; -lut6 lut6_5_ ( -//----- Input and output ports ----- - lut6_0___in[0:5] , lut6_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[1341:1404] , sram_blwl_outb[1341:1404] ); -//----- Truth Table for LUT[5], size=6. ----- -//----- SRAM bits for LUT[5], size=6, num_sram=64. ----- -//-----0000000000000000000000000000000000000000000000000000000000000000----- -wire [1341:1341] sram_blwl_1341_configbus0; -wire [1341:1341] sram_blwl_1341_configbus1; -wire [1341:1341] sram_blwl_1341_configbus0_b; -assign sram_blwl_1341_configbus0[1341:1341] = sram_blwl_bl[1341:1341] ; -assign sram_blwl_1341_configbus1[1341:1341] = sram_blwl_wl[1341:1341] ; -assign sram_blwl_1341_configbus0_b[1341:1341] = sram_blwl_blb[1341:1341] ; -sram6T_blwl sram_blwl_1341_ (sram_blwl_out[1341], sram_blwl_out[1341], sram_blwl_outb[1341], sram_blwl_1341_configbus0[1341:1341], sram_blwl_1341_configbus1[1341:1341] , sram_blwl_1341_configbus0_b[1341:1341] ); -wire [1342:1342] sram_blwl_1342_configbus0; -wire [1342:1342] sram_blwl_1342_configbus1; -wire [1342:1342] sram_blwl_1342_configbus0_b; -assign sram_blwl_1342_configbus0[1342:1342] = sram_blwl_bl[1342:1342] ; -assign sram_blwl_1342_configbus1[1342:1342] = sram_blwl_wl[1342:1342] ; -assign sram_blwl_1342_configbus0_b[1342:1342] = sram_blwl_blb[1342:1342] ; -sram6T_blwl sram_blwl_1342_ (sram_blwl_out[1342], sram_blwl_out[1342], sram_blwl_outb[1342], sram_blwl_1342_configbus0[1342:1342], sram_blwl_1342_configbus1[1342:1342] , sram_blwl_1342_configbus0_b[1342:1342] ); -wire [1343:1343] sram_blwl_1343_configbus0; -wire [1343:1343] sram_blwl_1343_configbus1; -wire [1343:1343] sram_blwl_1343_configbus0_b; -assign sram_blwl_1343_configbus0[1343:1343] = sram_blwl_bl[1343:1343] ; -assign sram_blwl_1343_configbus1[1343:1343] = sram_blwl_wl[1343:1343] ; -assign sram_blwl_1343_configbus0_b[1343:1343] = sram_blwl_blb[1343:1343] ; -sram6T_blwl sram_blwl_1343_ (sram_blwl_out[1343], sram_blwl_out[1343], sram_blwl_outb[1343], sram_blwl_1343_configbus0[1343:1343], sram_blwl_1343_configbus1[1343:1343] , sram_blwl_1343_configbus0_b[1343:1343] ); -wire [1344:1344] sram_blwl_1344_configbus0; -wire [1344:1344] sram_blwl_1344_configbus1; -wire [1344:1344] sram_blwl_1344_configbus0_b; -assign sram_blwl_1344_configbus0[1344:1344] = sram_blwl_bl[1344:1344] ; -assign sram_blwl_1344_configbus1[1344:1344] = sram_blwl_wl[1344:1344] ; -assign sram_blwl_1344_configbus0_b[1344:1344] = sram_blwl_blb[1344:1344] ; -sram6T_blwl sram_blwl_1344_ (sram_blwl_out[1344], sram_blwl_out[1344], sram_blwl_outb[1344], sram_blwl_1344_configbus0[1344:1344], sram_blwl_1344_configbus1[1344:1344] , sram_blwl_1344_configbus0_b[1344:1344] ); -wire [1345:1345] sram_blwl_1345_configbus0; -wire [1345:1345] sram_blwl_1345_configbus1; -wire [1345:1345] sram_blwl_1345_configbus0_b; -assign sram_blwl_1345_configbus0[1345:1345] = sram_blwl_bl[1345:1345] ; -assign sram_blwl_1345_configbus1[1345:1345] = sram_blwl_wl[1345:1345] ; -assign sram_blwl_1345_configbus0_b[1345:1345] = sram_blwl_blb[1345:1345] ; -sram6T_blwl sram_blwl_1345_ (sram_blwl_out[1345], sram_blwl_out[1345], sram_blwl_outb[1345], sram_blwl_1345_configbus0[1345:1345], sram_blwl_1345_configbus1[1345:1345] , sram_blwl_1345_configbus0_b[1345:1345] ); -wire [1346:1346] sram_blwl_1346_configbus0; -wire [1346:1346] sram_blwl_1346_configbus1; -wire [1346:1346] sram_blwl_1346_configbus0_b; -assign sram_blwl_1346_configbus0[1346:1346] = sram_blwl_bl[1346:1346] ; -assign sram_blwl_1346_configbus1[1346:1346] = sram_blwl_wl[1346:1346] ; -assign sram_blwl_1346_configbus0_b[1346:1346] = sram_blwl_blb[1346:1346] ; -sram6T_blwl sram_blwl_1346_ (sram_blwl_out[1346], sram_blwl_out[1346], sram_blwl_outb[1346], sram_blwl_1346_configbus0[1346:1346], sram_blwl_1346_configbus1[1346:1346] , sram_blwl_1346_configbus0_b[1346:1346] ); -wire [1347:1347] sram_blwl_1347_configbus0; -wire [1347:1347] sram_blwl_1347_configbus1; -wire [1347:1347] sram_blwl_1347_configbus0_b; -assign sram_blwl_1347_configbus0[1347:1347] = sram_blwl_bl[1347:1347] ; -assign sram_blwl_1347_configbus1[1347:1347] = sram_blwl_wl[1347:1347] ; -assign sram_blwl_1347_configbus0_b[1347:1347] = sram_blwl_blb[1347:1347] ; -sram6T_blwl sram_blwl_1347_ (sram_blwl_out[1347], sram_blwl_out[1347], sram_blwl_outb[1347], sram_blwl_1347_configbus0[1347:1347], sram_blwl_1347_configbus1[1347:1347] , sram_blwl_1347_configbus0_b[1347:1347] ); -wire [1348:1348] sram_blwl_1348_configbus0; -wire [1348:1348] sram_blwl_1348_configbus1; -wire [1348:1348] sram_blwl_1348_configbus0_b; -assign sram_blwl_1348_configbus0[1348:1348] = sram_blwl_bl[1348:1348] ; -assign sram_blwl_1348_configbus1[1348:1348] = sram_blwl_wl[1348:1348] ; -assign sram_blwl_1348_configbus0_b[1348:1348] = sram_blwl_blb[1348:1348] ; -sram6T_blwl sram_blwl_1348_ (sram_blwl_out[1348], sram_blwl_out[1348], sram_blwl_outb[1348], sram_blwl_1348_configbus0[1348:1348], sram_blwl_1348_configbus1[1348:1348] , sram_blwl_1348_configbus0_b[1348:1348] ); -wire [1349:1349] sram_blwl_1349_configbus0; -wire [1349:1349] sram_blwl_1349_configbus1; -wire [1349:1349] sram_blwl_1349_configbus0_b; -assign sram_blwl_1349_configbus0[1349:1349] = sram_blwl_bl[1349:1349] ; -assign sram_blwl_1349_configbus1[1349:1349] = sram_blwl_wl[1349:1349] ; -assign sram_blwl_1349_configbus0_b[1349:1349] = sram_blwl_blb[1349:1349] ; -sram6T_blwl sram_blwl_1349_ (sram_blwl_out[1349], sram_blwl_out[1349], sram_blwl_outb[1349], sram_blwl_1349_configbus0[1349:1349], sram_blwl_1349_configbus1[1349:1349] , sram_blwl_1349_configbus0_b[1349:1349] ); -wire [1350:1350] sram_blwl_1350_configbus0; -wire [1350:1350] sram_blwl_1350_configbus1; -wire [1350:1350] sram_blwl_1350_configbus0_b; -assign sram_blwl_1350_configbus0[1350:1350] = sram_blwl_bl[1350:1350] ; -assign sram_blwl_1350_configbus1[1350:1350] = sram_blwl_wl[1350:1350] ; -assign sram_blwl_1350_configbus0_b[1350:1350] = sram_blwl_blb[1350:1350] ; -sram6T_blwl sram_blwl_1350_ (sram_blwl_out[1350], sram_blwl_out[1350], sram_blwl_outb[1350], sram_blwl_1350_configbus0[1350:1350], sram_blwl_1350_configbus1[1350:1350] , sram_blwl_1350_configbus0_b[1350:1350] ); -wire [1351:1351] sram_blwl_1351_configbus0; -wire [1351:1351] sram_blwl_1351_configbus1; -wire [1351:1351] sram_blwl_1351_configbus0_b; -assign sram_blwl_1351_configbus0[1351:1351] = sram_blwl_bl[1351:1351] ; -assign sram_blwl_1351_configbus1[1351:1351] = sram_blwl_wl[1351:1351] ; -assign sram_blwl_1351_configbus0_b[1351:1351] = sram_blwl_blb[1351:1351] ; -sram6T_blwl sram_blwl_1351_ (sram_blwl_out[1351], sram_blwl_out[1351], sram_blwl_outb[1351], sram_blwl_1351_configbus0[1351:1351], sram_blwl_1351_configbus1[1351:1351] , sram_blwl_1351_configbus0_b[1351:1351] ); -wire [1352:1352] sram_blwl_1352_configbus0; -wire [1352:1352] sram_blwl_1352_configbus1; -wire [1352:1352] sram_blwl_1352_configbus0_b; -assign sram_blwl_1352_configbus0[1352:1352] = sram_blwl_bl[1352:1352] ; -assign sram_blwl_1352_configbus1[1352:1352] = sram_blwl_wl[1352:1352] ; -assign sram_blwl_1352_configbus0_b[1352:1352] = sram_blwl_blb[1352:1352] ; -sram6T_blwl sram_blwl_1352_ (sram_blwl_out[1352], sram_blwl_out[1352], sram_blwl_outb[1352], sram_blwl_1352_configbus0[1352:1352], sram_blwl_1352_configbus1[1352:1352] , sram_blwl_1352_configbus0_b[1352:1352] ); -wire [1353:1353] sram_blwl_1353_configbus0; -wire [1353:1353] sram_blwl_1353_configbus1; -wire [1353:1353] sram_blwl_1353_configbus0_b; -assign sram_blwl_1353_configbus0[1353:1353] = sram_blwl_bl[1353:1353] ; -assign sram_blwl_1353_configbus1[1353:1353] = sram_blwl_wl[1353:1353] ; -assign sram_blwl_1353_configbus0_b[1353:1353] = sram_blwl_blb[1353:1353] ; -sram6T_blwl sram_blwl_1353_ (sram_blwl_out[1353], sram_blwl_out[1353], sram_blwl_outb[1353], sram_blwl_1353_configbus0[1353:1353], sram_blwl_1353_configbus1[1353:1353] , sram_blwl_1353_configbus0_b[1353:1353] ); -wire [1354:1354] sram_blwl_1354_configbus0; -wire [1354:1354] sram_blwl_1354_configbus1; -wire [1354:1354] sram_blwl_1354_configbus0_b; -assign sram_blwl_1354_configbus0[1354:1354] = sram_blwl_bl[1354:1354] ; -assign sram_blwl_1354_configbus1[1354:1354] = sram_blwl_wl[1354:1354] ; -assign sram_blwl_1354_configbus0_b[1354:1354] = sram_blwl_blb[1354:1354] ; -sram6T_blwl sram_blwl_1354_ (sram_blwl_out[1354], sram_blwl_out[1354], sram_blwl_outb[1354], sram_blwl_1354_configbus0[1354:1354], sram_blwl_1354_configbus1[1354:1354] , sram_blwl_1354_configbus0_b[1354:1354] ); -wire [1355:1355] sram_blwl_1355_configbus0; -wire [1355:1355] sram_blwl_1355_configbus1; -wire [1355:1355] sram_blwl_1355_configbus0_b; -assign sram_blwl_1355_configbus0[1355:1355] = sram_blwl_bl[1355:1355] ; -assign sram_blwl_1355_configbus1[1355:1355] = sram_blwl_wl[1355:1355] ; -assign sram_blwl_1355_configbus0_b[1355:1355] = sram_blwl_blb[1355:1355] ; -sram6T_blwl sram_blwl_1355_ (sram_blwl_out[1355], sram_blwl_out[1355], sram_blwl_outb[1355], sram_blwl_1355_configbus0[1355:1355], sram_blwl_1355_configbus1[1355:1355] , sram_blwl_1355_configbus0_b[1355:1355] ); -wire [1356:1356] sram_blwl_1356_configbus0; -wire [1356:1356] sram_blwl_1356_configbus1; -wire [1356:1356] sram_blwl_1356_configbus0_b; -assign sram_blwl_1356_configbus0[1356:1356] = sram_blwl_bl[1356:1356] ; -assign sram_blwl_1356_configbus1[1356:1356] = sram_blwl_wl[1356:1356] ; -assign sram_blwl_1356_configbus0_b[1356:1356] = sram_blwl_blb[1356:1356] ; -sram6T_blwl sram_blwl_1356_ (sram_blwl_out[1356], sram_blwl_out[1356], sram_blwl_outb[1356], sram_blwl_1356_configbus0[1356:1356], sram_blwl_1356_configbus1[1356:1356] , sram_blwl_1356_configbus0_b[1356:1356] ); -wire [1357:1357] sram_blwl_1357_configbus0; -wire [1357:1357] sram_blwl_1357_configbus1; -wire [1357:1357] sram_blwl_1357_configbus0_b; -assign sram_blwl_1357_configbus0[1357:1357] = sram_blwl_bl[1357:1357] ; -assign sram_blwl_1357_configbus1[1357:1357] = sram_blwl_wl[1357:1357] ; -assign sram_blwl_1357_configbus0_b[1357:1357] = sram_blwl_blb[1357:1357] ; -sram6T_blwl sram_blwl_1357_ (sram_blwl_out[1357], sram_blwl_out[1357], sram_blwl_outb[1357], sram_blwl_1357_configbus0[1357:1357], sram_blwl_1357_configbus1[1357:1357] , sram_blwl_1357_configbus0_b[1357:1357] ); -wire [1358:1358] sram_blwl_1358_configbus0; -wire [1358:1358] sram_blwl_1358_configbus1; -wire [1358:1358] sram_blwl_1358_configbus0_b; -assign sram_blwl_1358_configbus0[1358:1358] = sram_blwl_bl[1358:1358] ; -assign sram_blwl_1358_configbus1[1358:1358] = sram_blwl_wl[1358:1358] ; -assign sram_blwl_1358_configbus0_b[1358:1358] = sram_blwl_blb[1358:1358] ; -sram6T_blwl sram_blwl_1358_ (sram_blwl_out[1358], sram_blwl_out[1358], sram_blwl_outb[1358], sram_blwl_1358_configbus0[1358:1358], sram_blwl_1358_configbus1[1358:1358] , sram_blwl_1358_configbus0_b[1358:1358] ); -wire [1359:1359] sram_blwl_1359_configbus0; -wire [1359:1359] sram_blwl_1359_configbus1; -wire [1359:1359] sram_blwl_1359_configbus0_b; -assign sram_blwl_1359_configbus0[1359:1359] = sram_blwl_bl[1359:1359] ; -assign sram_blwl_1359_configbus1[1359:1359] = sram_blwl_wl[1359:1359] ; -assign sram_blwl_1359_configbus0_b[1359:1359] = sram_blwl_blb[1359:1359] ; -sram6T_blwl sram_blwl_1359_ (sram_blwl_out[1359], sram_blwl_out[1359], sram_blwl_outb[1359], sram_blwl_1359_configbus0[1359:1359], sram_blwl_1359_configbus1[1359:1359] , sram_blwl_1359_configbus0_b[1359:1359] ); -wire [1360:1360] sram_blwl_1360_configbus0; -wire [1360:1360] sram_blwl_1360_configbus1; -wire [1360:1360] sram_blwl_1360_configbus0_b; -assign sram_blwl_1360_configbus0[1360:1360] = sram_blwl_bl[1360:1360] ; -assign sram_blwl_1360_configbus1[1360:1360] = sram_blwl_wl[1360:1360] ; -assign sram_blwl_1360_configbus0_b[1360:1360] = sram_blwl_blb[1360:1360] ; -sram6T_blwl sram_blwl_1360_ (sram_blwl_out[1360], sram_blwl_out[1360], sram_blwl_outb[1360], sram_blwl_1360_configbus0[1360:1360], sram_blwl_1360_configbus1[1360:1360] , sram_blwl_1360_configbus0_b[1360:1360] ); -wire [1361:1361] sram_blwl_1361_configbus0; -wire [1361:1361] sram_blwl_1361_configbus1; -wire [1361:1361] sram_blwl_1361_configbus0_b; -assign sram_blwl_1361_configbus0[1361:1361] = sram_blwl_bl[1361:1361] ; -assign sram_blwl_1361_configbus1[1361:1361] = sram_blwl_wl[1361:1361] ; -assign sram_blwl_1361_configbus0_b[1361:1361] = sram_blwl_blb[1361:1361] ; -sram6T_blwl sram_blwl_1361_ (sram_blwl_out[1361], sram_blwl_out[1361], sram_blwl_outb[1361], sram_blwl_1361_configbus0[1361:1361], sram_blwl_1361_configbus1[1361:1361] , sram_blwl_1361_configbus0_b[1361:1361] ); -wire [1362:1362] sram_blwl_1362_configbus0; -wire [1362:1362] sram_blwl_1362_configbus1; -wire [1362:1362] sram_blwl_1362_configbus0_b; -assign sram_blwl_1362_configbus0[1362:1362] = sram_blwl_bl[1362:1362] ; -assign sram_blwl_1362_configbus1[1362:1362] = sram_blwl_wl[1362:1362] ; -assign sram_blwl_1362_configbus0_b[1362:1362] = sram_blwl_blb[1362:1362] ; -sram6T_blwl sram_blwl_1362_ (sram_blwl_out[1362], sram_blwl_out[1362], sram_blwl_outb[1362], sram_blwl_1362_configbus0[1362:1362], sram_blwl_1362_configbus1[1362:1362] , sram_blwl_1362_configbus0_b[1362:1362] ); -wire [1363:1363] sram_blwl_1363_configbus0; -wire [1363:1363] sram_blwl_1363_configbus1; -wire [1363:1363] sram_blwl_1363_configbus0_b; -assign sram_blwl_1363_configbus0[1363:1363] = sram_blwl_bl[1363:1363] ; -assign sram_blwl_1363_configbus1[1363:1363] = sram_blwl_wl[1363:1363] ; -assign sram_blwl_1363_configbus0_b[1363:1363] = sram_blwl_blb[1363:1363] ; -sram6T_blwl sram_blwl_1363_ (sram_blwl_out[1363], sram_blwl_out[1363], sram_blwl_outb[1363], sram_blwl_1363_configbus0[1363:1363], sram_blwl_1363_configbus1[1363:1363] , sram_blwl_1363_configbus0_b[1363:1363] ); -wire [1364:1364] sram_blwl_1364_configbus0; -wire [1364:1364] sram_blwl_1364_configbus1; -wire [1364:1364] sram_blwl_1364_configbus0_b; -assign sram_blwl_1364_configbus0[1364:1364] = sram_blwl_bl[1364:1364] ; -assign sram_blwl_1364_configbus1[1364:1364] = sram_blwl_wl[1364:1364] ; -assign sram_blwl_1364_configbus0_b[1364:1364] = sram_blwl_blb[1364:1364] ; -sram6T_blwl sram_blwl_1364_ (sram_blwl_out[1364], sram_blwl_out[1364], sram_blwl_outb[1364], sram_blwl_1364_configbus0[1364:1364], sram_blwl_1364_configbus1[1364:1364] , sram_blwl_1364_configbus0_b[1364:1364] ); -wire [1365:1365] sram_blwl_1365_configbus0; -wire [1365:1365] sram_blwl_1365_configbus1; -wire [1365:1365] sram_blwl_1365_configbus0_b; -assign sram_blwl_1365_configbus0[1365:1365] = sram_blwl_bl[1365:1365] ; -assign sram_blwl_1365_configbus1[1365:1365] = sram_blwl_wl[1365:1365] ; -assign sram_blwl_1365_configbus0_b[1365:1365] = sram_blwl_blb[1365:1365] ; -sram6T_blwl sram_blwl_1365_ (sram_blwl_out[1365], sram_blwl_out[1365], sram_blwl_outb[1365], sram_blwl_1365_configbus0[1365:1365], sram_blwl_1365_configbus1[1365:1365] , sram_blwl_1365_configbus0_b[1365:1365] ); -wire [1366:1366] sram_blwl_1366_configbus0; -wire [1366:1366] sram_blwl_1366_configbus1; -wire [1366:1366] sram_blwl_1366_configbus0_b; -assign sram_blwl_1366_configbus0[1366:1366] = sram_blwl_bl[1366:1366] ; -assign sram_blwl_1366_configbus1[1366:1366] = sram_blwl_wl[1366:1366] ; -assign sram_blwl_1366_configbus0_b[1366:1366] = sram_blwl_blb[1366:1366] ; -sram6T_blwl sram_blwl_1366_ (sram_blwl_out[1366], sram_blwl_out[1366], sram_blwl_outb[1366], sram_blwl_1366_configbus0[1366:1366], sram_blwl_1366_configbus1[1366:1366] , sram_blwl_1366_configbus0_b[1366:1366] ); -wire [1367:1367] sram_blwl_1367_configbus0; -wire [1367:1367] sram_blwl_1367_configbus1; -wire [1367:1367] sram_blwl_1367_configbus0_b; -assign sram_blwl_1367_configbus0[1367:1367] = sram_blwl_bl[1367:1367] ; -assign sram_blwl_1367_configbus1[1367:1367] = sram_blwl_wl[1367:1367] ; -assign sram_blwl_1367_configbus0_b[1367:1367] = sram_blwl_blb[1367:1367] ; -sram6T_blwl sram_blwl_1367_ (sram_blwl_out[1367], sram_blwl_out[1367], sram_blwl_outb[1367], sram_blwl_1367_configbus0[1367:1367], sram_blwl_1367_configbus1[1367:1367] , sram_blwl_1367_configbus0_b[1367:1367] ); -wire [1368:1368] sram_blwl_1368_configbus0; -wire [1368:1368] sram_blwl_1368_configbus1; -wire [1368:1368] sram_blwl_1368_configbus0_b; -assign sram_blwl_1368_configbus0[1368:1368] = sram_blwl_bl[1368:1368] ; -assign sram_blwl_1368_configbus1[1368:1368] = sram_blwl_wl[1368:1368] ; -assign sram_blwl_1368_configbus0_b[1368:1368] = sram_blwl_blb[1368:1368] ; -sram6T_blwl sram_blwl_1368_ (sram_blwl_out[1368], sram_blwl_out[1368], sram_blwl_outb[1368], sram_blwl_1368_configbus0[1368:1368], sram_blwl_1368_configbus1[1368:1368] , sram_blwl_1368_configbus0_b[1368:1368] ); -wire [1369:1369] sram_blwl_1369_configbus0; -wire [1369:1369] sram_blwl_1369_configbus1; -wire [1369:1369] sram_blwl_1369_configbus0_b; -assign sram_blwl_1369_configbus0[1369:1369] = sram_blwl_bl[1369:1369] ; -assign sram_blwl_1369_configbus1[1369:1369] = sram_blwl_wl[1369:1369] ; -assign sram_blwl_1369_configbus0_b[1369:1369] = sram_blwl_blb[1369:1369] ; -sram6T_blwl sram_blwl_1369_ (sram_blwl_out[1369], sram_blwl_out[1369], sram_blwl_outb[1369], sram_blwl_1369_configbus0[1369:1369], sram_blwl_1369_configbus1[1369:1369] , sram_blwl_1369_configbus0_b[1369:1369] ); -wire [1370:1370] sram_blwl_1370_configbus0; -wire [1370:1370] sram_blwl_1370_configbus1; -wire [1370:1370] sram_blwl_1370_configbus0_b; -assign sram_blwl_1370_configbus0[1370:1370] = sram_blwl_bl[1370:1370] ; -assign sram_blwl_1370_configbus1[1370:1370] = sram_blwl_wl[1370:1370] ; -assign sram_blwl_1370_configbus0_b[1370:1370] = sram_blwl_blb[1370:1370] ; -sram6T_blwl sram_blwl_1370_ (sram_blwl_out[1370], sram_blwl_out[1370], sram_blwl_outb[1370], sram_blwl_1370_configbus0[1370:1370], sram_blwl_1370_configbus1[1370:1370] , sram_blwl_1370_configbus0_b[1370:1370] ); -wire [1371:1371] sram_blwl_1371_configbus0; -wire [1371:1371] sram_blwl_1371_configbus1; -wire [1371:1371] sram_blwl_1371_configbus0_b; -assign sram_blwl_1371_configbus0[1371:1371] = sram_blwl_bl[1371:1371] ; -assign sram_blwl_1371_configbus1[1371:1371] = sram_blwl_wl[1371:1371] ; -assign sram_blwl_1371_configbus0_b[1371:1371] = sram_blwl_blb[1371:1371] ; -sram6T_blwl sram_blwl_1371_ (sram_blwl_out[1371], sram_blwl_out[1371], sram_blwl_outb[1371], sram_blwl_1371_configbus0[1371:1371], sram_blwl_1371_configbus1[1371:1371] , sram_blwl_1371_configbus0_b[1371:1371] ); -wire [1372:1372] sram_blwl_1372_configbus0; -wire [1372:1372] sram_blwl_1372_configbus1; -wire [1372:1372] sram_blwl_1372_configbus0_b; -assign sram_blwl_1372_configbus0[1372:1372] = sram_blwl_bl[1372:1372] ; -assign sram_blwl_1372_configbus1[1372:1372] = sram_blwl_wl[1372:1372] ; -assign sram_blwl_1372_configbus0_b[1372:1372] = sram_blwl_blb[1372:1372] ; -sram6T_blwl sram_blwl_1372_ (sram_blwl_out[1372], sram_blwl_out[1372], sram_blwl_outb[1372], sram_blwl_1372_configbus0[1372:1372], sram_blwl_1372_configbus1[1372:1372] , sram_blwl_1372_configbus0_b[1372:1372] ); -wire [1373:1373] sram_blwl_1373_configbus0; -wire [1373:1373] sram_blwl_1373_configbus1; -wire [1373:1373] sram_blwl_1373_configbus0_b; -assign sram_blwl_1373_configbus0[1373:1373] = sram_blwl_bl[1373:1373] ; -assign sram_blwl_1373_configbus1[1373:1373] = sram_blwl_wl[1373:1373] ; -assign sram_blwl_1373_configbus0_b[1373:1373] = sram_blwl_blb[1373:1373] ; -sram6T_blwl sram_blwl_1373_ (sram_blwl_out[1373], sram_blwl_out[1373], sram_blwl_outb[1373], sram_blwl_1373_configbus0[1373:1373], sram_blwl_1373_configbus1[1373:1373] , sram_blwl_1373_configbus0_b[1373:1373] ); -wire [1374:1374] sram_blwl_1374_configbus0; -wire [1374:1374] sram_blwl_1374_configbus1; -wire [1374:1374] sram_blwl_1374_configbus0_b; -assign sram_blwl_1374_configbus0[1374:1374] = sram_blwl_bl[1374:1374] ; -assign sram_blwl_1374_configbus1[1374:1374] = sram_blwl_wl[1374:1374] ; -assign sram_blwl_1374_configbus0_b[1374:1374] = sram_blwl_blb[1374:1374] ; -sram6T_blwl sram_blwl_1374_ (sram_blwl_out[1374], sram_blwl_out[1374], sram_blwl_outb[1374], sram_blwl_1374_configbus0[1374:1374], sram_blwl_1374_configbus1[1374:1374] , sram_blwl_1374_configbus0_b[1374:1374] ); -wire [1375:1375] sram_blwl_1375_configbus0; -wire [1375:1375] sram_blwl_1375_configbus1; -wire [1375:1375] sram_blwl_1375_configbus0_b; -assign sram_blwl_1375_configbus0[1375:1375] = sram_blwl_bl[1375:1375] ; -assign sram_blwl_1375_configbus1[1375:1375] = sram_blwl_wl[1375:1375] ; -assign sram_blwl_1375_configbus0_b[1375:1375] = sram_blwl_blb[1375:1375] ; -sram6T_blwl sram_blwl_1375_ (sram_blwl_out[1375], sram_blwl_out[1375], sram_blwl_outb[1375], sram_blwl_1375_configbus0[1375:1375], sram_blwl_1375_configbus1[1375:1375] , sram_blwl_1375_configbus0_b[1375:1375] ); -wire [1376:1376] sram_blwl_1376_configbus0; -wire [1376:1376] sram_blwl_1376_configbus1; -wire [1376:1376] sram_blwl_1376_configbus0_b; -assign sram_blwl_1376_configbus0[1376:1376] = sram_blwl_bl[1376:1376] ; -assign sram_blwl_1376_configbus1[1376:1376] = sram_blwl_wl[1376:1376] ; -assign sram_blwl_1376_configbus0_b[1376:1376] = sram_blwl_blb[1376:1376] ; -sram6T_blwl sram_blwl_1376_ (sram_blwl_out[1376], sram_blwl_out[1376], sram_blwl_outb[1376], sram_blwl_1376_configbus0[1376:1376], sram_blwl_1376_configbus1[1376:1376] , sram_blwl_1376_configbus0_b[1376:1376] ); -wire [1377:1377] sram_blwl_1377_configbus0; -wire [1377:1377] sram_blwl_1377_configbus1; -wire [1377:1377] sram_blwl_1377_configbus0_b; -assign sram_blwl_1377_configbus0[1377:1377] = sram_blwl_bl[1377:1377] ; -assign sram_blwl_1377_configbus1[1377:1377] = sram_blwl_wl[1377:1377] ; -assign sram_blwl_1377_configbus0_b[1377:1377] = sram_blwl_blb[1377:1377] ; -sram6T_blwl sram_blwl_1377_ (sram_blwl_out[1377], sram_blwl_out[1377], sram_blwl_outb[1377], sram_blwl_1377_configbus0[1377:1377], sram_blwl_1377_configbus1[1377:1377] , sram_blwl_1377_configbus0_b[1377:1377] ); -wire [1378:1378] sram_blwl_1378_configbus0; -wire [1378:1378] sram_blwl_1378_configbus1; -wire [1378:1378] sram_blwl_1378_configbus0_b; -assign sram_blwl_1378_configbus0[1378:1378] = sram_blwl_bl[1378:1378] ; -assign sram_blwl_1378_configbus1[1378:1378] = sram_blwl_wl[1378:1378] ; -assign sram_blwl_1378_configbus0_b[1378:1378] = sram_blwl_blb[1378:1378] ; -sram6T_blwl sram_blwl_1378_ (sram_blwl_out[1378], sram_blwl_out[1378], sram_blwl_outb[1378], sram_blwl_1378_configbus0[1378:1378], sram_blwl_1378_configbus1[1378:1378] , sram_blwl_1378_configbus0_b[1378:1378] ); -wire [1379:1379] sram_blwl_1379_configbus0; -wire [1379:1379] sram_blwl_1379_configbus1; -wire [1379:1379] sram_blwl_1379_configbus0_b; -assign sram_blwl_1379_configbus0[1379:1379] = sram_blwl_bl[1379:1379] ; -assign sram_blwl_1379_configbus1[1379:1379] = sram_blwl_wl[1379:1379] ; -assign sram_blwl_1379_configbus0_b[1379:1379] = sram_blwl_blb[1379:1379] ; -sram6T_blwl sram_blwl_1379_ (sram_blwl_out[1379], sram_blwl_out[1379], sram_blwl_outb[1379], sram_blwl_1379_configbus0[1379:1379], sram_blwl_1379_configbus1[1379:1379] , sram_blwl_1379_configbus0_b[1379:1379] ); -wire [1380:1380] sram_blwl_1380_configbus0; -wire [1380:1380] sram_blwl_1380_configbus1; -wire [1380:1380] sram_blwl_1380_configbus0_b; -assign sram_blwl_1380_configbus0[1380:1380] = sram_blwl_bl[1380:1380] ; -assign sram_blwl_1380_configbus1[1380:1380] = sram_blwl_wl[1380:1380] ; -assign sram_blwl_1380_configbus0_b[1380:1380] = sram_blwl_blb[1380:1380] ; -sram6T_blwl sram_blwl_1380_ (sram_blwl_out[1380], sram_blwl_out[1380], sram_blwl_outb[1380], sram_blwl_1380_configbus0[1380:1380], sram_blwl_1380_configbus1[1380:1380] , sram_blwl_1380_configbus0_b[1380:1380] ); -wire [1381:1381] sram_blwl_1381_configbus0; -wire [1381:1381] sram_blwl_1381_configbus1; -wire [1381:1381] sram_blwl_1381_configbus0_b; -assign sram_blwl_1381_configbus0[1381:1381] = sram_blwl_bl[1381:1381] ; -assign sram_blwl_1381_configbus1[1381:1381] = sram_blwl_wl[1381:1381] ; -assign sram_blwl_1381_configbus0_b[1381:1381] = sram_blwl_blb[1381:1381] ; -sram6T_blwl sram_blwl_1381_ (sram_blwl_out[1381], sram_blwl_out[1381], sram_blwl_outb[1381], sram_blwl_1381_configbus0[1381:1381], sram_blwl_1381_configbus1[1381:1381] , sram_blwl_1381_configbus0_b[1381:1381] ); -wire [1382:1382] sram_blwl_1382_configbus0; -wire [1382:1382] sram_blwl_1382_configbus1; -wire [1382:1382] sram_blwl_1382_configbus0_b; -assign sram_blwl_1382_configbus0[1382:1382] = sram_blwl_bl[1382:1382] ; -assign sram_blwl_1382_configbus1[1382:1382] = sram_blwl_wl[1382:1382] ; -assign sram_blwl_1382_configbus0_b[1382:1382] = sram_blwl_blb[1382:1382] ; -sram6T_blwl sram_blwl_1382_ (sram_blwl_out[1382], sram_blwl_out[1382], sram_blwl_outb[1382], sram_blwl_1382_configbus0[1382:1382], sram_blwl_1382_configbus1[1382:1382] , sram_blwl_1382_configbus0_b[1382:1382] ); -wire [1383:1383] sram_blwl_1383_configbus0; -wire [1383:1383] sram_blwl_1383_configbus1; -wire [1383:1383] sram_blwl_1383_configbus0_b; -assign sram_blwl_1383_configbus0[1383:1383] = sram_blwl_bl[1383:1383] ; -assign sram_blwl_1383_configbus1[1383:1383] = sram_blwl_wl[1383:1383] ; -assign sram_blwl_1383_configbus0_b[1383:1383] = sram_blwl_blb[1383:1383] ; -sram6T_blwl sram_blwl_1383_ (sram_blwl_out[1383], sram_blwl_out[1383], sram_blwl_outb[1383], sram_blwl_1383_configbus0[1383:1383], sram_blwl_1383_configbus1[1383:1383] , sram_blwl_1383_configbus0_b[1383:1383] ); -wire [1384:1384] sram_blwl_1384_configbus0; -wire [1384:1384] sram_blwl_1384_configbus1; -wire [1384:1384] sram_blwl_1384_configbus0_b; -assign sram_blwl_1384_configbus0[1384:1384] = sram_blwl_bl[1384:1384] ; -assign sram_blwl_1384_configbus1[1384:1384] = sram_blwl_wl[1384:1384] ; -assign sram_blwl_1384_configbus0_b[1384:1384] = sram_blwl_blb[1384:1384] ; -sram6T_blwl sram_blwl_1384_ (sram_blwl_out[1384], sram_blwl_out[1384], sram_blwl_outb[1384], sram_blwl_1384_configbus0[1384:1384], sram_blwl_1384_configbus1[1384:1384] , sram_blwl_1384_configbus0_b[1384:1384] ); -wire [1385:1385] sram_blwl_1385_configbus0; -wire [1385:1385] sram_blwl_1385_configbus1; -wire [1385:1385] sram_blwl_1385_configbus0_b; -assign sram_blwl_1385_configbus0[1385:1385] = sram_blwl_bl[1385:1385] ; -assign sram_blwl_1385_configbus1[1385:1385] = sram_blwl_wl[1385:1385] ; -assign sram_blwl_1385_configbus0_b[1385:1385] = sram_blwl_blb[1385:1385] ; -sram6T_blwl sram_blwl_1385_ (sram_blwl_out[1385], sram_blwl_out[1385], sram_blwl_outb[1385], sram_blwl_1385_configbus0[1385:1385], sram_blwl_1385_configbus1[1385:1385] , sram_blwl_1385_configbus0_b[1385:1385] ); -wire [1386:1386] sram_blwl_1386_configbus0; -wire [1386:1386] sram_blwl_1386_configbus1; -wire [1386:1386] sram_blwl_1386_configbus0_b; -assign sram_blwl_1386_configbus0[1386:1386] = sram_blwl_bl[1386:1386] ; -assign sram_blwl_1386_configbus1[1386:1386] = sram_blwl_wl[1386:1386] ; -assign sram_blwl_1386_configbus0_b[1386:1386] = sram_blwl_blb[1386:1386] ; -sram6T_blwl sram_blwl_1386_ (sram_blwl_out[1386], sram_blwl_out[1386], sram_blwl_outb[1386], sram_blwl_1386_configbus0[1386:1386], sram_blwl_1386_configbus1[1386:1386] , sram_blwl_1386_configbus0_b[1386:1386] ); -wire [1387:1387] sram_blwl_1387_configbus0; -wire [1387:1387] sram_blwl_1387_configbus1; -wire [1387:1387] sram_blwl_1387_configbus0_b; -assign sram_blwl_1387_configbus0[1387:1387] = sram_blwl_bl[1387:1387] ; -assign sram_blwl_1387_configbus1[1387:1387] = sram_blwl_wl[1387:1387] ; -assign sram_blwl_1387_configbus0_b[1387:1387] = sram_blwl_blb[1387:1387] ; -sram6T_blwl sram_blwl_1387_ (sram_blwl_out[1387], sram_blwl_out[1387], sram_blwl_outb[1387], sram_blwl_1387_configbus0[1387:1387], sram_blwl_1387_configbus1[1387:1387] , sram_blwl_1387_configbus0_b[1387:1387] ); -wire [1388:1388] sram_blwl_1388_configbus0; -wire [1388:1388] sram_blwl_1388_configbus1; -wire [1388:1388] sram_blwl_1388_configbus0_b; -assign sram_blwl_1388_configbus0[1388:1388] = sram_blwl_bl[1388:1388] ; -assign sram_blwl_1388_configbus1[1388:1388] = sram_blwl_wl[1388:1388] ; -assign sram_blwl_1388_configbus0_b[1388:1388] = sram_blwl_blb[1388:1388] ; -sram6T_blwl sram_blwl_1388_ (sram_blwl_out[1388], sram_blwl_out[1388], sram_blwl_outb[1388], sram_blwl_1388_configbus0[1388:1388], sram_blwl_1388_configbus1[1388:1388] , sram_blwl_1388_configbus0_b[1388:1388] ); -wire [1389:1389] sram_blwl_1389_configbus0; -wire [1389:1389] sram_blwl_1389_configbus1; -wire [1389:1389] sram_blwl_1389_configbus0_b; -assign sram_blwl_1389_configbus0[1389:1389] = sram_blwl_bl[1389:1389] ; -assign sram_blwl_1389_configbus1[1389:1389] = sram_blwl_wl[1389:1389] ; -assign sram_blwl_1389_configbus0_b[1389:1389] = sram_blwl_blb[1389:1389] ; -sram6T_blwl sram_blwl_1389_ (sram_blwl_out[1389], sram_blwl_out[1389], sram_blwl_outb[1389], sram_blwl_1389_configbus0[1389:1389], sram_blwl_1389_configbus1[1389:1389] , sram_blwl_1389_configbus0_b[1389:1389] ); -wire [1390:1390] sram_blwl_1390_configbus0; -wire [1390:1390] sram_blwl_1390_configbus1; -wire [1390:1390] sram_blwl_1390_configbus0_b; -assign sram_blwl_1390_configbus0[1390:1390] = sram_blwl_bl[1390:1390] ; -assign sram_blwl_1390_configbus1[1390:1390] = sram_blwl_wl[1390:1390] ; -assign sram_blwl_1390_configbus0_b[1390:1390] = sram_blwl_blb[1390:1390] ; -sram6T_blwl sram_blwl_1390_ (sram_blwl_out[1390], sram_blwl_out[1390], sram_blwl_outb[1390], sram_blwl_1390_configbus0[1390:1390], sram_blwl_1390_configbus1[1390:1390] , sram_blwl_1390_configbus0_b[1390:1390] ); -wire [1391:1391] sram_blwl_1391_configbus0; -wire [1391:1391] sram_blwl_1391_configbus1; -wire [1391:1391] sram_blwl_1391_configbus0_b; -assign sram_blwl_1391_configbus0[1391:1391] = sram_blwl_bl[1391:1391] ; -assign sram_blwl_1391_configbus1[1391:1391] = sram_blwl_wl[1391:1391] ; -assign sram_blwl_1391_configbus0_b[1391:1391] = sram_blwl_blb[1391:1391] ; -sram6T_blwl sram_blwl_1391_ (sram_blwl_out[1391], sram_blwl_out[1391], sram_blwl_outb[1391], sram_blwl_1391_configbus0[1391:1391], sram_blwl_1391_configbus1[1391:1391] , sram_blwl_1391_configbus0_b[1391:1391] ); -wire [1392:1392] sram_blwl_1392_configbus0; -wire [1392:1392] sram_blwl_1392_configbus1; -wire [1392:1392] sram_blwl_1392_configbus0_b; -assign sram_blwl_1392_configbus0[1392:1392] = sram_blwl_bl[1392:1392] ; -assign sram_blwl_1392_configbus1[1392:1392] = sram_blwl_wl[1392:1392] ; -assign sram_blwl_1392_configbus0_b[1392:1392] = sram_blwl_blb[1392:1392] ; -sram6T_blwl sram_blwl_1392_ (sram_blwl_out[1392], sram_blwl_out[1392], sram_blwl_outb[1392], sram_blwl_1392_configbus0[1392:1392], sram_blwl_1392_configbus1[1392:1392] , sram_blwl_1392_configbus0_b[1392:1392] ); -wire [1393:1393] sram_blwl_1393_configbus0; -wire [1393:1393] sram_blwl_1393_configbus1; -wire [1393:1393] sram_blwl_1393_configbus0_b; -assign sram_blwl_1393_configbus0[1393:1393] = sram_blwl_bl[1393:1393] ; -assign sram_blwl_1393_configbus1[1393:1393] = sram_blwl_wl[1393:1393] ; -assign sram_blwl_1393_configbus0_b[1393:1393] = sram_blwl_blb[1393:1393] ; -sram6T_blwl sram_blwl_1393_ (sram_blwl_out[1393], sram_blwl_out[1393], sram_blwl_outb[1393], sram_blwl_1393_configbus0[1393:1393], sram_blwl_1393_configbus1[1393:1393] , sram_blwl_1393_configbus0_b[1393:1393] ); -wire [1394:1394] sram_blwl_1394_configbus0; -wire [1394:1394] sram_blwl_1394_configbus1; -wire [1394:1394] sram_blwl_1394_configbus0_b; -assign sram_blwl_1394_configbus0[1394:1394] = sram_blwl_bl[1394:1394] ; -assign sram_blwl_1394_configbus1[1394:1394] = sram_blwl_wl[1394:1394] ; -assign sram_blwl_1394_configbus0_b[1394:1394] = sram_blwl_blb[1394:1394] ; -sram6T_blwl sram_blwl_1394_ (sram_blwl_out[1394], sram_blwl_out[1394], sram_blwl_outb[1394], sram_blwl_1394_configbus0[1394:1394], sram_blwl_1394_configbus1[1394:1394] , sram_blwl_1394_configbus0_b[1394:1394] ); -wire [1395:1395] sram_blwl_1395_configbus0; -wire [1395:1395] sram_blwl_1395_configbus1; -wire [1395:1395] sram_blwl_1395_configbus0_b; -assign sram_blwl_1395_configbus0[1395:1395] = sram_blwl_bl[1395:1395] ; -assign sram_blwl_1395_configbus1[1395:1395] = sram_blwl_wl[1395:1395] ; -assign sram_blwl_1395_configbus0_b[1395:1395] = sram_blwl_blb[1395:1395] ; -sram6T_blwl sram_blwl_1395_ (sram_blwl_out[1395], sram_blwl_out[1395], sram_blwl_outb[1395], sram_blwl_1395_configbus0[1395:1395], sram_blwl_1395_configbus1[1395:1395] , sram_blwl_1395_configbus0_b[1395:1395] ); -wire [1396:1396] sram_blwl_1396_configbus0; -wire [1396:1396] sram_blwl_1396_configbus1; -wire [1396:1396] sram_blwl_1396_configbus0_b; -assign sram_blwl_1396_configbus0[1396:1396] = sram_blwl_bl[1396:1396] ; -assign sram_blwl_1396_configbus1[1396:1396] = sram_blwl_wl[1396:1396] ; -assign sram_blwl_1396_configbus0_b[1396:1396] = sram_blwl_blb[1396:1396] ; -sram6T_blwl sram_blwl_1396_ (sram_blwl_out[1396], sram_blwl_out[1396], sram_blwl_outb[1396], sram_blwl_1396_configbus0[1396:1396], sram_blwl_1396_configbus1[1396:1396] , sram_blwl_1396_configbus0_b[1396:1396] ); -wire [1397:1397] sram_blwl_1397_configbus0; -wire [1397:1397] sram_blwl_1397_configbus1; -wire [1397:1397] sram_blwl_1397_configbus0_b; -assign sram_blwl_1397_configbus0[1397:1397] = sram_blwl_bl[1397:1397] ; -assign sram_blwl_1397_configbus1[1397:1397] = sram_blwl_wl[1397:1397] ; -assign sram_blwl_1397_configbus0_b[1397:1397] = sram_blwl_blb[1397:1397] ; -sram6T_blwl sram_blwl_1397_ (sram_blwl_out[1397], sram_blwl_out[1397], sram_blwl_outb[1397], sram_blwl_1397_configbus0[1397:1397], sram_blwl_1397_configbus1[1397:1397] , sram_blwl_1397_configbus0_b[1397:1397] ); -wire [1398:1398] sram_blwl_1398_configbus0; -wire [1398:1398] sram_blwl_1398_configbus1; -wire [1398:1398] sram_blwl_1398_configbus0_b; -assign sram_blwl_1398_configbus0[1398:1398] = sram_blwl_bl[1398:1398] ; -assign sram_blwl_1398_configbus1[1398:1398] = sram_blwl_wl[1398:1398] ; -assign sram_blwl_1398_configbus0_b[1398:1398] = sram_blwl_blb[1398:1398] ; -sram6T_blwl sram_blwl_1398_ (sram_blwl_out[1398], sram_blwl_out[1398], sram_blwl_outb[1398], sram_blwl_1398_configbus0[1398:1398], sram_blwl_1398_configbus1[1398:1398] , sram_blwl_1398_configbus0_b[1398:1398] ); -wire [1399:1399] sram_blwl_1399_configbus0; -wire [1399:1399] sram_blwl_1399_configbus1; -wire [1399:1399] sram_blwl_1399_configbus0_b; -assign sram_blwl_1399_configbus0[1399:1399] = sram_blwl_bl[1399:1399] ; -assign sram_blwl_1399_configbus1[1399:1399] = sram_blwl_wl[1399:1399] ; -assign sram_blwl_1399_configbus0_b[1399:1399] = sram_blwl_blb[1399:1399] ; -sram6T_blwl sram_blwl_1399_ (sram_blwl_out[1399], sram_blwl_out[1399], sram_blwl_outb[1399], sram_blwl_1399_configbus0[1399:1399], sram_blwl_1399_configbus1[1399:1399] , sram_blwl_1399_configbus0_b[1399:1399] ); -wire [1400:1400] sram_blwl_1400_configbus0; -wire [1400:1400] sram_blwl_1400_configbus1; -wire [1400:1400] sram_blwl_1400_configbus0_b; -assign sram_blwl_1400_configbus0[1400:1400] = sram_blwl_bl[1400:1400] ; -assign sram_blwl_1400_configbus1[1400:1400] = sram_blwl_wl[1400:1400] ; -assign sram_blwl_1400_configbus0_b[1400:1400] = sram_blwl_blb[1400:1400] ; -sram6T_blwl sram_blwl_1400_ (sram_blwl_out[1400], sram_blwl_out[1400], sram_blwl_outb[1400], sram_blwl_1400_configbus0[1400:1400], sram_blwl_1400_configbus1[1400:1400] , sram_blwl_1400_configbus0_b[1400:1400] ); -wire [1401:1401] sram_blwl_1401_configbus0; -wire [1401:1401] sram_blwl_1401_configbus1; -wire [1401:1401] sram_blwl_1401_configbus0_b; -assign sram_blwl_1401_configbus0[1401:1401] = sram_blwl_bl[1401:1401] ; -assign sram_blwl_1401_configbus1[1401:1401] = sram_blwl_wl[1401:1401] ; -assign sram_blwl_1401_configbus0_b[1401:1401] = sram_blwl_blb[1401:1401] ; -sram6T_blwl sram_blwl_1401_ (sram_blwl_out[1401], sram_blwl_out[1401], sram_blwl_outb[1401], sram_blwl_1401_configbus0[1401:1401], sram_blwl_1401_configbus1[1401:1401] , sram_blwl_1401_configbus0_b[1401:1401] ); -wire [1402:1402] sram_blwl_1402_configbus0; -wire [1402:1402] sram_blwl_1402_configbus1; -wire [1402:1402] sram_blwl_1402_configbus0_b; -assign sram_blwl_1402_configbus0[1402:1402] = sram_blwl_bl[1402:1402] ; -assign sram_blwl_1402_configbus1[1402:1402] = sram_blwl_wl[1402:1402] ; -assign sram_blwl_1402_configbus0_b[1402:1402] = sram_blwl_blb[1402:1402] ; -sram6T_blwl sram_blwl_1402_ (sram_blwl_out[1402], sram_blwl_out[1402], sram_blwl_outb[1402], sram_blwl_1402_configbus0[1402:1402], sram_blwl_1402_configbus1[1402:1402] , sram_blwl_1402_configbus0_b[1402:1402] ); -wire [1403:1403] sram_blwl_1403_configbus0; -wire [1403:1403] sram_blwl_1403_configbus1; -wire [1403:1403] sram_blwl_1403_configbus0_b; -assign sram_blwl_1403_configbus0[1403:1403] = sram_blwl_bl[1403:1403] ; -assign sram_blwl_1403_configbus1[1403:1403] = sram_blwl_wl[1403:1403] ; -assign sram_blwl_1403_configbus0_b[1403:1403] = sram_blwl_blb[1403:1403] ; -sram6T_blwl sram_blwl_1403_ (sram_blwl_out[1403], sram_blwl_out[1403], sram_blwl_outb[1403], sram_blwl_1403_configbus0[1403:1403], sram_blwl_1403_configbus1[1403:1403] , sram_blwl_1403_configbus0_b[1403:1403] ); -wire [1404:1404] sram_blwl_1404_configbus0; -wire [1404:1404] sram_blwl_1404_configbus1; -wire [1404:1404] sram_blwl_1404_configbus0_b; -assign sram_blwl_1404_configbus0[1404:1404] = sram_blwl_bl[1404:1404] ; -assign sram_blwl_1404_configbus1[1404:1404] = sram_blwl_wl[1404:1404] ; -assign sram_blwl_1404_configbus0_b[1404:1404] = sram_blwl_blb[1404:1404] ; -sram6T_blwl sram_blwl_1404_ (sram_blwl_out[1404], sram_blwl_out[1404], sram_blwl_outb[1404], sram_blwl_1404_configbus0[1404:1404], sram_blwl_1404_configbus1[1404:1404] , sram_blwl_1404_configbus0_b[1404:1404] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- - -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_5_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6_ ----- -module grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble6___in_0_, -input wire mode_ble6___in_1_, -input wire mode_ble6___in_2_, -input wire mode_ble6___in_3_, -input wire mode_ble6___in_4_, -input wire mode_ble6___in_5_, -output wire mode_ble6___out_0_, -input wire mode_ble6___clk_0_, -input [1341:1405] sram_blwl_bl , -input [1341:1405] sram_blwl_wl , -input [1341:1405] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ lut6_0_ ( - lut6_0___in_0_, lut6_0___in_1_, lut6_0___in_2_, lut6_0___in_3_, lut6_0___in_4_, lut6_0___in_5_, lut6_0___out_0_, -sram_blwl_bl[1341:1404] , -sram_blwl_wl[1341:1404] , -sram_blwl_blb[1341:1404] ); -grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_405_ ; -assign in_bus_mux_1level_tapbuf_size2_405_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_405_[1] = lut6_0___out_0_ ; -wire [1405:1405] mux_1level_tapbuf_size2_405_configbus0; -wire [1405:1405] mux_1level_tapbuf_size2_405_configbus1; -wire [1405:1405] mux_1level_tapbuf_size2_405_sram_blwl_out ; -wire [1405:1405] mux_1level_tapbuf_size2_405_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_405_configbus0[1405:1405] = sram_blwl_bl[1405:1405] ; -assign mux_1level_tapbuf_size2_405_configbus1[1405:1405] = sram_blwl_wl[1405:1405] ; -wire [1405:1405] mux_1level_tapbuf_size2_405_configbus0_b; -assign mux_1level_tapbuf_size2_405_configbus0_b[1405:1405] = sram_blwl_blb[1405:1405] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_405_ (in_bus_mux_1level_tapbuf_size2_405_, mode_ble6___out_0_, mux_1level_tapbuf_size2_405_sram_blwl_out[1405:1405] , -mux_1level_tapbuf_size2_405_sram_blwl_outb[1405:1405] ); -//----- SRAM bits for MUX[405], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1405_ (mux_1level_tapbuf_size2_405_sram_blwl_out[1405:1405] ,mux_1level_tapbuf_size2_405_sram_blwl_out[1405:1405] ,mux_1level_tapbuf_size2_405_sram_blwl_outb[1405:1405] ,mux_1level_tapbuf_size2_405_configbus0[1405:1405], mux_1level_tapbuf_size2_405_configbus1[1405:1405] , mux_1level_tapbuf_size2_405_configbus0_b[1405:1405] ); -direct_interc direct_interc_80_ (mode_ble6___in_0_, lut6_0___in_0_ ); -direct_interc direct_interc_81_ (mode_ble6___in_1_, lut6_0___in_1_ ); -direct_interc direct_interc_82_ (mode_ble6___in_2_, lut6_0___in_2_ ); -direct_interc direct_interc_83_ (mode_ble6___in_3_, lut6_0___in_3_ ); -direct_interc direct_interc_84_ (mode_ble6___in_4_, lut6_0___in_4_ ); -direct_interc direct_interc_85_ (mode_ble6___in_5_, lut6_0___in_5_ ); -direct_interc direct_interc_86_ (lut6_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_87_ (mode_ble6___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6_ ----- -module grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut6___in_0_, -input wire mode_n1_lut6___in_1_, -input wire mode_n1_lut6___in_2_, -input wire mode_n1_lut6___in_3_, -input wire mode_n1_lut6___in_4_, -input wire mode_n1_lut6___in_5_, -output wire mode_n1_lut6___out_0_, -input wire mode_n1_lut6___clk_0_, -input [1341:1405] sram_blwl_bl , -input [1341:1405] sram_blwl_wl , -input [1341:1405] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6__ble6_0__mode_ble6_ ble6_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble6_0___in_0_, ble6_0___in_1_, ble6_0___in_2_, ble6_0___in_3_, ble6_0___in_4_, ble6_0___in_5_, ble6_0___out_0_, ble6_0___clk_0_, -sram_blwl_bl[1341:1405] , -sram_blwl_wl[1341:1405] , -sram_blwl_blb[1341:1405] ); -direct_interc direct_interc_88_ (ble6_0___out_0_, mode_n1_lut6___out_0_ ); -direct_interc direct_interc_89_ (mode_n1_lut6___in_0_, ble6_0___in_0_ ); -direct_interc direct_interc_90_ (mode_n1_lut6___in_1_, ble6_0___in_1_ ); -direct_interc direct_interc_91_ (mode_n1_lut6___in_2_, ble6_0___in_2_ ); -direct_interc direct_interc_92_ (mode_n1_lut6___in_3_, ble6_0___in_3_ ); -direct_interc direct_interc_93_ (mode_n1_lut6___in_4_, ble6_0___in_4_ ); -direct_interc direct_interc_94_ (mode_n1_lut6___in_5_, ble6_0___in_5_ ); -direct_interc direct_interc_95_ (mode_n1_lut6___clk_0_, ble6_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6_ ----- - -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ( -input wire lut6_0___in_0_, -input wire lut6_0___in_1_, -input wire lut6_0___in_2_, -input wire lut6_0___in_3_, -input wire lut6_0___in_4_, -input wire lut6_0___in_5_, -output wire lut6_0___out_0_, -input [1406:1469] sram_blwl_bl , -input [1406:1469] sram_blwl_wl , -input [1406:1469] sram_blwl_blb ); -wire [0:5] lut6_0___in; -assign lut6_0___in[0] = lut6_0___in_0_; -assign lut6_0___in[1] = lut6_0___in_1_; -assign lut6_0___in[2] = lut6_0___in_2_; -assign lut6_0___in[3] = lut6_0___in_3_; -assign lut6_0___in[4] = lut6_0___in_4_; -assign lut6_0___in[5] = lut6_0___in_5_; -wire [0:0] lut6_0___out; -assign lut6_0___out_0_ = lut6_0___out[0]; -wire [1406:1469] sram_blwl_out ; -wire [1406:1469] sram_blwl_outb ; -lut6 lut6_6_ ( -//----- Input and output ports ----- - lut6_0___in[0:5] , lut6_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[1406:1469] , sram_blwl_outb[1406:1469] ); -//----- Truth Table for LUT[6], size=6. ----- -//----- SRAM bits for LUT[6], size=6, num_sram=64. ----- -//-----0000000000000000000000000000000000000000000000000000000000000000----- -wire [1406:1406] sram_blwl_1406_configbus0; -wire [1406:1406] sram_blwl_1406_configbus1; -wire [1406:1406] sram_blwl_1406_configbus0_b; -assign sram_blwl_1406_configbus0[1406:1406] = sram_blwl_bl[1406:1406] ; -assign sram_blwl_1406_configbus1[1406:1406] = sram_blwl_wl[1406:1406] ; -assign sram_blwl_1406_configbus0_b[1406:1406] = sram_blwl_blb[1406:1406] ; -sram6T_blwl sram_blwl_1406_ (sram_blwl_out[1406], sram_blwl_out[1406], sram_blwl_outb[1406], sram_blwl_1406_configbus0[1406:1406], sram_blwl_1406_configbus1[1406:1406] , sram_blwl_1406_configbus0_b[1406:1406] ); -wire [1407:1407] sram_blwl_1407_configbus0; -wire [1407:1407] sram_blwl_1407_configbus1; -wire [1407:1407] sram_blwl_1407_configbus0_b; -assign sram_blwl_1407_configbus0[1407:1407] = sram_blwl_bl[1407:1407] ; -assign sram_blwl_1407_configbus1[1407:1407] = sram_blwl_wl[1407:1407] ; -assign sram_blwl_1407_configbus0_b[1407:1407] = sram_blwl_blb[1407:1407] ; -sram6T_blwl sram_blwl_1407_ (sram_blwl_out[1407], sram_blwl_out[1407], sram_blwl_outb[1407], sram_blwl_1407_configbus0[1407:1407], sram_blwl_1407_configbus1[1407:1407] , sram_blwl_1407_configbus0_b[1407:1407] ); -wire [1408:1408] sram_blwl_1408_configbus0; -wire [1408:1408] sram_blwl_1408_configbus1; -wire [1408:1408] sram_blwl_1408_configbus0_b; -assign sram_blwl_1408_configbus0[1408:1408] = sram_blwl_bl[1408:1408] ; -assign sram_blwl_1408_configbus1[1408:1408] = sram_blwl_wl[1408:1408] ; -assign sram_blwl_1408_configbus0_b[1408:1408] = sram_blwl_blb[1408:1408] ; -sram6T_blwl sram_blwl_1408_ (sram_blwl_out[1408], sram_blwl_out[1408], sram_blwl_outb[1408], sram_blwl_1408_configbus0[1408:1408], sram_blwl_1408_configbus1[1408:1408] , sram_blwl_1408_configbus0_b[1408:1408] ); -wire [1409:1409] sram_blwl_1409_configbus0; -wire [1409:1409] sram_blwl_1409_configbus1; -wire [1409:1409] sram_blwl_1409_configbus0_b; -assign sram_blwl_1409_configbus0[1409:1409] = sram_blwl_bl[1409:1409] ; -assign sram_blwl_1409_configbus1[1409:1409] = sram_blwl_wl[1409:1409] ; -assign sram_blwl_1409_configbus0_b[1409:1409] = sram_blwl_blb[1409:1409] ; -sram6T_blwl sram_blwl_1409_ (sram_blwl_out[1409], sram_blwl_out[1409], sram_blwl_outb[1409], sram_blwl_1409_configbus0[1409:1409], sram_blwl_1409_configbus1[1409:1409] , sram_blwl_1409_configbus0_b[1409:1409] ); -wire [1410:1410] sram_blwl_1410_configbus0; -wire [1410:1410] sram_blwl_1410_configbus1; -wire [1410:1410] sram_blwl_1410_configbus0_b; -assign sram_blwl_1410_configbus0[1410:1410] = sram_blwl_bl[1410:1410] ; -assign sram_blwl_1410_configbus1[1410:1410] = sram_blwl_wl[1410:1410] ; -assign sram_blwl_1410_configbus0_b[1410:1410] = sram_blwl_blb[1410:1410] ; -sram6T_blwl sram_blwl_1410_ (sram_blwl_out[1410], sram_blwl_out[1410], sram_blwl_outb[1410], sram_blwl_1410_configbus0[1410:1410], sram_blwl_1410_configbus1[1410:1410] , sram_blwl_1410_configbus0_b[1410:1410] ); -wire [1411:1411] sram_blwl_1411_configbus0; -wire [1411:1411] sram_blwl_1411_configbus1; -wire [1411:1411] sram_blwl_1411_configbus0_b; -assign sram_blwl_1411_configbus0[1411:1411] = sram_blwl_bl[1411:1411] ; -assign sram_blwl_1411_configbus1[1411:1411] = sram_blwl_wl[1411:1411] ; -assign sram_blwl_1411_configbus0_b[1411:1411] = sram_blwl_blb[1411:1411] ; -sram6T_blwl sram_blwl_1411_ (sram_blwl_out[1411], sram_blwl_out[1411], sram_blwl_outb[1411], sram_blwl_1411_configbus0[1411:1411], sram_blwl_1411_configbus1[1411:1411] , sram_blwl_1411_configbus0_b[1411:1411] ); -wire [1412:1412] sram_blwl_1412_configbus0; -wire [1412:1412] sram_blwl_1412_configbus1; -wire [1412:1412] sram_blwl_1412_configbus0_b; -assign sram_blwl_1412_configbus0[1412:1412] = sram_blwl_bl[1412:1412] ; -assign sram_blwl_1412_configbus1[1412:1412] = sram_blwl_wl[1412:1412] ; -assign sram_blwl_1412_configbus0_b[1412:1412] = sram_blwl_blb[1412:1412] ; -sram6T_blwl sram_blwl_1412_ (sram_blwl_out[1412], sram_blwl_out[1412], sram_blwl_outb[1412], sram_blwl_1412_configbus0[1412:1412], sram_blwl_1412_configbus1[1412:1412] , sram_blwl_1412_configbus0_b[1412:1412] ); -wire [1413:1413] sram_blwl_1413_configbus0; -wire [1413:1413] sram_blwl_1413_configbus1; -wire [1413:1413] sram_blwl_1413_configbus0_b; -assign sram_blwl_1413_configbus0[1413:1413] = sram_blwl_bl[1413:1413] ; -assign sram_blwl_1413_configbus1[1413:1413] = sram_blwl_wl[1413:1413] ; -assign sram_blwl_1413_configbus0_b[1413:1413] = sram_blwl_blb[1413:1413] ; -sram6T_blwl sram_blwl_1413_ (sram_blwl_out[1413], sram_blwl_out[1413], sram_blwl_outb[1413], sram_blwl_1413_configbus0[1413:1413], sram_blwl_1413_configbus1[1413:1413] , sram_blwl_1413_configbus0_b[1413:1413] ); -wire [1414:1414] sram_blwl_1414_configbus0; -wire [1414:1414] sram_blwl_1414_configbus1; -wire [1414:1414] sram_blwl_1414_configbus0_b; -assign sram_blwl_1414_configbus0[1414:1414] = sram_blwl_bl[1414:1414] ; -assign sram_blwl_1414_configbus1[1414:1414] = sram_blwl_wl[1414:1414] ; -assign sram_blwl_1414_configbus0_b[1414:1414] = sram_blwl_blb[1414:1414] ; -sram6T_blwl sram_blwl_1414_ (sram_blwl_out[1414], sram_blwl_out[1414], sram_blwl_outb[1414], sram_blwl_1414_configbus0[1414:1414], sram_blwl_1414_configbus1[1414:1414] , sram_blwl_1414_configbus0_b[1414:1414] ); -wire [1415:1415] sram_blwl_1415_configbus0; -wire [1415:1415] sram_blwl_1415_configbus1; -wire [1415:1415] sram_blwl_1415_configbus0_b; -assign sram_blwl_1415_configbus0[1415:1415] = sram_blwl_bl[1415:1415] ; -assign sram_blwl_1415_configbus1[1415:1415] = sram_blwl_wl[1415:1415] ; -assign sram_blwl_1415_configbus0_b[1415:1415] = sram_blwl_blb[1415:1415] ; -sram6T_blwl sram_blwl_1415_ (sram_blwl_out[1415], sram_blwl_out[1415], sram_blwl_outb[1415], sram_blwl_1415_configbus0[1415:1415], sram_blwl_1415_configbus1[1415:1415] , sram_blwl_1415_configbus0_b[1415:1415] ); -wire [1416:1416] sram_blwl_1416_configbus0; -wire [1416:1416] sram_blwl_1416_configbus1; -wire [1416:1416] sram_blwl_1416_configbus0_b; -assign sram_blwl_1416_configbus0[1416:1416] = sram_blwl_bl[1416:1416] ; -assign sram_blwl_1416_configbus1[1416:1416] = sram_blwl_wl[1416:1416] ; -assign sram_blwl_1416_configbus0_b[1416:1416] = sram_blwl_blb[1416:1416] ; -sram6T_blwl sram_blwl_1416_ (sram_blwl_out[1416], sram_blwl_out[1416], sram_blwl_outb[1416], sram_blwl_1416_configbus0[1416:1416], sram_blwl_1416_configbus1[1416:1416] , sram_blwl_1416_configbus0_b[1416:1416] ); -wire [1417:1417] sram_blwl_1417_configbus0; -wire [1417:1417] sram_blwl_1417_configbus1; -wire [1417:1417] sram_blwl_1417_configbus0_b; -assign sram_blwl_1417_configbus0[1417:1417] = sram_blwl_bl[1417:1417] ; -assign sram_blwl_1417_configbus1[1417:1417] = sram_blwl_wl[1417:1417] ; -assign sram_blwl_1417_configbus0_b[1417:1417] = sram_blwl_blb[1417:1417] ; -sram6T_blwl sram_blwl_1417_ (sram_blwl_out[1417], sram_blwl_out[1417], sram_blwl_outb[1417], sram_blwl_1417_configbus0[1417:1417], sram_blwl_1417_configbus1[1417:1417] , sram_blwl_1417_configbus0_b[1417:1417] ); -wire [1418:1418] sram_blwl_1418_configbus0; -wire [1418:1418] sram_blwl_1418_configbus1; -wire [1418:1418] sram_blwl_1418_configbus0_b; -assign sram_blwl_1418_configbus0[1418:1418] = sram_blwl_bl[1418:1418] ; -assign sram_blwl_1418_configbus1[1418:1418] = sram_blwl_wl[1418:1418] ; -assign sram_blwl_1418_configbus0_b[1418:1418] = sram_blwl_blb[1418:1418] ; -sram6T_blwl sram_blwl_1418_ (sram_blwl_out[1418], sram_blwl_out[1418], sram_blwl_outb[1418], sram_blwl_1418_configbus0[1418:1418], sram_blwl_1418_configbus1[1418:1418] , sram_blwl_1418_configbus0_b[1418:1418] ); -wire [1419:1419] sram_blwl_1419_configbus0; -wire [1419:1419] sram_blwl_1419_configbus1; -wire [1419:1419] sram_blwl_1419_configbus0_b; -assign sram_blwl_1419_configbus0[1419:1419] = sram_blwl_bl[1419:1419] ; -assign sram_blwl_1419_configbus1[1419:1419] = sram_blwl_wl[1419:1419] ; -assign sram_blwl_1419_configbus0_b[1419:1419] = sram_blwl_blb[1419:1419] ; -sram6T_blwl sram_blwl_1419_ (sram_blwl_out[1419], sram_blwl_out[1419], sram_blwl_outb[1419], sram_blwl_1419_configbus0[1419:1419], sram_blwl_1419_configbus1[1419:1419] , sram_blwl_1419_configbus0_b[1419:1419] ); -wire [1420:1420] sram_blwl_1420_configbus0; -wire [1420:1420] sram_blwl_1420_configbus1; -wire [1420:1420] sram_blwl_1420_configbus0_b; -assign sram_blwl_1420_configbus0[1420:1420] = sram_blwl_bl[1420:1420] ; -assign sram_blwl_1420_configbus1[1420:1420] = sram_blwl_wl[1420:1420] ; -assign sram_blwl_1420_configbus0_b[1420:1420] = sram_blwl_blb[1420:1420] ; -sram6T_blwl sram_blwl_1420_ (sram_blwl_out[1420], sram_blwl_out[1420], sram_blwl_outb[1420], sram_blwl_1420_configbus0[1420:1420], sram_blwl_1420_configbus1[1420:1420] , sram_blwl_1420_configbus0_b[1420:1420] ); -wire [1421:1421] sram_blwl_1421_configbus0; -wire [1421:1421] sram_blwl_1421_configbus1; -wire [1421:1421] sram_blwl_1421_configbus0_b; -assign sram_blwl_1421_configbus0[1421:1421] = sram_blwl_bl[1421:1421] ; -assign sram_blwl_1421_configbus1[1421:1421] = sram_blwl_wl[1421:1421] ; -assign sram_blwl_1421_configbus0_b[1421:1421] = sram_blwl_blb[1421:1421] ; -sram6T_blwl sram_blwl_1421_ (sram_blwl_out[1421], sram_blwl_out[1421], sram_blwl_outb[1421], sram_blwl_1421_configbus0[1421:1421], sram_blwl_1421_configbus1[1421:1421] , sram_blwl_1421_configbus0_b[1421:1421] ); -wire [1422:1422] sram_blwl_1422_configbus0; -wire [1422:1422] sram_blwl_1422_configbus1; -wire [1422:1422] sram_blwl_1422_configbus0_b; -assign sram_blwl_1422_configbus0[1422:1422] = sram_blwl_bl[1422:1422] ; -assign sram_blwl_1422_configbus1[1422:1422] = sram_blwl_wl[1422:1422] ; -assign sram_blwl_1422_configbus0_b[1422:1422] = sram_blwl_blb[1422:1422] ; -sram6T_blwl sram_blwl_1422_ (sram_blwl_out[1422], sram_blwl_out[1422], sram_blwl_outb[1422], sram_blwl_1422_configbus0[1422:1422], sram_blwl_1422_configbus1[1422:1422] , sram_blwl_1422_configbus0_b[1422:1422] ); -wire [1423:1423] sram_blwl_1423_configbus0; -wire [1423:1423] sram_blwl_1423_configbus1; -wire [1423:1423] sram_blwl_1423_configbus0_b; -assign sram_blwl_1423_configbus0[1423:1423] = sram_blwl_bl[1423:1423] ; -assign sram_blwl_1423_configbus1[1423:1423] = sram_blwl_wl[1423:1423] ; -assign sram_blwl_1423_configbus0_b[1423:1423] = sram_blwl_blb[1423:1423] ; -sram6T_blwl sram_blwl_1423_ (sram_blwl_out[1423], sram_blwl_out[1423], sram_blwl_outb[1423], sram_blwl_1423_configbus0[1423:1423], sram_blwl_1423_configbus1[1423:1423] , sram_blwl_1423_configbus0_b[1423:1423] ); -wire [1424:1424] sram_blwl_1424_configbus0; -wire [1424:1424] sram_blwl_1424_configbus1; -wire [1424:1424] sram_blwl_1424_configbus0_b; -assign sram_blwl_1424_configbus0[1424:1424] = sram_blwl_bl[1424:1424] ; -assign sram_blwl_1424_configbus1[1424:1424] = sram_blwl_wl[1424:1424] ; -assign sram_blwl_1424_configbus0_b[1424:1424] = sram_blwl_blb[1424:1424] ; -sram6T_blwl sram_blwl_1424_ (sram_blwl_out[1424], sram_blwl_out[1424], sram_blwl_outb[1424], sram_blwl_1424_configbus0[1424:1424], sram_blwl_1424_configbus1[1424:1424] , sram_blwl_1424_configbus0_b[1424:1424] ); -wire [1425:1425] sram_blwl_1425_configbus0; -wire [1425:1425] sram_blwl_1425_configbus1; -wire [1425:1425] sram_blwl_1425_configbus0_b; -assign sram_blwl_1425_configbus0[1425:1425] = sram_blwl_bl[1425:1425] ; -assign sram_blwl_1425_configbus1[1425:1425] = sram_blwl_wl[1425:1425] ; -assign sram_blwl_1425_configbus0_b[1425:1425] = sram_blwl_blb[1425:1425] ; -sram6T_blwl sram_blwl_1425_ (sram_blwl_out[1425], sram_blwl_out[1425], sram_blwl_outb[1425], sram_blwl_1425_configbus0[1425:1425], sram_blwl_1425_configbus1[1425:1425] , sram_blwl_1425_configbus0_b[1425:1425] ); -wire [1426:1426] sram_blwl_1426_configbus0; -wire [1426:1426] sram_blwl_1426_configbus1; -wire [1426:1426] sram_blwl_1426_configbus0_b; -assign sram_blwl_1426_configbus0[1426:1426] = sram_blwl_bl[1426:1426] ; -assign sram_blwl_1426_configbus1[1426:1426] = sram_blwl_wl[1426:1426] ; -assign sram_blwl_1426_configbus0_b[1426:1426] = sram_blwl_blb[1426:1426] ; -sram6T_blwl sram_blwl_1426_ (sram_blwl_out[1426], sram_blwl_out[1426], sram_blwl_outb[1426], sram_blwl_1426_configbus0[1426:1426], sram_blwl_1426_configbus1[1426:1426] , sram_blwl_1426_configbus0_b[1426:1426] ); -wire [1427:1427] sram_blwl_1427_configbus0; -wire [1427:1427] sram_blwl_1427_configbus1; -wire [1427:1427] sram_blwl_1427_configbus0_b; -assign sram_blwl_1427_configbus0[1427:1427] = sram_blwl_bl[1427:1427] ; -assign sram_blwl_1427_configbus1[1427:1427] = sram_blwl_wl[1427:1427] ; -assign sram_blwl_1427_configbus0_b[1427:1427] = sram_blwl_blb[1427:1427] ; -sram6T_blwl sram_blwl_1427_ (sram_blwl_out[1427], sram_blwl_out[1427], sram_blwl_outb[1427], sram_blwl_1427_configbus0[1427:1427], sram_blwl_1427_configbus1[1427:1427] , sram_blwl_1427_configbus0_b[1427:1427] ); -wire [1428:1428] sram_blwl_1428_configbus0; -wire [1428:1428] sram_blwl_1428_configbus1; -wire [1428:1428] sram_blwl_1428_configbus0_b; -assign sram_blwl_1428_configbus0[1428:1428] = sram_blwl_bl[1428:1428] ; -assign sram_blwl_1428_configbus1[1428:1428] = sram_blwl_wl[1428:1428] ; -assign sram_blwl_1428_configbus0_b[1428:1428] = sram_blwl_blb[1428:1428] ; -sram6T_blwl sram_blwl_1428_ (sram_blwl_out[1428], sram_blwl_out[1428], sram_blwl_outb[1428], sram_blwl_1428_configbus0[1428:1428], sram_blwl_1428_configbus1[1428:1428] , sram_blwl_1428_configbus0_b[1428:1428] ); -wire [1429:1429] sram_blwl_1429_configbus0; -wire [1429:1429] sram_blwl_1429_configbus1; -wire [1429:1429] sram_blwl_1429_configbus0_b; -assign sram_blwl_1429_configbus0[1429:1429] = sram_blwl_bl[1429:1429] ; -assign sram_blwl_1429_configbus1[1429:1429] = sram_blwl_wl[1429:1429] ; -assign sram_blwl_1429_configbus0_b[1429:1429] = sram_blwl_blb[1429:1429] ; -sram6T_blwl sram_blwl_1429_ (sram_blwl_out[1429], sram_blwl_out[1429], sram_blwl_outb[1429], sram_blwl_1429_configbus0[1429:1429], sram_blwl_1429_configbus1[1429:1429] , sram_blwl_1429_configbus0_b[1429:1429] ); -wire [1430:1430] sram_blwl_1430_configbus0; -wire [1430:1430] sram_blwl_1430_configbus1; -wire [1430:1430] sram_blwl_1430_configbus0_b; -assign sram_blwl_1430_configbus0[1430:1430] = sram_blwl_bl[1430:1430] ; -assign sram_blwl_1430_configbus1[1430:1430] = sram_blwl_wl[1430:1430] ; -assign sram_blwl_1430_configbus0_b[1430:1430] = sram_blwl_blb[1430:1430] ; -sram6T_blwl sram_blwl_1430_ (sram_blwl_out[1430], sram_blwl_out[1430], sram_blwl_outb[1430], sram_blwl_1430_configbus0[1430:1430], sram_blwl_1430_configbus1[1430:1430] , sram_blwl_1430_configbus0_b[1430:1430] ); -wire [1431:1431] sram_blwl_1431_configbus0; -wire [1431:1431] sram_blwl_1431_configbus1; -wire [1431:1431] sram_blwl_1431_configbus0_b; -assign sram_blwl_1431_configbus0[1431:1431] = sram_blwl_bl[1431:1431] ; -assign sram_blwl_1431_configbus1[1431:1431] = sram_blwl_wl[1431:1431] ; -assign sram_blwl_1431_configbus0_b[1431:1431] = sram_blwl_blb[1431:1431] ; -sram6T_blwl sram_blwl_1431_ (sram_blwl_out[1431], sram_blwl_out[1431], sram_blwl_outb[1431], sram_blwl_1431_configbus0[1431:1431], sram_blwl_1431_configbus1[1431:1431] , sram_blwl_1431_configbus0_b[1431:1431] ); -wire [1432:1432] sram_blwl_1432_configbus0; -wire [1432:1432] sram_blwl_1432_configbus1; -wire [1432:1432] sram_blwl_1432_configbus0_b; -assign sram_blwl_1432_configbus0[1432:1432] = sram_blwl_bl[1432:1432] ; -assign sram_blwl_1432_configbus1[1432:1432] = sram_blwl_wl[1432:1432] ; -assign sram_blwl_1432_configbus0_b[1432:1432] = sram_blwl_blb[1432:1432] ; -sram6T_blwl sram_blwl_1432_ (sram_blwl_out[1432], sram_blwl_out[1432], sram_blwl_outb[1432], sram_blwl_1432_configbus0[1432:1432], sram_blwl_1432_configbus1[1432:1432] , sram_blwl_1432_configbus0_b[1432:1432] ); -wire [1433:1433] sram_blwl_1433_configbus0; -wire [1433:1433] sram_blwl_1433_configbus1; -wire [1433:1433] sram_blwl_1433_configbus0_b; -assign sram_blwl_1433_configbus0[1433:1433] = sram_blwl_bl[1433:1433] ; -assign sram_blwl_1433_configbus1[1433:1433] = sram_blwl_wl[1433:1433] ; -assign sram_blwl_1433_configbus0_b[1433:1433] = sram_blwl_blb[1433:1433] ; -sram6T_blwl sram_blwl_1433_ (sram_blwl_out[1433], sram_blwl_out[1433], sram_blwl_outb[1433], sram_blwl_1433_configbus0[1433:1433], sram_blwl_1433_configbus1[1433:1433] , sram_blwl_1433_configbus0_b[1433:1433] ); -wire [1434:1434] sram_blwl_1434_configbus0; -wire [1434:1434] sram_blwl_1434_configbus1; -wire [1434:1434] sram_blwl_1434_configbus0_b; -assign sram_blwl_1434_configbus0[1434:1434] = sram_blwl_bl[1434:1434] ; -assign sram_blwl_1434_configbus1[1434:1434] = sram_blwl_wl[1434:1434] ; -assign sram_blwl_1434_configbus0_b[1434:1434] = sram_blwl_blb[1434:1434] ; -sram6T_blwl sram_blwl_1434_ (sram_blwl_out[1434], sram_blwl_out[1434], sram_blwl_outb[1434], sram_blwl_1434_configbus0[1434:1434], sram_blwl_1434_configbus1[1434:1434] , sram_blwl_1434_configbus0_b[1434:1434] ); -wire [1435:1435] sram_blwl_1435_configbus0; -wire [1435:1435] sram_blwl_1435_configbus1; -wire [1435:1435] sram_blwl_1435_configbus0_b; -assign sram_blwl_1435_configbus0[1435:1435] = sram_blwl_bl[1435:1435] ; -assign sram_blwl_1435_configbus1[1435:1435] = sram_blwl_wl[1435:1435] ; -assign sram_blwl_1435_configbus0_b[1435:1435] = sram_blwl_blb[1435:1435] ; -sram6T_blwl sram_blwl_1435_ (sram_blwl_out[1435], sram_blwl_out[1435], sram_blwl_outb[1435], sram_blwl_1435_configbus0[1435:1435], sram_blwl_1435_configbus1[1435:1435] , sram_blwl_1435_configbus0_b[1435:1435] ); -wire [1436:1436] sram_blwl_1436_configbus0; -wire [1436:1436] sram_blwl_1436_configbus1; -wire [1436:1436] sram_blwl_1436_configbus0_b; -assign sram_blwl_1436_configbus0[1436:1436] = sram_blwl_bl[1436:1436] ; -assign sram_blwl_1436_configbus1[1436:1436] = sram_blwl_wl[1436:1436] ; -assign sram_blwl_1436_configbus0_b[1436:1436] = sram_blwl_blb[1436:1436] ; -sram6T_blwl sram_blwl_1436_ (sram_blwl_out[1436], sram_blwl_out[1436], sram_blwl_outb[1436], sram_blwl_1436_configbus0[1436:1436], sram_blwl_1436_configbus1[1436:1436] , sram_blwl_1436_configbus0_b[1436:1436] ); -wire [1437:1437] sram_blwl_1437_configbus0; -wire [1437:1437] sram_blwl_1437_configbus1; -wire [1437:1437] sram_blwl_1437_configbus0_b; -assign sram_blwl_1437_configbus0[1437:1437] = sram_blwl_bl[1437:1437] ; -assign sram_blwl_1437_configbus1[1437:1437] = sram_blwl_wl[1437:1437] ; -assign sram_blwl_1437_configbus0_b[1437:1437] = sram_blwl_blb[1437:1437] ; -sram6T_blwl sram_blwl_1437_ (sram_blwl_out[1437], sram_blwl_out[1437], sram_blwl_outb[1437], sram_blwl_1437_configbus0[1437:1437], sram_blwl_1437_configbus1[1437:1437] , sram_blwl_1437_configbus0_b[1437:1437] ); -wire [1438:1438] sram_blwl_1438_configbus0; -wire [1438:1438] sram_blwl_1438_configbus1; -wire [1438:1438] sram_blwl_1438_configbus0_b; -assign sram_blwl_1438_configbus0[1438:1438] = sram_blwl_bl[1438:1438] ; -assign sram_blwl_1438_configbus1[1438:1438] = sram_blwl_wl[1438:1438] ; -assign sram_blwl_1438_configbus0_b[1438:1438] = sram_blwl_blb[1438:1438] ; -sram6T_blwl sram_blwl_1438_ (sram_blwl_out[1438], sram_blwl_out[1438], sram_blwl_outb[1438], sram_blwl_1438_configbus0[1438:1438], sram_blwl_1438_configbus1[1438:1438] , sram_blwl_1438_configbus0_b[1438:1438] ); -wire [1439:1439] sram_blwl_1439_configbus0; -wire [1439:1439] sram_blwl_1439_configbus1; -wire [1439:1439] sram_blwl_1439_configbus0_b; -assign sram_blwl_1439_configbus0[1439:1439] = sram_blwl_bl[1439:1439] ; -assign sram_blwl_1439_configbus1[1439:1439] = sram_blwl_wl[1439:1439] ; -assign sram_blwl_1439_configbus0_b[1439:1439] = sram_blwl_blb[1439:1439] ; -sram6T_blwl sram_blwl_1439_ (sram_blwl_out[1439], sram_blwl_out[1439], sram_blwl_outb[1439], sram_blwl_1439_configbus0[1439:1439], sram_blwl_1439_configbus1[1439:1439] , sram_blwl_1439_configbus0_b[1439:1439] ); -wire [1440:1440] sram_blwl_1440_configbus0; -wire [1440:1440] sram_blwl_1440_configbus1; -wire [1440:1440] sram_blwl_1440_configbus0_b; -assign sram_blwl_1440_configbus0[1440:1440] = sram_blwl_bl[1440:1440] ; -assign sram_blwl_1440_configbus1[1440:1440] = sram_blwl_wl[1440:1440] ; -assign sram_blwl_1440_configbus0_b[1440:1440] = sram_blwl_blb[1440:1440] ; -sram6T_blwl sram_blwl_1440_ (sram_blwl_out[1440], sram_blwl_out[1440], sram_blwl_outb[1440], sram_blwl_1440_configbus0[1440:1440], sram_blwl_1440_configbus1[1440:1440] , sram_blwl_1440_configbus0_b[1440:1440] ); -wire [1441:1441] sram_blwl_1441_configbus0; -wire [1441:1441] sram_blwl_1441_configbus1; -wire [1441:1441] sram_blwl_1441_configbus0_b; -assign sram_blwl_1441_configbus0[1441:1441] = sram_blwl_bl[1441:1441] ; -assign sram_blwl_1441_configbus1[1441:1441] = sram_blwl_wl[1441:1441] ; -assign sram_blwl_1441_configbus0_b[1441:1441] = sram_blwl_blb[1441:1441] ; -sram6T_blwl sram_blwl_1441_ (sram_blwl_out[1441], sram_blwl_out[1441], sram_blwl_outb[1441], sram_blwl_1441_configbus0[1441:1441], sram_blwl_1441_configbus1[1441:1441] , sram_blwl_1441_configbus0_b[1441:1441] ); -wire [1442:1442] sram_blwl_1442_configbus0; -wire [1442:1442] sram_blwl_1442_configbus1; -wire [1442:1442] sram_blwl_1442_configbus0_b; -assign sram_blwl_1442_configbus0[1442:1442] = sram_blwl_bl[1442:1442] ; -assign sram_blwl_1442_configbus1[1442:1442] = sram_blwl_wl[1442:1442] ; -assign sram_blwl_1442_configbus0_b[1442:1442] = sram_blwl_blb[1442:1442] ; -sram6T_blwl sram_blwl_1442_ (sram_blwl_out[1442], sram_blwl_out[1442], sram_blwl_outb[1442], sram_blwl_1442_configbus0[1442:1442], sram_blwl_1442_configbus1[1442:1442] , sram_blwl_1442_configbus0_b[1442:1442] ); -wire [1443:1443] sram_blwl_1443_configbus0; -wire [1443:1443] sram_blwl_1443_configbus1; -wire [1443:1443] sram_blwl_1443_configbus0_b; -assign sram_blwl_1443_configbus0[1443:1443] = sram_blwl_bl[1443:1443] ; -assign sram_blwl_1443_configbus1[1443:1443] = sram_blwl_wl[1443:1443] ; -assign sram_blwl_1443_configbus0_b[1443:1443] = sram_blwl_blb[1443:1443] ; -sram6T_blwl sram_blwl_1443_ (sram_blwl_out[1443], sram_blwl_out[1443], sram_blwl_outb[1443], sram_blwl_1443_configbus0[1443:1443], sram_blwl_1443_configbus1[1443:1443] , sram_blwl_1443_configbus0_b[1443:1443] ); -wire [1444:1444] sram_blwl_1444_configbus0; -wire [1444:1444] sram_blwl_1444_configbus1; -wire [1444:1444] sram_blwl_1444_configbus0_b; -assign sram_blwl_1444_configbus0[1444:1444] = sram_blwl_bl[1444:1444] ; -assign sram_blwl_1444_configbus1[1444:1444] = sram_blwl_wl[1444:1444] ; -assign sram_blwl_1444_configbus0_b[1444:1444] = sram_blwl_blb[1444:1444] ; -sram6T_blwl sram_blwl_1444_ (sram_blwl_out[1444], sram_blwl_out[1444], sram_blwl_outb[1444], sram_blwl_1444_configbus0[1444:1444], sram_blwl_1444_configbus1[1444:1444] , sram_blwl_1444_configbus0_b[1444:1444] ); -wire [1445:1445] sram_blwl_1445_configbus0; -wire [1445:1445] sram_blwl_1445_configbus1; -wire [1445:1445] sram_blwl_1445_configbus0_b; -assign sram_blwl_1445_configbus0[1445:1445] = sram_blwl_bl[1445:1445] ; -assign sram_blwl_1445_configbus1[1445:1445] = sram_blwl_wl[1445:1445] ; -assign sram_blwl_1445_configbus0_b[1445:1445] = sram_blwl_blb[1445:1445] ; -sram6T_blwl sram_blwl_1445_ (sram_blwl_out[1445], sram_blwl_out[1445], sram_blwl_outb[1445], sram_blwl_1445_configbus0[1445:1445], sram_blwl_1445_configbus1[1445:1445] , sram_blwl_1445_configbus0_b[1445:1445] ); -wire [1446:1446] sram_blwl_1446_configbus0; -wire [1446:1446] sram_blwl_1446_configbus1; -wire [1446:1446] sram_blwl_1446_configbus0_b; -assign sram_blwl_1446_configbus0[1446:1446] = sram_blwl_bl[1446:1446] ; -assign sram_blwl_1446_configbus1[1446:1446] = sram_blwl_wl[1446:1446] ; -assign sram_blwl_1446_configbus0_b[1446:1446] = sram_blwl_blb[1446:1446] ; -sram6T_blwl sram_blwl_1446_ (sram_blwl_out[1446], sram_blwl_out[1446], sram_blwl_outb[1446], sram_blwl_1446_configbus0[1446:1446], sram_blwl_1446_configbus1[1446:1446] , sram_blwl_1446_configbus0_b[1446:1446] ); -wire [1447:1447] sram_blwl_1447_configbus0; -wire [1447:1447] sram_blwl_1447_configbus1; -wire [1447:1447] sram_blwl_1447_configbus0_b; -assign sram_blwl_1447_configbus0[1447:1447] = sram_blwl_bl[1447:1447] ; -assign sram_blwl_1447_configbus1[1447:1447] = sram_blwl_wl[1447:1447] ; -assign sram_blwl_1447_configbus0_b[1447:1447] = sram_blwl_blb[1447:1447] ; -sram6T_blwl sram_blwl_1447_ (sram_blwl_out[1447], sram_blwl_out[1447], sram_blwl_outb[1447], sram_blwl_1447_configbus0[1447:1447], sram_blwl_1447_configbus1[1447:1447] , sram_blwl_1447_configbus0_b[1447:1447] ); -wire [1448:1448] sram_blwl_1448_configbus0; -wire [1448:1448] sram_blwl_1448_configbus1; -wire [1448:1448] sram_blwl_1448_configbus0_b; -assign sram_blwl_1448_configbus0[1448:1448] = sram_blwl_bl[1448:1448] ; -assign sram_blwl_1448_configbus1[1448:1448] = sram_blwl_wl[1448:1448] ; -assign sram_blwl_1448_configbus0_b[1448:1448] = sram_blwl_blb[1448:1448] ; -sram6T_blwl sram_blwl_1448_ (sram_blwl_out[1448], sram_blwl_out[1448], sram_blwl_outb[1448], sram_blwl_1448_configbus0[1448:1448], sram_blwl_1448_configbus1[1448:1448] , sram_blwl_1448_configbus0_b[1448:1448] ); -wire [1449:1449] sram_blwl_1449_configbus0; -wire [1449:1449] sram_blwl_1449_configbus1; -wire [1449:1449] sram_blwl_1449_configbus0_b; -assign sram_blwl_1449_configbus0[1449:1449] = sram_blwl_bl[1449:1449] ; -assign sram_blwl_1449_configbus1[1449:1449] = sram_blwl_wl[1449:1449] ; -assign sram_blwl_1449_configbus0_b[1449:1449] = sram_blwl_blb[1449:1449] ; -sram6T_blwl sram_blwl_1449_ (sram_blwl_out[1449], sram_blwl_out[1449], sram_blwl_outb[1449], sram_blwl_1449_configbus0[1449:1449], sram_blwl_1449_configbus1[1449:1449] , sram_blwl_1449_configbus0_b[1449:1449] ); -wire [1450:1450] sram_blwl_1450_configbus0; -wire [1450:1450] sram_blwl_1450_configbus1; -wire [1450:1450] sram_blwl_1450_configbus0_b; -assign sram_blwl_1450_configbus0[1450:1450] = sram_blwl_bl[1450:1450] ; -assign sram_blwl_1450_configbus1[1450:1450] = sram_blwl_wl[1450:1450] ; -assign sram_blwl_1450_configbus0_b[1450:1450] = sram_blwl_blb[1450:1450] ; -sram6T_blwl sram_blwl_1450_ (sram_blwl_out[1450], sram_blwl_out[1450], sram_blwl_outb[1450], sram_blwl_1450_configbus0[1450:1450], sram_blwl_1450_configbus1[1450:1450] , sram_blwl_1450_configbus0_b[1450:1450] ); -wire [1451:1451] sram_blwl_1451_configbus0; -wire [1451:1451] sram_blwl_1451_configbus1; -wire [1451:1451] sram_blwl_1451_configbus0_b; -assign sram_blwl_1451_configbus0[1451:1451] = sram_blwl_bl[1451:1451] ; -assign sram_blwl_1451_configbus1[1451:1451] = sram_blwl_wl[1451:1451] ; -assign sram_blwl_1451_configbus0_b[1451:1451] = sram_blwl_blb[1451:1451] ; -sram6T_blwl sram_blwl_1451_ (sram_blwl_out[1451], sram_blwl_out[1451], sram_blwl_outb[1451], sram_blwl_1451_configbus0[1451:1451], sram_blwl_1451_configbus1[1451:1451] , sram_blwl_1451_configbus0_b[1451:1451] ); -wire [1452:1452] sram_blwl_1452_configbus0; -wire [1452:1452] sram_blwl_1452_configbus1; -wire [1452:1452] sram_blwl_1452_configbus0_b; -assign sram_blwl_1452_configbus0[1452:1452] = sram_blwl_bl[1452:1452] ; -assign sram_blwl_1452_configbus1[1452:1452] = sram_blwl_wl[1452:1452] ; -assign sram_blwl_1452_configbus0_b[1452:1452] = sram_blwl_blb[1452:1452] ; -sram6T_blwl sram_blwl_1452_ (sram_blwl_out[1452], sram_blwl_out[1452], sram_blwl_outb[1452], sram_blwl_1452_configbus0[1452:1452], sram_blwl_1452_configbus1[1452:1452] , sram_blwl_1452_configbus0_b[1452:1452] ); -wire [1453:1453] sram_blwl_1453_configbus0; -wire [1453:1453] sram_blwl_1453_configbus1; -wire [1453:1453] sram_blwl_1453_configbus0_b; -assign sram_blwl_1453_configbus0[1453:1453] = sram_blwl_bl[1453:1453] ; -assign sram_blwl_1453_configbus1[1453:1453] = sram_blwl_wl[1453:1453] ; -assign sram_blwl_1453_configbus0_b[1453:1453] = sram_blwl_blb[1453:1453] ; -sram6T_blwl sram_blwl_1453_ (sram_blwl_out[1453], sram_blwl_out[1453], sram_blwl_outb[1453], sram_blwl_1453_configbus0[1453:1453], sram_blwl_1453_configbus1[1453:1453] , sram_blwl_1453_configbus0_b[1453:1453] ); -wire [1454:1454] sram_blwl_1454_configbus0; -wire [1454:1454] sram_blwl_1454_configbus1; -wire [1454:1454] sram_blwl_1454_configbus0_b; -assign sram_blwl_1454_configbus0[1454:1454] = sram_blwl_bl[1454:1454] ; -assign sram_blwl_1454_configbus1[1454:1454] = sram_blwl_wl[1454:1454] ; -assign sram_blwl_1454_configbus0_b[1454:1454] = sram_blwl_blb[1454:1454] ; -sram6T_blwl sram_blwl_1454_ (sram_blwl_out[1454], sram_blwl_out[1454], sram_blwl_outb[1454], sram_blwl_1454_configbus0[1454:1454], sram_blwl_1454_configbus1[1454:1454] , sram_blwl_1454_configbus0_b[1454:1454] ); -wire [1455:1455] sram_blwl_1455_configbus0; -wire [1455:1455] sram_blwl_1455_configbus1; -wire [1455:1455] sram_blwl_1455_configbus0_b; -assign sram_blwl_1455_configbus0[1455:1455] = sram_blwl_bl[1455:1455] ; -assign sram_blwl_1455_configbus1[1455:1455] = sram_blwl_wl[1455:1455] ; -assign sram_blwl_1455_configbus0_b[1455:1455] = sram_blwl_blb[1455:1455] ; -sram6T_blwl sram_blwl_1455_ (sram_blwl_out[1455], sram_blwl_out[1455], sram_blwl_outb[1455], sram_blwl_1455_configbus0[1455:1455], sram_blwl_1455_configbus1[1455:1455] , sram_blwl_1455_configbus0_b[1455:1455] ); -wire [1456:1456] sram_blwl_1456_configbus0; -wire [1456:1456] sram_blwl_1456_configbus1; -wire [1456:1456] sram_blwl_1456_configbus0_b; -assign sram_blwl_1456_configbus0[1456:1456] = sram_blwl_bl[1456:1456] ; -assign sram_blwl_1456_configbus1[1456:1456] = sram_blwl_wl[1456:1456] ; -assign sram_blwl_1456_configbus0_b[1456:1456] = sram_blwl_blb[1456:1456] ; -sram6T_blwl sram_blwl_1456_ (sram_blwl_out[1456], sram_blwl_out[1456], sram_blwl_outb[1456], sram_blwl_1456_configbus0[1456:1456], sram_blwl_1456_configbus1[1456:1456] , sram_blwl_1456_configbus0_b[1456:1456] ); -wire [1457:1457] sram_blwl_1457_configbus0; -wire [1457:1457] sram_blwl_1457_configbus1; -wire [1457:1457] sram_blwl_1457_configbus0_b; -assign sram_blwl_1457_configbus0[1457:1457] = sram_blwl_bl[1457:1457] ; -assign sram_blwl_1457_configbus1[1457:1457] = sram_blwl_wl[1457:1457] ; -assign sram_blwl_1457_configbus0_b[1457:1457] = sram_blwl_blb[1457:1457] ; -sram6T_blwl sram_blwl_1457_ (sram_blwl_out[1457], sram_blwl_out[1457], sram_blwl_outb[1457], sram_blwl_1457_configbus0[1457:1457], sram_blwl_1457_configbus1[1457:1457] , sram_blwl_1457_configbus0_b[1457:1457] ); -wire [1458:1458] sram_blwl_1458_configbus0; -wire [1458:1458] sram_blwl_1458_configbus1; -wire [1458:1458] sram_blwl_1458_configbus0_b; -assign sram_blwl_1458_configbus0[1458:1458] = sram_blwl_bl[1458:1458] ; -assign sram_blwl_1458_configbus1[1458:1458] = sram_blwl_wl[1458:1458] ; -assign sram_blwl_1458_configbus0_b[1458:1458] = sram_blwl_blb[1458:1458] ; -sram6T_blwl sram_blwl_1458_ (sram_blwl_out[1458], sram_blwl_out[1458], sram_blwl_outb[1458], sram_blwl_1458_configbus0[1458:1458], sram_blwl_1458_configbus1[1458:1458] , sram_blwl_1458_configbus0_b[1458:1458] ); -wire [1459:1459] sram_blwl_1459_configbus0; -wire [1459:1459] sram_blwl_1459_configbus1; -wire [1459:1459] sram_blwl_1459_configbus0_b; -assign sram_blwl_1459_configbus0[1459:1459] = sram_blwl_bl[1459:1459] ; -assign sram_blwl_1459_configbus1[1459:1459] = sram_blwl_wl[1459:1459] ; -assign sram_blwl_1459_configbus0_b[1459:1459] = sram_blwl_blb[1459:1459] ; -sram6T_blwl sram_blwl_1459_ (sram_blwl_out[1459], sram_blwl_out[1459], sram_blwl_outb[1459], sram_blwl_1459_configbus0[1459:1459], sram_blwl_1459_configbus1[1459:1459] , sram_blwl_1459_configbus0_b[1459:1459] ); -wire [1460:1460] sram_blwl_1460_configbus0; -wire [1460:1460] sram_blwl_1460_configbus1; -wire [1460:1460] sram_blwl_1460_configbus0_b; -assign sram_blwl_1460_configbus0[1460:1460] = sram_blwl_bl[1460:1460] ; -assign sram_blwl_1460_configbus1[1460:1460] = sram_blwl_wl[1460:1460] ; -assign sram_blwl_1460_configbus0_b[1460:1460] = sram_blwl_blb[1460:1460] ; -sram6T_blwl sram_blwl_1460_ (sram_blwl_out[1460], sram_blwl_out[1460], sram_blwl_outb[1460], sram_blwl_1460_configbus0[1460:1460], sram_blwl_1460_configbus1[1460:1460] , sram_blwl_1460_configbus0_b[1460:1460] ); -wire [1461:1461] sram_blwl_1461_configbus0; -wire [1461:1461] sram_blwl_1461_configbus1; -wire [1461:1461] sram_blwl_1461_configbus0_b; -assign sram_blwl_1461_configbus0[1461:1461] = sram_blwl_bl[1461:1461] ; -assign sram_blwl_1461_configbus1[1461:1461] = sram_blwl_wl[1461:1461] ; -assign sram_blwl_1461_configbus0_b[1461:1461] = sram_blwl_blb[1461:1461] ; -sram6T_blwl sram_blwl_1461_ (sram_blwl_out[1461], sram_blwl_out[1461], sram_blwl_outb[1461], sram_blwl_1461_configbus0[1461:1461], sram_blwl_1461_configbus1[1461:1461] , sram_blwl_1461_configbus0_b[1461:1461] ); -wire [1462:1462] sram_blwl_1462_configbus0; -wire [1462:1462] sram_blwl_1462_configbus1; -wire [1462:1462] sram_blwl_1462_configbus0_b; -assign sram_blwl_1462_configbus0[1462:1462] = sram_blwl_bl[1462:1462] ; -assign sram_blwl_1462_configbus1[1462:1462] = sram_blwl_wl[1462:1462] ; -assign sram_blwl_1462_configbus0_b[1462:1462] = sram_blwl_blb[1462:1462] ; -sram6T_blwl sram_blwl_1462_ (sram_blwl_out[1462], sram_blwl_out[1462], sram_blwl_outb[1462], sram_blwl_1462_configbus0[1462:1462], sram_blwl_1462_configbus1[1462:1462] , sram_blwl_1462_configbus0_b[1462:1462] ); -wire [1463:1463] sram_blwl_1463_configbus0; -wire [1463:1463] sram_blwl_1463_configbus1; -wire [1463:1463] sram_blwl_1463_configbus0_b; -assign sram_blwl_1463_configbus0[1463:1463] = sram_blwl_bl[1463:1463] ; -assign sram_blwl_1463_configbus1[1463:1463] = sram_blwl_wl[1463:1463] ; -assign sram_blwl_1463_configbus0_b[1463:1463] = sram_blwl_blb[1463:1463] ; -sram6T_blwl sram_blwl_1463_ (sram_blwl_out[1463], sram_blwl_out[1463], sram_blwl_outb[1463], sram_blwl_1463_configbus0[1463:1463], sram_blwl_1463_configbus1[1463:1463] , sram_blwl_1463_configbus0_b[1463:1463] ); -wire [1464:1464] sram_blwl_1464_configbus0; -wire [1464:1464] sram_blwl_1464_configbus1; -wire [1464:1464] sram_blwl_1464_configbus0_b; -assign sram_blwl_1464_configbus0[1464:1464] = sram_blwl_bl[1464:1464] ; -assign sram_blwl_1464_configbus1[1464:1464] = sram_blwl_wl[1464:1464] ; -assign sram_blwl_1464_configbus0_b[1464:1464] = sram_blwl_blb[1464:1464] ; -sram6T_blwl sram_blwl_1464_ (sram_blwl_out[1464], sram_blwl_out[1464], sram_blwl_outb[1464], sram_blwl_1464_configbus0[1464:1464], sram_blwl_1464_configbus1[1464:1464] , sram_blwl_1464_configbus0_b[1464:1464] ); -wire [1465:1465] sram_blwl_1465_configbus0; -wire [1465:1465] sram_blwl_1465_configbus1; -wire [1465:1465] sram_blwl_1465_configbus0_b; -assign sram_blwl_1465_configbus0[1465:1465] = sram_blwl_bl[1465:1465] ; -assign sram_blwl_1465_configbus1[1465:1465] = sram_blwl_wl[1465:1465] ; -assign sram_blwl_1465_configbus0_b[1465:1465] = sram_blwl_blb[1465:1465] ; -sram6T_blwl sram_blwl_1465_ (sram_blwl_out[1465], sram_blwl_out[1465], sram_blwl_outb[1465], sram_blwl_1465_configbus0[1465:1465], sram_blwl_1465_configbus1[1465:1465] , sram_blwl_1465_configbus0_b[1465:1465] ); -wire [1466:1466] sram_blwl_1466_configbus0; -wire [1466:1466] sram_blwl_1466_configbus1; -wire [1466:1466] sram_blwl_1466_configbus0_b; -assign sram_blwl_1466_configbus0[1466:1466] = sram_blwl_bl[1466:1466] ; -assign sram_blwl_1466_configbus1[1466:1466] = sram_blwl_wl[1466:1466] ; -assign sram_blwl_1466_configbus0_b[1466:1466] = sram_blwl_blb[1466:1466] ; -sram6T_blwl sram_blwl_1466_ (sram_blwl_out[1466], sram_blwl_out[1466], sram_blwl_outb[1466], sram_blwl_1466_configbus0[1466:1466], sram_blwl_1466_configbus1[1466:1466] , sram_blwl_1466_configbus0_b[1466:1466] ); -wire [1467:1467] sram_blwl_1467_configbus0; -wire [1467:1467] sram_blwl_1467_configbus1; -wire [1467:1467] sram_blwl_1467_configbus0_b; -assign sram_blwl_1467_configbus0[1467:1467] = sram_blwl_bl[1467:1467] ; -assign sram_blwl_1467_configbus1[1467:1467] = sram_blwl_wl[1467:1467] ; -assign sram_blwl_1467_configbus0_b[1467:1467] = sram_blwl_blb[1467:1467] ; -sram6T_blwl sram_blwl_1467_ (sram_blwl_out[1467], sram_blwl_out[1467], sram_blwl_outb[1467], sram_blwl_1467_configbus0[1467:1467], sram_blwl_1467_configbus1[1467:1467] , sram_blwl_1467_configbus0_b[1467:1467] ); -wire [1468:1468] sram_blwl_1468_configbus0; -wire [1468:1468] sram_blwl_1468_configbus1; -wire [1468:1468] sram_blwl_1468_configbus0_b; -assign sram_blwl_1468_configbus0[1468:1468] = sram_blwl_bl[1468:1468] ; -assign sram_blwl_1468_configbus1[1468:1468] = sram_blwl_wl[1468:1468] ; -assign sram_blwl_1468_configbus0_b[1468:1468] = sram_blwl_blb[1468:1468] ; -sram6T_blwl sram_blwl_1468_ (sram_blwl_out[1468], sram_blwl_out[1468], sram_blwl_outb[1468], sram_blwl_1468_configbus0[1468:1468], sram_blwl_1468_configbus1[1468:1468] , sram_blwl_1468_configbus0_b[1468:1468] ); -wire [1469:1469] sram_blwl_1469_configbus0; -wire [1469:1469] sram_blwl_1469_configbus1; -wire [1469:1469] sram_blwl_1469_configbus0_b; -assign sram_blwl_1469_configbus0[1469:1469] = sram_blwl_bl[1469:1469] ; -assign sram_blwl_1469_configbus1[1469:1469] = sram_blwl_wl[1469:1469] ; -assign sram_blwl_1469_configbus0_b[1469:1469] = sram_blwl_blb[1469:1469] ; -sram6T_blwl sram_blwl_1469_ (sram_blwl_out[1469], sram_blwl_out[1469], sram_blwl_outb[1469], sram_blwl_1469_configbus0[1469:1469], sram_blwl_1469_configbus1[1469:1469] , sram_blwl_1469_configbus0_b[1469:1469] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- - -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_6_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6_ ----- -module grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble6___in_0_, -input wire mode_ble6___in_1_, -input wire mode_ble6___in_2_, -input wire mode_ble6___in_3_, -input wire mode_ble6___in_4_, -input wire mode_ble6___in_5_, -output wire mode_ble6___out_0_, -input wire mode_ble6___clk_0_, -input [1406:1470] sram_blwl_bl , -input [1406:1470] sram_blwl_wl , -input [1406:1470] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ lut6_0_ ( - lut6_0___in_0_, lut6_0___in_1_, lut6_0___in_2_, lut6_0___in_3_, lut6_0___in_4_, lut6_0___in_5_, lut6_0___out_0_, -sram_blwl_bl[1406:1469] , -sram_blwl_wl[1406:1469] , -sram_blwl_blb[1406:1469] ); -grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_406_ ; -assign in_bus_mux_1level_tapbuf_size2_406_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_406_[1] = lut6_0___out_0_ ; -wire [1470:1470] mux_1level_tapbuf_size2_406_configbus0; -wire [1470:1470] mux_1level_tapbuf_size2_406_configbus1; -wire [1470:1470] mux_1level_tapbuf_size2_406_sram_blwl_out ; -wire [1470:1470] mux_1level_tapbuf_size2_406_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_406_configbus0[1470:1470] = sram_blwl_bl[1470:1470] ; -assign mux_1level_tapbuf_size2_406_configbus1[1470:1470] = sram_blwl_wl[1470:1470] ; -wire [1470:1470] mux_1level_tapbuf_size2_406_configbus0_b; -assign mux_1level_tapbuf_size2_406_configbus0_b[1470:1470] = sram_blwl_blb[1470:1470] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_406_ (in_bus_mux_1level_tapbuf_size2_406_, mode_ble6___out_0_, mux_1level_tapbuf_size2_406_sram_blwl_out[1470:1470] , -mux_1level_tapbuf_size2_406_sram_blwl_outb[1470:1470] ); -//----- SRAM bits for MUX[406], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1470_ (mux_1level_tapbuf_size2_406_sram_blwl_out[1470:1470] ,mux_1level_tapbuf_size2_406_sram_blwl_out[1470:1470] ,mux_1level_tapbuf_size2_406_sram_blwl_outb[1470:1470] ,mux_1level_tapbuf_size2_406_configbus0[1470:1470], mux_1level_tapbuf_size2_406_configbus1[1470:1470] , mux_1level_tapbuf_size2_406_configbus0_b[1470:1470] ); -direct_interc direct_interc_96_ (mode_ble6___in_0_, lut6_0___in_0_ ); -direct_interc direct_interc_97_ (mode_ble6___in_1_, lut6_0___in_1_ ); -direct_interc direct_interc_98_ (mode_ble6___in_2_, lut6_0___in_2_ ); -direct_interc direct_interc_99_ (mode_ble6___in_3_, lut6_0___in_3_ ); -direct_interc direct_interc_100_ (mode_ble6___in_4_, lut6_0___in_4_ ); -direct_interc direct_interc_101_ (mode_ble6___in_5_, lut6_0___in_5_ ); -direct_interc direct_interc_102_ (lut6_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_103_ (mode_ble6___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6_ ----- -module grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut6___in_0_, -input wire mode_n1_lut6___in_1_, -input wire mode_n1_lut6___in_2_, -input wire mode_n1_lut6___in_3_, -input wire mode_n1_lut6___in_4_, -input wire mode_n1_lut6___in_5_, -output wire mode_n1_lut6___out_0_, -input wire mode_n1_lut6___clk_0_, -input [1406:1470] sram_blwl_bl , -input [1406:1470] sram_blwl_wl , -input [1406:1470] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6__ble6_0__mode_ble6_ ble6_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble6_0___in_0_, ble6_0___in_1_, ble6_0___in_2_, ble6_0___in_3_, ble6_0___in_4_, ble6_0___in_5_, ble6_0___out_0_, ble6_0___clk_0_, -sram_blwl_bl[1406:1470] , -sram_blwl_wl[1406:1470] , -sram_blwl_blb[1406:1470] ); -direct_interc direct_interc_104_ (ble6_0___out_0_, mode_n1_lut6___out_0_ ); -direct_interc direct_interc_105_ (mode_n1_lut6___in_0_, ble6_0___in_0_ ); -direct_interc direct_interc_106_ (mode_n1_lut6___in_1_, ble6_0___in_1_ ); -direct_interc direct_interc_107_ (mode_n1_lut6___in_2_, ble6_0___in_2_ ); -direct_interc direct_interc_108_ (mode_n1_lut6___in_3_, ble6_0___in_3_ ); -direct_interc direct_interc_109_ (mode_n1_lut6___in_4_, ble6_0___in_4_ ); -direct_interc direct_interc_110_ (mode_n1_lut6___in_5_, ble6_0___in_5_ ); -direct_interc direct_interc_111_ (mode_n1_lut6___clk_0_, ble6_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6_ ----- - -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ( -input wire lut6_0___in_0_, -input wire lut6_0___in_1_, -input wire lut6_0___in_2_, -input wire lut6_0___in_3_, -input wire lut6_0___in_4_, -input wire lut6_0___in_5_, -output wire lut6_0___out_0_, -input [1471:1534] sram_blwl_bl , -input [1471:1534] sram_blwl_wl , -input [1471:1534] sram_blwl_blb ); -wire [0:5] lut6_0___in; -assign lut6_0___in[0] = lut6_0___in_0_; -assign lut6_0___in[1] = lut6_0___in_1_; -assign lut6_0___in[2] = lut6_0___in_2_; -assign lut6_0___in[3] = lut6_0___in_3_; -assign lut6_0___in[4] = lut6_0___in_4_; -assign lut6_0___in[5] = lut6_0___in_5_; -wire [0:0] lut6_0___out; -assign lut6_0___out_0_ = lut6_0___out[0]; -wire [1471:1534] sram_blwl_out ; -wire [1471:1534] sram_blwl_outb ; -lut6 lut6_7_ ( -//----- Input and output ports ----- - lut6_0___in[0:5] , lut6_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[1471:1534] , sram_blwl_outb[1471:1534] ); -//----- Truth Table for LUT[7], size=6. ----- -//----- SRAM bits for LUT[7], size=6, num_sram=64. ----- -//-----0000000000000000000000000000000000000000000000000000000000000000----- -wire [1471:1471] sram_blwl_1471_configbus0; -wire [1471:1471] sram_blwl_1471_configbus1; -wire [1471:1471] sram_blwl_1471_configbus0_b; -assign sram_blwl_1471_configbus0[1471:1471] = sram_blwl_bl[1471:1471] ; -assign sram_blwl_1471_configbus1[1471:1471] = sram_blwl_wl[1471:1471] ; -assign sram_blwl_1471_configbus0_b[1471:1471] = sram_blwl_blb[1471:1471] ; -sram6T_blwl sram_blwl_1471_ (sram_blwl_out[1471], sram_blwl_out[1471], sram_blwl_outb[1471], sram_blwl_1471_configbus0[1471:1471], sram_blwl_1471_configbus1[1471:1471] , sram_blwl_1471_configbus0_b[1471:1471] ); -wire [1472:1472] sram_blwl_1472_configbus0; -wire [1472:1472] sram_blwl_1472_configbus1; -wire [1472:1472] sram_blwl_1472_configbus0_b; -assign sram_blwl_1472_configbus0[1472:1472] = sram_blwl_bl[1472:1472] ; -assign sram_blwl_1472_configbus1[1472:1472] = sram_blwl_wl[1472:1472] ; -assign sram_blwl_1472_configbus0_b[1472:1472] = sram_blwl_blb[1472:1472] ; -sram6T_blwl sram_blwl_1472_ (sram_blwl_out[1472], sram_blwl_out[1472], sram_blwl_outb[1472], sram_blwl_1472_configbus0[1472:1472], sram_blwl_1472_configbus1[1472:1472] , sram_blwl_1472_configbus0_b[1472:1472] ); -wire [1473:1473] sram_blwl_1473_configbus0; -wire [1473:1473] sram_blwl_1473_configbus1; -wire [1473:1473] sram_blwl_1473_configbus0_b; -assign sram_blwl_1473_configbus0[1473:1473] = sram_blwl_bl[1473:1473] ; -assign sram_blwl_1473_configbus1[1473:1473] = sram_blwl_wl[1473:1473] ; -assign sram_blwl_1473_configbus0_b[1473:1473] = sram_blwl_blb[1473:1473] ; -sram6T_blwl sram_blwl_1473_ (sram_blwl_out[1473], sram_blwl_out[1473], sram_blwl_outb[1473], sram_blwl_1473_configbus0[1473:1473], sram_blwl_1473_configbus1[1473:1473] , sram_blwl_1473_configbus0_b[1473:1473] ); -wire [1474:1474] sram_blwl_1474_configbus0; -wire [1474:1474] sram_blwl_1474_configbus1; -wire [1474:1474] sram_blwl_1474_configbus0_b; -assign sram_blwl_1474_configbus0[1474:1474] = sram_blwl_bl[1474:1474] ; -assign sram_blwl_1474_configbus1[1474:1474] = sram_blwl_wl[1474:1474] ; -assign sram_blwl_1474_configbus0_b[1474:1474] = sram_blwl_blb[1474:1474] ; -sram6T_blwl sram_blwl_1474_ (sram_blwl_out[1474], sram_blwl_out[1474], sram_blwl_outb[1474], sram_blwl_1474_configbus0[1474:1474], sram_blwl_1474_configbus1[1474:1474] , sram_blwl_1474_configbus0_b[1474:1474] ); -wire [1475:1475] sram_blwl_1475_configbus0; -wire [1475:1475] sram_blwl_1475_configbus1; -wire [1475:1475] sram_blwl_1475_configbus0_b; -assign sram_blwl_1475_configbus0[1475:1475] = sram_blwl_bl[1475:1475] ; -assign sram_blwl_1475_configbus1[1475:1475] = sram_blwl_wl[1475:1475] ; -assign sram_blwl_1475_configbus0_b[1475:1475] = sram_blwl_blb[1475:1475] ; -sram6T_blwl sram_blwl_1475_ (sram_blwl_out[1475], sram_blwl_out[1475], sram_blwl_outb[1475], sram_blwl_1475_configbus0[1475:1475], sram_blwl_1475_configbus1[1475:1475] , sram_blwl_1475_configbus0_b[1475:1475] ); -wire [1476:1476] sram_blwl_1476_configbus0; -wire [1476:1476] sram_blwl_1476_configbus1; -wire [1476:1476] sram_blwl_1476_configbus0_b; -assign sram_blwl_1476_configbus0[1476:1476] = sram_blwl_bl[1476:1476] ; -assign sram_blwl_1476_configbus1[1476:1476] = sram_blwl_wl[1476:1476] ; -assign sram_blwl_1476_configbus0_b[1476:1476] = sram_blwl_blb[1476:1476] ; -sram6T_blwl sram_blwl_1476_ (sram_blwl_out[1476], sram_blwl_out[1476], sram_blwl_outb[1476], sram_blwl_1476_configbus0[1476:1476], sram_blwl_1476_configbus1[1476:1476] , sram_blwl_1476_configbus0_b[1476:1476] ); -wire [1477:1477] sram_blwl_1477_configbus0; -wire [1477:1477] sram_blwl_1477_configbus1; -wire [1477:1477] sram_blwl_1477_configbus0_b; -assign sram_blwl_1477_configbus0[1477:1477] = sram_blwl_bl[1477:1477] ; -assign sram_blwl_1477_configbus1[1477:1477] = sram_blwl_wl[1477:1477] ; -assign sram_blwl_1477_configbus0_b[1477:1477] = sram_blwl_blb[1477:1477] ; -sram6T_blwl sram_blwl_1477_ (sram_blwl_out[1477], sram_blwl_out[1477], sram_blwl_outb[1477], sram_blwl_1477_configbus0[1477:1477], sram_blwl_1477_configbus1[1477:1477] , sram_blwl_1477_configbus0_b[1477:1477] ); -wire [1478:1478] sram_blwl_1478_configbus0; -wire [1478:1478] sram_blwl_1478_configbus1; -wire [1478:1478] sram_blwl_1478_configbus0_b; -assign sram_blwl_1478_configbus0[1478:1478] = sram_blwl_bl[1478:1478] ; -assign sram_blwl_1478_configbus1[1478:1478] = sram_blwl_wl[1478:1478] ; -assign sram_blwl_1478_configbus0_b[1478:1478] = sram_blwl_blb[1478:1478] ; -sram6T_blwl sram_blwl_1478_ (sram_blwl_out[1478], sram_blwl_out[1478], sram_blwl_outb[1478], sram_blwl_1478_configbus0[1478:1478], sram_blwl_1478_configbus1[1478:1478] , sram_blwl_1478_configbus0_b[1478:1478] ); -wire [1479:1479] sram_blwl_1479_configbus0; -wire [1479:1479] sram_blwl_1479_configbus1; -wire [1479:1479] sram_blwl_1479_configbus0_b; -assign sram_blwl_1479_configbus0[1479:1479] = sram_blwl_bl[1479:1479] ; -assign sram_blwl_1479_configbus1[1479:1479] = sram_blwl_wl[1479:1479] ; -assign sram_blwl_1479_configbus0_b[1479:1479] = sram_blwl_blb[1479:1479] ; -sram6T_blwl sram_blwl_1479_ (sram_blwl_out[1479], sram_blwl_out[1479], sram_blwl_outb[1479], sram_blwl_1479_configbus0[1479:1479], sram_blwl_1479_configbus1[1479:1479] , sram_blwl_1479_configbus0_b[1479:1479] ); -wire [1480:1480] sram_blwl_1480_configbus0; -wire [1480:1480] sram_blwl_1480_configbus1; -wire [1480:1480] sram_blwl_1480_configbus0_b; -assign sram_blwl_1480_configbus0[1480:1480] = sram_blwl_bl[1480:1480] ; -assign sram_blwl_1480_configbus1[1480:1480] = sram_blwl_wl[1480:1480] ; -assign sram_blwl_1480_configbus0_b[1480:1480] = sram_blwl_blb[1480:1480] ; -sram6T_blwl sram_blwl_1480_ (sram_blwl_out[1480], sram_blwl_out[1480], sram_blwl_outb[1480], sram_blwl_1480_configbus0[1480:1480], sram_blwl_1480_configbus1[1480:1480] , sram_blwl_1480_configbus0_b[1480:1480] ); -wire [1481:1481] sram_blwl_1481_configbus0; -wire [1481:1481] sram_blwl_1481_configbus1; -wire [1481:1481] sram_blwl_1481_configbus0_b; -assign sram_blwl_1481_configbus0[1481:1481] = sram_blwl_bl[1481:1481] ; -assign sram_blwl_1481_configbus1[1481:1481] = sram_blwl_wl[1481:1481] ; -assign sram_blwl_1481_configbus0_b[1481:1481] = sram_blwl_blb[1481:1481] ; -sram6T_blwl sram_blwl_1481_ (sram_blwl_out[1481], sram_blwl_out[1481], sram_blwl_outb[1481], sram_blwl_1481_configbus0[1481:1481], sram_blwl_1481_configbus1[1481:1481] , sram_blwl_1481_configbus0_b[1481:1481] ); -wire [1482:1482] sram_blwl_1482_configbus0; -wire [1482:1482] sram_blwl_1482_configbus1; -wire [1482:1482] sram_blwl_1482_configbus0_b; -assign sram_blwl_1482_configbus0[1482:1482] = sram_blwl_bl[1482:1482] ; -assign sram_blwl_1482_configbus1[1482:1482] = sram_blwl_wl[1482:1482] ; -assign sram_blwl_1482_configbus0_b[1482:1482] = sram_blwl_blb[1482:1482] ; -sram6T_blwl sram_blwl_1482_ (sram_blwl_out[1482], sram_blwl_out[1482], sram_blwl_outb[1482], sram_blwl_1482_configbus0[1482:1482], sram_blwl_1482_configbus1[1482:1482] , sram_blwl_1482_configbus0_b[1482:1482] ); -wire [1483:1483] sram_blwl_1483_configbus0; -wire [1483:1483] sram_blwl_1483_configbus1; -wire [1483:1483] sram_blwl_1483_configbus0_b; -assign sram_blwl_1483_configbus0[1483:1483] = sram_blwl_bl[1483:1483] ; -assign sram_blwl_1483_configbus1[1483:1483] = sram_blwl_wl[1483:1483] ; -assign sram_blwl_1483_configbus0_b[1483:1483] = sram_blwl_blb[1483:1483] ; -sram6T_blwl sram_blwl_1483_ (sram_blwl_out[1483], sram_blwl_out[1483], sram_blwl_outb[1483], sram_blwl_1483_configbus0[1483:1483], sram_blwl_1483_configbus1[1483:1483] , sram_blwl_1483_configbus0_b[1483:1483] ); -wire [1484:1484] sram_blwl_1484_configbus0; -wire [1484:1484] sram_blwl_1484_configbus1; -wire [1484:1484] sram_blwl_1484_configbus0_b; -assign sram_blwl_1484_configbus0[1484:1484] = sram_blwl_bl[1484:1484] ; -assign sram_blwl_1484_configbus1[1484:1484] = sram_blwl_wl[1484:1484] ; -assign sram_blwl_1484_configbus0_b[1484:1484] = sram_blwl_blb[1484:1484] ; -sram6T_blwl sram_blwl_1484_ (sram_blwl_out[1484], sram_blwl_out[1484], sram_blwl_outb[1484], sram_blwl_1484_configbus0[1484:1484], sram_blwl_1484_configbus1[1484:1484] , sram_blwl_1484_configbus0_b[1484:1484] ); -wire [1485:1485] sram_blwl_1485_configbus0; -wire [1485:1485] sram_blwl_1485_configbus1; -wire [1485:1485] sram_blwl_1485_configbus0_b; -assign sram_blwl_1485_configbus0[1485:1485] = sram_blwl_bl[1485:1485] ; -assign sram_blwl_1485_configbus1[1485:1485] = sram_blwl_wl[1485:1485] ; -assign sram_blwl_1485_configbus0_b[1485:1485] = sram_blwl_blb[1485:1485] ; -sram6T_blwl sram_blwl_1485_ (sram_blwl_out[1485], sram_blwl_out[1485], sram_blwl_outb[1485], sram_blwl_1485_configbus0[1485:1485], sram_blwl_1485_configbus1[1485:1485] , sram_blwl_1485_configbus0_b[1485:1485] ); -wire [1486:1486] sram_blwl_1486_configbus0; -wire [1486:1486] sram_blwl_1486_configbus1; -wire [1486:1486] sram_blwl_1486_configbus0_b; -assign sram_blwl_1486_configbus0[1486:1486] = sram_blwl_bl[1486:1486] ; -assign sram_blwl_1486_configbus1[1486:1486] = sram_blwl_wl[1486:1486] ; -assign sram_blwl_1486_configbus0_b[1486:1486] = sram_blwl_blb[1486:1486] ; -sram6T_blwl sram_blwl_1486_ (sram_blwl_out[1486], sram_blwl_out[1486], sram_blwl_outb[1486], sram_blwl_1486_configbus0[1486:1486], sram_blwl_1486_configbus1[1486:1486] , sram_blwl_1486_configbus0_b[1486:1486] ); -wire [1487:1487] sram_blwl_1487_configbus0; -wire [1487:1487] sram_blwl_1487_configbus1; -wire [1487:1487] sram_blwl_1487_configbus0_b; -assign sram_blwl_1487_configbus0[1487:1487] = sram_blwl_bl[1487:1487] ; -assign sram_blwl_1487_configbus1[1487:1487] = sram_blwl_wl[1487:1487] ; -assign sram_blwl_1487_configbus0_b[1487:1487] = sram_blwl_blb[1487:1487] ; -sram6T_blwl sram_blwl_1487_ (sram_blwl_out[1487], sram_blwl_out[1487], sram_blwl_outb[1487], sram_blwl_1487_configbus0[1487:1487], sram_blwl_1487_configbus1[1487:1487] , sram_blwl_1487_configbus0_b[1487:1487] ); -wire [1488:1488] sram_blwl_1488_configbus0; -wire [1488:1488] sram_blwl_1488_configbus1; -wire [1488:1488] sram_blwl_1488_configbus0_b; -assign sram_blwl_1488_configbus0[1488:1488] = sram_blwl_bl[1488:1488] ; -assign sram_blwl_1488_configbus1[1488:1488] = sram_blwl_wl[1488:1488] ; -assign sram_blwl_1488_configbus0_b[1488:1488] = sram_blwl_blb[1488:1488] ; -sram6T_blwl sram_blwl_1488_ (sram_blwl_out[1488], sram_blwl_out[1488], sram_blwl_outb[1488], sram_blwl_1488_configbus0[1488:1488], sram_blwl_1488_configbus1[1488:1488] , sram_blwl_1488_configbus0_b[1488:1488] ); -wire [1489:1489] sram_blwl_1489_configbus0; -wire [1489:1489] sram_blwl_1489_configbus1; -wire [1489:1489] sram_blwl_1489_configbus0_b; -assign sram_blwl_1489_configbus0[1489:1489] = sram_blwl_bl[1489:1489] ; -assign sram_blwl_1489_configbus1[1489:1489] = sram_blwl_wl[1489:1489] ; -assign sram_blwl_1489_configbus0_b[1489:1489] = sram_blwl_blb[1489:1489] ; -sram6T_blwl sram_blwl_1489_ (sram_blwl_out[1489], sram_blwl_out[1489], sram_blwl_outb[1489], sram_blwl_1489_configbus0[1489:1489], sram_blwl_1489_configbus1[1489:1489] , sram_blwl_1489_configbus0_b[1489:1489] ); -wire [1490:1490] sram_blwl_1490_configbus0; -wire [1490:1490] sram_blwl_1490_configbus1; -wire [1490:1490] sram_blwl_1490_configbus0_b; -assign sram_blwl_1490_configbus0[1490:1490] = sram_blwl_bl[1490:1490] ; -assign sram_blwl_1490_configbus1[1490:1490] = sram_blwl_wl[1490:1490] ; -assign sram_blwl_1490_configbus0_b[1490:1490] = sram_blwl_blb[1490:1490] ; -sram6T_blwl sram_blwl_1490_ (sram_blwl_out[1490], sram_blwl_out[1490], sram_blwl_outb[1490], sram_blwl_1490_configbus0[1490:1490], sram_blwl_1490_configbus1[1490:1490] , sram_blwl_1490_configbus0_b[1490:1490] ); -wire [1491:1491] sram_blwl_1491_configbus0; -wire [1491:1491] sram_blwl_1491_configbus1; -wire [1491:1491] sram_blwl_1491_configbus0_b; -assign sram_blwl_1491_configbus0[1491:1491] = sram_blwl_bl[1491:1491] ; -assign sram_blwl_1491_configbus1[1491:1491] = sram_blwl_wl[1491:1491] ; -assign sram_blwl_1491_configbus0_b[1491:1491] = sram_blwl_blb[1491:1491] ; -sram6T_blwl sram_blwl_1491_ (sram_blwl_out[1491], sram_blwl_out[1491], sram_blwl_outb[1491], sram_blwl_1491_configbus0[1491:1491], sram_blwl_1491_configbus1[1491:1491] , sram_blwl_1491_configbus0_b[1491:1491] ); -wire [1492:1492] sram_blwl_1492_configbus0; -wire [1492:1492] sram_blwl_1492_configbus1; -wire [1492:1492] sram_blwl_1492_configbus0_b; -assign sram_blwl_1492_configbus0[1492:1492] = sram_blwl_bl[1492:1492] ; -assign sram_blwl_1492_configbus1[1492:1492] = sram_blwl_wl[1492:1492] ; -assign sram_blwl_1492_configbus0_b[1492:1492] = sram_blwl_blb[1492:1492] ; -sram6T_blwl sram_blwl_1492_ (sram_blwl_out[1492], sram_blwl_out[1492], sram_blwl_outb[1492], sram_blwl_1492_configbus0[1492:1492], sram_blwl_1492_configbus1[1492:1492] , sram_blwl_1492_configbus0_b[1492:1492] ); -wire [1493:1493] sram_blwl_1493_configbus0; -wire [1493:1493] sram_blwl_1493_configbus1; -wire [1493:1493] sram_blwl_1493_configbus0_b; -assign sram_blwl_1493_configbus0[1493:1493] = sram_blwl_bl[1493:1493] ; -assign sram_blwl_1493_configbus1[1493:1493] = sram_blwl_wl[1493:1493] ; -assign sram_blwl_1493_configbus0_b[1493:1493] = sram_blwl_blb[1493:1493] ; -sram6T_blwl sram_blwl_1493_ (sram_blwl_out[1493], sram_blwl_out[1493], sram_blwl_outb[1493], sram_blwl_1493_configbus0[1493:1493], sram_blwl_1493_configbus1[1493:1493] , sram_blwl_1493_configbus0_b[1493:1493] ); -wire [1494:1494] sram_blwl_1494_configbus0; -wire [1494:1494] sram_blwl_1494_configbus1; -wire [1494:1494] sram_blwl_1494_configbus0_b; -assign sram_blwl_1494_configbus0[1494:1494] = sram_blwl_bl[1494:1494] ; -assign sram_blwl_1494_configbus1[1494:1494] = sram_blwl_wl[1494:1494] ; -assign sram_blwl_1494_configbus0_b[1494:1494] = sram_blwl_blb[1494:1494] ; -sram6T_blwl sram_blwl_1494_ (sram_blwl_out[1494], sram_blwl_out[1494], sram_blwl_outb[1494], sram_blwl_1494_configbus0[1494:1494], sram_blwl_1494_configbus1[1494:1494] , sram_blwl_1494_configbus0_b[1494:1494] ); -wire [1495:1495] sram_blwl_1495_configbus0; -wire [1495:1495] sram_blwl_1495_configbus1; -wire [1495:1495] sram_blwl_1495_configbus0_b; -assign sram_blwl_1495_configbus0[1495:1495] = sram_blwl_bl[1495:1495] ; -assign sram_blwl_1495_configbus1[1495:1495] = sram_blwl_wl[1495:1495] ; -assign sram_blwl_1495_configbus0_b[1495:1495] = sram_blwl_blb[1495:1495] ; -sram6T_blwl sram_blwl_1495_ (sram_blwl_out[1495], sram_blwl_out[1495], sram_blwl_outb[1495], sram_blwl_1495_configbus0[1495:1495], sram_blwl_1495_configbus1[1495:1495] , sram_blwl_1495_configbus0_b[1495:1495] ); -wire [1496:1496] sram_blwl_1496_configbus0; -wire [1496:1496] sram_blwl_1496_configbus1; -wire [1496:1496] sram_blwl_1496_configbus0_b; -assign sram_blwl_1496_configbus0[1496:1496] = sram_blwl_bl[1496:1496] ; -assign sram_blwl_1496_configbus1[1496:1496] = sram_blwl_wl[1496:1496] ; -assign sram_blwl_1496_configbus0_b[1496:1496] = sram_blwl_blb[1496:1496] ; -sram6T_blwl sram_blwl_1496_ (sram_blwl_out[1496], sram_blwl_out[1496], sram_blwl_outb[1496], sram_blwl_1496_configbus0[1496:1496], sram_blwl_1496_configbus1[1496:1496] , sram_blwl_1496_configbus0_b[1496:1496] ); -wire [1497:1497] sram_blwl_1497_configbus0; -wire [1497:1497] sram_blwl_1497_configbus1; -wire [1497:1497] sram_blwl_1497_configbus0_b; -assign sram_blwl_1497_configbus0[1497:1497] = sram_blwl_bl[1497:1497] ; -assign sram_blwl_1497_configbus1[1497:1497] = sram_blwl_wl[1497:1497] ; -assign sram_blwl_1497_configbus0_b[1497:1497] = sram_blwl_blb[1497:1497] ; -sram6T_blwl sram_blwl_1497_ (sram_blwl_out[1497], sram_blwl_out[1497], sram_blwl_outb[1497], sram_blwl_1497_configbus0[1497:1497], sram_blwl_1497_configbus1[1497:1497] , sram_blwl_1497_configbus0_b[1497:1497] ); -wire [1498:1498] sram_blwl_1498_configbus0; -wire [1498:1498] sram_blwl_1498_configbus1; -wire [1498:1498] sram_blwl_1498_configbus0_b; -assign sram_blwl_1498_configbus0[1498:1498] = sram_blwl_bl[1498:1498] ; -assign sram_blwl_1498_configbus1[1498:1498] = sram_blwl_wl[1498:1498] ; -assign sram_blwl_1498_configbus0_b[1498:1498] = sram_blwl_blb[1498:1498] ; -sram6T_blwl sram_blwl_1498_ (sram_blwl_out[1498], sram_blwl_out[1498], sram_blwl_outb[1498], sram_blwl_1498_configbus0[1498:1498], sram_blwl_1498_configbus1[1498:1498] , sram_blwl_1498_configbus0_b[1498:1498] ); -wire [1499:1499] sram_blwl_1499_configbus0; -wire [1499:1499] sram_blwl_1499_configbus1; -wire [1499:1499] sram_blwl_1499_configbus0_b; -assign sram_blwl_1499_configbus0[1499:1499] = sram_blwl_bl[1499:1499] ; -assign sram_blwl_1499_configbus1[1499:1499] = sram_blwl_wl[1499:1499] ; -assign sram_blwl_1499_configbus0_b[1499:1499] = sram_blwl_blb[1499:1499] ; -sram6T_blwl sram_blwl_1499_ (sram_blwl_out[1499], sram_blwl_out[1499], sram_blwl_outb[1499], sram_blwl_1499_configbus0[1499:1499], sram_blwl_1499_configbus1[1499:1499] , sram_blwl_1499_configbus0_b[1499:1499] ); -wire [1500:1500] sram_blwl_1500_configbus0; -wire [1500:1500] sram_blwl_1500_configbus1; -wire [1500:1500] sram_blwl_1500_configbus0_b; -assign sram_blwl_1500_configbus0[1500:1500] = sram_blwl_bl[1500:1500] ; -assign sram_blwl_1500_configbus1[1500:1500] = sram_blwl_wl[1500:1500] ; -assign sram_blwl_1500_configbus0_b[1500:1500] = sram_blwl_blb[1500:1500] ; -sram6T_blwl sram_blwl_1500_ (sram_blwl_out[1500], sram_blwl_out[1500], sram_blwl_outb[1500], sram_blwl_1500_configbus0[1500:1500], sram_blwl_1500_configbus1[1500:1500] , sram_blwl_1500_configbus0_b[1500:1500] ); -wire [1501:1501] sram_blwl_1501_configbus0; -wire [1501:1501] sram_blwl_1501_configbus1; -wire [1501:1501] sram_blwl_1501_configbus0_b; -assign sram_blwl_1501_configbus0[1501:1501] = sram_blwl_bl[1501:1501] ; -assign sram_blwl_1501_configbus1[1501:1501] = sram_blwl_wl[1501:1501] ; -assign sram_blwl_1501_configbus0_b[1501:1501] = sram_blwl_blb[1501:1501] ; -sram6T_blwl sram_blwl_1501_ (sram_blwl_out[1501], sram_blwl_out[1501], sram_blwl_outb[1501], sram_blwl_1501_configbus0[1501:1501], sram_blwl_1501_configbus1[1501:1501] , sram_blwl_1501_configbus0_b[1501:1501] ); -wire [1502:1502] sram_blwl_1502_configbus0; -wire [1502:1502] sram_blwl_1502_configbus1; -wire [1502:1502] sram_blwl_1502_configbus0_b; -assign sram_blwl_1502_configbus0[1502:1502] = sram_blwl_bl[1502:1502] ; -assign sram_blwl_1502_configbus1[1502:1502] = sram_blwl_wl[1502:1502] ; -assign sram_blwl_1502_configbus0_b[1502:1502] = sram_blwl_blb[1502:1502] ; -sram6T_blwl sram_blwl_1502_ (sram_blwl_out[1502], sram_blwl_out[1502], sram_blwl_outb[1502], sram_blwl_1502_configbus0[1502:1502], sram_blwl_1502_configbus1[1502:1502] , sram_blwl_1502_configbus0_b[1502:1502] ); -wire [1503:1503] sram_blwl_1503_configbus0; -wire [1503:1503] sram_blwl_1503_configbus1; -wire [1503:1503] sram_blwl_1503_configbus0_b; -assign sram_blwl_1503_configbus0[1503:1503] = sram_blwl_bl[1503:1503] ; -assign sram_blwl_1503_configbus1[1503:1503] = sram_blwl_wl[1503:1503] ; -assign sram_blwl_1503_configbus0_b[1503:1503] = sram_blwl_blb[1503:1503] ; -sram6T_blwl sram_blwl_1503_ (sram_blwl_out[1503], sram_blwl_out[1503], sram_blwl_outb[1503], sram_blwl_1503_configbus0[1503:1503], sram_blwl_1503_configbus1[1503:1503] , sram_blwl_1503_configbus0_b[1503:1503] ); -wire [1504:1504] sram_blwl_1504_configbus0; -wire [1504:1504] sram_blwl_1504_configbus1; -wire [1504:1504] sram_blwl_1504_configbus0_b; -assign sram_blwl_1504_configbus0[1504:1504] = sram_blwl_bl[1504:1504] ; -assign sram_blwl_1504_configbus1[1504:1504] = sram_blwl_wl[1504:1504] ; -assign sram_blwl_1504_configbus0_b[1504:1504] = sram_blwl_blb[1504:1504] ; -sram6T_blwl sram_blwl_1504_ (sram_blwl_out[1504], sram_blwl_out[1504], sram_blwl_outb[1504], sram_blwl_1504_configbus0[1504:1504], sram_blwl_1504_configbus1[1504:1504] , sram_blwl_1504_configbus0_b[1504:1504] ); -wire [1505:1505] sram_blwl_1505_configbus0; -wire [1505:1505] sram_blwl_1505_configbus1; -wire [1505:1505] sram_blwl_1505_configbus0_b; -assign sram_blwl_1505_configbus0[1505:1505] = sram_blwl_bl[1505:1505] ; -assign sram_blwl_1505_configbus1[1505:1505] = sram_blwl_wl[1505:1505] ; -assign sram_blwl_1505_configbus0_b[1505:1505] = sram_blwl_blb[1505:1505] ; -sram6T_blwl sram_blwl_1505_ (sram_blwl_out[1505], sram_blwl_out[1505], sram_blwl_outb[1505], sram_blwl_1505_configbus0[1505:1505], sram_blwl_1505_configbus1[1505:1505] , sram_blwl_1505_configbus0_b[1505:1505] ); -wire [1506:1506] sram_blwl_1506_configbus0; -wire [1506:1506] sram_blwl_1506_configbus1; -wire [1506:1506] sram_blwl_1506_configbus0_b; -assign sram_blwl_1506_configbus0[1506:1506] = sram_blwl_bl[1506:1506] ; -assign sram_blwl_1506_configbus1[1506:1506] = sram_blwl_wl[1506:1506] ; -assign sram_blwl_1506_configbus0_b[1506:1506] = sram_blwl_blb[1506:1506] ; -sram6T_blwl sram_blwl_1506_ (sram_blwl_out[1506], sram_blwl_out[1506], sram_blwl_outb[1506], sram_blwl_1506_configbus0[1506:1506], sram_blwl_1506_configbus1[1506:1506] , sram_blwl_1506_configbus0_b[1506:1506] ); -wire [1507:1507] sram_blwl_1507_configbus0; -wire [1507:1507] sram_blwl_1507_configbus1; -wire [1507:1507] sram_blwl_1507_configbus0_b; -assign sram_blwl_1507_configbus0[1507:1507] = sram_blwl_bl[1507:1507] ; -assign sram_blwl_1507_configbus1[1507:1507] = sram_blwl_wl[1507:1507] ; -assign sram_blwl_1507_configbus0_b[1507:1507] = sram_blwl_blb[1507:1507] ; -sram6T_blwl sram_blwl_1507_ (sram_blwl_out[1507], sram_blwl_out[1507], sram_blwl_outb[1507], sram_blwl_1507_configbus0[1507:1507], sram_blwl_1507_configbus1[1507:1507] , sram_blwl_1507_configbus0_b[1507:1507] ); -wire [1508:1508] sram_blwl_1508_configbus0; -wire [1508:1508] sram_blwl_1508_configbus1; -wire [1508:1508] sram_blwl_1508_configbus0_b; -assign sram_blwl_1508_configbus0[1508:1508] = sram_blwl_bl[1508:1508] ; -assign sram_blwl_1508_configbus1[1508:1508] = sram_blwl_wl[1508:1508] ; -assign sram_blwl_1508_configbus0_b[1508:1508] = sram_blwl_blb[1508:1508] ; -sram6T_blwl sram_blwl_1508_ (sram_blwl_out[1508], sram_blwl_out[1508], sram_blwl_outb[1508], sram_blwl_1508_configbus0[1508:1508], sram_blwl_1508_configbus1[1508:1508] , sram_blwl_1508_configbus0_b[1508:1508] ); -wire [1509:1509] sram_blwl_1509_configbus0; -wire [1509:1509] sram_blwl_1509_configbus1; -wire [1509:1509] sram_blwl_1509_configbus0_b; -assign sram_blwl_1509_configbus0[1509:1509] = sram_blwl_bl[1509:1509] ; -assign sram_blwl_1509_configbus1[1509:1509] = sram_blwl_wl[1509:1509] ; -assign sram_blwl_1509_configbus0_b[1509:1509] = sram_blwl_blb[1509:1509] ; -sram6T_blwl sram_blwl_1509_ (sram_blwl_out[1509], sram_blwl_out[1509], sram_blwl_outb[1509], sram_blwl_1509_configbus0[1509:1509], sram_blwl_1509_configbus1[1509:1509] , sram_blwl_1509_configbus0_b[1509:1509] ); -wire [1510:1510] sram_blwl_1510_configbus0; -wire [1510:1510] sram_blwl_1510_configbus1; -wire [1510:1510] sram_blwl_1510_configbus0_b; -assign sram_blwl_1510_configbus0[1510:1510] = sram_blwl_bl[1510:1510] ; -assign sram_blwl_1510_configbus1[1510:1510] = sram_blwl_wl[1510:1510] ; -assign sram_blwl_1510_configbus0_b[1510:1510] = sram_blwl_blb[1510:1510] ; -sram6T_blwl sram_blwl_1510_ (sram_blwl_out[1510], sram_blwl_out[1510], sram_blwl_outb[1510], sram_blwl_1510_configbus0[1510:1510], sram_blwl_1510_configbus1[1510:1510] , sram_blwl_1510_configbus0_b[1510:1510] ); -wire [1511:1511] sram_blwl_1511_configbus0; -wire [1511:1511] sram_blwl_1511_configbus1; -wire [1511:1511] sram_blwl_1511_configbus0_b; -assign sram_blwl_1511_configbus0[1511:1511] = sram_blwl_bl[1511:1511] ; -assign sram_blwl_1511_configbus1[1511:1511] = sram_blwl_wl[1511:1511] ; -assign sram_blwl_1511_configbus0_b[1511:1511] = sram_blwl_blb[1511:1511] ; -sram6T_blwl sram_blwl_1511_ (sram_blwl_out[1511], sram_blwl_out[1511], sram_blwl_outb[1511], sram_blwl_1511_configbus0[1511:1511], sram_blwl_1511_configbus1[1511:1511] , sram_blwl_1511_configbus0_b[1511:1511] ); -wire [1512:1512] sram_blwl_1512_configbus0; -wire [1512:1512] sram_blwl_1512_configbus1; -wire [1512:1512] sram_blwl_1512_configbus0_b; -assign sram_blwl_1512_configbus0[1512:1512] = sram_blwl_bl[1512:1512] ; -assign sram_blwl_1512_configbus1[1512:1512] = sram_blwl_wl[1512:1512] ; -assign sram_blwl_1512_configbus0_b[1512:1512] = sram_blwl_blb[1512:1512] ; -sram6T_blwl sram_blwl_1512_ (sram_blwl_out[1512], sram_blwl_out[1512], sram_blwl_outb[1512], sram_blwl_1512_configbus0[1512:1512], sram_blwl_1512_configbus1[1512:1512] , sram_blwl_1512_configbus0_b[1512:1512] ); -wire [1513:1513] sram_blwl_1513_configbus0; -wire [1513:1513] sram_blwl_1513_configbus1; -wire [1513:1513] sram_blwl_1513_configbus0_b; -assign sram_blwl_1513_configbus0[1513:1513] = sram_blwl_bl[1513:1513] ; -assign sram_blwl_1513_configbus1[1513:1513] = sram_blwl_wl[1513:1513] ; -assign sram_blwl_1513_configbus0_b[1513:1513] = sram_blwl_blb[1513:1513] ; -sram6T_blwl sram_blwl_1513_ (sram_blwl_out[1513], sram_blwl_out[1513], sram_blwl_outb[1513], sram_blwl_1513_configbus0[1513:1513], sram_blwl_1513_configbus1[1513:1513] , sram_blwl_1513_configbus0_b[1513:1513] ); -wire [1514:1514] sram_blwl_1514_configbus0; -wire [1514:1514] sram_blwl_1514_configbus1; -wire [1514:1514] sram_blwl_1514_configbus0_b; -assign sram_blwl_1514_configbus0[1514:1514] = sram_blwl_bl[1514:1514] ; -assign sram_blwl_1514_configbus1[1514:1514] = sram_blwl_wl[1514:1514] ; -assign sram_blwl_1514_configbus0_b[1514:1514] = sram_blwl_blb[1514:1514] ; -sram6T_blwl sram_blwl_1514_ (sram_blwl_out[1514], sram_blwl_out[1514], sram_blwl_outb[1514], sram_blwl_1514_configbus0[1514:1514], sram_blwl_1514_configbus1[1514:1514] , sram_blwl_1514_configbus0_b[1514:1514] ); -wire [1515:1515] sram_blwl_1515_configbus0; -wire [1515:1515] sram_blwl_1515_configbus1; -wire [1515:1515] sram_blwl_1515_configbus0_b; -assign sram_blwl_1515_configbus0[1515:1515] = sram_blwl_bl[1515:1515] ; -assign sram_blwl_1515_configbus1[1515:1515] = sram_blwl_wl[1515:1515] ; -assign sram_blwl_1515_configbus0_b[1515:1515] = sram_blwl_blb[1515:1515] ; -sram6T_blwl sram_blwl_1515_ (sram_blwl_out[1515], sram_blwl_out[1515], sram_blwl_outb[1515], sram_blwl_1515_configbus0[1515:1515], sram_blwl_1515_configbus1[1515:1515] , sram_blwl_1515_configbus0_b[1515:1515] ); -wire [1516:1516] sram_blwl_1516_configbus0; -wire [1516:1516] sram_blwl_1516_configbus1; -wire [1516:1516] sram_blwl_1516_configbus0_b; -assign sram_blwl_1516_configbus0[1516:1516] = sram_blwl_bl[1516:1516] ; -assign sram_blwl_1516_configbus1[1516:1516] = sram_blwl_wl[1516:1516] ; -assign sram_blwl_1516_configbus0_b[1516:1516] = sram_blwl_blb[1516:1516] ; -sram6T_blwl sram_blwl_1516_ (sram_blwl_out[1516], sram_blwl_out[1516], sram_blwl_outb[1516], sram_blwl_1516_configbus0[1516:1516], sram_blwl_1516_configbus1[1516:1516] , sram_blwl_1516_configbus0_b[1516:1516] ); -wire [1517:1517] sram_blwl_1517_configbus0; -wire [1517:1517] sram_blwl_1517_configbus1; -wire [1517:1517] sram_blwl_1517_configbus0_b; -assign sram_blwl_1517_configbus0[1517:1517] = sram_blwl_bl[1517:1517] ; -assign sram_blwl_1517_configbus1[1517:1517] = sram_blwl_wl[1517:1517] ; -assign sram_blwl_1517_configbus0_b[1517:1517] = sram_blwl_blb[1517:1517] ; -sram6T_blwl sram_blwl_1517_ (sram_blwl_out[1517], sram_blwl_out[1517], sram_blwl_outb[1517], sram_blwl_1517_configbus0[1517:1517], sram_blwl_1517_configbus1[1517:1517] , sram_blwl_1517_configbus0_b[1517:1517] ); -wire [1518:1518] sram_blwl_1518_configbus0; -wire [1518:1518] sram_blwl_1518_configbus1; -wire [1518:1518] sram_blwl_1518_configbus0_b; -assign sram_blwl_1518_configbus0[1518:1518] = sram_blwl_bl[1518:1518] ; -assign sram_blwl_1518_configbus1[1518:1518] = sram_blwl_wl[1518:1518] ; -assign sram_blwl_1518_configbus0_b[1518:1518] = sram_blwl_blb[1518:1518] ; -sram6T_blwl sram_blwl_1518_ (sram_blwl_out[1518], sram_blwl_out[1518], sram_blwl_outb[1518], sram_blwl_1518_configbus0[1518:1518], sram_blwl_1518_configbus1[1518:1518] , sram_blwl_1518_configbus0_b[1518:1518] ); -wire [1519:1519] sram_blwl_1519_configbus0; -wire [1519:1519] sram_blwl_1519_configbus1; -wire [1519:1519] sram_blwl_1519_configbus0_b; -assign sram_blwl_1519_configbus0[1519:1519] = sram_blwl_bl[1519:1519] ; -assign sram_blwl_1519_configbus1[1519:1519] = sram_blwl_wl[1519:1519] ; -assign sram_blwl_1519_configbus0_b[1519:1519] = sram_blwl_blb[1519:1519] ; -sram6T_blwl sram_blwl_1519_ (sram_blwl_out[1519], sram_blwl_out[1519], sram_blwl_outb[1519], sram_blwl_1519_configbus0[1519:1519], sram_blwl_1519_configbus1[1519:1519] , sram_blwl_1519_configbus0_b[1519:1519] ); -wire [1520:1520] sram_blwl_1520_configbus0; -wire [1520:1520] sram_blwl_1520_configbus1; -wire [1520:1520] sram_blwl_1520_configbus0_b; -assign sram_blwl_1520_configbus0[1520:1520] = sram_blwl_bl[1520:1520] ; -assign sram_blwl_1520_configbus1[1520:1520] = sram_blwl_wl[1520:1520] ; -assign sram_blwl_1520_configbus0_b[1520:1520] = sram_blwl_blb[1520:1520] ; -sram6T_blwl sram_blwl_1520_ (sram_blwl_out[1520], sram_blwl_out[1520], sram_blwl_outb[1520], sram_blwl_1520_configbus0[1520:1520], sram_blwl_1520_configbus1[1520:1520] , sram_blwl_1520_configbus0_b[1520:1520] ); -wire [1521:1521] sram_blwl_1521_configbus0; -wire [1521:1521] sram_blwl_1521_configbus1; -wire [1521:1521] sram_blwl_1521_configbus0_b; -assign sram_blwl_1521_configbus0[1521:1521] = sram_blwl_bl[1521:1521] ; -assign sram_blwl_1521_configbus1[1521:1521] = sram_blwl_wl[1521:1521] ; -assign sram_blwl_1521_configbus0_b[1521:1521] = sram_blwl_blb[1521:1521] ; -sram6T_blwl sram_blwl_1521_ (sram_blwl_out[1521], sram_blwl_out[1521], sram_blwl_outb[1521], sram_blwl_1521_configbus0[1521:1521], sram_blwl_1521_configbus1[1521:1521] , sram_blwl_1521_configbus0_b[1521:1521] ); -wire [1522:1522] sram_blwl_1522_configbus0; -wire [1522:1522] sram_blwl_1522_configbus1; -wire [1522:1522] sram_blwl_1522_configbus0_b; -assign sram_blwl_1522_configbus0[1522:1522] = sram_blwl_bl[1522:1522] ; -assign sram_blwl_1522_configbus1[1522:1522] = sram_blwl_wl[1522:1522] ; -assign sram_blwl_1522_configbus0_b[1522:1522] = sram_blwl_blb[1522:1522] ; -sram6T_blwl sram_blwl_1522_ (sram_blwl_out[1522], sram_blwl_out[1522], sram_blwl_outb[1522], sram_blwl_1522_configbus0[1522:1522], sram_blwl_1522_configbus1[1522:1522] , sram_blwl_1522_configbus0_b[1522:1522] ); -wire [1523:1523] sram_blwl_1523_configbus0; -wire [1523:1523] sram_blwl_1523_configbus1; -wire [1523:1523] sram_blwl_1523_configbus0_b; -assign sram_blwl_1523_configbus0[1523:1523] = sram_blwl_bl[1523:1523] ; -assign sram_blwl_1523_configbus1[1523:1523] = sram_blwl_wl[1523:1523] ; -assign sram_blwl_1523_configbus0_b[1523:1523] = sram_blwl_blb[1523:1523] ; -sram6T_blwl sram_blwl_1523_ (sram_blwl_out[1523], sram_blwl_out[1523], sram_blwl_outb[1523], sram_blwl_1523_configbus0[1523:1523], sram_blwl_1523_configbus1[1523:1523] , sram_blwl_1523_configbus0_b[1523:1523] ); -wire [1524:1524] sram_blwl_1524_configbus0; -wire [1524:1524] sram_blwl_1524_configbus1; -wire [1524:1524] sram_blwl_1524_configbus0_b; -assign sram_blwl_1524_configbus0[1524:1524] = sram_blwl_bl[1524:1524] ; -assign sram_blwl_1524_configbus1[1524:1524] = sram_blwl_wl[1524:1524] ; -assign sram_blwl_1524_configbus0_b[1524:1524] = sram_blwl_blb[1524:1524] ; -sram6T_blwl sram_blwl_1524_ (sram_blwl_out[1524], sram_blwl_out[1524], sram_blwl_outb[1524], sram_blwl_1524_configbus0[1524:1524], sram_blwl_1524_configbus1[1524:1524] , sram_blwl_1524_configbus0_b[1524:1524] ); -wire [1525:1525] sram_blwl_1525_configbus0; -wire [1525:1525] sram_blwl_1525_configbus1; -wire [1525:1525] sram_blwl_1525_configbus0_b; -assign sram_blwl_1525_configbus0[1525:1525] = sram_blwl_bl[1525:1525] ; -assign sram_blwl_1525_configbus1[1525:1525] = sram_blwl_wl[1525:1525] ; -assign sram_blwl_1525_configbus0_b[1525:1525] = sram_blwl_blb[1525:1525] ; -sram6T_blwl sram_blwl_1525_ (sram_blwl_out[1525], sram_blwl_out[1525], sram_blwl_outb[1525], sram_blwl_1525_configbus0[1525:1525], sram_blwl_1525_configbus1[1525:1525] , sram_blwl_1525_configbus0_b[1525:1525] ); -wire [1526:1526] sram_blwl_1526_configbus0; -wire [1526:1526] sram_blwl_1526_configbus1; -wire [1526:1526] sram_blwl_1526_configbus0_b; -assign sram_blwl_1526_configbus0[1526:1526] = sram_blwl_bl[1526:1526] ; -assign sram_blwl_1526_configbus1[1526:1526] = sram_blwl_wl[1526:1526] ; -assign sram_blwl_1526_configbus0_b[1526:1526] = sram_blwl_blb[1526:1526] ; -sram6T_blwl sram_blwl_1526_ (sram_blwl_out[1526], sram_blwl_out[1526], sram_blwl_outb[1526], sram_blwl_1526_configbus0[1526:1526], sram_blwl_1526_configbus1[1526:1526] , sram_blwl_1526_configbus0_b[1526:1526] ); -wire [1527:1527] sram_blwl_1527_configbus0; -wire [1527:1527] sram_blwl_1527_configbus1; -wire [1527:1527] sram_blwl_1527_configbus0_b; -assign sram_blwl_1527_configbus0[1527:1527] = sram_blwl_bl[1527:1527] ; -assign sram_blwl_1527_configbus1[1527:1527] = sram_blwl_wl[1527:1527] ; -assign sram_blwl_1527_configbus0_b[1527:1527] = sram_blwl_blb[1527:1527] ; -sram6T_blwl sram_blwl_1527_ (sram_blwl_out[1527], sram_blwl_out[1527], sram_blwl_outb[1527], sram_blwl_1527_configbus0[1527:1527], sram_blwl_1527_configbus1[1527:1527] , sram_blwl_1527_configbus0_b[1527:1527] ); -wire [1528:1528] sram_blwl_1528_configbus0; -wire [1528:1528] sram_blwl_1528_configbus1; -wire [1528:1528] sram_blwl_1528_configbus0_b; -assign sram_blwl_1528_configbus0[1528:1528] = sram_blwl_bl[1528:1528] ; -assign sram_blwl_1528_configbus1[1528:1528] = sram_blwl_wl[1528:1528] ; -assign sram_blwl_1528_configbus0_b[1528:1528] = sram_blwl_blb[1528:1528] ; -sram6T_blwl sram_blwl_1528_ (sram_blwl_out[1528], sram_blwl_out[1528], sram_blwl_outb[1528], sram_blwl_1528_configbus0[1528:1528], sram_blwl_1528_configbus1[1528:1528] , sram_blwl_1528_configbus0_b[1528:1528] ); -wire [1529:1529] sram_blwl_1529_configbus0; -wire [1529:1529] sram_blwl_1529_configbus1; -wire [1529:1529] sram_blwl_1529_configbus0_b; -assign sram_blwl_1529_configbus0[1529:1529] = sram_blwl_bl[1529:1529] ; -assign sram_blwl_1529_configbus1[1529:1529] = sram_blwl_wl[1529:1529] ; -assign sram_blwl_1529_configbus0_b[1529:1529] = sram_blwl_blb[1529:1529] ; -sram6T_blwl sram_blwl_1529_ (sram_blwl_out[1529], sram_blwl_out[1529], sram_blwl_outb[1529], sram_blwl_1529_configbus0[1529:1529], sram_blwl_1529_configbus1[1529:1529] , sram_blwl_1529_configbus0_b[1529:1529] ); -wire [1530:1530] sram_blwl_1530_configbus0; -wire [1530:1530] sram_blwl_1530_configbus1; -wire [1530:1530] sram_blwl_1530_configbus0_b; -assign sram_blwl_1530_configbus0[1530:1530] = sram_blwl_bl[1530:1530] ; -assign sram_blwl_1530_configbus1[1530:1530] = sram_blwl_wl[1530:1530] ; -assign sram_blwl_1530_configbus0_b[1530:1530] = sram_blwl_blb[1530:1530] ; -sram6T_blwl sram_blwl_1530_ (sram_blwl_out[1530], sram_blwl_out[1530], sram_blwl_outb[1530], sram_blwl_1530_configbus0[1530:1530], sram_blwl_1530_configbus1[1530:1530] , sram_blwl_1530_configbus0_b[1530:1530] ); -wire [1531:1531] sram_blwl_1531_configbus0; -wire [1531:1531] sram_blwl_1531_configbus1; -wire [1531:1531] sram_blwl_1531_configbus0_b; -assign sram_blwl_1531_configbus0[1531:1531] = sram_blwl_bl[1531:1531] ; -assign sram_blwl_1531_configbus1[1531:1531] = sram_blwl_wl[1531:1531] ; -assign sram_blwl_1531_configbus0_b[1531:1531] = sram_blwl_blb[1531:1531] ; -sram6T_blwl sram_blwl_1531_ (sram_blwl_out[1531], sram_blwl_out[1531], sram_blwl_outb[1531], sram_blwl_1531_configbus0[1531:1531], sram_blwl_1531_configbus1[1531:1531] , sram_blwl_1531_configbus0_b[1531:1531] ); -wire [1532:1532] sram_blwl_1532_configbus0; -wire [1532:1532] sram_blwl_1532_configbus1; -wire [1532:1532] sram_blwl_1532_configbus0_b; -assign sram_blwl_1532_configbus0[1532:1532] = sram_blwl_bl[1532:1532] ; -assign sram_blwl_1532_configbus1[1532:1532] = sram_blwl_wl[1532:1532] ; -assign sram_blwl_1532_configbus0_b[1532:1532] = sram_blwl_blb[1532:1532] ; -sram6T_blwl sram_blwl_1532_ (sram_blwl_out[1532], sram_blwl_out[1532], sram_blwl_outb[1532], sram_blwl_1532_configbus0[1532:1532], sram_blwl_1532_configbus1[1532:1532] , sram_blwl_1532_configbus0_b[1532:1532] ); -wire [1533:1533] sram_blwl_1533_configbus0; -wire [1533:1533] sram_blwl_1533_configbus1; -wire [1533:1533] sram_blwl_1533_configbus0_b; -assign sram_blwl_1533_configbus0[1533:1533] = sram_blwl_bl[1533:1533] ; -assign sram_blwl_1533_configbus1[1533:1533] = sram_blwl_wl[1533:1533] ; -assign sram_blwl_1533_configbus0_b[1533:1533] = sram_blwl_blb[1533:1533] ; -sram6T_blwl sram_blwl_1533_ (sram_blwl_out[1533], sram_blwl_out[1533], sram_blwl_outb[1533], sram_blwl_1533_configbus0[1533:1533], sram_blwl_1533_configbus1[1533:1533] , sram_blwl_1533_configbus0_b[1533:1533] ); -wire [1534:1534] sram_blwl_1534_configbus0; -wire [1534:1534] sram_blwl_1534_configbus1; -wire [1534:1534] sram_blwl_1534_configbus0_b; -assign sram_blwl_1534_configbus0[1534:1534] = sram_blwl_bl[1534:1534] ; -assign sram_blwl_1534_configbus1[1534:1534] = sram_blwl_wl[1534:1534] ; -assign sram_blwl_1534_configbus0_b[1534:1534] = sram_blwl_blb[1534:1534] ; -sram6T_blwl sram_blwl_1534_ (sram_blwl_out[1534], sram_blwl_out[1534], sram_blwl_outb[1534], sram_blwl_1534_configbus0[1534:1534], sram_blwl_1534_configbus1[1534:1534] , sram_blwl_1534_configbus0_b[1534:1534] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- - -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_7_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6_ ----- -module grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble6___in_0_, -input wire mode_ble6___in_1_, -input wire mode_ble6___in_2_, -input wire mode_ble6___in_3_, -input wire mode_ble6___in_4_, -input wire mode_ble6___in_5_, -output wire mode_ble6___out_0_, -input wire mode_ble6___clk_0_, -input [1471:1535] sram_blwl_bl , -input [1471:1535] sram_blwl_wl , -input [1471:1535] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ lut6_0_ ( - lut6_0___in_0_, lut6_0___in_1_, lut6_0___in_2_, lut6_0___in_3_, lut6_0___in_4_, lut6_0___in_5_, lut6_0___out_0_, -sram_blwl_bl[1471:1534] , -sram_blwl_wl[1471:1534] , -sram_blwl_blb[1471:1534] ); -grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_407_ ; -assign in_bus_mux_1level_tapbuf_size2_407_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_407_[1] = lut6_0___out_0_ ; -wire [1535:1535] mux_1level_tapbuf_size2_407_configbus0; -wire [1535:1535] mux_1level_tapbuf_size2_407_configbus1; -wire [1535:1535] mux_1level_tapbuf_size2_407_sram_blwl_out ; -wire [1535:1535] mux_1level_tapbuf_size2_407_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_407_configbus0[1535:1535] = sram_blwl_bl[1535:1535] ; -assign mux_1level_tapbuf_size2_407_configbus1[1535:1535] = sram_blwl_wl[1535:1535] ; -wire [1535:1535] mux_1level_tapbuf_size2_407_configbus0_b; -assign mux_1level_tapbuf_size2_407_configbus0_b[1535:1535] = sram_blwl_blb[1535:1535] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_407_ (in_bus_mux_1level_tapbuf_size2_407_, mode_ble6___out_0_, mux_1level_tapbuf_size2_407_sram_blwl_out[1535:1535] , -mux_1level_tapbuf_size2_407_sram_blwl_outb[1535:1535] ); -//----- SRAM bits for MUX[407], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1535_ (mux_1level_tapbuf_size2_407_sram_blwl_out[1535:1535] ,mux_1level_tapbuf_size2_407_sram_blwl_out[1535:1535] ,mux_1level_tapbuf_size2_407_sram_blwl_outb[1535:1535] ,mux_1level_tapbuf_size2_407_configbus0[1535:1535], mux_1level_tapbuf_size2_407_configbus1[1535:1535] , mux_1level_tapbuf_size2_407_configbus0_b[1535:1535] ); -direct_interc direct_interc_112_ (mode_ble6___in_0_, lut6_0___in_0_ ); -direct_interc direct_interc_113_ (mode_ble6___in_1_, lut6_0___in_1_ ); -direct_interc direct_interc_114_ (mode_ble6___in_2_, lut6_0___in_2_ ); -direct_interc direct_interc_115_ (mode_ble6___in_3_, lut6_0___in_3_ ); -direct_interc direct_interc_116_ (mode_ble6___in_4_, lut6_0___in_4_ ); -direct_interc direct_interc_117_ (mode_ble6___in_5_, lut6_0___in_5_ ); -direct_interc direct_interc_118_ (lut6_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_119_ (mode_ble6___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6_ ----- -module grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut6___in_0_, -input wire mode_n1_lut6___in_1_, -input wire mode_n1_lut6___in_2_, -input wire mode_n1_lut6___in_3_, -input wire mode_n1_lut6___in_4_, -input wire mode_n1_lut6___in_5_, -output wire mode_n1_lut6___out_0_, -input wire mode_n1_lut6___clk_0_, -input [1471:1535] sram_blwl_bl , -input [1471:1535] sram_blwl_wl , -input [1471:1535] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6__ble6_0__mode_ble6_ ble6_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble6_0___in_0_, ble6_0___in_1_, ble6_0___in_2_, ble6_0___in_3_, ble6_0___in_4_, ble6_0___in_5_, ble6_0___out_0_, ble6_0___clk_0_, -sram_blwl_bl[1471:1535] , -sram_blwl_wl[1471:1535] , -sram_blwl_blb[1471:1535] ); -direct_interc direct_interc_120_ (ble6_0___out_0_, mode_n1_lut6___out_0_ ); -direct_interc direct_interc_121_ (mode_n1_lut6___in_0_, ble6_0___in_0_ ); -direct_interc direct_interc_122_ (mode_n1_lut6___in_1_, ble6_0___in_1_ ); -direct_interc direct_interc_123_ (mode_n1_lut6___in_2_, ble6_0___in_2_ ); -direct_interc direct_interc_124_ (mode_n1_lut6___in_3_, ble6_0___in_3_ ); -direct_interc direct_interc_125_ (mode_n1_lut6___in_4_, ble6_0___in_4_ ); -direct_interc direct_interc_126_ (mode_n1_lut6___in_5_, ble6_0___in_5_ ); -direct_interc direct_interc_127_ (mode_n1_lut6___clk_0_, ble6_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6_ ----- - -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ( -input wire lut6_0___in_0_, -input wire lut6_0___in_1_, -input wire lut6_0___in_2_, -input wire lut6_0___in_3_, -input wire lut6_0___in_4_, -input wire lut6_0___in_5_, -output wire lut6_0___out_0_, -input [1536:1599] sram_blwl_bl , -input [1536:1599] sram_blwl_wl , -input [1536:1599] sram_blwl_blb ); -wire [0:5] lut6_0___in; -assign lut6_0___in[0] = lut6_0___in_0_; -assign lut6_0___in[1] = lut6_0___in_1_; -assign lut6_0___in[2] = lut6_0___in_2_; -assign lut6_0___in[3] = lut6_0___in_3_; -assign lut6_0___in[4] = lut6_0___in_4_; -assign lut6_0___in[5] = lut6_0___in_5_; -wire [0:0] lut6_0___out; -assign lut6_0___out_0_ = lut6_0___out[0]; -wire [1536:1599] sram_blwl_out ; -wire [1536:1599] sram_blwl_outb ; -lut6 lut6_8_ ( -//----- Input and output ports ----- - lut6_0___in[0:5] , lut6_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[1536:1599] , sram_blwl_outb[1536:1599] ); -//----- Truth Table for LUT[8], size=6. ----- -//----- SRAM bits for LUT[8], size=6, num_sram=64. ----- -//-----0000000000000000000000000000000000000000000000000000000000000000----- -wire [1536:1536] sram_blwl_1536_configbus0; -wire [1536:1536] sram_blwl_1536_configbus1; -wire [1536:1536] sram_blwl_1536_configbus0_b; -assign sram_blwl_1536_configbus0[1536:1536] = sram_blwl_bl[1536:1536] ; -assign sram_blwl_1536_configbus1[1536:1536] = sram_blwl_wl[1536:1536] ; -assign sram_blwl_1536_configbus0_b[1536:1536] = sram_blwl_blb[1536:1536] ; -sram6T_blwl sram_blwl_1536_ (sram_blwl_out[1536], sram_blwl_out[1536], sram_blwl_outb[1536], sram_blwl_1536_configbus0[1536:1536], sram_blwl_1536_configbus1[1536:1536] , sram_blwl_1536_configbus0_b[1536:1536] ); -wire [1537:1537] sram_blwl_1537_configbus0; -wire [1537:1537] sram_blwl_1537_configbus1; -wire [1537:1537] sram_blwl_1537_configbus0_b; -assign sram_blwl_1537_configbus0[1537:1537] = sram_blwl_bl[1537:1537] ; -assign sram_blwl_1537_configbus1[1537:1537] = sram_blwl_wl[1537:1537] ; -assign sram_blwl_1537_configbus0_b[1537:1537] = sram_blwl_blb[1537:1537] ; -sram6T_blwl sram_blwl_1537_ (sram_blwl_out[1537], sram_blwl_out[1537], sram_blwl_outb[1537], sram_blwl_1537_configbus0[1537:1537], sram_blwl_1537_configbus1[1537:1537] , sram_blwl_1537_configbus0_b[1537:1537] ); -wire [1538:1538] sram_blwl_1538_configbus0; -wire [1538:1538] sram_blwl_1538_configbus1; -wire [1538:1538] sram_blwl_1538_configbus0_b; -assign sram_blwl_1538_configbus0[1538:1538] = sram_blwl_bl[1538:1538] ; -assign sram_blwl_1538_configbus1[1538:1538] = sram_blwl_wl[1538:1538] ; -assign sram_blwl_1538_configbus0_b[1538:1538] = sram_blwl_blb[1538:1538] ; -sram6T_blwl sram_blwl_1538_ (sram_blwl_out[1538], sram_blwl_out[1538], sram_blwl_outb[1538], sram_blwl_1538_configbus0[1538:1538], sram_blwl_1538_configbus1[1538:1538] , sram_blwl_1538_configbus0_b[1538:1538] ); -wire [1539:1539] sram_blwl_1539_configbus0; -wire [1539:1539] sram_blwl_1539_configbus1; -wire [1539:1539] sram_blwl_1539_configbus0_b; -assign sram_blwl_1539_configbus0[1539:1539] = sram_blwl_bl[1539:1539] ; -assign sram_blwl_1539_configbus1[1539:1539] = sram_blwl_wl[1539:1539] ; -assign sram_blwl_1539_configbus0_b[1539:1539] = sram_blwl_blb[1539:1539] ; -sram6T_blwl sram_blwl_1539_ (sram_blwl_out[1539], sram_blwl_out[1539], sram_blwl_outb[1539], sram_blwl_1539_configbus0[1539:1539], sram_blwl_1539_configbus1[1539:1539] , sram_blwl_1539_configbus0_b[1539:1539] ); -wire [1540:1540] sram_blwl_1540_configbus0; -wire [1540:1540] sram_blwl_1540_configbus1; -wire [1540:1540] sram_blwl_1540_configbus0_b; -assign sram_blwl_1540_configbus0[1540:1540] = sram_blwl_bl[1540:1540] ; -assign sram_blwl_1540_configbus1[1540:1540] = sram_blwl_wl[1540:1540] ; -assign sram_blwl_1540_configbus0_b[1540:1540] = sram_blwl_blb[1540:1540] ; -sram6T_blwl sram_blwl_1540_ (sram_blwl_out[1540], sram_blwl_out[1540], sram_blwl_outb[1540], sram_blwl_1540_configbus0[1540:1540], sram_blwl_1540_configbus1[1540:1540] , sram_blwl_1540_configbus0_b[1540:1540] ); -wire [1541:1541] sram_blwl_1541_configbus0; -wire [1541:1541] sram_blwl_1541_configbus1; -wire [1541:1541] sram_blwl_1541_configbus0_b; -assign sram_blwl_1541_configbus0[1541:1541] = sram_blwl_bl[1541:1541] ; -assign sram_blwl_1541_configbus1[1541:1541] = sram_blwl_wl[1541:1541] ; -assign sram_blwl_1541_configbus0_b[1541:1541] = sram_blwl_blb[1541:1541] ; -sram6T_blwl sram_blwl_1541_ (sram_blwl_out[1541], sram_blwl_out[1541], sram_blwl_outb[1541], sram_blwl_1541_configbus0[1541:1541], sram_blwl_1541_configbus1[1541:1541] , sram_blwl_1541_configbus0_b[1541:1541] ); -wire [1542:1542] sram_blwl_1542_configbus0; -wire [1542:1542] sram_blwl_1542_configbus1; -wire [1542:1542] sram_blwl_1542_configbus0_b; -assign sram_blwl_1542_configbus0[1542:1542] = sram_blwl_bl[1542:1542] ; -assign sram_blwl_1542_configbus1[1542:1542] = sram_blwl_wl[1542:1542] ; -assign sram_blwl_1542_configbus0_b[1542:1542] = sram_blwl_blb[1542:1542] ; -sram6T_blwl sram_blwl_1542_ (sram_blwl_out[1542], sram_blwl_out[1542], sram_blwl_outb[1542], sram_blwl_1542_configbus0[1542:1542], sram_blwl_1542_configbus1[1542:1542] , sram_blwl_1542_configbus0_b[1542:1542] ); -wire [1543:1543] sram_blwl_1543_configbus0; -wire [1543:1543] sram_blwl_1543_configbus1; -wire [1543:1543] sram_blwl_1543_configbus0_b; -assign sram_blwl_1543_configbus0[1543:1543] = sram_blwl_bl[1543:1543] ; -assign sram_blwl_1543_configbus1[1543:1543] = sram_blwl_wl[1543:1543] ; -assign sram_blwl_1543_configbus0_b[1543:1543] = sram_blwl_blb[1543:1543] ; -sram6T_blwl sram_blwl_1543_ (sram_blwl_out[1543], sram_blwl_out[1543], sram_blwl_outb[1543], sram_blwl_1543_configbus0[1543:1543], sram_blwl_1543_configbus1[1543:1543] , sram_blwl_1543_configbus0_b[1543:1543] ); -wire [1544:1544] sram_blwl_1544_configbus0; -wire [1544:1544] sram_blwl_1544_configbus1; -wire [1544:1544] sram_blwl_1544_configbus0_b; -assign sram_blwl_1544_configbus0[1544:1544] = sram_blwl_bl[1544:1544] ; -assign sram_blwl_1544_configbus1[1544:1544] = sram_blwl_wl[1544:1544] ; -assign sram_blwl_1544_configbus0_b[1544:1544] = sram_blwl_blb[1544:1544] ; -sram6T_blwl sram_blwl_1544_ (sram_blwl_out[1544], sram_blwl_out[1544], sram_blwl_outb[1544], sram_blwl_1544_configbus0[1544:1544], sram_blwl_1544_configbus1[1544:1544] , sram_blwl_1544_configbus0_b[1544:1544] ); -wire [1545:1545] sram_blwl_1545_configbus0; -wire [1545:1545] sram_blwl_1545_configbus1; -wire [1545:1545] sram_blwl_1545_configbus0_b; -assign sram_blwl_1545_configbus0[1545:1545] = sram_blwl_bl[1545:1545] ; -assign sram_blwl_1545_configbus1[1545:1545] = sram_blwl_wl[1545:1545] ; -assign sram_blwl_1545_configbus0_b[1545:1545] = sram_blwl_blb[1545:1545] ; -sram6T_blwl sram_blwl_1545_ (sram_blwl_out[1545], sram_blwl_out[1545], sram_blwl_outb[1545], sram_blwl_1545_configbus0[1545:1545], sram_blwl_1545_configbus1[1545:1545] , sram_blwl_1545_configbus0_b[1545:1545] ); -wire [1546:1546] sram_blwl_1546_configbus0; -wire [1546:1546] sram_blwl_1546_configbus1; -wire [1546:1546] sram_blwl_1546_configbus0_b; -assign sram_blwl_1546_configbus0[1546:1546] = sram_blwl_bl[1546:1546] ; -assign sram_blwl_1546_configbus1[1546:1546] = sram_blwl_wl[1546:1546] ; -assign sram_blwl_1546_configbus0_b[1546:1546] = sram_blwl_blb[1546:1546] ; -sram6T_blwl sram_blwl_1546_ (sram_blwl_out[1546], sram_blwl_out[1546], sram_blwl_outb[1546], sram_blwl_1546_configbus0[1546:1546], sram_blwl_1546_configbus1[1546:1546] , sram_blwl_1546_configbus0_b[1546:1546] ); -wire [1547:1547] sram_blwl_1547_configbus0; -wire [1547:1547] sram_blwl_1547_configbus1; -wire [1547:1547] sram_blwl_1547_configbus0_b; -assign sram_blwl_1547_configbus0[1547:1547] = sram_blwl_bl[1547:1547] ; -assign sram_blwl_1547_configbus1[1547:1547] = sram_blwl_wl[1547:1547] ; -assign sram_blwl_1547_configbus0_b[1547:1547] = sram_blwl_blb[1547:1547] ; -sram6T_blwl sram_blwl_1547_ (sram_blwl_out[1547], sram_blwl_out[1547], sram_blwl_outb[1547], sram_blwl_1547_configbus0[1547:1547], sram_blwl_1547_configbus1[1547:1547] , sram_blwl_1547_configbus0_b[1547:1547] ); -wire [1548:1548] sram_blwl_1548_configbus0; -wire [1548:1548] sram_blwl_1548_configbus1; -wire [1548:1548] sram_blwl_1548_configbus0_b; -assign sram_blwl_1548_configbus0[1548:1548] = sram_blwl_bl[1548:1548] ; -assign sram_blwl_1548_configbus1[1548:1548] = sram_blwl_wl[1548:1548] ; -assign sram_blwl_1548_configbus0_b[1548:1548] = sram_blwl_blb[1548:1548] ; -sram6T_blwl sram_blwl_1548_ (sram_blwl_out[1548], sram_blwl_out[1548], sram_blwl_outb[1548], sram_blwl_1548_configbus0[1548:1548], sram_blwl_1548_configbus1[1548:1548] , sram_blwl_1548_configbus0_b[1548:1548] ); -wire [1549:1549] sram_blwl_1549_configbus0; -wire [1549:1549] sram_blwl_1549_configbus1; -wire [1549:1549] sram_blwl_1549_configbus0_b; -assign sram_blwl_1549_configbus0[1549:1549] = sram_blwl_bl[1549:1549] ; -assign sram_blwl_1549_configbus1[1549:1549] = sram_blwl_wl[1549:1549] ; -assign sram_blwl_1549_configbus0_b[1549:1549] = sram_blwl_blb[1549:1549] ; -sram6T_blwl sram_blwl_1549_ (sram_blwl_out[1549], sram_blwl_out[1549], sram_blwl_outb[1549], sram_blwl_1549_configbus0[1549:1549], sram_blwl_1549_configbus1[1549:1549] , sram_blwl_1549_configbus0_b[1549:1549] ); -wire [1550:1550] sram_blwl_1550_configbus0; -wire [1550:1550] sram_blwl_1550_configbus1; -wire [1550:1550] sram_blwl_1550_configbus0_b; -assign sram_blwl_1550_configbus0[1550:1550] = sram_blwl_bl[1550:1550] ; -assign sram_blwl_1550_configbus1[1550:1550] = sram_blwl_wl[1550:1550] ; -assign sram_blwl_1550_configbus0_b[1550:1550] = sram_blwl_blb[1550:1550] ; -sram6T_blwl sram_blwl_1550_ (sram_blwl_out[1550], sram_blwl_out[1550], sram_blwl_outb[1550], sram_blwl_1550_configbus0[1550:1550], sram_blwl_1550_configbus1[1550:1550] , sram_blwl_1550_configbus0_b[1550:1550] ); -wire [1551:1551] sram_blwl_1551_configbus0; -wire [1551:1551] sram_blwl_1551_configbus1; -wire [1551:1551] sram_blwl_1551_configbus0_b; -assign sram_blwl_1551_configbus0[1551:1551] = sram_blwl_bl[1551:1551] ; -assign sram_blwl_1551_configbus1[1551:1551] = sram_blwl_wl[1551:1551] ; -assign sram_blwl_1551_configbus0_b[1551:1551] = sram_blwl_blb[1551:1551] ; -sram6T_blwl sram_blwl_1551_ (sram_blwl_out[1551], sram_blwl_out[1551], sram_blwl_outb[1551], sram_blwl_1551_configbus0[1551:1551], sram_blwl_1551_configbus1[1551:1551] , sram_blwl_1551_configbus0_b[1551:1551] ); -wire [1552:1552] sram_blwl_1552_configbus0; -wire [1552:1552] sram_blwl_1552_configbus1; -wire [1552:1552] sram_blwl_1552_configbus0_b; -assign sram_blwl_1552_configbus0[1552:1552] = sram_blwl_bl[1552:1552] ; -assign sram_blwl_1552_configbus1[1552:1552] = sram_blwl_wl[1552:1552] ; -assign sram_blwl_1552_configbus0_b[1552:1552] = sram_blwl_blb[1552:1552] ; -sram6T_blwl sram_blwl_1552_ (sram_blwl_out[1552], sram_blwl_out[1552], sram_blwl_outb[1552], sram_blwl_1552_configbus0[1552:1552], sram_blwl_1552_configbus1[1552:1552] , sram_blwl_1552_configbus0_b[1552:1552] ); -wire [1553:1553] sram_blwl_1553_configbus0; -wire [1553:1553] sram_blwl_1553_configbus1; -wire [1553:1553] sram_blwl_1553_configbus0_b; -assign sram_blwl_1553_configbus0[1553:1553] = sram_blwl_bl[1553:1553] ; -assign sram_blwl_1553_configbus1[1553:1553] = sram_blwl_wl[1553:1553] ; -assign sram_blwl_1553_configbus0_b[1553:1553] = sram_blwl_blb[1553:1553] ; -sram6T_blwl sram_blwl_1553_ (sram_blwl_out[1553], sram_blwl_out[1553], sram_blwl_outb[1553], sram_blwl_1553_configbus0[1553:1553], sram_blwl_1553_configbus1[1553:1553] , sram_blwl_1553_configbus0_b[1553:1553] ); -wire [1554:1554] sram_blwl_1554_configbus0; -wire [1554:1554] sram_blwl_1554_configbus1; -wire [1554:1554] sram_blwl_1554_configbus0_b; -assign sram_blwl_1554_configbus0[1554:1554] = sram_blwl_bl[1554:1554] ; -assign sram_blwl_1554_configbus1[1554:1554] = sram_blwl_wl[1554:1554] ; -assign sram_blwl_1554_configbus0_b[1554:1554] = sram_blwl_blb[1554:1554] ; -sram6T_blwl sram_blwl_1554_ (sram_blwl_out[1554], sram_blwl_out[1554], sram_blwl_outb[1554], sram_blwl_1554_configbus0[1554:1554], sram_blwl_1554_configbus1[1554:1554] , sram_blwl_1554_configbus0_b[1554:1554] ); -wire [1555:1555] sram_blwl_1555_configbus0; -wire [1555:1555] sram_blwl_1555_configbus1; -wire [1555:1555] sram_blwl_1555_configbus0_b; -assign sram_blwl_1555_configbus0[1555:1555] = sram_blwl_bl[1555:1555] ; -assign sram_blwl_1555_configbus1[1555:1555] = sram_blwl_wl[1555:1555] ; -assign sram_blwl_1555_configbus0_b[1555:1555] = sram_blwl_blb[1555:1555] ; -sram6T_blwl sram_blwl_1555_ (sram_blwl_out[1555], sram_blwl_out[1555], sram_blwl_outb[1555], sram_blwl_1555_configbus0[1555:1555], sram_blwl_1555_configbus1[1555:1555] , sram_blwl_1555_configbus0_b[1555:1555] ); -wire [1556:1556] sram_blwl_1556_configbus0; -wire [1556:1556] sram_blwl_1556_configbus1; -wire [1556:1556] sram_blwl_1556_configbus0_b; -assign sram_blwl_1556_configbus0[1556:1556] = sram_blwl_bl[1556:1556] ; -assign sram_blwl_1556_configbus1[1556:1556] = sram_blwl_wl[1556:1556] ; -assign sram_blwl_1556_configbus0_b[1556:1556] = sram_blwl_blb[1556:1556] ; -sram6T_blwl sram_blwl_1556_ (sram_blwl_out[1556], sram_blwl_out[1556], sram_blwl_outb[1556], sram_blwl_1556_configbus0[1556:1556], sram_blwl_1556_configbus1[1556:1556] , sram_blwl_1556_configbus0_b[1556:1556] ); -wire [1557:1557] sram_blwl_1557_configbus0; -wire [1557:1557] sram_blwl_1557_configbus1; -wire [1557:1557] sram_blwl_1557_configbus0_b; -assign sram_blwl_1557_configbus0[1557:1557] = sram_blwl_bl[1557:1557] ; -assign sram_blwl_1557_configbus1[1557:1557] = sram_blwl_wl[1557:1557] ; -assign sram_blwl_1557_configbus0_b[1557:1557] = sram_blwl_blb[1557:1557] ; -sram6T_blwl sram_blwl_1557_ (sram_blwl_out[1557], sram_blwl_out[1557], sram_blwl_outb[1557], sram_blwl_1557_configbus0[1557:1557], sram_blwl_1557_configbus1[1557:1557] , sram_blwl_1557_configbus0_b[1557:1557] ); -wire [1558:1558] sram_blwl_1558_configbus0; -wire [1558:1558] sram_blwl_1558_configbus1; -wire [1558:1558] sram_blwl_1558_configbus0_b; -assign sram_blwl_1558_configbus0[1558:1558] = sram_blwl_bl[1558:1558] ; -assign sram_blwl_1558_configbus1[1558:1558] = sram_blwl_wl[1558:1558] ; -assign sram_blwl_1558_configbus0_b[1558:1558] = sram_blwl_blb[1558:1558] ; -sram6T_blwl sram_blwl_1558_ (sram_blwl_out[1558], sram_blwl_out[1558], sram_blwl_outb[1558], sram_blwl_1558_configbus0[1558:1558], sram_blwl_1558_configbus1[1558:1558] , sram_blwl_1558_configbus0_b[1558:1558] ); -wire [1559:1559] sram_blwl_1559_configbus0; -wire [1559:1559] sram_blwl_1559_configbus1; -wire [1559:1559] sram_blwl_1559_configbus0_b; -assign sram_blwl_1559_configbus0[1559:1559] = sram_blwl_bl[1559:1559] ; -assign sram_blwl_1559_configbus1[1559:1559] = sram_blwl_wl[1559:1559] ; -assign sram_blwl_1559_configbus0_b[1559:1559] = sram_blwl_blb[1559:1559] ; -sram6T_blwl sram_blwl_1559_ (sram_blwl_out[1559], sram_blwl_out[1559], sram_blwl_outb[1559], sram_blwl_1559_configbus0[1559:1559], sram_blwl_1559_configbus1[1559:1559] , sram_blwl_1559_configbus0_b[1559:1559] ); -wire [1560:1560] sram_blwl_1560_configbus0; -wire [1560:1560] sram_blwl_1560_configbus1; -wire [1560:1560] sram_blwl_1560_configbus0_b; -assign sram_blwl_1560_configbus0[1560:1560] = sram_blwl_bl[1560:1560] ; -assign sram_blwl_1560_configbus1[1560:1560] = sram_blwl_wl[1560:1560] ; -assign sram_blwl_1560_configbus0_b[1560:1560] = sram_blwl_blb[1560:1560] ; -sram6T_blwl sram_blwl_1560_ (sram_blwl_out[1560], sram_blwl_out[1560], sram_blwl_outb[1560], sram_blwl_1560_configbus0[1560:1560], sram_blwl_1560_configbus1[1560:1560] , sram_blwl_1560_configbus0_b[1560:1560] ); -wire [1561:1561] sram_blwl_1561_configbus0; -wire [1561:1561] sram_blwl_1561_configbus1; -wire [1561:1561] sram_blwl_1561_configbus0_b; -assign sram_blwl_1561_configbus0[1561:1561] = sram_blwl_bl[1561:1561] ; -assign sram_blwl_1561_configbus1[1561:1561] = sram_blwl_wl[1561:1561] ; -assign sram_blwl_1561_configbus0_b[1561:1561] = sram_blwl_blb[1561:1561] ; -sram6T_blwl sram_blwl_1561_ (sram_blwl_out[1561], sram_blwl_out[1561], sram_blwl_outb[1561], sram_blwl_1561_configbus0[1561:1561], sram_blwl_1561_configbus1[1561:1561] , sram_blwl_1561_configbus0_b[1561:1561] ); -wire [1562:1562] sram_blwl_1562_configbus0; -wire [1562:1562] sram_blwl_1562_configbus1; -wire [1562:1562] sram_blwl_1562_configbus0_b; -assign sram_blwl_1562_configbus0[1562:1562] = sram_blwl_bl[1562:1562] ; -assign sram_blwl_1562_configbus1[1562:1562] = sram_blwl_wl[1562:1562] ; -assign sram_blwl_1562_configbus0_b[1562:1562] = sram_blwl_blb[1562:1562] ; -sram6T_blwl sram_blwl_1562_ (sram_blwl_out[1562], sram_blwl_out[1562], sram_blwl_outb[1562], sram_blwl_1562_configbus0[1562:1562], sram_blwl_1562_configbus1[1562:1562] , sram_blwl_1562_configbus0_b[1562:1562] ); -wire [1563:1563] sram_blwl_1563_configbus0; -wire [1563:1563] sram_blwl_1563_configbus1; -wire [1563:1563] sram_blwl_1563_configbus0_b; -assign sram_blwl_1563_configbus0[1563:1563] = sram_blwl_bl[1563:1563] ; -assign sram_blwl_1563_configbus1[1563:1563] = sram_blwl_wl[1563:1563] ; -assign sram_blwl_1563_configbus0_b[1563:1563] = sram_blwl_blb[1563:1563] ; -sram6T_blwl sram_blwl_1563_ (sram_blwl_out[1563], sram_blwl_out[1563], sram_blwl_outb[1563], sram_blwl_1563_configbus0[1563:1563], sram_blwl_1563_configbus1[1563:1563] , sram_blwl_1563_configbus0_b[1563:1563] ); -wire [1564:1564] sram_blwl_1564_configbus0; -wire [1564:1564] sram_blwl_1564_configbus1; -wire [1564:1564] sram_blwl_1564_configbus0_b; -assign sram_blwl_1564_configbus0[1564:1564] = sram_blwl_bl[1564:1564] ; -assign sram_blwl_1564_configbus1[1564:1564] = sram_blwl_wl[1564:1564] ; -assign sram_blwl_1564_configbus0_b[1564:1564] = sram_blwl_blb[1564:1564] ; -sram6T_blwl sram_blwl_1564_ (sram_blwl_out[1564], sram_blwl_out[1564], sram_blwl_outb[1564], sram_blwl_1564_configbus0[1564:1564], sram_blwl_1564_configbus1[1564:1564] , sram_blwl_1564_configbus0_b[1564:1564] ); -wire [1565:1565] sram_blwl_1565_configbus0; -wire [1565:1565] sram_blwl_1565_configbus1; -wire [1565:1565] sram_blwl_1565_configbus0_b; -assign sram_blwl_1565_configbus0[1565:1565] = sram_blwl_bl[1565:1565] ; -assign sram_blwl_1565_configbus1[1565:1565] = sram_blwl_wl[1565:1565] ; -assign sram_blwl_1565_configbus0_b[1565:1565] = sram_blwl_blb[1565:1565] ; -sram6T_blwl sram_blwl_1565_ (sram_blwl_out[1565], sram_blwl_out[1565], sram_blwl_outb[1565], sram_blwl_1565_configbus0[1565:1565], sram_blwl_1565_configbus1[1565:1565] , sram_blwl_1565_configbus0_b[1565:1565] ); -wire [1566:1566] sram_blwl_1566_configbus0; -wire [1566:1566] sram_blwl_1566_configbus1; -wire [1566:1566] sram_blwl_1566_configbus0_b; -assign sram_blwl_1566_configbus0[1566:1566] = sram_blwl_bl[1566:1566] ; -assign sram_blwl_1566_configbus1[1566:1566] = sram_blwl_wl[1566:1566] ; -assign sram_blwl_1566_configbus0_b[1566:1566] = sram_blwl_blb[1566:1566] ; -sram6T_blwl sram_blwl_1566_ (sram_blwl_out[1566], sram_blwl_out[1566], sram_blwl_outb[1566], sram_blwl_1566_configbus0[1566:1566], sram_blwl_1566_configbus1[1566:1566] , sram_blwl_1566_configbus0_b[1566:1566] ); -wire [1567:1567] sram_blwl_1567_configbus0; -wire [1567:1567] sram_blwl_1567_configbus1; -wire [1567:1567] sram_blwl_1567_configbus0_b; -assign sram_blwl_1567_configbus0[1567:1567] = sram_blwl_bl[1567:1567] ; -assign sram_blwl_1567_configbus1[1567:1567] = sram_blwl_wl[1567:1567] ; -assign sram_blwl_1567_configbus0_b[1567:1567] = sram_blwl_blb[1567:1567] ; -sram6T_blwl sram_blwl_1567_ (sram_blwl_out[1567], sram_blwl_out[1567], sram_blwl_outb[1567], sram_blwl_1567_configbus0[1567:1567], sram_blwl_1567_configbus1[1567:1567] , sram_blwl_1567_configbus0_b[1567:1567] ); -wire [1568:1568] sram_blwl_1568_configbus0; -wire [1568:1568] sram_blwl_1568_configbus1; -wire [1568:1568] sram_blwl_1568_configbus0_b; -assign sram_blwl_1568_configbus0[1568:1568] = sram_blwl_bl[1568:1568] ; -assign sram_blwl_1568_configbus1[1568:1568] = sram_blwl_wl[1568:1568] ; -assign sram_blwl_1568_configbus0_b[1568:1568] = sram_blwl_blb[1568:1568] ; -sram6T_blwl sram_blwl_1568_ (sram_blwl_out[1568], sram_blwl_out[1568], sram_blwl_outb[1568], sram_blwl_1568_configbus0[1568:1568], sram_blwl_1568_configbus1[1568:1568] , sram_blwl_1568_configbus0_b[1568:1568] ); -wire [1569:1569] sram_blwl_1569_configbus0; -wire [1569:1569] sram_blwl_1569_configbus1; -wire [1569:1569] sram_blwl_1569_configbus0_b; -assign sram_blwl_1569_configbus0[1569:1569] = sram_blwl_bl[1569:1569] ; -assign sram_blwl_1569_configbus1[1569:1569] = sram_blwl_wl[1569:1569] ; -assign sram_blwl_1569_configbus0_b[1569:1569] = sram_blwl_blb[1569:1569] ; -sram6T_blwl sram_blwl_1569_ (sram_blwl_out[1569], sram_blwl_out[1569], sram_blwl_outb[1569], sram_blwl_1569_configbus0[1569:1569], sram_blwl_1569_configbus1[1569:1569] , sram_blwl_1569_configbus0_b[1569:1569] ); -wire [1570:1570] sram_blwl_1570_configbus0; -wire [1570:1570] sram_blwl_1570_configbus1; -wire [1570:1570] sram_blwl_1570_configbus0_b; -assign sram_blwl_1570_configbus0[1570:1570] = sram_blwl_bl[1570:1570] ; -assign sram_blwl_1570_configbus1[1570:1570] = sram_blwl_wl[1570:1570] ; -assign sram_blwl_1570_configbus0_b[1570:1570] = sram_blwl_blb[1570:1570] ; -sram6T_blwl sram_blwl_1570_ (sram_blwl_out[1570], sram_blwl_out[1570], sram_blwl_outb[1570], sram_blwl_1570_configbus0[1570:1570], sram_blwl_1570_configbus1[1570:1570] , sram_blwl_1570_configbus0_b[1570:1570] ); -wire [1571:1571] sram_blwl_1571_configbus0; -wire [1571:1571] sram_blwl_1571_configbus1; -wire [1571:1571] sram_blwl_1571_configbus0_b; -assign sram_blwl_1571_configbus0[1571:1571] = sram_blwl_bl[1571:1571] ; -assign sram_blwl_1571_configbus1[1571:1571] = sram_blwl_wl[1571:1571] ; -assign sram_blwl_1571_configbus0_b[1571:1571] = sram_blwl_blb[1571:1571] ; -sram6T_blwl sram_blwl_1571_ (sram_blwl_out[1571], sram_blwl_out[1571], sram_blwl_outb[1571], sram_blwl_1571_configbus0[1571:1571], sram_blwl_1571_configbus1[1571:1571] , sram_blwl_1571_configbus0_b[1571:1571] ); -wire [1572:1572] sram_blwl_1572_configbus0; -wire [1572:1572] sram_blwl_1572_configbus1; -wire [1572:1572] sram_blwl_1572_configbus0_b; -assign sram_blwl_1572_configbus0[1572:1572] = sram_blwl_bl[1572:1572] ; -assign sram_blwl_1572_configbus1[1572:1572] = sram_blwl_wl[1572:1572] ; -assign sram_blwl_1572_configbus0_b[1572:1572] = sram_blwl_blb[1572:1572] ; -sram6T_blwl sram_blwl_1572_ (sram_blwl_out[1572], sram_blwl_out[1572], sram_blwl_outb[1572], sram_blwl_1572_configbus0[1572:1572], sram_blwl_1572_configbus1[1572:1572] , sram_blwl_1572_configbus0_b[1572:1572] ); -wire [1573:1573] sram_blwl_1573_configbus0; -wire [1573:1573] sram_blwl_1573_configbus1; -wire [1573:1573] sram_blwl_1573_configbus0_b; -assign sram_blwl_1573_configbus0[1573:1573] = sram_blwl_bl[1573:1573] ; -assign sram_blwl_1573_configbus1[1573:1573] = sram_blwl_wl[1573:1573] ; -assign sram_blwl_1573_configbus0_b[1573:1573] = sram_blwl_blb[1573:1573] ; -sram6T_blwl sram_blwl_1573_ (sram_blwl_out[1573], sram_blwl_out[1573], sram_blwl_outb[1573], sram_blwl_1573_configbus0[1573:1573], sram_blwl_1573_configbus1[1573:1573] , sram_blwl_1573_configbus0_b[1573:1573] ); -wire [1574:1574] sram_blwl_1574_configbus0; -wire [1574:1574] sram_blwl_1574_configbus1; -wire [1574:1574] sram_blwl_1574_configbus0_b; -assign sram_blwl_1574_configbus0[1574:1574] = sram_blwl_bl[1574:1574] ; -assign sram_blwl_1574_configbus1[1574:1574] = sram_blwl_wl[1574:1574] ; -assign sram_blwl_1574_configbus0_b[1574:1574] = sram_blwl_blb[1574:1574] ; -sram6T_blwl sram_blwl_1574_ (sram_blwl_out[1574], sram_blwl_out[1574], sram_blwl_outb[1574], sram_blwl_1574_configbus0[1574:1574], sram_blwl_1574_configbus1[1574:1574] , sram_blwl_1574_configbus0_b[1574:1574] ); -wire [1575:1575] sram_blwl_1575_configbus0; -wire [1575:1575] sram_blwl_1575_configbus1; -wire [1575:1575] sram_blwl_1575_configbus0_b; -assign sram_blwl_1575_configbus0[1575:1575] = sram_blwl_bl[1575:1575] ; -assign sram_blwl_1575_configbus1[1575:1575] = sram_blwl_wl[1575:1575] ; -assign sram_blwl_1575_configbus0_b[1575:1575] = sram_blwl_blb[1575:1575] ; -sram6T_blwl sram_blwl_1575_ (sram_blwl_out[1575], sram_blwl_out[1575], sram_blwl_outb[1575], sram_blwl_1575_configbus0[1575:1575], sram_blwl_1575_configbus1[1575:1575] , sram_blwl_1575_configbus0_b[1575:1575] ); -wire [1576:1576] sram_blwl_1576_configbus0; -wire [1576:1576] sram_blwl_1576_configbus1; -wire [1576:1576] sram_blwl_1576_configbus0_b; -assign sram_blwl_1576_configbus0[1576:1576] = sram_blwl_bl[1576:1576] ; -assign sram_blwl_1576_configbus1[1576:1576] = sram_blwl_wl[1576:1576] ; -assign sram_blwl_1576_configbus0_b[1576:1576] = sram_blwl_blb[1576:1576] ; -sram6T_blwl sram_blwl_1576_ (sram_blwl_out[1576], sram_blwl_out[1576], sram_blwl_outb[1576], sram_blwl_1576_configbus0[1576:1576], sram_blwl_1576_configbus1[1576:1576] , sram_blwl_1576_configbus0_b[1576:1576] ); -wire [1577:1577] sram_blwl_1577_configbus0; -wire [1577:1577] sram_blwl_1577_configbus1; -wire [1577:1577] sram_blwl_1577_configbus0_b; -assign sram_blwl_1577_configbus0[1577:1577] = sram_blwl_bl[1577:1577] ; -assign sram_blwl_1577_configbus1[1577:1577] = sram_blwl_wl[1577:1577] ; -assign sram_blwl_1577_configbus0_b[1577:1577] = sram_blwl_blb[1577:1577] ; -sram6T_blwl sram_blwl_1577_ (sram_blwl_out[1577], sram_blwl_out[1577], sram_blwl_outb[1577], sram_blwl_1577_configbus0[1577:1577], sram_blwl_1577_configbus1[1577:1577] , sram_blwl_1577_configbus0_b[1577:1577] ); -wire [1578:1578] sram_blwl_1578_configbus0; -wire [1578:1578] sram_blwl_1578_configbus1; -wire [1578:1578] sram_blwl_1578_configbus0_b; -assign sram_blwl_1578_configbus0[1578:1578] = sram_blwl_bl[1578:1578] ; -assign sram_blwl_1578_configbus1[1578:1578] = sram_blwl_wl[1578:1578] ; -assign sram_blwl_1578_configbus0_b[1578:1578] = sram_blwl_blb[1578:1578] ; -sram6T_blwl sram_blwl_1578_ (sram_blwl_out[1578], sram_blwl_out[1578], sram_blwl_outb[1578], sram_blwl_1578_configbus0[1578:1578], sram_blwl_1578_configbus1[1578:1578] , sram_blwl_1578_configbus0_b[1578:1578] ); -wire [1579:1579] sram_blwl_1579_configbus0; -wire [1579:1579] sram_blwl_1579_configbus1; -wire [1579:1579] sram_blwl_1579_configbus0_b; -assign sram_blwl_1579_configbus0[1579:1579] = sram_blwl_bl[1579:1579] ; -assign sram_blwl_1579_configbus1[1579:1579] = sram_blwl_wl[1579:1579] ; -assign sram_blwl_1579_configbus0_b[1579:1579] = sram_blwl_blb[1579:1579] ; -sram6T_blwl sram_blwl_1579_ (sram_blwl_out[1579], sram_blwl_out[1579], sram_blwl_outb[1579], sram_blwl_1579_configbus0[1579:1579], sram_blwl_1579_configbus1[1579:1579] , sram_blwl_1579_configbus0_b[1579:1579] ); -wire [1580:1580] sram_blwl_1580_configbus0; -wire [1580:1580] sram_blwl_1580_configbus1; -wire [1580:1580] sram_blwl_1580_configbus0_b; -assign sram_blwl_1580_configbus0[1580:1580] = sram_blwl_bl[1580:1580] ; -assign sram_blwl_1580_configbus1[1580:1580] = sram_blwl_wl[1580:1580] ; -assign sram_blwl_1580_configbus0_b[1580:1580] = sram_blwl_blb[1580:1580] ; -sram6T_blwl sram_blwl_1580_ (sram_blwl_out[1580], sram_blwl_out[1580], sram_blwl_outb[1580], sram_blwl_1580_configbus0[1580:1580], sram_blwl_1580_configbus1[1580:1580] , sram_blwl_1580_configbus0_b[1580:1580] ); -wire [1581:1581] sram_blwl_1581_configbus0; -wire [1581:1581] sram_blwl_1581_configbus1; -wire [1581:1581] sram_blwl_1581_configbus0_b; -assign sram_blwl_1581_configbus0[1581:1581] = sram_blwl_bl[1581:1581] ; -assign sram_blwl_1581_configbus1[1581:1581] = sram_blwl_wl[1581:1581] ; -assign sram_blwl_1581_configbus0_b[1581:1581] = sram_blwl_blb[1581:1581] ; -sram6T_blwl sram_blwl_1581_ (sram_blwl_out[1581], sram_blwl_out[1581], sram_blwl_outb[1581], sram_blwl_1581_configbus0[1581:1581], sram_blwl_1581_configbus1[1581:1581] , sram_blwl_1581_configbus0_b[1581:1581] ); -wire [1582:1582] sram_blwl_1582_configbus0; -wire [1582:1582] sram_blwl_1582_configbus1; -wire [1582:1582] sram_blwl_1582_configbus0_b; -assign sram_blwl_1582_configbus0[1582:1582] = sram_blwl_bl[1582:1582] ; -assign sram_blwl_1582_configbus1[1582:1582] = sram_blwl_wl[1582:1582] ; -assign sram_blwl_1582_configbus0_b[1582:1582] = sram_blwl_blb[1582:1582] ; -sram6T_blwl sram_blwl_1582_ (sram_blwl_out[1582], sram_blwl_out[1582], sram_blwl_outb[1582], sram_blwl_1582_configbus0[1582:1582], sram_blwl_1582_configbus1[1582:1582] , sram_blwl_1582_configbus0_b[1582:1582] ); -wire [1583:1583] sram_blwl_1583_configbus0; -wire [1583:1583] sram_blwl_1583_configbus1; -wire [1583:1583] sram_blwl_1583_configbus0_b; -assign sram_blwl_1583_configbus0[1583:1583] = sram_blwl_bl[1583:1583] ; -assign sram_blwl_1583_configbus1[1583:1583] = sram_blwl_wl[1583:1583] ; -assign sram_blwl_1583_configbus0_b[1583:1583] = sram_blwl_blb[1583:1583] ; -sram6T_blwl sram_blwl_1583_ (sram_blwl_out[1583], sram_blwl_out[1583], sram_blwl_outb[1583], sram_blwl_1583_configbus0[1583:1583], sram_blwl_1583_configbus1[1583:1583] , sram_blwl_1583_configbus0_b[1583:1583] ); -wire [1584:1584] sram_blwl_1584_configbus0; -wire [1584:1584] sram_blwl_1584_configbus1; -wire [1584:1584] sram_blwl_1584_configbus0_b; -assign sram_blwl_1584_configbus0[1584:1584] = sram_blwl_bl[1584:1584] ; -assign sram_blwl_1584_configbus1[1584:1584] = sram_blwl_wl[1584:1584] ; -assign sram_blwl_1584_configbus0_b[1584:1584] = sram_blwl_blb[1584:1584] ; -sram6T_blwl sram_blwl_1584_ (sram_blwl_out[1584], sram_blwl_out[1584], sram_blwl_outb[1584], sram_blwl_1584_configbus0[1584:1584], sram_blwl_1584_configbus1[1584:1584] , sram_blwl_1584_configbus0_b[1584:1584] ); -wire [1585:1585] sram_blwl_1585_configbus0; -wire [1585:1585] sram_blwl_1585_configbus1; -wire [1585:1585] sram_blwl_1585_configbus0_b; -assign sram_blwl_1585_configbus0[1585:1585] = sram_blwl_bl[1585:1585] ; -assign sram_blwl_1585_configbus1[1585:1585] = sram_blwl_wl[1585:1585] ; -assign sram_blwl_1585_configbus0_b[1585:1585] = sram_blwl_blb[1585:1585] ; -sram6T_blwl sram_blwl_1585_ (sram_blwl_out[1585], sram_blwl_out[1585], sram_blwl_outb[1585], sram_blwl_1585_configbus0[1585:1585], sram_blwl_1585_configbus1[1585:1585] , sram_blwl_1585_configbus0_b[1585:1585] ); -wire [1586:1586] sram_blwl_1586_configbus0; -wire [1586:1586] sram_blwl_1586_configbus1; -wire [1586:1586] sram_blwl_1586_configbus0_b; -assign sram_blwl_1586_configbus0[1586:1586] = sram_blwl_bl[1586:1586] ; -assign sram_blwl_1586_configbus1[1586:1586] = sram_blwl_wl[1586:1586] ; -assign sram_blwl_1586_configbus0_b[1586:1586] = sram_blwl_blb[1586:1586] ; -sram6T_blwl sram_blwl_1586_ (sram_blwl_out[1586], sram_blwl_out[1586], sram_blwl_outb[1586], sram_blwl_1586_configbus0[1586:1586], sram_blwl_1586_configbus1[1586:1586] , sram_blwl_1586_configbus0_b[1586:1586] ); -wire [1587:1587] sram_blwl_1587_configbus0; -wire [1587:1587] sram_blwl_1587_configbus1; -wire [1587:1587] sram_blwl_1587_configbus0_b; -assign sram_blwl_1587_configbus0[1587:1587] = sram_blwl_bl[1587:1587] ; -assign sram_blwl_1587_configbus1[1587:1587] = sram_blwl_wl[1587:1587] ; -assign sram_blwl_1587_configbus0_b[1587:1587] = sram_blwl_blb[1587:1587] ; -sram6T_blwl sram_blwl_1587_ (sram_blwl_out[1587], sram_blwl_out[1587], sram_blwl_outb[1587], sram_blwl_1587_configbus0[1587:1587], sram_blwl_1587_configbus1[1587:1587] , sram_blwl_1587_configbus0_b[1587:1587] ); -wire [1588:1588] sram_blwl_1588_configbus0; -wire [1588:1588] sram_blwl_1588_configbus1; -wire [1588:1588] sram_blwl_1588_configbus0_b; -assign sram_blwl_1588_configbus0[1588:1588] = sram_blwl_bl[1588:1588] ; -assign sram_blwl_1588_configbus1[1588:1588] = sram_blwl_wl[1588:1588] ; -assign sram_blwl_1588_configbus0_b[1588:1588] = sram_blwl_blb[1588:1588] ; -sram6T_blwl sram_blwl_1588_ (sram_blwl_out[1588], sram_blwl_out[1588], sram_blwl_outb[1588], sram_blwl_1588_configbus0[1588:1588], sram_blwl_1588_configbus1[1588:1588] , sram_blwl_1588_configbus0_b[1588:1588] ); -wire [1589:1589] sram_blwl_1589_configbus0; -wire [1589:1589] sram_blwl_1589_configbus1; -wire [1589:1589] sram_blwl_1589_configbus0_b; -assign sram_blwl_1589_configbus0[1589:1589] = sram_blwl_bl[1589:1589] ; -assign sram_blwl_1589_configbus1[1589:1589] = sram_blwl_wl[1589:1589] ; -assign sram_blwl_1589_configbus0_b[1589:1589] = sram_blwl_blb[1589:1589] ; -sram6T_blwl sram_blwl_1589_ (sram_blwl_out[1589], sram_blwl_out[1589], sram_blwl_outb[1589], sram_blwl_1589_configbus0[1589:1589], sram_blwl_1589_configbus1[1589:1589] , sram_blwl_1589_configbus0_b[1589:1589] ); -wire [1590:1590] sram_blwl_1590_configbus0; -wire [1590:1590] sram_blwl_1590_configbus1; -wire [1590:1590] sram_blwl_1590_configbus0_b; -assign sram_blwl_1590_configbus0[1590:1590] = sram_blwl_bl[1590:1590] ; -assign sram_blwl_1590_configbus1[1590:1590] = sram_blwl_wl[1590:1590] ; -assign sram_blwl_1590_configbus0_b[1590:1590] = sram_blwl_blb[1590:1590] ; -sram6T_blwl sram_blwl_1590_ (sram_blwl_out[1590], sram_blwl_out[1590], sram_blwl_outb[1590], sram_blwl_1590_configbus0[1590:1590], sram_blwl_1590_configbus1[1590:1590] , sram_blwl_1590_configbus0_b[1590:1590] ); -wire [1591:1591] sram_blwl_1591_configbus0; -wire [1591:1591] sram_blwl_1591_configbus1; -wire [1591:1591] sram_blwl_1591_configbus0_b; -assign sram_blwl_1591_configbus0[1591:1591] = sram_blwl_bl[1591:1591] ; -assign sram_blwl_1591_configbus1[1591:1591] = sram_blwl_wl[1591:1591] ; -assign sram_blwl_1591_configbus0_b[1591:1591] = sram_blwl_blb[1591:1591] ; -sram6T_blwl sram_blwl_1591_ (sram_blwl_out[1591], sram_blwl_out[1591], sram_blwl_outb[1591], sram_blwl_1591_configbus0[1591:1591], sram_blwl_1591_configbus1[1591:1591] , sram_blwl_1591_configbus0_b[1591:1591] ); -wire [1592:1592] sram_blwl_1592_configbus0; -wire [1592:1592] sram_blwl_1592_configbus1; -wire [1592:1592] sram_blwl_1592_configbus0_b; -assign sram_blwl_1592_configbus0[1592:1592] = sram_blwl_bl[1592:1592] ; -assign sram_blwl_1592_configbus1[1592:1592] = sram_blwl_wl[1592:1592] ; -assign sram_blwl_1592_configbus0_b[1592:1592] = sram_blwl_blb[1592:1592] ; -sram6T_blwl sram_blwl_1592_ (sram_blwl_out[1592], sram_blwl_out[1592], sram_blwl_outb[1592], sram_blwl_1592_configbus0[1592:1592], sram_blwl_1592_configbus1[1592:1592] , sram_blwl_1592_configbus0_b[1592:1592] ); -wire [1593:1593] sram_blwl_1593_configbus0; -wire [1593:1593] sram_blwl_1593_configbus1; -wire [1593:1593] sram_blwl_1593_configbus0_b; -assign sram_blwl_1593_configbus0[1593:1593] = sram_blwl_bl[1593:1593] ; -assign sram_blwl_1593_configbus1[1593:1593] = sram_blwl_wl[1593:1593] ; -assign sram_blwl_1593_configbus0_b[1593:1593] = sram_blwl_blb[1593:1593] ; -sram6T_blwl sram_blwl_1593_ (sram_blwl_out[1593], sram_blwl_out[1593], sram_blwl_outb[1593], sram_blwl_1593_configbus0[1593:1593], sram_blwl_1593_configbus1[1593:1593] , sram_blwl_1593_configbus0_b[1593:1593] ); -wire [1594:1594] sram_blwl_1594_configbus0; -wire [1594:1594] sram_blwl_1594_configbus1; -wire [1594:1594] sram_blwl_1594_configbus0_b; -assign sram_blwl_1594_configbus0[1594:1594] = sram_blwl_bl[1594:1594] ; -assign sram_blwl_1594_configbus1[1594:1594] = sram_blwl_wl[1594:1594] ; -assign sram_blwl_1594_configbus0_b[1594:1594] = sram_blwl_blb[1594:1594] ; -sram6T_blwl sram_blwl_1594_ (sram_blwl_out[1594], sram_blwl_out[1594], sram_blwl_outb[1594], sram_blwl_1594_configbus0[1594:1594], sram_blwl_1594_configbus1[1594:1594] , sram_blwl_1594_configbus0_b[1594:1594] ); -wire [1595:1595] sram_blwl_1595_configbus0; -wire [1595:1595] sram_blwl_1595_configbus1; -wire [1595:1595] sram_blwl_1595_configbus0_b; -assign sram_blwl_1595_configbus0[1595:1595] = sram_blwl_bl[1595:1595] ; -assign sram_blwl_1595_configbus1[1595:1595] = sram_blwl_wl[1595:1595] ; -assign sram_blwl_1595_configbus0_b[1595:1595] = sram_blwl_blb[1595:1595] ; -sram6T_blwl sram_blwl_1595_ (sram_blwl_out[1595], sram_blwl_out[1595], sram_blwl_outb[1595], sram_blwl_1595_configbus0[1595:1595], sram_blwl_1595_configbus1[1595:1595] , sram_blwl_1595_configbus0_b[1595:1595] ); -wire [1596:1596] sram_blwl_1596_configbus0; -wire [1596:1596] sram_blwl_1596_configbus1; -wire [1596:1596] sram_blwl_1596_configbus0_b; -assign sram_blwl_1596_configbus0[1596:1596] = sram_blwl_bl[1596:1596] ; -assign sram_blwl_1596_configbus1[1596:1596] = sram_blwl_wl[1596:1596] ; -assign sram_blwl_1596_configbus0_b[1596:1596] = sram_blwl_blb[1596:1596] ; -sram6T_blwl sram_blwl_1596_ (sram_blwl_out[1596], sram_blwl_out[1596], sram_blwl_outb[1596], sram_blwl_1596_configbus0[1596:1596], sram_blwl_1596_configbus1[1596:1596] , sram_blwl_1596_configbus0_b[1596:1596] ); -wire [1597:1597] sram_blwl_1597_configbus0; -wire [1597:1597] sram_blwl_1597_configbus1; -wire [1597:1597] sram_blwl_1597_configbus0_b; -assign sram_blwl_1597_configbus0[1597:1597] = sram_blwl_bl[1597:1597] ; -assign sram_blwl_1597_configbus1[1597:1597] = sram_blwl_wl[1597:1597] ; -assign sram_blwl_1597_configbus0_b[1597:1597] = sram_blwl_blb[1597:1597] ; -sram6T_blwl sram_blwl_1597_ (sram_blwl_out[1597], sram_blwl_out[1597], sram_blwl_outb[1597], sram_blwl_1597_configbus0[1597:1597], sram_blwl_1597_configbus1[1597:1597] , sram_blwl_1597_configbus0_b[1597:1597] ); -wire [1598:1598] sram_blwl_1598_configbus0; -wire [1598:1598] sram_blwl_1598_configbus1; -wire [1598:1598] sram_blwl_1598_configbus0_b; -assign sram_blwl_1598_configbus0[1598:1598] = sram_blwl_bl[1598:1598] ; -assign sram_blwl_1598_configbus1[1598:1598] = sram_blwl_wl[1598:1598] ; -assign sram_blwl_1598_configbus0_b[1598:1598] = sram_blwl_blb[1598:1598] ; -sram6T_blwl sram_blwl_1598_ (sram_blwl_out[1598], sram_blwl_out[1598], sram_blwl_outb[1598], sram_blwl_1598_configbus0[1598:1598], sram_blwl_1598_configbus1[1598:1598] , sram_blwl_1598_configbus0_b[1598:1598] ); -wire [1599:1599] sram_blwl_1599_configbus0; -wire [1599:1599] sram_blwl_1599_configbus1; -wire [1599:1599] sram_blwl_1599_configbus0_b; -assign sram_blwl_1599_configbus0[1599:1599] = sram_blwl_bl[1599:1599] ; -assign sram_blwl_1599_configbus1[1599:1599] = sram_blwl_wl[1599:1599] ; -assign sram_blwl_1599_configbus0_b[1599:1599] = sram_blwl_blb[1599:1599] ; -sram6T_blwl sram_blwl_1599_ (sram_blwl_out[1599], sram_blwl_out[1599], sram_blwl_outb[1599], sram_blwl_1599_configbus0[1599:1599], sram_blwl_1599_configbus1[1599:1599] , sram_blwl_1599_configbus0_b[1599:1599] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- - -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_8_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6_ ----- -module grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble6___in_0_, -input wire mode_ble6___in_1_, -input wire mode_ble6___in_2_, -input wire mode_ble6___in_3_, -input wire mode_ble6___in_4_, -input wire mode_ble6___in_5_, -output wire mode_ble6___out_0_, -input wire mode_ble6___clk_0_, -input [1536:1600] sram_blwl_bl , -input [1536:1600] sram_blwl_wl , -input [1536:1600] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ lut6_0_ ( - lut6_0___in_0_, lut6_0___in_1_, lut6_0___in_2_, lut6_0___in_3_, lut6_0___in_4_, lut6_0___in_5_, lut6_0___out_0_, -sram_blwl_bl[1536:1599] , -sram_blwl_wl[1536:1599] , -sram_blwl_blb[1536:1599] ); -grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_408_ ; -assign in_bus_mux_1level_tapbuf_size2_408_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_408_[1] = lut6_0___out_0_ ; -wire [1600:1600] mux_1level_tapbuf_size2_408_configbus0; -wire [1600:1600] mux_1level_tapbuf_size2_408_configbus1; -wire [1600:1600] mux_1level_tapbuf_size2_408_sram_blwl_out ; -wire [1600:1600] mux_1level_tapbuf_size2_408_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_408_configbus0[1600:1600] = sram_blwl_bl[1600:1600] ; -assign mux_1level_tapbuf_size2_408_configbus1[1600:1600] = sram_blwl_wl[1600:1600] ; -wire [1600:1600] mux_1level_tapbuf_size2_408_configbus0_b; -assign mux_1level_tapbuf_size2_408_configbus0_b[1600:1600] = sram_blwl_blb[1600:1600] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_408_ (in_bus_mux_1level_tapbuf_size2_408_, mode_ble6___out_0_, mux_1level_tapbuf_size2_408_sram_blwl_out[1600:1600] , -mux_1level_tapbuf_size2_408_sram_blwl_outb[1600:1600] ); -//----- SRAM bits for MUX[408], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1600_ (mux_1level_tapbuf_size2_408_sram_blwl_out[1600:1600] ,mux_1level_tapbuf_size2_408_sram_blwl_out[1600:1600] ,mux_1level_tapbuf_size2_408_sram_blwl_outb[1600:1600] ,mux_1level_tapbuf_size2_408_configbus0[1600:1600], mux_1level_tapbuf_size2_408_configbus1[1600:1600] , mux_1level_tapbuf_size2_408_configbus0_b[1600:1600] ); -direct_interc direct_interc_128_ (mode_ble6___in_0_, lut6_0___in_0_ ); -direct_interc direct_interc_129_ (mode_ble6___in_1_, lut6_0___in_1_ ); -direct_interc direct_interc_130_ (mode_ble6___in_2_, lut6_0___in_2_ ); -direct_interc direct_interc_131_ (mode_ble6___in_3_, lut6_0___in_3_ ); -direct_interc direct_interc_132_ (mode_ble6___in_4_, lut6_0___in_4_ ); -direct_interc direct_interc_133_ (mode_ble6___in_5_, lut6_0___in_5_ ); -direct_interc direct_interc_134_ (lut6_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_135_ (mode_ble6___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6_ ----- - -//----- Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6_ ----- -module grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut6___in_0_, -input wire mode_n1_lut6___in_1_, -input wire mode_n1_lut6___in_2_, -input wire mode_n1_lut6___in_3_, -input wire mode_n1_lut6___in_4_, -input wire mode_n1_lut6___in_5_, -output wire mode_n1_lut6___out_0_, -input wire mode_n1_lut6___clk_0_, -input [1536:1600] sram_blwl_bl , -input [1536:1600] sram_blwl_wl , -input [1536:1600] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6__ble6_0__mode_ble6_ ble6_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble6_0___in_0_, ble6_0___in_1_, ble6_0___in_2_, ble6_0___in_3_, ble6_0___in_4_, ble6_0___in_5_, ble6_0___out_0_, ble6_0___clk_0_, -sram_blwl_bl[1536:1600] , -sram_blwl_wl[1536:1600] , -sram_blwl_blb[1536:1600] ); -direct_interc direct_interc_136_ (ble6_0___out_0_, mode_n1_lut6___out_0_ ); -direct_interc direct_interc_137_ (mode_n1_lut6___in_0_, ble6_0___in_0_ ); -direct_interc direct_interc_138_ (mode_n1_lut6___in_1_, ble6_0___in_1_ ); -direct_interc direct_interc_139_ (mode_n1_lut6___in_2_, ble6_0___in_2_ ); -direct_interc direct_interc_140_ (mode_n1_lut6___in_3_, ble6_0___in_3_ ); -direct_interc direct_interc_141_ (mode_n1_lut6___in_4_, ble6_0___in_4_ ); -direct_interc direct_interc_142_ (mode_n1_lut6___in_5_, ble6_0___in_5_ ); -direct_interc direct_interc_143_ (mode_n1_lut6___clk_0_, ble6_0___clk_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6_ ----- - -//----- LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ( -input wire lut6_0___in_0_, -input wire lut6_0___in_1_, -input wire lut6_0___in_2_, -input wire lut6_0___in_3_, -input wire lut6_0___in_4_, -input wire lut6_0___in_5_, -output wire lut6_0___out_0_, -input [1601:1664] sram_blwl_bl , -input [1601:1664] sram_blwl_wl , -input [1601:1664] sram_blwl_blb ); -wire [0:5] lut6_0___in; -assign lut6_0___in[0] = lut6_0___in_0_; -assign lut6_0___in[1] = lut6_0___in_1_; -assign lut6_0___in[2] = lut6_0___in_2_; -assign lut6_0___in[3] = lut6_0___in_3_; -assign lut6_0___in[4] = lut6_0___in_4_; -assign lut6_0___in[5] = lut6_0___in_5_; -wire [0:0] lut6_0___out; -assign lut6_0___out_0_ = lut6_0___out[0]; -wire [1601:1664] sram_blwl_out ; -wire [1601:1664] sram_blwl_outb ; -lut6 lut6_9_ ( -//----- Input and output ports ----- - lut6_0___in[0:5] , lut6_0___out[0:0],//----- SRAM ports ----- -sram_blwl_out[1601:1664] , sram_blwl_outb[1601:1664] ); -//----- Truth Table for LUT node (n7). ----- -//----- Truth Table for LUT[9], size=6. ----- -// 0----- 1 -//----- SRAM bits for LUT[9], size=6, num_sram=64. ----- -//-----0101010101010101010101010101010101010101010101010101010101010101----- -wire [1601:1601] sram_blwl_1601_configbus0; -wire [1601:1601] sram_blwl_1601_configbus1; -wire [1601:1601] sram_blwl_1601_configbus0_b; -assign sram_blwl_1601_configbus0[1601:1601] = sram_blwl_bl[1601:1601] ; -assign sram_blwl_1601_configbus1[1601:1601] = sram_blwl_wl[1601:1601] ; -assign sram_blwl_1601_configbus0_b[1601:1601] = sram_blwl_blb[1601:1601] ; -sram6T_blwl sram_blwl_1601_ (sram_blwl_out[1601], sram_blwl_out[1601], sram_blwl_outb[1601], sram_blwl_1601_configbus0[1601:1601], sram_blwl_1601_configbus1[1601:1601] , sram_blwl_1601_configbus0_b[1601:1601] ); -wire [1602:1602] sram_blwl_1602_configbus0; -wire [1602:1602] sram_blwl_1602_configbus1; -wire [1602:1602] sram_blwl_1602_configbus0_b; -assign sram_blwl_1602_configbus0[1602:1602] = sram_blwl_bl[1602:1602] ; -assign sram_blwl_1602_configbus1[1602:1602] = sram_blwl_wl[1602:1602] ; -assign sram_blwl_1602_configbus0_b[1602:1602] = sram_blwl_blb[1602:1602] ; -sram6T_blwl sram_blwl_1602_ (sram_blwl_out[1602], sram_blwl_out[1602], sram_blwl_outb[1602], sram_blwl_1602_configbus0[1602:1602], sram_blwl_1602_configbus1[1602:1602] , sram_blwl_1602_configbus0_b[1602:1602] ); -wire [1603:1603] sram_blwl_1603_configbus0; -wire [1603:1603] sram_blwl_1603_configbus1; -wire [1603:1603] sram_blwl_1603_configbus0_b; -assign sram_blwl_1603_configbus0[1603:1603] = sram_blwl_bl[1603:1603] ; -assign sram_blwl_1603_configbus1[1603:1603] = sram_blwl_wl[1603:1603] ; -assign sram_blwl_1603_configbus0_b[1603:1603] = sram_blwl_blb[1603:1603] ; -sram6T_blwl sram_blwl_1603_ (sram_blwl_out[1603], sram_blwl_out[1603], sram_blwl_outb[1603], sram_blwl_1603_configbus0[1603:1603], sram_blwl_1603_configbus1[1603:1603] , sram_blwl_1603_configbus0_b[1603:1603] ); -wire [1604:1604] sram_blwl_1604_configbus0; -wire [1604:1604] sram_blwl_1604_configbus1; -wire [1604:1604] sram_blwl_1604_configbus0_b; -assign sram_blwl_1604_configbus0[1604:1604] = sram_blwl_bl[1604:1604] ; -assign sram_blwl_1604_configbus1[1604:1604] = sram_blwl_wl[1604:1604] ; -assign sram_blwl_1604_configbus0_b[1604:1604] = sram_blwl_blb[1604:1604] ; -sram6T_blwl sram_blwl_1604_ (sram_blwl_out[1604], sram_blwl_out[1604], sram_blwl_outb[1604], sram_blwl_1604_configbus0[1604:1604], sram_blwl_1604_configbus1[1604:1604] , sram_blwl_1604_configbus0_b[1604:1604] ); -wire [1605:1605] sram_blwl_1605_configbus0; -wire [1605:1605] sram_blwl_1605_configbus1; -wire [1605:1605] sram_blwl_1605_configbus0_b; -assign sram_blwl_1605_configbus0[1605:1605] = sram_blwl_bl[1605:1605] ; -assign sram_blwl_1605_configbus1[1605:1605] = sram_blwl_wl[1605:1605] ; -assign sram_blwl_1605_configbus0_b[1605:1605] = sram_blwl_blb[1605:1605] ; -sram6T_blwl sram_blwl_1605_ (sram_blwl_out[1605], sram_blwl_out[1605], sram_blwl_outb[1605], sram_blwl_1605_configbus0[1605:1605], sram_blwl_1605_configbus1[1605:1605] , sram_blwl_1605_configbus0_b[1605:1605] ); -wire [1606:1606] sram_blwl_1606_configbus0; -wire [1606:1606] sram_blwl_1606_configbus1; -wire [1606:1606] sram_blwl_1606_configbus0_b; -assign sram_blwl_1606_configbus0[1606:1606] = sram_blwl_bl[1606:1606] ; -assign sram_blwl_1606_configbus1[1606:1606] = sram_blwl_wl[1606:1606] ; -assign sram_blwl_1606_configbus0_b[1606:1606] = sram_blwl_blb[1606:1606] ; -sram6T_blwl sram_blwl_1606_ (sram_blwl_out[1606], sram_blwl_out[1606], sram_blwl_outb[1606], sram_blwl_1606_configbus0[1606:1606], sram_blwl_1606_configbus1[1606:1606] , sram_blwl_1606_configbus0_b[1606:1606] ); -wire [1607:1607] sram_blwl_1607_configbus0; -wire [1607:1607] sram_blwl_1607_configbus1; -wire [1607:1607] sram_blwl_1607_configbus0_b; -assign sram_blwl_1607_configbus0[1607:1607] = sram_blwl_bl[1607:1607] ; -assign sram_blwl_1607_configbus1[1607:1607] = sram_blwl_wl[1607:1607] ; -assign sram_blwl_1607_configbus0_b[1607:1607] = sram_blwl_blb[1607:1607] ; -sram6T_blwl sram_blwl_1607_ (sram_blwl_out[1607], sram_blwl_out[1607], sram_blwl_outb[1607], sram_blwl_1607_configbus0[1607:1607], sram_blwl_1607_configbus1[1607:1607] , sram_blwl_1607_configbus0_b[1607:1607] ); -wire [1608:1608] sram_blwl_1608_configbus0; -wire [1608:1608] sram_blwl_1608_configbus1; -wire [1608:1608] sram_blwl_1608_configbus0_b; -assign sram_blwl_1608_configbus0[1608:1608] = sram_blwl_bl[1608:1608] ; -assign sram_blwl_1608_configbus1[1608:1608] = sram_blwl_wl[1608:1608] ; -assign sram_blwl_1608_configbus0_b[1608:1608] = sram_blwl_blb[1608:1608] ; -sram6T_blwl sram_blwl_1608_ (sram_blwl_out[1608], sram_blwl_out[1608], sram_blwl_outb[1608], sram_blwl_1608_configbus0[1608:1608], sram_blwl_1608_configbus1[1608:1608] , sram_blwl_1608_configbus0_b[1608:1608] ); -wire [1609:1609] sram_blwl_1609_configbus0; -wire [1609:1609] sram_blwl_1609_configbus1; -wire [1609:1609] sram_blwl_1609_configbus0_b; -assign sram_blwl_1609_configbus0[1609:1609] = sram_blwl_bl[1609:1609] ; -assign sram_blwl_1609_configbus1[1609:1609] = sram_blwl_wl[1609:1609] ; -assign sram_blwl_1609_configbus0_b[1609:1609] = sram_blwl_blb[1609:1609] ; -sram6T_blwl sram_blwl_1609_ (sram_blwl_out[1609], sram_blwl_out[1609], sram_blwl_outb[1609], sram_blwl_1609_configbus0[1609:1609], sram_blwl_1609_configbus1[1609:1609] , sram_blwl_1609_configbus0_b[1609:1609] ); -wire [1610:1610] sram_blwl_1610_configbus0; -wire [1610:1610] sram_blwl_1610_configbus1; -wire [1610:1610] sram_blwl_1610_configbus0_b; -assign sram_blwl_1610_configbus0[1610:1610] = sram_blwl_bl[1610:1610] ; -assign sram_blwl_1610_configbus1[1610:1610] = sram_blwl_wl[1610:1610] ; -assign sram_blwl_1610_configbus0_b[1610:1610] = sram_blwl_blb[1610:1610] ; -sram6T_blwl sram_blwl_1610_ (sram_blwl_out[1610], sram_blwl_out[1610], sram_blwl_outb[1610], sram_blwl_1610_configbus0[1610:1610], sram_blwl_1610_configbus1[1610:1610] , sram_blwl_1610_configbus0_b[1610:1610] ); -wire [1611:1611] sram_blwl_1611_configbus0; -wire [1611:1611] sram_blwl_1611_configbus1; -wire [1611:1611] sram_blwl_1611_configbus0_b; -assign sram_blwl_1611_configbus0[1611:1611] = sram_blwl_bl[1611:1611] ; -assign sram_blwl_1611_configbus1[1611:1611] = sram_blwl_wl[1611:1611] ; -assign sram_blwl_1611_configbus0_b[1611:1611] = sram_blwl_blb[1611:1611] ; -sram6T_blwl sram_blwl_1611_ (sram_blwl_out[1611], sram_blwl_out[1611], sram_blwl_outb[1611], sram_blwl_1611_configbus0[1611:1611], sram_blwl_1611_configbus1[1611:1611] , sram_blwl_1611_configbus0_b[1611:1611] ); -wire [1612:1612] sram_blwl_1612_configbus0; -wire [1612:1612] sram_blwl_1612_configbus1; -wire [1612:1612] sram_blwl_1612_configbus0_b; -assign sram_blwl_1612_configbus0[1612:1612] = sram_blwl_bl[1612:1612] ; -assign sram_blwl_1612_configbus1[1612:1612] = sram_blwl_wl[1612:1612] ; -assign sram_blwl_1612_configbus0_b[1612:1612] = sram_blwl_blb[1612:1612] ; -sram6T_blwl sram_blwl_1612_ (sram_blwl_out[1612], sram_blwl_out[1612], sram_blwl_outb[1612], sram_blwl_1612_configbus0[1612:1612], sram_blwl_1612_configbus1[1612:1612] , sram_blwl_1612_configbus0_b[1612:1612] ); -wire [1613:1613] sram_blwl_1613_configbus0; -wire [1613:1613] sram_blwl_1613_configbus1; -wire [1613:1613] sram_blwl_1613_configbus0_b; -assign sram_blwl_1613_configbus0[1613:1613] = sram_blwl_bl[1613:1613] ; -assign sram_blwl_1613_configbus1[1613:1613] = sram_blwl_wl[1613:1613] ; -assign sram_blwl_1613_configbus0_b[1613:1613] = sram_blwl_blb[1613:1613] ; -sram6T_blwl sram_blwl_1613_ (sram_blwl_out[1613], sram_blwl_out[1613], sram_blwl_outb[1613], sram_blwl_1613_configbus0[1613:1613], sram_blwl_1613_configbus1[1613:1613] , sram_blwl_1613_configbus0_b[1613:1613] ); -wire [1614:1614] sram_blwl_1614_configbus0; -wire [1614:1614] sram_blwl_1614_configbus1; -wire [1614:1614] sram_blwl_1614_configbus0_b; -assign sram_blwl_1614_configbus0[1614:1614] = sram_blwl_bl[1614:1614] ; -assign sram_blwl_1614_configbus1[1614:1614] = sram_blwl_wl[1614:1614] ; -assign sram_blwl_1614_configbus0_b[1614:1614] = sram_blwl_blb[1614:1614] ; -sram6T_blwl sram_blwl_1614_ (sram_blwl_out[1614], sram_blwl_out[1614], sram_blwl_outb[1614], sram_blwl_1614_configbus0[1614:1614], sram_blwl_1614_configbus1[1614:1614] , sram_blwl_1614_configbus0_b[1614:1614] ); -wire [1615:1615] sram_blwl_1615_configbus0; -wire [1615:1615] sram_blwl_1615_configbus1; -wire [1615:1615] sram_blwl_1615_configbus0_b; -assign sram_blwl_1615_configbus0[1615:1615] = sram_blwl_bl[1615:1615] ; -assign sram_blwl_1615_configbus1[1615:1615] = sram_blwl_wl[1615:1615] ; -assign sram_blwl_1615_configbus0_b[1615:1615] = sram_blwl_blb[1615:1615] ; -sram6T_blwl sram_blwl_1615_ (sram_blwl_out[1615], sram_blwl_out[1615], sram_blwl_outb[1615], sram_blwl_1615_configbus0[1615:1615], sram_blwl_1615_configbus1[1615:1615] , sram_blwl_1615_configbus0_b[1615:1615] ); -wire [1616:1616] sram_blwl_1616_configbus0; -wire [1616:1616] sram_blwl_1616_configbus1; -wire [1616:1616] sram_blwl_1616_configbus0_b; -assign sram_blwl_1616_configbus0[1616:1616] = sram_blwl_bl[1616:1616] ; -assign sram_blwl_1616_configbus1[1616:1616] = sram_blwl_wl[1616:1616] ; -assign sram_blwl_1616_configbus0_b[1616:1616] = sram_blwl_blb[1616:1616] ; -sram6T_blwl sram_blwl_1616_ (sram_blwl_out[1616], sram_blwl_out[1616], sram_blwl_outb[1616], sram_blwl_1616_configbus0[1616:1616], sram_blwl_1616_configbus1[1616:1616] , sram_blwl_1616_configbus0_b[1616:1616] ); -wire [1617:1617] sram_blwl_1617_configbus0; -wire [1617:1617] sram_blwl_1617_configbus1; -wire [1617:1617] sram_blwl_1617_configbus0_b; -assign sram_blwl_1617_configbus0[1617:1617] = sram_blwl_bl[1617:1617] ; -assign sram_blwl_1617_configbus1[1617:1617] = sram_blwl_wl[1617:1617] ; -assign sram_blwl_1617_configbus0_b[1617:1617] = sram_blwl_blb[1617:1617] ; -sram6T_blwl sram_blwl_1617_ (sram_blwl_out[1617], sram_blwl_out[1617], sram_blwl_outb[1617], sram_blwl_1617_configbus0[1617:1617], sram_blwl_1617_configbus1[1617:1617] , sram_blwl_1617_configbus0_b[1617:1617] ); -wire [1618:1618] sram_blwl_1618_configbus0; -wire [1618:1618] sram_blwl_1618_configbus1; -wire [1618:1618] sram_blwl_1618_configbus0_b; -assign sram_blwl_1618_configbus0[1618:1618] = sram_blwl_bl[1618:1618] ; -assign sram_blwl_1618_configbus1[1618:1618] = sram_blwl_wl[1618:1618] ; -assign sram_blwl_1618_configbus0_b[1618:1618] = sram_blwl_blb[1618:1618] ; -sram6T_blwl sram_blwl_1618_ (sram_blwl_out[1618], sram_blwl_out[1618], sram_blwl_outb[1618], sram_blwl_1618_configbus0[1618:1618], sram_blwl_1618_configbus1[1618:1618] , sram_blwl_1618_configbus0_b[1618:1618] ); -wire [1619:1619] sram_blwl_1619_configbus0; -wire [1619:1619] sram_blwl_1619_configbus1; -wire [1619:1619] sram_blwl_1619_configbus0_b; -assign sram_blwl_1619_configbus0[1619:1619] = sram_blwl_bl[1619:1619] ; -assign sram_blwl_1619_configbus1[1619:1619] = sram_blwl_wl[1619:1619] ; -assign sram_blwl_1619_configbus0_b[1619:1619] = sram_blwl_blb[1619:1619] ; -sram6T_blwl sram_blwl_1619_ (sram_blwl_out[1619], sram_blwl_out[1619], sram_blwl_outb[1619], sram_blwl_1619_configbus0[1619:1619], sram_blwl_1619_configbus1[1619:1619] , sram_blwl_1619_configbus0_b[1619:1619] ); -wire [1620:1620] sram_blwl_1620_configbus0; -wire [1620:1620] sram_blwl_1620_configbus1; -wire [1620:1620] sram_blwl_1620_configbus0_b; -assign sram_blwl_1620_configbus0[1620:1620] = sram_blwl_bl[1620:1620] ; -assign sram_blwl_1620_configbus1[1620:1620] = sram_blwl_wl[1620:1620] ; -assign sram_blwl_1620_configbus0_b[1620:1620] = sram_blwl_blb[1620:1620] ; -sram6T_blwl sram_blwl_1620_ (sram_blwl_out[1620], sram_blwl_out[1620], sram_blwl_outb[1620], sram_blwl_1620_configbus0[1620:1620], sram_blwl_1620_configbus1[1620:1620] , sram_blwl_1620_configbus0_b[1620:1620] ); -wire [1621:1621] sram_blwl_1621_configbus0; -wire [1621:1621] sram_blwl_1621_configbus1; -wire [1621:1621] sram_blwl_1621_configbus0_b; -assign sram_blwl_1621_configbus0[1621:1621] = sram_blwl_bl[1621:1621] ; -assign sram_blwl_1621_configbus1[1621:1621] = sram_blwl_wl[1621:1621] ; -assign sram_blwl_1621_configbus0_b[1621:1621] = sram_blwl_blb[1621:1621] ; -sram6T_blwl sram_blwl_1621_ (sram_blwl_out[1621], sram_blwl_out[1621], sram_blwl_outb[1621], sram_blwl_1621_configbus0[1621:1621], sram_blwl_1621_configbus1[1621:1621] , sram_blwl_1621_configbus0_b[1621:1621] ); -wire [1622:1622] sram_blwl_1622_configbus0; -wire [1622:1622] sram_blwl_1622_configbus1; -wire [1622:1622] sram_blwl_1622_configbus0_b; -assign sram_blwl_1622_configbus0[1622:1622] = sram_blwl_bl[1622:1622] ; -assign sram_blwl_1622_configbus1[1622:1622] = sram_blwl_wl[1622:1622] ; -assign sram_blwl_1622_configbus0_b[1622:1622] = sram_blwl_blb[1622:1622] ; -sram6T_blwl sram_blwl_1622_ (sram_blwl_out[1622], sram_blwl_out[1622], sram_blwl_outb[1622], sram_blwl_1622_configbus0[1622:1622], sram_blwl_1622_configbus1[1622:1622] , sram_blwl_1622_configbus0_b[1622:1622] ); -wire [1623:1623] sram_blwl_1623_configbus0; -wire [1623:1623] sram_blwl_1623_configbus1; -wire [1623:1623] sram_blwl_1623_configbus0_b; -assign sram_blwl_1623_configbus0[1623:1623] = sram_blwl_bl[1623:1623] ; -assign sram_blwl_1623_configbus1[1623:1623] = sram_blwl_wl[1623:1623] ; -assign sram_blwl_1623_configbus0_b[1623:1623] = sram_blwl_blb[1623:1623] ; -sram6T_blwl sram_blwl_1623_ (sram_blwl_out[1623], sram_blwl_out[1623], sram_blwl_outb[1623], sram_blwl_1623_configbus0[1623:1623], sram_blwl_1623_configbus1[1623:1623] , sram_blwl_1623_configbus0_b[1623:1623] ); -wire [1624:1624] sram_blwl_1624_configbus0; -wire [1624:1624] sram_blwl_1624_configbus1; -wire [1624:1624] sram_blwl_1624_configbus0_b; -assign sram_blwl_1624_configbus0[1624:1624] = sram_blwl_bl[1624:1624] ; -assign sram_blwl_1624_configbus1[1624:1624] = sram_blwl_wl[1624:1624] ; -assign sram_blwl_1624_configbus0_b[1624:1624] = sram_blwl_blb[1624:1624] ; -sram6T_blwl sram_blwl_1624_ (sram_blwl_out[1624], sram_blwl_out[1624], sram_blwl_outb[1624], sram_blwl_1624_configbus0[1624:1624], sram_blwl_1624_configbus1[1624:1624] , sram_blwl_1624_configbus0_b[1624:1624] ); -wire [1625:1625] sram_blwl_1625_configbus0; -wire [1625:1625] sram_blwl_1625_configbus1; -wire [1625:1625] sram_blwl_1625_configbus0_b; -assign sram_blwl_1625_configbus0[1625:1625] = sram_blwl_bl[1625:1625] ; -assign sram_blwl_1625_configbus1[1625:1625] = sram_blwl_wl[1625:1625] ; -assign sram_blwl_1625_configbus0_b[1625:1625] = sram_blwl_blb[1625:1625] ; -sram6T_blwl sram_blwl_1625_ (sram_blwl_out[1625], sram_blwl_out[1625], sram_blwl_outb[1625], sram_blwl_1625_configbus0[1625:1625], sram_blwl_1625_configbus1[1625:1625] , sram_blwl_1625_configbus0_b[1625:1625] ); -wire [1626:1626] sram_blwl_1626_configbus0; -wire [1626:1626] sram_blwl_1626_configbus1; -wire [1626:1626] sram_blwl_1626_configbus0_b; -assign sram_blwl_1626_configbus0[1626:1626] = sram_blwl_bl[1626:1626] ; -assign sram_blwl_1626_configbus1[1626:1626] = sram_blwl_wl[1626:1626] ; -assign sram_blwl_1626_configbus0_b[1626:1626] = sram_blwl_blb[1626:1626] ; -sram6T_blwl sram_blwl_1626_ (sram_blwl_out[1626], sram_blwl_out[1626], sram_blwl_outb[1626], sram_blwl_1626_configbus0[1626:1626], sram_blwl_1626_configbus1[1626:1626] , sram_blwl_1626_configbus0_b[1626:1626] ); -wire [1627:1627] sram_blwl_1627_configbus0; -wire [1627:1627] sram_blwl_1627_configbus1; -wire [1627:1627] sram_blwl_1627_configbus0_b; -assign sram_blwl_1627_configbus0[1627:1627] = sram_blwl_bl[1627:1627] ; -assign sram_blwl_1627_configbus1[1627:1627] = sram_blwl_wl[1627:1627] ; -assign sram_blwl_1627_configbus0_b[1627:1627] = sram_blwl_blb[1627:1627] ; -sram6T_blwl sram_blwl_1627_ (sram_blwl_out[1627], sram_blwl_out[1627], sram_blwl_outb[1627], sram_blwl_1627_configbus0[1627:1627], sram_blwl_1627_configbus1[1627:1627] , sram_blwl_1627_configbus0_b[1627:1627] ); -wire [1628:1628] sram_blwl_1628_configbus0; -wire [1628:1628] sram_blwl_1628_configbus1; -wire [1628:1628] sram_blwl_1628_configbus0_b; -assign sram_blwl_1628_configbus0[1628:1628] = sram_blwl_bl[1628:1628] ; -assign sram_blwl_1628_configbus1[1628:1628] = sram_blwl_wl[1628:1628] ; -assign sram_blwl_1628_configbus0_b[1628:1628] = sram_blwl_blb[1628:1628] ; -sram6T_blwl sram_blwl_1628_ (sram_blwl_out[1628], sram_blwl_out[1628], sram_blwl_outb[1628], sram_blwl_1628_configbus0[1628:1628], sram_blwl_1628_configbus1[1628:1628] , sram_blwl_1628_configbus0_b[1628:1628] ); -wire [1629:1629] sram_blwl_1629_configbus0; -wire [1629:1629] sram_blwl_1629_configbus1; -wire [1629:1629] sram_blwl_1629_configbus0_b; -assign sram_blwl_1629_configbus0[1629:1629] = sram_blwl_bl[1629:1629] ; -assign sram_blwl_1629_configbus1[1629:1629] = sram_blwl_wl[1629:1629] ; -assign sram_blwl_1629_configbus0_b[1629:1629] = sram_blwl_blb[1629:1629] ; -sram6T_blwl sram_blwl_1629_ (sram_blwl_out[1629], sram_blwl_out[1629], sram_blwl_outb[1629], sram_blwl_1629_configbus0[1629:1629], sram_blwl_1629_configbus1[1629:1629] , sram_blwl_1629_configbus0_b[1629:1629] ); -wire [1630:1630] sram_blwl_1630_configbus0; -wire [1630:1630] sram_blwl_1630_configbus1; -wire [1630:1630] sram_blwl_1630_configbus0_b; -assign sram_blwl_1630_configbus0[1630:1630] = sram_blwl_bl[1630:1630] ; -assign sram_blwl_1630_configbus1[1630:1630] = sram_blwl_wl[1630:1630] ; -assign sram_blwl_1630_configbus0_b[1630:1630] = sram_blwl_blb[1630:1630] ; -sram6T_blwl sram_blwl_1630_ (sram_blwl_out[1630], sram_blwl_out[1630], sram_blwl_outb[1630], sram_blwl_1630_configbus0[1630:1630], sram_blwl_1630_configbus1[1630:1630] , sram_blwl_1630_configbus0_b[1630:1630] ); -wire [1631:1631] sram_blwl_1631_configbus0; -wire [1631:1631] sram_blwl_1631_configbus1; -wire [1631:1631] sram_blwl_1631_configbus0_b; -assign sram_blwl_1631_configbus0[1631:1631] = sram_blwl_bl[1631:1631] ; -assign sram_blwl_1631_configbus1[1631:1631] = sram_blwl_wl[1631:1631] ; -assign sram_blwl_1631_configbus0_b[1631:1631] = sram_blwl_blb[1631:1631] ; -sram6T_blwl sram_blwl_1631_ (sram_blwl_out[1631], sram_blwl_out[1631], sram_blwl_outb[1631], sram_blwl_1631_configbus0[1631:1631], sram_blwl_1631_configbus1[1631:1631] , sram_blwl_1631_configbus0_b[1631:1631] ); -wire [1632:1632] sram_blwl_1632_configbus0; -wire [1632:1632] sram_blwl_1632_configbus1; -wire [1632:1632] sram_blwl_1632_configbus0_b; -assign sram_blwl_1632_configbus0[1632:1632] = sram_blwl_bl[1632:1632] ; -assign sram_blwl_1632_configbus1[1632:1632] = sram_blwl_wl[1632:1632] ; -assign sram_blwl_1632_configbus0_b[1632:1632] = sram_blwl_blb[1632:1632] ; -sram6T_blwl sram_blwl_1632_ (sram_blwl_out[1632], sram_blwl_out[1632], sram_blwl_outb[1632], sram_blwl_1632_configbus0[1632:1632], sram_blwl_1632_configbus1[1632:1632] , sram_blwl_1632_configbus0_b[1632:1632] ); -wire [1633:1633] sram_blwl_1633_configbus0; -wire [1633:1633] sram_blwl_1633_configbus1; -wire [1633:1633] sram_blwl_1633_configbus0_b; -assign sram_blwl_1633_configbus0[1633:1633] = sram_blwl_bl[1633:1633] ; -assign sram_blwl_1633_configbus1[1633:1633] = sram_blwl_wl[1633:1633] ; -assign sram_blwl_1633_configbus0_b[1633:1633] = sram_blwl_blb[1633:1633] ; -sram6T_blwl sram_blwl_1633_ (sram_blwl_out[1633], sram_blwl_out[1633], sram_blwl_outb[1633], sram_blwl_1633_configbus0[1633:1633], sram_blwl_1633_configbus1[1633:1633] , sram_blwl_1633_configbus0_b[1633:1633] ); -wire [1634:1634] sram_blwl_1634_configbus0; -wire [1634:1634] sram_blwl_1634_configbus1; -wire [1634:1634] sram_blwl_1634_configbus0_b; -assign sram_blwl_1634_configbus0[1634:1634] = sram_blwl_bl[1634:1634] ; -assign sram_blwl_1634_configbus1[1634:1634] = sram_blwl_wl[1634:1634] ; -assign sram_blwl_1634_configbus0_b[1634:1634] = sram_blwl_blb[1634:1634] ; -sram6T_blwl sram_blwl_1634_ (sram_blwl_out[1634], sram_blwl_out[1634], sram_blwl_outb[1634], sram_blwl_1634_configbus0[1634:1634], sram_blwl_1634_configbus1[1634:1634] , sram_blwl_1634_configbus0_b[1634:1634] ); -wire [1635:1635] sram_blwl_1635_configbus0; -wire [1635:1635] sram_blwl_1635_configbus1; -wire [1635:1635] sram_blwl_1635_configbus0_b; -assign sram_blwl_1635_configbus0[1635:1635] = sram_blwl_bl[1635:1635] ; -assign sram_blwl_1635_configbus1[1635:1635] = sram_blwl_wl[1635:1635] ; -assign sram_blwl_1635_configbus0_b[1635:1635] = sram_blwl_blb[1635:1635] ; -sram6T_blwl sram_blwl_1635_ (sram_blwl_out[1635], sram_blwl_out[1635], sram_blwl_outb[1635], sram_blwl_1635_configbus0[1635:1635], sram_blwl_1635_configbus1[1635:1635] , sram_blwl_1635_configbus0_b[1635:1635] ); -wire [1636:1636] sram_blwl_1636_configbus0; -wire [1636:1636] sram_blwl_1636_configbus1; -wire [1636:1636] sram_blwl_1636_configbus0_b; -assign sram_blwl_1636_configbus0[1636:1636] = sram_blwl_bl[1636:1636] ; -assign sram_blwl_1636_configbus1[1636:1636] = sram_blwl_wl[1636:1636] ; -assign sram_blwl_1636_configbus0_b[1636:1636] = sram_blwl_blb[1636:1636] ; -sram6T_blwl sram_blwl_1636_ (sram_blwl_out[1636], sram_blwl_out[1636], sram_blwl_outb[1636], sram_blwl_1636_configbus0[1636:1636], sram_blwl_1636_configbus1[1636:1636] , sram_blwl_1636_configbus0_b[1636:1636] ); -wire [1637:1637] sram_blwl_1637_configbus0; -wire [1637:1637] sram_blwl_1637_configbus1; -wire [1637:1637] sram_blwl_1637_configbus0_b; -assign sram_blwl_1637_configbus0[1637:1637] = sram_blwl_bl[1637:1637] ; -assign sram_blwl_1637_configbus1[1637:1637] = sram_blwl_wl[1637:1637] ; -assign sram_blwl_1637_configbus0_b[1637:1637] = sram_blwl_blb[1637:1637] ; -sram6T_blwl sram_blwl_1637_ (sram_blwl_out[1637], sram_blwl_out[1637], sram_blwl_outb[1637], sram_blwl_1637_configbus0[1637:1637], sram_blwl_1637_configbus1[1637:1637] , sram_blwl_1637_configbus0_b[1637:1637] ); -wire [1638:1638] sram_blwl_1638_configbus0; -wire [1638:1638] sram_blwl_1638_configbus1; -wire [1638:1638] sram_blwl_1638_configbus0_b; -assign sram_blwl_1638_configbus0[1638:1638] = sram_blwl_bl[1638:1638] ; -assign sram_blwl_1638_configbus1[1638:1638] = sram_blwl_wl[1638:1638] ; -assign sram_blwl_1638_configbus0_b[1638:1638] = sram_blwl_blb[1638:1638] ; -sram6T_blwl sram_blwl_1638_ (sram_blwl_out[1638], sram_blwl_out[1638], sram_blwl_outb[1638], sram_blwl_1638_configbus0[1638:1638], sram_blwl_1638_configbus1[1638:1638] , sram_blwl_1638_configbus0_b[1638:1638] ); -wire [1639:1639] sram_blwl_1639_configbus0; -wire [1639:1639] sram_blwl_1639_configbus1; -wire [1639:1639] sram_blwl_1639_configbus0_b; -assign sram_blwl_1639_configbus0[1639:1639] = sram_blwl_bl[1639:1639] ; -assign sram_blwl_1639_configbus1[1639:1639] = sram_blwl_wl[1639:1639] ; -assign sram_blwl_1639_configbus0_b[1639:1639] = sram_blwl_blb[1639:1639] ; -sram6T_blwl sram_blwl_1639_ (sram_blwl_out[1639], sram_blwl_out[1639], sram_blwl_outb[1639], sram_blwl_1639_configbus0[1639:1639], sram_blwl_1639_configbus1[1639:1639] , sram_blwl_1639_configbus0_b[1639:1639] ); -wire [1640:1640] sram_blwl_1640_configbus0; -wire [1640:1640] sram_blwl_1640_configbus1; -wire [1640:1640] sram_blwl_1640_configbus0_b; -assign sram_blwl_1640_configbus0[1640:1640] = sram_blwl_bl[1640:1640] ; -assign sram_blwl_1640_configbus1[1640:1640] = sram_blwl_wl[1640:1640] ; -assign sram_blwl_1640_configbus0_b[1640:1640] = sram_blwl_blb[1640:1640] ; -sram6T_blwl sram_blwl_1640_ (sram_blwl_out[1640], sram_blwl_out[1640], sram_blwl_outb[1640], sram_blwl_1640_configbus0[1640:1640], sram_blwl_1640_configbus1[1640:1640] , sram_blwl_1640_configbus0_b[1640:1640] ); -wire [1641:1641] sram_blwl_1641_configbus0; -wire [1641:1641] sram_blwl_1641_configbus1; -wire [1641:1641] sram_blwl_1641_configbus0_b; -assign sram_blwl_1641_configbus0[1641:1641] = sram_blwl_bl[1641:1641] ; -assign sram_blwl_1641_configbus1[1641:1641] = sram_blwl_wl[1641:1641] ; -assign sram_blwl_1641_configbus0_b[1641:1641] = sram_blwl_blb[1641:1641] ; -sram6T_blwl sram_blwl_1641_ (sram_blwl_out[1641], sram_blwl_out[1641], sram_blwl_outb[1641], sram_blwl_1641_configbus0[1641:1641], sram_blwl_1641_configbus1[1641:1641] , sram_blwl_1641_configbus0_b[1641:1641] ); -wire [1642:1642] sram_blwl_1642_configbus0; -wire [1642:1642] sram_blwl_1642_configbus1; -wire [1642:1642] sram_blwl_1642_configbus0_b; -assign sram_blwl_1642_configbus0[1642:1642] = sram_blwl_bl[1642:1642] ; -assign sram_blwl_1642_configbus1[1642:1642] = sram_blwl_wl[1642:1642] ; -assign sram_blwl_1642_configbus0_b[1642:1642] = sram_blwl_blb[1642:1642] ; -sram6T_blwl sram_blwl_1642_ (sram_blwl_out[1642], sram_blwl_out[1642], sram_blwl_outb[1642], sram_blwl_1642_configbus0[1642:1642], sram_blwl_1642_configbus1[1642:1642] , sram_blwl_1642_configbus0_b[1642:1642] ); -wire [1643:1643] sram_blwl_1643_configbus0; -wire [1643:1643] sram_blwl_1643_configbus1; -wire [1643:1643] sram_blwl_1643_configbus0_b; -assign sram_blwl_1643_configbus0[1643:1643] = sram_blwl_bl[1643:1643] ; -assign sram_blwl_1643_configbus1[1643:1643] = sram_blwl_wl[1643:1643] ; -assign sram_blwl_1643_configbus0_b[1643:1643] = sram_blwl_blb[1643:1643] ; -sram6T_blwl sram_blwl_1643_ (sram_blwl_out[1643], sram_blwl_out[1643], sram_blwl_outb[1643], sram_blwl_1643_configbus0[1643:1643], sram_blwl_1643_configbus1[1643:1643] , sram_blwl_1643_configbus0_b[1643:1643] ); -wire [1644:1644] sram_blwl_1644_configbus0; -wire [1644:1644] sram_blwl_1644_configbus1; -wire [1644:1644] sram_blwl_1644_configbus0_b; -assign sram_blwl_1644_configbus0[1644:1644] = sram_blwl_bl[1644:1644] ; -assign sram_blwl_1644_configbus1[1644:1644] = sram_blwl_wl[1644:1644] ; -assign sram_blwl_1644_configbus0_b[1644:1644] = sram_blwl_blb[1644:1644] ; -sram6T_blwl sram_blwl_1644_ (sram_blwl_out[1644], sram_blwl_out[1644], sram_blwl_outb[1644], sram_blwl_1644_configbus0[1644:1644], sram_blwl_1644_configbus1[1644:1644] , sram_blwl_1644_configbus0_b[1644:1644] ); -wire [1645:1645] sram_blwl_1645_configbus0; -wire [1645:1645] sram_blwl_1645_configbus1; -wire [1645:1645] sram_blwl_1645_configbus0_b; -assign sram_blwl_1645_configbus0[1645:1645] = sram_blwl_bl[1645:1645] ; -assign sram_blwl_1645_configbus1[1645:1645] = sram_blwl_wl[1645:1645] ; -assign sram_blwl_1645_configbus0_b[1645:1645] = sram_blwl_blb[1645:1645] ; -sram6T_blwl sram_blwl_1645_ (sram_blwl_out[1645], sram_blwl_out[1645], sram_blwl_outb[1645], sram_blwl_1645_configbus0[1645:1645], sram_blwl_1645_configbus1[1645:1645] , sram_blwl_1645_configbus0_b[1645:1645] ); -wire [1646:1646] sram_blwl_1646_configbus0; -wire [1646:1646] sram_blwl_1646_configbus1; -wire [1646:1646] sram_blwl_1646_configbus0_b; -assign sram_blwl_1646_configbus0[1646:1646] = sram_blwl_bl[1646:1646] ; -assign sram_blwl_1646_configbus1[1646:1646] = sram_blwl_wl[1646:1646] ; -assign sram_blwl_1646_configbus0_b[1646:1646] = sram_blwl_blb[1646:1646] ; -sram6T_blwl sram_blwl_1646_ (sram_blwl_out[1646], sram_blwl_out[1646], sram_blwl_outb[1646], sram_blwl_1646_configbus0[1646:1646], sram_blwl_1646_configbus1[1646:1646] , sram_blwl_1646_configbus0_b[1646:1646] ); -wire [1647:1647] sram_blwl_1647_configbus0; -wire [1647:1647] sram_blwl_1647_configbus1; -wire [1647:1647] sram_blwl_1647_configbus0_b; -assign sram_blwl_1647_configbus0[1647:1647] = sram_blwl_bl[1647:1647] ; -assign sram_blwl_1647_configbus1[1647:1647] = sram_blwl_wl[1647:1647] ; -assign sram_blwl_1647_configbus0_b[1647:1647] = sram_blwl_blb[1647:1647] ; -sram6T_blwl sram_blwl_1647_ (sram_blwl_out[1647], sram_blwl_out[1647], sram_blwl_outb[1647], sram_blwl_1647_configbus0[1647:1647], sram_blwl_1647_configbus1[1647:1647] , sram_blwl_1647_configbus0_b[1647:1647] ); -wire [1648:1648] sram_blwl_1648_configbus0; -wire [1648:1648] sram_blwl_1648_configbus1; -wire [1648:1648] sram_blwl_1648_configbus0_b; -assign sram_blwl_1648_configbus0[1648:1648] = sram_blwl_bl[1648:1648] ; -assign sram_blwl_1648_configbus1[1648:1648] = sram_blwl_wl[1648:1648] ; -assign sram_blwl_1648_configbus0_b[1648:1648] = sram_blwl_blb[1648:1648] ; -sram6T_blwl sram_blwl_1648_ (sram_blwl_out[1648], sram_blwl_out[1648], sram_blwl_outb[1648], sram_blwl_1648_configbus0[1648:1648], sram_blwl_1648_configbus1[1648:1648] , sram_blwl_1648_configbus0_b[1648:1648] ); -wire [1649:1649] sram_blwl_1649_configbus0; -wire [1649:1649] sram_blwl_1649_configbus1; -wire [1649:1649] sram_blwl_1649_configbus0_b; -assign sram_blwl_1649_configbus0[1649:1649] = sram_blwl_bl[1649:1649] ; -assign sram_blwl_1649_configbus1[1649:1649] = sram_blwl_wl[1649:1649] ; -assign sram_blwl_1649_configbus0_b[1649:1649] = sram_blwl_blb[1649:1649] ; -sram6T_blwl sram_blwl_1649_ (sram_blwl_out[1649], sram_blwl_out[1649], sram_blwl_outb[1649], sram_blwl_1649_configbus0[1649:1649], sram_blwl_1649_configbus1[1649:1649] , sram_blwl_1649_configbus0_b[1649:1649] ); -wire [1650:1650] sram_blwl_1650_configbus0; -wire [1650:1650] sram_blwl_1650_configbus1; -wire [1650:1650] sram_blwl_1650_configbus0_b; -assign sram_blwl_1650_configbus0[1650:1650] = sram_blwl_bl[1650:1650] ; -assign sram_blwl_1650_configbus1[1650:1650] = sram_blwl_wl[1650:1650] ; -assign sram_blwl_1650_configbus0_b[1650:1650] = sram_blwl_blb[1650:1650] ; -sram6T_blwl sram_blwl_1650_ (sram_blwl_out[1650], sram_blwl_out[1650], sram_blwl_outb[1650], sram_blwl_1650_configbus0[1650:1650], sram_blwl_1650_configbus1[1650:1650] , sram_blwl_1650_configbus0_b[1650:1650] ); -wire [1651:1651] sram_blwl_1651_configbus0; -wire [1651:1651] sram_blwl_1651_configbus1; -wire [1651:1651] sram_blwl_1651_configbus0_b; -assign sram_blwl_1651_configbus0[1651:1651] = sram_blwl_bl[1651:1651] ; -assign sram_blwl_1651_configbus1[1651:1651] = sram_blwl_wl[1651:1651] ; -assign sram_blwl_1651_configbus0_b[1651:1651] = sram_blwl_blb[1651:1651] ; -sram6T_blwl sram_blwl_1651_ (sram_blwl_out[1651], sram_blwl_out[1651], sram_blwl_outb[1651], sram_blwl_1651_configbus0[1651:1651], sram_blwl_1651_configbus1[1651:1651] , sram_blwl_1651_configbus0_b[1651:1651] ); -wire [1652:1652] sram_blwl_1652_configbus0; -wire [1652:1652] sram_blwl_1652_configbus1; -wire [1652:1652] sram_blwl_1652_configbus0_b; -assign sram_blwl_1652_configbus0[1652:1652] = sram_blwl_bl[1652:1652] ; -assign sram_blwl_1652_configbus1[1652:1652] = sram_blwl_wl[1652:1652] ; -assign sram_blwl_1652_configbus0_b[1652:1652] = sram_blwl_blb[1652:1652] ; -sram6T_blwl sram_blwl_1652_ (sram_blwl_out[1652], sram_blwl_out[1652], sram_blwl_outb[1652], sram_blwl_1652_configbus0[1652:1652], sram_blwl_1652_configbus1[1652:1652] , sram_blwl_1652_configbus0_b[1652:1652] ); -wire [1653:1653] sram_blwl_1653_configbus0; -wire [1653:1653] sram_blwl_1653_configbus1; -wire [1653:1653] sram_blwl_1653_configbus0_b; -assign sram_blwl_1653_configbus0[1653:1653] = sram_blwl_bl[1653:1653] ; -assign sram_blwl_1653_configbus1[1653:1653] = sram_blwl_wl[1653:1653] ; -assign sram_blwl_1653_configbus0_b[1653:1653] = sram_blwl_blb[1653:1653] ; -sram6T_blwl sram_blwl_1653_ (sram_blwl_out[1653], sram_blwl_out[1653], sram_blwl_outb[1653], sram_blwl_1653_configbus0[1653:1653], sram_blwl_1653_configbus1[1653:1653] , sram_blwl_1653_configbus0_b[1653:1653] ); -wire [1654:1654] sram_blwl_1654_configbus0; -wire [1654:1654] sram_blwl_1654_configbus1; -wire [1654:1654] sram_blwl_1654_configbus0_b; -assign sram_blwl_1654_configbus0[1654:1654] = sram_blwl_bl[1654:1654] ; -assign sram_blwl_1654_configbus1[1654:1654] = sram_blwl_wl[1654:1654] ; -assign sram_blwl_1654_configbus0_b[1654:1654] = sram_blwl_blb[1654:1654] ; -sram6T_blwl sram_blwl_1654_ (sram_blwl_out[1654], sram_blwl_out[1654], sram_blwl_outb[1654], sram_blwl_1654_configbus0[1654:1654], sram_blwl_1654_configbus1[1654:1654] , sram_blwl_1654_configbus0_b[1654:1654] ); -wire [1655:1655] sram_blwl_1655_configbus0; -wire [1655:1655] sram_blwl_1655_configbus1; -wire [1655:1655] sram_blwl_1655_configbus0_b; -assign sram_blwl_1655_configbus0[1655:1655] = sram_blwl_bl[1655:1655] ; -assign sram_blwl_1655_configbus1[1655:1655] = sram_blwl_wl[1655:1655] ; -assign sram_blwl_1655_configbus0_b[1655:1655] = sram_blwl_blb[1655:1655] ; -sram6T_blwl sram_blwl_1655_ (sram_blwl_out[1655], sram_blwl_out[1655], sram_blwl_outb[1655], sram_blwl_1655_configbus0[1655:1655], sram_blwl_1655_configbus1[1655:1655] , sram_blwl_1655_configbus0_b[1655:1655] ); -wire [1656:1656] sram_blwl_1656_configbus0; -wire [1656:1656] sram_blwl_1656_configbus1; -wire [1656:1656] sram_blwl_1656_configbus0_b; -assign sram_blwl_1656_configbus0[1656:1656] = sram_blwl_bl[1656:1656] ; -assign sram_blwl_1656_configbus1[1656:1656] = sram_blwl_wl[1656:1656] ; -assign sram_blwl_1656_configbus0_b[1656:1656] = sram_blwl_blb[1656:1656] ; -sram6T_blwl sram_blwl_1656_ (sram_blwl_out[1656], sram_blwl_out[1656], sram_blwl_outb[1656], sram_blwl_1656_configbus0[1656:1656], sram_blwl_1656_configbus1[1656:1656] , sram_blwl_1656_configbus0_b[1656:1656] ); -wire [1657:1657] sram_blwl_1657_configbus0; -wire [1657:1657] sram_blwl_1657_configbus1; -wire [1657:1657] sram_blwl_1657_configbus0_b; -assign sram_blwl_1657_configbus0[1657:1657] = sram_blwl_bl[1657:1657] ; -assign sram_blwl_1657_configbus1[1657:1657] = sram_blwl_wl[1657:1657] ; -assign sram_blwl_1657_configbus0_b[1657:1657] = sram_blwl_blb[1657:1657] ; -sram6T_blwl sram_blwl_1657_ (sram_blwl_out[1657], sram_blwl_out[1657], sram_blwl_outb[1657], sram_blwl_1657_configbus0[1657:1657], sram_blwl_1657_configbus1[1657:1657] , sram_blwl_1657_configbus0_b[1657:1657] ); -wire [1658:1658] sram_blwl_1658_configbus0; -wire [1658:1658] sram_blwl_1658_configbus1; -wire [1658:1658] sram_blwl_1658_configbus0_b; -assign sram_blwl_1658_configbus0[1658:1658] = sram_blwl_bl[1658:1658] ; -assign sram_blwl_1658_configbus1[1658:1658] = sram_blwl_wl[1658:1658] ; -assign sram_blwl_1658_configbus0_b[1658:1658] = sram_blwl_blb[1658:1658] ; -sram6T_blwl sram_blwl_1658_ (sram_blwl_out[1658], sram_blwl_out[1658], sram_blwl_outb[1658], sram_blwl_1658_configbus0[1658:1658], sram_blwl_1658_configbus1[1658:1658] , sram_blwl_1658_configbus0_b[1658:1658] ); -wire [1659:1659] sram_blwl_1659_configbus0; -wire [1659:1659] sram_blwl_1659_configbus1; -wire [1659:1659] sram_blwl_1659_configbus0_b; -assign sram_blwl_1659_configbus0[1659:1659] = sram_blwl_bl[1659:1659] ; -assign sram_blwl_1659_configbus1[1659:1659] = sram_blwl_wl[1659:1659] ; -assign sram_blwl_1659_configbus0_b[1659:1659] = sram_blwl_blb[1659:1659] ; -sram6T_blwl sram_blwl_1659_ (sram_blwl_out[1659], sram_blwl_out[1659], sram_blwl_outb[1659], sram_blwl_1659_configbus0[1659:1659], sram_blwl_1659_configbus1[1659:1659] , sram_blwl_1659_configbus0_b[1659:1659] ); -wire [1660:1660] sram_blwl_1660_configbus0; -wire [1660:1660] sram_blwl_1660_configbus1; -wire [1660:1660] sram_blwl_1660_configbus0_b; -assign sram_blwl_1660_configbus0[1660:1660] = sram_blwl_bl[1660:1660] ; -assign sram_blwl_1660_configbus1[1660:1660] = sram_blwl_wl[1660:1660] ; -assign sram_blwl_1660_configbus0_b[1660:1660] = sram_blwl_blb[1660:1660] ; -sram6T_blwl sram_blwl_1660_ (sram_blwl_out[1660], sram_blwl_out[1660], sram_blwl_outb[1660], sram_blwl_1660_configbus0[1660:1660], sram_blwl_1660_configbus1[1660:1660] , sram_blwl_1660_configbus0_b[1660:1660] ); -wire [1661:1661] sram_blwl_1661_configbus0; -wire [1661:1661] sram_blwl_1661_configbus1; -wire [1661:1661] sram_blwl_1661_configbus0_b; -assign sram_blwl_1661_configbus0[1661:1661] = sram_blwl_bl[1661:1661] ; -assign sram_blwl_1661_configbus1[1661:1661] = sram_blwl_wl[1661:1661] ; -assign sram_blwl_1661_configbus0_b[1661:1661] = sram_blwl_blb[1661:1661] ; -sram6T_blwl sram_blwl_1661_ (sram_blwl_out[1661], sram_blwl_out[1661], sram_blwl_outb[1661], sram_blwl_1661_configbus0[1661:1661], sram_blwl_1661_configbus1[1661:1661] , sram_blwl_1661_configbus0_b[1661:1661] ); -wire [1662:1662] sram_blwl_1662_configbus0; -wire [1662:1662] sram_blwl_1662_configbus1; -wire [1662:1662] sram_blwl_1662_configbus0_b; -assign sram_blwl_1662_configbus0[1662:1662] = sram_blwl_bl[1662:1662] ; -assign sram_blwl_1662_configbus1[1662:1662] = sram_blwl_wl[1662:1662] ; -assign sram_blwl_1662_configbus0_b[1662:1662] = sram_blwl_blb[1662:1662] ; -sram6T_blwl sram_blwl_1662_ (sram_blwl_out[1662], sram_blwl_out[1662], sram_blwl_outb[1662], sram_blwl_1662_configbus0[1662:1662], sram_blwl_1662_configbus1[1662:1662] , sram_blwl_1662_configbus0_b[1662:1662] ); -wire [1663:1663] sram_blwl_1663_configbus0; -wire [1663:1663] sram_blwl_1663_configbus1; -wire [1663:1663] sram_blwl_1663_configbus0_b; -assign sram_blwl_1663_configbus0[1663:1663] = sram_blwl_bl[1663:1663] ; -assign sram_blwl_1663_configbus1[1663:1663] = sram_blwl_wl[1663:1663] ; -assign sram_blwl_1663_configbus0_b[1663:1663] = sram_blwl_blb[1663:1663] ; -sram6T_blwl sram_blwl_1663_ (sram_blwl_out[1663], sram_blwl_out[1663], sram_blwl_outb[1663], sram_blwl_1663_configbus0[1663:1663], sram_blwl_1663_configbus1[1663:1663] , sram_blwl_1663_configbus0_b[1663:1663] ); -wire [1664:1664] sram_blwl_1664_configbus0; -wire [1664:1664] sram_blwl_1664_configbus1; -wire [1664:1664] sram_blwl_1664_configbus0_b; -assign sram_blwl_1664_configbus0[1664:1664] = sram_blwl_bl[1664:1664] ; -assign sram_blwl_1664_configbus1[1664:1664] = sram_blwl_wl[1664:1664] ; -assign sram_blwl_1664_configbus0_b[1664:1664] = sram_blwl_blb[1664:1664] ; -sram6T_blwl sram_blwl_1664_ (sram_blwl_out[1664], sram_blwl_out[1664], sram_blwl_outb[1664], sram_blwl_1664_configbus0[1664:1664], sram_blwl_1664_configbus1[1664:1664] , sram_blwl_1664_configbus0_b[1664:1664] ); -endmodule -//----- END LUT Verilog module: grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ ----- - -//----- Flip-flop Verilog module: Q0 ----- -//----- Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- -module grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -input [0:0] Set, -input [0:0] Reset, -input [0:0] clk -//----- END Global ports of SPICE_MODEL(static_dff)----- -, -input wire ff_0___D_0_, -output wire ff_0___Q_0_); -static_dff dff_9_ (//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -endmodule -//----- END Flip-flop Verilog module: grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ----- - -//----- Programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6_ ----- -module grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_ble6___in_0_, -input wire mode_ble6___in_1_, -input wire mode_ble6___in_2_, -input wire mode_ble6___in_3_, -input wire mode_ble6___in_4_, -input wire mode_ble6___in_5_, -output wire mode_ble6___out_0_, -input wire mode_ble6___clk_0_, -input [1601:1665] sram_blwl_bl , -input [1601:1665] sram_blwl_wl , -input [1601:1665] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6__lut6_0_ lut6_0_ ( - lut6_0___in_0_, lut6_0___in_1_, lut6_0___in_2_, lut6_0___in_3_, lut6_0___in_4_, lut6_0___in_5_, lut6_0___out_0_, -sram_blwl_bl[1601:1664] , -sram_blwl_wl[1601:1664] , -sram_blwl_blb[1601:1664] ); -grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6__ff_0_ ff_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(static_dff) ----- -Set[0:0], -Reset[0:0], -clk[0:0] -//----- END Global ports of SPICE_MODEL(static_dff)----- -, - ff_0___D_0_, ff_0___Q_0_); -wire [0:1] in_bus_mux_1level_tapbuf_size2_409_ ; -assign in_bus_mux_1level_tapbuf_size2_409_[0] = ff_0___Q_0_ ; -assign in_bus_mux_1level_tapbuf_size2_409_[1] = lut6_0___out_0_ ; -wire [1665:1665] mux_1level_tapbuf_size2_409_configbus0; -wire [1665:1665] mux_1level_tapbuf_size2_409_configbus1; -wire [1665:1665] mux_1level_tapbuf_size2_409_sram_blwl_out ; -wire [1665:1665] mux_1level_tapbuf_size2_409_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_409_configbus0[1665:1665] = sram_blwl_bl[1665:1665] ; -assign mux_1level_tapbuf_size2_409_configbus1[1665:1665] = sram_blwl_wl[1665:1665] ; -wire [1665:1665] mux_1level_tapbuf_size2_409_configbus0_b; -assign mux_1level_tapbuf_size2_409_configbus0_b[1665:1665] = sram_blwl_blb[1665:1665] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_409_ (in_bus_mux_1level_tapbuf_size2_409_, mode_ble6___out_0_, mux_1level_tapbuf_size2_409_sram_blwl_out[1665:1665] , -mux_1level_tapbuf_size2_409_sram_blwl_outb[1665:1665] ); -//----- SRAM bits for MUX[409], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1665_ (mux_1level_tapbuf_size2_409_sram_blwl_out[1665:1665] ,mux_1level_tapbuf_size2_409_sram_blwl_out[1665:1665] ,mux_1level_tapbuf_size2_409_sram_blwl_outb[1665:1665] ,mux_1level_tapbuf_size2_409_configbus0[1665:1665], mux_1level_tapbuf_size2_409_configbus1[1665:1665] , mux_1level_tapbuf_size2_409_configbus0_b[1665:1665] ); -direct_interc direct_interc_144_ (mode_ble6___in_0_, lut6_0___in_0_ ); -direct_interc direct_interc_145_ (mode_ble6___in_1_, lut6_0___in_1_ ); -direct_interc direct_interc_146_ (mode_ble6___in_2_, lut6_0___in_2_ ); -direct_interc direct_interc_147_ (mode_ble6___in_3_, lut6_0___in_3_ ); -direct_interc direct_interc_148_ (mode_ble6___in_4_, lut6_0___in_4_ ); -direct_interc direct_interc_149_ (mode_ble6___in_5_, lut6_0___in_5_ ); -direct_interc direct_interc_150_ (lut6_0___out_0_, ff_0___D_0_ ); -direct_interc direct_interc_151_ (mode_ble6___clk_0_, ff_0___clk_0_ ); -endmodule -//----- END Programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6_ ----- - -//----- Programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6_ ----- -module grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_n1_lut6___in_0_, -input wire mode_n1_lut6___in_1_, -input wire mode_n1_lut6___in_2_, -input wire mode_n1_lut6___in_3_, -input wire mode_n1_lut6___in_4_, -input wire mode_n1_lut6___in_5_, -output wire mode_n1_lut6___out_0_, -input wire mode_n1_lut6___clk_0_, -input [1601:1665] sram_blwl_bl , -input [1601:1665] sram_blwl_wl , -input [1601:1665] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6__ble6_0__mode_ble6_ ble6_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - ble6_0___in_0_, ble6_0___in_1_, ble6_0___in_2_, ble6_0___in_3_, ble6_0___in_4_, ble6_0___in_5_, ble6_0___out_0_, ble6_0___clk_0_, -sram_blwl_bl[1601:1665] , -sram_blwl_wl[1601:1665] , -sram_blwl_blb[1601:1665] ); -direct_interc direct_interc_152_ (ble6_0___out_0_, mode_n1_lut6___out_0_ ); -direct_interc direct_interc_153_ (mode_n1_lut6___in_0_, ble6_0___in_0_ ); -direct_interc direct_interc_154_ (mode_n1_lut6___in_1_, ble6_0___in_1_ ); -direct_interc direct_interc_155_ (mode_n1_lut6___in_2_, ble6_0___in_2_ ); -direct_interc direct_interc_156_ (mode_n1_lut6___in_3_, ble6_0___in_3_ ); -direct_interc direct_interc_157_ (mode_n1_lut6___in_4_, ble6_0___in_4_ ); -direct_interc direct_interc_158_ (mode_n1_lut6___in_5_, ble6_0___in_5_ ); -direct_interc direct_interc_159_ (mode_n1_lut6___clk_0_, ble6_0___clk_0_ ); -endmodule -//----- END Programmable logic block Verilog module grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6_ ----- - -//----- Programmable logic block Verilog module grid_1__1__clb_0__mode_clb_ ----- -module grid_1__1__clb_0__mode_clb_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_clb___I_0_, -input wire mode_clb___I_1_, -input wire mode_clb___I_2_, -input wire mode_clb___I_3_, -input wire mode_clb___I_4_, -input wire mode_clb___I_5_, -input wire mode_clb___I_6_, -input wire mode_clb___I_7_, -input wire mode_clb___I_8_, -input wire mode_clb___I_9_, -input wire mode_clb___I_10_, -input wire mode_clb___I_11_, -input wire mode_clb___I_12_, -input wire mode_clb___I_13_, -input wire mode_clb___I_14_, -input wire mode_clb___I_15_, -input wire mode_clb___I_16_, -input wire mode_clb___I_17_, -input wire mode_clb___I_18_, -input wire mode_clb___I_19_, -input wire mode_clb___I_20_, -input wire mode_clb___I_21_, -input wire mode_clb___I_22_, -input wire mode_clb___I_23_, -input wire mode_clb___I_24_, -input wire mode_clb___I_25_, -input wire mode_clb___I_26_, -input wire mode_clb___I_27_, -input wire mode_clb___I_28_, -input wire mode_clb___I_29_, -input wire mode_clb___I_30_, -input wire mode_clb___I_31_, -input wire mode_clb___I_32_, -input wire mode_clb___I_33_, -input wire mode_clb___I_34_, -input wire mode_clb___I_35_, -input wire mode_clb___I_36_, -input wire mode_clb___I_37_, -input wire mode_clb___I_38_, -input wire mode_clb___I_39_, -output wire mode_clb___O_0_, -output wire mode_clb___O_1_, -output wire mode_clb___O_2_, -output wire mode_clb___O_3_, -output wire mode_clb___O_4_, -output wire mode_clb___O_5_, -output wire mode_clb___O_6_, -output wire mode_clb___O_7_, -output wire mode_clb___O_8_, -output wire mode_clb___O_9_, -input wire mode_clb___clk_0_, -input [1016:2625] sram_blwl_bl , -input [1016:2625] sram_blwl_wl , -input [1016:2625] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb__fle_0__mode_n1_lut6_ fle_0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_0___in_0_, fle_0___in_1_, fle_0___in_2_, fle_0___in_3_, fle_0___in_4_, fle_0___in_5_, fle_0___out_0_, fle_0___clk_0_, -sram_blwl_bl[1016:1080] , -sram_blwl_wl[1016:1080] , -sram_blwl_blb[1016:1080] ); -grid_1__1__clb_0__mode_clb__fle_1__mode_n1_lut6_ fle_1_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_1___in_0_, fle_1___in_1_, fle_1___in_2_, fle_1___in_3_, fle_1___in_4_, fle_1___in_5_, fle_1___out_0_, fle_1___clk_0_, -sram_blwl_bl[1081:1145] , -sram_blwl_wl[1081:1145] , -sram_blwl_blb[1081:1145] ); -grid_1__1__clb_0__mode_clb__fle_2__mode_n1_lut6_ fle_2_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_2___in_0_, fle_2___in_1_, fle_2___in_2_, fle_2___in_3_, fle_2___in_4_, fle_2___in_5_, fle_2___out_0_, fle_2___clk_0_, -sram_blwl_bl[1146:1210] , -sram_blwl_wl[1146:1210] , -sram_blwl_blb[1146:1210] ); -grid_1__1__clb_0__mode_clb__fle_3__mode_n1_lut6_ fle_3_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_3___in_0_, fle_3___in_1_, fle_3___in_2_, fle_3___in_3_, fle_3___in_4_, fle_3___in_5_, fle_3___out_0_, fle_3___clk_0_, -sram_blwl_bl[1211:1275] , -sram_blwl_wl[1211:1275] , -sram_blwl_blb[1211:1275] ); -grid_1__1__clb_0__mode_clb__fle_4__mode_n1_lut6_ fle_4_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_4___in_0_, fle_4___in_1_, fle_4___in_2_, fle_4___in_3_, fle_4___in_4_, fle_4___in_5_, fle_4___out_0_, fle_4___clk_0_, -sram_blwl_bl[1276:1340] , -sram_blwl_wl[1276:1340] , -sram_blwl_blb[1276:1340] ); -grid_1__1__clb_0__mode_clb__fle_5__mode_n1_lut6_ fle_5_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_5___in_0_, fle_5___in_1_, fle_5___in_2_, fle_5___in_3_, fle_5___in_4_, fle_5___in_5_, fle_5___out_0_, fle_5___clk_0_, -sram_blwl_bl[1341:1405] , -sram_blwl_wl[1341:1405] , -sram_blwl_blb[1341:1405] ); -grid_1__1__clb_0__mode_clb__fle_6__mode_n1_lut6_ fle_6_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_6___in_0_, fle_6___in_1_, fle_6___in_2_, fle_6___in_3_, fle_6___in_4_, fle_6___in_5_, fle_6___out_0_, fle_6___clk_0_, -sram_blwl_bl[1406:1470] , -sram_blwl_wl[1406:1470] , -sram_blwl_blb[1406:1470] ); -grid_1__1__clb_0__mode_clb__fle_7__mode_n1_lut6_ fle_7_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_7___in_0_, fle_7___in_1_, fle_7___in_2_, fle_7___in_3_, fle_7___in_4_, fle_7___in_5_, fle_7___out_0_, fle_7___clk_0_, -sram_blwl_bl[1471:1535] , -sram_blwl_wl[1471:1535] , -sram_blwl_blb[1471:1535] ); -grid_1__1__clb_0__mode_clb__fle_8__mode_n1_lut6_ fle_8_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_8___in_0_, fle_8___in_1_, fle_8___in_2_, fle_8___in_3_, fle_8___in_4_, fle_8___in_5_, fle_8___out_0_, fle_8___clk_0_, -sram_blwl_bl[1536:1600] , -sram_blwl_wl[1536:1600] , -sram_blwl_blb[1536:1600] ); -grid_1__1__clb_0__mode_clb__fle_9__mode_n1_lut6_ fle_9_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, - fle_9___in_0_, fle_9___in_1_, fle_9___in_2_, fle_9___in_3_, fle_9___in_4_, fle_9___in_5_, fle_9___out_0_, fle_9___clk_0_, -sram_blwl_bl[1601:1665] , -sram_blwl_wl[1601:1665] , -sram_blwl_blb[1601:1665] ); -direct_interc direct_interc_160_ (fle_0___out_0_, mode_clb___O_0_ ); -direct_interc direct_interc_161_ (fle_1___out_0_, mode_clb___O_1_ ); -direct_interc direct_interc_162_ (fle_2___out_0_, mode_clb___O_2_ ); -direct_interc direct_interc_163_ (fle_3___out_0_, mode_clb___O_3_ ); -direct_interc direct_interc_164_ (fle_4___out_0_, mode_clb___O_4_ ); -direct_interc direct_interc_165_ (fle_5___out_0_, mode_clb___O_5_ ); -direct_interc direct_interc_166_ (fle_6___out_0_, mode_clb___O_6_ ); -direct_interc direct_interc_167_ (fle_7___out_0_, mode_clb___O_7_ ); -direct_interc direct_interc_168_ (fle_8___out_0_, mode_clb___O_8_ ); -direct_interc direct_interc_169_ (fle_9___out_0_, mode_clb___O_9_ ); -wire [0:49] in_bus_mux_2level_size50_0_ ; -assign in_bus_mux_2level_size50_0_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_0_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_0_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_0_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_0_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_0_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_0_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_0_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_0_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_0_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_0_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_0_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_0_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_0_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_0_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_0_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_0_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_0_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_0_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_0_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_0_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_0_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_0_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_0_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_0_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_0_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_0_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_0_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_0_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_0_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_0_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_0_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_0_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_0_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_0_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_0_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_0_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_0_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_0_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_0_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_0_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_0_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_0_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_0_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_0_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_0_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_0_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_0_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_0_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_0_[49] = fle_9___out_0_ ; -wire [1666:1681] mux_2level_size50_0_configbus0; -wire [1666:1681] mux_2level_size50_0_configbus1; -wire [1666:1681] mux_2level_size50_0_sram_blwl_out ; -wire [1666:1681] mux_2level_size50_0_sram_blwl_outb ; -assign mux_2level_size50_0_configbus0[1666:1681] = sram_blwl_bl[1666:1681] ; -assign mux_2level_size50_0_configbus1[1666:1681] = sram_blwl_wl[1666:1681] ; -wire [1666:1681] mux_2level_size50_0_configbus0_b; -assign mux_2level_size50_0_configbus0_b[1666:1681] = sram_blwl_blb[1666:1681] ; -mux_2level_size50 mux_2level_size50_0_ (in_bus_mux_2level_size50_0_, fle_0___in_0_, mux_2level_size50_0_sram_blwl_out[1666:1681] , -mux_2level_size50_0_sram_blwl_outb[1666:1681] ); -//----- SRAM bits for MUX[0], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1666_ (mux_2level_size50_0_sram_blwl_out[1666:1666] ,mux_2level_size50_0_sram_blwl_out[1666:1666] ,mux_2level_size50_0_sram_blwl_outb[1666:1666] ,mux_2level_size50_0_configbus0[1666:1666], mux_2level_size50_0_configbus1[1666:1666] , mux_2level_size50_0_configbus0_b[1666:1666] ); -sram6T_blwl sram_blwl_1667_ (mux_2level_size50_0_sram_blwl_out[1667:1667] ,mux_2level_size50_0_sram_blwl_out[1667:1667] ,mux_2level_size50_0_sram_blwl_outb[1667:1667] ,mux_2level_size50_0_configbus0[1667:1667], mux_2level_size50_0_configbus1[1667:1667] , mux_2level_size50_0_configbus0_b[1667:1667] ); -sram6T_blwl sram_blwl_1668_ (mux_2level_size50_0_sram_blwl_out[1668:1668] ,mux_2level_size50_0_sram_blwl_out[1668:1668] ,mux_2level_size50_0_sram_blwl_outb[1668:1668] ,mux_2level_size50_0_configbus0[1668:1668], mux_2level_size50_0_configbus1[1668:1668] , mux_2level_size50_0_configbus0_b[1668:1668] ); -sram6T_blwl sram_blwl_1669_ (mux_2level_size50_0_sram_blwl_out[1669:1669] ,mux_2level_size50_0_sram_blwl_out[1669:1669] ,mux_2level_size50_0_sram_blwl_outb[1669:1669] ,mux_2level_size50_0_configbus0[1669:1669], mux_2level_size50_0_configbus1[1669:1669] , mux_2level_size50_0_configbus0_b[1669:1669] ); -sram6T_blwl sram_blwl_1670_ (mux_2level_size50_0_sram_blwl_out[1670:1670] ,mux_2level_size50_0_sram_blwl_out[1670:1670] ,mux_2level_size50_0_sram_blwl_outb[1670:1670] ,mux_2level_size50_0_configbus0[1670:1670], mux_2level_size50_0_configbus1[1670:1670] , mux_2level_size50_0_configbus0_b[1670:1670] ); -sram6T_blwl sram_blwl_1671_ (mux_2level_size50_0_sram_blwl_out[1671:1671] ,mux_2level_size50_0_sram_blwl_out[1671:1671] ,mux_2level_size50_0_sram_blwl_outb[1671:1671] ,mux_2level_size50_0_configbus0[1671:1671], mux_2level_size50_0_configbus1[1671:1671] , mux_2level_size50_0_configbus0_b[1671:1671] ); -sram6T_blwl sram_blwl_1672_ (mux_2level_size50_0_sram_blwl_out[1672:1672] ,mux_2level_size50_0_sram_blwl_out[1672:1672] ,mux_2level_size50_0_sram_blwl_outb[1672:1672] ,mux_2level_size50_0_configbus0[1672:1672], mux_2level_size50_0_configbus1[1672:1672] , mux_2level_size50_0_configbus0_b[1672:1672] ); -sram6T_blwl sram_blwl_1673_ (mux_2level_size50_0_sram_blwl_out[1673:1673] ,mux_2level_size50_0_sram_blwl_out[1673:1673] ,mux_2level_size50_0_sram_blwl_outb[1673:1673] ,mux_2level_size50_0_configbus0[1673:1673], mux_2level_size50_0_configbus1[1673:1673] , mux_2level_size50_0_configbus0_b[1673:1673] ); -sram6T_blwl sram_blwl_1674_ (mux_2level_size50_0_sram_blwl_out[1674:1674] ,mux_2level_size50_0_sram_blwl_out[1674:1674] ,mux_2level_size50_0_sram_blwl_outb[1674:1674] ,mux_2level_size50_0_configbus0[1674:1674], mux_2level_size50_0_configbus1[1674:1674] , mux_2level_size50_0_configbus0_b[1674:1674] ); -sram6T_blwl sram_blwl_1675_ (mux_2level_size50_0_sram_blwl_out[1675:1675] ,mux_2level_size50_0_sram_blwl_out[1675:1675] ,mux_2level_size50_0_sram_blwl_outb[1675:1675] ,mux_2level_size50_0_configbus0[1675:1675], mux_2level_size50_0_configbus1[1675:1675] , mux_2level_size50_0_configbus0_b[1675:1675] ); -sram6T_blwl sram_blwl_1676_ (mux_2level_size50_0_sram_blwl_out[1676:1676] ,mux_2level_size50_0_sram_blwl_out[1676:1676] ,mux_2level_size50_0_sram_blwl_outb[1676:1676] ,mux_2level_size50_0_configbus0[1676:1676], mux_2level_size50_0_configbus1[1676:1676] , mux_2level_size50_0_configbus0_b[1676:1676] ); -sram6T_blwl sram_blwl_1677_ (mux_2level_size50_0_sram_blwl_out[1677:1677] ,mux_2level_size50_0_sram_blwl_out[1677:1677] ,mux_2level_size50_0_sram_blwl_outb[1677:1677] ,mux_2level_size50_0_configbus0[1677:1677], mux_2level_size50_0_configbus1[1677:1677] , mux_2level_size50_0_configbus0_b[1677:1677] ); -sram6T_blwl sram_blwl_1678_ (mux_2level_size50_0_sram_blwl_out[1678:1678] ,mux_2level_size50_0_sram_blwl_out[1678:1678] ,mux_2level_size50_0_sram_blwl_outb[1678:1678] ,mux_2level_size50_0_configbus0[1678:1678], mux_2level_size50_0_configbus1[1678:1678] , mux_2level_size50_0_configbus0_b[1678:1678] ); -sram6T_blwl sram_blwl_1679_ (mux_2level_size50_0_sram_blwl_out[1679:1679] ,mux_2level_size50_0_sram_blwl_out[1679:1679] ,mux_2level_size50_0_sram_blwl_outb[1679:1679] ,mux_2level_size50_0_configbus0[1679:1679], mux_2level_size50_0_configbus1[1679:1679] , mux_2level_size50_0_configbus0_b[1679:1679] ); -sram6T_blwl sram_blwl_1680_ (mux_2level_size50_0_sram_blwl_out[1680:1680] ,mux_2level_size50_0_sram_blwl_out[1680:1680] ,mux_2level_size50_0_sram_blwl_outb[1680:1680] ,mux_2level_size50_0_configbus0[1680:1680], mux_2level_size50_0_configbus1[1680:1680] , mux_2level_size50_0_configbus0_b[1680:1680] ); -sram6T_blwl sram_blwl_1681_ (mux_2level_size50_0_sram_blwl_out[1681:1681] ,mux_2level_size50_0_sram_blwl_out[1681:1681] ,mux_2level_size50_0_sram_blwl_outb[1681:1681] ,mux_2level_size50_0_configbus0[1681:1681], mux_2level_size50_0_configbus1[1681:1681] , mux_2level_size50_0_configbus0_b[1681:1681] ); -wire [0:49] in_bus_mux_2level_size50_1_ ; -assign in_bus_mux_2level_size50_1_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_1_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_1_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_1_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_1_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_1_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_1_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_1_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_1_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_1_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_1_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_1_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_1_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_1_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_1_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_1_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_1_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_1_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_1_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_1_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_1_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_1_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_1_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_1_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_1_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_1_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_1_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_1_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_1_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_1_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_1_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_1_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_1_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_1_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_1_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_1_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_1_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_1_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_1_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_1_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_1_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_1_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_1_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_1_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_1_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_1_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_1_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_1_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_1_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_1_[49] = fle_9___out_0_ ; -wire [1682:1697] mux_2level_size50_1_configbus0; -wire [1682:1697] mux_2level_size50_1_configbus1; -wire [1682:1697] mux_2level_size50_1_sram_blwl_out ; -wire [1682:1697] mux_2level_size50_1_sram_blwl_outb ; -assign mux_2level_size50_1_configbus0[1682:1697] = sram_blwl_bl[1682:1697] ; -assign mux_2level_size50_1_configbus1[1682:1697] = sram_blwl_wl[1682:1697] ; -wire [1682:1697] mux_2level_size50_1_configbus0_b; -assign mux_2level_size50_1_configbus0_b[1682:1697] = sram_blwl_blb[1682:1697] ; -mux_2level_size50 mux_2level_size50_1_ (in_bus_mux_2level_size50_1_, fle_0___in_1_, mux_2level_size50_1_sram_blwl_out[1682:1697] , -mux_2level_size50_1_sram_blwl_outb[1682:1697] ); -//----- SRAM bits for MUX[1], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1682_ (mux_2level_size50_1_sram_blwl_out[1682:1682] ,mux_2level_size50_1_sram_blwl_out[1682:1682] ,mux_2level_size50_1_sram_blwl_outb[1682:1682] ,mux_2level_size50_1_configbus0[1682:1682], mux_2level_size50_1_configbus1[1682:1682] , mux_2level_size50_1_configbus0_b[1682:1682] ); -sram6T_blwl sram_blwl_1683_ (mux_2level_size50_1_sram_blwl_out[1683:1683] ,mux_2level_size50_1_sram_blwl_out[1683:1683] ,mux_2level_size50_1_sram_blwl_outb[1683:1683] ,mux_2level_size50_1_configbus0[1683:1683], mux_2level_size50_1_configbus1[1683:1683] , mux_2level_size50_1_configbus0_b[1683:1683] ); -sram6T_blwl sram_blwl_1684_ (mux_2level_size50_1_sram_blwl_out[1684:1684] ,mux_2level_size50_1_sram_blwl_out[1684:1684] ,mux_2level_size50_1_sram_blwl_outb[1684:1684] ,mux_2level_size50_1_configbus0[1684:1684], mux_2level_size50_1_configbus1[1684:1684] , mux_2level_size50_1_configbus0_b[1684:1684] ); -sram6T_blwl sram_blwl_1685_ (mux_2level_size50_1_sram_blwl_out[1685:1685] ,mux_2level_size50_1_sram_blwl_out[1685:1685] ,mux_2level_size50_1_sram_blwl_outb[1685:1685] ,mux_2level_size50_1_configbus0[1685:1685], mux_2level_size50_1_configbus1[1685:1685] , mux_2level_size50_1_configbus0_b[1685:1685] ); -sram6T_blwl sram_blwl_1686_ (mux_2level_size50_1_sram_blwl_out[1686:1686] ,mux_2level_size50_1_sram_blwl_out[1686:1686] ,mux_2level_size50_1_sram_blwl_outb[1686:1686] ,mux_2level_size50_1_configbus0[1686:1686], mux_2level_size50_1_configbus1[1686:1686] , mux_2level_size50_1_configbus0_b[1686:1686] ); -sram6T_blwl sram_blwl_1687_ (mux_2level_size50_1_sram_blwl_out[1687:1687] ,mux_2level_size50_1_sram_blwl_out[1687:1687] ,mux_2level_size50_1_sram_blwl_outb[1687:1687] ,mux_2level_size50_1_configbus0[1687:1687], mux_2level_size50_1_configbus1[1687:1687] , mux_2level_size50_1_configbus0_b[1687:1687] ); -sram6T_blwl sram_blwl_1688_ (mux_2level_size50_1_sram_blwl_out[1688:1688] ,mux_2level_size50_1_sram_blwl_out[1688:1688] ,mux_2level_size50_1_sram_blwl_outb[1688:1688] ,mux_2level_size50_1_configbus0[1688:1688], mux_2level_size50_1_configbus1[1688:1688] , mux_2level_size50_1_configbus0_b[1688:1688] ); -sram6T_blwl sram_blwl_1689_ (mux_2level_size50_1_sram_blwl_out[1689:1689] ,mux_2level_size50_1_sram_blwl_out[1689:1689] ,mux_2level_size50_1_sram_blwl_outb[1689:1689] ,mux_2level_size50_1_configbus0[1689:1689], mux_2level_size50_1_configbus1[1689:1689] , mux_2level_size50_1_configbus0_b[1689:1689] ); -sram6T_blwl sram_blwl_1690_ (mux_2level_size50_1_sram_blwl_out[1690:1690] ,mux_2level_size50_1_sram_blwl_out[1690:1690] ,mux_2level_size50_1_sram_blwl_outb[1690:1690] ,mux_2level_size50_1_configbus0[1690:1690], mux_2level_size50_1_configbus1[1690:1690] , mux_2level_size50_1_configbus0_b[1690:1690] ); -sram6T_blwl sram_blwl_1691_ (mux_2level_size50_1_sram_blwl_out[1691:1691] ,mux_2level_size50_1_sram_blwl_out[1691:1691] ,mux_2level_size50_1_sram_blwl_outb[1691:1691] ,mux_2level_size50_1_configbus0[1691:1691], mux_2level_size50_1_configbus1[1691:1691] , mux_2level_size50_1_configbus0_b[1691:1691] ); -sram6T_blwl sram_blwl_1692_ (mux_2level_size50_1_sram_blwl_out[1692:1692] ,mux_2level_size50_1_sram_blwl_out[1692:1692] ,mux_2level_size50_1_sram_blwl_outb[1692:1692] ,mux_2level_size50_1_configbus0[1692:1692], mux_2level_size50_1_configbus1[1692:1692] , mux_2level_size50_1_configbus0_b[1692:1692] ); -sram6T_blwl sram_blwl_1693_ (mux_2level_size50_1_sram_blwl_out[1693:1693] ,mux_2level_size50_1_sram_blwl_out[1693:1693] ,mux_2level_size50_1_sram_blwl_outb[1693:1693] ,mux_2level_size50_1_configbus0[1693:1693], mux_2level_size50_1_configbus1[1693:1693] , mux_2level_size50_1_configbus0_b[1693:1693] ); -sram6T_blwl sram_blwl_1694_ (mux_2level_size50_1_sram_blwl_out[1694:1694] ,mux_2level_size50_1_sram_blwl_out[1694:1694] ,mux_2level_size50_1_sram_blwl_outb[1694:1694] ,mux_2level_size50_1_configbus0[1694:1694], mux_2level_size50_1_configbus1[1694:1694] , mux_2level_size50_1_configbus0_b[1694:1694] ); -sram6T_blwl sram_blwl_1695_ (mux_2level_size50_1_sram_blwl_out[1695:1695] ,mux_2level_size50_1_sram_blwl_out[1695:1695] ,mux_2level_size50_1_sram_blwl_outb[1695:1695] ,mux_2level_size50_1_configbus0[1695:1695], mux_2level_size50_1_configbus1[1695:1695] , mux_2level_size50_1_configbus0_b[1695:1695] ); -sram6T_blwl sram_blwl_1696_ (mux_2level_size50_1_sram_blwl_out[1696:1696] ,mux_2level_size50_1_sram_blwl_out[1696:1696] ,mux_2level_size50_1_sram_blwl_outb[1696:1696] ,mux_2level_size50_1_configbus0[1696:1696], mux_2level_size50_1_configbus1[1696:1696] , mux_2level_size50_1_configbus0_b[1696:1696] ); -sram6T_blwl sram_blwl_1697_ (mux_2level_size50_1_sram_blwl_out[1697:1697] ,mux_2level_size50_1_sram_blwl_out[1697:1697] ,mux_2level_size50_1_sram_blwl_outb[1697:1697] ,mux_2level_size50_1_configbus0[1697:1697], mux_2level_size50_1_configbus1[1697:1697] , mux_2level_size50_1_configbus0_b[1697:1697] ); -wire [0:49] in_bus_mux_2level_size50_2_ ; -assign in_bus_mux_2level_size50_2_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_2_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_2_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_2_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_2_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_2_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_2_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_2_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_2_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_2_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_2_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_2_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_2_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_2_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_2_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_2_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_2_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_2_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_2_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_2_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_2_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_2_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_2_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_2_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_2_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_2_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_2_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_2_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_2_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_2_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_2_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_2_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_2_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_2_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_2_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_2_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_2_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_2_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_2_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_2_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_2_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_2_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_2_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_2_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_2_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_2_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_2_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_2_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_2_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_2_[49] = fle_9___out_0_ ; -wire [1698:1713] mux_2level_size50_2_configbus0; -wire [1698:1713] mux_2level_size50_2_configbus1; -wire [1698:1713] mux_2level_size50_2_sram_blwl_out ; -wire [1698:1713] mux_2level_size50_2_sram_blwl_outb ; -assign mux_2level_size50_2_configbus0[1698:1713] = sram_blwl_bl[1698:1713] ; -assign mux_2level_size50_2_configbus1[1698:1713] = sram_blwl_wl[1698:1713] ; -wire [1698:1713] mux_2level_size50_2_configbus0_b; -assign mux_2level_size50_2_configbus0_b[1698:1713] = sram_blwl_blb[1698:1713] ; -mux_2level_size50 mux_2level_size50_2_ (in_bus_mux_2level_size50_2_, fle_0___in_2_, mux_2level_size50_2_sram_blwl_out[1698:1713] , -mux_2level_size50_2_sram_blwl_outb[1698:1713] ); -//----- SRAM bits for MUX[2], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1698_ (mux_2level_size50_2_sram_blwl_out[1698:1698] ,mux_2level_size50_2_sram_blwl_out[1698:1698] ,mux_2level_size50_2_sram_blwl_outb[1698:1698] ,mux_2level_size50_2_configbus0[1698:1698], mux_2level_size50_2_configbus1[1698:1698] , mux_2level_size50_2_configbus0_b[1698:1698] ); -sram6T_blwl sram_blwl_1699_ (mux_2level_size50_2_sram_blwl_out[1699:1699] ,mux_2level_size50_2_sram_blwl_out[1699:1699] ,mux_2level_size50_2_sram_blwl_outb[1699:1699] ,mux_2level_size50_2_configbus0[1699:1699], mux_2level_size50_2_configbus1[1699:1699] , mux_2level_size50_2_configbus0_b[1699:1699] ); -sram6T_blwl sram_blwl_1700_ (mux_2level_size50_2_sram_blwl_out[1700:1700] ,mux_2level_size50_2_sram_blwl_out[1700:1700] ,mux_2level_size50_2_sram_blwl_outb[1700:1700] ,mux_2level_size50_2_configbus0[1700:1700], mux_2level_size50_2_configbus1[1700:1700] , mux_2level_size50_2_configbus0_b[1700:1700] ); -sram6T_blwl sram_blwl_1701_ (mux_2level_size50_2_sram_blwl_out[1701:1701] ,mux_2level_size50_2_sram_blwl_out[1701:1701] ,mux_2level_size50_2_sram_blwl_outb[1701:1701] ,mux_2level_size50_2_configbus0[1701:1701], mux_2level_size50_2_configbus1[1701:1701] , mux_2level_size50_2_configbus0_b[1701:1701] ); -sram6T_blwl sram_blwl_1702_ (mux_2level_size50_2_sram_blwl_out[1702:1702] ,mux_2level_size50_2_sram_blwl_out[1702:1702] ,mux_2level_size50_2_sram_blwl_outb[1702:1702] ,mux_2level_size50_2_configbus0[1702:1702], mux_2level_size50_2_configbus1[1702:1702] , mux_2level_size50_2_configbus0_b[1702:1702] ); -sram6T_blwl sram_blwl_1703_ (mux_2level_size50_2_sram_blwl_out[1703:1703] ,mux_2level_size50_2_sram_blwl_out[1703:1703] ,mux_2level_size50_2_sram_blwl_outb[1703:1703] ,mux_2level_size50_2_configbus0[1703:1703], mux_2level_size50_2_configbus1[1703:1703] , mux_2level_size50_2_configbus0_b[1703:1703] ); -sram6T_blwl sram_blwl_1704_ (mux_2level_size50_2_sram_blwl_out[1704:1704] ,mux_2level_size50_2_sram_blwl_out[1704:1704] ,mux_2level_size50_2_sram_blwl_outb[1704:1704] ,mux_2level_size50_2_configbus0[1704:1704], mux_2level_size50_2_configbus1[1704:1704] , mux_2level_size50_2_configbus0_b[1704:1704] ); -sram6T_blwl sram_blwl_1705_ (mux_2level_size50_2_sram_blwl_out[1705:1705] ,mux_2level_size50_2_sram_blwl_out[1705:1705] ,mux_2level_size50_2_sram_blwl_outb[1705:1705] ,mux_2level_size50_2_configbus0[1705:1705], mux_2level_size50_2_configbus1[1705:1705] , mux_2level_size50_2_configbus0_b[1705:1705] ); -sram6T_blwl sram_blwl_1706_ (mux_2level_size50_2_sram_blwl_out[1706:1706] ,mux_2level_size50_2_sram_blwl_out[1706:1706] ,mux_2level_size50_2_sram_blwl_outb[1706:1706] ,mux_2level_size50_2_configbus0[1706:1706], mux_2level_size50_2_configbus1[1706:1706] , mux_2level_size50_2_configbus0_b[1706:1706] ); -sram6T_blwl sram_blwl_1707_ (mux_2level_size50_2_sram_blwl_out[1707:1707] ,mux_2level_size50_2_sram_blwl_out[1707:1707] ,mux_2level_size50_2_sram_blwl_outb[1707:1707] ,mux_2level_size50_2_configbus0[1707:1707], mux_2level_size50_2_configbus1[1707:1707] , mux_2level_size50_2_configbus0_b[1707:1707] ); -sram6T_blwl sram_blwl_1708_ (mux_2level_size50_2_sram_blwl_out[1708:1708] ,mux_2level_size50_2_sram_blwl_out[1708:1708] ,mux_2level_size50_2_sram_blwl_outb[1708:1708] ,mux_2level_size50_2_configbus0[1708:1708], mux_2level_size50_2_configbus1[1708:1708] , mux_2level_size50_2_configbus0_b[1708:1708] ); -sram6T_blwl sram_blwl_1709_ (mux_2level_size50_2_sram_blwl_out[1709:1709] ,mux_2level_size50_2_sram_blwl_out[1709:1709] ,mux_2level_size50_2_sram_blwl_outb[1709:1709] ,mux_2level_size50_2_configbus0[1709:1709], mux_2level_size50_2_configbus1[1709:1709] , mux_2level_size50_2_configbus0_b[1709:1709] ); -sram6T_blwl sram_blwl_1710_ (mux_2level_size50_2_sram_blwl_out[1710:1710] ,mux_2level_size50_2_sram_blwl_out[1710:1710] ,mux_2level_size50_2_sram_blwl_outb[1710:1710] ,mux_2level_size50_2_configbus0[1710:1710], mux_2level_size50_2_configbus1[1710:1710] , mux_2level_size50_2_configbus0_b[1710:1710] ); -sram6T_blwl sram_blwl_1711_ (mux_2level_size50_2_sram_blwl_out[1711:1711] ,mux_2level_size50_2_sram_blwl_out[1711:1711] ,mux_2level_size50_2_sram_blwl_outb[1711:1711] ,mux_2level_size50_2_configbus0[1711:1711], mux_2level_size50_2_configbus1[1711:1711] , mux_2level_size50_2_configbus0_b[1711:1711] ); -sram6T_blwl sram_blwl_1712_ (mux_2level_size50_2_sram_blwl_out[1712:1712] ,mux_2level_size50_2_sram_blwl_out[1712:1712] ,mux_2level_size50_2_sram_blwl_outb[1712:1712] ,mux_2level_size50_2_configbus0[1712:1712], mux_2level_size50_2_configbus1[1712:1712] , mux_2level_size50_2_configbus0_b[1712:1712] ); -sram6T_blwl sram_blwl_1713_ (mux_2level_size50_2_sram_blwl_out[1713:1713] ,mux_2level_size50_2_sram_blwl_out[1713:1713] ,mux_2level_size50_2_sram_blwl_outb[1713:1713] ,mux_2level_size50_2_configbus0[1713:1713], mux_2level_size50_2_configbus1[1713:1713] , mux_2level_size50_2_configbus0_b[1713:1713] ); -wire [0:49] in_bus_mux_2level_size50_3_ ; -assign in_bus_mux_2level_size50_3_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_3_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_3_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_3_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_3_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_3_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_3_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_3_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_3_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_3_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_3_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_3_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_3_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_3_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_3_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_3_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_3_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_3_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_3_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_3_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_3_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_3_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_3_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_3_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_3_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_3_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_3_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_3_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_3_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_3_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_3_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_3_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_3_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_3_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_3_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_3_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_3_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_3_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_3_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_3_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_3_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_3_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_3_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_3_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_3_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_3_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_3_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_3_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_3_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_3_[49] = fle_9___out_0_ ; -wire [1714:1729] mux_2level_size50_3_configbus0; -wire [1714:1729] mux_2level_size50_3_configbus1; -wire [1714:1729] mux_2level_size50_3_sram_blwl_out ; -wire [1714:1729] mux_2level_size50_3_sram_blwl_outb ; -assign mux_2level_size50_3_configbus0[1714:1729] = sram_blwl_bl[1714:1729] ; -assign mux_2level_size50_3_configbus1[1714:1729] = sram_blwl_wl[1714:1729] ; -wire [1714:1729] mux_2level_size50_3_configbus0_b; -assign mux_2level_size50_3_configbus0_b[1714:1729] = sram_blwl_blb[1714:1729] ; -mux_2level_size50 mux_2level_size50_3_ (in_bus_mux_2level_size50_3_, fle_0___in_3_, mux_2level_size50_3_sram_blwl_out[1714:1729] , -mux_2level_size50_3_sram_blwl_outb[1714:1729] ); -//----- SRAM bits for MUX[3], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1714_ (mux_2level_size50_3_sram_blwl_out[1714:1714] ,mux_2level_size50_3_sram_blwl_out[1714:1714] ,mux_2level_size50_3_sram_blwl_outb[1714:1714] ,mux_2level_size50_3_configbus0[1714:1714], mux_2level_size50_3_configbus1[1714:1714] , mux_2level_size50_3_configbus0_b[1714:1714] ); -sram6T_blwl sram_blwl_1715_ (mux_2level_size50_3_sram_blwl_out[1715:1715] ,mux_2level_size50_3_sram_blwl_out[1715:1715] ,mux_2level_size50_3_sram_blwl_outb[1715:1715] ,mux_2level_size50_3_configbus0[1715:1715], mux_2level_size50_3_configbus1[1715:1715] , mux_2level_size50_3_configbus0_b[1715:1715] ); -sram6T_blwl sram_blwl_1716_ (mux_2level_size50_3_sram_blwl_out[1716:1716] ,mux_2level_size50_3_sram_blwl_out[1716:1716] ,mux_2level_size50_3_sram_blwl_outb[1716:1716] ,mux_2level_size50_3_configbus0[1716:1716], mux_2level_size50_3_configbus1[1716:1716] , mux_2level_size50_3_configbus0_b[1716:1716] ); -sram6T_blwl sram_blwl_1717_ (mux_2level_size50_3_sram_blwl_out[1717:1717] ,mux_2level_size50_3_sram_blwl_out[1717:1717] ,mux_2level_size50_3_sram_blwl_outb[1717:1717] ,mux_2level_size50_3_configbus0[1717:1717], mux_2level_size50_3_configbus1[1717:1717] , mux_2level_size50_3_configbus0_b[1717:1717] ); -sram6T_blwl sram_blwl_1718_ (mux_2level_size50_3_sram_blwl_out[1718:1718] ,mux_2level_size50_3_sram_blwl_out[1718:1718] ,mux_2level_size50_3_sram_blwl_outb[1718:1718] ,mux_2level_size50_3_configbus0[1718:1718], mux_2level_size50_3_configbus1[1718:1718] , mux_2level_size50_3_configbus0_b[1718:1718] ); -sram6T_blwl sram_blwl_1719_ (mux_2level_size50_3_sram_blwl_out[1719:1719] ,mux_2level_size50_3_sram_blwl_out[1719:1719] ,mux_2level_size50_3_sram_blwl_outb[1719:1719] ,mux_2level_size50_3_configbus0[1719:1719], mux_2level_size50_3_configbus1[1719:1719] , mux_2level_size50_3_configbus0_b[1719:1719] ); -sram6T_blwl sram_blwl_1720_ (mux_2level_size50_3_sram_blwl_out[1720:1720] ,mux_2level_size50_3_sram_blwl_out[1720:1720] ,mux_2level_size50_3_sram_blwl_outb[1720:1720] ,mux_2level_size50_3_configbus0[1720:1720], mux_2level_size50_3_configbus1[1720:1720] , mux_2level_size50_3_configbus0_b[1720:1720] ); -sram6T_blwl sram_blwl_1721_ (mux_2level_size50_3_sram_blwl_out[1721:1721] ,mux_2level_size50_3_sram_blwl_out[1721:1721] ,mux_2level_size50_3_sram_blwl_outb[1721:1721] ,mux_2level_size50_3_configbus0[1721:1721], mux_2level_size50_3_configbus1[1721:1721] , mux_2level_size50_3_configbus0_b[1721:1721] ); -sram6T_blwl sram_blwl_1722_ (mux_2level_size50_3_sram_blwl_out[1722:1722] ,mux_2level_size50_3_sram_blwl_out[1722:1722] ,mux_2level_size50_3_sram_blwl_outb[1722:1722] ,mux_2level_size50_3_configbus0[1722:1722], mux_2level_size50_3_configbus1[1722:1722] , mux_2level_size50_3_configbus0_b[1722:1722] ); -sram6T_blwl sram_blwl_1723_ (mux_2level_size50_3_sram_blwl_out[1723:1723] ,mux_2level_size50_3_sram_blwl_out[1723:1723] ,mux_2level_size50_3_sram_blwl_outb[1723:1723] ,mux_2level_size50_3_configbus0[1723:1723], mux_2level_size50_3_configbus1[1723:1723] , mux_2level_size50_3_configbus0_b[1723:1723] ); -sram6T_blwl sram_blwl_1724_ (mux_2level_size50_3_sram_blwl_out[1724:1724] ,mux_2level_size50_3_sram_blwl_out[1724:1724] ,mux_2level_size50_3_sram_blwl_outb[1724:1724] ,mux_2level_size50_3_configbus0[1724:1724], mux_2level_size50_3_configbus1[1724:1724] , mux_2level_size50_3_configbus0_b[1724:1724] ); -sram6T_blwl sram_blwl_1725_ (mux_2level_size50_3_sram_blwl_out[1725:1725] ,mux_2level_size50_3_sram_blwl_out[1725:1725] ,mux_2level_size50_3_sram_blwl_outb[1725:1725] ,mux_2level_size50_3_configbus0[1725:1725], mux_2level_size50_3_configbus1[1725:1725] , mux_2level_size50_3_configbus0_b[1725:1725] ); -sram6T_blwl sram_blwl_1726_ (mux_2level_size50_3_sram_blwl_out[1726:1726] ,mux_2level_size50_3_sram_blwl_out[1726:1726] ,mux_2level_size50_3_sram_blwl_outb[1726:1726] ,mux_2level_size50_3_configbus0[1726:1726], mux_2level_size50_3_configbus1[1726:1726] , mux_2level_size50_3_configbus0_b[1726:1726] ); -sram6T_blwl sram_blwl_1727_ (mux_2level_size50_3_sram_blwl_out[1727:1727] ,mux_2level_size50_3_sram_blwl_out[1727:1727] ,mux_2level_size50_3_sram_blwl_outb[1727:1727] ,mux_2level_size50_3_configbus0[1727:1727], mux_2level_size50_3_configbus1[1727:1727] , mux_2level_size50_3_configbus0_b[1727:1727] ); -sram6T_blwl sram_blwl_1728_ (mux_2level_size50_3_sram_blwl_out[1728:1728] ,mux_2level_size50_3_sram_blwl_out[1728:1728] ,mux_2level_size50_3_sram_blwl_outb[1728:1728] ,mux_2level_size50_3_configbus0[1728:1728], mux_2level_size50_3_configbus1[1728:1728] , mux_2level_size50_3_configbus0_b[1728:1728] ); -sram6T_blwl sram_blwl_1729_ (mux_2level_size50_3_sram_blwl_out[1729:1729] ,mux_2level_size50_3_sram_blwl_out[1729:1729] ,mux_2level_size50_3_sram_blwl_outb[1729:1729] ,mux_2level_size50_3_configbus0[1729:1729], mux_2level_size50_3_configbus1[1729:1729] , mux_2level_size50_3_configbus0_b[1729:1729] ); -wire [0:49] in_bus_mux_2level_size50_4_ ; -assign in_bus_mux_2level_size50_4_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_4_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_4_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_4_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_4_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_4_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_4_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_4_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_4_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_4_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_4_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_4_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_4_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_4_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_4_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_4_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_4_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_4_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_4_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_4_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_4_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_4_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_4_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_4_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_4_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_4_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_4_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_4_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_4_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_4_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_4_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_4_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_4_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_4_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_4_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_4_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_4_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_4_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_4_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_4_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_4_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_4_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_4_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_4_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_4_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_4_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_4_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_4_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_4_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_4_[49] = fle_9___out_0_ ; -wire [1730:1745] mux_2level_size50_4_configbus0; -wire [1730:1745] mux_2level_size50_4_configbus1; -wire [1730:1745] mux_2level_size50_4_sram_blwl_out ; -wire [1730:1745] mux_2level_size50_4_sram_blwl_outb ; -assign mux_2level_size50_4_configbus0[1730:1745] = sram_blwl_bl[1730:1745] ; -assign mux_2level_size50_4_configbus1[1730:1745] = sram_blwl_wl[1730:1745] ; -wire [1730:1745] mux_2level_size50_4_configbus0_b; -assign mux_2level_size50_4_configbus0_b[1730:1745] = sram_blwl_blb[1730:1745] ; -mux_2level_size50 mux_2level_size50_4_ (in_bus_mux_2level_size50_4_, fle_0___in_4_, mux_2level_size50_4_sram_blwl_out[1730:1745] , -mux_2level_size50_4_sram_blwl_outb[1730:1745] ); -//----- SRAM bits for MUX[4], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1730_ (mux_2level_size50_4_sram_blwl_out[1730:1730] ,mux_2level_size50_4_sram_blwl_out[1730:1730] ,mux_2level_size50_4_sram_blwl_outb[1730:1730] ,mux_2level_size50_4_configbus0[1730:1730], mux_2level_size50_4_configbus1[1730:1730] , mux_2level_size50_4_configbus0_b[1730:1730] ); -sram6T_blwl sram_blwl_1731_ (mux_2level_size50_4_sram_blwl_out[1731:1731] ,mux_2level_size50_4_sram_blwl_out[1731:1731] ,mux_2level_size50_4_sram_blwl_outb[1731:1731] ,mux_2level_size50_4_configbus0[1731:1731], mux_2level_size50_4_configbus1[1731:1731] , mux_2level_size50_4_configbus0_b[1731:1731] ); -sram6T_blwl sram_blwl_1732_ (mux_2level_size50_4_sram_blwl_out[1732:1732] ,mux_2level_size50_4_sram_blwl_out[1732:1732] ,mux_2level_size50_4_sram_blwl_outb[1732:1732] ,mux_2level_size50_4_configbus0[1732:1732], mux_2level_size50_4_configbus1[1732:1732] , mux_2level_size50_4_configbus0_b[1732:1732] ); -sram6T_blwl sram_blwl_1733_ (mux_2level_size50_4_sram_blwl_out[1733:1733] ,mux_2level_size50_4_sram_blwl_out[1733:1733] ,mux_2level_size50_4_sram_blwl_outb[1733:1733] ,mux_2level_size50_4_configbus0[1733:1733], mux_2level_size50_4_configbus1[1733:1733] , mux_2level_size50_4_configbus0_b[1733:1733] ); -sram6T_blwl sram_blwl_1734_ (mux_2level_size50_4_sram_blwl_out[1734:1734] ,mux_2level_size50_4_sram_blwl_out[1734:1734] ,mux_2level_size50_4_sram_blwl_outb[1734:1734] ,mux_2level_size50_4_configbus0[1734:1734], mux_2level_size50_4_configbus1[1734:1734] , mux_2level_size50_4_configbus0_b[1734:1734] ); -sram6T_blwl sram_blwl_1735_ (mux_2level_size50_4_sram_blwl_out[1735:1735] ,mux_2level_size50_4_sram_blwl_out[1735:1735] ,mux_2level_size50_4_sram_blwl_outb[1735:1735] ,mux_2level_size50_4_configbus0[1735:1735], mux_2level_size50_4_configbus1[1735:1735] , mux_2level_size50_4_configbus0_b[1735:1735] ); -sram6T_blwl sram_blwl_1736_ (mux_2level_size50_4_sram_blwl_out[1736:1736] ,mux_2level_size50_4_sram_blwl_out[1736:1736] ,mux_2level_size50_4_sram_blwl_outb[1736:1736] ,mux_2level_size50_4_configbus0[1736:1736], mux_2level_size50_4_configbus1[1736:1736] , mux_2level_size50_4_configbus0_b[1736:1736] ); -sram6T_blwl sram_blwl_1737_ (mux_2level_size50_4_sram_blwl_out[1737:1737] ,mux_2level_size50_4_sram_blwl_out[1737:1737] ,mux_2level_size50_4_sram_blwl_outb[1737:1737] ,mux_2level_size50_4_configbus0[1737:1737], mux_2level_size50_4_configbus1[1737:1737] , mux_2level_size50_4_configbus0_b[1737:1737] ); -sram6T_blwl sram_blwl_1738_ (mux_2level_size50_4_sram_blwl_out[1738:1738] ,mux_2level_size50_4_sram_blwl_out[1738:1738] ,mux_2level_size50_4_sram_blwl_outb[1738:1738] ,mux_2level_size50_4_configbus0[1738:1738], mux_2level_size50_4_configbus1[1738:1738] , mux_2level_size50_4_configbus0_b[1738:1738] ); -sram6T_blwl sram_blwl_1739_ (mux_2level_size50_4_sram_blwl_out[1739:1739] ,mux_2level_size50_4_sram_blwl_out[1739:1739] ,mux_2level_size50_4_sram_blwl_outb[1739:1739] ,mux_2level_size50_4_configbus0[1739:1739], mux_2level_size50_4_configbus1[1739:1739] , mux_2level_size50_4_configbus0_b[1739:1739] ); -sram6T_blwl sram_blwl_1740_ (mux_2level_size50_4_sram_blwl_out[1740:1740] ,mux_2level_size50_4_sram_blwl_out[1740:1740] ,mux_2level_size50_4_sram_blwl_outb[1740:1740] ,mux_2level_size50_4_configbus0[1740:1740], mux_2level_size50_4_configbus1[1740:1740] , mux_2level_size50_4_configbus0_b[1740:1740] ); -sram6T_blwl sram_blwl_1741_ (mux_2level_size50_4_sram_blwl_out[1741:1741] ,mux_2level_size50_4_sram_blwl_out[1741:1741] ,mux_2level_size50_4_sram_blwl_outb[1741:1741] ,mux_2level_size50_4_configbus0[1741:1741], mux_2level_size50_4_configbus1[1741:1741] , mux_2level_size50_4_configbus0_b[1741:1741] ); -sram6T_blwl sram_blwl_1742_ (mux_2level_size50_4_sram_blwl_out[1742:1742] ,mux_2level_size50_4_sram_blwl_out[1742:1742] ,mux_2level_size50_4_sram_blwl_outb[1742:1742] ,mux_2level_size50_4_configbus0[1742:1742], mux_2level_size50_4_configbus1[1742:1742] , mux_2level_size50_4_configbus0_b[1742:1742] ); -sram6T_blwl sram_blwl_1743_ (mux_2level_size50_4_sram_blwl_out[1743:1743] ,mux_2level_size50_4_sram_blwl_out[1743:1743] ,mux_2level_size50_4_sram_blwl_outb[1743:1743] ,mux_2level_size50_4_configbus0[1743:1743], mux_2level_size50_4_configbus1[1743:1743] , mux_2level_size50_4_configbus0_b[1743:1743] ); -sram6T_blwl sram_blwl_1744_ (mux_2level_size50_4_sram_blwl_out[1744:1744] ,mux_2level_size50_4_sram_blwl_out[1744:1744] ,mux_2level_size50_4_sram_blwl_outb[1744:1744] ,mux_2level_size50_4_configbus0[1744:1744], mux_2level_size50_4_configbus1[1744:1744] , mux_2level_size50_4_configbus0_b[1744:1744] ); -sram6T_blwl sram_blwl_1745_ (mux_2level_size50_4_sram_blwl_out[1745:1745] ,mux_2level_size50_4_sram_blwl_out[1745:1745] ,mux_2level_size50_4_sram_blwl_outb[1745:1745] ,mux_2level_size50_4_configbus0[1745:1745], mux_2level_size50_4_configbus1[1745:1745] , mux_2level_size50_4_configbus0_b[1745:1745] ); -wire [0:49] in_bus_mux_2level_size50_5_ ; -assign in_bus_mux_2level_size50_5_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_5_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_5_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_5_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_5_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_5_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_5_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_5_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_5_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_5_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_5_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_5_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_5_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_5_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_5_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_5_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_5_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_5_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_5_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_5_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_5_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_5_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_5_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_5_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_5_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_5_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_5_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_5_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_5_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_5_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_5_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_5_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_5_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_5_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_5_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_5_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_5_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_5_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_5_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_5_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_5_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_5_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_5_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_5_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_5_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_5_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_5_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_5_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_5_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_5_[49] = fle_9___out_0_ ; -wire [1746:1761] mux_2level_size50_5_configbus0; -wire [1746:1761] mux_2level_size50_5_configbus1; -wire [1746:1761] mux_2level_size50_5_sram_blwl_out ; -wire [1746:1761] mux_2level_size50_5_sram_blwl_outb ; -assign mux_2level_size50_5_configbus0[1746:1761] = sram_blwl_bl[1746:1761] ; -assign mux_2level_size50_5_configbus1[1746:1761] = sram_blwl_wl[1746:1761] ; -wire [1746:1761] mux_2level_size50_5_configbus0_b; -assign mux_2level_size50_5_configbus0_b[1746:1761] = sram_blwl_blb[1746:1761] ; -mux_2level_size50 mux_2level_size50_5_ (in_bus_mux_2level_size50_5_, fle_0___in_5_, mux_2level_size50_5_sram_blwl_out[1746:1761] , -mux_2level_size50_5_sram_blwl_outb[1746:1761] ); -//----- SRAM bits for MUX[5], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1746_ (mux_2level_size50_5_sram_blwl_out[1746:1746] ,mux_2level_size50_5_sram_blwl_out[1746:1746] ,mux_2level_size50_5_sram_blwl_outb[1746:1746] ,mux_2level_size50_5_configbus0[1746:1746], mux_2level_size50_5_configbus1[1746:1746] , mux_2level_size50_5_configbus0_b[1746:1746] ); -sram6T_blwl sram_blwl_1747_ (mux_2level_size50_5_sram_blwl_out[1747:1747] ,mux_2level_size50_5_sram_blwl_out[1747:1747] ,mux_2level_size50_5_sram_blwl_outb[1747:1747] ,mux_2level_size50_5_configbus0[1747:1747], mux_2level_size50_5_configbus1[1747:1747] , mux_2level_size50_5_configbus0_b[1747:1747] ); -sram6T_blwl sram_blwl_1748_ (mux_2level_size50_5_sram_blwl_out[1748:1748] ,mux_2level_size50_5_sram_blwl_out[1748:1748] ,mux_2level_size50_5_sram_blwl_outb[1748:1748] ,mux_2level_size50_5_configbus0[1748:1748], mux_2level_size50_5_configbus1[1748:1748] , mux_2level_size50_5_configbus0_b[1748:1748] ); -sram6T_blwl sram_blwl_1749_ (mux_2level_size50_5_sram_blwl_out[1749:1749] ,mux_2level_size50_5_sram_blwl_out[1749:1749] ,mux_2level_size50_5_sram_blwl_outb[1749:1749] ,mux_2level_size50_5_configbus0[1749:1749], mux_2level_size50_5_configbus1[1749:1749] , mux_2level_size50_5_configbus0_b[1749:1749] ); -sram6T_blwl sram_blwl_1750_ (mux_2level_size50_5_sram_blwl_out[1750:1750] ,mux_2level_size50_5_sram_blwl_out[1750:1750] ,mux_2level_size50_5_sram_blwl_outb[1750:1750] ,mux_2level_size50_5_configbus0[1750:1750], mux_2level_size50_5_configbus1[1750:1750] , mux_2level_size50_5_configbus0_b[1750:1750] ); -sram6T_blwl sram_blwl_1751_ (mux_2level_size50_5_sram_blwl_out[1751:1751] ,mux_2level_size50_5_sram_blwl_out[1751:1751] ,mux_2level_size50_5_sram_blwl_outb[1751:1751] ,mux_2level_size50_5_configbus0[1751:1751], mux_2level_size50_5_configbus1[1751:1751] , mux_2level_size50_5_configbus0_b[1751:1751] ); -sram6T_blwl sram_blwl_1752_ (mux_2level_size50_5_sram_blwl_out[1752:1752] ,mux_2level_size50_5_sram_blwl_out[1752:1752] ,mux_2level_size50_5_sram_blwl_outb[1752:1752] ,mux_2level_size50_5_configbus0[1752:1752], mux_2level_size50_5_configbus1[1752:1752] , mux_2level_size50_5_configbus0_b[1752:1752] ); -sram6T_blwl sram_blwl_1753_ (mux_2level_size50_5_sram_blwl_out[1753:1753] ,mux_2level_size50_5_sram_blwl_out[1753:1753] ,mux_2level_size50_5_sram_blwl_outb[1753:1753] ,mux_2level_size50_5_configbus0[1753:1753], mux_2level_size50_5_configbus1[1753:1753] , mux_2level_size50_5_configbus0_b[1753:1753] ); -sram6T_blwl sram_blwl_1754_ (mux_2level_size50_5_sram_blwl_out[1754:1754] ,mux_2level_size50_5_sram_blwl_out[1754:1754] ,mux_2level_size50_5_sram_blwl_outb[1754:1754] ,mux_2level_size50_5_configbus0[1754:1754], mux_2level_size50_5_configbus1[1754:1754] , mux_2level_size50_5_configbus0_b[1754:1754] ); -sram6T_blwl sram_blwl_1755_ (mux_2level_size50_5_sram_blwl_out[1755:1755] ,mux_2level_size50_5_sram_blwl_out[1755:1755] ,mux_2level_size50_5_sram_blwl_outb[1755:1755] ,mux_2level_size50_5_configbus0[1755:1755], mux_2level_size50_5_configbus1[1755:1755] , mux_2level_size50_5_configbus0_b[1755:1755] ); -sram6T_blwl sram_blwl_1756_ (mux_2level_size50_5_sram_blwl_out[1756:1756] ,mux_2level_size50_5_sram_blwl_out[1756:1756] ,mux_2level_size50_5_sram_blwl_outb[1756:1756] ,mux_2level_size50_5_configbus0[1756:1756], mux_2level_size50_5_configbus1[1756:1756] , mux_2level_size50_5_configbus0_b[1756:1756] ); -sram6T_blwl sram_blwl_1757_ (mux_2level_size50_5_sram_blwl_out[1757:1757] ,mux_2level_size50_5_sram_blwl_out[1757:1757] ,mux_2level_size50_5_sram_blwl_outb[1757:1757] ,mux_2level_size50_5_configbus0[1757:1757], mux_2level_size50_5_configbus1[1757:1757] , mux_2level_size50_5_configbus0_b[1757:1757] ); -sram6T_blwl sram_blwl_1758_ (mux_2level_size50_5_sram_blwl_out[1758:1758] ,mux_2level_size50_5_sram_blwl_out[1758:1758] ,mux_2level_size50_5_sram_blwl_outb[1758:1758] ,mux_2level_size50_5_configbus0[1758:1758], mux_2level_size50_5_configbus1[1758:1758] , mux_2level_size50_5_configbus0_b[1758:1758] ); -sram6T_blwl sram_blwl_1759_ (mux_2level_size50_5_sram_blwl_out[1759:1759] ,mux_2level_size50_5_sram_blwl_out[1759:1759] ,mux_2level_size50_5_sram_blwl_outb[1759:1759] ,mux_2level_size50_5_configbus0[1759:1759], mux_2level_size50_5_configbus1[1759:1759] , mux_2level_size50_5_configbus0_b[1759:1759] ); -sram6T_blwl sram_blwl_1760_ (mux_2level_size50_5_sram_blwl_out[1760:1760] ,mux_2level_size50_5_sram_blwl_out[1760:1760] ,mux_2level_size50_5_sram_blwl_outb[1760:1760] ,mux_2level_size50_5_configbus0[1760:1760], mux_2level_size50_5_configbus1[1760:1760] , mux_2level_size50_5_configbus0_b[1760:1760] ); -sram6T_blwl sram_blwl_1761_ (mux_2level_size50_5_sram_blwl_out[1761:1761] ,mux_2level_size50_5_sram_blwl_out[1761:1761] ,mux_2level_size50_5_sram_blwl_outb[1761:1761] ,mux_2level_size50_5_configbus0[1761:1761], mux_2level_size50_5_configbus1[1761:1761] , mux_2level_size50_5_configbus0_b[1761:1761] ); -direct_interc direct_interc_170_ (mode_clb___clk_0_, fle_0___clk_0_ ); -wire [0:49] in_bus_mux_2level_size50_6_ ; -assign in_bus_mux_2level_size50_6_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_6_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_6_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_6_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_6_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_6_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_6_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_6_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_6_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_6_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_6_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_6_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_6_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_6_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_6_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_6_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_6_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_6_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_6_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_6_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_6_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_6_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_6_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_6_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_6_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_6_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_6_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_6_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_6_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_6_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_6_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_6_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_6_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_6_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_6_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_6_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_6_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_6_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_6_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_6_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_6_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_6_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_6_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_6_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_6_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_6_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_6_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_6_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_6_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_6_[49] = fle_9___out_0_ ; -wire [1762:1777] mux_2level_size50_6_configbus0; -wire [1762:1777] mux_2level_size50_6_configbus1; -wire [1762:1777] mux_2level_size50_6_sram_blwl_out ; -wire [1762:1777] mux_2level_size50_6_sram_blwl_outb ; -assign mux_2level_size50_6_configbus0[1762:1777] = sram_blwl_bl[1762:1777] ; -assign mux_2level_size50_6_configbus1[1762:1777] = sram_blwl_wl[1762:1777] ; -wire [1762:1777] mux_2level_size50_6_configbus0_b; -assign mux_2level_size50_6_configbus0_b[1762:1777] = sram_blwl_blb[1762:1777] ; -mux_2level_size50 mux_2level_size50_6_ (in_bus_mux_2level_size50_6_, fle_1___in_0_, mux_2level_size50_6_sram_blwl_out[1762:1777] , -mux_2level_size50_6_sram_blwl_outb[1762:1777] ); -//----- SRAM bits for MUX[6], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1762_ (mux_2level_size50_6_sram_blwl_out[1762:1762] ,mux_2level_size50_6_sram_blwl_out[1762:1762] ,mux_2level_size50_6_sram_blwl_outb[1762:1762] ,mux_2level_size50_6_configbus0[1762:1762], mux_2level_size50_6_configbus1[1762:1762] , mux_2level_size50_6_configbus0_b[1762:1762] ); -sram6T_blwl sram_blwl_1763_ (mux_2level_size50_6_sram_blwl_out[1763:1763] ,mux_2level_size50_6_sram_blwl_out[1763:1763] ,mux_2level_size50_6_sram_blwl_outb[1763:1763] ,mux_2level_size50_6_configbus0[1763:1763], mux_2level_size50_6_configbus1[1763:1763] , mux_2level_size50_6_configbus0_b[1763:1763] ); -sram6T_blwl sram_blwl_1764_ (mux_2level_size50_6_sram_blwl_out[1764:1764] ,mux_2level_size50_6_sram_blwl_out[1764:1764] ,mux_2level_size50_6_sram_blwl_outb[1764:1764] ,mux_2level_size50_6_configbus0[1764:1764], mux_2level_size50_6_configbus1[1764:1764] , mux_2level_size50_6_configbus0_b[1764:1764] ); -sram6T_blwl sram_blwl_1765_ (mux_2level_size50_6_sram_blwl_out[1765:1765] ,mux_2level_size50_6_sram_blwl_out[1765:1765] ,mux_2level_size50_6_sram_blwl_outb[1765:1765] ,mux_2level_size50_6_configbus0[1765:1765], mux_2level_size50_6_configbus1[1765:1765] , mux_2level_size50_6_configbus0_b[1765:1765] ); -sram6T_blwl sram_blwl_1766_ (mux_2level_size50_6_sram_blwl_out[1766:1766] ,mux_2level_size50_6_sram_blwl_out[1766:1766] ,mux_2level_size50_6_sram_blwl_outb[1766:1766] ,mux_2level_size50_6_configbus0[1766:1766], mux_2level_size50_6_configbus1[1766:1766] , mux_2level_size50_6_configbus0_b[1766:1766] ); -sram6T_blwl sram_blwl_1767_ (mux_2level_size50_6_sram_blwl_out[1767:1767] ,mux_2level_size50_6_sram_blwl_out[1767:1767] ,mux_2level_size50_6_sram_blwl_outb[1767:1767] ,mux_2level_size50_6_configbus0[1767:1767], mux_2level_size50_6_configbus1[1767:1767] , mux_2level_size50_6_configbus0_b[1767:1767] ); -sram6T_blwl sram_blwl_1768_ (mux_2level_size50_6_sram_blwl_out[1768:1768] ,mux_2level_size50_6_sram_blwl_out[1768:1768] ,mux_2level_size50_6_sram_blwl_outb[1768:1768] ,mux_2level_size50_6_configbus0[1768:1768], mux_2level_size50_6_configbus1[1768:1768] , mux_2level_size50_6_configbus0_b[1768:1768] ); -sram6T_blwl sram_blwl_1769_ (mux_2level_size50_6_sram_blwl_out[1769:1769] ,mux_2level_size50_6_sram_blwl_out[1769:1769] ,mux_2level_size50_6_sram_blwl_outb[1769:1769] ,mux_2level_size50_6_configbus0[1769:1769], mux_2level_size50_6_configbus1[1769:1769] , mux_2level_size50_6_configbus0_b[1769:1769] ); -sram6T_blwl sram_blwl_1770_ (mux_2level_size50_6_sram_blwl_out[1770:1770] ,mux_2level_size50_6_sram_blwl_out[1770:1770] ,mux_2level_size50_6_sram_blwl_outb[1770:1770] ,mux_2level_size50_6_configbus0[1770:1770], mux_2level_size50_6_configbus1[1770:1770] , mux_2level_size50_6_configbus0_b[1770:1770] ); -sram6T_blwl sram_blwl_1771_ (mux_2level_size50_6_sram_blwl_out[1771:1771] ,mux_2level_size50_6_sram_blwl_out[1771:1771] ,mux_2level_size50_6_sram_blwl_outb[1771:1771] ,mux_2level_size50_6_configbus0[1771:1771], mux_2level_size50_6_configbus1[1771:1771] , mux_2level_size50_6_configbus0_b[1771:1771] ); -sram6T_blwl sram_blwl_1772_ (mux_2level_size50_6_sram_blwl_out[1772:1772] ,mux_2level_size50_6_sram_blwl_out[1772:1772] ,mux_2level_size50_6_sram_blwl_outb[1772:1772] ,mux_2level_size50_6_configbus0[1772:1772], mux_2level_size50_6_configbus1[1772:1772] , mux_2level_size50_6_configbus0_b[1772:1772] ); -sram6T_blwl sram_blwl_1773_ (mux_2level_size50_6_sram_blwl_out[1773:1773] ,mux_2level_size50_6_sram_blwl_out[1773:1773] ,mux_2level_size50_6_sram_blwl_outb[1773:1773] ,mux_2level_size50_6_configbus0[1773:1773], mux_2level_size50_6_configbus1[1773:1773] , mux_2level_size50_6_configbus0_b[1773:1773] ); -sram6T_blwl sram_blwl_1774_ (mux_2level_size50_6_sram_blwl_out[1774:1774] ,mux_2level_size50_6_sram_blwl_out[1774:1774] ,mux_2level_size50_6_sram_blwl_outb[1774:1774] ,mux_2level_size50_6_configbus0[1774:1774], mux_2level_size50_6_configbus1[1774:1774] , mux_2level_size50_6_configbus0_b[1774:1774] ); -sram6T_blwl sram_blwl_1775_ (mux_2level_size50_6_sram_blwl_out[1775:1775] ,mux_2level_size50_6_sram_blwl_out[1775:1775] ,mux_2level_size50_6_sram_blwl_outb[1775:1775] ,mux_2level_size50_6_configbus0[1775:1775], mux_2level_size50_6_configbus1[1775:1775] , mux_2level_size50_6_configbus0_b[1775:1775] ); -sram6T_blwl sram_blwl_1776_ (mux_2level_size50_6_sram_blwl_out[1776:1776] ,mux_2level_size50_6_sram_blwl_out[1776:1776] ,mux_2level_size50_6_sram_blwl_outb[1776:1776] ,mux_2level_size50_6_configbus0[1776:1776], mux_2level_size50_6_configbus1[1776:1776] , mux_2level_size50_6_configbus0_b[1776:1776] ); -sram6T_blwl sram_blwl_1777_ (mux_2level_size50_6_sram_blwl_out[1777:1777] ,mux_2level_size50_6_sram_blwl_out[1777:1777] ,mux_2level_size50_6_sram_blwl_outb[1777:1777] ,mux_2level_size50_6_configbus0[1777:1777], mux_2level_size50_6_configbus1[1777:1777] , mux_2level_size50_6_configbus0_b[1777:1777] ); -wire [0:49] in_bus_mux_2level_size50_7_ ; -assign in_bus_mux_2level_size50_7_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_7_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_7_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_7_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_7_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_7_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_7_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_7_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_7_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_7_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_7_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_7_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_7_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_7_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_7_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_7_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_7_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_7_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_7_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_7_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_7_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_7_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_7_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_7_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_7_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_7_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_7_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_7_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_7_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_7_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_7_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_7_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_7_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_7_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_7_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_7_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_7_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_7_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_7_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_7_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_7_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_7_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_7_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_7_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_7_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_7_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_7_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_7_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_7_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_7_[49] = fle_9___out_0_ ; -wire [1778:1793] mux_2level_size50_7_configbus0; -wire [1778:1793] mux_2level_size50_7_configbus1; -wire [1778:1793] mux_2level_size50_7_sram_blwl_out ; -wire [1778:1793] mux_2level_size50_7_sram_blwl_outb ; -assign mux_2level_size50_7_configbus0[1778:1793] = sram_blwl_bl[1778:1793] ; -assign mux_2level_size50_7_configbus1[1778:1793] = sram_blwl_wl[1778:1793] ; -wire [1778:1793] mux_2level_size50_7_configbus0_b; -assign mux_2level_size50_7_configbus0_b[1778:1793] = sram_blwl_blb[1778:1793] ; -mux_2level_size50 mux_2level_size50_7_ (in_bus_mux_2level_size50_7_, fle_1___in_1_, mux_2level_size50_7_sram_blwl_out[1778:1793] , -mux_2level_size50_7_sram_blwl_outb[1778:1793] ); -//----- SRAM bits for MUX[7], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1778_ (mux_2level_size50_7_sram_blwl_out[1778:1778] ,mux_2level_size50_7_sram_blwl_out[1778:1778] ,mux_2level_size50_7_sram_blwl_outb[1778:1778] ,mux_2level_size50_7_configbus0[1778:1778], mux_2level_size50_7_configbus1[1778:1778] , mux_2level_size50_7_configbus0_b[1778:1778] ); -sram6T_blwl sram_blwl_1779_ (mux_2level_size50_7_sram_blwl_out[1779:1779] ,mux_2level_size50_7_sram_blwl_out[1779:1779] ,mux_2level_size50_7_sram_blwl_outb[1779:1779] ,mux_2level_size50_7_configbus0[1779:1779], mux_2level_size50_7_configbus1[1779:1779] , mux_2level_size50_7_configbus0_b[1779:1779] ); -sram6T_blwl sram_blwl_1780_ (mux_2level_size50_7_sram_blwl_out[1780:1780] ,mux_2level_size50_7_sram_blwl_out[1780:1780] ,mux_2level_size50_7_sram_blwl_outb[1780:1780] ,mux_2level_size50_7_configbus0[1780:1780], mux_2level_size50_7_configbus1[1780:1780] , mux_2level_size50_7_configbus0_b[1780:1780] ); -sram6T_blwl sram_blwl_1781_ (mux_2level_size50_7_sram_blwl_out[1781:1781] ,mux_2level_size50_7_sram_blwl_out[1781:1781] ,mux_2level_size50_7_sram_blwl_outb[1781:1781] ,mux_2level_size50_7_configbus0[1781:1781], mux_2level_size50_7_configbus1[1781:1781] , mux_2level_size50_7_configbus0_b[1781:1781] ); -sram6T_blwl sram_blwl_1782_ (mux_2level_size50_7_sram_blwl_out[1782:1782] ,mux_2level_size50_7_sram_blwl_out[1782:1782] ,mux_2level_size50_7_sram_blwl_outb[1782:1782] ,mux_2level_size50_7_configbus0[1782:1782], mux_2level_size50_7_configbus1[1782:1782] , mux_2level_size50_7_configbus0_b[1782:1782] ); -sram6T_blwl sram_blwl_1783_ (mux_2level_size50_7_sram_blwl_out[1783:1783] ,mux_2level_size50_7_sram_blwl_out[1783:1783] ,mux_2level_size50_7_sram_blwl_outb[1783:1783] ,mux_2level_size50_7_configbus0[1783:1783], mux_2level_size50_7_configbus1[1783:1783] , mux_2level_size50_7_configbus0_b[1783:1783] ); -sram6T_blwl sram_blwl_1784_ (mux_2level_size50_7_sram_blwl_out[1784:1784] ,mux_2level_size50_7_sram_blwl_out[1784:1784] ,mux_2level_size50_7_sram_blwl_outb[1784:1784] ,mux_2level_size50_7_configbus0[1784:1784], mux_2level_size50_7_configbus1[1784:1784] , mux_2level_size50_7_configbus0_b[1784:1784] ); -sram6T_blwl sram_blwl_1785_ (mux_2level_size50_7_sram_blwl_out[1785:1785] ,mux_2level_size50_7_sram_blwl_out[1785:1785] ,mux_2level_size50_7_sram_blwl_outb[1785:1785] ,mux_2level_size50_7_configbus0[1785:1785], mux_2level_size50_7_configbus1[1785:1785] , mux_2level_size50_7_configbus0_b[1785:1785] ); -sram6T_blwl sram_blwl_1786_ (mux_2level_size50_7_sram_blwl_out[1786:1786] ,mux_2level_size50_7_sram_blwl_out[1786:1786] ,mux_2level_size50_7_sram_blwl_outb[1786:1786] ,mux_2level_size50_7_configbus0[1786:1786], mux_2level_size50_7_configbus1[1786:1786] , mux_2level_size50_7_configbus0_b[1786:1786] ); -sram6T_blwl sram_blwl_1787_ (mux_2level_size50_7_sram_blwl_out[1787:1787] ,mux_2level_size50_7_sram_blwl_out[1787:1787] ,mux_2level_size50_7_sram_blwl_outb[1787:1787] ,mux_2level_size50_7_configbus0[1787:1787], mux_2level_size50_7_configbus1[1787:1787] , mux_2level_size50_7_configbus0_b[1787:1787] ); -sram6T_blwl sram_blwl_1788_ (mux_2level_size50_7_sram_blwl_out[1788:1788] ,mux_2level_size50_7_sram_blwl_out[1788:1788] ,mux_2level_size50_7_sram_blwl_outb[1788:1788] ,mux_2level_size50_7_configbus0[1788:1788], mux_2level_size50_7_configbus1[1788:1788] , mux_2level_size50_7_configbus0_b[1788:1788] ); -sram6T_blwl sram_blwl_1789_ (mux_2level_size50_7_sram_blwl_out[1789:1789] ,mux_2level_size50_7_sram_blwl_out[1789:1789] ,mux_2level_size50_7_sram_blwl_outb[1789:1789] ,mux_2level_size50_7_configbus0[1789:1789], mux_2level_size50_7_configbus1[1789:1789] , mux_2level_size50_7_configbus0_b[1789:1789] ); -sram6T_blwl sram_blwl_1790_ (mux_2level_size50_7_sram_blwl_out[1790:1790] ,mux_2level_size50_7_sram_blwl_out[1790:1790] ,mux_2level_size50_7_sram_blwl_outb[1790:1790] ,mux_2level_size50_7_configbus0[1790:1790], mux_2level_size50_7_configbus1[1790:1790] , mux_2level_size50_7_configbus0_b[1790:1790] ); -sram6T_blwl sram_blwl_1791_ (mux_2level_size50_7_sram_blwl_out[1791:1791] ,mux_2level_size50_7_sram_blwl_out[1791:1791] ,mux_2level_size50_7_sram_blwl_outb[1791:1791] ,mux_2level_size50_7_configbus0[1791:1791], mux_2level_size50_7_configbus1[1791:1791] , mux_2level_size50_7_configbus0_b[1791:1791] ); -sram6T_blwl sram_blwl_1792_ (mux_2level_size50_7_sram_blwl_out[1792:1792] ,mux_2level_size50_7_sram_blwl_out[1792:1792] ,mux_2level_size50_7_sram_blwl_outb[1792:1792] ,mux_2level_size50_7_configbus0[1792:1792], mux_2level_size50_7_configbus1[1792:1792] , mux_2level_size50_7_configbus0_b[1792:1792] ); -sram6T_blwl sram_blwl_1793_ (mux_2level_size50_7_sram_blwl_out[1793:1793] ,mux_2level_size50_7_sram_blwl_out[1793:1793] ,mux_2level_size50_7_sram_blwl_outb[1793:1793] ,mux_2level_size50_7_configbus0[1793:1793], mux_2level_size50_7_configbus1[1793:1793] , mux_2level_size50_7_configbus0_b[1793:1793] ); -wire [0:49] in_bus_mux_2level_size50_8_ ; -assign in_bus_mux_2level_size50_8_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_8_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_8_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_8_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_8_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_8_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_8_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_8_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_8_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_8_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_8_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_8_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_8_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_8_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_8_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_8_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_8_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_8_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_8_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_8_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_8_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_8_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_8_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_8_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_8_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_8_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_8_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_8_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_8_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_8_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_8_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_8_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_8_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_8_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_8_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_8_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_8_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_8_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_8_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_8_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_8_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_8_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_8_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_8_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_8_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_8_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_8_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_8_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_8_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_8_[49] = fle_9___out_0_ ; -wire [1794:1809] mux_2level_size50_8_configbus0; -wire [1794:1809] mux_2level_size50_8_configbus1; -wire [1794:1809] mux_2level_size50_8_sram_blwl_out ; -wire [1794:1809] mux_2level_size50_8_sram_blwl_outb ; -assign mux_2level_size50_8_configbus0[1794:1809] = sram_blwl_bl[1794:1809] ; -assign mux_2level_size50_8_configbus1[1794:1809] = sram_blwl_wl[1794:1809] ; -wire [1794:1809] mux_2level_size50_8_configbus0_b; -assign mux_2level_size50_8_configbus0_b[1794:1809] = sram_blwl_blb[1794:1809] ; -mux_2level_size50 mux_2level_size50_8_ (in_bus_mux_2level_size50_8_, fle_1___in_2_, mux_2level_size50_8_sram_blwl_out[1794:1809] , -mux_2level_size50_8_sram_blwl_outb[1794:1809] ); -//----- SRAM bits for MUX[8], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1794_ (mux_2level_size50_8_sram_blwl_out[1794:1794] ,mux_2level_size50_8_sram_blwl_out[1794:1794] ,mux_2level_size50_8_sram_blwl_outb[1794:1794] ,mux_2level_size50_8_configbus0[1794:1794], mux_2level_size50_8_configbus1[1794:1794] , mux_2level_size50_8_configbus0_b[1794:1794] ); -sram6T_blwl sram_blwl_1795_ (mux_2level_size50_8_sram_blwl_out[1795:1795] ,mux_2level_size50_8_sram_blwl_out[1795:1795] ,mux_2level_size50_8_sram_blwl_outb[1795:1795] ,mux_2level_size50_8_configbus0[1795:1795], mux_2level_size50_8_configbus1[1795:1795] , mux_2level_size50_8_configbus0_b[1795:1795] ); -sram6T_blwl sram_blwl_1796_ (mux_2level_size50_8_sram_blwl_out[1796:1796] ,mux_2level_size50_8_sram_blwl_out[1796:1796] ,mux_2level_size50_8_sram_blwl_outb[1796:1796] ,mux_2level_size50_8_configbus0[1796:1796], mux_2level_size50_8_configbus1[1796:1796] , mux_2level_size50_8_configbus0_b[1796:1796] ); -sram6T_blwl sram_blwl_1797_ (mux_2level_size50_8_sram_blwl_out[1797:1797] ,mux_2level_size50_8_sram_blwl_out[1797:1797] ,mux_2level_size50_8_sram_blwl_outb[1797:1797] ,mux_2level_size50_8_configbus0[1797:1797], mux_2level_size50_8_configbus1[1797:1797] , mux_2level_size50_8_configbus0_b[1797:1797] ); -sram6T_blwl sram_blwl_1798_ (mux_2level_size50_8_sram_blwl_out[1798:1798] ,mux_2level_size50_8_sram_blwl_out[1798:1798] ,mux_2level_size50_8_sram_blwl_outb[1798:1798] ,mux_2level_size50_8_configbus0[1798:1798], mux_2level_size50_8_configbus1[1798:1798] , mux_2level_size50_8_configbus0_b[1798:1798] ); -sram6T_blwl sram_blwl_1799_ (mux_2level_size50_8_sram_blwl_out[1799:1799] ,mux_2level_size50_8_sram_blwl_out[1799:1799] ,mux_2level_size50_8_sram_blwl_outb[1799:1799] ,mux_2level_size50_8_configbus0[1799:1799], mux_2level_size50_8_configbus1[1799:1799] , mux_2level_size50_8_configbus0_b[1799:1799] ); -sram6T_blwl sram_blwl_1800_ (mux_2level_size50_8_sram_blwl_out[1800:1800] ,mux_2level_size50_8_sram_blwl_out[1800:1800] ,mux_2level_size50_8_sram_blwl_outb[1800:1800] ,mux_2level_size50_8_configbus0[1800:1800], mux_2level_size50_8_configbus1[1800:1800] , mux_2level_size50_8_configbus0_b[1800:1800] ); -sram6T_blwl sram_blwl_1801_ (mux_2level_size50_8_sram_blwl_out[1801:1801] ,mux_2level_size50_8_sram_blwl_out[1801:1801] ,mux_2level_size50_8_sram_blwl_outb[1801:1801] ,mux_2level_size50_8_configbus0[1801:1801], mux_2level_size50_8_configbus1[1801:1801] , mux_2level_size50_8_configbus0_b[1801:1801] ); -sram6T_blwl sram_blwl_1802_ (mux_2level_size50_8_sram_blwl_out[1802:1802] ,mux_2level_size50_8_sram_blwl_out[1802:1802] ,mux_2level_size50_8_sram_blwl_outb[1802:1802] ,mux_2level_size50_8_configbus0[1802:1802], mux_2level_size50_8_configbus1[1802:1802] , mux_2level_size50_8_configbus0_b[1802:1802] ); -sram6T_blwl sram_blwl_1803_ (mux_2level_size50_8_sram_blwl_out[1803:1803] ,mux_2level_size50_8_sram_blwl_out[1803:1803] ,mux_2level_size50_8_sram_blwl_outb[1803:1803] ,mux_2level_size50_8_configbus0[1803:1803], mux_2level_size50_8_configbus1[1803:1803] , mux_2level_size50_8_configbus0_b[1803:1803] ); -sram6T_blwl sram_blwl_1804_ (mux_2level_size50_8_sram_blwl_out[1804:1804] ,mux_2level_size50_8_sram_blwl_out[1804:1804] ,mux_2level_size50_8_sram_blwl_outb[1804:1804] ,mux_2level_size50_8_configbus0[1804:1804], mux_2level_size50_8_configbus1[1804:1804] , mux_2level_size50_8_configbus0_b[1804:1804] ); -sram6T_blwl sram_blwl_1805_ (mux_2level_size50_8_sram_blwl_out[1805:1805] ,mux_2level_size50_8_sram_blwl_out[1805:1805] ,mux_2level_size50_8_sram_blwl_outb[1805:1805] ,mux_2level_size50_8_configbus0[1805:1805], mux_2level_size50_8_configbus1[1805:1805] , mux_2level_size50_8_configbus0_b[1805:1805] ); -sram6T_blwl sram_blwl_1806_ (mux_2level_size50_8_sram_blwl_out[1806:1806] ,mux_2level_size50_8_sram_blwl_out[1806:1806] ,mux_2level_size50_8_sram_blwl_outb[1806:1806] ,mux_2level_size50_8_configbus0[1806:1806], mux_2level_size50_8_configbus1[1806:1806] , mux_2level_size50_8_configbus0_b[1806:1806] ); -sram6T_blwl sram_blwl_1807_ (mux_2level_size50_8_sram_blwl_out[1807:1807] ,mux_2level_size50_8_sram_blwl_out[1807:1807] ,mux_2level_size50_8_sram_blwl_outb[1807:1807] ,mux_2level_size50_8_configbus0[1807:1807], mux_2level_size50_8_configbus1[1807:1807] , mux_2level_size50_8_configbus0_b[1807:1807] ); -sram6T_blwl sram_blwl_1808_ (mux_2level_size50_8_sram_blwl_out[1808:1808] ,mux_2level_size50_8_sram_blwl_out[1808:1808] ,mux_2level_size50_8_sram_blwl_outb[1808:1808] ,mux_2level_size50_8_configbus0[1808:1808], mux_2level_size50_8_configbus1[1808:1808] , mux_2level_size50_8_configbus0_b[1808:1808] ); -sram6T_blwl sram_blwl_1809_ (mux_2level_size50_8_sram_blwl_out[1809:1809] ,mux_2level_size50_8_sram_blwl_out[1809:1809] ,mux_2level_size50_8_sram_blwl_outb[1809:1809] ,mux_2level_size50_8_configbus0[1809:1809], mux_2level_size50_8_configbus1[1809:1809] , mux_2level_size50_8_configbus0_b[1809:1809] ); -wire [0:49] in_bus_mux_2level_size50_9_ ; -assign in_bus_mux_2level_size50_9_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_9_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_9_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_9_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_9_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_9_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_9_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_9_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_9_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_9_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_9_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_9_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_9_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_9_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_9_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_9_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_9_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_9_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_9_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_9_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_9_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_9_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_9_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_9_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_9_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_9_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_9_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_9_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_9_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_9_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_9_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_9_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_9_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_9_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_9_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_9_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_9_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_9_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_9_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_9_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_9_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_9_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_9_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_9_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_9_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_9_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_9_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_9_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_9_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_9_[49] = fle_9___out_0_ ; -wire [1810:1825] mux_2level_size50_9_configbus0; -wire [1810:1825] mux_2level_size50_9_configbus1; -wire [1810:1825] mux_2level_size50_9_sram_blwl_out ; -wire [1810:1825] mux_2level_size50_9_sram_blwl_outb ; -assign mux_2level_size50_9_configbus0[1810:1825] = sram_blwl_bl[1810:1825] ; -assign mux_2level_size50_9_configbus1[1810:1825] = sram_blwl_wl[1810:1825] ; -wire [1810:1825] mux_2level_size50_9_configbus0_b; -assign mux_2level_size50_9_configbus0_b[1810:1825] = sram_blwl_blb[1810:1825] ; -mux_2level_size50 mux_2level_size50_9_ (in_bus_mux_2level_size50_9_, fle_1___in_3_, mux_2level_size50_9_sram_blwl_out[1810:1825] , -mux_2level_size50_9_sram_blwl_outb[1810:1825] ); -//----- SRAM bits for MUX[9], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1810_ (mux_2level_size50_9_sram_blwl_out[1810:1810] ,mux_2level_size50_9_sram_blwl_out[1810:1810] ,mux_2level_size50_9_sram_blwl_outb[1810:1810] ,mux_2level_size50_9_configbus0[1810:1810], mux_2level_size50_9_configbus1[1810:1810] , mux_2level_size50_9_configbus0_b[1810:1810] ); -sram6T_blwl sram_blwl_1811_ (mux_2level_size50_9_sram_blwl_out[1811:1811] ,mux_2level_size50_9_sram_blwl_out[1811:1811] ,mux_2level_size50_9_sram_blwl_outb[1811:1811] ,mux_2level_size50_9_configbus0[1811:1811], mux_2level_size50_9_configbus1[1811:1811] , mux_2level_size50_9_configbus0_b[1811:1811] ); -sram6T_blwl sram_blwl_1812_ (mux_2level_size50_9_sram_blwl_out[1812:1812] ,mux_2level_size50_9_sram_blwl_out[1812:1812] ,mux_2level_size50_9_sram_blwl_outb[1812:1812] ,mux_2level_size50_9_configbus0[1812:1812], mux_2level_size50_9_configbus1[1812:1812] , mux_2level_size50_9_configbus0_b[1812:1812] ); -sram6T_blwl sram_blwl_1813_ (mux_2level_size50_9_sram_blwl_out[1813:1813] ,mux_2level_size50_9_sram_blwl_out[1813:1813] ,mux_2level_size50_9_sram_blwl_outb[1813:1813] ,mux_2level_size50_9_configbus0[1813:1813], mux_2level_size50_9_configbus1[1813:1813] , mux_2level_size50_9_configbus0_b[1813:1813] ); -sram6T_blwl sram_blwl_1814_ (mux_2level_size50_9_sram_blwl_out[1814:1814] ,mux_2level_size50_9_sram_blwl_out[1814:1814] ,mux_2level_size50_9_sram_blwl_outb[1814:1814] ,mux_2level_size50_9_configbus0[1814:1814], mux_2level_size50_9_configbus1[1814:1814] , mux_2level_size50_9_configbus0_b[1814:1814] ); -sram6T_blwl sram_blwl_1815_ (mux_2level_size50_9_sram_blwl_out[1815:1815] ,mux_2level_size50_9_sram_blwl_out[1815:1815] ,mux_2level_size50_9_sram_blwl_outb[1815:1815] ,mux_2level_size50_9_configbus0[1815:1815], mux_2level_size50_9_configbus1[1815:1815] , mux_2level_size50_9_configbus0_b[1815:1815] ); -sram6T_blwl sram_blwl_1816_ (mux_2level_size50_9_sram_blwl_out[1816:1816] ,mux_2level_size50_9_sram_blwl_out[1816:1816] ,mux_2level_size50_9_sram_blwl_outb[1816:1816] ,mux_2level_size50_9_configbus0[1816:1816], mux_2level_size50_9_configbus1[1816:1816] , mux_2level_size50_9_configbus0_b[1816:1816] ); -sram6T_blwl sram_blwl_1817_ (mux_2level_size50_9_sram_blwl_out[1817:1817] ,mux_2level_size50_9_sram_blwl_out[1817:1817] ,mux_2level_size50_9_sram_blwl_outb[1817:1817] ,mux_2level_size50_9_configbus0[1817:1817], mux_2level_size50_9_configbus1[1817:1817] , mux_2level_size50_9_configbus0_b[1817:1817] ); -sram6T_blwl sram_blwl_1818_ (mux_2level_size50_9_sram_blwl_out[1818:1818] ,mux_2level_size50_9_sram_blwl_out[1818:1818] ,mux_2level_size50_9_sram_blwl_outb[1818:1818] ,mux_2level_size50_9_configbus0[1818:1818], mux_2level_size50_9_configbus1[1818:1818] , mux_2level_size50_9_configbus0_b[1818:1818] ); -sram6T_blwl sram_blwl_1819_ (mux_2level_size50_9_sram_blwl_out[1819:1819] ,mux_2level_size50_9_sram_blwl_out[1819:1819] ,mux_2level_size50_9_sram_blwl_outb[1819:1819] ,mux_2level_size50_9_configbus0[1819:1819], mux_2level_size50_9_configbus1[1819:1819] , mux_2level_size50_9_configbus0_b[1819:1819] ); -sram6T_blwl sram_blwl_1820_ (mux_2level_size50_9_sram_blwl_out[1820:1820] ,mux_2level_size50_9_sram_blwl_out[1820:1820] ,mux_2level_size50_9_sram_blwl_outb[1820:1820] ,mux_2level_size50_9_configbus0[1820:1820], mux_2level_size50_9_configbus1[1820:1820] , mux_2level_size50_9_configbus0_b[1820:1820] ); -sram6T_blwl sram_blwl_1821_ (mux_2level_size50_9_sram_blwl_out[1821:1821] ,mux_2level_size50_9_sram_blwl_out[1821:1821] ,mux_2level_size50_9_sram_blwl_outb[1821:1821] ,mux_2level_size50_9_configbus0[1821:1821], mux_2level_size50_9_configbus1[1821:1821] , mux_2level_size50_9_configbus0_b[1821:1821] ); -sram6T_blwl sram_blwl_1822_ (mux_2level_size50_9_sram_blwl_out[1822:1822] ,mux_2level_size50_9_sram_blwl_out[1822:1822] ,mux_2level_size50_9_sram_blwl_outb[1822:1822] ,mux_2level_size50_9_configbus0[1822:1822], mux_2level_size50_9_configbus1[1822:1822] , mux_2level_size50_9_configbus0_b[1822:1822] ); -sram6T_blwl sram_blwl_1823_ (mux_2level_size50_9_sram_blwl_out[1823:1823] ,mux_2level_size50_9_sram_blwl_out[1823:1823] ,mux_2level_size50_9_sram_blwl_outb[1823:1823] ,mux_2level_size50_9_configbus0[1823:1823], mux_2level_size50_9_configbus1[1823:1823] , mux_2level_size50_9_configbus0_b[1823:1823] ); -sram6T_blwl sram_blwl_1824_ (mux_2level_size50_9_sram_blwl_out[1824:1824] ,mux_2level_size50_9_sram_blwl_out[1824:1824] ,mux_2level_size50_9_sram_blwl_outb[1824:1824] ,mux_2level_size50_9_configbus0[1824:1824], mux_2level_size50_9_configbus1[1824:1824] , mux_2level_size50_9_configbus0_b[1824:1824] ); -sram6T_blwl sram_blwl_1825_ (mux_2level_size50_9_sram_blwl_out[1825:1825] ,mux_2level_size50_9_sram_blwl_out[1825:1825] ,mux_2level_size50_9_sram_blwl_outb[1825:1825] ,mux_2level_size50_9_configbus0[1825:1825], mux_2level_size50_9_configbus1[1825:1825] , mux_2level_size50_9_configbus0_b[1825:1825] ); -wire [0:49] in_bus_mux_2level_size50_10_ ; -assign in_bus_mux_2level_size50_10_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_10_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_10_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_10_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_10_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_10_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_10_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_10_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_10_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_10_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_10_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_10_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_10_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_10_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_10_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_10_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_10_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_10_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_10_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_10_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_10_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_10_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_10_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_10_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_10_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_10_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_10_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_10_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_10_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_10_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_10_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_10_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_10_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_10_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_10_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_10_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_10_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_10_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_10_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_10_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_10_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_10_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_10_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_10_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_10_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_10_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_10_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_10_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_10_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_10_[49] = fle_9___out_0_ ; -wire [1826:1841] mux_2level_size50_10_configbus0; -wire [1826:1841] mux_2level_size50_10_configbus1; -wire [1826:1841] mux_2level_size50_10_sram_blwl_out ; -wire [1826:1841] mux_2level_size50_10_sram_blwl_outb ; -assign mux_2level_size50_10_configbus0[1826:1841] = sram_blwl_bl[1826:1841] ; -assign mux_2level_size50_10_configbus1[1826:1841] = sram_blwl_wl[1826:1841] ; -wire [1826:1841] mux_2level_size50_10_configbus0_b; -assign mux_2level_size50_10_configbus0_b[1826:1841] = sram_blwl_blb[1826:1841] ; -mux_2level_size50 mux_2level_size50_10_ (in_bus_mux_2level_size50_10_, fle_1___in_4_, mux_2level_size50_10_sram_blwl_out[1826:1841] , -mux_2level_size50_10_sram_blwl_outb[1826:1841] ); -//----- SRAM bits for MUX[10], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1826_ (mux_2level_size50_10_sram_blwl_out[1826:1826] ,mux_2level_size50_10_sram_blwl_out[1826:1826] ,mux_2level_size50_10_sram_blwl_outb[1826:1826] ,mux_2level_size50_10_configbus0[1826:1826], mux_2level_size50_10_configbus1[1826:1826] , mux_2level_size50_10_configbus0_b[1826:1826] ); -sram6T_blwl sram_blwl_1827_ (mux_2level_size50_10_sram_blwl_out[1827:1827] ,mux_2level_size50_10_sram_blwl_out[1827:1827] ,mux_2level_size50_10_sram_blwl_outb[1827:1827] ,mux_2level_size50_10_configbus0[1827:1827], mux_2level_size50_10_configbus1[1827:1827] , mux_2level_size50_10_configbus0_b[1827:1827] ); -sram6T_blwl sram_blwl_1828_ (mux_2level_size50_10_sram_blwl_out[1828:1828] ,mux_2level_size50_10_sram_blwl_out[1828:1828] ,mux_2level_size50_10_sram_blwl_outb[1828:1828] ,mux_2level_size50_10_configbus0[1828:1828], mux_2level_size50_10_configbus1[1828:1828] , mux_2level_size50_10_configbus0_b[1828:1828] ); -sram6T_blwl sram_blwl_1829_ (mux_2level_size50_10_sram_blwl_out[1829:1829] ,mux_2level_size50_10_sram_blwl_out[1829:1829] ,mux_2level_size50_10_sram_blwl_outb[1829:1829] ,mux_2level_size50_10_configbus0[1829:1829], mux_2level_size50_10_configbus1[1829:1829] , mux_2level_size50_10_configbus0_b[1829:1829] ); -sram6T_blwl sram_blwl_1830_ (mux_2level_size50_10_sram_blwl_out[1830:1830] ,mux_2level_size50_10_sram_blwl_out[1830:1830] ,mux_2level_size50_10_sram_blwl_outb[1830:1830] ,mux_2level_size50_10_configbus0[1830:1830], mux_2level_size50_10_configbus1[1830:1830] , mux_2level_size50_10_configbus0_b[1830:1830] ); -sram6T_blwl sram_blwl_1831_ (mux_2level_size50_10_sram_blwl_out[1831:1831] ,mux_2level_size50_10_sram_blwl_out[1831:1831] ,mux_2level_size50_10_sram_blwl_outb[1831:1831] ,mux_2level_size50_10_configbus0[1831:1831], mux_2level_size50_10_configbus1[1831:1831] , mux_2level_size50_10_configbus0_b[1831:1831] ); -sram6T_blwl sram_blwl_1832_ (mux_2level_size50_10_sram_blwl_out[1832:1832] ,mux_2level_size50_10_sram_blwl_out[1832:1832] ,mux_2level_size50_10_sram_blwl_outb[1832:1832] ,mux_2level_size50_10_configbus0[1832:1832], mux_2level_size50_10_configbus1[1832:1832] , mux_2level_size50_10_configbus0_b[1832:1832] ); -sram6T_blwl sram_blwl_1833_ (mux_2level_size50_10_sram_blwl_out[1833:1833] ,mux_2level_size50_10_sram_blwl_out[1833:1833] ,mux_2level_size50_10_sram_blwl_outb[1833:1833] ,mux_2level_size50_10_configbus0[1833:1833], mux_2level_size50_10_configbus1[1833:1833] , mux_2level_size50_10_configbus0_b[1833:1833] ); -sram6T_blwl sram_blwl_1834_ (mux_2level_size50_10_sram_blwl_out[1834:1834] ,mux_2level_size50_10_sram_blwl_out[1834:1834] ,mux_2level_size50_10_sram_blwl_outb[1834:1834] ,mux_2level_size50_10_configbus0[1834:1834], mux_2level_size50_10_configbus1[1834:1834] , mux_2level_size50_10_configbus0_b[1834:1834] ); -sram6T_blwl sram_blwl_1835_ (mux_2level_size50_10_sram_blwl_out[1835:1835] ,mux_2level_size50_10_sram_blwl_out[1835:1835] ,mux_2level_size50_10_sram_blwl_outb[1835:1835] ,mux_2level_size50_10_configbus0[1835:1835], mux_2level_size50_10_configbus1[1835:1835] , mux_2level_size50_10_configbus0_b[1835:1835] ); -sram6T_blwl sram_blwl_1836_ (mux_2level_size50_10_sram_blwl_out[1836:1836] ,mux_2level_size50_10_sram_blwl_out[1836:1836] ,mux_2level_size50_10_sram_blwl_outb[1836:1836] ,mux_2level_size50_10_configbus0[1836:1836], mux_2level_size50_10_configbus1[1836:1836] , mux_2level_size50_10_configbus0_b[1836:1836] ); -sram6T_blwl sram_blwl_1837_ (mux_2level_size50_10_sram_blwl_out[1837:1837] ,mux_2level_size50_10_sram_blwl_out[1837:1837] ,mux_2level_size50_10_sram_blwl_outb[1837:1837] ,mux_2level_size50_10_configbus0[1837:1837], mux_2level_size50_10_configbus1[1837:1837] , mux_2level_size50_10_configbus0_b[1837:1837] ); -sram6T_blwl sram_blwl_1838_ (mux_2level_size50_10_sram_blwl_out[1838:1838] ,mux_2level_size50_10_sram_blwl_out[1838:1838] ,mux_2level_size50_10_sram_blwl_outb[1838:1838] ,mux_2level_size50_10_configbus0[1838:1838], mux_2level_size50_10_configbus1[1838:1838] , mux_2level_size50_10_configbus0_b[1838:1838] ); -sram6T_blwl sram_blwl_1839_ (mux_2level_size50_10_sram_blwl_out[1839:1839] ,mux_2level_size50_10_sram_blwl_out[1839:1839] ,mux_2level_size50_10_sram_blwl_outb[1839:1839] ,mux_2level_size50_10_configbus0[1839:1839], mux_2level_size50_10_configbus1[1839:1839] , mux_2level_size50_10_configbus0_b[1839:1839] ); -sram6T_blwl sram_blwl_1840_ (mux_2level_size50_10_sram_blwl_out[1840:1840] ,mux_2level_size50_10_sram_blwl_out[1840:1840] ,mux_2level_size50_10_sram_blwl_outb[1840:1840] ,mux_2level_size50_10_configbus0[1840:1840], mux_2level_size50_10_configbus1[1840:1840] , mux_2level_size50_10_configbus0_b[1840:1840] ); -sram6T_blwl sram_blwl_1841_ (mux_2level_size50_10_sram_blwl_out[1841:1841] ,mux_2level_size50_10_sram_blwl_out[1841:1841] ,mux_2level_size50_10_sram_blwl_outb[1841:1841] ,mux_2level_size50_10_configbus0[1841:1841], mux_2level_size50_10_configbus1[1841:1841] , mux_2level_size50_10_configbus0_b[1841:1841] ); -wire [0:49] in_bus_mux_2level_size50_11_ ; -assign in_bus_mux_2level_size50_11_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_11_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_11_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_11_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_11_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_11_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_11_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_11_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_11_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_11_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_11_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_11_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_11_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_11_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_11_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_11_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_11_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_11_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_11_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_11_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_11_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_11_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_11_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_11_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_11_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_11_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_11_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_11_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_11_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_11_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_11_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_11_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_11_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_11_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_11_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_11_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_11_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_11_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_11_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_11_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_11_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_11_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_11_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_11_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_11_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_11_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_11_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_11_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_11_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_11_[49] = fle_9___out_0_ ; -wire [1842:1857] mux_2level_size50_11_configbus0; -wire [1842:1857] mux_2level_size50_11_configbus1; -wire [1842:1857] mux_2level_size50_11_sram_blwl_out ; -wire [1842:1857] mux_2level_size50_11_sram_blwl_outb ; -assign mux_2level_size50_11_configbus0[1842:1857] = sram_blwl_bl[1842:1857] ; -assign mux_2level_size50_11_configbus1[1842:1857] = sram_blwl_wl[1842:1857] ; -wire [1842:1857] mux_2level_size50_11_configbus0_b; -assign mux_2level_size50_11_configbus0_b[1842:1857] = sram_blwl_blb[1842:1857] ; -mux_2level_size50 mux_2level_size50_11_ (in_bus_mux_2level_size50_11_, fle_1___in_5_, mux_2level_size50_11_sram_blwl_out[1842:1857] , -mux_2level_size50_11_sram_blwl_outb[1842:1857] ); -//----- SRAM bits for MUX[11], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1842_ (mux_2level_size50_11_sram_blwl_out[1842:1842] ,mux_2level_size50_11_sram_blwl_out[1842:1842] ,mux_2level_size50_11_sram_blwl_outb[1842:1842] ,mux_2level_size50_11_configbus0[1842:1842], mux_2level_size50_11_configbus1[1842:1842] , mux_2level_size50_11_configbus0_b[1842:1842] ); -sram6T_blwl sram_blwl_1843_ (mux_2level_size50_11_sram_blwl_out[1843:1843] ,mux_2level_size50_11_sram_blwl_out[1843:1843] ,mux_2level_size50_11_sram_blwl_outb[1843:1843] ,mux_2level_size50_11_configbus0[1843:1843], mux_2level_size50_11_configbus1[1843:1843] , mux_2level_size50_11_configbus0_b[1843:1843] ); -sram6T_blwl sram_blwl_1844_ (mux_2level_size50_11_sram_blwl_out[1844:1844] ,mux_2level_size50_11_sram_blwl_out[1844:1844] ,mux_2level_size50_11_sram_blwl_outb[1844:1844] ,mux_2level_size50_11_configbus0[1844:1844], mux_2level_size50_11_configbus1[1844:1844] , mux_2level_size50_11_configbus0_b[1844:1844] ); -sram6T_blwl sram_blwl_1845_ (mux_2level_size50_11_sram_blwl_out[1845:1845] ,mux_2level_size50_11_sram_blwl_out[1845:1845] ,mux_2level_size50_11_sram_blwl_outb[1845:1845] ,mux_2level_size50_11_configbus0[1845:1845], mux_2level_size50_11_configbus1[1845:1845] , mux_2level_size50_11_configbus0_b[1845:1845] ); -sram6T_blwl sram_blwl_1846_ (mux_2level_size50_11_sram_blwl_out[1846:1846] ,mux_2level_size50_11_sram_blwl_out[1846:1846] ,mux_2level_size50_11_sram_blwl_outb[1846:1846] ,mux_2level_size50_11_configbus0[1846:1846], mux_2level_size50_11_configbus1[1846:1846] , mux_2level_size50_11_configbus0_b[1846:1846] ); -sram6T_blwl sram_blwl_1847_ (mux_2level_size50_11_sram_blwl_out[1847:1847] ,mux_2level_size50_11_sram_blwl_out[1847:1847] ,mux_2level_size50_11_sram_blwl_outb[1847:1847] ,mux_2level_size50_11_configbus0[1847:1847], mux_2level_size50_11_configbus1[1847:1847] , mux_2level_size50_11_configbus0_b[1847:1847] ); -sram6T_blwl sram_blwl_1848_ (mux_2level_size50_11_sram_blwl_out[1848:1848] ,mux_2level_size50_11_sram_blwl_out[1848:1848] ,mux_2level_size50_11_sram_blwl_outb[1848:1848] ,mux_2level_size50_11_configbus0[1848:1848], mux_2level_size50_11_configbus1[1848:1848] , mux_2level_size50_11_configbus0_b[1848:1848] ); -sram6T_blwl sram_blwl_1849_ (mux_2level_size50_11_sram_blwl_out[1849:1849] ,mux_2level_size50_11_sram_blwl_out[1849:1849] ,mux_2level_size50_11_sram_blwl_outb[1849:1849] ,mux_2level_size50_11_configbus0[1849:1849], mux_2level_size50_11_configbus1[1849:1849] , mux_2level_size50_11_configbus0_b[1849:1849] ); -sram6T_blwl sram_blwl_1850_ (mux_2level_size50_11_sram_blwl_out[1850:1850] ,mux_2level_size50_11_sram_blwl_out[1850:1850] ,mux_2level_size50_11_sram_blwl_outb[1850:1850] ,mux_2level_size50_11_configbus0[1850:1850], mux_2level_size50_11_configbus1[1850:1850] , mux_2level_size50_11_configbus0_b[1850:1850] ); -sram6T_blwl sram_blwl_1851_ (mux_2level_size50_11_sram_blwl_out[1851:1851] ,mux_2level_size50_11_sram_blwl_out[1851:1851] ,mux_2level_size50_11_sram_blwl_outb[1851:1851] ,mux_2level_size50_11_configbus0[1851:1851], mux_2level_size50_11_configbus1[1851:1851] , mux_2level_size50_11_configbus0_b[1851:1851] ); -sram6T_blwl sram_blwl_1852_ (mux_2level_size50_11_sram_blwl_out[1852:1852] ,mux_2level_size50_11_sram_blwl_out[1852:1852] ,mux_2level_size50_11_sram_blwl_outb[1852:1852] ,mux_2level_size50_11_configbus0[1852:1852], mux_2level_size50_11_configbus1[1852:1852] , mux_2level_size50_11_configbus0_b[1852:1852] ); -sram6T_blwl sram_blwl_1853_ (mux_2level_size50_11_sram_blwl_out[1853:1853] ,mux_2level_size50_11_sram_blwl_out[1853:1853] ,mux_2level_size50_11_sram_blwl_outb[1853:1853] ,mux_2level_size50_11_configbus0[1853:1853], mux_2level_size50_11_configbus1[1853:1853] , mux_2level_size50_11_configbus0_b[1853:1853] ); -sram6T_blwl sram_blwl_1854_ (mux_2level_size50_11_sram_blwl_out[1854:1854] ,mux_2level_size50_11_sram_blwl_out[1854:1854] ,mux_2level_size50_11_sram_blwl_outb[1854:1854] ,mux_2level_size50_11_configbus0[1854:1854], mux_2level_size50_11_configbus1[1854:1854] , mux_2level_size50_11_configbus0_b[1854:1854] ); -sram6T_blwl sram_blwl_1855_ (mux_2level_size50_11_sram_blwl_out[1855:1855] ,mux_2level_size50_11_sram_blwl_out[1855:1855] ,mux_2level_size50_11_sram_blwl_outb[1855:1855] ,mux_2level_size50_11_configbus0[1855:1855], mux_2level_size50_11_configbus1[1855:1855] , mux_2level_size50_11_configbus0_b[1855:1855] ); -sram6T_blwl sram_blwl_1856_ (mux_2level_size50_11_sram_blwl_out[1856:1856] ,mux_2level_size50_11_sram_blwl_out[1856:1856] ,mux_2level_size50_11_sram_blwl_outb[1856:1856] ,mux_2level_size50_11_configbus0[1856:1856], mux_2level_size50_11_configbus1[1856:1856] , mux_2level_size50_11_configbus0_b[1856:1856] ); -sram6T_blwl sram_blwl_1857_ (mux_2level_size50_11_sram_blwl_out[1857:1857] ,mux_2level_size50_11_sram_blwl_out[1857:1857] ,mux_2level_size50_11_sram_blwl_outb[1857:1857] ,mux_2level_size50_11_configbus0[1857:1857], mux_2level_size50_11_configbus1[1857:1857] , mux_2level_size50_11_configbus0_b[1857:1857] ); -direct_interc direct_interc_171_ (mode_clb___clk_0_, fle_1___clk_0_ ); -wire [0:49] in_bus_mux_2level_size50_12_ ; -assign in_bus_mux_2level_size50_12_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_12_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_12_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_12_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_12_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_12_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_12_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_12_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_12_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_12_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_12_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_12_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_12_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_12_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_12_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_12_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_12_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_12_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_12_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_12_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_12_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_12_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_12_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_12_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_12_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_12_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_12_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_12_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_12_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_12_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_12_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_12_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_12_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_12_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_12_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_12_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_12_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_12_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_12_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_12_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_12_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_12_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_12_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_12_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_12_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_12_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_12_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_12_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_12_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_12_[49] = fle_9___out_0_ ; -wire [1858:1873] mux_2level_size50_12_configbus0; -wire [1858:1873] mux_2level_size50_12_configbus1; -wire [1858:1873] mux_2level_size50_12_sram_blwl_out ; -wire [1858:1873] mux_2level_size50_12_sram_blwl_outb ; -assign mux_2level_size50_12_configbus0[1858:1873] = sram_blwl_bl[1858:1873] ; -assign mux_2level_size50_12_configbus1[1858:1873] = sram_blwl_wl[1858:1873] ; -wire [1858:1873] mux_2level_size50_12_configbus0_b; -assign mux_2level_size50_12_configbus0_b[1858:1873] = sram_blwl_blb[1858:1873] ; -mux_2level_size50 mux_2level_size50_12_ (in_bus_mux_2level_size50_12_, fle_2___in_0_, mux_2level_size50_12_sram_blwl_out[1858:1873] , -mux_2level_size50_12_sram_blwl_outb[1858:1873] ); -//----- SRAM bits for MUX[12], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1858_ (mux_2level_size50_12_sram_blwl_out[1858:1858] ,mux_2level_size50_12_sram_blwl_out[1858:1858] ,mux_2level_size50_12_sram_blwl_outb[1858:1858] ,mux_2level_size50_12_configbus0[1858:1858], mux_2level_size50_12_configbus1[1858:1858] , mux_2level_size50_12_configbus0_b[1858:1858] ); -sram6T_blwl sram_blwl_1859_ (mux_2level_size50_12_sram_blwl_out[1859:1859] ,mux_2level_size50_12_sram_blwl_out[1859:1859] ,mux_2level_size50_12_sram_blwl_outb[1859:1859] ,mux_2level_size50_12_configbus0[1859:1859], mux_2level_size50_12_configbus1[1859:1859] , mux_2level_size50_12_configbus0_b[1859:1859] ); -sram6T_blwl sram_blwl_1860_ (mux_2level_size50_12_sram_blwl_out[1860:1860] ,mux_2level_size50_12_sram_blwl_out[1860:1860] ,mux_2level_size50_12_sram_blwl_outb[1860:1860] ,mux_2level_size50_12_configbus0[1860:1860], mux_2level_size50_12_configbus1[1860:1860] , mux_2level_size50_12_configbus0_b[1860:1860] ); -sram6T_blwl sram_blwl_1861_ (mux_2level_size50_12_sram_blwl_out[1861:1861] ,mux_2level_size50_12_sram_blwl_out[1861:1861] ,mux_2level_size50_12_sram_blwl_outb[1861:1861] ,mux_2level_size50_12_configbus0[1861:1861], mux_2level_size50_12_configbus1[1861:1861] , mux_2level_size50_12_configbus0_b[1861:1861] ); -sram6T_blwl sram_blwl_1862_ (mux_2level_size50_12_sram_blwl_out[1862:1862] ,mux_2level_size50_12_sram_blwl_out[1862:1862] ,mux_2level_size50_12_sram_blwl_outb[1862:1862] ,mux_2level_size50_12_configbus0[1862:1862], mux_2level_size50_12_configbus1[1862:1862] , mux_2level_size50_12_configbus0_b[1862:1862] ); -sram6T_blwl sram_blwl_1863_ (mux_2level_size50_12_sram_blwl_out[1863:1863] ,mux_2level_size50_12_sram_blwl_out[1863:1863] ,mux_2level_size50_12_sram_blwl_outb[1863:1863] ,mux_2level_size50_12_configbus0[1863:1863], mux_2level_size50_12_configbus1[1863:1863] , mux_2level_size50_12_configbus0_b[1863:1863] ); -sram6T_blwl sram_blwl_1864_ (mux_2level_size50_12_sram_blwl_out[1864:1864] ,mux_2level_size50_12_sram_blwl_out[1864:1864] ,mux_2level_size50_12_sram_blwl_outb[1864:1864] ,mux_2level_size50_12_configbus0[1864:1864], mux_2level_size50_12_configbus1[1864:1864] , mux_2level_size50_12_configbus0_b[1864:1864] ); -sram6T_blwl sram_blwl_1865_ (mux_2level_size50_12_sram_blwl_out[1865:1865] ,mux_2level_size50_12_sram_blwl_out[1865:1865] ,mux_2level_size50_12_sram_blwl_outb[1865:1865] ,mux_2level_size50_12_configbus0[1865:1865], mux_2level_size50_12_configbus1[1865:1865] , mux_2level_size50_12_configbus0_b[1865:1865] ); -sram6T_blwl sram_blwl_1866_ (mux_2level_size50_12_sram_blwl_out[1866:1866] ,mux_2level_size50_12_sram_blwl_out[1866:1866] ,mux_2level_size50_12_sram_blwl_outb[1866:1866] ,mux_2level_size50_12_configbus0[1866:1866], mux_2level_size50_12_configbus1[1866:1866] , mux_2level_size50_12_configbus0_b[1866:1866] ); -sram6T_blwl sram_blwl_1867_ (mux_2level_size50_12_sram_blwl_out[1867:1867] ,mux_2level_size50_12_sram_blwl_out[1867:1867] ,mux_2level_size50_12_sram_blwl_outb[1867:1867] ,mux_2level_size50_12_configbus0[1867:1867], mux_2level_size50_12_configbus1[1867:1867] , mux_2level_size50_12_configbus0_b[1867:1867] ); -sram6T_blwl sram_blwl_1868_ (mux_2level_size50_12_sram_blwl_out[1868:1868] ,mux_2level_size50_12_sram_blwl_out[1868:1868] ,mux_2level_size50_12_sram_blwl_outb[1868:1868] ,mux_2level_size50_12_configbus0[1868:1868], mux_2level_size50_12_configbus1[1868:1868] , mux_2level_size50_12_configbus0_b[1868:1868] ); -sram6T_blwl sram_blwl_1869_ (mux_2level_size50_12_sram_blwl_out[1869:1869] ,mux_2level_size50_12_sram_blwl_out[1869:1869] ,mux_2level_size50_12_sram_blwl_outb[1869:1869] ,mux_2level_size50_12_configbus0[1869:1869], mux_2level_size50_12_configbus1[1869:1869] , mux_2level_size50_12_configbus0_b[1869:1869] ); -sram6T_blwl sram_blwl_1870_ (mux_2level_size50_12_sram_blwl_out[1870:1870] ,mux_2level_size50_12_sram_blwl_out[1870:1870] ,mux_2level_size50_12_sram_blwl_outb[1870:1870] ,mux_2level_size50_12_configbus0[1870:1870], mux_2level_size50_12_configbus1[1870:1870] , mux_2level_size50_12_configbus0_b[1870:1870] ); -sram6T_blwl sram_blwl_1871_ (mux_2level_size50_12_sram_blwl_out[1871:1871] ,mux_2level_size50_12_sram_blwl_out[1871:1871] ,mux_2level_size50_12_sram_blwl_outb[1871:1871] ,mux_2level_size50_12_configbus0[1871:1871], mux_2level_size50_12_configbus1[1871:1871] , mux_2level_size50_12_configbus0_b[1871:1871] ); -sram6T_blwl sram_blwl_1872_ (mux_2level_size50_12_sram_blwl_out[1872:1872] ,mux_2level_size50_12_sram_blwl_out[1872:1872] ,mux_2level_size50_12_sram_blwl_outb[1872:1872] ,mux_2level_size50_12_configbus0[1872:1872], mux_2level_size50_12_configbus1[1872:1872] , mux_2level_size50_12_configbus0_b[1872:1872] ); -sram6T_blwl sram_blwl_1873_ (mux_2level_size50_12_sram_blwl_out[1873:1873] ,mux_2level_size50_12_sram_blwl_out[1873:1873] ,mux_2level_size50_12_sram_blwl_outb[1873:1873] ,mux_2level_size50_12_configbus0[1873:1873], mux_2level_size50_12_configbus1[1873:1873] , mux_2level_size50_12_configbus0_b[1873:1873] ); -wire [0:49] in_bus_mux_2level_size50_13_ ; -assign in_bus_mux_2level_size50_13_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_13_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_13_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_13_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_13_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_13_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_13_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_13_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_13_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_13_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_13_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_13_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_13_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_13_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_13_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_13_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_13_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_13_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_13_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_13_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_13_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_13_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_13_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_13_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_13_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_13_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_13_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_13_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_13_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_13_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_13_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_13_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_13_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_13_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_13_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_13_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_13_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_13_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_13_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_13_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_13_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_13_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_13_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_13_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_13_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_13_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_13_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_13_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_13_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_13_[49] = fle_9___out_0_ ; -wire [1874:1889] mux_2level_size50_13_configbus0; -wire [1874:1889] mux_2level_size50_13_configbus1; -wire [1874:1889] mux_2level_size50_13_sram_blwl_out ; -wire [1874:1889] mux_2level_size50_13_sram_blwl_outb ; -assign mux_2level_size50_13_configbus0[1874:1889] = sram_blwl_bl[1874:1889] ; -assign mux_2level_size50_13_configbus1[1874:1889] = sram_blwl_wl[1874:1889] ; -wire [1874:1889] mux_2level_size50_13_configbus0_b; -assign mux_2level_size50_13_configbus0_b[1874:1889] = sram_blwl_blb[1874:1889] ; -mux_2level_size50 mux_2level_size50_13_ (in_bus_mux_2level_size50_13_, fle_2___in_1_, mux_2level_size50_13_sram_blwl_out[1874:1889] , -mux_2level_size50_13_sram_blwl_outb[1874:1889] ); -//----- SRAM bits for MUX[13], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1874_ (mux_2level_size50_13_sram_blwl_out[1874:1874] ,mux_2level_size50_13_sram_blwl_out[1874:1874] ,mux_2level_size50_13_sram_blwl_outb[1874:1874] ,mux_2level_size50_13_configbus0[1874:1874], mux_2level_size50_13_configbus1[1874:1874] , mux_2level_size50_13_configbus0_b[1874:1874] ); -sram6T_blwl sram_blwl_1875_ (mux_2level_size50_13_sram_blwl_out[1875:1875] ,mux_2level_size50_13_sram_blwl_out[1875:1875] ,mux_2level_size50_13_sram_blwl_outb[1875:1875] ,mux_2level_size50_13_configbus0[1875:1875], mux_2level_size50_13_configbus1[1875:1875] , mux_2level_size50_13_configbus0_b[1875:1875] ); -sram6T_blwl sram_blwl_1876_ (mux_2level_size50_13_sram_blwl_out[1876:1876] ,mux_2level_size50_13_sram_blwl_out[1876:1876] ,mux_2level_size50_13_sram_blwl_outb[1876:1876] ,mux_2level_size50_13_configbus0[1876:1876], mux_2level_size50_13_configbus1[1876:1876] , mux_2level_size50_13_configbus0_b[1876:1876] ); -sram6T_blwl sram_blwl_1877_ (mux_2level_size50_13_sram_blwl_out[1877:1877] ,mux_2level_size50_13_sram_blwl_out[1877:1877] ,mux_2level_size50_13_sram_blwl_outb[1877:1877] ,mux_2level_size50_13_configbus0[1877:1877], mux_2level_size50_13_configbus1[1877:1877] , mux_2level_size50_13_configbus0_b[1877:1877] ); -sram6T_blwl sram_blwl_1878_ (mux_2level_size50_13_sram_blwl_out[1878:1878] ,mux_2level_size50_13_sram_blwl_out[1878:1878] ,mux_2level_size50_13_sram_blwl_outb[1878:1878] ,mux_2level_size50_13_configbus0[1878:1878], mux_2level_size50_13_configbus1[1878:1878] , mux_2level_size50_13_configbus0_b[1878:1878] ); -sram6T_blwl sram_blwl_1879_ (mux_2level_size50_13_sram_blwl_out[1879:1879] ,mux_2level_size50_13_sram_blwl_out[1879:1879] ,mux_2level_size50_13_sram_blwl_outb[1879:1879] ,mux_2level_size50_13_configbus0[1879:1879], mux_2level_size50_13_configbus1[1879:1879] , mux_2level_size50_13_configbus0_b[1879:1879] ); -sram6T_blwl sram_blwl_1880_ (mux_2level_size50_13_sram_blwl_out[1880:1880] ,mux_2level_size50_13_sram_blwl_out[1880:1880] ,mux_2level_size50_13_sram_blwl_outb[1880:1880] ,mux_2level_size50_13_configbus0[1880:1880], mux_2level_size50_13_configbus1[1880:1880] , mux_2level_size50_13_configbus0_b[1880:1880] ); -sram6T_blwl sram_blwl_1881_ (mux_2level_size50_13_sram_blwl_out[1881:1881] ,mux_2level_size50_13_sram_blwl_out[1881:1881] ,mux_2level_size50_13_sram_blwl_outb[1881:1881] ,mux_2level_size50_13_configbus0[1881:1881], mux_2level_size50_13_configbus1[1881:1881] , mux_2level_size50_13_configbus0_b[1881:1881] ); -sram6T_blwl sram_blwl_1882_ (mux_2level_size50_13_sram_blwl_out[1882:1882] ,mux_2level_size50_13_sram_blwl_out[1882:1882] ,mux_2level_size50_13_sram_blwl_outb[1882:1882] ,mux_2level_size50_13_configbus0[1882:1882], mux_2level_size50_13_configbus1[1882:1882] , mux_2level_size50_13_configbus0_b[1882:1882] ); -sram6T_blwl sram_blwl_1883_ (mux_2level_size50_13_sram_blwl_out[1883:1883] ,mux_2level_size50_13_sram_blwl_out[1883:1883] ,mux_2level_size50_13_sram_blwl_outb[1883:1883] ,mux_2level_size50_13_configbus0[1883:1883], mux_2level_size50_13_configbus1[1883:1883] , mux_2level_size50_13_configbus0_b[1883:1883] ); -sram6T_blwl sram_blwl_1884_ (mux_2level_size50_13_sram_blwl_out[1884:1884] ,mux_2level_size50_13_sram_blwl_out[1884:1884] ,mux_2level_size50_13_sram_blwl_outb[1884:1884] ,mux_2level_size50_13_configbus0[1884:1884], mux_2level_size50_13_configbus1[1884:1884] , mux_2level_size50_13_configbus0_b[1884:1884] ); -sram6T_blwl sram_blwl_1885_ (mux_2level_size50_13_sram_blwl_out[1885:1885] ,mux_2level_size50_13_sram_blwl_out[1885:1885] ,mux_2level_size50_13_sram_blwl_outb[1885:1885] ,mux_2level_size50_13_configbus0[1885:1885], mux_2level_size50_13_configbus1[1885:1885] , mux_2level_size50_13_configbus0_b[1885:1885] ); -sram6T_blwl sram_blwl_1886_ (mux_2level_size50_13_sram_blwl_out[1886:1886] ,mux_2level_size50_13_sram_blwl_out[1886:1886] ,mux_2level_size50_13_sram_blwl_outb[1886:1886] ,mux_2level_size50_13_configbus0[1886:1886], mux_2level_size50_13_configbus1[1886:1886] , mux_2level_size50_13_configbus0_b[1886:1886] ); -sram6T_blwl sram_blwl_1887_ (mux_2level_size50_13_sram_blwl_out[1887:1887] ,mux_2level_size50_13_sram_blwl_out[1887:1887] ,mux_2level_size50_13_sram_blwl_outb[1887:1887] ,mux_2level_size50_13_configbus0[1887:1887], mux_2level_size50_13_configbus1[1887:1887] , mux_2level_size50_13_configbus0_b[1887:1887] ); -sram6T_blwl sram_blwl_1888_ (mux_2level_size50_13_sram_blwl_out[1888:1888] ,mux_2level_size50_13_sram_blwl_out[1888:1888] ,mux_2level_size50_13_sram_blwl_outb[1888:1888] ,mux_2level_size50_13_configbus0[1888:1888], mux_2level_size50_13_configbus1[1888:1888] , mux_2level_size50_13_configbus0_b[1888:1888] ); -sram6T_blwl sram_blwl_1889_ (mux_2level_size50_13_sram_blwl_out[1889:1889] ,mux_2level_size50_13_sram_blwl_out[1889:1889] ,mux_2level_size50_13_sram_blwl_outb[1889:1889] ,mux_2level_size50_13_configbus0[1889:1889], mux_2level_size50_13_configbus1[1889:1889] , mux_2level_size50_13_configbus0_b[1889:1889] ); -wire [0:49] in_bus_mux_2level_size50_14_ ; -assign in_bus_mux_2level_size50_14_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_14_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_14_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_14_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_14_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_14_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_14_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_14_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_14_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_14_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_14_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_14_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_14_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_14_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_14_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_14_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_14_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_14_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_14_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_14_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_14_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_14_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_14_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_14_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_14_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_14_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_14_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_14_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_14_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_14_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_14_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_14_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_14_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_14_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_14_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_14_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_14_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_14_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_14_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_14_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_14_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_14_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_14_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_14_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_14_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_14_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_14_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_14_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_14_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_14_[49] = fle_9___out_0_ ; -wire [1890:1905] mux_2level_size50_14_configbus0; -wire [1890:1905] mux_2level_size50_14_configbus1; -wire [1890:1905] mux_2level_size50_14_sram_blwl_out ; -wire [1890:1905] mux_2level_size50_14_sram_blwl_outb ; -assign mux_2level_size50_14_configbus0[1890:1905] = sram_blwl_bl[1890:1905] ; -assign mux_2level_size50_14_configbus1[1890:1905] = sram_blwl_wl[1890:1905] ; -wire [1890:1905] mux_2level_size50_14_configbus0_b; -assign mux_2level_size50_14_configbus0_b[1890:1905] = sram_blwl_blb[1890:1905] ; -mux_2level_size50 mux_2level_size50_14_ (in_bus_mux_2level_size50_14_, fle_2___in_2_, mux_2level_size50_14_sram_blwl_out[1890:1905] , -mux_2level_size50_14_sram_blwl_outb[1890:1905] ); -//----- SRAM bits for MUX[14], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1890_ (mux_2level_size50_14_sram_blwl_out[1890:1890] ,mux_2level_size50_14_sram_blwl_out[1890:1890] ,mux_2level_size50_14_sram_blwl_outb[1890:1890] ,mux_2level_size50_14_configbus0[1890:1890], mux_2level_size50_14_configbus1[1890:1890] , mux_2level_size50_14_configbus0_b[1890:1890] ); -sram6T_blwl sram_blwl_1891_ (mux_2level_size50_14_sram_blwl_out[1891:1891] ,mux_2level_size50_14_sram_blwl_out[1891:1891] ,mux_2level_size50_14_sram_blwl_outb[1891:1891] ,mux_2level_size50_14_configbus0[1891:1891], mux_2level_size50_14_configbus1[1891:1891] , mux_2level_size50_14_configbus0_b[1891:1891] ); -sram6T_blwl sram_blwl_1892_ (mux_2level_size50_14_sram_blwl_out[1892:1892] ,mux_2level_size50_14_sram_blwl_out[1892:1892] ,mux_2level_size50_14_sram_blwl_outb[1892:1892] ,mux_2level_size50_14_configbus0[1892:1892], mux_2level_size50_14_configbus1[1892:1892] , mux_2level_size50_14_configbus0_b[1892:1892] ); -sram6T_blwl sram_blwl_1893_ (mux_2level_size50_14_sram_blwl_out[1893:1893] ,mux_2level_size50_14_sram_blwl_out[1893:1893] ,mux_2level_size50_14_sram_blwl_outb[1893:1893] ,mux_2level_size50_14_configbus0[1893:1893], mux_2level_size50_14_configbus1[1893:1893] , mux_2level_size50_14_configbus0_b[1893:1893] ); -sram6T_blwl sram_blwl_1894_ (mux_2level_size50_14_sram_blwl_out[1894:1894] ,mux_2level_size50_14_sram_blwl_out[1894:1894] ,mux_2level_size50_14_sram_blwl_outb[1894:1894] ,mux_2level_size50_14_configbus0[1894:1894], mux_2level_size50_14_configbus1[1894:1894] , mux_2level_size50_14_configbus0_b[1894:1894] ); -sram6T_blwl sram_blwl_1895_ (mux_2level_size50_14_sram_blwl_out[1895:1895] ,mux_2level_size50_14_sram_blwl_out[1895:1895] ,mux_2level_size50_14_sram_blwl_outb[1895:1895] ,mux_2level_size50_14_configbus0[1895:1895], mux_2level_size50_14_configbus1[1895:1895] , mux_2level_size50_14_configbus0_b[1895:1895] ); -sram6T_blwl sram_blwl_1896_ (mux_2level_size50_14_sram_blwl_out[1896:1896] ,mux_2level_size50_14_sram_blwl_out[1896:1896] ,mux_2level_size50_14_sram_blwl_outb[1896:1896] ,mux_2level_size50_14_configbus0[1896:1896], mux_2level_size50_14_configbus1[1896:1896] , mux_2level_size50_14_configbus0_b[1896:1896] ); -sram6T_blwl sram_blwl_1897_ (mux_2level_size50_14_sram_blwl_out[1897:1897] ,mux_2level_size50_14_sram_blwl_out[1897:1897] ,mux_2level_size50_14_sram_blwl_outb[1897:1897] ,mux_2level_size50_14_configbus0[1897:1897], mux_2level_size50_14_configbus1[1897:1897] , mux_2level_size50_14_configbus0_b[1897:1897] ); -sram6T_blwl sram_blwl_1898_ (mux_2level_size50_14_sram_blwl_out[1898:1898] ,mux_2level_size50_14_sram_blwl_out[1898:1898] ,mux_2level_size50_14_sram_blwl_outb[1898:1898] ,mux_2level_size50_14_configbus0[1898:1898], mux_2level_size50_14_configbus1[1898:1898] , mux_2level_size50_14_configbus0_b[1898:1898] ); -sram6T_blwl sram_blwl_1899_ (mux_2level_size50_14_sram_blwl_out[1899:1899] ,mux_2level_size50_14_sram_blwl_out[1899:1899] ,mux_2level_size50_14_sram_blwl_outb[1899:1899] ,mux_2level_size50_14_configbus0[1899:1899], mux_2level_size50_14_configbus1[1899:1899] , mux_2level_size50_14_configbus0_b[1899:1899] ); -sram6T_blwl sram_blwl_1900_ (mux_2level_size50_14_sram_blwl_out[1900:1900] ,mux_2level_size50_14_sram_blwl_out[1900:1900] ,mux_2level_size50_14_sram_blwl_outb[1900:1900] ,mux_2level_size50_14_configbus0[1900:1900], mux_2level_size50_14_configbus1[1900:1900] , mux_2level_size50_14_configbus0_b[1900:1900] ); -sram6T_blwl sram_blwl_1901_ (mux_2level_size50_14_sram_blwl_out[1901:1901] ,mux_2level_size50_14_sram_blwl_out[1901:1901] ,mux_2level_size50_14_sram_blwl_outb[1901:1901] ,mux_2level_size50_14_configbus0[1901:1901], mux_2level_size50_14_configbus1[1901:1901] , mux_2level_size50_14_configbus0_b[1901:1901] ); -sram6T_blwl sram_blwl_1902_ (mux_2level_size50_14_sram_blwl_out[1902:1902] ,mux_2level_size50_14_sram_blwl_out[1902:1902] ,mux_2level_size50_14_sram_blwl_outb[1902:1902] ,mux_2level_size50_14_configbus0[1902:1902], mux_2level_size50_14_configbus1[1902:1902] , mux_2level_size50_14_configbus0_b[1902:1902] ); -sram6T_blwl sram_blwl_1903_ (mux_2level_size50_14_sram_blwl_out[1903:1903] ,mux_2level_size50_14_sram_blwl_out[1903:1903] ,mux_2level_size50_14_sram_blwl_outb[1903:1903] ,mux_2level_size50_14_configbus0[1903:1903], mux_2level_size50_14_configbus1[1903:1903] , mux_2level_size50_14_configbus0_b[1903:1903] ); -sram6T_blwl sram_blwl_1904_ (mux_2level_size50_14_sram_blwl_out[1904:1904] ,mux_2level_size50_14_sram_blwl_out[1904:1904] ,mux_2level_size50_14_sram_blwl_outb[1904:1904] ,mux_2level_size50_14_configbus0[1904:1904], mux_2level_size50_14_configbus1[1904:1904] , mux_2level_size50_14_configbus0_b[1904:1904] ); -sram6T_blwl sram_blwl_1905_ (mux_2level_size50_14_sram_blwl_out[1905:1905] ,mux_2level_size50_14_sram_blwl_out[1905:1905] ,mux_2level_size50_14_sram_blwl_outb[1905:1905] ,mux_2level_size50_14_configbus0[1905:1905], mux_2level_size50_14_configbus1[1905:1905] , mux_2level_size50_14_configbus0_b[1905:1905] ); -wire [0:49] in_bus_mux_2level_size50_15_ ; -assign in_bus_mux_2level_size50_15_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_15_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_15_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_15_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_15_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_15_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_15_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_15_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_15_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_15_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_15_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_15_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_15_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_15_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_15_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_15_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_15_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_15_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_15_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_15_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_15_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_15_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_15_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_15_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_15_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_15_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_15_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_15_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_15_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_15_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_15_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_15_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_15_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_15_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_15_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_15_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_15_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_15_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_15_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_15_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_15_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_15_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_15_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_15_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_15_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_15_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_15_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_15_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_15_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_15_[49] = fle_9___out_0_ ; -wire [1906:1921] mux_2level_size50_15_configbus0; -wire [1906:1921] mux_2level_size50_15_configbus1; -wire [1906:1921] mux_2level_size50_15_sram_blwl_out ; -wire [1906:1921] mux_2level_size50_15_sram_blwl_outb ; -assign mux_2level_size50_15_configbus0[1906:1921] = sram_blwl_bl[1906:1921] ; -assign mux_2level_size50_15_configbus1[1906:1921] = sram_blwl_wl[1906:1921] ; -wire [1906:1921] mux_2level_size50_15_configbus0_b; -assign mux_2level_size50_15_configbus0_b[1906:1921] = sram_blwl_blb[1906:1921] ; -mux_2level_size50 mux_2level_size50_15_ (in_bus_mux_2level_size50_15_, fle_2___in_3_, mux_2level_size50_15_sram_blwl_out[1906:1921] , -mux_2level_size50_15_sram_blwl_outb[1906:1921] ); -//----- SRAM bits for MUX[15], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1906_ (mux_2level_size50_15_sram_blwl_out[1906:1906] ,mux_2level_size50_15_sram_blwl_out[1906:1906] ,mux_2level_size50_15_sram_blwl_outb[1906:1906] ,mux_2level_size50_15_configbus0[1906:1906], mux_2level_size50_15_configbus1[1906:1906] , mux_2level_size50_15_configbus0_b[1906:1906] ); -sram6T_blwl sram_blwl_1907_ (mux_2level_size50_15_sram_blwl_out[1907:1907] ,mux_2level_size50_15_sram_blwl_out[1907:1907] ,mux_2level_size50_15_sram_blwl_outb[1907:1907] ,mux_2level_size50_15_configbus0[1907:1907], mux_2level_size50_15_configbus1[1907:1907] , mux_2level_size50_15_configbus0_b[1907:1907] ); -sram6T_blwl sram_blwl_1908_ (mux_2level_size50_15_sram_blwl_out[1908:1908] ,mux_2level_size50_15_sram_blwl_out[1908:1908] ,mux_2level_size50_15_sram_blwl_outb[1908:1908] ,mux_2level_size50_15_configbus0[1908:1908], mux_2level_size50_15_configbus1[1908:1908] , mux_2level_size50_15_configbus0_b[1908:1908] ); -sram6T_blwl sram_blwl_1909_ (mux_2level_size50_15_sram_blwl_out[1909:1909] ,mux_2level_size50_15_sram_blwl_out[1909:1909] ,mux_2level_size50_15_sram_blwl_outb[1909:1909] ,mux_2level_size50_15_configbus0[1909:1909], mux_2level_size50_15_configbus1[1909:1909] , mux_2level_size50_15_configbus0_b[1909:1909] ); -sram6T_blwl sram_blwl_1910_ (mux_2level_size50_15_sram_blwl_out[1910:1910] ,mux_2level_size50_15_sram_blwl_out[1910:1910] ,mux_2level_size50_15_sram_blwl_outb[1910:1910] ,mux_2level_size50_15_configbus0[1910:1910], mux_2level_size50_15_configbus1[1910:1910] , mux_2level_size50_15_configbus0_b[1910:1910] ); -sram6T_blwl sram_blwl_1911_ (mux_2level_size50_15_sram_blwl_out[1911:1911] ,mux_2level_size50_15_sram_blwl_out[1911:1911] ,mux_2level_size50_15_sram_blwl_outb[1911:1911] ,mux_2level_size50_15_configbus0[1911:1911], mux_2level_size50_15_configbus1[1911:1911] , mux_2level_size50_15_configbus0_b[1911:1911] ); -sram6T_blwl sram_blwl_1912_ (mux_2level_size50_15_sram_blwl_out[1912:1912] ,mux_2level_size50_15_sram_blwl_out[1912:1912] ,mux_2level_size50_15_sram_blwl_outb[1912:1912] ,mux_2level_size50_15_configbus0[1912:1912], mux_2level_size50_15_configbus1[1912:1912] , mux_2level_size50_15_configbus0_b[1912:1912] ); -sram6T_blwl sram_blwl_1913_ (mux_2level_size50_15_sram_blwl_out[1913:1913] ,mux_2level_size50_15_sram_blwl_out[1913:1913] ,mux_2level_size50_15_sram_blwl_outb[1913:1913] ,mux_2level_size50_15_configbus0[1913:1913], mux_2level_size50_15_configbus1[1913:1913] , mux_2level_size50_15_configbus0_b[1913:1913] ); -sram6T_blwl sram_blwl_1914_ (mux_2level_size50_15_sram_blwl_out[1914:1914] ,mux_2level_size50_15_sram_blwl_out[1914:1914] ,mux_2level_size50_15_sram_blwl_outb[1914:1914] ,mux_2level_size50_15_configbus0[1914:1914], mux_2level_size50_15_configbus1[1914:1914] , mux_2level_size50_15_configbus0_b[1914:1914] ); -sram6T_blwl sram_blwl_1915_ (mux_2level_size50_15_sram_blwl_out[1915:1915] ,mux_2level_size50_15_sram_blwl_out[1915:1915] ,mux_2level_size50_15_sram_blwl_outb[1915:1915] ,mux_2level_size50_15_configbus0[1915:1915], mux_2level_size50_15_configbus1[1915:1915] , mux_2level_size50_15_configbus0_b[1915:1915] ); -sram6T_blwl sram_blwl_1916_ (mux_2level_size50_15_sram_blwl_out[1916:1916] ,mux_2level_size50_15_sram_blwl_out[1916:1916] ,mux_2level_size50_15_sram_blwl_outb[1916:1916] ,mux_2level_size50_15_configbus0[1916:1916], mux_2level_size50_15_configbus1[1916:1916] , mux_2level_size50_15_configbus0_b[1916:1916] ); -sram6T_blwl sram_blwl_1917_ (mux_2level_size50_15_sram_blwl_out[1917:1917] ,mux_2level_size50_15_sram_blwl_out[1917:1917] ,mux_2level_size50_15_sram_blwl_outb[1917:1917] ,mux_2level_size50_15_configbus0[1917:1917], mux_2level_size50_15_configbus1[1917:1917] , mux_2level_size50_15_configbus0_b[1917:1917] ); -sram6T_blwl sram_blwl_1918_ (mux_2level_size50_15_sram_blwl_out[1918:1918] ,mux_2level_size50_15_sram_blwl_out[1918:1918] ,mux_2level_size50_15_sram_blwl_outb[1918:1918] ,mux_2level_size50_15_configbus0[1918:1918], mux_2level_size50_15_configbus1[1918:1918] , mux_2level_size50_15_configbus0_b[1918:1918] ); -sram6T_blwl sram_blwl_1919_ (mux_2level_size50_15_sram_blwl_out[1919:1919] ,mux_2level_size50_15_sram_blwl_out[1919:1919] ,mux_2level_size50_15_sram_blwl_outb[1919:1919] ,mux_2level_size50_15_configbus0[1919:1919], mux_2level_size50_15_configbus1[1919:1919] , mux_2level_size50_15_configbus0_b[1919:1919] ); -sram6T_blwl sram_blwl_1920_ (mux_2level_size50_15_sram_blwl_out[1920:1920] ,mux_2level_size50_15_sram_blwl_out[1920:1920] ,mux_2level_size50_15_sram_blwl_outb[1920:1920] ,mux_2level_size50_15_configbus0[1920:1920], mux_2level_size50_15_configbus1[1920:1920] , mux_2level_size50_15_configbus0_b[1920:1920] ); -sram6T_blwl sram_blwl_1921_ (mux_2level_size50_15_sram_blwl_out[1921:1921] ,mux_2level_size50_15_sram_blwl_out[1921:1921] ,mux_2level_size50_15_sram_blwl_outb[1921:1921] ,mux_2level_size50_15_configbus0[1921:1921], mux_2level_size50_15_configbus1[1921:1921] , mux_2level_size50_15_configbus0_b[1921:1921] ); -wire [0:49] in_bus_mux_2level_size50_16_ ; -assign in_bus_mux_2level_size50_16_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_16_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_16_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_16_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_16_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_16_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_16_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_16_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_16_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_16_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_16_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_16_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_16_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_16_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_16_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_16_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_16_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_16_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_16_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_16_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_16_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_16_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_16_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_16_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_16_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_16_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_16_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_16_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_16_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_16_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_16_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_16_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_16_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_16_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_16_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_16_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_16_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_16_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_16_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_16_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_16_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_16_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_16_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_16_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_16_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_16_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_16_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_16_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_16_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_16_[49] = fle_9___out_0_ ; -wire [1922:1937] mux_2level_size50_16_configbus0; -wire [1922:1937] mux_2level_size50_16_configbus1; -wire [1922:1937] mux_2level_size50_16_sram_blwl_out ; -wire [1922:1937] mux_2level_size50_16_sram_blwl_outb ; -assign mux_2level_size50_16_configbus0[1922:1937] = sram_blwl_bl[1922:1937] ; -assign mux_2level_size50_16_configbus1[1922:1937] = sram_blwl_wl[1922:1937] ; -wire [1922:1937] mux_2level_size50_16_configbus0_b; -assign mux_2level_size50_16_configbus0_b[1922:1937] = sram_blwl_blb[1922:1937] ; -mux_2level_size50 mux_2level_size50_16_ (in_bus_mux_2level_size50_16_, fle_2___in_4_, mux_2level_size50_16_sram_blwl_out[1922:1937] , -mux_2level_size50_16_sram_blwl_outb[1922:1937] ); -//----- SRAM bits for MUX[16], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1922_ (mux_2level_size50_16_sram_blwl_out[1922:1922] ,mux_2level_size50_16_sram_blwl_out[1922:1922] ,mux_2level_size50_16_sram_blwl_outb[1922:1922] ,mux_2level_size50_16_configbus0[1922:1922], mux_2level_size50_16_configbus1[1922:1922] , mux_2level_size50_16_configbus0_b[1922:1922] ); -sram6T_blwl sram_blwl_1923_ (mux_2level_size50_16_sram_blwl_out[1923:1923] ,mux_2level_size50_16_sram_blwl_out[1923:1923] ,mux_2level_size50_16_sram_blwl_outb[1923:1923] ,mux_2level_size50_16_configbus0[1923:1923], mux_2level_size50_16_configbus1[1923:1923] , mux_2level_size50_16_configbus0_b[1923:1923] ); -sram6T_blwl sram_blwl_1924_ (mux_2level_size50_16_sram_blwl_out[1924:1924] ,mux_2level_size50_16_sram_blwl_out[1924:1924] ,mux_2level_size50_16_sram_blwl_outb[1924:1924] ,mux_2level_size50_16_configbus0[1924:1924], mux_2level_size50_16_configbus1[1924:1924] , mux_2level_size50_16_configbus0_b[1924:1924] ); -sram6T_blwl sram_blwl_1925_ (mux_2level_size50_16_sram_blwl_out[1925:1925] ,mux_2level_size50_16_sram_blwl_out[1925:1925] ,mux_2level_size50_16_sram_blwl_outb[1925:1925] ,mux_2level_size50_16_configbus0[1925:1925], mux_2level_size50_16_configbus1[1925:1925] , mux_2level_size50_16_configbus0_b[1925:1925] ); -sram6T_blwl sram_blwl_1926_ (mux_2level_size50_16_sram_blwl_out[1926:1926] ,mux_2level_size50_16_sram_blwl_out[1926:1926] ,mux_2level_size50_16_sram_blwl_outb[1926:1926] ,mux_2level_size50_16_configbus0[1926:1926], mux_2level_size50_16_configbus1[1926:1926] , mux_2level_size50_16_configbus0_b[1926:1926] ); -sram6T_blwl sram_blwl_1927_ (mux_2level_size50_16_sram_blwl_out[1927:1927] ,mux_2level_size50_16_sram_blwl_out[1927:1927] ,mux_2level_size50_16_sram_blwl_outb[1927:1927] ,mux_2level_size50_16_configbus0[1927:1927], mux_2level_size50_16_configbus1[1927:1927] , mux_2level_size50_16_configbus0_b[1927:1927] ); -sram6T_blwl sram_blwl_1928_ (mux_2level_size50_16_sram_blwl_out[1928:1928] ,mux_2level_size50_16_sram_blwl_out[1928:1928] ,mux_2level_size50_16_sram_blwl_outb[1928:1928] ,mux_2level_size50_16_configbus0[1928:1928], mux_2level_size50_16_configbus1[1928:1928] , mux_2level_size50_16_configbus0_b[1928:1928] ); -sram6T_blwl sram_blwl_1929_ (mux_2level_size50_16_sram_blwl_out[1929:1929] ,mux_2level_size50_16_sram_blwl_out[1929:1929] ,mux_2level_size50_16_sram_blwl_outb[1929:1929] ,mux_2level_size50_16_configbus0[1929:1929], mux_2level_size50_16_configbus1[1929:1929] , mux_2level_size50_16_configbus0_b[1929:1929] ); -sram6T_blwl sram_blwl_1930_ (mux_2level_size50_16_sram_blwl_out[1930:1930] ,mux_2level_size50_16_sram_blwl_out[1930:1930] ,mux_2level_size50_16_sram_blwl_outb[1930:1930] ,mux_2level_size50_16_configbus0[1930:1930], mux_2level_size50_16_configbus1[1930:1930] , mux_2level_size50_16_configbus0_b[1930:1930] ); -sram6T_blwl sram_blwl_1931_ (mux_2level_size50_16_sram_blwl_out[1931:1931] ,mux_2level_size50_16_sram_blwl_out[1931:1931] ,mux_2level_size50_16_sram_blwl_outb[1931:1931] ,mux_2level_size50_16_configbus0[1931:1931], mux_2level_size50_16_configbus1[1931:1931] , mux_2level_size50_16_configbus0_b[1931:1931] ); -sram6T_blwl sram_blwl_1932_ (mux_2level_size50_16_sram_blwl_out[1932:1932] ,mux_2level_size50_16_sram_blwl_out[1932:1932] ,mux_2level_size50_16_sram_blwl_outb[1932:1932] ,mux_2level_size50_16_configbus0[1932:1932], mux_2level_size50_16_configbus1[1932:1932] , mux_2level_size50_16_configbus0_b[1932:1932] ); -sram6T_blwl sram_blwl_1933_ (mux_2level_size50_16_sram_blwl_out[1933:1933] ,mux_2level_size50_16_sram_blwl_out[1933:1933] ,mux_2level_size50_16_sram_blwl_outb[1933:1933] ,mux_2level_size50_16_configbus0[1933:1933], mux_2level_size50_16_configbus1[1933:1933] , mux_2level_size50_16_configbus0_b[1933:1933] ); -sram6T_blwl sram_blwl_1934_ (mux_2level_size50_16_sram_blwl_out[1934:1934] ,mux_2level_size50_16_sram_blwl_out[1934:1934] ,mux_2level_size50_16_sram_blwl_outb[1934:1934] ,mux_2level_size50_16_configbus0[1934:1934], mux_2level_size50_16_configbus1[1934:1934] , mux_2level_size50_16_configbus0_b[1934:1934] ); -sram6T_blwl sram_blwl_1935_ (mux_2level_size50_16_sram_blwl_out[1935:1935] ,mux_2level_size50_16_sram_blwl_out[1935:1935] ,mux_2level_size50_16_sram_blwl_outb[1935:1935] ,mux_2level_size50_16_configbus0[1935:1935], mux_2level_size50_16_configbus1[1935:1935] , mux_2level_size50_16_configbus0_b[1935:1935] ); -sram6T_blwl sram_blwl_1936_ (mux_2level_size50_16_sram_blwl_out[1936:1936] ,mux_2level_size50_16_sram_blwl_out[1936:1936] ,mux_2level_size50_16_sram_blwl_outb[1936:1936] ,mux_2level_size50_16_configbus0[1936:1936], mux_2level_size50_16_configbus1[1936:1936] , mux_2level_size50_16_configbus0_b[1936:1936] ); -sram6T_blwl sram_blwl_1937_ (mux_2level_size50_16_sram_blwl_out[1937:1937] ,mux_2level_size50_16_sram_blwl_out[1937:1937] ,mux_2level_size50_16_sram_blwl_outb[1937:1937] ,mux_2level_size50_16_configbus0[1937:1937], mux_2level_size50_16_configbus1[1937:1937] , mux_2level_size50_16_configbus0_b[1937:1937] ); -wire [0:49] in_bus_mux_2level_size50_17_ ; -assign in_bus_mux_2level_size50_17_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_17_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_17_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_17_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_17_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_17_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_17_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_17_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_17_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_17_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_17_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_17_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_17_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_17_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_17_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_17_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_17_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_17_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_17_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_17_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_17_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_17_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_17_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_17_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_17_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_17_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_17_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_17_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_17_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_17_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_17_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_17_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_17_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_17_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_17_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_17_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_17_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_17_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_17_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_17_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_17_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_17_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_17_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_17_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_17_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_17_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_17_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_17_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_17_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_17_[49] = fle_9___out_0_ ; -wire [1938:1953] mux_2level_size50_17_configbus0; -wire [1938:1953] mux_2level_size50_17_configbus1; -wire [1938:1953] mux_2level_size50_17_sram_blwl_out ; -wire [1938:1953] mux_2level_size50_17_sram_blwl_outb ; -assign mux_2level_size50_17_configbus0[1938:1953] = sram_blwl_bl[1938:1953] ; -assign mux_2level_size50_17_configbus1[1938:1953] = sram_blwl_wl[1938:1953] ; -wire [1938:1953] mux_2level_size50_17_configbus0_b; -assign mux_2level_size50_17_configbus0_b[1938:1953] = sram_blwl_blb[1938:1953] ; -mux_2level_size50 mux_2level_size50_17_ (in_bus_mux_2level_size50_17_, fle_2___in_5_, mux_2level_size50_17_sram_blwl_out[1938:1953] , -mux_2level_size50_17_sram_blwl_outb[1938:1953] ); -//----- SRAM bits for MUX[17], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1938_ (mux_2level_size50_17_sram_blwl_out[1938:1938] ,mux_2level_size50_17_sram_blwl_out[1938:1938] ,mux_2level_size50_17_sram_blwl_outb[1938:1938] ,mux_2level_size50_17_configbus0[1938:1938], mux_2level_size50_17_configbus1[1938:1938] , mux_2level_size50_17_configbus0_b[1938:1938] ); -sram6T_blwl sram_blwl_1939_ (mux_2level_size50_17_sram_blwl_out[1939:1939] ,mux_2level_size50_17_sram_blwl_out[1939:1939] ,mux_2level_size50_17_sram_blwl_outb[1939:1939] ,mux_2level_size50_17_configbus0[1939:1939], mux_2level_size50_17_configbus1[1939:1939] , mux_2level_size50_17_configbus0_b[1939:1939] ); -sram6T_blwl sram_blwl_1940_ (mux_2level_size50_17_sram_blwl_out[1940:1940] ,mux_2level_size50_17_sram_blwl_out[1940:1940] ,mux_2level_size50_17_sram_blwl_outb[1940:1940] ,mux_2level_size50_17_configbus0[1940:1940], mux_2level_size50_17_configbus1[1940:1940] , mux_2level_size50_17_configbus0_b[1940:1940] ); -sram6T_blwl sram_blwl_1941_ (mux_2level_size50_17_sram_blwl_out[1941:1941] ,mux_2level_size50_17_sram_blwl_out[1941:1941] ,mux_2level_size50_17_sram_blwl_outb[1941:1941] ,mux_2level_size50_17_configbus0[1941:1941], mux_2level_size50_17_configbus1[1941:1941] , mux_2level_size50_17_configbus0_b[1941:1941] ); -sram6T_blwl sram_blwl_1942_ (mux_2level_size50_17_sram_blwl_out[1942:1942] ,mux_2level_size50_17_sram_blwl_out[1942:1942] ,mux_2level_size50_17_sram_blwl_outb[1942:1942] ,mux_2level_size50_17_configbus0[1942:1942], mux_2level_size50_17_configbus1[1942:1942] , mux_2level_size50_17_configbus0_b[1942:1942] ); -sram6T_blwl sram_blwl_1943_ (mux_2level_size50_17_sram_blwl_out[1943:1943] ,mux_2level_size50_17_sram_blwl_out[1943:1943] ,mux_2level_size50_17_sram_blwl_outb[1943:1943] ,mux_2level_size50_17_configbus0[1943:1943], mux_2level_size50_17_configbus1[1943:1943] , mux_2level_size50_17_configbus0_b[1943:1943] ); -sram6T_blwl sram_blwl_1944_ (mux_2level_size50_17_sram_blwl_out[1944:1944] ,mux_2level_size50_17_sram_blwl_out[1944:1944] ,mux_2level_size50_17_sram_blwl_outb[1944:1944] ,mux_2level_size50_17_configbus0[1944:1944], mux_2level_size50_17_configbus1[1944:1944] , mux_2level_size50_17_configbus0_b[1944:1944] ); -sram6T_blwl sram_blwl_1945_ (mux_2level_size50_17_sram_blwl_out[1945:1945] ,mux_2level_size50_17_sram_blwl_out[1945:1945] ,mux_2level_size50_17_sram_blwl_outb[1945:1945] ,mux_2level_size50_17_configbus0[1945:1945], mux_2level_size50_17_configbus1[1945:1945] , mux_2level_size50_17_configbus0_b[1945:1945] ); -sram6T_blwl sram_blwl_1946_ (mux_2level_size50_17_sram_blwl_out[1946:1946] ,mux_2level_size50_17_sram_blwl_out[1946:1946] ,mux_2level_size50_17_sram_blwl_outb[1946:1946] ,mux_2level_size50_17_configbus0[1946:1946], mux_2level_size50_17_configbus1[1946:1946] , mux_2level_size50_17_configbus0_b[1946:1946] ); -sram6T_blwl sram_blwl_1947_ (mux_2level_size50_17_sram_blwl_out[1947:1947] ,mux_2level_size50_17_sram_blwl_out[1947:1947] ,mux_2level_size50_17_sram_blwl_outb[1947:1947] ,mux_2level_size50_17_configbus0[1947:1947], mux_2level_size50_17_configbus1[1947:1947] , mux_2level_size50_17_configbus0_b[1947:1947] ); -sram6T_blwl sram_blwl_1948_ (mux_2level_size50_17_sram_blwl_out[1948:1948] ,mux_2level_size50_17_sram_blwl_out[1948:1948] ,mux_2level_size50_17_sram_blwl_outb[1948:1948] ,mux_2level_size50_17_configbus0[1948:1948], mux_2level_size50_17_configbus1[1948:1948] , mux_2level_size50_17_configbus0_b[1948:1948] ); -sram6T_blwl sram_blwl_1949_ (mux_2level_size50_17_sram_blwl_out[1949:1949] ,mux_2level_size50_17_sram_blwl_out[1949:1949] ,mux_2level_size50_17_sram_blwl_outb[1949:1949] ,mux_2level_size50_17_configbus0[1949:1949], mux_2level_size50_17_configbus1[1949:1949] , mux_2level_size50_17_configbus0_b[1949:1949] ); -sram6T_blwl sram_blwl_1950_ (mux_2level_size50_17_sram_blwl_out[1950:1950] ,mux_2level_size50_17_sram_blwl_out[1950:1950] ,mux_2level_size50_17_sram_blwl_outb[1950:1950] ,mux_2level_size50_17_configbus0[1950:1950], mux_2level_size50_17_configbus1[1950:1950] , mux_2level_size50_17_configbus0_b[1950:1950] ); -sram6T_blwl sram_blwl_1951_ (mux_2level_size50_17_sram_blwl_out[1951:1951] ,mux_2level_size50_17_sram_blwl_out[1951:1951] ,mux_2level_size50_17_sram_blwl_outb[1951:1951] ,mux_2level_size50_17_configbus0[1951:1951], mux_2level_size50_17_configbus1[1951:1951] , mux_2level_size50_17_configbus0_b[1951:1951] ); -sram6T_blwl sram_blwl_1952_ (mux_2level_size50_17_sram_blwl_out[1952:1952] ,mux_2level_size50_17_sram_blwl_out[1952:1952] ,mux_2level_size50_17_sram_blwl_outb[1952:1952] ,mux_2level_size50_17_configbus0[1952:1952], mux_2level_size50_17_configbus1[1952:1952] , mux_2level_size50_17_configbus0_b[1952:1952] ); -sram6T_blwl sram_blwl_1953_ (mux_2level_size50_17_sram_blwl_out[1953:1953] ,mux_2level_size50_17_sram_blwl_out[1953:1953] ,mux_2level_size50_17_sram_blwl_outb[1953:1953] ,mux_2level_size50_17_configbus0[1953:1953], mux_2level_size50_17_configbus1[1953:1953] , mux_2level_size50_17_configbus0_b[1953:1953] ); -direct_interc direct_interc_172_ (mode_clb___clk_0_, fle_2___clk_0_ ); -wire [0:49] in_bus_mux_2level_size50_18_ ; -assign in_bus_mux_2level_size50_18_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_18_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_18_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_18_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_18_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_18_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_18_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_18_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_18_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_18_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_18_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_18_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_18_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_18_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_18_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_18_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_18_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_18_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_18_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_18_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_18_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_18_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_18_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_18_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_18_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_18_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_18_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_18_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_18_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_18_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_18_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_18_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_18_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_18_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_18_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_18_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_18_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_18_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_18_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_18_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_18_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_18_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_18_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_18_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_18_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_18_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_18_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_18_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_18_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_18_[49] = fle_9___out_0_ ; -wire [1954:1969] mux_2level_size50_18_configbus0; -wire [1954:1969] mux_2level_size50_18_configbus1; -wire [1954:1969] mux_2level_size50_18_sram_blwl_out ; -wire [1954:1969] mux_2level_size50_18_sram_blwl_outb ; -assign mux_2level_size50_18_configbus0[1954:1969] = sram_blwl_bl[1954:1969] ; -assign mux_2level_size50_18_configbus1[1954:1969] = sram_blwl_wl[1954:1969] ; -wire [1954:1969] mux_2level_size50_18_configbus0_b; -assign mux_2level_size50_18_configbus0_b[1954:1969] = sram_blwl_blb[1954:1969] ; -mux_2level_size50 mux_2level_size50_18_ (in_bus_mux_2level_size50_18_, fle_3___in_0_, mux_2level_size50_18_sram_blwl_out[1954:1969] , -mux_2level_size50_18_sram_blwl_outb[1954:1969] ); -//----- SRAM bits for MUX[18], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1954_ (mux_2level_size50_18_sram_blwl_out[1954:1954] ,mux_2level_size50_18_sram_blwl_out[1954:1954] ,mux_2level_size50_18_sram_blwl_outb[1954:1954] ,mux_2level_size50_18_configbus0[1954:1954], mux_2level_size50_18_configbus1[1954:1954] , mux_2level_size50_18_configbus0_b[1954:1954] ); -sram6T_blwl sram_blwl_1955_ (mux_2level_size50_18_sram_blwl_out[1955:1955] ,mux_2level_size50_18_sram_blwl_out[1955:1955] ,mux_2level_size50_18_sram_blwl_outb[1955:1955] ,mux_2level_size50_18_configbus0[1955:1955], mux_2level_size50_18_configbus1[1955:1955] , mux_2level_size50_18_configbus0_b[1955:1955] ); -sram6T_blwl sram_blwl_1956_ (mux_2level_size50_18_sram_blwl_out[1956:1956] ,mux_2level_size50_18_sram_blwl_out[1956:1956] ,mux_2level_size50_18_sram_blwl_outb[1956:1956] ,mux_2level_size50_18_configbus0[1956:1956], mux_2level_size50_18_configbus1[1956:1956] , mux_2level_size50_18_configbus0_b[1956:1956] ); -sram6T_blwl sram_blwl_1957_ (mux_2level_size50_18_sram_blwl_out[1957:1957] ,mux_2level_size50_18_sram_blwl_out[1957:1957] ,mux_2level_size50_18_sram_blwl_outb[1957:1957] ,mux_2level_size50_18_configbus0[1957:1957], mux_2level_size50_18_configbus1[1957:1957] , mux_2level_size50_18_configbus0_b[1957:1957] ); -sram6T_blwl sram_blwl_1958_ (mux_2level_size50_18_sram_blwl_out[1958:1958] ,mux_2level_size50_18_sram_blwl_out[1958:1958] ,mux_2level_size50_18_sram_blwl_outb[1958:1958] ,mux_2level_size50_18_configbus0[1958:1958], mux_2level_size50_18_configbus1[1958:1958] , mux_2level_size50_18_configbus0_b[1958:1958] ); -sram6T_blwl sram_blwl_1959_ (mux_2level_size50_18_sram_blwl_out[1959:1959] ,mux_2level_size50_18_sram_blwl_out[1959:1959] ,mux_2level_size50_18_sram_blwl_outb[1959:1959] ,mux_2level_size50_18_configbus0[1959:1959], mux_2level_size50_18_configbus1[1959:1959] , mux_2level_size50_18_configbus0_b[1959:1959] ); -sram6T_blwl sram_blwl_1960_ (mux_2level_size50_18_sram_blwl_out[1960:1960] ,mux_2level_size50_18_sram_blwl_out[1960:1960] ,mux_2level_size50_18_sram_blwl_outb[1960:1960] ,mux_2level_size50_18_configbus0[1960:1960], mux_2level_size50_18_configbus1[1960:1960] , mux_2level_size50_18_configbus0_b[1960:1960] ); -sram6T_blwl sram_blwl_1961_ (mux_2level_size50_18_sram_blwl_out[1961:1961] ,mux_2level_size50_18_sram_blwl_out[1961:1961] ,mux_2level_size50_18_sram_blwl_outb[1961:1961] ,mux_2level_size50_18_configbus0[1961:1961], mux_2level_size50_18_configbus1[1961:1961] , mux_2level_size50_18_configbus0_b[1961:1961] ); -sram6T_blwl sram_blwl_1962_ (mux_2level_size50_18_sram_blwl_out[1962:1962] ,mux_2level_size50_18_sram_blwl_out[1962:1962] ,mux_2level_size50_18_sram_blwl_outb[1962:1962] ,mux_2level_size50_18_configbus0[1962:1962], mux_2level_size50_18_configbus1[1962:1962] , mux_2level_size50_18_configbus0_b[1962:1962] ); -sram6T_blwl sram_blwl_1963_ (mux_2level_size50_18_sram_blwl_out[1963:1963] ,mux_2level_size50_18_sram_blwl_out[1963:1963] ,mux_2level_size50_18_sram_blwl_outb[1963:1963] ,mux_2level_size50_18_configbus0[1963:1963], mux_2level_size50_18_configbus1[1963:1963] , mux_2level_size50_18_configbus0_b[1963:1963] ); -sram6T_blwl sram_blwl_1964_ (mux_2level_size50_18_sram_blwl_out[1964:1964] ,mux_2level_size50_18_sram_blwl_out[1964:1964] ,mux_2level_size50_18_sram_blwl_outb[1964:1964] ,mux_2level_size50_18_configbus0[1964:1964], mux_2level_size50_18_configbus1[1964:1964] , mux_2level_size50_18_configbus0_b[1964:1964] ); -sram6T_blwl sram_blwl_1965_ (mux_2level_size50_18_sram_blwl_out[1965:1965] ,mux_2level_size50_18_sram_blwl_out[1965:1965] ,mux_2level_size50_18_sram_blwl_outb[1965:1965] ,mux_2level_size50_18_configbus0[1965:1965], mux_2level_size50_18_configbus1[1965:1965] , mux_2level_size50_18_configbus0_b[1965:1965] ); -sram6T_blwl sram_blwl_1966_ (mux_2level_size50_18_sram_blwl_out[1966:1966] ,mux_2level_size50_18_sram_blwl_out[1966:1966] ,mux_2level_size50_18_sram_blwl_outb[1966:1966] ,mux_2level_size50_18_configbus0[1966:1966], mux_2level_size50_18_configbus1[1966:1966] , mux_2level_size50_18_configbus0_b[1966:1966] ); -sram6T_blwl sram_blwl_1967_ (mux_2level_size50_18_sram_blwl_out[1967:1967] ,mux_2level_size50_18_sram_blwl_out[1967:1967] ,mux_2level_size50_18_sram_blwl_outb[1967:1967] ,mux_2level_size50_18_configbus0[1967:1967], mux_2level_size50_18_configbus1[1967:1967] , mux_2level_size50_18_configbus0_b[1967:1967] ); -sram6T_blwl sram_blwl_1968_ (mux_2level_size50_18_sram_blwl_out[1968:1968] ,mux_2level_size50_18_sram_blwl_out[1968:1968] ,mux_2level_size50_18_sram_blwl_outb[1968:1968] ,mux_2level_size50_18_configbus0[1968:1968], mux_2level_size50_18_configbus1[1968:1968] , mux_2level_size50_18_configbus0_b[1968:1968] ); -sram6T_blwl sram_blwl_1969_ (mux_2level_size50_18_sram_blwl_out[1969:1969] ,mux_2level_size50_18_sram_blwl_out[1969:1969] ,mux_2level_size50_18_sram_blwl_outb[1969:1969] ,mux_2level_size50_18_configbus0[1969:1969], mux_2level_size50_18_configbus1[1969:1969] , mux_2level_size50_18_configbus0_b[1969:1969] ); -wire [0:49] in_bus_mux_2level_size50_19_ ; -assign in_bus_mux_2level_size50_19_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_19_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_19_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_19_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_19_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_19_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_19_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_19_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_19_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_19_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_19_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_19_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_19_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_19_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_19_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_19_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_19_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_19_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_19_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_19_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_19_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_19_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_19_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_19_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_19_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_19_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_19_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_19_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_19_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_19_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_19_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_19_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_19_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_19_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_19_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_19_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_19_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_19_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_19_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_19_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_19_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_19_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_19_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_19_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_19_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_19_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_19_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_19_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_19_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_19_[49] = fle_9___out_0_ ; -wire [1970:1985] mux_2level_size50_19_configbus0; -wire [1970:1985] mux_2level_size50_19_configbus1; -wire [1970:1985] mux_2level_size50_19_sram_blwl_out ; -wire [1970:1985] mux_2level_size50_19_sram_blwl_outb ; -assign mux_2level_size50_19_configbus0[1970:1985] = sram_blwl_bl[1970:1985] ; -assign mux_2level_size50_19_configbus1[1970:1985] = sram_blwl_wl[1970:1985] ; -wire [1970:1985] mux_2level_size50_19_configbus0_b; -assign mux_2level_size50_19_configbus0_b[1970:1985] = sram_blwl_blb[1970:1985] ; -mux_2level_size50 mux_2level_size50_19_ (in_bus_mux_2level_size50_19_, fle_3___in_1_, mux_2level_size50_19_sram_blwl_out[1970:1985] , -mux_2level_size50_19_sram_blwl_outb[1970:1985] ); -//----- SRAM bits for MUX[19], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1970_ (mux_2level_size50_19_sram_blwl_out[1970:1970] ,mux_2level_size50_19_sram_blwl_out[1970:1970] ,mux_2level_size50_19_sram_blwl_outb[1970:1970] ,mux_2level_size50_19_configbus0[1970:1970], mux_2level_size50_19_configbus1[1970:1970] , mux_2level_size50_19_configbus0_b[1970:1970] ); -sram6T_blwl sram_blwl_1971_ (mux_2level_size50_19_sram_blwl_out[1971:1971] ,mux_2level_size50_19_sram_blwl_out[1971:1971] ,mux_2level_size50_19_sram_blwl_outb[1971:1971] ,mux_2level_size50_19_configbus0[1971:1971], mux_2level_size50_19_configbus1[1971:1971] , mux_2level_size50_19_configbus0_b[1971:1971] ); -sram6T_blwl sram_blwl_1972_ (mux_2level_size50_19_sram_blwl_out[1972:1972] ,mux_2level_size50_19_sram_blwl_out[1972:1972] ,mux_2level_size50_19_sram_blwl_outb[1972:1972] ,mux_2level_size50_19_configbus0[1972:1972], mux_2level_size50_19_configbus1[1972:1972] , mux_2level_size50_19_configbus0_b[1972:1972] ); -sram6T_blwl sram_blwl_1973_ (mux_2level_size50_19_sram_blwl_out[1973:1973] ,mux_2level_size50_19_sram_blwl_out[1973:1973] ,mux_2level_size50_19_sram_blwl_outb[1973:1973] ,mux_2level_size50_19_configbus0[1973:1973], mux_2level_size50_19_configbus1[1973:1973] , mux_2level_size50_19_configbus0_b[1973:1973] ); -sram6T_blwl sram_blwl_1974_ (mux_2level_size50_19_sram_blwl_out[1974:1974] ,mux_2level_size50_19_sram_blwl_out[1974:1974] ,mux_2level_size50_19_sram_blwl_outb[1974:1974] ,mux_2level_size50_19_configbus0[1974:1974], mux_2level_size50_19_configbus1[1974:1974] , mux_2level_size50_19_configbus0_b[1974:1974] ); -sram6T_blwl sram_blwl_1975_ (mux_2level_size50_19_sram_blwl_out[1975:1975] ,mux_2level_size50_19_sram_blwl_out[1975:1975] ,mux_2level_size50_19_sram_blwl_outb[1975:1975] ,mux_2level_size50_19_configbus0[1975:1975], mux_2level_size50_19_configbus1[1975:1975] , mux_2level_size50_19_configbus0_b[1975:1975] ); -sram6T_blwl sram_blwl_1976_ (mux_2level_size50_19_sram_blwl_out[1976:1976] ,mux_2level_size50_19_sram_blwl_out[1976:1976] ,mux_2level_size50_19_sram_blwl_outb[1976:1976] ,mux_2level_size50_19_configbus0[1976:1976], mux_2level_size50_19_configbus1[1976:1976] , mux_2level_size50_19_configbus0_b[1976:1976] ); -sram6T_blwl sram_blwl_1977_ (mux_2level_size50_19_sram_blwl_out[1977:1977] ,mux_2level_size50_19_sram_blwl_out[1977:1977] ,mux_2level_size50_19_sram_blwl_outb[1977:1977] ,mux_2level_size50_19_configbus0[1977:1977], mux_2level_size50_19_configbus1[1977:1977] , mux_2level_size50_19_configbus0_b[1977:1977] ); -sram6T_blwl sram_blwl_1978_ (mux_2level_size50_19_sram_blwl_out[1978:1978] ,mux_2level_size50_19_sram_blwl_out[1978:1978] ,mux_2level_size50_19_sram_blwl_outb[1978:1978] ,mux_2level_size50_19_configbus0[1978:1978], mux_2level_size50_19_configbus1[1978:1978] , mux_2level_size50_19_configbus0_b[1978:1978] ); -sram6T_blwl sram_blwl_1979_ (mux_2level_size50_19_sram_blwl_out[1979:1979] ,mux_2level_size50_19_sram_blwl_out[1979:1979] ,mux_2level_size50_19_sram_blwl_outb[1979:1979] ,mux_2level_size50_19_configbus0[1979:1979], mux_2level_size50_19_configbus1[1979:1979] , mux_2level_size50_19_configbus0_b[1979:1979] ); -sram6T_blwl sram_blwl_1980_ (mux_2level_size50_19_sram_blwl_out[1980:1980] ,mux_2level_size50_19_sram_blwl_out[1980:1980] ,mux_2level_size50_19_sram_blwl_outb[1980:1980] ,mux_2level_size50_19_configbus0[1980:1980], mux_2level_size50_19_configbus1[1980:1980] , mux_2level_size50_19_configbus0_b[1980:1980] ); -sram6T_blwl sram_blwl_1981_ (mux_2level_size50_19_sram_blwl_out[1981:1981] ,mux_2level_size50_19_sram_blwl_out[1981:1981] ,mux_2level_size50_19_sram_blwl_outb[1981:1981] ,mux_2level_size50_19_configbus0[1981:1981], mux_2level_size50_19_configbus1[1981:1981] , mux_2level_size50_19_configbus0_b[1981:1981] ); -sram6T_blwl sram_blwl_1982_ (mux_2level_size50_19_sram_blwl_out[1982:1982] ,mux_2level_size50_19_sram_blwl_out[1982:1982] ,mux_2level_size50_19_sram_blwl_outb[1982:1982] ,mux_2level_size50_19_configbus0[1982:1982], mux_2level_size50_19_configbus1[1982:1982] , mux_2level_size50_19_configbus0_b[1982:1982] ); -sram6T_blwl sram_blwl_1983_ (mux_2level_size50_19_sram_blwl_out[1983:1983] ,mux_2level_size50_19_sram_blwl_out[1983:1983] ,mux_2level_size50_19_sram_blwl_outb[1983:1983] ,mux_2level_size50_19_configbus0[1983:1983], mux_2level_size50_19_configbus1[1983:1983] , mux_2level_size50_19_configbus0_b[1983:1983] ); -sram6T_blwl sram_blwl_1984_ (mux_2level_size50_19_sram_blwl_out[1984:1984] ,mux_2level_size50_19_sram_blwl_out[1984:1984] ,mux_2level_size50_19_sram_blwl_outb[1984:1984] ,mux_2level_size50_19_configbus0[1984:1984], mux_2level_size50_19_configbus1[1984:1984] , mux_2level_size50_19_configbus0_b[1984:1984] ); -sram6T_blwl sram_blwl_1985_ (mux_2level_size50_19_sram_blwl_out[1985:1985] ,mux_2level_size50_19_sram_blwl_out[1985:1985] ,mux_2level_size50_19_sram_blwl_outb[1985:1985] ,mux_2level_size50_19_configbus0[1985:1985], mux_2level_size50_19_configbus1[1985:1985] , mux_2level_size50_19_configbus0_b[1985:1985] ); -wire [0:49] in_bus_mux_2level_size50_20_ ; -assign in_bus_mux_2level_size50_20_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_20_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_20_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_20_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_20_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_20_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_20_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_20_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_20_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_20_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_20_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_20_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_20_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_20_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_20_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_20_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_20_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_20_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_20_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_20_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_20_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_20_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_20_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_20_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_20_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_20_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_20_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_20_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_20_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_20_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_20_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_20_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_20_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_20_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_20_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_20_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_20_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_20_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_20_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_20_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_20_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_20_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_20_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_20_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_20_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_20_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_20_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_20_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_20_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_20_[49] = fle_9___out_0_ ; -wire [1986:2001] mux_2level_size50_20_configbus0; -wire [1986:2001] mux_2level_size50_20_configbus1; -wire [1986:2001] mux_2level_size50_20_sram_blwl_out ; -wire [1986:2001] mux_2level_size50_20_sram_blwl_outb ; -assign mux_2level_size50_20_configbus0[1986:2001] = sram_blwl_bl[1986:2001] ; -assign mux_2level_size50_20_configbus1[1986:2001] = sram_blwl_wl[1986:2001] ; -wire [1986:2001] mux_2level_size50_20_configbus0_b; -assign mux_2level_size50_20_configbus0_b[1986:2001] = sram_blwl_blb[1986:2001] ; -mux_2level_size50 mux_2level_size50_20_ (in_bus_mux_2level_size50_20_, fle_3___in_2_, mux_2level_size50_20_sram_blwl_out[1986:2001] , -mux_2level_size50_20_sram_blwl_outb[1986:2001] ); -//----- SRAM bits for MUX[20], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_1986_ (mux_2level_size50_20_sram_blwl_out[1986:1986] ,mux_2level_size50_20_sram_blwl_out[1986:1986] ,mux_2level_size50_20_sram_blwl_outb[1986:1986] ,mux_2level_size50_20_configbus0[1986:1986], mux_2level_size50_20_configbus1[1986:1986] , mux_2level_size50_20_configbus0_b[1986:1986] ); -sram6T_blwl sram_blwl_1987_ (mux_2level_size50_20_sram_blwl_out[1987:1987] ,mux_2level_size50_20_sram_blwl_out[1987:1987] ,mux_2level_size50_20_sram_blwl_outb[1987:1987] ,mux_2level_size50_20_configbus0[1987:1987], mux_2level_size50_20_configbus1[1987:1987] , mux_2level_size50_20_configbus0_b[1987:1987] ); -sram6T_blwl sram_blwl_1988_ (mux_2level_size50_20_sram_blwl_out[1988:1988] ,mux_2level_size50_20_sram_blwl_out[1988:1988] ,mux_2level_size50_20_sram_blwl_outb[1988:1988] ,mux_2level_size50_20_configbus0[1988:1988], mux_2level_size50_20_configbus1[1988:1988] , mux_2level_size50_20_configbus0_b[1988:1988] ); -sram6T_blwl sram_blwl_1989_ (mux_2level_size50_20_sram_blwl_out[1989:1989] ,mux_2level_size50_20_sram_blwl_out[1989:1989] ,mux_2level_size50_20_sram_blwl_outb[1989:1989] ,mux_2level_size50_20_configbus0[1989:1989], mux_2level_size50_20_configbus1[1989:1989] , mux_2level_size50_20_configbus0_b[1989:1989] ); -sram6T_blwl sram_blwl_1990_ (mux_2level_size50_20_sram_blwl_out[1990:1990] ,mux_2level_size50_20_sram_blwl_out[1990:1990] ,mux_2level_size50_20_sram_blwl_outb[1990:1990] ,mux_2level_size50_20_configbus0[1990:1990], mux_2level_size50_20_configbus1[1990:1990] , mux_2level_size50_20_configbus0_b[1990:1990] ); -sram6T_blwl sram_blwl_1991_ (mux_2level_size50_20_sram_blwl_out[1991:1991] ,mux_2level_size50_20_sram_blwl_out[1991:1991] ,mux_2level_size50_20_sram_blwl_outb[1991:1991] ,mux_2level_size50_20_configbus0[1991:1991], mux_2level_size50_20_configbus1[1991:1991] , mux_2level_size50_20_configbus0_b[1991:1991] ); -sram6T_blwl sram_blwl_1992_ (mux_2level_size50_20_sram_blwl_out[1992:1992] ,mux_2level_size50_20_sram_blwl_out[1992:1992] ,mux_2level_size50_20_sram_blwl_outb[1992:1992] ,mux_2level_size50_20_configbus0[1992:1992], mux_2level_size50_20_configbus1[1992:1992] , mux_2level_size50_20_configbus0_b[1992:1992] ); -sram6T_blwl sram_blwl_1993_ (mux_2level_size50_20_sram_blwl_out[1993:1993] ,mux_2level_size50_20_sram_blwl_out[1993:1993] ,mux_2level_size50_20_sram_blwl_outb[1993:1993] ,mux_2level_size50_20_configbus0[1993:1993], mux_2level_size50_20_configbus1[1993:1993] , mux_2level_size50_20_configbus0_b[1993:1993] ); -sram6T_blwl sram_blwl_1994_ (mux_2level_size50_20_sram_blwl_out[1994:1994] ,mux_2level_size50_20_sram_blwl_out[1994:1994] ,mux_2level_size50_20_sram_blwl_outb[1994:1994] ,mux_2level_size50_20_configbus0[1994:1994], mux_2level_size50_20_configbus1[1994:1994] , mux_2level_size50_20_configbus0_b[1994:1994] ); -sram6T_blwl sram_blwl_1995_ (mux_2level_size50_20_sram_blwl_out[1995:1995] ,mux_2level_size50_20_sram_blwl_out[1995:1995] ,mux_2level_size50_20_sram_blwl_outb[1995:1995] ,mux_2level_size50_20_configbus0[1995:1995], mux_2level_size50_20_configbus1[1995:1995] , mux_2level_size50_20_configbus0_b[1995:1995] ); -sram6T_blwl sram_blwl_1996_ (mux_2level_size50_20_sram_blwl_out[1996:1996] ,mux_2level_size50_20_sram_blwl_out[1996:1996] ,mux_2level_size50_20_sram_blwl_outb[1996:1996] ,mux_2level_size50_20_configbus0[1996:1996], mux_2level_size50_20_configbus1[1996:1996] , mux_2level_size50_20_configbus0_b[1996:1996] ); -sram6T_blwl sram_blwl_1997_ (mux_2level_size50_20_sram_blwl_out[1997:1997] ,mux_2level_size50_20_sram_blwl_out[1997:1997] ,mux_2level_size50_20_sram_blwl_outb[1997:1997] ,mux_2level_size50_20_configbus0[1997:1997], mux_2level_size50_20_configbus1[1997:1997] , mux_2level_size50_20_configbus0_b[1997:1997] ); -sram6T_blwl sram_blwl_1998_ (mux_2level_size50_20_sram_blwl_out[1998:1998] ,mux_2level_size50_20_sram_blwl_out[1998:1998] ,mux_2level_size50_20_sram_blwl_outb[1998:1998] ,mux_2level_size50_20_configbus0[1998:1998], mux_2level_size50_20_configbus1[1998:1998] , mux_2level_size50_20_configbus0_b[1998:1998] ); -sram6T_blwl sram_blwl_1999_ (mux_2level_size50_20_sram_blwl_out[1999:1999] ,mux_2level_size50_20_sram_blwl_out[1999:1999] ,mux_2level_size50_20_sram_blwl_outb[1999:1999] ,mux_2level_size50_20_configbus0[1999:1999], mux_2level_size50_20_configbus1[1999:1999] , mux_2level_size50_20_configbus0_b[1999:1999] ); -sram6T_blwl sram_blwl_2000_ (mux_2level_size50_20_sram_blwl_out[2000:2000] ,mux_2level_size50_20_sram_blwl_out[2000:2000] ,mux_2level_size50_20_sram_blwl_outb[2000:2000] ,mux_2level_size50_20_configbus0[2000:2000], mux_2level_size50_20_configbus1[2000:2000] , mux_2level_size50_20_configbus0_b[2000:2000] ); -sram6T_blwl sram_blwl_2001_ (mux_2level_size50_20_sram_blwl_out[2001:2001] ,mux_2level_size50_20_sram_blwl_out[2001:2001] ,mux_2level_size50_20_sram_blwl_outb[2001:2001] ,mux_2level_size50_20_configbus0[2001:2001], mux_2level_size50_20_configbus1[2001:2001] , mux_2level_size50_20_configbus0_b[2001:2001] ); -wire [0:49] in_bus_mux_2level_size50_21_ ; -assign in_bus_mux_2level_size50_21_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_21_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_21_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_21_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_21_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_21_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_21_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_21_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_21_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_21_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_21_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_21_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_21_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_21_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_21_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_21_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_21_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_21_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_21_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_21_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_21_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_21_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_21_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_21_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_21_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_21_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_21_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_21_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_21_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_21_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_21_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_21_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_21_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_21_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_21_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_21_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_21_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_21_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_21_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_21_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_21_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_21_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_21_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_21_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_21_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_21_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_21_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_21_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_21_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_21_[49] = fle_9___out_0_ ; -wire [2002:2017] mux_2level_size50_21_configbus0; -wire [2002:2017] mux_2level_size50_21_configbus1; -wire [2002:2017] mux_2level_size50_21_sram_blwl_out ; -wire [2002:2017] mux_2level_size50_21_sram_blwl_outb ; -assign mux_2level_size50_21_configbus0[2002:2017] = sram_blwl_bl[2002:2017] ; -assign mux_2level_size50_21_configbus1[2002:2017] = sram_blwl_wl[2002:2017] ; -wire [2002:2017] mux_2level_size50_21_configbus0_b; -assign mux_2level_size50_21_configbus0_b[2002:2017] = sram_blwl_blb[2002:2017] ; -mux_2level_size50 mux_2level_size50_21_ (in_bus_mux_2level_size50_21_, fle_3___in_3_, mux_2level_size50_21_sram_blwl_out[2002:2017] , -mux_2level_size50_21_sram_blwl_outb[2002:2017] ); -//----- SRAM bits for MUX[21], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2002_ (mux_2level_size50_21_sram_blwl_out[2002:2002] ,mux_2level_size50_21_sram_blwl_out[2002:2002] ,mux_2level_size50_21_sram_blwl_outb[2002:2002] ,mux_2level_size50_21_configbus0[2002:2002], mux_2level_size50_21_configbus1[2002:2002] , mux_2level_size50_21_configbus0_b[2002:2002] ); -sram6T_blwl sram_blwl_2003_ (mux_2level_size50_21_sram_blwl_out[2003:2003] ,mux_2level_size50_21_sram_blwl_out[2003:2003] ,mux_2level_size50_21_sram_blwl_outb[2003:2003] ,mux_2level_size50_21_configbus0[2003:2003], mux_2level_size50_21_configbus1[2003:2003] , mux_2level_size50_21_configbus0_b[2003:2003] ); -sram6T_blwl sram_blwl_2004_ (mux_2level_size50_21_sram_blwl_out[2004:2004] ,mux_2level_size50_21_sram_blwl_out[2004:2004] ,mux_2level_size50_21_sram_blwl_outb[2004:2004] ,mux_2level_size50_21_configbus0[2004:2004], mux_2level_size50_21_configbus1[2004:2004] , mux_2level_size50_21_configbus0_b[2004:2004] ); -sram6T_blwl sram_blwl_2005_ (mux_2level_size50_21_sram_blwl_out[2005:2005] ,mux_2level_size50_21_sram_blwl_out[2005:2005] ,mux_2level_size50_21_sram_blwl_outb[2005:2005] ,mux_2level_size50_21_configbus0[2005:2005], mux_2level_size50_21_configbus1[2005:2005] , mux_2level_size50_21_configbus0_b[2005:2005] ); -sram6T_blwl sram_blwl_2006_ (mux_2level_size50_21_sram_blwl_out[2006:2006] ,mux_2level_size50_21_sram_blwl_out[2006:2006] ,mux_2level_size50_21_sram_blwl_outb[2006:2006] ,mux_2level_size50_21_configbus0[2006:2006], mux_2level_size50_21_configbus1[2006:2006] , mux_2level_size50_21_configbus0_b[2006:2006] ); -sram6T_blwl sram_blwl_2007_ (mux_2level_size50_21_sram_blwl_out[2007:2007] ,mux_2level_size50_21_sram_blwl_out[2007:2007] ,mux_2level_size50_21_sram_blwl_outb[2007:2007] ,mux_2level_size50_21_configbus0[2007:2007], mux_2level_size50_21_configbus1[2007:2007] , mux_2level_size50_21_configbus0_b[2007:2007] ); -sram6T_blwl sram_blwl_2008_ (mux_2level_size50_21_sram_blwl_out[2008:2008] ,mux_2level_size50_21_sram_blwl_out[2008:2008] ,mux_2level_size50_21_sram_blwl_outb[2008:2008] ,mux_2level_size50_21_configbus0[2008:2008], mux_2level_size50_21_configbus1[2008:2008] , mux_2level_size50_21_configbus0_b[2008:2008] ); -sram6T_blwl sram_blwl_2009_ (mux_2level_size50_21_sram_blwl_out[2009:2009] ,mux_2level_size50_21_sram_blwl_out[2009:2009] ,mux_2level_size50_21_sram_blwl_outb[2009:2009] ,mux_2level_size50_21_configbus0[2009:2009], mux_2level_size50_21_configbus1[2009:2009] , mux_2level_size50_21_configbus0_b[2009:2009] ); -sram6T_blwl sram_blwl_2010_ (mux_2level_size50_21_sram_blwl_out[2010:2010] ,mux_2level_size50_21_sram_blwl_out[2010:2010] ,mux_2level_size50_21_sram_blwl_outb[2010:2010] ,mux_2level_size50_21_configbus0[2010:2010], mux_2level_size50_21_configbus1[2010:2010] , mux_2level_size50_21_configbus0_b[2010:2010] ); -sram6T_blwl sram_blwl_2011_ (mux_2level_size50_21_sram_blwl_out[2011:2011] ,mux_2level_size50_21_sram_blwl_out[2011:2011] ,mux_2level_size50_21_sram_blwl_outb[2011:2011] ,mux_2level_size50_21_configbus0[2011:2011], mux_2level_size50_21_configbus1[2011:2011] , mux_2level_size50_21_configbus0_b[2011:2011] ); -sram6T_blwl sram_blwl_2012_ (mux_2level_size50_21_sram_blwl_out[2012:2012] ,mux_2level_size50_21_sram_blwl_out[2012:2012] ,mux_2level_size50_21_sram_blwl_outb[2012:2012] ,mux_2level_size50_21_configbus0[2012:2012], mux_2level_size50_21_configbus1[2012:2012] , mux_2level_size50_21_configbus0_b[2012:2012] ); -sram6T_blwl sram_blwl_2013_ (mux_2level_size50_21_sram_blwl_out[2013:2013] ,mux_2level_size50_21_sram_blwl_out[2013:2013] ,mux_2level_size50_21_sram_blwl_outb[2013:2013] ,mux_2level_size50_21_configbus0[2013:2013], mux_2level_size50_21_configbus1[2013:2013] , mux_2level_size50_21_configbus0_b[2013:2013] ); -sram6T_blwl sram_blwl_2014_ (mux_2level_size50_21_sram_blwl_out[2014:2014] ,mux_2level_size50_21_sram_blwl_out[2014:2014] ,mux_2level_size50_21_sram_blwl_outb[2014:2014] ,mux_2level_size50_21_configbus0[2014:2014], mux_2level_size50_21_configbus1[2014:2014] , mux_2level_size50_21_configbus0_b[2014:2014] ); -sram6T_blwl sram_blwl_2015_ (mux_2level_size50_21_sram_blwl_out[2015:2015] ,mux_2level_size50_21_sram_blwl_out[2015:2015] ,mux_2level_size50_21_sram_blwl_outb[2015:2015] ,mux_2level_size50_21_configbus0[2015:2015], mux_2level_size50_21_configbus1[2015:2015] , mux_2level_size50_21_configbus0_b[2015:2015] ); -sram6T_blwl sram_blwl_2016_ (mux_2level_size50_21_sram_blwl_out[2016:2016] ,mux_2level_size50_21_sram_blwl_out[2016:2016] ,mux_2level_size50_21_sram_blwl_outb[2016:2016] ,mux_2level_size50_21_configbus0[2016:2016], mux_2level_size50_21_configbus1[2016:2016] , mux_2level_size50_21_configbus0_b[2016:2016] ); -sram6T_blwl sram_blwl_2017_ (mux_2level_size50_21_sram_blwl_out[2017:2017] ,mux_2level_size50_21_sram_blwl_out[2017:2017] ,mux_2level_size50_21_sram_blwl_outb[2017:2017] ,mux_2level_size50_21_configbus0[2017:2017], mux_2level_size50_21_configbus1[2017:2017] , mux_2level_size50_21_configbus0_b[2017:2017] ); -wire [0:49] in_bus_mux_2level_size50_22_ ; -assign in_bus_mux_2level_size50_22_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_22_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_22_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_22_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_22_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_22_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_22_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_22_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_22_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_22_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_22_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_22_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_22_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_22_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_22_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_22_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_22_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_22_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_22_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_22_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_22_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_22_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_22_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_22_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_22_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_22_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_22_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_22_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_22_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_22_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_22_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_22_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_22_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_22_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_22_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_22_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_22_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_22_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_22_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_22_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_22_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_22_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_22_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_22_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_22_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_22_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_22_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_22_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_22_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_22_[49] = fle_9___out_0_ ; -wire [2018:2033] mux_2level_size50_22_configbus0; -wire [2018:2033] mux_2level_size50_22_configbus1; -wire [2018:2033] mux_2level_size50_22_sram_blwl_out ; -wire [2018:2033] mux_2level_size50_22_sram_blwl_outb ; -assign mux_2level_size50_22_configbus0[2018:2033] = sram_blwl_bl[2018:2033] ; -assign mux_2level_size50_22_configbus1[2018:2033] = sram_blwl_wl[2018:2033] ; -wire [2018:2033] mux_2level_size50_22_configbus0_b; -assign mux_2level_size50_22_configbus0_b[2018:2033] = sram_blwl_blb[2018:2033] ; -mux_2level_size50 mux_2level_size50_22_ (in_bus_mux_2level_size50_22_, fle_3___in_4_, mux_2level_size50_22_sram_blwl_out[2018:2033] , -mux_2level_size50_22_sram_blwl_outb[2018:2033] ); -//----- SRAM bits for MUX[22], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2018_ (mux_2level_size50_22_sram_blwl_out[2018:2018] ,mux_2level_size50_22_sram_blwl_out[2018:2018] ,mux_2level_size50_22_sram_blwl_outb[2018:2018] ,mux_2level_size50_22_configbus0[2018:2018], mux_2level_size50_22_configbus1[2018:2018] , mux_2level_size50_22_configbus0_b[2018:2018] ); -sram6T_blwl sram_blwl_2019_ (mux_2level_size50_22_sram_blwl_out[2019:2019] ,mux_2level_size50_22_sram_blwl_out[2019:2019] ,mux_2level_size50_22_sram_blwl_outb[2019:2019] ,mux_2level_size50_22_configbus0[2019:2019], mux_2level_size50_22_configbus1[2019:2019] , mux_2level_size50_22_configbus0_b[2019:2019] ); -sram6T_blwl sram_blwl_2020_ (mux_2level_size50_22_sram_blwl_out[2020:2020] ,mux_2level_size50_22_sram_blwl_out[2020:2020] ,mux_2level_size50_22_sram_blwl_outb[2020:2020] ,mux_2level_size50_22_configbus0[2020:2020], mux_2level_size50_22_configbus1[2020:2020] , mux_2level_size50_22_configbus0_b[2020:2020] ); -sram6T_blwl sram_blwl_2021_ (mux_2level_size50_22_sram_blwl_out[2021:2021] ,mux_2level_size50_22_sram_blwl_out[2021:2021] ,mux_2level_size50_22_sram_blwl_outb[2021:2021] ,mux_2level_size50_22_configbus0[2021:2021], mux_2level_size50_22_configbus1[2021:2021] , mux_2level_size50_22_configbus0_b[2021:2021] ); -sram6T_blwl sram_blwl_2022_ (mux_2level_size50_22_sram_blwl_out[2022:2022] ,mux_2level_size50_22_sram_blwl_out[2022:2022] ,mux_2level_size50_22_sram_blwl_outb[2022:2022] ,mux_2level_size50_22_configbus0[2022:2022], mux_2level_size50_22_configbus1[2022:2022] , mux_2level_size50_22_configbus0_b[2022:2022] ); -sram6T_blwl sram_blwl_2023_ (mux_2level_size50_22_sram_blwl_out[2023:2023] ,mux_2level_size50_22_sram_blwl_out[2023:2023] ,mux_2level_size50_22_sram_blwl_outb[2023:2023] ,mux_2level_size50_22_configbus0[2023:2023], mux_2level_size50_22_configbus1[2023:2023] , mux_2level_size50_22_configbus0_b[2023:2023] ); -sram6T_blwl sram_blwl_2024_ (mux_2level_size50_22_sram_blwl_out[2024:2024] ,mux_2level_size50_22_sram_blwl_out[2024:2024] ,mux_2level_size50_22_sram_blwl_outb[2024:2024] ,mux_2level_size50_22_configbus0[2024:2024], mux_2level_size50_22_configbus1[2024:2024] , mux_2level_size50_22_configbus0_b[2024:2024] ); -sram6T_blwl sram_blwl_2025_ (mux_2level_size50_22_sram_blwl_out[2025:2025] ,mux_2level_size50_22_sram_blwl_out[2025:2025] ,mux_2level_size50_22_sram_blwl_outb[2025:2025] ,mux_2level_size50_22_configbus0[2025:2025], mux_2level_size50_22_configbus1[2025:2025] , mux_2level_size50_22_configbus0_b[2025:2025] ); -sram6T_blwl sram_blwl_2026_ (mux_2level_size50_22_sram_blwl_out[2026:2026] ,mux_2level_size50_22_sram_blwl_out[2026:2026] ,mux_2level_size50_22_sram_blwl_outb[2026:2026] ,mux_2level_size50_22_configbus0[2026:2026], mux_2level_size50_22_configbus1[2026:2026] , mux_2level_size50_22_configbus0_b[2026:2026] ); -sram6T_blwl sram_blwl_2027_ (mux_2level_size50_22_sram_blwl_out[2027:2027] ,mux_2level_size50_22_sram_blwl_out[2027:2027] ,mux_2level_size50_22_sram_blwl_outb[2027:2027] ,mux_2level_size50_22_configbus0[2027:2027], mux_2level_size50_22_configbus1[2027:2027] , mux_2level_size50_22_configbus0_b[2027:2027] ); -sram6T_blwl sram_blwl_2028_ (mux_2level_size50_22_sram_blwl_out[2028:2028] ,mux_2level_size50_22_sram_blwl_out[2028:2028] ,mux_2level_size50_22_sram_blwl_outb[2028:2028] ,mux_2level_size50_22_configbus0[2028:2028], mux_2level_size50_22_configbus1[2028:2028] , mux_2level_size50_22_configbus0_b[2028:2028] ); -sram6T_blwl sram_blwl_2029_ (mux_2level_size50_22_sram_blwl_out[2029:2029] ,mux_2level_size50_22_sram_blwl_out[2029:2029] ,mux_2level_size50_22_sram_blwl_outb[2029:2029] ,mux_2level_size50_22_configbus0[2029:2029], mux_2level_size50_22_configbus1[2029:2029] , mux_2level_size50_22_configbus0_b[2029:2029] ); -sram6T_blwl sram_blwl_2030_ (mux_2level_size50_22_sram_blwl_out[2030:2030] ,mux_2level_size50_22_sram_blwl_out[2030:2030] ,mux_2level_size50_22_sram_blwl_outb[2030:2030] ,mux_2level_size50_22_configbus0[2030:2030], mux_2level_size50_22_configbus1[2030:2030] , mux_2level_size50_22_configbus0_b[2030:2030] ); -sram6T_blwl sram_blwl_2031_ (mux_2level_size50_22_sram_blwl_out[2031:2031] ,mux_2level_size50_22_sram_blwl_out[2031:2031] ,mux_2level_size50_22_sram_blwl_outb[2031:2031] ,mux_2level_size50_22_configbus0[2031:2031], mux_2level_size50_22_configbus1[2031:2031] , mux_2level_size50_22_configbus0_b[2031:2031] ); -sram6T_blwl sram_blwl_2032_ (mux_2level_size50_22_sram_blwl_out[2032:2032] ,mux_2level_size50_22_sram_blwl_out[2032:2032] ,mux_2level_size50_22_sram_blwl_outb[2032:2032] ,mux_2level_size50_22_configbus0[2032:2032], mux_2level_size50_22_configbus1[2032:2032] , mux_2level_size50_22_configbus0_b[2032:2032] ); -sram6T_blwl sram_blwl_2033_ (mux_2level_size50_22_sram_blwl_out[2033:2033] ,mux_2level_size50_22_sram_blwl_out[2033:2033] ,mux_2level_size50_22_sram_blwl_outb[2033:2033] ,mux_2level_size50_22_configbus0[2033:2033], mux_2level_size50_22_configbus1[2033:2033] , mux_2level_size50_22_configbus0_b[2033:2033] ); -wire [0:49] in_bus_mux_2level_size50_23_ ; -assign in_bus_mux_2level_size50_23_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_23_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_23_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_23_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_23_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_23_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_23_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_23_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_23_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_23_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_23_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_23_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_23_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_23_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_23_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_23_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_23_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_23_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_23_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_23_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_23_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_23_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_23_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_23_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_23_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_23_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_23_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_23_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_23_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_23_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_23_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_23_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_23_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_23_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_23_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_23_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_23_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_23_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_23_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_23_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_23_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_23_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_23_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_23_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_23_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_23_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_23_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_23_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_23_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_23_[49] = fle_9___out_0_ ; -wire [2034:2049] mux_2level_size50_23_configbus0; -wire [2034:2049] mux_2level_size50_23_configbus1; -wire [2034:2049] mux_2level_size50_23_sram_blwl_out ; -wire [2034:2049] mux_2level_size50_23_sram_blwl_outb ; -assign mux_2level_size50_23_configbus0[2034:2049] = sram_blwl_bl[2034:2049] ; -assign mux_2level_size50_23_configbus1[2034:2049] = sram_blwl_wl[2034:2049] ; -wire [2034:2049] mux_2level_size50_23_configbus0_b; -assign mux_2level_size50_23_configbus0_b[2034:2049] = sram_blwl_blb[2034:2049] ; -mux_2level_size50 mux_2level_size50_23_ (in_bus_mux_2level_size50_23_, fle_3___in_5_, mux_2level_size50_23_sram_blwl_out[2034:2049] , -mux_2level_size50_23_sram_blwl_outb[2034:2049] ); -//----- SRAM bits for MUX[23], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2034_ (mux_2level_size50_23_sram_blwl_out[2034:2034] ,mux_2level_size50_23_sram_blwl_out[2034:2034] ,mux_2level_size50_23_sram_blwl_outb[2034:2034] ,mux_2level_size50_23_configbus0[2034:2034], mux_2level_size50_23_configbus1[2034:2034] , mux_2level_size50_23_configbus0_b[2034:2034] ); -sram6T_blwl sram_blwl_2035_ (mux_2level_size50_23_sram_blwl_out[2035:2035] ,mux_2level_size50_23_sram_blwl_out[2035:2035] ,mux_2level_size50_23_sram_blwl_outb[2035:2035] ,mux_2level_size50_23_configbus0[2035:2035], mux_2level_size50_23_configbus1[2035:2035] , mux_2level_size50_23_configbus0_b[2035:2035] ); -sram6T_blwl sram_blwl_2036_ (mux_2level_size50_23_sram_blwl_out[2036:2036] ,mux_2level_size50_23_sram_blwl_out[2036:2036] ,mux_2level_size50_23_sram_blwl_outb[2036:2036] ,mux_2level_size50_23_configbus0[2036:2036], mux_2level_size50_23_configbus1[2036:2036] , mux_2level_size50_23_configbus0_b[2036:2036] ); -sram6T_blwl sram_blwl_2037_ (mux_2level_size50_23_sram_blwl_out[2037:2037] ,mux_2level_size50_23_sram_blwl_out[2037:2037] ,mux_2level_size50_23_sram_blwl_outb[2037:2037] ,mux_2level_size50_23_configbus0[2037:2037], mux_2level_size50_23_configbus1[2037:2037] , mux_2level_size50_23_configbus0_b[2037:2037] ); -sram6T_blwl sram_blwl_2038_ (mux_2level_size50_23_sram_blwl_out[2038:2038] ,mux_2level_size50_23_sram_blwl_out[2038:2038] ,mux_2level_size50_23_sram_blwl_outb[2038:2038] ,mux_2level_size50_23_configbus0[2038:2038], mux_2level_size50_23_configbus1[2038:2038] , mux_2level_size50_23_configbus0_b[2038:2038] ); -sram6T_blwl sram_blwl_2039_ (mux_2level_size50_23_sram_blwl_out[2039:2039] ,mux_2level_size50_23_sram_blwl_out[2039:2039] ,mux_2level_size50_23_sram_blwl_outb[2039:2039] ,mux_2level_size50_23_configbus0[2039:2039], mux_2level_size50_23_configbus1[2039:2039] , mux_2level_size50_23_configbus0_b[2039:2039] ); -sram6T_blwl sram_blwl_2040_ (mux_2level_size50_23_sram_blwl_out[2040:2040] ,mux_2level_size50_23_sram_blwl_out[2040:2040] ,mux_2level_size50_23_sram_blwl_outb[2040:2040] ,mux_2level_size50_23_configbus0[2040:2040], mux_2level_size50_23_configbus1[2040:2040] , mux_2level_size50_23_configbus0_b[2040:2040] ); -sram6T_blwl sram_blwl_2041_ (mux_2level_size50_23_sram_blwl_out[2041:2041] ,mux_2level_size50_23_sram_blwl_out[2041:2041] ,mux_2level_size50_23_sram_blwl_outb[2041:2041] ,mux_2level_size50_23_configbus0[2041:2041], mux_2level_size50_23_configbus1[2041:2041] , mux_2level_size50_23_configbus0_b[2041:2041] ); -sram6T_blwl sram_blwl_2042_ (mux_2level_size50_23_sram_blwl_out[2042:2042] ,mux_2level_size50_23_sram_blwl_out[2042:2042] ,mux_2level_size50_23_sram_blwl_outb[2042:2042] ,mux_2level_size50_23_configbus0[2042:2042], mux_2level_size50_23_configbus1[2042:2042] , mux_2level_size50_23_configbus0_b[2042:2042] ); -sram6T_blwl sram_blwl_2043_ (mux_2level_size50_23_sram_blwl_out[2043:2043] ,mux_2level_size50_23_sram_blwl_out[2043:2043] ,mux_2level_size50_23_sram_blwl_outb[2043:2043] ,mux_2level_size50_23_configbus0[2043:2043], mux_2level_size50_23_configbus1[2043:2043] , mux_2level_size50_23_configbus0_b[2043:2043] ); -sram6T_blwl sram_blwl_2044_ (mux_2level_size50_23_sram_blwl_out[2044:2044] ,mux_2level_size50_23_sram_blwl_out[2044:2044] ,mux_2level_size50_23_sram_blwl_outb[2044:2044] ,mux_2level_size50_23_configbus0[2044:2044], mux_2level_size50_23_configbus1[2044:2044] , mux_2level_size50_23_configbus0_b[2044:2044] ); -sram6T_blwl sram_blwl_2045_ (mux_2level_size50_23_sram_blwl_out[2045:2045] ,mux_2level_size50_23_sram_blwl_out[2045:2045] ,mux_2level_size50_23_sram_blwl_outb[2045:2045] ,mux_2level_size50_23_configbus0[2045:2045], mux_2level_size50_23_configbus1[2045:2045] , mux_2level_size50_23_configbus0_b[2045:2045] ); -sram6T_blwl sram_blwl_2046_ (mux_2level_size50_23_sram_blwl_out[2046:2046] ,mux_2level_size50_23_sram_blwl_out[2046:2046] ,mux_2level_size50_23_sram_blwl_outb[2046:2046] ,mux_2level_size50_23_configbus0[2046:2046], mux_2level_size50_23_configbus1[2046:2046] , mux_2level_size50_23_configbus0_b[2046:2046] ); -sram6T_blwl sram_blwl_2047_ (mux_2level_size50_23_sram_blwl_out[2047:2047] ,mux_2level_size50_23_sram_blwl_out[2047:2047] ,mux_2level_size50_23_sram_blwl_outb[2047:2047] ,mux_2level_size50_23_configbus0[2047:2047], mux_2level_size50_23_configbus1[2047:2047] , mux_2level_size50_23_configbus0_b[2047:2047] ); -sram6T_blwl sram_blwl_2048_ (mux_2level_size50_23_sram_blwl_out[2048:2048] ,mux_2level_size50_23_sram_blwl_out[2048:2048] ,mux_2level_size50_23_sram_blwl_outb[2048:2048] ,mux_2level_size50_23_configbus0[2048:2048], mux_2level_size50_23_configbus1[2048:2048] , mux_2level_size50_23_configbus0_b[2048:2048] ); -sram6T_blwl sram_blwl_2049_ (mux_2level_size50_23_sram_blwl_out[2049:2049] ,mux_2level_size50_23_sram_blwl_out[2049:2049] ,mux_2level_size50_23_sram_blwl_outb[2049:2049] ,mux_2level_size50_23_configbus0[2049:2049], mux_2level_size50_23_configbus1[2049:2049] , mux_2level_size50_23_configbus0_b[2049:2049] ); -direct_interc direct_interc_173_ (mode_clb___clk_0_, fle_3___clk_0_ ); -wire [0:49] in_bus_mux_2level_size50_24_ ; -assign in_bus_mux_2level_size50_24_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_24_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_24_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_24_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_24_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_24_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_24_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_24_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_24_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_24_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_24_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_24_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_24_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_24_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_24_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_24_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_24_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_24_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_24_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_24_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_24_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_24_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_24_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_24_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_24_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_24_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_24_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_24_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_24_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_24_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_24_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_24_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_24_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_24_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_24_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_24_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_24_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_24_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_24_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_24_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_24_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_24_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_24_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_24_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_24_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_24_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_24_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_24_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_24_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_24_[49] = fle_9___out_0_ ; -wire [2050:2065] mux_2level_size50_24_configbus0; -wire [2050:2065] mux_2level_size50_24_configbus1; -wire [2050:2065] mux_2level_size50_24_sram_blwl_out ; -wire [2050:2065] mux_2level_size50_24_sram_blwl_outb ; -assign mux_2level_size50_24_configbus0[2050:2065] = sram_blwl_bl[2050:2065] ; -assign mux_2level_size50_24_configbus1[2050:2065] = sram_blwl_wl[2050:2065] ; -wire [2050:2065] mux_2level_size50_24_configbus0_b; -assign mux_2level_size50_24_configbus0_b[2050:2065] = sram_blwl_blb[2050:2065] ; -mux_2level_size50 mux_2level_size50_24_ (in_bus_mux_2level_size50_24_, fle_4___in_0_, mux_2level_size50_24_sram_blwl_out[2050:2065] , -mux_2level_size50_24_sram_blwl_outb[2050:2065] ); -//----- SRAM bits for MUX[24], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2050_ (mux_2level_size50_24_sram_blwl_out[2050:2050] ,mux_2level_size50_24_sram_blwl_out[2050:2050] ,mux_2level_size50_24_sram_blwl_outb[2050:2050] ,mux_2level_size50_24_configbus0[2050:2050], mux_2level_size50_24_configbus1[2050:2050] , mux_2level_size50_24_configbus0_b[2050:2050] ); -sram6T_blwl sram_blwl_2051_ (mux_2level_size50_24_sram_blwl_out[2051:2051] ,mux_2level_size50_24_sram_blwl_out[2051:2051] ,mux_2level_size50_24_sram_blwl_outb[2051:2051] ,mux_2level_size50_24_configbus0[2051:2051], mux_2level_size50_24_configbus1[2051:2051] , mux_2level_size50_24_configbus0_b[2051:2051] ); -sram6T_blwl sram_blwl_2052_ (mux_2level_size50_24_sram_blwl_out[2052:2052] ,mux_2level_size50_24_sram_blwl_out[2052:2052] ,mux_2level_size50_24_sram_blwl_outb[2052:2052] ,mux_2level_size50_24_configbus0[2052:2052], mux_2level_size50_24_configbus1[2052:2052] , mux_2level_size50_24_configbus0_b[2052:2052] ); -sram6T_blwl sram_blwl_2053_ (mux_2level_size50_24_sram_blwl_out[2053:2053] ,mux_2level_size50_24_sram_blwl_out[2053:2053] ,mux_2level_size50_24_sram_blwl_outb[2053:2053] ,mux_2level_size50_24_configbus0[2053:2053], mux_2level_size50_24_configbus1[2053:2053] , mux_2level_size50_24_configbus0_b[2053:2053] ); -sram6T_blwl sram_blwl_2054_ (mux_2level_size50_24_sram_blwl_out[2054:2054] ,mux_2level_size50_24_sram_blwl_out[2054:2054] ,mux_2level_size50_24_sram_blwl_outb[2054:2054] ,mux_2level_size50_24_configbus0[2054:2054], mux_2level_size50_24_configbus1[2054:2054] , mux_2level_size50_24_configbus0_b[2054:2054] ); -sram6T_blwl sram_blwl_2055_ (mux_2level_size50_24_sram_blwl_out[2055:2055] ,mux_2level_size50_24_sram_blwl_out[2055:2055] ,mux_2level_size50_24_sram_blwl_outb[2055:2055] ,mux_2level_size50_24_configbus0[2055:2055], mux_2level_size50_24_configbus1[2055:2055] , mux_2level_size50_24_configbus0_b[2055:2055] ); -sram6T_blwl sram_blwl_2056_ (mux_2level_size50_24_sram_blwl_out[2056:2056] ,mux_2level_size50_24_sram_blwl_out[2056:2056] ,mux_2level_size50_24_sram_blwl_outb[2056:2056] ,mux_2level_size50_24_configbus0[2056:2056], mux_2level_size50_24_configbus1[2056:2056] , mux_2level_size50_24_configbus0_b[2056:2056] ); -sram6T_blwl sram_blwl_2057_ (mux_2level_size50_24_sram_blwl_out[2057:2057] ,mux_2level_size50_24_sram_blwl_out[2057:2057] ,mux_2level_size50_24_sram_blwl_outb[2057:2057] ,mux_2level_size50_24_configbus0[2057:2057], mux_2level_size50_24_configbus1[2057:2057] , mux_2level_size50_24_configbus0_b[2057:2057] ); -sram6T_blwl sram_blwl_2058_ (mux_2level_size50_24_sram_blwl_out[2058:2058] ,mux_2level_size50_24_sram_blwl_out[2058:2058] ,mux_2level_size50_24_sram_blwl_outb[2058:2058] ,mux_2level_size50_24_configbus0[2058:2058], mux_2level_size50_24_configbus1[2058:2058] , mux_2level_size50_24_configbus0_b[2058:2058] ); -sram6T_blwl sram_blwl_2059_ (mux_2level_size50_24_sram_blwl_out[2059:2059] ,mux_2level_size50_24_sram_blwl_out[2059:2059] ,mux_2level_size50_24_sram_blwl_outb[2059:2059] ,mux_2level_size50_24_configbus0[2059:2059], mux_2level_size50_24_configbus1[2059:2059] , mux_2level_size50_24_configbus0_b[2059:2059] ); -sram6T_blwl sram_blwl_2060_ (mux_2level_size50_24_sram_blwl_out[2060:2060] ,mux_2level_size50_24_sram_blwl_out[2060:2060] ,mux_2level_size50_24_sram_blwl_outb[2060:2060] ,mux_2level_size50_24_configbus0[2060:2060], mux_2level_size50_24_configbus1[2060:2060] , mux_2level_size50_24_configbus0_b[2060:2060] ); -sram6T_blwl sram_blwl_2061_ (mux_2level_size50_24_sram_blwl_out[2061:2061] ,mux_2level_size50_24_sram_blwl_out[2061:2061] ,mux_2level_size50_24_sram_blwl_outb[2061:2061] ,mux_2level_size50_24_configbus0[2061:2061], mux_2level_size50_24_configbus1[2061:2061] , mux_2level_size50_24_configbus0_b[2061:2061] ); -sram6T_blwl sram_blwl_2062_ (mux_2level_size50_24_sram_blwl_out[2062:2062] ,mux_2level_size50_24_sram_blwl_out[2062:2062] ,mux_2level_size50_24_sram_blwl_outb[2062:2062] ,mux_2level_size50_24_configbus0[2062:2062], mux_2level_size50_24_configbus1[2062:2062] , mux_2level_size50_24_configbus0_b[2062:2062] ); -sram6T_blwl sram_blwl_2063_ (mux_2level_size50_24_sram_blwl_out[2063:2063] ,mux_2level_size50_24_sram_blwl_out[2063:2063] ,mux_2level_size50_24_sram_blwl_outb[2063:2063] ,mux_2level_size50_24_configbus0[2063:2063], mux_2level_size50_24_configbus1[2063:2063] , mux_2level_size50_24_configbus0_b[2063:2063] ); -sram6T_blwl sram_blwl_2064_ (mux_2level_size50_24_sram_blwl_out[2064:2064] ,mux_2level_size50_24_sram_blwl_out[2064:2064] ,mux_2level_size50_24_sram_blwl_outb[2064:2064] ,mux_2level_size50_24_configbus0[2064:2064], mux_2level_size50_24_configbus1[2064:2064] , mux_2level_size50_24_configbus0_b[2064:2064] ); -sram6T_blwl sram_blwl_2065_ (mux_2level_size50_24_sram_blwl_out[2065:2065] ,mux_2level_size50_24_sram_blwl_out[2065:2065] ,mux_2level_size50_24_sram_blwl_outb[2065:2065] ,mux_2level_size50_24_configbus0[2065:2065], mux_2level_size50_24_configbus1[2065:2065] , mux_2level_size50_24_configbus0_b[2065:2065] ); -wire [0:49] in_bus_mux_2level_size50_25_ ; -assign in_bus_mux_2level_size50_25_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_25_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_25_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_25_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_25_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_25_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_25_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_25_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_25_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_25_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_25_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_25_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_25_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_25_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_25_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_25_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_25_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_25_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_25_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_25_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_25_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_25_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_25_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_25_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_25_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_25_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_25_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_25_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_25_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_25_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_25_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_25_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_25_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_25_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_25_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_25_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_25_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_25_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_25_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_25_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_25_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_25_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_25_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_25_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_25_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_25_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_25_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_25_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_25_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_25_[49] = fle_9___out_0_ ; -wire [2066:2081] mux_2level_size50_25_configbus0; -wire [2066:2081] mux_2level_size50_25_configbus1; -wire [2066:2081] mux_2level_size50_25_sram_blwl_out ; -wire [2066:2081] mux_2level_size50_25_sram_blwl_outb ; -assign mux_2level_size50_25_configbus0[2066:2081] = sram_blwl_bl[2066:2081] ; -assign mux_2level_size50_25_configbus1[2066:2081] = sram_blwl_wl[2066:2081] ; -wire [2066:2081] mux_2level_size50_25_configbus0_b; -assign mux_2level_size50_25_configbus0_b[2066:2081] = sram_blwl_blb[2066:2081] ; -mux_2level_size50 mux_2level_size50_25_ (in_bus_mux_2level_size50_25_, fle_4___in_1_, mux_2level_size50_25_sram_blwl_out[2066:2081] , -mux_2level_size50_25_sram_blwl_outb[2066:2081] ); -//----- SRAM bits for MUX[25], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2066_ (mux_2level_size50_25_sram_blwl_out[2066:2066] ,mux_2level_size50_25_sram_blwl_out[2066:2066] ,mux_2level_size50_25_sram_blwl_outb[2066:2066] ,mux_2level_size50_25_configbus0[2066:2066], mux_2level_size50_25_configbus1[2066:2066] , mux_2level_size50_25_configbus0_b[2066:2066] ); -sram6T_blwl sram_blwl_2067_ (mux_2level_size50_25_sram_blwl_out[2067:2067] ,mux_2level_size50_25_sram_blwl_out[2067:2067] ,mux_2level_size50_25_sram_blwl_outb[2067:2067] ,mux_2level_size50_25_configbus0[2067:2067], mux_2level_size50_25_configbus1[2067:2067] , mux_2level_size50_25_configbus0_b[2067:2067] ); -sram6T_blwl sram_blwl_2068_ (mux_2level_size50_25_sram_blwl_out[2068:2068] ,mux_2level_size50_25_sram_blwl_out[2068:2068] ,mux_2level_size50_25_sram_blwl_outb[2068:2068] ,mux_2level_size50_25_configbus0[2068:2068], mux_2level_size50_25_configbus1[2068:2068] , mux_2level_size50_25_configbus0_b[2068:2068] ); -sram6T_blwl sram_blwl_2069_ (mux_2level_size50_25_sram_blwl_out[2069:2069] ,mux_2level_size50_25_sram_blwl_out[2069:2069] ,mux_2level_size50_25_sram_blwl_outb[2069:2069] ,mux_2level_size50_25_configbus0[2069:2069], mux_2level_size50_25_configbus1[2069:2069] , mux_2level_size50_25_configbus0_b[2069:2069] ); -sram6T_blwl sram_blwl_2070_ (mux_2level_size50_25_sram_blwl_out[2070:2070] ,mux_2level_size50_25_sram_blwl_out[2070:2070] ,mux_2level_size50_25_sram_blwl_outb[2070:2070] ,mux_2level_size50_25_configbus0[2070:2070], mux_2level_size50_25_configbus1[2070:2070] , mux_2level_size50_25_configbus0_b[2070:2070] ); -sram6T_blwl sram_blwl_2071_ (mux_2level_size50_25_sram_blwl_out[2071:2071] ,mux_2level_size50_25_sram_blwl_out[2071:2071] ,mux_2level_size50_25_sram_blwl_outb[2071:2071] ,mux_2level_size50_25_configbus0[2071:2071], mux_2level_size50_25_configbus1[2071:2071] , mux_2level_size50_25_configbus0_b[2071:2071] ); -sram6T_blwl sram_blwl_2072_ (mux_2level_size50_25_sram_blwl_out[2072:2072] ,mux_2level_size50_25_sram_blwl_out[2072:2072] ,mux_2level_size50_25_sram_blwl_outb[2072:2072] ,mux_2level_size50_25_configbus0[2072:2072], mux_2level_size50_25_configbus1[2072:2072] , mux_2level_size50_25_configbus0_b[2072:2072] ); -sram6T_blwl sram_blwl_2073_ (mux_2level_size50_25_sram_blwl_out[2073:2073] ,mux_2level_size50_25_sram_blwl_out[2073:2073] ,mux_2level_size50_25_sram_blwl_outb[2073:2073] ,mux_2level_size50_25_configbus0[2073:2073], mux_2level_size50_25_configbus1[2073:2073] , mux_2level_size50_25_configbus0_b[2073:2073] ); -sram6T_blwl sram_blwl_2074_ (mux_2level_size50_25_sram_blwl_out[2074:2074] ,mux_2level_size50_25_sram_blwl_out[2074:2074] ,mux_2level_size50_25_sram_blwl_outb[2074:2074] ,mux_2level_size50_25_configbus0[2074:2074], mux_2level_size50_25_configbus1[2074:2074] , mux_2level_size50_25_configbus0_b[2074:2074] ); -sram6T_blwl sram_blwl_2075_ (mux_2level_size50_25_sram_blwl_out[2075:2075] ,mux_2level_size50_25_sram_blwl_out[2075:2075] ,mux_2level_size50_25_sram_blwl_outb[2075:2075] ,mux_2level_size50_25_configbus0[2075:2075], mux_2level_size50_25_configbus1[2075:2075] , mux_2level_size50_25_configbus0_b[2075:2075] ); -sram6T_blwl sram_blwl_2076_ (mux_2level_size50_25_sram_blwl_out[2076:2076] ,mux_2level_size50_25_sram_blwl_out[2076:2076] ,mux_2level_size50_25_sram_blwl_outb[2076:2076] ,mux_2level_size50_25_configbus0[2076:2076], mux_2level_size50_25_configbus1[2076:2076] , mux_2level_size50_25_configbus0_b[2076:2076] ); -sram6T_blwl sram_blwl_2077_ (mux_2level_size50_25_sram_blwl_out[2077:2077] ,mux_2level_size50_25_sram_blwl_out[2077:2077] ,mux_2level_size50_25_sram_blwl_outb[2077:2077] ,mux_2level_size50_25_configbus0[2077:2077], mux_2level_size50_25_configbus1[2077:2077] , mux_2level_size50_25_configbus0_b[2077:2077] ); -sram6T_blwl sram_blwl_2078_ (mux_2level_size50_25_sram_blwl_out[2078:2078] ,mux_2level_size50_25_sram_blwl_out[2078:2078] ,mux_2level_size50_25_sram_blwl_outb[2078:2078] ,mux_2level_size50_25_configbus0[2078:2078], mux_2level_size50_25_configbus1[2078:2078] , mux_2level_size50_25_configbus0_b[2078:2078] ); -sram6T_blwl sram_blwl_2079_ (mux_2level_size50_25_sram_blwl_out[2079:2079] ,mux_2level_size50_25_sram_blwl_out[2079:2079] ,mux_2level_size50_25_sram_blwl_outb[2079:2079] ,mux_2level_size50_25_configbus0[2079:2079], mux_2level_size50_25_configbus1[2079:2079] , mux_2level_size50_25_configbus0_b[2079:2079] ); -sram6T_blwl sram_blwl_2080_ (mux_2level_size50_25_sram_blwl_out[2080:2080] ,mux_2level_size50_25_sram_blwl_out[2080:2080] ,mux_2level_size50_25_sram_blwl_outb[2080:2080] ,mux_2level_size50_25_configbus0[2080:2080], mux_2level_size50_25_configbus1[2080:2080] , mux_2level_size50_25_configbus0_b[2080:2080] ); -sram6T_blwl sram_blwl_2081_ (mux_2level_size50_25_sram_blwl_out[2081:2081] ,mux_2level_size50_25_sram_blwl_out[2081:2081] ,mux_2level_size50_25_sram_blwl_outb[2081:2081] ,mux_2level_size50_25_configbus0[2081:2081], mux_2level_size50_25_configbus1[2081:2081] , mux_2level_size50_25_configbus0_b[2081:2081] ); -wire [0:49] in_bus_mux_2level_size50_26_ ; -assign in_bus_mux_2level_size50_26_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_26_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_26_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_26_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_26_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_26_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_26_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_26_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_26_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_26_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_26_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_26_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_26_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_26_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_26_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_26_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_26_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_26_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_26_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_26_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_26_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_26_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_26_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_26_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_26_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_26_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_26_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_26_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_26_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_26_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_26_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_26_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_26_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_26_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_26_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_26_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_26_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_26_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_26_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_26_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_26_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_26_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_26_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_26_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_26_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_26_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_26_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_26_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_26_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_26_[49] = fle_9___out_0_ ; -wire [2082:2097] mux_2level_size50_26_configbus0; -wire [2082:2097] mux_2level_size50_26_configbus1; -wire [2082:2097] mux_2level_size50_26_sram_blwl_out ; -wire [2082:2097] mux_2level_size50_26_sram_blwl_outb ; -assign mux_2level_size50_26_configbus0[2082:2097] = sram_blwl_bl[2082:2097] ; -assign mux_2level_size50_26_configbus1[2082:2097] = sram_blwl_wl[2082:2097] ; -wire [2082:2097] mux_2level_size50_26_configbus0_b; -assign mux_2level_size50_26_configbus0_b[2082:2097] = sram_blwl_blb[2082:2097] ; -mux_2level_size50 mux_2level_size50_26_ (in_bus_mux_2level_size50_26_, fle_4___in_2_, mux_2level_size50_26_sram_blwl_out[2082:2097] , -mux_2level_size50_26_sram_blwl_outb[2082:2097] ); -//----- SRAM bits for MUX[26], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2082_ (mux_2level_size50_26_sram_blwl_out[2082:2082] ,mux_2level_size50_26_sram_blwl_out[2082:2082] ,mux_2level_size50_26_sram_blwl_outb[2082:2082] ,mux_2level_size50_26_configbus0[2082:2082], mux_2level_size50_26_configbus1[2082:2082] , mux_2level_size50_26_configbus0_b[2082:2082] ); -sram6T_blwl sram_blwl_2083_ (mux_2level_size50_26_sram_blwl_out[2083:2083] ,mux_2level_size50_26_sram_blwl_out[2083:2083] ,mux_2level_size50_26_sram_blwl_outb[2083:2083] ,mux_2level_size50_26_configbus0[2083:2083], mux_2level_size50_26_configbus1[2083:2083] , mux_2level_size50_26_configbus0_b[2083:2083] ); -sram6T_blwl sram_blwl_2084_ (mux_2level_size50_26_sram_blwl_out[2084:2084] ,mux_2level_size50_26_sram_blwl_out[2084:2084] ,mux_2level_size50_26_sram_blwl_outb[2084:2084] ,mux_2level_size50_26_configbus0[2084:2084], mux_2level_size50_26_configbus1[2084:2084] , mux_2level_size50_26_configbus0_b[2084:2084] ); -sram6T_blwl sram_blwl_2085_ (mux_2level_size50_26_sram_blwl_out[2085:2085] ,mux_2level_size50_26_sram_blwl_out[2085:2085] ,mux_2level_size50_26_sram_blwl_outb[2085:2085] ,mux_2level_size50_26_configbus0[2085:2085], mux_2level_size50_26_configbus1[2085:2085] , mux_2level_size50_26_configbus0_b[2085:2085] ); -sram6T_blwl sram_blwl_2086_ (mux_2level_size50_26_sram_blwl_out[2086:2086] ,mux_2level_size50_26_sram_blwl_out[2086:2086] ,mux_2level_size50_26_sram_blwl_outb[2086:2086] ,mux_2level_size50_26_configbus0[2086:2086], mux_2level_size50_26_configbus1[2086:2086] , mux_2level_size50_26_configbus0_b[2086:2086] ); -sram6T_blwl sram_blwl_2087_ (mux_2level_size50_26_sram_blwl_out[2087:2087] ,mux_2level_size50_26_sram_blwl_out[2087:2087] ,mux_2level_size50_26_sram_blwl_outb[2087:2087] ,mux_2level_size50_26_configbus0[2087:2087], mux_2level_size50_26_configbus1[2087:2087] , mux_2level_size50_26_configbus0_b[2087:2087] ); -sram6T_blwl sram_blwl_2088_ (mux_2level_size50_26_sram_blwl_out[2088:2088] ,mux_2level_size50_26_sram_blwl_out[2088:2088] ,mux_2level_size50_26_sram_blwl_outb[2088:2088] ,mux_2level_size50_26_configbus0[2088:2088], mux_2level_size50_26_configbus1[2088:2088] , mux_2level_size50_26_configbus0_b[2088:2088] ); -sram6T_blwl sram_blwl_2089_ (mux_2level_size50_26_sram_blwl_out[2089:2089] ,mux_2level_size50_26_sram_blwl_out[2089:2089] ,mux_2level_size50_26_sram_blwl_outb[2089:2089] ,mux_2level_size50_26_configbus0[2089:2089], mux_2level_size50_26_configbus1[2089:2089] , mux_2level_size50_26_configbus0_b[2089:2089] ); -sram6T_blwl sram_blwl_2090_ (mux_2level_size50_26_sram_blwl_out[2090:2090] ,mux_2level_size50_26_sram_blwl_out[2090:2090] ,mux_2level_size50_26_sram_blwl_outb[2090:2090] ,mux_2level_size50_26_configbus0[2090:2090], mux_2level_size50_26_configbus1[2090:2090] , mux_2level_size50_26_configbus0_b[2090:2090] ); -sram6T_blwl sram_blwl_2091_ (mux_2level_size50_26_sram_blwl_out[2091:2091] ,mux_2level_size50_26_sram_blwl_out[2091:2091] ,mux_2level_size50_26_sram_blwl_outb[2091:2091] ,mux_2level_size50_26_configbus0[2091:2091], mux_2level_size50_26_configbus1[2091:2091] , mux_2level_size50_26_configbus0_b[2091:2091] ); -sram6T_blwl sram_blwl_2092_ (mux_2level_size50_26_sram_blwl_out[2092:2092] ,mux_2level_size50_26_sram_blwl_out[2092:2092] ,mux_2level_size50_26_sram_blwl_outb[2092:2092] ,mux_2level_size50_26_configbus0[2092:2092], mux_2level_size50_26_configbus1[2092:2092] , mux_2level_size50_26_configbus0_b[2092:2092] ); -sram6T_blwl sram_blwl_2093_ (mux_2level_size50_26_sram_blwl_out[2093:2093] ,mux_2level_size50_26_sram_blwl_out[2093:2093] ,mux_2level_size50_26_sram_blwl_outb[2093:2093] ,mux_2level_size50_26_configbus0[2093:2093], mux_2level_size50_26_configbus1[2093:2093] , mux_2level_size50_26_configbus0_b[2093:2093] ); -sram6T_blwl sram_blwl_2094_ (mux_2level_size50_26_sram_blwl_out[2094:2094] ,mux_2level_size50_26_sram_blwl_out[2094:2094] ,mux_2level_size50_26_sram_blwl_outb[2094:2094] ,mux_2level_size50_26_configbus0[2094:2094], mux_2level_size50_26_configbus1[2094:2094] , mux_2level_size50_26_configbus0_b[2094:2094] ); -sram6T_blwl sram_blwl_2095_ (mux_2level_size50_26_sram_blwl_out[2095:2095] ,mux_2level_size50_26_sram_blwl_out[2095:2095] ,mux_2level_size50_26_sram_blwl_outb[2095:2095] ,mux_2level_size50_26_configbus0[2095:2095], mux_2level_size50_26_configbus1[2095:2095] , mux_2level_size50_26_configbus0_b[2095:2095] ); -sram6T_blwl sram_blwl_2096_ (mux_2level_size50_26_sram_blwl_out[2096:2096] ,mux_2level_size50_26_sram_blwl_out[2096:2096] ,mux_2level_size50_26_sram_blwl_outb[2096:2096] ,mux_2level_size50_26_configbus0[2096:2096], mux_2level_size50_26_configbus1[2096:2096] , mux_2level_size50_26_configbus0_b[2096:2096] ); -sram6T_blwl sram_blwl_2097_ (mux_2level_size50_26_sram_blwl_out[2097:2097] ,mux_2level_size50_26_sram_blwl_out[2097:2097] ,mux_2level_size50_26_sram_blwl_outb[2097:2097] ,mux_2level_size50_26_configbus0[2097:2097], mux_2level_size50_26_configbus1[2097:2097] , mux_2level_size50_26_configbus0_b[2097:2097] ); -wire [0:49] in_bus_mux_2level_size50_27_ ; -assign in_bus_mux_2level_size50_27_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_27_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_27_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_27_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_27_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_27_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_27_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_27_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_27_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_27_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_27_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_27_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_27_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_27_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_27_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_27_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_27_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_27_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_27_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_27_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_27_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_27_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_27_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_27_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_27_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_27_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_27_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_27_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_27_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_27_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_27_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_27_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_27_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_27_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_27_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_27_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_27_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_27_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_27_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_27_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_27_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_27_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_27_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_27_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_27_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_27_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_27_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_27_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_27_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_27_[49] = fle_9___out_0_ ; -wire [2098:2113] mux_2level_size50_27_configbus0; -wire [2098:2113] mux_2level_size50_27_configbus1; -wire [2098:2113] mux_2level_size50_27_sram_blwl_out ; -wire [2098:2113] mux_2level_size50_27_sram_blwl_outb ; -assign mux_2level_size50_27_configbus0[2098:2113] = sram_blwl_bl[2098:2113] ; -assign mux_2level_size50_27_configbus1[2098:2113] = sram_blwl_wl[2098:2113] ; -wire [2098:2113] mux_2level_size50_27_configbus0_b; -assign mux_2level_size50_27_configbus0_b[2098:2113] = sram_blwl_blb[2098:2113] ; -mux_2level_size50 mux_2level_size50_27_ (in_bus_mux_2level_size50_27_, fle_4___in_3_, mux_2level_size50_27_sram_blwl_out[2098:2113] , -mux_2level_size50_27_sram_blwl_outb[2098:2113] ); -//----- SRAM bits for MUX[27], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2098_ (mux_2level_size50_27_sram_blwl_out[2098:2098] ,mux_2level_size50_27_sram_blwl_out[2098:2098] ,mux_2level_size50_27_sram_blwl_outb[2098:2098] ,mux_2level_size50_27_configbus0[2098:2098], mux_2level_size50_27_configbus1[2098:2098] , mux_2level_size50_27_configbus0_b[2098:2098] ); -sram6T_blwl sram_blwl_2099_ (mux_2level_size50_27_sram_blwl_out[2099:2099] ,mux_2level_size50_27_sram_blwl_out[2099:2099] ,mux_2level_size50_27_sram_blwl_outb[2099:2099] ,mux_2level_size50_27_configbus0[2099:2099], mux_2level_size50_27_configbus1[2099:2099] , mux_2level_size50_27_configbus0_b[2099:2099] ); -sram6T_blwl sram_blwl_2100_ (mux_2level_size50_27_sram_blwl_out[2100:2100] ,mux_2level_size50_27_sram_blwl_out[2100:2100] ,mux_2level_size50_27_sram_blwl_outb[2100:2100] ,mux_2level_size50_27_configbus0[2100:2100], mux_2level_size50_27_configbus1[2100:2100] , mux_2level_size50_27_configbus0_b[2100:2100] ); -sram6T_blwl sram_blwl_2101_ (mux_2level_size50_27_sram_blwl_out[2101:2101] ,mux_2level_size50_27_sram_blwl_out[2101:2101] ,mux_2level_size50_27_sram_blwl_outb[2101:2101] ,mux_2level_size50_27_configbus0[2101:2101], mux_2level_size50_27_configbus1[2101:2101] , mux_2level_size50_27_configbus0_b[2101:2101] ); -sram6T_blwl sram_blwl_2102_ (mux_2level_size50_27_sram_blwl_out[2102:2102] ,mux_2level_size50_27_sram_blwl_out[2102:2102] ,mux_2level_size50_27_sram_blwl_outb[2102:2102] ,mux_2level_size50_27_configbus0[2102:2102], mux_2level_size50_27_configbus1[2102:2102] , mux_2level_size50_27_configbus0_b[2102:2102] ); -sram6T_blwl sram_blwl_2103_ (mux_2level_size50_27_sram_blwl_out[2103:2103] ,mux_2level_size50_27_sram_blwl_out[2103:2103] ,mux_2level_size50_27_sram_blwl_outb[2103:2103] ,mux_2level_size50_27_configbus0[2103:2103], mux_2level_size50_27_configbus1[2103:2103] , mux_2level_size50_27_configbus0_b[2103:2103] ); -sram6T_blwl sram_blwl_2104_ (mux_2level_size50_27_sram_blwl_out[2104:2104] ,mux_2level_size50_27_sram_blwl_out[2104:2104] ,mux_2level_size50_27_sram_blwl_outb[2104:2104] ,mux_2level_size50_27_configbus0[2104:2104], mux_2level_size50_27_configbus1[2104:2104] , mux_2level_size50_27_configbus0_b[2104:2104] ); -sram6T_blwl sram_blwl_2105_ (mux_2level_size50_27_sram_blwl_out[2105:2105] ,mux_2level_size50_27_sram_blwl_out[2105:2105] ,mux_2level_size50_27_sram_blwl_outb[2105:2105] ,mux_2level_size50_27_configbus0[2105:2105], mux_2level_size50_27_configbus1[2105:2105] , mux_2level_size50_27_configbus0_b[2105:2105] ); -sram6T_blwl sram_blwl_2106_ (mux_2level_size50_27_sram_blwl_out[2106:2106] ,mux_2level_size50_27_sram_blwl_out[2106:2106] ,mux_2level_size50_27_sram_blwl_outb[2106:2106] ,mux_2level_size50_27_configbus0[2106:2106], mux_2level_size50_27_configbus1[2106:2106] , mux_2level_size50_27_configbus0_b[2106:2106] ); -sram6T_blwl sram_blwl_2107_ (mux_2level_size50_27_sram_blwl_out[2107:2107] ,mux_2level_size50_27_sram_blwl_out[2107:2107] ,mux_2level_size50_27_sram_blwl_outb[2107:2107] ,mux_2level_size50_27_configbus0[2107:2107], mux_2level_size50_27_configbus1[2107:2107] , mux_2level_size50_27_configbus0_b[2107:2107] ); -sram6T_blwl sram_blwl_2108_ (mux_2level_size50_27_sram_blwl_out[2108:2108] ,mux_2level_size50_27_sram_blwl_out[2108:2108] ,mux_2level_size50_27_sram_blwl_outb[2108:2108] ,mux_2level_size50_27_configbus0[2108:2108], mux_2level_size50_27_configbus1[2108:2108] , mux_2level_size50_27_configbus0_b[2108:2108] ); -sram6T_blwl sram_blwl_2109_ (mux_2level_size50_27_sram_blwl_out[2109:2109] ,mux_2level_size50_27_sram_blwl_out[2109:2109] ,mux_2level_size50_27_sram_blwl_outb[2109:2109] ,mux_2level_size50_27_configbus0[2109:2109], mux_2level_size50_27_configbus1[2109:2109] , mux_2level_size50_27_configbus0_b[2109:2109] ); -sram6T_blwl sram_blwl_2110_ (mux_2level_size50_27_sram_blwl_out[2110:2110] ,mux_2level_size50_27_sram_blwl_out[2110:2110] ,mux_2level_size50_27_sram_blwl_outb[2110:2110] ,mux_2level_size50_27_configbus0[2110:2110], mux_2level_size50_27_configbus1[2110:2110] , mux_2level_size50_27_configbus0_b[2110:2110] ); -sram6T_blwl sram_blwl_2111_ (mux_2level_size50_27_sram_blwl_out[2111:2111] ,mux_2level_size50_27_sram_blwl_out[2111:2111] ,mux_2level_size50_27_sram_blwl_outb[2111:2111] ,mux_2level_size50_27_configbus0[2111:2111], mux_2level_size50_27_configbus1[2111:2111] , mux_2level_size50_27_configbus0_b[2111:2111] ); -sram6T_blwl sram_blwl_2112_ (mux_2level_size50_27_sram_blwl_out[2112:2112] ,mux_2level_size50_27_sram_blwl_out[2112:2112] ,mux_2level_size50_27_sram_blwl_outb[2112:2112] ,mux_2level_size50_27_configbus0[2112:2112], mux_2level_size50_27_configbus1[2112:2112] , mux_2level_size50_27_configbus0_b[2112:2112] ); -sram6T_blwl sram_blwl_2113_ (mux_2level_size50_27_sram_blwl_out[2113:2113] ,mux_2level_size50_27_sram_blwl_out[2113:2113] ,mux_2level_size50_27_sram_blwl_outb[2113:2113] ,mux_2level_size50_27_configbus0[2113:2113], mux_2level_size50_27_configbus1[2113:2113] , mux_2level_size50_27_configbus0_b[2113:2113] ); -wire [0:49] in_bus_mux_2level_size50_28_ ; -assign in_bus_mux_2level_size50_28_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_28_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_28_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_28_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_28_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_28_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_28_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_28_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_28_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_28_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_28_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_28_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_28_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_28_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_28_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_28_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_28_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_28_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_28_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_28_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_28_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_28_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_28_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_28_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_28_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_28_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_28_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_28_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_28_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_28_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_28_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_28_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_28_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_28_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_28_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_28_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_28_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_28_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_28_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_28_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_28_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_28_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_28_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_28_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_28_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_28_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_28_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_28_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_28_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_28_[49] = fle_9___out_0_ ; -wire [2114:2129] mux_2level_size50_28_configbus0; -wire [2114:2129] mux_2level_size50_28_configbus1; -wire [2114:2129] mux_2level_size50_28_sram_blwl_out ; -wire [2114:2129] mux_2level_size50_28_sram_blwl_outb ; -assign mux_2level_size50_28_configbus0[2114:2129] = sram_blwl_bl[2114:2129] ; -assign mux_2level_size50_28_configbus1[2114:2129] = sram_blwl_wl[2114:2129] ; -wire [2114:2129] mux_2level_size50_28_configbus0_b; -assign mux_2level_size50_28_configbus0_b[2114:2129] = sram_blwl_blb[2114:2129] ; -mux_2level_size50 mux_2level_size50_28_ (in_bus_mux_2level_size50_28_, fle_4___in_4_, mux_2level_size50_28_sram_blwl_out[2114:2129] , -mux_2level_size50_28_sram_blwl_outb[2114:2129] ); -//----- SRAM bits for MUX[28], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2114_ (mux_2level_size50_28_sram_blwl_out[2114:2114] ,mux_2level_size50_28_sram_blwl_out[2114:2114] ,mux_2level_size50_28_sram_blwl_outb[2114:2114] ,mux_2level_size50_28_configbus0[2114:2114], mux_2level_size50_28_configbus1[2114:2114] , mux_2level_size50_28_configbus0_b[2114:2114] ); -sram6T_blwl sram_blwl_2115_ (mux_2level_size50_28_sram_blwl_out[2115:2115] ,mux_2level_size50_28_sram_blwl_out[2115:2115] ,mux_2level_size50_28_sram_blwl_outb[2115:2115] ,mux_2level_size50_28_configbus0[2115:2115], mux_2level_size50_28_configbus1[2115:2115] , mux_2level_size50_28_configbus0_b[2115:2115] ); -sram6T_blwl sram_blwl_2116_ (mux_2level_size50_28_sram_blwl_out[2116:2116] ,mux_2level_size50_28_sram_blwl_out[2116:2116] ,mux_2level_size50_28_sram_blwl_outb[2116:2116] ,mux_2level_size50_28_configbus0[2116:2116], mux_2level_size50_28_configbus1[2116:2116] , mux_2level_size50_28_configbus0_b[2116:2116] ); -sram6T_blwl sram_blwl_2117_ (mux_2level_size50_28_sram_blwl_out[2117:2117] ,mux_2level_size50_28_sram_blwl_out[2117:2117] ,mux_2level_size50_28_sram_blwl_outb[2117:2117] ,mux_2level_size50_28_configbus0[2117:2117], mux_2level_size50_28_configbus1[2117:2117] , mux_2level_size50_28_configbus0_b[2117:2117] ); -sram6T_blwl sram_blwl_2118_ (mux_2level_size50_28_sram_blwl_out[2118:2118] ,mux_2level_size50_28_sram_blwl_out[2118:2118] ,mux_2level_size50_28_sram_blwl_outb[2118:2118] ,mux_2level_size50_28_configbus0[2118:2118], mux_2level_size50_28_configbus1[2118:2118] , mux_2level_size50_28_configbus0_b[2118:2118] ); -sram6T_blwl sram_blwl_2119_ (mux_2level_size50_28_sram_blwl_out[2119:2119] ,mux_2level_size50_28_sram_blwl_out[2119:2119] ,mux_2level_size50_28_sram_blwl_outb[2119:2119] ,mux_2level_size50_28_configbus0[2119:2119], mux_2level_size50_28_configbus1[2119:2119] , mux_2level_size50_28_configbus0_b[2119:2119] ); -sram6T_blwl sram_blwl_2120_ (mux_2level_size50_28_sram_blwl_out[2120:2120] ,mux_2level_size50_28_sram_blwl_out[2120:2120] ,mux_2level_size50_28_sram_blwl_outb[2120:2120] ,mux_2level_size50_28_configbus0[2120:2120], mux_2level_size50_28_configbus1[2120:2120] , mux_2level_size50_28_configbus0_b[2120:2120] ); -sram6T_blwl sram_blwl_2121_ (mux_2level_size50_28_sram_blwl_out[2121:2121] ,mux_2level_size50_28_sram_blwl_out[2121:2121] ,mux_2level_size50_28_sram_blwl_outb[2121:2121] ,mux_2level_size50_28_configbus0[2121:2121], mux_2level_size50_28_configbus1[2121:2121] , mux_2level_size50_28_configbus0_b[2121:2121] ); -sram6T_blwl sram_blwl_2122_ (mux_2level_size50_28_sram_blwl_out[2122:2122] ,mux_2level_size50_28_sram_blwl_out[2122:2122] ,mux_2level_size50_28_sram_blwl_outb[2122:2122] ,mux_2level_size50_28_configbus0[2122:2122], mux_2level_size50_28_configbus1[2122:2122] , mux_2level_size50_28_configbus0_b[2122:2122] ); -sram6T_blwl sram_blwl_2123_ (mux_2level_size50_28_sram_blwl_out[2123:2123] ,mux_2level_size50_28_sram_blwl_out[2123:2123] ,mux_2level_size50_28_sram_blwl_outb[2123:2123] ,mux_2level_size50_28_configbus0[2123:2123], mux_2level_size50_28_configbus1[2123:2123] , mux_2level_size50_28_configbus0_b[2123:2123] ); -sram6T_blwl sram_blwl_2124_ (mux_2level_size50_28_sram_blwl_out[2124:2124] ,mux_2level_size50_28_sram_blwl_out[2124:2124] ,mux_2level_size50_28_sram_blwl_outb[2124:2124] ,mux_2level_size50_28_configbus0[2124:2124], mux_2level_size50_28_configbus1[2124:2124] , mux_2level_size50_28_configbus0_b[2124:2124] ); -sram6T_blwl sram_blwl_2125_ (mux_2level_size50_28_sram_blwl_out[2125:2125] ,mux_2level_size50_28_sram_blwl_out[2125:2125] ,mux_2level_size50_28_sram_blwl_outb[2125:2125] ,mux_2level_size50_28_configbus0[2125:2125], mux_2level_size50_28_configbus1[2125:2125] , mux_2level_size50_28_configbus0_b[2125:2125] ); -sram6T_blwl sram_blwl_2126_ (mux_2level_size50_28_sram_blwl_out[2126:2126] ,mux_2level_size50_28_sram_blwl_out[2126:2126] ,mux_2level_size50_28_sram_blwl_outb[2126:2126] ,mux_2level_size50_28_configbus0[2126:2126], mux_2level_size50_28_configbus1[2126:2126] , mux_2level_size50_28_configbus0_b[2126:2126] ); -sram6T_blwl sram_blwl_2127_ (mux_2level_size50_28_sram_blwl_out[2127:2127] ,mux_2level_size50_28_sram_blwl_out[2127:2127] ,mux_2level_size50_28_sram_blwl_outb[2127:2127] ,mux_2level_size50_28_configbus0[2127:2127], mux_2level_size50_28_configbus1[2127:2127] , mux_2level_size50_28_configbus0_b[2127:2127] ); -sram6T_blwl sram_blwl_2128_ (mux_2level_size50_28_sram_blwl_out[2128:2128] ,mux_2level_size50_28_sram_blwl_out[2128:2128] ,mux_2level_size50_28_sram_blwl_outb[2128:2128] ,mux_2level_size50_28_configbus0[2128:2128], mux_2level_size50_28_configbus1[2128:2128] , mux_2level_size50_28_configbus0_b[2128:2128] ); -sram6T_blwl sram_blwl_2129_ (mux_2level_size50_28_sram_blwl_out[2129:2129] ,mux_2level_size50_28_sram_blwl_out[2129:2129] ,mux_2level_size50_28_sram_blwl_outb[2129:2129] ,mux_2level_size50_28_configbus0[2129:2129], mux_2level_size50_28_configbus1[2129:2129] , mux_2level_size50_28_configbus0_b[2129:2129] ); -wire [0:49] in_bus_mux_2level_size50_29_ ; -assign in_bus_mux_2level_size50_29_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_29_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_29_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_29_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_29_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_29_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_29_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_29_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_29_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_29_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_29_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_29_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_29_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_29_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_29_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_29_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_29_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_29_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_29_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_29_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_29_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_29_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_29_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_29_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_29_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_29_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_29_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_29_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_29_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_29_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_29_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_29_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_29_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_29_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_29_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_29_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_29_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_29_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_29_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_29_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_29_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_29_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_29_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_29_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_29_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_29_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_29_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_29_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_29_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_29_[49] = fle_9___out_0_ ; -wire [2130:2145] mux_2level_size50_29_configbus0; -wire [2130:2145] mux_2level_size50_29_configbus1; -wire [2130:2145] mux_2level_size50_29_sram_blwl_out ; -wire [2130:2145] mux_2level_size50_29_sram_blwl_outb ; -assign mux_2level_size50_29_configbus0[2130:2145] = sram_blwl_bl[2130:2145] ; -assign mux_2level_size50_29_configbus1[2130:2145] = sram_blwl_wl[2130:2145] ; -wire [2130:2145] mux_2level_size50_29_configbus0_b; -assign mux_2level_size50_29_configbus0_b[2130:2145] = sram_blwl_blb[2130:2145] ; -mux_2level_size50 mux_2level_size50_29_ (in_bus_mux_2level_size50_29_, fle_4___in_5_, mux_2level_size50_29_sram_blwl_out[2130:2145] , -mux_2level_size50_29_sram_blwl_outb[2130:2145] ); -//----- SRAM bits for MUX[29], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2130_ (mux_2level_size50_29_sram_blwl_out[2130:2130] ,mux_2level_size50_29_sram_blwl_out[2130:2130] ,mux_2level_size50_29_sram_blwl_outb[2130:2130] ,mux_2level_size50_29_configbus0[2130:2130], mux_2level_size50_29_configbus1[2130:2130] , mux_2level_size50_29_configbus0_b[2130:2130] ); -sram6T_blwl sram_blwl_2131_ (mux_2level_size50_29_sram_blwl_out[2131:2131] ,mux_2level_size50_29_sram_blwl_out[2131:2131] ,mux_2level_size50_29_sram_blwl_outb[2131:2131] ,mux_2level_size50_29_configbus0[2131:2131], mux_2level_size50_29_configbus1[2131:2131] , mux_2level_size50_29_configbus0_b[2131:2131] ); -sram6T_blwl sram_blwl_2132_ (mux_2level_size50_29_sram_blwl_out[2132:2132] ,mux_2level_size50_29_sram_blwl_out[2132:2132] ,mux_2level_size50_29_sram_blwl_outb[2132:2132] ,mux_2level_size50_29_configbus0[2132:2132], mux_2level_size50_29_configbus1[2132:2132] , mux_2level_size50_29_configbus0_b[2132:2132] ); -sram6T_blwl sram_blwl_2133_ (mux_2level_size50_29_sram_blwl_out[2133:2133] ,mux_2level_size50_29_sram_blwl_out[2133:2133] ,mux_2level_size50_29_sram_blwl_outb[2133:2133] ,mux_2level_size50_29_configbus0[2133:2133], mux_2level_size50_29_configbus1[2133:2133] , mux_2level_size50_29_configbus0_b[2133:2133] ); -sram6T_blwl sram_blwl_2134_ (mux_2level_size50_29_sram_blwl_out[2134:2134] ,mux_2level_size50_29_sram_blwl_out[2134:2134] ,mux_2level_size50_29_sram_blwl_outb[2134:2134] ,mux_2level_size50_29_configbus0[2134:2134], mux_2level_size50_29_configbus1[2134:2134] , mux_2level_size50_29_configbus0_b[2134:2134] ); -sram6T_blwl sram_blwl_2135_ (mux_2level_size50_29_sram_blwl_out[2135:2135] ,mux_2level_size50_29_sram_blwl_out[2135:2135] ,mux_2level_size50_29_sram_blwl_outb[2135:2135] ,mux_2level_size50_29_configbus0[2135:2135], mux_2level_size50_29_configbus1[2135:2135] , mux_2level_size50_29_configbus0_b[2135:2135] ); -sram6T_blwl sram_blwl_2136_ (mux_2level_size50_29_sram_blwl_out[2136:2136] ,mux_2level_size50_29_sram_blwl_out[2136:2136] ,mux_2level_size50_29_sram_blwl_outb[2136:2136] ,mux_2level_size50_29_configbus0[2136:2136], mux_2level_size50_29_configbus1[2136:2136] , mux_2level_size50_29_configbus0_b[2136:2136] ); -sram6T_blwl sram_blwl_2137_ (mux_2level_size50_29_sram_blwl_out[2137:2137] ,mux_2level_size50_29_sram_blwl_out[2137:2137] ,mux_2level_size50_29_sram_blwl_outb[2137:2137] ,mux_2level_size50_29_configbus0[2137:2137], mux_2level_size50_29_configbus1[2137:2137] , mux_2level_size50_29_configbus0_b[2137:2137] ); -sram6T_blwl sram_blwl_2138_ (mux_2level_size50_29_sram_blwl_out[2138:2138] ,mux_2level_size50_29_sram_blwl_out[2138:2138] ,mux_2level_size50_29_sram_blwl_outb[2138:2138] ,mux_2level_size50_29_configbus0[2138:2138], mux_2level_size50_29_configbus1[2138:2138] , mux_2level_size50_29_configbus0_b[2138:2138] ); -sram6T_blwl sram_blwl_2139_ (mux_2level_size50_29_sram_blwl_out[2139:2139] ,mux_2level_size50_29_sram_blwl_out[2139:2139] ,mux_2level_size50_29_sram_blwl_outb[2139:2139] ,mux_2level_size50_29_configbus0[2139:2139], mux_2level_size50_29_configbus1[2139:2139] , mux_2level_size50_29_configbus0_b[2139:2139] ); -sram6T_blwl sram_blwl_2140_ (mux_2level_size50_29_sram_blwl_out[2140:2140] ,mux_2level_size50_29_sram_blwl_out[2140:2140] ,mux_2level_size50_29_sram_blwl_outb[2140:2140] ,mux_2level_size50_29_configbus0[2140:2140], mux_2level_size50_29_configbus1[2140:2140] , mux_2level_size50_29_configbus0_b[2140:2140] ); -sram6T_blwl sram_blwl_2141_ (mux_2level_size50_29_sram_blwl_out[2141:2141] ,mux_2level_size50_29_sram_blwl_out[2141:2141] ,mux_2level_size50_29_sram_blwl_outb[2141:2141] ,mux_2level_size50_29_configbus0[2141:2141], mux_2level_size50_29_configbus1[2141:2141] , mux_2level_size50_29_configbus0_b[2141:2141] ); -sram6T_blwl sram_blwl_2142_ (mux_2level_size50_29_sram_blwl_out[2142:2142] ,mux_2level_size50_29_sram_blwl_out[2142:2142] ,mux_2level_size50_29_sram_blwl_outb[2142:2142] ,mux_2level_size50_29_configbus0[2142:2142], mux_2level_size50_29_configbus1[2142:2142] , mux_2level_size50_29_configbus0_b[2142:2142] ); -sram6T_blwl sram_blwl_2143_ (mux_2level_size50_29_sram_blwl_out[2143:2143] ,mux_2level_size50_29_sram_blwl_out[2143:2143] ,mux_2level_size50_29_sram_blwl_outb[2143:2143] ,mux_2level_size50_29_configbus0[2143:2143], mux_2level_size50_29_configbus1[2143:2143] , mux_2level_size50_29_configbus0_b[2143:2143] ); -sram6T_blwl sram_blwl_2144_ (mux_2level_size50_29_sram_blwl_out[2144:2144] ,mux_2level_size50_29_sram_blwl_out[2144:2144] ,mux_2level_size50_29_sram_blwl_outb[2144:2144] ,mux_2level_size50_29_configbus0[2144:2144], mux_2level_size50_29_configbus1[2144:2144] , mux_2level_size50_29_configbus0_b[2144:2144] ); -sram6T_blwl sram_blwl_2145_ (mux_2level_size50_29_sram_blwl_out[2145:2145] ,mux_2level_size50_29_sram_blwl_out[2145:2145] ,mux_2level_size50_29_sram_blwl_outb[2145:2145] ,mux_2level_size50_29_configbus0[2145:2145], mux_2level_size50_29_configbus1[2145:2145] , mux_2level_size50_29_configbus0_b[2145:2145] ); -direct_interc direct_interc_174_ (mode_clb___clk_0_, fle_4___clk_0_ ); -wire [0:49] in_bus_mux_2level_size50_30_ ; -assign in_bus_mux_2level_size50_30_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_30_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_30_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_30_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_30_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_30_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_30_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_30_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_30_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_30_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_30_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_30_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_30_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_30_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_30_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_30_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_30_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_30_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_30_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_30_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_30_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_30_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_30_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_30_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_30_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_30_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_30_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_30_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_30_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_30_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_30_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_30_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_30_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_30_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_30_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_30_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_30_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_30_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_30_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_30_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_30_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_30_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_30_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_30_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_30_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_30_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_30_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_30_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_30_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_30_[49] = fle_9___out_0_ ; -wire [2146:2161] mux_2level_size50_30_configbus0; -wire [2146:2161] mux_2level_size50_30_configbus1; -wire [2146:2161] mux_2level_size50_30_sram_blwl_out ; -wire [2146:2161] mux_2level_size50_30_sram_blwl_outb ; -assign mux_2level_size50_30_configbus0[2146:2161] = sram_blwl_bl[2146:2161] ; -assign mux_2level_size50_30_configbus1[2146:2161] = sram_blwl_wl[2146:2161] ; -wire [2146:2161] mux_2level_size50_30_configbus0_b; -assign mux_2level_size50_30_configbus0_b[2146:2161] = sram_blwl_blb[2146:2161] ; -mux_2level_size50 mux_2level_size50_30_ (in_bus_mux_2level_size50_30_, fle_5___in_0_, mux_2level_size50_30_sram_blwl_out[2146:2161] , -mux_2level_size50_30_sram_blwl_outb[2146:2161] ); -//----- SRAM bits for MUX[30], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2146_ (mux_2level_size50_30_sram_blwl_out[2146:2146] ,mux_2level_size50_30_sram_blwl_out[2146:2146] ,mux_2level_size50_30_sram_blwl_outb[2146:2146] ,mux_2level_size50_30_configbus0[2146:2146], mux_2level_size50_30_configbus1[2146:2146] , mux_2level_size50_30_configbus0_b[2146:2146] ); -sram6T_blwl sram_blwl_2147_ (mux_2level_size50_30_sram_blwl_out[2147:2147] ,mux_2level_size50_30_sram_blwl_out[2147:2147] ,mux_2level_size50_30_sram_blwl_outb[2147:2147] ,mux_2level_size50_30_configbus0[2147:2147], mux_2level_size50_30_configbus1[2147:2147] , mux_2level_size50_30_configbus0_b[2147:2147] ); -sram6T_blwl sram_blwl_2148_ (mux_2level_size50_30_sram_blwl_out[2148:2148] ,mux_2level_size50_30_sram_blwl_out[2148:2148] ,mux_2level_size50_30_sram_blwl_outb[2148:2148] ,mux_2level_size50_30_configbus0[2148:2148], mux_2level_size50_30_configbus1[2148:2148] , mux_2level_size50_30_configbus0_b[2148:2148] ); -sram6T_blwl sram_blwl_2149_ (mux_2level_size50_30_sram_blwl_out[2149:2149] ,mux_2level_size50_30_sram_blwl_out[2149:2149] ,mux_2level_size50_30_sram_blwl_outb[2149:2149] ,mux_2level_size50_30_configbus0[2149:2149], mux_2level_size50_30_configbus1[2149:2149] , mux_2level_size50_30_configbus0_b[2149:2149] ); -sram6T_blwl sram_blwl_2150_ (mux_2level_size50_30_sram_blwl_out[2150:2150] ,mux_2level_size50_30_sram_blwl_out[2150:2150] ,mux_2level_size50_30_sram_blwl_outb[2150:2150] ,mux_2level_size50_30_configbus0[2150:2150], mux_2level_size50_30_configbus1[2150:2150] , mux_2level_size50_30_configbus0_b[2150:2150] ); -sram6T_blwl sram_blwl_2151_ (mux_2level_size50_30_sram_blwl_out[2151:2151] ,mux_2level_size50_30_sram_blwl_out[2151:2151] ,mux_2level_size50_30_sram_blwl_outb[2151:2151] ,mux_2level_size50_30_configbus0[2151:2151], mux_2level_size50_30_configbus1[2151:2151] , mux_2level_size50_30_configbus0_b[2151:2151] ); -sram6T_blwl sram_blwl_2152_ (mux_2level_size50_30_sram_blwl_out[2152:2152] ,mux_2level_size50_30_sram_blwl_out[2152:2152] ,mux_2level_size50_30_sram_blwl_outb[2152:2152] ,mux_2level_size50_30_configbus0[2152:2152], mux_2level_size50_30_configbus1[2152:2152] , mux_2level_size50_30_configbus0_b[2152:2152] ); -sram6T_blwl sram_blwl_2153_ (mux_2level_size50_30_sram_blwl_out[2153:2153] ,mux_2level_size50_30_sram_blwl_out[2153:2153] ,mux_2level_size50_30_sram_blwl_outb[2153:2153] ,mux_2level_size50_30_configbus0[2153:2153], mux_2level_size50_30_configbus1[2153:2153] , mux_2level_size50_30_configbus0_b[2153:2153] ); -sram6T_blwl sram_blwl_2154_ (mux_2level_size50_30_sram_blwl_out[2154:2154] ,mux_2level_size50_30_sram_blwl_out[2154:2154] ,mux_2level_size50_30_sram_blwl_outb[2154:2154] ,mux_2level_size50_30_configbus0[2154:2154], mux_2level_size50_30_configbus1[2154:2154] , mux_2level_size50_30_configbus0_b[2154:2154] ); -sram6T_blwl sram_blwl_2155_ (mux_2level_size50_30_sram_blwl_out[2155:2155] ,mux_2level_size50_30_sram_blwl_out[2155:2155] ,mux_2level_size50_30_sram_blwl_outb[2155:2155] ,mux_2level_size50_30_configbus0[2155:2155], mux_2level_size50_30_configbus1[2155:2155] , mux_2level_size50_30_configbus0_b[2155:2155] ); -sram6T_blwl sram_blwl_2156_ (mux_2level_size50_30_sram_blwl_out[2156:2156] ,mux_2level_size50_30_sram_blwl_out[2156:2156] ,mux_2level_size50_30_sram_blwl_outb[2156:2156] ,mux_2level_size50_30_configbus0[2156:2156], mux_2level_size50_30_configbus1[2156:2156] , mux_2level_size50_30_configbus0_b[2156:2156] ); -sram6T_blwl sram_blwl_2157_ (mux_2level_size50_30_sram_blwl_out[2157:2157] ,mux_2level_size50_30_sram_blwl_out[2157:2157] ,mux_2level_size50_30_sram_blwl_outb[2157:2157] ,mux_2level_size50_30_configbus0[2157:2157], mux_2level_size50_30_configbus1[2157:2157] , mux_2level_size50_30_configbus0_b[2157:2157] ); -sram6T_blwl sram_blwl_2158_ (mux_2level_size50_30_sram_blwl_out[2158:2158] ,mux_2level_size50_30_sram_blwl_out[2158:2158] ,mux_2level_size50_30_sram_blwl_outb[2158:2158] ,mux_2level_size50_30_configbus0[2158:2158], mux_2level_size50_30_configbus1[2158:2158] , mux_2level_size50_30_configbus0_b[2158:2158] ); -sram6T_blwl sram_blwl_2159_ (mux_2level_size50_30_sram_blwl_out[2159:2159] ,mux_2level_size50_30_sram_blwl_out[2159:2159] ,mux_2level_size50_30_sram_blwl_outb[2159:2159] ,mux_2level_size50_30_configbus0[2159:2159], mux_2level_size50_30_configbus1[2159:2159] , mux_2level_size50_30_configbus0_b[2159:2159] ); -sram6T_blwl sram_blwl_2160_ (mux_2level_size50_30_sram_blwl_out[2160:2160] ,mux_2level_size50_30_sram_blwl_out[2160:2160] ,mux_2level_size50_30_sram_blwl_outb[2160:2160] ,mux_2level_size50_30_configbus0[2160:2160], mux_2level_size50_30_configbus1[2160:2160] , mux_2level_size50_30_configbus0_b[2160:2160] ); -sram6T_blwl sram_blwl_2161_ (mux_2level_size50_30_sram_blwl_out[2161:2161] ,mux_2level_size50_30_sram_blwl_out[2161:2161] ,mux_2level_size50_30_sram_blwl_outb[2161:2161] ,mux_2level_size50_30_configbus0[2161:2161], mux_2level_size50_30_configbus1[2161:2161] , mux_2level_size50_30_configbus0_b[2161:2161] ); -wire [0:49] in_bus_mux_2level_size50_31_ ; -assign in_bus_mux_2level_size50_31_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_31_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_31_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_31_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_31_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_31_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_31_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_31_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_31_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_31_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_31_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_31_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_31_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_31_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_31_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_31_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_31_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_31_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_31_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_31_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_31_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_31_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_31_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_31_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_31_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_31_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_31_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_31_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_31_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_31_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_31_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_31_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_31_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_31_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_31_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_31_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_31_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_31_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_31_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_31_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_31_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_31_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_31_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_31_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_31_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_31_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_31_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_31_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_31_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_31_[49] = fle_9___out_0_ ; -wire [2162:2177] mux_2level_size50_31_configbus0; -wire [2162:2177] mux_2level_size50_31_configbus1; -wire [2162:2177] mux_2level_size50_31_sram_blwl_out ; -wire [2162:2177] mux_2level_size50_31_sram_blwl_outb ; -assign mux_2level_size50_31_configbus0[2162:2177] = sram_blwl_bl[2162:2177] ; -assign mux_2level_size50_31_configbus1[2162:2177] = sram_blwl_wl[2162:2177] ; -wire [2162:2177] mux_2level_size50_31_configbus0_b; -assign mux_2level_size50_31_configbus0_b[2162:2177] = sram_blwl_blb[2162:2177] ; -mux_2level_size50 mux_2level_size50_31_ (in_bus_mux_2level_size50_31_, fle_5___in_1_, mux_2level_size50_31_sram_blwl_out[2162:2177] , -mux_2level_size50_31_sram_blwl_outb[2162:2177] ); -//----- SRAM bits for MUX[31], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2162_ (mux_2level_size50_31_sram_blwl_out[2162:2162] ,mux_2level_size50_31_sram_blwl_out[2162:2162] ,mux_2level_size50_31_sram_blwl_outb[2162:2162] ,mux_2level_size50_31_configbus0[2162:2162], mux_2level_size50_31_configbus1[2162:2162] , mux_2level_size50_31_configbus0_b[2162:2162] ); -sram6T_blwl sram_blwl_2163_ (mux_2level_size50_31_sram_blwl_out[2163:2163] ,mux_2level_size50_31_sram_blwl_out[2163:2163] ,mux_2level_size50_31_sram_blwl_outb[2163:2163] ,mux_2level_size50_31_configbus0[2163:2163], mux_2level_size50_31_configbus1[2163:2163] , mux_2level_size50_31_configbus0_b[2163:2163] ); -sram6T_blwl sram_blwl_2164_ (mux_2level_size50_31_sram_blwl_out[2164:2164] ,mux_2level_size50_31_sram_blwl_out[2164:2164] ,mux_2level_size50_31_sram_blwl_outb[2164:2164] ,mux_2level_size50_31_configbus0[2164:2164], mux_2level_size50_31_configbus1[2164:2164] , mux_2level_size50_31_configbus0_b[2164:2164] ); -sram6T_blwl sram_blwl_2165_ (mux_2level_size50_31_sram_blwl_out[2165:2165] ,mux_2level_size50_31_sram_blwl_out[2165:2165] ,mux_2level_size50_31_sram_blwl_outb[2165:2165] ,mux_2level_size50_31_configbus0[2165:2165], mux_2level_size50_31_configbus1[2165:2165] , mux_2level_size50_31_configbus0_b[2165:2165] ); -sram6T_blwl sram_blwl_2166_ (mux_2level_size50_31_sram_blwl_out[2166:2166] ,mux_2level_size50_31_sram_blwl_out[2166:2166] ,mux_2level_size50_31_sram_blwl_outb[2166:2166] ,mux_2level_size50_31_configbus0[2166:2166], mux_2level_size50_31_configbus1[2166:2166] , mux_2level_size50_31_configbus0_b[2166:2166] ); -sram6T_blwl sram_blwl_2167_ (mux_2level_size50_31_sram_blwl_out[2167:2167] ,mux_2level_size50_31_sram_blwl_out[2167:2167] ,mux_2level_size50_31_sram_blwl_outb[2167:2167] ,mux_2level_size50_31_configbus0[2167:2167], mux_2level_size50_31_configbus1[2167:2167] , mux_2level_size50_31_configbus0_b[2167:2167] ); -sram6T_blwl sram_blwl_2168_ (mux_2level_size50_31_sram_blwl_out[2168:2168] ,mux_2level_size50_31_sram_blwl_out[2168:2168] ,mux_2level_size50_31_sram_blwl_outb[2168:2168] ,mux_2level_size50_31_configbus0[2168:2168], mux_2level_size50_31_configbus1[2168:2168] , mux_2level_size50_31_configbus0_b[2168:2168] ); -sram6T_blwl sram_blwl_2169_ (mux_2level_size50_31_sram_blwl_out[2169:2169] ,mux_2level_size50_31_sram_blwl_out[2169:2169] ,mux_2level_size50_31_sram_blwl_outb[2169:2169] ,mux_2level_size50_31_configbus0[2169:2169], mux_2level_size50_31_configbus1[2169:2169] , mux_2level_size50_31_configbus0_b[2169:2169] ); -sram6T_blwl sram_blwl_2170_ (mux_2level_size50_31_sram_blwl_out[2170:2170] ,mux_2level_size50_31_sram_blwl_out[2170:2170] ,mux_2level_size50_31_sram_blwl_outb[2170:2170] ,mux_2level_size50_31_configbus0[2170:2170], mux_2level_size50_31_configbus1[2170:2170] , mux_2level_size50_31_configbus0_b[2170:2170] ); -sram6T_blwl sram_blwl_2171_ (mux_2level_size50_31_sram_blwl_out[2171:2171] ,mux_2level_size50_31_sram_blwl_out[2171:2171] ,mux_2level_size50_31_sram_blwl_outb[2171:2171] ,mux_2level_size50_31_configbus0[2171:2171], mux_2level_size50_31_configbus1[2171:2171] , mux_2level_size50_31_configbus0_b[2171:2171] ); -sram6T_blwl sram_blwl_2172_ (mux_2level_size50_31_sram_blwl_out[2172:2172] ,mux_2level_size50_31_sram_blwl_out[2172:2172] ,mux_2level_size50_31_sram_blwl_outb[2172:2172] ,mux_2level_size50_31_configbus0[2172:2172], mux_2level_size50_31_configbus1[2172:2172] , mux_2level_size50_31_configbus0_b[2172:2172] ); -sram6T_blwl sram_blwl_2173_ (mux_2level_size50_31_sram_blwl_out[2173:2173] ,mux_2level_size50_31_sram_blwl_out[2173:2173] ,mux_2level_size50_31_sram_blwl_outb[2173:2173] ,mux_2level_size50_31_configbus0[2173:2173], mux_2level_size50_31_configbus1[2173:2173] , mux_2level_size50_31_configbus0_b[2173:2173] ); -sram6T_blwl sram_blwl_2174_ (mux_2level_size50_31_sram_blwl_out[2174:2174] ,mux_2level_size50_31_sram_blwl_out[2174:2174] ,mux_2level_size50_31_sram_blwl_outb[2174:2174] ,mux_2level_size50_31_configbus0[2174:2174], mux_2level_size50_31_configbus1[2174:2174] , mux_2level_size50_31_configbus0_b[2174:2174] ); -sram6T_blwl sram_blwl_2175_ (mux_2level_size50_31_sram_blwl_out[2175:2175] ,mux_2level_size50_31_sram_blwl_out[2175:2175] ,mux_2level_size50_31_sram_blwl_outb[2175:2175] ,mux_2level_size50_31_configbus0[2175:2175], mux_2level_size50_31_configbus1[2175:2175] , mux_2level_size50_31_configbus0_b[2175:2175] ); -sram6T_blwl sram_blwl_2176_ (mux_2level_size50_31_sram_blwl_out[2176:2176] ,mux_2level_size50_31_sram_blwl_out[2176:2176] ,mux_2level_size50_31_sram_blwl_outb[2176:2176] ,mux_2level_size50_31_configbus0[2176:2176], mux_2level_size50_31_configbus1[2176:2176] , mux_2level_size50_31_configbus0_b[2176:2176] ); -sram6T_blwl sram_blwl_2177_ (mux_2level_size50_31_sram_blwl_out[2177:2177] ,mux_2level_size50_31_sram_blwl_out[2177:2177] ,mux_2level_size50_31_sram_blwl_outb[2177:2177] ,mux_2level_size50_31_configbus0[2177:2177], mux_2level_size50_31_configbus1[2177:2177] , mux_2level_size50_31_configbus0_b[2177:2177] ); -wire [0:49] in_bus_mux_2level_size50_32_ ; -assign in_bus_mux_2level_size50_32_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_32_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_32_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_32_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_32_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_32_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_32_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_32_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_32_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_32_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_32_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_32_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_32_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_32_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_32_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_32_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_32_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_32_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_32_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_32_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_32_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_32_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_32_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_32_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_32_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_32_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_32_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_32_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_32_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_32_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_32_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_32_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_32_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_32_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_32_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_32_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_32_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_32_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_32_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_32_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_32_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_32_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_32_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_32_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_32_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_32_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_32_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_32_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_32_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_32_[49] = fle_9___out_0_ ; -wire [2178:2193] mux_2level_size50_32_configbus0; -wire [2178:2193] mux_2level_size50_32_configbus1; -wire [2178:2193] mux_2level_size50_32_sram_blwl_out ; -wire [2178:2193] mux_2level_size50_32_sram_blwl_outb ; -assign mux_2level_size50_32_configbus0[2178:2193] = sram_blwl_bl[2178:2193] ; -assign mux_2level_size50_32_configbus1[2178:2193] = sram_blwl_wl[2178:2193] ; -wire [2178:2193] mux_2level_size50_32_configbus0_b; -assign mux_2level_size50_32_configbus0_b[2178:2193] = sram_blwl_blb[2178:2193] ; -mux_2level_size50 mux_2level_size50_32_ (in_bus_mux_2level_size50_32_, fle_5___in_2_, mux_2level_size50_32_sram_blwl_out[2178:2193] , -mux_2level_size50_32_sram_blwl_outb[2178:2193] ); -//----- SRAM bits for MUX[32], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2178_ (mux_2level_size50_32_sram_blwl_out[2178:2178] ,mux_2level_size50_32_sram_blwl_out[2178:2178] ,mux_2level_size50_32_sram_blwl_outb[2178:2178] ,mux_2level_size50_32_configbus0[2178:2178], mux_2level_size50_32_configbus1[2178:2178] , mux_2level_size50_32_configbus0_b[2178:2178] ); -sram6T_blwl sram_blwl_2179_ (mux_2level_size50_32_sram_blwl_out[2179:2179] ,mux_2level_size50_32_sram_blwl_out[2179:2179] ,mux_2level_size50_32_sram_blwl_outb[2179:2179] ,mux_2level_size50_32_configbus0[2179:2179], mux_2level_size50_32_configbus1[2179:2179] , mux_2level_size50_32_configbus0_b[2179:2179] ); -sram6T_blwl sram_blwl_2180_ (mux_2level_size50_32_sram_blwl_out[2180:2180] ,mux_2level_size50_32_sram_blwl_out[2180:2180] ,mux_2level_size50_32_sram_blwl_outb[2180:2180] ,mux_2level_size50_32_configbus0[2180:2180], mux_2level_size50_32_configbus1[2180:2180] , mux_2level_size50_32_configbus0_b[2180:2180] ); -sram6T_blwl sram_blwl_2181_ (mux_2level_size50_32_sram_blwl_out[2181:2181] ,mux_2level_size50_32_sram_blwl_out[2181:2181] ,mux_2level_size50_32_sram_blwl_outb[2181:2181] ,mux_2level_size50_32_configbus0[2181:2181], mux_2level_size50_32_configbus1[2181:2181] , mux_2level_size50_32_configbus0_b[2181:2181] ); -sram6T_blwl sram_blwl_2182_ (mux_2level_size50_32_sram_blwl_out[2182:2182] ,mux_2level_size50_32_sram_blwl_out[2182:2182] ,mux_2level_size50_32_sram_blwl_outb[2182:2182] ,mux_2level_size50_32_configbus0[2182:2182], mux_2level_size50_32_configbus1[2182:2182] , mux_2level_size50_32_configbus0_b[2182:2182] ); -sram6T_blwl sram_blwl_2183_ (mux_2level_size50_32_sram_blwl_out[2183:2183] ,mux_2level_size50_32_sram_blwl_out[2183:2183] ,mux_2level_size50_32_sram_blwl_outb[2183:2183] ,mux_2level_size50_32_configbus0[2183:2183], mux_2level_size50_32_configbus1[2183:2183] , mux_2level_size50_32_configbus0_b[2183:2183] ); -sram6T_blwl sram_blwl_2184_ (mux_2level_size50_32_sram_blwl_out[2184:2184] ,mux_2level_size50_32_sram_blwl_out[2184:2184] ,mux_2level_size50_32_sram_blwl_outb[2184:2184] ,mux_2level_size50_32_configbus0[2184:2184], mux_2level_size50_32_configbus1[2184:2184] , mux_2level_size50_32_configbus0_b[2184:2184] ); -sram6T_blwl sram_blwl_2185_ (mux_2level_size50_32_sram_blwl_out[2185:2185] ,mux_2level_size50_32_sram_blwl_out[2185:2185] ,mux_2level_size50_32_sram_blwl_outb[2185:2185] ,mux_2level_size50_32_configbus0[2185:2185], mux_2level_size50_32_configbus1[2185:2185] , mux_2level_size50_32_configbus0_b[2185:2185] ); -sram6T_blwl sram_blwl_2186_ (mux_2level_size50_32_sram_blwl_out[2186:2186] ,mux_2level_size50_32_sram_blwl_out[2186:2186] ,mux_2level_size50_32_sram_blwl_outb[2186:2186] ,mux_2level_size50_32_configbus0[2186:2186], mux_2level_size50_32_configbus1[2186:2186] , mux_2level_size50_32_configbus0_b[2186:2186] ); -sram6T_blwl sram_blwl_2187_ (mux_2level_size50_32_sram_blwl_out[2187:2187] ,mux_2level_size50_32_sram_blwl_out[2187:2187] ,mux_2level_size50_32_sram_blwl_outb[2187:2187] ,mux_2level_size50_32_configbus0[2187:2187], mux_2level_size50_32_configbus1[2187:2187] , mux_2level_size50_32_configbus0_b[2187:2187] ); -sram6T_blwl sram_blwl_2188_ (mux_2level_size50_32_sram_blwl_out[2188:2188] ,mux_2level_size50_32_sram_blwl_out[2188:2188] ,mux_2level_size50_32_sram_blwl_outb[2188:2188] ,mux_2level_size50_32_configbus0[2188:2188], mux_2level_size50_32_configbus1[2188:2188] , mux_2level_size50_32_configbus0_b[2188:2188] ); -sram6T_blwl sram_blwl_2189_ (mux_2level_size50_32_sram_blwl_out[2189:2189] ,mux_2level_size50_32_sram_blwl_out[2189:2189] ,mux_2level_size50_32_sram_blwl_outb[2189:2189] ,mux_2level_size50_32_configbus0[2189:2189], mux_2level_size50_32_configbus1[2189:2189] , mux_2level_size50_32_configbus0_b[2189:2189] ); -sram6T_blwl sram_blwl_2190_ (mux_2level_size50_32_sram_blwl_out[2190:2190] ,mux_2level_size50_32_sram_blwl_out[2190:2190] ,mux_2level_size50_32_sram_blwl_outb[2190:2190] ,mux_2level_size50_32_configbus0[2190:2190], mux_2level_size50_32_configbus1[2190:2190] , mux_2level_size50_32_configbus0_b[2190:2190] ); -sram6T_blwl sram_blwl_2191_ (mux_2level_size50_32_sram_blwl_out[2191:2191] ,mux_2level_size50_32_sram_blwl_out[2191:2191] ,mux_2level_size50_32_sram_blwl_outb[2191:2191] ,mux_2level_size50_32_configbus0[2191:2191], mux_2level_size50_32_configbus1[2191:2191] , mux_2level_size50_32_configbus0_b[2191:2191] ); -sram6T_blwl sram_blwl_2192_ (mux_2level_size50_32_sram_blwl_out[2192:2192] ,mux_2level_size50_32_sram_blwl_out[2192:2192] ,mux_2level_size50_32_sram_blwl_outb[2192:2192] ,mux_2level_size50_32_configbus0[2192:2192], mux_2level_size50_32_configbus1[2192:2192] , mux_2level_size50_32_configbus0_b[2192:2192] ); -sram6T_blwl sram_blwl_2193_ (mux_2level_size50_32_sram_blwl_out[2193:2193] ,mux_2level_size50_32_sram_blwl_out[2193:2193] ,mux_2level_size50_32_sram_blwl_outb[2193:2193] ,mux_2level_size50_32_configbus0[2193:2193], mux_2level_size50_32_configbus1[2193:2193] , mux_2level_size50_32_configbus0_b[2193:2193] ); -wire [0:49] in_bus_mux_2level_size50_33_ ; -assign in_bus_mux_2level_size50_33_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_33_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_33_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_33_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_33_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_33_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_33_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_33_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_33_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_33_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_33_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_33_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_33_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_33_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_33_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_33_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_33_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_33_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_33_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_33_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_33_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_33_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_33_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_33_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_33_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_33_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_33_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_33_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_33_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_33_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_33_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_33_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_33_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_33_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_33_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_33_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_33_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_33_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_33_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_33_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_33_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_33_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_33_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_33_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_33_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_33_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_33_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_33_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_33_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_33_[49] = fle_9___out_0_ ; -wire [2194:2209] mux_2level_size50_33_configbus0; -wire [2194:2209] mux_2level_size50_33_configbus1; -wire [2194:2209] mux_2level_size50_33_sram_blwl_out ; -wire [2194:2209] mux_2level_size50_33_sram_blwl_outb ; -assign mux_2level_size50_33_configbus0[2194:2209] = sram_blwl_bl[2194:2209] ; -assign mux_2level_size50_33_configbus1[2194:2209] = sram_blwl_wl[2194:2209] ; -wire [2194:2209] mux_2level_size50_33_configbus0_b; -assign mux_2level_size50_33_configbus0_b[2194:2209] = sram_blwl_blb[2194:2209] ; -mux_2level_size50 mux_2level_size50_33_ (in_bus_mux_2level_size50_33_, fle_5___in_3_, mux_2level_size50_33_sram_blwl_out[2194:2209] , -mux_2level_size50_33_sram_blwl_outb[2194:2209] ); -//----- SRAM bits for MUX[33], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2194_ (mux_2level_size50_33_sram_blwl_out[2194:2194] ,mux_2level_size50_33_sram_blwl_out[2194:2194] ,mux_2level_size50_33_sram_blwl_outb[2194:2194] ,mux_2level_size50_33_configbus0[2194:2194], mux_2level_size50_33_configbus1[2194:2194] , mux_2level_size50_33_configbus0_b[2194:2194] ); -sram6T_blwl sram_blwl_2195_ (mux_2level_size50_33_sram_blwl_out[2195:2195] ,mux_2level_size50_33_sram_blwl_out[2195:2195] ,mux_2level_size50_33_sram_blwl_outb[2195:2195] ,mux_2level_size50_33_configbus0[2195:2195], mux_2level_size50_33_configbus1[2195:2195] , mux_2level_size50_33_configbus0_b[2195:2195] ); -sram6T_blwl sram_blwl_2196_ (mux_2level_size50_33_sram_blwl_out[2196:2196] ,mux_2level_size50_33_sram_blwl_out[2196:2196] ,mux_2level_size50_33_sram_blwl_outb[2196:2196] ,mux_2level_size50_33_configbus0[2196:2196], mux_2level_size50_33_configbus1[2196:2196] , mux_2level_size50_33_configbus0_b[2196:2196] ); -sram6T_blwl sram_blwl_2197_ (mux_2level_size50_33_sram_blwl_out[2197:2197] ,mux_2level_size50_33_sram_blwl_out[2197:2197] ,mux_2level_size50_33_sram_blwl_outb[2197:2197] ,mux_2level_size50_33_configbus0[2197:2197], mux_2level_size50_33_configbus1[2197:2197] , mux_2level_size50_33_configbus0_b[2197:2197] ); -sram6T_blwl sram_blwl_2198_ (mux_2level_size50_33_sram_blwl_out[2198:2198] ,mux_2level_size50_33_sram_blwl_out[2198:2198] ,mux_2level_size50_33_sram_blwl_outb[2198:2198] ,mux_2level_size50_33_configbus0[2198:2198], mux_2level_size50_33_configbus1[2198:2198] , mux_2level_size50_33_configbus0_b[2198:2198] ); -sram6T_blwl sram_blwl_2199_ (mux_2level_size50_33_sram_blwl_out[2199:2199] ,mux_2level_size50_33_sram_blwl_out[2199:2199] ,mux_2level_size50_33_sram_blwl_outb[2199:2199] ,mux_2level_size50_33_configbus0[2199:2199], mux_2level_size50_33_configbus1[2199:2199] , mux_2level_size50_33_configbus0_b[2199:2199] ); -sram6T_blwl sram_blwl_2200_ (mux_2level_size50_33_sram_blwl_out[2200:2200] ,mux_2level_size50_33_sram_blwl_out[2200:2200] ,mux_2level_size50_33_sram_blwl_outb[2200:2200] ,mux_2level_size50_33_configbus0[2200:2200], mux_2level_size50_33_configbus1[2200:2200] , mux_2level_size50_33_configbus0_b[2200:2200] ); -sram6T_blwl sram_blwl_2201_ (mux_2level_size50_33_sram_blwl_out[2201:2201] ,mux_2level_size50_33_sram_blwl_out[2201:2201] ,mux_2level_size50_33_sram_blwl_outb[2201:2201] ,mux_2level_size50_33_configbus0[2201:2201], mux_2level_size50_33_configbus1[2201:2201] , mux_2level_size50_33_configbus0_b[2201:2201] ); -sram6T_blwl sram_blwl_2202_ (mux_2level_size50_33_sram_blwl_out[2202:2202] ,mux_2level_size50_33_sram_blwl_out[2202:2202] ,mux_2level_size50_33_sram_blwl_outb[2202:2202] ,mux_2level_size50_33_configbus0[2202:2202], mux_2level_size50_33_configbus1[2202:2202] , mux_2level_size50_33_configbus0_b[2202:2202] ); -sram6T_blwl sram_blwl_2203_ (mux_2level_size50_33_sram_blwl_out[2203:2203] ,mux_2level_size50_33_sram_blwl_out[2203:2203] ,mux_2level_size50_33_sram_blwl_outb[2203:2203] ,mux_2level_size50_33_configbus0[2203:2203], mux_2level_size50_33_configbus1[2203:2203] , mux_2level_size50_33_configbus0_b[2203:2203] ); -sram6T_blwl sram_blwl_2204_ (mux_2level_size50_33_sram_blwl_out[2204:2204] ,mux_2level_size50_33_sram_blwl_out[2204:2204] ,mux_2level_size50_33_sram_blwl_outb[2204:2204] ,mux_2level_size50_33_configbus0[2204:2204], mux_2level_size50_33_configbus1[2204:2204] , mux_2level_size50_33_configbus0_b[2204:2204] ); -sram6T_blwl sram_blwl_2205_ (mux_2level_size50_33_sram_blwl_out[2205:2205] ,mux_2level_size50_33_sram_blwl_out[2205:2205] ,mux_2level_size50_33_sram_blwl_outb[2205:2205] ,mux_2level_size50_33_configbus0[2205:2205], mux_2level_size50_33_configbus1[2205:2205] , mux_2level_size50_33_configbus0_b[2205:2205] ); -sram6T_blwl sram_blwl_2206_ (mux_2level_size50_33_sram_blwl_out[2206:2206] ,mux_2level_size50_33_sram_blwl_out[2206:2206] ,mux_2level_size50_33_sram_blwl_outb[2206:2206] ,mux_2level_size50_33_configbus0[2206:2206], mux_2level_size50_33_configbus1[2206:2206] , mux_2level_size50_33_configbus0_b[2206:2206] ); -sram6T_blwl sram_blwl_2207_ (mux_2level_size50_33_sram_blwl_out[2207:2207] ,mux_2level_size50_33_sram_blwl_out[2207:2207] ,mux_2level_size50_33_sram_blwl_outb[2207:2207] ,mux_2level_size50_33_configbus0[2207:2207], mux_2level_size50_33_configbus1[2207:2207] , mux_2level_size50_33_configbus0_b[2207:2207] ); -sram6T_blwl sram_blwl_2208_ (mux_2level_size50_33_sram_blwl_out[2208:2208] ,mux_2level_size50_33_sram_blwl_out[2208:2208] ,mux_2level_size50_33_sram_blwl_outb[2208:2208] ,mux_2level_size50_33_configbus0[2208:2208], mux_2level_size50_33_configbus1[2208:2208] , mux_2level_size50_33_configbus0_b[2208:2208] ); -sram6T_blwl sram_blwl_2209_ (mux_2level_size50_33_sram_blwl_out[2209:2209] ,mux_2level_size50_33_sram_blwl_out[2209:2209] ,mux_2level_size50_33_sram_blwl_outb[2209:2209] ,mux_2level_size50_33_configbus0[2209:2209], mux_2level_size50_33_configbus1[2209:2209] , mux_2level_size50_33_configbus0_b[2209:2209] ); -wire [0:49] in_bus_mux_2level_size50_34_ ; -assign in_bus_mux_2level_size50_34_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_34_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_34_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_34_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_34_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_34_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_34_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_34_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_34_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_34_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_34_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_34_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_34_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_34_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_34_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_34_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_34_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_34_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_34_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_34_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_34_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_34_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_34_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_34_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_34_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_34_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_34_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_34_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_34_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_34_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_34_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_34_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_34_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_34_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_34_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_34_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_34_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_34_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_34_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_34_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_34_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_34_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_34_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_34_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_34_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_34_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_34_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_34_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_34_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_34_[49] = fle_9___out_0_ ; -wire [2210:2225] mux_2level_size50_34_configbus0; -wire [2210:2225] mux_2level_size50_34_configbus1; -wire [2210:2225] mux_2level_size50_34_sram_blwl_out ; -wire [2210:2225] mux_2level_size50_34_sram_blwl_outb ; -assign mux_2level_size50_34_configbus0[2210:2225] = sram_blwl_bl[2210:2225] ; -assign mux_2level_size50_34_configbus1[2210:2225] = sram_blwl_wl[2210:2225] ; -wire [2210:2225] mux_2level_size50_34_configbus0_b; -assign mux_2level_size50_34_configbus0_b[2210:2225] = sram_blwl_blb[2210:2225] ; -mux_2level_size50 mux_2level_size50_34_ (in_bus_mux_2level_size50_34_, fle_5___in_4_, mux_2level_size50_34_sram_blwl_out[2210:2225] , -mux_2level_size50_34_sram_blwl_outb[2210:2225] ); -//----- SRAM bits for MUX[34], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2210_ (mux_2level_size50_34_sram_blwl_out[2210:2210] ,mux_2level_size50_34_sram_blwl_out[2210:2210] ,mux_2level_size50_34_sram_blwl_outb[2210:2210] ,mux_2level_size50_34_configbus0[2210:2210], mux_2level_size50_34_configbus1[2210:2210] , mux_2level_size50_34_configbus0_b[2210:2210] ); -sram6T_blwl sram_blwl_2211_ (mux_2level_size50_34_sram_blwl_out[2211:2211] ,mux_2level_size50_34_sram_blwl_out[2211:2211] ,mux_2level_size50_34_sram_blwl_outb[2211:2211] ,mux_2level_size50_34_configbus0[2211:2211], mux_2level_size50_34_configbus1[2211:2211] , mux_2level_size50_34_configbus0_b[2211:2211] ); -sram6T_blwl sram_blwl_2212_ (mux_2level_size50_34_sram_blwl_out[2212:2212] ,mux_2level_size50_34_sram_blwl_out[2212:2212] ,mux_2level_size50_34_sram_blwl_outb[2212:2212] ,mux_2level_size50_34_configbus0[2212:2212], mux_2level_size50_34_configbus1[2212:2212] , mux_2level_size50_34_configbus0_b[2212:2212] ); -sram6T_blwl sram_blwl_2213_ (mux_2level_size50_34_sram_blwl_out[2213:2213] ,mux_2level_size50_34_sram_blwl_out[2213:2213] ,mux_2level_size50_34_sram_blwl_outb[2213:2213] ,mux_2level_size50_34_configbus0[2213:2213], mux_2level_size50_34_configbus1[2213:2213] , mux_2level_size50_34_configbus0_b[2213:2213] ); -sram6T_blwl sram_blwl_2214_ (mux_2level_size50_34_sram_blwl_out[2214:2214] ,mux_2level_size50_34_sram_blwl_out[2214:2214] ,mux_2level_size50_34_sram_blwl_outb[2214:2214] ,mux_2level_size50_34_configbus0[2214:2214], mux_2level_size50_34_configbus1[2214:2214] , mux_2level_size50_34_configbus0_b[2214:2214] ); -sram6T_blwl sram_blwl_2215_ (mux_2level_size50_34_sram_blwl_out[2215:2215] ,mux_2level_size50_34_sram_blwl_out[2215:2215] ,mux_2level_size50_34_sram_blwl_outb[2215:2215] ,mux_2level_size50_34_configbus0[2215:2215], mux_2level_size50_34_configbus1[2215:2215] , mux_2level_size50_34_configbus0_b[2215:2215] ); -sram6T_blwl sram_blwl_2216_ (mux_2level_size50_34_sram_blwl_out[2216:2216] ,mux_2level_size50_34_sram_blwl_out[2216:2216] ,mux_2level_size50_34_sram_blwl_outb[2216:2216] ,mux_2level_size50_34_configbus0[2216:2216], mux_2level_size50_34_configbus1[2216:2216] , mux_2level_size50_34_configbus0_b[2216:2216] ); -sram6T_blwl sram_blwl_2217_ (mux_2level_size50_34_sram_blwl_out[2217:2217] ,mux_2level_size50_34_sram_blwl_out[2217:2217] ,mux_2level_size50_34_sram_blwl_outb[2217:2217] ,mux_2level_size50_34_configbus0[2217:2217], mux_2level_size50_34_configbus1[2217:2217] , mux_2level_size50_34_configbus0_b[2217:2217] ); -sram6T_blwl sram_blwl_2218_ (mux_2level_size50_34_sram_blwl_out[2218:2218] ,mux_2level_size50_34_sram_blwl_out[2218:2218] ,mux_2level_size50_34_sram_blwl_outb[2218:2218] ,mux_2level_size50_34_configbus0[2218:2218], mux_2level_size50_34_configbus1[2218:2218] , mux_2level_size50_34_configbus0_b[2218:2218] ); -sram6T_blwl sram_blwl_2219_ (mux_2level_size50_34_sram_blwl_out[2219:2219] ,mux_2level_size50_34_sram_blwl_out[2219:2219] ,mux_2level_size50_34_sram_blwl_outb[2219:2219] ,mux_2level_size50_34_configbus0[2219:2219], mux_2level_size50_34_configbus1[2219:2219] , mux_2level_size50_34_configbus0_b[2219:2219] ); -sram6T_blwl sram_blwl_2220_ (mux_2level_size50_34_sram_blwl_out[2220:2220] ,mux_2level_size50_34_sram_blwl_out[2220:2220] ,mux_2level_size50_34_sram_blwl_outb[2220:2220] ,mux_2level_size50_34_configbus0[2220:2220], mux_2level_size50_34_configbus1[2220:2220] , mux_2level_size50_34_configbus0_b[2220:2220] ); -sram6T_blwl sram_blwl_2221_ (mux_2level_size50_34_sram_blwl_out[2221:2221] ,mux_2level_size50_34_sram_blwl_out[2221:2221] ,mux_2level_size50_34_sram_blwl_outb[2221:2221] ,mux_2level_size50_34_configbus0[2221:2221], mux_2level_size50_34_configbus1[2221:2221] , mux_2level_size50_34_configbus0_b[2221:2221] ); -sram6T_blwl sram_blwl_2222_ (mux_2level_size50_34_sram_blwl_out[2222:2222] ,mux_2level_size50_34_sram_blwl_out[2222:2222] ,mux_2level_size50_34_sram_blwl_outb[2222:2222] ,mux_2level_size50_34_configbus0[2222:2222], mux_2level_size50_34_configbus1[2222:2222] , mux_2level_size50_34_configbus0_b[2222:2222] ); -sram6T_blwl sram_blwl_2223_ (mux_2level_size50_34_sram_blwl_out[2223:2223] ,mux_2level_size50_34_sram_blwl_out[2223:2223] ,mux_2level_size50_34_sram_blwl_outb[2223:2223] ,mux_2level_size50_34_configbus0[2223:2223], mux_2level_size50_34_configbus1[2223:2223] , mux_2level_size50_34_configbus0_b[2223:2223] ); -sram6T_blwl sram_blwl_2224_ (mux_2level_size50_34_sram_blwl_out[2224:2224] ,mux_2level_size50_34_sram_blwl_out[2224:2224] ,mux_2level_size50_34_sram_blwl_outb[2224:2224] ,mux_2level_size50_34_configbus0[2224:2224], mux_2level_size50_34_configbus1[2224:2224] , mux_2level_size50_34_configbus0_b[2224:2224] ); -sram6T_blwl sram_blwl_2225_ (mux_2level_size50_34_sram_blwl_out[2225:2225] ,mux_2level_size50_34_sram_blwl_out[2225:2225] ,mux_2level_size50_34_sram_blwl_outb[2225:2225] ,mux_2level_size50_34_configbus0[2225:2225], mux_2level_size50_34_configbus1[2225:2225] , mux_2level_size50_34_configbus0_b[2225:2225] ); -wire [0:49] in_bus_mux_2level_size50_35_ ; -assign in_bus_mux_2level_size50_35_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_35_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_35_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_35_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_35_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_35_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_35_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_35_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_35_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_35_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_35_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_35_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_35_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_35_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_35_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_35_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_35_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_35_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_35_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_35_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_35_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_35_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_35_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_35_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_35_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_35_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_35_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_35_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_35_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_35_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_35_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_35_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_35_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_35_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_35_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_35_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_35_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_35_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_35_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_35_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_35_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_35_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_35_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_35_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_35_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_35_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_35_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_35_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_35_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_35_[49] = fle_9___out_0_ ; -wire [2226:2241] mux_2level_size50_35_configbus0; -wire [2226:2241] mux_2level_size50_35_configbus1; -wire [2226:2241] mux_2level_size50_35_sram_blwl_out ; -wire [2226:2241] mux_2level_size50_35_sram_blwl_outb ; -assign mux_2level_size50_35_configbus0[2226:2241] = sram_blwl_bl[2226:2241] ; -assign mux_2level_size50_35_configbus1[2226:2241] = sram_blwl_wl[2226:2241] ; -wire [2226:2241] mux_2level_size50_35_configbus0_b; -assign mux_2level_size50_35_configbus0_b[2226:2241] = sram_blwl_blb[2226:2241] ; -mux_2level_size50 mux_2level_size50_35_ (in_bus_mux_2level_size50_35_, fle_5___in_5_, mux_2level_size50_35_sram_blwl_out[2226:2241] , -mux_2level_size50_35_sram_blwl_outb[2226:2241] ); -//----- SRAM bits for MUX[35], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2226_ (mux_2level_size50_35_sram_blwl_out[2226:2226] ,mux_2level_size50_35_sram_blwl_out[2226:2226] ,mux_2level_size50_35_sram_blwl_outb[2226:2226] ,mux_2level_size50_35_configbus0[2226:2226], mux_2level_size50_35_configbus1[2226:2226] , mux_2level_size50_35_configbus0_b[2226:2226] ); -sram6T_blwl sram_blwl_2227_ (mux_2level_size50_35_sram_blwl_out[2227:2227] ,mux_2level_size50_35_sram_blwl_out[2227:2227] ,mux_2level_size50_35_sram_blwl_outb[2227:2227] ,mux_2level_size50_35_configbus0[2227:2227], mux_2level_size50_35_configbus1[2227:2227] , mux_2level_size50_35_configbus0_b[2227:2227] ); -sram6T_blwl sram_blwl_2228_ (mux_2level_size50_35_sram_blwl_out[2228:2228] ,mux_2level_size50_35_sram_blwl_out[2228:2228] ,mux_2level_size50_35_sram_blwl_outb[2228:2228] ,mux_2level_size50_35_configbus0[2228:2228], mux_2level_size50_35_configbus1[2228:2228] , mux_2level_size50_35_configbus0_b[2228:2228] ); -sram6T_blwl sram_blwl_2229_ (mux_2level_size50_35_sram_blwl_out[2229:2229] ,mux_2level_size50_35_sram_blwl_out[2229:2229] ,mux_2level_size50_35_sram_blwl_outb[2229:2229] ,mux_2level_size50_35_configbus0[2229:2229], mux_2level_size50_35_configbus1[2229:2229] , mux_2level_size50_35_configbus0_b[2229:2229] ); -sram6T_blwl sram_blwl_2230_ (mux_2level_size50_35_sram_blwl_out[2230:2230] ,mux_2level_size50_35_sram_blwl_out[2230:2230] ,mux_2level_size50_35_sram_blwl_outb[2230:2230] ,mux_2level_size50_35_configbus0[2230:2230], mux_2level_size50_35_configbus1[2230:2230] , mux_2level_size50_35_configbus0_b[2230:2230] ); -sram6T_blwl sram_blwl_2231_ (mux_2level_size50_35_sram_blwl_out[2231:2231] ,mux_2level_size50_35_sram_blwl_out[2231:2231] ,mux_2level_size50_35_sram_blwl_outb[2231:2231] ,mux_2level_size50_35_configbus0[2231:2231], mux_2level_size50_35_configbus1[2231:2231] , mux_2level_size50_35_configbus0_b[2231:2231] ); -sram6T_blwl sram_blwl_2232_ (mux_2level_size50_35_sram_blwl_out[2232:2232] ,mux_2level_size50_35_sram_blwl_out[2232:2232] ,mux_2level_size50_35_sram_blwl_outb[2232:2232] ,mux_2level_size50_35_configbus0[2232:2232], mux_2level_size50_35_configbus1[2232:2232] , mux_2level_size50_35_configbus0_b[2232:2232] ); -sram6T_blwl sram_blwl_2233_ (mux_2level_size50_35_sram_blwl_out[2233:2233] ,mux_2level_size50_35_sram_blwl_out[2233:2233] ,mux_2level_size50_35_sram_blwl_outb[2233:2233] ,mux_2level_size50_35_configbus0[2233:2233], mux_2level_size50_35_configbus1[2233:2233] , mux_2level_size50_35_configbus0_b[2233:2233] ); -sram6T_blwl sram_blwl_2234_ (mux_2level_size50_35_sram_blwl_out[2234:2234] ,mux_2level_size50_35_sram_blwl_out[2234:2234] ,mux_2level_size50_35_sram_blwl_outb[2234:2234] ,mux_2level_size50_35_configbus0[2234:2234], mux_2level_size50_35_configbus1[2234:2234] , mux_2level_size50_35_configbus0_b[2234:2234] ); -sram6T_blwl sram_blwl_2235_ (mux_2level_size50_35_sram_blwl_out[2235:2235] ,mux_2level_size50_35_sram_blwl_out[2235:2235] ,mux_2level_size50_35_sram_blwl_outb[2235:2235] ,mux_2level_size50_35_configbus0[2235:2235], mux_2level_size50_35_configbus1[2235:2235] , mux_2level_size50_35_configbus0_b[2235:2235] ); -sram6T_blwl sram_blwl_2236_ (mux_2level_size50_35_sram_blwl_out[2236:2236] ,mux_2level_size50_35_sram_blwl_out[2236:2236] ,mux_2level_size50_35_sram_blwl_outb[2236:2236] ,mux_2level_size50_35_configbus0[2236:2236], mux_2level_size50_35_configbus1[2236:2236] , mux_2level_size50_35_configbus0_b[2236:2236] ); -sram6T_blwl sram_blwl_2237_ (mux_2level_size50_35_sram_blwl_out[2237:2237] ,mux_2level_size50_35_sram_blwl_out[2237:2237] ,mux_2level_size50_35_sram_blwl_outb[2237:2237] ,mux_2level_size50_35_configbus0[2237:2237], mux_2level_size50_35_configbus1[2237:2237] , mux_2level_size50_35_configbus0_b[2237:2237] ); -sram6T_blwl sram_blwl_2238_ (mux_2level_size50_35_sram_blwl_out[2238:2238] ,mux_2level_size50_35_sram_blwl_out[2238:2238] ,mux_2level_size50_35_sram_blwl_outb[2238:2238] ,mux_2level_size50_35_configbus0[2238:2238], mux_2level_size50_35_configbus1[2238:2238] , mux_2level_size50_35_configbus0_b[2238:2238] ); -sram6T_blwl sram_blwl_2239_ (mux_2level_size50_35_sram_blwl_out[2239:2239] ,mux_2level_size50_35_sram_blwl_out[2239:2239] ,mux_2level_size50_35_sram_blwl_outb[2239:2239] ,mux_2level_size50_35_configbus0[2239:2239], mux_2level_size50_35_configbus1[2239:2239] , mux_2level_size50_35_configbus0_b[2239:2239] ); -sram6T_blwl sram_blwl_2240_ (mux_2level_size50_35_sram_blwl_out[2240:2240] ,mux_2level_size50_35_sram_blwl_out[2240:2240] ,mux_2level_size50_35_sram_blwl_outb[2240:2240] ,mux_2level_size50_35_configbus0[2240:2240], mux_2level_size50_35_configbus1[2240:2240] , mux_2level_size50_35_configbus0_b[2240:2240] ); -sram6T_blwl sram_blwl_2241_ (mux_2level_size50_35_sram_blwl_out[2241:2241] ,mux_2level_size50_35_sram_blwl_out[2241:2241] ,mux_2level_size50_35_sram_blwl_outb[2241:2241] ,mux_2level_size50_35_configbus0[2241:2241], mux_2level_size50_35_configbus1[2241:2241] , mux_2level_size50_35_configbus0_b[2241:2241] ); -direct_interc direct_interc_175_ (mode_clb___clk_0_, fle_5___clk_0_ ); -wire [0:49] in_bus_mux_2level_size50_36_ ; -assign in_bus_mux_2level_size50_36_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_36_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_36_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_36_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_36_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_36_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_36_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_36_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_36_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_36_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_36_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_36_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_36_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_36_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_36_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_36_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_36_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_36_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_36_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_36_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_36_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_36_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_36_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_36_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_36_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_36_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_36_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_36_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_36_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_36_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_36_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_36_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_36_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_36_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_36_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_36_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_36_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_36_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_36_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_36_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_36_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_36_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_36_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_36_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_36_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_36_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_36_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_36_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_36_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_36_[49] = fle_9___out_0_ ; -wire [2242:2257] mux_2level_size50_36_configbus0; -wire [2242:2257] mux_2level_size50_36_configbus1; -wire [2242:2257] mux_2level_size50_36_sram_blwl_out ; -wire [2242:2257] mux_2level_size50_36_sram_blwl_outb ; -assign mux_2level_size50_36_configbus0[2242:2257] = sram_blwl_bl[2242:2257] ; -assign mux_2level_size50_36_configbus1[2242:2257] = sram_blwl_wl[2242:2257] ; -wire [2242:2257] mux_2level_size50_36_configbus0_b; -assign mux_2level_size50_36_configbus0_b[2242:2257] = sram_blwl_blb[2242:2257] ; -mux_2level_size50 mux_2level_size50_36_ (in_bus_mux_2level_size50_36_, fle_6___in_0_, mux_2level_size50_36_sram_blwl_out[2242:2257] , -mux_2level_size50_36_sram_blwl_outb[2242:2257] ); -//----- SRAM bits for MUX[36], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2242_ (mux_2level_size50_36_sram_blwl_out[2242:2242] ,mux_2level_size50_36_sram_blwl_out[2242:2242] ,mux_2level_size50_36_sram_blwl_outb[2242:2242] ,mux_2level_size50_36_configbus0[2242:2242], mux_2level_size50_36_configbus1[2242:2242] , mux_2level_size50_36_configbus0_b[2242:2242] ); -sram6T_blwl sram_blwl_2243_ (mux_2level_size50_36_sram_blwl_out[2243:2243] ,mux_2level_size50_36_sram_blwl_out[2243:2243] ,mux_2level_size50_36_sram_blwl_outb[2243:2243] ,mux_2level_size50_36_configbus0[2243:2243], mux_2level_size50_36_configbus1[2243:2243] , mux_2level_size50_36_configbus0_b[2243:2243] ); -sram6T_blwl sram_blwl_2244_ (mux_2level_size50_36_sram_blwl_out[2244:2244] ,mux_2level_size50_36_sram_blwl_out[2244:2244] ,mux_2level_size50_36_sram_blwl_outb[2244:2244] ,mux_2level_size50_36_configbus0[2244:2244], mux_2level_size50_36_configbus1[2244:2244] , mux_2level_size50_36_configbus0_b[2244:2244] ); -sram6T_blwl sram_blwl_2245_ (mux_2level_size50_36_sram_blwl_out[2245:2245] ,mux_2level_size50_36_sram_blwl_out[2245:2245] ,mux_2level_size50_36_sram_blwl_outb[2245:2245] ,mux_2level_size50_36_configbus0[2245:2245], mux_2level_size50_36_configbus1[2245:2245] , mux_2level_size50_36_configbus0_b[2245:2245] ); -sram6T_blwl sram_blwl_2246_ (mux_2level_size50_36_sram_blwl_out[2246:2246] ,mux_2level_size50_36_sram_blwl_out[2246:2246] ,mux_2level_size50_36_sram_blwl_outb[2246:2246] ,mux_2level_size50_36_configbus0[2246:2246], mux_2level_size50_36_configbus1[2246:2246] , mux_2level_size50_36_configbus0_b[2246:2246] ); -sram6T_blwl sram_blwl_2247_ (mux_2level_size50_36_sram_blwl_out[2247:2247] ,mux_2level_size50_36_sram_blwl_out[2247:2247] ,mux_2level_size50_36_sram_blwl_outb[2247:2247] ,mux_2level_size50_36_configbus0[2247:2247], mux_2level_size50_36_configbus1[2247:2247] , mux_2level_size50_36_configbus0_b[2247:2247] ); -sram6T_blwl sram_blwl_2248_ (mux_2level_size50_36_sram_blwl_out[2248:2248] ,mux_2level_size50_36_sram_blwl_out[2248:2248] ,mux_2level_size50_36_sram_blwl_outb[2248:2248] ,mux_2level_size50_36_configbus0[2248:2248], mux_2level_size50_36_configbus1[2248:2248] , mux_2level_size50_36_configbus0_b[2248:2248] ); -sram6T_blwl sram_blwl_2249_ (mux_2level_size50_36_sram_blwl_out[2249:2249] ,mux_2level_size50_36_sram_blwl_out[2249:2249] ,mux_2level_size50_36_sram_blwl_outb[2249:2249] ,mux_2level_size50_36_configbus0[2249:2249], mux_2level_size50_36_configbus1[2249:2249] , mux_2level_size50_36_configbus0_b[2249:2249] ); -sram6T_blwl sram_blwl_2250_ (mux_2level_size50_36_sram_blwl_out[2250:2250] ,mux_2level_size50_36_sram_blwl_out[2250:2250] ,mux_2level_size50_36_sram_blwl_outb[2250:2250] ,mux_2level_size50_36_configbus0[2250:2250], mux_2level_size50_36_configbus1[2250:2250] , mux_2level_size50_36_configbus0_b[2250:2250] ); -sram6T_blwl sram_blwl_2251_ (mux_2level_size50_36_sram_blwl_out[2251:2251] ,mux_2level_size50_36_sram_blwl_out[2251:2251] ,mux_2level_size50_36_sram_blwl_outb[2251:2251] ,mux_2level_size50_36_configbus0[2251:2251], mux_2level_size50_36_configbus1[2251:2251] , mux_2level_size50_36_configbus0_b[2251:2251] ); -sram6T_blwl sram_blwl_2252_ (mux_2level_size50_36_sram_blwl_out[2252:2252] ,mux_2level_size50_36_sram_blwl_out[2252:2252] ,mux_2level_size50_36_sram_blwl_outb[2252:2252] ,mux_2level_size50_36_configbus0[2252:2252], mux_2level_size50_36_configbus1[2252:2252] , mux_2level_size50_36_configbus0_b[2252:2252] ); -sram6T_blwl sram_blwl_2253_ (mux_2level_size50_36_sram_blwl_out[2253:2253] ,mux_2level_size50_36_sram_blwl_out[2253:2253] ,mux_2level_size50_36_sram_blwl_outb[2253:2253] ,mux_2level_size50_36_configbus0[2253:2253], mux_2level_size50_36_configbus1[2253:2253] , mux_2level_size50_36_configbus0_b[2253:2253] ); -sram6T_blwl sram_blwl_2254_ (mux_2level_size50_36_sram_blwl_out[2254:2254] ,mux_2level_size50_36_sram_blwl_out[2254:2254] ,mux_2level_size50_36_sram_blwl_outb[2254:2254] ,mux_2level_size50_36_configbus0[2254:2254], mux_2level_size50_36_configbus1[2254:2254] , mux_2level_size50_36_configbus0_b[2254:2254] ); -sram6T_blwl sram_blwl_2255_ (mux_2level_size50_36_sram_blwl_out[2255:2255] ,mux_2level_size50_36_sram_blwl_out[2255:2255] ,mux_2level_size50_36_sram_blwl_outb[2255:2255] ,mux_2level_size50_36_configbus0[2255:2255], mux_2level_size50_36_configbus1[2255:2255] , mux_2level_size50_36_configbus0_b[2255:2255] ); -sram6T_blwl sram_blwl_2256_ (mux_2level_size50_36_sram_blwl_out[2256:2256] ,mux_2level_size50_36_sram_blwl_out[2256:2256] ,mux_2level_size50_36_sram_blwl_outb[2256:2256] ,mux_2level_size50_36_configbus0[2256:2256], mux_2level_size50_36_configbus1[2256:2256] , mux_2level_size50_36_configbus0_b[2256:2256] ); -sram6T_blwl sram_blwl_2257_ (mux_2level_size50_36_sram_blwl_out[2257:2257] ,mux_2level_size50_36_sram_blwl_out[2257:2257] ,mux_2level_size50_36_sram_blwl_outb[2257:2257] ,mux_2level_size50_36_configbus0[2257:2257], mux_2level_size50_36_configbus1[2257:2257] , mux_2level_size50_36_configbus0_b[2257:2257] ); -wire [0:49] in_bus_mux_2level_size50_37_ ; -assign in_bus_mux_2level_size50_37_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_37_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_37_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_37_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_37_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_37_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_37_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_37_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_37_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_37_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_37_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_37_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_37_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_37_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_37_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_37_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_37_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_37_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_37_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_37_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_37_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_37_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_37_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_37_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_37_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_37_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_37_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_37_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_37_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_37_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_37_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_37_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_37_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_37_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_37_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_37_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_37_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_37_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_37_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_37_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_37_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_37_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_37_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_37_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_37_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_37_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_37_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_37_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_37_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_37_[49] = fle_9___out_0_ ; -wire [2258:2273] mux_2level_size50_37_configbus0; -wire [2258:2273] mux_2level_size50_37_configbus1; -wire [2258:2273] mux_2level_size50_37_sram_blwl_out ; -wire [2258:2273] mux_2level_size50_37_sram_blwl_outb ; -assign mux_2level_size50_37_configbus0[2258:2273] = sram_blwl_bl[2258:2273] ; -assign mux_2level_size50_37_configbus1[2258:2273] = sram_blwl_wl[2258:2273] ; -wire [2258:2273] mux_2level_size50_37_configbus0_b; -assign mux_2level_size50_37_configbus0_b[2258:2273] = sram_blwl_blb[2258:2273] ; -mux_2level_size50 mux_2level_size50_37_ (in_bus_mux_2level_size50_37_, fle_6___in_1_, mux_2level_size50_37_sram_blwl_out[2258:2273] , -mux_2level_size50_37_sram_blwl_outb[2258:2273] ); -//----- SRAM bits for MUX[37], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2258_ (mux_2level_size50_37_sram_blwl_out[2258:2258] ,mux_2level_size50_37_sram_blwl_out[2258:2258] ,mux_2level_size50_37_sram_blwl_outb[2258:2258] ,mux_2level_size50_37_configbus0[2258:2258], mux_2level_size50_37_configbus1[2258:2258] , mux_2level_size50_37_configbus0_b[2258:2258] ); -sram6T_blwl sram_blwl_2259_ (mux_2level_size50_37_sram_blwl_out[2259:2259] ,mux_2level_size50_37_sram_blwl_out[2259:2259] ,mux_2level_size50_37_sram_blwl_outb[2259:2259] ,mux_2level_size50_37_configbus0[2259:2259], mux_2level_size50_37_configbus1[2259:2259] , mux_2level_size50_37_configbus0_b[2259:2259] ); -sram6T_blwl sram_blwl_2260_ (mux_2level_size50_37_sram_blwl_out[2260:2260] ,mux_2level_size50_37_sram_blwl_out[2260:2260] ,mux_2level_size50_37_sram_blwl_outb[2260:2260] ,mux_2level_size50_37_configbus0[2260:2260], mux_2level_size50_37_configbus1[2260:2260] , mux_2level_size50_37_configbus0_b[2260:2260] ); -sram6T_blwl sram_blwl_2261_ (mux_2level_size50_37_sram_blwl_out[2261:2261] ,mux_2level_size50_37_sram_blwl_out[2261:2261] ,mux_2level_size50_37_sram_blwl_outb[2261:2261] ,mux_2level_size50_37_configbus0[2261:2261], mux_2level_size50_37_configbus1[2261:2261] , mux_2level_size50_37_configbus0_b[2261:2261] ); -sram6T_blwl sram_blwl_2262_ (mux_2level_size50_37_sram_blwl_out[2262:2262] ,mux_2level_size50_37_sram_blwl_out[2262:2262] ,mux_2level_size50_37_sram_blwl_outb[2262:2262] ,mux_2level_size50_37_configbus0[2262:2262], mux_2level_size50_37_configbus1[2262:2262] , mux_2level_size50_37_configbus0_b[2262:2262] ); -sram6T_blwl sram_blwl_2263_ (mux_2level_size50_37_sram_blwl_out[2263:2263] ,mux_2level_size50_37_sram_blwl_out[2263:2263] ,mux_2level_size50_37_sram_blwl_outb[2263:2263] ,mux_2level_size50_37_configbus0[2263:2263], mux_2level_size50_37_configbus1[2263:2263] , mux_2level_size50_37_configbus0_b[2263:2263] ); -sram6T_blwl sram_blwl_2264_ (mux_2level_size50_37_sram_blwl_out[2264:2264] ,mux_2level_size50_37_sram_blwl_out[2264:2264] ,mux_2level_size50_37_sram_blwl_outb[2264:2264] ,mux_2level_size50_37_configbus0[2264:2264], mux_2level_size50_37_configbus1[2264:2264] , mux_2level_size50_37_configbus0_b[2264:2264] ); -sram6T_blwl sram_blwl_2265_ (mux_2level_size50_37_sram_blwl_out[2265:2265] ,mux_2level_size50_37_sram_blwl_out[2265:2265] ,mux_2level_size50_37_sram_blwl_outb[2265:2265] ,mux_2level_size50_37_configbus0[2265:2265], mux_2level_size50_37_configbus1[2265:2265] , mux_2level_size50_37_configbus0_b[2265:2265] ); -sram6T_blwl sram_blwl_2266_ (mux_2level_size50_37_sram_blwl_out[2266:2266] ,mux_2level_size50_37_sram_blwl_out[2266:2266] ,mux_2level_size50_37_sram_blwl_outb[2266:2266] ,mux_2level_size50_37_configbus0[2266:2266], mux_2level_size50_37_configbus1[2266:2266] , mux_2level_size50_37_configbus0_b[2266:2266] ); -sram6T_blwl sram_blwl_2267_ (mux_2level_size50_37_sram_blwl_out[2267:2267] ,mux_2level_size50_37_sram_blwl_out[2267:2267] ,mux_2level_size50_37_sram_blwl_outb[2267:2267] ,mux_2level_size50_37_configbus0[2267:2267], mux_2level_size50_37_configbus1[2267:2267] , mux_2level_size50_37_configbus0_b[2267:2267] ); -sram6T_blwl sram_blwl_2268_ (mux_2level_size50_37_sram_blwl_out[2268:2268] ,mux_2level_size50_37_sram_blwl_out[2268:2268] ,mux_2level_size50_37_sram_blwl_outb[2268:2268] ,mux_2level_size50_37_configbus0[2268:2268], mux_2level_size50_37_configbus1[2268:2268] , mux_2level_size50_37_configbus0_b[2268:2268] ); -sram6T_blwl sram_blwl_2269_ (mux_2level_size50_37_sram_blwl_out[2269:2269] ,mux_2level_size50_37_sram_blwl_out[2269:2269] ,mux_2level_size50_37_sram_blwl_outb[2269:2269] ,mux_2level_size50_37_configbus0[2269:2269], mux_2level_size50_37_configbus1[2269:2269] , mux_2level_size50_37_configbus0_b[2269:2269] ); -sram6T_blwl sram_blwl_2270_ (mux_2level_size50_37_sram_blwl_out[2270:2270] ,mux_2level_size50_37_sram_blwl_out[2270:2270] ,mux_2level_size50_37_sram_blwl_outb[2270:2270] ,mux_2level_size50_37_configbus0[2270:2270], mux_2level_size50_37_configbus1[2270:2270] , mux_2level_size50_37_configbus0_b[2270:2270] ); -sram6T_blwl sram_blwl_2271_ (mux_2level_size50_37_sram_blwl_out[2271:2271] ,mux_2level_size50_37_sram_blwl_out[2271:2271] ,mux_2level_size50_37_sram_blwl_outb[2271:2271] ,mux_2level_size50_37_configbus0[2271:2271], mux_2level_size50_37_configbus1[2271:2271] , mux_2level_size50_37_configbus0_b[2271:2271] ); -sram6T_blwl sram_blwl_2272_ (mux_2level_size50_37_sram_blwl_out[2272:2272] ,mux_2level_size50_37_sram_blwl_out[2272:2272] ,mux_2level_size50_37_sram_blwl_outb[2272:2272] ,mux_2level_size50_37_configbus0[2272:2272], mux_2level_size50_37_configbus1[2272:2272] , mux_2level_size50_37_configbus0_b[2272:2272] ); -sram6T_blwl sram_blwl_2273_ (mux_2level_size50_37_sram_blwl_out[2273:2273] ,mux_2level_size50_37_sram_blwl_out[2273:2273] ,mux_2level_size50_37_sram_blwl_outb[2273:2273] ,mux_2level_size50_37_configbus0[2273:2273], mux_2level_size50_37_configbus1[2273:2273] , mux_2level_size50_37_configbus0_b[2273:2273] ); -wire [0:49] in_bus_mux_2level_size50_38_ ; -assign in_bus_mux_2level_size50_38_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_38_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_38_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_38_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_38_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_38_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_38_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_38_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_38_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_38_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_38_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_38_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_38_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_38_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_38_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_38_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_38_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_38_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_38_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_38_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_38_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_38_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_38_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_38_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_38_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_38_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_38_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_38_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_38_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_38_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_38_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_38_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_38_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_38_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_38_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_38_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_38_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_38_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_38_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_38_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_38_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_38_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_38_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_38_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_38_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_38_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_38_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_38_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_38_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_38_[49] = fle_9___out_0_ ; -wire [2274:2289] mux_2level_size50_38_configbus0; -wire [2274:2289] mux_2level_size50_38_configbus1; -wire [2274:2289] mux_2level_size50_38_sram_blwl_out ; -wire [2274:2289] mux_2level_size50_38_sram_blwl_outb ; -assign mux_2level_size50_38_configbus0[2274:2289] = sram_blwl_bl[2274:2289] ; -assign mux_2level_size50_38_configbus1[2274:2289] = sram_blwl_wl[2274:2289] ; -wire [2274:2289] mux_2level_size50_38_configbus0_b; -assign mux_2level_size50_38_configbus0_b[2274:2289] = sram_blwl_blb[2274:2289] ; -mux_2level_size50 mux_2level_size50_38_ (in_bus_mux_2level_size50_38_, fle_6___in_2_, mux_2level_size50_38_sram_blwl_out[2274:2289] , -mux_2level_size50_38_sram_blwl_outb[2274:2289] ); -//----- SRAM bits for MUX[38], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2274_ (mux_2level_size50_38_sram_blwl_out[2274:2274] ,mux_2level_size50_38_sram_blwl_out[2274:2274] ,mux_2level_size50_38_sram_blwl_outb[2274:2274] ,mux_2level_size50_38_configbus0[2274:2274], mux_2level_size50_38_configbus1[2274:2274] , mux_2level_size50_38_configbus0_b[2274:2274] ); -sram6T_blwl sram_blwl_2275_ (mux_2level_size50_38_sram_blwl_out[2275:2275] ,mux_2level_size50_38_sram_blwl_out[2275:2275] ,mux_2level_size50_38_sram_blwl_outb[2275:2275] ,mux_2level_size50_38_configbus0[2275:2275], mux_2level_size50_38_configbus1[2275:2275] , mux_2level_size50_38_configbus0_b[2275:2275] ); -sram6T_blwl sram_blwl_2276_ (mux_2level_size50_38_sram_blwl_out[2276:2276] ,mux_2level_size50_38_sram_blwl_out[2276:2276] ,mux_2level_size50_38_sram_blwl_outb[2276:2276] ,mux_2level_size50_38_configbus0[2276:2276], mux_2level_size50_38_configbus1[2276:2276] , mux_2level_size50_38_configbus0_b[2276:2276] ); -sram6T_blwl sram_blwl_2277_ (mux_2level_size50_38_sram_blwl_out[2277:2277] ,mux_2level_size50_38_sram_blwl_out[2277:2277] ,mux_2level_size50_38_sram_blwl_outb[2277:2277] ,mux_2level_size50_38_configbus0[2277:2277], mux_2level_size50_38_configbus1[2277:2277] , mux_2level_size50_38_configbus0_b[2277:2277] ); -sram6T_blwl sram_blwl_2278_ (mux_2level_size50_38_sram_blwl_out[2278:2278] ,mux_2level_size50_38_sram_blwl_out[2278:2278] ,mux_2level_size50_38_sram_blwl_outb[2278:2278] ,mux_2level_size50_38_configbus0[2278:2278], mux_2level_size50_38_configbus1[2278:2278] , mux_2level_size50_38_configbus0_b[2278:2278] ); -sram6T_blwl sram_blwl_2279_ (mux_2level_size50_38_sram_blwl_out[2279:2279] ,mux_2level_size50_38_sram_blwl_out[2279:2279] ,mux_2level_size50_38_sram_blwl_outb[2279:2279] ,mux_2level_size50_38_configbus0[2279:2279], mux_2level_size50_38_configbus1[2279:2279] , mux_2level_size50_38_configbus0_b[2279:2279] ); -sram6T_blwl sram_blwl_2280_ (mux_2level_size50_38_sram_blwl_out[2280:2280] ,mux_2level_size50_38_sram_blwl_out[2280:2280] ,mux_2level_size50_38_sram_blwl_outb[2280:2280] ,mux_2level_size50_38_configbus0[2280:2280], mux_2level_size50_38_configbus1[2280:2280] , mux_2level_size50_38_configbus0_b[2280:2280] ); -sram6T_blwl sram_blwl_2281_ (mux_2level_size50_38_sram_blwl_out[2281:2281] ,mux_2level_size50_38_sram_blwl_out[2281:2281] ,mux_2level_size50_38_sram_blwl_outb[2281:2281] ,mux_2level_size50_38_configbus0[2281:2281], mux_2level_size50_38_configbus1[2281:2281] , mux_2level_size50_38_configbus0_b[2281:2281] ); -sram6T_blwl sram_blwl_2282_ (mux_2level_size50_38_sram_blwl_out[2282:2282] ,mux_2level_size50_38_sram_blwl_out[2282:2282] ,mux_2level_size50_38_sram_blwl_outb[2282:2282] ,mux_2level_size50_38_configbus0[2282:2282], mux_2level_size50_38_configbus1[2282:2282] , mux_2level_size50_38_configbus0_b[2282:2282] ); -sram6T_blwl sram_blwl_2283_ (mux_2level_size50_38_sram_blwl_out[2283:2283] ,mux_2level_size50_38_sram_blwl_out[2283:2283] ,mux_2level_size50_38_sram_blwl_outb[2283:2283] ,mux_2level_size50_38_configbus0[2283:2283], mux_2level_size50_38_configbus1[2283:2283] , mux_2level_size50_38_configbus0_b[2283:2283] ); -sram6T_blwl sram_blwl_2284_ (mux_2level_size50_38_sram_blwl_out[2284:2284] ,mux_2level_size50_38_sram_blwl_out[2284:2284] ,mux_2level_size50_38_sram_blwl_outb[2284:2284] ,mux_2level_size50_38_configbus0[2284:2284], mux_2level_size50_38_configbus1[2284:2284] , mux_2level_size50_38_configbus0_b[2284:2284] ); -sram6T_blwl sram_blwl_2285_ (mux_2level_size50_38_sram_blwl_out[2285:2285] ,mux_2level_size50_38_sram_blwl_out[2285:2285] ,mux_2level_size50_38_sram_blwl_outb[2285:2285] ,mux_2level_size50_38_configbus0[2285:2285], mux_2level_size50_38_configbus1[2285:2285] , mux_2level_size50_38_configbus0_b[2285:2285] ); -sram6T_blwl sram_blwl_2286_ (mux_2level_size50_38_sram_blwl_out[2286:2286] ,mux_2level_size50_38_sram_blwl_out[2286:2286] ,mux_2level_size50_38_sram_blwl_outb[2286:2286] ,mux_2level_size50_38_configbus0[2286:2286], mux_2level_size50_38_configbus1[2286:2286] , mux_2level_size50_38_configbus0_b[2286:2286] ); -sram6T_blwl sram_blwl_2287_ (mux_2level_size50_38_sram_blwl_out[2287:2287] ,mux_2level_size50_38_sram_blwl_out[2287:2287] ,mux_2level_size50_38_sram_blwl_outb[2287:2287] ,mux_2level_size50_38_configbus0[2287:2287], mux_2level_size50_38_configbus1[2287:2287] , mux_2level_size50_38_configbus0_b[2287:2287] ); -sram6T_blwl sram_blwl_2288_ (mux_2level_size50_38_sram_blwl_out[2288:2288] ,mux_2level_size50_38_sram_blwl_out[2288:2288] ,mux_2level_size50_38_sram_blwl_outb[2288:2288] ,mux_2level_size50_38_configbus0[2288:2288], mux_2level_size50_38_configbus1[2288:2288] , mux_2level_size50_38_configbus0_b[2288:2288] ); -sram6T_blwl sram_blwl_2289_ (mux_2level_size50_38_sram_blwl_out[2289:2289] ,mux_2level_size50_38_sram_blwl_out[2289:2289] ,mux_2level_size50_38_sram_blwl_outb[2289:2289] ,mux_2level_size50_38_configbus0[2289:2289], mux_2level_size50_38_configbus1[2289:2289] , mux_2level_size50_38_configbus0_b[2289:2289] ); -wire [0:49] in_bus_mux_2level_size50_39_ ; -assign in_bus_mux_2level_size50_39_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_39_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_39_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_39_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_39_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_39_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_39_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_39_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_39_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_39_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_39_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_39_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_39_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_39_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_39_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_39_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_39_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_39_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_39_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_39_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_39_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_39_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_39_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_39_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_39_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_39_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_39_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_39_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_39_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_39_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_39_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_39_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_39_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_39_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_39_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_39_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_39_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_39_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_39_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_39_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_39_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_39_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_39_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_39_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_39_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_39_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_39_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_39_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_39_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_39_[49] = fle_9___out_0_ ; -wire [2290:2305] mux_2level_size50_39_configbus0; -wire [2290:2305] mux_2level_size50_39_configbus1; -wire [2290:2305] mux_2level_size50_39_sram_blwl_out ; -wire [2290:2305] mux_2level_size50_39_sram_blwl_outb ; -assign mux_2level_size50_39_configbus0[2290:2305] = sram_blwl_bl[2290:2305] ; -assign mux_2level_size50_39_configbus1[2290:2305] = sram_blwl_wl[2290:2305] ; -wire [2290:2305] mux_2level_size50_39_configbus0_b; -assign mux_2level_size50_39_configbus0_b[2290:2305] = sram_blwl_blb[2290:2305] ; -mux_2level_size50 mux_2level_size50_39_ (in_bus_mux_2level_size50_39_, fle_6___in_3_, mux_2level_size50_39_sram_blwl_out[2290:2305] , -mux_2level_size50_39_sram_blwl_outb[2290:2305] ); -//----- SRAM bits for MUX[39], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2290_ (mux_2level_size50_39_sram_blwl_out[2290:2290] ,mux_2level_size50_39_sram_blwl_out[2290:2290] ,mux_2level_size50_39_sram_blwl_outb[2290:2290] ,mux_2level_size50_39_configbus0[2290:2290], mux_2level_size50_39_configbus1[2290:2290] , mux_2level_size50_39_configbus0_b[2290:2290] ); -sram6T_blwl sram_blwl_2291_ (mux_2level_size50_39_sram_blwl_out[2291:2291] ,mux_2level_size50_39_sram_blwl_out[2291:2291] ,mux_2level_size50_39_sram_blwl_outb[2291:2291] ,mux_2level_size50_39_configbus0[2291:2291], mux_2level_size50_39_configbus1[2291:2291] , mux_2level_size50_39_configbus0_b[2291:2291] ); -sram6T_blwl sram_blwl_2292_ (mux_2level_size50_39_sram_blwl_out[2292:2292] ,mux_2level_size50_39_sram_blwl_out[2292:2292] ,mux_2level_size50_39_sram_blwl_outb[2292:2292] ,mux_2level_size50_39_configbus0[2292:2292], mux_2level_size50_39_configbus1[2292:2292] , mux_2level_size50_39_configbus0_b[2292:2292] ); -sram6T_blwl sram_blwl_2293_ (mux_2level_size50_39_sram_blwl_out[2293:2293] ,mux_2level_size50_39_sram_blwl_out[2293:2293] ,mux_2level_size50_39_sram_blwl_outb[2293:2293] ,mux_2level_size50_39_configbus0[2293:2293], mux_2level_size50_39_configbus1[2293:2293] , mux_2level_size50_39_configbus0_b[2293:2293] ); -sram6T_blwl sram_blwl_2294_ (mux_2level_size50_39_sram_blwl_out[2294:2294] ,mux_2level_size50_39_sram_blwl_out[2294:2294] ,mux_2level_size50_39_sram_blwl_outb[2294:2294] ,mux_2level_size50_39_configbus0[2294:2294], mux_2level_size50_39_configbus1[2294:2294] , mux_2level_size50_39_configbus0_b[2294:2294] ); -sram6T_blwl sram_blwl_2295_ (mux_2level_size50_39_sram_blwl_out[2295:2295] ,mux_2level_size50_39_sram_blwl_out[2295:2295] ,mux_2level_size50_39_sram_blwl_outb[2295:2295] ,mux_2level_size50_39_configbus0[2295:2295], mux_2level_size50_39_configbus1[2295:2295] , mux_2level_size50_39_configbus0_b[2295:2295] ); -sram6T_blwl sram_blwl_2296_ (mux_2level_size50_39_sram_blwl_out[2296:2296] ,mux_2level_size50_39_sram_blwl_out[2296:2296] ,mux_2level_size50_39_sram_blwl_outb[2296:2296] ,mux_2level_size50_39_configbus0[2296:2296], mux_2level_size50_39_configbus1[2296:2296] , mux_2level_size50_39_configbus0_b[2296:2296] ); -sram6T_blwl sram_blwl_2297_ (mux_2level_size50_39_sram_blwl_out[2297:2297] ,mux_2level_size50_39_sram_blwl_out[2297:2297] ,mux_2level_size50_39_sram_blwl_outb[2297:2297] ,mux_2level_size50_39_configbus0[2297:2297], mux_2level_size50_39_configbus1[2297:2297] , mux_2level_size50_39_configbus0_b[2297:2297] ); -sram6T_blwl sram_blwl_2298_ (mux_2level_size50_39_sram_blwl_out[2298:2298] ,mux_2level_size50_39_sram_blwl_out[2298:2298] ,mux_2level_size50_39_sram_blwl_outb[2298:2298] ,mux_2level_size50_39_configbus0[2298:2298], mux_2level_size50_39_configbus1[2298:2298] , mux_2level_size50_39_configbus0_b[2298:2298] ); -sram6T_blwl sram_blwl_2299_ (mux_2level_size50_39_sram_blwl_out[2299:2299] ,mux_2level_size50_39_sram_blwl_out[2299:2299] ,mux_2level_size50_39_sram_blwl_outb[2299:2299] ,mux_2level_size50_39_configbus0[2299:2299], mux_2level_size50_39_configbus1[2299:2299] , mux_2level_size50_39_configbus0_b[2299:2299] ); -sram6T_blwl sram_blwl_2300_ (mux_2level_size50_39_sram_blwl_out[2300:2300] ,mux_2level_size50_39_sram_blwl_out[2300:2300] ,mux_2level_size50_39_sram_blwl_outb[2300:2300] ,mux_2level_size50_39_configbus0[2300:2300], mux_2level_size50_39_configbus1[2300:2300] , mux_2level_size50_39_configbus0_b[2300:2300] ); -sram6T_blwl sram_blwl_2301_ (mux_2level_size50_39_sram_blwl_out[2301:2301] ,mux_2level_size50_39_sram_blwl_out[2301:2301] ,mux_2level_size50_39_sram_blwl_outb[2301:2301] ,mux_2level_size50_39_configbus0[2301:2301], mux_2level_size50_39_configbus1[2301:2301] , mux_2level_size50_39_configbus0_b[2301:2301] ); -sram6T_blwl sram_blwl_2302_ (mux_2level_size50_39_sram_blwl_out[2302:2302] ,mux_2level_size50_39_sram_blwl_out[2302:2302] ,mux_2level_size50_39_sram_blwl_outb[2302:2302] ,mux_2level_size50_39_configbus0[2302:2302], mux_2level_size50_39_configbus1[2302:2302] , mux_2level_size50_39_configbus0_b[2302:2302] ); -sram6T_blwl sram_blwl_2303_ (mux_2level_size50_39_sram_blwl_out[2303:2303] ,mux_2level_size50_39_sram_blwl_out[2303:2303] ,mux_2level_size50_39_sram_blwl_outb[2303:2303] ,mux_2level_size50_39_configbus0[2303:2303], mux_2level_size50_39_configbus1[2303:2303] , mux_2level_size50_39_configbus0_b[2303:2303] ); -sram6T_blwl sram_blwl_2304_ (mux_2level_size50_39_sram_blwl_out[2304:2304] ,mux_2level_size50_39_sram_blwl_out[2304:2304] ,mux_2level_size50_39_sram_blwl_outb[2304:2304] ,mux_2level_size50_39_configbus0[2304:2304], mux_2level_size50_39_configbus1[2304:2304] , mux_2level_size50_39_configbus0_b[2304:2304] ); -sram6T_blwl sram_blwl_2305_ (mux_2level_size50_39_sram_blwl_out[2305:2305] ,mux_2level_size50_39_sram_blwl_out[2305:2305] ,mux_2level_size50_39_sram_blwl_outb[2305:2305] ,mux_2level_size50_39_configbus0[2305:2305], mux_2level_size50_39_configbus1[2305:2305] , mux_2level_size50_39_configbus0_b[2305:2305] ); -wire [0:49] in_bus_mux_2level_size50_40_ ; -assign in_bus_mux_2level_size50_40_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_40_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_40_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_40_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_40_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_40_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_40_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_40_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_40_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_40_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_40_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_40_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_40_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_40_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_40_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_40_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_40_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_40_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_40_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_40_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_40_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_40_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_40_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_40_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_40_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_40_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_40_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_40_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_40_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_40_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_40_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_40_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_40_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_40_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_40_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_40_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_40_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_40_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_40_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_40_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_40_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_40_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_40_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_40_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_40_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_40_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_40_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_40_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_40_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_40_[49] = fle_9___out_0_ ; -wire [2306:2321] mux_2level_size50_40_configbus0; -wire [2306:2321] mux_2level_size50_40_configbus1; -wire [2306:2321] mux_2level_size50_40_sram_blwl_out ; -wire [2306:2321] mux_2level_size50_40_sram_blwl_outb ; -assign mux_2level_size50_40_configbus0[2306:2321] = sram_blwl_bl[2306:2321] ; -assign mux_2level_size50_40_configbus1[2306:2321] = sram_blwl_wl[2306:2321] ; -wire [2306:2321] mux_2level_size50_40_configbus0_b; -assign mux_2level_size50_40_configbus0_b[2306:2321] = sram_blwl_blb[2306:2321] ; -mux_2level_size50 mux_2level_size50_40_ (in_bus_mux_2level_size50_40_, fle_6___in_4_, mux_2level_size50_40_sram_blwl_out[2306:2321] , -mux_2level_size50_40_sram_blwl_outb[2306:2321] ); -//----- SRAM bits for MUX[40], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2306_ (mux_2level_size50_40_sram_blwl_out[2306:2306] ,mux_2level_size50_40_sram_blwl_out[2306:2306] ,mux_2level_size50_40_sram_blwl_outb[2306:2306] ,mux_2level_size50_40_configbus0[2306:2306], mux_2level_size50_40_configbus1[2306:2306] , mux_2level_size50_40_configbus0_b[2306:2306] ); -sram6T_blwl sram_blwl_2307_ (mux_2level_size50_40_sram_blwl_out[2307:2307] ,mux_2level_size50_40_sram_blwl_out[2307:2307] ,mux_2level_size50_40_sram_blwl_outb[2307:2307] ,mux_2level_size50_40_configbus0[2307:2307], mux_2level_size50_40_configbus1[2307:2307] , mux_2level_size50_40_configbus0_b[2307:2307] ); -sram6T_blwl sram_blwl_2308_ (mux_2level_size50_40_sram_blwl_out[2308:2308] ,mux_2level_size50_40_sram_blwl_out[2308:2308] ,mux_2level_size50_40_sram_blwl_outb[2308:2308] ,mux_2level_size50_40_configbus0[2308:2308], mux_2level_size50_40_configbus1[2308:2308] , mux_2level_size50_40_configbus0_b[2308:2308] ); -sram6T_blwl sram_blwl_2309_ (mux_2level_size50_40_sram_blwl_out[2309:2309] ,mux_2level_size50_40_sram_blwl_out[2309:2309] ,mux_2level_size50_40_sram_blwl_outb[2309:2309] ,mux_2level_size50_40_configbus0[2309:2309], mux_2level_size50_40_configbus1[2309:2309] , mux_2level_size50_40_configbus0_b[2309:2309] ); -sram6T_blwl sram_blwl_2310_ (mux_2level_size50_40_sram_blwl_out[2310:2310] ,mux_2level_size50_40_sram_blwl_out[2310:2310] ,mux_2level_size50_40_sram_blwl_outb[2310:2310] ,mux_2level_size50_40_configbus0[2310:2310], mux_2level_size50_40_configbus1[2310:2310] , mux_2level_size50_40_configbus0_b[2310:2310] ); -sram6T_blwl sram_blwl_2311_ (mux_2level_size50_40_sram_blwl_out[2311:2311] ,mux_2level_size50_40_sram_blwl_out[2311:2311] ,mux_2level_size50_40_sram_blwl_outb[2311:2311] ,mux_2level_size50_40_configbus0[2311:2311], mux_2level_size50_40_configbus1[2311:2311] , mux_2level_size50_40_configbus0_b[2311:2311] ); -sram6T_blwl sram_blwl_2312_ (mux_2level_size50_40_sram_blwl_out[2312:2312] ,mux_2level_size50_40_sram_blwl_out[2312:2312] ,mux_2level_size50_40_sram_blwl_outb[2312:2312] ,mux_2level_size50_40_configbus0[2312:2312], mux_2level_size50_40_configbus1[2312:2312] , mux_2level_size50_40_configbus0_b[2312:2312] ); -sram6T_blwl sram_blwl_2313_ (mux_2level_size50_40_sram_blwl_out[2313:2313] ,mux_2level_size50_40_sram_blwl_out[2313:2313] ,mux_2level_size50_40_sram_blwl_outb[2313:2313] ,mux_2level_size50_40_configbus0[2313:2313], mux_2level_size50_40_configbus1[2313:2313] , mux_2level_size50_40_configbus0_b[2313:2313] ); -sram6T_blwl sram_blwl_2314_ (mux_2level_size50_40_sram_blwl_out[2314:2314] ,mux_2level_size50_40_sram_blwl_out[2314:2314] ,mux_2level_size50_40_sram_blwl_outb[2314:2314] ,mux_2level_size50_40_configbus0[2314:2314], mux_2level_size50_40_configbus1[2314:2314] , mux_2level_size50_40_configbus0_b[2314:2314] ); -sram6T_blwl sram_blwl_2315_ (mux_2level_size50_40_sram_blwl_out[2315:2315] ,mux_2level_size50_40_sram_blwl_out[2315:2315] ,mux_2level_size50_40_sram_blwl_outb[2315:2315] ,mux_2level_size50_40_configbus0[2315:2315], mux_2level_size50_40_configbus1[2315:2315] , mux_2level_size50_40_configbus0_b[2315:2315] ); -sram6T_blwl sram_blwl_2316_ (mux_2level_size50_40_sram_blwl_out[2316:2316] ,mux_2level_size50_40_sram_blwl_out[2316:2316] ,mux_2level_size50_40_sram_blwl_outb[2316:2316] ,mux_2level_size50_40_configbus0[2316:2316], mux_2level_size50_40_configbus1[2316:2316] , mux_2level_size50_40_configbus0_b[2316:2316] ); -sram6T_blwl sram_blwl_2317_ (mux_2level_size50_40_sram_blwl_out[2317:2317] ,mux_2level_size50_40_sram_blwl_out[2317:2317] ,mux_2level_size50_40_sram_blwl_outb[2317:2317] ,mux_2level_size50_40_configbus0[2317:2317], mux_2level_size50_40_configbus1[2317:2317] , mux_2level_size50_40_configbus0_b[2317:2317] ); -sram6T_blwl sram_blwl_2318_ (mux_2level_size50_40_sram_blwl_out[2318:2318] ,mux_2level_size50_40_sram_blwl_out[2318:2318] ,mux_2level_size50_40_sram_blwl_outb[2318:2318] ,mux_2level_size50_40_configbus0[2318:2318], mux_2level_size50_40_configbus1[2318:2318] , mux_2level_size50_40_configbus0_b[2318:2318] ); -sram6T_blwl sram_blwl_2319_ (mux_2level_size50_40_sram_blwl_out[2319:2319] ,mux_2level_size50_40_sram_blwl_out[2319:2319] ,mux_2level_size50_40_sram_blwl_outb[2319:2319] ,mux_2level_size50_40_configbus0[2319:2319], mux_2level_size50_40_configbus1[2319:2319] , mux_2level_size50_40_configbus0_b[2319:2319] ); -sram6T_blwl sram_blwl_2320_ (mux_2level_size50_40_sram_blwl_out[2320:2320] ,mux_2level_size50_40_sram_blwl_out[2320:2320] ,mux_2level_size50_40_sram_blwl_outb[2320:2320] ,mux_2level_size50_40_configbus0[2320:2320], mux_2level_size50_40_configbus1[2320:2320] , mux_2level_size50_40_configbus0_b[2320:2320] ); -sram6T_blwl sram_blwl_2321_ (mux_2level_size50_40_sram_blwl_out[2321:2321] ,mux_2level_size50_40_sram_blwl_out[2321:2321] ,mux_2level_size50_40_sram_blwl_outb[2321:2321] ,mux_2level_size50_40_configbus0[2321:2321], mux_2level_size50_40_configbus1[2321:2321] , mux_2level_size50_40_configbus0_b[2321:2321] ); -wire [0:49] in_bus_mux_2level_size50_41_ ; -assign in_bus_mux_2level_size50_41_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_41_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_41_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_41_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_41_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_41_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_41_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_41_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_41_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_41_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_41_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_41_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_41_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_41_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_41_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_41_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_41_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_41_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_41_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_41_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_41_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_41_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_41_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_41_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_41_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_41_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_41_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_41_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_41_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_41_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_41_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_41_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_41_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_41_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_41_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_41_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_41_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_41_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_41_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_41_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_41_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_41_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_41_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_41_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_41_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_41_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_41_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_41_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_41_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_41_[49] = fle_9___out_0_ ; -wire [2322:2337] mux_2level_size50_41_configbus0; -wire [2322:2337] mux_2level_size50_41_configbus1; -wire [2322:2337] mux_2level_size50_41_sram_blwl_out ; -wire [2322:2337] mux_2level_size50_41_sram_blwl_outb ; -assign mux_2level_size50_41_configbus0[2322:2337] = sram_blwl_bl[2322:2337] ; -assign mux_2level_size50_41_configbus1[2322:2337] = sram_blwl_wl[2322:2337] ; -wire [2322:2337] mux_2level_size50_41_configbus0_b; -assign mux_2level_size50_41_configbus0_b[2322:2337] = sram_blwl_blb[2322:2337] ; -mux_2level_size50 mux_2level_size50_41_ (in_bus_mux_2level_size50_41_, fle_6___in_5_, mux_2level_size50_41_sram_blwl_out[2322:2337] , -mux_2level_size50_41_sram_blwl_outb[2322:2337] ); -//----- SRAM bits for MUX[41], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2322_ (mux_2level_size50_41_sram_blwl_out[2322:2322] ,mux_2level_size50_41_sram_blwl_out[2322:2322] ,mux_2level_size50_41_sram_blwl_outb[2322:2322] ,mux_2level_size50_41_configbus0[2322:2322], mux_2level_size50_41_configbus1[2322:2322] , mux_2level_size50_41_configbus0_b[2322:2322] ); -sram6T_blwl sram_blwl_2323_ (mux_2level_size50_41_sram_blwl_out[2323:2323] ,mux_2level_size50_41_sram_blwl_out[2323:2323] ,mux_2level_size50_41_sram_blwl_outb[2323:2323] ,mux_2level_size50_41_configbus0[2323:2323], mux_2level_size50_41_configbus1[2323:2323] , mux_2level_size50_41_configbus0_b[2323:2323] ); -sram6T_blwl sram_blwl_2324_ (mux_2level_size50_41_sram_blwl_out[2324:2324] ,mux_2level_size50_41_sram_blwl_out[2324:2324] ,mux_2level_size50_41_sram_blwl_outb[2324:2324] ,mux_2level_size50_41_configbus0[2324:2324], mux_2level_size50_41_configbus1[2324:2324] , mux_2level_size50_41_configbus0_b[2324:2324] ); -sram6T_blwl sram_blwl_2325_ (mux_2level_size50_41_sram_blwl_out[2325:2325] ,mux_2level_size50_41_sram_blwl_out[2325:2325] ,mux_2level_size50_41_sram_blwl_outb[2325:2325] ,mux_2level_size50_41_configbus0[2325:2325], mux_2level_size50_41_configbus1[2325:2325] , mux_2level_size50_41_configbus0_b[2325:2325] ); -sram6T_blwl sram_blwl_2326_ (mux_2level_size50_41_sram_blwl_out[2326:2326] ,mux_2level_size50_41_sram_blwl_out[2326:2326] ,mux_2level_size50_41_sram_blwl_outb[2326:2326] ,mux_2level_size50_41_configbus0[2326:2326], mux_2level_size50_41_configbus1[2326:2326] , mux_2level_size50_41_configbus0_b[2326:2326] ); -sram6T_blwl sram_blwl_2327_ (mux_2level_size50_41_sram_blwl_out[2327:2327] ,mux_2level_size50_41_sram_blwl_out[2327:2327] ,mux_2level_size50_41_sram_blwl_outb[2327:2327] ,mux_2level_size50_41_configbus0[2327:2327], mux_2level_size50_41_configbus1[2327:2327] , mux_2level_size50_41_configbus0_b[2327:2327] ); -sram6T_blwl sram_blwl_2328_ (mux_2level_size50_41_sram_blwl_out[2328:2328] ,mux_2level_size50_41_sram_blwl_out[2328:2328] ,mux_2level_size50_41_sram_blwl_outb[2328:2328] ,mux_2level_size50_41_configbus0[2328:2328], mux_2level_size50_41_configbus1[2328:2328] , mux_2level_size50_41_configbus0_b[2328:2328] ); -sram6T_blwl sram_blwl_2329_ (mux_2level_size50_41_sram_blwl_out[2329:2329] ,mux_2level_size50_41_sram_blwl_out[2329:2329] ,mux_2level_size50_41_sram_blwl_outb[2329:2329] ,mux_2level_size50_41_configbus0[2329:2329], mux_2level_size50_41_configbus1[2329:2329] , mux_2level_size50_41_configbus0_b[2329:2329] ); -sram6T_blwl sram_blwl_2330_ (mux_2level_size50_41_sram_blwl_out[2330:2330] ,mux_2level_size50_41_sram_blwl_out[2330:2330] ,mux_2level_size50_41_sram_blwl_outb[2330:2330] ,mux_2level_size50_41_configbus0[2330:2330], mux_2level_size50_41_configbus1[2330:2330] , mux_2level_size50_41_configbus0_b[2330:2330] ); -sram6T_blwl sram_blwl_2331_ (mux_2level_size50_41_sram_blwl_out[2331:2331] ,mux_2level_size50_41_sram_blwl_out[2331:2331] ,mux_2level_size50_41_sram_blwl_outb[2331:2331] ,mux_2level_size50_41_configbus0[2331:2331], mux_2level_size50_41_configbus1[2331:2331] , mux_2level_size50_41_configbus0_b[2331:2331] ); -sram6T_blwl sram_blwl_2332_ (mux_2level_size50_41_sram_blwl_out[2332:2332] ,mux_2level_size50_41_sram_blwl_out[2332:2332] ,mux_2level_size50_41_sram_blwl_outb[2332:2332] ,mux_2level_size50_41_configbus0[2332:2332], mux_2level_size50_41_configbus1[2332:2332] , mux_2level_size50_41_configbus0_b[2332:2332] ); -sram6T_blwl sram_blwl_2333_ (mux_2level_size50_41_sram_blwl_out[2333:2333] ,mux_2level_size50_41_sram_blwl_out[2333:2333] ,mux_2level_size50_41_sram_blwl_outb[2333:2333] ,mux_2level_size50_41_configbus0[2333:2333], mux_2level_size50_41_configbus1[2333:2333] , mux_2level_size50_41_configbus0_b[2333:2333] ); -sram6T_blwl sram_blwl_2334_ (mux_2level_size50_41_sram_blwl_out[2334:2334] ,mux_2level_size50_41_sram_blwl_out[2334:2334] ,mux_2level_size50_41_sram_blwl_outb[2334:2334] ,mux_2level_size50_41_configbus0[2334:2334], mux_2level_size50_41_configbus1[2334:2334] , mux_2level_size50_41_configbus0_b[2334:2334] ); -sram6T_blwl sram_blwl_2335_ (mux_2level_size50_41_sram_blwl_out[2335:2335] ,mux_2level_size50_41_sram_blwl_out[2335:2335] ,mux_2level_size50_41_sram_blwl_outb[2335:2335] ,mux_2level_size50_41_configbus0[2335:2335], mux_2level_size50_41_configbus1[2335:2335] , mux_2level_size50_41_configbus0_b[2335:2335] ); -sram6T_blwl sram_blwl_2336_ (mux_2level_size50_41_sram_blwl_out[2336:2336] ,mux_2level_size50_41_sram_blwl_out[2336:2336] ,mux_2level_size50_41_sram_blwl_outb[2336:2336] ,mux_2level_size50_41_configbus0[2336:2336], mux_2level_size50_41_configbus1[2336:2336] , mux_2level_size50_41_configbus0_b[2336:2336] ); -sram6T_blwl sram_blwl_2337_ (mux_2level_size50_41_sram_blwl_out[2337:2337] ,mux_2level_size50_41_sram_blwl_out[2337:2337] ,mux_2level_size50_41_sram_blwl_outb[2337:2337] ,mux_2level_size50_41_configbus0[2337:2337], mux_2level_size50_41_configbus1[2337:2337] , mux_2level_size50_41_configbus0_b[2337:2337] ); -direct_interc direct_interc_176_ (mode_clb___clk_0_, fle_6___clk_0_ ); -wire [0:49] in_bus_mux_2level_size50_42_ ; -assign in_bus_mux_2level_size50_42_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_42_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_42_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_42_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_42_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_42_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_42_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_42_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_42_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_42_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_42_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_42_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_42_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_42_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_42_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_42_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_42_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_42_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_42_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_42_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_42_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_42_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_42_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_42_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_42_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_42_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_42_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_42_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_42_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_42_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_42_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_42_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_42_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_42_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_42_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_42_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_42_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_42_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_42_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_42_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_42_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_42_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_42_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_42_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_42_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_42_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_42_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_42_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_42_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_42_[49] = fle_9___out_0_ ; -wire [2338:2353] mux_2level_size50_42_configbus0; -wire [2338:2353] mux_2level_size50_42_configbus1; -wire [2338:2353] mux_2level_size50_42_sram_blwl_out ; -wire [2338:2353] mux_2level_size50_42_sram_blwl_outb ; -assign mux_2level_size50_42_configbus0[2338:2353] = sram_blwl_bl[2338:2353] ; -assign mux_2level_size50_42_configbus1[2338:2353] = sram_blwl_wl[2338:2353] ; -wire [2338:2353] mux_2level_size50_42_configbus0_b; -assign mux_2level_size50_42_configbus0_b[2338:2353] = sram_blwl_blb[2338:2353] ; -mux_2level_size50 mux_2level_size50_42_ (in_bus_mux_2level_size50_42_, fle_7___in_0_, mux_2level_size50_42_sram_blwl_out[2338:2353] , -mux_2level_size50_42_sram_blwl_outb[2338:2353] ); -//----- SRAM bits for MUX[42], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2338_ (mux_2level_size50_42_sram_blwl_out[2338:2338] ,mux_2level_size50_42_sram_blwl_out[2338:2338] ,mux_2level_size50_42_sram_blwl_outb[2338:2338] ,mux_2level_size50_42_configbus0[2338:2338], mux_2level_size50_42_configbus1[2338:2338] , mux_2level_size50_42_configbus0_b[2338:2338] ); -sram6T_blwl sram_blwl_2339_ (mux_2level_size50_42_sram_blwl_out[2339:2339] ,mux_2level_size50_42_sram_blwl_out[2339:2339] ,mux_2level_size50_42_sram_blwl_outb[2339:2339] ,mux_2level_size50_42_configbus0[2339:2339], mux_2level_size50_42_configbus1[2339:2339] , mux_2level_size50_42_configbus0_b[2339:2339] ); -sram6T_blwl sram_blwl_2340_ (mux_2level_size50_42_sram_blwl_out[2340:2340] ,mux_2level_size50_42_sram_blwl_out[2340:2340] ,mux_2level_size50_42_sram_blwl_outb[2340:2340] ,mux_2level_size50_42_configbus0[2340:2340], mux_2level_size50_42_configbus1[2340:2340] , mux_2level_size50_42_configbus0_b[2340:2340] ); -sram6T_blwl sram_blwl_2341_ (mux_2level_size50_42_sram_blwl_out[2341:2341] ,mux_2level_size50_42_sram_blwl_out[2341:2341] ,mux_2level_size50_42_sram_blwl_outb[2341:2341] ,mux_2level_size50_42_configbus0[2341:2341], mux_2level_size50_42_configbus1[2341:2341] , mux_2level_size50_42_configbus0_b[2341:2341] ); -sram6T_blwl sram_blwl_2342_ (mux_2level_size50_42_sram_blwl_out[2342:2342] ,mux_2level_size50_42_sram_blwl_out[2342:2342] ,mux_2level_size50_42_sram_blwl_outb[2342:2342] ,mux_2level_size50_42_configbus0[2342:2342], mux_2level_size50_42_configbus1[2342:2342] , mux_2level_size50_42_configbus0_b[2342:2342] ); -sram6T_blwl sram_blwl_2343_ (mux_2level_size50_42_sram_blwl_out[2343:2343] ,mux_2level_size50_42_sram_blwl_out[2343:2343] ,mux_2level_size50_42_sram_blwl_outb[2343:2343] ,mux_2level_size50_42_configbus0[2343:2343], mux_2level_size50_42_configbus1[2343:2343] , mux_2level_size50_42_configbus0_b[2343:2343] ); -sram6T_blwl sram_blwl_2344_ (mux_2level_size50_42_sram_blwl_out[2344:2344] ,mux_2level_size50_42_sram_blwl_out[2344:2344] ,mux_2level_size50_42_sram_blwl_outb[2344:2344] ,mux_2level_size50_42_configbus0[2344:2344], mux_2level_size50_42_configbus1[2344:2344] , mux_2level_size50_42_configbus0_b[2344:2344] ); -sram6T_blwl sram_blwl_2345_ (mux_2level_size50_42_sram_blwl_out[2345:2345] ,mux_2level_size50_42_sram_blwl_out[2345:2345] ,mux_2level_size50_42_sram_blwl_outb[2345:2345] ,mux_2level_size50_42_configbus0[2345:2345], mux_2level_size50_42_configbus1[2345:2345] , mux_2level_size50_42_configbus0_b[2345:2345] ); -sram6T_blwl sram_blwl_2346_ (mux_2level_size50_42_sram_blwl_out[2346:2346] ,mux_2level_size50_42_sram_blwl_out[2346:2346] ,mux_2level_size50_42_sram_blwl_outb[2346:2346] ,mux_2level_size50_42_configbus0[2346:2346], mux_2level_size50_42_configbus1[2346:2346] , mux_2level_size50_42_configbus0_b[2346:2346] ); -sram6T_blwl sram_blwl_2347_ (mux_2level_size50_42_sram_blwl_out[2347:2347] ,mux_2level_size50_42_sram_blwl_out[2347:2347] ,mux_2level_size50_42_sram_blwl_outb[2347:2347] ,mux_2level_size50_42_configbus0[2347:2347], mux_2level_size50_42_configbus1[2347:2347] , mux_2level_size50_42_configbus0_b[2347:2347] ); -sram6T_blwl sram_blwl_2348_ (mux_2level_size50_42_sram_blwl_out[2348:2348] ,mux_2level_size50_42_sram_blwl_out[2348:2348] ,mux_2level_size50_42_sram_blwl_outb[2348:2348] ,mux_2level_size50_42_configbus0[2348:2348], mux_2level_size50_42_configbus1[2348:2348] , mux_2level_size50_42_configbus0_b[2348:2348] ); -sram6T_blwl sram_blwl_2349_ (mux_2level_size50_42_sram_blwl_out[2349:2349] ,mux_2level_size50_42_sram_blwl_out[2349:2349] ,mux_2level_size50_42_sram_blwl_outb[2349:2349] ,mux_2level_size50_42_configbus0[2349:2349], mux_2level_size50_42_configbus1[2349:2349] , mux_2level_size50_42_configbus0_b[2349:2349] ); -sram6T_blwl sram_blwl_2350_ (mux_2level_size50_42_sram_blwl_out[2350:2350] ,mux_2level_size50_42_sram_blwl_out[2350:2350] ,mux_2level_size50_42_sram_blwl_outb[2350:2350] ,mux_2level_size50_42_configbus0[2350:2350], mux_2level_size50_42_configbus1[2350:2350] , mux_2level_size50_42_configbus0_b[2350:2350] ); -sram6T_blwl sram_blwl_2351_ (mux_2level_size50_42_sram_blwl_out[2351:2351] ,mux_2level_size50_42_sram_blwl_out[2351:2351] ,mux_2level_size50_42_sram_blwl_outb[2351:2351] ,mux_2level_size50_42_configbus0[2351:2351], mux_2level_size50_42_configbus1[2351:2351] , mux_2level_size50_42_configbus0_b[2351:2351] ); -sram6T_blwl sram_blwl_2352_ (mux_2level_size50_42_sram_blwl_out[2352:2352] ,mux_2level_size50_42_sram_blwl_out[2352:2352] ,mux_2level_size50_42_sram_blwl_outb[2352:2352] ,mux_2level_size50_42_configbus0[2352:2352], mux_2level_size50_42_configbus1[2352:2352] , mux_2level_size50_42_configbus0_b[2352:2352] ); -sram6T_blwl sram_blwl_2353_ (mux_2level_size50_42_sram_blwl_out[2353:2353] ,mux_2level_size50_42_sram_blwl_out[2353:2353] ,mux_2level_size50_42_sram_blwl_outb[2353:2353] ,mux_2level_size50_42_configbus0[2353:2353], mux_2level_size50_42_configbus1[2353:2353] , mux_2level_size50_42_configbus0_b[2353:2353] ); -wire [0:49] in_bus_mux_2level_size50_43_ ; -assign in_bus_mux_2level_size50_43_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_43_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_43_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_43_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_43_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_43_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_43_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_43_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_43_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_43_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_43_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_43_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_43_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_43_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_43_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_43_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_43_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_43_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_43_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_43_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_43_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_43_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_43_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_43_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_43_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_43_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_43_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_43_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_43_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_43_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_43_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_43_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_43_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_43_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_43_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_43_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_43_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_43_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_43_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_43_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_43_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_43_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_43_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_43_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_43_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_43_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_43_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_43_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_43_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_43_[49] = fle_9___out_0_ ; -wire [2354:2369] mux_2level_size50_43_configbus0; -wire [2354:2369] mux_2level_size50_43_configbus1; -wire [2354:2369] mux_2level_size50_43_sram_blwl_out ; -wire [2354:2369] mux_2level_size50_43_sram_blwl_outb ; -assign mux_2level_size50_43_configbus0[2354:2369] = sram_blwl_bl[2354:2369] ; -assign mux_2level_size50_43_configbus1[2354:2369] = sram_blwl_wl[2354:2369] ; -wire [2354:2369] mux_2level_size50_43_configbus0_b; -assign mux_2level_size50_43_configbus0_b[2354:2369] = sram_blwl_blb[2354:2369] ; -mux_2level_size50 mux_2level_size50_43_ (in_bus_mux_2level_size50_43_, fle_7___in_1_, mux_2level_size50_43_sram_blwl_out[2354:2369] , -mux_2level_size50_43_sram_blwl_outb[2354:2369] ); -//----- SRAM bits for MUX[43], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2354_ (mux_2level_size50_43_sram_blwl_out[2354:2354] ,mux_2level_size50_43_sram_blwl_out[2354:2354] ,mux_2level_size50_43_sram_blwl_outb[2354:2354] ,mux_2level_size50_43_configbus0[2354:2354], mux_2level_size50_43_configbus1[2354:2354] , mux_2level_size50_43_configbus0_b[2354:2354] ); -sram6T_blwl sram_blwl_2355_ (mux_2level_size50_43_sram_blwl_out[2355:2355] ,mux_2level_size50_43_sram_blwl_out[2355:2355] ,mux_2level_size50_43_sram_blwl_outb[2355:2355] ,mux_2level_size50_43_configbus0[2355:2355], mux_2level_size50_43_configbus1[2355:2355] , mux_2level_size50_43_configbus0_b[2355:2355] ); -sram6T_blwl sram_blwl_2356_ (mux_2level_size50_43_sram_blwl_out[2356:2356] ,mux_2level_size50_43_sram_blwl_out[2356:2356] ,mux_2level_size50_43_sram_blwl_outb[2356:2356] ,mux_2level_size50_43_configbus0[2356:2356], mux_2level_size50_43_configbus1[2356:2356] , mux_2level_size50_43_configbus0_b[2356:2356] ); -sram6T_blwl sram_blwl_2357_ (mux_2level_size50_43_sram_blwl_out[2357:2357] ,mux_2level_size50_43_sram_blwl_out[2357:2357] ,mux_2level_size50_43_sram_blwl_outb[2357:2357] ,mux_2level_size50_43_configbus0[2357:2357], mux_2level_size50_43_configbus1[2357:2357] , mux_2level_size50_43_configbus0_b[2357:2357] ); -sram6T_blwl sram_blwl_2358_ (mux_2level_size50_43_sram_blwl_out[2358:2358] ,mux_2level_size50_43_sram_blwl_out[2358:2358] ,mux_2level_size50_43_sram_blwl_outb[2358:2358] ,mux_2level_size50_43_configbus0[2358:2358], mux_2level_size50_43_configbus1[2358:2358] , mux_2level_size50_43_configbus0_b[2358:2358] ); -sram6T_blwl sram_blwl_2359_ (mux_2level_size50_43_sram_blwl_out[2359:2359] ,mux_2level_size50_43_sram_blwl_out[2359:2359] ,mux_2level_size50_43_sram_blwl_outb[2359:2359] ,mux_2level_size50_43_configbus0[2359:2359], mux_2level_size50_43_configbus1[2359:2359] , mux_2level_size50_43_configbus0_b[2359:2359] ); -sram6T_blwl sram_blwl_2360_ (mux_2level_size50_43_sram_blwl_out[2360:2360] ,mux_2level_size50_43_sram_blwl_out[2360:2360] ,mux_2level_size50_43_sram_blwl_outb[2360:2360] ,mux_2level_size50_43_configbus0[2360:2360], mux_2level_size50_43_configbus1[2360:2360] , mux_2level_size50_43_configbus0_b[2360:2360] ); -sram6T_blwl sram_blwl_2361_ (mux_2level_size50_43_sram_blwl_out[2361:2361] ,mux_2level_size50_43_sram_blwl_out[2361:2361] ,mux_2level_size50_43_sram_blwl_outb[2361:2361] ,mux_2level_size50_43_configbus0[2361:2361], mux_2level_size50_43_configbus1[2361:2361] , mux_2level_size50_43_configbus0_b[2361:2361] ); -sram6T_blwl sram_blwl_2362_ (mux_2level_size50_43_sram_blwl_out[2362:2362] ,mux_2level_size50_43_sram_blwl_out[2362:2362] ,mux_2level_size50_43_sram_blwl_outb[2362:2362] ,mux_2level_size50_43_configbus0[2362:2362], mux_2level_size50_43_configbus1[2362:2362] , mux_2level_size50_43_configbus0_b[2362:2362] ); -sram6T_blwl sram_blwl_2363_ (mux_2level_size50_43_sram_blwl_out[2363:2363] ,mux_2level_size50_43_sram_blwl_out[2363:2363] ,mux_2level_size50_43_sram_blwl_outb[2363:2363] ,mux_2level_size50_43_configbus0[2363:2363], mux_2level_size50_43_configbus1[2363:2363] , mux_2level_size50_43_configbus0_b[2363:2363] ); -sram6T_blwl sram_blwl_2364_ (mux_2level_size50_43_sram_blwl_out[2364:2364] ,mux_2level_size50_43_sram_blwl_out[2364:2364] ,mux_2level_size50_43_sram_blwl_outb[2364:2364] ,mux_2level_size50_43_configbus0[2364:2364], mux_2level_size50_43_configbus1[2364:2364] , mux_2level_size50_43_configbus0_b[2364:2364] ); -sram6T_blwl sram_blwl_2365_ (mux_2level_size50_43_sram_blwl_out[2365:2365] ,mux_2level_size50_43_sram_blwl_out[2365:2365] ,mux_2level_size50_43_sram_blwl_outb[2365:2365] ,mux_2level_size50_43_configbus0[2365:2365], mux_2level_size50_43_configbus1[2365:2365] , mux_2level_size50_43_configbus0_b[2365:2365] ); -sram6T_blwl sram_blwl_2366_ (mux_2level_size50_43_sram_blwl_out[2366:2366] ,mux_2level_size50_43_sram_blwl_out[2366:2366] ,mux_2level_size50_43_sram_blwl_outb[2366:2366] ,mux_2level_size50_43_configbus0[2366:2366], mux_2level_size50_43_configbus1[2366:2366] , mux_2level_size50_43_configbus0_b[2366:2366] ); -sram6T_blwl sram_blwl_2367_ (mux_2level_size50_43_sram_blwl_out[2367:2367] ,mux_2level_size50_43_sram_blwl_out[2367:2367] ,mux_2level_size50_43_sram_blwl_outb[2367:2367] ,mux_2level_size50_43_configbus0[2367:2367], mux_2level_size50_43_configbus1[2367:2367] , mux_2level_size50_43_configbus0_b[2367:2367] ); -sram6T_blwl sram_blwl_2368_ (mux_2level_size50_43_sram_blwl_out[2368:2368] ,mux_2level_size50_43_sram_blwl_out[2368:2368] ,mux_2level_size50_43_sram_blwl_outb[2368:2368] ,mux_2level_size50_43_configbus0[2368:2368], mux_2level_size50_43_configbus1[2368:2368] , mux_2level_size50_43_configbus0_b[2368:2368] ); -sram6T_blwl sram_blwl_2369_ (mux_2level_size50_43_sram_blwl_out[2369:2369] ,mux_2level_size50_43_sram_blwl_out[2369:2369] ,mux_2level_size50_43_sram_blwl_outb[2369:2369] ,mux_2level_size50_43_configbus0[2369:2369], mux_2level_size50_43_configbus1[2369:2369] , mux_2level_size50_43_configbus0_b[2369:2369] ); -wire [0:49] in_bus_mux_2level_size50_44_ ; -assign in_bus_mux_2level_size50_44_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_44_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_44_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_44_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_44_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_44_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_44_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_44_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_44_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_44_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_44_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_44_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_44_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_44_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_44_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_44_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_44_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_44_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_44_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_44_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_44_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_44_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_44_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_44_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_44_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_44_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_44_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_44_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_44_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_44_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_44_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_44_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_44_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_44_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_44_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_44_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_44_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_44_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_44_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_44_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_44_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_44_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_44_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_44_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_44_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_44_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_44_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_44_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_44_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_44_[49] = fle_9___out_0_ ; -wire [2370:2385] mux_2level_size50_44_configbus0; -wire [2370:2385] mux_2level_size50_44_configbus1; -wire [2370:2385] mux_2level_size50_44_sram_blwl_out ; -wire [2370:2385] mux_2level_size50_44_sram_blwl_outb ; -assign mux_2level_size50_44_configbus0[2370:2385] = sram_blwl_bl[2370:2385] ; -assign mux_2level_size50_44_configbus1[2370:2385] = sram_blwl_wl[2370:2385] ; -wire [2370:2385] mux_2level_size50_44_configbus0_b; -assign mux_2level_size50_44_configbus0_b[2370:2385] = sram_blwl_blb[2370:2385] ; -mux_2level_size50 mux_2level_size50_44_ (in_bus_mux_2level_size50_44_, fle_7___in_2_, mux_2level_size50_44_sram_blwl_out[2370:2385] , -mux_2level_size50_44_sram_blwl_outb[2370:2385] ); -//----- SRAM bits for MUX[44], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2370_ (mux_2level_size50_44_sram_blwl_out[2370:2370] ,mux_2level_size50_44_sram_blwl_out[2370:2370] ,mux_2level_size50_44_sram_blwl_outb[2370:2370] ,mux_2level_size50_44_configbus0[2370:2370], mux_2level_size50_44_configbus1[2370:2370] , mux_2level_size50_44_configbus0_b[2370:2370] ); -sram6T_blwl sram_blwl_2371_ (mux_2level_size50_44_sram_blwl_out[2371:2371] ,mux_2level_size50_44_sram_blwl_out[2371:2371] ,mux_2level_size50_44_sram_blwl_outb[2371:2371] ,mux_2level_size50_44_configbus0[2371:2371], mux_2level_size50_44_configbus1[2371:2371] , mux_2level_size50_44_configbus0_b[2371:2371] ); -sram6T_blwl sram_blwl_2372_ (mux_2level_size50_44_sram_blwl_out[2372:2372] ,mux_2level_size50_44_sram_blwl_out[2372:2372] ,mux_2level_size50_44_sram_blwl_outb[2372:2372] ,mux_2level_size50_44_configbus0[2372:2372], mux_2level_size50_44_configbus1[2372:2372] , mux_2level_size50_44_configbus0_b[2372:2372] ); -sram6T_blwl sram_blwl_2373_ (mux_2level_size50_44_sram_blwl_out[2373:2373] ,mux_2level_size50_44_sram_blwl_out[2373:2373] ,mux_2level_size50_44_sram_blwl_outb[2373:2373] ,mux_2level_size50_44_configbus0[2373:2373], mux_2level_size50_44_configbus1[2373:2373] , mux_2level_size50_44_configbus0_b[2373:2373] ); -sram6T_blwl sram_blwl_2374_ (mux_2level_size50_44_sram_blwl_out[2374:2374] ,mux_2level_size50_44_sram_blwl_out[2374:2374] ,mux_2level_size50_44_sram_blwl_outb[2374:2374] ,mux_2level_size50_44_configbus0[2374:2374], mux_2level_size50_44_configbus1[2374:2374] , mux_2level_size50_44_configbus0_b[2374:2374] ); -sram6T_blwl sram_blwl_2375_ (mux_2level_size50_44_sram_blwl_out[2375:2375] ,mux_2level_size50_44_sram_blwl_out[2375:2375] ,mux_2level_size50_44_sram_blwl_outb[2375:2375] ,mux_2level_size50_44_configbus0[2375:2375], mux_2level_size50_44_configbus1[2375:2375] , mux_2level_size50_44_configbus0_b[2375:2375] ); -sram6T_blwl sram_blwl_2376_ (mux_2level_size50_44_sram_blwl_out[2376:2376] ,mux_2level_size50_44_sram_blwl_out[2376:2376] ,mux_2level_size50_44_sram_blwl_outb[2376:2376] ,mux_2level_size50_44_configbus0[2376:2376], mux_2level_size50_44_configbus1[2376:2376] , mux_2level_size50_44_configbus0_b[2376:2376] ); -sram6T_blwl sram_blwl_2377_ (mux_2level_size50_44_sram_blwl_out[2377:2377] ,mux_2level_size50_44_sram_blwl_out[2377:2377] ,mux_2level_size50_44_sram_blwl_outb[2377:2377] ,mux_2level_size50_44_configbus0[2377:2377], mux_2level_size50_44_configbus1[2377:2377] , mux_2level_size50_44_configbus0_b[2377:2377] ); -sram6T_blwl sram_blwl_2378_ (mux_2level_size50_44_sram_blwl_out[2378:2378] ,mux_2level_size50_44_sram_blwl_out[2378:2378] ,mux_2level_size50_44_sram_blwl_outb[2378:2378] ,mux_2level_size50_44_configbus0[2378:2378], mux_2level_size50_44_configbus1[2378:2378] , mux_2level_size50_44_configbus0_b[2378:2378] ); -sram6T_blwl sram_blwl_2379_ (mux_2level_size50_44_sram_blwl_out[2379:2379] ,mux_2level_size50_44_sram_blwl_out[2379:2379] ,mux_2level_size50_44_sram_blwl_outb[2379:2379] ,mux_2level_size50_44_configbus0[2379:2379], mux_2level_size50_44_configbus1[2379:2379] , mux_2level_size50_44_configbus0_b[2379:2379] ); -sram6T_blwl sram_blwl_2380_ (mux_2level_size50_44_sram_blwl_out[2380:2380] ,mux_2level_size50_44_sram_blwl_out[2380:2380] ,mux_2level_size50_44_sram_blwl_outb[2380:2380] ,mux_2level_size50_44_configbus0[2380:2380], mux_2level_size50_44_configbus1[2380:2380] , mux_2level_size50_44_configbus0_b[2380:2380] ); -sram6T_blwl sram_blwl_2381_ (mux_2level_size50_44_sram_blwl_out[2381:2381] ,mux_2level_size50_44_sram_blwl_out[2381:2381] ,mux_2level_size50_44_sram_blwl_outb[2381:2381] ,mux_2level_size50_44_configbus0[2381:2381], mux_2level_size50_44_configbus1[2381:2381] , mux_2level_size50_44_configbus0_b[2381:2381] ); -sram6T_blwl sram_blwl_2382_ (mux_2level_size50_44_sram_blwl_out[2382:2382] ,mux_2level_size50_44_sram_blwl_out[2382:2382] ,mux_2level_size50_44_sram_blwl_outb[2382:2382] ,mux_2level_size50_44_configbus0[2382:2382], mux_2level_size50_44_configbus1[2382:2382] , mux_2level_size50_44_configbus0_b[2382:2382] ); -sram6T_blwl sram_blwl_2383_ (mux_2level_size50_44_sram_blwl_out[2383:2383] ,mux_2level_size50_44_sram_blwl_out[2383:2383] ,mux_2level_size50_44_sram_blwl_outb[2383:2383] ,mux_2level_size50_44_configbus0[2383:2383], mux_2level_size50_44_configbus1[2383:2383] , mux_2level_size50_44_configbus0_b[2383:2383] ); -sram6T_blwl sram_blwl_2384_ (mux_2level_size50_44_sram_blwl_out[2384:2384] ,mux_2level_size50_44_sram_blwl_out[2384:2384] ,mux_2level_size50_44_sram_blwl_outb[2384:2384] ,mux_2level_size50_44_configbus0[2384:2384], mux_2level_size50_44_configbus1[2384:2384] , mux_2level_size50_44_configbus0_b[2384:2384] ); -sram6T_blwl sram_blwl_2385_ (mux_2level_size50_44_sram_blwl_out[2385:2385] ,mux_2level_size50_44_sram_blwl_out[2385:2385] ,mux_2level_size50_44_sram_blwl_outb[2385:2385] ,mux_2level_size50_44_configbus0[2385:2385], mux_2level_size50_44_configbus1[2385:2385] , mux_2level_size50_44_configbus0_b[2385:2385] ); -wire [0:49] in_bus_mux_2level_size50_45_ ; -assign in_bus_mux_2level_size50_45_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_45_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_45_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_45_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_45_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_45_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_45_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_45_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_45_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_45_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_45_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_45_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_45_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_45_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_45_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_45_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_45_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_45_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_45_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_45_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_45_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_45_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_45_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_45_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_45_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_45_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_45_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_45_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_45_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_45_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_45_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_45_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_45_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_45_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_45_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_45_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_45_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_45_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_45_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_45_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_45_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_45_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_45_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_45_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_45_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_45_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_45_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_45_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_45_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_45_[49] = fle_9___out_0_ ; -wire [2386:2401] mux_2level_size50_45_configbus0; -wire [2386:2401] mux_2level_size50_45_configbus1; -wire [2386:2401] mux_2level_size50_45_sram_blwl_out ; -wire [2386:2401] mux_2level_size50_45_sram_blwl_outb ; -assign mux_2level_size50_45_configbus0[2386:2401] = sram_blwl_bl[2386:2401] ; -assign mux_2level_size50_45_configbus1[2386:2401] = sram_blwl_wl[2386:2401] ; -wire [2386:2401] mux_2level_size50_45_configbus0_b; -assign mux_2level_size50_45_configbus0_b[2386:2401] = sram_blwl_blb[2386:2401] ; -mux_2level_size50 mux_2level_size50_45_ (in_bus_mux_2level_size50_45_, fle_7___in_3_, mux_2level_size50_45_sram_blwl_out[2386:2401] , -mux_2level_size50_45_sram_blwl_outb[2386:2401] ); -//----- SRAM bits for MUX[45], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2386_ (mux_2level_size50_45_sram_blwl_out[2386:2386] ,mux_2level_size50_45_sram_blwl_out[2386:2386] ,mux_2level_size50_45_sram_blwl_outb[2386:2386] ,mux_2level_size50_45_configbus0[2386:2386], mux_2level_size50_45_configbus1[2386:2386] , mux_2level_size50_45_configbus0_b[2386:2386] ); -sram6T_blwl sram_blwl_2387_ (mux_2level_size50_45_sram_blwl_out[2387:2387] ,mux_2level_size50_45_sram_blwl_out[2387:2387] ,mux_2level_size50_45_sram_blwl_outb[2387:2387] ,mux_2level_size50_45_configbus0[2387:2387], mux_2level_size50_45_configbus1[2387:2387] , mux_2level_size50_45_configbus0_b[2387:2387] ); -sram6T_blwl sram_blwl_2388_ (mux_2level_size50_45_sram_blwl_out[2388:2388] ,mux_2level_size50_45_sram_blwl_out[2388:2388] ,mux_2level_size50_45_sram_blwl_outb[2388:2388] ,mux_2level_size50_45_configbus0[2388:2388], mux_2level_size50_45_configbus1[2388:2388] , mux_2level_size50_45_configbus0_b[2388:2388] ); -sram6T_blwl sram_blwl_2389_ (mux_2level_size50_45_sram_blwl_out[2389:2389] ,mux_2level_size50_45_sram_blwl_out[2389:2389] ,mux_2level_size50_45_sram_blwl_outb[2389:2389] ,mux_2level_size50_45_configbus0[2389:2389], mux_2level_size50_45_configbus1[2389:2389] , mux_2level_size50_45_configbus0_b[2389:2389] ); -sram6T_blwl sram_blwl_2390_ (mux_2level_size50_45_sram_blwl_out[2390:2390] ,mux_2level_size50_45_sram_blwl_out[2390:2390] ,mux_2level_size50_45_sram_blwl_outb[2390:2390] ,mux_2level_size50_45_configbus0[2390:2390], mux_2level_size50_45_configbus1[2390:2390] , mux_2level_size50_45_configbus0_b[2390:2390] ); -sram6T_blwl sram_blwl_2391_ (mux_2level_size50_45_sram_blwl_out[2391:2391] ,mux_2level_size50_45_sram_blwl_out[2391:2391] ,mux_2level_size50_45_sram_blwl_outb[2391:2391] ,mux_2level_size50_45_configbus0[2391:2391], mux_2level_size50_45_configbus1[2391:2391] , mux_2level_size50_45_configbus0_b[2391:2391] ); -sram6T_blwl sram_blwl_2392_ (mux_2level_size50_45_sram_blwl_out[2392:2392] ,mux_2level_size50_45_sram_blwl_out[2392:2392] ,mux_2level_size50_45_sram_blwl_outb[2392:2392] ,mux_2level_size50_45_configbus0[2392:2392], mux_2level_size50_45_configbus1[2392:2392] , mux_2level_size50_45_configbus0_b[2392:2392] ); -sram6T_blwl sram_blwl_2393_ (mux_2level_size50_45_sram_blwl_out[2393:2393] ,mux_2level_size50_45_sram_blwl_out[2393:2393] ,mux_2level_size50_45_sram_blwl_outb[2393:2393] ,mux_2level_size50_45_configbus0[2393:2393], mux_2level_size50_45_configbus1[2393:2393] , mux_2level_size50_45_configbus0_b[2393:2393] ); -sram6T_blwl sram_blwl_2394_ (mux_2level_size50_45_sram_blwl_out[2394:2394] ,mux_2level_size50_45_sram_blwl_out[2394:2394] ,mux_2level_size50_45_sram_blwl_outb[2394:2394] ,mux_2level_size50_45_configbus0[2394:2394], mux_2level_size50_45_configbus1[2394:2394] , mux_2level_size50_45_configbus0_b[2394:2394] ); -sram6T_blwl sram_blwl_2395_ (mux_2level_size50_45_sram_blwl_out[2395:2395] ,mux_2level_size50_45_sram_blwl_out[2395:2395] ,mux_2level_size50_45_sram_blwl_outb[2395:2395] ,mux_2level_size50_45_configbus0[2395:2395], mux_2level_size50_45_configbus1[2395:2395] , mux_2level_size50_45_configbus0_b[2395:2395] ); -sram6T_blwl sram_blwl_2396_ (mux_2level_size50_45_sram_blwl_out[2396:2396] ,mux_2level_size50_45_sram_blwl_out[2396:2396] ,mux_2level_size50_45_sram_blwl_outb[2396:2396] ,mux_2level_size50_45_configbus0[2396:2396], mux_2level_size50_45_configbus1[2396:2396] , mux_2level_size50_45_configbus0_b[2396:2396] ); -sram6T_blwl sram_blwl_2397_ (mux_2level_size50_45_sram_blwl_out[2397:2397] ,mux_2level_size50_45_sram_blwl_out[2397:2397] ,mux_2level_size50_45_sram_blwl_outb[2397:2397] ,mux_2level_size50_45_configbus0[2397:2397], mux_2level_size50_45_configbus1[2397:2397] , mux_2level_size50_45_configbus0_b[2397:2397] ); -sram6T_blwl sram_blwl_2398_ (mux_2level_size50_45_sram_blwl_out[2398:2398] ,mux_2level_size50_45_sram_blwl_out[2398:2398] ,mux_2level_size50_45_sram_blwl_outb[2398:2398] ,mux_2level_size50_45_configbus0[2398:2398], mux_2level_size50_45_configbus1[2398:2398] , mux_2level_size50_45_configbus0_b[2398:2398] ); -sram6T_blwl sram_blwl_2399_ (mux_2level_size50_45_sram_blwl_out[2399:2399] ,mux_2level_size50_45_sram_blwl_out[2399:2399] ,mux_2level_size50_45_sram_blwl_outb[2399:2399] ,mux_2level_size50_45_configbus0[2399:2399], mux_2level_size50_45_configbus1[2399:2399] , mux_2level_size50_45_configbus0_b[2399:2399] ); -sram6T_blwl sram_blwl_2400_ (mux_2level_size50_45_sram_blwl_out[2400:2400] ,mux_2level_size50_45_sram_blwl_out[2400:2400] ,mux_2level_size50_45_sram_blwl_outb[2400:2400] ,mux_2level_size50_45_configbus0[2400:2400], mux_2level_size50_45_configbus1[2400:2400] , mux_2level_size50_45_configbus0_b[2400:2400] ); -sram6T_blwl sram_blwl_2401_ (mux_2level_size50_45_sram_blwl_out[2401:2401] ,mux_2level_size50_45_sram_blwl_out[2401:2401] ,mux_2level_size50_45_sram_blwl_outb[2401:2401] ,mux_2level_size50_45_configbus0[2401:2401], mux_2level_size50_45_configbus1[2401:2401] , mux_2level_size50_45_configbus0_b[2401:2401] ); -wire [0:49] in_bus_mux_2level_size50_46_ ; -assign in_bus_mux_2level_size50_46_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_46_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_46_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_46_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_46_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_46_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_46_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_46_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_46_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_46_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_46_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_46_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_46_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_46_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_46_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_46_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_46_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_46_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_46_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_46_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_46_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_46_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_46_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_46_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_46_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_46_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_46_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_46_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_46_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_46_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_46_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_46_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_46_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_46_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_46_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_46_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_46_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_46_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_46_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_46_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_46_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_46_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_46_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_46_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_46_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_46_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_46_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_46_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_46_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_46_[49] = fle_9___out_0_ ; -wire [2402:2417] mux_2level_size50_46_configbus0; -wire [2402:2417] mux_2level_size50_46_configbus1; -wire [2402:2417] mux_2level_size50_46_sram_blwl_out ; -wire [2402:2417] mux_2level_size50_46_sram_blwl_outb ; -assign mux_2level_size50_46_configbus0[2402:2417] = sram_blwl_bl[2402:2417] ; -assign mux_2level_size50_46_configbus1[2402:2417] = sram_blwl_wl[2402:2417] ; -wire [2402:2417] mux_2level_size50_46_configbus0_b; -assign mux_2level_size50_46_configbus0_b[2402:2417] = sram_blwl_blb[2402:2417] ; -mux_2level_size50 mux_2level_size50_46_ (in_bus_mux_2level_size50_46_, fle_7___in_4_, mux_2level_size50_46_sram_blwl_out[2402:2417] , -mux_2level_size50_46_sram_blwl_outb[2402:2417] ); -//----- SRAM bits for MUX[46], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2402_ (mux_2level_size50_46_sram_blwl_out[2402:2402] ,mux_2level_size50_46_sram_blwl_out[2402:2402] ,mux_2level_size50_46_sram_blwl_outb[2402:2402] ,mux_2level_size50_46_configbus0[2402:2402], mux_2level_size50_46_configbus1[2402:2402] , mux_2level_size50_46_configbus0_b[2402:2402] ); -sram6T_blwl sram_blwl_2403_ (mux_2level_size50_46_sram_blwl_out[2403:2403] ,mux_2level_size50_46_sram_blwl_out[2403:2403] ,mux_2level_size50_46_sram_blwl_outb[2403:2403] ,mux_2level_size50_46_configbus0[2403:2403], mux_2level_size50_46_configbus1[2403:2403] , mux_2level_size50_46_configbus0_b[2403:2403] ); -sram6T_blwl sram_blwl_2404_ (mux_2level_size50_46_sram_blwl_out[2404:2404] ,mux_2level_size50_46_sram_blwl_out[2404:2404] ,mux_2level_size50_46_sram_blwl_outb[2404:2404] ,mux_2level_size50_46_configbus0[2404:2404], mux_2level_size50_46_configbus1[2404:2404] , mux_2level_size50_46_configbus0_b[2404:2404] ); -sram6T_blwl sram_blwl_2405_ (mux_2level_size50_46_sram_blwl_out[2405:2405] ,mux_2level_size50_46_sram_blwl_out[2405:2405] ,mux_2level_size50_46_sram_blwl_outb[2405:2405] ,mux_2level_size50_46_configbus0[2405:2405], mux_2level_size50_46_configbus1[2405:2405] , mux_2level_size50_46_configbus0_b[2405:2405] ); -sram6T_blwl sram_blwl_2406_ (mux_2level_size50_46_sram_blwl_out[2406:2406] ,mux_2level_size50_46_sram_blwl_out[2406:2406] ,mux_2level_size50_46_sram_blwl_outb[2406:2406] ,mux_2level_size50_46_configbus0[2406:2406], mux_2level_size50_46_configbus1[2406:2406] , mux_2level_size50_46_configbus0_b[2406:2406] ); -sram6T_blwl sram_blwl_2407_ (mux_2level_size50_46_sram_blwl_out[2407:2407] ,mux_2level_size50_46_sram_blwl_out[2407:2407] ,mux_2level_size50_46_sram_blwl_outb[2407:2407] ,mux_2level_size50_46_configbus0[2407:2407], mux_2level_size50_46_configbus1[2407:2407] , mux_2level_size50_46_configbus0_b[2407:2407] ); -sram6T_blwl sram_blwl_2408_ (mux_2level_size50_46_sram_blwl_out[2408:2408] ,mux_2level_size50_46_sram_blwl_out[2408:2408] ,mux_2level_size50_46_sram_blwl_outb[2408:2408] ,mux_2level_size50_46_configbus0[2408:2408], mux_2level_size50_46_configbus1[2408:2408] , mux_2level_size50_46_configbus0_b[2408:2408] ); -sram6T_blwl sram_blwl_2409_ (mux_2level_size50_46_sram_blwl_out[2409:2409] ,mux_2level_size50_46_sram_blwl_out[2409:2409] ,mux_2level_size50_46_sram_blwl_outb[2409:2409] ,mux_2level_size50_46_configbus0[2409:2409], mux_2level_size50_46_configbus1[2409:2409] , mux_2level_size50_46_configbus0_b[2409:2409] ); -sram6T_blwl sram_blwl_2410_ (mux_2level_size50_46_sram_blwl_out[2410:2410] ,mux_2level_size50_46_sram_blwl_out[2410:2410] ,mux_2level_size50_46_sram_blwl_outb[2410:2410] ,mux_2level_size50_46_configbus0[2410:2410], mux_2level_size50_46_configbus1[2410:2410] , mux_2level_size50_46_configbus0_b[2410:2410] ); -sram6T_blwl sram_blwl_2411_ (mux_2level_size50_46_sram_blwl_out[2411:2411] ,mux_2level_size50_46_sram_blwl_out[2411:2411] ,mux_2level_size50_46_sram_blwl_outb[2411:2411] ,mux_2level_size50_46_configbus0[2411:2411], mux_2level_size50_46_configbus1[2411:2411] , mux_2level_size50_46_configbus0_b[2411:2411] ); -sram6T_blwl sram_blwl_2412_ (mux_2level_size50_46_sram_blwl_out[2412:2412] ,mux_2level_size50_46_sram_blwl_out[2412:2412] ,mux_2level_size50_46_sram_blwl_outb[2412:2412] ,mux_2level_size50_46_configbus0[2412:2412], mux_2level_size50_46_configbus1[2412:2412] , mux_2level_size50_46_configbus0_b[2412:2412] ); -sram6T_blwl sram_blwl_2413_ (mux_2level_size50_46_sram_blwl_out[2413:2413] ,mux_2level_size50_46_sram_blwl_out[2413:2413] ,mux_2level_size50_46_sram_blwl_outb[2413:2413] ,mux_2level_size50_46_configbus0[2413:2413], mux_2level_size50_46_configbus1[2413:2413] , mux_2level_size50_46_configbus0_b[2413:2413] ); -sram6T_blwl sram_blwl_2414_ (mux_2level_size50_46_sram_blwl_out[2414:2414] ,mux_2level_size50_46_sram_blwl_out[2414:2414] ,mux_2level_size50_46_sram_blwl_outb[2414:2414] ,mux_2level_size50_46_configbus0[2414:2414], mux_2level_size50_46_configbus1[2414:2414] , mux_2level_size50_46_configbus0_b[2414:2414] ); -sram6T_blwl sram_blwl_2415_ (mux_2level_size50_46_sram_blwl_out[2415:2415] ,mux_2level_size50_46_sram_blwl_out[2415:2415] ,mux_2level_size50_46_sram_blwl_outb[2415:2415] ,mux_2level_size50_46_configbus0[2415:2415], mux_2level_size50_46_configbus1[2415:2415] , mux_2level_size50_46_configbus0_b[2415:2415] ); -sram6T_blwl sram_blwl_2416_ (mux_2level_size50_46_sram_blwl_out[2416:2416] ,mux_2level_size50_46_sram_blwl_out[2416:2416] ,mux_2level_size50_46_sram_blwl_outb[2416:2416] ,mux_2level_size50_46_configbus0[2416:2416], mux_2level_size50_46_configbus1[2416:2416] , mux_2level_size50_46_configbus0_b[2416:2416] ); -sram6T_blwl sram_blwl_2417_ (mux_2level_size50_46_sram_blwl_out[2417:2417] ,mux_2level_size50_46_sram_blwl_out[2417:2417] ,mux_2level_size50_46_sram_blwl_outb[2417:2417] ,mux_2level_size50_46_configbus0[2417:2417], mux_2level_size50_46_configbus1[2417:2417] , mux_2level_size50_46_configbus0_b[2417:2417] ); -wire [0:49] in_bus_mux_2level_size50_47_ ; -assign in_bus_mux_2level_size50_47_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_47_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_47_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_47_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_47_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_47_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_47_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_47_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_47_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_47_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_47_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_47_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_47_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_47_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_47_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_47_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_47_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_47_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_47_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_47_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_47_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_47_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_47_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_47_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_47_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_47_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_47_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_47_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_47_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_47_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_47_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_47_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_47_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_47_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_47_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_47_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_47_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_47_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_47_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_47_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_47_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_47_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_47_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_47_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_47_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_47_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_47_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_47_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_47_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_47_[49] = fle_9___out_0_ ; -wire [2418:2433] mux_2level_size50_47_configbus0; -wire [2418:2433] mux_2level_size50_47_configbus1; -wire [2418:2433] mux_2level_size50_47_sram_blwl_out ; -wire [2418:2433] mux_2level_size50_47_sram_blwl_outb ; -assign mux_2level_size50_47_configbus0[2418:2433] = sram_blwl_bl[2418:2433] ; -assign mux_2level_size50_47_configbus1[2418:2433] = sram_blwl_wl[2418:2433] ; -wire [2418:2433] mux_2level_size50_47_configbus0_b; -assign mux_2level_size50_47_configbus0_b[2418:2433] = sram_blwl_blb[2418:2433] ; -mux_2level_size50 mux_2level_size50_47_ (in_bus_mux_2level_size50_47_, fle_7___in_5_, mux_2level_size50_47_sram_blwl_out[2418:2433] , -mux_2level_size50_47_sram_blwl_outb[2418:2433] ); -//----- SRAM bits for MUX[47], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2418_ (mux_2level_size50_47_sram_blwl_out[2418:2418] ,mux_2level_size50_47_sram_blwl_out[2418:2418] ,mux_2level_size50_47_sram_blwl_outb[2418:2418] ,mux_2level_size50_47_configbus0[2418:2418], mux_2level_size50_47_configbus1[2418:2418] , mux_2level_size50_47_configbus0_b[2418:2418] ); -sram6T_blwl sram_blwl_2419_ (mux_2level_size50_47_sram_blwl_out[2419:2419] ,mux_2level_size50_47_sram_blwl_out[2419:2419] ,mux_2level_size50_47_sram_blwl_outb[2419:2419] ,mux_2level_size50_47_configbus0[2419:2419], mux_2level_size50_47_configbus1[2419:2419] , mux_2level_size50_47_configbus0_b[2419:2419] ); -sram6T_blwl sram_blwl_2420_ (mux_2level_size50_47_sram_blwl_out[2420:2420] ,mux_2level_size50_47_sram_blwl_out[2420:2420] ,mux_2level_size50_47_sram_blwl_outb[2420:2420] ,mux_2level_size50_47_configbus0[2420:2420], mux_2level_size50_47_configbus1[2420:2420] , mux_2level_size50_47_configbus0_b[2420:2420] ); -sram6T_blwl sram_blwl_2421_ (mux_2level_size50_47_sram_blwl_out[2421:2421] ,mux_2level_size50_47_sram_blwl_out[2421:2421] ,mux_2level_size50_47_sram_blwl_outb[2421:2421] ,mux_2level_size50_47_configbus0[2421:2421], mux_2level_size50_47_configbus1[2421:2421] , mux_2level_size50_47_configbus0_b[2421:2421] ); -sram6T_blwl sram_blwl_2422_ (mux_2level_size50_47_sram_blwl_out[2422:2422] ,mux_2level_size50_47_sram_blwl_out[2422:2422] ,mux_2level_size50_47_sram_blwl_outb[2422:2422] ,mux_2level_size50_47_configbus0[2422:2422], mux_2level_size50_47_configbus1[2422:2422] , mux_2level_size50_47_configbus0_b[2422:2422] ); -sram6T_blwl sram_blwl_2423_ (mux_2level_size50_47_sram_blwl_out[2423:2423] ,mux_2level_size50_47_sram_blwl_out[2423:2423] ,mux_2level_size50_47_sram_blwl_outb[2423:2423] ,mux_2level_size50_47_configbus0[2423:2423], mux_2level_size50_47_configbus1[2423:2423] , mux_2level_size50_47_configbus0_b[2423:2423] ); -sram6T_blwl sram_blwl_2424_ (mux_2level_size50_47_sram_blwl_out[2424:2424] ,mux_2level_size50_47_sram_blwl_out[2424:2424] ,mux_2level_size50_47_sram_blwl_outb[2424:2424] ,mux_2level_size50_47_configbus0[2424:2424], mux_2level_size50_47_configbus1[2424:2424] , mux_2level_size50_47_configbus0_b[2424:2424] ); -sram6T_blwl sram_blwl_2425_ (mux_2level_size50_47_sram_blwl_out[2425:2425] ,mux_2level_size50_47_sram_blwl_out[2425:2425] ,mux_2level_size50_47_sram_blwl_outb[2425:2425] ,mux_2level_size50_47_configbus0[2425:2425], mux_2level_size50_47_configbus1[2425:2425] , mux_2level_size50_47_configbus0_b[2425:2425] ); -sram6T_blwl sram_blwl_2426_ (mux_2level_size50_47_sram_blwl_out[2426:2426] ,mux_2level_size50_47_sram_blwl_out[2426:2426] ,mux_2level_size50_47_sram_blwl_outb[2426:2426] ,mux_2level_size50_47_configbus0[2426:2426], mux_2level_size50_47_configbus1[2426:2426] , mux_2level_size50_47_configbus0_b[2426:2426] ); -sram6T_blwl sram_blwl_2427_ (mux_2level_size50_47_sram_blwl_out[2427:2427] ,mux_2level_size50_47_sram_blwl_out[2427:2427] ,mux_2level_size50_47_sram_blwl_outb[2427:2427] ,mux_2level_size50_47_configbus0[2427:2427], mux_2level_size50_47_configbus1[2427:2427] , mux_2level_size50_47_configbus0_b[2427:2427] ); -sram6T_blwl sram_blwl_2428_ (mux_2level_size50_47_sram_blwl_out[2428:2428] ,mux_2level_size50_47_sram_blwl_out[2428:2428] ,mux_2level_size50_47_sram_blwl_outb[2428:2428] ,mux_2level_size50_47_configbus0[2428:2428], mux_2level_size50_47_configbus1[2428:2428] , mux_2level_size50_47_configbus0_b[2428:2428] ); -sram6T_blwl sram_blwl_2429_ (mux_2level_size50_47_sram_blwl_out[2429:2429] ,mux_2level_size50_47_sram_blwl_out[2429:2429] ,mux_2level_size50_47_sram_blwl_outb[2429:2429] ,mux_2level_size50_47_configbus0[2429:2429], mux_2level_size50_47_configbus1[2429:2429] , mux_2level_size50_47_configbus0_b[2429:2429] ); -sram6T_blwl sram_blwl_2430_ (mux_2level_size50_47_sram_blwl_out[2430:2430] ,mux_2level_size50_47_sram_blwl_out[2430:2430] ,mux_2level_size50_47_sram_blwl_outb[2430:2430] ,mux_2level_size50_47_configbus0[2430:2430], mux_2level_size50_47_configbus1[2430:2430] , mux_2level_size50_47_configbus0_b[2430:2430] ); -sram6T_blwl sram_blwl_2431_ (mux_2level_size50_47_sram_blwl_out[2431:2431] ,mux_2level_size50_47_sram_blwl_out[2431:2431] ,mux_2level_size50_47_sram_blwl_outb[2431:2431] ,mux_2level_size50_47_configbus0[2431:2431], mux_2level_size50_47_configbus1[2431:2431] , mux_2level_size50_47_configbus0_b[2431:2431] ); -sram6T_blwl sram_blwl_2432_ (mux_2level_size50_47_sram_blwl_out[2432:2432] ,mux_2level_size50_47_sram_blwl_out[2432:2432] ,mux_2level_size50_47_sram_blwl_outb[2432:2432] ,mux_2level_size50_47_configbus0[2432:2432], mux_2level_size50_47_configbus1[2432:2432] , mux_2level_size50_47_configbus0_b[2432:2432] ); -sram6T_blwl sram_blwl_2433_ (mux_2level_size50_47_sram_blwl_out[2433:2433] ,mux_2level_size50_47_sram_blwl_out[2433:2433] ,mux_2level_size50_47_sram_blwl_outb[2433:2433] ,mux_2level_size50_47_configbus0[2433:2433], mux_2level_size50_47_configbus1[2433:2433] , mux_2level_size50_47_configbus0_b[2433:2433] ); -direct_interc direct_interc_177_ (mode_clb___clk_0_, fle_7___clk_0_ ); -wire [0:49] in_bus_mux_2level_size50_48_ ; -assign in_bus_mux_2level_size50_48_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_48_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_48_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_48_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_48_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_48_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_48_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_48_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_48_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_48_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_48_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_48_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_48_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_48_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_48_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_48_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_48_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_48_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_48_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_48_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_48_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_48_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_48_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_48_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_48_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_48_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_48_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_48_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_48_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_48_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_48_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_48_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_48_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_48_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_48_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_48_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_48_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_48_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_48_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_48_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_48_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_48_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_48_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_48_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_48_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_48_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_48_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_48_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_48_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_48_[49] = fle_9___out_0_ ; -wire [2434:2449] mux_2level_size50_48_configbus0; -wire [2434:2449] mux_2level_size50_48_configbus1; -wire [2434:2449] mux_2level_size50_48_sram_blwl_out ; -wire [2434:2449] mux_2level_size50_48_sram_blwl_outb ; -assign mux_2level_size50_48_configbus0[2434:2449] = sram_blwl_bl[2434:2449] ; -assign mux_2level_size50_48_configbus1[2434:2449] = sram_blwl_wl[2434:2449] ; -wire [2434:2449] mux_2level_size50_48_configbus0_b; -assign mux_2level_size50_48_configbus0_b[2434:2449] = sram_blwl_blb[2434:2449] ; -mux_2level_size50 mux_2level_size50_48_ (in_bus_mux_2level_size50_48_, fle_8___in_0_, mux_2level_size50_48_sram_blwl_out[2434:2449] , -mux_2level_size50_48_sram_blwl_outb[2434:2449] ); -//----- SRAM bits for MUX[48], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2434_ (mux_2level_size50_48_sram_blwl_out[2434:2434] ,mux_2level_size50_48_sram_blwl_out[2434:2434] ,mux_2level_size50_48_sram_blwl_outb[2434:2434] ,mux_2level_size50_48_configbus0[2434:2434], mux_2level_size50_48_configbus1[2434:2434] , mux_2level_size50_48_configbus0_b[2434:2434] ); -sram6T_blwl sram_blwl_2435_ (mux_2level_size50_48_sram_blwl_out[2435:2435] ,mux_2level_size50_48_sram_blwl_out[2435:2435] ,mux_2level_size50_48_sram_blwl_outb[2435:2435] ,mux_2level_size50_48_configbus0[2435:2435], mux_2level_size50_48_configbus1[2435:2435] , mux_2level_size50_48_configbus0_b[2435:2435] ); -sram6T_blwl sram_blwl_2436_ (mux_2level_size50_48_sram_blwl_out[2436:2436] ,mux_2level_size50_48_sram_blwl_out[2436:2436] ,mux_2level_size50_48_sram_blwl_outb[2436:2436] ,mux_2level_size50_48_configbus0[2436:2436], mux_2level_size50_48_configbus1[2436:2436] , mux_2level_size50_48_configbus0_b[2436:2436] ); -sram6T_blwl sram_blwl_2437_ (mux_2level_size50_48_sram_blwl_out[2437:2437] ,mux_2level_size50_48_sram_blwl_out[2437:2437] ,mux_2level_size50_48_sram_blwl_outb[2437:2437] ,mux_2level_size50_48_configbus0[2437:2437], mux_2level_size50_48_configbus1[2437:2437] , mux_2level_size50_48_configbus0_b[2437:2437] ); -sram6T_blwl sram_blwl_2438_ (mux_2level_size50_48_sram_blwl_out[2438:2438] ,mux_2level_size50_48_sram_blwl_out[2438:2438] ,mux_2level_size50_48_sram_blwl_outb[2438:2438] ,mux_2level_size50_48_configbus0[2438:2438], mux_2level_size50_48_configbus1[2438:2438] , mux_2level_size50_48_configbus0_b[2438:2438] ); -sram6T_blwl sram_blwl_2439_ (mux_2level_size50_48_sram_blwl_out[2439:2439] ,mux_2level_size50_48_sram_blwl_out[2439:2439] ,mux_2level_size50_48_sram_blwl_outb[2439:2439] ,mux_2level_size50_48_configbus0[2439:2439], mux_2level_size50_48_configbus1[2439:2439] , mux_2level_size50_48_configbus0_b[2439:2439] ); -sram6T_blwl sram_blwl_2440_ (mux_2level_size50_48_sram_blwl_out[2440:2440] ,mux_2level_size50_48_sram_blwl_out[2440:2440] ,mux_2level_size50_48_sram_blwl_outb[2440:2440] ,mux_2level_size50_48_configbus0[2440:2440], mux_2level_size50_48_configbus1[2440:2440] , mux_2level_size50_48_configbus0_b[2440:2440] ); -sram6T_blwl sram_blwl_2441_ (mux_2level_size50_48_sram_blwl_out[2441:2441] ,mux_2level_size50_48_sram_blwl_out[2441:2441] ,mux_2level_size50_48_sram_blwl_outb[2441:2441] ,mux_2level_size50_48_configbus0[2441:2441], mux_2level_size50_48_configbus1[2441:2441] , mux_2level_size50_48_configbus0_b[2441:2441] ); -sram6T_blwl sram_blwl_2442_ (mux_2level_size50_48_sram_blwl_out[2442:2442] ,mux_2level_size50_48_sram_blwl_out[2442:2442] ,mux_2level_size50_48_sram_blwl_outb[2442:2442] ,mux_2level_size50_48_configbus0[2442:2442], mux_2level_size50_48_configbus1[2442:2442] , mux_2level_size50_48_configbus0_b[2442:2442] ); -sram6T_blwl sram_blwl_2443_ (mux_2level_size50_48_sram_blwl_out[2443:2443] ,mux_2level_size50_48_sram_blwl_out[2443:2443] ,mux_2level_size50_48_sram_blwl_outb[2443:2443] ,mux_2level_size50_48_configbus0[2443:2443], mux_2level_size50_48_configbus1[2443:2443] , mux_2level_size50_48_configbus0_b[2443:2443] ); -sram6T_blwl sram_blwl_2444_ (mux_2level_size50_48_sram_blwl_out[2444:2444] ,mux_2level_size50_48_sram_blwl_out[2444:2444] ,mux_2level_size50_48_sram_blwl_outb[2444:2444] ,mux_2level_size50_48_configbus0[2444:2444], mux_2level_size50_48_configbus1[2444:2444] , mux_2level_size50_48_configbus0_b[2444:2444] ); -sram6T_blwl sram_blwl_2445_ (mux_2level_size50_48_sram_blwl_out[2445:2445] ,mux_2level_size50_48_sram_blwl_out[2445:2445] ,mux_2level_size50_48_sram_blwl_outb[2445:2445] ,mux_2level_size50_48_configbus0[2445:2445], mux_2level_size50_48_configbus1[2445:2445] , mux_2level_size50_48_configbus0_b[2445:2445] ); -sram6T_blwl sram_blwl_2446_ (mux_2level_size50_48_sram_blwl_out[2446:2446] ,mux_2level_size50_48_sram_blwl_out[2446:2446] ,mux_2level_size50_48_sram_blwl_outb[2446:2446] ,mux_2level_size50_48_configbus0[2446:2446], mux_2level_size50_48_configbus1[2446:2446] , mux_2level_size50_48_configbus0_b[2446:2446] ); -sram6T_blwl sram_blwl_2447_ (mux_2level_size50_48_sram_blwl_out[2447:2447] ,mux_2level_size50_48_sram_blwl_out[2447:2447] ,mux_2level_size50_48_sram_blwl_outb[2447:2447] ,mux_2level_size50_48_configbus0[2447:2447], mux_2level_size50_48_configbus1[2447:2447] , mux_2level_size50_48_configbus0_b[2447:2447] ); -sram6T_blwl sram_blwl_2448_ (mux_2level_size50_48_sram_blwl_out[2448:2448] ,mux_2level_size50_48_sram_blwl_out[2448:2448] ,mux_2level_size50_48_sram_blwl_outb[2448:2448] ,mux_2level_size50_48_configbus0[2448:2448], mux_2level_size50_48_configbus1[2448:2448] , mux_2level_size50_48_configbus0_b[2448:2448] ); -sram6T_blwl sram_blwl_2449_ (mux_2level_size50_48_sram_blwl_out[2449:2449] ,mux_2level_size50_48_sram_blwl_out[2449:2449] ,mux_2level_size50_48_sram_blwl_outb[2449:2449] ,mux_2level_size50_48_configbus0[2449:2449], mux_2level_size50_48_configbus1[2449:2449] , mux_2level_size50_48_configbus0_b[2449:2449] ); -wire [0:49] in_bus_mux_2level_size50_49_ ; -assign in_bus_mux_2level_size50_49_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_49_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_49_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_49_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_49_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_49_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_49_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_49_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_49_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_49_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_49_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_49_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_49_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_49_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_49_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_49_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_49_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_49_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_49_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_49_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_49_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_49_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_49_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_49_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_49_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_49_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_49_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_49_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_49_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_49_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_49_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_49_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_49_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_49_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_49_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_49_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_49_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_49_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_49_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_49_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_49_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_49_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_49_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_49_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_49_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_49_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_49_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_49_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_49_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_49_[49] = fle_9___out_0_ ; -wire [2450:2465] mux_2level_size50_49_configbus0; -wire [2450:2465] mux_2level_size50_49_configbus1; -wire [2450:2465] mux_2level_size50_49_sram_blwl_out ; -wire [2450:2465] mux_2level_size50_49_sram_blwl_outb ; -assign mux_2level_size50_49_configbus0[2450:2465] = sram_blwl_bl[2450:2465] ; -assign mux_2level_size50_49_configbus1[2450:2465] = sram_blwl_wl[2450:2465] ; -wire [2450:2465] mux_2level_size50_49_configbus0_b; -assign mux_2level_size50_49_configbus0_b[2450:2465] = sram_blwl_blb[2450:2465] ; -mux_2level_size50 mux_2level_size50_49_ (in_bus_mux_2level_size50_49_, fle_8___in_1_, mux_2level_size50_49_sram_blwl_out[2450:2465] , -mux_2level_size50_49_sram_blwl_outb[2450:2465] ); -//----- SRAM bits for MUX[49], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2450_ (mux_2level_size50_49_sram_blwl_out[2450:2450] ,mux_2level_size50_49_sram_blwl_out[2450:2450] ,mux_2level_size50_49_sram_blwl_outb[2450:2450] ,mux_2level_size50_49_configbus0[2450:2450], mux_2level_size50_49_configbus1[2450:2450] , mux_2level_size50_49_configbus0_b[2450:2450] ); -sram6T_blwl sram_blwl_2451_ (mux_2level_size50_49_sram_blwl_out[2451:2451] ,mux_2level_size50_49_sram_blwl_out[2451:2451] ,mux_2level_size50_49_sram_blwl_outb[2451:2451] ,mux_2level_size50_49_configbus0[2451:2451], mux_2level_size50_49_configbus1[2451:2451] , mux_2level_size50_49_configbus0_b[2451:2451] ); -sram6T_blwl sram_blwl_2452_ (mux_2level_size50_49_sram_blwl_out[2452:2452] ,mux_2level_size50_49_sram_blwl_out[2452:2452] ,mux_2level_size50_49_sram_blwl_outb[2452:2452] ,mux_2level_size50_49_configbus0[2452:2452], mux_2level_size50_49_configbus1[2452:2452] , mux_2level_size50_49_configbus0_b[2452:2452] ); -sram6T_blwl sram_blwl_2453_ (mux_2level_size50_49_sram_blwl_out[2453:2453] ,mux_2level_size50_49_sram_blwl_out[2453:2453] ,mux_2level_size50_49_sram_blwl_outb[2453:2453] ,mux_2level_size50_49_configbus0[2453:2453], mux_2level_size50_49_configbus1[2453:2453] , mux_2level_size50_49_configbus0_b[2453:2453] ); -sram6T_blwl sram_blwl_2454_ (mux_2level_size50_49_sram_blwl_out[2454:2454] ,mux_2level_size50_49_sram_blwl_out[2454:2454] ,mux_2level_size50_49_sram_blwl_outb[2454:2454] ,mux_2level_size50_49_configbus0[2454:2454], mux_2level_size50_49_configbus1[2454:2454] , mux_2level_size50_49_configbus0_b[2454:2454] ); -sram6T_blwl sram_blwl_2455_ (mux_2level_size50_49_sram_blwl_out[2455:2455] ,mux_2level_size50_49_sram_blwl_out[2455:2455] ,mux_2level_size50_49_sram_blwl_outb[2455:2455] ,mux_2level_size50_49_configbus0[2455:2455], mux_2level_size50_49_configbus1[2455:2455] , mux_2level_size50_49_configbus0_b[2455:2455] ); -sram6T_blwl sram_blwl_2456_ (mux_2level_size50_49_sram_blwl_out[2456:2456] ,mux_2level_size50_49_sram_blwl_out[2456:2456] ,mux_2level_size50_49_sram_blwl_outb[2456:2456] ,mux_2level_size50_49_configbus0[2456:2456], mux_2level_size50_49_configbus1[2456:2456] , mux_2level_size50_49_configbus0_b[2456:2456] ); -sram6T_blwl sram_blwl_2457_ (mux_2level_size50_49_sram_blwl_out[2457:2457] ,mux_2level_size50_49_sram_blwl_out[2457:2457] ,mux_2level_size50_49_sram_blwl_outb[2457:2457] ,mux_2level_size50_49_configbus0[2457:2457], mux_2level_size50_49_configbus1[2457:2457] , mux_2level_size50_49_configbus0_b[2457:2457] ); -sram6T_blwl sram_blwl_2458_ (mux_2level_size50_49_sram_blwl_out[2458:2458] ,mux_2level_size50_49_sram_blwl_out[2458:2458] ,mux_2level_size50_49_sram_blwl_outb[2458:2458] ,mux_2level_size50_49_configbus0[2458:2458], mux_2level_size50_49_configbus1[2458:2458] , mux_2level_size50_49_configbus0_b[2458:2458] ); -sram6T_blwl sram_blwl_2459_ (mux_2level_size50_49_sram_blwl_out[2459:2459] ,mux_2level_size50_49_sram_blwl_out[2459:2459] ,mux_2level_size50_49_sram_blwl_outb[2459:2459] ,mux_2level_size50_49_configbus0[2459:2459], mux_2level_size50_49_configbus1[2459:2459] , mux_2level_size50_49_configbus0_b[2459:2459] ); -sram6T_blwl sram_blwl_2460_ (mux_2level_size50_49_sram_blwl_out[2460:2460] ,mux_2level_size50_49_sram_blwl_out[2460:2460] ,mux_2level_size50_49_sram_blwl_outb[2460:2460] ,mux_2level_size50_49_configbus0[2460:2460], mux_2level_size50_49_configbus1[2460:2460] , mux_2level_size50_49_configbus0_b[2460:2460] ); -sram6T_blwl sram_blwl_2461_ (mux_2level_size50_49_sram_blwl_out[2461:2461] ,mux_2level_size50_49_sram_blwl_out[2461:2461] ,mux_2level_size50_49_sram_blwl_outb[2461:2461] ,mux_2level_size50_49_configbus0[2461:2461], mux_2level_size50_49_configbus1[2461:2461] , mux_2level_size50_49_configbus0_b[2461:2461] ); -sram6T_blwl sram_blwl_2462_ (mux_2level_size50_49_sram_blwl_out[2462:2462] ,mux_2level_size50_49_sram_blwl_out[2462:2462] ,mux_2level_size50_49_sram_blwl_outb[2462:2462] ,mux_2level_size50_49_configbus0[2462:2462], mux_2level_size50_49_configbus1[2462:2462] , mux_2level_size50_49_configbus0_b[2462:2462] ); -sram6T_blwl sram_blwl_2463_ (mux_2level_size50_49_sram_blwl_out[2463:2463] ,mux_2level_size50_49_sram_blwl_out[2463:2463] ,mux_2level_size50_49_sram_blwl_outb[2463:2463] ,mux_2level_size50_49_configbus0[2463:2463], mux_2level_size50_49_configbus1[2463:2463] , mux_2level_size50_49_configbus0_b[2463:2463] ); -sram6T_blwl sram_blwl_2464_ (mux_2level_size50_49_sram_blwl_out[2464:2464] ,mux_2level_size50_49_sram_blwl_out[2464:2464] ,mux_2level_size50_49_sram_blwl_outb[2464:2464] ,mux_2level_size50_49_configbus0[2464:2464], mux_2level_size50_49_configbus1[2464:2464] , mux_2level_size50_49_configbus0_b[2464:2464] ); -sram6T_blwl sram_blwl_2465_ (mux_2level_size50_49_sram_blwl_out[2465:2465] ,mux_2level_size50_49_sram_blwl_out[2465:2465] ,mux_2level_size50_49_sram_blwl_outb[2465:2465] ,mux_2level_size50_49_configbus0[2465:2465], mux_2level_size50_49_configbus1[2465:2465] , mux_2level_size50_49_configbus0_b[2465:2465] ); -wire [0:49] in_bus_mux_2level_size50_50_ ; -assign in_bus_mux_2level_size50_50_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_50_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_50_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_50_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_50_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_50_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_50_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_50_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_50_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_50_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_50_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_50_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_50_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_50_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_50_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_50_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_50_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_50_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_50_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_50_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_50_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_50_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_50_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_50_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_50_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_50_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_50_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_50_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_50_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_50_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_50_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_50_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_50_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_50_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_50_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_50_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_50_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_50_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_50_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_50_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_50_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_50_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_50_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_50_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_50_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_50_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_50_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_50_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_50_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_50_[49] = fle_9___out_0_ ; -wire [2466:2481] mux_2level_size50_50_configbus0; -wire [2466:2481] mux_2level_size50_50_configbus1; -wire [2466:2481] mux_2level_size50_50_sram_blwl_out ; -wire [2466:2481] mux_2level_size50_50_sram_blwl_outb ; -assign mux_2level_size50_50_configbus0[2466:2481] = sram_blwl_bl[2466:2481] ; -assign mux_2level_size50_50_configbus1[2466:2481] = sram_blwl_wl[2466:2481] ; -wire [2466:2481] mux_2level_size50_50_configbus0_b; -assign mux_2level_size50_50_configbus0_b[2466:2481] = sram_blwl_blb[2466:2481] ; -mux_2level_size50 mux_2level_size50_50_ (in_bus_mux_2level_size50_50_, fle_8___in_2_, mux_2level_size50_50_sram_blwl_out[2466:2481] , -mux_2level_size50_50_sram_blwl_outb[2466:2481] ); -//----- SRAM bits for MUX[50], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2466_ (mux_2level_size50_50_sram_blwl_out[2466:2466] ,mux_2level_size50_50_sram_blwl_out[2466:2466] ,mux_2level_size50_50_sram_blwl_outb[2466:2466] ,mux_2level_size50_50_configbus0[2466:2466], mux_2level_size50_50_configbus1[2466:2466] , mux_2level_size50_50_configbus0_b[2466:2466] ); -sram6T_blwl sram_blwl_2467_ (mux_2level_size50_50_sram_blwl_out[2467:2467] ,mux_2level_size50_50_sram_blwl_out[2467:2467] ,mux_2level_size50_50_sram_blwl_outb[2467:2467] ,mux_2level_size50_50_configbus0[2467:2467], mux_2level_size50_50_configbus1[2467:2467] , mux_2level_size50_50_configbus0_b[2467:2467] ); -sram6T_blwl sram_blwl_2468_ (mux_2level_size50_50_sram_blwl_out[2468:2468] ,mux_2level_size50_50_sram_blwl_out[2468:2468] ,mux_2level_size50_50_sram_blwl_outb[2468:2468] ,mux_2level_size50_50_configbus0[2468:2468], mux_2level_size50_50_configbus1[2468:2468] , mux_2level_size50_50_configbus0_b[2468:2468] ); -sram6T_blwl sram_blwl_2469_ (mux_2level_size50_50_sram_blwl_out[2469:2469] ,mux_2level_size50_50_sram_blwl_out[2469:2469] ,mux_2level_size50_50_sram_blwl_outb[2469:2469] ,mux_2level_size50_50_configbus0[2469:2469], mux_2level_size50_50_configbus1[2469:2469] , mux_2level_size50_50_configbus0_b[2469:2469] ); -sram6T_blwl sram_blwl_2470_ (mux_2level_size50_50_sram_blwl_out[2470:2470] ,mux_2level_size50_50_sram_blwl_out[2470:2470] ,mux_2level_size50_50_sram_blwl_outb[2470:2470] ,mux_2level_size50_50_configbus0[2470:2470], mux_2level_size50_50_configbus1[2470:2470] , mux_2level_size50_50_configbus0_b[2470:2470] ); -sram6T_blwl sram_blwl_2471_ (mux_2level_size50_50_sram_blwl_out[2471:2471] ,mux_2level_size50_50_sram_blwl_out[2471:2471] ,mux_2level_size50_50_sram_blwl_outb[2471:2471] ,mux_2level_size50_50_configbus0[2471:2471], mux_2level_size50_50_configbus1[2471:2471] , mux_2level_size50_50_configbus0_b[2471:2471] ); -sram6T_blwl sram_blwl_2472_ (mux_2level_size50_50_sram_blwl_out[2472:2472] ,mux_2level_size50_50_sram_blwl_out[2472:2472] ,mux_2level_size50_50_sram_blwl_outb[2472:2472] ,mux_2level_size50_50_configbus0[2472:2472], mux_2level_size50_50_configbus1[2472:2472] , mux_2level_size50_50_configbus0_b[2472:2472] ); -sram6T_blwl sram_blwl_2473_ (mux_2level_size50_50_sram_blwl_out[2473:2473] ,mux_2level_size50_50_sram_blwl_out[2473:2473] ,mux_2level_size50_50_sram_blwl_outb[2473:2473] ,mux_2level_size50_50_configbus0[2473:2473], mux_2level_size50_50_configbus1[2473:2473] , mux_2level_size50_50_configbus0_b[2473:2473] ); -sram6T_blwl sram_blwl_2474_ (mux_2level_size50_50_sram_blwl_out[2474:2474] ,mux_2level_size50_50_sram_blwl_out[2474:2474] ,mux_2level_size50_50_sram_blwl_outb[2474:2474] ,mux_2level_size50_50_configbus0[2474:2474], mux_2level_size50_50_configbus1[2474:2474] , mux_2level_size50_50_configbus0_b[2474:2474] ); -sram6T_blwl sram_blwl_2475_ (mux_2level_size50_50_sram_blwl_out[2475:2475] ,mux_2level_size50_50_sram_blwl_out[2475:2475] ,mux_2level_size50_50_sram_blwl_outb[2475:2475] ,mux_2level_size50_50_configbus0[2475:2475], mux_2level_size50_50_configbus1[2475:2475] , mux_2level_size50_50_configbus0_b[2475:2475] ); -sram6T_blwl sram_blwl_2476_ (mux_2level_size50_50_sram_blwl_out[2476:2476] ,mux_2level_size50_50_sram_blwl_out[2476:2476] ,mux_2level_size50_50_sram_blwl_outb[2476:2476] ,mux_2level_size50_50_configbus0[2476:2476], mux_2level_size50_50_configbus1[2476:2476] , mux_2level_size50_50_configbus0_b[2476:2476] ); -sram6T_blwl sram_blwl_2477_ (mux_2level_size50_50_sram_blwl_out[2477:2477] ,mux_2level_size50_50_sram_blwl_out[2477:2477] ,mux_2level_size50_50_sram_blwl_outb[2477:2477] ,mux_2level_size50_50_configbus0[2477:2477], mux_2level_size50_50_configbus1[2477:2477] , mux_2level_size50_50_configbus0_b[2477:2477] ); -sram6T_blwl sram_blwl_2478_ (mux_2level_size50_50_sram_blwl_out[2478:2478] ,mux_2level_size50_50_sram_blwl_out[2478:2478] ,mux_2level_size50_50_sram_blwl_outb[2478:2478] ,mux_2level_size50_50_configbus0[2478:2478], mux_2level_size50_50_configbus1[2478:2478] , mux_2level_size50_50_configbus0_b[2478:2478] ); -sram6T_blwl sram_blwl_2479_ (mux_2level_size50_50_sram_blwl_out[2479:2479] ,mux_2level_size50_50_sram_blwl_out[2479:2479] ,mux_2level_size50_50_sram_blwl_outb[2479:2479] ,mux_2level_size50_50_configbus0[2479:2479], mux_2level_size50_50_configbus1[2479:2479] , mux_2level_size50_50_configbus0_b[2479:2479] ); -sram6T_blwl sram_blwl_2480_ (mux_2level_size50_50_sram_blwl_out[2480:2480] ,mux_2level_size50_50_sram_blwl_out[2480:2480] ,mux_2level_size50_50_sram_blwl_outb[2480:2480] ,mux_2level_size50_50_configbus0[2480:2480], mux_2level_size50_50_configbus1[2480:2480] , mux_2level_size50_50_configbus0_b[2480:2480] ); -sram6T_blwl sram_blwl_2481_ (mux_2level_size50_50_sram_blwl_out[2481:2481] ,mux_2level_size50_50_sram_blwl_out[2481:2481] ,mux_2level_size50_50_sram_blwl_outb[2481:2481] ,mux_2level_size50_50_configbus0[2481:2481], mux_2level_size50_50_configbus1[2481:2481] , mux_2level_size50_50_configbus0_b[2481:2481] ); -wire [0:49] in_bus_mux_2level_size50_51_ ; -assign in_bus_mux_2level_size50_51_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_51_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_51_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_51_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_51_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_51_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_51_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_51_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_51_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_51_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_51_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_51_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_51_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_51_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_51_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_51_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_51_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_51_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_51_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_51_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_51_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_51_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_51_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_51_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_51_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_51_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_51_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_51_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_51_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_51_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_51_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_51_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_51_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_51_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_51_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_51_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_51_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_51_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_51_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_51_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_51_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_51_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_51_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_51_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_51_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_51_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_51_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_51_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_51_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_51_[49] = fle_9___out_0_ ; -wire [2482:2497] mux_2level_size50_51_configbus0; -wire [2482:2497] mux_2level_size50_51_configbus1; -wire [2482:2497] mux_2level_size50_51_sram_blwl_out ; -wire [2482:2497] mux_2level_size50_51_sram_blwl_outb ; -assign mux_2level_size50_51_configbus0[2482:2497] = sram_blwl_bl[2482:2497] ; -assign mux_2level_size50_51_configbus1[2482:2497] = sram_blwl_wl[2482:2497] ; -wire [2482:2497] mux_2level_size50_51_configbus0_b; -assign mux_2level_size50_51_configbus0_b[2482:2497] = sram_blwl_blb[2482:2497] ; -mux_2level_size50 mux_2level_size50_51_ (in_bus_mux_2level_size50_51_, fle_8___in_3_, mux_2level_size50_51_sram_blwl_out[2482:2497] , -mux_2level_size50_51_sram_blwl_outb[2482:2497] ); -//----- SRAM bits for MUX[51], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2482_ (mux_2level_size50_51_sram_blwl_out[2482:2482] ,mux_2level_size50_51_sram_blwl_out[2482:2482] ,mux_2level_size50_51_sram_blwl_outb[2482:2482] ,mux_2level_size50_51_configbus0[2482:2482], mux_2level_size50_51_configbus1[2482:2482] , mux_2level_size50_51_configbus0_b[2482:2482] ); -sram6T_blwl sram_blwl_2483_ (mux_2level_size50_51_sram_blwl_out[2483:2483] ,mux_2level_size50_51_sram_blwl_out[2483:2483] ,mux_2level_size50_51_sram_blwl_outb[2483:2483] ,mux_2level_size50_51_configbus0[2483:2483], mux_2level_size50_51_configbus1[2483:2483] , mux_2level_size50_51_configbus0_b[2483:2483] ); -sram6T_blwl sram_blwl_2484_ (mux_2level_size50_51_sram_blwl_out[2484:2484] ,mux_2level_size50_51_sram_blwl_out[2484:2484] ,mux_2level_size50_51_sram_blwl_outb[2484:2484] ,mux_2level_size50_51_configbus0[2484:2484], mux_2level_size50_51_configbus1[2484:2484] , mux_2level_size50_51_configbus0_b[2484:2484] ); -sram6T_blwl sram_blwl_2485_ (mux_2level_size50_51_sram_blwl_out[2485:2485] ,mux_2level_size50_51_sram_blwl_out[2485:2485] ,mux_2level_size50_51_sram_blwl_outb[2485:2485] ,mux_2level_size50_51_configbus0[2485:2485], mux_2level_size50_51_configbus1[2485:2485] , mux_2level_size50_51_configbus0_b[2485:2485] ); -sram6T_blwl sram_blwl_2486_ (mux_2level_size50_51_sram_blwl_out[2486:2486] ,mux_2level_size50_51_sram_blwl_out[2486:2486] ,mux_2level_size50_51_sram_blwl_outb[2486:2486] ,mux_2level_size50_51_configbus0[2486:2486], mux_2level_size50_51_configbus1[2486:2486] , mux_2level_size50_51_configbus0_b[2486:2486] ); -sram6T_blwl sram_blwl_2487_ (mux_2level_size50_51_sram_blwl_out[2487:2487] ,mux_2level_size50_51_sram_blwl_out[2487:2487] ,mux_2level_size50_51_sram_blwl_outb[2487:2487] ,mux_2level_size50_51_configbus0[2487:2487], mux_2level_size50_51_configbus1[2487:2487] , mux_2level_size50_51_configbus0_b[2487:2487] ); -sram6T_blwl sram_blwl_2488_ (mux_2level_size50_51_sram_blwl_out[2488:2488] ,mux_2level_size50_51_sram_blwl_out[2488:2488] ,mux_2level_size50_51_sram_blwl_outb[2488:2488] ,mux_2level_size50_51_configbus0[2488:2488], mux_2level_size50_51_configbus1[2488:2488] , mux_2level_size50_51_configbus0_b[2488:2488] ); -sram6T_blwl sram_blwl_2489_ (mux_2level_size50_51_sram_blwl_out[2489:2489] ,mux_2level_size50_51_sram_blwl_out[2489:2489] ,mux_2level_size50_51_sram_blwl_outb[2489:2489] ,mux_2level_size50_51_configbus0[2489:2489], mux_2level_size50_51_configbus1[2489:2489] , mux_2level_size50_51_configbus0_b[2489:2489] ); -sram6T_blwl sram_blwl_2490_ (mux_2level_size50_51_sram_blwl_out[2490:2490] ,mux_2level_size50_51_sram_blwl_out[2490:2490] ,mux_2level_size50_51_sram_blwl_outb[2490:2490] ,mux_2level_size50_51_configbus0[2490:2490], mux_2level_size50_51_configbus1[2490:2490] , mux_2level_size50_51_configbus0_b[2490:2490] ); -sram6T_blwl sram_blwl_2491_ (mux_2level_size50_51_sram_blwl_out[2491:2491] ,mux_2level_size50_51_sram_blwl_out[2491:2491] ,mux_2level_size50_51_sram_blwl_outb[2491:2491] ,mux_2level_size50_51_configbus0[2491:2491], mux_2level_size50_51_configbus1[2491:2491] , mux_2level_size50_51_configbus0_b[2491:2491] ); -sram6T_blwl sram_blwl_2492_ (mux_2level_size50_51_sram_blwl_out[2492:2492] ,mux_2level_size50_51_sram_blwl_out[2492:2492] ,mux_2level_size50_51_sram_blwl_outb[2492:2492] ,mux_2level_size50_51_configbus0[2492:2492], mux_2level_size50_51_configbus1[2492:2492] , mux_2level_size50_51_configbus0_b[2492:2492] ); -sram6T_blwl sram_blwl_2493_ (mux_2level_size50_51_sram_blwl_out[2493:2493] ,mux_2level_size50_51_sram_blwl_out[2493:2493] ,mux_2level_size50_51_sram_blwl_outb[2493:2493] ,mux_2level_size50_51_configbus0[2493:2493], mux_2level_size50_51_configbus1[2493:2493] , mux_2level_size50_51_configbus0_b[2493:2493] ); -sram6T_blwl sram_blwl_2494_ (mux_2level_size50_51_sram_blwl_out[2494:2494] ,mux_2level_size50_51_sram_blwl_out[2494:2494] ,mux_2level_size50_51_sram_blwl_outb[2494:2494] ,mux_2level_size50_51_configbus0[2494:2494], mux_2level_size50_51_configbus1[2494:2494] , mux_2level_size50_51_configbus0_b[2494:2494] ); -sram6T_blwl sram_blwl_2495_ (mux_2level_size50_51_sram_blwl_out[2495:2495] ,mux_2level_size50_51_sram_blwl_out[2495:2495] ,mux_2level_size50_51_sram_blwl_outb[2495:2495] ,mux_2level_size50_51_configbus0[2495:2495], mux_2level_size50_51_configbus1[2495:2495] , mux_2level_size50_51_configbus0_b[2495:2495] ); -sram6T_blwl sram_blwl_2496_ (mux_2level_size50_51_sram_blwl_out[2496:2496] ,mux_2level_size50_51_sram_blwl_out[2496:2496] ,mux_2level_size50_51_sram_blwl_outb[2496:2496] ,mux_2level_size50_51_configbus0[2496:2496], mux_2level_size50_51_configbus1[2496:2496] , mux_2level_size50_51_configbus0_b[2496:2496] ); -sram6T_blwl sram_blwl_2497_ (mux_2level_size50_51_sram_blwl_out[2497:2497] ,mux_2level_size50_51_sram_blwl_out[2497:2497] ,mux_2level_size50_51_sram_blwl_outb[2497:2497] ,mux_2level_size50_51_configbus0[2497:2497], mux_2level_size50_51_configbus1[2497:2497] , mux_2level_size50_51_configbus0_b[2497:2497] ); -wire [0:49] in_bus_mux_2level_size50_52_ ; -assign in_bus_mux_2level_size50_52_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_52_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_52_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_52_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_52_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_52_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_52_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_52_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_52_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_52_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_52_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_52_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_52_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_52_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_52_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_52_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_52_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_52_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_52_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_52_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_52_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_52_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_52_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_52_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_52_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_52_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_52_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_52_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_52_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_52_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_52_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_52_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_52_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_52_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_52_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_52_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_52_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_52_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_52_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_52_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_52_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_52_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_52_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_52_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_52_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_52_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_52_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_52_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_52_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_52_[49] = fle_9___out_0_ ; -wire [2498:2513] mux_2level_size50_52_configbus0; -wire [2498:2513] mux_2level_size50_52_configbus1; -wire [2498:2513] mux_2level_size50_52_sram_blwl_out ; -wire [2498:2513] mux_2level_size50_52_sram_blwl_outb ; -assign mux_2level_size50_52_configbus0[2498:2513] = sram_blwl_bl[2498:2513] ; -assign mux_2level_size50_52_configbus1[2498:2513] = sram_blwl_wl[2498:2513] ; -wire [2498:2513] mux_2level_size50_52_configbus0_b; -assign mux_2level_size50_52_configbus0_b[2498:2513] = sram_blwl_blb[2498:2513] ; -mux_2level_size50 mux_2level_size50_52_ (in_bus_mux_2level_size50_52_, fle_8___in_4_, mux_2level_size50_52_sram_blwl_out[2498:2513] , -mux_2level_size50_52_sram_blwl_outb[2498:2513] ); -//----- SRAM bits for MUX[52], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2498_ (mux_2level_size50_52_sram_blwl_out[2498:2498] ,mux_2level_size50_52_sram_blwl_out[2498:2498] ,mux_2level_size50_52_sram_blwl_outb[2498:2498] ,mux_2level_size50_52_configbus0[2498:2498], mux_2level_size50_52_configbus1[2498:2498] , mux_2level_size50_52_configbus0_b[2498:2498] ); -sram6T_blwl sram_blwl_2499_ (mux_2level_size50_52_sram_blwl_out[2499:2499] ,mux_2level_size50_52_sram_blwl_out[2499:2499] ,mux_2level_size50_52_sram_blwl_outb[2499:2499] ,mux_2level_size50_52_configbus0[2499:2499], mux_2level_size50_52_configbus1[2499:2499] , mux_2level_size50_52_configbus0_b[2499:2499] ); -sram6T_blwl sram_blwl_2500_ (mux_2level_size50_52_sram_blwl_out[2500:2500] ,mux_2level_size50_52_sram_blwl_out[2500:2500] ,mux_2level_size50_52_sram_blwl_outb[2500:2500] ,mux_2level_size50_52_configbus0[2500:2500], mux_2level_size50_52_configbus1[2500:2500] , mux_2level_size50_52_configbus0_b[2500:2500] ); -sram6T_blwl sram_blwl_2501_ (mux_2level_size50_52_sram_blwl_out[2501:2501] ,mux_2level_size50_52_sram_blwl_out[2501:2501] ,mux_2level_size50_52_sram_blwl_outb[2501:2501] ,mux_2level_size50_52_configbus0[2501:2501], mux_2level_size50_52_configbus1[2501:2501] , mux_2level_size50_52_configbus0_b[2501:2501] ); -sram6T_blwl sram_blwl_2502_ (mux_2level_size50_52_sram_blwl_out[2502:2502] ,mux_2level_size50_52_sram_blwl_out[2502:2502] ,mux_2level_size50_52_sram_blwl_outb[2502:2502] ,mux_2level_size50_52_configbus0[2502:2502], mux_2level_size50_52_configbus1[2502:2502] , mux_2level_size50_52_configbus0_b[2502:2502] ); -sram6T_blwl sram_blwl_2503_ (mux_2level_size50_52_sram_blwl_out[2503:2503] ,mux_2level_size50_52_sram_blwl_out[2503:2503] ,mux_2level_size50_52_sram_blwl_outb[2503:2503] ,mux_2level_size50_52_configbus0[2503:2503], mux_2level_size50_52_configbus1[2503:2503] , mux_2level_size50_52_configbus0_b[2503:2503] ); -sram6T_blwl sram_blwl_2504_ (mux_2level_size50_52_sram_blwl_out[2504:2504] ,mux_2level_size50_52_sram_blwl_out[2504:2504] ,mux_2level_size50_52_sram_blwl_outb[2504:2504] ,mux_2level_size50_52_configbus0[2504:2504], mux_2level_size50_52_configbus1[2504:2504] , mux_2level_size50_52_configbus0_b[2504:2504] ); -sram6T_blwl sram_blwl_2505_ (mux_2level_size50_52_sram_blwl_out[2505:2505] ,mux_2level_size50_52_sram_blwl_out[2505:2505] ,mux_2level_size50_52_sram_blwl_outb[2505:2505] ,mux_2level_size50_52_configbus0[2505:2505], mux_2level_size50_52_configbus1[2505:2505] , mux_2level_size50_52_configbus0_b[2505:2505] ); -sram6T_blwl sram_blwl_2506_ (mux_2level_size50_52_sram_blwl_out[2506:2506] ,mux_2level_size50_52_sram_blwl_out[2506:2506] ,mux_2level_size50_52_sram_blwl_outb[2506:2506] ,mux_2level_size50_52_configbus0[2506:2506], mux_2level_size50_52_configbus1[2506:2506] , mux_2level_size50_52_configbus0_b[2506:2506] ); -sram6T_blwl sram_blwl_2507_ (mux_2level_size50_52_sram_blwl_out[2507:2507] ,mux_2level_size50_52_sram_blwl_out[2507:2507] ,mux_2level_size50_52_sram_blwl_outb[2507:2507] ,mux_2level_size50_52_configbus0[2507:2507], mux_2level_size50_52_configbus1[2507:2507] , mux_2level_size50_52_configbus0_b[2507:2507] ); -sram6T_blwl sram_blwl_2508_ (mux_2level_size50_52_sram_blwl_out[2508:2508] ,mux_2level_size50_52_sram_blwl_out[2508:2508] ,mux_2level_size50_52_sram_blwl_outb[2508:2508] ,mux_2level_size50_52_configbus0[2508:2508], mux_2level_size50_52_configbus1[2508:2508] , mux_2level_size50_52_configbus0_b[2508:2508] ); -sram6T_blwl sram_blwl_2509_ (mux_2level_size50_52_sram_blwl_out[2509:2509] ,mux_2level_size50_52_sram_blwl_out[2509:2509] ,mux_2level_size50_52_sram_blwl_outb[2509:2509] ,mux_2level_size50_52_configbus0[2509:2509], mux_2level_size50_52_configbus1[2509:2509] , mux_2level_size50_52_configbus0_b[2509:2509] ); -sram6T_blwl sram_blwl_2510_ (mux_2level_size50_52_sram_blwl_out[2510:2510] ,mux_2level_size50_52_sram_blwl_out[2510:2510] ,mux_2level_size50_52_sram_blwl_outb[2510:2510] ,mux_2level_size50_52_configbus0[2510:2510], mux_2level_size50_52_configbus1[2510:2510] , mux_2level_size50_52_configbus0_b[2510:2510] ); -sram6T_blwl sram_blwl_2511_ (mux_2level_size50_52_sram_blwl_out[2511:2511] ,mux_2level_size50_52_sram_blwl_out[2511:2511] ,mux_2level_size50_52_sram_blwl_outb[2511:2511] ,mux_2level_size50_52_configbus0[2511:2511], mux_2level_size50_52_configbus1[2511:2511] , mux_2level_size50_52_configbus0_b[2511:2511] ); -sram6T_blwl sram_blwl_2512_ (mux_2level_size50_52_sram_blwl_out[2512:2512] ,mux_2level_size50_52_sram_blwl_out[2512:2512] ,mux_2level_size50_52_sram_blwl_outb[2512:2512] ,mux_2level_size50_52_configbus0[2512:2512], mux_2level_size50_52_configbus1[2512:2512] , mux_2level_size50_52_configbus0_b[2512:2512] ); -sram6T_blwl sram_blwl_2513_ (mux_2level_size50_52_sram_blwl_out[2513:2513] ,mux_2level_size50_52_sram_blwl_out[2513:2513] ,mux_2level_size50_52_sram_blwl_outb[2513:2513] ,mux_2level_size50_52_configbus0[2513:2513], mux_2level_size50_52_configbus1[2513:2513] , mux_2level_size50_52_configbus0_b[2513:2513] ); -wire [0:49] in_bus_mux_2level_size50_53_ ; -assign in_bus_mux_2level_size50_53_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_53_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_53_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_53_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_53_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_53_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_53_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_53_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_53_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_53_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_53_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_53_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_53_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_53_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_53_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_53_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_53_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_53_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_53_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_53_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_53_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_53_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_53_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_53_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_53_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_53_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_53_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_53_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_53_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_53_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_53_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_53_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_53_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_53_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_53_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_53_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_53_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_53_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_53_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_53_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_53_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_53_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_53_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_53_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_53_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_53_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_53_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_53_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_53_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_53_[49] = fle_9___out_0_ ; -wire [2514:2529] mux_2level_size50_53_configbus0; -wire [2514:2529] mux_2level_size50_53_configbus1; -wire [2514:2529] mux_2level_size50_53_sram_blwl_out ; -wire [2514:2529] mux_2level_size50_53_sram_blwl_outb ; -assign mux_2level_size50_53_configbus0[2514:2529] = sram_blwl_bl[2514:2529] ; -assign mux_2level_size50_53_configbus1[2514:2529] = sram_blwl_wl[2514:2529] ; -wire [2514:2529] mux_2level_size50_53_configbus0_b; -assign mux_2level_size50_53_configbus0_b[2514:2529] = sram_blwl_blb[2514:2529] ; -mux_2level_size50 mux_2level_size50_53_ (in_bus_mux_2level_size50_53_, fle_8___in_5_, mux_2level_size50_53_sram_blwl_out[2514:2529] , -mux_2level_size50_53_sram_blwl_outb[2514:2529] ); -//----- SRAM bits for MUX[53], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2514_ (mux_2level_size50_53_sram_blwl_out[2514:2514] ,mux_2level_size50_53_sram_blwl_out[2514:2514] ,mux_2level_size50_53_sram_blwl_outb[2514:2514] ,mux_2level_size50_53_configbus0[2514:2514], mux_2level_size50_53_configbus1[2514:2514] , mux_2level_size50_53_configbus0_b[2514:2514] ); -sram6T_blwl sram_blwl_2515_ (mux_2level_size50_53_sram_blwl_out[2515:2515] ,mux_2level_size50_53_sram_blwl_out[2515:2515] ,mux_2level_size50_53_sram_blwl_outb[2515:2515] ,mux_2level_size50_53_configbus0[2515:2515], mux_2level_size50_53_configbus1[2515:2515] , mux_2level_size50_53_configbus0_b[2515:2515] ); -sram6T_blwl sram_blwl_2516_ (mux_2level_size50_53_sram_blwl_out[2516:2516] ,mux_2level_size50_53_sram_blwl_out[2516:2516] ,mux_2level_size50_53_sram_blwl_outb[2516:2516] ,mux_2level_size50_53_configbus0[2516:2516], mux_2level_size50_53_configbus1[2516:2516] , mux_2level_size50_53_configbus0_b[2516:2516] ); -sram6T_blwl sram_blwl_2517_ (mux_2level_size50_53_sram_blwl_out[2517:2517] ,mux_2level_size50_53_sram_blwl_out[2517:2517] ,mux_2level_size50_53_sram_blwl_outb[2517:2517] ,mux_2level_size50_53_configbus0[2517:2517], mux_2level_size50_53_configbus1[2517:2517] , mux_2level_size50_53_configbus0_b[2517:2517] ); -sram6T_blwl sram_blwl_2518_ (mux_2level_size50_53_sram_blwl_out[2518:2518] ,mux_2level_size50_53_sram_blwl_out[2518:2518] ,mux_2level_size50_53_sram_blwl_outb[2518:2518] ,mux_2level_size50_53_configbus0[2518:2518], mux_2level_size50_53_configbus1[2518:2518] , mux_2level_size50_53_configbus0_b[2518:2518] ); -sram6T_blwl sram_blwl_2519_ (mux_2level_size50_53_sram_blwl_out[2519:2519] ,mux_2level_size50_53_sram_blwl_out[2519:2519] ,mux_2level_size50_53_sram_blwl_outb[2519:2519] ,mux_2level_size50_53_configbus0[2519:2519], mux_2level_size50_53_configbus1[2519:2519] , mux_2level_size50_53_configbus0_b[2519:2519] ); -sram6T_blwl sram_blwl_2520_ (mux_2level_size50_53_sram_blwl_out[2520:2520] ,mux_2level_size50_53_sram_blwl_out[2520:2520] ,mux_2level_size50_53_sram_blwl_outb[2520:2520] ,mux_2level_size50_53_configbus0[2520:2520], mux_2level_size50_53_configbus1[2520:2520] , mux_2level_size50_53_configbus0_b[2520:2520] ); -sram6T_blwl sram_blwl_2521_ (mux_2level_size50_53_sram_blwl_out[2521:2521] ,mux_2level_size50_53_sram_blwl_out[2521:2521] ,mux_2level_size50_53_sram_blwl_outb[2521:2521] ,mux_2level_size50_53_configbus0[2521:2521], mux_2level_size50_53_configbus1[2521:2521] , mux_2level_size50_53_configbus0_b[2521:2521] ); -sram6T_blwl sram_blwl_2522_ (mux_2level_size50_53_sram_blwl_out[2522:2522] ,mux_2level_size50_53_sram_blwl_out[2522:2522] ,mux_2level_size50_53_sram_blwl_outb[2522:2522] ,mux_2level_size50_53_configbus0[2522:2522], mux_2level_size50_53_configbus1[2522:2522] , mux_2level_size50_53_configbus0_b[2522:2522] ); -sram6T_blwl sram_blwl_2523_ (mux_2level_size50_53_sram_blwl_out[2523:2523] ,mux_2level_size50_53_sram_blwl_out[2523:2523] ,mux_2level_size50_53_sram_blwl_outb[2523:2523] ,mux_2level_size50_53_configbus0[2523:2523], mux_2level_size50_53_configbus1[2523:2523] , mux_2level_size50_53_configbus0_b[2523:2523] ); -sram6T_blwl sram_blwl_2524_ (mux_2level_size50_53_sram_blwl_out[2524:2524] ,mux_2level_size50_53_sram_blwl_out[2524:2524] ,mux_2level_size50_53_sram_blwl_outb[2524:2524] ,mux_2level_size50_53_configbus0[2524:2524], mux_2level_size50_53_configbus1[2524:2524] , mux_2level_size50_53_configbus0_b[2524:2524] ); -sram6T_blwl sram_blwl_2525_ (mux_2level_size50_53_sram_blwl_out[2525:2525] ,mux_2level_size50_53_sram_blwl_out[2525:2525] ,mux_2level_size50_53_sram_blwl_outb[2525:2525] ,mux_2level_size50_53_configbus0[2525:2525], mux_2level_size50_53_configbus1[2525:2525] , mux_2level_size50_53_configbus0_b[2525:2525] ); -sram6T_blwl sram_blwl_2526_ (mux_2level_size50_53_sram_blwl_out[2526:2526] ,mux_2level_size50_53_sram_blwl_out[2526:2526] ,mux_2level_size50_53_sram_blwl_outb[2526:2526] ,mux_2level_size50_53_configbus0[2526:2526], mux_2level_size50_53_configbus1[2526:2526] , mux_2level_size50_53_configbus0_b[2526:2526] ); -sram6T_blwl sram_blwl_2527_ (mux_2level_size50_53_sram_blwl_out[2527:2527] ,mux_2level_size50_53_sram_blwl_out[2527:2527] ,mux_2level_size50_53_sram_blwl_outb[2527:2527] ,mux_2level_size50_53_configbus0[2527:2527], mux_2level_size50_53_configbus1[2527:2527] , mux_2level_size50_53_configbus0_b[2527:2527] ); -sram6T_blwl sram_blwl_2528_ (mux_2level_size50_53_sram_blwl_out[2528:2528] ,mux_2level_size50_53_sram_blwl_out[2528:2528] ,mux_2level_size50_53_sram_blwl_outb[2528:2528] ,mux_2level_size50_53_configbus0[2528:2528], mux_2level_size50_53_configbus1[2528:2528] , mux_2level_size50_53_configbus0_b[2528:2528] ); -sram6T_blwl sram_blwl_2529_ (mux_2level_size50_53_sram_blwl_out[2529:2529] ,mux_2level_size50_53_sram_blwl_out[2529:2529] ,mux_2level_size50_53_sram_blwl_outb[2529:2529] ,mux_2level_size50_53_configbus0[2529:2529], mux_2level_size50_53_configbus1[2529:2529] , mux_2level_size50_53_configbus0_b[2529:2529] ); -direct_interc direct_interc_178_ (mode_clb___clk_0_, fle_8___clk_0_ ); -wire [0:49] in_bus_mux_2level_size50_54_ ; -assign in_bus_mux_2level_size50_54_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_54_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_54_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_54_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_54_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_54_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_54_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_54_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_54_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_54_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_54_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_54_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_54_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_54_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_54_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_54_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_54_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_54_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_54_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_54_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_54_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_54_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_54_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_54_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_54_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_54_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_54_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_54_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_54_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_54_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_54_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_54_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_54_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_54_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_54_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_54_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_54_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_54_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_54_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_54_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_54_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_54_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_54_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_54_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_54_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_54_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_54_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_54_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_54_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_54_[49] = fle_9___out_0_ ; -wire [2530:2545] mux_2level_size50_54_configbus0; -wire [2530:2545] mux_2level_size50_54_configbus1; -wire [2530:2545] mux_2level_size50_54_sram_blwl_out ; -wire [2530:2545] mux_2level_size50_54_sram_blwl_outb ; -assign mux_2level_size50_54_configbus0[2530:2545] = sram_blwl_bl[2530:2545] ; -assign mux_2level_size50_54_configbus1[2530:2545] = sram_blwl_wl[2530:2545] ; -wire [2530:2545] mux_2level_size50_54_configbus0_b; -assign mux_2level_size50_54_configbus0_b[2530:2545] = sram_blwl_blb[2530:2545] ; -mux_2level_size50 mux_2level_size50_54_ (in_bus_mux_2level_size50_54_, fle_9___in_0_, mux_2level_size50_54_sram_blwl_out[2530:2545] , -mux_2level_size50_54_sram_blwl_outb[2530:2545] ); -//----- SRAM bits for MUX[54], level=2, select_path_id=22. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----0010000000000010----- -sram6T_blwl sram_blwl_2530_ (mux_2level_size50_54_sram_blwl_out[2530:2530] ,mux_2level_size50_54_sram_blwl_out[2530:2530] ,mux_2level_size50_54_sram_blwl_outb[2530:2530] ,mux_2level_size50_54_configbus0[2530:2530], mux_2level_size50_54_configbus1[2530:2530] , mux_2level_size50_54_configbus0_b[2530:2530] ); -sram6T_blwl sram_blwl_2531_ (mux_2level_size50_54_sram_blwl_out[2531:2531] ,mux_2level_size50_54_sram_blwl_out[2531:2531] ,mux_2level_size50_54_sram_blwl_outb[2531:2531] ,mux_2level_size50_54_configbus0[2531:2531], mux_2level_size50_54_configbus1[2531:2531] , mux_2level_size50_54_configbus0_b[2531:2531] ); -sram6T_blwl sram_blwl_2532_ (mux_2level_size50_54_sram_blwl_out[2532:2532] ,mux_2level_size50_54_sram_blwl_out[2532:2532] ,mux_2level_size50_54_sram_blwl_outb[2532:2532] ,mux_2level_size50_54_configbus0[2532:2532], mux_2level_size50_54_configbus1[2532:2532] , mux_2level_size50_54_configbus0_b[2532:2532] ); -sram6T_blwl sram_blwl_2533_ (mux_2level_size50_54_sram_blwl_out[2533:2533] ,mux_2level_size50_54_sram_blwl_out[2533:2533] ,mux_2level_size50_54_sram_blwl_outb[2533:2533] ,mux_2level_size50_54_configbus0[2533:2533], mux_2level_size50_54_configbus1[2533:2533] , mux_2level_size50_54_configbus0_b[2533:2533] ); -sram6T_blwl sram_blwl_2534_ (mux_2level_size50_54_sram_blwl_out[2534:2534] ,mux_2level_size50_54_sram_blwl_out[2534:2534] ,mux_2level_size50_54_sram_blwl_outb[2534:2534] ,mux_2level_size50_54_configbus0[2534:2534], mux_2level_size50_54_configbus1[2534:2534] , mux_2level_size50_54_configbus0_b[2534:2534] ); -sram6T_blwl sram_blwl_2535_ (mux_2level_size50_54_sram_blwl_out[2535:2535] ,mux_2level_size50_54_sram_blwl_out[2535:2535] ,mux_2level_size50_54_sram_blwl_outb[2535:2535] ,mux_2level_size50_54_configbus0[2535:2535], mux_2level_size50_54_configbus1[2535:2535] , mux_2level_size50_54_configbus0_b[2535:2535] ); -sram6T_blwl sram_blwl_2536_ (mux_2level_size50_54_sram_blwl_out[2536:2536] ,mux_2level_size50_54_sram_blwl_out[2536:2536] ,mux_2level_size50_54_sram_blwl_outb[2536:2536] ,mux_2level_size50_54_configbus0[2536:2536], mux_2level_size50_54_configbus1[2536:2536] , mux_2level_size50_54_configbus0_b[2536:2536] ); -sram6T_blwl sram_blwl_2537_ (mux_2level_size50_54_sram_blwl_out[2537:2537] ,mux_2level_size50_54_sram_blwl_out[2537:2537] ,mux_2level_size50_54_sram_blwl_outb[2537:2537] ,mux_2level_size50_54_configbus0[2537:2537], mux_2level_size50_54_configbus1[2537:2537] , mux_2level_size50_54_configbus0_b[2537:2537] ); -sram6T_blwl sram_blwl_2538_ (mux_2level_size50_54_sram_blwl_out[2538:2538] ,mux_2level_size50_54_sram_blwl_out[2538:2538] ,mux_2level_size50_54_sram_blwl_outb[2538:2538] ,mux_2level_size50_54_configbus0[2538:2538], mux_2level_size50_54_configbus1[2538:2538] , mux_2level_size50_54_configbus0_b[2538:2538] ); -sram6T_blwl sram_blwl_2539_ (mux_2level_size50_54_sram_blwl_out[2539:2539] ,mux_2level_size50_54_sram_blwl_out[2539:2539] ,mux_2level_size50_54_sram_blwl_outb[2539:2539] ,mux_2level_size50_54_configbus0[2539:2539], mux_2level_size50_54_configbus1[2539:2539] , mux_2level_size50_54_configbus0_b[2539:2539] ); -sram6T_blwl sram_blwl_2540_ (mux_2level_size50_54_sram_blwl_out[2540:2540] ,mux_2level_size50_54_sram_blwl_out[2540:2540] ,mux_2level_size50_54_sram_blwl_outb[2540:2540] ,mux_2level_size50_54_configbus0[2540:2540], mux_2level_size50_54_configbus1[2540:2540] , mux_2level_size50_54_configbus0_b[2540:2540] ); -sram6T_blwl sram_blwl_2541_ (mux_2level_size50_54_sram_blwl_out[2541:2541] ,mux_2level_size50_54_sram_blwl_out[2541:2541] ,mux_2level_size50_54_sram_blwl_outb[2541:2541] ,mux_2level_size50_54_configbus0[2541:2541], mux_2level_size50_54_configbus1[2541:2541] , mux_2level_size50_54_configbus0_b[2541:2541] ); -sram6T_blwl sram_blwl_2542_ (mux_2level_size50_54_sram_blwl_out[2542:2542] ,mux_2level_size50_54_sram_blwl_out[2542:2542] ,mux_2level_size50_54_sram_blwl_outb[2542:2542] ,mux_2level_size50_54_configbus0[2542:2542], mux_2level_size50_54_configbus1[2542:2542] , mux_2level_size50_54_configbus0_b[2542:2542] ); -sram6T_blwl sram_blwl_2543_ (mux_2level_size50_54_sram_blwl_out[2543:2543] ,mux_2level_size50_54_sram_blwl_out[2543:2543] ,mux_2level_size50_54_sram_blwl_outb[2543:2543] ,mux_2level_size50_54_configbus0[2543:2543], mux_2level_size50_54_configbus1[2543:2543] , mux_2level_size50_54_configbus0_b[2543:2543] ); -sram6T_blwl sram_blwl_2544_ (mux_2level_size50_54_sram_blwl_out[2544:2544] ,mux_2level_size50_54_sram_blwl_out[2544:2544] ,mux_2level_size50_54_sram_blwl_outb[2544:2544] ,mux_2level_size50_54_configbus0[2544:2544], mux_2level_size50_54_configbus1[2544:2544] , mux_2level_size50_54_configbus0_b[2544:2544] ); -sram6T_blwl sram_blwl_2545_ (mux_2level_size50_54_sram_blwl_out[2545:2545] ,mux_2level_size50_54_sram_blwl_out[2545:2545] ,mux_2level_size50_54_sram_blwl_outb[2545:2545] ,mux_2level_size50_54_configbus0[2545:2545], mux_2level_size50_54_configbus1[2545:2545] , mux_2level_size50_54_configbus0_b[2545:2545] ); -wire [0:49] in_bus_mux_2level_size50_55_ ; -assign in_bus_mux_2level_size50_55_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_55_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_55_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_55_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_55_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_55_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_55_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_55_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_55_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_55_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_55_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_55_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_55_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_55_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_55_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_55_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_55_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_55_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_55_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_55_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_55_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_55_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_55_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_55_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_55_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_55_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_55_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_55_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_55_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_55_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_55_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_55_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_55_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_55_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_55_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_55_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_55_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_55_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_55_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_55_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_55_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_55_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_55_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_55_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_55_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_55_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_55_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_55_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_55_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_55_[49] = fle_9___out_0_ ; -wire [2546:2561] mux_2level_size50_55_configbus0; -wire [2546:2561] mux_2level_size50_55_configbus1; -wire [2546:2561] mux_2level_size50_55_sram_blwl_out ; -wire [2546:2561] mux_2level_size50_55_sram_blwl_outb ; -assign mux_2level_size50_55_configbus0[2546:2561] = sram_blwl_bl[2546:2561] ; -assign mux_2level_size50_55_configbus1[2546:2561] = sram_blwl_wl[2546:2561] ; -wire [2546:2561] mux_2level_size50_55_configbus0_b; -assign mux_2level_size50_55_configbus0_b[2546:2561] = sram_blwl_blb[2546:2561] ; -mux_2level_size50 mux_2level_size50_55_ (in_bus_mux_2level_size50_55_, fle_9___in_1_, mux_2level_size50_55_sram_blwl_out[2546:2561] , -mux_2level_size50_55_sram_blwl_outb[2546:2561] ); -//----- SRAM bits for MUX[55], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2546_ (mux_2level_size50_55_sram_blwl_out[2546:2546] ,mux_2level_size50_55_sram_blwl_out[2546:2546] ,mux_2level_size50_55_sram_blwl_outb[2546:2546] ,mux_2level_size50_55_configbus0[2546:2546], mux_2level_size50_55_configbus1[2546:2546] , mux_2level_size50_55_configbus0_b[2546:2546] ); -sram6T_blwl sram_blwl_2547_ (mux_2level_size50_55_sram_blwl_out[2547:2547] ,mux_2level_size50_55_sram_blwl_out[2547:2547] ,mux_2level_size50_55_sram_blwl_outb[2547:2547] ,mux_2level_size50_55_configbus0[2547:2547], mux_2level_size50_55_configbus1[2547:2547] , mux_2level_size50_55_configbus0_b[2547:2547] ); -sram6T_blwl sram_blwl_2548_ (mux_2level_size50_55_sram_blwl_out[2548:2548] ,mux_2level_size50_55_sram_blwl_out[2548:2548] ,mux_2level_size50_55_sram_blwl_outb[2548:2548] ,mux_2level_size50_55_configbus0[2548:2548], mux_2level_size50_55_configbus1[2548:2548] , mux_2level_size50_55_configbus0_b[2548:2548] ); -sram6T_blwl sram_blwl_2549_ (mux_2level_size50_55_sram_blwl_out[2549:2549] ,mux_2level_size50_55_sram_blwl_out[2549:2549] ,mux_2level_size50_55_sram_blwl_outb[2549:2549] ,mux_2level_size50_55_configbus0[2549:2549], mux_2level_size50_55_configbus1[2549:2549] , mux_2level_size50_55_configbus0_b[2549:2549] ); -sram6T_blwl sram_blwl_2550_ (mux_2level_size50_55_sram_blwl_out[2550:2550] ,mux_2level_size50_55_sram_blwl_out[2550:2550] ,mux_2level_size50_55_sram_blwl_outb[2550:2550] ,mux_2level_size50_55_configbus0[2550:2550], mux_2level_size50_55_configbus1[2550:2550] , mux_2level_size50_55_configbus0_b[2550:2550] ); -sram6T_blwl sram_blwl_2551_ (mux_2level_size50_55_sram_blwl_out[2551:2551] ,mux_2level_size50_55_sram_blwl_out[2551:2551] ,mux_2level_size50_55_sram_blwl_outb[2551:2551] ,mux_2level_size50_55_configbus0[2551:2551], mux_2level_size50_55_configbus1[2551:2551] , mux_2level_size50_55_configbus0_b[2551:2551] ); -sram6T_blwl sram_blwl_2552_ (mux_2level_size50_55_sram_blwl_out[2552:2552] ,mux_2level_size50_55_sram_blwl_out[2552:2552] ,mux_2level_size50_55_sram_blwl_outb[2552:2552] ,mux_2level_size50_55_configbus0[2552:2552], mux_2level_size50_55_configbus1[2552:2552] , mux_2level_size50_55_configbus0_b[2552:2552] ); -sram6T_blwl sram_blwl_2553_ (mux_2level_size50_55_sram_blwl_out[2553:2553] ,mux_2level_size50_55_sram_blwl_out[2553:2553] ,mux_2level_size50_55_sram_blwl_outb[2553:2553] ,mux_2level_size50_55_configbus0[2553:2553], mux_2level_size50_55_configbus1[2553:2553] , mux_2level_size50_55_configbus0_b[2553:2553] ); -sram6T_blwl sram_blwl_2554_ (mux_2level_size50_55_sram_blwl_out[2554:2554] ,mux_2level_size50_55_sram_blwl_out[2554:2554] ,mux_2level_size50_55_sram_blwl_outb[2554:2554] ,mux_2level_size50_55_configbus0[2554:2554], mux_2level_size50_55_configbus1[2554:2554] , mux_2level_size50_55_configbus0_b[2554:2554] ); -sram6T_blwl sram_blwl_2555_ (mux_2level_size50_55_sram_blwl_out[2555:2555] ,mux_2level_size50_55_sram_blwl_out[2555:2555] ,mux_2level_size50_55_sram_blwl_outb[2555:2555] ,mux_2level_size50_55_configbus0[2555:2555], mux_2level_size50_55_configbus1[2555:2555] , mux_2level_size50_55_configbus0_b[2555:2555] ); -sram6T_blwl sram_blwl_2556_ (mux_2level_size50_55_sram_blwl_out[2556:2556] ,mux_2level_size50_55_sram_blwl_out[2556:2556] ,mux_2level_size50_55_sram_blwl_outb[2556:2556] ,mux_2level_size50_55_configbus0[2556:2556], mux_2level_size50_55_configbus1[2556:2556] , mux_2level_size50_55_configbus0_b[2556:2556] ); -sram6T_blwl sram_blwl_2557_ (mux_2level_size50_55_sram_blwl_out[2557:2557] ,mux_2level_size50_55_sram_blwl_out[2557:2557] ,mux_2level_size50_55_sram_blwl_outb[2557:2557] ,mux_2level_size50_55_configbus0[2557:2557], mux_2level_size50_55_configbus1[2557:2557] , mux_2level_size50_55_configbus0_b[2557:2557] ); -sram6T_blwl sram_blwl_2558_ (mux_2level_size50_55_sram_blwl_out[2558:2558] ,mux_2level_size50_55_sram_blwl_out[2558:2558] ,mux_2level_size50_55_sram_blwl_outb[2558:2558] ,mux_2level_size50_55_configbus0[2558:2558], mux_2level_size50_55_configbus1[2558:2558] , mux_2level_size50_55_configbus0_b[2558:2558] ); -sram6T_blwl sram_blwl_2559_ (mux_2level_size50_55_sram_blwl_out[2559:2559] ,mux_2level_size50_55_sram_blwl_out[2559:2559] ,mux_2level_size50_55_sram_blwl_outb[2559:2559] ,mux_2level_size50_55_configbus0[2559:2559], mux_2level_size50_55_configbus1[2559:2559] , mux_2level_size50_55_configbus0_b[2559:2559] ); -sram6T_blwl sram_blwl_2560_ (mux_2level_size50_55_sram_blwl_out[2560:2560] ,mux_2level_size50_55_sram_blwl_out[2560:2560] ,mux_2level_size50_55_sram_blwl_outb[2560:2560] ,mux_2level_size50_55_configbus0[2560:2560], mux_2level_size50_55_configbus1[2560:2560] , mux_2level_size50_55_configbus0_b[2560:2560] ); -sram6T_blwl sram_blwl_2561_ (mux_2level_size50_55_sram_blwl_out[2561:2561] ,mux_2level_size50_55_sram_blwl_out[2561:2561] ,mux_2level_size50_55_sram_blwl_outb[2561:2561] ,mux_2level_size50_55_configbus0[2561:2561], mux_2level_size50_55_configbus1[2561:2561] , mux_2level_size50_55_configbus0_b[2561:2561] ); -wire [0:49] in_bus_mux_2level_size50_56_ ; -assign in_bus_mux_2level_size50_56_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_56_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_56_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_56_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_56_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_56_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_56_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_56_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_56_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_56_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_56_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_56_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_56_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_56_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_56_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_56_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_56_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_56_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_56_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_56_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_56_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_56_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_56_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_56_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_56_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_56_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_56_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_56_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_56_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_56_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_56_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_56_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_56_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_56_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_56_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_56_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_56_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_56_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_56_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_56_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_56_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_56_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_56_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_56_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_56_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_56_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_56_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_56_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_56_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_56_[49] = fle_9___out_0_ ; -wire [2562:2577] mux_2level_size50_56_configbus0; -wire [2562:2577] mux_2level_size50_56_configbus1; -wire [2562:2577] mux_2level_size50_56_sram_blwl_out ; -wire [2562:2577] mux_2level_size50_56_sram_blwl_outb ; -assign mux_2level_size50_56_configbus0[2562:2577] = sram_blwl_bl[2562:2577] ; -assign mux_2level_size50_56_configbus1[2562:2577] = sram_blwl_wl[2562:2577] ; -wire [2562:2577] mux_2level_size50_56_configbus0_b; -assign mux_2level_size50_56_configbus0_b[2562:2577] = sram_blwl_blb[2562:2577] ; -mux_2level_size50 mux_2level_size50_56_ (in_bus_mux_2level_size50_56_, fle_9___in_2_, mux_2level_size50_56_sram_blwl_out[2562:2577] , -mux_2level_size50_56_sram_blwl_outb[2562:2577] ); -//----- SRAM bits for MUX[56], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2562_ (mux_2level_size50_56_sram_blwl_out[2562:2562] ,mux_2level_size50_56_sram_blwl_out[2562:2562] ,mux_2level_size50_56_sram_blwl_outb[2562:2562] ,mux_2level_size50_56_configbus0[2562:2562], mux_2level_size50_56_configbus1[2562:2562] , mux_2level_size50_56_configbus0_b[2562:2562] ); -sram6T_blwl sram_blwl_2563_ (mux_2level_size50_56_sram_blwl_out[2563:2563] ,mux_2level_size50_56_sram_blwl_out[2563:2563] ,mux_2level_size50_56_sram_blwl_outb[2563:2563] ,mux_2level_size50_56_configbus0[2563:2563], mux_2level_size50_56_configbus1[2563:2563] , mux_2level_size50_56_configbus0_b[2563:2563] ); -sram6T_blwl sram_blwl_2564_ (mux_2level_size50_56_sram_blwl_out[2564:2564] ,mux_2level_size50_56_sram_blwl_out[2564:2564] ,mux_2level_size50_56_sram_blwl_outb[2564:2564] ,mux_2level_size50_56_configbus0[2564:2564], mux_2level_size50_56_configbus1[2564:2564] , mux_2level_size50_56_configbus0_b[2564:2564] ); -sram6T_blwl sram_blwl_2565_ (mux_2level_size50_56_sram_blwl_out[2565:2565] ,mux_2level_size50_56_sram_blwl_out[2565:2565] ,mux_2level_size50_56_sram_blwl_outb[2565:2565] ,mux_2level_size50_56_configbus0[2565:2565], mux_2level_size50_56_configbus1[2565:2565] , mux_2level_size50_56_configbus0_b[2565:2565] ); -sram6T_blwl sram_blwl_2566_ (mux_2level_size50_56_sram_blwl_out[2566:2566] ,mux_2level_size50_56_sram_blwl_out[2566:2566] ,mux_2level_size50_56_sram_blwl_outb[2566:2566] ,mux_2level_size50_56_configbus0[2566:2566], mux_2level_size50_56_configbus1[2566:2566] , mux_2level_size50_56_configbus0_b[2566:2566] ); -sram6T_blwl sram_blwl_2567_ (mux_2level_size50_56_sram_blwl_out[2567:2567] ,mux_2level_size50_56_sram_blwl_out[2567:2567] ,mux_2level_size50_56_sram_blwl_outb[2567:2567] ,mux_2level_size50_56_configbus0[2567:2567], mux_2level_size50_56_configbus1[2567:2567] , mux_2level_size50_56_configbus0_b[2567:2567] ); -sram6T_blwl sram_blwl_2568_ (mux_2level_size50_56_sram_blwl_out[2568:2568] ,mux_2level_size50_56_sram_blwl_out[2568:2568] ,mux_2level_size50_56_sram_blwl_outb[2568:2568] ,mux_2level_size50_56_configbus0[2568:2568], mux_2level_size50_56_configbus1[2568:2568] , mux_2level_size50_56_configbus0_b[2568:2568] ); -sram6T_blwl sram_blwl_2569_ (mux_2level_size50_56_sram_blwl_out[2569:2569] ,mux_2level_size50_56_sram_blwl_out[2569:2569] ,mux_2level_size50_56_sram_blwl_outb[2569:2569] ,mux_2level_size50_56_configbus0[2569:2569], mux_2level_size50_56_configbus1[2569:2569] , mux_2level_size50_56_configbus0_b[2569:2569] ); -sram6T_blwl sram_blwl_2570_ (mux_2level_size50_56_sram_blwl_out[2570:2570] ,mux_2level_size50_56_sram_blwl_out[2570:2570] ,mux_2level_size50_56_sram_blwl_outb[2570:2570] ,mux_2level_size50_56_configbus0[2570:2570], mux_2level_size50_56_configbus1[2570:2570] , mux_2level_size50_56_configbus0_b[2570:2570] ); -sram6T_blwl sram_blwl_2571_ (mux_2level_size50_56_sram_blwl_out[2571:2571] ,mux_2level_size50_56_sram_blwl_out[2571:2571] ,mux_2level_size50_56_sram_blwl_outb[2571:2571] ,mux_2level_size50_56_configbus0[2571:2571], mux_2level_size50_56_configbus1[2571:2571] , mux_2level_size50_56_configbus0_b[2571:2571] ); -sram6T_blwl sram_blwl_2572_ (mux_2level_size50_56_sram_blwl_out[2572:2572] ,mux_2level_size50_56_sram_blwl_out[2572:2572] ,mux_2level_size50_56_sram_blwl_outb[2572:2572] ,mux_2level_size50_56_configbus0[2572:2572], mux_2level_size50_56_configbus1[2572:2572] , mux_2level_size50_56_configbus0_b[2572:2572] ); -sram6T_blwl sram_blwl_2573_ (mux_2level_size50_56_sram_blwl_out[2573:2573] ,mux_2level_size50_56_sram_blwl_out[2573:2573] ,mux_2level_size50_56_sram_blwl_outb[2573:2573] ,mux_2level_size50_56_configbus0[2573:2573], mux_2level_size50_56_configbus1[2573:2573] , mux_2level_size50_56_configbus0_b[2573:2573] ); -sram6T_blwl sram_blwl_2574_ (mux_2level_size50_56_sram_blwl_out[2574:2574] ,mux_2level_size50_56_sram_blwl_out[2574:2574] ,mux_2level_size50_56_sram_blwl_outb[2574:2574] ,mux_2level_size50_56_configbus0[2574:2574], mux_2level_size50_56_configbus1[2574:2574] , mux_2level_size50_56_configbus0_b[2574:2574] ); -sram6T_blwl sram_blwl_2575_ (mux_2level_size50_56_sram_blwl_out[2575:2575] ,mux_2level_size50_56_sram_blwl_out[2575:2575] ,mux_2level_size50_56_sram_blwl_outb[2575:2575] ,mux_2level_size50_56_configbus0[2575:2575], mux_2level_size50_56_configbus1[2575:2575] , mux_2level_size50_56_configbus0_b[2575:2575] ); -sram6T_blwl sram_blwl_2576_ (mux_2level_size50_56_sram_blwl_out[2576:2576] ,mux_2level_size50_56_sram_blwl_out[2576:2576] ,mux_2level_size50_56_sram_blwl_outb[2576:2576] ,mux_2level_size50_56_configbus0[2576:2576], mux_2level_size50_56_configbus1[2576:2576] , mux_2level_size50_56_configbus0_b[2576:2576] ); -sram6T_blwl sram_blwl_2577_ (mux_2level_size50_56_sram_blwl_out[2577:2577] ,mux_2level_size50_56_sram_blwl_out[2577:2577] ,mux_2level_size50_56_sram_blwl_outb[2577:2577] ,mux_2level_size50_56_configbus0[2577:2577], mux_2level_size50_56_configbus1[2577:2577] , mux_2level_size50_56_configbus0_b[2577:2577] ); -wire [0:49] in_bus_mux_2level_size50_57_ ; -assign in_bus_mux_2level_size50_57_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_57_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_57_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_57_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_57_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_57_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_57_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_57_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_57_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_57_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_57_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_57_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_57_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_57_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_57_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_57_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_57_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_57_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_57_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_57_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_57_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_57_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_57_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_57_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_57_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_57_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_57_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_57_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_57_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_57_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_57_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_57_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_57_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_57_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_57_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_57_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_57_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_57_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_57_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_57_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_57_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_57_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_57_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_57_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_57_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_57_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_57_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_57_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_57_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_57_[49] = fle_9___out_0_ ; -wire [2578:2593] mux_2level_size50_57_configbus0; -wire [2578:2593] mux_2level_size50_57_configbus1; -wire [2578:2593] mux_2level_size50_57_sram_blwl_out ; -wire [2578:2593] mux_2level_size50_57_sram_blwl_outb ; -assign mux_2level_size50_57_configbus0[2578:2593] = sram_blwl_bl[2578:2593] ; -assign mux_2level_size50_57_configbus1[2578:2593] = sram_blwl_wl[2578:2593] ; -wire [2578:2593] mux_2level_size50_57_configbus0_b; -assign mux_2level_size50_57_configbus0_b[2578:2593] = sram_blwl_blb[2578:2593] ; -mux_2level_size50 mux_2level_size50_57_ (in_bus_mux_2level_size50_57_, fle_9___in_3_, mux_2level_size50_57_sram_blwl_out[2578:2593] , -mux_2level_size50_57_sram_blwl_outb[2578:2593] ); -//----- SRAM bits for MUX[57], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2578_ (mux_2level_size50_57_sram_blwl_out[2578:2578] ,mux_2level_size50_57_sram_blwl_out[2578:2578] ,mux_2level_size50_57_sram_blwl_outb[2578:2578] ,mux_2level_size50_57_configbus0[2578:2578], mux_2level_size50_57_configbus1[2578:2578] , mux_2level_size50_57_configbus0_b[2578:2578] ); -sram6T_blwl sram_blwl_2579_ (mux_2level_size50_57_sram_blwl_out[2579:2579] ,mux_2level_size50_57_sram_blwl_out[2579:2579] ,mux_2level_size50_57_sram_blwl_outb[2579:2579] ,mux_2level_size50_57_configbus0[2579:2579], mux_2level_size50_57_configbus1[2579:2579] , mux_2level_size50_57_configbus0_b[2579:2579] ); -sram6T_blwl sram_blwl_2580_ (mux_2level_size50_57_sram_blwl_out[2580:2580] ,mux_2level_size50_57_sram_blwl_out[2580:2580] ,mux_2level_size50_57_sram_blwl_outb[2580:2580] ,mux_2level_size50_57_configbus0[2580:2580], mux_2level_size50_57_configbus1[2580:2580] , mux_2level_size50_57_configbus0_b[2580:2580] ); -sram6T_blwl sram_blwl_2581_ (mux_2level_size50_57_sram_blwl_out[2581:2581] ,mux_2level_size50_57_sram_blwl_out[2581:2581] ,mux_2level_size50_57_sram_blwl_outb[2581:2581] ,mux_2level_size50_57_configbus0[2581:2581], mux_2level_size50_57_configbus1[2581:2581] , mux_2level_size50_57_configbus0_b[2581:2581] ); -sram6T_blwl sram_blwl_2582_ (mux_2level_size50_57_sram_blwl_out[2582:2582] ,mux_2level_size50_57_sram_blwl_out[2582:2582] ,mux_2level_size50_57_sram_blwl_outb[2582:2582] ,mux_2level_size50_57_configbus0[2582:2582], mux_2level_size50_57_configbus1[2582:2582] , mux_2level_size50_57_configbus0_b[2582:2582] ); -sram6T_blwl sram_blwl_2583_ (mux_2level_size50_57_sram_blwl_out[2583:2583] ,mux_2level_size50_57_sram_blwl_out[2583:2583] ,mux_2level_size50_57_sram_blwl_outb[2583:2583] ,mux_2level_size50_57_configbus0[2583:2583], mux_2level_size50_57_configbus1[2583:2583] , mux_2level_size50_57_configbus0_b[2583:2583] ); -sram6T_blwl sram_blwl_2584_ (mux_2level_size50_57_sram_blwl_out[2584:2584] ,mux_2level_size50_57_sram_blwl_out[2584:2584] ,mux_2level_size50_57_sram_blwl_outb[2584:2584] ,mux_2level_size50_57_configbus0[2584:2584], mux_2level_size50_57_configbus1[2584:2584] , mux_2level_size50_57_configbus0_b[2584:2584] ); -sram6T_blwl sram_blwl_2585_ (mux_2level_size50_57_sram_blwl_out[2585:2585] ,mux_2level_size50_57_sram_blwl_out[2585:2585] ,mux_2level_size50_57_sram_blwl_outb[2585:2585] ,mux_2level_size50_57_configbus0[2585:2585], mux_2level_size50_57_configbus1[2585:2585] , mux_2level_size50_57_configbus0_b[2585:2585] ); -sram6T_blwl sram_blwl_2586_ (mux_2level_size50_57_sram_blwl_out[2586:2586] ,mux_2level_size50_57_sram_blwl_out[2586:2586] ,mux_2level_size50_57_sram_blwl_outb[2586:2586] ,mux_2level_size50_57_configbus0[2586:2586], mux_2level_size50_57_configbus1[2586:2586] , mux_2level_size50_57_configbus0_b[2586:2586] ); -sram6T_blwl sram_blwl_2587_ (mux_2level_size50_57_sram_blwl_out[2587:2587] ,mux_2level_size50_57_sram_blwl_out[2587:2587] ,mux_2level_size50_57_sram_blwl_outb[2587:2587] ,mux_2level_size50_57_configbus0[2587:2587], mux_2level_size50_57_configbus1[2587:2587] , mux_2level_size50_57_configbus0_b[2587:2587] ); -sram6T_blwl sram_blwl_2588_ (mux_2level_size50_57_sram_blwl_out[2588:2588] ,mux_2level_size50_57_sram_blwl_out[2588:2588] ,mux_2level_size50_57_sram_blwl_outb[2588:2588] ,mux_2level_size50_57_configbus0[2588:2588], mux_2level_size50_57_configbus1[2588:2588] , mux_2level_size50_57_configbus0_b[2588:2588] ); -sram6T_blwl sram_blwl_2589_ (mux_2level_size50_57_sram_blwl_out[2589:2589] ,mux_2level_size50_57_sram_blwl_out[2589:2589] ,mux_2level_size50_57_sram_blwl_outb[2589:2589] ,mux_2level_size50_57_configbus0[2589:2589], mux_2level_size50_57_configbus1[2589:2589] , mux_2level_size50_57_configbus0_b[2589:2589] ); -sram6T_blwl sram_blwl_2590_ (mux_2level_size50_57_sram_blwl_out[2590:2590] ,mux_2level_size50_57_sram_blwl_out[2590:2590] ,mux_2level_size50_57_sram_blwl_outb[2590:2590] ,mux_2level_size50_57_configbus0[2590:2590], mux_2level_size50_57_configbus1[2590:2590] , mux_2level_size50_57_configbus0_b[2590:2590] ); -sram6T_blwl sram_blwl_2591_ (mux_2level_size50_57_sram_blwl_out[2591:2591] ,mux_2level_size50_57_sram_blwl_out[2591:2591] ,mux_2level_size50_57_sram_blwl_outb[2591:2591] ,mux_2level_size50_57_configbus0[2591:2591], mux_2level_size50_57_configbus1[2591:2591] , mux_2level_size50_57_configbus0_b[2591:2591] ); -sram6T_blwl sram_blwl_2592_ (mux_2level_size50_57_sram_blwl_out[2592:2592] ,mux_2level_size50_57_sram_blwl_out[2592:2592] ,mux_2level_size50_57_sram_blwl_outb[2592:2592] ,mux_2level_size50_57_configbus0[2592:2592], mux_2level_size50_57_configbus1[2592:2592] , mux_2level_size50_57_configbus0_b[2592:2592] ); -sram6T_blwl sram_blwl_2593_ (mux_2level_size50_57_sram_blwl_out[2593:2593] ,mux_2level_size50_57_sram_blwl_out[2593:2593] ,mux_2level_size50_57_sram_blwl_outb[2593:2593] ,mux_2level_size50_57_configbus0[2593:2593], mux_2level_size50_57_configbus1[2593:2593] , mux_2level_size50_57_configbus0_b[2593:2593] ); -wire [0:49] in_bus_mux_2level_size50_58_ ; -assign in_bus_mux_2level_size50_58_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_58_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_58_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_58_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_58_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_58_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_58_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_58_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_58_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_58_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_58_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_58_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_58_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_58_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_58_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_58_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_58_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_58_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_58_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_58_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_58_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_58_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_58_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_58_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_58_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_58_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_58_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_58_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_58_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_58_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_58_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_58_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_58_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_58_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_58_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_58_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_58_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_58_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_58_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_58_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_58_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_58_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_58_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_58_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_58_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_58_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_58_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_58_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_58_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_58_[49] = fle_9___out_0_ ; -wire [2594:2609] mux_2level_size50_58_configbus0; -wire [2594:2609] mux_2level_size50_58_configbus1; -wire [2594:2609] mux_2level_size50_58_sram_blwl_out ; -wire [2594:2609] mux_2level_size50_58_sram_blwl_outb ; -assign mux_2level_size50_58_configbus0[2594:2609] = sram_blwl_bl[2594:2609] ; -assign mux_2level_size50_58_configbus1[2594:2609] = sram_blwl_wl[2594:2609] ; -wire [2594:2609] mux_2level_size50_58_configbus0_b; -assign mux_2level_size50_58_configbus0_b[2594:2609] = sram_blwl_blb[2594:2609] ; -mux_2level_size50 mux_2level_size50_58_ (in_bus_mux_2level_size50_58_, fle_9___in_4_, mux_2level_size50_58_sram_blwl_out[2594:2609] , -mux_2level_size50_58_sram_blwl_outb[2594:2609] ); -//----- SRAM bits for MUX[58], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2594_ (mux_2level_size50_58_sram_blwl_out[2594:2594] ,mux_2level_size50_58_sram_blwl_out[2594:2594] ,mux_2level_size50_58_sram_blwl_outb[2594:2594] ,mux_2level_size50_58_configbus0[2594:2594], mux_2level_size50_58_configbus1[2594:2594] , mux_2level_size50_58_configbus0_b[2594:2594] ); -sram6T_blwl sram_blwl_2595_ (mux_2level_size50_58_sram_blwl_out[2595:2595] ,mux_2level_size50_58_sram_blwl_out[2595:2595] ,mux_2level_size50_58_sram_blwl_outb[2595:2595] ,mux_2level_size50_58_configbus0[2595:2595], mux_2level_size50_58_configbus1[2595:2595] , mux_2level_size50_58_configbus0_b[2595:2595] ); -sram6T_blwl sram_blwl_2596_ (mux_2level_size50_58_sram_blwl_out[2596:2596] ,mux_2level_size50_58_sram_blwl_out[2596:2596] ,mux_2level_size50_58_sram_blwl_outb[2596:2596] ,mux_2level_size50_58_configbus0[2596:2596], mux_2level_size50_58_configbus1[2596:2596] , mux_2level_size50_58_configbus0_b[2596:2596] ); -sram6T_blwl sram_blwl_2597_ (mux_2level_size50_58_sram_blwl_out[2597:2597] ,mux_2level_size50_58_sram_blwl_out[2597:2597] ,mux_2level_size50_58_sram_blwl_outb[2597:2597] ,mux_2level_size50_58_configbus0[2597:2597], mux_2level_size50_58_configbus1[2597:2597] , mux_2level_size50_58_configbus0_b[2597:2597] ); -sram6T_blwl sram_blwl_2598_ (mux_2level_size50_58_sram_blwl_out[2598:2598] ,mux_2level_size50_58_sram_blwl_out[2598:2598] ,mux_2level_size50_58_sram_blwl_outb[2598:2598] ,mux_2level_size50_58_configbus0[2598:2598], mux_2level_size50_58_configbus1[2598:2598] , mux_2level_size50_58_configbus0_b[2598:2598] ); -sram6T_blwl sram_blwl_2599_ (mux_2level_size50_58_sram_blwl_out[2599:2599] ,mux_2level_size50_58_sram_blwl_out[2599:2599] ,mux_2level_size50_58_sram_blwl_outb[2599:2599] ,mux_2level_size50_58_configbus0[2599:2599], mux_2level_size50_58_configbus1[2599:2599] , mux_2level_size50_58_configbus0_b[2599:2599] ); -sram6T_blwl sram_blwl_2600_ (mux_2level_size50_58_sram_blwl_out[2600:2600] ,mux_2level_size50_58_sram_blwl_out[2600:2600] ,mux_2level_size50_58_sram_blwl_outb[2600:2600] ,mux_2level_size50_58_configbus0[2600:2600], mux_2level_size50_58_configbus1[2600:2600] , mux_2level_size50_58_configbus0_b[2600:2600] ); -sram6T_blwl sram_blwl_2601_ (mux_2level_size50_58_sram_blwl_out[2601:2601] ,mux_2level_size50_58_sram_blwl_out[2601:2601] ,mux_2level_size50_58_sram_blwl_outb[2601:2601] ,mux_2level_size50_58_configbus0[2601:2601], mux_2level_size50_58_configbus1[2601:2601] , mux_2level_size50_58_configbus0_b[2601:2601] ); -sram6T_blwl sram_blwl_2602_ (mux_2level_size50_58_sram_blwl_out[2602:2602] ,mux_2level_size50_58_sram_blwl_out[2602:2602] ,mux_2level_size50_58_sram_blwl_outb[2602:2602] ,mux_2level_size50_58_configbus0[2602:2602], mux_2level_size50_58_configbus1[2602:2602] , mux_2level_size50_58_configbus0_b[2602:2602] ); -sram6T_blwl sram_blwl_2603_ (mux_2level_size50_58_sram_blwl_out[2603:2603] ,mux_2level_size50_58_sram_blwl_out[2603:2603] ,mux_2level_size50_58_sram_blwl_outb[2603:2603] ,mux_2level_size50_58_configbus0[2603:2603], mux_2level_size50_58_configbus1[2603:2603] , mux_2level_size50_58_configbus0_b[2603:2603] ); -sram6T_blwl sram_blwl_2604_ (mux_2level_size50_58_sram_blwl_out[2604:2604] ,mux_2level_size50_58_sram_blwl_out[2604:2604] ,mux_2level_size50_58_sram_blwl_outb[2604:2604] ,mux_2level_size50_58_configbus0[2604:2604], mux_2level_size50_58_configbus1[2604:2604] , mux_2level_size50_58_configbus0_b[2604:2604] ); -sram6T_blwl sram_blwl_2605_ (mux_2level_size50_58_sram_blwl_out[2605:2605] ,mux_2level_size50_58_sram_blwl_out[2605:2605] ,mux_2level_size50_58_sram_blwl_outb[2605:2605] ,mux_2level_size50_58_configbus0[2605:2605], mux_2level_size50_58_configbus1[2605:2605] , mux_2level_size50_58_configbus0_b[2605:2605] ); -sram6T_blwl sram_blwl_2606_ (mux_2level_size50_58_sram_blwl_out[2606:2606] ,mux_2level_size50_58_sram_blwl_out[2606:2606] ,mux_2level_size50_58_sram_blwl_outb[2606:2606] ,mux_2level_size50_58_configbus0[2606:2606], mux_2level_size50_58_configbus1[2606:2606] , mux_2level_size50_58_configbus0_b[2606:2606] ); -sram6T_blwl sram_blwl_2607_ (mux_2level_size50_58_sram_blwl_out[2607:2607] ,mux_2level_size50_58_sram_blwl_out[2607:2607] ,mux_2level_size50_58_sram_blwl_outb[2607:2607] ,mux_2level_size50_58_configbus0[2607:2607], mux_2level_size50_58_configbus1[2607:2607] , mux_2level_size50_58_configbus0_b[2607:2607] ); -sram6T_blwl sram_blwl_2608_ (mux_2level_size50_58_sram_blwl_out[2608:2608] ,mux_2level_size50_58_sram_blwl_out[2608:2608] ,mux_2level_size50_58_sram_blwl_outb[2608:2608] ,mux_2level_size50_58_configbus0[2608:2608], mux_2level_size50_58_configbus1[2608:2608] , mux_2level_size50_58_configbus0_b[2608:2608] ); -sram6T_blwl sram_blwl_2609_ (mux_2level_size50_58_sram_blwl_out[2609:2609] ,mux_2level_size50_58_sram_blwl_out[2609:2609] ,mux_2level_size50_58_sram_blwl_outb[2609:2609] ,mux_2level_size50_58_configbus0[2609:2609], mux_2level_size50_58_configbus1[2609:2609] , mux_2level_size50_58_configbus0_b[2609:2609] ); -wire [0:49] in_bus_mux_2level_size50_59_ ; -assign in_bus_mux_2level_size50_59_[0] = mode_clb___I_0_ ; -assign in_bus_mux_2level_size50_59_[1] = mode_clb___I_1_ ; -assign in_bus_mux_2level_size50_59_[2] = mode_clb___I_2_ ; -assign in_bus_mux_2level_size50_59_[3] = mode_clb___I_3_ ; -assign in_bus_mux_2level_size50_59_[4] = mode_clb___I_4_ ; -assign in_bus_mux_2level_size50_59_[5] = mode_clb___I_5_ ; -assign in_bus_mux_2level_size50_59_[6] = mode_clb___I_6_ ; -assign in_bus_mux_2level_size50_59_[7] = mode_clb___I_7_ ; -assign in_bus_mux_2level_size50_59_[8] = mode_clb___I_8_ ; -assign in_bus_mux_2level_size50_59_[9] = mode_clb___I_9_ ; -assign in_bus_mux_2level_size50_59_[10] = mode_clb___I_10_ ; -assign in_bus_mux_2level_size50_59_[11] = mode_clb___I_11_ ; -assign in_bus_mux_2level_size50_59_[12] = mode_clb___I_12_ ; -assign in_bus_mux_2level_size50_59_[13] = mode_clb___I_13_ ; -assign in_bus_mux_2level_size50_59_[14] = mode_clb___I_14_ ; -assign in_bus_mux_2level_size50_59_[15] = mode_clb___I_15_ ; -assign in_bus_mux_2level_size50_59_[16] = mode_clb___I_16_ ; -assign in_bus_mux_2level_size50_59_[17] = mode_clb___I_17_ ; -assign in_bus_mux_2level_size50_59_[18] = mode_clb___I_18_ ; -assign in_bus_mux_2level_size50_59_[19] = mode_clb___I_19_ ; -assign in_bus_mux_2level_size50_59_[20] = mode_clb___I_20_ ; -assign in_bus_mux_2level_size50_59_[21] = mode_clb___I_21_ ; -assign in_bus_mux_2level_size50_59_[22] = mode_clb___I_22_ ; -assign in_bus_mux_2level_size50_59_[23] = mode_clb___I_23_ ; -assign in_bus_mux_2level_size50_59_[24] = mode_clb___I_24_ ; -assign in_bus_mux_2level_size50_59_[25] = mode_clb___I_25_ ; -assign in_bus_mux_2level_size50_59_[26] = mode_clb___I_26_ ; -assign in_bus_mux_2level_size50_59_[27] = mode_clb___I_27_ ; -assign in_bus_mux_2level_size50_59_[28] = mode_clb___I_28_ ; -assign in_bus_mux_2level_size50_59_[29] = mode_clb___I_29_ ; -assign in_bus_mux_2level_size50_59_[30] = mode_clb___I_30_ ; -assign in_bus_mux_2level_size50_59_[31] = mode_clb___I_31_ ; -assign in_bus_mux_2level_size50_59_[32] = mode_clb___I_32_ ; -assign in_bus_mux_2level_size50_59_[33] = mode_clb___I_33_ ; -assign in_bus_mux_2level_size50_59_[34] = mode_clb___I_34_ ; -assign in_bus_mux_2level_size50_59_[35] = mode_clb___I_35_ ; -assign in_bus_mux_2level_size50_59_[36] = mode_clb___I_36_ ; -assign in_bus_mux_2level_size50_59_[37] = mode_clb___I_37_ ; -assign in_bus_mux_2level_size50_59_[38] = mode_clb___I_38_ ; -assign in_bus_mux_2level_size50_59_[39] = mode_clb___I_39_ ; -assign in_bus_mux_2level_size50_59_[40] = fle_0___out_0_ ; -assign in_bus_mux_2level_size50_59_[41] = fle_1___out_0_ ; -assign in_bus_mux_2level_size50_59_[42] = fle_2___out_0_ ; -assign in_bus_mux_2level_size50_59_[43] = fle_3___out_0_ ; -assign in_bus_mux_2level_size50_59_[44] = fle_4___out_0_ ; -assign in_bus_mux_2level_size50_59_[45] = fle_5___out_0_ ; -assign in_bus_mux_2level_size50_59_[46] = fle_6___out_0_ ; -assign in_bus_mux_2level_size50_59_[47] = fle_7___out_0_ ; -assign in_bus_mux_2level_size50_59_[48] = fle_8___out_0_ ; -assign in_bus_mux_2level_size50_59_[49] = fle_9___out_0_ ; -wire [2610:2625] mux_2level_size50_59_configbus0; -wire [2610:2625] mux_2level_size50_59_configbus1; -wire [2610:2625] mux_2level_size50_59_sram_blwl_out ; -wire [2610:2625] mux_2level_size50_59_sram_blwl_outb ; -assign mux_2level_size50_59_configbus0[2610:2625] = sram_blwl_bl[2610:2625] ; -assign mux_2level_size50_59_configbus1[2610:2625] = sram_blwl_wl[2610:2625] ; -wire [2610:2625] mux_2level_size50_59_configbus0_b; -assign mux_2level_size50_59_configbus0_b[2610:2625] = sram_blwl_blb[2610:2625] ; -mux_2level_size50 mux_2level_size50_59_ (in_bus_mux_2level_size50_59_, fle_9___in_5_, mux_2level_size50_59_sram_blwl_out[2610:2625] , -mux_2level_size50_59_sram_blwl_outb[2610:2625] ); -//----- SRAM bits for MUX[59], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1000000010000000----- -sram6T_blwl sram_blwl_2610_ (mux_2level_size50_59_sram_blwl_out[2610:2610] ,mux_2level_size50_59_sram_blwl_out[2610:2610] ,mux_2level_size50_59_sram_blwl_outb[2610:2610] ,mux_2level_size50_59_configbus0[2610:2610], mux_2level_size50_59_configbus1[2610:2610] , mux_2level_size50_59_configbus0_b[2610:2610] ); -sram6T_blwl sram_blwl_2611_ (mux_2level_size50_59_sram_blwl_out[2611:2611] ,mux_2level_size50_59_sram_blwl_out[2611:2611] ,mux_2level_size50_59_sram_blwl_outb[2611:2611] ,mux_2level_size50_59_configbus0[2611:2611], mux_2level_size50_59_configbus1[2611:2611] , mux_2level_size50_59_configbus0_b[2611:2611] ); -sram6T_blwl sram_blwl_2612_ (mux_2level_size50_59_sram_blwl_out[2612:2612] ,mux_2level_size50_59_sram_blwl_out[2612:2612] ,mux_2level_size50_59_sram_blwl_outb[2612:2612] ,mux_2level_size50_59_configbus0[2612:2612], mux_2level_size50_59_configbus1[2612:2612] , mux_2level_size50_59_configbus0_b[2612:2612] ); -sram6T_blwl sram_blwl_2613_ (mux_2level_size50_59_sram_blwl_out[2613:2613] ,mux_2level_size50_59_sram_blwl_out[2613:2613] ,mux_2level_size50_59_sram_blwl_outb[2613:2613] ,mux_2level_size50_59_configbus0[2613:2613], mux_2level_size50_59_configbus1[2613:2613] , mux_2level_size50_59_configbus0_b[2613:2613] ); -sram6T_blwl sram_blwl_2614_ (mux_2level_size50_59_sram_blwl_out[2614:2614] ,mux_2level_size50_59_sram_blwl_out[2614:2614] ,mux_2level_size50_59_sram_blwl_outb[2614:2614] ,mux_2level_size50_59_configbus0[2614:2614], mux_2level_size50_59_configbus1[2614:2614] , mux_2level_size50_59_configbus0_b[2614:2614] ); -sram6T_blwl sram_blwl_2615_ (mux_2level_size50_59_sram_blwl_out[2615:2615] ,mux_2level_size50_59_sram_blwl_out[2615:2615] ,mux_2level_size50_59_sram_blwl_outb[2615:2615] ,mux_2level_size50_59_configbus0[2615:2615], mux_2level_size50_59_configbus1[2615:2615] , mux_2level_size50_59_configbus0_b[2615:2615] ); -sram6T_blwl sram_blwl_2616_ (mux_2level_size50_59_sram_blwl_out[2616:2616] ,mux_2level_size50_59_sram_blwl_out[2616:2616] ,mux_2level_size50_59_sram_blwl_outb[2616:2616] ,mux_2level_size50_59_configbus0[2616:2616], mux_2level_size50_59_configbus1[2616:2616] , mux_2level_size50_59_configbus0_b[2616:2616] ); -sram6T_blwl sram_blwl_2617_ (mux_2level_size50_59_sram_blwl_out[2617:2617] ,mux_2level_size50_59_sram_blwl_out[2617:2617] ,mux_2level_size50_59_sram_blwl_outb[2617:2617] ,mux_2level_size50_59_configbus0[2617:2617], mux_2level_size50_59_configbus1[2617:2617] , mux_2level_size50_59_configbus0_b[2617:2617] ); -sram6T_blwl sram_blwl_2618_ (mux_2level_size50_59_sram_blwl_out[2618:2618] ,mux_2level_size50_59_sram_blwl_out[2618:2618] ,mux_2level_size50_59_sram_blwl_outb[2618:2618] ,mux_2level_size50_59_configbus0[2618:2618], mux_2level_size50_59_configbus1[2618:2618] , mux_2level_size50_59_configbus0_b[2618:2618] ); -sram6T_blwl sram_blwl_2619_ (mux_2level_size50_59_sram_blwl_out[2619:2619] ,mux_2level_size50_59_sram_blwl_out[2619:2619] ,mux_2level_size50_59_sram_blwl_outb[2619:2619] ,mux_2level_size50_59_configbus0[2619:2619], mux_2level_size50_59_configbus1[2619:2619] , mux_2level_size50_59_configbus0_b[2619:2619] ); -sram6T_blwl sram_blwl_2620_ (mux_2level_size50_59_sram_blwl_out[2620:2620] ,mux_2level_size50_59_sram_blwl_out[2620:2620] ,mux_2level_size50_59_sram_blwl_outb[2620:2620] ,mux_2level_size50_59_configbus0[2620:2620], mux_2level_size50_59_configbus1[2620:2620] , mux_2level_size50_59_configbus0_b[2620:2620] ); -sram6T_blwl sram_blwl_2621_ (mux_2level_size50_59_sram_blwl_out[2621:2621] ,mux_2level_size50_59_sram_blwl_out[2621:2621] ,mux_2level_size50_59_sram_blwl_outb[2621:2621] ,mux_2level_size50_59_configbus0[2621:2621], mux_2level_size50_59_configbus1[2621:2621] , mux_2level_size50_59_configbus0_b[2621:2621] ); -sram6T_blwl sram_blwl_2622_ (mux_2level_size50_59_sram_blwl_out[2622:2622] ,mux_2level_size50_59_sram_blwl_out[2622:2622] ,mux_2level_size50_59_sram_blwl_outb[2622:2622] ,mux_2level_size50_59_configbus0[2622:2622], mux_2level_size50_59_configbus1[2622:2622] , mux_2level_size50_59_configbus0_b[2622:2622] ); -sram6T_blwl sram_blwl_2623_ (mux_2level_size50_59_sram_blwl_out[2623:2623] ,mux_2level_size50_59_sram_blwl_out[2623:2623] ,mux_2level_size50_59_sram_blwl_outb[2623:2623] ,mux_2level_size50_59_configbus0[2623:2623], mux_2level_size50_59_configbus1[2623:2623] , mux_2level_size50_59_configbus0_b[2623:2623] ); -sram6T_blwl sram_blwl_2624_ (mux_2level_size50_59_sram_blwl_out[2624:2624] ,mux_2level_size50_59_sram_blwl_out[2624:2624] ,mux_2level_size50_59_sram_blwl_outb[2624:2624] ,mux_2level_size50_59_configbus0[2624:2624], mux_2level_size50_59_configbus1[2624:2624] , mux_2level_size50_59_configbus0_b[2624:2624] ); -sram6T_blwl sram_blwl_2625_ (mux_2level_size50_59_sram_blwl_out[2625:2625] ,mux_2level_size50_59_sram_blwl_out[2625:2625] ,mux_2level_size50_59_sram_blwl_outb[2625:2625] ,mux_2level_size50_59_configbus0[2625:2625], mux_2level_size50_59_configbus1[2625:2625] , mux_2level_size50_59_configbus0_b[2625:2625] ); -direct_interc direct_interc_179_ (mode_clb___clk_0_, fle_9___clk_0_ ); -endmodule -//----- END Programmable logic block Verilog module grid_1__1__clb_0__mode_clb_ ----- - -//----- END ----- - -//----- Grid[1][1], Capactity: 1 ----- -//----- Top Protocol ----- -module grid_1__1_( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input top_height_0__pin_0_, -input top_height_0__pin_4_, -input top_height_0__pin_8_, -input top_height_0__pin_12_, -input top_height_0__pin_16_, -input top_height_0__pin_20_, -input top_height_0__pin_24_, -input top_height_0__pin_28_, -input top_height_0__pin_32_, -input top_height_0__pin_36_, -output top_height_0__pin_40_, -output top_height_0__pin_44_, -output top_height_0__pin_48_, -input right_height_0__pin_1_, -input right_height_0__pin_5_, -input right_height_0__pin_9_, -input right_height_0__pin_13_, -input right_height_0__pin_17_, -input right_height_0__pin_21_, -input right_height_0__pin_25_, -input right_height_0__pin_29_, -input right_height_0__pin_33_, -input right_height_0__pin_37_, -output right_height_0__pin_41_, -output right_height_0__pin_45_, -output right_height_0__pin_49_, -input bottom_height_0__pin_2_, -input bottom_height_0__pin_6_, -input bottom_height_0__pin_10_, -input bottom_height_0__pin_14_, -input bottom_height_0__pin_18_, -input bottom_height_0__pin_22_, -input bottom_height_0__pin_26_, -input bottom_height_0__pin_30_, -input bottom_height_0__pin_34_, -input bottom_height_0__pin_38_, -output bottom_height_0__pin_42_, -output bottom_height_0__pin_46_, -input bottom_height_0__pin_50_, -input left_height_0__pin_3_, -input left_height_0__pin_7_, -input left_height_0__pin_11_, -input left_height_0__pin_15_, -input left_height_0__pin_19_, -input left_height_0__pin_23_, -input left_height_0__pin_27_, -input left_height_0__pin_31_, -input left_height_0__pin_35_, -input left_height_0__pin_39_, -output left_height_0__pin_43_, -output left_height_0__pin_47_, -input [1016:2625] sram_blwl_bl , -input [1016:2625] sram_blwl_wl , -input [1016:2625] sram_blwl_blb ); -grid_1__1__clb_0__mode_clb_ grid_1__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -top_height_0__pin_0_ , -right_height_0__pin_1_ , -bottom_height_0__pin_2_ , -left_height_0__pin_3_ , -top_height_0__pin_4_ , -right_height_0__pin_5_ , -bottom_height_0__pin_6_ , -left_height_0__pin_7_ , -top_height_0__pin_8_ , -right_height_0__pin_9_ , -bottom_height_0__pin_10_ , -left_height_0__pin_11_ , -top_height_0__pin_12_ , -right_height_0__pin_13_ , -bottom_height_0__pin_14_ , -left_height_0__pin_15_ , -top_height_0__pin_16_ , -right_height_0__pin_17_ , -bottom_height_0__pin_18_ , -left_height_0__pin_19_ , -top_height_0__pin_20_ , -right_height_0__pin_21_ , -bottom_height_0__pin_22_ , -left_height_0__pin_23_ , -top_height_0__pin_24_ , -right_height_0__pin_25_ , -bottom_height_0__pin_26_ , -left_height_0__pin_27_ , -top_height_0__pin_28_ , -right_height_0__pin_29_ , -bottom_height_0__pin_30_ , -left_height_0__pin_31_ , -top_height_0__pin_32_ , -right_height_0__pin_33_ , -bottom_height_0__pin_34_ , -left_height_0__pin_35_ , -top_height_0__pin_36_ , -right_height_0__pin_37_ , -bottom_height_0__pin_38_ , -left_height_0__pin_39_ , -top_height_0__pin_40_ , -right_height_0__pin_41_ , -bottom_height_0__pin_42_ , -left_height_0__pin_43_ , -top_height_0__pin_44_ , -right_height_0__pin_45_ , -bottom_height_0__pin_46_ , -left_height_0__pin_47_ , -top_height_0__pin_48_ , -right_height_0__pin_49_ , -bottom_height_0__pin_50_ -//---- IOPAD ---- -, -//---- SRAM ---- -sram_blwl_bl[1016:2625] , -sram_blwl_wl[1016:2625] , -sram_blwl_blb[1016:2625] ); -endmodule -//----- END Top Protocol ----- -//----- END Grid[1][1], Capactity: 1 ----- - diff --git a/examples/verilog_test_example_2/lb/grid_1_2.v b/examples/verilog_test_example_2/lb/grid_1_2.v deleted file mode 100644 index b31c26e88..000000000 --- a/examples/verilog_test_example_2/lb/grid_1_2.v +++ /dev/null @@ -1,694 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Physical Logic Block [1][2] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Grid[1][2] type_descriptor: io[0] ----- -//----- IO Verilog module: grid_1__2__io_0__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_0__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [24:24] gfpga_pad_iopad -, -input [2650:2650] sram_blwl_bl , -input [2650:2650] sram_blwl_wl , -input [2650:2650] sram_blwl_blb ); -wire [2650:2650] sram_blwl_out ; -wire [2650:2650] sram_blwl_outb ; -wire [2650:2650] sram_blwl_2650_configbus0; -wire [2650:2650] sram_blwl_2650_configbus1; -wire [2650:2650] sram_blwl_2650_configbus0_b; -assign sram_blwl_2650_configbus0[2650:2650] = sram_blwl_bl[2650:2650] ; -assign sram_blwl_2650_configbus1[2650:2650] = sram_blwl_wl[2650:2650] ; -assign sram_blwl_2650_configbus0_b[2650:2650] = sram_blwl_blb[2650:2650] ; -iopad iopad_24_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[24], sram_blwl_out[2650:2650] , sram_blwl_outb[2650:2650] ); -sram6T_blwl sram_blwl_2650_ (sram_blwl_out[2650], sram_blwl_out[2650], sram_blwl_outb[2650], sram_blwl_2650_configbus0[2650:2650], sram_blwl_2650_configbus1[2650:2650] , sram_blwl_2650_configbus0_b[2650:2650] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_0__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_0__mode_io_phy_ ----- -module grid_1__2__io_0__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [24:24] gfpga_pad_iopad , -input [2650:2650] sram_blwl_bl , -input [2650:2650] sram_blwl_wl , -input [2650:2650] sram_blwl_blb ); -grid_1__2__io_0__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[24:24] , -sram_blwl_bl[2650:2650] , -sram_blwl_wl[2650:2650] , -sram_blwl_blb[2650:2650] ); -direct_interc direct_interc_228_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_229_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_0__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[1] ----- -//----- IO Verilog module: grid_1__2__io_1__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_1__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [25:25] gfpga_pad_iopad -, -input [2651:2651] sram_blwl_bl , -input [2651:2651] sram_blwl_wl , -input [2651:2651] sram_blwl_blb ); -wire [2651:2651] sram_blwl_out ; -wire [2651:2651] sram_blwl_outb ; -wire [2651:2651] sram_blwl_2651_configbus0; -wire [2651:2651] sram_blwl_2651_configbus1; -wire [2651:2651] sram_blwl_2651_configbus0_b; -assign sram_blwl_2651_configbus0[2651:2651] = sram_blwl_bl[2651:2651] ; -assign sram_blwl_2651_configbus1[2651:2651] = sram_blwl_wl[2651:2651] ; -assign sram_blwl_2651_configbus0_b[2651:2651] = sram_blwl_blb[2651:2651] ; -iopad iopad_25_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[25], sram_blwl_out[2651:2651] , sram_blwl_outb[2651:2651] ); -sram6T_blwl sram_blwl_2651_ (sram_blwl_out[2651], sram_blwl_out[2651], sram_blwl_outb[2651], sram_blwl_2651_configbus0[2651:2651], sram_blwl_2651_configbus1[2651:2651] , sram_blwl_2651_configbus0_b[2651:2651] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_1__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_1__mode_io_phy_ ----- -module grid_1__2__io_1__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [25:25] gfpga_pad_iopad , -input [2651:2651] sram_blwl_bl , -input [2651:2651] sram_blwl_wl , -input [2651:2651] sram_blwl_blb ); -grid_1__2__io_1__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[25:25] , -sram_blwl_bl[2651:2651] , -sram_blwl_wl[2651:2651] , -sram_blwl_blb[2651:2651] ); -direct_interc direct_interc_230_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_231_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_1__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[2] ----- -//----- IO Verilog module: grid_1__2__io_2__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_2__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [26:26] gfpga_pad_iopad -, -input [2652:2652] sram_blwl_bl , -input [2652:2652] sram_blwl_wl , -input [2652:2652] sram_blwl_blb ); -wire [2652:2652] sram_blwl_out ; -wire [2652:2652] sram_blwl_outb ; -wire [2652:2652] sram_blwl_2652_configbus0; -wire [2652:2652] sram_blwl_2652_configbus1; -wire [2652:2652] sram_blwl_2652_configbus0_b; -assign sram_blwl_2652_configbus0[2652:2652] = sram_blwl_bl[2652:2652] ; -assign sram_blwl_2652_configbus1[2652:2652] = sram_blwl_wl[2652:2652] ; -assign sram_blwl_2652_configbus0_b[2652:2652] = sram_blwl_blb[2652:2652] ; -iopad iopad_26_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[26], sram_blwl_out[2652:2652] , sram_blwl_outb[2652:2652] ); -sram6T_blwl sram_blwl_2652_ (sram_blwl_out[2652], sram_blwl_out[2652], sram_blwl_outb[2652], sram_blwl_2652_configbus0[2652:2652], sram_blwl_2652_configbus1[2652:2652] , sram_blwl_2652_configbus0_b[2652:2652] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_2__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_2__mode_io_phy_ ----- -module grid_1__2__io_2__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [26:26] gfpga_pad_iopad , -input [2652:2652] sram_blwl_bl , -input [2652:2652] sram_blwl_wl , -input [2652:2652] sram_blwl_blb ); -grid_1__2__io_2__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[26:26] , -sram_blwl_bl[2652:2652] , -sram_blwl_wl[2652:2652] , -sram_blwl_blb[2652:2652] ); -direct_interc direct_interc_232_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_233_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_2__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[3] ----- -//----- IO Verilog module: grid_1__2__io_3__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_3__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [27:27] gfpga_pad_iopad -, -input [2653:2653] sram_blwl_bl , -input [2653:2653] sram_blwl_wl , -input [2653:2653] sram_blwl_blb ); -wire [2653:2653] sram_blwl_out ; -wire [2653:2653] sram_blwl_outb ; -wire [2653:2653] sram_blwl_2653_configbus0; -wire [2653:2653] sram_blwl_2653_configbus1; -wire [2653:2653] sram_blwl_2653_configbus0_b; -assign sram_blwl_2653_configbus0[2653:2653] = sram_blwl_bl[2653:2653] ; -assign sram_blwl_2653_configbus1[2653:2653] = sram_blwl_wl[2653:2653] ; -assign sram_blwl_2653_configbus0_b[2653:2653] = sram_blwl_blb[2653:2653] ; -iopad iopad_27_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[27], sram_blwl_out[2653:2653] , sram_blwl_outb[2653:2653] ); -sram6T_blwl sram_blwl_2653_ (sram_blwl_out[2653], sram_blwl_out[2653], sram_blwl_outb[2653], sram_blwl_2653_configbus0[2653:2653], sram_blwl_2653_configbus1[2653:2653] , sram_blwl_2653_configbus0_b[2653:2653] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_3__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_3__mode_io_phy_ ----- -module grid_1__2__io_3__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [27:27] gfpga_pad_iopad , -input [2653:2653] sram_blwl_bl , -input [2653:2653] sram_blwl_wl , -input [2653:2653] sram_blwl_blb ); -grid_1__2__io_3__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[27:27] , -sram_blwl_bl[2653:2653] , -sram_blwl_wl[2653:2653] , -sram_blwl_blb[2653:2653] ); -direct_interc direct_interc_234_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_235_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_3__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[4] ----- -//----- IO Verilog module: grid_1__2__io_4__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_4__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [28:28] gfpga_pad_iopad -, -input [2654:2654] sram_blwl_bl , -input [2654:2654] sram_blwl_wl , -input [2654:2654] sram_blwl_blb ); -wire [2654:2654] sram_blwl_out ; -wire [2654:2654] sram_blwl_outb ; -wire [2654:2654] sram_blwl_2654_configbus0; -wire [2654:2654] sram_blwl_2654_configbus1; -wire [2654:2654] sram_blwl_2654_configbus0_b; -assign sram_blwl_2654_configbus0[2654:2654] = sram_blwl_bl[2654:2654] ; -assign sram_blwl_2654_configbus1[2654:2654] = sram_blwl_wl[2654:2654] ; -assign sram_blwl_2654_configbus0_b[2654:2654] = sram_blwl_blb[2654:2654] ; -iopad iopad_28_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[28], sram_blwl_out[2654:2654] , sram_blwl_outb[2654:2654] ); -sram6T_blwl sram_blwl_2654_ (sram_blwl_out[2654], sram_blwl_out[2654], sram_blwl_outb[2654], sram_blwl_2654_configbus0[2654:2654], sram_blwl_2654_configbus1[2654:2654] , sram_blwl_2654_configbus0_b[2654:2654] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_4__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_4__mode_io_phy_ ----- -module grid_1__2__io_4__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [28:28] gfpga_pad_iopad , -input [2654:2654] sram_blwl_bl , -input [2654:2654] sram_blwl_wl , -input [2654:2654] sram_blwl_blb ); -grid_1__2__io_4__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[28:28] , -sram_blwl_bl[2654:2654] , -sram_blwl_wl[2654:2654] , -sram_blwl_blb[2654:2654] ); -direct_interc direct_interc_236_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_237_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_4__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[5] ----- -//----- IO Verilog module: grid_1__2__io_5__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_5__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [29:29] gfpga_pad_iopad -, -input [2655:2655] sram_blwl_bl , -input [2655:2655] sram_blwl_wl , -input [2655:2655] sram_blwl_blb ); -wire [2655:2655] sram_blwl_out ; -wire [2655:2655] sram_blwl_outb ; -wire [2655:2655] sram_blwl_2655_configbus0; -wire [2655:2655] sram_blwl_2655_configbus1; -wire [2655:2655] sram_blwl_2655_configbus0_b; -assign sram_blwl_2655_configbus0[2655:2655] = sram_blwl_bl[2655:2655] ; -assign sram_blwl_2655_configbus1[2655:2655] = sram_blwl_wl[2655:2655] ; -assign sram_blwl_2655_configbus0_b[2655:2655] = sram_blwl_blb[2655:2655] ; -iopad iopad_29_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[29], sram_blwl_out[2655:2655] , sram_blwl_outb[2655:2655] ); -sram6T_blwl sram_blwl_2655_ (sram_blwl_out[2655], sram_blwl_out[2655], sram_blwl_outb[2655], sram_blwl_2655_configbus0[2655:2655], sram_blwl_2655_configbus1[2655:2655] , sram_blwl_2655_configbus0_b[2655:2655] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_5__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_5__mode_io_phy_ ----- -module grid_1__2__io_5__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [29:29] gfpga_pad_iopad , -input [2655:2655] sram_blwl_bl , -input [2655:2655] sram_blwl_wl , -input [2655:2655] sram_blwl_blb ); -grid_1__2__io_5__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[29:29] , -sram_blwl_bl[2655:2655] , -sram_blwl_wl[2655:2655] , -sram_blwl_blb[2655:2655] ); -direct_interc direct_interc_238_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_239_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_5__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[6] ----- -//----- IO Verilog module: grid_1__2__io_6__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_6__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [30:30] gfpga_pad_iopad -, -input [2656:2656] sram_blwl_bl , -input [2656:2656] sram_blwl_wl , -input [2656:2656] sram_blwl_blb ); -wire [2656:2656] sram_blwl_out ; -wire [2656:2656] sram_blwl_outb ; -wire [2656:2656] sram_blwl_2656_configbus0; -wire [2656:2656] sram_blwl_2656_configbus1; -wire [2656:2656] sram_blwl_2656_configbus0_b; -assign sram_blwl_2656_configbus0[2656:2656] = sram_blwl_bl[2656:2656] ; -assign sram_blwl_2656_configbus1[2656:2656] = sram_blwl_wl[2656:2656] ; -assign sram_blwl_2656_configbus0_b[2656:2656] = sram_blwl_blb[2656:2656] ; -iopad iopad_30_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[30], sram_blwl_out[2656:2656] , sram_blwl_outb[2656:2656] ); -sram6T_blwl sram_blwl_2656_ (sram_blwl_out[2656], sram_blwl_out[2656], sram_blwl_outb[2656], sram_blwl_2656_configbus0[2656:2656], sram_blwl_2656_configbus1[2656:2656] , sram_blwl_2656_configbus0_b[2656:2656] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_6__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_6__mode_io_phy_ ----- -module grid_1__2__io_6__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [30:30] gfpga_pad_iopad , -input [2656:2656] sram_blwl_bl , -input [2656:2656] sram_blwl_wl , -input [2656:2656] sram_blwl_blb ); -grid_1__2__io_6__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[30:30] , -sram_blwl_bl[2656:2656] , -sram_blwl_wl[2656:2656] , -sram_blwl_blb[2656:2656] ); -direct_interc direct_interc_240_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_241_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_6__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2] type_descriptor: io[7] ----- -//----- IO Verilog module: grid_1__2__io_7__mode_io_phy__iopad_0_ ----- -module grid_1__2__io_7__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [31:31] gfpga_pad_iopad -, -input [2657:2657] sram_blwl_bl , -input [2657:2657] sram_blwl_wl , -input [2657:2657] sram_blwl_blb ); -wire [2657:2657] sram_blwl_out ; -wire [2657:2657] sram_blwl_outb ; -wire [2657:2657] sram_blwl_2657_configbus0; -wire [2657:2657] sram_blwl_2657_configbus1; -wire [2657:2657] sram_blwl_2657_configbus0_b; -assign sram_blwl_2657_configbus0[2657:2657] = sram_blwl_bl[2657:2657] ; -assign sram_blwl_2657_configbus1[2657:2657] = sram_blwl_wl[2657:2657] ; -assign sram_blwl_2657_configbus0_b[2657:2657] = sram_blwl_blb[2657:2657] ; -iopad iopad_31_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[31], sram_blwl_out[2657:2657] , sram_blwl_outb[2657:2657] ); -sram6T_blwl sram_blwl_2657_ (sram_blwl_out[2657], sram_blwl_out[2657], sram_blwl_outb[2657], sram_blwl_2657_configbus0[2657:2657], sram_blwl_2657_configbus1[2657:2657] , sram_blwl_2657_configbus0_b[2657:2657] ); -endmodule -//----- END IO Verilog module: grid_1__2__io_7__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_1__2__io_7__mode_io_phy_ ----- -module grid_1__2__io_7__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [31:31] gfpga_pad_iopad , -input [2657:2657] sram_blwl_bl , -input [2657:2657] sram_blwl_wl , -input [2657:2657] sram_blwl_blb ); -grid_1__2__io_7__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[31:31] , -sram_blwl_bl[2657:2657] , -sram_blwl_wl[2657:2657] , -sram_blwl_blb[2657:2657] ); -direct_interc direct_interc_242_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_243_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_1__2__io_7__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[1][2], Capactity: 8 ----- -//----- Top Protocol ----- -module grid_1__2_( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input bottom_height_0__pin_0_, -output bottom_height_0__pin_1_, -input bottom_height_0__pin_2_, -output bottom_height_0__pin_3_, -input bottom_height_0__pin_4_, -output bottom_height_0__pin_5_, -input bottom_height_0__pin_6_, -output bottom_height_0__pin_7_, -input bottom_height_0__pin_8_, -output bottom_height_0__pin_9_, -input bottom_height_0__pin_10_, -output bottom_height_0__pin_11_, -input bottom_height_0__pin_12_, -output bottom_height_0__pin_13_, -input bottom_height_0__pin_14_, -output bottom_height_0__pin_15_, -input [31:24] gfpga_pad_iopad , -input [2650:2657] sram_blwl_bl , -input [2650:2657] sram_blwl_wl , -input [2650:2657] sram_blwl_blb ); -grid_1__2__io_0__mode_io_phy_ grid_1__2__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_0_, -bottom_height_0__pin_1_ -//---- IOPAD ---- -, -gfpga_pad_iopad[24:24] , -//---- SRAM ---- -sram_blwl_bl[2650:2650] , -sram_blwl_wl[2650:2650] , -sram_blwl_blb[2650:2650] ); -grid_1__2__io_1__mode_io_phy_ grid_1__2__1_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_2_, -bottom_height_0__pin_3_ -//---- IOPAD ---- -, -gfpga_pad_iopad[25:25] , -//---- SRAM ---- -sram_blwl_bl[2651:2651] , -sram_blwl_wl[2651:2651] , -sram_blwl_blb[2651:2651] ); -grid_1__2__io_2__mode_io_phy_ grid_1__2__2_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_4_, -bottom_height_0__pin_5_ -//---- IOPAD ---- -, -gfpga_pad_iopad[26:26] , -//---- SRAM ---- -sram_blwl_bl[2652:2652] , -sram_blwl_wl[2652:2652] , -sram_blwl_blb[2652:2652] ); -grid_1__2__io_3__mode_io_phy_ grid_1__2__3_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_6_, -bottom_height_0__pin_7_ -//---- IOPAD ---- -, -gfpga_pad_iopad[27:27] , -//---- SRAM ---- -sram_blwl_bl[2653:2653] , -sram_blwl_wl[2653:2653] , -sram_blwl_blb[2653:2653] ); -grid_1__2__io_4__mode_io_phy_ grid_1__2__4_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_8_, -bottom_height_0__pin_9_ -//---- IOPAD ---- -, -gfpga_pad_iopad[28:28] , -//---- SRAM ---- -sram_blwl_bl[2654:2654] , -sram_blwl_wl[2654:2654] , -sram_blwl_blb[2654:2654] ); -grid_1__2__io_5__mode_io_phy_ grid_1__2__5_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_10_, -bottom_height_0__pin_11_ -//---- IOPAD ---- -, -gfpga_pad_iopad[29:29] , -//---- SRAM ---- -sram_blwl_bl[2655:2655] , -sram_blwl_wl[2655:2655] , -sram_blwl_blb[2655:2655] ); -grid_1__2__io_6__mode_io_phy_ grid_1__2__6_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_12_, -bottom_height_0__pin_13_ -//---- IOPAD ---- -, -gfpga_pad_iopad[30:30] , -//---- SRAM ---- -sram_blwl_bl[2656:2656] , -sram_blwl_wl[2656:2656] , -sram_blwl_blb[2656:2656] ); -grid_1__2__io_7__mode_io_phy_ grid_1__2__7_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -bottom_height_0__pin_14_, -bottom_height_0__pin_15_ -//---- IOPAD ---- -, -gfpga_pad_iopad[31:31] , -//---- SRAM ---- -sram_blwl_bl[2657:2657] , -sram_blwl_wl[2657:2657] , -sram_blwl_blb[2657:2657] ); -endmodule -//----- END Top Protocol ----- -//----- END Grid[1][2], Capactity: 8 ----- - diff --git a/examples/verilog_test_example_2/lb/grid_2_1.v b/examples/verilog_test_example_2/lb/grid_2_1.v deleted file mode 100644 index 86f112489..000000000 --- a/examples/verilog_test_example_2/lb/grid_2_1.v +++ /dev/null @@ -1,694 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Physical Logic Block [2][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Grid[2][1] type_descriptor: io[0] ----- -//----- IO Verilog module: grid_2__1__io_0__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_0__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [8:8] gfpga_pad_iopad -, -input [2634:2634] sram_blwl_bl , -input [2634:2634] sram_blwl_wl , -input [2634:2634] sram_blwl_blb ); -wire [2634:2634] sram_blwl_out ; -wire [2634:2634] sram_blwl_outb ; -wire [2634:2634] sram_blwl_2634_configbus0; -wire [2634:2634] sram_blwl_2634_configbus1; -wire [2634:2634] sram_blwl_2634_configbus0_b; -assign sram_blwl_2634_configbus0[2634:2634] = sram_blwl_bl[2634:2634] ; -assign sram_blwl_2634_configbus1[2634:2634] = sram_blwl_wl[2634:2634] ; -assign sram_blwl_2634_configbus0_b[2634:2634] = sram_blwl_blb[2634:2634] ; -iopad iopad_8_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[8], sram_blwl_out[2634:2634] , sram_blwl_outb[2634:2634] ); -sram6T_blwl sram_blwl_2634_ (sram_blwl_out[2634], sram_blwl_out[2634], sram_blwl_outb[2634], sram_blwl_2634_configbus0[2634:2634], sram_blwl_2634_configbus1[2634:2634] , sram_blwl_2634_configbus0_b[2634:2634] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_0__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_0__mode_io_phy_ ----- -module grid_2__1__io_0__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [8:8] gfpga_pad_iopad , -input [2634:2634] sram_blwl_bl , -input [2634:2634] sram_blwl_wl , -input [2634:2634] sram_blwl_blb ); -grid_2__1__io_0__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[8:8] , -sram_blwl_bl[2634:2634] , -sram_blwl_wl[2634:2634] , -sram_blwl_blb[2634:2634] ); -direct_interc direct_interc_196_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_197_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_0__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[1] ----- -//----- IO Verilog module: grid_2__1__io_1__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_1__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [9:9] gfpga_pad_iopad -, -input [2635:2635] sram_blwl_bl , -input [2635:2635] sram_blwl_wl , -input [2635:2635] sram_blwl_blb ); -wire [2635:2635] sram_blwl_out ; -wire [2635:2635] sram_blwl_outb ; -wire [2635:2635] sram_blwl_2635_configbus0; -wire [2635:2635] sram_blwl_2635_configbus1; -wire [2635:2635] sram_blwl_2635_configbus0_b; -assign sram_blwl_2635_configbus0[2635:2635] = sram_blwl_bl[2635:2635] ; -assign sram_blwl_2635_configbus1[2635:2635] = sram_blwl_wl[2635:2635] ; -assign sram_blwl_2635_configbus0_b[2635:2635] = sram_blwl_blb[2635:2635] ; -iopad iopad_9_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[9], sram_blwl_out[2635:2635] , sram_blwl_outb[2635:2635] ); -sram6T_blwl sram_blwl_2635_ (sram_blwl_out[2635], sram_blwl_out[2635], sram_blwl_outb[2635], sram_blwl_2635_configbus0[2635:2635], sram_blwl_2635_configbus1[2635:2635] , sram_blwl_2635_configbus0_b[2635:2635] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_1__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_1__mode_io_phy_ ----- -module grid_2__1__io_1__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [9:9] gfpga_pad_iopad , -input [2635:2635] sram_blwl_bl , -input [2635:2635] sram_blwl_wl , -input [2635:2635] sram_blwl_blb ); -grid_2__1__io_1__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[9:9] , -sram_blwl_bl[2635:2635] , -sram_blwl_wl[2635:2635] , -sram_blwl_blb[2635:2635] ); -direct_interc direct_interc_198_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_199_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_1__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[2] ----- -//----- IO Verilog module: grid_2__1__io_2__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_2__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [10:10] gfpga_pad_iopad -, -input [2636:2636] sram_blwl_bl , -input [2636:2636] sram_blwl_wl , -input [2636:2636] sram_blwl_blb ); -wire [2636:2636] sram_blwl_out ; -wire [2636:2636] sram_blwl_outb ; -wire [2636:2636] sram_blwl_2636_configbus0; -wire [2636:2636] sram_blwl_2636_configbus1; -wire [2636:2636] sram_blwl_2636_configbus0_b; -assign sram_blwl_2636_configbus0[2636:2636] = sram_blwl_bl[2636:2636] ; -assign sram_blwl_2636_configbus1[2636:2636] = sram_blwl_wl[2636:2636] ; -assign sram_blwl_2636_configbus0_b[2636:2636] = sram_blwl_blb[2636:2636] ; -iopad iopad_10_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[10], sram_blwl_out[2636:2636] , sram_blwl_outb[2636:2636] ); -sram6T_blwl sram_blwl_2636_ (sram_blwl_out[2636], sram_blwl_out[2636], sram_blwl_outb[2636], sram_blwl_2636_configbus0[2636:2636], sram_blwl_2636_configbus1[2636:2636] , sram_blwl_2636_configbus0_b[2636:2636] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_2__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_2__mode_io_phy_ ----- -module grid_2__1__io_2__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [10:10] gfpga_pad_iopad , -input [2636:2636] sram_blwl_bl , -input [2636:2636] sram_blwl_wl , -input [2636:2636] sram_blwl_blb ); -grid_2__1__io_2__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[10:10] , -sram_blwl_bl[2636:2636] , -sram_blwl_wl[2636:2636] , -sram_blwl_blb[2636:2636] ); -direct_interc direct_interc_200_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_201_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_2__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[3] ----- -//----- IO Verilog module: grid_2__1__io_3__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_3__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [11:11] gfpga_pad_iopad -, -input [2637:2637] sram_blwl_bl , -input [2637:2637] sram_blwl_wl , -input [2637:2637] sram_blwl_blb ); -wire [2637:2637] sram_blwl_out ; -wire [2637:2637] sram_blwl_outb ; -wire [2637:2637] sram_blwl_2637_configbus0; -wire [2637:2637] sram_blwl_2637_configbus1; -wire [2637:2637] sram_blwl_2637_configbus0_b; -assign sram_blwl_2637_configbus0[2637:2637] = sram_blwl_bl[2637:2637] ; -assign sram_blwl_2637_configbus1[2637:2637] = sram_blwl_wl[2637:2637] ; -assign sram_blwl_2637_configbus0_b[2637:2637] = sram_blwl_blb[2637:2637] ; -iopad iopad_11_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[11], sram_blwl_out[2637:2637] , sram_blwl_outb[2637:2637] ); -sram6T_blwl sram_blwl_2637_ (sram_blwl_out[2637], sram_blwl_out[2637], sram_blwl_outb[2637], sram_blwl_2637_configbus0[2637:2637], sram_blwl_2637_configbus1[2637:2637] , sram_blwl_2637_configbus0_b[2637:2637] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_3__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_3__mode_io_phy_ ----- -module grid_2__1__io_3__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [11:11] gfpga_pad_iopad , -input [2637:2637] sram_blwl_bl , -input [2637:2637] sram_blwl_wl , -input [2637:2637] sram_blwl_blb ); -grid_2__1__io_3__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[11:11] , -sram_blwl_bl[2637:2637] , -sram_blwl_wl[2637:2637] , -sram_blwl_blb[2637:2637] ); -direct_interc direct_interc_202_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_203_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_3__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[4] ----- -//----- IO Verilog module: grid_2__1__io_4__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_4__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [12:12] gfpga_pad_iopad -, -input [2638:2638] sram_blwl_bl , -input [2638:2638] sram_blwl_wl , -input [2638:2638] sram_blwl_blb ); -wire [2638:2638] sram_blwl_out ; -wire [2638:2638] sram_blwl_outb ; -wire [2638:2638] sram_blwl_2638_configbus0; -wire [2638:2638] sram_blwl_2638_configbus1; -wire [2638:2638] sram_blwl_2638_configbus0_b; -assign sram_blwl_2638_configbus0[2638:2638] = sram_blwl_bl[2638:2638] ; -assign sram_blwl_2638_configbus1[2638:2638] = sram_blwl_wl[2638:2638] ; -assign sram_blwl_2638_configbus0_b[2638:2638] = sram_blwl_blb[2638:2638] ; -iopad iopad_12_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[12], sram_blwl_out[2638:2638] , sram_blwl_outb[2638:2638] ); -sram6T_blwl sram_blwl_2638_ (sram_blwl_out[2638], sram_blwl_out[2638], sram_blwl_outb[2638], sram_blwl_2638_configbus0[2638:2638], sram_blwl_2638_configbus1[2638:2638] , sram_blwl_2638_configbus0_b[2638:2638] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_4__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_4__mode_io_phy_ ----- -module grid_2__1__io_4__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [12:12] gfpga_pad_iopad , -input [2638:2638] sram_blwl_bl , -input [2638:2638] sram_blwl_wl , -input [2638:2638] sram_blwl_blb ); -grid_2__1__io_4__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[12:12] , -sram_blwl_bl[2638:2638] , -sram_blwl_wl[2638:2638] , -sram_blwl_blb[2638:2638] ); -direct_interc direct_interc_204_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_205_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_4__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[5] ----- -//----- IO Verilog module: grid_2__1__io_5__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_5__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [13:13] gfpga_pad_iopad -, -input [2639:2639] sram_blwl_bl , -input [2639:2639] sram_blwl_wl , -input [2639:2639] sram_blwl_blb ); -wire [2639:2639] sram_blwl_out ; -wire [2639:2639] sram_blwl_outb ; -wire [2639:2639] sram_blwl_2639_configbus0; -wire [2639:2639] sram_blwl_2639_configbus1; -wire [2639:2639] sram_blwl_2639_configbus0_b; -assign sram_blwl_2639_configbus0[2639:2639] = sram_blwl_bl[2639:2639] ; -assign sram_blwl_2639_configbus1[2639:2639] = sram_blwl_wl[2639:2639] ; -assign sram_blwl_2639_configbus0_b[2639:2639] = sram_blwl_blb[2639:2639] ; -iopad iopad_13_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[13], sram_blwl_out[2639:2639] , sram_blwl_outb[2639:2639] ); -sram6T_blwl sram_blwl_2639_ (sram_blwl_out[2639], sram_blwl_out[2639], sram_blwl_outb[2639], sram_blwl_2639_configbus0[2639:2639], sram_blwl_2639_configbus1[2639:2639] , sram_blwl_2639_configbus0_b[2639:2639] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_5__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_5__mode_io_phy_ ----- -module grid_2__1__io_5__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [13:13] gfpga_pad_iopad , -input [2639:2639] sram_blwl_bl , -input [2639:2639] sram_blwl_wl , -input [2639:2639] sram_blwl_blb ); -grid_2__1__io_5__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[13:13] , -sram_blwl_bl[2639:2639] , -sram_blwl_wl[2639:2639] , -sram_blwl_blb[2639:2639] ); -direct_interc direct_interc_206_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_207_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_5__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[6] ----- -//----- IO Verilog module: grid_2__1__io_6__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_6__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [14:14] gfpga_pad_iopad -, -input [2640:2640] sram_blwl_bl , -input [2640:2640] sram_blwl_wl , -input [2640:2640] sram_blwl_blb ); -wire [2640:2640] sram_blwl_out ; -wire [2640:2640] sram_blwl_outb ; -wire [2640:2640] sram_blwl_2640_configbus0; -wire [2640:2640] sram_blwl_2640_configbus1; -wire [2640:2640] sram_blwl_2640_configbus0_b; -assign sram_blwl_2640_configbus0[2640:2640] = sram_blwl_bl[2640:2640] ; -assign sram_blwl_2640_configbus1[2640:2640] = sram_blwl_wl[2640:2640] ; -assign sram_blwl_2640_configbus0_b[2640:2640] = sram_blwl_blb[2640:2640] ; -iopad iopad_14_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[14], sram_blwl_out[2640:2640] , sram_blwl_outb[2640:2640] ); -sram6T_blwl sram_blwl_2640_ (sram_blwl_out[2640], sram_blwl_out[2640], sram_blwl_outb[2640], sram_blwl_2640_configbus0[2640:2640], sram_blwl_2640_configbus1[2640:2640] , sram_blwl_2640_configbus0_b[2640:2640] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_6__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_6__mode_io_phy_ ----- -module grid_2__1__io_6__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [14:14] gfpga_pad_iopad , -input [2640:2640] sram_blwl_bl , -input [2640:2640] sram_blwl_wl , -input [2640:2640] sram_blwl_blb ); -grid_2__1__io_6__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[14:14] , -sram_blwl_bl[2640:2640] , -sram_blwl_wl[2640:2640] , -sram_blwl_blb[2640:2640] ); -direct_interc direct_interc_208_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_209_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_6__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1] type_descriptor: io[7] ----- -//----- IO Verilog module: grid_2__1__io_7__mode_io_phy__iopad_0_ ----- -module grid_2__1__io_7__mode_io_phy__iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -input [0:0] zin -//----- END Global ports of SPICE_MODEL(iopad)----- -, -input wire iopad_0___outpad_0_, -output wire iopad_0___inpad_0_, -inout [15:15] gfpga_pad_iopad -, -input [2641:2641] sram_blwl_bl , -input [2641:2641] sram_blwl_wl , -input [2641:2641] sram_blwl_blb ); -wire [2641:2641] sram_blwl_out ; -wire [2641:2641] sram_blwl_outb ; -wire [2641:2641] sram_blwl_2641_configbus0; -wire [2641:2641] sram_blwl_2641_configbus1; -wire [2641:2641] sram_blwl_2641_configbus0_b; -assign sram_blwl_2641_configbus0[2641:2641] = sram_blwl_bl[2641:2641] ; -assign sram_blwl_2641_configbus1[2641:2641] = sram_blwl_wl[2641:2641] ; -assign sram_blwl_2641_configbus0_b[2641:2641] = sram_blwl_blb[2641:2641] ; -iopad iopad_15_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_,gfpga_pad_iopad[15], sram_blwl_out[2641:2641] , sram_blwl_outb[2641:2641] ); -sram6T_blwl sram_blwl_2641_ (sram_blwl_out[2641], sram_blwl_out[2641], sram_blwl_outb[2641], sram_blwl_2641_configbus0[2641:2641], sram_blwl_2641_configbus1[2641:2641] , sram_blwl_2641_configbus0_b[2641:2641] ); -endmodule -//----- END IO Verilog module: grid_2__1__io_7__mode_io_phy__iopad_0_ ----- - -//----- Physical programmable logic block Verilog module grid_2__1__io_7__mode_io_phy_ ----- -module grid_2__1__io_7__mode_io_phy_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input wire mode_io_phy___outpad_0_, -output wire mode_io_phy___inpad_0_, -input [15:15] gfpga_pad_iopad , -input [2641:2641] sram_blwl_bl , -input [2641:2641] sram_blwl_wl , -input [2641:2641] sram_blwl_blb ); -grid_2__1__io_7__mode_io_phy__iopad_0_ iopad_0_ ( -//----- BEGIN Global ports of SPICE_MODEL(iopad) ----- -zin[0:0] -//----- END Global ports of SPICE_MODEL(iopad)----- -, - iopad_0___outpad_0_, iopad_0___inpad_0_, -gfpga_pad_iopad[15:15] , -sram_blwl_bl[2641:2641] , -sram_blwl_wl[2641:2641] , -sram_blwl_blb[2641:2641] ); -direct_interc direct_interc_210_ (iopad_0___inpad_0_, mode_io_phy___inpad_0_ ); -direct_interc direct_interc_211_ (mode_io_phy___outpad_0_, iopad_0___outpad_0_ ); -endmodule -//----- END Idle programmable logic block Verilog module grid_2__1__io_7__mode_io_phy_ ----- - -//----- END ----- - -//----- Grid[2][1], Capactity: 8 ----- -//----- Top Protocol ----- -module grid_2__1_( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input left_height_0__pin_0_, -output left_height_0__pin_1_, -input left_height_0__pin_2_, -output left_height_0__pin_3_, -input left_height_0__pin_4_, -output left_height_0__pin_5_, -input left_height_0__pin_6_, -output left_height_0__pin_7_, -input left_height_0__pin_8_, -output left_height_0__pin_9_, -input left_height_0__pin_10_, -output left_height_0__pin_11_, -input left_height_0__pin_12_, -output left_height_0__pin_13_, -input left_height_0__pin_14_, -output left_height_0__pin_15_, -input [15:8] gfpga_pad_iopad , -input [2634:2641] sram_blwl_bl , -input [2634:2641] sram_blwl_wl , -input [2634:2641] sram_blwl_blb ); -grid_2__1__io_0__mode_io_phy_ grid_2__1__0_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_0_, -left_height_0__pin_1_ -//---- IOPAD ---- -, -gfpga_pad_iopad[8:8] , -//---- SRAM ---- -sram_blwl_bl[2634:2634] , -sram_blwl_wl[2634:2634] , -sram_blwl_blb[2634:2634] ); -grid_2__1__io_1__mode_io_phy_ grid_2__1__1_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_2_, -left_height_0__pin_3_ -//---- IOPAD ---- -, -gfpga_pad_iopad[9:9] , -//---- SRAM ---- -sram_blwl_bl[2635:2635] , -sram_blwl_wl[2635:2635] , -sram_blwl_blb[2635:2635] ); -grid_2__1__io_2__mode_io_phy_ grid_2__1__2_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_4_, -left_height_0__pin_5_ -//---- IOPAD ---- -, -gfpga_pad_iopad[10:10] , -//---- SRAM ---- -sram_blwl_bl[2636:2636] , -sram_blwl_wl[2636:2636] , -sram_blwl_blb[2636:2636] ); -grid_2__1__io_3__mode_io_phy_ grid_2__1__3_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_6_, -left_height_0__pin_7_ -//---- IOPAD ---- -, -gfpga_pad_iopad[11:11] , -//---- SRAM ---- -sram_blwl_bl[2637:2637] , -sram_blwl_wl[2637:2637] , -sram_blwl_blb[2637:2637] ); -grid_2__1__io_4__mode_io_phy_ grid_2__1__4_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_8_, -left_height_0__pin_9_ -//---- IOPAD ---- -, -gfpga_pad_iopad[12:12] , -//---- SRAM ---- -sram_blwl_bl[2638:2638] , -sram_blwl_wl[2638:2638] , -sram_blwl_blb[2638:2638] ); -grid_2__1__io_5__mode_io_phy_ grid_2__1__5_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_10_, -left_height_0__pin_11_ -//---- IOPAD ---- -, -gfpga_pad_iopad[13:13] , -//---- SRAM ---- -sram_blwl_bl[2639:2639] , -sram_blwl_wl[2639:2639] , -sram_blwl_blb[2639:2639] ); -grid_2__1__io_6__mode_io_phy_ grid_2__1__6_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_12_, -left_height_0__pin_13_ -//---- IOPAD ---- -, -gfpga_pad_iopad[14:14] , -//---- SRAM ---- -sram_blwl_bl[2640:2640] , -sram_blwl_wl[2640:2640] , -sram_blwl_blb[2640:2640] ); -grid_2__1__io_7__mode_io_phy_ grid_2__1__7_ ( -//----- BEGIN Global ports ----- -zin[0:0], -clk[0:0], -Reset[0:0], -Set[0:0] -//----- END Global ports ----- -, -left_height_0__pin_14_, -left_height_0__pin_15_ -//---- IOPAD ---- -, -gfpga_pad_iopad[15:15] , -//---- SRAM ---- -sram_blwl_bl[2641:2641] , -sram_blwl_wl[2641:2641] , -sram_blwl_blb[2641:2641] ); -endmodule -//----- END Top Protocol ----- -//----- END Grid[2][1], Capactity: 8 ----- - diff --git a/examples/verilog_test_example_2/lb/logic_blocks.v b/examples/verilog_test_example_2/lb/logic_blocks.v deleted file mode 100644 index a0146cd6a..000000000 --- a/examples/verilog_test_example_2/lb/logic_blocks.v +++ /dev/null @@ -1,16 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Header file -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -`include "./verilog_test_example_2/lb/grid_1_2.v" -`include "./verilog_test_example_2/lb/grid_1_0.v" -`include "./verilog_test_example_2/lb/grid_2_1.v" -`include "./verilog_test_example_2/lb/grid_0_1.v" -`include "./verilog_test_example_2/lb/grid_1_1.v" diff --git a/examples/verilog_test_example_2/routing/cbx_1_0.v b/examples/verilog_test_example_2/routing/cbx_1_0.v deleted file mode 100644 index 01d4863e8..000000000 --- a/examples/verilog_test_example_2/routing/cbx_1_0.v +++ /dev/null @@ -1,948 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Connection Block - X direction [1][0] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Connection Box -X direction [1][0] ----- -module cbx_1__0_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input chanx_1__0__midout_0_, - -input chanx_1__0__midout_1_, - -input chanx_1__0__midout_2_, - -input chanx_1__0__midout_3_, - -input chanx_1__0__midout_4_, - -input chanx_1__0__midout_5_, - -input chanx_1__0__midout_6_, - -input chanx_1__0__midout_7_, - -input chanx_1__0__midout_8_, - -input chanx_1__0__midout_9_, - -input chanx_1__0__midout_10_, - -input chanx_1__0__midout_11_, - -input chanx_1__0__midout_12_, - -input chanx_1__0__midout_13_, - -input chanx_1__0__midout_14_, - -input chanx_1__0__midout_15_, - -input chanx_1__0__midout_16_, - -input chanx_1__0__midout_17_, - -input chanx_1__0__midout_18_, - -input chanx_1__0__midout_19_, - -input chanx_1__0__midout_20_, - -input chanx_1__0__midout_21_, - -input chanx_1__0__midout_22_, - -input chanx_1__0__midout_23_, - -input chanx_1__0__midout_24_, - -input chanx_1__0__midout_25_, - -input chanx_1__0__midout_26_, - -input chanx_1__0__midout_27_, - -input chanx_1__0__midout_28_, - -input chanx_1__0__midout_29_, - -input chanx_1__0__midout_30_, - -input chanx_1__0__midout_31_, - -input chanx_1__0__midout_32_, - -input chanx_1__0__midout_33_, - -input chanx_1__0__midout_34_, - -input chanx_1__0__midout_35_, - -input chanx_1__0__midout_36_, - -input chanx_1__0__midout_37_, - -input chanx_1__0__midout_38_, - -input chanx_1__0__midout_39_, - -input chanx_1__0__midout_40_, - -input chanx_1__0__midout_41_, - -input chanx_1__0__midout_42_, - -input chanx_1__0__midout_43_, - -input chanx_1__0__midout_44_, - -input chanx_1__0__midout_45_, - -input chanx_1__0__midout_46_, - -input chanx_1__0__midout_47_, - -input chanx_1__0__midout_48_, - -input chanx_1__0__midout_49_, - -input chanx_1__0__midout_50_, - -input chanx_1__0__midout_51_, - -input chanx_1__0__midout_52_, - -input chanx_1__0__midout_53_, - -input chanx_1__0__midout_54_, - -input chanx_1__0__midout_55_, - -input chanx_1__0__midout_56_, - -input chanx_1__0__midout_57_, - -input chanx_1__0__midout_58_, - -input chanx_1__0__midout_59_, - -input chanx_1__0__midout_60_, - -input chanx_1__0__midout_61_, - -input chanx_1__0__midout_62_, - -input chanx_1__0__midout_63_, - -input chanx_1__0__midout_64_, - -input chanx_1__0__midout_65_, - -input chanx_1__0__midout_66_, - -input chanx_1__0__midout_67_, - -input chanx_1__0__midout_68_, - -input chanx_1__0__midout_69_, - -input chanx_1__0__midout_70_, - -input chanx_1__0__midout_71_, - -input chanx_1__0__midout_72_, - -input chanx_1__0__midout_73_, - -input chanx_1__0__midout_74_, - -input chanx_1__0__midout_75_, - -input chanx_1__0__midout_76_, - -input chanx_1__0__midout_77_, - -input chanx_1__0__midout_78_, - -input chanx_1__0__midout_79_, - -input chanx_1__0__midout_80_, - -input chanx_1__0__midout_81_, - -input chanx_1__0__midout_82_, - -input chanx_1__0__midout_83_, - -input chanx_1__0__midout_84_, - -input chanx_1__0__midout_85_, - -input chanx_1__0__midout_86_, - -input chanx_1__0__midout_87_, - -input chanx_1__0__midout_88_, - -input chanx_1__0__midout_89_, - -input chanx_1__0__midout_90_, - -input chanx_1__0__midout_91_, - -input chanx_1__0__midout_92_, - -input chanx_1__0__midout_93_, - -input chanx_1__0__midout_94_, - -input chanx_1__0__midout_95_, - -input chanx_1__0__midout_96_, - -input chanx_1__0__midout_97_, - -input chanx_1__0__midout_98_, - -input chanx_1__0__midout_99_, - -output grid_1__1__pin_0__2__2_, - -output grid_1__1__pin_0__2__6_, - -output grid_1__1__pin_0__2__10_, - -output grid_1__1__pin_0__2__14_, - -output grid_1__1__pin_0__2__18_, - -output grid_1__1__pin_0__2__22_, - -output grid_1__1__pin_0__2__26_, - -output grid_1__1__pin_0__2__30_, - -output grid_1__1__pin_0__2__34_, - -output grid_1__1__pin_0__2__38_, - -output grid_1__1__pin_0__2__50_, - -output grid_1__0__pin_0__0__0_, - -output grid_1__0__pin_0__0__2_, - -output grid_1__0__pin_0__0__4_, - -output grid_1__0__pin_0__0__6_, - -output grid_1__0__pin_0__0__8_, - -output grid_1__0__pin_0__0__10_, - -output grid_1__0__pin_0__0__12_, - -output grid_1__0__pin_0__0__14_, - -input [440:583] sram_blwl_bl , -input [440:583] sram_blwl_wl , -input [440:583] sram_blwl_blb ); -wire [0:15] mux_2level_tapbuf_size16_0_inbus; -assign mux_2level_tapbuf_size16_0_inbus[0] = chanx_1__0__midout_0_; -assign mux_2level_tapbuf_size16_0_inbus[1] = chanx_1__0__midout_1_; -assign mux_2level_tapbuf_size16_0_inbus[2] = chanx_1__0__midout_12_; -assign mux_2level_tapbuf_size16_0_inbus[3] = chanx_1__0__midout_13_; -assign mux_2level_tapbuf_size16_0_inbus[4] = chanx_1__0__midout_24_; -assign mux_2level_tapbuf_size16_0_inbus[5] = chanx_1__0__midout_25_; -assign mux_2level_tapbuf_size16_0_inbus[6] = chanx_1__0__midout_38_; -assign mux_2level_tapbuf_size16_0_inbus[7] = chanx_1__0__midout_39_; -assign mux_2level_tapbuf_size16_0_inbus[8] = chanx_1__0__midout_50_; -assign mux_2level_tapbuf_size16_0_inbus[9] = chanx_1__0__midout_51_; -assign mux_2level_tapbuf_size16_0_inbus[10] = chanx_1__0__midout_62_; -assign mux_2level_tapbuf_size16_0_inbus[11] = chanx_1__0__midout_63_; -assign mux_2level_tapbuf_size16_0_inbus[12] = chanx_1__0__midout_74_; -assign mux_2level_tapbuf_size16_0_inbus[13] = chanx_1__0__midout_75_; -assign mux_2level_tapbuf_size16_0_inbus[14] = chanx_1__0__midout_88_; -assign mux_2level_tapbuf_size16_0_inbus[15] = chanx_1__0__midout_89_; -wire [440:447] mux_2level_tapbuf_size16_0_configbus0; -wire [440:447] mux_2level_tapbuf_size16_0_configbus1; -wire [440:447] mux_2level_tapbuf_size16_0_sram_blwl_out ; -wire [440:447] mux_2level_tapbuf_size16_0_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_0_configbus0[440:447] = sram_blwl_bl[440:447] ; -assign mux_2level_tapbuf_size16_0_configbus1[440:447] = sram_blwl_wl[440:447] ; -wire [440:447] mux_2level_tapbuf_size16_0_configbus0_b; -assign mux_2level_tapbuf_size16_0_configbus0_b[440:447] = sram_blwl_blb[440:447] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_0_ (mux_2level_tapbuf_size16_0_inbus, grid_1__1__pin_0__2__2_, mux_2level_tapbuf_size16_0_sram_blwl_out[440:447] , -mux_2level_tapbuf_size16_0_sram_blwl_outb[440:447] ); -//----- SRAM bits for MUX[0], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_440_ (mux_2level_tapbuf_size16_0_sram_blwl_out[440:440] ,mux_2level_tapbuf_size16_0_sram_blwl_out[440:440] ,mux_2level_tapbuf_size16_0_sram_blwl_outb[440:440] ,mux_2level_tapbuf_size16_0_configbus0[440:440], mux_2level_tapbuf_size16_0_configbus1[440:440] , mux_2level_tapbuf_size16_0_configbus0_b[440:440] ); -sram6T_blwl sram_blwl_441_ (mux_2level_tapbuf_size16_0_sram_blwl_out[441:441] ,mux_2level_tapbuf_size16_0_sram_blwl_out[441:441] ,mux_2level_tapbuf_size16_0_sram_blwl_outb[441:441] ,mux_2level_tapbuf_size16_0_configbus0[441:441], mux_2level_tapbuf_size16_0_configbus1[441:441] , mux_2level_tapbuf_size16_0_configbus0_b[441:441] ); -sram6T_blwl sram_blwl_442_ (mux_2level_tapbuf_size16_0_sram_blwl_out[442:442] ,mux_2level_tapbuf_size16_0_sram_blwl_out[442:442] ,mux_2level_tapbuf_size16_0_sram_blwl_outb[442:442] ,mux_2level_tapbuf_size16_0_configbus0[442:442], mux_2level_tapbuf_size16_0_configbus1[442:442] , mux_2level_tapbuf_size16_0_configbus0_b[442:442] ); -sram6T_blwl sram_blwl_443_ (mux_2level_tapbuf_size16_0_sram_blwl_out[443:443] ,mux_2level_tapbuf_size16_0_sram_blwl_out[443:443] ,mux_2level_tapbuf_size16_0_sram_blwl_outb[443:443] ,mux_2level_tapbuf_size16_0_configbus0[443:443], mux_2level_tapbuf_size16_0_configbus1[443:443] , mux_2level_tapbuf_size16_0_configbus0_b[443:443] ); -sram6T_blwl sram_blwl_444_ (mux_2level_tapbuf_size16_0_sram_blwl_out[444:444] ,mux_2level_tapbuf_size16_0_sram_blwl_out[444:444] ,mux_2level_tapbuf_size16_0_sram_blwl_outb[444:444] ,mux_2level_tapbuf_size16_0_configbus0[444:444], mux_2level_tapbuf_size16_0_configbus1[444:444] , mux_2level_tapbuf_size16_0_configbus0_b[444:444] ); -sram6T_blwl sram_blwl_445_ (mux_2level_tapbuf_size16_0_sram_blwl_out[445:445] ,mux_2level_tapbuf_size16_0_sram_blwl_out[445:445] ,mux_2level_tapbuf_size16_0_sram_blwl_outb[445:445] ,mux_2level_tapbuf_size16_0_configbus0[445:445], mux_2level_tapbuf_size16_0_configbus1[445:445] , mux_2level_tapbuf_size16_0_configbus0_b[445:445] ); -sram6T_blwl sram_blwl_446_ (mux_2level_tapbuf_size16_0_sram_blwl_out[446:446] ,mux_2level_tapbuf_size16_0_sram_blwl_out[446:446] ,mux_2level_tapbuf_size16_0_sram_blwl_outb[446:446] ,mux_2level_tapbuf_size16_0_configbus0[446:446], mux_2level_tapbuf_size16_0_configbus1[446:446] , mux_2level_tapbuf_size16_0_configbus0_b[446:446] ); -sram6T_blwl sram_blwl_447_ (mux_2level_tapbuf_size16_0_sram_blwl_out[447:447] ,mux_2level_tapbuf_size16_0_sram_blwl_out[447:447] ,mux_2level_tapbuf_size16_0_sram_blwl_outb[447:447] ,mux_2level_tapbuf_size16_0_configbus0[447:447], mux_2level_tapbuf_size16_0_configbus1[447:447] , mux_2level_tapbuf_size16_0_configbus0_b[447:447] ); -wire [0:15] mux_2level_tapbuf_size16_1_inbus; -assign mux_2level_tapbuf_size16_1_inbus[0] = chanx_1__0__midout_0_; -assign mux_2level_tapbuf_size16_1_inbus[1] = chanx_1__0__midout_1_; -assign mux_2level_tapbuf_size16_1_inbus[2] = chanx_1__0__midout_14_; -assign mux_2level_tapbuf_size16_1_inbus[3] = chanx_1__0__midout_15_; -assign mux_2level_tapbuf_size16_1_inbus[4] = chanx_1__0__midout_26_; -assign mux_2level_tapbuf_size16_1_inbus[5] = chanx_1__0__midout_27_; -assign mux_2level_tapbuf_size16_1_inbus[6] = chanx_1__0__midout_38_; -assign mux_2level_tapbuf_size16_1_inbus[7] = chanx_1__0__midout_39_; -assign mux_2level_tapbuf_size16_1_inbus[8] = chanx_1__0__midout_50_; -assign mux_2level_tapbuf_size16_1_inbus[9] = chanx_1__0__midout_51_; -assign mux_2level_tapbuf_size16_1_inbus[10] = chanx_1__0__midout_64_; -assign mux_2level_tapbuf_size16_1_inbus[11] = chanx_1__0__midout_65_; -assign mux_2level_tapbuf_size16_1_inbus[12] = chanx_1__0__midout_76_; -assign mux_2level_tapbuf_size16_1_inbus[13] = chanx_1__0__midout_77_; -assign mux_2level_tapbuf_size16_1_inbus[14] = chanx_1__0__midout_88_; -assign mux_2level_tapbuf_size16_1_inbus[15] = chanx_1__0__midout_89_; -wire [448:455] mux_2level_tapbuf_size16_1_configbus0; -wire [448:455] mux_2level_tapbuf_size16_1_configbus1; -wire [448:455] mux_2level_tapbuf_size16_1_sram_blwl_out ; -wire [448:455] mux_2level_tapbuf_size16_1_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_1_configbus0[448:455] = sram_blwl_bl[448:455] ; -assign mux_2level_tapbuf_size16_1_configbus1[448:455] = sram_blwl_wl[448:455] ; -wire [448:455] mux_2level_tapbuf_size16_1_configbus0_b; -assign mux_2level_tapbuf_size16_1_configbus0_b[448:455] = sram_blwl_blb[448:455] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_1_ (mux_2level_tapbuf_size16_1_inbus, grid_1__1__pin_0__2__6_, mux_2level_tapbuf_size16_1_sram_blwl_out[448:455] , -mux_2level_tapbuf_size16_1_sram_blwl_outb[448:455] ); -//----- SRAM bits for MUX[1], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_448_ (mux_2level_tapbuf_size16_1_sram_blwl_out[448:448] ,mux_2level_tapbuf_size16_1_sram_blwl_out[448:448] ,mux_2level_tapbuf_size16_1_sram_blwl_outb[448:448] ,mux_2level_tapbuf_size16_1_configbus0[448:448], mux_2level_tapbuf_size16_1_configbus1[448:448] , mux_2level_tapbuf_size16_1_configbus0_b[448:448] ); -sram6T_blwl sram_blwl_449_ (mux_2level_tapbuf_size16_1_sram_blwl_out[449:449] ,mux_2level_tapbuf_size16_1_sram_blwl_out[449:449] ,mux_2level_tapbuf_size16_1_sram_blwl_outb[449:449] ,mux_2level_tapbuf_size16_1_configbus0[449:449], mux_2level_tapbuf_size16_1_configbus1[449:449] , mux_2level_tapbuf_size16_1_configbus0_b[449:449] ); -sram6T_blwl sram_blwl_450_ (mux_2level_tapbuf_size16_1_sram_blwl_out[450:450] ,mux_2level_tapbuf_size16_1_sram_blwl_out[450:450] ,mux_2level_tapbuf_size16_1_sram_blwl_outb[450:450] ,mux_2level_tapbuf_size16_1_configbus0[450:450], mux_2level_tapbuf_size16_1_configbus1[450:450] , mux_2level_tapbuf_size16_1_configbus0_b[450:450] ); -sram6T_blwl sram_blwl_451_ (mux_2level_tapbuf_size16_1_sram_blwl_out[451:451] ,mux_2level_tapbuf_size16_1_sram_blwl_out[451:451] ,mux_2level_tapbuf_size16_1_sram_blwl_outb[451:451] ,mux_2level_tapbuf_size16_1_configbus0[451:451], mux_2level_tapbuf_size16_1_configbus1[451:451] , mux_2level_tapbuf_size16_1_configbus0_b[451:451] ); -sram6T_blwl sram_blwl_452_ (mux_2level_tapbuf_size16_1_sram_blwl_out[452:452] ,mux_2level_tapbuf_size16_1_sram_blwl_out[452:452] ,mux_2level_tapbuf_size16_1_sram_blwl_outb[452:452] ,mux_2level_tapbuf_size16_1_configbus0[452:452], mux_2level_tapbuf_size16_1_configbus1[452:452] , mux_2level_tapbuf_size16_1_configbus0_b[452:452] ); -sram6T_blwl sram_blwl_453_ (mux_2level_tapbuf_size16_1_sram_blwl_out[453:453] ,mux_2level_tapbuf_size16_1_sram_blwl_out[453:453] ,mux_2level_tapbuf_size16_1_sram_blwl_outb[453:453] ,mux_2level_tapbuf_size16_1_configbus0[453:453], mux_2level_tapbuf_size16_1_configbus1[453:453] , mux_2level_tapbuf_size16_1_configbus0_b[453:453] ); -sram6T_blwl sram_blwl_454_ (mux_2level_tapbuf_size16_1_sram_blwl_out[454:454] ,mux_2level_tapbuf_size16_1_sram_blwl_out[454:454] ,mux_2level_tapbuf_size16_1_sram_blwl_outb[454:454] ,mux_2level_tapbuf_size16_1_configbus0[454:454], mux_2level_tapbuf_size16_1_configbus1[454:454] , mux_2level_tapbuf_size16_1_configbus0_b[454:454] ); -sram6T_blwl sram_blwl_455_ (mux_2level_tapbuf_size16_1_sram_blwl_out[455:455] ,mux_2level_tapbuf_size16_1_sram_blwl_out[455:455] ,mux_2level_tapbuf_size16_1_sram_blwl_outb[455:455] ,mux_2level_tapbuf_size16_1_configbus0[455:455], mux_2level_tapbuf_size16_1_configbus1[455:455] , mux_2level_tapbuf_size16_1_configbus0_b[455:455] ); -wire [0:15] mux_2level_tapbuf_size16_2_inbus; -assign mux_2level_tapbuf_size16_2_inbus[0] = chanx_1__0__midout_2_; -assign mux_2level_tapbuf_size16_2_inbus[1] = chanx_1__0__midout_3_; -assign mux_2level_tapbuf_size16_2_inbus[2] = chanx_1__0__midout_14_; -assign mux_2level_tapbuf_size16_2_inbus[3] = chanx_1__0__midout_15_; -assign mux_2level_tapbuf_size16_2_inbus[4] = chanx_1__0__midout_28_; -assign mux_2level_tapbuf_size16_2_inbus[5] = chanx_1__0__midout_29_; -assign mux_2level_tapbuf_size16_2_inbus[6] = chanx_1__0__midout_40_; -assign mux_2level_tapbuf_size16_2_inbus[7] = chanx_1__0__midout_41_; -assign mux_2level_tapbuf_size16_2_inbus[8] = chanx_1__0__midout_52_; -assign mux_2level_tapbuf_size16_2_inbus[9] = chanx_1__0__midout_53_; -assign mux_2level_tapbuf_size16_2_inbus[10] = chanx_1__0__midout_64_; -assign mux_2level_tapbuf_size16_2_inbus[11] = chanx_1__0__midout_65_; -assign mux_2level_tapbuf_size16_2_inbus[12] = chanx_1__0__midout_78_; -assign mux_2level_tapbuf_size16_2_inbus[13] = chanx_1__0__midout_79_; -assign mux_2level_tapbuf_size16_2_inbus[14] = chanx_1__0__midout_90_; -assign mux_2level_tapbuf_size16_2_inbus[15] = chanx_1__0__midout_91_; -wire [456:463] mux_2level_tapbuf_size16_2_configbus0; -wire [456:463] mux_2level_tapbuf_size16_2_configbus1; -wire [456:463] mux_2level_tapbuf_size16_2_sram_blwl_out ; -wire [456:463] mux_2level_tapbuf_size16_2_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_2_configbus0[456:463] = sram_blwl_bl[456:463] ; -assign mux_2level_tapbuf_size16_2_configbus1[456:463] = sram_blwl_wl[456:463] ; -wire [456:463] mux_2level_tapbuf_size16_2_configbus0_b; -assign mux_2level_tapbuf_size16_2_configbus0_b[456:463] = sram_blwl_blb[456:463] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_2_ (mux_2level_tapbuf_size16_2_inbus, grid_1__1__pin_0__2__10_, mux_2level_tapbuf_size16_2_sram_blwl_out[456:463] , -mux_2level_tapbuf_size16_2_sram_blwl_outb[456:463] ); -//----- SRAM bits for MUX[2], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_456_ (mux_2level_tapbuf_size16_2_sram_blwl_out[456:456] ,mux_2level_tapbuf_size16_2_sram_blwl_out[456:456] ,mux_2level_tapbuf_size16_2_sram_blwl_outb[456:456] ,mux_2level_tapbuf_size16_2_configbus0[456:456], mux_2level_tapbuf_size16_2_configbus1[456:456] , mux_2level_tapbuf_size16_2_configbus0_b[456:456] ); -sram6T_blwl sram_blwl_457_ (mux_2level_tapbuf_size16_2_sram_blwl_out[457:457] ,mux_2level_tapbuf_size16_2_sram_blwl_out[457:457] ,mux_2level_tapbuf_size16_2_sram_blwl_outb[457:457] ,mux_2level_tapbuf_size16_2_configbus0[457:457], mux_2level_tapbuf_size16_2_configbus1[457:457] , mux_2level_tapbuf_size16_2_configbus0_b[457:457] ); -sram6T_blwl sram_blwl_458_ (mux_2level_tapbuf_size16_2_sram_blwl_out[458:458] ,mux_2level_tapbuf_size16_2_sram_blwl_out[458:458] ,mux_2level_tapbuf_size16_2_sram_blwl_outb[458:458] ,mux_2level_tapbuf_size16_2_configbus0[458:458], mux_2level_tapbuf_size16_2_configbus1[458:458] , mux_2level_tapbuf_size16_2_configbus0_b[458:458] ); -sram6T_blwl sram_blwl_459_ (mux_2level_tapbuf_size16_2_sram_blwl_out[459:459] ,mux_2level_tapbuf_size16_2_sram_blwl_out[459:459] ,mux_2level_tapbuf_size16_2_sram_blwl_outb[459:459] ,mux_2level_tapbuf_size16_2_configbus0[459:459], mux_2level_tapbuf_size16_2_configbus1[459:459] , mux_2level_tapbuf_size16_2_configbus0_b[459:459] ); -sram6T_blwl sram_blwl_460_ (mux_2level_tapbuf_size16_2_sram_blwl_out[460:460] ,mux_2level_tapbuf_size16_2_sram_blwl_out[460:460] ,mux_2level_tapbuf_size16_2_sram_blwl_outb[460:460] ,mux_2level_tapbuf_size16_2_configbus0[460:460], mux_2level_tapbuf_size16_2_configbus1[460:460] , mux_2level_tapbuf_size16_2_configbus0_b[460:460] ); -sram6T_blwl sram_blwl_461_ (mux_2level_tapbuf_size16_2_sram_blwl_out[461:461] ,mux_2level_tapbuf_size16_2_sram_blwl_out[461:461] ,mux_2level_tapbuf_size16_2_sram_blwl_outb[461:461] ,mux_2level_tapbuf_size16_2_configbus0[461:461], mux_2level_tapbuf_size16_2_configbus1[461:461] , mux_2level_tapbuf_size16_2_configbus0_b[461:461] ); -sram6T_blwl sram_blwl_462_ (mux_2level_tapbuf_size16_2_sram_blwl_out[462:462] ,mux_2level_tapbuf_size16_2_sram_blwl_out[462:462] ,mux_2level_tapbuf_size16_2_sram_blwl_outb[462:462] ,mux_2level_tapbuf_size16_2_configbus0[462:462], mux_2level_tapbuf_size16_2_configbus1[462:462] , mux_2level_tapbuf_size16_2_configbus0_b[462:462] ); -sram6T_blwl sram_blwl_463_ (mux_2level_tapbuf_size16_2_sram_blwl_out[463:463] ,mux_2level_tapbuf_size16_2_sram_blwl_out[463:463] ,mux_2level_tapbuf_size16_2_sram_blwl_outb[463:463] ,mux_2level_tapbuf_size16_2_configbus0[463:463], mux_2level_tapbuf_size16_2_configbus1[463:463] , mux_2level_tapbuf_size16_2_configbus0_b[463:463] ); -wire [0:15] mux_2level_tapbuf_size16_3_inbus; -assign mux_2level_tapbuf_size16_3_inbus[0] = chanx_1__0__midout_4_; -assign mux_2level_tapbuf_size16_3_inbus[1] = chanx_1__0__midout_5_; -assign mux_2level_tapbuf_size16_3_inbus[2] = chanx_1__0__midout_16_; -assign mux_2level_tapbuf_size16_3_inbus[3] = chanx_1__0__midout_17_; -assign mux_2level_tapbuf_size16_3_inbus[4] = chanx_1__0__midout_28_; -assign mux_2level_tapbuf_size16_3_inbus[5] = chanx_1__0__midout_29_; -assign mux_2level_tapbuf_size16_3_inbus[6] = chanx_1__0__midout_40_; -assign mux_2level_tapbuf_size16_3_inbus[7] = chanx_1__0__midout_41_; -assign mux_2level_tapbuf_size16_3_inbus[8] = chanx_1__0__midout_54_; -assign mux_2level_tapbuf_size16_3_inbus[9] = chanx_1__0__midout_55_; -assign mux_2level_tapbuf_size16_3_inbus[10] = chanx_1__0__midout_66_; -assign mux_2level_tapbuf_size16_3_inbus[11] = chanx_1__0__midout_67_; -assign mux_2level_tapbuf_size16_3_inbus[12] = chanx_1__0__midout_78_; -assign mux_2level_tapbuf_size16_3_inbus[13] = chanx_1__0__midout_79_; -assign mux_2level_tapbuf_size16_3_inbus[14] = chanx_1__0__midout_90_; -assign mux_2level_tapbuf_size16_3_inbus[15] = chanx_1__0__midout_91_; -wire [464:471] mux_2level_tapbuf_size16_3_configbus0; -wire [464:471] mux_2level_tapbuf_size16_3_configbus1; -wire [464:471] mux_2level_tapbuf_size16_3_sram_blwl_out ; -wire [464:471] mux_2level_tapbuf_size16_3_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_3_configbus0[464:471] = sram_blwl_bl[464:471] ; -assign mux_2level_tapbuf_size16_3_configbus1[464:471] = sram_blwl_wl[464:471] ; -wire [464:471] mux_2level_tapbuf_size16_3_configbus0_b; -assign mux_2level_tapbuf_size16_3_configbus0_b[464:471] = sram_blwl_blb[464:471] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_3_ (mux_2level_tapbuf_size16_3_inbus, grid_1__1__pin_0__2__14_, mux_2level_tapbuf_size16_3_sram_blwl_out[464:471] , -mux_2level_tapbuf_size16_3_sram_blwl_outb[464:471] ); -//----- SRAM bits for MUX[3], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_464_ (mux_2level_tapbuf_size16_3_sram_blwl_out[464:464] ,mux_2level_tapbuf_size16_3_sram_blwl_out[464:464] ,mux_2level_tapbuf_size16_3_sram_blwl_outb[464:464] ,mux_2level_tapbuf_size16_3_configbus0[464:464], mux_2level_tapbuf_size16_3_configbus1[464:464] , mux_2level_tapbuf_size16_3_configbus0_b[464:464] ); -sram6T_blwl sram_blwl_465_ (mux_2level_tapbuf_size16_3_sram_blwl_out[465:465] ,mux_2level_tapbuf_size16_3_sram_blwl_out[465:465] ,mux_2level_tapbuf_size16_3_sram_blwl_outb[465:465] ,mux_2level_tapbuf_size16_3_configbus0[465:465], mux_2level_tapbuf_size16_3_configbus1[465:465] , mux_2level_tapbuf_size16_3_configbus0_b[465:465] ); -sram6T_blwl sram_blwl_466_ (mux_2level_tapbuf_size16_3_sram_blwl_out[466:466] ,mux_2level_tapbuf_size16_3_sram_blwl_out[466:466] ,mux_2level_tapbuf_size16_3_sram_blwl_outb[466:466] ,mux_2level_tapbuf_size16_3_configbus0[466:466], mux_2level_tapbuf_size16_3_configbus1[466:466] , mux_2level_tapbuf_size16_3_configbus0_b[466:466] ); -sram6T_blwl sram_blwl_467_ (mux_2level_tapbuf_size16_3_sram_blwl_out[467:467] ,mux_2level_tapbuf_size16_3_sram_blwl_out[467:467] ,mux_2level_tapbuf_size16_3_sram_blwl_outb[467:467] ,mux_2level_tapbuf_size16_3_configbus0[467:467], mux_2level_tapbuf_size16_3_configbus1[467:467] , mux_2level_tapbuf_size16_3_configbus0_b[467:467] ); -sram6T_blwl sram_blwl_468_ (mux_2level_tapbuf_size16_3_sram_blwl_out[468:468] ,mux_2level_tapbuf_size16_3_sram_blwl_out[468:468] ,mux_2level_tapbuf_size16_3_sram_blwl_outb[468:468] ,mux_2level_tapbuf_size16_3_configbus0[468:468], mux_2level_tapbuf_size16_3_configbus1[468:468] , mux_2level_tapbuf_size16_3_configbus0_b[468:468] ); -sram6T_blwl sram_blwl_469_ (mux_2level_tapbuf_size16_3_sram_blwl_out[469:469] ,mux_2level_tapbuf_size16_3_sram_blwl_out[469:469] ,mux_2level_tapbuf_size16_3_sram_blwl_outb[469:469] ,mux_2level_tapbuf_size16_3_configbus0[469:469], mux_2level_tapbuf_size16_3_configbus1[469:469] , mux_2level_tapbuf_size16_3_configbus0_b[469:469] ); -sram6T_blwl sram_blwl_470_ (mux_2level_tapbuf_size16_3_sram_blwl_out[470:470] ,mux_2level_tapbuf_size16_3_sram_blwl_out[470:470] ,mux_2level_tapbuf_size16_3_sram_blwl_outb[470:470] ,mux_2level_tapbuf_size16_3_configbus0[470:470], mux_2level_tapbuf_size16_3_configbus1[470:470] , mux_2level_tapbuf_size16_3_configbus0_b[470:470] ); -sram6T_blwl sram_blwl_471_ (mux_2level_tapbuf_size16_3_sram_blwl_out[471:471] ,mux_2level_tapbuf_size16_3_sram_blwl_out[471:471] ,mux_2level_tapbuf_size16_3_sram_blwl_outb[471:471] ,mux_2level_tapbuf_size16_3_configbus0[471:471], mux_2level_tapbuf_size16_3_configbus1[471:471] , mux_2level_tapbuf_size16_3_configbus0_b[471:471] ); -wire [0:15] mux_2level_tapbuf_size16_4_inbus; -assign mux_2level_tapbuf_size16_4_inbus[0] = chanx_1__0__midout_4_; -assign mux_2level_tapbuf_size16_4_inbus[1] = chanx_1__0__midout_5_; -assign mux_2level_tapbuf_size16_4_inbus[2] = chanx_1__0__midout_18_; -assign mux_2level_tapbuf_size16_4_inbus[3] = chanx_1__0__midout_19_; -assign mux_2level_tapbuf_size16_4_inbus[4] = chanx_1__0__midout_30_; -assign mux_2level_tapbuf_size16_4_inbus[5] = chanx_1__0__midout_31_; -assign mux_2level_tapbuf_size16_4_inbus[6] = chanx_1__0__midout_42_; -assign mux_2level_tapbuf_size16_4_inbus[7] = chanx_1__0__midout_43_; -assign mux_2level_tapbuf_size16_4_inbus[8] = chanx_1__0__midout_54_; -assign mux_2level_tapbuf_size16_4_inbus[9] = chanx_1__0__midout_55_; -assign mux_2level_tapbuf_size16_4_inbus[10] = chanx_1__0__midout_68_; -assign mux_2level_tapbuf_size16_4_inbus[11] = chanx_1__0__midout_69_; -assign mux_2level_tapbuf_size16_4_inbus[12] = chanx_1__0__midout_80_; -assign mux_2level_tapbuf_size16_4_inbus[13] = chanx_1__0__midout_81_; -assign mux_2level_tapbuf_size16_4_inbus[14] = chanx_1__0__midout_92_; -assign mux_2level_tapbuf_size16_4_inbus[15] = chanx_1__0__midout_93_; -wire [472:479] mux_2level_tapbuf_size16_4_configbus0; -wire [472:479] mux_2level_tapbuf_size16_4_configbus1; -wire [472:479] mux_2level_tapbuf_size16_4_sram_blwl_out ; -wire [472:479] mux_2level_tapbuf_size16_4_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_4_configbus0[472:479] = sram_blwl_bl[472:479] ; -assign mux_2level_tapbuf_size16_4_configbus1[472:479] = sram_blwl_wl[472:479] ; -wire [472:479] mux_2level_tapbuf_size16_4_configbus0_b; -assign mux_2level_tapbuf_size16_4_configbus0_b[472:479] = sram_blwl_blb[472:479] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_4_ (mux_2level_tapbuf_size16_4_inbus, grid_1__1__pin_0__2__18_, mux_2level_tapbuf_size16_4_sram_blwl_out[472:479] , -mux_2level_tapbuf_size16_4_sram_blwl_outb[472:479] ); -//----- SRAM bits for MUX[4], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_472_ (mux_2level_tapbuf_size16_4_sram_blwl_out[472:472] ,mux_2level_tapbuf_size16_4_sram_blwl_out[472:472] ,mux_2level_tapbuf_size16_4_sram_blwl_outb[472:472] ,mux_2level_tapbuf_size16_4_configbus0[472:472], mux_2level_tapbuf_size16_4_configbus1[472:472] , mux_2level_tapbuf_size16_4_configbus0_b[472:472] ); -sram6T_blwl sram_blwl_473_ (mux_2level_tapbuf_size16_4_sram_blwl_out[473:473] ,mux_2level_tapbuf_size16_4_sram_blwl_out[473:473] ,mux_2level_tapbuf_size16_4_sram_blwl_outb[473:473] ,mux_2level_tapbuf_size16_4_configbus0[473:473], mux_2level_tapbuf_size16_4_configbus1[473:473] , mux_2level_tapbuf_size16_4_configbus0_b[473:473] ); -sram6T_blwl sram_blwl_474_ (mux_2level_tapbuf_size16_4_sram_blwl_out[474:474] ,mux_2level_tapbuf_size16_4_sram_blwl_out[474:474] ,mux_2level_tapbuf_size16_4_sram_blwl_outb[474:474] ,mux_2level_tapbuf_size16_4_configbus0[474:474], mux_2level_tapbuf_size16_4_configbus1[474:474] , mux_2level_tapbuf_size16_4_configbus0_b[474:474] ); -sram6T_blwl sram_blwl_475_ (mux_2level_tapbuf_size16_4_sram_blwl_out[475:475] ,mux_2level_tapbuf_size16_4_sram_blwl_out[475:475] ,mux_2level_tapbuf_size16_4_sram_blwl_outb[475:475] ,mux_2level_tapbuf_size16_4_configbus0[475:475], mux_2level_tapbuf_size16_4_configbus1[475:475] , mux_2level_tapbuf_size16_4_configbus0_b[475:475] ); -sram6T_blwl sram_blwl_476_ (mux_2level_tapbuf_size16_4_sram_blwl_out[476:476] ,mux_2level_tapbuf_size16_4_sram_blwl_out[476:476] ,mux_2level_tapbuf_size16_4_sram_blwl_outb[476:476] ,mux_2level_tapbuf_size16_4_configbus0[476:476], mux_2level_tapbuf_size16_4_configbus1[476:476] , mux_2level_tapbuf_size16_4_configbus0_b[476:476] ); -sram6T_blwl sram_blwl_477_ (mux_2level_tapbuf_size16_4_sram_blwl_out[477:477] ,mux_2level_tapbuf_size16_4_sram_blwl_out[477:477] ,mux_2level_tapbuf_size16_4_sram_blwl_outb[477:477] ,mux_2level_tapbuf_size16_4_configbus0[477:477], mux_2level_tapbuf_size16_4_configbus1[477:477] , mux_2level_tapbuf_size16_4_configbus0_b[477:477] ); -sram6T_blwl sram_blwl_478_ (mux_2level_tapbuf_size16_4_sram_blwl_out[478:478] ,mux_2level_tapbuf_size16_4_sram_blwl_out[478:478] ,mux_2level_tapbuf_size16_4_sram_blwl_outb[478:478] ,mux_2level_tapbuf_size16_4_configbus0[478:478], mux_2level_tapbuf_size16_4_configbus1[478:478] , mux_2level_tapbuf_size16_4_configbus0_b[478:478] ); -sram6T_blwl sram_blwl_479_ (mux_2level_tapbuf_size16_4_sram_blwl_out[479:479] ,mux_2level_tapbuf_size16_4_sram_blwl_out[479:479] ,mux_2level_tapbuf_size16_4_sram_blwl_outb[479:479] ,mux_2level_tapbuf_size16_4_configbus0[479:479], mux_2level_tapbuf_size16_4_configbus1[479:479] , mux_2level_tapbuf_size16_4_configbus0_b[479:479] ); -wire [0:15] mux_2level_tapbuf_size16_5_inbus; -assign mux_2level_tapbuf_size16_5_inbus[0] = chanx_1__0__midout_6_; -assign mux_2level_tapbuf_size16_5_inbus[1] = chanx_1__0__midout_7_; -assign mux_2level_tapbuf_size16_5_inbus[2] = chanx_1__0__midout_18_; -assign mux_2level_tapbuf_size16_5_inbus[3] = chanx_1__0__midout_19_; -assign mux_2level_tapbuf_size16_5_inbus[4] = chanx_1__0__midout_30_; -assign mux_2level_tapbuf_size16_5_inbus[5] = chanx_1__0__midout_31_; -assign mux_2level_tapbuf_size16_5_inbus[6] = chanx_1__0__midout_44_; -assign mux_2level_tapbuf_size16_5_inbus[7] = chanx_1__0__midout_45_; -assign mux_2level_tapbuf_size16_5_inbus[8] = chanx_1__0__midout_56_; -assign mux_2level_tapbuf_size16_5_inbus[9] = chanx_1__0__midout_57_; -assign mux_2level_tapbuf_size16_5_inbus[10] = chanx_1__0__midout_68_; -assign mux_2level_tapbuf_size16_5_inbus[11] = chanx_1__0__midout_69_; -assign mux_2level_tapbuf_size16_5_inbus[12] = chanx_1__0__midout_80_; -assign mux_2level_tapbuf_size16_5_inbus[13] = chanx_1__0__midout_81_; -assign mux_2level_tapbuf_size16_5_inbus[14] = chanx_1__0__midout_94_; -assign mux_2level_tapbuf_size16_5_inbus[15] = chanx_1__0__midout_95_; -wire [480:487] mux_2level_tapbuf_size16_5_configbus0; -wire [480:487] mux_2level_tapbuf_size16_5_configbus1; -wire [480:487] mux_2level_tapbuf_size16_5_sram_blwl_out ; -wire [480:487] mux_2level_tapbuf_size16_5_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_5_configbus0[480:487] = sram_blwl_bl[480:487] ; -assign mux_2level_tapbuf_size16_5_configbus1[480:487] = sram_blwl_wl[480:487] ; -wire [480:487] mux_2level_tapbuf_size16_5_configbus0_b; -assign mux_2level_tapbuf_size16_5_configbus0_b[480:487] = sram_blwl_blb[480:487] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_5_ (mux_2level_tapbuf_size16_5_inbus, grid_1__1__pin_0__2__22_, mux_2level_tapbuf_size16_5_sram_blwl_out[480:487] , -mux_2level_tapbuf_size16_5_sram_blwl_outb[480:487] ); -//----- SRAM bits for MUX[5], level=2, select_path_id=3. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10000001----- -sram6T_blwl sram_blwl_480_ (mux_2level_tapbuf_size16_5_sram_blwl_out[480:480] ,mux_2level_tapbuf_size16_5_sram_blwl_out[480:480] ,mux_2level_tapbuf_size16_5_sram_blwl_outb[480:480] ,mux_2level_tapbuf_size16_5_configbus0[480:480], mux_2level_tapbuf_size16_5_configbus1[480:480] , mux_2level_tapbuf_size16_5_configbus0_b[480:480] ); -sram6T_blwl sram_blwl_481_ (mux_2level_tapbuf_size16_5_sram_blwl_out[481:481] ,mux_2level_tapbuf_size16_5_sram_blwl_out[481:481] ,mux_2level_tapbuf_size16_5_sram_blwl_outb[481:481] ,mux_2level_tapbuf_size16_5_configbus0[481:481], mux_2level_tapbuf_size16_5_configbus1[481:481] , mux_2level_tapbuf_size16_5_configbus0_b[481:481] ); -sram6T_blwl sram_blwl_482_ (mux_2level_tapbuf_size16_5_sram_blwl_out[482:482] ,mux_2level_tapbuf_size16_5_sram_blwl_out[482:482] ,mux_2level_tapbuf_size16_5_sram_blwl_outb[482:482] ,mux_2level_tapbuf_size16_5_configbus0[482:482], mux_2level_tapbuf_size16_5_configbus1[482:482] , mux_2level_tapbuf_size16_5_configbus0_b[482:482] ); -sram6T_blwl sram_blwl_483_ (mux_2level_tapbuf_size16_5_sram_blwl_out[483:483] ,mux_2level_tapbuf_size16_5_sram_blwl_out[483:483] ,mux_2level_tapbuf_size16_5_sram_blwl_outb[483:483] ,mux_2level_tapbuf_size16_5_configbus0[483:483], mux_2level_tapbuf_size16_5_configbus1[483:483] , mux_2level_tapbuf_size16_5_configbus0_b[483:483] ); -sram6T_blwl sram_blwl_484_ (mux_2level_tapbuf_size16_5_sram_blwl_out[484:484] ,mux_2level_tapbuf_size16_5_sram_blwl_out[484:484] ,mux_2level_tapbuf_size16_5_sram_blwl_outb[484:484] ,mux_2level_tapbuf_size16_5_configbus0[484:484], mux_2level_tapbuf_size16_5_configbus1[484:484] , mux_2level_tapbuf_size16_5_configbus0_b[484:484] ); -sram6T_blwl sram_blwl_485_ (mux_2level_tapbuf_size16_5_sram_blwl_out[485:485] ,mux_2level_tapbuf_size16_5_sram_blwl_out[485:485] ,mux_2level_tapbuf_size16_5_sram_blwl_outb[485:485] ,mux_2level_tapbuf_size16_5_configbus0[485:485], mux_2level_tapbuf_size16_5_configbus1[485:485] , mux_2level_tapbuf_size16_5_configbus0_b[485:485] ); -sram6T_blwl sram_blwl_486_ (mux_2level_tapbuf_size16_5_sram_blwl_out[486:486] ,mux_2level_tapbuf_size16_5_sram_blwl_out[486:486] ,mux_2level_tapbuf_size16_5_sram_blwl_outb[486:486] ,mux_2level_tapbuf_size16_5_configbus0[486:486], mux_2level_tapbuf_size16_5_configbus1[486:486] , mux_2level_tapbuf_size16_5_configbus0_b[486:486] ); -sram6T_blwl sram_blwl_487_ (mux_2level_tapbuf_size16_5_sram_blwl_out[487:487] ,mux_2level_tapbuf_size16_5_sram_blwl_out[487:487] ,mux_2level_tapbuf_size16_5_sram_blwl_outb[487:487] ,mux_2level_tapbuf_size16_5_configbus0[487:487], mux_2level_tapbuf_size16_5_configbus1[487:487] , mux_2level_tapbuf_size16_5_configbus0_b[487:487] ); -wire [0:15] mux_2level_tapbuf_size16_6_inbus; -assign mux_2level_tapbuf_size16_6_inbus[0] = chanx_1__0__midout_8_; -assign mux_2level_tapbuf_size16_6_inbus[1] = chanx_1__0__midout_9_; -assign mux_2level_tapbuf_size16_6_inbus[2] = chanx_1__0__midout_20_; -assign mux_2level_tapbuf_size16_6_inbus[3] = chanx_1__0__midout_21_; -assign mux_2level_tapbuf_size16_6_inbus[4] = chanx_1__0__midout_32_; -assign mux_2level_tapbuf_size16_6_inbus[5] = chanx_1__0__midout_33_; -assign mux_2level_tapbuf_size16_6_inbus[6] = chanx_1__0__midout_44_; -assign mux_2level_tapbuf_size16_6_inbus[7] = chanx_1__0__midout_45_; -assign mux_2level_tapbuf_size16_6_inbus[8] = chanx_1__0__midout_58_; -assign mux_2level_tapbuf_size16_6_inbus[9] = chanx_1__0__midout_59_; -assign mux_2level_tapbuf_size16_6_inbus[10] = chanx_1__0__midout_70_; -assign mux_2level_tapbuf_size16_6_inbus[11] = chanx_1__0__midout_71_; -assign mux_2level_tapbuf_size16_6_inbus[12] = chanx_1__0__midout_82_; -assign mux_2level_tapbuf_size16_6_inbus[13] = chanx_1__0__midout_83_; -assign mux_2level_tapbuf_size16_6_inbus[14] = chanx_1__0__midout_94_; -assign mux_2level_tapbuf_size16_6_inbus[15] = chanx_1__0__midout_95_; -wire [488:495] mux_2level_tapbuf_size16_6_configbus0; -wire [488:495] mux_2level_tapbuf_size16_6_configbus1; -wire [488:495] mux_2level_tapbuf_size16_6_sram_blwl_out ; -wire [488:495] mux_2level_tapbuf_size16_6_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_6_configbus0[488:495] = sram_blwl_bl[488:495] ; -assign mux_2level_tapbuf_size16_6_configbus1[488:495] = sram_blwl_wl[488:495] ; -wire [488:495] mux_2level_tapbuf_size16_6_configbus0_b; -assign mux_2level_tapbuf_size16_6_configbus0_b[488:495] = sram_blwl_blb[488:495] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_6_ (mux_2level_tapbuf_size16_6_inbus, grid_1__1__pin_0__2__26_, mux_2level_tapbuf_size16_6_sram_blwl_out[488:495] , -mux_2level_tapbuf_size16_6_sram_blwl_outb[488:495] ); -//----- SRAM bits for MUX[6], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_488_ (mux_2level_tapbuf_size16_6_sram_blwl_out[488:488] ,mux_2level_tapbuf_size16_6_sram_blwl_out[488:488] ,mux_2level_tapbuf_size16_6_sram_blwl_outb[488:488] ,mux_2level_tapbuf_size16_6_configbus0[488:488], mux_2level_tapbuf_size16_6_configbus1[488:488] , mux_2level_tapbuf_size16_6_configbus0_b[488:488] ); -sram6T_blwl sram_blwl_489_ (mux_2level_tapbuf_size16_6_sram_blwl_out[489:489] ,mux_2level_tapbuf_size16_6_sram_blwl_out[489:489] ,mux_2level_tapbuf_size16_6_sram_blwl_outb[489:489] ,mux_2level_tapbuf_size16_6_configbus0[489:489], mux_2level_tapbuf_size16_6_configbus1[489:489] , mux_2level_tapbuf_size16_6_configbus0_b[489:489] ); -sram6T_blwl sram_blwl_490_ (mux_2level_tapbuf_size16_6_sram_blwl_out[490:490] ,mux_2level_tapbuf_size16_6_sram_blwl_out[490:490] ,mux_2level_tapbuf_size16_6_sram_blwl_outb[490:490] ,mux_2level_tapbuf_size16_6_configbus0[490:490], mux_2level_tapbuf_size16_6_configbus1[490:490] , mux_2level_tapbuf_size16_6_configbus0_b[490:490] ); -sram6T_blwl sram_blwl_491_ (mux_2level_tapbuf_size16_6_sram_blwl_out[491:491] ,mux_2level_tapbuf_size16_6_sram_blwl_out[491:491] ,mux_2level_tapbuf_size16_6_sram_blwl_outb[491:491] ,mux_2level_tapbuf_size16_6_configbus0[491:491], mux_2level_tapbuf_size16_6_configbus1[491:491] , mux_2level_tapbuf_size16_6_configbus0_b[491:491] ); -sram6T_blwl sram_blwl_492_ (mux_2level_tapbuf_size16_6_sram_blwl_out[492:492] ,mux_2level_tapbuf_size16_6_sram_blwl_out[492:492] ,mux_2level_tapbuf_size16_6_sram_blwl_outb[492:492] ,mux_2level_tapbuf_size16_6_configbus0[492:492], mux_2level_tapbuf_size16_6_configbus1[492:492] , mux_2level_tapbuf_size16_6_configbus0_b[492:492] ); -sram6T_blwl sram_blwl_493_ (mux_2level_tapbuf_size16_6_sram_blwl_out[493:493] ,mux_2level_tapbuf_size16_6_sram_blwl_out[493:493] ,mux_2level_tapbuf_size16_6_sram_blwl_outb[493:493] ,mux_2level_tapbuf_size16_6_configbus0[493:493], mux_2level_tapbuf_size16_6_configbus1[493:493] , mux_2level_tapbuf_size16_6_configbus0_b[493:493] ); -sram6T_blwl sram_blwl_494_ (mux_2level_tapbuf_size16_6_sram_blwl_out[494:494] ,mux_2level_tapbuf_size16_6_sram_blwl_out[494:494] ,mux_2level_tapbuf_size16_6_sram_blwl_outb[494:494] ,mux_2level_tapbuf_size16_6_configbus0[494:494], mux_2level_tapbuf_size16_6_configbus1[494:494] , mux_2level_tapbuf_size16_6_configbus0_b[494:494] ); -sram6T_blwl sram_blwl_495_ (mux_2level_tapbuf_size16_6_sram_blwl_out[495:495] ,mux_2level_tapbuf_size16_6_sram_blwl_out[495:495] ,mux_2level_tapbuf_size16_6_sram_blwl_outb[495:495] ,mux_2level_tapbuf_size16_6_configbus0[495:495], mux_2level_tapbuf_size16_6_configbus1[495:495] , mux_2level_tapbuf_size16_6_configbus0_b[495:495] ); -wire [0:15] mux_2level_tapbuf_size16_7_inbus; -assign mux_2level_tapbuf_size16_7_inbus[0] = chanx_1__0__midout_8_; -assign mux_2level_tapbuf_size16_7_inbus[1] = chanx_1__0__midout_9_; -assign mux_2level_tapbuf_size16_7_inbus[2] = chanx_1__0__midout_20_; -assign mux_2level_tapbuf_size16_7_inbus[3] = chanx_1__0__midout_21_; -assign mux_2level_tapbuf_size16_7_inbus[4] = chanx_1__0__midout_34_; -assign mux_2level_tapbuf_size16_7_inbus[5] = chanx_1__0__midout_35_; -assign mux_2level_tapbuf_size16_7_inbus[6] = chanx_1__0__midout_46_; -assign mux_2level_tapbuf_size16_7_inbus[7] = chanx_1__0__midout_47_; -assign mux_2level_tapbuf_size16_7_inbus[8] = chanx_1__0__midout_58_; -assign mux_2level_tapbuf_size16_7_inbus[9] = chanx_1__0__midout_59_; -assign mux_2level_tapbuf_size16_7_inbus[10] = chanx_1__0__midout_70_; -assign mux_2level_tapbuf_size16_7_inbus[11] = chanx_1__0__midout_71_; -assign mux_2level_tapbuf_size16_7_inbus[12] = chanx_1__0__midout_84_; -assign mux_2level_tapbuf_size16_7_inbus[13] = chanx_1__0__midout_85_; -assign mux_2level_tapbuf_size16_7_inbus[14] = chanx_1__0__midout_96_; -assign mux_2level_tapbuf_size16_7_inbus[15] = chanx_1__0__midout_97_; -wire [496:503] mux_2level_tapbuf_size16_7_configbus0; -wire [496:503] mux_2level_tapbuf_size16_7_configbus1; -wire [496:503] mux_2level_tapbuf_size16_7_sram_blwl_out ; -wire [496:503] mux_2level_tapbuf_size16_7_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_7_configbus0[496:503] = sram_blwl_bl[496:503] ; -assign mux_2level_tapbuf_size16_7_configbus1[496:503] = sram_blwl_wl[496:503] ; -wire [496:503] mux_2level_tapbuf_size16_7_configbus0_b; -assign mux_2level_tapbuf_size16_7_configbus0_b[496:503] = sram_blwl_blb[496:503] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_7_ (mux_2level_tapbuf_size16_7_inbus, grid_1__1__pin_0__2__30_, mux_2level_tapbuf_size16_7_sram_blwl_out[496:503] , -mux_2level_tapbuf_size16_7_sram_blwl_outb[496:503] ); -//----- SRAM bits for MUX[7], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_496_ (mux_2level_tapbuf_size16_7_sram_blwl_out[496:496] ,mux_2level_tapbuf_size16_7_sram_blwl_out[496:496] ,mux_2level_tapbuf_size16_7_sram_blwl_outb[496:496] ,mux_2level_tapbuf_size16_7_configbus0[496:496], mux_2level_tapbuf_size16_7_configbus1[496:496] , mux_2level_tapbuf_size16_7_configbus0_b[496:496] ); -sram6T_blwl sram_blwl_497_ (mux_2level_tapbuf_size16_7_sram_blwl_out[497:497] ,mux_2level_tapbuf_size16_7_sram_blwl_out[497:497] ,mux_2level_tapbuf_size16_7_sram_blwl_outb[497:497] ,mux_2level_tapbuf_size16_7_configbus0[497:497], mux_2level_tapbuf_size16_7_configbus1[497:497] , mux_2level_tapbuf_size16_7_configbus0_b[497:497] ); -sram6T_blwl sram_blwl_498_ (mux_2level_tapbuf_size16_7_sram_blwl_out[498:498] ,mux_2level_tapbuf_size16_7_sram_blwl_out[498:498] ,mux_2level_tapbuf_size16_7_sram_blwl_outb[498:498] ,mux_2level_tapbuf_size16_7_configbus0[498:498], mux_2level_tapbuf_size16_7_configbus1[498:498] , mux_2level_tapbuf_size16_7_configbus0_b[498:498] ); -sram6T_blwl sram_blwl_499_ (mux_2level_tapbuf_size16_7_sram_blwl_out[499:499] ,mux_2level_tapbuf_size16_7_sram_blwl_out[499:499] ,mux_2level_tapbuf_size16_7_sram_blwl_outb[499:499] ,mux_2level_tapbuf_size16_7_configbus0[499:499], mux_2level_tapbuf_size16_7_configbus1[499:499] , mux_2level_tapbuf_size16_7_configbus0_b[499:499] ); -sram6T_blwl sram_blwl_500_ (mux_2level_tapbuf_size16_7_sram_blwl_out[500:500] ,mux_2level_tapbuf_size16_7_sram_blwl_out[500:500] ,mux_2level_tapbuf_size16_7_sram_blwl_outb[500:500] ,mux_2level_tapbuf_size16_7_configbus0[500:500], mux_2level_tapbuf_size16_7_configbus1[500:500] , mux_2level_tapbuf_size16_7_configbus0_b[500:500] ); -sram6T_blwl sram_blwl_501_ (mux_2level_tapbuf_size16_7_sram_blwl_out[501:501] ,mux_2level_tapbuf_size16_7_sram_blwl_out[501:501] ,mux_2level_tapbuf_size16_7_sram_blwl_outb[501:501] ,mux_2level_tapbuf_size16_7_configbus0[501:501], mux_2level_tapbuf_size16_7_configbus1[501:501] , mux_2level_tapbuf_size16_7_configbus0_b[501:501] ); -sram6T_blwl sram_blwl_502_ (mux_2level_tapbuf_size16_7_sram_blwl_out[502:502] ,mux_2level_tapbuf_size16_7_sram_blwl_out[502:502] ,mux_2level_tapbuf_size16_7_sram_blwl_outb[502:502] ,mux_2level_tapbuf_size16_7_configbus0[502:502], mux_2level_tapbuf_size16_7_configbus1[502:502] , mux_2level_tapbuf_size16_7_configbus0_b[502:502] ); -sram6T_blwl sram_blwl_503_ (mux_2level_tapbuf_size16_7_sram_blwl_out[503:503] ,mux_2level_tapbuf_size16_7_sram_blwl_out[503:503] ,mux_2level_tapbuf_size16_7_sram_blwl_outb[503:503] ,mux_2level_tapbuf_size16_7_configbus0[503:503], mux_2level_tapbuf_size16_7_configbus1[503:503] , mux_2level_tapbuf_size16_7_configbus0_b[503:503] ); -wire [0:15] mux_2level_tapbuf_size16_8_inbus; -assign mux_2level_tapbuf_size16_8_inbus[0] = chanx_1__0__midout_10_; -assign mux_2level_tapbuf_size16_8_inbus[1] = chanx_1__0__midout_11_; -assign mux_2level_tapbuf_size16_8_inbus[2] = chanx_1__0__midout_22_; -assign mux_2level_tapbuf_size16_8_inbus[3] = chanx_1__0__midout_23_; -assign mux_2level_tapbuf_size16_8_inbus[4] = chanx_1__0__midout_34_; -assign mux_2level_tapbuf_size16_8_inbus[5] = chanx_1__0__midout_35_; -assign mux_2level_tapbuf_size16_8_inbus[6] = chanx_1__0__midout_48_; -assign mux_2level_tapbuf_size16_8_inbus[7] = chanx_1__0__midout_49_; -assign mux_2level_tapbuf_size16_8_inbus[8] = chanx_1__0__midout_60_; -assign mux_2level_tapbuf_size16_8_inbus[9] = chanx_1__0__midout_61_; -assign mux_2level_tapbuf_size16_8_inbus[10] = chanx_1__0__midout_72_; -assign mux_2level_tapbuf_size16_8_inbus[11] = chanx_1__0__midout_73_; -assign mux_2level_tapbuf_size16_8_inbus[12] = chanx_1__0__midout_84_; -assign mux_2level_tapbuf_size16_8_inbus[13] = chanx_1__0__midout_85_; -assign mux_2level_tapbuf_size16_8_inbus[14] = chanx_1__0__midout_98_; -assign mux_2level_tapbuf_size16_8_inbus[15] = chanx_1__0__midout_99_; -wire [504:511] mux_2level_tapbuf_size16_8_configbus0; -wire [504:511] mux_2level_tapbuf_size16_8_configbus1; -wire [504:511] mux_2level_tapbuf_size16_8_sram_blwl_out ; -wire [504:511] mux_2level_tapbuf_size16_8_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_8_configbus0[504:511] = sram_blwl_bl[504:511] ; -assign mux_2level_tapbuf_size16_8_configbus1[504:511] = sram_blwl_wl[504:511] ; -wire [504:511] mux_2level_tapbuf_size16_8_configbus0_b; -assign mux_2level_tapbuf_size16_8_configbus0_b[504:511] = sram_blwl_blb[504:511] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_8_ (mux_2level_tapbuf_size16_8_inbus, grid_1__1__pin_0__2__34_, mux_2level_tapbuf_size16_8_sram_blwl_out[504:511] , -mux_2level_tapbuf_size16_8_sram_blwl_outb[504:511] ); -//----- SRAM bits for MUX[8], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_504_ (mux_2level_tapbuf_size16_8_sram_blwl_out[504:504] ,mux_2level_tapbuf_size16_8_sram_blwl_out[504:504] ,mux_2level_tapbuf_size16_8_sram_blwl_outb[504:504] ,mux_2level_tapbuf_size16_8_configbus0[504:504], mux_2level_tapbuf_size16_8_configbus1[504:504] , mux_2level_tapbuf_size16_8_configbus0_b[504:504] ); -sram6T_blwl sram_blwl_505_ (mux_2level_tapbuf_size16_8_sram_blwl_out[505:505] ,mux_2level_tapbuf_size16_8_sram_blwl_out[505:505] ,mux_2level_tapbuf_size16_8_sram_blwl_outb[505:505] ,mux_2level_tapbuf_size16_8_configbus0[505:505], mux_2level_tapbuf_size16_8_configbus1[505:505] , mux_2level_tapbuf_size16_8_configbus0_b[505:505] ); -sram6T_blwl sram_blwl_506_ (mux_2level_tapbuf_size16_8_sram_blwl_out[506:506] ,mux_2level_tapbuf_size16_8_sram_blwl_out[506:506] ,mux_2level_tapbuf_size16_8_sram_blwl_outb[506:506] ,mux_2level_tapbuf_size16_8_configbus0[506:506], mux_2level_tapbuf_size16_8_configbus1[506:506] , mux_2level_tapbuf_size16_8_configbus0_b[506:506] ); -sram6T_blwl sram_blwl_507_ (mux_2level_tapbuf_size16_8_sram_blwl_out[507:507] ,mux_2level_tapbuf_size16_8_sram_blwl_out[507:507] ,mux_2level_tapbuf_size16_8_sram_blwl_outb[507:507] ,mux_2level_tapbuf_size16_8_configbus0[507:507], mux_2level_tapbuf_size16_8_configbus1[507:507] , mux_2level_tapbuf_size16_8_configbus0_b[507:507] ); -sram6T_blwl sram_blwl_508_ (mux_2level_tapbuf_size16_8_sram_blwl_out[508:508] ,mux_2level_tapbuf_size16_8_sram_blwl_out[508:508] ,mux_2level_tapbuf_size16_8_sram_blwl_outb[508:508] ,mux_2level_tapbuf_size16_8_configbus0[508:508], mux_2level_tapbuf_size16_8_configbus1[508:508] , mux_2level_tapbuf_size16_8_configbus0_b[508:508] ); -sram6T_blwl sram_blwl_509_ (mux_2level_tapbuf_size16_8_sram_blwl_out[509:509] ,mux_2level_tapbuf_size16_8_sram_blwl_out[509:509] ,mux_2level_tapbuf_size16_8_sram_blwl_outb[509:509] ,mux_2level_tapbuf_size16_8_configbus0[509:509], mux_2level_tapbuf_size16_8_configbus1[509:509] , mux_2level_tapbuf_size16_8_configbus0_b[509:509] ); -sram6T_blwl sram_blwl_510_ (mux_2level_tapbuf_size16_8_sram_blwl_out[510:510] ,mux_2level_tapbuf_size16_8_sram_blwl_out[510:510] ,mux_2level_tapbuf_size16_8_sram_blwl_outb[510:510] ,mux_2level_tapbuf_size16_8_configbus0[510:510], mux_2level_tapbuf_size16_8_configbus1[510:510] , mux_2level_tapbuf_size16_8_configbus0_b[510:510] ); -sram6T_blwl sram_blwl_511_ (mux_2level_tapbuf_size16_8_sram_blwl_out[511:511] ,mux_2level_tapbuf_size16_8_sram_blwl_out[511:511] ,mux_2level_tapbuf_size16_8_sram_blwl_outb[511:511] ,mux_2level_tapbuf_size16_8_configbus0[511:511], mux_2level_tapbuf_size16_8_configbus1[511:511] , mux_2level_tapbuf_size16_8_configbus0_b[511:511] ); -wire [0:15] mux_2level_tapbuf_size16_9_inbus; -assign mux_2level_tapbuf_size16_9_inbus[0] = chanx_1__0__midout_10_; -assign mux_2level_tapbuf_size16_9_inbus[1] = chanx_1__0__midout_11_; -assign mux_2level_tapbuf_size16_9_inbus[2] = chanx_1__0__midout_24_; -assign mux_2level_tapbuf_size16_9_inbus[3] = chanx_1__0__midout_25_; -assign mux_2level_tapbuf_size16_9_inbus[4] = chanx_1__0__midout_36_; -assign mux_2level_tapbuf_size16_9_inbus[5] = chanx_1__0__midout_37_; -assign mux_2level_tapbuf_size16_9_inbus[6] = chanx_1__0__midout_48_; -assign mux_2level_tapbuf_size16_9_inbus[7] = chanx_1__0__midout_49_; -assign mux_2level_tapbuf_size16_9_inbus[8] = chanx_1__0__midout_60_; -assign mux_2level_tapbuf_size16_9_inbus[9] = chanx_1__0__midout_61_; -assign mux_2level_tapbuf_size16_9_inbus[10] = chanx_1__0__midout_74_; -assign mux_2level_tapbuf_size16_9_inbus[11] = chanx_1__0__midout_75_; -assign mux_2level_tapbuf_size16_9_inbus[12] = chanx_1__0__midout_86_; -assign mux_2level_tapbuf_size16_9_inbus[13] = chanx_1__0__midout_87_; -assign mux_2level_tapbuf_size16_9_inbus[14] = chanx_1__0__midout_98_; -assign mux_2level_tapbuf_size16_9_inbus[15] = chanx_1__0__midout_99_; -wire [512:519] mux_2level_tapbuf_size16_9_configbus0; -wire [512:519] mux_2level_tapbuf_size16_9_configbus1; -wire [512:519] mux_2level_tapbuf_size16_9_sram_blwl_out ; -wire [512:519] mux_2level_tapbuf_size16_9_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_9_configbus0[512:519] = sram_blwl_bl[512:519] ; -assign mux_2level_tapbuf_size16_9_configbus1[512:519] = sram_blwl_wl[512:519] ; -wire [512:519] mux_2level_tapbuf_size16_9_configbus0_b; -assign mux_2level_tapbuf_size16_9_configbus0_b[512:519] = sram_blwl_blb[512:519] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_9_ (mux_2level_tapbuf_size16_9_inbus, grid_1__1__pin_0__2__38_, mux_2level_tapbuf_size16_9_sram_blwl_out[512:519] , -mux_2level_tapbuf_size16_9_sram_blwl_outb[512:519] ); -//----- SRAM bits for MUX[9], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_512_ (mux_2level_tapbuf_size16_9_sram_blwl_out[512:512] ,mux_2level_tapbuf_size16_9_sram_blwl_out[512:512] ,mux_2level_tapbuf_size16_9_sram_blwl_outb[512:512] ,mux_2level_tapbuf_size16_9_configbus0[512:512], mux_2level_tapbuf_size16_9_configbus1[512:512] , mux_2level_tapbuf_size16_9_configbus0_b[512:512] ); -sram6T_blwl sram_blwl_513_ (mux_2level_tapbuf_size16_9_sram_blwl_out[513:513] ,mux_2level_tapbuf_size16_9_sram_blwl_out[513:513] ,mux_2level_tapbuf_size16_9_sram_blwl_outb[513:513] ,mux_2level_tapbuf_size16_9_configbus0[513:513], mux_2level_tapbuf_size16_9_configbus1[513:513] , mux_2level_tapbuf_size16_9_configbus0_b[513:513] ); -sram6T_blwl sram_blwl_514_ (mux_2level_tapbuf_size16_9_sram_blwl_out[514:514] ,mux_2level_tapbuf_size16_9_sram_blwl_out[514:514] ,mux_2level_tapbuf_size16_9_sram_blwl_outb[514:514] ,mux_2level_tapbuf_size16_9_configbus0[514:514], mux_2level_tapbuf_size16_9_configbus1[514:514] , mux_2level_tapbuf_size16_9_configbus0_b[514:514] ); -sram6T_blwl sram_blwl_515_ (mux_2level_tapbuf_size16_9_sram_blwl_out[515:515] ,mux_2level_tapbuf_size16_9_sram_blwl_out[515:515] ,mux_2level_tapbuf_size16_9_sram_blwl_outb[515:515] ,mux_2level_tapbuf_size16_9_configbus0[515:515], mux_2level_tapbuf_size16_9_configbus1[515:515] , mux_2level_tapbuf_size16_9_configbus0_b[515:515] ); -sram6T_blwl sram_blwl_516_ (mux_2level_tapbuf_size16_9_sram_blwl_out[516:516] ,mux_2level_tapbuf_size16_9_sram_blwl_out[516:516] ,mux_2level_tapbuf_size16_9_sram_blwl_outb[516:516] ,mux_2level_tapbuf_size16_9_configbus0[516:516], mux_2level_tapbuf_size16_9_configbus1[516:516] , mux_2level_tapbuf_size16_9_configbus0_b[516:516] ); -sram6T_blwl sram_blwl_517_ (mux_2level_tapbuf_size16_9_sram_blwl_out[517:517] ,mux_2level_tapbuf_size16_9_sram_blwl_out[517:517] ,mux_2level_tapbuf_size16_9_sram_blwl_outb[517:517] ,mux_2level_tapbuf_size16_9_configbus0[517:517], mux_2level_tapbuf_size16_9_configbus1[517:517] , mux_2level_tapbuf_size16_9_configbus0_b[517:517] ); -sram6T_blwl sram_blwl_518_ (mux_2level_tapbuf_size16_9_sram_blwl_out[518:518] ,mux_2level_tapbuf_size16_9_sram_blwl_out[518:518] ,mux_2level_tapbuf_size16_9_sram_blwl_outb[518:518] ,mux_2level_tapbuf_size16_9_configbus0[518:518], mux_2level_tapbuf_size16_9_configbus1[518:518] , mux_2level_tapbuf_size16_9_configbus0_b[518:518] ); -sram6T_blwl sram_blwl_519_ (mux_2level_tapbuf_size16_9_sram_blwl_out[519:519] ,mux_2level_tapbuf_size16_9_sram_blwl_out[519:519] ,mux_2level_tapbuf_size16_9_sram_blwl_outb[519:519] ,mux_2level_tapbuf_size16_9_configbus0[519:519], mux_2level_tapbuf_size16_9_configbus1[519:519] , mux_2level_tapbuf_size16_9_configbus0_b[519:519] ); -wire [0:15] mux_2level_tapbuf_size16_10_inbus; -assign mux_2level_tapbuf_size16_10_inbus[0] = chanx_1__0__midout_0_; -assign mux_2level_tapbuf_size16_10_inbus[1] = chanx_1__0__midout_1_; -assign mux_2level_tapbuf_size16_10_inbus[2] = chanx_1__0__midout_12_; -assign mux_2level_tapbuf_size16_10_inbus[3] = chanx_1__0__midout_13_; -assign mux_2level_tapbuf_size16_10_inbus[4] = chanx_1__0__midout_24_; -assign mux_2level_tapbuf_size16_10_inbus[5] = chanx_1__0__midout_25_; -assign mux_2level_tapbuf_size16_10_inbus[6] = chanx_1__0__midout_36_; -assign mux_2level_tapbuf_size16_10_inbus[7] = chanx_1__0__midout_37_; -assign mux_2level_tapbuf_size16_10_inbus[8] = chanx_1__0__midout_50_; -assign mux_2level_tapbuf_size16_10_inbus[9] = chanx_1__0__midout_51_; -assign mux_2level_tapbuf_size16_10_inbus[10] = chanx_1__0__midout_62_; -assign mux_2level_tapbuf_size16_10_inbus[11] = chanx_1__0__midout_63_; -assign mux_2level_tapbuf_size16_10_inbus[12] = chanx_1__0__midout_74_; -assign mux_2level_tapbuf_size16_10_inbus[13] = chanx_1__0__midout_75_; -assign mux_2level_tapbuf_size16_10_inbus[14] = chanx_1__0__midout_86_; -assign mux_2level_tapbuf_size16_10_inbus[15] = chanx_1__0__midout_87_; -wire [520:527] mux_2level_tapbuf_size16_10_configbus0; -wire [520:527] mux_2level_tapbuf_size16_10_configbus1; -wire [520:527] mux_2level_tapbuf_size16_10_sram_blwl_out ; -wire [520:527] mux_2level_tapbuf_size16_10_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_10_configbus0[520:527] = sram_blwl_bl[520:527] ; -assign mux_2level_tapbuf_size16_10_configbus1[520:527] = sram_blwl_wl[520:527] ; -wire [520:527] mux_2level_tapbuf_size16_10_configbus0_b; -assign mux_2level_tapbuf_size16_10_configbus0_b[520:527] = sram_blwl_blb[520:527] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_10_ (mux_2level_tapbuf_size16_10_inbus, grid_1__0__pin_0__0__0_, mux_2level_tapbuf_size16_10_sram_blwl_out[520:527] , -mux_2level_tapbuf_size16_10_sram_blwl_outb[520:527] ); -//----- SRAM bits for MUX[10], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_520_ (mux_2level_tapbuf_size16_10_sram_blwl_out[520:520] ,mux_2level_tapbuf_size16_10_sram_blwl_out[520:520] ,mux_2level_tapbuf_size16_10_sram_blwl_outb[520:520] ,mux_2level_tapbuf_size16_10_configbus0[520:520], mux_2level_tapbuf_size16_10_configbus1[520:520] , mux_2level_tapbuf_size16_10_configbus0_b[520:520] ); -sram6T_blwl sram_blwl_521_ (mux_2level_tapbuf_size16_10_sram_blwl_out[521:521] ,mux_2level_tapbuf_size16_10_sram_blwl_out[521:521] ,mux_2level_tapbuf_size16_10_sram_blwl_outb[521:521] ,mux_2level_tapbuf_size16_10_configbus0[521:521], mux_2level_tapbuf_size16_10_configbus1[521:521] , mux_2level_tapbuf_size16_10_configbus0_b[521:521] ); -sram6T_blwl sram_blwl_522_ (mux_2level_tapbuf_size16_10_sram_blwl_out[522:522] ,mux_2level_tapbuf_size16_10_sram_blwl_out[522:522] ,mux_2level_tapbuf_size16_10_sram_blwl_outb[522:522] ,mux_2level_tapbuf_size16_10_configbus0[522:522], mux_2level_tapbuf_size16_10_configbus1[522:522] , mux_2level_tapbuf_size16_10_configbus0_b[522:522] ); -sram6T_blwl sram_blwl_523_ (mux_2level_tapbuf_size16_10_sram_blwl_out[523:523] ,mux_2level_tapbuf_size16_10_sram_blwl_out[523:523] ,mux_2level_tapbuf_size16_10_sram_blwl_outb[523:523] ,mux_2level_tapbuf_size16_10_configbus0[523:523], mux_2level_tapbuf_size16_10_configbus1[523:523] , mux_2level_tapbuf_size16_10_configbus0_b[523:523] ); -sram6T_blwl sram_blwl_524_ (mux_2level_tapbuf_size16_10_sram_blwl_out[524:524] ,mux_2level_tapbuf_size16_10_sram_blwl_out[524:524] ,mux_2level_tapbuf_size16_10_sram_blwl_outb[524:524] ,mux_2level_tapbuf_size16_10_configbus0[524:524], mux_2level_tapbuf_size16_10_configbus1[524:524] , mux_2level_tapbuf_size16_10_configbus0_b[524:524] ); -sram6T_blwl sram_blwl_525_ (mux_2level_tapbuf_size16_10_sram_blwl_out[525:525] ,mux_2level_tapbuf_size16_10_sram_blwl_out[525:525] ,mux_2level_tapbuf_size16_10_sram_blwl_outb[525:525] ,mux_2level_tapbuf_size16_10_configbus0[525:525], mux_2level_tapbuf_size16_10_configbus1[525:525] , mux_2level_tapbuf_size16_10_configbus0_b[525:525] ); -sram6T_blwl sram_blwl_526_ (mux_2level_tapbuf_size16_10_sram_blwl_out[526:526] ,mux_2level_tapbuf_size16_10_sram_blwl_out[526:526] ,mux_2level_tapbuf_size16_10_sram_blwl_outb[526:526] ,mux_2level_tapbuf_size16_10_configbus0[526:526], mux_2level_tapbuf_size16_10_configbus1[526:526] , mux_2level_tapbuf_size16_10_configbus0_b[526:526] ); -sram6T_blwl sram_blwl_527_ (mux_2level_tapbuf_size16_10_sram_blwl_out[527:527] ,mux_2level_tapbuf_size16_10_sram_blwl_out[527:527] ,mux_2level_tapbuf_size16_10_sram_blwl_outb[527:527] ,mux_2level_tapbuf_size16_10_configbus0[527:527], mux_2level_tapbuf_size16_10_configbus1[527:527] , mux_2level_tapbuf_size16_10_configbus0_b[527:527] ); -wire [0:15] mux_2level_tapbuf_size16_11_inbus; -assign mux_2level_tapbuf_size16_11_inbus[0] = chanx_1__0__midout_0_; -assign mux_2level_tapbuf_size16_11_inbus[1] = chanx_1__0__midout_1_; -assign mux_2level_tapbuf_size16_11_inbus[2] = chanx_1__0__midout_14_; -assign mux_2level_tapbuf_size16_11_inbus[3] = chanx_1__0__midout_15_; -assign mux_2level_tapbuf_size16_11_inbus[4] = chanx_1__0__midout_26_; -assign mux_2level_tapbuf_size16_11_inbus[5] = chanx_1__0__midout_27_; -assign mux_2level_tapbuf_size16_11_inbus[6] = chanx_1__0__midout_38_; -assign mux_2level_tapbuf_size16_11_inbus[7] = chanx_1__0__midout_39_; -assign mux_2level_tapbuf_size16_11_inbus[8] = chanx_1__0__midout_50_; -assign mux_2level_tapbuf_size16_11_inbus[9] = chanx_1__0__midout_51_; -assign mux_2level_tapbuf_size16_11_inbus[10] = chanx_1__0__midout_64_; -assign mux_2level_tapbuf_size16_11_inbus[11] = chanx_1__0__midout_65_; -assign mux_2level_tapbuf_size16_11_inbus[12] = chanx_1__0__midout_76_; -assign mux_2level_tapbuf_size16_11_inbus[13] = chanx_1__0__midout_77_; -assign mux_2level_tapbuf_size16_11_inbus[14] = chanx_1__0__midout_88_; -assign mux_2level_tapbuf_size16_11_inbus[15] = chanx_1__0__midout_89_; -wire [528:535] mux_2level_tapbuf_size16_11_configbus0; -wire [528:535] mux_2level_tapbuf_size16_11_configbus1; -wire [528:535] mux_2level_tapbuf_size16_11_sram_blwl_out ; -wire [528:535] mux_2level_tapbuf_size16_11_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_11_configbus0[528:535] = sram_blwl_bl[528:535] ; -assign mux_2level_tapbuf_size16_11_configbus1[528:535] = sram_blwl_wl[528:535] ; -wire [528:535] mux_2level_tapbuf_size16_11_configbus0_b; -assign mux_2level_tapbuf_size16_11_configbus0_b[528:535] = sram_blwl_blb[528:535] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_11_ (mux_2level_tapbuf_size16_11_inbus, grid_1__0__pin_0__0__2_, mux_2level_tapbuf_size16_11_sram_blwl_out[528:535] , -mux_2level_tapbuf_size16_11_sram_blwl_outb[528:535] ); -//----- SRAM bits for MUX[11], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_528_ (mux_2level_tapbuf_size16_11_sram_blwl_out[528:528] ,mux_2level_tapbuf_size16_11_sram_blwl_out[528:528] ,mux_2level_tapbuf_size16_11_sram_blwl_outb[528:528] ,mux_2level_tapbuf_size16_11_configbus0[528:528], mux_2level_tapbuf_size16_11_configbus1[528:528] , mux_2level_tapbuf_size16_11_configbus0_b[528:528] ); -sram6T_blwl sram_blwl_529_ (mux_2level_tapbuf_size16_11_sram_blwl_out[529:529] ,mux_2level_tapbuf_size16_11_sram_blwl_out[529:529] ,mux_2level_tapbuf_size16_11_sram_blwl_outb[529:529] ,mux_2level_tapbuf_size16_11_configbus0[529:529], mux_2level_tapbuf_size16_11_configbus1[529:529] , mux_2level_tapbuf_size16_11_configbus0_b[529:529] ); -sram6T_blwl sram_blwl_530_ (mux_2level_tapbuf_size16_11_sram_blwl_out[530:530] ,mux_2level_tapbuf_size16_11_sram_blwl_out[530:530] ,mux_2level_tapbuf_size16_11_sram_blwl_outb[530:530] ,mux_2level_tapbuf_size16_11_configbus0[530:530], mux_2level_tapbuf_size16_11_configbus1[530:530] , mux_2level_tapbuf_size16_11_configbus0_b[530:530] ); -sram6T_blwl sram_blwl_531_ (mux_2level_tapbuf_size16_11_sram_blwl_out[531:531] ,mux_2level_tapbuf_size16_11_sram_blwl_out[531:531] ,mux_2level_tapbuf_size16_11_sram_blwl_outb[531:531] ,mux_2level_tapbuf_size16_11_configbus0[531:531], mux_2level_tapbuf_size16_11_configbus1[531:531] , mux_2level_tapbuf_size16_11_configbus0_b[531:531] ); -sram6T_blwl sram_blwl_532_ (mux_2level_tapbuf_size16_11_sram_blwl_out[532:532] ,mux_2level_tapbuf_size16_11_sram_blwl_out[532:532] ,mux_2level_tapbuf_size16_11_sram_blwl_outb[532:532] ,mux_2level_tapbuf_size16_11_configbus0[532:532], mux_2level_tapbuf_size16_11_configbus1[532:532] , mux_2level_tapbuf_size16_11_configbus0_b[532:532] ); -sram6T_blwl sram_blwl_533_ (mux_2level_tapbuf_size16_11_sram_blwl_out[533:533] ,mux_2level_tapbuf_size16_11_sram_blwl_out[533:533] ,mux_2level_tapbuf_size16_11_sram_blwl_outb[533:533] ,mux_2level_tapbuf_size16_11_configbus0[533:533], mux_2level_tapbuf_size16_11_configbus1[533:533] , mux_2level_tapbuf_size16_11_configbus0_b[533:533] ); -sram6T_blwl sram_blwl_534_ (mux_2level_tapbuf_size16_11_sram_blwl_out[534:534] ,mux_2level_tapbuf_size16_11_sram_blwl_out[534:534] ,mux_2level_tapbuf_size16_11_sram_blwl_outb[534:534] ,mux_2level_tapbuf_size16_11_configbus0[534:534], mux_2level_tapbuf_size16_11_configbus1[534:534] , mux_2level_tapbuf_size16_11_configbus0_b[534:534] ); -sram6T_blwl sram_blwl_535_ (mux_2level_tapbuf_size16_11_sram_blwl_out[535:535] ,mux_2level_tapbuf_size16_11_sram_blwl_out[535:535] ,mux_2level_tapbuf_size16_11_sram_blwl_outb[535:535] ,mux_2level_tapbuf_size16_11_configbus0[535:535], mux_2level_tapbuf_size16_11_configbus1[535:535] , mux_2level_tapbuf_size16_11_configbus0_b[535:535] ); -wire [0:15] mux_2level_tapbuf_size16_12_inbus; -assign mux_2level_tapbuf_size16_12_inbus[0] = chanx_1__0__midout_2_; -assign mux_2level_tapbuf_size16_12_inbus[1] = chanx_1__0__midout_3_; -assign mux_2level_tapbuf_size16_12_inbus[2] = chanx_1__0__midout_14_; -assign mux_2level_tapbuf_size16_12_inbus[3] = chanx_1__0__midout_15_; -assign mux_2level_tapbuf_size16_12_inbus[4] = chanx_1__0__midout_28_; -assign mux_2level_tapbuf_size16_12_inbus[5] = chanx_1__0__midout_29_; -assign mux_2level_tapbuf_size16_12_inbus[6] = chanx_1__0__midout_40_; -assign mux_2level_tapbuf_size16_12_inbus[7] = chanx_1__0__midout_41_; -assign mux_2level_tapbuf_size16_12_inbus[8] = chanx_1__0__midout_52_; -assign mux_2level_tapbuf_size16_12_inbus[9] = chanx_1__0__midout_53_; -assign mux_2level_tapbuf_size16_12_inbus[10] = chanx_1__0__midout_64_; -assign mux_2level_tapbuf_size16_12_inbus[11] = chanx_1__0__midout_65_; -assign mux_2level_tapbuf_size16_12_inbus[12] = chanx_1__0__midout_78_; -assign mux_2level_tapbuf_size16_12_inbus[13] = chanx_1__0__midout_79_; -assign mux_2level_tapbuf_size16_12_inbus[14] = chanx_1__0__midout_90_; -assign mux_2level_tapbuf_size16_12_inbus[15] = chanx_1__0__midout_91_; -wire [536:543] mux_2level_tapbuf_size16_12_configbus0; -wire [536:543] mux_2level_tapbuf_size16_12_configbus1; -wire [536:543] mux_2level_tapbuf_size16_12_sram_blwl_out ; -wire [536:543] mux_2level_tapbuf_size16_12_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_12_configbus0[536:543] = sram_blwl_bl[536:543] ; -assign mux_2level_tapbuf_size16_12_configbus1[536:543] = sram_blwl_wl[536:543] ; -wire [536:543] mux_2level_tapbuf_size16_12_configbus0_b; -assign mux_2level_tapbuf_size16_12_configbus0_b[536:543] = sram_blwl_blb[536:543] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_12_ (mux_2level_tapbuf_size16_12_inbus, grid_1__0__pin_0__0__4_, mux_2level_tapbuf_size16_12_sram_blwl_out[536:543] , -mux_2level_tapbuf_size16_12_sram_blwl_outb[536:543] ); -//----- SRAM bits for MUX[12], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_536_ (mux_2level_tapbuf_size16_12_sram_blwl_out[536:536] ,mux_2level_tapbuf_size16_12_sram_blwl_out[536:536] ,mux_2level_tapbuf_size16_12_sram_blwl_outb[536:536] ,mux_2level_tapbuf_size16_12_configbus0[536:536], mux_2level_tapbuf_size16_12_configbus1[536:536] , mux_2level_tapbuf_size16_12_configbus0_b[536:536] ); -sram6T_blwl sram_blwl_537_ (mux_2level_tapbuf_size16_12_sram_blwl_out[537:537] ,mux_2level_tapbuf_size16_12_sram_blwl_out[537:537] ,mux_2level_tapbuf_size16_12_sram_blwl_outb[537:537] ,mux_2level_tapbuf_size16_12_configbus0[537:537], mux_2level_tapbuf_size16_12_configbus1[537:537] , mux_2level_tapbuf_size16_12_configbus0_b[537:537] ); -sram6T_blwl sram_blwl_538_ (mux_2level_tapbuf_size16_12_sram_blwl_out[538:538] ,mux_2level_tapbuf_size16_12_sram_blwl_out[538:538] ,mux_2level_tapbuf_size16_12_sram_blwl_outb[538:538] ,mux_2level_tapbuf_size16_12_configbus0[538:538], mux_2level_tapbuf_size16_12_configbus1[538:538] , mux_2level_tapbuf_size16_12_configbus0_b[538:538] ); -sram6T_blwl sram_blwl_539_ (mux_2level_tapbuf_size16_12_sram_blwl_out[539:539] ,mux_2level_tapbuf_size16_12_sram_blwl_out[539:539] ,mux_2level_tapbuf_size16_12_sram_blwl_outb[539:539] ,mux_2level_tapbuf_size16_12_configbus0[539:539], mux_2level_tapbuf_size16_12_configbus1[539:539] , mux_2level_tapbuf_size16_12_configbus0_b[539:539] ); -sram6T_blwl sram_blwl_540_ (mux_2level_tapbuf_size16_12_sram_blwl_out[540:540] ,mux_2level_tapbuf_size16_12_sram_blwl_out[540:540] ,mux_2level_tapbuf_size16_12_sram_blwl_outb[540:540] ,mux_2level_tapbuf_size16_12_configbus0[540:540], mux_2level_tapbuf_size16_12_configbus1[540:540] , mux_2level_tapbuf_size16_12_configbus0_b[540:540] ); -sram6T_blwl sram_blwl_541_ (mux_2level_tapbuf_size16_12_sram_blwl_out[541:541] ,mux_2level_tapbuf_size16_12_sram_blwl_out[541:541] ,mux_2level_tapbuf_size16_12_sram_blwl_outb[541:541] ,mux_2level_tapbuf_size16_12_configbus0[541:541], mux_2level_tapbuf_size16_12_configbus1[541:541] , mux_2level_tapbuf_size16_12_configbus0_b[541:541] ); -sram6T_blwl sram_blwl_542_ (mux_2level_tapbuf_size16_12_sram_blwl_out[542:542] ,mux_2level_tapbuf_size16_12_sram_blwl_out[542:542] ,mux_2level_tapbuf_size16_12_sram_blwl_outb[542:542] ,mux_2level_tapbuf_size16_12_configbus0[542:542], mux_2level_tapbuf_size16_12_configbus1[542:542] , mux_2level_tapbuf_size16_12_configbus0_b[542:542] ); -sram6T_blwl sram_blwl_543_ (mux_2level_tapbuf_size16_12_sram_blwl_out[543:543] ,mux_2level_tapbuf_size16_12_sram_blwl_out[543:543] ,mux_2level_tapbuf_size16_12_sram_blwl_outb[543:543] ,mux_2level_tapbuf_size16_12_configbus0[543:543], mux_2level_tapbuf_size16_12_configbus1[543:543] , mux_2level_tapbuf_size16_12_configbus0_b[543:543] ); -wire [0:15] mux_2level_tapbuf_size16_13_inbus; -assign mux_2level_tapbuf_size16_13_inbus[0] = chanx_1__0__midout_4_; -assign mux_2level_tapbuf_size16_13_inbus[1] = chanx_1__0__midout_5_; -assign mux_2level_tapbuf_size16_13_inbus[2] = chanx_1__0__midout_16_; -assign mux_2level_tapbuf_size16_13_inbus[3] = chanx_1__0__midout_17_; -assign mux_2level_tapbuf_size16_13_inbus[4] = chanx_1__0__midout_28_; -assign mux_2level_tapbuf_size16_13_inbus[5] = chanx_1__0__midout_29_; -assign mux_2level_tapbuf_size16_13_inbus[6] = chanx_1__0__midout_42_; -assign mux_2level_tapbuf_size16_13_inbus[7] = chanx_1__0__midout_43_; -assign mux_2level_tapbuf_size16_13_inbus[8] = chanx_1__0__midout_54_; -assign mux_2level_tapbuf_size16_13_inbus[9] = chanx_1__0__midout_55_; -assign mux_2level_tapbuf_size16_13_inbus[10] = chanx_1__0__midout_66_; -assign mux_2level_tapbuf_size16_13_inbus[11] = chanx_1__0__midout_67_; -assign mux_2level_tapbuf_size16_13_inbus[12] = chanx_1__0__midout_78_; -assign mux_2level_tapbuf_size16_13_inbus[13] = chanx_1__0__midout_79_; -assign mux_2level_tapbuf_size16_13_inbus[14] = chanx_1__0__midout_92_; -assign mux_2level_tapbuf_size16_13_inbus[15] = chanx_1__0__midout_93_; -wire [544:551] mux_2level_tapbuf_size16_13_configbus0; -wire [544:551] mux_2level_tapbuf_size16_13_configbus1; -wire [544:551] mux_2level_tapbuf_size16_13_sram_blwl_out ; -wire [544:551] mux_2level_tapbuf_size16_13_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_13_configbus0[544:551] = sram_blwl_bl[544:551] ; -assign mux_2level_tapbuf_size16_13_configbus1[544:551] = sram_blwl_wl[544:551] ; -wire [544:551] mux_2level_tapbuf_size16_13_configbus0_b; -assign mux_2level_tapbuf_size16_13_configbus0_b[544:551] = sram_blwl_blb[544:551] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_13_ (mux_2level_tapbuf_size16_13_inbus, grid_1__0__pin_0__0__6_, mux_2level_tapbuf_size16_13_sram_blwl_out[544:551] , -mux_2level_tapbuf_size16_13_sram_blwl_outb[544:551] ); -//----- SRAM bits for MUX[13], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_544_ (mux_2level_tapbuf_size16_13_sram_blwl_out[544:544] ,mux_2level_tapbuf_size16_13_sram_blwl_out[544:544] ,mux_2level_tapbuf_size16_13_sram_blwl_outb[544:544] ,mux_2level_tapbuf_size16_13_configbus0[544:544], mux_2level_tapbuf_size16_13_configbus1[544:544] , mux_2level_tapbuf_size16_13_configbus0_b[544:544] ); -sram6T_blwl sram_blwl_545_ (mux_2level_tapbuf_size16_13_sram_blwl_out[545:545] ,mux_2level_tapbuf_size16_13_sram_blwl_out[545:545] ,mux_2level_tapbuf_size16_13_sram_blwl_outb[545:545] ,mux_2level_tapbuf_size16_13_configbus0[545:545], mux_2level_tapbuf_size16_13_configbus1[545:545] , mux_2level_tapbuf_size16_13_configbus0_b[545:545] ); -sram6T_blwl sram_blwl_546_ (mux_2level_tapbuf_size16_13_sram_blwl_out[546:546] ,mux_2level_tapbuf_size16_13_sram_blwl_out[546:546] ,mux_2level_tapbuf_size16_13_sram_blwl_outb[546:546] ,mux_2level_tapbuf_size16_13_configbus0[546:546], mux_2level_tapbuf_size16_13_configbus1[546:546] , mux_2level_tapbuf_size16_13_configbus0_b[546:546] ); -sram6T_blwl sram_blwl_547_ (mux_2level_tapbuf_size16_13_sram_blwl_out[547:547] ,mux_2level_tapbuf_size16_13_sram_blwl_out[547:547] ,mux_2level_tapbuf_size16_13_sram_blwl_outb[547:547] ,mux_2level_tapbuf_size16_13_configbus0[547:547], mux_2level_tapbuf_size16_13_configbus1[547:547] , mux_2level_tapbuf_size16_13_configbus0_b[547:547] ); -sram6T_blwl sram_blwl_548_ (mux_2level_tapbuf_size16_13_sram_blwl_out[548:548] ,mux_2level_tapbuf_size16_13_sram_blwl_out[548:548] ,mux_2level_tapbuf_size16_13_sram_blwl_outb[548:548] ,mux_2level_tapbuf_size16_13_configbus0[548:548], mux_2level_tapbuf_size16_13_configbus1[548:548] , mux_2level_tapbuf_size16_13_configbus0_b[548:548] ); -sram6T_blwl sram_blwl_549_ (mux_2level_tapbuf_size16_13_sram_blwl_out[549:549] ,mux_2level_tapbuf_size16_13_sram_blwl_out[549:549] ,mux_2level_tapbuf_size16_13_sram_blwl_outb[549:549] ,mux_2level_tapbuf_size16_13_configbus0[549:549], mux_2level_tapbuf_size16_13_configbus1[549:549] , mux_2level_tapbuf_size16_13_configbus0_b[549:549] ); -sram6T_blwl sram_blwl_550_ (mux_2level_tapbuf_size16_13_sram_blwl_out[550:550] ,mux_2level_tapbuf_size16_13_sram_blwl_out[550:550] ,mux_2level_tapbuf_size16_13_sram_blwl_outb[550:550] ,mux_2level_tapbuf_size16_13_configbus0[550:550], mux_2level_tapbuf_size16_13_configbus1[550:550] , mux_2level_tapbuf_size16_13_configbus0_b[550:550] ); -sram6T_blwl sram_blwl_551_ (mux_2level_tapbuf_size16_13_sram_blwl_out[551:551] ,mux_2level_tapbuf_size16_13_sram_blwl_out[551:551] ,mux_2level_tapbuf_size16_13_sram_blwl_outb[551:551] ,mux_2level_tapbuf_size16_13_configbus0[551:551], mux_2level_tapbuf_size16_13_configbus1[551:551] , mux_2level_tapbuf_size16_13_configbus0_b[551:551] ); -wire [0:15] mux_2level_tapbuf_size16_14_inbus; -assign mux_2level_tapbuf_size16_14_inbus[0] = chanx_1__0__midout_6_; -assign mux_2level_tapbuf_size16_14_inbus[1] = chanx_1__0__midout_7_; -assign mux_2level_tapbuf_size16_14_inbus[2] = chanx_1__0__midout_18_; -assign mux_2level_tapbuf_size16_14_inbus[3] = chanx_1__0__midout_19_; -assign mux_2level_tapbuf_size16_14_inbus[4] = chanx_1__0__midout_30_; -assign mux_2level_tapbuf_size16_14_inbus[5] = chanx_1__0__midout_31_; -assign mux_2level_tapbuf_size16_14_inbus[6] = chanx_1__0__midout_42_; -assign mux_2level_tapbuf_size16_14_inbus[7] = chanx_1__0__midout_43_; -assign mux_2level_tapbuf_size16_14_inbus[8] = chanx_1__0__midout_56_; -assign mux_2level_tapbuf_size16_14_inbus[9] = chanx_1__0__midout_57_; -assign mux_2level_tapbuf_size16_14_inbus[10] = chanx_1__0__midout_68_; -assign mux_2level_tapbuf_size16_14_inbus[11] = chanx_1__0__midout_69_; -assign mux_2level_tapbuf_size16_14_inbus[12] = chanx_1__0__midout_80_; -assign mux_2level_tapbuf_size16_14_inbus[13] = chanx_1__0__midout_81_; -assign mux_2level_tapbuf_size16_14_inbus[14] = chanx_1__0__midout_92_; -assign mux_2level_tapbuf_size16_14_inbus[15] = chanx_1__0__midout_93_; -wire [552:559] mux_2level_tapbuf_size16_14_configbus0; -wire [552:559] mux_2level_tapbuf_size16_14_configbus1; -wire [552:559] mux_2level_tapbuf_size16_14_sram_blwl_out ; -wire [552:559] mux_2level_tapbuf_size16_14_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_14_configbus0[552:559] = sram_blwl_bl[552:559] ; -assign mux_2level_tapbuf_size16_14_configbus1[552:559] = sram_blwl_wl[552:559] ; -wire [552:559] mux_2level_tapbuf_size16_14_configbus0_b; -assign mux_2level_tapbuf_size16_14_configbus0_b[552:559] = sram_blwl_blb[552:559] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_14_ (mux_2level_tapbuf_size16_14_inbus, grid_1__0__pin_0__0__8_, mux_2level_tapbuf_size16_14_sram_blwl_out[552:559] , -mux_2level_tapbuf_size16_14_sram_blwl_outb[552:559] ); -//----- SRAM bits for MUX[14], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_552_ (mux_2level_tapbuf_size16_14_sram_blwl_out[552:552] ,mux_2level_tapbuf_size16_14_sram_blwl_out[552:552] ,mux_2level_tapbuf_size16_14_sram_blwl_outb[552:552] ,mux_2level_tapbuf_size16_14_configbus0[552:552], mux_2level_tapbuf_size16_14_configbus1[552:552] , mux_2level_tapbuf_size16_14_configbus0_b[552:552] ); -sram6T_blwl sram_blwl_553_ (mux_2level_tapbuf_size16_14_sram_blwl_out[553:553] ,mux_2level_tapbuf_size16_14_sram_blwl_out[553:553] ,mux_2level_tapbuf_size16_14_sram_blwl_outb[553:553] ,mux_2level_tapbuf_size16_14_configbus0[553:553], mux_2level_tapbuf_size16_14_configbus1[553:553] , mux_2level_tapbuf_size16_14_configbus0_b[553:553] ); -sram6T_blwl sram_blwl_554_ (mux_2level_tapbuf_size16_14_sram_blwl_out[554:554] ,mux_2level_tapbuf_size16_14_sram_blwl_out[554:554] ,mux_2level_tapbuf_size16_14_sram_blwl_outb[554:554] ,mux_2level_tapbuf_size16_14_configbus0[554:554], mux_2level_tapbuf_size16_14_configbus1[554:554] , mux_2level_tapbuf_size16_14_configbus0_b[554:554] ); -sram6T_blwl sram_blwl_555_ (mux_2level_tapbuf_size16_14_sram_blwl_out[555:555] ,mux_2level_tapbuf_size16_14_sram_blwl_out[555:555] ,mux_2level_tapbuf_size16_14_sram_blwl_outb[555:555] ,mux_2level_tapbuf_size16_14_configbus0[555:555], mux_2level_tapbuf_size16_14_configbus1[555:555] , mux_2level_tapbuf_size16_14_configbus0_b[555:555] ); -sram6T_blwl sram_blwl_556_ (mux_2level_tapbuf_size16_14_sram_blwl_out[556:556] ,mux_2level_tapbuf_size16_14_sram_blwl_out[556:556] ,mux_2level_tapbuf_size16_14_sram_blwl_outb[556:556] ,mux_2level_tapbuf_size16_14_configbus0[556:556], mux_2level_tapbuf_size16_14_configbus1[556:556] , mux_2level_tapbuf_size16_14_configbus0_b[556:556] ); -sram6T_blwl sram_blwl_557_ (mux_2level_tapbuf_size16_14_sram_blwl_out[557:557] ,mux_2level_tapbuf_size16_14_sram_blwl_out[557:557] ,mux_2level_tapbuf_size16_14_sram_blwl_outb[557:557] ,mux_2level_tapbuf_size16_14_configbus0[557:557], mux_2level_tapbuf_size16_14_configbus1[557:557] , mux_2level_tapbuf_size16_14_configbus0_b[557:557] ); -sram6T_blwl sram_blwl_558_ (mux_2level_tapbuf_size16_14_sram_blwl_out[558:558] ,mux_2level_tapbuf_size16_14_sram_blwl_out[558:558] ,mux_2level_tapbuf_size16_14_sram_blwl_outb[558:558] ,mux_2level_tapbuf_size16_14_configbus0[558:558], mux_2level_tapbuf_size16_14_configbus1[558:558] , mux_2level_tapbuf_size16_14_configbus0_b[558:558] ); -sram6T_blwl sram_blwl_559_ (mux_2level_tapbuf_size16_14_sram_blwl_out[559:559] ,mux_2level_tapbuf_size16_14_sram_blwl_out[559:559] ,mux_2level_tapbuf_size16_14_sram_blwl_outb[559:559] ,mux_2level_tapbuf_size16_14_configbus0[559:559], mux_2level_tapbuf_size16_14_configbus1[559:559] , mux_2level_tapbuf_size16_14_configbus0_b[559:559] ); -wire [0:15] mux_2level_tapbuf_size16_15_inbus; -assign mux_2level_tapbuf_size16_15_inbus[0] = chanx_1__0__midout_6_; -assign mux_2level_tapbuf_size16_15_inbus[1] = chanx_1__0__midout_7_; -assign mux_2level_tapbuf_size16_15_inbus[2] = chanx_1__0__midout_20_; -assign mux_2level_tapbuf_size16_15_inbus[3] = chanx_1__0__midout_21_; -assign mux_2level_tapbuf_size16_15_inbus[4] = chanx_1__0__midout_32_; -assign mux_2level_tapbuf_size16_15_inbus[5] = chanx_1__0__midout_33_; -assign mux_2level_tapbuf_size16_15_inbus[6] = chanx_1__0__midout_44_; -assign mux_2level_tapbuf_size16_15_inbus[7] = chanx_1__0__midout_45_; -assign mux_2level_tapbuf_size16_15_inbus[8] = chanx_1__0__midout_56_; -assign mux_2level_tapbuf_size16_15_inbus[9] = chanx_1__0__midout_57_; -assign mux_2level_tapbuf_size16_15_inbus[10] = chanx_1__0__midout_70_; -assign mux_2level_tapbuf_size16_15_inbus[11] = chanx_1__0__midout_71_; -assign mux_2level_tapbuf_size16_15_inbus[12] = chanx_1__0__midout_82_; -assign mux_2level_tapbuf_size16_15_inbus[13] = chanx_1__0__midout_83_; -assign mux_2level_tapbuf_size16_15_inbus[14] = chanx_1__0__midout_94_; -assign mux_2level_tapbuf_size16_15_inbus[15] = chanx_1__0__midout_95_; -wire [560:567] mux_2level_tapbuf_size16_15_configbus0; -wire [560:567] mux_2level_tapbuf_size16_15_configbus1; -wire [560:567] mux_2level_tapbuf_size16_15_sram_blwl_out ; -wire [560:567] mux_2level_tapbuf_size16_15_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_15_configbus0[560:567] = sram_blwl_bl[560:567] ; -assign mux_2level_tapbuf_size16_15_configbus1[560:567] = sram_blwl_wl[560:567] ; -wire [560:567] mux_2level_tapbuf_size16_15_configbus0_b; -assign mux_2level_tapbuf_size16_15_configbus0_b[560:567] = sram_blwl_blb[560:567] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_15_ (mux_2level_tapbuf_size16_15_inbus, grid_1__0__pin_0__0__10_, mux_2level_tapbuf_size16_15_sram_blwl_out[560:567] , -mux_2level_tapbuf_size16_15_sram_blwl_outb[560:567] ); -//----- SRAM bits for MUX[15], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_560_ (mux_2level_tapbuf_size16_15_sram_blwl_out[560:560] ,mux_2level_tapbuf_size16_15_sram_blwl_out[560:560] ,mux_2level_tapbuf_size16_15_sram_blwl_outb[560:560] ,mux_2level_tapbuf_size16_15_configbus0[560:560], mux_2level_tapbuf_size16_15_configbus1[560:560] , mux_2level_tapbuf_size16_15_configbus0_b[560:560] ); -sram6T_blwl sram_blwl_561_ (mux_2level_tapbuf_size16_15_sram_blwl_out[561:561] ,mux_2level_tapbuf_size16_15_sram_blwl_out[561:561] ,mux_2level_tapbuf_size16_15_sram_blwl_outb[561:561] ,mux_2level_tapbuf_size16_15_configbus0[561:561], mux_2level_tapbuf_size16_15_configbus1[561:561] , mux_2level_tapbuf_size16_15_configbus0_b[561:561] ); -sram6T_blwl sram_blwl_562_ (mux_2level_tapbuf_size16_15_sram_blwl_out[562:562] ,mux_2level_tapbuf_size16_15_sram_blwl_out[562:562] ,mux_2level_tapbuf_size16_15_sram_blwl_outb[562:562] ,mux_2level_tapbuf_size16_15_configbus0[562:562], mux_2level_tapbuf_size16_15_configbus1[562:562] , mux_2level_tapbuf_size16_15_configbus0_b[562:562] ); -sram6T_blwl sram_blwl_563_ (mux_2level_tapbuf_size16_15_sram_blwl_out[563:563] ,mux_2level_tapbuf_size16_15_sram_blwl_out[563:563] ,mux_2level_tapbuf_size16_15_sram_blwl_outb[563:563] ,mux_2level_tapbuf_size16_15_configbus0[563:563], mux_2level_tapbuf_size16_15_configbus1[563:563] , mux_2level_tapbuf_size16_15_configbus0_b[563:563] ); -sram6T_blwl sram_blwl_564_ (mux_2level_tapbuf_size16_15_sram_blwl_out[564:564] ,mux_2level_tapbuf_size16_15_sram_blwl_out[564:564] ,mux_2level_tapbuf_size16_15_sram_blwl_outb[564:564] ,mux_2level_tapbuf_size16_15_configbus0[564:564], mux_2level_tapbuf_size16_15_configbus1[564:564] , mux_2level_tapbuf_size16_15_configbus0_b[564:564] ); -sram6T_blwl sram_blwl_565_ (mux_2level_tapbuf_size16_15_sram_blwl_out[565:565] ,mux_2level_tapbuf_size16_15_sram_blwl_out[565:565] ,mux_2level_tapbuf_size16_15_sram_blwl_outb[565:565] ,mux_2level_tapbuf_size16_15_configbus0[565:565], mux_2level_tapbuf_size16_15_configbus1[565:565] , mux_2level_tapbuf_size16_15_configbus0_b[565:565] ); -sram6T_blwl sram_blwl_566_ (mux_2level_tapbuf_size16_15_sram_blwl_out[566:566] ,mux_2level_tapbuf_size16_15_sram_blwl_out[566:566] ,mux_2level_tapbuf_size16_15_sram_blwl_outb[566:566] ,mux_2level_tapbuf_size16_15_configbus0[566:566], mux_2level_tapbuf_size16_15_configbus1[566:566] , mux_2level_tapbuf_size16_15_configbus0_b[566:566] ); -sram6T_blwl sram_blwl_567_ (mux_2level_tapbuf_size16_15_sram_blwl_out[567:567] ,mux_2level_tapbuf_size16_15_sram_blwl_out[567:567] ,mux_2level_tapbuf_size16_15_sram_blwl_outb[567:567] ,mux_2level_tapbuf_size16_15_configbus0[567:567], mux_2level_tapbuf_size16_15_configbus1[567:567] , mux_2level_tapbuf_size16_15_configbus0_b[567:567] ); -wire [0:15] mux_2level_tapbuf_size16_16_inbus; -assign mux_2level_tapbuf_size16_16_inbus[0] = chanx_1__0__midout_8_; -assign mux_2level_tapbuf_size16_16_inbus[1] = chanx_1__0__midout_9_; -assign mux_2level_tapbuf_size16_16_inbus[2] = chanx_1__0__midout_20_; -assign mux_2level_tapbuf_size16_16_inbus[3] = chanx_1__0__midout_21_; -assign mux_2level_tapbuf_size16_16_inbus[4] = chanx_1__0__midout_34_; -assign mux_2level_tapbuf_size16_16_inbus[5] = chanx_1__0__midout_35_; -assign mux_2level_tapbuf_size16_16_inbus[6] = chanx_1__0__midout_46_; -assign mux_2level_tapbuf_size16_16_inbus[7] = chanx_1__0__midout_47_; -assign mux_2level_tapbuf_size16_16_inbus[8] = chanx_1__0__midout_58_; -assign mux_2level_tapbuf_size16_16_inbus[9] = chanx_1__0__midout_59_; -assign mux_2level_tapbuf_size16_16_inbus[10] = chanx_1__0__midout_70_; -assign mux_2level_tapbuf_size16_16_inbus[11] = chanx_1__0__midout_71_; -assign mux_2level_tapbuf_size16_16_inbus[12] = chanx_1__0__midout_84_; -assign mux_2level_tapbuf_size16_16_inbus[13] = chanx_1__0__midout_85_; -assign mux_2level_tapbuf_size16_16_inbus[14] = chanx_1__0__midout_96_; -assign mux_2level_tapbuf_size16_16_inbus[15] = chanx_1__0__midout_97_; -wire [568:575] mux_2level_tapbuf_size16_16_configbus0; -wire [568:575] mux_2level_tapbuf_size16_16_configbus1; -wire [568:575] mux_2level_tapbuf_size16_16_sram_blwl_out ; -wire [568:575] mux_2level_tapbuf_size16_16_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_16_configbus0[568:575] = sram_blwl_bl[568:575] ; -assign mux_2level_tapbuf_size16_16_configbus1[568:575] = sram_blwl_wl[568:575] ; -wire [568:575] mux_2level_tapbuf_size16_16_configbus0_b; -assign mux_2level_tapbuf_size16_16_configbus0_b[568:575] = sram_blwl_blb[568:575] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_16_ (mux_2level_tapbuf_size16_16_inbus, grid_1__0__pin_0__0__12_, mux_2level_tapbuf_size16_16_sram_blwl_out[568:575] , -mux_2level_tapbuf_size16_16_sram_blwl_outb[568:575] ); -//----- SRAM bits for MUX[16], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_568_ (mux_2level_tapbuf_size16_16_sram_blwl_out[568:568] ,mux_2level_tapbuf_size16_16_sram_blwl_out[568:568] ,mux_2level_tapbuf_size16_16_sram_blwl_outb[568:568] ,mux_2level_tapbuf_size16_16_configbus0[568:568], mux_2level_tapbuf_size16_16_configbus1[568:568] , mux_2level_tapbuf_size16_16_configbus0_b[568:568] ); -sram6T_blwl sram_blwl_569_ (mux_2level_tapbuf_size16_16_sram_blwl_out[569:569] ,mux_2level_tapbuf_size16_16_sram_blwl_out[569:569] ,mux_2level_tapbuf_size16_16_sram_blwl_outb[569:569] ,mux_2level_tapbuf_size16_16_configbus0[569:569], mux_2level_tapbuf_size16_16_configbus1[569:569] , mux_2level_tapbuf_size16_16_configbus0_b[569:569] ); -sram6T_blwl sram_blwl_570_ (mux_2level_tapbuf_size16_16_sram_blwl_out[570:570] ,mux_2level_tapbuf_size16_16_sram_blwl_out[570:570] ,mux_2level_tapbuf_size16_16_sram_blwl_outb[570:570] ,mux_2level_tapbuf_size16_16_configbus0[570:570], mux_2level_tapbuf_size16_16_configbus1[570:570] , mux_2level_tapbuf_size16_16_configbus0_b[570:570] ); -sram6T_blwl sram_blwl_571_ (mux_2level_tapbuf_size16_16_sram_blwl_out[571:571] ,mux_2level_tapbuf_size16_16_sram_blwl_out[571:571] ,mux_2level_tapbuf_size16_16_sram_blwl_outb[571:571] ,mux_2level_tapbuf_size16_16_configbus0[571:571], mux_2level_tapbuf_size16_16_configbus1[571:571] , mux_2level_tapbuf_size16_16_configbus0_b[571:571] ); -sram6T_blwl sram_blwl_572_ (mux_2level_tapbuf_size16_16_sram_blwl_out[572:572] ,mux_2level_tapbuf_size16_16_sram_blwl_out[572:572] ,mux_2level_tapbuf_size16_16_sram_blwl_outb[572:572] ,mux_2level_tapbuf_size16_16_configbus0[572:572], mux_2level_tapbuf_size16_16_configbus1[572:572] , mux_2level_tapbuf_size16_16_configbus0_b[572:572] ); -sram6T_blwl sram_blwl_573_ (mux_2level_tapbuf_size16_16_sram_blwl_out[573:573] ,mux_2level_tapbuf_size16_16_sram_blwl_out[573:573] ,mux_2level_tapbuf_size16_16_sram_blwl_outb[573:573] ,mux_2level_tapbuf_size16_16_configbus0[573:573], mux_2level_tapbuf_size16_16_configbus1[573:573] , mux_2level_tapbuf_size16_16_configbus0_b[573:573] ); -sram6T_blwl sram_blwl_574_ (mux_2level_tapbuf_size16_16_sram_blwl_out[574:574] ,mux_2level_tapbuf_size16_16_sram_blwl_out[574:574] ,mux_2level_tapbuf_size16_16_sram_blwl_outb[574:574] ,mux_2level_tapbuf_size16_16_configbus0[574:574], mux_2level_tapbuf_size16_16_configbus1[574:574] , mux_2level_tapbuf_size16_16_configbus0_b[574:574] ); -sram6T_blwl sram_blwl_575_ (mux_2level_tapbuf_size16_16_sram_blwl_out[575:575] ,mux_2level_tapbuf_size16_16_sram_blwl_out[575:575] ,mux_2level_tapbuf_size16_16_sram_blwl_outb[575:575] ,mux_2level_tapbuf_size16_16_configbus0[575:575], mux_2level_tapbuf_size16_16_configbus1[575:575] , mux_2level_tapbuf_size16_16_configbus0_b[575:575] ); -wire [0:15] mux_2level_tapbuf_size16_17_inbus; -assign mux_2level_tapbuf_size16_17_inbus[0] = chanx_1__0__midout_10_; -assign mux_2level_tapbuf_size16_17_inbus[1] = chanx_1__0__midout_11_; -assign mux_2level_tapbuf_size16_17_inbus[2] = chanx_1__0__midout_22_; -assign mux_2level_tapbuf_size16_17_inbus[3] = chanx_1__0__midout_23_; -assign mux_2level_tapbuf_size16_17_inbus[4] = chanx_1__0__midout_34_; -assign mux_2level_tapbuf_size16_17_inbus[5] = chanx_1__0__midout_35_; -assign mux_2level_tapbuf_size16_17_inbus[6] = chanx_1__0__midout_48_; -assign mux_2level_tapbuf_size16_17_inbus[7] = chanx_1__0__midout_49_; -assign mux_2level_tapbuf_size16_17_inbus[8] = chanx_1__0__midout_60_; -assign mux_2level_tapbuf_size16_17_inbus[9] = chanx_1__0__midout_61_; -assign mux_2level_tapbuf_size16_17_inbus[10] = chanx_1__0__midout_72_; -assign mux_2level_tapbuf_size16_17_inbus[11] = chanx_1__0__midout_73_; -assign mux_2level_tapbuf_size16_17_inbus[12] = chanx_1__0__midout_84_; -assign mux_2level_tapbuf_size16_17_inbus[13] = chanx_1__0__midout_85_; -assign mux_2level_tapbuf_size16_17_inbus[14] = chanx_1__0__midout_98_; -assign mux_2level_tapbuf_size16_17_inbus[15] = chanx_1__0__midout_99_; -wire [576:583] mux_2level_tapbuf_size16_17_configbus0; -wire [576:583] mux_2level_tapbuf_size16_17_configbus1; -wire [576:583] mux_2level_tapbuf_size16_17_sram_blwl_out ; -wire [576:583] mux_2level_tapbuf_size16_17_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_17_configbus0[576:583] = sram_blwl_bl[576:583] ; -assign mux_2level_tapbuf_size16_17_configbus1[576:583] = sram_blwl_wl[576:583] ; -wire [576:583] mux_2level_tapbuf_size16_17_configbus0_b; -assign mux_2level_tapbuf_size16_17_configbus0_b[576:583] = sram_blwl_blb[576:583] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_17_ (mux_2level_tapbuf_size16_17_inbus, grid_1__0__pin_0__0__14_, mux_2level_tapbuf_size16_17_sram_blwl_out[576:583] , -mux_2level_tapbuf_size16_17_sram_blwl_outb[576:583] ); -//----- SRAM bits for MUX[17], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_576_ (mux_2level_tapbuf_size16_17_sram_blwl_out[576:576] ,mux_2level_tapbuf_size16_17_sram_blwl_out[576:576] ,mux_2level_tapbuf_size16_17_sram_blwl_outb[576:576] ,mux_2level_tapbuf_size16_17_configbus0[576:576], mux_2level_tapbuf_size16_17_configbus1[576:576] , mux_2level_tapbuf_size16_17_configbus0_b[576:576] ); -sram6T_blwl sram_blwl_577_ (mux_2level_tapbuf_size16_17_sram_blwl_out[577:577] ,mux_2level_tapbuf_size16_17_sram_blwl_out[577:577] ,mux_2level_tapbuf_size16_17_sram_blwl_outb[577:577] ,mux_2level_tapbuf_size16_17_configbus0[577:577], mux_2level_tapbuf_size16_17_configbus1[577:577] , mux_2level_tapbuf_size16_17_configbus0_b[577:577] ); -sram6T_blwl sram_blwl_578_ (mux_2level_tapbuf_size16_17_sram_blwl_out[578:578] ,mux_2level_tapbuf_size16_17_sram_blwl_out[578:578] ,mux_2level_tapbuf_size16_17_sram_blwl_outb[578:578] ,mux_2level_tapbuf_size16_17_configbus0[578:578], mux_2level_tapbuf_size16_17_configbus1[578:578] , mux_2level_tapbuf_size16_17_configbus0_b[578:578] ); -sram6T_blwl sram_blwl_579_ (mux_2level_tapbuf_size16_17_sram_blwl_out[579:579] ,mux_2level_tapbuf_size16_17_sram_blwl_out[579:579] ,mux_2level_tapbuf_size16_17_sram_blwl_outb[579:579] ,mux_2level_tapbuf_size16_17_configbus0[579:579], mux_2level_tapbuf_size16_17_configbus1[579:579] , mux_2level_tapbuf_size16_17_configbus0_b[579:579] ); -sram6T_blwl sram_blwl_580_ (mux_2level_tapbuf_size16_17_sram_blwl_out[580:580] ,mux_2level_tapbuf_size16_17_sram_blwl_out[580:580] ,mux_2level_tapbuf_size16_17_sram_blwl_outb[580:580] ,mux_2level_tapbuf_size16_17_configbus0[580:580], mux_2level_tapbuf_size16_17_configbus1[580:580] , mux_2level_tapbuf_size16_17_configbus0_b[580:580] ); -sram6T_blwl sram_blwl_581_ (mux_2level_tapbuf_size16_17_sram_blwl_out[581:581] ,mux_2level_tapbuf_size16_17_sram_blwl_out[581:581] ,mux_2level_tapbuf_size16_17_sram_blwl_outb[581:581] ,mux_2level_tapbuf_size16_17_configbus0[581:581], mux_2level_tapbuf_size16_17_configbus1[581:581] , mux_2level_tapbuf_size16_17_configbus0_b[581:581] ); -sram6T_blwl sram_blwl_582_ (mux_2level_tapbuf_size16_17_sram_blwl_out[582:582] ,mux_2level_tapbuf_size16_17_sram_blwl_out[582:582] ,mux_2level_tapbuf_size16_17_sram_blwl_outb[582:582] ,mux_2level_tapbuf_size16_17_configbus0[582:582], mux_2level_tapbuf_size16_17_configbus1[582:582] , mux_2level_tapbuf_size16_17_configbus0_b[582:582] ); -sram6T_blwl sram_blwl_583_ (mux_2level_tapbuf_size16_17_sram_blwl_out[583:583] ,mux_2level_tapbuf_size16_17_sram_blwl_out[583:583] ,mux_2level_tapbuf_size16_17_sram_blwl_outb[583:583] ,mux_2level_tapbuf_size16_17_configbus0[583:583], mux_2level_tapbuf_size16_17_configbus1[583:583] , mux_2level_tapbuf_size16_17_configbus0_b[583:583] ); -endmodule -//----- END Verilog Module of Connection Box -X direction [1][0] ----- - diff --git a/examples/verilog_test_example_2/routing/cbx_1_1.v b/examples/verilog_test_example_2/routing/cbx_1_1.v deleted file mode 100644 index 00f5ca2e8..000000000 --- a/examples/verilog_test_example_2/routing/cbx_1_1.v +++ /dev/null @@ -1,946 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Connection Block - X direction [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Connection Box -X direction [1][1] ----- -module cbx_1__1_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input chanx_1__1__midout_0_, - -input chanx_1__1__midout_1_, - -input chanx_1__1__midout_2_, - -input chanx_1__1__midout_3_, - -input chanx_1__1__midout_4_, - -input chanx_1__1__midout_5_, - -input chanx_1__1__midout_6_, - -input chanx_1__1__midout_7_, - -input chanx_1__1__midout_8_, - -input chanx_1__1__midout_9_, - -input chanx_1__1__midout_10_, - -input chanx_1__1__midout_11_, - -input chanx_1__1__midout_12_, - -input chanx_1__1__midout_13_, - -input chanx_1__1__midout_14_, - -input chanx_1__1__midout_15_, - -input chanx_1__1__midout_16_, - -input chanx_1__1__midout_17_, - -input chanx_1__1__midout_18_, - -input chanx_1__1__midout_19_, - -input chanx_1__1__midout_20_, - -input chanx_1__1__midout_21_, - -input chanx_1__1__midout_22_, - -input chanx_1__1__midout_23_, - -input chanx_1__1__midout_24_, - -input chanx_1__1__midout_25_, - -input chanx_1__1__midout_26_, - -input chanx_1__1__midout_27_, - -input chanx_1__1__midout_28_, - -input chanx_1__1__midout_29_, - -input chanx_1__1__midout_30_, - -input chanx_1__1__midout_31_, - -input chanx_1__1__midout_32_, - -input chanx_1__1__midout_33_, - -input chanx_1__1__midout_34_, - -input chanx_1__1__midout_35_, - -input chanx_1__1__midout_36_, - -input chanx_1__1__midout_37_, - -input chanx_1__1__midout_38_, - -input chanx_1__1__midout_39_, - -input chanx_1__1__midout_40_, - -input chanx_1__1__midout_41_, - -input chanx_1__1__midout_42_, - -input chanx_1__1__midout_43_, - -input chanx_1__1__midout_44_, - -input chanx_1__1__midout_45_, - -input chanx_1__1__midout_46_, - -input chanx_1__1__midout_47_, - -input chanx_1__1__midout_48_, - -input chanx_1__1__midout_49_, - -input chanx_1__1__midout_50_, - -input chanx_1__1__midout_51_, - -input chanx_1__1__midout_52_, - -input chanx_1__1__midout_53_, - -input chanx_1__1__midout_54_, - -input chanx_1__1__midout_55_, - -input chanx_1__1__midout_56_, - -input chanx_1__1__midout_57_, - -input chanx_1__1__midout_58_, - -input chanx_1__1__midout_59_, - -input chanx_1__1__midout_60_, - -input chanx_1__1__midout_61_, - -input chanx_1__1__midout_62_, - -input chanx_1__1__midout_63_, - -input chanx_1__1__midout_64_, - -input chanx_1__1__midout_65_, - -input chanx_1__1__midout_66_, - -input chanx_1__1__midout_67_, - -input chanx_1__1__midout_68_, - -input chanx_1__1__midout_69_, - -input chanx_1__1__midout_70_, - -input chanx_1__1__midout_71_, - -input chanx_1__1__midout_72_, - -input chanx_1__1__midout_73_, - -input chanx_1__1__midout_74_, - -input chanx_1__1__midout_75_, - -input chanx_1__1__midout_76_, - -input chanx_1__1__midout_77_, - -input chanx_1__1__midout_78_, - -input chanx_1__1__midout_79_, - -input chanx_1__1__midout_80_, - -input chanx_1__1__midout_81_, - -input chanx_1__1__midout_82_, - -input chanx_1__1__midout_83_, - -input chanx_1__1__midout_84_, - -input chanx_1__1__midout_85_, - -input chanx_1__1__midout_86_, - -input chanx_1__1__midout_87_, - -input chanx_1__1__midout_88_, - -input chanx_1__1__midout_89_, - -input chanx_1__1__midout_90_, - -input chanx_1__1__midout_91_, - -input chanx_1__1__midout_92_, - -input chanx_1__1__midout_93_, - -input chanx_1__1__midout_94_, - -input chanx_1__1__midout_95_, - -input chanx_1__1__midout_96_, - -input chanx_1__1__midout_97_, - -input chanx_1__1__midout_98_, - -input chanx_1__1__midout_99_, - -output grid_1__2__pin_0__2__0_, - -output grid_1__2__pin_0__2__2_, - -output grid_1__2__pin_0__2__4_, - -output grid_1__2__pin_0__2__6_, - -output grid_1__2__pin_0__2__8_, - -output grid_1__2__pin_0__2__10_, - -output grid_1__2__pin_0__2__12_, - -output grid_1__2__pin_0__2__14_, - -output grid_1__1__pin_0__0__0_, - -output grid_1__1__pin_0__0__4_, - -output grid_1__1__pin_0__0__8_, - -output grid_1__1__pin_0__0__12_, - -output grid_1__1__pin_0__0__16_, - -output grid_1__1__pin_0__0__20_, - -output grid_1__1__pin_0__0__24_, - -output grid_1__1__pin_0__0__28_, - -output grid_1__1__pin_0__0__32_, - -output grid_1__1__pin_0__0__36_, - -input [584:727] sram_blwl_bl , -input [584:727] sram_blwl_wl , -input [584:727] sram_blwl_blb ); -wire [0:15] mux_2level_tapbuf_size16_18_inbus; -assign mux_2level_tapbuf_size16_18_inbus[0] = chanx_1__1__midout_6_; -assign mux_2level_tapbuf_size16_18_inbus[1] = chanx_1__1__midout_7_; -assign mux_2level_tapbuf_size16_18_inbus[2] = chanx_1__1__midout_10_; -assign mux_2level_tapbuf_size16_18_inbus[3] = chanx_1__1__midout_11_; -assign mux_2level_tapbuf_size16_18_inbus[4] = chanx_1__1__midout_30_; -assign mux_2level_tapbuf_size16_18_inbus[5] = chanx_1__1__midout_31_; -assign mux_2level_tapbuf_size16_18_inbus[6] = chanx_1__1__midout_36_; -assign mux_2level_tapbuf_size16_18_inbus[7] = chanx_1__1__midout_37_; -assign mux_2level_tapbuf_size16_18_inbus[8] = chanx_1__1__midout_48_; -assign mux_2level_tapbuf_size16_18_inbus[9] = chanx_1__1__midout_49_; -assign mux_2level_tapbuf_size16_18_inbus[10] = chanx_1__1__midout_60_; -assign mux_2level_tapbuf_size16_18_inbus[11] = chanx_1__1__midout_61_; -assign mux_2level_tapbuf_size16_18_inbus[12] = chanx_1__1__midout_74_; -assign mux_2level_tapbuf_size16_18_inbus[13] = chanx_1__1__midout_75_; -assign mux_2level_tapbuf_size16_18_inbus[14] = chanx_1__1__midout_88_; -assign mux_2level_tapbuf_size16_18_inbus[15] = chanx_1__1__midout_89_; -wire [584:591] mux_2level_tapbuf_size16_18_configbus0; -wire [584:591] mux_2level_tapbuf_size16_18_configbus1; -wire [584:591] mux_2level_tapbuf_size16_18_sram_blwl_out ; -wire [584:591] mux_2level_tapbuf_size16_18_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_18_configbus0[584:591] = sram_blwl_bl[584:591] ; -assign mux_2level_tapbuf_size16_18_configbus1[584:591] = sram_blwl_wl[584:591] ; -wire [584:591] mux_2level_tapbuf_size16_18_configbus0_b; -assign mux_2level_tapbuf_size16_18_configbus0_b[584:591] = sram_blwl_blb[584:591] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_18_ (mux_2level_tapbuf_size16_18_inbus, grid_1__2__pin_0__2__0_, mux_2level_tapbuf_size16_18_sram_blwl_out[584:591] , -mux_2level_tapbuf_size16_18_sram_blwl_outb[584:591] ); -//----- SRAM bits for MUX[18], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_584_ (mux_2level_tapbuf_size16_18_sram_blwl_out[584:584] ,mux_2level_tapbuf_size16_18_sram_blwl_out[584:584] ,mux_2level_tapbuf_size16_18_sram_blwl_outb[584:584] ,mux_2level_tapbuf_size16_18_configbus0[584:584], mux_2level_tapbuf_size16_18_configbus1[584:584] , mux_2level_tapbuf_size16_18_configbus0_b[584:584] ); -sram6T_blwl sram_blwl_585_ (mux_2level_tapbuf_size16_18_sram_blwl_out[585:585] ,mux_2level_tapbuf_size16_18_sram_blwl_out[585:585] ,mux_2level_tapbuf_size16_18_sram_blwl_outb[585:585] ,mux_2level_tapbuf_size16_18_configbus0[585:585], mux_2level_tapbuf_size16_18_configbus1[585:585] , mux_2level_tapbuf_size16_18_configbus0_b[585:585] ); -sram6T_blwl sram_blwl_586_ (mux_2level_tapbuf_size16_18_sram_blwl_out[586:586] ,mux_2level_tapbuf_size16_18_sram_blwl_out[586:586] ,mux_2level_tapbuf_size16_18_sram_blwl_outb[586:586] ,mux_2level_tapbuf_size16_18_configbus0[586:586], mux_2level_tapbuf_size16_18_configbus1[586:586] , mux_2level_tapbuf_size16_18_configbus0_b[586:586] ); -sram6T_blwl sram_blwl_587_ (mux_2level_tapbuf_size16_18_sram_blwl_out[587:587] ,mux_2level_tapbuf_size16_18_sram_blwl_out[587:587] ,mux_2level_tapbuf_size16_18_sram_blwl_outb[587:587] ,mux_2level_tapbuf_size16_18_configbus0[587:587], mux_2level_tapbuf_size16_18_configbus1[587:587] , mux_2level_tapbuf_size16_18_configbus0_b[587:587] ); -sram6T_blwl sram_blwl_588_ (mux_2level_tapbuf_size16_18_sram_blwl_out[588:588] ,mux_2level_tapbuf_size16_18_sram_blwl_out[588:588] ,mux_2level_tapbuf_size16_18_sram_blwl_outb[588:588] ,mux_2level_tapbuf_size16_18_configbus0[588:588], mux_2level_tapbuf_size16_18_configbus1[588:588] , mux_2level_tapbuf_size16_18_configbus0_b[588:588] ); -sram6T_blwl sram_blwl_589_ (mux_2level_tapbuf_size16_18_sram_blwl_out[589:589] ,mux_2level_tapbuf_size16_18_sram_blwl_out[589:589] ,mux_2level_tapbuf_size16_18_sram_blwl_outb[589:589] ,mux_2level_tapbuf_size16_18_configbus0[589:589], mux_2level_tapbuf_size16_18_configbus1[589:589] , mux_2level_tapbuf_size16_18_configbus0_b[589:589] ); -sram6T_blwl sram_blwl_590_ (mux_2level_tapbuf_size16_18_sram_blwl_out[590:590] ,mux_2level_tapbuf_size16_18_sram_blwl_out[590:590] ,mux_2level_tapbuf_size16_18_sram_blwl_outb[590:590] ,mux_2level_tapbuf_size16_18_configbus0[590:590], mux_2level_tapbuf_size16_18_configbus1[590:590] , mux_2level_tapbuf_size16_18_configbus0_b[590:590] ); -sram6T_blwl sram_blwl_591_ (mux_2level_tapbuf_size16_18_sram_blwl_out[591:591] ,mux_2level_tapbuf_size16_18_sram_blwl_out[591:591] ,mux_2level_tapbuf_size16_18_sram_blwl_outb[591:591] ,mux_2level_tapbuf_size16_18_configbus0[591:591], mux_2level_tapbuf_size16_18_configbus1[591:591] , mux_2level_tapbuf_size16_18_configbus0_b[591:591] ); -wire [0:15] mux_2level_tapbuf_size16_19_inbus; -assign mux_2level_tapbuf_size16_19_inbus[0] = chanx_1__1__midout_0_; -assign mux_2level_tapbuf_size16_19_inbus[1] = chanx_1__1__midout_1_; -assign mux_2level_tapbuf_size16_19_inbus[2] = chanx_1__1__midout_12_; -assign mux_2level_tapbuf_size16_19_inbus[3] = chanx_1__1__midout_13_; -assign mux_2level_tapbuf_size16_19_inbus[4] = chanx_1__1__midout_24_; -assign mux_2level_tapbuf_size16_19_inbus[5] = chanx_1__1__midout_25_; -assign mux_2level_tapbuf_size16_19_inbus[6] = chanx_1__1__midout_36_; -assign mux_2level_tapbuf_size16_19_inbus[7] = chanx_1__1__midout_37_; -assign mux_2level_tapbuf_size16_19_inbus[8] = chanx_1__1__midout_54_; -assign mux_2level_tapbuf_size16_19_inbus[9] = chanx_1__1__midout_55_; -assign mux_2level_tapbuf_size16_19_inbus[10] = chanx_1__1__midout_66_; -assign mux_2level_tapbuf_size16_19_inbus[11] = chanx_1__1__midout_67_; -assign mux_2level_tapbuf_size16_19_inbus[12] = chanx_1__1__midout_76_; -assign mux_2level_tapbuf_size16_19_inbus[13] = chanx_1__1__midout_77_; -assign mux_2level_tapbuf_size16_19_inbus[14] = chanx_1__1__midout_88_; -assign mux_2level_tapbuf_size16_19_inbus[15] = chanx_1__1__midout_89_; -wire [592:599] mux_2level_tapbuf_size16_19_configbus0; -wire [592:599] mux_2level_tapbuf_size16_19_configbus1; -wire [592:599] mux_2level_tapbuf_size16_19_sram_blwl_out ; -wire [592:599] mux_2level_tapbuf_size16_19_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_19_configbus0[592:599] = sram_blwl_bl[592:599] ; -assign mux_2level_tapbuf_size16_19_configbus1[592:599] = sram_blwl_wl[592:599] ; -wire [592:599] mux_2level_tapbuf_size16_19_configbus0_b; -assign mux_2level_tapbuf_size16_19_configbus0_b[592:599] = sram_blwl_blb[592:599] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_19_ (mux_2level_tapbuf_size16_19_inbus, grid_1__2__pin_0__2__2_, mux_2level_tapbuf_size16_19_sram_blwl_out[592:599] , -mux_2level_tapbuf_size16_19_sram_blwl_outb[592:599] ); -//----- SRAM bits for MUX[19], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_592_ (mux_2level_tapbuf_size16_19_sram_blwl_out[592:592] ,mux_2level_tapbuf_size16_19_sram_blwl_out[592:592] ,mux_2level_tapbuf_size16_19_sram_blwl_outb[592:592] ,mux_2level_tapbuf_size16_19_configbus0[592:592], mux_2level_tapbuf_size16_19_configbus1[592:592] , mux_2level_tapbuf_size16_19_configbus0_b[592:592] ); -sram6T_blwl sram_blwl_593_ (mux_2level_tapbuf_size16_19_sram_blwl_out[593:593] ,mux_2level_tapbuf_size16_19_sram_blwl_out[593:593] ,mux_2level_tapbuf_size16_19_sram_blwl_outb[593:593] ,mux_2level_tapbuf_size16_19_configbus0[593:593], mux_2level_tapbuf_size16_19_configbus1[593:593] , mux_2level_tapbuf_size16_19_configbus0_b[593:593] ); -sram6T_blwl sram_blwl_594_ (mux_2level_tapbuf_size16_19_sram_blwl_out[594:594] ,mux_2level_tapbuf_size16_19_sram_blwl_out[594:594] ,mux_2level_tapbuf_size16_19_sram_blwl_outb[594:594] ,mux_2level_tapbuf_size16_19_configbus0[594:594], mux_2level_tapbuf_size16_19_configbus1[594:594] , mux_2level_tapbuf_size16_19_configbus0_b[594:594] ); -sram6T_blwl sram_blwl_595_ (mux_2level_tapbuf_size16_19_sram_blwl_out[595:595] ,mux_2level_tapbuf_size16_19_sram_blwl_out[595:595] ,mux_2level_tapbuf_size16_19_sram_blwl_outb[595:595] ,mux_2level_tapbuf_size16_19_configbus0[595:595], mux_2level_tapbuf_size16_19_configbus1[595:595] , mux_2level_tapbuf_size16_19_configbus0_b[595:595] ); -sram6T_blwl sram_blwl_596_ (mux_2level_tapbuf_size16_19_sram_blwl_out[596:596] ,mux_2level_tapbuf_size16_19_sram_blwl_out[596:596] ,mux_2level_tapbuf_size16_19_sram_blwl_outb[596:596] ,mux_2level_tapbuf_size16_19_configbus0[596:596], mux_2level_tapbuf_size16_19_configbus1[596:596] , mux_2level_tapbuf_size16_19_configbus0_b[596:596] ); -sram6T_blwl sram_blwl_597_ (mux_2level_tapbuf_size16_19_sram_blwl_out[597:597] ,mux_2level_tapbuf_size16_19_sram_blwl_out[597:597] ,mux_2level_tapbuf_size16_19_sram_blwl_outb[597:597] ,mux_2level_tapbuf_size16_19_configbus0[597:597], mux_2level_tapbuf_size16_19_configbus1[597:597] , mux_2level_tapbuf_size16_19_configbus0_b[597:597] ); -sram6T_blwl sram_blwl_598_ (mux_2level_tapbuf_size16_19_sram_blwl_out[598:598] ,mux_2level_tapbuf_size16_19_sram_blwl_out[598:598] ,mux_2level_tapbuf_size16_19_sram_blwl_outb[598:598] ,mux_2level_tapbuf_size16_19_configbus0[598:598], mux_2level_tapbuf_size16_19_configbus1[598:598] , mux_2level_tapbuf_size16_19_configbus0_b[598:598] ); -sram6T_blwl sram_blwl_599_ (mux_2level_tapbuf_size16_19_sram_blwl_out[599:599] ,mux_2level_tapbuf_size16_19_sram_blwl_out[599:599] ,mux_2level_tapbuf_size16_19_sram_blwl_outb[599:599] ,mux_2level_tapbuf_size16_19_configbus0[599:599], mux_2level_tapbuf_size16_19_configbus1[599:599] , mux_2level_tapbuf_size16_19_configbus0_b[599:599] ); -wire [0:15] mux_2level_tapbuf_size16_20_inbus; -assign mux_2level_tapbuf_size16_20_inbus[0] = chanx_1__1__midout_0_; -assign mux_2level_tapbuf_size16_20_inbus[1] = chanx_1__1__midout_1_; -assign mux_2level_tapbuf_size16_20_inbus[2] = chanx_1__1__midout_22_; -assign mux_2level_tapbuf_size16_20_inbus[3] = chanx_1__1__midout_23_; -assign mux_2level_tapbuf_size16_20_inbus[4] = chanx_1__1__midout_26_; -assign mux_2level_tapbuf_size16_20_inbus[5] = chanx_1__1__midout_27_; -assign mux_2level_tapbuf_size16_20_inbus[6] = chanx_1__1__midout_42_; -assign mux_2level_tapbuf_size16_20_inbus[7] = chanx_1__1__midout_43_; -assign mux_2level_tapbuf_size16_20_inbus[8] = chanx_1__1__midout_54_; -assign mux_2level_tapbuf_size16_20_inbus[9] = chanx_1__1__midout_55_; -assign mux_2level_tapbuf_size16_20_inbus[10] = chanx_1__1__midout_64_; -assign mux_2level_tapbuf_size16_20_inbus[11] = chanx_1__1__midout_65_; -assign mux_2level_tapbuf_size16_20_inbus[12] = chanx_1__1__midout_78_; -assign mux_2level_tapbuf_size16_20_inbus[13] = chanx_1__1__midout_79_; -assign mux_2level_tapbuf_size16_20_inbus[14] = chanx_1__1__midout_90_; -assign mux_2level_tapbuf_size16_20_inbus[15] = chanx_1__1__midout_91_; -wire [600:607] mux_2level_tapbuf_size16_20_configbus0; -wire [600:607] mux_2level_tapbuf_size16_20_configbus1; -wire [600:607] mux_2level_tapbuf_size16_20_sram_blwl_out ; -wire [600:607] mux_2level_tapbuf_size16_20_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_20_configbus0[600:607] = sram_blwl_bl[600:607] ; -assign mux_2level_tapbuf_size16_20_configbus1[600:607] = sram_blwl_wl[600:607] ; -wire [600:607] mux_2level_tapbuf_size16_20_configbus0_b; -assign mux_2level_tapbuf_size16_20_configbus0_b[600:607] = sram_blwl_blb[600:607] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_20_ (mux_2level_tapbuf_size16_20_inbus, grid_1__2__pin_0__2__4_, mux_2level_tapbuf_size16_20_sram_blwl_out[600:607] , -mux_2level_tapbuf_size16_20_sram_blwl_outb[600:607] ); -//----- SRAM bits for MUX[20], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_600_ (mux_2level_tapbuf_size16_20_sram_blwl_out[600:600] ,mux_2level_tapbuf_size16_20_sram_blwl_out[600:600] ,mux_2level_tapbuf_size16_20_sram_blwl_outb[600:600] ,mux_2level_tapbuf_size16_20_configbus0[600:600], mux_2level_tapbuf_size16_20_configbus1[600:600] , mux_2level_tapbuf_size16_20_configbus0_b[600:600] ); -sram6T_blwl sram_blwl_601_ (mux_2level_tapbuf_size16_20_sram_blwl_out[601:601] ,mux_2level_tapbuf_size16_20_sram_blwl_out[601:601] ,mux_2level_tapbuf_size16_20_sram_blwl_outb[601:601] ,mux_2level_tapbuf_size16_20_configbus0[601:601], mux_2level_tapbuf_size16_20_configbus1[601:601] , mux_2level_tapbuf_size16_20_configbus0_b[601:601] ); -sram6T_blwl sram_blwl_602_ (mux_2level_tapbuf_size16_20_sram_blwl_out[602:602] ,mux_2level_tapbuf_size16_20_sram_blwl_out[602:602] ,mux_2level_tapbuf_size16_20_sram_blwl_outb[602:602] ,mux_2level_tapbuf_size16_20_configbus0[602:602], mux_2level_tapbuf_size16_20_configbus1[602:602] , mux_2level_tapbuf_size16_20_configbus0_b[602:602] ); -sram6T_blwl sram_blwl_603_ (mux_2level_tapbuf_size16_20_sram_blwl_out[603:603] ,mux_2level_tapbuf_size16_20_sram_blwl_out[603:603] ,mux_2level_tapbuf_size16_20_sram_blwl_outb[603:603] ,mux_2level_tapbuf_size16_20_configbus0[603:603], mux_2level_tapbuf_size16_20_configbus1[603:603] , mux_2level_tapbuf_size16_20_configbus0_b[603:603] ); -sram6T_blwl sram_blwl_604_ (mux_2level_tapbuf_size16_20_sram_blwl_out[604:604] ,mux_2level_tapbuf_size16_20_sram_blwl_out[604:604] ,mux_2level_tapbuf_size16_20_sram_blwl_outb[604:604] ,mux_2level_tapbuf_size16_20_configbus0[604:604], mux_2level_tapbuf_size16_20_configbus1[604:604] , mux_2level_tapbuf_size16_20_configbus0_b[604:604] ); -sram6T_blwl sram_blwl_605_ (mux_2level_tapbuf_size16_20_sram_blwl_out[605:605] ,mux_2level_tapbuf_size16_20_sram_blwl_out[605:605] ,mux_2level_tapbuf_size16_20_sram_blwl_outb[605:605] ,mux_2level_tapbuf_size16_20_configbus0[605:605], mux_2level_tapbuf_size16_20_configbus1[605:605] , mux_2level_tapbuf_size16_20_configbus0_b[605:605] ); -sram6T_blwl sram_blwl_606_ (mux_2level_tapbuf_size16_20_sram_blwl_out[606:606] ,mux_2level_tapbuf_size16_20_sram_blwl_out[606:606] ,mux_2level_tapbuf_size16_20_sram_blwl_outb[606:606] ,mux_2level_tapbuf_size16_20_configbus0[606:606], mux_2level_tapbuf_size16_20_configbus1[606:606] , mux_2level_tapbuf_size16_20_configbus0_b[606:606] ); -sram6T_blwl sram_blwl_607_ (mux_2level_tapbuf_size16_20_sram_blwl_out[607:607] ,mux_2level_tapbuf_size16_20_sram_blwl_out[607:607] ,mux_2level_tapbuf_size16_20_sram_blwl_outb[607:607] ,mux_2level_tapbuf_size16_20_configbus0[607:607], mux_2level_tapbuf_size16_20_configbus1[607:607] , mux_2level_tapbuf_size16_20_configbus0_b[607:607] ); -wire [0:15] mux_2level_tapbuf_size16_21_inbus; -assign mux_2level_tapbuf_size16_21_inbus[0] = chanx_1__1__midout_2_; -assign mux_2level_tapbuf_size16_21_inbus[1] = chanx_1__1__midout_3_; -assign mux_2level_tapbuf_size16_21_inbus[2] = chanx_1__1__midout_22_; -assign mux_2level_tapbuf_size16_21_inbus[3] = chanx_1__1__midout_23_; -assign mux_2level_tapbuf_size16_21_inbus[4] = chanx_1__1__midout_28_; -assign mux_2level_tapbuf_size16_21_inbus[5] = chanx_1__1__midout_29_; -assign mux_2level_tapbuf_size16_21_inbus[6] = chanx_1__1__midout_40_; -assign mux_2level_tapbuf_size16_21_inbus[7] = chanx_1__1__midout_41_; -assign mux_2level_tapbuf_size16_21_inbus[8] = chanx_1__1__midout_52_; -assign mux_2level_tapbuf_size16_21_inbus[9] = chanx_1__1__midout_53_; -assign mux_2level_tapbuf_size16_21_inbus[10] = chanx_1__1__midout_64_; -assign mux_2level_tapbuf_size16_21_inbus[11] = chanx_1__1__midout_65_; -assign mux_2level_tapbuf_size16_21_inbus[12] = chanx_1__1__midout_80_; -assign mux_2level_tapbuf_size16_21_inbus[13] = chanx_1__1__midout_81_; -assign mux_2level_tapbuf_size16_21_inbus[14] = chanx_1__1__midout_92_; -assign mux_2level_tapbuf_size16_21_inbus[15] = chanx_1__1__midout_93_; -wire [608:615] mux_2level_tapbuf_size16_21_configbus0; -wire [608:615] mux_2level_tapbuf_size16_21_configbus1; -wire [608:615] mux_2level_tapbuf_size16_21_sram_blwl_out ; -wire [608:615] mux_2level_tapbuf_size16_21_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_21_configbus0[608:615] = sram_blwl_bl[608:615] ; -assign mux_2level_tapbuf_size16_21_configbus1[608:615] = sram_blwl_wl[608:615] ; -wire [608:615] mux_2level_tapbuf_size16_21_configbus0_b; -assign mux_2level_tapbuf_size16_21_configbus0_b[608:615] = sram_blwl_blb[608:615] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_21_ (mux_2level_tapbuf_size16_21_inbus, grid_1__2__pin_0__2__6_, mux_2level_tapbuf_size16_21_sram_blwl_out[608:615] , -mux_2level_tapbuf_size16_21_sram_blwl_outb[608:615] ); -//----- SRAM bits for MUX[21], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_608_ (mux_2level_tapbuf_size16_21_sram_blwl_out[608:608] ,mux_2level_tapbuf_size16_21_sram_blwl_out[608:608] ,mux_2level_tapbuf_size16_21_sram_blwl_outb[608:608] ,mux_2level_tapbuf_size16_21_configbus0[608:608], mux_2level_tapbuf_size16_21_configbus1[608:608] , mux_2level_tapbuf_size16_21_configbus0_b[608:608] ); -sram6T_blwl sram_blwl_609_ (mux_2level_tapbuf_size16_21_sram_blwl_out[609:609] ,mux_2level_tapbuf_size16_21_sram_blwl_out[609:609] ,mux_2level_tapbuf_size16_21_sram_blwl_outb[609:609] ,mux_2level_tapbuf_size16_21_configbus0[609:609], mux_2level_tapbuf_size16_21_configbus1[609:609] , mux_2level_tapbuf_size16_21_configbus0_b[609:609] ); -sram6T_blwl sram_blwl_610_ (mux_2level_tapbuf_size16_21_sram_blwl_out[610:610] ,mux_2level_tapbuf_size16_21_sram_blwl_out[610:610] ,mux_2level_tapbuf_size16_21_sram_blwl_outb[610:610] ,mux_2level_tapbuf_size16_21_configbus0[610:610], mux_2level_tapbuf_size16_21_configbus1[610:610] , mux_2level_tapbuf_size16_21_configbus0_b[610:610] ); -sram6T_blwl sram_blwl_611_ (mux_2level_tapbuf_size16_21_sram_blwl_out[611:611] ,mux_2level_tapbuf_size16_21_sram_blwl_out[611:611] ,mux_2level_tapbuf_size16_21_sram_blwl_outb[611:611] ,mux_2level_tapbuf_size16_21_configbus0[611:611], mux_2level_tapbuf_size16_21_configbus1[611:611] , mux_2level_tapbuf_size16_21_configbus0_b[611:611] ); -sram6T_blwl sram_blwl_612_ (mux_2level_tapbuf_size16_21_sram_blwl_out[612:612] ,mux_2level_tapbuf_size16_21_sram_blwl_out[612:612] ,mux_2level_tapbuf_size16_21_sram_blwl_outb[612:612] ,mux_2level_tapbuf_size16_21_configbus0[612:612], mux_2level_tapbuf_size16_21_configbus1[612:612] , mux_2level_tapbuf_size16_21_configbus0_b[612:612] ); -sram6T_blwl sram_blwl_613_ (mux_2level_tapbuf_size16_21_sram_blwl_out[613:613] ,mux_2level_tapbuf_size16_21_sram_blwl_out[613:613] ,mux_2level_tapbuf_size16_21_sram_blwl_outb[613:613] ,mux_2level_tapbuf_size16_21_configbus0[613:613], mux_2level_tapbuf_size16_21_configbus1[613:613] , mux_2level_tapbuf_size16_21_configbus0_b[613:613] ); -sram6T_blwl sram_blwl_614_ (mux_2level_tapbuf_size16_21_sram_blwl_out[614:614] ,mux_2level_tapbuf_size16_21_sram_blwl_out[614:614] ,mux_2level_tapbuf_size16_21_sram_blwl_outb[614:614] ,mux_2level_tapbuf_size16_21_configbus0[614:614], mux_2level_tapbuf_size16_21_configbus1[614:614] , mux_2level_tapbuf_size16_21_configbus0_b[614:614] ); -sram6T_blwl sram_blwl_615_ (mux_2level_tapbuf_size16_21_sram_blwl_out[615:615] ,mux_2level_tapbuf_size16_21_sram_blwl_out[615:615] ,mux_2level_tapbuf_size16_21_sram_blwl_outb[615:615] ,mux_2level_tapbuf_size16_21_configbus0[615:615], mux_2level_tapbuf_size16_21_configbus1[615:615] , mux_2level_tapbuf_size16_21_configbus0_b[615:615] ); -wire [0:15] mux_2level_tapbuf_size16_22_inbus; -assign mux_2level_tapbuf_size16_22_inbus[0] = chanx_1__1__midout_4_; -assign mux_2level_tapbuf_size16_22_inbus[1] = chanx_1__1__midout_5_; -assign mux_2level_tapbuf_size16_22_inbus[2] = chanx_1__1__midout_16_; -assign mux_2level_tapbuf_size16_22_inbus[3] = chanx_1__1__midout_17_; -assign mux_2level_tapbuf_size16_22_inbus[4] = chanx_1__1__midout_38_; -assign mux_2level_tapbuf_size16_22_inbus[5] = chanx_1__1__midout_39_; -assign mux_2level_tapbuf_size16_22_inbus[6] = chanx_1__1__midout_46_; -assign mux_2level_tapbuf_size16_22_inbus[7] = chanx_1__1__midout_47_; -assign mux_2level_tapbuf_size16_22_inbus[8] = chanx_1__1__midout_58_; -assign mux_2level_tapbuf_size16_22_inbus[9] = chanx_1__1__midout_59_; -assign mux_2level_tapbuf_size16_22_inbus[10] = chanx_1__1__midout_68_; -assign mux_2level_tapbuf_size16_22_inbus[11] = chanx_1__1__midout_69_; -assign mux_2level_tapbuf_size16_22_inbus[12] = chanx_1__1__midout_82_; -assign mux_2level_tapbuf_size16_22_inbus[13] = chanx_1__1__midout_83_; -assign mux_2level_tapbuf_size16_22_inbus[14] = chanx_1__1__midout_94_; -assign mux_2level_tapbuf_size16_22_inbus[15] = chanx_1__1__midout_95_; -wire [616:623] mux_2level_tapbuf_size16_22_configbus0; -wire [616:623] mux_2level_tapbuf_size16_22_configbus1; -wire [616:623] mux_2level_tapbuf_size16_22_sram_blwl_out ; -wire [616:623] mux_2level_tapbuf_size16_22_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_22_configbus0[616:623] = sram_blwl_bl[616:623] ; -assign mux_2level_tapbuf_size16_22_configbus1[616:623] = sram_blwl_wl[616:623] ; -wire [616:623] mux_2level_tapbuf_size16_22_configbus0_b; -assign mux_2level_tapbuf_size16_22_configbus0_b[616:623] = sram_blwl_blb[616:623] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_22_ (mux_2level_tapbuf_size16_22_inbus, grid_1__2__pin_0__2__8_, mux_2level_tapbuf_size16_22_sram_blwl_out[616:623] , -mux_2level_tapbuf_size16_22_sram_blwl_outb[616:623] ); -//----- SRAM bits for MUX[22], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_616_ (mux_2level_tapbuf_size16_22_sram_blwl_out[616:616] ,mux_2level_tapbuf_size16_22_sram_blwl_out[616:616] ,mux_2level_tapbuf_size16_22_sram_blwl_outb[616:616] ,mux_2level_tapbuf_size16_22_configbus0[616:616], mux_2level_tapbuf_size16_22_configbus1[616:616] , mux_2level_tapbuf_size16_22_configbus0_b[616:616] ); -sram6T_blwl sram_blwl_617_ (mux_2level_tapbuf_size16_22_sram_blwl_out[617:617] ,mux_2level_tapbuf_size16_22_sram_blwl_out[617:617] ,mux_2level_tapbuf_size16_22_sram_blwl_outb[617:617] ,mux_2level_tapbuf_size16_22_configbus0[617:617], mux_2level_tapbuf_size16_22_configbus1[617:617] , mux_2level_tapbuf_size16_22_configbus0_b[617:617] ); -sram6T_blwl sram_blwl_618_ (mux_2level_tapbuf_size16_22_sram_blwl_out[618:618] ,mux_2level_tapbuf_size16_22_sram_blwl_out[618:618] ,mux_2level_tapbuf_size16_22_sram_blwl_outb[618:618] ,mux_2level_tapbuf_size16_22_configbus0[618:618], mux_2level_tapbuf_size16_22_configbus1[618:618] , mux_2level_tapbuf_size16_22_configbus0_b[618:618] ); -sram6T_blwl sram_blwl_619_ (mux_2level_tapbuf_size16_22_sram_blwl_out[619:619] ,mux_2level_tapbuf_size16_22_sram_blwl_out[619:619] ,mux_2level_tapbuf_size16_22_sram_blwl_outb[619:619] ,mux_2level_tapbuf_size16_22_configbus0[619:619], mux_2level_tapbuf_size16_22_configbus1[619:619] , mux_2level_tapbuf_size16_22_configbus0_b[619:619] ); -sram6T_blwl sram_blwl_620_ (mux_2level_tapbuf_size16_22_sram_blwl_out[620:620] ,mux_2level_tapbuf_size16_22_sram_blwl_out[620:620] ,mux_2level_tapbuf_size16_22_sram_blwl_outb[620:620] ,mux_2level_tapbuf_size16_22_configbus0[620:620], mux_2level_tapbuf_size16_22_configbus1[620:620] , mux_2level_tapbuf_size16_22_configbus0_b[620:620] ); -sram6T_blwl sram_blwl_621_ (mux_2level_tapbuf_size16_22_sram_blwl_out[621:621] ,mux_2level_tapbuf_size16_22_sram_blwl_out[621:621] ,mux_2level_tapbuf_size16_22_sram_blwl_outb[621:621] ,mux_2level_tapbuf_size16_22_configbus0[621:621], mux_2level_tapbuf_size16_22_configbus1[621:621] , mux_2level_tapbuf_size16_22_configbus0_b[621:621] ); -sram6T_blwl sram_blwl_622_ (mux_2level_tapbuf_size16_22_sram_blwl_out[622:622] ,mux_2level_tapbuf_size16_22_sram_blwl_out[622:622] ,mux_2level_tapbuf_size16_22_sram_blwl_outb[622:622] ,mux_2level_tapbuf_size16_22_configbus0[622:622], mux_2level_tapbuf_size16_22_configbus1[622:622] , mux_2level_tapbuf_size16_22_configbus0_b[622:622] ); -sram6T_blwl sram_blwl_623_ (mux_2level_tapbuf_size16_22_sram_blwl_out[623:623] ,mux_2level_tapbuf_size16_22_sram_blwl_out[623:623] ,mux_2level_tapbuf_size16_22_sram_blwl_outb[623:623] ,mux_2level_tapbuf_size16_22_configbus0[623:623], mux_2level_tapbuf_size16_22_configbus1[623:623] , mux_2level_tapbuf_size16_22_configbus0_b[623:623] ); -wire [0:15] mux_2level_tapbuf_size16_23_inbus; -assign mux_2level_tapbuf_size16_23_inbus[0] = chanx_1__1__midout_14_; -assign mux_2level_tapbuf_size16_23_inbus[1] = chanx_1__1__midout_15_; -assign mux_2level_tapbuf_size16_23_inbus[2] = chanx_1__1__midout_18_; -assign mux_2level_tapbuf_size16_23_inbus[3] = chanx_1__1__midout_19_; -assign mux_2level_tapbuf_size16_23_inbus[4] = chanx_1__1__midout_38_; -assign mux_2level_tapbuf_size16_23_inbus[5] = chanx_1__1__midout_39_; -assign mux_2level_tapbuf_size16_23_inbus[6] = chanx_1__1__midout_44_; -assign mux_2level_tapbuf_size16_23_inbus[7] = chanx_1__1__midout_45_; -assign mux_2level_tapbuf_size16_23_inbus[8] = chanx_1__1__midout_56_; -assign mux_2level_tapbuf_size16_23_inbus[9] = chanx_1__1__midout_57_; -assign mux_2level_tapbuf_size16_23_inbus[10] = chanx_1__1__midout_70_; -assign mux_2level_tapbuf_size16_23_inbus[11] = chanx_1__1__midout_71_; -assign mux_2level_tapbuf_size16_23_inbus[12] = chanx_1__1__midout_82_; -assign mux_2level_tapbuf_size16_23_inbus[13] = chanx_1__1__midout_83_; -assign mux_2level_tapbuf_size16_23_inbus[14] = chanx_1__1__midout_96_; -assign mux_2level_tapbuf_size16_23_inbus[15] = chanx_1__1__midout_97_; -wire [624:631] mux_2level_tapbuf_size16_23_configbus0; -wire [624:631] mux_2level_tapbuf_size16_23_configbus1; -wire [624:631] mux_2level_tapbuf_size16_23_sram_blwl_out ; -wire [624:631] mux_2level_tapbuf_size16_23_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_23_configbus0[624:631] = sram_blwl_bl[624:631] ; -assign mux_2level_tapbuf_size16_23_configbus1[624:631] = sram_blwl_wl[624:631] ; -wire [624:631] mux_2level_tapbuf_size16_23_configbus0_b; -assign mux_2level_tapbuf_size16_23_configbus0_b[624:631] = sram_blwl_blb[624:631] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_23_ (mux_2level_tapbuf_size16_23_inbus, grid_1__2__pin_0__2__10_, mux_2level_tapbuf_size16_23_sram_blwl_out[624:631] , -mux_2level_tapbuf_size16_23_sram_blwl_outb[624:631] ); -//----- SRAM bits for MUX[23], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_624_ (mux_2level_tapbuf_size16_23_sram_blwl_out[624:624] ,mux_2level_tapbuf_size16_23_sram_blwl_out[624:624] ,mux_2level_tapbuf_size16_23_sram_blwl_outb[624:624] ,mux_2level_tapbuf_size16_23_configbus0[624:624], mux_2level_tapbuf_size16_23_configbus1[624:624] , mux_2level_tapbuf_size16_23_configbus0_b[624:624] ); -sram6T_blwl sram_blwl_625_ (mux_2level_tapbuf_size16_23_sram_blwl_out[625:625] ,mux_2level_tapbuf_size16_23_sram_blwl_out[625:625] ,mux_2level_tapbuf_size16_23_sram_blwl_outb[625:625] ,mux_2level_tapbuf_size16_23_configbus0[625:625], mux_2level_tapbuf_size16_23_configbus1[625:625] , mux_2level_tapbuf_size16_23_configbus0_b[625:625] ); -sram6T_blwl sram_blwl_626_ (mux_2level_tapbuf_size16_23_sram_blwl_out[626:626] ,mux_2level_tapbuf_size16_23_sram_blwl_out[626:626] ,mux_2level_tapbuf_size16_23_sram_blwl_outb[626:626] ,mux_2level_tapbuf_size16_23_configbus0[626:626], mux_2level_tapbuf_size16_23_configbus1[626:626] , mux_2level_tapbuf_size16_23_configbus0_b[626:626] ); -sram6T_blwl sram_blwl_627_ (mux_2level_tapbuf_size16_23_sram_blwl_out[627:627] ,mux_2level_tapbuf_size16_23_sram_blwl_out[627:627] ,mux_2level_tapbuf_size16_23_sram_blwl_outb[627:627] ,mux_2level_tapbuf_size16_23_configbus0[627:627], mux_2level_tapbuf_size16_23_configbus1[627:627] , mux_2level_tapbuf_size16_23_configbus0_b[627:627] ); -sram6T_blwl sram_blwl_628_ (mux_2level_tapbuf_size16_23_sram_blwl_out[628:628] ,mux_2level_tapbuf_size16_23_sram_blwl_out[628:628] ,mux_2level_tapbuf_size16_23_sram_blwl_outb[628:628] ,mux_2level_tapbuf_size16_23_configbus0[628:628], mux_2level_tapbuf_size16_23_configbus1[628:628] , mux_2level_tapbuf_size16_23_configbus0_b[628:628] ); -sram6T_blwl sram_blwl_629_ (mux_2level_tapbuf_size16_23_sram_blwl_out[629:629] ,mux_2level_tapbuf_size16_23_sram_blwl_out[629:629] ,mux_2level_tapbuf_size16_23_sram_blwl_outb[629:629] ,mux_2level_tapbuf_size16_23_configbus0[629:629], mux_2level_tapbuf_size16_23_configbus1[629:629] , mux_2level_tapbuf_size16_23_configbus0_b[629:629] ); -sram6T_blwl sram_blwl_630_ (mux_2level_tapbuf_size16_23_sram_blwl_out[630:630] ,mux_2level_tapbuf_size16_23_sram_blwl_out[630:630] ,mux_2level_tapbuf_size16_23_sram_blwl_outb[630:630] ,mux_2level_tapbuf_size16_23_configbus0[630:630], mux_2level_tapbuf_size16_23_configbus1[630:630] , mux_2level_tapbuf_size16_23_configbus0_b[630:630] ); -sram6T_blwl sram_blwl_631_ (mux_2level_tapbuf_size16_23_sram_blwl_out[631:631] ,mux_2level_tapbuf_size16_23_sram_blwl_out[631:631] ,mux_2level_tapbuf_size16_23_sram_blwl_outb[631:631] ,mux_2level_tapbuf_size16_23_configbus0[631:631], mux_2level_tapbuf_size16_23_configbus1[631:631] , mux_2level_tapbuf_size16_23_configbus0_b[631:631] ); -wire [0:15] mux_2level_tapbuf_size16_24_inbus; -assign mux_2level_tapbuf_size16_24_inbus[0] = chanx_1__1__midout_8_; -assign mux_2level_tapbuf_size16_24_inbus[1] = chanx_1__1__midout_9_; -assign mux_2level_tapbuf_size16_24_inbus[2] = chanx_1__1__midout_20_; -assign mux_2level_tapbuf_size16_24_inbus[3] = chanx_1__1__midout_21_; -assign mux_2level_tapbuf_size16_24_inbus[4] = chanx_1__1__midout_32_; -assign mux_2level_tapbuf_size16_24_inbus[5] = chanx_1__1__midout_33_; -assign mux_2level_tapbuf_size16_24_inbus[6] = chanx_1__1__midout_44_; -assign mux_2level_tapbuf_size16_24_inbus[7] = chanx_1__1__midout_45_; -assign mux_2level_tapbuf_size16_24_inbus[8] = chanx_1__1__midout_62_; -assign mux_2level_tapbuf_size16_24_inbus[9] = chanx_1__1__midout_63_; -assign mux_2level_tapbuf_size16_24_inbus[10] = chanx_1__1__midout_72_; -assign mux_2level_tapbuf_size16_24_inbus[11] = chanx_1__1__midout_73_; -assign mux_2level_tapbuf_size16_24_inbus[12] = chanx_1__1__midout_84_; -assign mux_2level_tapbuf_size16_24_inbus[13] = chanx_1__1__midout_85_; -assign mux_2level_tapbuf_size16_24_inbus[14] = chanx_1__1__midout_96_; -assign mux_2level_tapbuf_size16_24_inbus[15] = chanx_1__1__midout_97_; -wire [632:639] mux_2level_tapbuf_size16_24_configbus0; -wire [632:639] mux_2level_tapbuf_size16_24_configbus1; -wire [632:639] mux_2level_tapbuf_size16_24_sram_blwl_out ; -wire [632:639] mux_2level_tapbuf_size16_24_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_24_configbus0[632:639] = sram_blwl_bl[632:639] ; -assign mux_2level_tapbuf_size16_24_configbus1[632:639] = sram_blwl_wl[632:639] ; -wire [632:639] mux_2level_tapbuf_size16_24_configbus0_b; -assign mux_2level_tapbuf_size16_24_configbus0_b[632:639] = sram_blwl_blb[632:639] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_24_ (mux_2level_tapbuf_size16_24_inbus, grid_1__2__pin_0__2__12_, mux_2level_tapbuf_size16_24_sram_blwl_out[632:639] , -mux_2level_tapbuf_size16_24_sram_blwl_outb[632:639] ); -//----- SRAM bits for MUX[24], level=2, select_path_id=2. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10000010----- -sram6T_blwl sram_blwl_632_ (mux_2level_tapbuf_size16_24_sram_blwl_out[632:632] ,mux_2level_tapbuf_size16_24_sram_blwl_out[632:632] ,mux_2level_tapbuf_size16_24_sram_blwl_outb[632:632] ,mux_2level_tapbuf_size16_24_configbus0[632:632], mux_2level_tapbuf_size16_24_configbus1[632:632] , mux_2level_tapbuf_size16_24_configbus0_b[632:632] ); -sram6T_blwl sram_blwl_633_ (mux_2level_tapbuf_size16_24_sram_blwl_out[633:633] ,mux_2level_tapbuf_size16_24_sram_blwl_out[633:633] ,mux_2level_tapbuf_size16_24_sram_blwl_outb[633:633] ,mux_2level_tapbuf_size16_24_configbus0[633:633], mux_2level_tapbuf_size16_24_configbus1[633:633] , mux_2level_tapbuf_size16_24_configbus0_b[633:633] ); -sram6T_blwl sram_blwl_634_ (mux_2level_tapbuf_size16_24_sram_blwl_out[634:634] ,mux_2level_tapbuf_size16_24_sram_blwl_out[634:634] ,mux_2level_tapbuf_size16_24_sram_blwl_outb[634:634] ,mux_2level_tapbuf_size16_24_configbus0[634:634], mux_2level_tapbuf_size16_24_configbus1[634:634] , mux_2level_tapbuf_size16_24_configbus0_b[634:634] ); -sram6T_blwl sram_blwl_635_ (mux_2level_tapbuf_size16_24_sram_blwl_out[635:635] ,mux_2level_tapbuf_size16_24_sram_blwl_out[635:635] ,mux_2level_tapbuf_size16_24_sram_blwl_outb[635:635] ,mux_2level_tapbuf_size16_24_configbus0[635:635], mux_2level_tapbuf_size16_24_configbus1[635:635] , mux_2level_tapbuf_size16_24_configbus0_b[635:635] ); -sram6T_blwl sram_blwl_636_ (mux_2level_tapbuf_size16_24_sram_blwl_out[636:636] ,mux_2level_tapbuf_size16_24_sram_blwl_out[636:636] ,mux_2level_tapbuf_size16_24_sram_blwl_outb[636:636] ,mux_2level_tapbuf_size16_24_configbus0[636:636], mux_2level_tapbuf_size16_24_configbus1[636:636] , mux_2level_tapbuf_size16_24_configbus0_b[636:636] ); -sram6T_blwl sram_blwl_637_ (mux_2level_tapbuf_size16_24_sram_blwl_out[637:637] ,mux_2level_tapbuf_size16_24_sram_blwl_out[637:637] ,mux_2level_tapbuf_size16_24_sram_blwl_outb[637:637] ,mux_2level_tapbuf_size16_24_configbus0[637:637], mux_2level_tapbuf_size16_24_configbus1[637:637] , mux_2level_tapbuf_size16_24_configbus0_b[637:637] ); -sram6T_blwl sram_blwl_638_ (mux_2level_tapbuf_size16_24_sram_blwl_out[638:638] ,mux_2level_tapbuf_size16_24_sram_blwl_out[638:638] ,mux_2level_tapbuf_size16_24_sram_blwl_outb[638:638] ,mux_2level_tapbuf_size16_24_configbus0[638:638], mux_2level_tapbuf_size16_24_configbus1[638:638] , mux_2level_tapbuf_size16_24_configbus0_b[638:638] ); -sram6T_blwl sram_blwl_639_ (mux_2level_tapbuf_size16_24_sram_blwl_out[639:639] ,mux_2level_tapbuf_size16_24_sram_blwl_out[639:639] ,mux_2level_tapbuf_size16_24_sram_blwl_outb[639:639] ,mux_2level_tapbuf_size16_24_configbus0[639:639], mux_2level_tapbuf_size16_24_configbus1[639:639] , mux_2level_tapbuf_size16_24_configbus0_b[639:639] ); -wire [0:15] mux_2level_tapbuf_size16_25_inbus; -assign mux_2level_tapbuf_size16_25_inbus[0] = chanx_1__1__midout_8_; -assign mux_2level_tapbuf_size16_25_inbus[1] = chanx_1__1__midout_9_; -assign mux_2level_tapbuf_size16_25_inbus[2] = chanx_1__1__midout_30_; -assign mux_2level_tapbuf_size16_25_inbus[3] = chanx_1__1__midout_31_; -assign mux_2level_tapbuf_size16_25_inbus[4] = chanx_1__1__midout_34_; -assign mux_2level_tapbuf_size16_25_inbus[5] = chanx_1__1__midout_35_; -assign mux_2level_tapbuf_size16_25_inbus[6] = chanx_1__1__midout_50_; -assign mux_2level_tapbuf_size16_25_inbus[7] = chanx_1__1__midout_51_; -assign mux_2level_tapbuf_size16_25_inbus[8] = chanx_1__1__midout_62_; -assign mux_2level_tapbuf_size16_25_inbus[9] = chanx_1__1__midout_63_; -assign mux_2level_tapbuf_size16_25_inbus[10] = chanx_1__1__midout_74_; -assign mux_2level_tapbuf_size16_25_inbus[11] = chanx_1__1__midout_75_; -assign mux_2level_tapbuf_size16_25_inbus[12] = chanx_1__1__midout_86_; -assign mux_2level_tapbuf_size16_25_inbus[13] = chanx_1__1__midout_87_; -assign mux_2level_tapbuf_size16_25_inbus[14] = chanx_1__1__midout_98_; -assign mux_2level_tapbuf_size16_25_inbus[15] = chanx_1__1__midout_99_; -wire [640:647] mux_2level_tapbuf_size16_25_configbus0; -wire [640:647] mux_2level_tapbuf_size16_25_configbus1; -wire [640:647] mux_2level_tapbuf_size16_25_sram_blwl_out ; -wire [640:647] mux_2level_tapbuf_size16_25_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_25_configbus0[640:647] = sram_blwl_bl[640:647] ; -assign mux_2level_tapbuf_size16_25_configbus1[640:647] = sram_blwl_wl[640:647] ; -wire [640:647] mux_2level_tapbuf_size16_25_configbus0_b; -assign mux_2level_tapbuf_size16_25_configbus0_b[640:647] = sram_blwl_blb[640:647] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_25_ (mux_2level_tapbuf_size16_25_inbus, grid_1__2__pin_0__2__14_, mux_2level_tapbuf_size16_25_sram_blwl_out[640:647] , -mux_2level_tapbuf_size16_25_sram_blwl_outb[640:647] ); -//----- SRAM bits for MUX[25], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_640_ (mux_2level_tapbuf_size16_25_sram_blwl_out[640:640] ,mux_2level_tapbuf_size16_25_sram_blwl_out[640:640] ,mux_2level_tapbuf_size16_25_sram_blwl_outb[640:640] ,mux_2level_tapbuf_size16_25_configbus0[640:640], mux_2level_tapbuf_size16_25_configbus1[640:640] , mux_2level_tapbuf_size16_25_configbus0_b[640:640] ); -sram6T_blwl sram_blwl_641_ (mux_2level_tapbuf_size16_25_sram_blwl_out[641:641] ,mux_2level_tapbuf_size16_25_sram_blwl_out[641:641] ,mux_2level_tapbuf_size16_25_sram_blwl_outb[641:641] ,mux_2level_tapbuf_size16_25_configbus0[641:641], mux_2level_tapbuf_size16_25_configbus1[641:641] , mux_2level_tapbuf_size16_25_configbus0_b[641:641] ); -sram6T_blwl sram_blwl_642_ (mux_2level_tapbuf_size16_25_sram_blwl_out[642:642] ,mux_2level_tapbuf_size16_25_sram_blwl_out[642:642] ,mux_2level_tapbuf_size16_25_sram_blwl_outb[642:642] ,mux_2level_tapbuf_size16_25_configbus0[642:642], mux_2level_tapbuf_size16_25_configbus1[642:642] , mux_2level_tapbuf_size16_25_configbus0_b[642:642] ); -sram6T_blwl sram_blwl_643_ (mux_2level_tapbuf_size16_25_sram_blwl_out[643:643] ,mux_2level_tapbuf_size16_25_sram_blwl_out[643:643] ,mux_2level_tapbuf_size16_25_sram_blwl_outb[643:643] ,mux_2level_tapbuf_size16_25_configbus0[643:643], mux_2level_tapbuf_size16_25_configbus1[643:643] , mux_2level_tapbuf_size16_25_configbus0_b[643:643] ); -sram6T_blwl sram_blwl_644_ (mux_2level_tapbuf_size16_25_sram_blwl_out[644:644] ,mux_2level_tapbuf_size16_25_sram_blwl_out[644:644] ,mux_2level_tapbuf_size16_25_sram_blwl_outb[644:644] ,mux_2level_tapbuf_size16_25_configbus0[644:644], mux_2level_tapbuf_size16_25_configbus1[644:644] , mux_2level_tapbuf_size16_25_configbus0_b[644:644] ); -sram6T_blwl sram_blwl_645_ (mux_2level_tapbuf_size16_25_sram_blwl_out[645:645] ,mux_2level_tapbuf_size16_25_sram_blwl_out[645:645] ,mux_2level_tapbuf_size16_25_sram_blwl_outb[645:645] ,mux_2level_tapbuf_size16_25_configbus0[645:645], mux_2level_tapbuf_size16_25_configbus1[645:645] , mux_2level_tapbuf_size16_25_configbus0_b[645:645] ); -sram6T_blwl sram_blwl_646_ (mux_2level_tapbuf_size16_25_sram_blwl_out[646:646] ,mux_2level_tapbuf_size16_25_sram_blwl_out[646:646] ,mux_2level_tapbuf_size16_25_sram_blwl_outb[646:646] ,mux_2level_tapbuf_size16_25_configbus0[646:646], mux_2level_tapbuf_size16_25_configbus1[646:646] , mux_2level_tapbuf_size16_25_configbus0_b[646:646] ); -sram6T_blwl sram_blwl_647_ (mux_2level_tapbuf_size16_25_sram_blwl_out[647:647] ,mux_2level_tapbuf_size16_25_sram_blwl_out[647:647] ,mux_2level_tapbuf_size16_25_sram_blwl_outb[647:647] ,mux_2level_tapbuf_size16_25_configbus0[647:647], mux_2level_tapbuf_size16_25_configbus1[647:647] , mux_2level_tapbuf_size16_25_configbus0_b[647:647] ); -wire [0:15] mux_2level_tapbuf_size16_26_inbus; -assign mux_2level_tapbuf_size16_26_inbus[0] = chanx_1__1__midout_6_; -assign mux_2level_tapbuf_size16_26_inbus[1] = chanx_1__1__midout_7_; -assign mux_2level_tapbuf_size16_26_inbus[2] = chanx_1__1__midout_10_; -assign mux_2level_tapbuf_size16_26_inbus[3] = chanx_1__1__midout_11_; -assign mux_2level_tapbuf_size16_26_inbus[4] = chanx_1__1__midout_30_; -assign mux_2level_tapbuf_size16_26_inbus[5] = chanx_1__1__midout_31_; -assign mux_2level_tapbuf_size16_26_inbus[6] = chanx_1__1__midout_34_; -assign mux_2level_tapbuf_size16_26_inbus[7] = chanx_1__1__midout_35_; -assign mux_2level_tapbuf_size16_26_inbus[8] = chanx_1__1__midout_48_; -assign mux_2level_tapbuf_size16_26_inbus[9] = chanx_1__1__midout_49_; -assign mux_2level_tapbuf_size16_26_inbus[10] = chanx_1__1__midout_60_; -assign mux_2level_tapbuf_size16_26_inbus[11] = chanx_1__1__midout_61_; -assign mux_2level_tapbuf_size16_26_inbus[12] = chanx_1__1__midout_74_; -assign mux_2level_tapbuf_size16_26_inbus[13] = chanx_1__1__midout_75_; -assign mux_2level_tapbuf_size16_26_inbus[14] = chanx_1__1__midout_86_; -assign mux_2level_tapbuf_size16_26_inbus[15] = chanx_1__1__midout_87_; -wire [648:655] mux_2level_tapbuf_size16_26_configbus0; -wire [648:655] mux_2level_tapbuf_size16_26_configbus1; -wire [648:655] mux_2level_tapbuf_size16_26_sram_blwl_out ; -wire [648:655] mux_2level_tapbuf_size16_26_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_26_configbus0[648:655] = sram_blwl_bl[648:655] ; -assign mux_2level_tapbuf_size16_26_configbus1[648:655] = sram_blwl_wl[648:655] ; -wire [648:655] mux_2level_tapbuf_size16_26_configbus0_b; -assign mux_2level_tapbuf_size16_26_configbus0_b[648:655] = sram_blwl_blb[648:655] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_26_ (mux_2level_tapbuf_size16_26_inbus, grid_1__1__pin_0__0__0_, mux_2level_tapbuf_size16_26_sram_blwl_out[648:655] , -mux_2level_tapbuf_size16_26_sram_blwl_outb[648:655] ); -//----- SRAM bits for MUX[26], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_648_ (mux_2level_tapbuf_size16_26_sram_blwl_out[648:648] ,mux_2level_tapbuf_size16_26_sram_blwl_out[648:648] ,mux_2level_tapbuf_size16_26_sram_blwl_outb[648:648] ,mux_2level_tapbuf_size16_26_configbus0[648:648], mux_2level_tapbuf_size16_26_configbus1[648:648] , mux_2level_tapbuf_size16_26_configbus0_b[648:648] ); -sram6T_blwl sram_blwl_649_ (mux_2level_tapbuf_size16_26_sram_blwl_out[649:649] ,mux_2level_tapbuf_size16_26_sram_blwl_out[649:649] ,mux_2level_tapbuf_size16_26_sram_blwl_outb[649:649] ,mux_2level_tapbuf_size16_26_configbus0[649:649], mux_2level_tapbuf_size16_26_configbus1[649:649] , mux_2level_tapbuf_size16_26_configbus0_b[649:649] ); -sram6T_blwl sram_blwl_650_ (mux_2level_tapbuf_size16_26_sram_blwl_out[650:650] ,mux_2level_tapbuf_size16_26_sram_blwl_out[650:650] ,mux_2level_tapbuf_size16_26_sram_blwl_outb[650:650] ,mux_2level_tapbuf_size16_26_configbus0[650:650], mux_2level_tapbuf_size16_26_configbus1[650:650] , mux_2level_tapbuf_size16_26_configbus0_b[650:650] ); -sram6T_blwl sram_blwl_651_ (mux_2level_tapbuf_size16_26_sram_blwl_out[651:651] ,mux_2level_tapbuf_size16_26_sram_blwl_out[651:651] ,mux_2level_tapbuf_size16_26_sram_blwl_outb[651:651] ,mux_2level_tapbuf_size16_26_configbus0[651:651], mux_2level_tapbuf_size16_26_configbus1[651:651] , mux_2level_tapbuf_size16_26_configbus0_b[651:651] ); -sram6T_blwl sram_blwl_652_ (mux_2level_tapbuf_size16_26_sram_blwl_out[652:652] ,mux_2level_tapbuf_size16_26_sram_blwl_out[652:652] ,mux_2level_tapbuf_size16_26_sram_blwl_outb[652:652] ,mux_2level_tapbuf_size16_26_configbus0[652:652], mux_2level_tapbuf_size16_26_configbus1[652:652] , mux_2level_tapbuf_size16_26_configbus0_b[652:652] ); -sram6T_blwl sram_blwl_653_ (mux_2level_tapbuf_size16_26_sram_blwl_out[653:653] ,mux_2level_tapbuf_size16_26_sram_blwl_out[653:653] ,mux_2level_tapbuf_size16_26_sram_blwl_outb[653:653] ,mux_2level_tapbuf_size16_26_configbus0[653:653], mux_2level_tapbuf_size16_26_configbus1[653:653] , mux_2level_tapbuf_size16_26_configbus0_b[653:653] ); -sram6T_blwl sram_blwl_654_ (mux_2level_tapbuf_size16_26_sram_blwl_out[654:654] ,mux_2level_tapbuf_size16_26_sram_blwl_out[654:654] ,mux_2level_tapbuf_size16_26_sram_blwl_outb[654:654] ,mux_2level_tapbuf_size16_26_configbus0[654:654], mux_2level_tapbuf_size16_26_configbus1[654:654] , mux_2level_tapbuf_size16_26_configbus0_b[654:654] ); -sram6T_blwl sram_blwl_655_ (mux_2level_tapbuf_size16_26_sram_blwl_out[655:655] ,mux_2level_tapbuf_size16_26_sram_blwl_out[655:655] ,mux_2level_tapbuf_size16_26_sram_blwl_outb[655:655] ,mux_2level_tapbuf_size16_26_configbus0[655:655], mux_2level_tapbuf_size16_26_configbus1[655:655] , mux_2level_tapbuf_size16_26_configbus0_b[655:655] ); -wire [0:15] mux_2level_tapbuf_size16_27_inbus; -assign mux_2level_tapbuf_size16_27_inbus[0] = chanx_1__1__midout_6_; -assign mux_2level_tapbuf_size16_27_inbus[1] = chanx_1__1__midout_7_; -assign mux_2level_tapbuf_size16_27_inbus[2] = chanx_1__1__midout_10_; -assign mux_2level_tapbuf_size16_27_inbus[3] = chanx_1__1__midout_11_; -assign mux_2level_tapbuf_size16_27_inbus[4] = chanx_1__1__midout_24_; -assign mux_2level_tapbuf_size16_27_inbus[5] = chanx_1__1__midout_25_; -assign mux_2level_tapbuf_size16_27_inbus[6] = chanx_1__1__midout_36_; -assign mux_2level_tapbuf_size16_27_inbus[7] = chanx_1__1__midout_37_; -assign mux_2level_tapbuf_size16_27_inbus[8] = chanx_1__1__midout_48_; -assign mux_2level_tapbuf_size16_27_inbus[9] = chanx_1__1__midout_49_; -assign mux_2level_tapbuf_size16_27_inbus[10] = chanx_1__1__midout_60_; -assign mux_2level_tapbuf_size16_27_inbus[11] = chanx_1__1__midout_61_; -assign mux_2level_tapbuf_size16_27_inbus[12] = chanx_1__1__midout_76_; -assign mux_2level_tapbuf_size16_27_inbus[13] = chanx_1__1__midout_77_; -assign mux_2level_tapbuf_size16_27_inbus[14] = chanx_1__1__midout_88_; -assign mux_2level_tapbuf_size16_27_inbus[15] = chanx_1__1__midout_89_; -wire [656:663] mux_2level_tapbuf_size16_27_configbus0; -wire [656:663] mux_2level_tapbuf_size16_27_configbus1; -wire [656:663] mux_2level_tapbuf_size16_27_sram_blwl_out ; -wire [656:663] mux_2level_tapbuf_size16_27_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_27_configbus0[656:663] = sram_blwl_bl[656:663] ; -assign mux_2level_tapbuf_size16_27_configbus1[656:663] = sram_blwl_wl[656:663] ; -wire [656:663] mux_2level_tapbuf_size16_27_configbus0_b; -assign mux_2level_tapbuf_size16_27_configbus0_b[656:663] = sram_blwl_blb[656:663] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_27_ (mux_2level_tapbuf_size16_27_inbus, grid_1__1__pin_0__0__4_, mux_2level_tapbuf_size16_27_sram_blwl_out[656:663] , -mux_2level_tapbuf_size16_27_sram_blwl_outb[656:663] ); -//----- SRAM bits for MUX[27], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_656_ (mux_2level_tapbuf_size16_27_sram_blwl_out[656:656] ,mux_2level_tapbuf_size16_27_sram_blwl_out[656:656] ,mux_2level_tapbuf_size16_27_sram_blwl_outb[656:656] ,mux_2level_tapbuf_size16_27_configbus0[656:656], mux_2level_tapbuf_size16_27_configbus1[656:656] , mux_2level_tapbuf_size16_27_configbus0_b[656:656] ); -sram6T_blwl sram_blwl_657_ (mux_2level_tapbuf_size16_27_sram_blwl_out[657:657] ,mux_2level_tapbuf_size16_27_sram_blwl_out[657:657] ,mux_2level_tapbuf_size16_27_sram_blwl_outb[657:657] ,mux_2level_tapbuf_size16_27_configbus0[657:657], mux_2level_tapbuf_size16_27_configbus1[657:657] , mux_2level_tapbuf_size16_27_configbus0_b[657:657] ); -sram6T_blwl sram_blwl_658_ (mux_2level_tapbuf_size16_27_sram_blwl_out[658:658] ,mux_2level_tapbuf_size16_27_sram_blwl_out[658:658] ,mux_2level_tapbuf_size16_27_sram_blwl_outb[658:658] ,mux_2level_tapbuf_size16_27_configbus0[658:658], mux_2level_tapbuf_size16_27_configbus1[658:658] , mux_2level_tapbuf_size16_27_configbus0_b[658:658] ); -sram6T_blwl sram_blwl_659_ (mux_2level_tapbuf_size16_27_sram_blwl_out[659:659] ,mux_2level_tapbuf_size16_27_sram_blwl_out[659:659] ,mux_2level_tapbuf_size16_27_sram_blwl_outb[659:659] ,mux_2level_tapbuf_size16_27_configbus0[659:659], mux_2level_tapbuf_size16_27_configbus1[659:659] , mux_2level_tapbuf_size16_27_configbus0_b[659:659] ); -sram6T_blwl sram_blwl_660_ (mux_2level_tapbuf_size16_27_sram_blwl_out[660:660] ,mux_2level_tapbuf_size16_27_sram_blwl_out[660:660] ,mux_2level_tapbuf_size16_27_sram_blwl_outb[660:660] ,mux_2level_tapbuf_size16_27_configbus0[660:660], mux_2level_tapbuf_size16_27_configbus1[660:660] , mux_2level_tapbuf_size16_27_configbus0_b[660:660] ); -sram6T_blwl sram_blwl_661_ (mux_2level_tapbuf_size16_27_sram_blwl_out[661:661] ,mux_2level_tapbuf_size16_27_sram_blwl_out[661:661] ,mux_2level_tapbuf_size16_27_sram_blwl_outb[661:661] ,mux_2level_tapbuf_size16_27_configbus0[661:661], mux_2level_tapbuf_size16_27_configbus1[661:661] , mux_2level_tapbuf_size16_27_configbus0_b[661:661] ); -sram6T_blwl sram_blwl_662_ (mux_2level_tapbuf_size16_27_sram_blwl_out[662:662] ,mux_2level_tapbuf_size16_27_sram_blwl_out[662:662] ,mux_2level_tapbuf_size16_27_sram_blwl_outb[662:662] ,mux_2level_tapbuf_size16_27_configbus0[662:662], mux_2level_tapbuf_size16_27_configbus1[662:662] , mux_2level_tapbuf_size16_27_configbus0_b[662:662] ); -sram6T_blwl sram_blwl_663_ (mux_2level_tapbuf_size16_27_sram_blwl_out[663:663] ,mux_2level_tapbuf_size16_27_sram_blwl_out[663:663] ,mux_2level_tapbuf_size16_27_sram_blwl_outb[663:663] ,mux_2level_tapbuf_size16_27_configbus0[663:663], mux_2level_tapbuf_size16_27_configbus1[663:663] , mux_2level_tapbuf_size16_27_configbus0_b[663:663] ); -wire [0:15] mux_2level_tapbuf_size16_28_inbus; -assign mux_2level_tapbuf_size16_28_inbus[0] = chanx_1__1__midout_0_; -assign mux_2level_tapbuf_size16_28_inbus[1] = chanx_1__1__midout_1_; -assign mux_2level_tapbuf_size16_28_inbus[2] = chanx_1__1__midout_12_; -assign mux_2level_tapbuf_size16_28_inbus[3] = chanx_1__1__midout_13_; -assign mux_2level_tapbuf_size16_28_inbus[4] = chanx_1__1__midout_24_; -assign mux_2level_tapbuf_size16_28_inbus[5] = chanx_1__1__midout_25_; -assign mux_2level_tapbuf_size16_28_inbus[6] = chanx_1__1__midout_42_; -assign mux_2level_tapbuf_size16_28_inbus[7] = chanx_1__1__midout_43_; -assign mux_2level_tapbuf_size16_28_inbus[8] = chanx_1__1__midout_54_; -assign mux_2level_tapbuf_size16_28_inbus[9] = chanx_1__1__midout_55_; -assign mux_2level_tapbuf_size16_28_inbus[10] = chanx_1__1__midout_66_; -assign mux_2level_tapbuf_size16_28_inbus[11] = chanx_1__1__midout_67_; -assign mux_2level_tapbuf_size16_28_inbus[12] = chanx_1__1__midout_76_; -assign mux_2level_tapbuf_size16_28_inbus[13] = chanx_1__1__midout_77_; -assign mux_2level_tapbuf_size16_28_inbus[14] = chanx_1__1__midout_90_; -assign mux_2level_tapbuf_size16_28_inbus[15] = chanx_1__1__midout_91_; -wire [664:671] mux_2level_tapbuf_size16_28_configbus0; -wire [664:671] mux_2level_tapbuf_size16_28_configbus1; -wire [664:671] mux_2level_tapbuf_size16_28_sram_blwl_out ; -wire [664:671] mux_2level_tapbuf_size16_28_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_28_configbus0[664:671] = sram_blwl_bl[664:671] ; -assign mux_2level_tapbuf_size16_28_configbus1[664:671] = sram_blwl_wl[664:671] ; -wire [664:671] mux_2level_tapbuf_size16_28_configbus0_b; -assign mux_2level_tapbuf_size16_28_configbus0_b[664:671] = sram_blwl_blb[664:671] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_28_ (mux_2level_tapbuf_size16_28_inbus, grid_1__1__pin_0__0__8_, mux_2level_tapbuf_size16_28_sram_blwl_out[664:671] , -mux_2level_tapbuf_size16_28_sram_blwl_outb[664:671] ); -//----- SRAM bits for MUX[28], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_664_ (mux_2level_tapbuf_size16_28_sram_blwl_out[664:664] ,mux_2level_tapbuf_size16_28_sram_blwl_out[664:664] ,mux_2level_tapbuf_size16_28_sram_blwl_outb[664:664] ,mux_2level_tapbuf_size16_28_configbus0[664:664], mux_2level_tapbuf_size16_28_configbus1[664:664] , mux_2level_tapbuf_size16_28_configbus0_b[664:664] ); -sram6T_blwl sram_blwl_665_ (mux_2level_tapbuf_size16_28_sram_blwl_out[665:665] ,mux_2level_tapbuf_size16_28_sram_blwl_out[665:665] ,mux_2level_tapbuf_size16_28_sram_blwl_outb[665:665] ,mux_2level_tapbuf_size16_28_configbus0[665:665], mux_2level_tapbuf_size16_28_configbus1[665:665] , mux_2level_tapbuf_size16_28_configbus0_b[665:665] ); -sram6T_blwl sram_blwl_666_ (mux_2level_tapbuf_size16_28_sram_blwl_out[666:666] ,mux_2level_tapbuf_size16_28_sram_blwl_out[666:666] ,mux_2level_tapbuf_size16_28_sram_blwl_outb[666:666] ,mux_2level_tapbuf_size16_28_configbus0[666:666], mux_2level_tapbuf_size16_28_configbus1[666:666] , mux_2level_tapbuf_size16_28_configbus0_b[666:666] ); -sram6T_blwl sram_blwl_667_ (mux_2level_tapbuf_size16_28_sram_blwl_out[667:667] ,mux_2level_tapbuf_size16_28_sram_blwl_out[667:667] ,mux_2level_tapbuf_size16_28_sram_blwl_outb[667:667] ,mux_2level_tapbuf_size16_28_configbus0[667:667], mux_2level_tapbuf_size16_28_configbus1[667:667] , mux_2level_tapbuf_size16_28_configbus0_b[667:667] ); -sram6T_blwl sram_blwl_668_ (mux_2level_tapbuf_size16_28_sram_blwl_out[668:668] ,mux_2level_tapbuf_size16_28_sram_blwl_out[668:668] ,mux_2level_tapbuf_size16_28_sram_blwl_outb[668:668] ,mux_2level_tapbuf_size16_28_configbus0[668:668], mux_2level_tapbuf_size16_28_configbus1[668:668] , mux_2level_tapbuf_size16_28_configbus0_b[668:668] ); -sram6T_blwl sram_blwl_669_ (mux_2level_tapbuf_size16_28_sram_blwl_out[669:669] ,mux_2level_tapbuf_size16_28_sram_blwl_out[669:669] ,mux_2level_tapbuf_size16_28_sram_blwl_outb[669:669] ,mux_2level_tapbuf_size16_28_configbus0[669:669], mux_2level_tapbuf_size16_28_configbus1[669:669] , mux_2level_tapbuf_size16_28_configbus0_b[669:669] ); -sram6T_blwl sram_blwl_670_ (mux_2level_tapbuf_size16_28_sram_blwl_out[670:670] ,mux_2level_tapbuf_size16_28_sram_blwl_out[670:670] ,mux_2level_tapbuf_size16_28_sram_blwl_outb[670:670] ,mux_2level_tapbuf_size16_28_configbus0[670:670], mux_2level_tapbuf_size16_28_configbus1[670:670] , mux_2level_tapbuf_size16_28_configbus0_b[670:670] ); -sram6T_blwl sram_blwl_671_ (mux_2level_tapbuf_size16_28_sram_blwl_out[671:671] ,mux_2level_tapbuf_size16_28_sram_blwl_out[671:671] ,mux_2level_tapbuf_size16_28_sram_blwl_outb[671:671] ,mux_2level_tapbuf_size16_28_configbus0[671:671], mux_2level_tapbuf_size16_28_configbus1[671:671] , mux_2level_tapbuf_size16_28_configbus0_b[671:671] ); -wire [0:15] mux_2level_tapbuf_size16_29_inbus; -assign mux_2level_tapbuf_size16_29_inbus[0] = chanx_1__1__midout_0_; -assign mux_2level_tapbuf_size16_29_inbus[1] = chanx_1__1__midout_1_; -assign mux_2level_tapbuf_size16_29_inbus[2] = chanx_1__1__midout_22_; -assign mux_2level_tapbuf_size16_29_inbus[3] = chanx_1__1__midout_23_; -assign mux_2level_tapbuf_size16_29_inbus[4] = chanx_1__1__midout_26_; -assign mux_2level_tapbuf_size16_29_inbus[5] = chanx_1__1__midout_27_; -assign mux_2level_tapbuf_size16_29_inbus[6] = chanx_1__1__midout_42_; -assign mux_2level_tapbuf_size16_29_inbus[7] = chanx_1__1__midout_43_; -assign mux_2level_tapbuf_size16_29_inbus[8] = chanx_1__1__midout_54_; -assign mux_2level_tapbuf_size16_29_inbus[9] = chanx_1__1__midout_55_; -assign mux_2level_tapbuf_size16_29_inbus[10] = chanx_1__1__midout_64_; -assign mux_2level_tapbuf_size16_29_inbus[11] = chanx_1__1__midout_65_; -assign mux_2level_tapbuf_size16_29_inbus[12] = chanx_1__1__midout_78_; -assign mux_2level_tapbuf_size16_29_inbus[13] = chanx_1__1__midout_79_; -assign mux_2level_tapbuf_size16_29_inbus[14] = chanx_1__1__midout_90_; -assign mux_2level_tapbuf_size16_29_inbus[15] = chanx_1__1__midout_91_; -wire [672:679] mux_2level_tapbuf_size16_29_configbus0; -wire [672:679] mux_2level_tapbuf_size16_29_configbus1; -wire [672:679] mux_2level_tapbuf_size16_29_sram_blwl_out ; -wire [672:679] mux_2level_tapbuf_size16_29_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_29_configbus0[672:679] = sram_blwl_bl[672:679] ; -assign mux_2level_tapbuf_size16_29_configbus1[672:679] = sram_blwl_wl[672:679] ; -wire [672:679] mux_2level_tapbuf_size16_29_configbus0_b; -assign mux_2level_tapbuf_size16_29_configbus0_b[672:679] = sram_blwl_blb[672:679] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_29_ (mux_2level_tapbuf_size16_29_inbus, grid_1__1__pin_0__0__12_, mux_2level_tapbuf_size16_29_sram_blwl_out[672:679] , -mux_2level_tapbuf_size16_29_sram_blwl_outb[672:679] ); -//----- SRAM bits for MUX[29], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_672_ (mux_2level_tapbuf_size16_29_sram_blwl_out[672:672] ,mux_2level_tapbuf_size16_29_sram_blwl_out[672:672] ,mux_2level_tapbuf_size16_29_sram_blwl_outb[672:672] ,mux_2level_tapbuf_size16_29_configbus0[672:672], mux_2level_tapbuf_size16_29_configbus1[672:672] , mux_2level_tapbuf_size16_29_configbus0_b[672:672] ); -sram6T_blwl sram_blwl_673_ (mux_2level_tapbuf_size16_29_sram_blwl_out[673:673] ,mux_2level_tapbuf_size16_29_sram_blwl_out[673:673] ,mux_2level_tapbuf_size16_29_sram_blwl_outb[673:673] ,mux_2level_tapbuf_size16_29_configbus0[673:673], mux_2level_tapbuf_size16_29_configbus1[673:673] , mux_2level_tapbuf_size16_29_configbus0_b[673:673] ); -sram6T_blwl sram_blwl_674_ (mux_2level_tapbuf_size16_29_sram_blwl_out[674:674] ,mux_2level_tapbuf_size16_29_sram_blwl_out[674:674] ,mux_2level_tapbuf_size16_29_sram_blwl_outb[674:674] ,mux_2level_tapbuf_size16_29_configbus0[674:674], mux_2level_tapbuf_size16_29_configbus1[674:674] , mux_2level_tapbuf_size16_29_configbus0_b[674:674] ); -sram6T_blwl sram_blwl_675_ (mux_2level_tapbuf_size16_29_sram_blwl_out[675:675] ,mux_2level_tapbuf_size16_29_sram_blwl_out[675:675] ,mux_2level_tapbuf_size16_29_sram_blwl_outb[675:675] ,mux_2level_tapbuf_size16_29_configbus0[675:675], mux_2level_tapbuf_size16_29_configbus1[675:675] , mux_2level_tapbuf_size16_29_configbus0_b[675:675] ); -sram6T_blwl sram_blwl_676_ (mux_2level_tapbuf_size16_29_sram_blwl_out[676:676] ,mux_2level_tapbuf_size16_29_sram_blwl_out[676:676] ,mux_2level_tapbuf_size16_29_sram_blwl_outb[676:676] ,mux_2level_tapbuf_size16_29_configbus0[676:676], mux_2level_tapbuf_size16_29_configbus1[676:676] , mux_2level_tapbuf_size16_29_configbus0_b[676:676] ); -sram6T_blwl sram_blwl_677_ (mux_2level_tapbuf_size16_29_sram_blwl_out[677:677] ,mux_2level_tapbuf_size16_29_sram_blwl_out[677:677] ,mux_2level_tapbuf_size16_29_sram_blwl_outb[677:677] ,mux_2level_tapbuf_size16_29_configbus0[677:677], mux_2level_tapbuf_size16_29_configbus1[677:677] , mux_2level_tapbuf_size16_29_configbus0_b[677:677] ); -sram6T_blwl sram_blwl_678_ (mux_2level_tapbuf_size16_29_sram_blwl_out[678:678] ,mux_2level_tapbuf_size16_29_sram_blwl_out[678:678] ,mux_2level_tapbuf_size16_29_sram_blwl_outb[678:678] ,mux_2level_tapbuf_size16_29_configbus0[678:678], mux_2level_tapbuf_size16_29_configbus1[678:678] , mux_2level_tapbuf_size16_29_configbus0_b[678:678] ); -sram6T_blwl sram_blwl_679_ (mux_2level_tapbuf_size16_29_sram_blwl_out[679:679] ,mux_2level_tapbuf_size16_29_sram_blwl_out[679:679] ,mux_2level_tapbuf_size16_29_sram_blwl_outb[679:679] ,mux_2level_tapbuf_size16_29_configbus0[679:679], mux_2level_tapbuf_size16_29_configbus1[679:679] , mux_2level_tapbuf_size16_29_configbus0_b[679:679] ); -wire [0:15] mux_2level_tapbuf_size16_30_inbus; -assign mux_2level_tapbuf_size16_30_inbus[0] = chanx_1__1__midout_2_; -assign mux_2level_tapbuf_size16_30_inbus[1] = chanx_1__1__midout_3_; -assign mux_2level_tapbuf_size16_30_inbus[2] = chanx_1__1__midout_22_; -assign mux_2level_tapbuf_size16_30_inbus[3] = chanx_1__1__midout_23_; -assign mux_2level_tapbuf_size16_30_inbus[4] = chanx_1__1__midout_28_; -assign mux_2level_tapbuf_size16_30_inbus[5] = chanx_1__1__midout_29_; -assign mux_2level_tapbuf_size16_30_inbus[6] = chanx_1__1__midout_40_; -assign mux_2level_tapbuf_size16_30_inbus[7] = chanx_1__1__midout_41_; -assign mux_2level_tapbuf_size16_30_inbus[8] = chanx_1__1__midout_52_; -assign mux_2level_tapbuf_size16_30_inbus[9] = chanx_1__1__midout_53_; -assign mux_2level_tapbuf_size16_30_inbus[10] = chanx_1__1__midout_64_; -assign mux_2level_tapbuf_size16_30_inbus[11] = chanx_1__1__midout_65_; -assign mux_2level_tapbuf_size16_30_inbus[12] = chanx_1__1__midout_80_; -assign mux_2level_tapbuf_size16_30_inbus[13] = chanx_1__1__midout_81_; -assign mux_2level_tapbuf_size16_30_inbus[14] = chanx_1__1__midout_92_; -assign mux_2level_tapbuf_size16_30_inbus[15] = chanx_1__1__midout_93_; -wire [680:687] mux_2level_tapbuf_size16_30_configbus0; -wire [680:687] mux_2level_tapbuf_size16_30_configbus1; -wire [680:687] mux_2level_tapbuf_size16_30_sram_blwl_out ; -wire [680:687] mux_2level_tapbuf_size16_30_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_30_configbus0[680:687] = sram_blwl_bl[680:687] ; -assign mux_2level_tapbuf_size16_30_configbus1[680:687] = sram_blwl_wl[680:687] ; -wire [680:687] mux_2level_tapbuf_size16_30_configbus0_b; -assign mux_2level_tapbuf_size16_30_configbus0_b[680:687] = sram_blwl_blb[680:687] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_30_ (mux_2level_tapbuf_size16_30_inbus, grid_1__1__pin_0__0__16_, mux_2level_tapbuf_size16_30_sram_blwl_out[680:687] , -mux_2level_tapbuf_size16_30_sram_blwl_outb[680:687] ); -//----- SRAM bits for MUX[30], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_680_ (mux_2level_tapbuf_size16_30_sram_blwl_out[680:680] ,mux_2level_tapbuf_size16_30_sram_blwl_out[680:680] ,mux_2level_tapbuf_size16_30_sram_blwl_outb[680:680] ,mux_2level_tapbuf_size16_30_configbus0[680:680], mux_2level_tapbuf_size16_30_configbus1[680:680] , mux_2level_tapbuf_size16_30_configbus0_b[680:680] ); -sram6T_blwl sram_blwl_681_ (mux_2level_tapbuf_size16_30_sram_blwl_out[681:681] ,mux_2level_tapbuf_size16_30_sram_blwl_out[681:681] ,mux_2level_tapbuf_size16_30_sram_blwl_outb[681:681] ,mux_2level_tapbuf_size16_30_configbus0[681:681], mux_2level_tapbuf_size16_30_configbus1[681:681] , mux_2level_tapbuf_size16_30_configbus0_b[681:681] ); -sram6T_blwl sram_blwl_682_ (mux_2level_tapbuf_size16_30_sram_blwl_out[682:682] ,mux_2level_tapbuf_size16_30_sram_blwl_out[682:682] ,mux_2level_tapbuf_size16_30_sram_blwl_outb[682:682] ,mux_2level_tapbuf_size16_30_configbus0[682:682], mux_2level_tapbuf_size16_30_configbus1[682:682] , mux_2level_tapbuf_size16_30_configbus0_b[682:682] ); -sram6T_blwl sram_blwl_683_ (mux_2level_tapbuf_size16_30_sram_blwl_out[683:683] ,mux_2level_tapbuf_size16_30_sram_blwl_out[683:683] ,mux_2level_tapbuf_size16_30_sram_blwl_outb[683:683] ,mux_2level_tapbuf_size16_30_configbus0[683:683], mux_2level_tapbuf_size16_30_configbus1[683:683] , mux_2level_tapbuf_size16_30_configbus0_b[683:683] ); -sram6T_blwl sram_blwl_684_ (mux_2level_tapbuf_size16_30_sram_blwl_out[684:684] ,mux_2level_tapbuf_size16_30_sram_blwl_out[684:684] ,mux_2level_tapbuf_size16_30_sram_blwl_outb[684:684] ,mux_2level_tapbuf_size16_30_configbus0[684:684], mux_2level_tapbuf_size16_30_configbus1[684:684] , mux_2level_tapbuf_size16_30_configbus0_b[684:684] ); -sram6T_blwl sram_blwl_685_ (mux_2level_tapbuf_size16_30_sram_blwl_out[685:685] ,mux_2level_tapbuf_size16_30_sram_blwl_out[685:685] ,mux_2level_tapbuf_size16_30_sram_blwl_outb[685:685] ,mux_2level_tapbuf_size16_30_configbus0[685:685], mux_2level_tapbuf_size16_30_configbus1[685:685] , mux_2level_tapbuf_size16_30_configbus0_b[685:685] ); -sram6T_blwl sram_blwl_686_ (mux_2level_tapbuf_size16_30_sram_blwl_out[686:686] ,mux_2level_tapbuf_size16_30_sram_blwl_out[686:686] ,mux_2level_tapbuf_size16_30_sram_blwl_outb[686:686] ,mux_2level_tapbuf_size16_30_configbus0[686:686], mux_2level_tapbuf_size16_30_configbus1[686:686] , mux_2level_tapbuf_size16_30_configbus0_b[686:686] ); -sram6T_blwl sram_blwl_687_ (mux_2level_tapbuf_size16_30_sram_blwl_out[687:687] ,mux_2level_tapbuf_size16_30_sram_blwl_out[687:687] ,mux_2level_tapbuf_size16_30_sram_blwl_outb[687:687] ,mux_2level_tapbuf_size16_30_configbus0[687:687], mux_2level_tapbuf_size16_30_configbus1[687:687] , mux_2level_tapbuf_size16_30_configbus0_b[687:687] ); -wire [0:15] mux_2level_tapbuf_size16_31_inbus; -assign mux_2level_tapbuf_size16_31_inbus[0] = chanx_1__1__midout_4_; -assign mux_2level_tapbuf_size16_31_inbus[1] = chanx_1__1__midout_5_; -assign mux_2level_tapbuf_size16_31_inbus[2] = chanx_1__1__midout_16_; -assign mux_2level_tapbuf_size16_31_inbus[3] = chanx_1__1__midout_17_; -assign mux_2level_tapbuf_size16_31_inbus[4] = chanx_1__1__midout_28_; -assign mux_2level_tapbuf_size16_31_inbus[5] = chanx_1__1__midout_29_; -assign mux_2level_tapbuf_size16_31_inbus[6] = chanx_1__1__midout_40_; -assign mux_2level_tapbuf_size16_31_inbus[7] = chanx_1__1__midout_41_; -assign mux_2level_tapbuf_size16_31_inbus[8] = chanx_1__1__midout_58_; -assign mux_2level_tapbuf_size16_31_inbus[9] = chanx_1__1__midout_59_; -assign mux_2level_tapbuf_size16_31_inbus[10] = chanx_1__1__midout_68_; -assign mux_2level_tapbuf_size16_31_inbus[11] = chanx_1__1__midout_69_; -assign mux_2level_tapbuf_size16_31_inbus[12] = chanx_1__1__midout_80_; -assign mux_2level_tapbuf_size16_31_inbus[13] = chanx_1__1__midout_81_; -assign mux_2level_tapbuf_size16_31_inbus[14] = chanx_1__1__midout_92_; -assign mux_2level_tapbuf_size16_31_inbus[15] = chanx_1__1__midout_93_; -wire [688:695] mux_2level_tapbuf_size16_31_configbus0; -wire [688:695] mux_2level_tapbuf_size16_31_configbus1; -wire [688:695] mux_2level_tapbuf_size16_31_sram_blwl_out ; -wire [688:695] mux_2level_tapbuf_size16_31_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_31_configbus0[688:695] = sram_blwl_bl[688:695] ; -assign mux_2level_tapbuf_size16_31_configbus1[688:695] = sram_blwl_wl[688:695] ; -wire [688:695] mux_2level_tapbuf_size16_31_configbus0_b; -assign mux_2level_tapbuf_size16_31_configbus0_b[688:695] = sram_blwl_blb[688:695] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_31_ (mux_2level_tapbuf_size16_31_inbus, grid_1__1__pin_0__0__20_, mux_2level_tapbuf_size16_31_sram_blwl_out[688:695] , -mux_2level_tapbuf_size16_31_sram_blwl_outb[688:695] ); -//----- SRAM bits for MUX[31], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_688_ (mux_2level_tapbuf_size16_31_sram_blwl_out[688:688] ,mux_2level_tapbuf_size16_31_sram_blwl_out[688:688] ,mux_2level_tapbuf_size16_31_sram_blwl_outb[688:688] ,mux_2level_tapbuf_size16_31_configbus0[688:688], mux_2level_tapbuf_size16_31_configbus1[688:688] , mux_2level_tapbuf_size16_31_configbus0_b[688:688] ); -sram6T_blwl sram_blwl_689_ (mux_2level_tapbuf_size16_31_sram_blwl_out[689:689] ,mux_2level_tapbuf_size16_31_sram_blwl_out[689:689] ,mux_2level_tapbuf_size16_31_sram_blwl_outb[689:689] ,mux_2level_tapbuf_size16_31_configbus0[689:689], mux_2level_tapbuf_size16_31_configbus1[689:689] , mux_2level_tapbuf_size16_31_configbus0_b[689:689] ); -sram6T_blwl sram_blwl_690_ (mux_2level_tapbuf_size16_31_sram_blwl_out[690:690] ,mux_2level_tapbuf_size16_31_sram_blwl_out[690:690] ,mux_2level_tapbuf_size16_31_sram_blwl_outb[690:690] ,mux_2level_tapbuf_size16_31_configbus0[690:690], mux_2level_tapbuf_size16_31_configbus1[690:690] , mux_2level_tapbuf_size16_31_configbus0_b[690:690] ); -sram6T_blwl sram_blwl_691_ (mux_2level_tapbuf_size16_31_sram_blwl_out[691:691] ,mux_2level_tapbuf_size16_31_sram_blwl_out[691:691] ,mux_2level_tapbuf_size16_31_sram_blwl_outb[691:691] ,mux_2level_tapbuf_size16_31_configbus0[691:691], mux_2level_tapbuf_size16_31_configbus1[691:691] , mux_2level_tapbuf_size16_31_configbus0_b[691:691] ); -sram6T_blwl sram_blwl_692_ (mux_2level_tapbuf_size16_31_sram_blwl_out[692:692] ,mux_2level_tapbuf_size16_31_sram_blwl_out[692:692] ,mux_2level_tapbuf_size16_31_sram_blwl_outb[692:692] ,mux_2level_tapbuf_size16_31_configbus0[692:692], mux_2level_tapbuf_size16_31_configbus1[692:692] , mux_2level_tapbuf_size16_31_configbus0_b[692:692] ); -sram6T_blwl sram_blwl_693_ (mux_2level_tapbuf_size16_31_sram_blwl_out[693:693] ,mux_2level_tapbuf_size16_31_sram_blwl_out[693:693] ,mux_2level_tapbuf_size16_31_sram_blwl_outb[693:693] ,mux_2level_tapbuf_size16_31_configbus0[693:693], mux_2level_tapbuf_size16_31_configbus1[693:693] , mux_2level_tapbuf_size16_31_configbus0_b[693:693] ); -sram6T_blwl sram_blwl_694_ (mux_2level_tapbuf_size16_31_sram_blwl_out[694:694] ,mux_2level_tapbuf_size16_31_sram_blwl_out[694:694] ,mux_2level_tapbuf_size16_31_sram_blwl_outb[694:694] ,mux_2level_tapbuf_size16_31_configbus0[694:694], mux_2level_tapbuf_size16_31_configbus1[694:694] , mux_2level_tapbuf_size16_31_configbus0_b[694:694] ); -sram6T_blwl sram_blwl_695_ (mux_2level_tapbuf_size16_31_sram_blwl_out[695:695] ,mux_2level_tapbuf_size16_31_sram_blwl_out[695:695] ,mux_2level_tapbuf_size16_31_sram_blwl_outb[695:695] ,mux_2level_tapbuf_size16_31_configbus0[695:695], mux_2level_tapbuf_size16_31_configbus1[695:695] , mux_2level_tapbuf_size16_31_configbus0_b[695:695] ); -wire [0:15] mux_2level_tapbuf_size16_32_inbus; -assign mux_2level_tapbuf_size16_32_inbus[0] = chanx_1__1__midout_4_; -assign mux_2level_tapbuf_size16_32_inbus[1] = chanx_1__1__midout_5_; -assign mux_2level_tapbuf_size16_32_inbus[2] = chanx_1__1__midout_18_; -assign mux_2level_tapbuf_size16_32_inbus[3] = chanx_1__1__midout_19_; -assign mux_2level_tapbuf_size16_32_inbus[4] = chanx_1__1__midout_38_; -assign mux_2level_tapbuf_size16_32_inbus[5] = chanx_1__1__midout_39_; -assign mux_2level_tapbuf_size16_32_inbus[6] = chanx_1__1__midout_46_; -assign mux_2level_tapbuf_size16_32_inbus[7] = chanx_1__1__midout_47_; -assign mux_2level_tapbuf_size16_32_inbus[8] = chanx_1__1__midout_58_; -assign mux_2level_tapbuf_size16_32_inbus[9] = chanx_1__1__midout_59_; -assign mux_2level_tapbuf_size16_32_inbus[10] = chanx_1__1__midout_70_; -assign mux_2level_tapbuf_size16_32_inbus[11] = chanx_1__1__midout_71_; -assign mux_2level_tapbuf_size16_32_inbus[12] = chanx_1__1__midout_82_; -assign mux_2level_tapbuf_size16_32_inbus[13] = chanx_1__1__midout_83_; -assign mux_2level_tapbuf_size16_32_inbus[14] = chanx_1__1__midout_94_; -assign mux_2level_tapbuf_size16_32_inbus[15] = chanx_1__1__midout_95_; -wire [696:703] mux_2level_tapbuf_size16_32_configbus0; -wire [696:703] mux_2level_tapbuf_size16_32_configbus1; -wire [696:703] mux_2level_tapbuf_size16_32_sram_blwl_out ; -wire [696:703] mux_2level_tapbuf_size16_32_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_32_configbus0[696:703] = sram_blwl_bl[696:703] ; -assign mux_2level_tapbuf_size16_32_configbus1[696:703] = sram_blwl_wl[696:703] ; -wire [696:703] mux_2level_tapbuf_size16_32_configbus0_b; -assign mux_2level_tapbuf_size16_32_configbus0_b[696:703] = sram_blwl_blb[696:703] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_32_ (mux_2level_tapbuf_size16_32_inbus, grid_1__1__pin_0__0__24_, mux_2level_tapbuf_size16_32_sram_blwl_out[696:703] , -mux_2level_tapbuf_size16_32_sram_blwl_outb[696:703] ); -//----- SRAM bits for MUX[32], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_696_ (mux_2level_tapbuf_size16_32_sram_blwl_out[696:696] ,mux_2level_tapbuf_size16_32_sram_blwl_out[696:696] ,mux_2level_tapbuf_size16_32_sram_blwl_outb[696:696] ,mux_2level_tapbuf_size16_32_configbus0[696:696], mux_2level_tapbuf_size16_32_configbus1[696:696] , mux_2level_tapbuf_size16_32_configbus0_b[696:696] ); -sram6T_blwl sram_blwl_697_ (mux_2level_tapbuf_size16_32_sram_blwl_out[697:697] ,mux_2level_tapbuf_size16_32_sram_blwl_out[697:697] ,mux_2level_tapbuf_size16_32_sram_blwl_outb[697:697] ,mux_2level_tapbuf_size16_32_configbus0[697:697], mux_2level_tapbuf_size16_32_configbus1[697:697] , mux_2level_tapbuf_size16_32_configbus0_b[697:697] ); -sram6T_blwl sram_blwl_698_ (mux_2level_tapbuf_size16_32_sram_blwl_out[698:698] ,mux_2level_tapbuf_size16_32_sram_blwl_out[698:698] ,mux_2level_tapbuf_size16_32_sram_blwl_outb[698:698] ,mux_2level_tapbuf_size16_32_configbus0[698:698], mux_2level_tapbuf_size16_32_configbus1[698:698] , mux_2level_tapbuf_size16_32_configbus0_b[698:698] ); -sram6T_blwl sram_blwl_699_ (mux_2level_tapbuf_size16_32_sram_blwl_out[699:699] ,mux_2level_tapbuf_size16_32_sram_blwl_out[699:699] ,mux_2level_tapbuf_size16_32_sram_blwl_outb[699:699] ,mux_2level_tapbuf_size16_32_configbus0[699:699], mux_2level_tapbuf_size16_32_configbus1[699:699] , mux_2level_tapbuf_size16_32_configbus0_b[699:699] ); -sram6T_blwl sram_blwl_700_ (mux_2level_tapbuf_size16_32_sram_blwl_out[700:700] ,mux_2level_tapbuf_size16_32_sram_blwl_out[700:700] ,mux_2level_tapbuf_size16_32_sram_blwl_outb[700:700] ,mux_2level_tapbuf_size16_32_configbus0[700:700], mux_2level_tapbuf_size16_32_configbus1[700:700] , mux_2level_tapbuf_size16_32_configbus0_b[700:700] ); -sram6T_blwl sram_blwl_701_ (mux_2level_tapbuf_size16_32_sram_blwl_out[701:701] ,mux_2level_tapbuf_size16_32_sram_blwl_out[701:701] ,mux_2level_tapbuf_size16_32_sram_blwl_outb[701:701] ,mux_2level_tapbuf_size16_32_configbus0[701:701], mux_2level_tapbuf_size16_32_configbus1[701:701] , mux_2level_tapbuf_size16_32_configbus0_b[701:701] ); -sram6T_blwl sram_blwl_702_ (mux_2level_tapbuf_size16_32_sram_blwl_out[702:702] ,mux_2level_tapbuf_size16_32_sram_blwl_out[702:702] ,mux_2level_tapbuf_size16_32_sram_blwl_outb[702:702] ,mux_2level_tapbuf_size16_32_configbus0[702:702], mux_2level_tapbuf_size16_32_configbus1[702:702] , mux_2level_tapbuf_size16_32_configbus0_b[702:702] ); -sram6T_blwl sram_blwl_703_ (mux_2level_tapbuf_size16_32_sram_blwl_out[703:703] ,mux_2level_tapbuf_size16_32_sram_blwl_out[703:703] ,mux_2level_tapbuf_size16_32_sram_blwl_outb[703:703] ,mux_2level_tapbuf_size16_32_configbus0[703:703], mux_2level_tapbuf_size16_32_configbus1[703:703] , mux_2level_tapbuf_size16_32_configbus0_b[703:703] ); -wire [0:15] mux_2level_tapbuf_size16_33_inbus; -assign mux_2level_tapbuf_size16_33_inbus[0] = chanx_1__1__midout_14_; -assign mux_2level_tapbuf_size16_33_inbus[1] = chanx_1__1__midout_15_; -assign mux_2level_tapbuf_size16_33_inbus[2] = chanx_1__1__midout_18_; -assign mux_2level_tapbuf_size16_33_inbus[3] = chanx_1__1__midout_19_; -assign mux_2level_tapbuf_size16_33_inbus[4] = chanx_1__1__midout_38_; -assign mux_2level_tapbuf_size16_33_inbus[5] = chanx_1__1__midout_39_; -assign mux_2level_tapbuf_size16_33_inbus[6] = chanx_1__1__midout_44_; -assign mux_2level_tapbuf_size16_33_inbus[7] = chanx_1__1__midout_45_; -assign mux_2level_tapbuf_size16_33_inbus[8] = chanx_1__1__midout_56_; -assign mux_2level_tapbuf_size16_33_inbus[9] = chanx_1__1__midout_57_; -assign mux_2level_tapbuf_size16_33_inbus[10] = chanx_1__1__midout_70_; -assign mux_2level_tapbuf_size16_33_inbus[11] = chanx_1__1__midout_71_; -assign mux_2level_tapbuf_size16_33_inbus[12] = chanx_1__1__midout_82_; -assign mux_2level_tapbuf_size16_33_inbus[13] = chanx_1__1__midout_83_; -assign mux_2level_tapbuf_size16_33_inbus[14] = chanx_1__1__midout_96_; -assign mux_2level_tapbuf_size16_33_inbus[15] = chanx_1__1__midout_97_; -wire [704:711] mux_2level_tapbuf_size16_33_configbus0; -wire [704:711] mux_2level_tapbuf_size16_33_configbus1; -wire [704:711] mux_2level_tapbuf_size16_33_sram_blwl_out ; -wire [704:711] mux_2level_tapbuf_size16_33_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_33_configbus0[704:711] = sram_blwl_bl[704:711] ; -assign mux_2level_tapbuf_size16_33_configbus1[704:711] = sram_blwl_wl[704:711] ; -wire [704:711] mux_2level_tapbuf_size16_33_configbus0_b; -assign mux_2level_tapbuf_size16_33_configbus0_b[704:711] = sram_blwl_blb[704:711] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_33_ (mux_2level_tapbuf_size16_33_inbus, grid_1__1__pin_0__0__28_, mux_2level_tapbuf_size16_33_sram_blwl_out[704:711] , -mux_2level_tapbuf_size16_33_sram_blwl_outb[704:711] ); -//----- SRAM bits for MUX[33], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_704_ (mux_2level_tapbuf_size16_33_sram_blwl_out[704:704] ,mux_2level_tapbuf_size16_33_sram_blwl_out[704:704] ,mux_2level_tapbuf_size16_33_sram_blwl_outb[704:704] ,mux_2level_tapbuf_size16_33_configbus0[704:704], mux_2level_tapbuf_size16_33_configbus1[704:704] , mux_2level_tapbuf_size16_33_configbus0_b[704:704] ); -sram6T_blwl sram_blwl_705_ (mux_2level_tapbuf_size16_33_sram_blwl_out[705:705] ,mux_2level_tapbuf_size16_33_sram_blwl_out[705:705] ,mux_2level_tapbuf_size16_33_sram_blwl_outb[705:705] ,mux_2level_tapbuf_size16_33_configbus0[705:705], mux_2level_tapbuf_size16_33_configbus1[705:705] , mux_2level_tapbuf_size16_33_configbus0_b[705:705] ); -sram6T_blwl sram_blwl_706_ (mux_2level_tapbuf_size16_33_sram_blwl_out[706:706] ,mux_2level_tapbuf_size16_33_sram_blwl_out[706:706] ,mux_2level_tapbuf_size16_33_sram_blwl_outb[706:706] ,mux_2level_tapbuf_size16_33_configbus0[706:706], mux_2level_tapbuf_size16_33_configbus1[706:706] , mux_2level_tapbuf_size16_33_configbus0_b[706:706] ); -sram6T_blwl sram_blwl_707_ (mux_2level_tapbuf_size16_33_sram_blwl_out[707:707] ,mux_2level_tapbuf_size16_33_sram_blwl_out[707:707] ,mux_2level_tapbuf_size16_33_sram_blwl_outb[707:707] ,mux_2level_tapbuf_size16_33_configbus0[707:707], mux_2level_tapbuf_size16_33_configbus1[707:707] , mux_2level_tapbuf_size16_33_configbus0_b[707:707] ); -sram6T_blwl sram_blwl_708_ (mux_2level_tapbuf_size16_33_sram_blwl_out[708:708] ,mux_2level_tapbuf_size16_33_sram_blwl_out[708:708] ,mux_2level_tapbuf_size16_33_sram_blwl_outb[708:708] ,mux_2level_tapbuf_size16_33_configbus0[708:708], mux_2level_tapbuf_size16_33_configbus1[708:708] , mux_2level_tapbuf_size16_33_configbus0_b[708:708] ); -sram6T_blwl sram_blwl_709_ (mux_2level_tapbuf_size16_33_sram_blwl_out[709:709] ,mux_2level_tapbuf_size16_33_sram_blwl_out[709:709] ,mux_2level_tapbuf_size16_33_sram_blwl_outb[709:709] ,mux_2level_tapbuf_size16_33_configbus0[709:709], mux_2level_tapbuf_size16_33_configbus1[709:709] , mux_2level_tapbuf_size16_33_configbus0_b[709:709] ); -sram6T_blwl sram_blwl_710_ (mux_2level_tapbuf_size16_33_sram_blwl_out[710:710] ,mux_2level_tapbuf_size16_33_sram_blwl_out[710:710] ,mux_2level_tapbuf_size16_33_sram_blwl_outb[710:710] ,mux_2level_tapbuf_size16_33_configbus0[710:710], mux_2level_tapbuf_size16_33_configbus1[710:710] , mux_2level_tapbuf_size16_33_configbus0_b[710:710] ); -sram6T_blwl sram_blwl_711_ (mux_2level_tapbuf_size16_33_sram_blwl_out[711:711] ,mux_2level_tapbuf_size16_33_sram_blwl_out[711:711] ,mux_2level_tapbuf_size16_33_sram_blwl_outb[711:711] ,mux_2level_tapbuf_size16_33_configbus0[711:711], mux_2level_tapbuf_size16_33_configbus1[711:711] , mux_2level_tapbuf_size16_33_configbus0_b[711:711] ); -wire [0:15] mux_2level_tapbuf_size16_34_inbus; -assign mux_2level_tapbuf_size16_34_inbus[0] = chanx_1__1__midout_8_; -assign mux_2level_tapbuf_size16_34_inbus[1] = chanx_1__1__midout_9_; -assign mux_2level_tapbuf_size16_34_inbus[2] = chanx_1__1__midout_20_; -assign mux_2level_tapbuf_size16_34_inbus[3] = chanx_1__1__midout_21_; -assign mux_2level_tapbuf_size16_34_inbus[4] = chanx_1__1__midout_32_; -assign mux_2level_tapbuf_size16_34_inbus[5] = chanx_1__1__midout_33_; -assign mux_2level_tapbuf_size16_34_inbus[6] = chanx_1__1__midout_44_; -assign mux_2level_tapbuf_size16_34_inbus[7] = chanx_1__1__midout_45_; -assign mux_2level_tapbuf_size16_34_inbus[8] = chanx_1__1__midout_62_; -assign mux_2level_tapbuf_size16_34_inbus[9] = chanx_1__1__midout_63_; -assign mux_2level_tapbuf_size16_34_inbus[10] = chanx_1__1__midout_72_; -assign mux_2level_tapbuf_size16_34_inbus[11] = chanx_1__1__midout_73_; -assign mux_2level_tapbuf_size16_34_inbus[12] = chanx_1__1__midout_84_; -assign mux_2level_tapbuf_size16_34_inbus[13] = chanx_1__1__midout_85_; -assign mux_2level_tapbuf_size16_34_inbus[14] = chanx_1__1__midout_96_; -assign mux_2level_tapbuf_size16_34_inbus[15] = chanx_1__1__midout_97_; -wire [712:719] mux_2level_tapbuf_size16_34_configbus0; -wire [712:719] mux_2level_tapbuf_size16_34_configbus1; -wire [712:719] mux_2level_tapbuf_size16_34_sram_blwl_out ; -wire [712:719] mux_2level_tapbuf_size16_34_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_34_configbus0[712:719] = sram_blwl_bl[712:719] ; -assign mux_2level_tapbuf_size16_34_configbus1[712:719] = sram_blwl_wl[712:719] ; -wire [712:719] mux_2level_tapbuf_size16_34_configbus0_b; -assign mux_2level_tapbuf_size16_34_configbus0_b[712:719] = sram_blwl_blb[712:719] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_34_ (mux_2level_tapbuf_size16_34_inbus, grid_1__1__pin_0__0__32_, mux_2level_tapbuf_size16_34_sram_blwl_out[712:719] , -mux_2level_tapbuf_size16_34_sram_blwl_outb[712:719] ); -//----- SRAM bits for MUX[34], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_712_ (mux_2level_tapbuf_size16_34_sram_blwl_out[712:712] ,mux_2level_tapbuf_size16_34_sram_blwl_out[712:712] ,mux_2level_tapbuf_size16_34_sram_blwl_outb[712:712] ,mux_2level_tapbuf_size16_34_configbus0[712:712], mux_2level_tapbuf_size16_34_configbus1[712:712] , mux_2level_tapbuf_size16_34_configbus0_b[712:712] ); -sram6T_blwl sram_blwl_713_ (mux_2level_tapbuf_size16_34_sram_blwl_out[713:713] ,mux_2level_tapbuf_size16_34_sram_blwl_out[713:713] ,mux_2level_tapbuf_size16_34_sram_blwl_outb[713:713] ,mux_2level_tapbuf_size16_34_configbus0[713:713], mux_2level_tapbuf_size16_34_configbus1[713:713] , mux_2level_tapbuf_size16_34_configbus0_b[713:713] ); -sram6T_blwl sram_blwl_714_ (mux_2level_tapbuf_size16_34_sram_blwl_out[714:714] ,mux_2level_tapbuf_size16_34_sram_blwl_out[714:714] ,mux_2level_tapbuf_size16_34_sram_blwl_outb[714:714] ,mux_2level_tapbuf_size16_34_configbus0[714:714], mux_2level_tapbuf_size16_34_configbus1[714:714] , mux_2level_tapbuf_size16_34_configbus0_b[714:714] ); -sram6T_blwl sram_blwl_715_ (mux_2level_tapbuf_size16_34_sram_blwl_out[715:715] ,mux_2level_tapbuf_size16_34_sram_blwl_out[715:715] ,mux_2level_tapbuf_size16_34_sram_blwl_outb[715:715] ,mux_2level_tapbuf_size16_34_configbus0[715:715], mux_2level_tapbuf_size16_34_configbus1[715:715] , mux_2level_tapbuf_size16_34_configbus0_b[715:715] ); -sram6T_blwl sram_blwl_716_ (mux_2level_tapbuf_size16_34_sram_blwl_out[716:716] ,mux_2level_tapbuf_size16_34_sram_blwl_out[716:716] ,mux_2level_tapbuf_size16_34_sram_blwl_outb[716:716] ,mux_2level_tapbuf_size16_34_configbus0[716:716], mux_2level_tapbuf_size16_34_configbus1[716:716] , mux_2level_tapbuf_size16_34_configbus0_b[716:716] ); -sram6T_blwl sram_blwl_717_ (mux_2level_tapbuf_size16_34_sram_blwl_out[717:717] ,mux_2level_tapbuf_size16_34_sram_blwl_out[717:717] ,mux_2level_tapbuf_size16_34_sram_blwl_outb[717:717] ,mux_2level_tapbuf_size16_34_configbus0[717:717], mux_2level_tapbuf_size16_34_configbus1[717:717] , mux_2level_tapbuf_size16_34_configbus0_b[717:717] ); -sram6T_blwl sram_blwl_718_ (mux_2level_tapbuf_size16_34_sram_blwl_out[718:718] ,mux_2level_tapbuf_size16_34_sram_blwl_out[718:718] ,mux_2level_tapbuf_size16_34_sram_blwl_outb[718:718] ,mux_2level_tapbuf_size16_34_configbus0[718:718], mux_2level_tapbuf_size16_34_configbus1[718:718] , mux_2level_tapbuf_size16_34_configbus0_b[718:718] ); -sram6T_blwl sram_blwl_719_ (mux_2level_tapbuf_size16_34_sram_blwl_out[719:719] ,mux_2level_tapbuf_size16_34_sram_blwl_out[719:719] ,mux_2level_tapbuf_size16_34_sram_blwl_outb[719:719] ,mux_2level_tapbuf_size16_34_configbus0[719:719], mux_2level_tapbuf_size16_34_configbus1[719:719] , mux_2level_tapbuf_size16_34_configbus0_b[719:719] ); -wire [0:15] mux_2level_tapbuf_size16_35_inbus; -assign mux_2level_tapbuf_size16_35_inbus[0] = chanx_1__1__midout_8_; -assign mux_2level_tapbuf_size16_35_inbus[1] = chanx_1__1__midout_9_; -assign mux_2level_tapbuf_size16_35_inbus[2] = chanx_1__1__midout_20_; -assign mux_2level_tapbuf_size16_35_inbus[3] = chanx_1__1__midout_21_; -assign mux_2level_tapbuf_size16_35_inbus[4] = chanx_1__1__midout_34_; -assign mux_2level_tapbuf_size16_35_inbus[5] = chanx_1__1__midout_35_; -assign mux_2level_tapbuf_size16_35_inbus[6] = chanx_1__1__midout_50_; -assign mux_2level_tapbuf_size16_35_inbus[7] = chanx_1__1__midout_51_; -assign mux_2level_tapbuf_size16_35_inbus[8] = chanx_1__1__midout_62_; -assign mux_2level_tapbuf_size16_35_inbus[9] = chanx_1__1__midout_63_; -assign mux_2level_tapbuf_size16_35_inbus[10] = chanx_1__1__midout_72_; -assign mux_2level_tapbuf_size16_35_inbus[11] = chanx_1__1__midout_73_; -assign mux_2level_tapbuf_size16_35_inbus[12] = chanx_1__1__midout_86_; -assign mux_2level_tapbuf_size16_35_inbus[13] = chanx_1__1__midout_87_; -assign mux_2level_tapbuf_size16_35_inbus[14] = chanx_1__1__midout_98_; -assign mux_2level_tapbuf_size16_35_inbus[15] = chanx_1__1__midout_99_; -wire [720:727] mux_2level_tapbuf_size16_35_configbus0; -wire [720:727] mux_2level_tapbuf_size16_35_configbus1; -wire [720:727] mux_2level_tapbuf_size16_35_sram_blwl_out ; -wire [720:727] mux_2level_tapbuf_size16_35_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_35_configbus0[720:727] = sram_blwl_bl[720:727] ; -assign mux_2level_tapbuf_size16_35_configbus1[720:727] = sram_blwl_wl[720:727] ; -wire [720:727] mux_2level_tapbuf_size16_35_configbus0_b; -assign mux_2level_tapbuf_size16_35_configbus0_b[720:727] = sram_blwl_blb[720:727] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_35_ (mux_2level_tapbuf_size16_35_inbus, grid_1__1__pin_0__0__36_, mux_2level_tapbuf_size16_35_sram_blwl_out[720:727] , -mux_2level_tapbuf_size16_35_sram_blwl_outb[720:727] ); -//----- SRAM bits for MUX[35], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_720_ (mux_2level_tapbuf_size16_35_sram_blwl_out[720:720] ,mux_2level_tapbuf_size16_35_sram_blwl_out[720:720] ,mux_2level_tapbuf_size16_35_sram_blwl_outb[720:720] ,mux_2level_tapbuf_size16_35_configbus0[720:720], mux_2level_tapbuf_size16_35_configbus1[720:720] , mux_2level_tapbuf_size16_35_configbus0_b[720:720] ); -sram6T_blwl sram_blwl_721_ (mux_2level_tapbuf_size16_35_sram_blwl_out[721:721] ,mux_2level_tapbuf_size16_35_sram_blwl_out[721:721] ,mux_2level_tapbuf_size16_35_sram_blwl_outb[721:721] ,mux_2level_tapbuf_size16_35_configbus0[721:721], mux_2level_tapbuf_size16_35_configbus1[721:721] , mux_2level_tapbuf_size16_35_configbus0_b[721:721] ); -sram6T_blwl sram_blwl_722_ (mux_2level_tapbuf_size16_35_sram_blwl_out[722:722] ,mux_2level_tapbuf_size16_35_sram_blwl_out[722:722] ,mux_2level_tapbuf_size16_35_sram_blwl_outb[722:722] ,mux_2level_tapbuf_size16_35_configbus0[722:722], mux_2level_tapbuf_size16_35_configbus1[722:722] , mux_2level_tapbuf_size16_35_configbus0_b[722:722] ); -sram6T_blwl sram_blwl_723_ (mux_2level_tapbuf_size16_35_sram_blwl_out[723:723] ,mux_2level_tapbuf_size16_35_sram_blwl_out[723:723] ,mux_2level_tapbuf_size16_35_sram_blwl_outb[723:723] ,mux_2level_tapbuf_size16_35_configbus0[723:723], mux_2level_tapbuf_size16_35_configbus1[723:723] , mux_2level_tapbuf_size16_35_configbus0_b[723:723] ); -sram6T_blwl sram_blwl_724_ (mux_2level_tapbuf_size16_35_sram_blwl_out[724:724] ,mux_2level_tapbuf_size16_35_sram_blwl_out[724:724] ,mux_2level_tapbuf_size16_35_sram_blwl_outb[724:724] ,mux_2level_tapbuf_size16_35_configbus0[724:724], mux_2level_tapbuf_size16_35_configbus1[724:724] , mux_2level_tapbuf_size16_35_configbus0_b[724:724] ); -sram6T_blwl sram_blwl_725_ (mux_2level_tapbuf_size16_35_sram_blwl_out[725:725] ,mux_2level_tapbuf_size16_35_sram_blwl_out[725:725] ,mux_2level_tapbuf_size16_35_sram_blwl_outb[725:725] ,mux_2level_tapbuf_size16_35_configbus0[725:725], mux_2level_tapbuf_size16_35_configbus1[725:725] , mux_2level_tapbuf_size16_35_configbus0_b[725:725] ); -sram6T_blwl sram_blwl_726_ (mux_2level_tapbuf_size16_35_sram_blwl_out[726:726] ,mux_2level_tapbuf_size16_35_sram_blwl_out[726:726] ,mux_2level_tapbuf_size16_35_sram_blwl_outb[726:726] ,mux_2level_tapbuf_size16_35_configbus0[726:726], mux_2level_tapbuf_size16_35_configbus1[726:726] , mux_2level_tapbuf_size16_35_configbus0_b[726:726] ); -sram6T_blwl sram_blwl_727_ (mux_2level_tapbuf_size16_35_sram_blwl_out[727:727] ,mux_2level_tapbuf_size16_35_sram_blwl_out[727:727] ,mux_2level_tapbuf_size16_35_sram_blwl_outb[727:727] ,mux_2level_tapbuf_size16_35_configbus0[727:727], mux_2level_tapbuf_size16_35_configbus1[727:727] , mux_2level_tapbuf_size16_35_configbus0_b[727:727] ); -endmodule -//----- END Verilog Module of Connection Box -X direction [1][1] ----- - diff --git a/examples/verilog_test_example_2/routing/cby_0_1.v b/examples/verilog_test_example_2/routing/cby_0_1.v deleted file mode 100644 index 24d1026ef..000000000 --- a/examples/verilog_test_example_2/routing/cby_0_1.v +++ /dev/null @@ -1,946 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Connection Block - Y direction [0][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Connection Box -Y direction [0][1] ----- -module cby_0__1_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input chany_0__1__midout_0_, - -input chany_0__1__midout_1_, - -input chany_0__1__midout_2_, - -input chany_0__1__midout_3_, - -input chany_0__1__midout_4_, - -input chany_0__1__midout_5_, - -input chany_0__1__midout_6_, - -input chany_0__1__midout_7_, - -input chany_0__1__midout_8_, - -input chany_0__1__midout_9_, - -input chany_0__1__midout_10_, - -input chany_0__1__midout_11_, - -input chany_0__1__midout_12_, - -input chany_0__1__midout_13_, - -input chany_0__1__midout_14_, - -input chany_0__1__midout_15_, - -input chany_0__1__midout_16_, - -input chany_0__1__midout_17_, - -input chany_0__1__midout_18_, - -input chany_0__1__midout_19_, - -input chany_0__1__midout_20_, - -input chany_0__1__midout_21_, - -input chany_0__1__midout_22_, - -input chany_0__1__midout_23_, - -input chany_0__1__midout_24_, - -input chany_0__1__midout_25_, - -input chany_0__1__midout_26_, - -input chany_0__1__midout_27_, - -input chany_0__1__midout_28_, - -input chany_0__1__midout_29_, - -input chany_0__1__midout_30_, - -input chany_0__1__midout_31_, - -input chany_0__1__midout_32_, - -input chany_0__1__midout_33_, - -input chany_0__1__midout_34_, - -input chany_0__1__midout_35_, - -input chany_0__1__midout_36_, - -input chany_0__1__midout_37_, - -input chany_0__1__midout_38_, - -input chany_0__1__midout_39_, - -input chany_0__1__midout_40_, - -input chany_0__1__midout_41_, - -input chany_0__1__midout_42_, - -input chany_0__1__midout_43_, - -input chany_0__1__midout_44_, - -input chany_0__1__midout_45_, - -input chany_0__1__midout_46_, - -input chany_0__1__midout_47_, - -input chany_0__1__midout_48_, - -input chany_0__1__midout_49_, - -input chany_0__1__midout_50_, - -input chany_0__1__midout_51_, - -input chany_0__1__midout_52_, - -input chany_0__1__midout_53_, - -input chany_0__1__midout_54_, - -input chany_0__1__midout_55_, - -input chany_0__1__midout_56_, - -input chany_0__1__midout_57_, - -input chany_0__1__midout_58_, - -input chany_0__1__midout_59_, - -input chany_0__1__midout_60_, - -input chany_0__1__midout_61_, - -input chany_0__1__midout_62_, - -input chany_0__1__midout_63_, - -input chany_0__1__midout_64_, - -input chany_0__1__midout_65_, - -input chany_0__1__midout_66_, - -input chany_0__1__midout_67_, - -input chany_0__1__midout_68_, - -input chany_0__1__midout_69_, - -input chany_0__1__midout_70_, - -input chany_0__1__midout_71_, - -input chany_0__1__midout_72_, - -input chany_0__1__midout_73_, - -input chany_0__1__midout_74_, - -input chany_0__1__midout_75_, - -input chany_0__1__midout_76_, - -input chany_0__1__midout_77_, - -input chany_0__1__midout_78_, - -input chany_0__1__midout_79_, - -input chany_0__1__midout_80_, - -input chany_0__1__midout_81_, - -input chany_0__1__midout_82_, - -input chany_0__1__midout_83_, - -input chany_0__1__midout_84_, - -input chany_0__1__midout_85_, - -input chany_0__1__midout_86_, - -input chany_0__1__midout_87_, - -input chany_0__1__midout_88_, - -input chany_0__1__midout_89_, - -input chany_0__1__midout_90_, - -input chany_0__1__midout_91_, - -input chany_0__1__midout_92_, - -input chany_0__1__midout_93_, - -input chany_0__1__midout_94_, - -input chany_0__1__midout_95_, - -input chany_0__1__midout_96_, - -input chany_0__1__midout_97_, - -input chany_0__1__midout_98_, - -input chany_0__1__midout_99_, - -output grid_1__1__pin_0__3__3_, - -output grid_1__1__pin_0__3__7_, - -output grid_1__1__pin_0__3__11_, - -output grid_1__1__pin_0__3__15_, - -output grid_1__1__pin_0__3__19_, - -output grid_1__1__pin_0__3__23_, - -output grid_1__1__pin_0__3__27_, - -output grid_1__1__pin_0__3__31_, - -output grid_1__1__pin_0__3__35_, - -output grid_1__1__pin_0__3__39_, - -output grid_0__1__pin_0__1__0_, - -output grid_0__1__pin_0__1__2_, - -output grid_0__1__pin_0__1__4_, - -output grid_0__1__pin_0__1__6_, - -output grid_0__1__pin_0__1__8_, - -output grid_0__1__pin_0__1__10_, - -output grid_0__1__pin_0__1__12_, - -output grid_0__1__pin_0__1__14_, - -input [728:871] sram_blwl_bl , -input [728:871] sram_blwl_wl , -input [728:871] sram_blwl_blb ); -wire [0:15] mux_2level_tapbuf_size16_36_inbus; -assign mux_2level_tapbuf_size16_36_inbus[0] = chany_0__1__midout_0_; -assign mux_2level_tapbuf_size16_36_inbus[1] = chany_0__1__midout_1_; -assign mux_2level_tapbuf_size16_36_inbus[2] = chany_0__1__midout_12_; -assign mux_2level_tapbuf_size16_36_inbus[3] = chany_0__1__midout_13_; -assign mux_2level_tapbuf_size16_36_inbus[4] = chany_0__1__midout_24_; -assign mux_2level_tapbuf_size16_36_inbus[5] = chany_0__1__midout_25_; -assign mux_2level_tapbuf_size16_36_inbus[6] = chany_0__1__midout_38_; -assign mux_2level_tapbuf_size16_36_inbus[7] = chany_0__1__midout_39_; -assign mux_2level_tapbuf_size16_36_inbus[8] = chany_0__1__midout_50_; -assign mux_2level_tapbuf_size16_36_inbus[9] = chany_0__1__midout_51_; -assign mux_2level_tapbuf_size16_36_inbus[10] = chany_0__1__midout_62_; -assign mux_2level_tapbuf_size16_36_inbus[11] = chany_0__1__midout_63_; -assign mux_2level_tapbuf_size16_36_inbus[12] = chany_0__1__midout_74_; -assign mux_2level_tapbuf_size16_36_inbus[13] = chany_0__1__midout_75_; -assign mux_2level_tapbuf_size16_36_inbus[14] = chany_0__1__midout_88_; -assign mux_2level_tapbuf_size16_36_inbus[15] = chany_0__1__midout_89_; -wire [728:735] mux_2level_tapbuf_size16_36_configbus0; -wire [728:735] mux_2level_tapbuf_size16_36_configbus1; -wire [728:735] mux_2level_tapbuf_size16_36_sram_blwl_out ; -wire [728:735] mux_2level_tapbuf_size16_36_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_36_configbus0[728:735] = sram_blwl_bl[728:735] ; -assign mux_2level_tapbuf_size16_36_configbus1[728:735] = sram_blwl_wl[728:735] ; -wire [728:735] mux_2level_tapbuf_size16_36_configbus0_b; -assign mux_2level_tapbuf_size16_36_configbus0_b[728:735] = sram_blwl_blb[728:735] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_36_ (mux_2level_tapbuf_size16_36_inbus, grid_1__1__pin_0__3__3_, mux_2level_tapbuf_size16_36_sram_blwl_out[728:735] , -mux_2level_tapbuf_size16_36_sram_blwl_outb[728:735] ); -//----- SRAM bits for MUX[36], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_728_ (mux_2level_tapbuf_size16_36_sram_blwl_out[728:728] ,mux_2level_tapbuf_size16_36_sram_blwl_out[728:728] ,mux_2level_tapbuf_size16_36_sram_blwl_outb[728:728] ,mux_2level_tapbuf_size16_36_configbus0[728:728], mux_2level_tapbuf_size16_36_configbus1[728:728] , mux_2level_tapbuf_size16_36_configbus0_b[728:728] ); -sram6T_blwl sram_blwl_729_ (mux_2level_tapbuf_size16_36_sram_blwl_out[729:729] ,mux_2level_tapbuf_size16_36_sram_blwl_out[729:729] ,mux_2level_tapbuf_size16_36_sram_blwl_outb[729:729] ,mux_2level_tapbuf_size16_36_configbus0[729:729], mux_2level_tapbuf_size16_36_configbus1[729:729] , mux_2level_tapbuf_size16_36_configbus0_b[729:729] ); -sram6T_blwl sram_blwl_730_ (mux_2level_tapbuf_size16_36_sram_blwl_out[730:730] ,mux_2level_tapbuf_size16_36_sram_blwl_out[730:730] ,mux_2level_tapbuf_size16_36_sram_blwl_outb[730:730] ,mux_2level_tapbuf_size16_36_configbus0[730:730], mux_2level_tapbuf_size16_36_configbus1[730:730] , mux_2level_tapbuf_size16_36_configbus0_b[730:730] ); -sram6T_blwl sram_blwl_731_ (mux_2level_tapbuf_size16_36_sram_blwl_out[731:731] ,mux_2level_tapbuf_size16_36_sram_blwl_out[731:731] ,mux_2level_tapbuf_size16_36_sram_blwl_outb[731:731] ,mux_2level_tapbuf_size16_36_configbus0[731:731], mux_2level_tapbuf_size16_36_configbus1[731:731] , mux_2level_tapbuf_size16_36_configbus0_b[731:731] ); -sram6T_blwl sram_blwl_732_ (mux_2level_tapbuf_size16_36_sram_blwl_out[732:732] ,mux_2level_tapbuf_size16_36_sram_blwl_out[732:732] ,mux_2level_tapbuf_size16_36_sram_blwl_outb[732:732] ,mux_2level_tapbuf_size16_36_configbus0[732:732], mux_2level_tapbuf_size16_36_configbus1[732:732] , mux_2level_tapbuf_size16_36_configbus0_b[732:732] ); -sram6T_blwl sram_blwl_733_ (mux_2level_tapbuf_size16_36_sram_blwl_out[733:733] ,mux_2level_tapbuf_size16_36_sram_blwl_out[733:733] ,mux_2level_tapbuf_size16_36_sram_blwl_outb[733:733] ,mux_2level_tapbuf_size16_36_configbus0[733:733], mux_2level_tapbuf_size16_36_configbus1[733:733] , mux_2level_tapbuf_size16_36_configbus0_b[733:733] ); -sram6T_blwl sram_blwl_734_ (mux_2level_tapbuf_size16_36_sram_blwl_out[734:734] ,mux_2level_tapbuf_size16_36_sram_blwl_out[734:734] ,mux_2level_tapbuf_size16_36_sram_blwl_outb[734:734] ,mux_2level_tapbuf_size16_36_configbus0[734:734], mux_2level_tapbuf_size16_36_configbus1[734:734] , mux_2level_tapbuf_size16_36_configbus0_b[734:734] ); -sram6T_blwl sram_blwl_735_ (mux_2level_tapbuf_size16_36_sram_blwl_out[735:735] ,mux_2level_tapbuf_size16_36_sram_blwl_out[735:735] ,mux_2level_tapbuf_size16_36_sram_blwl_outb[735:735] ,mux_2level_tapbuf_size16_36_configbus0[735:735], mux_2level_tapbuf_size16_36_configbus1[735:735] , mux_2level_tapbuf_size16_36_configbus0_b[735:735] ); -wire [0:15] mux_2level_tapbuf_size16_37_inbus; -assign mux_2level_tapbuf_size16_37_inbus[0] = chany_0__1__midout_2_; -assign mux_2level_tapbuf_size16_37_inbus[1] = chany_0__1__midout_3_; -assign mux_2level_tapbuf_size16_37_inbus[2] = chany_0__1__midout_14_; -assign mux_2level_tapbuf_size16_37_inbus[3] = chany_0__1__midout_15_; -assign mux_2level_tapbuf_size16_37_inbus[4] = chany_0__1__midout_26_; -assign mux_2level_tapbuf_size16_37_inbus[5] = chany_0__1__midout_27_; -assign mux_2level_tapbuf_size16_37_inbus[6] = chany_0__1__midout_38_; -assign mux_2level_tapbuf_size16_37_inbus[7] = chany_0__1__midout_39_; -assign mux_2level_tapbuf_size16_37_inbus[8] = chany_0__1__midout_52_; -assign mux_2level_tapbuf_size16_37_inbus[9] = chany_0__1__midout_53_; -assign mux_2level_tapbuf_size16_37_inbus[10] = chany_0__1__midout_64_; -assign mux_2level_tapbuf_size16_37_inbus[11] = chany_0__1__midout_65_; -assign mux_2level_tapbuf_size16_37_inbus[12] = chany_0__1__midout_76_; -assign mux_2level_tapbuf_size16_37_inbus[13] = chany_0__1__midout_77_; -assign mux_2level_tapbuf_size16_37_inbus[14] = chany_0__1__midout_88_; -assign mux_2level_tapbuf_size16_37_inbus[15] = chany_0__1__midout_89_; -wire [736:743] mux_2level_tapbuf_size16_37_configbus0; -wire [736:743] mux_2level_tapbuf_size16_37_configbus1; -wire [736:743] mux_2level_tapbuf_size16_37_sram_blwl_out ; -wire [736:743] mux_2level_tapbuf_size16_37_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_37_configbus0[736:743] = sram_blwl_bl[736:743] ; -assign mux_2level_tapbuf_size16_37_configbus1[736:743] = sram_blwl_wl[736:743] ; -wire [736:743] mux_2level_tapbuf_size16_37_configbus0_b; -assign mux_2level_tapbuf_size16_37_configbus0_b[736:743] = sram_blwl_blb[736:743] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_37_ (mux_2level_tapbuf_size16_37_inbus, grid_1__1__pin_0__3__7_, mux_2level_tapbuf_size16_37_sram_blwl_out[736:743] , -mux_2level_tapbuf_size16_37_sram_blwl_outb[736:743] ); -//----- SRAM bits for MUX[37], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_736_ (mux_2level_tapbuf_size16_37_sram_blwl_out[736:736] ,mux_2level_tapbuf_size16_37_sram_blwl_out[736:736] ,mux_2level_tapbuf_size16_37_sram_blwl_outb[736:736] ,mux_2level_tapbuf_size16_37_configbus0[736:736], mux_2level_tapbuf_size16_37_configbus1[736:736] , mux_2level_tapbuf_size16_37_configbus0_b[736:736] ); -sram6T_blwl sram_blwl_737_ (mux_2level_tapbuf_size16_37_sram_blwl_out[737:737] ,mux_2level_tapbuf_size16_37_sram_blwl_out[737:737] ,mux_2level_tapbuf_size16_37_sram_blwl_outb[737:737] ,mux_2level_tapbuf_size16_37_configbus0[737:737], mux_2level_tapbuf_size16_37_configbus1[737:737] , mux_2level_tapbuf_size16_37_configbus0_b[737:737] ); -sram6T_blwl sram_blwl_738_ (mux_2level_tapbuf_size16_37_sram_blwl_out[738:738] ,mux_2level_tapbuf_size16_37_sram_blwl_out[738:738] ,mux_2level_tapbuf_size16_37_sram_blwl_outb[738:738] ,mux_2level_tapbuf_size16_37_configbus0[738:738], mux_2level_tapbuf_size16_37_configbus1[738:738] , mux_2level_tapbuf_size16_37_configbus0_b[738:738] ); -sram6T_blwl sram_blwl_739_ (mux_2level_tapbuf_size16_37_sram_blwl_out[739:739] ,mux_2level_tapbuf_size16_37_sram_blwl_out[739:739] ,mux_2level_tapbuf_size16_37_sram_blwl_outb[739:739] ,mux_2level_tapbuf_size16_37_configbus0[739:739], mux_2level_tapbuf_size16_37_configbus1[739:739] , mux_2level_tapbuf_size16_37_configbus0_b[739:739] ); -sram6T_blwl sram_blwl_740_ (mux_2level_tapbuf_size16_37_sram_blwl_out[740:740] ,mux_2level_tapbuf_size16_37_sram_blwl_out[740:740] ,mux_2level_tapbuf_size16_37_sram_blwl_outb[740:740] ,mux_2level_tapbuf_size16_37_configbus0[740:740], mux_2level_tapbuf_size16_37_configbus1[740:740] , mux_2level_tapbuf_size16_37_configbus0_b[740:740] ); -sram6T_blwl sram_blwl_741_ (mux_2level_tapbuf_size16_37_sram_blwl_out[741:741] ,mux_2level_tapbuf_size16_37_sram_blwl_out[741:741] ,mux_2level_tapbuf_size16_37_sram_blwl_outb[741:741] ,mux_2level_tapbuf_size16_37_configbus0[741:741], mux_2level_tapbuf_size16_37_configbus1[741:741] , mux_2level_tapbuf_size16_37_configbus0_b[741:741] ); -sram6T_blwl sram_blwl_742_ (mux_2level_tapbuf_size16_37_sram_blwl_out[742:742] ,mux_2level_tapbuf_size16_37_sram_blwl_out[742:742] ,mux_2level_tapbuf_size16_37_sram_blwl_outb[742:742] ,mux_2level_tapbuf_size16_37_configbus0[742:742], mux_2level_tapbuf_size16_37_configbus1[742:742] , mux_2level_tapbuf_size16_37_configbus0_b[742:742] ); -sram6T_blwl sram_blwl_743_ (mux_2level_tapbuf_size16_37_sram_blwl_out[743:743] ,mux_2level_tapbuf_size16_37_sram_blwl_out[743:743] ,mux_2level_tapbuf_size16_37_sram_blwl_outb[743:743] ,mux_2level_tapbuf_size16_37_configbus0[743:743], mux_2level_tapbuf_size16_37_configbus1[743:743] , mux_2level_tapbuf_size16_37_configbus0_b[743:743] ); -wire [0:15] mux_2level_tapbuf_size16_38_inbus; -assign mux_2level_tapbuf_size16_38_inbus[0] = chany_0__1__midout_2_; -assign mux_2level_tapbuf_size16_38_inbus[1] = chany_0__1__midout_3_; -assign mux_2level_tapbuf_size16_38_inbus[2] = chany_0__1__midout_14_; -assign mux_2level_tapbuf_size16_38_inbus[3] = chany_0__1__midout_15_; -assign mux_2level_tapbuf_size16_38_inbus[4] = chany_0__1__midout_28_; -assign mux_2level_tapbuf_size16_38_inbus[5] = chany_0__1__midout_29_; -assign mux_2level_tapbuf_size16_38_inbus[6] = chany_0__1__midout_40_; -assign mux_2level_tapbuf_size16_38_inbus[7] = chany_0__1__midout_41_; -assign mux_2level_tapbuf_size16_38_inbus[8] = chany_0__1__midout_52_; -assign mux_2level_tapbuf_size16_38_inbus[9] = chany_0__1__midout_53_; -assign mux_2level_tapbuf_size16_38_inbus[10] = chany_0__1__midout_64_; -assign mux_2level_tapbuf_size16_38_inbus[11] = chany_0__1__midout_65_; -assign mux_2level_tapbuf_size16_38_inbus[12] = chany_0__1__midout_78_; -assign mux_2level_tapbuf_size16_38_inbus[13] = chany_0__1__midout_79_; -assign mux_2level_tapbuf_size16_38_inbus[14] = chany_0__1__midout_90_; -assign mux_2level_tapbuf_size16_38_inbus[15] = chany_0__1__midout_91_; -wire [744:751] mux_2level_tapbuf_size16_38_configbus0; -wire [744:751] mux_2level_tapbuf_size16_38_configbus1; -wire [744:751] mux_2level_tapbuf_size16_38_sram_blwl_out ; -wire [744:751] mux_2level_tapbuf_size16_38_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_38_configbus0[744:751] = sram_blwl_bl[744:751] ; -assign mux_2level_tapbuf_size16_38_configbus1[744:751] = sram_blwl_wl[744:751] ; -wire [744:751] mux_2level_tapbuf_size16_38_configbus0_b; -assign mux_2level_tapbuf_size16_38_configbus0_b[744:751] = sram_blwl_blb[744:751] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_38_ (mux_2level_tapbuf_size16_38_inbus, grid_1__1__pin_0__3__11_, mux_2level_tapbuf_size16_38_sram_blwl_out[744:751] , -mux_2level_tapbuf_size16_38_sram_blwl_outb[744:751] ); -//----- SRAM bits for MUX[38], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_744_ (mux_2level_tapbuf_size16_38_sram_blwl_out[744:744] ,mux_2level_tapbuf_size16_38_sram_blwl_out[744:744] ,mux_2level_tapbuf_size16_38_sram_blwl_outb[744:744] ,mux_2level_tapbuf_size16_38_configbus0[744:744], mux_2level_tapbuf_size16_38_configbus1[744:744] , mux_2level_tapbuf_size16_38_configbus0_b[744:744] ); -sram6T_blwl sram_blwl_745_ (mux_2level_tapbuf_size16_38_sram_blwl_out[745:745] ,mux_2level_tapbuf_size16_38_sram_blwl_out[745:745] ,mux_2level_tapbuf_size16_38_sram_blwl_outb[745:745] ,mux_2level_tapbuf_size16_38_configbus0[745:745], mux_2level_tapbuf_size16_38_configbus1[745:745] , mux_2level_tapbuf_size16_38_configbus0_b[745:745] ); -sram6T_blwl sram_blwl_746_ (mux_2level_tapbuf_size16_38_sram_blwl_out[746:746] ,mux_2level_tapbuf_size16_38_sram_blwl_out[746:746] ,mux_2level_tapbuf_size16_38_sram_blwl_outb[746:746] ,mux_2level_tapbuf_size16_38_configbus0[746:746], mux_2level_tapbuf_size16_38_configbus1[746:746] , mux_2level_tapbuf_size16_38_configbus0_b[746:746] ); -sram6T_blwl sram_blwl_747_ (mux_2level_tapbuf_size16_38_sram_blwl_out[747:747] ,mux_2level_tapbuf_size16_38_sram_blwl_out[747:747] ,mux_2level_tapbuf_size16_38_sram_blwl_outb[747:747] ,mux_2level_tapbuf_size16_38_configbus0[747:747], mux_2level_tapbuf_size16_38_configbus1[747:747] , mux_2level_tapbuf_size16_38_configbus0_b[747:747] ); -sram6T_blwl sram_blwl_748_ (mux_2level_tapbuf_size16_38_sram_blwl_out[748:748] ,mux_2level_tapbuf_size16_38_sram_blwl_out[748:748] ,mux_2level_tapbuf_size16_38_sram_blwl_outb[748:748] ,mux_2level_tapbuf_size16_38_configbus0[748:748], mux_2level_tapbuf_size16_38_configbus1[748:748] , mux_2level_tapbuf_size16_38_configbus0_b[748:748] ); -sram6T_blwl sram_blwl_749_ (mux_2level_tapbuf_size16_38_sram_blwl_out[749:749] ,mux_2level_tapbuf_size16_38_sram_blwl_out[749:749] ,mux_2level_tapbuf_size16_38_sram_blwl_outb[749:749] ,mux_2level_tapbuf_size16_38_configbus0[749:749], mux_2level_tapbuf_size16_38_configbus1[749:749] , mux_2level_tapbuf_size16_38_configbus0_b[749:749] ); -sram6T_blwl sram_blwl_750_ (mux_2level_tapbuf_size16_38_sram_blwl_out[750:750] ,mux_2level_tapbuf_size16_38_sram_blwl_out[750:750] ,mux_2level_tapbuf_size16_38_sram_blwl_outb[750:750] ,mux_2level_tapbuf_size16_38_configbus0[750:750], mux_2level_tapbuf_size16_38_configbus1[750:750] , mux_2level_tapbuf_size16_38_configbus0_b[750:750] ); -sram6T_blwl sram_blwl_751_ (mux_2level_tapbuf_size16_38_sram_blwl_out[751:751] ,mux_2level_tapbuf_size16_38_sram_blwl_out[751:751] ,mux_2level_tapbuf_size16_38_sram_blwl_outb[751:751] ,mux_2level_tapbuf_size16_38_configbus0[751:751], mux_2level_tapbuf_size16_38_configbus1[751:751] , mux_2level_tapbuf_size16_38_configbus0_b[751:751] ); -wire [0:15] mux_2level_tapbuf_size16_39_inbus; -assign mux_2level_tapbuf_size16_39_inbus[0] = chany_0__1__midout_4_; -assign mux_2level_tapbuf_size16_39_inbus[1] = chany_0__1__midout_5_; -assign mux_2level_tapbuf_size16_39_inbus[2] = chany_0__1__midout_16_; -assign mux_2level_tapbuf_size16_39_inbus[3] = chany_0__1__midout_17_; -assign mux_2level_tapbuf_size16_39_inbus[4] = chany_0__1__midout_28_; -assign mux_2level_tapbuf_size16_39_inbus[5] = chany_0__1__midout_29_; -assign mux_2level_tapbuf_size16_39_inbus[6] = chany_0__1__midout_42_; -assign mux_2level_tapbuf_size16_39_inbus[7] = chany_0__1__midout_43_; -assign mux_2level_tapbuf_size16_39_inbus[8] = chany_0__1__midout_54_; -assign mux_2level_tapbuf_size16_39_inbus[9] = chany_0__1__midout_55_; -assign mux_2level_tapbuf_size16_39_inbus[10] = chany_0__1__midout_66_; -assign mux_2level_tapbuf_size16_39_inbus[11] = chany_0__1__midout_67_; -assign mux_2level_tapbuf_size16_39_inbus[12] = chany_0__1__midout_78_; -assign mux_2level_tapbuf_size16_39_inbus[13] = chany_0__1__midout_79_; -assign mux_2level_tapbuf_size16_39_inbus[14] = chany_0__1__midout_92_; -assign mux_2level_tapbuf_size16_39_inbus[15] = chany_0__1__midout_93_; -wire [752:759] mux_2level_tapbuf_size16_39_configbus0; -wire [752:759] mux_2level_tapbuf_size16_39_configbus1; -wire [752:759] mux_2level_tapbuf_size16_39_sram_blwl_out ; -wire [752:759] mux_2level_tapbuf_size16_39_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_39_configbus0[752:759] = sram_blwl_bl[752:759] ; -assign mux_2level_tapbuf_size16_39_configbus1[752:759] = sram_blwl_wl[752:759] ; -wire [752:759] mux_2level_tapbuf_size16_39_configbus0_b; -assign mux_2level_tapbuf_size16_39_configbus0_b[752:759] = sram_blwl_blb[752:759] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_39_ (mux_2level_tapbuf_size16_39_inbus, grid_1__1__pin_0__3__15_, mux_2level_tapbuf_size16_39_sram_blwl_out[752:759] , -mux_2level_tapbuf_size16_39_sram_blwl_outb[752:759] ); -//----- SRAM bits for MUX[39], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_752_ (mux_2level_tapbuf_size16_39_sram_blwl_out[752:752] ,mux_2level_tapbuf_size16_39_sram_blwl_out[752:752] ,mux_2level_tapbuf_size16_39_sram_blwl_outb[752:752] ,mux_2level_tapbuf_size16_39_configbus0[752:752], mux_2level_tapbuf_size16_39_configbus1[752:752] , mux_2level_tapbuf_size16_39_configbus0_b[752:752] ); -sram6T_blwl sram_blwl_753_ (mux_2level_tapbuf_size16_39_sram_blwl_out[753:753] ,mux_2level_tapbuf_size16_39_sram_blwl_out[753:753] ,mux_2level_tapbuf_size16_39_sram_blwl_outb[753:753] ,mux_2level_tapbuf_size16_39_configbus0[753:753], mux_2level_tapbuf_size16_39_configbus1[753:753] , mux_2level_tapbuf_size16_39_configbus0_b[753:753] ); -sram6T_blwl sram_blwl_754_ (mux_2level_tapbuf_size16_39_sram_blwl_out[754:754] ,mux_2level_tapbuf_size16_39_sram_blwl_out[754:754] ,mux_2level_tapbuf_size16_39_sram_blwl_outb[754:754] ,mux_2level_tapbuf_size16_39_configbus0[754:754], mux_2level_tapbuf_size16_39_configbus1[754:754] , mux_2level_tapbuf_size16_39_configbus0_b[754:754] ); -sram6T_blwl sram_blwl_755_ (mux_2level_tapbuf_size16_39_sram_blwl_out[755:755] ,mux_2level_tapbuf_size16_39_sram_blwl_out[755:755] ,mux_2level_tapbuf_size16_39_sram_blwl_outb[755:755] ,mux_2level_tapbuf_size16_39_configbus0[755:755], mux_2level_tapbuf_size16_39_configbus1[755:755] , mux_2level_tapbuf_size16_39_configbus0_b[755:755] ); -sram6T_blwl sram_blwl_756_ (mux_2level_tapbuf_size16_39_sram_blwl_out[756:756] ,mux_2level_tapbuf_size16_39_sram_blwl_out[756:756] ,mux_2level_tapbuf_size16_39_sram_blwl_outb[756:756] ,mux_2level_tapbuf_size16_39_configbus0[756:756], mux_2level_tapbuf_size16_39_configbus1[756:756] , mux_2level_tapbuf_size16_39_configbus0_b[756:756] ); -sram6T_blwl sram_blwl_757_ (mux_2level_tapbuf_size16_39_sram_blwl_out[757:757] ,mux_2level_tapbuf_size16_39_sram_blwl_out[757:757] ,mux_2level_tapbuf_size16_39_sram_blwl_outb[757:757] ,mux_2level_tapbuf_size16_39_configbus0[757:757], mux_2level_tapbuf_size16_39_configbus1[757:757] , mux_2level_tapbuf_size16_39_configbus0_b[757:757] ); -sram6T_blwl sram_blwl_758_ (mux_2level_tapbuf_size16_39_sram_blwl_out[758:758] ,mux_2level_tapbuf_size16_39_sram_blwl_out[758:758] ,mux_2level_tapbuf_size16_39_sram_blwl_outb[758:758] ,mux_2level_tapbuf_size16_39_configbus0[758:758], mux_2level_tapbuf_size16_39_configbus1[758:758] , mux_2level_tapbuf_size16_39_configbus0_b[758:758] ); -sram6T_blwl sram_blwl_759_ (mux_2level_tapbuf_size16_39_sram_blwl_out[759:759] ,mux_2level_tapbuf_size16_39_sram_blwl_out[759:759] ,mux_2level_tapbuf_size16_39_sram_blwl_outb[759:759] ,mux_2level_tapbuf_size16_39_configbus0[759:759], mux_2level_tapbuf_size16_39_configbus1[759:759] , mux_2level_tapbuf_size16_39_configbus0_b[759:759] ); -wire [0:15] mux_2level_tapbuf_size16_40_inbus; -assign mux_2level_tapbuf_size16_40_inbus[0] = chany_0__1__midout_4_; -assign mux_2level_tapbuf_size16_40_inbus[1] = chany_0__1__midout_5_; -assign mux_2level_tapbuf_size16_40_inbus[2] = chany_0__1__midout_18_; -assign mux_2level_tapbuf_size16_40_inbus[3] = chany_0__1__midout_19_; -assign mux_2level_tapbuf_size16_40_inbus[4] = chany_0__1__midout_30_; -assign mux_2level_tapbuf_size16_40_inbus[5] = chany_0__1__midout_31_; -assign mux_2level_tapbuf_size16_40_inbus[6] = chany_0__1__midout_42_; -assign mux_2level_tapbuf_size16_40_inbus[7] = chany_0__1__midout_43_; -assign mux_2level_tapbuf_size16_40_inbus[8] = chany_0__1__midout_54_; -assign mux_2level_tapbuf_size16_40_inbus[9] = chany_0__1__midout_55_; -assign mux_2level_tapbuf_size16_40_inbus[10] = chany_0__1__midout_68_; -assign mux_2level_tapbuf_size16_40_inbus[11] = chany_0__1__midout_69_; -assign mux_2level_tapbuf_size16_40_inbus[12] = chany_0__1__midout_80_; -assign mux_2level_tapbuf_size16_40_inbus[13] = chany_0__1__midout_81_; -assign mux_2level_tapbuf_size16_40_inbus[14] = chany_0__1__midout_92_; -assign mux_2level_tapbuf_size16_40_inbus[15] = chany_0__1__midout_93_; -wire [760:767] mux_2level_tapbuf_size16_40_configbus0; -wire [760:767] mux_2level_tapbuf_size16_40_configbus1; -wire [760:767] mux_2level_tapbuf_size16_40_sram_blwl_out ; -wire [760:767] mux_2level_tapbuf_size16_40_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_40_configbus0[760:767] = sram_blwl_bl[760:767] ; -assign mux_2level_tapbuf_size16_40_configbus1[760:767] = sram_blwl_wl[760:767] ; -wire [760:767] mux_2level_tapbuf_size16_40_configbus0_b; -assign mux_2level_tapbuf_size16_40_configbus0_b[760:767] = sram_blwl_blb[760:767] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_40_ (mux_2level_tapbuf_size16_40_inbus, grid_1__1__pin_0__3__19_, mux_2level_tapbuf_size16_40_sram_blwl_out[760:767] , -mux_2level_tapbuf_size16_40_sram_blwl_outb[760:767] ); -//----- SRAM bits for MUX[40], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_760_ (mux_2level_tapbuf_size16_40_sram_blwl_out[760:760] ,mux_2level_tapbuf_size16_40_sram_blwl_out[760:760] ,mux_2level_tapbuf_size16_40_sram_blwl_outb[760:760] ,mux_2level_tapbuf_size16_40_configbus0[760:760], mux_2level_tapbuf_size16_40_configbus1[760:760] , mux_2level_tapbuf_size16_40_configbus0_b[760:760] ); -sram6T_blwl sram_blwl_761_ (mux_2level_tapbuf_size16_40_sram_blwl_out[761:761] ,mux_2level_tapbuf_size16_40_sram_blwl_out[761:761] ,mux_2level_tapbuf_size16_40_sram_blwl_outb[761:761] ,mux_2level_tapbuf_size16_40_configbus0[761:761], mux_2level_tapbuf_size16_40_configbus1[761:761] , mux_2level_tapbuf_size16_40_configbus0_b[761:761] ); -sram6T_blwl sram_blwl_762_ (mux_2level_tapbuf_size16_40_sram_blwl_out[762:762] ,mux_2level_tapbuf_size16_40_sram_blwl_out[762:762] ,mux_2level_tapbuf_size16_40_sram_blwl_outb[762:762] ,mux_2level_tapbuf_size16_40_configbus0[762:762], mux_2level_tapbuf_size16_40_configbus1[762:762] , mux_2level_tapbuf_size16_40_configbus0_b[762:762] ); -sram6T_blwl sram_blwl_763_ (mux_2level_tapbuf_size16_40_sram_blwl_out[763:763] ,mux_2level_tapbuf_size16_40_sram_blwl_out[763:763] ,mux_2level_tapbuf_size16_40_sram_blwl_outb[763:763] ,mux_2level_tapbuf_size16_40_configbus0[763:763], mux_2level_tapbuf_size16_40_configbus1[763:763] , mux_2level_tapbuf_size16_40_configbus0_b[763:763] ); -sram6T_blwl sram_blwl_764_ (mux_2level_tapbuf_size16_40_sram_blwl_out[764:764] ,mux_2level_tapbuf_size16_40_sram_blwl_out[764:764] ,mux_2level_tapbuf_size16_40_sram_blwl_outb[764:764] ,mux_2level_tapbuf_size16_40_configbus0[764:764], mux_2level_tapbuf_size16_40_configbus1[764:764] , mux_2level_tapbuf_size16_40_configbus0_b[764:764] ); -sram6T_blwl sram_blwl_765_ (mux_2level_tapbuf_size16_40_sram_blwl_out[765:765] ,mux_2level_tapbuf_size16_40_sram_blwl_out[765:765] ,mux_2level_tapbuf_size16_40_sram_blwl_outb[765:765] ,mux_2level_tapbuf_size16_40_configbus0[765:765], mux_2level_tapbuf_size16_40_configbus1[765:765] , mux_2level_tapbuf_size16_40_configbus0_b[765:765] ); -sram6T_blwl sram_blwl_766_ (mux_2level_tapbuf_size16_40_sram_blwl_out[766:766] ,mux_2level_tapbuf_size16_40_sram_blwl_out[766:766] ,mux_2level_tapbuf_size16_40_sram_blwl_outb[766:766] ,mux_2level_tapbuf_size16_40_configbus0[766:766], mux_2level_tapbuf_size16_40_configbus1[766:766] , mux_2level_tapbuf_size16_40_configbus0_b[766:766] ); -sram6T_blwl sram_blwl_767_ (mux_2level_tapbuf_size16_40_sram_blwl_out[767:767] ,mux_2level_tapbuf_size16_40_sram_blwl_out[767:767] ,mux_2level_tapbuf_size16_40_sram_blwl_outb[767:767] ,mux_2level_tapbuf_size16_40_configbus0[767:767], mux_2level_tapbuf_size16_40_configbus1[767:767] , mux_2level_tapbuf_size16_40_configbus0_b[767:767] ); -wire [0:15] mux_2level_tapbuf_size16_41_inbus; -assign mux_2level_tapbuf_size16_41_inbus[0] = chany_0__1__midout_6_; -assign mux_2level_tapbuf_size16_41_inbus[1] = chany_0__1__midout_7_; -assign mux_2level_tapbuf_size16_41_inbus[2] = chany_0__1__midout_18_; -assign mux_2level_tapbuf_size16_41_inbus[3] = chany_0__1__midout_19_; -assign mux_2level_tapbuf_size16_41_inbus[4] = chany_0__1__midout_32_; -assign mux_2level_tapbuf_size16_41_inbus[5] = chany_0__1__midout_33_; -assign mux_2level_tapbuf_size16_41_inbus[6] = chany_0__1__midout_44_; -assign mux_2level_tapbuf_size16_41_inbus[7] = chany_0__1__midout_45_; -assign mux_2level_tapbuf_size16_41_inbus[8] = chany_0__1__midout_56_; -assign mux_2level_tapbuf_size16_41_inbus[9] = chany_0__1__midout_57_; -assign mux_2level_tapbuf_size16_41_inbus[10] = chany_0__1__midout_68_; -assign mux_2level_tapbuf_size16_41_inbus[11] = chany_0__1__midout_69_; -assign mux_2level_tapbuf_size16_41_inbus[12] = chany_0__1__midout_82_; -assign mux_2level_tapbuf_size16_41_inbus[13] = chany_0__1__midout_83_; -assign mux_2level_tapbuf_size16_41_inbus[14] = chany_0__1__midout_94_; -assign mux_2level_tapbuf_size16_41_inbus[15] = chany_0__1__midout_95_; -wire [768:775] mux_2level_tapbuf_size16_41_configbus0; -wire [768:775] mux_2level_tapbuf_size16_41_configbus1; -wire [768:775] mux_2level_tapbuf_size16_41_sram_blwl_out ; -wire [768:775] mux_2level_tapbuf_size16_41_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_41_configbus0[768:775] = sram_blwl_bl[768:775] ; -assign mux_2level_tapbuf_size16_41_configbus1[768:775] = sram_blwl_wl[768:775] ; -wire [768:775] mux_2level_tapbuf_size16_41_configbus0_b; -assign mux_2level_tapbuf_size16_41_configbus0_b[768:775] = sram_blwl_blb[768:775] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_41_ (mux_2level_tapbuf_size16_41_inbus, grid_1__1__pin_0__3__23_, mux_2level_tapbuf_size16_41_sram_blwl_out[768:775] , -mux_2level_tapbuf_size16_41_sram_blwl_outb[768:775] ); -//----- SRAM bits for MUX[41], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_768_ (mux_2level_tapbuf_size16_41_sram_blwl_out[768:768] ,mux_2level_tapbuf_size16_41_sram_blwl_out[768:768] ,mux_2level_tapbuf_size16_41_sram_blwl_outb[768:768] ,mux_2level_tapbuf_size16_41_configbus0[768:768], mux_2level_tapbuf_size16_41_configbus1[768:768] , mux_2level_tapbuf_size16_41_configbus0_b[768:768] ); -sram6T_blwl sram_blwl_769_ (mux_2level_tapbuf_size16_41_sram_blwl_out[769:769] ,mux_2level_tapbuf_size16_41_sram_blwl_out[769:769] ,mux_2level_tapbuf_size16_41_sram_blwl_outb[769:769] ,mux_2level_tapbuf_size16_41_configbus0[769:769], mux_2level_tapbuf_size16_41_configbus1[769:769] , mux_2level_tapbuf_size16_41_configbus0_b[769:769] ); -sram6T_blwl sram_blwl_770_ (mux_2level_tapbuf_size16_41_sram_blwl_out[770:770] ,mux_2level_tapbuf_size16_41_sram_blwl_out[770:770] ,mux_2level_tapbuf_size16_41_sram_blwl_outb[770:770] ,mux_2level_tapbuf_size16_41_configbus0[770:770], mux_2level_tapbuf_size16_41_configbus1[770:770] , mux_2level_tapbuf_size16_41_configbus0_b[770:770] ); -sram6T_blwl sram_blwl_771_ (mux_2level_tapbuf_size16_41_sram_blwl_out[771:771] ,mux_2level_tapbuf_size16_41_sram_blwl_out[771:771] ,mux_2level_tapbuf_size16_41_sram_blwl_outb[771:771] ,mux_2level_tapbuf_size16_41_configbus0[771:771], mux_2level_tapbuf_size16_41_configbus1[771:771] , mux_2level_tapbuf_size16_41_configbus0_b[771:771] ); -sram6T_blwl sram_blwl_772_ (mux_2level_tapbuf_size16_41_sram_blwl_out[772:772] ,mux_2level_tapbuf_size16_41_sram_blwl_out[772:772] ,mux_2level_tapbuf_size16_41_sram_blwl_outb[772:772] ,mux_2level_tapbuf_size16_41_configbus0[772:772], mux_2level_tapbuf_size16_41_configbus1[772:772] , mux_2level_tapbuf_size16_41_configbus0_b[772:772] ); -sram6T_blwl sram_blwl_773_ (mux_2level_tapbuf_size16_41_sram_blwl_out[773:773] ,mux_2level_tapbuf_size16_41_sram_blwl_out[773:773] ,mux_2level_tapbuf_size16_41_sram_blwl_outb[773:773] ,mux_2level_tapbuf_size16_41_configbus0[773:773], mux_2level_tapbuf_size16_41_configbus1[773:773] , mux_2level_tapbuf_size16_41_configbus0_b[773:773] ); -sram6T_blwl sram_blwl_774_ (mux_2level_tapbuf_size16_41_sram_blwl_out[774:774] ,mux_2level_tapbuf_size16_41_sram_blwl_out[774:774] ,mux_2level_tapbuf_size16_41_sram_blwl_outb[774:774] ,mux_2level_tapbuf_size16_41_configbus0[774:774], mux_2level_tapbuf_size16_41_configbus1[774:774] , mux_2level_tapbuf_size16_41_configbus0_b[774:774] ); -sram6T_blwl sram_blwl_775_ (mux_2level_tapbuf_size16_41_sram_blwl_out[775:775] ,mux_2level_tapbuf_size16_41_sram_blwl_out[775:775] ,mux_2level_tapbuf_size16_41_sram_blwl_outb[775:775] ,mux_2level_tapbuf_size16_41_configbus0[775:775], mux_2level_tapbuf_size16_41_configbus1[775:775] , mux_2level_tapbuf_size16_41_configbus0_b[775:775] ); -wire [0:15] mux_2level_tapbuf_size16_42_inbus; -assign mux_2level_tapbuf_size16_42_inbus[0] = chany_0__1__midout_8_; -assign mux_2level_tapbuf_size16_42_inbus[1] = chany_0__1__midout_9_; -assign mux_2level_tapbuf_size16_42_inbus[2] = chany_0__1__midout_20_; -assign mux_2level_tapbuf_size16_42_inbus[3] = chany_0__1__midout_21_; -assign mux_2level_tapbuf_size16_42_inbus[4] = chany_0__1__midout_32_; -assign mux_2level_tapbuf_size16_42_inbus[5] = chany_0__1__midout_33_; -assign mux_2level_tapbuf_size16_42_inbus[6] = chany_0__1__midout_44_; -assign mux_2level_tapbuf_size16_42_inbus[7] = chany_0__1__midout_45_; -assign mux_2level_tapbuf_size16_42_inbus[8] = chany_0__1__midout_58_; -assign mux_2level_tapbuf_size16_42_inbus[9] = chany_0__1__midout_59_; -assign mux_2level_tapbuf_size16_42_inbus[10] = chany_0__1__midout_70_; -assign mux_2level_tapbuf_size16_42_inbus[11] = chany_0__1__midout_71_; -assign mux_2level_tapbuf_size16_42_inbus[12] = chany_0__1__midout_82_; -assign mux_2level_tapbuf_size16_42_inbus[13] = chany_0__1__midout_83_; -assign mux_2level_tapbuf_size16_42_inbus[14] = chany_0__1__midout_94_; -assign mux_2level_tapbuf_size16_42_inbus[15] = chany_0__1__midout_95_; -wire [776:783] mux_2level_tapbuf_size16_42_configbus0; -wire [776:783] mux_2level_tapbuf_size16_42_configbus1; -wire [776:783] mux_2level_tapbuf_size16_42_sram_blwl_out ; -wire [776:783] mux_2level_tapbuf_size16_42_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_42_configbus0[776:783] = sram_blwl_bl[776:783] ; -assign mux_2level_tapbuf_size16_42_configbus1[776:783] = sram_blwl_wl[776:783] ; -wire [776:783] mux_2level_tapbuf_size16_42_configbus0_b; -assign mux_2level_tapbuf_size16_42_configbus0_b[776:783] = sram_blwl_blb[776:783] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_42_ (mux_2level_tapbuf_size16_42_inbus, grid_1__1__pin_0__3__27_, mux_2level_tapbuf_size16_42_sram_blwl_out[776:783] , -mux_2level_tapbuf_size16_42_sram_blwl_outb[776:783] ); -//----- SRAM bits for MUX[42], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_776_ (mux_2level_tapbuf_size16_42_sram_blwl_out[776:776] ,mux_2level_tapbuf_size16_42_sram_blwl_out[776:776] ,mux_2level_tapbuf_size16_42_sram_blwl_outb[776:776] ,mux_2level_tapbuf_size16_42_configbus0[776:776], mux_2level_tapbuf_size16_42_configbus1[776:776] , mux_2level_tapbuf_size16_42_configbus0_b[776:776] ); -sram6T_blwl sram_blwl_777_ (mux_2level_tapbuf_size16_42_sram_blwl_out[777:777] ,mux_2level_tapbuf_size16_42_sram_blwl_out[777:777] ,mux_2level_tapbuf_size16_42_sram_blwl_outb[777:777] ,mux_2level_tapbuf_size16_42_configbus0[777:777], mux_2level_tapbuf_size16_42_configbus1[777:777] , mux_2level_tapbuf_size16_42_configbus0_b[777:777] ); -sram6T_blwl sram_blwl_778_ (mux_2level_tapbuf_size16_42_sram_blwl_out[778:778] ,mux_2level_tapbuf_size16_42_sram_blwl_out[778:778] ,mux_2level_tapbuf_size16_42_sram_blwl_outb[778:778] ,mux_2level_tapbuf_size16_42_configbus0[778:778], mux_2level_tapbuf_size16_42_configbus1[778:778] , mux_2level_tapbuf_size16_42_configbus0_b[778:778] ); -sram6T_blwl sram_blwl_779_ (mux_2level_tapbuf_size16_42_sram_blwl_out[779:779] ,mux_2level_tapbuf_size16_42_sram_blwl_out[779:779] ,mux_2level_tapbuf_size16_42_sram_blwl_outb[779:779] ,mux_2level_tapbuf_size16_42_configbus0[779:779], mux_2level_tapbuf_size16_42_configbus1[779:779] , mux_2level_tapbuf_size16_42_configbus0_b[779:779] ); -sram6T_blwl sram_blwl_780_ (mux_2level_tapbuf_size16_42_sram_blwl_out[780:780] ,mux_2level_tapbuf_size16_42_sram_blwl_out[780:780] ,mux_2level_tapbuf_size16_42_sram_blwl_outb[780:780] ,mux_2level_tapbuf_size16_42_configbus0[780:780], mux_2level_tapbuf_size16_42_configbus1[780:780] , mux_2level_tapbuf_size16_42_configbus0_b[780:780] ); -sram6T_blwl sram_blwl_781_ (mux_2level_tapbuf_size16_42_sram_blwl_out[781:781] ,mux_2level_tapbuf_size16_42_sram_blwl_out[781:781] ,mux_2level_tapbuf_size16_42_sram_blwl_outb[781:781] ,mux_2level_tapbuf_size16_42_configbus0[781:781], mux_2level_tapbuf_size16_42_configbus1[781:781] , mux_2level_tapbuf_size16_42_configbus0_b[781:781] ); -sram6T_blwl sram_blwl_782_ (mux_2level_tapbuf_size16_42_sram_blwl_out[782:782] ,mux_2level_tapbuf_size16_42_sram_blwl_out[782:782] ,mux_2level_tapbuf_size16_42_sram_blwl_outb[782:782] ,mux_2level_tapbuf_size16_42_configbus0[782:782], mux_2level_tapbuf_size16_42_configbus1[782:782] , mux_2level_tapbuf_size16_42_configbus0_b[782:782] ); -sram6T_blwl sram_blwl_783_ (mux_2level_tapbuf_size16_42_sram_blwl_out[783:783] ,mux_2level_tapbuf_size16_42_sram_blwl_out[783:783] ,mux_2level_tapbuf_size16_42_sram_blwl_outb[783:783] ,mux_2level_tapbuf_size16_42_configbus0[783:783], mux_2level_tapbuf_size16_42_configbus1[783:783] , mux_2level_tapbuf_size16_42_configbus0_b[783:783] ); -wire [0:15] mux_2level_tapbuf_size16_43_inbus; -assign mux_2level_tapbuf_size16_43_inbus[0] = chany_0__1__midout_8_; -assign mux_2level_tapbuf_size16_43_inbus[1] = chany_0__1__midout_9_; -assign mux_2level_tapbuf_size16_43_inbus[2] = chany_0__1__midout_22_; -assign mux_2level_tapbuf_size16_43_inbus[3] = chany_0__1__midout_23_; -assign mux_2level_tapbuf_size16_43_inbus[4] = chany_0__1__midout_34_; -assign mux_2level_tapbuf_size16_43_inbus[5] = chany_0__1__midout_35_; -assign mux_2level_tapbuf_size16_43_inbus[6] = chany_0__1__midout_46_; -assign mux_2level_tapbuf_size16_43_inbus[7] = chany_0__1__midout_47_; -assign mux_2level_tapbuf_size16_43_inbus[8] = chany_0__1__midout_58_; -assign mux_2level_tapbuf_size16_43_inbus[9] = chany_0__1__midout_59_; -assign mux_2level_tapbuf_size16_43_inbus[10] = chany_0__1__midout_72_; -assign mux_2level_tapbuf_size16_43_inbus[11] = chany_0__1__midout_73_; -assign mux_2level_tapbuf_size16_43_inbus[12] = chany_0__1__midout_84_; -assign mux_2level_tapbuf_size16_43_inbus[13] = chany_0__1__midout_85_; -assign mux_2level_tapbuf_size16_43_inbus[14] = chany_0__1__midout_96_; -assign mux_2level_tapbuf_size16_43_inbus[15] = chany_0__1__midout_97_; -wire [784:791] mux_2level_tapbuf_size16_43_configbus0; -wire [784:791] mux_2level_tapbuf_size16_43_configbus1; -wire [784:791] mux_2level_tapbuf_size16_43_sram_blwl_out ; -wire [784:791] mux_2level_tapbuf_size16_43_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_43_configbus0[784:791] = sram_blwl_bl[784:791] ; -assign mux_2level_tapbuf_size16_43_configbus1[784:791] = sram_blwl_wl[784:791] ; -wire [784:791] mux_2level_tapbuf_size16_43_configbus0_b; -assign mux_2level_tapbuf_size16_43_configbus0_b[784:791] = sram_blwl_blb[784:791] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_43_ (mux_2level_tapbuf_size16_43_inbus, grid_1__1__pin_0__3__31_, mux_2level_tapbuf_size16_43_sram_blwl_out[784:791] , -mux_2level_tapbuf_size16_43_sram_blwl_outb[784:791] ); -//----- SRAM bits for MUX[43], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_784_ (mux_2level_tapbuf_size16_43_sram_blwl_out[784:784] ,mux_2level_tapbuf_size16_43_sram_blwl_out[784:784] ,mux_2level_tapbuf_size16_43_sram_blwl_outb[784:784] ,mux_2level_tapbuf_size16_43_configbus0[784:784], mux_2level_tapbuf_size16_43_configbus1[784:784] , mux_2level_tapbuf_size16_43_configbus0_b[784:784] ); -sram6T_blwl sram_blwl_785_ (mux_2level_tapbuf_size16_43_sram_blwl_out[785:785] ,mux_2level_tapbuf_size16_43_sram_blwl_out[785:785] ,mux_2level_tapbuf_size16_43_sram_blwl_outb[785:785] ,mux_2level_tapbuf_size16_43_configbus0[785:785], mux_2level_tapbuf_size16_43_configbus1[785:785] , mux_2level_tapbuf_size16_43_configbus0_b[785:785] ); -sram6T_blwl sram_blwl_786_ (mux_2level_tapbuf_size16_43_sram_blwl_out[786:786] ,mux_2level_tapbuf_size16_43_sram_blwl_out[786:786] ,mux_2level_tapbuf_size16_43_sram_blwl_outb[786:786] ,mux_2level_tapbuf_size16_43_configbus0[786:786], mux_2level_tapbuf_size16_43_configbus1[786:786] , mux_2level_tapbuf_size16_43_configbus0_b[786:786] ); -sram6T_blwl sram_blwl_787_ (mux_2level_tapbuf_size16_43_sram_blwl_out[787:787] ,mux_2level_tapbuf_size16_43_sram_blwl_out[787:787] ,mux_2level_tapbuf_size16_43_sram_blwl_outb[787:787] ,mux_2level_tapbuf_size16_43_configbus0[787:787], mux_2level_tapbuf_size16_43_configbus1[787:787] , mux_2level_tapbuf_size16_43_configbus0_b[787:787] ); -sram6T_blwl sram_blwl_788_ (mux_2level_tapbuf_size16_43_sram_blwl_out[788:788] ,mux_2level_tapbuf_size16_43_sram_blwl_out[788:788] ,mux_2level_tapbuf_size16_43_sram_blwl_outb[788:788] ,mux_2level_tapbuf_size16_43_configbus0[788:788], mux_2level_tapbuf_size16_43_configbus1[788:788] , mux_2level_tapbuf_size16_43_configbus0_b[788:788] ); -sram6T_blwl sram_blwl_789_ (mux_2level_tapbuf_size16_43_sram_blwl_out[789:789] ,mux_2level_tapbuf_size16_43_sram_blwl_out[789:789] ,mux_2level_tapbuf_size16_43_sram_blwl_outb[789:789] ,mux_2level_tapbuf_size16_43_configbus0[789:789], mux_2level_tapbuf_size16_43_configbus1[789:789] , mux_2level_tapbuf_size16_43_configbus0_b[789:789] ); -sram6T_blwl sram_blwl_790_ (mux_2level_tapbuf_size16_43_sram_blwl_out[790:790] ,mux_2level_tapbuf_size16_43_sram_blwl_out[790:790] ,mux_2level_tapbuf_size16_43_sram_blwl_outb[790:790] ,mux_2level_tapbuf_size16_43_configbus0[790:790], mux_2level_tapbuf_size16_43_configbus1[790:790] , mux_2level_tapbuf_size16_43_configbus0_b[790:790] ); -sram6T_blwl sram_blwl_791_ (mux_2level_tapbuf_size16_43_sram_blwl_out[791:791] ,mux_2level_tapbuf_size16_43_sram_blwl_out[791:791] ,mux_2level_tapbuf_size16_43_sram_blwl_outb[791:791] ,mux_2level_tapbuf_size16_43_configbus0[791:791], mux_2level_tapbuf_size16_43_configbus1[791:791] , mux_2level_tapbuf_size16_43_configbus0_b[791:791] ); -wire [0:15] mux_2level_tapbuf_size16_44_inbus; -assign mux_2level_tapbuf_size16_44_inbus[0] = chany_0__1__midout_10_; -assign mux_2level_tapbuf_size16_44_inbus[1] = chany_0__1__midout_11_; -assign mux_2level_tapbuf_size16_44_inbus[2] = chany_0__1__midout_22_; -assign mux_2level_tapbuf_size16_44_inbus[3] = chany_0__1__midout_23_; -assign mux_2level_tapbuf_size16_44_inbus[4] = chany_0__1__midout_34_; -assign mux_2level_tapbuf_size16_44_inbus[5] = chany_0__1__midout_35_; -assign mux_2level_tapbuf_size16_44_inbus[6] = chany_0__1__midout_48_; -assign mux_2level_tapbuf_size16_44_inbus[7] = chany_0__1__midout_49_; -assign mux_2level_tapbuf_size16_44_inbus[8] = chany_0__1__midout_60_; -assign mux_2level_tapbuf_size16_44_inbus[9] = chany_0__1__midout_61_; -assign mux_2level_tapbuf_size16_44_inbus[10] = chany_0__1__midout_72_; -assign mux_2level_tapbuf_size16_44_inbus[11] = chany_0__1__midout_73_; -assign mux_2level_tapbuf_size16_44_inbus[12] = chany_0__1__midout_84_; -assign mux_2level_tapbuf_size16_44_inbus[13] = chany_0__1__midout_85_; -assign mux_2level_tapbuf_size16_44_inbus[14] = chany_0__1__midout_98_; -assign mux_2level_tapbuf_size16_44_inbus[15] = chany_0__1__midout_99_; -wire [792:799] mux_2level_tapbuf_size16_44_configbus0; -wire [792:799] mux_2level_tapbuf_size16_44_configbus1; -wire [792:799] mux_2level_tapbuf_size16_44_sram_blwl_out ; -wire [792:799] mux_2level_tapbuf_size16_44_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_44_configbus0[792:799] = sram_blwl_bl[792:799] ; -assign mux_2level_tapbuf_size16_44_configbus1[792:799] = sram_blwl_wl[792:799] ; -wire [792:799] mux_2level_tapbuf_size16_44_configbus0_b; -assign mux_2level_tapbuf_size16_44_configbus0_b[792:799] = sram_blwl_blb[792:799] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_44_ (mux_2level_tapbuf_size16_44_inbus, grid_1__1__pin_0__3__35_, mux_2level_tapbuf_size16_44_sram_blwl_out[792:799] , -mux_2level_tapbuf_size16_44_sram_blwl_outb[792:799] ); -//----- SRAM bits for MUX[44], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_792_ (mux_2level_tapbuf_size16_44_sram_blwl_out[792:792] ,mux_2level_tapbuf_size16_44_sram_blwl_out[792:792] ,mux_2level_tapbuf_size16_44_sram_blwl_outb[792:792] ,mux_2level_tapbuf_size16_44_configbus0[792:792], mux_2level_tapbuf_size16_44_configbus1[792:792] , mux_2level_tapbuf_size16_44_configbus0_b[792:792] ); -sram6T_blwl sram_blwl_793_ (mux_2level_tapbuf_size16_44_sram_blwl_out[793:793] ,mux_2level_tapbuf_size16_44_sram_blwl_out[793:793] ,mux_2level_tapbuf_size16_44_sram_blwl_outb[793:793] ,mux_2level_tapbuf_size16_44_configbus0[793:793], mux_2level_tapbuf_size16_44_configbus1[793:793] , mux_2level_tapbuf_size16_44_configbus0_b[793:793] ); -sram6T_blwl sram_blwl_794_ (mux_2level_tapbuf_size16_44_sram_blwl_out[794:794] ,mux_2level_tapbuf_size16_44_sram_blwl_out[794:794] ,mux_2level_tapbuf_size16_44_sram_blwl_outb[794:794] ,mux_2level_tapbuf_size16_44_configbus0[794:794], mux_2level_tapbuf_size16_44_configbus1[794:794] , mux_2level_tapbuf_size16_44_configbus0_b[794:794] ); -sram6T_blwl sram_blwl_795_ (mux_2level_tapbuf_size16_44_sram_blwl_out[795:795] ,mux_2level_tapbuf_size16_44_sram_blwl_out[795:795] ,mux_2level_tapbuf_size16_44_sram_blwl_outb[795:795] ,mux_2level_tapbuf_size16_44_configbus0[795:795], mux_2level_tapbuf_size16_44_configbus1[795:795] , mux_2level_tapbuf_size16_44_configbus0_b[795:795] ); -sram6T_blwl sram_blwl_796_ (mux_2level_tapbuf_size16_44_sram_blwl_out[796:796] ,mux_2level_tapbuf_size16_44_sram_blwl_out[796:796] ,mux_2level_tapbuf_size16_44_sram_blwl_outb[796:796] ,mux_2level_tapbuf_size16_44_configbus0[796:796], mux_2level_tapbuf_size16_44_configbus1[796:796] , mux_2level_tapbuf_size16_44_configbus0_b[796:796] ); -sram6T_blwl sram_blwl_797_ (mux_2level_tapbuf_size16_44_sram_blwl_out[797:797] ,mux_2level_tapbuf_size16_44_sram_blwl_out[797:797] ,mux_2level_tapbuf_size16_44_sram_blwl_outb[797:797] ,mux_2level_tapbuf_size16_44_configbus0[797:797], mux_2level_tapbuf_size16_44_configbus1[797:797] , mux_2level_tapbuf_size16_44_configbus0_b[797:797] ); -sram6T_blwl sram_blwl_798_ (mux_2level_tapbuf_size16_44_sram_blwl_out[798:798] ,mux_2level_tapbuf_size16_44_sram_blwl_out[798:798] ,mux_2level_tapbuf_size16_44_sram_blwl_outb[798:798] ,mux_2level_tapbuf_size16_44_configbus0[798:798], mux_2level_tapbuf_size16_44_configbus1[798:798] , mux_2level_tapbuf_size16_44_configbus0_b[798:798] ); -sram6T_blwl sram_blwl_799_ (mux_2level_tapbuf_size16_44_sram_blwl_out[799:799] ,mux_2level_tapbuf_size16_44_sram_blwl_out[799:799] ,mux_2level_tapbuf_size16_44_sram_blwl_outb[799:799] ,mux_2level_tapbuf_size16_44_configbus0[799:799], mux_2level_tapbuf_size16_44_configbus1[799:799] , mux_2level_tapbuf_size16_44_configbus0_b[799:799] ); -wire [0:15] mux_2level_tapbuf_size16_45_inbus; -assign mux_2level_tapbuf_size16_45_inbus[0] = chany_0__1__midout_12_; -assign mux_2level_tapbuf_size16_45_inbus[1] = chany_0__1__midout_13_; -assign mux_2level_tapbuf_size16_45_inbus[2] = chany_0__1__midout_24_; -assign mux_2level_tapbuf_size16_45_inbus[3] = chany_0__1__midout_25_; -assign mux_2level_tapbuf_size16_45_inbus[4] = chany_0__1__midout_36_; -assign mux_2level_tapbuf_size16_45_inbus[5] = chany_0__1__midout_37_; -assign mux_2level_tapbuf_size16_45_inbus[6] = chany_0__1__midout_48_; -assign mux_2level_tapbuf_size16_45_inbus[7] = chany_0__1__midout_49_; -assign mux_2level_tapbuf_size16_45_inbus[8] = chany_0__1__midout_62_; -assign mux_2level_tapbuf_size16_45_inbus[9] = chany_0__1__midout_63_; -assign mux_2level_tapbuf_size16_45_inbus[10] = chany_0__1__midout_74_; -assign mux_2level_tapbuf_size16_45_inbus[11] = chany_0__1__midout_75_; -assign mux_2level_tapbuf_size16_45_inbus[12] = chany_0__1__midout_86_; -assign mux_2level_tapbuf_size16_45_inbus[13] = chany_0__1__midout_87_; -assign mux_2level_tapbuf_size16_45_inbus[14] = chany_0__1__midout_98_; -assign mux_2level_tapbuf_size16_45_inbus[15] = chany_0__1__midout_99_; -wire [800:807] mux_2level_tapbuf_size16_45_configbus0; -wire [800:807] mux_2level_tapbuf_size16_45_configbus1; -wire [800:807] mux_2level_tapbuf_size16_45_sram_blwl_out ; -wire [800:807] mux_2level_tapbuf_size16_45_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_45_configbus0[800:807] = sram_blwl_bl[800:807] ; -assign mux_2level_tapbuf_size16_45_configbus1[800:807] = sram_blwl_wl[800:807] ; -wire [800:807] mux_2level_tapbuf_size16_45_configbus0_b; -assign mux_2level_tapbuf_size16_45_configbus0_b[800:807] = sram_blwl_blb[800:807] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_45_ (mux_2level_tapbuf_size16_45_inbus, grid_1__1__pin_0__3__39_, mux_2level_tapbuf_size16_45_sram_blwl_out[800:807] , -mux_2level_tapbuf_size16_45_sram_blwl_outb[800:807] ); -//----- SRAM bits for MUX[45], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_800_ (mux_2level_tapbuf_size16_45_sram_blwl_out[800:800] ,mux_2level_tapbuf_size16_45_sram_blwl_out[800:800] ,mux_2level_tapbuf_size16_45_sram_blwl_outb[800:800] ,mux_2level_tapbuf_size16_45_configbus0[800:800], mux_2level_tapbuf_size16_45_configbus1[800:800] , mux_2level_tapbuf_size16_45_configbus0_b[800:800] ); -sram6T_blwl sram_blwl_801_ (mux_2level_tapbuf_size16_45_sram_blwl_out[801:801] ,mux_2level_tapbuf_size16_45_sram_blwl_out[801:801] ,mux_2level_tapbuf_size16_45_sram_blwl_outb[801:801] ,mux_2level_tapbuf_size16_45_configbus0[801:801], mux_2level_tapbuf_size16_45_configbus1[801:801] , mux_2level_tapbuf_size16_45_configbus0_b[801:801] ); -sram6T_blwl sram_blwl_802_ (mux_2level_tapbuf_size16_45_sram_blwl_out[802:802] ,mux_2level_tapbuf_size16_45_sram_blwl_out[802:802] ,mux_2level_tapbuf_size16_45_sram_blwl_outb[802:802] ,mux_2level_tapbuf_size16_45_configbus0[802:802], mux_2level_tapbuf_size16_45_configbus1[802:802] , mux_2level_tapbuf_size16_45_configbus0_b[802:802] ); -sram6T_blwl sram_blwl_803_ (mux_2level_tapbuf_size16_45_sram_blwl_out[803:803] ,mux_2level_tapbuf_size16_45_sram_blwl_out[803:803] ,mux_2level_tapbuf_size16_45_sram_blwl_outb[803:803] ,mux_2level_tapbuf_size16_45_configbus0[803:803], mux_2level_tapbuf_size16_45_configbus1[803:803] , mux_2level_tapbuf_size16_45_configbus0_b[803:803] ); -sram6T_blwl sram_blwl_804_ (mux_2level_tapbuf_size16_45_sram_blwl_out[804:804] ,mux_2level_tapbuf_size16_45_sram_blwl_out[804:804] ,mux_2level_tapbuf_size16_45_sram_blwl_outb[804:804] ,mux_2level_tapbuf_size16_45_configbus0[804:804], mux_2level_tapbuf_size16_45_configbus1[804:804] , mux_2level_tapbuf_size16_45_configbus0_b[804:804] ); -sram6T_blwl sram_blwl_805_ (mux_2level_tapbuf_size16_45_sram_blwl_out[805:805] ,mux_2level_tapbuf_size16_45_sram_blwl_out[805:805] ,mux_2level_tapbuf_size16_45_sram_blwl_outb[805:805] ,mux_2level_tapbuf_size16_45_configbus0[805:805], mux_2level_tapbuf_size16_45_configbus1[805:805] , mux_2level_tapbuf_size16_45_configbus0_b[805:805] ); -sram6T_blwl sram_blwl_806_ (mux_2level_tapbuf_size16_45_sram_blwl_out[806:806] ,mux_2level_tapbuf_size16_45_sram_blwl_out[806:806] ,mux_2level_tapbuf_size16_45_sram_blwl_outb[806:806] ,mux_2level_tapbuf_size16_45_configbus0[806:806], mux_2level_tapbuf_size16_45_configbus1[806:806] , mux_2level_tapbuf_size16_45_configbus0_b[806:806] ); -sram6T_blwl sram_blwl_807_ (mux_2level_tapbuf_size16_45_sram_blwl_out[807:807] ,mux_2level_tapbuf_size16_45_sram_blwl_out[807:807] ,mux_2level_tapbuf_size16_45_sram_blwl_outb[807:807] ,mux_2level_tapbuf_size16_45_configbus0[807:807], mux_2level_tapbuf_size16_45_configbus1[807:807] , mux_2level_tapbuf_size16_45_configbus0_b[807:807] ); -wire [0:15] mux_2level_tapbuf_size16_46_inbus; -assign mux_2level_tapbuf_size16_46_inbus[0] = chany_0__1__midout_0_; -assign mux_2level_tapbuf_size16_46_inbus[1] = chany_0__1__midout_1_; -assign mux_2level_tapbuf_size16_46_inbus[2] = chany_0__1__midout_12_; -assign mux_2level_tapbuf_size16_46_inbus[3] = chany_0__1__midout_13_; -assign mux_2level_tapbuf_size16_46_inbus[4] = chany_0__1__midout_24_; -assign mux_2level_tapbuf_size16_46_inbus[5] = chany_0__1__midout_25_; -assign mux_2level_tapbuf_size16_46_inbus[6] = chany_0__1__midout_36_; -assign mux_2level_tapbuf_size16_46_inbus[7] = chany_0__1__midout_37_; -assign mux_2level_tapbuf_size16_46_inbus[8] = chany_0__1__midout_50_; -assign mux_2level_tapbuf_size16_46_inbus[9] = chany_0__1__midout_51_; -assign mux_2level_tapbuf_size16_46_inbus[10] = chany_0__1__midout_62_; -assign mux_2level_tapbuf_size16_46_inbus[11] = chany_0__1__midout_63_; -assign mux_2level_tapbuf_size16_46_inbus[12] = chany_0__1__midout_74_; -assign mux_2level_tapbuf_size16_46_inbus[13] = chany_0__1__midout_75_; -assign mux_2level_tapbuf_size16_46_inbus[14] = chany_0__1__midout_86_; -assign mux_2level_tapbuf_size16_46_inbus[15] = chany_0__1__midout_87_; -wire [808:815] mux_2level_tapbuf_size16_46_configbus0; -wire [808:815] mux_2level_tapbuf_size16_46_configbus1; -wire [808:815] mux_2level_tapbuf_size16_46_sram_blwl_out ; -wire [808:815] mux_2level_tapbuf_size16_46_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_46_configbus0[808:815] = sram_blwl_bl[808:815] ; -assign mux_2level_tapbuf_size16_46_configbus1[808:815] = sram_blwl_wl[808:815] ; -wire [808:815] mux_2level_tapbuf_size16_46_configbus0_b; -assign mux_2level_tapbuf_size16_46_configbus0_b[808:815] = sram_blwl_blb[808:815] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_46_ (mux_2level_tapbuf_size16_46_inbus, grid_0__1__pin_0__1__0_, mux_2level_tapbuf_size16_46_sram_blwl_out[808:815] , -mux_2level_tapbuf_size16_46_sram_blwl_outb[808:815] ); -//----- SRAM bits for MUX[46], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_808_ (mux_2level_tapbuf_size16_46_sram_blwl_out[808:808] ,mux_2level_tapbuf_size16_46_sram_blwl_out[808:808] ,mux_2level_tapbuf_size16_46_sram_blwl_outb[808:808] ,mux_2level_tapbuf_size16_46_configbus0[808:808], mux_2level_tapbuf_size16_46_configbus1[808:808] , mux_2level_tapbuf_size16_46_configbus0_b[808:808] ); -sram6T_blwl sram_blwl_809_ (mux_2level_tapbuf_size16_46_sram_blwl_out[809:809] ,mux_2level_tapbuf_size16_46_sram_blwl_out[809:809] ,mux_2level_tapbuf_size16_46_sram_blwl_outb[809:809] ,mux_2level_tapbuf_size16_46_configbus0[809:809], mux_2level_tapbuf_size16_46_configbus1[809:809] , mux_2level_tapbuf_size16_46_configbus0_b[809:809] ); -sram6T_blwl sram_blwl_810_ (mux_2level_tapbuf_size16_46_sram_blwl_out[810:810] ,mux_2level_tapbuf_size16_46_sram_blwl_out[810:810] ,mux_2level_tapbuf_size16_46_sram_blwl_outb[810:810] ,mux_2level_tapbuf_size16_46_configbus0[810:810], mux_2level_tapbuf_size16_46_configbus1[810:810] , mux_2level_tapbuf_size16_46_configbus0_b[810:810] ); -sram6T_blwl sram_blwl_811_ (mux_2level_tapbuf_size16_46_sram_blwl_out[811:811] ,mux_2level_tapbuf_size16_46_sram_blwl_out[811:811] ,mux_2level_tapbuf_size16_46_sram_blwl_outb[811:811] ,mux_2level_tapbuf_size16_46_configbus0[811:811], mux_2level_tapbuf_size16_46_configbus1[811:811] , mux_2level_tapbuf_size16_46_configbus0_b[811:811] ); -sram6T_blwl sram_blwl_812_ (mux_2level_tapbuf_size16_46_sram_blwl_out[812:812] ,mux_2level_tapbuf_size16_46_sram_blwl_out[812:812] ,mux_2level_tapbuf_size16_46_sram_blwl_outb[812:812] ,mux_2level_tapbuf_size16_46_configbus0[812:812], mux_2level_tapbuf_size16_46_configbus1[812:812] , mux_2level_tapbuf_size16_46_configbus0_b[812:812] ); -sram6T_blwl sram_blwl_813_ (mux_2level_tapbuf_size16_46_sram_blwl_out[813:813] ,mux_2level_tapbuf_size16_46_sram_blwl_out[813:813] ,mux_2level_tapbuf_size16_46_sram_blwl_outb[813:813] ,mux_2level_tapbuf_size16_46_configbus0[813:813], mux_2level_tapbuf_size16_46_configbus1[813:813] , mux_2level_tapbuf_size16_46_configbus0_b[813:813] ); -sram6T_blwl sram_blwl_814_ (mux_2level_tapbuf_size16_46_sram_blwl_out[814:814] ,mux_2level_tapbuf_size16_46_sram_blwl_out[814:814] ,mux_2level_tapbuf_size16_46_sram_blwl_outb[814:814] ,mux_2level_tapbuf_size16_46_configbus0[814:814], mux_2level_tapbuf_size16_46_configbus1[814:814] , mux_2level_tapbuf_size16_46_configbus0_b[814:814] ); -sram6T_blwl sram_blwl_815_ (mux_2level_tapbuf_size16_46_sram_blwl_out[815:815] ,mux_2level_tapbuf_size16_46_sram_blwl_out[815:815] ,mux_2level_tapbuf_size16_46_sram_blwl_outb[815:815] ,mux_2level_tapbuf_size16_46_configbus0[815:815], mux_2level_tapbuf_size16_46_configbus1[815:815] , mux_2level_tapbuf_size16_46_configbus0_b[815:815] ); -wire [0:15] mux_2level_tapbuf_size16_47_inbus; -assign mux_2level_tapbuf_size16_47_inbus[0] = chany_0__1__midout_0_; -assign mux_2level_tapbuf_size16_47_inbus[1] = chany_0__1__midout_1_; -assign mux_2level_tapbuf_size16_47_inbus[2] = chany_0__1__midout_14_; -assign mux_2level_tapbuf_size16_47_inbus[3] = chany_0__1__midout_15_; -assign mux_2level_tapbuf_size16_47_inbus[4] = chany_0__1__midout_26_; -assign mux_2level_tapbuf_size16_47_inbus[5] = chany_0__1__midout_27_; -assign mux_2level_tapbuf_size16_47_inbus[6] = chany_0__1__midout_38_; -assign mux_2level_tapbuf_size16_47_inbus[7] = chany_0__1__midout_39_; -assign mux_2level_tapbuf_size16_47_inbus[8] = chany_0__1__midout_50_; -assign mux_2level_tapbuf_size16_47_inbus[9] = chany_0__1__midout_51_; -assign mux_2level_tapbuf_size16_47_inbus[10] = chany_0__1__midout_64_; -assign mux_2level_tapbuf_size16_47_inbus[11] = chany_0__1__midout_65_; -assign mux_2level_tapbuf_size16_47_inbus[12] = chany_0__1__midout_76_; -assign mux_2level_tapbuf_size16_47_inbus[13] = chany_0__1__midout_77_; -assign mux_2level_tapbuf_size16_47_inbus[14] = chany_0__1__midout_88_; -assign mux_2level_tapbuf_size16_47_inbus[15] = chany_0__1__midout_89_; -wire [816:823] mux_2level_tapbuf_size16_47_configbus0; -wire [816:823] mux_2level_tapbuf_size16_47_configbus1; -wire [816:823] mux_2level_tapbuf_size16_47_sram_blwl_out ; -wire [816:823] mux_2level_tapbuf_size16_47_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_47_configbus0[816:823] = sram_blwl_bl[816:823] ; -assign mux_2level_tapbuf_size16_47_configbus1[816:823] = sram_blwl_wl[816:823] ; -wire [816:823] mux_2level_tapbuf_size16_47_configbus0_b; -assign mux_2level_tapbuf_size16_47_configbus0_b[816:823] = sram_blwl_blb[816:823] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_47_ (mux_2level_tapbuf_size16_47_inbus, grid_0__1__pin_0__1__2_, mux_2level_tapbuf_size16_47_sram_blwl_out[816:823] , -mux_2level_tapbuf_size16_47_sram_blwl_outb[816:823] ); -//----- SRAM bits for MUX[47], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_816_ (mux_2level_tapbuf_size16_47_sram_blwl_out[816:816] ,mux_2level_tapbuf_size16_47_sram_blwl_out[816:816] ,mux_2level_tapbuf_size16_47_sram_blwl_outb[816:816] ,mux_2level_tapbuf_size16_47_configbus0[816:816], mux_2level_tapbuf_size16_47_configbus1[816:816] , mux_2level_tapbuf_size16_47_configbus0_b[816:816] ); -sram6T_blwl sram_blwl_817_ (mux_2level_tapbuf_size16_47_sram_blwl_out[817:817] ,mux_2level_tapbuf_size16_47_sram_blwl_out[817:817] ,mux_2level_tapbuf_size16_47_sram_blwl_outb[817:817] ,mux_2level_tapbuf_size16_47_configbus0[817:817], mux_2level_tapbuf_size16_47_configbus1[817:817] , mux_2level_tapbuf_size16_47_configbus0_b[817:817] ); -sram6T_blwl sram_blwl_818_ (mux_2level_tapbuf_size16_47_sram_blwl_out[818:818] ,mux_2level_tapbuf_size16_47_sram_blwl_out[818:818] ,mux_2level_tapbuf_size16_47_sram_blwl_outb[818:818] ,mux_2level_tapbuf_size16_47_configbus0[818:818], mux_2level_tapbuf_size16_47_configbus1[818:818] , mux_2level_tapbuf_size16_47_configbus0_b[818:818] ); -sram6T_blwl sram_blwl_819_ (mux_2level_tapbuf_size16_47_sram_blwl_out[819:819] ,mux_2level_tapbuf_size16_47_sram_blwl_out[819:819] ,mux_2level_tapbuf_size16_47_sram_blwl_outb[819:819] ,mux_2level_tapbuf_size16_47_configbus0[819:819], mux_2level_tapbuf_size16_47_configbus1[819:819] , mux_2level_tapbuf_size16_47_configbus0_b[819:819] ); -sram6T_blwl sram_blwl_820_ (mux_2level_tapbuf_size16_47_sram_blwl_out[820:820] ,mux_2level_tapbuf_size16_47_sram_blwl_out[820:820] ,mux_2level_tapbuf_size16_47_sram_blwl_outb[820:820] ,mux_2level_tapbuf_size16_47_configbus0[820:820], mux_2level_tapbuf_size16_47_configbus1[820:820] , mux_2level_tapbuf_size16_47_configbus0_b[820:820] ); -sram6T_blwl sram_blwl_821_ (mux_2level_tapbuf_size16_47_sram_blwl_out[821:821] ,mux_2level_tapbuf_size16_47_sram_blwl_out[821:821] ,mux_2level_tapbuf_size16_47_sram_blwl_outb[821:821] ,mux_2level_tapbuf_size16_47_configbus0[821:821], mux_2level_tapbuf_size16_47_configbus1[821:821] , mux_2level_tapbuf_size16_47_configbus0_b[821:821] ); -sram6T_blwl sram_blwl_822_ (mux_2level_tapbuf_size16_47_sram_blwl_out[822:822] ,mux_2level_tapbuf_size16_47_sram_blwl_out[822:822] ,mux_2level_tapbuf_size16_47_sram_blwl_outb[822:822] ,mux_2level_tapbuf_size16_47_configbus0[822:822], mux_2level_tapbuf_size16_47_configbus1[822:822] , mux_2level_tapbuf_size16_47_configbus0_b[822:822] ); -sram6T_blwl sram_blwl_823_ (mux_2level_tapbuf_size16_47_sram_blwl_out[823:823] ,mux_2level_tapbuf_size16_47_sram_blwl_out[823:823] ,mux_2level_tapbuf_size16_47_sram_blwl_outb[823:823] ,mux_2level_tapbuf_size16_47_configbus0[823:823], mux_2level_tapbuf_size16_47_configbus1[823:823] , mux_2level_tapbuf_size16_47_configbus0_b[823:823] ); -wire [0:15] mux_2level_tapbuf_size16_48_inbus; -assign mux_2level_tapbuf_size16_48_inbus[0] = chany_0__1__midout_2_; -assign mux_2level_tapbuf_size16_48_inbus[1] = chany_0__1__midout_3_; -assign mux_2level_tapbuf_size16_48_inbus[2] = chany_0__1__midout_16_; -assign mux_2level_tapbuf_size16_48_inbus[3] = chany_0__1__midout_17_; -assign mux_2level_tapbuf_size16_48_inbus[4] = chany_0__1__midout_28_; -assign mux_2level_tapbuf_size16_48_inbus[5] = chany_0__1__midout_29_; -assign mux_2level_tapbuf_size16_48_inbus[6] = chany_0__1__midout_40_; -assign mux_2level_tapbuf_size16_48_inbus[7] = chany_0__1__midout_41_; -assign mux_2level_tapbuf_size16_48_inbus[8] = chany_0__1__midout_52_; -assign mux_2level_tapbuf_size16_48_inbus[9] = chany_0__1__midout_53_; -assign mux_2level_tapbuf_size16_48_inbus[10] = chany_0__1__midout_66_; -assign mux_2level_tapbuf_size16_48_inbus[11] = chany_0__1__midout_67_; -assign mux_2level_tapbuf_size16_48_inbus[12] = chany_0__1__midout_78_; -assign mux_2level_tapbuf_size16_48_inbus[13] = chany_0__1__midout_79_; -assign mux_2level_tapbuf_size16_48_inbus[14] = chany_0__1__midout_90_; -assign mux_2level_tapbuf_size16_48_inbus[15] = chany_0__1__midout_91_; -wire [824:831] mux_2level_tapbuf_size16_48_configbus0; -wire [824:831] mux_2level_tapbuf_size16_48_configbus1; -wire [824:831] mux_2level_tapbuf_size16_48_sram_blwl_out ; -wire [824:831] mux_2level_tapbuf_size16_48_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_48_configbus0[824:831] = sram_blwl_bl[824:831] ; -assign mux_2level_tapbuf_size16_48_configbus1[824:831] = sram_blwl_wl[824:831] ; -wire [824:831] mux_2level_tapbuf_size16_48_configbus0_b; -assign mux_2level_tapbuf_size16_48_configbus0_b[824:831] = sram_blwl_blb[824:831] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_48_ (mux_2level_tapbuf_size16_48_inbus, grid_0__1__pin_0__1__4_, mux_2level_tapbuf_size16_48_sram_blwl_out[824:831] , -mux_2level_tapbuf_size16_48_sram_blwl_outb[824:831] ); -//----- SRAM bits for MUX[48], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_824_ (mux_2level_tapbuf_size16_48_sram_blwl_out[824:824] ,mux_2level_tapbuf_size16_48_sram_blwl_out[824:824] ,mux_2level_tapbuf_size16_48_sram_blwl_outb[824:824] ,mux_2level_tapbuf_size16_48_configbus0[824:824], mux_2level_tapbuf_size16_48_configbus1[824:824] , mux_2level_tapbuf_size16_48_configbus0_b[824:824] ); -sram6T_blwl sram_blwl_825_ (mux_2level_tapbuf_size16_48_sram_blwl_out[825:825] ,mux_2level_tapbuf_size16_48_sram_blwl_out[825:825] ,mux_2level_tapbuf_size16_48_sram_blwl_outb[825:825] ,mux_2level_tapbuf_size16_48_configbus0[825:825], mux_2level_tapbuf_size16_48_configbus1[825:825] , mux_2level_tapbuf_size16_48_configbus0_b[825:825] ); -sram6T_blwl sram_blwl_826_ (mux_2level_tapbuf_size16_48_sram_blwl_out[826:826] ,mux_2level_tapbuf_size16_48_sram_blwl_out[826:826] ,mux_2level_tapbuf_size16_48_sram_blwl_outb[826:826] ,mux_2level_tapbuf_size16_48_configbus0[826:826], mux_2level_tapbuf_size16_48_configbus1[826:826] , mux_2level_tapbuf_size16_48_configbus0_b[826:826] ); -sram6T_blwl sram_blwl_827_ (mux_2level_tapbuf_size16_48_sram_blwl_out[827:827] ,mux_2level_tapbuf_size16_48_sram_blwl_out[827:827] ,mux_2level_tapbuf_size16_48_sram_blwl_outb[827:827] ,mux_2level_tapbuf_size16_48_configbus0[827:827], mux_2level_tapbuf_size16_48_configbus1[827:827] , mux_2level_tapbuf_size16_48_configbus0_b[827:827] ); -sram6T_blwl sram_blwl_828_ (mux_2level_tapbuf_size16_48_sram_blwl_out[828:828] ,mux_2level_tapbuf_size16_48_sram_blwl_out[828:828] ,mux_2level_tapbuf_size16_48_sram_blwl_outb[828:828] ,mux_2level_tapbuf_size16_48_configbus0[828:828], mux_2level_tapbuf_size16_48_configbus1[828:828] , mux_2level_tapbuf_size16_48_configbus0_b[828:828] ); -sram6T_blwl sram_blwl_829_ (mux_2level_tapbuf_size16_48_sram_blwl_out[829:829] ,mux_2level_tapbuf_size16_48_sram_blwl_out[829:829] ,mux_2level_tapbuf_size16_48_sram_blwl_outb[829:829] ,mux_2level_tapbuf_size16_48_configbus0[829:829], mux_2level_tapbuf_size16_48_configbus1[829:829] , mux_2level_tapbuf_size16_48_configbus0_b[829:829] ); -sram6T_blwl sram_blwl_830_ (mux_2level_tapbuf_size16_48_sram_blwl_out[830:830] ,mux_2level_tapbuf_size16_48_sram_blwl_out[830:830] ,mux_2level_tapbuf_size16_48_sram_blwl_outb[830:830] ,mux_2level_tapbuf_size16_48_configbus0[830:830], mux_2level_tapbuf_size16_48_configbus1[830:830] , mux_2level_tapbuf_size16_48_configbus0_b[830:830] ); -sram6T_blwl sram_blwl_831_ (mux_2level_tapbuf_size16_48_sram_blwl_out[831:831] ,mux_2level_tapbuf_size16_48_sram_blwl_out[831:831] ,mux_2level_tapbuf_size16_48_sram_blwl_outb[831:831] ,mux_2level_tapbuf_size16_48_configbus0[831:831], mux_2level_tapbuf_size16_48_configbus1[831:831] , mux_2level_tapbuf_size16_48_configbus0_b[831:831] ); -wire [0:15] mux_2level_tapbuf_size16_49_inbus; -assign mux_2level_tapbuf_size16_49_inbus[0] = chany_0__1__midout_4_; -assign mux_2level_tapbuf_size16_49_inbus[1] = chany_0__1__midout_5_; -assign mux_2level_tapbuf_size16_49_inbus[2] = chany_0__1__midout_16_; -assign mux_2level_tapbuf_size16_49_inbus[3] = chany_0__1__midout_17_; -assign mux_2level_tapbuf_size16_49_inbus[4] = chany_0__1__midout_30_; -assign mux_2level_tapbuf_size16_49_inbus[5] = chany_0__1__midout_31_; -assign mux_2level_tapbuf_size16_49_inbus[6] = chany_0__1__midout_42_; -assign mux_2level_tapbuf_size16_49_inbus[7] = chany_0__1__midout_43_; -assign mux_2level_tapbuf_size16_49_inbus[8] = chany_0__1__midout_54_; -assign mux_2level_tapbuf_size16_49_inbus[9] = chany_0__1__midout_55_; -assign mux_2level_tapbuf_size16_49_inbus[10] = chany_0__1__midout_66_; -assign mux_2level_tapbuf_size16_49_inbus[11] = chany_0__1__midout_67_; -assign mux_2level_tapbuf_size16_49_inbus[12] = chany_0__1__midout_80_; -assign mux_2level_tapbuf_size16_49_inbus[13] = chany_0__1__midout_81_; -assign mux_2level_tapbuf_size16_49_inbus[14] = chany_0__1__midout_92_; -assign mux_2level_tapbuf_size16_49_inbus[15] = chany_0__1__midout_93_; -wire [832:839] mux_2level_tapbuf_size16_49_configbus0; -wire [832:839] mux_2level_tapbuf_size16_49_configbus1; -wire [832:839] mux_2level_tapbuf_size16_49_sram_blwl_out ; -wire [832:839] mux_2level_tapbuf_size16_49_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_49_configbus0[832:839] = sram_blwl_bl[832:839] ; -assign mux_2level_tapbuf_size16_49_configbus1[832:839] = sram_blwl_wl[832:839] ; -wire [832:839] mux_2level_tapbuf_size16_49_configbus0_b; -assign mux_2level_tapbuf_size16_49_configbus0_b[832:839] = sram_blwl_blb[832:839] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_49_ (mux_2level_tapbuf_size16_49_inbus, grid_0__1__pin_0__1__6_, mux_2level_tapbuf_size16_49_sram_blwl_out[832:839] , -mux_2level_tapbuf_size16_49_sram_blwl_outb[832:839] ); -//----- SRAM bits for MUX[49], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_832_ (mux_2level_tapbuf_size16_49_sram_blwl_out[832:832] ,mux_2level_tapbuf_size16_49_sram_blwl_out[832:832] ,mux_2level_tapbuf_size16_49_sram_blwl_outb[832:832] ,mux_2level_tapbuf_size16_49_configbus0[832:832], mux_2level_tapbuf_size16_49_configbus1[832:832] , mux_2level_tapbuf_size16_49_configbus0_b[832:832] ); -sram6T_blwl sram_blwl_833_ (mux_2level_tapbuf_size16_49_sram_blwl_out[833:833] ,mux_2level_tapbuf_size16_49_sram_blwl_out[833:833] ,mux_2level_tapbuf_size16_49_sram_blwl_outb[833:833] ,mux_2level_tapbuf_size16_49_configbus0[833:833], mux_2level_tapbuf_size16_49_configbus1[833:833] , mux_2level_tapbuf_size16_49_configbus0_b[833:833] ); -sram6T_blwl sram_blwl_834_ (mux_2level_tapbuf_size16_49_sram_blwl_out[834:834] ,mux_2level_tapbuf_size16_49_sram_blwl_out[834:834] ,mux_2level_tapbuf_size16_49_sram_blwl_outb[834:834] ,mux_2level_tapbuf_size16_49_configbus0[834:834], mux_2level_tapbuf_size16_49_configbus1[834:834] , mux_2level_tapbuf_size16_49_configbus0_b[834:834] ); -sram6T_blwl sram_blwl_835_ (mux_2level_tapbuf_size16_49_sram_blwl_out[835:835] ,mux_2level_tapbuf_size16_49_sram_blwl_out[835:835] ,mux_2level_tapbuf_size16_49_sram_blwl_outb[835:835] ,mux_2level_tapbuf_size16_49_configbus0[835:835], mux_2level_tapbuf_size16_49_configbus1[835:835] , mux_2level_tapbuf_size16_49_configbus0_b[835:835] ); -sram6T_blwl sram_blwl_836_ (mux_2level_tapbuf_size16_49_sram_blwl_out[836:836] ,mux_2level_tapbuf_size16_49_sram_blwl_out[836:836] ,mux_2level_tapbuf_size16_49_sram_blwl_outb[836:836] ,mux_2level_tapbuf_size16_49_configbus0[836:836], mux_2level_tapbuf_size16_49_configbus1[836:836] , mux_2level_tapbuf_size16_49_configbus0_b[836:836] ); -sram6T_blwl sram_blwl_837_ (mux_2level_tapbuf_size16_49_sram_blwl_out[837:837] ,mux_2level_tapbuf_size16_49_sram_blwl_out[837:837] ,mux_2level_tapbuf_size16_49_sram_blwl_outb[837:837] ,mux_2level_tapbuf_size16_49_configbus0[837:837], mux_2level_tapbuf_size16_49_configbus1[837:837] , mux_2level_tapbuf_size16_49_configbus0_b[837:837] ); -sram6T_blwl sram_blwl_838_ (mux_2level_tapbuf_size16_49_sram_blwl_out[838:838] ,mux_2level_tapbuf_size16_49_sram_blwl_out[838:838] ,mux_2level_tapbuf_size16_49_sram_blwl_outb[838:838] ,mux_2level_tapbuf_size16_49_configbus0[838:838], mux_2level_tapbuf_size16_49_configbus1[838:838] , mux_2level_tapbuf_size16_49_configbus0_b[838:838] ); -sram6T_blwl sram_blwl_839_ (mux_2level_tapbuf_size16_49_sram_blwl_out[839:839] ,mux_2level_tapbuf_size16_49_sram_blwl_out[839:839] ,mux_2level_tapbuf_size16_49_sram_blwl_outb[839:839] ,mux_2level_tapbuf_size16_49_configbus0[839:839], mux_2level_tapbuf_size16_49_configbus1[839:839] , mux_2level_tapbuf_size16_49_configbus0_b[839:839] ); -wire [0:15] mux_2level_tapbuf_size16_50_inbus; -assign mux_2level_tapbuf_size16_50_inbus[0] = chany_0__1__midout_6_; -assign mux_2level_tapbuf_size16_50_inbus[1] = chany_0__1__midout_7_; -assign mux_2level_tapbuf_size16_50_inbus[2] = chany_0__1__midout_18_; -assign mux_2level_tapbuf_size16_50_inbus[3] = chany_0__1__midout_19_; -assign mux_2level_tapbuf_size16_50_inbus[4] = chany_0__1__midout_30_; -assign mux_2level_tapbuf_size16_50_inbus[5] = chany_0__1__midout_31_; -assign mux_2level_tapbuf_size16_50_inbus[6] = chany_0__1__midout_44_; -assign mux_2level_tapbuf_size16_50_inbus[7] = chany_0__1__midout_45_; -assign mux_2level_tapbuf_size16_50_inbus[8] = chany_0__1__midout_56_; -assign mux_2level_tapbuf_size16_50_inbus[9] = chany_0__1__midout_57_; -assign mux_2level_tapbuf_size16_50_inbus[10] = chany_0__1__midout_68_; -assign mux_2level_tapbuf_size16_50_inbus[11] = chany_0__1__midout_69_; -assign mux_2level_tapbuf_size16_50_inbus[12] = chany_0__1__midout_80_; -assign mux_2level_tapbuf_size16_50_inbus[13] = chany_0__1__midout_81_; -assign mux_2level_tapbuf_size16_50_inbus[14] = chany_0__1__midout_94_; -assign mux_2level_tapbuf_size16_50_inbus[15] = chany_0__1__midout_95_; -wire [840:847] mux_2level_tapbuf_size16_50_configbus0; -wire [840:847] mux_2level_tapbuf_size16_50_configbus1; -wire [840:847] mux_2level_tapbuf_size16_50_sram_blwl_out ; -wire [840:847] mux_2level_tapbuf_size16_50_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_50_configbus0[840:847] = sram_blwl_bl[840:847] ; -assign mux_2level_tapbuf_size16_50_configbus1[840:847] = sram_blwl_wl[840:847] ; -wire [840:847] mux_2level_tapbuf_size16_50_configbus0_b; -assign mux_2level_tapbuf_size16_50_configbus0_b[840:847] = sram_blwl_blb[840:847] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_50_ (mux_2level_tapbuf_size16_50_inbus, grid_0__1__pin_0__1__8_, mux_2level_tapbuf_size16_50_sram_blwl_out[840:847] , -mux_2level_tapbuf_size16_50_sram_blwl_outb[840:847] ); -//----- SRAM bits for MUX[50], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_840_ (mux_2level_tapbuf_size16_50_sram_blwl_out[840:840] ,mux_2level_tapbuf_size16_50_sram_blwl_out[840:840] ,mux_2level_tapbuf_size16_50_sram_blwl_outb[840:840] ,mux_2level_tapbuf_size16_50_configbus0[840:840], mux_2level_tapbuf_size16_50_configbus1[840:840] , mux_2level_tapbuf_size16_50_configbus0_b[840:840] ); -sram6T_blwl sram_blwl_841_ (mux_2level_tapbuf_size16_50_sram_blwl_out[841:841] ,mux_2level_tapbuf_size16_50_sram_blwl_out[841:841] ,mux_2level_tapbuf_size16_50_sram_blwl_outb[841:841] ,mux_2level_tapbuf_size16_50_configbus0[841:841], mux_2level_tapbuf_size16_50_configbus1[841:841] , mux_2level_tapbuf_size16_50_configbus0_b[841:841] ); -sram6T_blwl sram_blwl_842_ (mux_2level_tapbuf_size16_50_sram_blwl_out[842:842] ,mux_2level_tapbuf_size16_50_sram_blwl_out[842:842] ,mux_2level_tapbuf_size16_50_sram_blwl_outb[842:842] ,mux_2level_tapbuf_size16_50_configbus0[842:842], mux_2level_tapbuf_size16_50_configbus1[842:842] , mux_2level_tapbuf_size16_50_configbus0_b[842:842] ); -sram6T_blwl sram_blwl_843_ (mux_2level_tapbuf_size16_50_sram_blwl_out[843:843] ,mux_2level_tapbuf_size16_50_sram_blwl_out[843:843] ,mux_2level_tapbuf_size16_50_sram_blwl_outb[843:843] ,mux_2level_tapbuf_size16_50_configbus0[843:843], mux_2level_tapbuf_size16_50_configbus1[843:843] , mux_2level_tapbuf_size16_50_configbus0_b[843:843] ); -sram6T_blwl sram_blwl_844_ (mux_2level_tapbuf_size16_50_sram_blwl_out[844:844] ,mux_2level_tapbuf_size16_50_sram_blwl_out[844:844] ,mux_2level_tapbuf_size16_50_sram_blwl_outb[844:844] ,mux_2level_tapbuf_size16_50_configbus0[844:844], mux_2level_tapbuf_size16_50_configbus1[844:844] , mux_2level_tapbuf_size16_50_configbus0_b[844:844] ); -sram6T_blwl sram_blwl_845_ (mux_2level_tapbuf_size16_50_sram_blwl_out[845:845] ,mux_2level_tapbuf_size16_50_sram_blwl_out[845:845] ,mux_2level_tapbuf_size16_50_sram_blwl_outb[845:845] ,mux_2level_tapbuf_size16_50_configbus0[845:845], mux_2level_tapbuf_size16_50_configbus1[845:845] , mux_2level_tapbuf_size16_50_configbus0_b[845:845] ); -sram6T_blwl sram_blwl_846_ (mux_2level_tapbuf_size16_50_sram_blwl_out[846:846] ,mux_2level_tapbuf_size16_50_sram_blwl_out[846:846] ,mux_2level_tapbuf_size16_50_sram_blwl_outb[846:846] ,mux_2level_tapbuf_size16_50_configbus0[846:846], mux_2level_tapbuf_size16_50_configbus1[846:846] , mux_2level_tapbuf_size16_50_configbus0_b[846:846] ); -sram6T_blwl sram_blwl_847_ (mux_2level_tapbuf_size16_50_sram_blwl_out[847:847] ,mux_2level_tapbuf_size16_50_sram_blwl_out[847:847] ,mux_2level_tapbuf_size16_50_sram_blwl_outb[847:847] ,mux_2level_tapbuf_size16_50_configbus0[847:847], mux_2level_tapbuf_size16_50_configbus1[847:847] , mux_2level_tapbuf_size16_50_configbus0_b[847:847] ); -wire [0:15] mux_2level_tapbuf_size16_51_inbus; -assign mux_2level_tapbuf_size16_51_inbus[0] = chany_0__1__midout_8_; -assign mux_2level_tapbuf_size16_51_inbus[1] = chany_0__1__midout_9_; -assign mux_2level_tapbuf_size16_51_inbus[2] = chany_0__1__midout_20_; -assign mux_2level_tapbuf_size16_51_inbus[3] = chany_0__1__midout_21_; -assign mux_2level_tapbuf_size16_51_inbus[4] = chany_0__1__midout_32_; -assign mux_2level_tapbuf_size16_51_inbus[5] = chany_0__1__midout_33_; -assign mux_2level_tapbuf_size16_51_inbus[6] = chany_0__1__midout_44_; -assign mux_2level_tapbuf_size16_51_inbus[7] = chany_0__1__midout_45_; -assign mux_2level_tapbuf_size16_51_inbus[8] = chany_0__1__midout_58_; -assign mux_2level_tapbuf_size16_51_inbus[9] = chany_0__1__midout_59_; -assign mux_2level_tapbuf_size16_51_inbus[10] = chany_0__1__midout_70_; -assign mux_2level_tapbuf_size16_51_inbus[11] = chany_0__1__midout_71_; -assign mux_2level_tapbuf_size16_51_inbus[12] = chany_0__1__midout_82_; -assign mux_2level_tapbuf_size16_51_inbus[13] = chany_0__1__midout_83_; -assign mux_2level_tapbuf_size16_51_inbus[14] = chany_0__1__midout_94_; -assign mux_2level_tapbuf_size16_51_inbus[15] = chany_0__1__midout_95_; -wire [848:855] mux_2level_tapbuf_size16_51_configbus0; -wire [848:855] mux_2level_tapbuf_size16_51_configbus1; -wire [848:855] mux_2level_tapbuf_size16_51_sram_blwl_out ; -wire [848:855] mux_2level_tapbuf_size16_51_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_51_configbus0[848:855] = sram_blwl_bl[848:855] ; -assign mux_2level_tapbuf_size16_51_configbus1[848:855] = sram_blwl_wl[848:855] ; -wire [848:855] mux_2level_tapbuf_size16_51_configbus0_b; -assign mux_2level_tapbuf_size16_51_configbus0_b[848:855] = sram_blwl_blb[848:855] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_51_ (mux_2level_tapbuf_size16_51_inbus, grid_0__1__pin_0__1__10_, mux_2level_tapbuf_size16_51_sram_blwl_out[848:855] , -mux_2level_tapbuf_size16_51_sram_blwl_outb[848:855] ); -//----- SRAM bits for MUX[51], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_848_ (mux_2level_tapbuf_size16_51_sram_blwl_out[848:848] ,mux_2level_tapbuf_size16_51_sram_blwl_out[848:848] ,mux_2level_tapbuf_size16_51_sram_blwl_outb[848:848] ,mux_2level_tapbuf_size16_51_configbus0[848:848], mux_2level_tapbuf_size16_51_configbus1[848:848] , mux_2level_tapbuf_size16_51_configbus0_b[848:848] ); -sram6T_blwl sram_blwl_849_ (mux_2level_tapbuf_size16_51_sram_blwl_out[849:849] ,mux_2level_tapbuf_size16_51_sram_blwl_out[849:849] ,mux_2level_tapbuf_size16_51_sram_blwl_outb[849:849] ,mux_2level_tapbuf_size16_51_configbus0[849:849], mux_2level_tapbuf_size16_51_configbus1[849:849] , mux_2level_tapbuf_size16_51_configbus0_b[849:849] ); -sram6T_blwl sram_blwl_850_ (mux_2level_tapbuf_size16_51_sram_blwl_out[850:850] ,mux_2level_tapbuf_size16_51_sram_blwl_out[850:850] ,mux_2level_tapbuf_size16_51_sram_blwl_outb[850:850] ,mux_2level_tapbuf_size16_51_configbus0[850:850], mux_2level_tapbuf_size16_51_configbus1[850:850] , mux_2level_tapbuf_size16_51_configbus0_b[850:850] ); -sram6T_blwl sram_blwl_851_ (mux_2level_tapbuf_size16_51_sram_blwl_out[851:851] ,mux_2level_tapbuf_size16_51_sram_blwl_out[851:851] ,mux_2level_tapbuf_size16_51_sram_blwl_outb[851:851] ,mux_2level_tapbuf_size16_51_configbus0[851:851], mux_2level_tapbuf_size16_51_configbus1[851:851] , mux_2level_tapbuf_size16_51_configbus0_b[851:851] ); -sram6T_blwl sram_blwl_852_ (mux_2level_tapbuf_size16_51_sram_blwl_out[852:852] ,mux_2level_tapbuf_size16_51_sram_blwl_out[852:852] ,mux_2level_tapbuf_size16_51_sram_blwl_outb[852:852] ,mux_2level_tapbuf_size16_51_configbus0[852:852], mux_2level_tapbuf_size16_51_configbus1[852:852] , mux_2level_tapbuf_size16_51_configbus0_b[852:852] ); -sram6T_blwl sram_blwl_853_ (mux_2level_tapbuf_size16_51_sram_blwl_out[853:853] ,mux_2level_tapbuf_size16_51_sram_blwl_out[853:853] ,mux_2level_tapbuf_size16_51_sram_blwl_outb[853:853] ,mux_2level_tapbuf_size16_51_configbus0[853:853], mux_2level_tapbuf_size16_51_configbus1[853:853] , mux_2level_tapbuf_size16_51_configbus0_b[853:853] ); -sram6T_blwl sram_blwl_854_ (mux_2level_tapbuf_size16_51_sram_blwl_out[854:854] ,mux_2level_tapbuf_size16_51_sram_blwl_out[854:854] ,mux_2level_tapbuf_size16_51_sram_blwl_outb[854:854] ,mux_2level_tapbuf_size16_51_configbus0[854:854], mux_2level_tapbuf_size16_51_configbus1[854:854] , mux_2level_tapbuf_size16_51_configbus0_b[854:854] ); -sram6T_blwl sram_blwl_855_ (mux_2level_tapbuf_size16_51_sram_blwl_out[855:855] ,mux_2level_tapbuf_size16_51_sram_blwl_out[855:855] ,mux_2level_tapbuf_size16_51_sram_blwl_outb[855:855] ,mux_2level_tapbuf_size16_51_configbus0[855:855], mux_2level_tapbuf_size16_51_configbus1[855:855] , mux_2level_tapbuf_size16_51_configbus0_b[855:855] ); -wire [0:15] mux_2level_tapbuf_size16_52_inbus; -assign mux_2level_tapbuf_size16_52_inbus[0] = chany_0__1__midout_8_; -assign mux_2level_tapbuf_size16_52_inbus[1] = chany_0__1__midout_9_; -assign mux_2level_tapbuf_size16_52_inbus[2] = chany_0__1__midout_22_; -assign mux_2level_tapbuf_size16_52_inbus[3] = chany_0__1__midout_23_; -assign mux_2level_tapbuf_size16_52_inbus[4] = chany_0__1__midout_34_; -assign mux_2level_tapbuf_size16_52_inbus[5] = chany_0__1__midout_35_; -assign mux_2level_tapbuf_size16_52_inbus[6] = chany_0__1__midout_46_; -assign mux_2level_tapbuf_size16_52_inbus[7] = chany_0__1__midout_47_; -assign mux_2level_tapbuf_size16_52_inbus[8] = chany_0__1__midout_58_; -assign mux_2level_tapbuf_size16_52_inbus[9] = chany_0__1__midout_59_; -assign mux_2level_tapbuf_size16_52_inbus[10] = chany_0__1__midout_72_; -assign mux_2level_tapbuf_size16_52_inbus[11] = chany_0__1__midout_73_; -assign mux_2level_tapbuf_size16_52_inbus[12] = chany_0__1__midout_84_; -assign mux_2level_tapbuf_size16_52_inbus[13] = chany_0__1__midout_85_; -assign mux_2level_tapbuf_size16_52_inbus[14] = chany_0__1__midout_96_; -assign mux_2level_tapbuf_size16_52_inbus[15] = chany_0__1__midout_97_; -wire [856:863] mux_2level_tapbuf_size16_52_configbus0; -wire [856:863] mux_2level_tapbuf_size16_52_configbus1; -wire [856:863] mux_2level_tapbuf_size16_52_sram_blwl_out ; -wire [856:863] mux_2level_tapbuf_size16_52_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_52_configbus0[856:863] = sram_blwl_bl[856:863] ; -assign mux_2level_tapbuf_size16_52_configbus1[856:863] = sram_blwl_wl[856:863] ; -wire [856:863] mux_2level_tapbuf_size16_52_configbus0_b; -assign mux_2level_tapbuf_size16_52_configbus0_b[856:863] = sram_blwl_blb[856:863] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_52_ (mux_2level_tapbuf_size16_52_inbus, grid_0__1__pin_0__1__12_, mux_2level_tapbuf_size16_52_sram_blwl_out[856:863] , -mux_2level_tapbuf_size16_52_sram_blwl_outb[856:863] ); -//----- SRAM bits for MUX[52], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_856_ (mux_2level_tapbuf_size16_52_sram_blwl_out[856:856] ,mux_2level_tapbuf_size16_52_sram_blwl_out[856:856] ,mux_2level_tapbuf_size16_52_sram_blwl_outb[856:856] ,mux_2level_tapbuf_size16_52_configbus0[856:856], mux_2level_tapbuf_size16_52_configbus1[856:856] , mux_2level_tapbuf_size16_52_configbus0_b[856:856] ); -sram6T_blwl sram_blwl_857_ (mux_2level_tapbuf_size16_52_sram_blwl_out[857:857] ,mux_2level_tapbuf_size16_52_sram_blwl_out[857:857] ,mux_2level_tapbuf_size16_52_sram_blwl_outb[857:857] ,mux_2level_tapbuf_size16_52_configbus0[857:857], mux_2level_tapbuf_size16_52_configbus1[857:857] , mux_2level_tapbuf_size16_52_configbus0_b[857:857] ); -sram6T_blwl sram_blwl_858_ (mux_2level_tapbuf_size16_52_sram_blwl_out[858:858] ,mux_2level_tapbuf_size16_52_sram_blwl_out[858:858] ,mux_2level_tapbuf_size16_52_sram_blwl_outb[858:858] ,mux_2level_tapbuf_size16_52_configbus0[858:858], mux_2level_tapbuf_size16_52_configbus1[858:858] , mux_2level_tapbuf_size16_52_configbus0_b[858:858] ); -sram6T_blwl sram_blwl_859_ (mux_2level_tapbuf_size16_52_sram_blwl_out[859:859] ,mux_2level_tapbuf_size16_52_sram_blwl_out[859:859] ,mux_2level_tapbuf_size16_52_sram_blwl_outb[859:859] ,mux_2level_tapbuf_size16_52_configbus0[859:859], mux_2level_tapbuf_size16_52_configbus1[859:859] , mux_2level_tapbuf_size16_52_configbus0_b[859:859] ); -sram6T_blwl sram_blwl_860_ (mux_2level_tapbuf_size16_52_sram_blwl_out[860:860] ,mux_2level_tapbuf_size16_52_sram_blwl_out[860:860] ,mux_2level_tapbuf_size16_52_sram_blwl_outb[860:860] ,mux_2level_tapbuf_size16_52_configbus0[860:860], mux_2level_tapbuf_size16_52_configbus1[860:860] , mux_2level_tapbuf_size16_52_configbus0_b[860:860] ); -sram6T_blwl sram_blwl_861_ (mux_2level_tapbuf_size16_52_sram_blwl_out[861:861] ,mux_2level_tapbuf_size16_52_sram_blwl_out[861:861] ,mux_2level_tapbuf_size16_52_sram_blwl_outb[861:861] ,mux_2level_tapbuf_size16_52_configbus0[861:861], mux_2level_tapbuf_size16_52_configbus1[861:861] , mux_2level_tapbuf_size16_52_configbus0_b[861:861] ); -sram6T_blwl sram_blwl_862_ (mux_2level_tapbuf_size16_52_sram_blwl_out[862:862] ,mux_2level_tapbuf_size16_52_sram_blwl_out[862:862] ,mux_2level_tapbuf_size16_52_sram_blwl_outb[862:862] ,mux_2level_tapbuf_size16_52_configbus0[862:862], mux_2level_tapbuf_size16_52_configbus1[862:862] , mux_2level_tapbuf_size16_52_configbus0_b[862:862] ); -sram6T_blwl sram_blwl_863_ (mux_2level_tapbuf_size16_52_sram_blwl_out[863:863] ,mux_2level_tapbuf_size16_52_sram_blwl_out[863:863] ,mux_2level_tapbuf_size16_52_sram_blwl_outb[863:863] ,mux_2level_tapbuf_size16_52_configbus0[863:863], mux_2level_tapbuf_size16_52_configbus1[863:863] , mux_2level_tapbuf_size16_52_configbus0_b[863:863] ); -wire [0:15] mux_2level_tapbuf_size16_53_inbus; -assign mux_2level_tapbuf_size16_53_inbus[0] = chany_0__1__midout_10_; -assign mux_2level_tapbuf_size16_53_inbus[1] = chany_0__1__midout_11_; -assign mux_2level_tapbuf_size16_53_inbus[2] = chany_0__1__midout_22_; -assign mux_2level_tapbuf_size16_53_inbus[3] = chany_0__1__midout_23_; -assign mux_2level_tapbuf_size16_53_inbus[4] = chany_0__1__midout_36_; -assign mux_2level_tapbuf_size16_53_inbus[5] = chany_0__1__midout_37_; -assign mux_2level_tapbuf_size16_53_inbus[6] = chany_0__1__midout_48_; -assign mux_2level_tapbuf_size16_53_inbus[7] = chany_0__1__midout_49_; -assign mux_2level_tapbuf_size16_53_inbus[8] = chany_0__1__midout_60_; -assign mux_2level_tapbuf_size16_53_inbus[9] = chany_0__1__midout_61_; -assign mux_2level_tapbuf_size16_53_inbus[10] = chany_0__1__midout_72_; -assign mux_2level_tapbuf_size16_53_inbus[11] = chany_0__1__midout_73_; -assign mux_2level_tapbuf_size16_53_inbus[12] = chany_0__1__midout_86_; -assign mux_2level_tapbuf_size16_53_inbus[13] = chany_0__1__midout_87_; -assign mux_2level_tapbuf_size16_53_inbus[14] = chany_0__1__midout_98_; -assign mux_2level_tapbuf_size16_53_inbus[15] = chany_0__1__midout_99_; -wire [864:871] mux_2level_tapbuf_size16_53_configbus0; -wire [864:871] mux_2level_tapbuf_size16_53_configbus1; -wire [864:871] mux_2level_tapbuf_size16_53_sram_blwl_out ; -wire [864:871] mux_2level_tapbuf_size16_53_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_53_configbus0[864:871] = sram_blwl_bl[864:871] ; -assign mux_2level_tapbuf_size16_53_configbus1[864:871] = sram_blwl_wl[864:871] ; -wire [864:871] mux_2level_tapbuf_size16_53_configbus0_b; -assign mux_2level_tapbuf_size16_53_configbus0_b[864:871] = sram_blwl_blb[864:871] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_53_ (mux_2level_tapbuf_size16_53_inbus, grid_0__1__pin_0__1__14_, mux_2level_tapbuf_size16_53_sram_blwl_out[864:871] , -mux_2level_tapbuf_size16_53_sram_blwl_outb[864:871] ); -//----- SRAM bits for MUX[53], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_864_ (mux_2level_tapbuf_size16_53_sram_blwl_out[864:864] ,mux_2level_tapbuf_size16_53_sram_blwl_out[864:864] ,mux_2level_tapbuf_size16_53_sram_blwl_outb[864:864] ,mux_2level_tapbuf_size16_53_configbus0[864:864], mux_2level_tapbuf_size16_53_configbus1[864:864] , mux_2level_tapbuf_size16_53_configbus0_b[864:864] ); -sram6T_blwl sram_blwl_865_ (mux_2level_tapbuf_size16_53_sram_blwl_out[865:865] ,mux_2level_tapbuf_size16_53_sram_blwl_out[865:865] ,mux_2level_tapbuf_size16_53_sram_blwl_outb[865:865] ,mux_2level_tapbuf_size16_53_configbus0[865:865], mux_2level_tapbuf_size16_53_configbus1[865:865] , mux_2level_tapbuf_size16_53_configbus0_b[865:865] ); -sram6T_blwl sram_blwl_866_ (mux_2level_tapbuf_size16_53_sram_blwl_out[866:866] ,mux_2level_tapbuf_size16_53_sram_blwl_out[866:866] ,mux_2level_tapbuf_size16_53_sram_blwl_outb[866:866] ,mux_2level_tapbuf_size16_53_configbus0[866:866], mux_2level_tapbuf_size16_53_configbus1[866:866] , mux_2level_tapbuf_size16_53_configbus0_b[866:866] ); -sram6T_blwl sram_blwl_867_ (mux_2level_tapbuf_size16_53_sram_blwl_out[867:867] ,mux_2level_tapbuf_size16_53_sram_blwl_out[867:867] ,mux_2level_tapbuf_size16_53_sram_blwl_outb[867:867] ,mux_2level_tapbuf_size16_53_configbus0[867:867], mux_2level_tapbuf_size16_53_configbus1[867:867] , mux_2level_tapbuf_size16_53_configbus0_b[867:867] ); -sram6T_blwl sram_blwl_868_ (mux_2level_tapbuf_size16_53_sram_blwl_out[868:868] ,mux_2level_tapbuf_size16_53_sram_blwl_out[868:868] ,mux_2level_tapbuf_size16_53_sram_blwl_outb[868:868] ,mux_2level_tapbuf_size16_53_configbus0[868:868], mux_2level_tapbuf_size16_53_configbus1[868:868] , mux_2level_tapbuf_size16_53_configbus0_b[868:868] ); -sram6T_blwl sram_blwl_869_ (mux_2level_tapbuf_size16_53_sram_blwl_out[869:869] ,mux_2level_tapbuf_size16_53_sram_blwl_out[869:869] ,mux_2level_tapbuf_size16_53_sram_blwl_outb[869:869] ,mux_2level_tapbuf_size16_53_configbus0[869:869], mux_2level_tapbuf_size16_53_configbus1[869:869] , mux_2level_tapbuf_size16_53_configbus0_b[869:869] ); -sram6T_blwl sram_blwl_870_ (mux_2level_tapbuf_size16_53_sram_blwl_out[870:870] ,mux_2level_tapbuf_size16_53_sram_blwl_out[870:870] ,mux_2level_tapbuf_size16_53_sram_blwl_outb[870:870] ,mux_2level_tapbuf_size16_53_configbus0[870:870], mux_2level_tapbuf_size16_53_configbus1[870:870] , mux_2level_tapbuf_size16_53_configbus0_b[870:870] ); -sram6T_blwl sram_blwl_871_ (mux_2level_tapbuf_size16_53_sram_blwl_out[871:871] ,mux_2level_tapbuf_size16_53_sram_blwl_out[871:871] ,mux_2level_tapbuf_size16_53_sram_blwl_outb[871:871] ,mux_2level_tapbuf_size16_53_configbus0[871:871], mux_2level_tapbuf_size16_53_configbus1[871:871] , mux_2level_tapbuf_size16_53_configbus0_b[871:871] ); -endmodule -//----- END Verilog Module of Connection Box -Y direction [0][1] ----- - diff --git a/examples/verilog_test_example_2/routing/cby_1_1.v b/examples/verilog_test_example_2/routing/cby_1_1.v deleted file mode 100644 index 49c82c0f8..000000000 --- a/examples/verilog_test_example_2/routing/cby_1_1.v +++ /dev/null @@ -1,946 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Connection Block - Y direction [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Connection Box -Y direction [1][1] ----- -module cby_1__1_ ( -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -input chany_1__1__midout_0_, - -input chany_1__1__midout_1_, - -input chany_1__1__midout_2_, - -input chany_1__1__midout_3_, - -input chany_1__1__midout_4_, - -input chany_1__1__midout_5_, - -input chany_1__1__midout_6_, - -input chany_1__1__midout_7_, - -input chany_1__1__midout_8_, - -input chany_1__1__midout_9_, - -input chany_1__1__midout_10_, - -input chany_1__1__midout_11_, - -input chany_1__1__midout_12_, - -input chany_1__1__midout_13_, - -input chany_1__1__midout_14_, - -input chany_1__1__midout_15_, - -input chany_1__1__midout_16_, - -input chany_1__1__midout_17_, - -input chany_1__1__midout_18_, - -input chany_1__1__midout_19_, - -input chany_1__1__midout_20_, - -input chany_1__1__midout_21_, - -input chany_1__1__midout_22_, - -input chany_1__1__midout_23_, - -input chany_1__1__midout_24_, - -input chany_1__1__midout_25_, - -input chany_1__1__midout_26_, - -input chany_1__1__midout_27_, - -input chany_1__1__midout_28_, - -input chany_1__1__midout_29_, - -input chany_1__1__midout_30_, - -input chany_1__1__midout_31_, - -input chany_1__1__midout_32_, - -input chany_1__1__midout_33_, - -input chany_1__1__midout_34_, - -input chany_1__1__midout_35_, - -input chany_1__1__midout_36_, - -input chany_1__1__midout_37_, - -input chany_1__1__midout_38_, - -input chany_1__1__midout_39_, - -input chany_1__1__midout_40_, - -input chany_1__1__midout_41_, - -input chany_1__1__midout_42_, - -input chany_1__1__midout_43_, - -input chany_1__1__midout_44_, - -input chany_1__1__midout_45_, - -input chany_1__1__midout_46_, - -input chany_1__1__midout_47_, - -input chany_1__1__midout_48_, - -input chany_1__1__midout_49_, - -input chany_1__1__midout_50_, - -input chany_1__1__midout_51_, - -input chany_1__1__midout_52_, - -input chany_1__1__midout_53_, - -input chany_1__1__midout_54_, - -input chany_1__1__midout_55_, - -input chany_1__1__midout_56_, - -input chany_1__1__midout_57_, - -input chany_1__1__midout_58_, - -input chany_1__1__midout_59_, - -input chany_1__1__midout_60_, - -input chany_1__1__midout_61_, - -input chany_1__1__midout_62_, - -input chany_1__1__midout_63_, - -input chany_1__1__midout_64_, - -input chany_1__1__midout_65_, - -input chany_1__1__midout_66_, - -input chany_1__1__midout_67_, - -input chany_1__1__midout_68_, - -input chany_1__1__midout_69_, - -input chany_1__1__midout_70_, - -input chany_1__1__midout_71_, - -input chany_1__1__midout_72_, - -input chany_1__1__midout_73_, - -input chany_1__1__midout_74_, - -input chany_1__1__midout_75_, - -input chany_1__1__midout_76_, - -input chany_1__1__midout_77_, - -input chany_1__1__midout_78_, - -input chany_1__1__midout_79_, - -input chany_1__1__midout_80_, - -input chany_1__1__midout_81_, - -input chany_1__1__midout_82_, - -input chany_1__1__midout_83_, - -input chany_1__1__midout_84_, - -input chany_1__1__midout_85_, - -input chany_1__1__midout_86_, - -input chany_1__1__midout_87_, - -input chany_1__1__midout_88_, - -input chany_1__1__midout_89_, - -input chany_1__1__midout_90_, - -input chany_1__1__midout_91_, - -input chany_1__1__midout_92_, - -input chany_1__1__midout_93_, - -input chany_1__1__midout_94_, - -input chany_1__1__midout_95_, - -input chany_1__1__midout_96_, - -input chany_1__1__midout_97_, - -input chany_1__1__midout_98_, - -input chany_1__1__midout_99_, - -output grid_2__1__pin_0__3__0_, - -output grid_2__1__pin_0__3__2_, - -output grid_2__1__pin_0__3__4_, - -output grid_2__1__pin_0__3__6_, - -output grid_2__1__pin_0__3__8_, - -output grid_2__1__pin_0__3__10_, - -output grid_2__1__pin_0__3__12_, - -output grid_2__1__pin_0__3__14_, - -output grid_1__1__pin_0__1__1_, - -output grid_1__1__pin_0__1__5_, - -output grid_1__1__pin_0__1__9_, - -output grid_1__1__pin_0__1__13_, - -output grid_1__1__pin_0__1__17_, - -output grid_1__1__pin_0__1__21_, - -output grid_1__1__pin_0__1__25_, - -output grid_1__1__pin_0__1__29_, - -output grid_1__1__pin_0__1__33_, - -output grid_1__1__pin_0__1__37_, - -input [872:1015] sram_blwl_bl , -input [872:1015] sram_blwl_wl , -input [872:1015] sram_blwl_blb ); -wire [0:15] mux_2level_tapbuf_size16_54_inbus; -assign mux_2level_tapbuf_size16_54_inbus[0] = chany_1__1__midout_6_; -assign mux_2level_tapbuf_size16_54_inbus[1] = chany_1__1__midout_7_; -assign mux_2level_tapbuf_size16_54_inbus[2] = chany_1__1__midout_10_; -assign mux_2level_tapbuf_size16_54_inbus[3] = chany_1__1__midout_11_; -assign mux_2level_tapbuf_size16_54_inbus[4] = chany_1__1__midout_24_; -assign mux_2level_tapbuf_size16_54_inbus[5] = chany_1__1__midout_25_; -assign mux_2level_tapbuf_size16_54_inbus[6] = chany_1__1__midout_36_; -assign mux_2level_tapbuf_size16_54_inbus[7] = chany_1__1__midout_37_; -assign mux_2level_tapbuf_size16_54_inbus[8] = chany_1__1__midout_48_; -assign mux_2level_tapbuf_size16_54_inbus[9] = chany_1__1__midout_49_; -assign mux_2level_tapbuf_size16_54_inbus[10] = chany_1__1__midout_60_; -assign mux_2level_tapbuf_size16_54_inbus[11] = chany_1__1__midout_61_; -assign mux_2level_tapbuf_size16_54_inbus[12] = chany_1__1__midout_76_; -assign mux_2level_tapbuf_size16_54_inbus[13] = chany_1__1__midout_77_; -assign mux_2level_tapbuf_size16_54_inbus[14] = chany_1__1__midout_88_; -assign mux_2level_tapbuf_size16_54_inbus[15] = chany_1__1__midout_89_; -wire [872:879] mux_2level_tapbuf_size16_54_configbus0; -wire [872:879] mux_2level_tapbuf_size16_54_configbus1; -wire [872:879] mux_2level_tapbuf_size16_54_sram_blwl_out ; -wire [872:879] mux_2level_tapbuf_size16_54_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_54_configbus0[872:879] = sram_blwl_bl[872:879] ; -assign mux_2level_tapbuf_size16_54_configbus1[872:879] = sram_blwl_wl[872:879] ; -wire [872:879] mux_2level_tapbuf_size16_54_configbus0_b; -assign mux_2level_tapbuf_size16_54_configbus0_b[872:879] = sram_blwl_blb[872:879] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_54_ (mux_2level_tapbuf_size16_54_inbus, grid_2__1__pin_0__3__0_, mux_2level_tapbuf_size16_54_sram_blwl_out[872:879] , -mux_2level_tapbuf_size16_54_sram_blwl_outb[872:879] ); -//----- SRAM bits for MUX[54], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_872_ (mux_2level_tapbuf_size16_54_sram_blwl_out[872:872] ,mux_2level_tapbuf_size16_54_sram_blwl_out[872:872] ,mux_2level_tapbuf_size16_54_sram_blwl_outb[872:872] ,mux_2level_tapbuf_size16_54_configbus0[872:872], mux_2level_tapbuf_size16_54_configbus1[872:872] , mux_2level_tapbuf_size16_54_configbus0_b[872:872] ); -sram6T_blwl sram_blwl_873_ (mux_2level_tapbuf_size16_54_sram_blwl_out[873:873] ,mux_2level_tapbuf_size16_54_sram_blwl_out[873:873] ,mux_2level_tapbuf_size16_54_sram_blwl_outb[873:873] ,mux_2level_tapbuf_size16_54_configbus0[873:873], mux_2level_tapbuf_size16_54_configbus1[873:873] , mux_2level_tapbuf_size16_54_configbus0_b[873:873] ); -sram6T_blwl sram_blwl_874_ (mux_2level_tapbuf_size16_54_sram_blwl_out[874:874] ,mux_2level_tapbuf_size16_54_sram_blwl_out[874:874] ,mux_2level_tapbuf_size16_54_sram_blwl_outb[874:874] ,mux_2level_tapbuf_size16_54_configbus0[874:874], mux_2level_tapbuf_size16_54_configbus1[874:874] , mux_2level_tapbuf_size16_54_configbus0_b[874:874] ); -sram6T_blwl sram_blwl_875_ (mux_2level_tapbuf_size16_54_sram_blwl_out[875:875] ,mux_2level_tapbuf_size16_54_sram_blwl_out[875:875] ,mux_2level_tapbuf_size16_54_sram_blwl_outb[875:875] ,mux_2level_tapbuf_size16_54_configbus0[875:875], mux_2level_tapbuf_size16_54_configbus1[875:875] , mux_2level_tapbuf_size16_54_configbus0_b[875:875] ); -sram6T_blwl sram_blwl_876_ (mux_2level_tapbuf_size16_54_sram_blwl_out[876:876] ,mux_2level_tapbuf_size16_54_sram_blwl_out[876:876] ,mux_2level_tapbuf_size16_54_sram_blwl_outb[876:876] ,mux_2level_tapbuf_size16_54_configbus0[876:876], mux_2level_tapbuf_size16_54_configbus1[876:876] , mux_2level_tapbuf_size16_54_configbus0_b[876:876] ); -sram6T_blwl sram_blwl_877_ (mux_2level_tapbuf_size16_54_sram_blwl_out[877:877] ,mux_2level_tapbuf_size16_54_sram_blwl_out[877:877] ,mux_2level_tapbuf_size16_54_sram_blwl_outb[877:877] ,mux_2level_tapbuf_size16_54_configbus0[877:877], mux_2level_tapbuf_size16_54_configbus1[877:877] , mux_2level_tapbuf_size16_54_configbus0_b[877:877] ); -sram6T_blwl sram_blwl_878_ (mux_2level_tapbuf_size16_54_sram_blwl_out[878:878] ,mux_2level_tapbuf_size16_54_sram_blwl_out[878:878] ,mux_2level_tapbuf_size16_54_sram_blwl_outb[878:878] ,mux_2level_tapbuf_size16_54_configbus0[878:878], mux_2level_tapbuf_size16_54_configbus1[878:878] , mux_2level_tapbuf_size16_54_configbus0_b[878:878] ); -sram6T_blwl sram_blwl_879_ (mux_2level_tapbuf_size16_54_sram_blwl_out[879:879] ,mux_2level_tapbuf_size16_54_sram_blwl_out[879:879] ,mux_2level_tapbuf_size16_54_sram_blwl_outb[879:879] ,mux_2level_tapbuf_size16_54_configbus0[879:879], mux_2level_tapbuf_size16_54_configbus1[879:879] , mux_2level_tapbuf_size16_54_configbus0_b[879:879] ); -wire [0:15] mux_2level_tapbuf_size16_55_inbus; -assign mux_2level_tapbuf_size16_55_inbus[0] = chany_1__1__midout_0_; -assign mux_2level_tapbuf_size16_55_inbus[1] = chany_1__1__midout_1_; -assign mux_2level_tapbuf_size16_55_inbus[2] = chany_1__1__midout_12_; -assign mux_2level_tapbuf_size16_55_inbus[3] = chany_1__1__midout_13_; -assign mux_2level_tapbuf_size16_55_inbus[4] = chany_1__1__midout_24_; -assign mux_2level_tapbuf_size16_55_inbus[5] = chany_1__1__midout_25_; -assign mux_2level_tapbuf_size16_55_inbus[6] = chany_1__1__midout_42_; -assign mux_2level_tapbuf_size16_55_inbus[7] = chany_1__1__midout_43_; -assign mux_2level_tapbuf_size16_55_inbus[8] = chany_1__1__midout_54_; -assign mux_2level_tapbuf_size16_55_inbus[9] = chany_1__1__midout_55_; -assign mux_2level_tapbuf_size16_55_inbus[10] = chany_1__1__midout_66_; -assign mux_2level_tapbuf_size16_55_inbus[11] = chany_1__1__midout_67_; -assign mux_2level_tapbuf_size16_55_inbus[12] = chany_1__1__midout_76_; -assign mux_2level_tapbuf_size16_55_inbus[13] = chany_1__1__midout_77_; -assign mux_2level_tapbuf_size16_55_inbus[14] = chany_1__1__midout_90_; -assign mux_2level_tapbuf_size16_55_inbus[15] = chany_1__1__midout_91_; -wire [880:887] mux_2level_tapbuf_size16_55_configbus0; -wire [880:887] mux_2level_tapbuf_size16_55_configbus1; -wire [880:887] mux_2level_tapbuf_size16_55_sram_blwl_out ; -wire [880:887] mux_2level_tapbuf_size16_55_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_55_configbus0[880:887] = sram_blwl_bl[880:887] ; -assign mux_2level_tapbuf_size16_55_configbus1[880:887] = sram_blwl_wl[880:887] ; -wire [880:887] mux_2level_tapbuf_size16_55_configbus0_b; -assign mux_2level_tapbuf_size16_55_configbus0_b[880:887] = sram_blwl_blb[880:887] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_55_ (mux_2level_tapbuf_size16_55_inbus, grid_2__1__pin_0__3__2_, mux_2level_tapbuf_size16_55_sram_blwl_out[880:887] , -mux_2level_tapbuf_size16_55_sram_blwl_outb[880:887] ); -//----- SRAM bits for MUX[55], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_880_ (mux_2level_tapbuf_size16_55_sram_blwl_out[880:880] ,mux_2level_tapbuf_size16_55_sram_blwl_out[880:880] ,mux_2level_tapbuf_size16_55_sram_blwl_outb[880:880] ,mux_2level_tapbuf_size16_55_configbus0[880:880], mux_2level_tapbuf_size16_55_configbus1[880:880] , mux_2level_tapbuf_size16_55_configbus0_b[880:880] ); -sram6T_blwl sram_blwl_881_ (mux_2level_tapbuf_size16_55_sram_blwl_out[881:881] ,mux_2level_tapbuf_size16_55_sram_blwl_out[881:881] ,mux_2level_tapbuf_size16_55_sram_blwl_outb[881:881] ,mux_2level_tapbuf_size16_55_configbus0[881:881], mux_2level_tapbuf_size16_55_configbus1[881:881] , mux_2level_tapbuf_size16_55_configbus0_b[881:881] ); -sram6T_blwl sram_blwl_882_ (mux_2level_tapbuf_size16_55_sram_blwl_out[882:882] ,mux_2level_tapbuf_size16_55_sram_blwl_out[882:882] ,mux_2level_tapbuf_size16_55_sram_blwl_outb[882:882] ,mux_2level_tapbuf_size16_55_configbus0[882:882], mux_2level_tapbuf_size16_55_configbus1[882:882] , mux_2level_tapbuf_size16_55_configbus0_b[882:882] ); -sram6T_blwl sram_blwl_883_ (mux_2level_tapbuf_size16_55_sram_blwl_out[883:883] ,mux_2level_tapbuf_size16_55_sram_blwl_out[883:883] ,mux_2level_tapbuf_size16_55_sram_blwl_outb[883:883] ,mux_2level_tapbuf_size16_55_configbus0[883:883], mux_2level_tapbuf_size16_55_configbus1[883:883] , mux_2level_tapbuf_size16_55_configbus0_b[883:883] ); -sram6T_blwl sram_blwl_884_ (mux_2level_tapbuf_size16_55_sram_blwl_out[884:884] ,mux_2level_tapbuf_size16_55_sram_blwl_out[884:884] ,mux_2level_tapbuf_size16_55_sram_blwl_outb[884:884] ,mux_2level_tapbuf_size16_55_configbus0[884:884], mux_2level_tapbuf_size16_55_configbus1[884:884] , mux_2level_tapbuf_size16_55_configbus0_b[884:884] ); -sram6T_blwl sram_blwl_885_ (mux_2level_tapbuf_size16_55_sram_blwl_out[885:885] ,mux_2level_tapbuf_size16_55_sram_blwl_out[885:885] ,mux_2level_tapbuf_size16_55_sram_blwl_outb[885:885] ,mux_2level_tapbuf_size16_55_configbus0[885:885], mux_2level_tapbuf_size16_55_configbus1[885:885] , mux_2level_tapbuf_size16_55_configbus0_b[885:885] ); -sram6T_blwl sram_blwl_886_ (mux_2level_tapbuf_size16_55_sram_blwl_out[886:886] ,mux_2level_tapbuf_size16_55_sram_blwl_out[886:886] ,mux_2level_tapbuf_size16_55_sram_blwl_outb[886:886] ,mux_2level_tapbuf_size16_55_configbus0[886:886], mux_2level_tapbuf_size16_55_configbus1[886:886] , mux_2level_tapbuf_size16_55_configbus0_b[886:886] ); -sram6T_blwl sram_blwl_887_ (mux_2level_tapbuf_size16_55_sram_blwl_out[887:887] ,mux_2level_tapbuf_size16_55_sram_blwl_out[887:887] ,mux_2level_tapbuf_size16_55_sram_blwl_outb[887:887] ,mux_2level_tapbuf_size16_55_configbus0[887:887], mux_2level_tapbuf_size16_55_configbus1[887:887] , mux_2level_tapbuf_size16_55_configbus0_b[887:887] ); -wire [0:15] mux_2level_tapbuf_size16_56_inbus; -assign mux_2level_tapbuf_size16_56_inbus[0] = chany_1__1__midout_2_; -assign mux_2level_tapbuf_size16_56_inbus[1] = chany_1__1__midout_3_; -assign mux_2level_tapbuf_size16_56_inbus[2] = chany_1__1__midout_22_; -assign mux_2level_tapbuf_size16_56_inbus[3] = chany_1__1__midout_23_; -assign mux_2level_tapbuf_size16_56_inbus[4] = chany_1__1__midout_26_; -assign mux_2level_tapbuf_size16_56_inbus[5] = chany_1__1__midout_27_; -assign mux_2level_tapbuf_size16_56_inbus[6] = chany_1__1__midout_42_; -assign mux_2level_tapbuf_size16_56_inbus[7] = chany_1__1__midout_43_; -assign mux_2level_tapbuf_size16_56_inbus[8] = chany_1__1__midout_52_; -assign mux_2level_tapbuf_size16_56_inbus[9] = chany_1__1__midout_53_; -assign mux_2level_tapbuf_size16_56_inbus[10] = chany_1__1__midout_64_; -assign mux_2level_tapbuf_size16_56_inbus[11] = chany_1__1__midout_65_; -assign mux_2level_tapbuf_size16_56_inbus[12] = chany_1__1__midout_78_; -assign mux_2level_tapbuf_size16_56_inbus[13] = chany_1__1__midout_79_; -assign mux_2level_tapbuf_size16_56_inbus[14] = chany_1__1__midout_90_; -assign mux_2level_tapbuf_size16_56_inbus[15] = chany_1__1__midout_91_; -wire [888:895] mux_2level_tapbuf_size16_56_configbus0; -wire [888:895] mux_2level_tapbuf_size16_56_configbus1; -wire [888:895] mux_2level_tapbuf_size16_56_sram_blwl_out ; -wire [888:895] mux_2level_tapbuf_size16_56_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_56_configbus0[888:895] = sram_blwl_bl[888:895] ; -assign mux_2level_tapbuf_size16_56_configbus1[888:895] = sram_blwl_wl[888:895] ; -wire [888:895] mux_2level_tapbuf_size16_56_configbus0_b; -assign mux_2level_tapbuf_size16_56_configbus0_b[888:895] = sram_blwl_blb[888:895] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_56_ (mux_2level_tapbuf_size16_56_inbus, grid_2__1__pin_0__3__4_, mux_2level_tapbuf_size16_56_sram_blwl_out[888:895] , -mux_2level_tapbuf_size16_56_sram_blwl_outb[888:895] ); -//----- SRAM bits for MUX[56], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_888_ (mux_2level_tapbuf_size16_56_sram_blwl_out[888:888] ,mux_2level_tapbuf_size16_56_sram_blwl_out[888:888] ,mux_2level_tapbuf_size16_56_sram_blwl_outb[888:888] ,mux_2level_tapbuf_size16_56_configbus0[888:888], mux_2level_tapbuf_size16_56_configbus1[888:888] , mux_2level_tapbuf_size16_56_configbus0_b[888:888] ); -sram6T_blwl sram_blwl_889_ (mux_2level_tapbuf_size16_56_sram_blwl_out[889:889] ,mux_2level_tapbuf_size16_56_sram_blwl_out[889:889] ,mux_2level_tapbuf_size16_56_sram_blwl_outb[889:889] ,mux_2level_tapbuf_size16_56_configbus0[889:889], mux_2level_tapbuf_size16_56_configbus1[889:889] , mux_2level_tapbuf_size16_56_configbus0_b[889:889] ); -sram6T_blwl sram_blwl_890_ (mux_2level_tapbuf_size16_56_sram_blwl_out[890:890] ,mux_2level_tapbuf_size16_56_sram_blwl_out[890:890] ,mux_2level_tapbuf_size16_56_sram_blwl_outb[890:890] ,mux_2level_tapbuf_size16_56_configbus0[890:890], mux_2level_tapbuf_size16_56_configbus1[890:890] , mux_2level_tapbuf_size16_56_configbus0_b[890:890] ); -sram6T_blwl sram_blwl_891_ (mux_2level_tapbuf_size16_56_sram_blwl_out[891:891] ,mux_2level_tapbuf_size16_56_sram_blwl_out[891:891] ,mux_2level_tapbuf_size16_56_sram_blwl_outb[891:891] ,mux_2level_tapbuf_size16_56_configbus0[891:891], mux_2level_tapbuf_size16_56_configbus1[891:891] , mux_2level_tapbuf_size16_56_configbus0_b[891:891] ); -sram6T_blwl sram_blwl_892_ (mux_2level_tapbuf_size16_56_sram_blwl_out[892:892] ,mux_2level_tapbuf_size16_56_sram_blwl_out[892:892] ,mux_2level_tapbuf_size16_56_sram_blwl_outb[892:892] ,mux_2level_tapbuf_size16_56_configbus0[892:892], mux_2level_tapbuf_size16_56_configbus1[892:892] , mux_2level_tapbuf_size16_56_configbus0_b[892:892] ); -sram6T_blwl sram_blwl_893_ (mux_2level_tapbuf_size16_56_sram_blwl_out[893:893] ,mux_2level_tapbuf_size16_56_sram_blwl_out[893:893] ,mux_2level_tapbuf_size16_56_sram_blwl_outb[893:893] ,mux_2level_tapbuf_size16_56_configbus0[893:893], mux_2level_tapbuf_size16_56_configbus1[893:893] , mux_2level_tapbuf_size16_56_configbus0_b[893:893] ); -sram6T_blwl sram_blwl_894_ (mux_2level_tapbuf_size16_56_sram_blwl_out[894:894] ,mux_2level_tapbuf_size16_56_sram_blwl_out[894:894] ,mux_2level_tapbuf_size16_56_sram_blwl_outb[894:894] ,mux_2level_tapbuf_size16_56_configbus0[894:894], mux_2level_tapbuf_size16_56_configbus1[894:894] , mux_2level_tapbuf_size16_56_configbus0_b[894:894] ); -sram6T_blwl sram_blwl_895_ (mux_2level_tapbuf_size16_56_sram_blwl_out[895:895] ,mux_2level_tapbuf_size16_56_sram_blwl_out[895:895] ,mux_2level_tapbuf_size16_56_sram_blwl_outb[895:895] ,mux_2level_tapbuf_size16_56_configbus0[895:895], mux_2level_tapbuf_size16_56_configbus1[895:895] , mux_2level_tapbuf_size16_56_configbus0_b[895:895] ); -wire [0:15] mux_2level_tapbuf_size16_57_inbus; -assign mux_2level_tapbuf_size16_57_inbus[0] = chany_1__1__midout_2_; -assign mux_2level_tapbuf_size16_57_inbus[1] = chany_1__1__midout_3_; -assign mux_2level_tapbuf_size16_57_inbus[2] = chany_1__1__midout_16_; -assign mux_2level_tapbuf_size16_57_inbus[3] = chany_1__1__midout_17_; -assign mux_2level_tapbuf_size16_57_inbus[4] = chany_1__1__midout_28_; -assign mux_2level_tapbuf_size16_57_inbus[5] = chany_1__1__midout_29_; -assign mux_2level_tapbuf_size16_57_inbus[6] = chany_1__1__midout_40_; -assign mux_2level_tapbuf_size16_57_inbus[7] = chany_1__1__midout_41_; -assign mux_2level_tapbuf_size16_57_inbus[8] = chany_1__1__midout_52_; -assign mux_2level_tapbuf_size16_57_inbus[9] = chany_1__1__midout_53_; -assign mux_2level_tapbuf_size16_57_inbus[10] = chany_1__1__midout_68_; -assign mux_2level_tapbuf_size16_57_inbus[11] = chany_1__1__midout_69_; -assign mux_2level_tapbuf_size16_57_inbus[12] = chany_1__1__midout_80_; -assign mux_2level_tapbuf_size16_57_inbus[13] = chany_1__1__midout_81_; -assign mux_2level_tapbuf_size16_57_inbus[14] = chany_1__1__midout_92_; -assign mux_2level_tapbuf_size16_57_inbus[15] = chany_1__1__midout_93_; -wire [896:903] mux_2level_tapbuf_size16_57_configbus0; -wire [896:903] mux_2level_tapbuf_size16_57_configbus1; -wire [896:903] mux_2level_tapbuf_size16_57_sram_blwl_out ; -wire [896:903] mux_2level_tapbuf_size16_57_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_57_configbus0[896:903] = sram_blwl_bl[896:903] ; -assign mux_2level_tapbuf_size16_57_configbus1[896:903] = sram_blwl_wl[896:903] ; -wire [896:903] mux_2level_tapbuf_size16_57_configbus0_b; -assign mux_2level_tapbuf_size16_57_configbus0_b[896:903] = sram_blwl_blb[896:903] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_57_ (mux_2level_tapbuf_size16_57_inbus, grid_2__1__pin_0__3__6_, mux_2level_tapbuf_size16_57_sram_blwl_out[896:903] , -mux_2level_tapbuf_size16_57_sram_blwl_outb[896:903] ); -//----- SRAM bits for MUX[57], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_896_ (mux_2level_tapbuf_size16_57_sram_blwl_out[896:896] ,mux_2level_tapbuf_size16_57_sram_blwl_out[896:896] ,mux_2level_tapbuf_size16_57_sram_blwl_outb[896:896] ,mux_2level_tapbuf_size16_57_configbus0[896:896], mux_2level_tapbuf_size16_57_configbus1[896:896] , mux_2level_tapbuf_size16_57_configbus0_b[896:896] ); -sram6T_blwl sram_blwl_897_ (mux_2level_tapbuf_size16_57_sram_blwl_out[897:897] ,mux_2level_tapbuf_size16_57_sram_blwl_out[897:897] ,mux_2level_tapbuf_size16_57_sram_blwl_outb[897:897] ,mux_2level_tapbuf_size16_57_configbus0[897:897], mux_2level_tapbuf_size16_57_configbus1[897:897] , mux_2level_tapbuf_size16_57_configbus0_b[897:897] ); -sram6T_blwl sram_blwl_898_ (mux_2level_tapbuf_size16_57_sram_blwl_out[898:898] ,mux_2level_tapbuf_size16_57_sram_blwl_out[898:898] ,mux_2level_tapbuf_size16_57_sram_blwl_outb[898:898] ,mux_2level_tapbuf_size16_57_configbus0[898:898], mux_2level_tapbuf_size16_57_configbus1[898:898] , mux_2level_tapbuf_size16_57_configbus0_b[898:898] ); -sram6T_blwl sram_blwl_899_ (mux_2level_tapbuf_size16_57_sram_blwl_out[899:899] ,mux_2level_tapbuf_size16_57_sram_blwl_out[899:899] ,mux_2level_tapbuf_size16_57_sram_blwl_outb[899:899] ,mux_2level_tapbuf_size16_57_configbus0[899:899], mux_2level_tapbuf_size16_57_configbus1[899:899] , mux_2level_tapbuf_size16_57_configbus0_b[899:899] ); -sram6T_blwl sram_blwl_900_ (mux_2level_tapbuf_size16_57_sram_blwl_out[900:900] ,mux_2level_tapbuf_size16_57_sram_blwl_out[900:900] ,mux_2level_tapbuf_size16_57_sram_blwl_outb[900:900] ,mux_2level_tapbuf_size16_57_configbus0[900:900], mux_2level_tapbuf_size16_57_configbus1[900:900] , mux_2level_tapbuf_size16_57_configbus0_b[900:900] ); -sram6T_blwl sram_blwl_901_ (mux_2level_tapbuf_size16_57_sram_blwl_out[901:901] ,mux_2level_tapbuf_size16_57_sram_blwl_out[901:901] ,mux_2level_tapbuf_size16_57_sram_blwl_outb[901:901] ,mux_2level_tapbuf_size16_57_configbus0[901:901], mux_2level_tapbuf_size16_57_configbus1[901:901] , mux_2level_tapbuf_size16_57_configbus0_b[901:901] ); -sram6T_blwl sram_blwl_902_ (mux_2level_tapbuf_size16_57_sram_blwl_out[902:902] ,mux_2level_tapbuf_size16_57_sram_blwl_out[902:902] ,mux_2level_tapbuf_size16_57_sram_blwl_outb[902:902] ,mux_2level_tapbuf_size16_57_configbus0[902:902], mux_2level_tapbuf_size16_57_configbus1[902:902] , mux_2level_tapbuf_size16_57_configbus0_b[902:902] ); -sram6T_blwl sram_blwl_903_ (mux_2level_tapbuf_size16_57_sram_blwl_out[903:903] ,mux_2level_tapbuf_size16_57_sram_blwl_out[903:903] ,mux_2level_tapbuf_size16_57_sram_blwl_outb[903:903] ,mux_2level_tapbuf_size16_57_configbus0[903:903], mux_2level_tapbuf_size16_57_configbus1[903:903] , mux_2level_tapbuf_size16_57_configbus0_b[903:903] ); -wire [0:15] mux_2level_tapbuf_size16_58_inbus; -assign mux_2level_tapbuf_size16_58_inbus[0] = chany_1__1__midout_4_; -assign mux_2level_tapbuf_size16_58_inbus[1] = chany_1__1__midout_5_; -assign mux_2level_tapbuf_size16_58_inbus[2] = chany_1__1__midout_16_; -assign mux_2level_tapbuf_size16_58_inbus[3] = chany_1__1__midout_17_; -assign mux_2level_tapbuf_size16_58_inbus[4] = chany_1__1__midout_38_; -assign mux_2level_tapbuf_size16_58_inbus[5] = chany_1__1__midout_39_; -assign mux_2level_tapbuf_size16_58_inbus[6] = chany_1__1__midout_46_; -assign mux_2level_tapbuf_size16_58_inbus[7] = chany_1__1__midout_47_; -assign mux_2level_tapbuf_size16_58_inbus[8] = chany_1__1__midout_58_; -assign mux_2level_tapbuf_size16_58_inbus[9] = chany_1__1__midout_59_; -assign mux_2level_tapbuf_size16_58_inbus[10] = chany_1__1__midout_68_; -assign mux_2level_tapbuf_size16_58_inbus[11] = chany_1__1__midout_69_; -assign mux_2level_tapbuf_size16_58_inbus[12] = chany_1__1__midout_82_; -assign mux_2level_tapbuf_size16_58_inbus[13] = chany_1__1__midout_83_; -assign mux_2level_tapbuf_size16_58_inbus[14] = chany_1__1__midout_94_; -assign mux_2level_tapbuf_size16_58_inbus[15] = chany_1__1__midout_95_; -wire [904:911] mux_2level_tapbuf_size16_58_configbus0; -wire [904:911] mux_2level_tapbuf_size16_58_configbus1; -wire [904:911] mux_2level_tapbuf_size16_58_sram_blwl_out ; -wire [904:911] mux_2level_tapbuf_size16_58_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_58_configbus0[904:911] = sram_blwl_bl[904:911] ; -assign mux_2level_tapbuf_size16_58_configbus1[904:911] = sram_blwl_wl[904:911] ; -wire [904:911] mux_2level_tapbuf_size16_58_configbus0_b; -assign mux_2level_tapbuf_size16_58_configbus0_b[904:911] = sram_blwl_blb[904:911] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_58_ (mux_2level_tapbuf_size16_58_inbus, grid_2__1__pin_0__3__8_, mux_2level_tapbuf_size16_58_sram_blwl_out[904:911] , -mux_2level_tapbuf_size16_58_sram_blwl_outb[904:911] ); -//----- SRAM bits for MUX[58], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_904_ (mux_2level_tapbuf_size16_58_sram_blwl_out[904:904] ,mux_2level_tapbuf_size16_58_sram_blwl_out[904:904] ,mux_2level_tapbuf_size16_58_sram_blwl_outb[904:904] ,mux_2level_tapbuf_size16_58_configbus0[904:904], mux_2level_tapbuf_size16_58_configbus1[904:904] , mux_2level_tapbuf_size16_58_configbus0_b[904:904] ); -sram6T_blwl sram_blwl_905_ (mux_2level_tapbuf_size16_58_sram_blwl_out[905:905] ,mux_2level_tapbuf_size16_58_sram_blwl_out[905:905] ,mux_2level_tapbuf_size16_58_sram_blwl_outb[905:905] ,mux_2level_tapbuf_size16_58_configbus0[905:905], mux_2level_tapbuf_size16_58_configbus1[905:905] , mux_2level_tapbuf_size16_58_configbus0_b[905:905] ); -sram6T_blwl sram_blwl_906_ (mux_2level_tapbuf_size16_58_sram_blwl_out[906:906] ,mux_2level_tapbuf_size16_58_sram_blwl_out[906:906] ,mux_2level_tapbuf_size16_58_sram_blwl_outb[906:906] ,mux_2level_tapbuf_size16_58_configbus0[906:906], mux_2level_tapbuf_size16_58_configbus1[906:906] , mux_2level_tapbuf_size16_58_configbus0_b[906:906] ); -sram6T_blwl sram_blwl_907_ (mux_2level_tapbuf_size16_58_sram_blwl_out[907:907] ,mux_2level_tapbuf_size16_58_sram_blwl_out[907:907] ,mux_2level_tapbuf_size16_58_sram_blwl_outb[907:907] ,mux_2level_tapbuf_size16_58_configbus0[907:907], mux_2level_tapbuf_size16_58_configbus1[907:907] , mux_2level_tapbuf_size16_58_configbus0_b[907:907] ); -sram6T_blwl sram_blwl_908_ (mux_2level_tapbuf_size16_58_sram_blwl_out[908:908] ,mux_2level_tapbuf_size16_58_sram_blwl_out[908:908] ,mux_2level_tapbuf_size16_58_sram_blwl_outb[908:908] ,mux_2level_tapbuf_size16_58_configbus0[908:908], mux_2level_tapbuf_size16_58_configbus1[908:908] , mux_2level_tapbuf_size16_58_configbus0_b[908:908] ); -sram6T_blwl sram_blwl_909_ (mux_2level_tapbuf_size16_58_sram_blwl_out[909:909] ,mux_2level_tapbuf_size16_58_sram_blwl_out[909:909] ,mux_2level_tapbuf_size16_58_sram_blwl_outb[909:909] ,mux_2level_tapbuf_size16_58_configbus0[909:909], mux_2level_tapbuf_size16_58_configbus1[909:909] , mux_2level_tapbuf_size16_58_configbus0_b[909:909] ); -sram6T_blwl sram_blwl_910_ (mux_2level_tapbuf_size16_58_sram_blwl_out[910:910] ,mux_2level_tapbuf_size16_58_sram_blwl_out[910:910] ,mux_2level_tapbuf_size16_58_sram_blwl_outb[910:910] ,mux_2level_tapbuf_size16_58_configbus0[910:910], mux_2level_tapbuf_size16_58_configbus1[910:910] , mux_2level_tapbuf_size16_58_configbus0_b[910:910] ); -sram6T_blwl sram_blwl_911_ (mux_2level_tapbuf_size16_58_sram_blwl_out[911:911] ,mux_2level_tapbuf_size16_58_sram_blwl_out[911:911] ,mux_2level_tapbuf_size16_58_sram_blwl_outb[911:911] ,mux_2level_tapbuf_size16_58_configbus0[911:911], mux_2level_tapbuf_size16_58_configbus1[911:911] , mux_2level_tapbuf_size16_58_configbus0_b[911:911] ); -wire [0:15] mux_2level_tapbuf_size16_59_inbus; -assign mux_2level_tapbuf_size16_59_inbus[0] = chany_1__1__midout_14_; -assign mux_2level_tapbuf_size16_59_inbus[1] = chany_1__1__midout_15_; -assign mux_2level_tapbuf_size16_59_inbus[2] = chany_1__1__midout_18_; -assign mux_2level_tapbuf_size16_59_inbus[3] = chany_1__1__midout_19_; -assign mux_2level_tapbuf_size16_59_inbus[4] = chany_1__1__midout_38_; -assign mux_2level_tapbuf_size16_59_inbus[5] = chany_1__1__midout_39_; -assign mux_2level_tapbuf_size16_59_inbus[6] = chany_1__1__midout_44_; -assign mux_2level_tapbuf_size16_59_inbus[7] = chany_1__1__midout_45_; -assign mux_2level_tapbuf_size16_59_inbus[8] = chany_1__1__midout_56_; -assign mux_2level_tapbuf_size16_59_inbus[9] = chany_1__1__midout_57_; -assign mux_2level_tapbuf_size16_59_inbus[10] = chany_1__1__midout_70_; -assign mux_2level_tapbuf_size16_59_inbus[11] = chany_1__1__midout_71_; -assign mux_2level_tapbuf_size16_59_inbus[12] = chany_1__1__midout_82_; -assign mux_2level_tapbuf_size16_59_inbus[13] = chany_1__1__midout_83_; -assign mux_2level_tapbuf_size16_59_inbus[14] = chany_1__1__midout_96_; -assign mux_2level_tapbuf_size16_59_inbus[15] = chany_1__1__midout_97_; -wire [912:919] mux_2level_tapbuf_size16_59_configbus0; -wire [912:919] mux_2level_tapbuf_size16_59_configbus1; -wire [912:919] mux_2level_tapbuf_size16_59_sram_blwl_out ; -wire [912:919] mux_2level_tapbuf_size16_59_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_59_configbus0[912:919] = sram_blwl_bl[912:919] ; -assign mux_2level_tapbuf_size16_59_configbus1[912:919] = sram_blwl_wl[912:919] ; -wire [912:919] mux_2level_tapbuf_size16_59_configbus0_b; -assign mux_2level_tapbuf_size16_59_configbus0_b[912:919] = sram_blwl_blb[912:919] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_59_ (mux_2level_tapbuf_size16_59_inbus, grid_2__1__pin_0__3__10_, mux_2level_tapbuf_size16_59_sram_blwl_out[912:919] , -mux_2level_tapbuf_size16_59_sram_blwl_outb[912:919] ); -//----- SRAM bits for MUX[59], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_912_ (mux_2level_tapbuf_size16_59_sram_blwl_out[912:912] ,mux_2level_tapbuf_size16_59_sram_blwl_out[912:912] ,mux_2level_tapbuf_size16_59_sram_blwl_outb[912:912] ,mux_2level_tapbuf_size16_59_configbus0[912:912], mux_2level_tapbuf_size16_59_configbus1[912:912] , mux_2level_tapbuf_size16_59_configbus0_b[912:912] ); -sram6T_blwl sram_blwl_913_ (mux_2level_tapbuf_size16_59_sram_blwl_out[913:913] ,mux_2level_tapbuf_size16_59_sram_blwl_out[913:913] ,mux_2level_tapbuf_size16_59_sram_blwl_outb[913:913] ,mux_2level_tapbuf_size16_59_configbus0[913:913], mux_2level_tapbuf_size16_59_configbus1[913:913] , mux_2level_tapbuf_size16_59_configbus0_b[913:913] ); -sram6T_blwl sram_blwl_914_ (mux_2level_tapbuf_size16_59_sram_blwl_out[914:914] ,mux_2level_tapbuf_size16_59_sram_blwl_out[914:914] ,mux_2level_tapbuf_size16_59_sram_blwl_outb[914:914] ,mux_2level_tapbuf_size16_59_configbus0[914:914], mux_2level_tapbuf_size16_59_configbus1[914:914] , mux_2level_tapbuf_size16_59_configbus0_b[914:914] ); -sram6T_blwl sram_blwl_915_ (mux_2level_tapbuf_size16_59_sram_blwl_out[915:915] ,mux_2level_tapbuf_size16_59_sram_blwl_out[915:915] ,mux_2level_tapbuf_size16_59_sram_blwl_outb[915:915] ,mux_2level_tapbuf_size16_59_configbus0[915:915], mux_2level_tapbuf_size16_59_configbus1[915:915] , mux_2level_tapbuf_size16_59_configbus0_b[915:915] ); -sram6T_blwl sram_blwl_916_ (mux_2level_tapbuf_size16_59_sram_blwl_out[916:916] ,mux_2level_tapbuf_size16_59_sram_blwl_out[916:916] ,mux_2level_tapbuf_size16_59_sram_blwl_outb[916:916] ,mux_2level_tapbuf_size16_59_configbus0[916:916], mux_2level_tapbuf_size16_59_configbus1[916:916] , mux_2level_tapbuf_size16_59_configbus0_b[916:916] ); -sram6T_blwl sram_blwl_917_ (mux_2level_tapbuf_size16_59_sram_blwl_out[917:917] ,mux_2level_tapbuf_size16_59_sram_blwl_out[917:917] ,mux_2level_tapbuf_size16_59_sram_blwl_outb[917:917] ,mux_2level_tapbuf_size16_59_configbus0[917:917], mux_2level_tapbuf_size16_59_configbus1[917:917] , mux_2level_tapbuf_size16_59_configbus0_b[917:917] ); -sram6T_blwl sram_blwl_918_ (mux_2level_tapbuf_size16_59_sram_blwl_out[918:918] ,mux_2level_tapbuf_size16_59_sram_blwl_out[918:918] ,mux_2level_tapbuf_size16_59_sram_blwl_outb[918:918] ,mux_2level_tapbuf_size16_59_configbus0[918:918], mux_2level_tapbuf_size16_59_configbus1[918:918] , mux_2level_tapbuf_size16_59_configbus0_b[918:918] ); -sram6T_blwl sram_blwl_919_ (mux_2level_tapbuf_size16_59_sram_blwl_out[919:919] ,mux_2level_tapbuf_size16_59_sram_blwl_out[919:919] ,mux_2level_tapbuf_size16_59_sram_blwl_outb[919:919] ,mux_2level_tapbuf_size16_59_configbus0[919:919], mux_2level_tapbuf_size16_59_configbus1[919:919] , mux_2level_tapbuf_size16_59_configbus0_b[919:919] ); -wire [0:15] mux_2level_tapbuf_size16_60_inbus; -assign mux_2level_tapbuf_size16_60_inbus[0] = chany_1__1__midout_8_; -assign mux_2level_tapbuf_size16_60_inbus[1] = chany_1__1__midout_9_; -assign mux_2level_tapbuf_size16_60_inbus[2] = chany_1__1__midout_20_; -assign mux_2level_tapbuf_size16_60_inbus[3] = chany_1__1__midout_21_; -assign mux_2level_tapbuf_size16_60_inbus[4] = chany_1__1__midout_32_; -assign mux_2level_tapbuf_size16_60_inbus[5] = chany_1__1__midout_33_; -assign mux_2level_tapbuf_size16_60_inbus[6] = chany_1__1__midout_50_; -assign mux_2level_tapbuf_size16_60_inbus[7] = chany_1__1__midout_51_; -assign mux_2level_tapbuf_size16_60_inbus[8] = chany_1__1__midout_62_; -assign mux_2level_tapbuf_size16_60_inbus[9] = chany_1__1__midout_63_; -assign mux_2level_tapbuf_size16_60_inbus[10] = chany_1__1__midout_72_; -assign mux_2level_tapbuf_size16_60_inbus[11] = chany_1__1__midout_73_; -assign mux_2level_tapbuf_size16_60_inbus[12] = chany_1__1__midout_84_; -assign mux_2level_tapbuf_size16_60_inbus[13] = chany_1__1__midout_85_; -assign mux_2level_tapbuf_size16_60_inbus[14] = chany_1__1__midout_98_; -assign mux_2level_tapbuf_size16_60_inbus[15] = chany_1__1__midout_99_; -wire [920:927] mux_2level_tapbuf_size16_60_configbus0; -wire [920:927] mux_2level_tapbuf_size16_60_configbus1; -wire [920:927] mux_2level_tapbuf_size16_60_sram_blwl_out ; -wire [920:927] mux_2level_tapbuf_size16_60_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_60_configbus0[920:927] = sram_blwl_bl[920:927] ; -assign mux_2level_tapbuf_size16_60_configbus1[920:927] = sram_blwl_wl[920:927] ; -wire [920:927] mux_2level_tapbuf_size16_60_configbus0_b; -assign mux_2level_tapbuf_size16_60_configbus0_b[920:927] = sram_blwl_blb[920:927] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_60_ (mux_2level_tapbuf_size16_60_inbus, grid_2__1__pin_0__3__12_, mux_2level_tapbuf_size16_60_sram_blwl_out[920:927] , -mux_2level_tapbuf_size16_60_sram_blwl_outb[920:927] ); -//----- SRAM bits for MUX[60], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_920_ (mux_2level_tapbuf_size16_60_sram_blwl_out[920:920] ,mux_2level_tapbuf_size16_60_sram_blwl_out[920:920] ,mux_2level_tapbuf_size16_60_sram_blwl_outb[920:920] ,mux_2level_tapbuf_size16_60_configbus0[920:920], mux_2level_tapbuf_size16_60_configbus1[920:920] , mux_2level_tapbuf_size16_60_configbus0_b[920:920] ); -sram6T_blwl sram_blwl_921_ (mux_2level_tapbuf_size16_60_sram_blwl_out[921:921] ,mux_2level_tapbuf_size16_60_sram_blwl_out[921:921] ,mux_2level_tapbuf_size16_60_sram_blwl_outb[921:921] ,mux_2level_tapbuf_size16_60_configbus0[921:921], mux_2level_tapbuf_size16_60_configbus1[921:921] , mux_2level_tapbuf_size16_60_configbus0_b[921:921] ); -sram6T_blwl sram_blwl_922_ (mux_2level_tapbuf_size16_60_sram_blwl_out[922:922] ,mux_2level_tapbuf_size16_60_sram_blwl_out[922:922] ,mux_2level_tapbuf_size16_60_sram_blwl_outb[922:922] ,mux_2level_tapbuf_size16_60_configbus0[922:922], mux_2level_tapbuf_size16_60_configbus1[922:922] , mux_2level_tapbuf_size16_60_configbus0_b[922:922] ); -sram6T_blwl sram_blwl_923_ (mux_2level_tapbuf_size16_60_sram_blwl_out[923:923] ,mux_2level_tapbuf_size16_60_sram_blwl_out[923:923] ,mux_2level_tapbuf_size16_60_sram_blwl_outb[923:923] ,mux_2level_tapbuf_size16_60_configbus0[923:923], mux_2level_tapbuf_size16_60_configbus1[923:923] , mux_2level_tapbuf_size16_60_configbus0_b[923:923] ); -sram6T_blwl sram_blwl_924_ (mux_2level_tapbuf_size16_60_sram_blwl_out[924:924] ,mux_2level_tapbuf_size16_60_sram_blwl_out[924:924] ,mux_2level_tapbuf_size16_60_sram_blwl_outb[924:924] ,mux_2level_tapbuf_size16_60_configbus0[924:924], mux_2level_tapbuf_size16_60_configbus1[924:924] , mux_2level_tapbuf_size16_60_configbus0_b[924:924] ); -sram6T_blwl sram_blwl_925_ (mux_2level_tapbuf_size16_60_sram_blwl_out[925:925] ,mux_2level_tapbuf_size16_60_sram_blwl_out[925:925] ,mux_2level_tapbuf_size16_60_sram_blwl_outb[925:925] ,mux_2level_tapbuf_size16_60_configbus0[925:925], mux_2level_tapbuf_size16_60_configbus1[925:925] , mux_2level_tapbuf_size16_60_configbus0_b[925:925] ); -sram6T_blwl sram_blwl_926_ (mux_2level_tapbuf_size16_60_sram_blwl_out[926:926] ,mux_2level_tapbuf_size16_60_sram_blwl_out[926:926] ,mux_2level_tapbuf_size16_60_sram_blwl_outb[926:926] ,mux_2level_tapbuf_size16_60_configbus0[926:926], mux_2level_tapbuf_size16_60_configbus1[926:926] , mux_2level_tapbuf_size16_60_configbus0_b[926:926] ); -sram6T_blwl sram_blwl_927_ (mux_2level_tapbuf_size16_60_sram_blwl_out[927:927] ,mux_2level_tapbuf_size16_60_sram_blwl_out[927:927] ,mux_2level_tapbuf_size16_60_sram_blwl_outb[927:927] ,mux_2level_tapbuf_size16_60_configbus0[927:927], mux_2level_tapbuf_size16_60_configbus1[927:927] , mux_2level_tapbuf_size16_60_configbus0_b[927:927] ); -wire [0:15] mux_2level_tapbuf_size16_61_inbus; -assign mux_2level_tapbuf_size16_61_inbus[0] = chany_1__1__midout_10_; -assign mux_2level_tapbuf_size16_61_inbus[1] = chany_1__1__midout_11_; -assign mux_2level_tapbuf_size16_61_inbus[2] = chany_1__1__midout_30_; -assign mux_2level_tapbuf_size16_61_inbus[3] = chany_1__1__midout_31_; -assign mux_2level_tapbuf_size16_61_inbus[4] = chany_1__1__midout_34_; -assign mux_2level_tapbuf_size16_61_inbus[5] = chany_1__1__midout_35_; -assign mux_2level_tapbuf_size16_61_inbus[6] = chany_1__1__midout_50_; -assign mux_2level_tapbuf_size16_61_inbus[7] = chany_1__1__midout_51_; -assign mux_2level_tapbuf_size16_61_inbus[8] = chany_1__1__midout_60_; -assign mux_2level_tapbuf_size16_61_inbus[9] = chany_1__1__midout_61_; -assign mux_2level_tapbuf_size16_61_inbus[10] = chany_1__1__midout_74_; -assign mux_2level_tapbuf_size16_61_inbus[11] = chany_1__1__midout_75_; -assign mux_2level_tapbuf_size16_61_inbus[12] = chany_1__1__midout_86_; -assign mux_2level_tapbuf_size16_61_inbus[13] = chany_1__1__midout_87_; -assign mux_2level_tapbuf_size16_61_inbus[14] = chany_1__1__midout_98_; -assign mux_2level_tapbuf_size16_61_inbus[15] = chany_1__1__midout_99_; -wire [928:935] mux_2level_tapbuf_size16_61_configbus0; -wire [928:935] mux_2level_tapbuf_size16_61_configbus1; -wire [928:935] mux_2level_tapbuf_size16_61_sram_blwl_out ; -wire [928:935] mux_2level_tapbuf_size16_61_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_61_configbus0[928:935] = sram_blwl_bl[928:935] ; -assign mux_2level_tapbuf_size16_61_configbus1[928:935] = sram_blwl_wl[928:935] ; -wire [928:935] mux_2level_tapbuf_size16_61_configbus0_b; -assign mux_2level_tapbuf_size16_61_configbus0_b[928:935] = sram_blwl_blb[928:935] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_61_ (mux_2level_tapbuf_size16_61_inbus, grid_2__1__pin_0__3__14_, mux_2level_tapbuf_size16_61_sram_blwl_out[928:935] , -mux_2level_tapbuf_size16_61_sram_blwl_outb[928:935] ); -//----- SRAM bits for MUX[61], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_928_ (mux_2level_tapbuf_size16_61_sram_blwl_out[928:928] ,mux_2level_tapbuf_size16_61_sram_blwl_out[928:928] ,mux_2level_tapbuf_size16_61_sram_blwl_outb[928:928] ,mux_2level_tapbuf_size16_61_configbus0[928:928], mux_2level_tapbuf_size16_61_configbus1[928:928] , mux_2level_tapbuf_size16_61_configbus0_b[928:928] ); -sram6T_blwl sram_blwl_929_ (mux_2level_tapbuf_size16_61_sram_blwl_out[929:929] ,mux_2level_tapbuf_size16_61_sram_blwl_out[929:929] ,mux_2level_tapbuf_size16_61_sram_blwl_outb[929:929] ,mux_2level_tapbuf_size16_61_configbus0[929:929], mux_2level_tapbuf_size16_61_configbus1[929:929] , mux_2level_tapbuf_size16_61_configbus0_b[929:929] ); -sram6T_blwl sram_blwl_930_ (mux_2level_tapbuf_size16_61_sram_blwl_out[930:930] ,mux_2level_tapbuf_size16_61_sram_blwl_out[930:930] ,mux_2level_tapbuf_size16_61_sram_blwl_outb[930:930] ,mux_2level_tapbuf_size16_61_configbus0[930:930], mux_2level_tapbuf_size16_61_configbus1[930:930] , mux_2level_tapbuf_size16_61_configbus0_b[930:930] ); -sram6T_blwl sram_blwl_931_ (mux_2level_tapbuf_size16_61_sram_blwl_out[931:931] ,mux_2level_tapbuf_size16_61_sram_blwl_out[931:931] ,mux_2level_tapbuf_size16_61_sram_blwl_outb[931:931] ,mux_2level_tapbuf_size16_61_configbus0[931:931], mux_2level_tapbuf_size16_61_configbus1[931:931] , mux_2level_tapbuf_size16_61_configbus0_b[931:931] ); -sram6T_blwl sram_blwl_932_ (mux_2level_tapbuf_size16_61_sram_blwl_out[932:932] ,mux_2level_tapbuf_size16_61_sram_blwl_out[932:932] ,mux_2level_tapbuf_size16_61_sram_blwl_outb[932:932] ,mux_2level_tapbuf_size16_61_configbus0[932:932], mux_2level_tapbuf_size16_61_configbus1[932:932] , mux_2level_tapbuf_size16_61_configbus0_b[932:932] ); -sram6T_blwl sram_blwl_933_ (mux_2level_tapbuf_size16_61_sram_blwl_out[933:933] ,mux_2level_tapbuf_size16_61_sram_blwl_out[933:933] ,mux_2level_tapbuf_size16_61_sram_blwl_outb[933:933] ,mux_2level_tapbuf_size16_61_configbus0[933:933], mux_2level_tapbuf_size16_61_configbus1[933:933] , mux_2level_tapbuf_size16_61_configbus0_b[933:933] ); -sram6T_blwl sram_blwl_934_ (mux_2level_tapbuf_size16_61_sram_blwl_out[934:934] ,mux_2level_tapbuf_size16_61_sram_blwl_out[934:934] ,mux_2level_tapbuf_size16_61_sram_blwl_outb[934:934] ,mux_2level_tapbuf_size16_61_configbus0[934:934], mux_2level_tapbuf_size16_61_configbus1[934:934] , mux_2level_tapbuf_size16_61_configbus0_b[934:934] ); -sram6T_blwl sram_blwl_935_ (mux_2level_tapbuf_size16_61_sram_blwl_out[935:935] ,mux_2level_tapbuf_size16_61_sram_blwl_out[935:935] ,mux_2level_tapbuf_size16_61_sram_blwl_outb[935:935] ,mux_2level_tapbuf_size16_61_configbus0[935:935], mux_2level_tapbuf_size16_61_configbus1[935:935] , mux_2level_tapbuf_size16_61_configbus0_b[935:935] ); -wire [0:15] mux_2level_tapbuf_size16_62_inbus; -assign mux_2level_tapbuf_size16_62_inbus[0] = chany_1__1__midout_6_; -assign mux_2level_tapbuf_size16_62_inbus[1] = chany_1__1__midout_7_; -assign mux_2level_tapbuf_size16_62_inbus[2] = chany_1__1__midout_10_; -assign mux_2level_tapbuf_size16_62_inbus[3] = chany_1__1__midout_11_; -assign mux_2level_tapbuf_size16_62_inbus[4] = chany_1__1__midout_30_; -assign mux_2level_tapbuf_size16_62_inbus[5] = chany_1__1__midout_31_; -assign mux_2level_tapbuf_size16_62_inbus[6] = chany_1__1__midout_34_; -assign mux_2level_tapbuf_size16_62_inbus[7] = chany_1__1__midout_35_; -assign mux_2level_tapbuf_size16_62_inbus[8] = chany_1__1__midout_48_; -assign mux_2level_tapbuf_size16_62_inbus[9] = chany_1__1__midout_49_; -assign mux_2level_tapbuf_size16_62_inbus[10] = chany_1__1__midout_60_; -assign mux_2level_tapbuf_size16_62_inbus[11] = chany_1__1__midout_61_; -assign mux_2level_tapbuf_size16_62_inbus[12] = chany_1__1__midout_74_; -assign mux_2level_tapbuf_size16_62_inbus[13] = chany_1__1__midout_75_; -assign mux_2level_tapbuf_size16_62_inbus[14] = chany_1__1__midout_86_; -assign mux_2level_tapbuf_size16_62_inbus[15] = chany_1__1__midout_87_; -wire [936:943] mux_2level_tapbuf_size16_62_configbus0; -wire [936:943] mux_2level_tapbuf_size16_62_configbus1; -wire [936:943] mux_2level_tapbuf_size16_62_sram_blwl_out ; -wire [936:943] mux_2level_tapbuf_size16_62_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_62_configbus0[936:943] = sram_blwl_bl[936:943] ; -assign mux_2level_tapbuf_size16_62_configbus1[936:943] = sram_blwl_wl[936:943] ; -wire [936:943] mux_2level_tapbuf_size16_62_configbus0_b; -assign mux_2level_tapbuf_size16_62_configbus0_b[936:943] = sram_blwl_blb[936:943] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_62_ (mux_2level_tapbuf_size16_62_inbus, grid_1__1__pin_0__1__1_, mux_2level_tapbuf_size16_62_sram_blwl_out[936:943] , -mux_2level_tapbuf_size16_62_sram_blwl_outb[936:943] ); -//----- SRAM bits for MUX[62], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_936_ (mux_2level_tapbuf_size16_62_sram_blwl_out[936:936] ,mux_2level_tapbuf_size16_62_sram_blwl_out[936:936] ,mux_2level_tapbuf_size16_62_sram_blwl_outb[936:936] ,mux_2level_tapbuf_size16_62_configbus0[936:936], mux_2level_tapbuf_size16_62_configbus1[936:936] , mux_2level_tapbuf_size16_62_configbus0_b[936:936] ); -sram6T_blwl sram_blwl_937_ (mux_2level_tapbuf_size16_62_sram_blwl_out[937:937] ,mux_2level_tapbuf_size16_62_sram_blwl_out[937:937] ,mux_2level_tapbuf_size16_62_sram_blwl_outb[937:937] ,mux_2level_tapbuf_size16_62_configbus0[937:937], mux_2level_tapbuf_size16_62_configbus1[937:937] , mux_2level_tapbuf_size16_62_configbus0_b[937:937] ); -sram6T_blwl sram_blwl_938_ (mux_2level_tapbuf_size16_62_sram_blwl_out[938:938] ,mux_2level_tapbuf_size16_62_sram_blwl_out[938:938] ,mux_2level_tapbuf_size16_62_sram_blwl_outb[938:938] ,mux_2level_tapbuf_size16_62_configbus0[938:938], mux_2level_tapbuf_size16_62_configbus1[938:938] , mux_2level_tapbuf_size16_62_configbus0_b[938:938] ); -sram6T_blwl sram_blwl_939_ (mux_2level_tapbuf_size16_62_sram_blwl_out[939:939] ,mux_2level_tapbuf_size16_62_sram_blwl_out[939:939] ,mux_2level_tapbuf_size16_62_sram_blwl_outb[939:939] ,mux_2level_tapbuf_size16_62_configbus0[939:939], mux_2level_tapbuf_size16_62_configbus1[939:939] , mux_2level_tapbuf_size16_62_configbus0_b[939:939] ); -sram6T_blwl sram_blwl_940_ (mux_2level_tapbuf_size16_62_sram_blwl_out[940:940] ,mux_2level_tapbuf_size16_62_sram_blwl_out[940:940] ,mux_2level_tapbuf_size16_62_sram_blwl_outb[940:940] ,mux_2level_tapbuf_size16_62_configbus0[940:940], mux_2level_tapbuf_size16_62_configbus1[940:940] , mux_2level_tapbuf_size16_62_configbus0_b[940:940] ); -sram6T_blwl sram_blwl_941_ (mux_2level_tapbuf_size16_62_sram_blwl_out[941:941] ,mux_2level_tapbuf_size16_62_sram_blwl_out[941:941] ,mux_2level_tapbuf_size16_62_sram_blwl_outb[941:941] ,mux_2level_tapbuf_size16_62_configbus0[941:941], mux_2level_tapbuf_size16_62_configbus1[941:941] , mux_2level_tapbuf_size16_62_configbus0_b[941:941] ); -sram6T_blwl sram_blwl_942_ (mux_2level_tapbuf_size16_62_sram_blwl_out[942:942] ,mux_2level_tapbuf_size16_62_sram_blwl_out[942:942] ,mux_2level_tapbuf_size16_62_sram_blwl_outb[942:942] ,mux_2level_tapbuf_size16_62_configbus0[942:942], mux_2level_tapbuf_size16_62_configbus1[942:942] , mux_2level_tapbuf_size16_62_configbus0_b[942:942] ); -sram6T_blwl sram_blwl_943_ (mux_2level_tapbuf_size16_62_sram_blwl_out[943:943] ,mux_2level_tapbuf_size16_62_sram_blwl_out[943:943] ,mux_2level_tapbuf_size16_62_sram_blwl_outb[943:943] ,mux_2level_tapbuf_size16_62_configbus0[943:943], mux_2level_tapbuf_size16_62_configbus1[943:943] , mux_2level_tapbuf_size16_62_configbus0_b[943:943] ); -wire [0:15] mux_2level_tapbuf_size16_63_inbus; -assign mux_2level_tapbuf_size16_63_inbus[0] = chany_1__1__midout_6_; -assign mux_2level_tapbuf_size16_63_inbus[1] = chany_1__1__midout_7_; -assign mux_2level_tapbuf_size16_63_inbus[2] = chany_1__1__midout_12_; -assign mux_2level_tapbuf_size16_63_inbus[3] = chany_1__1__midout_13_; -assign mux_2level_tapbuf_size16_63_inbus[4] = chany_1__1__midout_24_; -assign mux_2level_tapbuf_size16_63_inbus[5] = chany_1__1__midout_25_; -assign mux_2level_tapbuf_size16_63_inbus[6] = chany_1__1__midout_36_; -assign mux_2level_tapbuf_size16_63_inbus[7] = chany_1__1__midout_37_; -assign mux_2level_tapbuf_size16_63_inbus[8] = chany_1__1__midout_48_; -assign mux_2level_tapbuf_size16_63_inbus[9] = chany_1__1__midout_49_; -assign mux_2level_tapbuf_size16_63_inbus[10] = chany_1__1__midout_66_; -assign mux_2level_tapbuf_size16_63_inbus[11] = chany_1__1__midout_67_; -assign mux_2level_tapbuf_size16_63_inbus[12] = chany_1__1__midout_76_; -assign mux_2level_tapbuf_size16_63_inbus[13] = chany_1__1__midout_77_; -assign mux_2level_tapbuf_size16_63_inbus[14] = chany_1__1__midout_88_; -assign mux_2level_tapbuf_size16_63_inbus[15] = chany_1__1__midout_89_; -wire [944:951] mux_2level_tapbuf_size16_63_configbus0; -wire [944:951] mux_2level_tapbuf_size16_63_configbus1; -wire [944:951] mux_2level_tapbuf_size16_63_sram_blwl_out ; -wire [944:951] mux_2level_tapbuf_size16_63_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_63_configbus0[944:951] = sram_blwl_bl[944:951] ; -assign mux_2level_tapbuf_size16_63_configbus1[944:951] = sram_blwl_wl[944:951] ; -wire [944:951] mux_2level_tapbuf_size16_63_configbus0_b; -assign mux_2level_tapbuf_size16_63_configbus0_b[944:951] = sram_blwl_blb[944:951] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_63_ (mux_2level_tapbuf_size16_63_inbus, grid_1__1__pin_0__1__5_, mux_2level_tapbuf_size16_63_sram_blwl_out[944:951] , -mux_2level_tapbuf_size16_63_sram_blwl_outb[944:951] ); -//----- SRAM bits for MUX[63], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_944_ (mux_2level_tapbuf_size16_63_sram_blwl_out[944:944] ,mux_2level_tapbuf_size16_63_sram_blwl_out[944:944] ,mux_2level_tapbuf_size16_63_sram_blwl_outb[944:944] ,mux_2level_tapbuf_size16_63_configbus0[944:944], mux_2level_tapbuf_size16_63_configbus1[944:944] , mux_2level_tapbuf_size16_63_configbus0_b[944:944] ); -sram6T_blwl sram_blwl_945_ (mux_2level_tapbuf_size16_63_sram_blwl_out[945:945] ,mux_2level_tapbuf_size16_63_sram_blwl_out[945:945] ,mux_2level_tapbuf_size16_63_sram_blwl_outb[945:945] ,mux_2level_tapbuf_size16_63_configbus0[945:945], mux_2level_tapbuf_size16_63_configbus1[945:945] , mux_2level_tapbuf_size16_63_configbus0_b[945:945] ); -sram6T_blwl sram_blwl_946_ (mux_2level_tapbuf_size16_63_sram_blwl_out[946:946] ,mux_2level_tapbuf_size16_63_sram_blwl_out[946:946] ,mux_2level_tapbuf_size16_63_sram_blwl_outb[946:946] ,mux_2level_tapbuf_size16_63_configbus0[946:946], mux_2level_tapbuf_size16_63_configbus1[946:946] , mux_2level_tapbuf_size16_63_configbus0_b[946:946] ); -sram6T_blwl sram_blwl_947_ (mux_2level_tapbuf_size16_63_sram_blwl_out[947:947] ,mux_2level_tapbuf_size16_63_sram_blwl_out[947:947] ,mux_2level_tapbuf_size16_63_sram_blwl_outb[947:947] ,mux_2level_tapbuf_size16_63_configbus0[947:947], mux_2level_tapbuf_size16_63_configbus1[947:947] , mux_2level_tapbuf_size16_63_configbus0_b[947:947] ); -sram6T_blwl sram_blwl_948_ (mux_2level_tapbuf_size16_63_sram_blwl_out[948:948] ,mux_2level_tapbuf_size16_63_sram_blwl_out[948:948] ,mux_2level_tapbuf_size16_63_sram_blwl_outb[948:948] ,mux_2level_tapbuf_size16_63_configbus0[948:948], mux_2level_tapbuf_size16_63_configbus1[948:948] , mux_2level_tapbuf_size16_63_configbus0_b[948:948] ); -sram6T_blwl sram_blwl_949_ (mux_2level_tapbuf_size16_63_sram_blwl_out[949:949] ,mux_2level_tapbuf_size16_63_sram_blwl_out[949:949] ,mux_2level_tapbuf_size16_63_sram_blwl_outb[949:949] ,mux_2level_tapbuf_size16_63_configbus0[949:949], mux_2level_tapbuf_size16_63_configbus1[949:949] , mux_2level_tapbuf_size16_63_configbus0_b[949:949] ); -sram6T_blwl sram_blwl_950_ (mux_2level_tapbuf_size16_63_sram_blwl_out[950:950] ,mux_2level_tapbuf_size16_63_sram_blwl_out[950:950] ,mux_2level_tapbuf_size16_63_sram_blwl_outb[950:950] ,mux_2level_tapbuf_size16_63_configbus0[950:950], mux_2level_tapbuf_size16_63_configbus1[950:950] , mux_2level_tapbuf_size16_63_configbus0_b[950:950] ); -sram6T_blwl sram_blwl_951_ (mux_2level_tapbuf_size16_63_sram_blwl_out[951:951] ,mux_2level_tapbuf_size16_63_sram_blwl_out[951:951] ,mux_2level_tapbuf_size16_63_sram_blwl_outb[951:951] ,mux_2level_tapbuf_size16_63_configbus0[951:951], mux_2level_tapbuf_size16_63_configbus1[951:951] , mux_2level_tapbuf_size16_63_configbus0_b[951:951] ); -wire [0:15] mux_2level_tapbuf_size16_64_inbus; -assign mux_2level_tapbuf_size16_64_inbus[0] = chany_1__1__midout_0_; -assign mux_2level_tapbuf_size16_64_inbus[1] = chany_1__1__midout_1_; -assign mux_2level_tapbuf_size16_64_inbus[2] = chany_1__1__midout_12_; -assign mux_2level_tapbuf_size16_64_inbus[3] = chany_1__1__midout_13_; -assign mux_2level_tapbuf_size16_64_inbus[4] = chany_1__1__midout_24_; -assign mux_2level_tapbuf_size16_64_inbus[5] = chany_1__1__midout_25_; -assign mux_2level_tapbuf_size16_64_inbus[6] = chany_1__1__midout_42_; -assign mux_2level_tapbuf_size16_64_inbus[7] = chany_1__1__midout_43_; -assign mux_2level_tapbuf_size16_64_inbus[8] = chany_1__1__midout_54_; -assign mux_2level_tapbuf_size16_64_inbus[9] = chany_1__1__midout_55_; -assign mux_2level_tapbuf_size16_64_inbus[10] = chany_1__1__midout_66_; -assign mux_2level_tapbuf_size16_64_inbus[11] = chany_1__1__midout_67_; -assign mux_2level_tapbuf_size16_64_inbus[12] = chany_1__1__midout_76_; -assign mux_2level_tapbuf_size16_64_inbus[13] = chany_1__1__midout_77_; -assign mux_2level_tapbuf_size16_64_inbus[14] = chany_1__1__midout_90_; -assign mux_2level_tapbuf_size16_64_inbus[15] = chany_1__1__midout_91_; -wire [952:959] mux_2level_tapbuf_size16_64_configbus0; -wire [952:959] mux_2level_tapbuf_size16_64_configbus1; -wire [952:959] mux_2level_tapbuf_size16_64_sram_blwl_out ; -wire [952:959] mux_2level_tapbuf_size16_64_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_64_configbus0[952:959] = sram_blwl_bl[952:959] ; -assign mux_2level_tapbuf_size16_64_configbus1[952:959] = sram_blwl_wl[952:959] ; -wire [952:959] mux_2level_tapbuf_size16_64_configbus0_b; -assign mux_2level_tapbuf_size16_64_configbus0_b[952:959] = sram_blwl_blb[952:959] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_64_ (mux_2level_tapbuf_size16_64_inbus, grid_1__1__pin_0__1__9_, mux_2level_tapbuf_size16_64_sram_blwl_out[952:959] , -mux_2level_tapbuf_size16_64_sram_blwl_outb[952:959] ); -//----- SRAM bits for MUX[64], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_952_ (mux_2level_tapbuf_size16_64_sram_blwl_out[952:952] ,mux_2level_tapbuf_size16_64_sram_blwl_out[952:952] ,mux_2level_tapbuf_size16_64_sram_blwl_outb[952:952] ,mux_2level_tapbuf_size16_64_configbus0[952:952], mux_2level_tapbuf_size16_64_configbus1[952:952] , mux_2level_tapbuf_size16_64_configbus0_b[952:952] ); -sram6T_blwl sram_blwl_953_ (mux_2level_tapbuf_size16_64_sram_blwl_out[953:953] ,mux_2level_tapbuf_size16_64_sram_blwl_out[953:953] ,mux_2level_tapbuf_size16_64_sram_blwl_outb[953:953] ,mux_2level_tapbuf_size16_64_configbus0[953:953], mux_2level_tapbuf_size16_64_configbus1[953:953] , mux_2level_tapbuf_size16_64_configbus0_b[953:953] ); -sram6T_blwl sram_blwl_954_ (mux_2level_tapbuf_size16_64_sram_blwl_out[954:954] ,mux_2level_tapbuf_size16_64_sram_blwl_out[954:954] ,mux_2level_tapbuf_size16_64_sram_blwl_outb[954:954] ,mux_2level_tapbuf_size16_64_configbus0[954:954], mux_2level_tapbuf_size16_64_configbus1[954:954] , mux_2level_tapbuf_size16_64_configbus0_b[954:954] ); -sram6T_blwl sram_blwl_955_ (mux_2level_tapbuf_size16_64_sram_blwl_out[955:955] ,mux_2level_tapbuf_size16_64_sram_blwl_out[955:955] ,mux_2level_tapbuf_size16_64_sram_blwl_outb[955:955] ,mux_2level_tapbuf_size16_64_configbus0[955:955], mux_2level_tapbuf_size16_64_configbus1[955:955] , mux_2level_tapbuf_size16_64_configbus0_b[955:955] ); -sram6T_blwl sram_blwl_956_ (mux_2level_tapbuf_size16_64_sram_blwl_out[956:956] ,mux_2level_tapbuf_size16_64_sram_blwl_out[956:956] ,mux_2level_tapbuf_size16_64_sram_blwl_outb[956:956] ,mux_2level_tapbuf_size16_64_configbus0[956:956], mux_2level_tapbuf_size16_64_configbus1[956:956] , mux_2level_tapbuf_size16_64_configbus0_b[956:956] ); -sram6T_blwl sram_blwl_957_ (mux_2level_tapbuf_size16_64_sram_blwl_out[957:957] ,mux_2level_tapbuf_size16_64_sram_blwl_out[957:957] ,mux_2level_tapbuf_size16_64_sram_blwl_outb[957:957] ,mux_2level_tapbuf_size16_64_configbus0[957:957], mux_2level_tapbuf_size16_64_configbus1[957:957] , mux_2level_tapbuf_size16_64_configbus0_b[957:957] ); -sram6T_blwl sram_blwl_958_ (mux_2level_tapbuf_size16_64_sram_blwl_out[958:958] ,mux_2level_tapbuf_size16_64_sram_blwl_out[958:958] ,mux_2level_tapbuf_size16_64_sram_blwl_outb[958:958] ,mux_2level_tapbuf_size16_64_configbus0[958:958], mux_2level_tapbuf_size16_64_configbus1[958:958] , mux_2level_tapbuf_size16_64_configbus0_b[958:958] ); -sram6T_blwl sram_blwl_959_ (mux_2level_tapbuf_size16_64_sram_blwl_out[959:959] ,mux_2level_tapbuf_size16_64_sram_blwl_out[959:959] ,mux_2level_tapbuf_size16_64_sram_blwl_outb[959:959] ,mux_2level_tapbuf_size16_64_configbus0[959:959], mux_2level_tapbuf_size16_64_configbus1[959:959] , mux_2level_tapbuf_size16_64_configbus0_b[959:959] ); -wire [0:15] mux_2level_tapbuf_size16_65_inbus; -assign mux_2level_tapbuf_size16_65_inbus[0] = chany_1__1__midout_2_; -assign mux_2level_tapbuf_size16_65_inbus[1] = chany_1__1__midout_3_; -assign mux_2level_tapbuf_size16_65_inbus[2] = chany_1__1__midout_22_; -assign mux_2level_tapbuf_size16_65_inbus[3] = chany_1__1__midout_23_; -assign mux_2level_tapbuf_size16_65_inbus[4] = chany_1__1__midout_26_; -assign mux_2level_tapbuf_size16_65_inbus[5] = chany_1__1__midout_27_; -assign mux_2level_tapbuf_size16_65_inbus[6] = chany_1__1__midout_42_; -assign mux_2level_tapbuf_size16_65_inbus[7] = chany_1__1__midout_43_; -assign mux_2level_tapbuf_size16_65_inbus[8] = chany_1__1__midout_52_; -assign mux_2level_tapbuf_size16_65_inbus[9] = chany_1__1__midout_53_; -assign mux_2level_tapbuf_size16_65_inbus[10] = chany_1__1__midout_64_; -assign mux_2level_tapbuf_size16_65_inbus[11] = chany_1__1__midout_65_; -assign mux_2level_tapbuf_size16_65_inbus[12] = chany_1__1__midout_78_; -assign mux_2level_tapbuf_size16_65_inbus[13] = chany_1__1__midout_79_; -assign mux_2level_tapbuf_size16_65_inbus[14] = chany_1__1__midout_90_; -assign mux_2level_tapbuf_size16_65_inbus[15] = chany_1__1__midout_91_; -wire [960:967] mux_2level_tapbuf_size16_65_configbus0; -wire [960:967] mux_2level_tapbuf_size16_65_configbus1; -wire [960:967] mux_2level_tapbuf_size16_65_sram_blwl_out ; -wire [960:967] mux_2level_tapbuf_size16_65_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_65_configbus0[960:967] = sram_blwl_bl[960:967] ; -assign mux_2level_tapbuf_size16_65_configbus1[960:967] = sram_blwl_wl[960:967] ; -wire [960:967] mux_2level_tapbuf_size16_65_configbus0_b; -assign mux_2level_tapbuf_size16_65_configbus0_b[960:967] = sram_blwl_blb[960:967] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_65_ (mux_2level_tapbuf_size16_65_inbus, grid_1__1__pin_0__1__13_, mux_2level_tapbuf_size16_65_sram_blwl_out[960:967] , -mux_2level_tapbuf_size16_65_sram_blwl_outb[960:967] ); -//----- SRAM bits for MUX[65], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_960_ (mux_2level_tapbuf_size16_65_sram_blwl_out[960:960] ,mux_2level_tapbuf_size16_65_sram_blwl_out[960:960] ,mux_2level_tapbuf_size16_65_sram_blwl_outb[960:960] ,mux_2level_tapbuf_size16_65_configbus0[960:960], mux_2level_tapbuf_size16_65_configbus1[960:960] , mux_2level_tapbuf_size16_65_configbus0_b[960:960] ); -sram6T_blwl sram_blwl_961_ (mux_2level_tapbuf_size16_65_sram_blwl_out[961:961] ,mux_2level_tapbuf_size16_65_sram_blwl_out[961:961] ,mux_2level_tapbuf_size16_65_sram_blwl_outb[961:961] ,mux_2level_tapbuf_size16_65_configbus0[961:961], mux_2level_tapbuf_size16_65_configbus1[961:961] , mux_2level_tapbuf_size16_65_configbus0_b[961:961] ); -sram6T_blwl sram_blwl_962_ (mux_2level_tapbuf_size16_65_sram_blwl_out[962:962] ,mux_2level_tapbuf_size16_65_sram_blwl_out[962:962] ,mux_2level_tapbuf_size16_65_sram_blwl_outb[962:962] ,mux_2level_tapbuf_size16_65_configbus0[962:962], mux_2level_tapbuf_size16_65_configbus1[962:962] , mux_2level_tapbuf_size16_65_configbus0_b[962:962] ); -sram6T_blwl sram_blwl_963_ (mux_2level_tapbuf_size16_65_sram_blwl_out[963:963] ,mux_2level_tapbuf_size16_65_sram_blwl_out[963:963] ,mux_2level_tapbuf_size16_65_sram_blwl_outb[963:963] ,mux_2level_tapbuf_size16_65_configbus0[963:963], mux_2level_tapbuf_size16_65_configbus1[963:963] , mux_2level_tapbuf_size16_65_configbus0_b[963:963] ); -sram6T_blwl sram_blwl_964_ (mux_2level_tapbuf_size16_65_sram_blwl_out[964:964] ,mux_2level_tapbuf_size16_65_sram_blwl_out[964:964] ,mux_2level_tapbuf_size16_65_sram_blwl_outb[964:964] ,mux_2level_tapbuf_size16_65_configbus0[964:964], mux_2level_tapbuf_size16_65_configbus1[964:964] , mux_2level_tapbuf_size16_65_configbus0_b[964:964] ); -sram6T_blwl sram_blwl_965_ (mux_2level_tapbuf_size16_65_sram_blwl_out[965:965] ,mux_2level_tapbuf_size16_65_sram_blwl_out[965:965] ,mux_2level_tapbuf_size16_65_sram_blwl_outb[965:965] ,mux_2level_tapbuf_size16_65_configbus0[965:965], mux_2level_tapbuf_size16_65_configbus1[965:965] , mux_2level_tapbuf_size16_65_configbus0_b[965:965] ); -sram6T_blwl sram_blwl_966_ (mux_2level_tapbuf_size16_65_sram_blwl_out[966:966] ,mux_2level_tapbuf_size16_65_sram_blwl_out[966:966] ,mux_2level_tapbuf_size16_65_sram_blwl_outb[966:966] ,mux_2level_tapbuf_size16_65_configbus0[966:966], mux_2level_tapbuf_size16_65_configbus1[966:966] , mux_2level_tapbuf_size16_65_configbus0_b[966:966] ); -sram6T_blwl sram_blwl_967_ (mux_2level_tapbuf_size16_65_sram_blwl_out[967:967] ,mux_2level_tapbuf_size16_65_sram_blwl_out[967:967] ,mux_2level_tapbuf_size16_65_sram_blwl_outb[967:967] ,mux_2level_tapbuf_size16_65_configbus0[967:967], mux_2level_tapbuf_size16_65_configbus1[967:967] , mux_2level_tapbuf_size16_65_configbus0_b[967:967] ); -wire [0:15] mux_2level_tapbuf_size16_66_inbus; -assign mux_2level_tapbuf_size16_66_inbus[0] = chany_1__1__midout_2_; -assign mux_2level_tapbuf_size16_66_inbus[1] = chany_1__1__midout_3_; -assign mux_2level_tapbuf_size16_66_inbus[2] = chany_1__1__midout_22_; -assign mux_2level_tapbuf_size16_66_inbus[3] = chany_1__1__midout_23_; -assign mux_2level_tapbuf_size16_66_inbus[4] = chany_1__1__midout_28_; -assign mux_2level_tapbuf_size16_66_inbus[5] = chany_1__1__midout_29_; -assign mux_2level_tapbuf_size16_66_inbus[6] = chany_1__1__midout_40_; -assign mux_2level_tapbuf_size16_66_inbus[7] = chany_1__1__midout_41_; -assign mux_2level_tapbuf_size16_66_inbus[8] = chany_1__1__midout_52_; -assign mux_2level_tapbuf_size16_66_inbus[9] = chany_1__1__midout_53_; -assign mux_2level_tapbuf_size16_66_inbus[10] = chany_1__1__midout_64_; -assign mux_2level_tapbuf_size16_66_inbus[11] = chany_1__1__midout_65_; -assign mux_2level_tapbuf_size16_66_inbus[12] = chany_1__1__midout_80_; -assign mux_2level_tapbuf_size16_66_inbus[13] = chany_1__1__midout_81_; -assign mux_2level_tapbuf_size16_66_inbus[14] = chany_1__1__midout_92_; -assign mux_2level_tapbuf_size16_66_inbus[15] = chany_1__1__midout_93_; -wire [968:975] mux_2level_tapbuf_size16_66_configbus0; -wire [968:975] mux_2level_tapbuf_size16_66_configbus1; -wire [968:975] mux_2level_tapbuf_size16_66_sram_blwl_out ; -wire [968:975] mux_2level_tapbuf_size16_66_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_66_configbus0[968:975] = sram_blwl_bl[968:975] ; -assign mux_2level_tapbuf_size16_66_configbus1[968:975] = sram_blwl_wl[968:975] ; -wire [968:975] mux_2level_tapbuf_size16_66_configbus0_b; -assign mux_2level_tapbuf_size16_66_configbus0_b[968:975] = sram_blwl_blb[968:975] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_66_ (mux_2level_tapbuf_size16_66_inbus, grid_1__1__pin_0__1__17_, mux_2level_tapbuf_size16_66_sram_blwl_out[968:975] , -mux_2level_tapbuf_size16_66_sram_blwl_outb[968:975] ); -//----- SRAM bits for MUX[66], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_968_ (mux_2level_tapbuf_size16_66_sram_blwl_out[968:968] ,mux_2level_tapbuf_size16_66_sram_blwl_out[968:968] ,mux_2level_tapbuf_size16_66_sram_blwl_outb[968:968] ,mux_2level_tapbuf_size16_66_configbus0[968:968], mux_2level_tapbuf_size16_66_configbus1[968:968] , mux_2level_tapbuf_size16_66_configbus0_b[968:968] ); -sram6T_blwl sram_blwl_969_ (mux_2level_tapbuf_size16_66_sram_blwl_out[969:969] ,mux_2level_tapbuf_size16_66_sram_blwl_out[969:969] ,mux_2level_tapbuf_size16_66_sram_blwl_outb[969:969] ,mux_2level_tapbuf_size16_66_configbus0[969:969], mux_2level_tapbuf_size16_66_configbus1[969:969] , mux_2level_tapbuf_size16_66_configbus0_b[969:969] ); -sram6T_blwl sram_blwl_970_ (mux_2level_tapbuf_size16_66_sram_blwl_out[970:970] ,mux_2level_tapbuf_size16_66_sram_blwl_out[970:970] ,mux_2level_tapbuf_size16_66_sram_blwl_outb[970:970] ,mux_2level_tapbuf_size16_66_configbus0[970:970], mux_2level_tapbuf_size16_66_configbus1[970:970] , mux_2level_tapbuf_size16_66_configbus0_b[970:970] ); -sram6T_blwl sram_blwl_971_ (mux_2level_tapbuf_size16_66_sram_blwl_out[971:971] ,mux_2level_tapbuf_size16_66_sram_blwl_out[971:971] ,mux_2level_tapbuf_size16_66_sram_blwl_outb[971:971] ,mux_2level_tapbuf_size16_66_configbus0[971:971], mux_2level_tapbuf_size16_66_configbus1[971:971] , mux_2level_tapbuf_size16_66_configbus0_b[971:971] ); -sram6T_blwl sram_blwl_972_ (mux_2level_tapbuf_size16_66_sram_blwl_out[972:972] ,mux_2level_tapbuf_size16_66_sram_blwl_out[972:972] ,mux_2level_tapbuf_size16_66_sram_blwl_outb[972:972] ,mux_2level_tapbuf_size16_66_configbus0[972:972], mux_2level_tapbuf_size16_66_configbus1[972:972] , mux_2level_tapbuf_size16_66_configbus0_b[972:972] ); -sram6T_blwl sram_blwl_973_ (mux_2level_tapbuf_size16_66_sram_blwl_out[973:973] ,mux_2level_tapbuf_size16_66_sram_blwl_out[973:973] ,mux_2level_tapbuf_size16_66_sram_blwl_outb[973:973] ,mux_2level_tapbuf_size16_66_configbus0[973:973], mux_2level_tapbuf_size16_66_configbus1[973:973] , mux_2level_tapbuf_size16_66_configbus0_b[973:973] ); -sram6T_blwl sram_blwl_974_ (mux_2level_tapbuf_size16_66_sram_blwl_out[974:974] ,mux_2level_tapbuf_size16_66_sram_blwl_out[974:974] ,mux_2level_tapbuf_size16_66_sram_blwl_outb[974:974] ,mux_2level_tapbuf_size16_66_configbus0[974:974], mux_2level_tapbuf_size16_66_configbus1[974:974] , mux_2level_tapbuf_size16_66_configbus0_b[974:974] ); -sram6T_blwl sram_blwl_975_ (mux_2level_tapbuf_size16_66_sram_blwl_out[975:975] ,mux_2level_tapbuf_size16_66_sram_blwl_out[975:975] ,mux_2level_tapbuf_size16_66_sram_blwl_outb[975:975] ,mux_2level_tapbuf_size16_66_configbus0[975:975], mux_2level_tapbuf_size16_66_configbus1[975:975] , mux_2level_tapbuf_size16_66_configbus0_b[975:975] ); -wire [0:15] mux_2level_tapbuf_size16_67_inbus; -assign mux_2level_tapbuf_size16_67_inbus[0] = chany_1__1__midout_4_; -assign mux_2level_tapbuf_size16_67_inbus[1] = chany_1__1__midout_5_; -assign mux_2level_tapbuf_size16_67_inbus[2] = chany_1__1__midout_16_; -assign mux_2level_tapbuf_size16_67_inbus[3] = chany_1__1__midout_17_; -assign mux_2level_tapbuf_size16_67_inbus[4] = chany_1__1__midout_28_; -assign mux_2level_tapbuf_size16_67_inbus[5] = chany_1__1__midout_29_; -assign mux_2level_tapbuf_size16_67_inbus[6] = chany_1__1__midout_46_; -assign mux_2level_tapbuf_size16_67_inbus[7] = chany_1__1__midout_47_; -assign mux_2level_tapbuf_size16_67_inbus[8] = chany_1__1__midout_58_; -assign mux_2level_tapbuf_size16_67_inbus[9] = chany_1__1__midout_59_; -assign mux_2level_tapbuf_size16_67_inbus[10] = chany_1__1__midout_68_; -assign mux_2level_tapbuf_size16_67_inbus[11] = chany_1__1__midout_69_; -assign mux_2level_tapbuf_size16_67_inbus[12] = chany_1__1__midout_80_; -assign mux_2level_tapbuf_size16_67_inbus[13] = chany_1__1__midout_81_; -assign mux_2level_tapbuf_size16_67_inbus[14] = chany_1__1__midout_94_; -assign mux_2level_tapbuf_size16_67_inbus[15] = chany_1__1__midout_95_; -wire [976:983] mux_2level_tapbuf_size16_67_configbus0; -wire [976:983] mux_2level_tapbuf_size16_67_configbus1; -wire [976:983] mux_2level_tapbuf_size16_67_sram_blwl_out ; -wire [976:983] mux_2level_tapbuf_size16_67_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_67_configbus0[976:983] = sram_blwl_bl[976:983] ; -assign mux_2level_tapbuf_size16_67_configbus1[976:983] = sram_blwl_wl[976:983] ; -wire [976:983] mux_2level_tapbuf_size16_67_configbus0_b; -assign mux_2level_tapbuf_size16_67_configbus0_b[976:983] = sram_blwl_blb[976:983] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_67_ (mux_2level_tapbuf_size16_67_inbus, grid_1__1__pin_0__1__21_, mux_2level_tapbuf_size16_67_sram_blwl_out[976:983] , -mux_2level_tapbuf_size16_67_sram_blwl_outb[976:983] ); -//----- SRAM bits for MUX[67], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_976_ (mux_2level_tapbuf_size16_67_sram_blwl_out[976:976] ,mux_2level_tapbuf_size16_67_sram_blwl_out[976:976] ,mux_2level_tapbuf_size16_67_sram_blwl_outb[976:976] ,mux_2level_tapbuf_size16_67_configbus0[976:976], mux_2level_tapbuf_size16_67_configbus1[976:976] , mux_2level_tapbuf_size16_67_configbus0_b[976:976] ); -sram6T_blwl sram_blwl_977_ (mux_2level_tapbuf_size16_67_sram_blwl_out[977:977] ,mux_2level_tapbuf_size16_67_sram_blwl_out[977:977] ,mux_2level_tapbuf_size16_67_sram_blwl_outb[977:977] ,mux_2level_tapbuf_size16_67_configbus0[977:977], mux_2level_tapbuf_size16_67_configbus1[977:977] , mux_2level_tapbuf_size16_67_configbus0_b[977:977] ); -sram6T_blwl sram_blwl_978_ (mux_2level_tapbuf_size16_67_sram_blwl_out[978:978] ,mux_2level_tapbuf_size16_67_sram_blwl_out[978:978] ,mux_2level_tapbuf_size16_67_sram_blwl_outb[978:978] ,mux_2level_tapbuf_size16_67_configbus0[978:978], mux_2level_tapbuf_size16_67_configbus1[978:978] , mux_2level_tapbuf_size16_67_configbus0_b[978:978] ); -sram6T_blwl sram_blwl_979_ (mux_2level_tapbuf_size16_67_sram_blwl_out[979:979] ,mux_2level_tapbuf_size16_67_sram_blwl_out[979:979] ,mux_2level_tapbuf_size16_67_sram_blwl_outb[979:979] ,mux_2level_tapbuf_size16_67_configbus0[979:979], mux_2level_tapbuf_size16_67_configbus1[979:979] , mux_2level_tapbuf_size16_67_configbus0_b[979:979] ); -sram6T_blwl sram_blwl_980_ (mux_2level_tapbuf_size16_67_sram_blwl_out[980:980] ,mux_2level_tapbuf_size16_67_sram_blwl_out[980:980] ,mux_2level_tapbuf_size16_67_sram_blwl_outb[980:980] ,mux_2level_tapbuf_size16_67_configbus0[980:980], mux_2level_tapbuf_size16_67_configbus1[980:980] , mux_2level_tapbuf_size16_67_configbus0_b[980:980] ); -sram6T_blwl sram_blwl_981_ (mux_2level_tapbuf_size16_67_sram_blwl_out[981:981] ,mux_2level_tapbuf_size16_67_sram_blwl_out[981:981] ,mux_2level_tapbuf_size16_67_sram_blwl_outb[981:981] ,mux_2level_tapbuf_size16_67_configbus0[981:981], mux_2level_tapbuf_size16_67_configbus1[981:981] , mux_2level_tapbuf_size16_67_configbus0_b[981:981] ); -sram6T_blwl sram_blwl_982_ (mux_2level_tapbuf_size16_67_sram_blwl_out[982:982] ,mux_2level_tapbuf_size16_67_sram_blwl_out[982:982] ,mux_2level_tapbuf_size16_67_sram_blwl_outb[982:982] ,mux_2level_tapbuf_size16_67_configbus0[982:982], mux_2level_tapbuf_size16_67_configbus1[982:982] , mux_2level_tapbuf_size16_67_configbus0_b[982:982] ); -sram6T_blwl sram_blwl_983_ (mux_2level_tapbuf_size16_67_sram_blwl_out[983:983] ,mux_2level_tapbuf_size16_67_sram_blwl_out[983:983] ,mux_2level_tapbuf_size16_67_sram_blwl_outb[983:983] ,mux_2level_tapbuf_size16_67_configbus0[983:983], mux_2level_tapbuf_size16_67_configbus1[983:983] , mux_2level_tapbuf_size16_67_configbus0_b[983:983] ); -wire [0:15] mux_2level_tapbuf_size16_68_inbus; -assign mux_2level_tapbuf_size16_68_inbus[0] = chany_1__1__midout_4_; -assign mux_2level_tapbuf_size16_68_inbus[1] = chany_1__1__midout_5_; -assign mux_2level_tapbuf_size16_68_inbus[2] = chany_1__1__midout_18_; -assign mux_2level_tapbuf_size16_68_inbus[3] = chany_1__1__midout_19_; -assign mux_2level_tapbuf_size16_68_inbus[4] = chany_1__1__midout_38_; -assign mux_2level_tapbuf_size16_68_inbus[5] = chany_1__1__midout_39_; -assign mux_2level_tapbuf_size16_68_inbus[6] = chany_1__1__midout_46_; -assign mux_2level_tapbuf_size16_68_inbus[7] = chany_1__1__midout_47_; -assign mux_2level_tapbuf_size16_68_inbus[8] = chany_1__1__midout_58_; -assign mux_2level_tapbuf_size16_68_inbus[9] = chany_1__1__midout_59_; -assign mux_2level_tapbuf_size16_68_inbus[10] = chany_1__1__midout_70_; -assign mux_2level_tapbuf_size16_68_inbus[11] = chany_1__1__midout_71_; -assign mux_2level_tapbuf_size16_68_inbus[12] = chany_1__1__midout_82_; -assign mux_2level_tapbuf_size16_68_inbus[13] = chany_1__1__midout_83_; -assign mux_2level_tapbuf_size16_68_inbus[14] = chany_1__1__midout_94_; -assign mux_2level_tapbuf_size16_68_inbus[15] = chany_1__1__midout_95_; -wire [984:991] mux_2level_tapbuf_size16_68_configbus0; -wire [984:991] mux_2level_tapbuf_size16_68_configbus1; -wire [984:991] mux_2level_tapbuf_size16_68_sram_blwl_out ; -wire [984:991] mux_2level_tapbuf_size16_68_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_68_configbus0[984:991] = sram_blwl_bl[984:991] ; -assign mux_2level_tapbuf_size16_68_configbus1[984:991] = sram_blwl_wl[984:991] ; -wire [984:991] mux_2level_tapbuf_size16_68_configbus0_b; -assign mux_2level_tapbuf_size16_68_configbus0_b[984:991] = sram_blwl_blb[984:991] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_68_ (mux_2level_tapbuf_size16_68_inbus, grid_1__1__pin_0__1__25_, mux_2level_tapbuf_size16_68_sram_blwl_out[984:991] , -mux_2level_tapbuf_size16_68_sram_blwl_outb[984:991] ); -//----- SRAM bits for MUX[68], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_984_ (mux_2level_tapbuf_size16_68_sram_blwl_out[984:984] ,mux_2level_tapbuf_size16_68_sram_blwl_out[984:984] ,mux_2level_tapbuf_size16_68_sram_blwl_outb[984:984] ,mux_2level_tapbuf_size16_68_configbus0[984:984], mux_2level_tapbuf_size16_68_configbus1[984:984] , mux_2level_tapbuf_size16_68_configbus0_b[984:984] ); -sram6T_blwl sram_blwl_985_ (mux_2level_tapbuf_size16_68_sram_blwl_out[985:985] ,mux_2level_tapbuf_size16_68_sram_blwl_out[985:985] ,mux_2level_tapbuf_size16_68_sram_blwl_outb[985:985] ,mux_2level_tapbuf_size16_68_configbus0[985:985], mux_2level_tapbuf_size16_68_configbus1[985:985] , mux_2level_tapbuf_size16_68_configbus0_b[985:985] ); -sram6T_blwl sram_blwl_986_ (mux_2level_tapbuf_size16_68_sram_blwl_out[986:986] ,mux_2level_tapbuf_size16_68_sram_blwl_out[986:986] ,mux_2level_tapbuf_size16_68_sram_blwl_outb[986:986] ,mux_2level_tapbuf_size16_68_configbus0[986:986], mux_2level_tapbuf_size16_68_configbus1[986:986] , mux_2level_tapbuf_size16_68_configbus0_b[986:986] ); -sram6T_blwl sram_blwl_987_ (mux_2level_tapbuf_size16_68_sram_blwl_out[987:987] ,mux_2level_tapbuf_size16_68_sram_blwl_out[987:987] ,mux_2level_tapbuf_size16_68_sram_blwl_outb[987:987] ,mux_2level_tapbuf_size16_68_configbus0[987:987], mux_2level_tapbuf_size16_68_configbus1[987:987] , mux_2level_tapbuf_size16_68_configbus0_b[987:987] ); -sram6T_blwl sram_blwl_988_ (mux_2level_tapbuf_size16_68_sram_blwl_out[988:988] ,mux_2level_tapbuf_size16_68_sram_blwl_out[988:988] ,mux_2level_tapbuf_size16_68_sram_blwl_outb[988:988] ,mux_2level_tapbuf_size16_68_configbus0[988:988], mux_2level_tapbuf_size16_68_configbus1[988:988] , mux_2level_tapbuf_size16_68_configbus0_b[988:988] ); -sram6T_blwl sram_blwl_989_ (mux_2level_tapbuf_size16_68_sram_blwl_out[989:989] ,mux_2level_tapbuf_size16_68_sram_blwl_out[989:989] ,mux_2level_tapbuf_size16_68_sram_blwl_outb[989:989] ,mux_2level_tapbuf_size16_68_configbus0[989:989], mux_2level_tapbuf_size16_68_configbus1[989:989] , mux_2level_tapbuf_size16_68_configbus0_b[989:989] ); -sram6T_blwl sram_blwl_990_ (mux_2level_tapbuf_size16_68_sram_blwl_out[990:990] ,mux_2level_tapbuf_size16_68_sram_blwl_out[990:990] ,mux_2level_tapbuf_size16_68_sram_blwl_outb[990:990] ,mux_2level_tapbuf_size16_68_configbus0[990:990], mux_2level_tapbuf_size16_68_configbus1[990:990] , mux_2level_tapbuf_size16_68_configbus0_b[990:990] ); -sram6T_blwl sram_blwl_991_ (mux_2level_tapbuf_size16_68_sram_blwl_out[991:991] ,mux_2level_tapbuf_size16_68_sram_blwl_out[991:991] ,mux_2level_tapbuf_size16_68_sram_blwl_outb[991:991] ,mux_2level_tapbuf_size16_68_configbus0[991:991], mux_2level_tapbuf_size16_68_configbus1[991:991] , mux_2level_tapbuf_size16_68_configbus0_b[991:991] ); -wire [0:15] mux_2level_tapbuf_size16_69_inbus; -assign mux_2level_tapbuf_size16_69_inbus[0] = chany_1__1__midout_14_; -assign mux_2level_tapbuf_size16_69_inbus[1] = chany_1__1__midout_15_; -assign mux_2level_tapbuf_size16_69_inbus[2] = chany_1__1__midout_18_; -assign mux_2level_tapbuf_size16_69_inbus[3] = chany_1__1__midout_19_; -assign mux_2level_tapbuf_size16_69_inbus[4] = chany_1__1__midout_32_; -assign mux_2level_tapbuf_size16_69_inbus[5] = chany_1__1__midout_33_; -assign mux_2level_tapbuf_size16_69_inbus[6] = chany_1__1__midout_44_; -assign mux_2level_tapbuf_size16_69_inbus[7] = chany_1__1__midout_45_; -assign mux_2level_tapbuf_size16_69_inbus[8] = chany_1__1__midout_56_; -assign mux_2level_tapbuf_size16_69_inbus[9] = chany_1__1__midout_57_; -assign mux_2level_tapbuf_size16_69_inbus[10] = chany_1__1__midout_70_; -assign mux_2level_tapbuf_size16_69_inbus[11] = chany_1__1__midout_71_; -assign mux_2level_tapbuf_size16_69_inbus[12] = chany_1__1__midout_84_; -assign mux_2level_tapbuf_size16_69_inbus[13] = chany_1__1__midout_85_; -assign mux_2level_tapbuf_size16_69_inbus[14] = chany_1__1__midout_96_; -assign mux_2level_tapbuf_size16_69_inbus[15] = chany_1__1__midout_97_; -wire [992:999] mux_2level_tapbuf_size16_69_configbus0; -wire [992:999] mux_2level_tapbuf_size16_69_configbus1; -wire [992:999] mux_2level_tapbuf_size16_69_sram_blwl_out ; -wire [992:999] mux_2level_tapbuf_size16_69_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_69_configbus0[992:999] = sram_blwl_bl[992:999] ; -assign mux_2level_tapbuf_size16_69_configbus1[992:999] = sram_blwl_wl[992:999] ; -wire [992:999] mux_2level_tapbuf_size16_69_configbus0_b; -assign mux_2level_tapbuf_size16_69_configbus0_b[992:999] = sram_blwl_blb[992:999] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_69_ (mux_2level_tapbuf_size16_69_inbus, grid_1__1__pin_0__1__29_, mux_2level_tapbuf_size16_69_sram_blwl_out[992:999] , -mux_2level_tapbuf_size16_69_sram_blwl_outb[992:999] ); -//----- SRAM bits for MUX[69], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_992_ (mux_2level_tapbuf_size16_69_sram_blwl_out[992:992] ,mux_2level_tapbuf_size16_69_sram_blwl_out[992:992] ,mux_2level_tapbuf_size16_69_sram_blwl_outb[992:992] ,mux_2level_tapbuf_size16_69_configbus0[992:992], mux_2level_tapbuf_size16_69_configbus1[992:992] , mux_2level_tapbuf_size16_69_configbus0_b[992:992] ); -sram6T_blwl sram_blwl_993_ (mux_2level_tapbuf_size16_69_sram_blwl_out[993:993] ,mux_2level_tapbuf_size16_69_sram_blwl_out[993:993] ,mux_2level_tapbuf_size16_69_sram_blwl_outb[993:993] ,mux_2level_tapbuf_size16_69_configbus0[993:993], mux_2level_tapbuf_size16_69_configbus1[993:993] , mux_2level_tapbuf_size16_69_configbus0_b[993:993] ); -sram6T_blwl sram_blwl_994_ (mux_2level_tapbuf_size16_69_sram_blwl_out[994:994] ,mux_2level_tapbuf_size16_69_sram_blwl_out[994:994] ,mux_2level_tapbuf_size16_69_sram_blwl_outb[994:994] ,mux_2level_tapbuf_size16_69_configbus0[994:994], mux_2level_tapbuf_size16_69_configbus1[994:994] , mux_2level_tapbuf_size16_69_configbus0_b[994:994] ); -sram6T_blwl sram_blwl_995_ (mux_2level_tapbuf_size16_69_sram_blwl_out[995:995] ,mux_2level_tapbuf_size16_69_sram_blwl_out[995:995] ,mux_2level_tapbuf_size16_69_sram_blwl_outb[995:995] ,mux_2level_tapbuf_size16_69_configbus0[995:995], mux_2level_tapbuf_size16_69_configbus1[995:995] , mux_2level_tapbuf_size16_69_configbus0_b[995:995] ); -sram6T_blwl sram_blwl_996_ (mux_2level_tapbuf_size16_69_sram_blwl_out[996:996] ,mux_2level_tapbuf_size16_69_sram_blwl_out[996:996] ,mux_2level_tapbuf_size16_69_sram_blwl_outb[996:996] ,mux_2level_tapbuf_size16_69_configbus0[996:996], mux_2level_tapbuf_size16_69_configbus1[996:996] , mux_2level_tapbuf_size16_69_configbus0_b[996:996] ); -sram6T_blwl sram_blwl_997_ (mux_2level_tapbuf_size16_69_sram_blwl_out[997:997] ,mux_2level_tapbuf_size16_69_sram_blwl_out[997:997] ,mux_2level_tapbuf_size16_69_sram_blwl_outb[997:997] ,mux_2level_tapbuf_size16_69_configbus0[997:997], mux_2level_tapbuf_size16_69_configbus1[997:997] , mux_2level_tapbuf_size16_69_configbus0_b[997:997] ); -sram6T_blwl sram_blwl_998_ (mux_2level_tapbuf_size16_69_sram_blwl_out[998:998] ,mux_2level_tapbuf_size16_69_sram_blwl_out[998:998] ,mux_2level_tapbuf_size16_69_sram_blwl_outb[998:998] ,mux_2level_tapbuf_size16_69_configbus0[998:998], mux_2level_tapbuf_size16_69_configbus1[998:998] , mux_2level_tapbuf_size16_69_configbus0_b[998:998] ); -sram6T_blwl sram_blwl_999_ (mux_2level_tapbuf_size16_69_sram_blwl_out[999:999] ,mux_2level_tapbuf_size16_69_sram_blwl_out[999:999] ,mux_2level_tapbuf_size16_69_sram_blwl_outb[999:999] ,mux_2level_tapbuf_size16_69_configbus0[999:999], mux_2level_tapbuf_size16_69_configbus1[999:999] , mux_2level_tapbuf_size16_69_configbus0_b[999:999] ); -wire [0:15] mux_2level_tapbuf_size16_70_inbus; -assign mux_2level_tapbuf_size16_70_inbus[0] = chany_1__1__midout_8_; -assign mux_2level_tapbuf_size16_70_inbus[1] = chany_1__1__midout_9_; -assign mux_2level_tapbuf_size16_70_inbus[2] = chany_1__1__midout_20_; -assign mux_2level_tapbuf_size16_70_inbus[3] = chany_1__1__midout_21_; -assign mux_2level_tapbuf_size16_70_inbus[4] = chany_1__1__midout_32_; -assign mux_2level_tapbuf_size16_70_inbus[5] = chany_1__1__midout_33_; -assign mux_2level_tapbuf_size16_70_inbus[6] = chany_1__1__midout_44_; -assign mux_2level_tapbuf_size16_70_inbus[7] = chany_1__1__midout_45_; -assign mux_2level_tapbuf_size16_70_inbus[8] = chany_1__1__midout_62_; -assign mux_2level_tapbuf_size16_70_inbus[9] = chany_1__1__midout_63_; -assign mux_2level_tapbuf_size16_70_inbus[10] = chany_1__1__midout_72_; -assign mux_2level_tapbuf_size16_70_inbus[11] = chany_1__1__midout_73_; -assign mux_2level_tapbuf_size16_70_inbus[12] = chany_1__1__midout_84_; -assign mux_2level_tapbuf_size16_70_inbus[13] = chany_1__1__midout_85_; -assign mux_2level_tapbuf_size16_70_inbus[14] = chany_1__1__midout_96_; -assign mux_2level_tapbuf_size16_70_inbus[15] = chany_1__1__midout_97_; -wire [1000:1007] mux_2level_tapbuf_size16_70_configbus0; -wire [1000:1007] mux_2level_tapbuf_size16_70_configbus1; -wire [1000:1007] mux_2level_tapbuf_size16_70_sram_blwl_out ; -wire [1000:1007] mux_2level_tapbuf_size16_70_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_70_configbus0[1000:1007] = sram_blwl_bl[1000:1007] ; -assign mux_2level_tapbuf_size16_70_configbus1[1000:1007] = sram_blwl_wl[1000:1007] ; -wire [1000:1007] mux_2level_tapbuf_size16_70_configbus0_b; -assign mux_2level_tapbuf_size16_70_configbus0_b[1000:1007] = sram_blwl_blb[1000:1007] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_70_ (mux_2level_tapbuf_size16_70_inbus, grid_1__1__pin_0__1__33_, mux_2level_tapbuf_size16_70_sram_blwl_out[1000:1007] , -mux_2level_tapbuf_size16_70_sram_blwl_outb[1000:1007] ); -//----- SRAM bits for MUX[70], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_1000_ (mux_2level_tapbuf_size16_70_sram_blwl_out[1000:1000] ,mux_2level_tapbuf_size16_70_sram_blwl_out[1000:1000] ,mux_2level_tapbuf_size16_70_sram_blwl_outb[1000:1000] ,mux_2level_tapbuf_size16_70_configbus0[1000:1000], mux_2level_tapbuf_size16_70_configbus1[1000:1000] , mux_2level_tapbuf_size16_70_configbus0_b[1000:1000] ); -sram6T_blwl sram_blwl_1001_ (mux_2level_tapbuf_size16_70_sram_blwl_out[1001:1001] ,mux_2level_tapbuf_size16_70_sram_blwl_out[1001:1001] ,mux_2level_tapbuf_size16_70_sram_blwl_outb[1001:1001] ,mux_2level_tapbuf_size16_70_configbus0[1001:1001], mux_2level_tapbuf_size16_70_configbus1[1001:1001] , mux_2level_tapbuf_size16_70_configbus0_b[1001:1001] ); -sram6T_blwl sram_blwl_1002_ (mux_2level_tapbuf_size16_70_sram_blwl_out[1002:1002] ,mux_2level_tapbuf_size16_70_sram_blwl_out[1002:1002] ,mux_2level_tapbuf_size16_70_sram_blwl_outb[1002:1002] ,mux_2level_tapbuf_size16_70_configbus0[1002:1002], mux_2level_tapbuf_size16_70_configbus1[1002:1002] , mux_2level_tapbuf_size16_70_configbus0_b[1002:1002] ); -sram6T_blwl sram_blwl_1003_ (mux_2level_tapbuf_size16_70_sram_blwl_out[1003:1003] ,mux_2level_tapbuf_size16_70_sram_blwl_out[1003:1003] ,mux_2level_tapbuf_size16_70_sram_blwl_outb[1003:1003] ,mux_2level_tapbuf_size16_70_configbus0[1003:1003], mux_2level_tapbuf_size16_70_configbus1[1003:1003] , mux_2level_tapbuf_size16_70_configbus0_b[1003:1003] ); -sram6T_blwl sram_blwl_1004_ (mux_2level_tapbuf_size16_70_sram_blwl_out[1004:1004] ,mux_2level_tapbuf_size16_70_sram_blwl_out[1004:1004] ,mux_2level_tapbuf_size16_70_sram_blwl_outb[1004:1004] ,mux_2level_tapbuf_size16_70_configbus0[1004:1004], mux_2level_tapbuf_size16_70_configbus1[1004:1004] , mux_2level_tapbuf_size16_70_configbus0_b[1004:1004] ); -sram6T_blwl sram_blwl_1005_ (mux_2level_tapbuf_size16_70_sram_blwl_out[1005:1005] ,mux_2level_tapbuf_size16_70_sram_blwl_out[1005:1005] ,mux_2level_tapbuf_size16_70_sram_blwl_outb[1005:1005] ,mux_2level_tapbuf_size16_70_configbus0[1005:1005], mux_2level_tapbuf_size16_70_configbus1[1005:1005] , mux_2level_tapbuf_size16_70_configbus0_b[1005:1005] ); -sram6T_blwl sram_blwl_1006_ (mux_2level_tapbuf_size16_70_sram_blwl_out[1006:1006] ,mux_2level_tapbuf_size16_70_sram_blwl_out[1006:1006] ,mux_2level_tapbuf_size16_70_sram_blwl_outb[1006:1006] ,mux_2level_tapbuf_size16_70_configbus0[1006:1006], mux_2level_tapbuf_size16_70_configbus1[1006:1006] , mux_2level_tapbuf_size16_70_configbus0_b[1006:1006] ); -sram6T_blwl sram_blwl_1007_ (mux_2level_tapbuf_size16_70_sram_blwl_out[1007:1007] ,mux_2level_tapbuf_size16_70_sram_blwl_out[1007:1007] ,mux_2level_tapbuf_size16_70_sram_blwl_outb[1007:1007] ,mux_2level_tapbuf_size16_70_configbus0[1007:1007], mux_2level_tapbuf_size16_70_configbus1[1007:1007] , mux_2level_tapbuf_size16_70_configbus0_b[1007:1007] ); -wire [0:15] mux_2level_tapbuf_size16_71_inbus; -assign mux_2level_tapbuf_size16_71_inbus[0] = chany_1__1__midout_8_; -assign mux_2level_tapbuf_size16_71_inbus[1] = chany_1__1__midout_9_; -assign mux_2level_tapbuf_size16_71_inbus[2] = chany_1__1__midout_30_; -assign mux_2level_tapbuf_size16_71_inbus[3] = chany_1__1__midout_31_; -assign mux_2level_tapbuf_size16_71_inbus[4] = chany_1__1__midout_34_; -assign mux_2level_tapbuf_size16_71_inbus[5] = chany_1__1__midout_35_; -assign mux_2level_tapbuf_size16_71_inbus[6] = chany_1__1__midout_50_; -assign mux_2level_tapbuf_size16_71_inbus[7] = chany_1__1__midout_51_; -assign mux_2level_tapbuf_size16_71_inbus[8] = chany_1__1__midout_62_; -assign mux_2level_tapbuf_size16_71_inbus[9] = chany_1__1__midout_63_; -assign mux_2level_tapbuf_size16_71_inbus[10] = chany_1__1__midout_74_; -assign mux_2level_tapbuf_size16_71_inbus[11] = chany_1__1__midout_75_; -assign mux_2level_tapbuf_size16_71_inbus[12] = chany_1__1__midout_86_; -assign mux_2level_tapbuf_size16_71_inbus[13] = chany_1__1__midout_87_; -assign mux_2level_tapbuf_size16_71_inbus[14] = chany_1__1__midout_98_; -assign mux_2level_tapbuf_size16_71_inbus[15] = chany_1__1__midout_99_; -wire [1008:1015] mux_2level_tapbuf_size16_71_configbus0; -wire [1008:1015] mux_2level_tapbuf_size16_71_configbus1; -wire [1008:1015] mux_2level_tapbuf_size16_71_sram_blwl_out ; -wire [1008:1015] mux_2level_tapbuf_size16_71_sram_blwl_outb ; -assign mux_2level_tapbuf_size16_71_configbus0[1008:1015] = sram_blwl_bl[1008:1015] ; -assign mux_2level_tapbuf_size16_71_configbus1[1008:1015] = sram_blwl_wl[1008:1015] ; -wire [1008:1015] mux_2level_tapbuf_size16_71_configbus0_b; -assign mux_2level_tapbuf_size16_71_configbus0_b[1008:1015] = sram_blwl_blb[1008:1015] ; -mux_2level_tapbuf_size16 mux_2level_tapbuf_size16_71_ (mux_2level_tapbuf_size16_71_inbus, grid_1__1__pin_0__1__37_, mux_2level_tapbuf_size16_71_sram_blwl_out[1008:1015] , -mux_2level_tapbuf_size16_71_sram_blwl_outb[1008:1015] ); -//----- SRAM bits for MUX[71], level=2, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----10001000----- -sram6T_blwl sram_blwl_1008_ (mux_2level_tapbuf_size16_71_sram_blwl_out[1008:1008] ,mux_2level_tapbuf_size16_71_sram_blwl_out[1008:1008] ,mux_2level_tapbuf_size16_71_sram_blwl_outb[1008:1008] ,mux_2level_tapbuf_size16_71_configbus0[1008:1008], mux_2level_tapbuf_size16_71_configbus1[1008:1008] , mux_2level_tapbuf_size16_71_configbus0_b[1008:1008] ); -sram6T_blwl sram_blwl_1009_ (mux_2level_tapbuf_size16_71_sram_blwl_out[1009:1009] ,mux_2level_tapbuf_size16_71_sram_blwl_out[1009:1009] ,mux_2level_tapbuf_size16_71_sram_blwl_outb[1009:1009] ,mux_2level_tapbuf_size16_71_configbus0[1009:1009], mux_2level_tapbuf_size16_71_configbus1[1009:1009] , mux_2level_tapbuf_size16_71_configbus0_b[1009:1009] ); -sram6T_blwl sram_blwl_1010_ (mux_2level_tapbuf_size16_71_sram_blwl_out[1010:1010] ,mux_2level_tapbuf_size16_71_sram_blwl_out[1010:1010] ,mux_2level_tapbuf_size16_71_sram_blwl_outb[1010:1010] ,mux_2level_tapbuf_size16_71_configbus0[1010:1010], mux_2level_tapbuf_size16_71_configbus1[1010:1010] , mux_2level_tapbuf_size16_71_configbus0_b[1010:1010] ); -sram6T_blwl sram_blwl_1011_ (mux_2level_tapbuf_size16_71_sram_blwl_out[1011:1011] ,mux_2level_tapbuf_size16_71_sram_blwl_out[1011:1011] ,mux_2level_tapbuf_size16_71_sram_blwl_outb[1011:1011] ,mux_2level_tapbuf_size16_71_configbus0[1011:1011], mux_2level_tapbuf_size16_71_configbus1[1011:1011] , mux_2level_tapbuf_size16_71_configbus0_b[1011:1011] ); -sram6T_blwl sram_blwl_1012_ (mux_2level_tapbuf_size16_71_sram_blwl_out[1012:1012] ,mux_2level_tapbuf_size16_71_sram_blwl_out[1012:1012] ,mux_2level_tapbuf_size16_71_sram_blwl_outb[1012:1012] ,mux_2level_tapbuf_size16_71_configbus0[1012:1012], mux_2level_tapbuf_size16_71_configbus1[1012:1012] , mux_2level_tapbuf_size16_71_configbus0_b[1012:1012] ); -sram6T_blwl sram_blwl_1013_ (mux_2level_tapbuf_size16_71_sram_blwl_out[1013:1013] ,mux_2level_tapbuf_size16_71_sram_blwl_out[1013:1013] ,mux_2level_tapbuf_size16_71_sram_blwl_outb[1013:1013] ,mux_2level_tapbuf_size16_71_configbus0[1013:1013], mux_2level_tapbuf_size16_71_configbus1[1013:1013] , mux_2level_tapbuf_size16_71_configbus0_b[1013:1013] ); -sram6T_blwl sram_blwl_1014_ (mux_2level_tapbuf_size16_71_sram_blwl_out[1014:1014] ,mux_2level_tapbuf_size16_71_sram_blwl_out[1014:1014] ,mux_2level_tapbuf_size16_71_sram_blwl_outb[1014:1014] ,mux_2level_tapbuf_size16_71_configbus0[1014:1014], mux_2level_tapbuf_size16_71_configbus1[1014:1014] , mux_2level_tapbuf_size16_71_configbus0_b[1014:1014] ); -sram6T_blwl sram_blwl_1015_ (mux_2level_tapbuf_size16_71_sram_blwl_out[1015:1015] ,mux_2level_tapbuf_size16_71_sram_blwl_out[1015:1015] ,mux_2level_tapbuf_size16_71_sram_blwl_outb[1015:1015] ,mux_2level_tapbuf_size16_71_configbus0[1015:1015], mux_2level_tapbuf_size16_71_configbus1[1015:1015] , mux_2level_tapbuf_size16_71_configbus0_b[1015:1015] ); -endmodule -//----- END Verilog Module of Connection Box -Y direction [1][1] ----- - diff --git a/examples/verilog_test_example_2/routing/chanx_1_0.v b/examples/verilog_test_example_2/routing/chanx_1_0.v deleted file mode 100644 index 0ce4af12d..000000000 --- a/examples/verilog_test_example_2/routing/chanx_1_0.v +++ /dev/null @@ -1,525 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Routing Channel - X direction [1][0] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Channel X [1][0] ----- -module chanx_1__0_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, - input in0, //--- track 0 input - output out1, //--- track 1 output - input in2, //--- track 2 input - output out3, //--- track 3 output - input in4, //--- track 4 input - output out5, //--- track 5 output - input in6, //--- track 6 input - output out7, //--- track 7 output - input in8, //--- track 8 input - output out9, //--- track 9 output - input in10, //--- track 10 input - output out11, //--- track 11 output - input in12, //--- track 12 input - output out13, //--- track 13 output - input in14, //--- track 14 input - output out15, //--- track 15 output - input in16, //--- track 16 input - output out17, //--- track 17 output - input in18, //--- track 18 input - output out19, //--- track 19 output - input in20, //--- track 20 input - output out21, //--- track 21 output - input in22, //--- track 22 input - output out23, //--- track 23 output - input in24, //--- track 24 input - output out25, //--- track 25 output - input in26, //--- track 26 input - output out27, //--- track 27 output - input in28, //--- track 28 input - output out29, //--- track 29 output - input in30, //--- track 30 input - output out31, //--- track 31 output - input in32, //--- track 32 input - output out33, //--- track 33 output - input in34, //--- track 34 input - output out35, //--- track 35 output - input in36, //--- track 36 input - output out37, //--- track 37 output - input in38, //--- track 38 input - output out39, //--- track 39 output - input in40, //--- track 40 input - output out41, //--- track 41 output - input in42, //--- track 42 input - output out43, //--- track 43 output - input in44, //--- track 44 input - output out45, //--- track 45 output - input in46, //--- track 46 input - output out47, //--- track 47 output - input in48, //--- track 48 input - output out49, //--- track 49 output - input in50, //--- track 50 input - output out51, //--- track 51 output - input in52, //--- track 52 input - output out53, //--- track 53 output - input in54, //--- track 54 input - output out55, //--- track 55 output - input in56, //--- track 56 input - output out57, //--- track 57 output - input in58, //--- track 58 input - output out59, //--- track 59 output - input in60, //--- track 60 input - output out61, //--- track 61 output - input in62, //--- track 62 input - output out63, //--- track 63 output - input in64, //--- track 64 input - output out65, //--- track 65 output - input in66, //--- track 66 input - output out67, //--- track 67 output - input in68, //--- track 68 input - output out69, //--- track 69 output - input in70, //--- track 70 input - output out71, //--- track 71 output - input in72, //--- track 72 input - output out73, //--- track 73 output - input in74, //--- track 74 input - output out75, //--- track 75 output - input in76, //--- track 76 input - output out77, //--- track 77 output - input in78, //--- track 78 input - output out79, //--- track 79 output - input in80, //--- track 80 input - output out81, //--- track 81 output - input in82, //--- track 82 input - output out83, //--- track 83 output - input in84, //--- track 84 input - output out85, //--- track 85 output - input in86, //--- track 86 input - output out87, //--- track 87 output - input in88, //--- track 88 input - output out89, //--- track 89 output - input in90, //--- track 90 input - output out91, //--- track 91 output - input in92, //--- track 92 input - output out93, //--- track 93 output - input in94, //--- track 94 input - output out95, //--- track 95 output - input in96, //--- track 96 input - output out97, //--- track 97 output - input in98, //--- track 98 input - output out99, //--- track 99 output - output out0, //--- track 0 output - input in1, //--- track 1 input - output out2, //--- track 2 output - input in3, //--- track 3 input - output out4, //--- track 4 output - input in5, //--- track 5 input - output out6, //--- track 6 output - input in7, //--- track 7 input - output out8, //--- track 8 output - input in9, //--- track 9 input - output out10, //--- track 10 output - input in11, //--- track 11 input - output out12, //--- track 12 output - input in13, //--- track 13 input - output out14, //--- track 14 output - input in15, //--- track 15 input - output out16, //--- track 16 output - input in17, //--- track 17 input - output out18, //--- track 18 output - input in19, //--- track 19 input - output out20, //--- track 20 output - input in21, //--- track 21 input - output out22, //--- track 22 output - input in23, //--- track 23 input - output out24, //--- track 24 output - input in25, //--- track 25 input - output out26, //--- track 26 output - input in27, //--- track 27 input - output out28, //--- track 28 output - input in29, //--- track 29 input - output out30, //--- track 30 output - input in31, //--- track 31 input - output out32, //--- track 32 output - input in33, //--- track 33 input - output out34, //--- track 34 output - input in35, //--- track 35 input - output out36, //--- track 36 output - input in37, //--- track 37 input - output out38, //--- track 38 output - input in39, //--- track 39 input - output out40, //--- track 40 output - input in41, //--- track 41 input - output out42, //--- track 42 output - input in43, //--- track 43 input - output out44, //--- track 44 output - input in45, //--- track 45 input - output out46, //--- track 46 output - input in47, //--- track 47 input - output out48, //--- track 48 output - input in49, //--- track 49 input - output out50, //--- track 50 output - input in51, //--- track 51 input - output out52, //--- track 52 output - input in53, //--- track 53 input - output out54, //--- track 54 output - input in55, //--- track 55 input - output out56, //--- track 56 output - input in57, //--- track 57 input - output out58, //--- track 58 output - input in59, //--- track 59 input - output out60, //--- track 60 output - input in61, //--- track 61 input - output out62, //--- track 62 output - input in63, //--- track 63 input - output out64, //--- track 64 output - input in65, //--- track 65 input - output out66, //--- track 66 output - input in67, //--- track 67 input - output out68, //--- track 68 output - input in69, //--- track 69 input - output out70, //--- track 70 output - input in71, //--- track 71 input - output out72, //--- track 72 output - input in73, //--- track 73 input - output out74, //--- track 74 output - input in75, //--- track 75 input - output out76, //--- track 76 output - input in77, //--- track 77 input - output out78, //--- track 78 output - input in79, //--- track 79 input - output out80, //--- track 80 output - input in81, //--- track 81 input - output out82, //--- track 82 output - input in83, //--- track 83 input - output out84, //--- track 84 output - input in85, //--- track 85 input - output out86, //--- track 86 output - input in87, //--- track 87 input - output out88, //--- track 88 output - input in89, //--- track 89 input - output out90, //--- track 90 output - input in91, //--- track 91 input - output out92, //--- track 92 output - input in93, //--- track 93 input - output out94, //--- track 94 output - input in95, //--- track 95 input - output out96, //--- track 96 output - input in97, //--- track 97 input - output out98, //--- track 98 output - input in99, //--- track 99 input - output mid_out0, // Middle output 0 to logic blocks - output mid_out1, // Middle output 1 to logic blocks - output mid_out2, // Middle output 2 to logic blocks - output mid_out3, // Middle output 3 to logic blocks - output mid_out4, // Middle output 4 to logic blocks - output mid_out5, // Middle output 5 to logic blocks - output mid_out6, // Middle output 6 to logic blocks - output mid_out7, // Middle output 7 to logic blocks - output mid_out8, // Middle output 8 to logic blocks - output mid_out9, // Middle output 9 to logic blocks - output mid_out10, // Middle output 10 to logic blocks - output mid_out11, // Middle output 11 to logic blocks - output mid_out12, // Middle output 12 to logic blocks - output mid_out13, // Middle output 13 to logic blocks - output mid_out14, // Middle output 14 to logic blocks - output mid_out15, // Middle output 15 to logic blocks - output mid_out16, // Middle output 16 to logic blocks - output mid_out17, // Middle output 17 to logic blocks - output mid_out18, // Middle output 18 to logic blocks - output mid_out19, // Middle output 19 to logic blocks - output mid_out20, // Middle output 20 to logic blocks - output mid_out21, // Middle output 21 to logic blocks - output mid_out22, // Middle output 22 to logic blocks - output mid_out23, // Middle output 23 to logic blocks - output mid_out24, // Middle output 24 to logic blocks - output mid_out25, // Middle output 25 to logic blocks - output mid_out26, // Middle output 26 to logic blocks - output mid_out27, // Middle output 27 to logic blocks - output mid_out28, // Middle output 28 to logic blocks - output mid_out29, // Middle output 29 to logic blocks - output mid_out30, // Middle output 30 to logic blocks - output mid_out31, // Middle output 31 to logic blocks - output mid_out32, // Middle output 32 to logic blocks - output mid_out33, // Middle output 33 to logic blocks - output mid_out34, // Middle output 34 to logic blocks - output mid_out35, // Middle output 35 to logic blocks - output mid_out36, // Middle output 36 to logic blocks - output mid_out37, // Middle output 37 to logic blocks - output mid_out38, // Middle output 38 to logic blocks - output mid_out39, // Middle output 39 to logic blocks - output mid_out40, // Middle output 40 to logic blocks - output mid_out41, // Middle output 41 to logic blocks - output mid_out42, // Middle output 42 to logic blocks - output mid_out43, // Middle output 43 to logic blocks - output mid_out44, // Middle output 44 to logic blocks - output mid_out45, // Middle output 45 to logic blocks - output mid_out46, // Middle output 46 to logic blocks - output mid_out47, // Middle output 47 to logic blocks - output mid_out48, // Middle output 48 to logic blocks - output mid_out49, // Middle output 49 to logic blocks - output mid_out50, // Middle output 50 to logic blocks - output mid_out51, // Middle output 51 to logic blocks - output mid_out52, // Middle output 52 to logic blocks - output mid_out53, // Middle output 53 to logic blocks - output mid_out54, // Middle output 54 to logic blocks - output mid_out55, // Middle output 55 to logic blocks - output mid_out56, // Middle output 56 to logic blocks - output mid_out57, // Middle output 57 to logic blocks - output mid_out58, // Middle output 58 to logic blocks - output mid_out59, // Middle output 59 to logic blocks - output mid_out60, // Middle output 60 to logic blocks - output mid_out61, // Middle output 61 to logic blocks - output mid_out62, // Middle output 62 to logic blocks - output mid_out63, // Middle output 63 to logic blocks - output mid_out64, // Middle output 64 to logic blocks - output mid_out65, // Middle output 65 to logic blocks - output mid_out66, // Middle output 66 to logic blocks - output mid_out67, // Middle output 67 to logic blocks - output mid_out68, // Middle output 68 to logic blocks - output mid_out69, // Middle output 69 to logic blocks - output mid_out70, // Middle output 70 to logic blocks - output mid_out71, // Middle output 71 to logic blocks - output mid_out72, // Middle output 72 to logic blocks - output mid_out73, // Middle output 73 to logic blocks - output mid_out74, // Middle output 74 to logic blocks - output mid_out75, // Middle output 75 to logic blocks - output mid_out76, // Middle output 76 to logic blocks - output mid_out77, // Middle output 77 to logic blocks - output mid_out78, // Middle output 78 to logic blocks - output mid_out79, // Middle output 79 to logic blocks - output mid_out80, // Middle output 80 to logic blocks - output mid_out81, // Middle output 81 to logic blocks - output mid_out82, // Middle output 82 to logic blocks - output mid_out83, // Middle output 83 to logic blocks - output mid_out84, // Middle output 84 to logic blocks - output mid_out85, // Middle output 85 to logic blocks - output mid_out86, // Middle output 86 to logic blocks - output mid_out87, // Middle output 87 to logic blocks - output mid_out88, // Middle output 88 to logic blocks - output mid_out89, // Middle output 89 to logic blocks - output mid_out90, // Middle output 90 to logic blocks - output mid_out91, // Middle output 91 to logic blocks - output mid_out92, // Middle output 92 to logic blocks - output mid_out93, // Middle output 93 to logic blocks - output mid_out94, // Middle output 94 to logic blocks - output mid_out95, // Middle output 95 to logic blocks - output mid_out96, // Middle output 96 to logic blocks - output mid_out97, // Middle output 97 to logic blocks - output mid_out98, // Middle output 98 to logic blocks - output mid_out99 // Middle output 99 to logic blocks - ); -assign out0 = in0; -assign mid_out0 = in0; -assign out1 = in1; -assign mid_out1 = in1; -assign out2 = in2; -assign mid_out2 = in2; -assign out3 = in3; -assign mid_out3 = in3; -assign out4 = in4; -assign mid_out4 = in4; -assign out5 = in5; -assign mid_out5 = in5; -assign out6 = in6; -assign mid_out6 = in6; -assign out7 = in7; -assign mid_out7 = in7; -assign out8 = in8; -assign mid_out8 = in8; -assign out9 = in9; -assign mid_out9 = in9; -assign out10 = in10; -assign mid_out10 = in10; -assign out11 = in11; -assign mid_out11 = in11; -assign out12 = in12; -assign mid_out12 = in12; -assign out13 = in13; -assign mid_out13 = in13; -assign out14 = in14; -assign mid_out14 = in14; -assign out15 = in15; -assign mid_out15 = in15; -assign out16 = in16; -assign mid_out16 = in16; -assign out17 = in17; -assign mid_out17 = in17; -assign out18 = in18; -assign mid_out18 = in18; -assign out19 = in19; -assign mid_out19 = in19; -assign out20 = in20; -assign mid_out20 = in20; -assign out21 = in21; -assign mid_out21 = in21; -assign out22 = in22; -assign mid_out22 = in22; -assign out23 = in23; -assign mid_out23 = in23; -assign out24 = in24; -assign mid_out24 = in24; -assign out25 = in25; -assign mid_out25 = in25; -assign out26 = in26; -assign mid_out26 = in26; -assign out27 = in27; -assign mid_out27 = in27; -assign out28 = in28; -assign mid_out28 = in28; -assign out29 = in29; -assign mid_out29 = in29; -assign out30 = in30; -assign mid_out30 = in30; -assign out31 = in31; -assign mid_out31 = in31; -assign out32 = in32; -assign mid_out32 = in32; -assign out33 = in33; -assign mid_out33 = in33; -assign out34 = in34; -assign mid_out34 = in34; -assign out35 = in35; -assign mid_out35 = in35; -assign out36 = in36; -assign mid_out36 = in36; -assign out37 = in37; -assign mid_out37 = in37; -assign out38 = in38; -assign mid_out38 = in38; -assign out39 = in39; -assign mid_out39 = in39; -assign out40 = in40; -assign mid_out40 = in40; -assign out41 = in41; -assign mid_out41 = in41; -assign out42 = in42; -assign mid_out42 = in42; -assign out43 = in43; -assign mid_out43 = in43; -assign out44 = in44; -assign mid_out44 = in44; -assign out45 = in45; -assign mid_out45 = in45; -assign out46 = in46; -assign mid_out46 = in46; -assign out47 = in47; -assign mid_out47 = in47; -assign out48 = in48; -assign mid_out48 = in48; -assign out49 = in49; -assign mid_out49 = in49; -assign out50 = in50; -assign mid_out50 = in50; -assign out51 = in51; -assign mid_out51 = in51; -assign out52 = in52; -assign mid_out52 = in52; -assign out53 = in53; -assign mid_out53 = in53; -assign out54 = in54; -assign mid_out54 = in54; -assign out55 = in55; -assign mid_out55 = in55; -assign out56 = in56; -assign mid_out56 = in56; -assign out57 = in57; -assign mid_out57 = in57; -assign out58 = in58; -assign mid_out58 = in58; -assign out59 = in59; -assign mid_out59 = in59; -assign out60 = in60; -assign mid_out60 = in60; -assign out61 = in61; -assign mid_out61 = in61; -assign out62 = in62; -assign mid_out62 = in62; -assign out63 = in63; -assign mid_out63 = in63; -assign out64 = in64; -assign mid_out64 = in64; -assign out65 = in65; -assign mid_out65 = in65; -assign out66 = in66; -assign mid_out66 = in66; -assign out67 = in67; -assign mid_out67 = in67; -assign out68 = in68; -assign mid_out68 = in68; -assign out69 = in69; -assign mid_out69 = in69; -assign out70 = in70; -assign mid_out70 = in70; -assign out71 = in71; -assign mid_out71 = in71; -assign out72 = in72; -assign mid_out72 = in72; -assign out73 = in73; -assign mid_out73 = in73; -assign out74 = in74; -assign mid_out74 = in74; -assign out75 = in75; -assign mid_out75 = in75; -assign out76 = in76; -assign mid_out76 = in76; -assign out77 = in77; -assign mid_out77 = in77; -assign out78 = in78; -assign mid_out78 = in78; -assign out79 = in79; -assign mid_out79 = in79; -assign out80 = in80; -assign mid_out80 = in80; -assign out81 = in81; -assign mid_out81 = in81; -assign out82 = in82; -assign mid_out82 = in82; -assign out83 = in83; -assign mid_out83 = in83; -assign out84 = in84; -assign mid_out84 = in84; -assign out85 = in85; -assign mid_out85 = in85; -assign out86 = in86; -assign mid_out86 = in86; -assign out87 = in87; -assign mid_out87 = in87; -assign out88 = in88; -assign mid_out88 = in88; -assign out89 = in89; -assign mid_out89 = in89; -assign out90 = in90; -assign mid_out90 = in90; -assign out91 = in91; -assign mid_out91 = in91; -assign out92 = in92; -assign mid_out92 = in92; -assign out93 = in93; -assign mid_out93 = in93; -assign out94 = in94; -assign mid_out94 = in94; -assign out95 = in95; -assign mid_out95 = in95; -assign out96 = in96; -assign mid_out96 = in96; -assign out97 = in97; -assign mid_out97 = in97; -assign out98 = in98; -assign mid_out98 = in98; -assign out99 = in99; -assign mid_out99 = in99; -endmodule -//----- END Verilog Module of Channel X [1][0] ----- - diff --git a/examples/verilog_test_example_2/routing/chanx_1_1.v b/examples/verilog_test_example_2/routing/chanx_1_1.v deleted file mode 100644 index f5a2f5a58..000000000 --- a/examples/verilog_test_example_2/routing/chanx_1_1.v +++ /dev/null @@ -1,525 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Routing Channel - X direction [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Channel X [1][1] ----- -module chanx_1__1_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, - input in0, //--- track 0 input - output out1, //--- track 1 output - input in2, //--- track 2 input - output out3, //--- track 3 output - input in4, //--- track 4 input - output out5, //--- track 5 output - input in6, //--- track 6 input - output out7, //--- track 7 output - input in8, //--- track 8 input - output out9, //--- track 9 output - input in10, //--- track 10 input - output out11, //--- track 11 output - input in12, //--- track 12 input - output out13, //--- track 13 output - input in14, //--- track 14 input - output out15, //--- track 15 output - input in16, //--- track 16 input - output out17, //--- track 17 output - input in18, //--- track 18 input - output out19, //--- track 19 output - input in20, //--- track 20 input - output out21, //--- track 21 output - input in22, //--- track 22 input - output out23, //--- track 23 output - input in24, //--- track 24 input - output out25, //--- track 25 output - input in26, //--- track 26 input - output out27, //--- track 27 output - input in28, //--- track 28 input - output out29, //--- track 29 output - input in30, //--- track 30 input - output out31, //--- track 31 output - input in32, //--- track 32 input - output out33, //--- track 33 output - input in34, //--- track 34 input - output out35, //--- track 35 output - input in36, //--- track 36 input - output out37, //--- track 37 output - input in38, //--- track 38 input - output out39, //--- track 39 output - input in40, //--- track 40 input - output out41, //--- track 41 output - input in42, //--- track 42 input - output out43, //--- track 43 output - input in44, //--- track 44 input - output out45, //--- track 45 output - input in46, //--- track 46 input - output out47, //--- track 47 output - input in48, //--- track 48 input - output out49, //--- track 49 output - input in50, //--- track 50 input - output out51, //--- track 51 output - input in52, //--- track 52 input - output out53, //--- track 53 output - input in54, //--- track 54 input - output out55, //--- track 55 output - input in56, //--- track 56 input - output out57, //--- track 57 output - input in58, //--- track 58 input - output out59, //--- track 59 output - input in60, //--- track 60 input - output out61, //--- track 61 output - input in62, //--- track 62 input - output out63, //--- track 63 output - input in64, //--- track 64 input - output out65, //--- track 65 output - input in66, //--- track 66 input - output out67, //--- track 67 output - input in68, //--- track 68 input - output out69, //--- track 69 output - input in70, //--- track 70 input - output out71, //--- track 71 output - input in72, //--- track 72 input - output out73, //--- track 73 output - input in74, //--- track 74 input - output out75, //--- track 75 output - input in76, //--- track 76 input - output out77, //--- track 77 output - input in78, //--- track 78 input - output out79, //--- track 79 output - input in80, //--- track 80 input - output out81, //--- track 81 output - input in82, //--- track 82 input - output out83, //--- track 83 output - input in84, //--- track 84 input - output out85, //--- track 85 output - input in86, //--- track 86 input - output out87, //--- track 87 output - input in88, //--- track 88 input - output out89, //--- track 89 output - input in90, //--- track 90 input - output out91, //--- track 91 output - input in92, //--- track 92 input - output out93, //--- track 93 output - input in94, //--- track 94 input - output out95, //--- track 95 output - input in96, //--- track 96 input - output out97, //--- track 97 output - input in98, //--- track 98 input - output out99, //--- track 99 output - output out0, //--- track 0 output - input in1, //--- track 1 input - output out2, //--- track 2 output - input in3, //--- track 3 input - output out4, //--- track 4 output - input in5, //--- track 5 input - output out6, //--- track 6 output - input in7, //--- track 7 input - output out8, //--- track 8 output - input in9, //--- track 9 input - output out10, //--- track 10 output - input in11, //--- track 11 input - output out12, //--- track 12 output - input in13, //--- track 13 input - output out14, //--- track 14 output - input in15, //--- track 15 input - output out16, //--- track 16 output - input in17, //--- track 17 input - output out18, //--- track 18 output - input in19, //--- track 19 input - output out20, //--- track 20 output - input in21, //--- track 21 input - output out22, //--- track 22 output - input in23, //--- track 23 input - output out24, //--- track 24 output - input in25, //--- track 25 input - output out26, //--- track 26 output - input in27, //--- track 27 input - output out28, //--- track 28 output - input in29, //--- track 29 input - output out30, //--- track 30 output - input in31, //--- track 31 input - output out32, //--- track 32 output - input in33, //--- track 33 input - output out34, //--- track 34 output - input in35, //--- track 35 input - output out36, //--- track 36 output - input in37, //--- track 37 input - output out38, //--- track 38 output - input in39, //--- track 39 input - output out40, //--- track 40 output - input in41, //--- track 41 input - output out42, //--- track 42 output - input in43, //--- track 43 input - output out44, //--- track 44 output - input in45, //--- track 45 input - output out46, //--- track 46 output - input in47, //--- track 47 input - output out48, //--- track 48 output - input in49, //--- track 49 input - output out50, //--- track 50 output - input in51, //--- track 51 input - output out52, //--- track 52 output - input in53, //--- track 53 input - output out54, //--- track 54 output - input in55, //--- track 55 input - output out56, //--- track 56 output - input in57, //--- track 57 input - output out58, //--- track 58 output - input in59, //--- track 59 input - output out60, //--- track 60 output - input in61, //--- track 61 input - output out62, //--- track 62 output - input in63, //--- track 63 input - output out64, //--- track 64 output - input in65, //--- track 65 input - output out66, //--- track 66 output - input in67, //--- track 67 input - output out68, //--- track 68 output - input in69, //--- track 69 input - output out70, //--- track 70 output - input in71, //--- track 71 input - output out72, //--- track 72 output - input in73, //--- track 73 input - output out74, //--- track 74 output - input in75, //--- track 75 input - output out76, //--- track 76 output - input in77, //--- track 77 input - output out78, //--- track 78 output - input in79, //--- track 79 input - output out80, //--- track 80 output - input in81, //--- track 81 input - output out82, //--- track 82 output - input in83, //--- track 83 input - output out84, //--- track 84 output - input in85, //--- track 85 input - output out86, //--- track 86 output - input in87, //--- track 87 input - output out88, //--- track 88 output - input in89, //--- track 89 input - output out90, //--- track 90 output - input in91, //--- track 91 input - output out92, //--- track 92 output - input in93, //--- track 93 input - output out94, //--- track 94 output - input in95, //--- track 95 input - output out96, //--- track 96 output - input in97, //--- track 97 input - output out98, //--- track 98 output - input in99, //--- track 99 input - output mid_out0, // Middle output 0 to logic blocks - output mid_out1, // Middle output 1 to logic blocks - output mid_out2, // Middle output 2 to logic blocks - output mid_out3, // Middle output 3 to logic blocks - output mid_out4, // Middle output 4 to logic blocks - output mid_out5, // Middle output 5 to logic blocks - output mid_out6, // Middle output 6 to logic blocks - output mid_out7, // Middle output 7 to logic blocks - output mid_out8, // Middle output 8 to logic blocks - output mid_out9, // Middle output 9 to logic blocks - output mid_out10, // Middle output 10 to logic blocks - output mid_out11, // Middle output 11 to logic blocks - output mid_out12, // Middle output 12 to logic blocks - output mid_out13, // Middle output 13 to logic blocks - output mid_out14, // Middle output 14 to logic blocks - output mid_out15, // Middle output 15 to logic blocks - output mid_out16, // Middle output 16 to logic blocks - output mid_out17, // Middle output 17 to logic blocks - output mid_out18, // Middle output 18 to logic blocks - output mid_out19, // Middle output 19 to logic blocks - output mid_out20, // Middle output 20 to logic blocks - output mid_out21, // Middle output 21 to logic blocks - output mid_out22, // Middle output 22 to logic blocks - output mid_out23, // Middle output 23 to logic blocks - output mid_out24, // Middle output 24 to logic blocks - output mid_out25, // Middle output 25 to logic blocks - output mid_out26, // Middle output 26 to logic blocks - output mid_out27, // Middle output 27 to logic blocks - output mid_out28, // Middle output 28 to logic blocks - output mid_out29, // Middle output 29 to logic blocks - output mid_out30, // Middle output 30 to logic blocks - output mid_out31, // Middle output 31 to logic blocks - output mid_out32, // Middle output 32 to logic blocks - output mid_out33, // Middle output 33 to logic blocks - output mid_out34, // Middle output 34 to logic blocks - output mid_out35, // Middle output 35 to logic blocks - output mid_out36, // Middle output 36 to logic blocks - output mid_out37, // Middle output 37 to logic blocks - output mid_out38, // Middle output 38 to logic blocks - output mid_out39, // Middle output 39 to logic blocks - output mid_out40, // Middle output 40 to logic blocks - output mid_out41, // Middle output 41 to logic blocks - output mid_out42, // Middle output 42 to logic blocks - output mid_out43, // Middle output 43 to logic blocks - output mid_out44, // Middle output 44 to logic blocks - output mid_out45, // Middle output 45 to logic blocks - output mid_out46, // Middle output 46 to logic blocks - output mid_out47, // Middle output 47 to logic blocks - output mid_out48, // Middle output 48 to logic blocks - output mid_out49, // Middle output 49 to logic blocks - output mid_out50, // Middle output 50 to logic blocks - output mid_out51, // Middle output 51 to logic blocks - output mid_out52, // Middle output 52 to logic blocks - output mid_out53, // Middle output 53 to logic blocks - output mid_out54, // Middle output 54 to logic blocks - output mid_out55, // Middle output 55 to logic blocks - output mid_out56, // Middle output 56 to logic blocks - output mid_out57, // Middle output 57 to logic blocks - output mid_out58, // Middle output 58 to logic blocks - output mid_out59, // Middle output 59 to logic blocks - output mid_out60, // Middle output 60 to logic blocks - output mid_out61, // Middle output 61 to logic blocks - output mid_out62, // Middle output 62 to logic blocks - output mid_out63, // Middle output 63 to logic blocks - output mid_out64, // Middle output 64 to logic blocks - output mid_out65, // Middle output 65 to logic blocks - output mid_out66, // Middle output 66 to logic blocks - output mid_out67, // Middle output 67 to logic blocks - output mid_out68, // Middle output 68 to logic blocks - output mid_out69, // Middle output 69 to logic blocks - output mid_out70, // Middle output 70 to logic blocks - output mid_out71, // Middle output 71 to logic blocks - output mid_out72, // Middle output 72 to logic blocks - output mid_out73, // Middle output 73 to logic blocks - output mid_out74, // Middle output 74 to logic blocks - output mid_out75, // Middle output 75 to logic blocks - output mid_out76, // Middle output 76 to logic blocks - output mid_out77, // Middle output 77 to logic blocks - output mid_out78, // Middle output 78 to logic blocks - output mid_out79, // Middle output 79 to logic blocks - output mid_out80, // Middle output 80 to logic blocks - output mid_out81, // Middle output 81 to logic blocks - output mid_out82, // Middle output 82 to logic blocks - output mid_out83, // Middle output 83 to logic blocks - output mid_out84, // Middle output 84 to logic blocks - output mid_out85, // Middle output 85 to logic blocks - output mid_out86, // Middle output 86 to logic blocks - output mid_out87, // Middle output 87 to logic blocks - output mid_out88, // Middle output 88 to logic blocks - output mid_out89, // Middle output 89 to logic blocks - output mid_out90, // Middle output 90 to logic blocks - output mid_out91, // Middle output 91 to logic blocks - output mid_out92, // Middle output 92 to logic blocks - output mid_out93, // Middle output 93 to logic blocks - output mid_out94, // Middle output 94 to logic blocks - output mid_out95, // Middle output 95 to logic blocks - output mid_out96, // Middle output 96 to logic blocks - output mid_out97, // Middle output 97 to logic blocks - output mid_out98, // Middle output 98 to logic blocks - output mid_out99 // Middle output 99 to logic blocks - ); -assign out0 = in0; -assign mid_out0 = in0; -assign out1 = in1; -assign mid_out1 = in1; -assign out2 = in2; -assign mid_out2 = in2; -assign out3 = in3; -assign mid_out3 = in3; -assign out4 = in4; -assign mid_out4 = in4; -assign out5 = in5; -assign mid_out5 = in5; -assign out6 = in6; -assign mid_out6 = in6; -assign out7 = in7; -assign mid_out7 = in7; -assign out8 = in8; -assign mid_out8 = in8; -assign out9 = in9; -assign mid_out9 = in9; -assign out10 = in10; -assign mid_out10 = in10; -assign out11 = in11; -assign mid_out11 = in11; -assign out12 = in12; -assign mid_out12 = in12; -assign out13 = in13; -assign mid_out13 = in13; -assign out14 = in14; -assign mid_out14 = in14; -assign out15 = in15; -assign mid_out15 = in15; -assign out16 = in16; -assign mid_out16 = in16; -assign out17 = in17; -assign mid_out17 = in17; -assign out18 = in18; -assign mid_out18 = in18; -assign out19 = in19; -assign mid_out19 = in19; -assign out20 = in20; -assign mid_out20 = in20; -assign out21 = in21; -assign mid_out21 = in21; -assign out22 = in22; -assign mid_out22 = in22; -assign out23 = in23; -assign mid_out23 = in23; -assign out24 = in24; -assign mid_out24 = in24; -assign out25 = in25; -assign mid_out25 = in25; -assign out26 = in26; -assign mid_out26 = in26; -assign out27 = in27; -assign mid_out27 = in27; -assign out28 = in28; -assign mid_out28 = in28; -assign out29 = in29; -assign mid_out29 = in29; -assign out30 = in30; -assign mid_out30 = in30; -assign out31 = in31; -assign mid_out31 = in31; -assign out32 = in32; -assign mid_out32 = in32; -assign out33 = in33; -assign mid_out33 = in33; -assign out34 = in34; -assign mid_out34 = in34; -assign out35 = in35; -assign mid_out35 = in35; -assign out36 = in36; -assign mid_out36 = in36; -assign out37 = in37; -assign mid_out37 = in37; -assign out38 = in38; -assign mid_out38 = in38; -assign out39 = in39; -assign mid_out39 = in39; -assign out40 = in40; -assign mid_out40 = in40; -assign out41 = in41; -assign mid_out41 = in41; -assign out42 = in42; -assign mid_out42 = in42; -assign out43 = in43; -assign mid_out43 = in43; -assign out44 = in44; -assign mid_out44 = in44; -assign out45 = in45; -assign mid_out45 = in45; -assign out46 = in46; -assign mid_out46 = in46; -assign out47 = in47; -assign mid_out47 = in47; -assign out48 = in48; -assign mid_out48 = in48; -assign out49 = in49; -assign mid_out49 = in49; -assign out50 = in50; -assign mid_out50 = in50; -assign out51 = in51; -assign mid_out51 = in51; -assign out52 = in52; -assign mid_out52 = in52; -assign out53 = in53; -assign mid_out53 = in53; -assign out54 = in54; -assign mid_out54 = in54; -assign out55 = in55; -assign mid_out55 = in55; -assign out56 = in56; -assign mid_out56 = in56; -assign out57 = in57; -assign mid_out57 = in57; -assign out58 = in58; -assign mid_out58 = in58; -assign out59 = in59; -assign mid_out59 = in59; -assign out60 = in60; -assign mid_out60 = in60; -assign out61 = in61; -assign mid_out61 = in61; -assign out62 = in62; -assign mid_out62 = in62; -assign out63 = in63; -assign mid_out63 = in63; -assign out64 = in64; -assign mid_out64 = in64; -assign out65 = in65; -assign mid_out65 = in65; -assign out66 = in66; -assign mid_out66 = in66; -assign out67 = in67; -assign mid_out67 = in67; -assign out68 = in68; -assign mid_out68 = in68; -assign out69 = in69; -assign mid_out69 = in69; -assign out70 = in70; -assign mid_out70 = in70; -assign out71 = in71; -assign mid_out71 = in71; -assign out72 = in72; -assign mid_out72 = in72; -assign out73 = in73; -assign mid_out73 = in73; -assign out74 = in74; -assign mid_out74 = in74; -assign out75 = in75; -assign mid_out75 = in75; -assign out76 = in76; -assign mid_out76 = in76; -assign out77 = in77; -assign mid_out77 = in77; -assign out78 = in78; -assign mid_out78 = in78; -assign out79 = in79; -assign mid_out79 = in79; -assign out80 = in80; -assign mid_out80 = in80; -assign out81 = in81; -assign mid_out81 = in81; -assign out82 = in82; -assign mid_out82 = in82; -assign out83 = in83; -assign mid_out83 = in83; -assign out84 = in84; -assign mid_out84 = in84; -assign out85 = in85; -assign mid_out85 = in85; -assign out86 = in86; -assign mid_out86 = in86; -assign out87 = in87; -assign mid_out87 = in87; -assign out88 = in88; -assign mid_out88 = in88; -assign out89 = in89; -assign mid_out89 = in89; -assign out90 = in90; -assign mid_out90 = in90; -assign out91 = in91; -assign mid_out91 = in91; -assign out92 = in92; -assign mid_out92 = in92; -assign out93 = in93; -assign mid_out93 = in93; -assign out94 = in94; -assign mid_out94 = in94; -assign out95 = in95; -assign mid_out95 = in95; -assign out96 = in96; -assign mid_out96 = in96; -assign out97 = in97; -assign mid_out97 = in97; -assign out98 = in98; -assign mid_out98 = in98; -assign out99 = in99; -assign mid_out99 = in99; -endmodule -//----- END Verilog Module of Channel X [1][1] ----- - diff --git a/examples/verilog_test_example_2/routing/chany_0_1.v b/examples/verilog_test_example_2/routing/chany_0_1.v deleted file mode 100644 index 0edcb3748..000000000 --- a/examples/verilog_test_example_2/routing/chany_0_1.v +++ /dev/null @@ -1,525 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Routing Channel - Y direction [0][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module Channel Y [0][1] ----- -module chany_0__1_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, - input in0, //--- track 0 input - output out1, //--- track 1 output - input in2, //--- track 2 input - output out3, //--- track 3 output - input in4, //--- track 4 input - output out5, //--- track 5 output - input in6, //--- track 6 input - output out7, //--- track 7 output - input in8, //--- track 8 input - output out9, //--- track 9 output - input in10, //--- track 10 input - output out11, //--- track 11 output - input in12, //--- track 12 input - output out13, //--- track 13 output - input in14, //--- track 14 input - output out15, //--- track 15 output - input in16, //--- track 16 input - output out17, //--- track 17 output - input in18, //--- track 18 input - output out19, //--- track 19 output - input in20, //--- track 20 input - output out21, //--- track 21 output - input in22, //--- track 22 input - output out23, //--- track 23 output - input in24, //--- track 24 input - output out25, //--- track 25 output - input in26, //--- track 26 input - output out27, //--- track 27 output - input in28, //--- track 28 input - output out29, //--- track 29 output - input in30, //--- track 30 input - output out31, //--- track 31 output - input in32, //--- track 32 input - output out33, //--- track 33 output - input in34, //--- track 34 input - output out35, //--- track 35 output - input in36, //--- track 36 input - output out37, //--- track 37 output - input in38, //--- track 38 input - output out39, //--- track 39 output - input in40, //--- track 40 input - output out41, //--- track 41 output - input in42, //--- track 42 input - output out43, //--- track 43 output - input in44, //--- track 44 input - output out45, //--- track 45 output - input in46, //--- track 46 input - output out47, //--- track 47 output - input in48, //--- track 48 input - output out49, //--- track 49 output - input in50, //--- track 50 input - output out51, //--- track 51 output - input in52, //--- track 52 input - output out53, //--- track 53 output - input in54, //--- track 54 input - output out55, //--- track 55 output - input in56, //--- track 56 input - output out57, //--- track 57 output - input in58, //--- track 58 input - output out59, //--- track 59 output - input in60, //--- track 60 input - output out61, //--- track 61 output - input in62, //--- track 62 input - output out63, //--- track 63 output - input in64, //--- track 64 input - output out65, //--- track 65 output - input in66, //--- track 66 input - output out67, //--- track 67 output - input in68, //--- track 68 input - output out69, //--- track 69 output - input in70, //--- track 70 input - output out71, //--- track 71 output - input in72, //--- track 72 input - output out73, //--- track 73 output - input in74, //--- track 74 input - output out75, //--- track 75 output - input in76, //--- track 76 input - output out77, //--- track 77 output - input in78, //--- track 78 input - output out79, //--- track 79 output - input in80, //--- track 80 input - output out81, //--- track 81 output - input in82, //--- track 82 input - output out83, //--- track 83 output - input in84, //--- track 84 input - output out85, //--- track 85 output - input in86, //--- track 86 input - output out87, //--- track 87 output - input in88, //--- track 88 input - output out89, //--- track 89 output - input in90, //--- track 90 input - output out91, //--- track 91 output - input in92, //--- track 92 input - output out93, //--- track 93 output - input in94, //--- track 94 input - output out95, //--- track 95 output - input in96, //--- track 96 input - output out97, //--- track 97 output - input in98, //--- track 98 input - output out99, //--- track 99 output - output out0, //--- track 0 output - input in1, //--- track 1 input - output out2, //--- track 2 output - input in3, //--- track 3 input - output out4, //--- track 4 output - input in5, //--- track 5 input - output out6, //--- track 6 output - input in7, //--- track 7 input - output out8, //--- track 8 output - input in9, //--- track 9 input - output out10, //--- track 10 output - input in11, //--- track 11 input - output out12, //--- track 12 output - input in13, //--- track 13 input - output out14, //--- track 14 output - input in15, //--- track 15 input - output out16, //--- track 16 output - input in17, //--- track 17 input - output out18, //--- track 18 output - input in19, //--- track 19 input - output out20, //--- track 20 output - input in21, //--- track 21 input - output out22, //--- track 22 output - input in23, //--- track 23 input - output out24, //--- track 24 output - input in25, //--- track 25 input - output out26, //--- track 26 output - input in27, //--- track 27 input - output out28, //--- track 28 output - input in29, //--- track 29 input - output out30, //--- track 30 output - input in31, //--- track 31 input - output out32, //--- track 32 output - input in33, //--- track 33 input - output out34, //--- track 34 output - input in35, //--- track 35 input - output out36, //--- track 36 output - input in37, //--- track 37 input - output out38, //--- track 38 output - input in39, //--- track 39 input - output out40, //--- track 40 output - input in41, //--- track 41 input - output out42, //--- track 42 output - input in43, //--- track 43 input - output out44, //--- track 44 output - input in45, //--- track 45 input - output out46, //--- track 46 output - input in47, //--- track 47 input - output out48, //--- track 48 output - input in49, //--- track 49 input - output out50, //--- track 50 output - input in51, //--- track 51 input - output out52, //--- track 52 output - input in53, //--- track 53 input - output out54, //--- track 54 output - input in55, //--- track 55 input - output out56, //--- track 56 output - input in57, //--- track 57 input - output out58, //--- track 58 output - input in59, //--- track 59 input - output out60, //--- track 60 output - input in61, //--- track 61 input - output out62, //--- track 62 output - input in63, //--- track 63 input - output out64, //--- track 64 output - input in65, //--- track 65 input - output out66, //--- track 66 output - input in67, //--- track 67 input - output out68, //--- track 68 output - input in69, //--- track 69 input - output out70, //--- track 70 output - input in71, //--- track 71 input - output out72, //--- track 72 output - input in73, //--- track 73 input - output out74, //--- track 74 output - input in75, //--- track 75 input - output out76, //--- track 76 output - input in77, //--- track 77 input - output out78, //--- track 78 output - input in79, //--- track 79 input - output out80, //--- track 80 output - input in81, //--- track 81 input - output out82, //--- track 82 output - input in83, //--- track 83 input - output out84, //--- track 84 output - input in85, //--- track 85 input - output out86, //--- track 86 output - input in87, //--- track 87 input - output out88, //--- track 88 output - input in89, //--- track 89 input - output out90, //--- track 90 output - input in91, //--- track 91 input - output out92, //--- track 92 output - input in93, //--- track 93 input - output out94, //--- track 94 output - input in95, //--- track 95 input - output out96, //--- track 96 output - input in97, //--- track 97 input - output out98, //--- track 98 output - input in99, //--- track 99 input - output mid_out0, // Middle output 0 to logic blocks - output mid_out1, // Middle output 1 to logic blocks - output mid_out2, // Middle output 2 to logic blocks - output mid_out3, // Middle output 3 to logic blocks - output mid_out4, // Middle output 4 to logic blocks - output mid_out5, // Middle output 5 to logic blocks - output mid_out6, // Middle output 6 to logic blocks - output mid_out7, // Middle output 7 to logic blocks - output mid_out8, // Middle output 8 to logic blocks - output mid_out9, // Middle output 9 to logic blocks - output mid_out10, // Middle output 10 to logic blocks - output mid_out11, // Middle output 11 to logic blocks - output mid_out12, // Middle output 12 to logic blocks - output mid_out13, // Middle output 13 to logic blocks - output mid_out14, // Middle output 14 to logic blocks - output mid_out15, // Middle output 15 to logic blocks - output mid_out16, // Middle output 16 to logic blocks - output mid_out17, // Middle output 17 to logic blocks - output mid_out18, // Middle output 18 to logic blocks - output mid_out19, // Middle output 19 to logic blocks - output mid_out20, // Middle output 20 to logic blocks - output mid_out21, // Middle output 21 to logic blocks - output mid_out22, // Middle output 22 to logic blocks - output mid_out23, // Middle output 23 to logic blocks - output mid_out24, // Middle output 24 to logic blocks - output mid_out25, // Middle output 25 to logic blocks - output mid_out26, // Middle output 26 to logic blocks - output mid_out27, // Middle output 27 to logic blocks - output mid_out28, // Middle output 28 to logic blocks - output mid_out29, // Middle output 29 to logic blocks - output mid_out30, // Middle output 30 to logic blocks - output mid_out31, // Middle output 31 to logic blocks - output mid_out32, // Middle output 32 to logic blocks - output mid_out33, // Middle output 33 to logic blocks - output mid_out34, // Middle output 34 to logic blocks - output mid_out35, // Middle output 35 to logic blocks - output mid_out36, // Middle output 36 to logic blocks - output mid_out37, // Middle output 37 to logic blocks - output mid_out38, // Middle output 38 to logic blocks - output mid_out39, // Middle output 39 to logic blocks - output mid_out40, // Middle output 40 to logic blocks - output mid_out41, // Middle output 41 to logic blocks - output mid_out42, // Middle output 42 to logic blocks - output mid_out43, // Middle output 43 to logic blocks - output mid_out44, // Middle output 44 to logic blocks - output mid_out45, // Middle output 45 to logic blocks - output mid_out46, // Middle output 46 to logic blocks - output mid_out47, // Middle output 47 to logic blocks - output mid_out48, // Middle output 48 to logic blocks - output mid_out49, // Middle output 49 to logic blocks - output mid_out50, // Middle output 50 to logic blocks - output mid_out51, // Middle output 51 to logic blocks - output mid_out52, // Middle output 52 to logic blocks - output mid_out53, // Middle output 53 to logic blocks - output mid_out54, // Middle output 54 to logic blocks - output mid_out55, // Middle output 55 to logic blocks - output mid_out56, // Middle output 56 to logic blocks - output mid_out57, // Middle output 57 to logic blocks - output mid_out58, // Middle output 58 to logic blocks - output mid_out59, // Middle output 59 to logic blocks - output mid_out60, // Middle output 60 to logic blocks - output mid_out61, // Middle output 61 to logic blocks - output mid_out62, // Middle output 62 to logic blocks - output mid_out63, // Middle output 63 to logic blocks - output mid_out64, // Middle output 64 to logic blocks - output mid_out65, // Middle output 65 to logic blocks - output mid_out66, // Middle output 66 to logic blocks - output mid_out67, // Middle output 67 to logic blocks - output mid_out68, // Middle output 68 to logic blocks - output mid_out69, // Middle output 69 to logic blocks - output mid_out70, // Middle output 70 to logic blocks - output mid_out71, // Middle output 71 to logic blocks - output mid_out72, // Middle output 72 to logic blocks - output mid_out73, // Middle output 73 to logic blocks - output mid_out74, // Middle output 74 to logic blocks - output mid_out75, // Middle output 75 to logic blocks - output mid_out76, // Middle output 76 to logic blocks - output mid_out77, // Middle output 77 to logic blocks - output mid_out78, // Middle output 78 to logic blocks - output mid_out79, // Middle output 79 to logic blocks - output mid_out80, // Middle output 80 to logic blocks - output mid_out81, // Middle output 81 to logic blocks - output mid_out82, // Middle output 82 to logic blocks - output mid_out83, // Middle output 83 to logic blocks - output mid_out84, // Middle output 84 to logic blocks - output mid_out85, // Middle output 85 to logic blocks - output mid_out86, // Middle output 86 to logic blocks - output mid_out87, // Middle output 87 to logic blocks - output mid_out88, // Middle output 88 to logic blocks - output mid_out89, // Middle output 89 to logic blocks - output mid_out90, // Middle output 90 to logic blocks - output mid_out91, // Middle output 91 to logic blocks - output mid_out92, // Middle output 92 to logic blocks - output mid_out93, // Middle output 93 to logic blocks - output mid_out94, // Middle output 94 to logic blocks - output mid_out95, // Middle output 95 to logic blocks - output mid_out96, // Middle output 96 to logic blocks - output mid_out97, // Middle output 97 to logic blocks - output mid_out98, // Middle output 98 to logic blocks - output mid_out99 // Middle output 99 to logic blocks - ); -assign out0 = in0; -assign mid_out0 = in0; -assign out1 = in1; -assign mid_out1 = in1; -assign out2 = in2; -assign mid_out2 = in2; -assign out3 = in3; -assign mid_out3 = in3; -assign out4 = in4; -assign mid_out4 = in4; -assign out5 = in5; -assign mid_out5 = in5; -assign out6 = in6; -assign mid_out6 = in6; -assign out7 = in7; -assign mid_out7 = in7; -assign out8 = in8; -assign mid_out8 = in8; -assign out9 = in9; -assign mid_out9 = in9; -assign out10 = in10; -assign mid_out10 = in10; -assign out11 = in11; -assign mid_out11 = in11; -assign out12 = in12; -assign mid_out12 = in12; -assign out13 = in13; -assign mid_out13 = in13; -assign out14 = in14; -assign mid_out14 = in14; -assign out15 = in15; -assign mid_out15 = in15; -assign out16 = in16; -assign mid_out16 = in16; -assign out17 = in17; -assign mid_out17 = in17; -assign out18 = in18; -assign mid_out18 = in18; -assign out19 = in19; -assign mid_out19 = in19; -assign out20 = in20; -assign mid_out20 = in20; -assign out21 = in21; -assign mid_out21 = in21; -assign out22 = in22; -assign mid_out22 = in22; -assign out23 = in23; -assign mid_out23 = in23; -assign out24 = in24; -assign mid_out24 = in24; -assign out25 = in25; -assign mid_out25 = in25; -assign out26 = in26; -assign mid_out26 = in26; -assign out27 = in27; -assign mid_out27 = in27; -assign out28 = in28; -assign mid_out28 = in28; -assign out29 = in29; -assign mid_out29 = in29; -assign out30 = in30; -assign mid_out30 = in30; -assign out31 = in31; -assign mid_out31 = in31; -assign out32 = in32; -assign mid_out32 = in32; -assign out33 = in33; -assign mid_out33 = in33; -assign out34 = in34; -assign mid_out34 = in34; -assign out35 = in35; -assign mid_out35 = in35; -assign out36 = in36; -assign mid_out36 = in36; -assign out37 = in37; -assign mid_out37 = in37; -assign out38 = in38; -assign mid_out38 = in38; -assign out39 = in39; -assign mid_out39 = in39; -assign out40 = in40; -assign mid_out40 = in40; -assign out41 = in41; -assign mid_out41 = in41; -assign out42 = in42; -assign mid_out42 = in42; -assign out43 = in43; -assign mid_out43 = in43; -assign out44 = in44; -assign mid_out44 = in44; -assign out45 = in45; -assign mid_out45 = in45; -assign out46 = in46; -assign mid_out46 = in46; -assign out47 = in47; -assign mid_out47 = in47; -assign out48 = in48; -assign mid_out48 = in48; -assign out49 = in49; -assign mid_out49 = in49; -assign out50 = in50; -assign mid_out50 = in50; -assign out51 = in51; -assign mid_out51 = in51; -assign out52 = in52; -assign mid_out52 = in52; -assign out53 = in53; -assign mid_out53 = in53; -assign out54 = in54; -assign mid_out54 = in54; -assign out55 = in55; -assign mid_out55 = in55; -assign out56 = in56; -assign mid_out56 = in56; -assign out57 = in57; -assign mid_out57 = in57; -assign out58 = in58; -assign mid_out58 = in58; -assign out59 = in59; -assign mid_out59 = in59; -assign out60 = in60; -assign mid_out60 = in60; -assign out61 = in61; -assign mid_out61 = in61; -assign out62 = in62; -assign mid_out62 = in62; -assign out63 = in63; -assign mid_out63 = in63; -assign out64 = in64; -assign mid_out64 = in64; -assign out65 = in65; -assign mid_out65 = in65; -assign out66 = in66; -assign mid_out66 = in66; -assign out67 = in67; -assign mid_out67 = in67; -assign out68 = in68; -assign mid_out68 = in68; -assign out69 = in69; -assign mid_out69 = in69; -assign out70 = in70; -assign mid_out70 = in70; -assign out71 = in71; -assign mid_out71 = in71; -assign out72 = in72; -assign mid_out72 = in72; -assign out73 = in73; -assign mid_out73 = in73; -assign out74 = in74; -assign mid_out74 = in74; -assign out75 = in75; -assign mid_out75 = in75; -assign out76 = in76; -assign mid_out76 = in76; -assign out77 = in77; -assign mid_out77 = in77; -assign out78 = in78; -assign mid_out78 = in78; -assign out79 = in79; -assign mid_out79 = in79; -assign out80 = in80; -assign mid_out80 = in80; -assign out81 = in81; -assign mid_out81 = in81; -assign out82 = in82; -assign mid_out82 = in82; -assign out83 = in83; -assign mid_out83 = in83; -assign out84 = in84; -assign mid_out84 = in84; -assign out85 = in85; -assign mid_out85 = in85; -assign out86 = in86; -assign mid_out86 = in86; -assign out87 = in87; -assign mid_out87 = in87; -assign out88 = in88; -assign mid_out88 = in88; -assign out89 = in89; -assign mid_out89 = in89; -assign out90 = in90; -assign mid_out90 = in90; -assign out91 = in91; -assign mid_out91 = in91; -assign out92 = in92; -assign mid_out92 = in92; -assign out93 = in93; -assign mid_out93 = in93; -assign out94 = in94; -assign mid_out94 = in94; -assign out95 = in95; -assign mid_out95 = in95; -assign out96 = in96; -assign mid_out96 = in96; -assign out97 = in97; -assign mid_out97 = in97; -assign out98 = in98; -assign mid_out98 = in98; -assign out99 = in99; -assign mid_out99 = in99; -endmodule -//----- END Verilog Module of Channel Y [0][1] ----- - diff --git a/examples/verilog_test_example_2/routing/chany_1_1.v b/examples/verilog_test_example_2/routing/chany_1_1.v deleted file mode 100644 index d6d5d4970..000000000 --- a/examples/verilog_test_example_2/routing/chany_1_1.v +++ /dev/null @@ -1,525 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Routing Channel - Y direction [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module Channel Y [1][1] ----- -module chany_1__1_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, - input in0, //--- track 0 input - output out1, //--- track 1 output - input in2, //--- track 2 input - output out3, //--- track 3 output - input in4, //--- track 4 input - output out5, //--- track 5 output - input in6, //--- track 6 input - output out7, //--- track 7 output - input in8, //--- track 8 input - output out9, //--- track 9 output - input in10, //--- track 10 input - output out11, //--- track 11 output - input in12, //--- track 12 input - output out13, //--- track 13 output - input in14, //--- track 14 input - output out15, //--- track 15 output - input in16, //--- track 16 input - output out17, //--- track 17 output - input in18, //--- track 18 input - output out19, //--- track 19 output - input in20, //--- track 20 input - output out21, //--- track 21 output - input in22, //--- track 22 input - output out23, //--- track 23 output - input in24, //--- track 24 input - output out25, //--- track 25 output - input in26, //--- track 26 input - output out27, //--- track 27 output - input in28, //--- track 28 input - output out29, //--- track 29 output - input in30, //--- track 30 input - output out31, //--- track 31 output - input in32, //--- track 32 input - output out33, //--- track 33 output - input in34, //--- track 34 input - output out35, //--- track 35 output - input in36, //--- track 36 input - output out37, //--- track 37 output - input in38, //--- track 38 input - output out39, //--- track 39 output - input in40, //--- track 40 input - output out41, //--- track 41 output - input in42, //--- track 42 input - output out43, //--- track 43 output - input in44, //--- track 44 input - output out45, //--- track 45 output - input in46, //--- track 46 input - output out47, //--- track 47 output - input in48, //--- track 48 input - output out49, //--- track 49 output - input in50, //--- track 50 input - output out51, //--- track 51 output - input in52, //--- track 52 input - output out53, //--- track 53 output - input in54, //--- track 54 input - output out55, //--- track 55 output - input in56, //--- track 56 input - output out57, //--- track 57 output - input in58, //--- track 58 input - output out59, //--- track 59 output - input in60, //--- track 60 input - output out61, //--- track 61 output - input in62, //--- track 62 input - output out63, //--- track 63 output - input in64, //--- track 64 input - output out65, //--- track 65 output - input in66, //--- track 66 input - output out67, //--- track 67 output - input in68, //--- track 68 input - output out69, //--- track 69 output - input in70, //--- track 70 input - output out71, //--- track 71 output - input in72, //--- track 72 input - output out73, //--- track 73 output - input in74, //--- track 74 input - output out75, //--- track 75 output - input in76, //--- track 76 input - output out77, //--- track 77 output - input in78, //--- track 78 input - output out79, //--- track 79 output - input in80, //--- track 80 input - output out81, //--- track 81 output - input in82, //--- track 82 input - output out83, //--- track 83 output - input in84, //--- track 84 input - output out85, //--- track 85 output - input in86, //--- track 86 input - output out87, //--- track 87 output - input in88, //--- track 88 input - output out89, //--- track 89 output - input in90, //--- track 90 input - output out91, //--- track 91 output - input in92, //--- track 92 input - output out93, //--- track 93 output - input in94, //--- track 94 input - output out95, //--- track 95 output - input in96, //--- track 96 input - output out97, //--- track 97 output - input in98, //--- track 98 input - output out99, //--- track 99 output - output out0, //--- track 0 output - input in1, //--- track 1 input - output out2, //--- track 2 output - input in3, //--- track 3 input - output out4, //--- track 4 output - input in5, //--- track 5 input - output out6, //--- track 6 output - input in7, //--- track 7 input - output out8, //--- track 8 output - input in9, //--- track 9 input - output out10, //--- track 10 output - input in11, //--- track 11 input - output out12, //--- track 12 output - input in13, //--- track 13 input - output out14, //--- track 14 output - input in15, //--- track 15 input - output out16, //--- track 16 output - input in17, //--- track 17 input - output out18, //--- track 18 output - input in19, //--- track 19 input - output out20, //--- track 20 output - input in21, //--- track 21 input - output out22, //--- track 22 output - input in23, //--- track 23 input - output out24, //--- track 24 output - input in25, //--- track 25 input - output out26, //--- track 26 output - input in27, //--- track 27 input - output out28, //--- track 28 output - input in29, //--- track 29 input - output out30, //--- track 30 output - input in31, //--- track 31 input - output out32, //--- track 32 output - input in33, //--- track 33 input - output out34, //--- track 34 output - input in35, //--- track 35 input - output out36, //--- track 36 output - input in37, //--- track 37 input - output out38, //--- track 38 output - input in39, //--- track 39 input - output out40, //--- track 40 output - input in41, //--- track 41 input - output out42, //--- track 42 output - input in43, //--- track 43 input - output out44, //--- track 44 output - input in45, //--- track 45 input - output out46, //--- track 46 output - input in47, //--- track 47 input - output out48, //--- track 48 output - input in49, //--- track 49 input - output out50, //--- track 50 output - input in51, //--- track 51 input - output out52, //--- track 52 output - input in53, //--- track 53 input - output out54, //--- track 54 output - input in55, //--- track 55 input - output out56, //--- track 56 output - input in57, //--- track 57 input - output out58, //--- track 58 output - input in59, //--- track 59 input - output out60, //--- track 60 output - input in61, //--- track 61 input - output out62, //--- track 62 output - input in63, //--- track 63 input - output out64, //--- track 64 output - input in65, //--- track 65 input - output out66, //--- track 66 output - input in67, //--- track 67 input - output out68, //--- track 68 output - input in69, //--- track 69 input - output out70, //--- track 70 output - input in71, //--- track 71 input - output out72, //--- track 72 output - input in73, //--- track 73 input - output out74, //--- track 74 output - input in75, //--- track 75 input - output out76, //--- track 76 output - input in77, //--- track 77 input - output out78, //--- track 78 output - input in79, //--- track 79 input - output out80, //--- track 80 output - input in81, //--- track 81 input - output out82, //--- track 82 output - input in83, //--- track 83 input - output out84, //--- track 84 output - input in85, //--- track 85 input - output out86, //--- track 86 output - input in87, //--- track 87 input - output out88, //--- track 88 output - input in89, //--- track 89 input - output out90, //--- track 90 output - input in91, //--- track 91 input - output out92, //--- track 92 output - input in93, //--- track 93 input - output out94, //--- track 94 output - input in95, //--- track 95 input - output out96, //--- track 96 output - input in97, //--- track 97 input - output out98, //--- track 98 output - input in99, //--- track 99 input - output mid_out0, // Middle output 0 to logic blocks - output mid_out1, // Middle output 1 to logic blocks - output mid_out2, // Middle output 2 to logic blocks - output mid_out3, // Middle output 3 to logic blocks - output mid_out4, // Middle output 4 to logic blocks - output mid_out5, // Middle output 5 to logic blocks - output mid_out6, // Middle output 6 to logic blocks - output mid_out7, // Middle output 7 to logic blocks - output mid_out8, // Middle output 8 to logic blocks - output mid_out9, // Middle output 9 to logic blocks - output mid_out10, // Middle output 10 to logic blocks - output mid_out11, // Middle output 11 to logic blocks - output mid_out12, // Middle output 12 to logic blocks - output mid_out13, // Middle output 13 to logic blocks - output mid_out14, // Middle output 14 to logic blocks - output mid_out15, // Middle output 15 to logic blocks - output mid_out16, // Middle output 16 to logic blocks - output mid_out17, // Middle output 17 to logic blocks - output mid_out18, // Middle output 18 to logic blocks - output mid_out19, // Middle output 19 to logic blocks - output mid_out20, // Middle output 20 to logic blocks - output mid_out21, // Middle output 21 to logic blocks - output mid_out22, // Middle output 22 to logic blocks - output mid_out23, // Middle output 23 to logic blocks - output mid_out24, // Middle output 24 to logic blocks - output mid_out25, // Middle output 25 to logic blocks - output mid_out26, // Middle output 26 to logic blocks - output mid_out27, // Middle output 27 to logic blocks - output mid_out28, // Middle output 28 to logic blocks - output mid_out29, // Middle output 29 to logic blocks - output mid_out30, // Middle output 30 to logic blocks - output mid_out31, // Middle output 31 to logic blocks - output mid_out32, // Middle output 32 to logic blocks - output mid_out33, // Middle output 33 to logic blocks - output mid_out34, // Middle output 34 to logic blocks - output mid_out35, // Middle output 35 to logic blocks - output mid_out36, // Middle output 36 to logic blocks - output mid_out37, // Middle output 37 to logic blocks - output mid_out38, // Middle output 38 to logic blocks - output mid_out39, // Middle output 39 to logic blocks - output mid_out40, // Middle output 40 to logic blocks - output mid_out41, // Middle output 41 to logic blocks - output mid_out42, // Middle output 42 to logic blocks - output mid_out43, // Middle output 43 to logic blocks - output mid_out44, // Middle output 44 to logic blocks - output mid_out45, // Middle output 45 to logic blocks - output mid_out46, // Middle output 46 to logic blocks - output mid_out47, // Middle output 47 to logic blocks - output mid_out48, // Middle output 48 to logic blocks - output mid_out49, // Middle output 49 to logic blocks - output mid_out50, // Middle output 50 to logic blocks - output mid_out51, // Middle output 51 to logic blocks - output mid_out52, // Middle output 52 to logic blocks - output mid_out53, // Middle output 53 to logic blocks - output mid_out54, // Middle output 54 to logic blocks - output mid_out55, // Middle output 55 to logic blocks - output mid_out56, // Middle output 56 to logic blocks - output mid_out57, // Middle output 57 to logic blocks - output mid_out58, // Middle output 58 to logic blocks - output mid_out59, // Middle output 59 to logic blocks - output mid_out60, // Middle output 60 to logic blocks - output mid_out61, // Middle output 61 to logic blocks - output mid_out62, // Middle output 62 to logic blocks - output mid_out63, // Middle output 63 to logic blocks - output mid_out64, // Middle output 64 to logic blocks - output mid_out65, // Middle output 65 to logic blocks - output mid_out66, // Middle output 66 to logic blocks - output mid_out67, // Middle output 67 to logic blocks - output mid_out68, // Middle output 68 to logic blocks - output mid_out69, // Middle output 69 to logic blocks - output mid_out70, // Middle output 70 to logic blocks - output mid_out71, // Middle output 71 to logic blocks - output mid_out72, // Middle output 72 to logic blocks - output mid_out73, // Middle output 73 to logic blocks - output mid_out74, // Middle output 74 to logic blocks - output mid_out75, // Middle output 75 to logic blocks - output mid_out76, // Middle output 76 to logic blocks - output mid_out77, // Middle output 77 to logic blocks - output mid_out78, // Middle output 78 to logic blocks - output mid_out79, // Middle output 79 to logic blocks - output mid_out80, // Middle output 80 to logic blocks - output mid_out81, // Middle output 81 to logic blocks - output mid_out82, // Middle output 82 to logic blocks - output mid_out83, // Middle output 83 to logic blocks - output mid_out84, // Middle output 84 to logic blocks - output mid_out85, // Middle output 85 to logic blocks - output mid_out86, // Middle output 86 to logic blocks - output mid_out87, // Middle output 87 to logic blocks - output mid_out88, // Middle output 88 to logic blocks - output mid_out89, // Middle output 89 to logic blocks - output mid_out90, // Middle output 90 to logic blocks - output mid_out91, // Middle output 91 to logic blocks - output mid_out92, // Middle output 92 to logic blocks - output mid_out93, // Middle output 93 to logic blocks - output mid_out94, // Middle output 94 to logic blocks - output mid_out95, // Middle output 95 to logic blocks - output mid_out96, // Middle output 96 to logic blocks - output mid_out97, // Middle output 97 to logic blocks - output mid_out98, // Middle output 98 to logic blocks - output mid_out99 // Middle output 99 to logic blocks - ); -assign out0 = in0; -assign mid_out0 = in0; -assign out1 = in1; -assign mid_out1 = in1; -assign out2 = in2; -assign mid_out2 = in2; -assign out3 = in3; -assign mid_out3 = in3; -assign out4 = in4; -assign mid_out4 = in4; -assign out5 = in5; -assign mid_out5 = in5; -assign out6 = in6; -assign mid_out6 = in6; -assign out7 = in7; -assign mid_out7 = in7; -assign out8 = in8; -assign mid_out8 = in8; -assign out9 = in9; -assign mid_out9 = in9; -assign out10 = in10; -assign mid_out10 = in10; -assign out11 = in11; -assign mid_out11 = in11; -assign out12 = in12; -assign mid_out12 = in12; -assign out13 = in13; -assign mid_out13 = in13; -assign out14 = in14; -assign mid_out14 = in14; -assign out15 = in15; -assign mid_out15 = in15; -assign out16 = in16; -assign mid_out16 = in16; -assign out17 = in17; -assign mid_out17 = in17; -assign out18 = in18; -assign mid_out18 = in18; -assign out19 = in19; -assign mid_out19 = in19; -assign out20 = in20; -assign mid_out20 = in20; -assign out21 = in21; -assign mid_out21 = in21; -assign out22 = in22; -assign mid_out22 = in22; -assign out23 = in23; -assign mid_out23 = in23; -assign out24 = in24; -assign mid_out24 = in24; -assign out25 = in25; -assign mid_out25 = in25; -assign out26 = in26; -assign mid_out26 = in26; -assign out27 = in27; -assign mid_out27 = in27; -assign out28 = in28; -assign mid_out28 = in28; -assign out29 = in29; -assign mid_out29 = in29; -assign out30 = in30; -assign mid_out30 = in30; -assign out31 = in31; -assign mid_out31 = in31; -assign out32 = in32; -assign mid_out32 = in32; -assign out33 = in33; -assign mid_out33 = in33; -assign out34 = in34; -assign mid_out34 = in34; -assign out35 = in35; -assign mid_out35 = in35; -assign out36 = in36; -assign mid_out36 = in36; -assign out37 = in37; -assign mid_out37 = in37; -assign out38 = in38; -assign mid_out38 = in38; -assign out39 = in39; -assign mid_out39 = in39; -assign out40 = in40; -assign mid_out40 = in40; -assign out41 = in41; -assign mid_out41 = in41; -assign out42 = in42; -assign mid_out42 = in42; -assign out43 = in43; -assign mid_out43 = in43; -assign out44 = in44; -assign mid_out44 = in44; -assign out45 = in45; -assign mid_out45 = in45; -assign out46 = in46; -assign mid_out46 = in46; -assign out47 = in47; -assign mid_out47 = in47; -assign out48 = in48; -assign mid_out48 = in48; -assign out49 = in49; -assign mid_out49 = in49; -assign out50 = in50; -assign mid_out50 = in50; -assign out51 = in51; -assign mid_out51 = in51; -assign out52 = in52; -assign mid_out52 = in52; -assign out53 = in53; -assign mid_out53 = in53; -assign out54 = in54; -assign mid_out54 = in54; -assign out55 = in55; -assign mid_out55 = in55; -assign out56 = in56; -assign mid_out56 = in56; -assign out57 = in57; -assign mid_out57 = in57; -assign out58 = in58; -assign mid_out58 = in58; -assign out59 = in59; -assign mid_out59 = in59; -assign out60 = in60; -assign mid_out60 = in60; -assign out61 = in61; -assign mid_out61 = in61; -assign out62 = in62; -assign mid_out62 = in62; -assign out63 = in63; -assign mid_out63 = in63; -assign out64 = in64; -assign mid_out64 = in64; -assign out65 = in65; -assign mid_out65 = in65; -assign out66 = in66; -assign mid_out66 = in66; -assign out67 = in67; -assign mid_out67 = in67; -assign out68 = in68; -assign mid_out68 = in68; -assign out69 = in69; -assign mid_out69 = in69; -assign out70 = in70; -assign mid_out70 = in70; -assign out71 = in71; -assign mid_out71 = in71; -assign out72 = in72; -assign mid_out72 = in72; -assign out73 = in73; -assign mid_out73 = in73; -assign out74 = in74; -assign mid_out74 = in74; -assign out75 = in75; -assign mid_out75 = in75; -assign out76 = in76; -assign mid_out76 = in76; -assign out77 = in77; -assign mid_out77 = in77; -assign out78 = in78; -assign mid_out78 = in78; -assign out79 = in79; -assign mid_out79 = in79; -assign out80 = in80; -assign mid_out80 = in80; -assign out81 = in81; -assign mid_out81 = in81; -assign out82 = in82; -assign mid_out82 = in82; -assign out83 = in83; -assign mid_out83 = in83; -assign out84 = in84; -assign mid_out84 = in84; -assign out85 = in85; -assign mid_out85 = in85; -assign out86 = in86; -assign mid_out86 = in86; -assign out87 = in87; -assign mid_out87 = in87; -assign out88 = in88; -assign mid_out88 = in88; -assign out89 = in89; -assign mid_out89 = in89; -assign out90 = in90; -assign mid_out90 = in90; -assign out91 = in91; -assign mid_out91 = in91; -assign out92 = in92; -assign mid_out92 = in92; -assign out93 = in93; -assign mid_out93 = in93; -assign out94 = in94; -assign mid_out94 = in94; -assign out95 = in95; -assign mid_out95 = in95; -assign out96 = in96; -assign mid_out96 = in96; -assign out97 = in97; -assign mid_out97 = in97; -assign out98 = in98; -assign mid_out98 = in98; -assign out99 = in99; -assign mid_out99 = in99; -endmodule -//----- END Verilog Module of Channel Y [1][1] ----- - diff --git a/examples/verilog_test_example_2/routing/routing.v b/examples/verilog_test_example_2/routing/routing.v deleted file mode 100644 index 02ef0bfd9..000000000 --- a/examples/verilog_test_example_2/routing/routing.v +++ /dev/null @@ -1,23 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Header file -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -`include "./verilog_test_example_2/routing/cby_1_1.v" -`include "./verilog_test_example_2/routing/cby_0_1.v" -`include "./verilog_test_example_2/routing/cbx_1_1.v" -`include "./verilog_test_example_2/routing/cbx_1_0.v" -`include "./verilog_test_example_2/routing/sb_1_1.v" -`include "./verilog_test_example_2/routing/sb_1_0.v" -`include "./verilog_test_example_2/routing/sb_0_1.v" -`include "./verilog_test_example_2/routing/sb_0_0.v" -`include "./verilog_test_example_2/routing/chany_1_1.v" -`include "./verilog_test_example_2/routing/chany_0_1.v" -`include "./verilog_test_example_2/routing/chanx_1_1.v" -`include "./verilog_test_example_2/routing/chanx_1_0.v" diff --git a/examples/verilog_test_example_2/routing/sb_0_0.v b/examples/verilog_test_example_2/routing/sb_0_0.v deleted file mode 100644 index d691bfc4d..000000000 --- a/examples/verilog_test_example_2/routing/sb_0_0.v +++ /dev/null @@ -1,1955 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Switch Block [0][0] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Switch Box[0][0] ----- -module sb_0__0_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -//----- Inputs/outputs of top side ----- - output chany_0__1__out_0_, - input chany_0__1__in_1_, - output chany_0__1__out_2_, - input chany_0__1__in_3_, - output chany_0__1__out_4_, - input chany_0__1__in_5_, - output chany_0__1__out_6_, - input chany_0__1__in_7_, - output chany_0__1__out_8_, - input chany_0__1__in_9_, - output chany_0__1__out_10_, - input chany_0__1__in_11_, - output chany_0__1__out_12_, - input chany_0__1__in_13_, - output chany_0__1__out_14_, - input chany_0__1__in_15_, - output chany_0__1__out_16_, - input chany_0__1__in_17_, - output chany_0__1__out_18_, - input chany_0__1__in_19_, - output chany_0__1__out_20_, - input chany_0__1__in_21_, - output chany_0__1__out_22_, - input chany_0__1__in_23_, - output chany_0__1__out_24_, - input chany_0__1__in_25_, - output chany_0__1__out_26_, - input chany_0__1__in_27_, - output chany_0__1__out_28_, - input chany_0__1__in_29_, - output chany_0__1__out_30_, - input chany_0__1__in_31_, - output chany_0__1__out_32_, - input chany_0__1__in_33_, - output chany_0__1__out_34_, - input chany_0__1__in_35_, - output chany_0__1__out_36_, - input chany_0__1__in_37_, - output chany_0__1__out_38_, - input chany_0__1__in_39_, - output chany_0__1__out_40_, - input chany_0__1__in_41_, - output chany_0__1__out_42_, - input chany_0__1__in_43_, - output chany_0__1__out_44_, - input chany_0__1__in_45_, - output chany_0__1__out_46_, - input chany_0__1__in_47_, - output chany_0__1__out_48_, - input chany_0__1__in_49_, - output chany_0__1__out_50_, - input chany_0__1__in_51_, - output chany_0__1__out_52_, - input chany_0__1__in_53_, - output chany_0__1__out_54_, - input chany_0__1__in_55_, - output chany_0__1__out_56_, - input chany_0__1__in_57_, - output chany_0__1__out_58_, - input chany_0__1__in_59_, - output chany_0__1__out_60_, - input chany_0__1__in_61_, - output chany_0__1__out_62_, - input chany_0__1__in_63_, - output chany_0__1__out_64_, - input chany_0__1__in_65_, - output chany_0__1__out_66_, - input chany_0__1__in_67_, - output chany_0__1__out_68_, - input chany_0__1__in_69_, - output chany_0__1__out_70_, - input chany_0__1__in_71_, - output chany_0__1__out_72_, - input chany_0__1__in_73_, - output chany_0__1__out_74_, - input chany_0__1__in_75_, - output chany_0__1__out_76_, - input chany_0__1__in_77_, - output chany_0__1__out_78_, - input chany_0__1__in_79_, - output chany_0__1__out_80_, - input chany_0__1__in_81_, - output chany_0__1__out_82_, - input chany_0__1__in_83_, - output chany_0__1__out_84_, - input chany_0__1__in_85_, - output chany_0__1__out_86_, - input chany_0__1__in_87_, - output chany_0__1__out_88_, - input chany_0__1__in_89_, - output chany_0__1__out_90_, - input chany_0__1__in_91_, - output chany_0__1__out_92_, - input chany_0__1__in_93_, - output chany_0__1__out_94_, - input chany_0__1__in_95_, - output chany_0__1__out_96_, - input chany_0__1__in_97_, - output chany_0__1__out_98_, - input chany_0__1__in_99_, -input grid_0__1__pin_0__1__1_, -input grid_0__1__pin_0__1__3_, -input grid_0__1__pin_0__1__5_, -input grid_0__1__pin_0__1__7_, -input grid_0__1__pin_0__1__9_, -input grid_0__1__pin_0__1__11_, -input grid_0__1__pin_0__1__13_, -input grid_0__1__pin_0__1__15_, -input grid_1__1__pin_0__3__43_, -input grid_1__1__pin_0__3__47_, -//----- Inputs/outputs of right side ----- - output chanx_1__0__out_0_, - input chanx_1__0__in_1_, - output chanx_1__0__out_2_, - input chanx_1__0__in_3_, - output chanx_1__0__out_4_, - input chanx_1__0__in_5_, - output chanx_1__0__out_6_, - input chanx_1__0__in_7_, - output chanx_1__0__out_8_, - input chanx_1__0__in_9_, - output chanx_1__0__out_10_, - input chanx_1__0__in_11_, - output chanx_1__0__out_12_, - input chanx_1__0__in_13_, - output chanx_1__0__out_14_, - input chanx_1__0__in_15_, - output chanx_1__0__out_16_, - input chanx_1__0__in_17_, - output chanx_1__0__out_18_, - input chanx_1__0__in_19_, - output chanx_1__0__out_20_, - input chanx_1__0__in_21_, - output chanx_1__0__out_22_, - input chanx_1__0__in_23_, - output chanx_1__0__out_24_, - input chanx_1__0__in_25_, - output chanx_1__0__out_26_, - input chanx_1__0__in_27_, - output chanx_1__0__out_28_, - input chanx_1__0__in_29_, - output chanx_1__0__out_30_, - input chanx_1__0__in_31_, - output chanx_1__0__out_32_, - input chanx_1__0__in_33_, - output chanx_1__0__out_34_, - input chanx_1__0__in_35_, - output chanx_1__0__out_36_, - input chanx_1__0__in_37_, - output chanx_1__0__out_38_, - input chanx_1__0__in_39_, - output chanx_1__0__out_40_, - input chanx_1__0__in_41_, - output chanx_1__0__out_42_, - input chanx_1__0__in_43_, - output chanx_1__0__out_44_, - input chanx_1__0__in_45_, - output chanx_1__0__out_46_, - input chanx_1__0__in_47_, - output chanx_1__0__out_48_, - input chanx_1__0__in_49_, - output chanx_1__0__out_50_, - input chanx_1__0__in_51_, - output chanx_1__0__out_52_, - input chanx_1__0__in_53_, - output chanx_1__0__out_54_, - input chanx_1__0__in_55_, - output chanx_1__0__out_56_, - input chanx_1__0__in_57_, - output chanx_1__0__out_58_, - input chanx_1__0__in_59_, - output chanx_1__0__out_60_, - input chanx_1__0__in_61_, - output chanx_1__0__out_62_, - input chanx_1__0__in_63_, - output chanx_1__0__out_64_, - input chanx_1__0__in_65_, - output chanx_1__0__out_66_, - input chanx_1__0__in_67_, - output chanx_1__0__out_68_, - input chanx_1__0__in_69_, - output chanx_1__0__out_70_, - input chanx_1__0__in_71_, - output chanx_1__0__out_72_, - input chanx_1__0__in_73_, - output chanx_1__0__out_74_, - input chanx_1__0__in_75_, - output chanx_1__0__out_76_, - input chanx_1__0__in_77_, - output chanx_1__0__out_78_, - input chanx_1__0__in_79_, - output chanx_1__0__out_80_, - input chanx_1__0__in_81_, - output chanx_1__0__out_82_, - input chanx_1__0__in_83_, - output chanx_1__0__out_84_, - input chanx_1__0__in_85_, - output chanx_1__0__out_86_, - input chanx_1__0__in_87_, - output chanx_1__0__out_88_, - input chanx_1__0__in_89_, - output chanx_1__0__out_90_, - input chanx_1__0__in_91_, - output chanx_1__0__out_92_, - input chanx_1__0__in_93_, - output chanx_1__0__out_94_, - input chanx_1__0__in_95_, - output chanx_1__0__out_96_, - input chanx_1__0__in_97_, - output chanx_1__0__out_98_, - input chanx_1__0__in_99_, -input grid_1__1__pin_0__2__42_, -input grid_1__1__pin_0__2__46_, -input grid_1__0__pin_0__0__1_, -input grid_1__0__pin_0__0__3_, -input grid_1__0__pin_0__0__5_, -input grid_1__0__pin_0__0__7_, -input grid_1__0__pin_0__0__9_, -input grid_1__0__pin_0__0__11_, -input grid_1__0__pin_0__0__13_, -input grid_1__0__pin_0__0__15_, -//----- Inputs/outputs of bottom side ----- -//----- Inputs/outputs of left side ----- -input [0:99] sram_blwl_bl , -input [0:99] sram_blwl_wl , -input [0:99] sram_blwl_blb ); -//----- top side Multiplexers ----- -wire [0:1] mux_1level_tapbuf_size2_0_inbus; -assign mux_1level_tapbuf_size2_0_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_0_inbus[1] = chanx_1__0__in_3_ ; -wire [0:0] mux_1level_tapbuf_size2_0_configbus0; -wire [0:0] mux_1level_tapbuf_size2_0_configbus1; -wire [0:0] mux_1level_tapbuf_size2_0_sram_blwl_out ; -wire [0:0] mux_1level_tapbuf_size2_0_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_0_configbus0[0:0] = sram_blwl_bl[0:0] ; -assign mux_1level_tapbuf_size2_0_configbus1[0:0] = sram_blwl_wl[0:0] ; -wire [0:0] mux_1level_tapbuf_size2_0_configbus0_b; -assign mux_1level_tapbuf_size2_0_configbus0_b[0:0] = sram_blwl_blb[0:0] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_0_ (mux_1level_tapbuf_size2_0_inbus, chany_0__1__out_0_ , mux_1level_tapbuf_size2_0_sram_blwl_out[0:0] , -mux_1level_tapbuf_size2_0_sram_blwl_outb[0:0] ); -//----- SRAM bits for MUX[0], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_0_ (mux_1level_tapbuf_size2_0_sram_blwl_out[0:0] ,mux_1level_tapbuf_size2_0_sram_blwl_out[0:0] ,mux_1level_tapbuf_size2_0_sram_blwl_outb[0:0] ,mux_1level_tapbuf_size2_0_configbus0[0:0], mux_1level_tapbuf_size2_0_configbus1[0:0] , mux_1level_tapbuf_size2_0_configbus0_b[0:0] ); -wire [0:1] mux_1level_tapbuf_size2_1_inbus; -assign mux_1level_tapbuf_size2_1_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_1_inbus[1] = chanx_1__0__in_5_ ; -wire [1:1] mux_1level_tapbuf_size2_1_configbus0; -wire [1:1] mux_1level_tapbuf_size2_1_configbus1; -wire [1:1] mux_1level_tapbuf_size2_1_sram_blwl_out ; -wire [1:1] mux_1level_tapbuf_size2_1_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_1_configbus0[1:1] = sram_blwl_bl[1:1] ; -assign mux_1level_tapbuf_size2_1_configbus1[1:1] = sram_blwl_wl[1:1] ; -wire [1:1] mux_1level_tapbuf_size2_1_configbus0_b; -assign mux_1level_tapbuf_size2_1_configbus0_b[1:1] = sram_blwl_blb[1:1] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_1_ (mux_1level_tapbuf_size2_1_inbus, chany_0__1__out_2_ , mux_1level_tapbuf_size2_1_sram_blwl_out[1:1] , -mux_1level_tapbuf_size2_1_sram_blwl_outb[1:1] ); -//----- SRAM bits for MUX[1], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_1_ (mux_1level_tapbuf_size2_1_sram_blwl_out[1:1] ,mux_1level_tapbuf_size2_1_sram_blwl_out[1:1] ,mux_1level_tapbuf_size2_1_sram_blwl_outb[1:1] ,mux_1level_tapbuf_size2_1_configbus0[1:1], mux_1level_tapbuf_size2_1_configbus1[1:1] , mux_1level_tapbuf_size2_1_configbus0_b[1:1] ); -wire [0:1] mux_1level_tapbuf_size2_2_inbus; -assign mux_1level_tapbuf_size2_2_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_2_inbus[1] = chanx_1__0__in_7_ ; -wire [2:2] mux_1level_tapbuf_size2_2_configbus0; -wire [2:2] mux_1level_tapbuf_size2_2_configbus1; -wire [2:2] mux_1level_tapbuf_size2_2_sram_blwl_out ; -wire [2:2] mux_1level_tapbuf_size2_2_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_2_configbus0[2:2] = sram_blwl_bl[2:2] ; -assign mux_1level_tapbuf_size2_2_configbus1[2:2] = sram_blwl_wl[2:2] ; -wire [2:2] mux_1level_tapbuf_size2_2_configbus0_b; -assign mux_1level_tapbuf_size2_2_configbus0_b[2:2] = sram_blwl_blb[2:2] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_2_ (mux_1level_tapbuf_size2_2_inbus, chany_0__1__out_4_ , mux_1level_tapbuf_size2_2_sram_blwl_out[2:2] , -mux_1level_tapbuf_size2_2_sram_blwl_outb[2:2] ); -//----- SRAM bits for MUX[2], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_2_ (mux_1level_tapbuf_size2_2_sram_blwl_out[2:2] ,mux_1level_tapbuf_size2_2_sram_blwl_out[2:2] ,mux_1level_tapbuf_size2_2_sram_blwl_outb[2:2] ,mux_1level_tapbuf_size2_2_configbus0[2:2], mux_1level_tapbuf_size2_2_configbus1[2:2] , mux_1level_tapbuf_size2_2_configbus0_b[2:2] ); -wire [0:1] mux_1level_tapbuf_size2_3_inbus; -assign mux_1level_tapbuf_size2_3_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_3_inbus[1] = chanx_1__0__in_9_ ; -wire [3:3] mux_1level_tapbuf_size2_3_configbus0; -wire [3:3] mux_1level_tapbuf_size2_3_configbus1; -wire [3:3] mux_1level_tapbuf_size2_3_sram_blwl_out ; -wire [3:3] mux_1level_tapbuf_size2_3_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_3_configbus0[3:3] = sram_blwl_bl[3:3] ; -assign mux_1level_tapbuf_size2_3_configbus1[3:3] = sram_blwl_wl[3:3] ; -wire [3:3] mux_1level_tapbuf_size2_3_configbus0_b; -assign mux_1level_tapbuf_size2_3_configbus0_b[3:3] = sram_blwl_blb[3:3] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_3_ (mux_1level_tapbuf_size2_3_inbus, chany_0__1__out_6_ , mux_1level_tapbuf_size2_3_sram_blwl_out[3:3] , -mux_1level_tapbuf_size2_3_sram_blwl_outb[3:3] ); -//----- SRAM bits for MUX[3], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_3_ (mux_1level_tapbuf_size2_3_sram_blwl_out[3:3] ,mux_1level_tapbuf_size2_3_sram_blwl_out[3:3] ,mux_1level_tapbuf_size2_3_sram_blwl_outb[3:3] ,mux_1level_tapbuf_size2_3_configbus0[3:3], mux_1level_tapbuf_size2_3_configbus1[3:3] , mux_1level_tapbuf_size2_3_configbus0_b[3:3] ); -wire [0:1] mux_1level_tapbuf_size2_4_inbus; -assign mux_1level_tapbuf_size2_4_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_4_inbus[1] = chanx_1__0__in_11_ ; -wire [4:4] mux_1level_tapbuf_size2_4_configbus0; -wire [4:4] mux_1level_tapbuf_size2_4_configbus1; -wire [4:4] mux_1level_tapbuf_size2_4_sram_blwl_out ; -wire [4:4] mux_1level_tapbuf_size2_4_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_4_configbus0[4:4] = sram_blwl_bl[4:4] ; -assign mux_1level_tapbuf_size2_4_configbus1[4:4] = sram_blwl_wl[4:4] ; -wire [4:4] mux_1level_tapbuf_size2_4_configbus0_b; -assign mux_1level_tapbuf_size2_4_configbus0_b[4:4] = sram_blwl_blb[4:4] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_4_ (mux_1level_tapbuf_size2_4_inbus, chany_0__1__out_8_ , mux_1level_tapbuf_size2_4_sram_blwl_out[4:4] , -mux_1level_tapbuf_size2_4_sram_blwl_outb[4:4] ); -//----- SRAM bits for MUX[4], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_4_ (mux_1level_tapbuf_size2_4_sram_blwl_out[4:4] ,mux_1level_tapbuf_size2_4_sram_blwl_out[4:4] ,mux_1level_tapbuf_size2_4_sram_blwl_outb[4:4] ,mux_1level_tapbuf_size2_4_configbus0[4:4], mux_1level_tapbuf_size2_4_configbus1[4:4] , mux_1level_tapbuf_size2_4_configbus0_b[4:4] ); -wire [0:1] mux_1level_tapbuf_size2_5_inbus; -assign mux_1level_tapbuf_size2_5_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_5_inbus[1] = chanx_1__0__in_13_ ; -wire [5:5] mux_1level_tapbuf_size2_5_configbus0; -wire [5:5] mux_1level_tapbuf_size2_5_configbus1; -wire [5:5] mux_1level_tapbuf_size2_5_sram_blwl_out ; -wire [5:5] mux_1level_tapbuf_size2_5_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_5_configbus0[5:5] = sram_blwl_bl[5:5] ; -assign mux_1level_tapbuf_size2_5_configbus1[5:5] = sram_blwl_wl[5:5] ; -wire [5:5] mux_1level_tapbuf_size2_5_configbus0_b; -assign mux_1level_tapbuf_size2_5_configbus0_b[5:5] = sram_blwl_blb[5:5] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_5_ (mux_1level_tapbuf_size2_5_inbus, chany_0__1__out_10_ , mux_1level_tapbuf_size2_5_sram_blwl_out[5:5] , -mux_1level_tapbuf_size2_5_sram_blwl_outb[5:5] ); -//----- SRAM bits for MUX[5], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_5_ (mux_1level_tapbuf_size2_5_sram_blwl_out[5:5] ,mux_1level_tapbuf_size2_5_sram_blwl_out[5:5] ,mux_1level_tapbuf_size2_5_sram_blwl_outb[5:5] ,mux_1level_tapbuf_size2_5_configbus0[5:5], mux_1level_tapbuf_size2_5_configbus1[5:5] , mux_1level_tapbuf_size2_5_configbus0_b[5:5] ); -wire [0:1] mux_1level_tapbuf_size2_6_inbus; -assign mux_1level_tapbuf_size2_6_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_6_inbus[1] = chanx_1__0__in_15_ ; -wire [6:6] mux_1level_tapbuf_size2_6_configbus0; -wire [6:6] mux_1level_tapbuf_size2_6_configbus1; -wire [6:6] mux_1level_tapbuf_size2_6_sram_blwl_out ; -wire [6:6] mux_1level_tapbuf_size2_6_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_6_configbus0[6:6] = sram_blwl_bl[6:6] ; -assign mux_1level_tapbuf_size2_6_configbus1[6:6] = sram_blwl_wl[6:6] ; -wire [6:6] mux_1level_tapbuf_size2_6_configbus0_b; -assign mux_1level_tapbuf_size2_6_configbus0_b[6:6] = sram_blwl_blb[6:6] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_6_ (mux_1level_tapbuf_size2_6_inbus, chany_0__1__out_12_ , mux_1level_tapbuf_size2_6_sram_blwl_out[6:6] , -mux_1level_tapbuf_size2_6_sram_blwl_outb[6:6] ); -//----- SRAM bits for MUX[6], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_6_ (mux_1level_tapbuf_size2_6_sram_blwl_out[6:6] ,mux_1level_tapbuf_size2_6_sram_blwl_out[6:6] ,mux_1level_tapbuf_size2_6_sram_blwl_outb[6:6] ,mux_1level_tapbuf_size2_6_configbus0[6:6], mux_1level_tapbuf_size2_6_configbus1[6:6] , mux_1level_tapbuf_size2_6_configbus0_b[6:6] ); -wire [0:1] mux_1level_tapbuf_size2_7_inbus; -assign mux_1level_tapbuf_size2_7_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_7_inbus[1] = chanx_1__0__in_17_ ; -wire [7:7] mux_1level_tapbuf_size2_7_configbus0; -wire [7:7] mux_1level_tapbuf_size2_7_configbus1; -wire [7:7] mux_1level_tapbuf_size2_7_sram_blwl_out ; -wire [7:7] mux_1level_tapbuf_size2_7_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_7_configbus0[7:7] = sram_blwl_bl[7:7] ; -assign mux_1level_tapbuf_size2_7_configbus1[7:7] = sram_blwl_wl[7:7] ; -wire [7:7] mux_1level_tapbuf_size2_7_configbus0_b; -assign mux_1level_tapbuf_size2_7_configbus0_b[7:7] = sram_blwl_blb[7:7] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_7_ (mux_1level_tapbuf_size2_7_inbus, chany_0__1__out_14_ , mux_1level_tapbuf_size2_7_sram_blwl_out[7:7] , -mux_1level_tapbuf_size2_7_sram_blwl_outb[7:7] ); -//----- SRAM bits for MUX[7], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_7_ (mux_1level_tapbuf_size2_7_sram_blwl_out[7:7] ,mux_1level_tapbuf_size2_7_sram_blwl_out[7:7] ,mux_1level_tapbuf_size2_7_sram_blwl_outb[7:7] ,mux_1level_tapbuf_size2_7_configbus0[7:7], mux_1level_tapbuf_size2_7_configbus1[7:7] , mux_1level_tapbuf_size2_7_configbus0_b[7:7] ); -wire [0:1] mux_1level_tapbuf_size2_8_inbus; -assign mux_1level_tapbuf_size2_8_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_8_inbus[1] = chanx_1__0__in_19_ ; -wire [8:8] mux_1level_tapbuf_size2_8_configbus0; -wire [8:8] mux_1level_tapbuf_size2_8_configbus1; -wire [8:8] mux_1level_tapbuf_size2_8_sram_blwl_out ; -wire [8:8] mux_1level_tapbuf_size2_8_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_8_configbus0[8:8] = sram_blwl_bl[8:8] ; -assign mux_1level_tapbuf_size2_8_configbus1[8:8] = sram_blwl_wl[8:8] ; -wire [8:8] mux_1level_tapbuf_size2_8_configbus0_b; -assign mux_1level_tapbuf_size2_8_configbus0_b[8:8] = sram_blwl_blb[8:8] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_8_ (mux_1level_tapbuf_size2_8_inbus, chany_0__1__out_16_ , mux_1level_tapbuf_size2_8_sram_blwl_out[8:8] , -mux_1level_tapbuf_size2_8_sram_blwl_outb[8:8] ); -//----- SRAM bits for MUX[8], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_8_ (mux_1level_tapbuf_size2_8_sram_blwl_out[8:8] ,mux_1level_tapbuf_size2_8_sram_blwl_out[8:8] ,mux_1level_tapbuf_size2_8_sram_blwl_outb[8:8] ,mux_1level_tapbuf_size2_8_configbus0[8:8], mux_1level_tapbuf_size2_8_configbus1[8:8] , mux_1level_tapbuf_size2_8_configbus0_b[8:8] ); -wire [0:1] mux_1level_tapbuf_size2_9_inbus; -assign mux_1level_tapbuf_size2_9_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_9_inbus[1] = chanx_1__0__in_21_ ; -wire [9:9] mux_1level_tapbuf_size2_9_configbus0; -wire [9:9] mux_1level_tapbuf_size2_9_configbus1; -wire [9:9] mux_1level_tapbuf_size2_9_sram_blwl_out ; -wire [9:9] mux_1level_tapbuf_size2_9_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_9_configbus0[9:9] = sram_blwl_bl[9:9] ; -assign mux_1level_tapbuf_size2_9_configbus1[9:9] = sram_blwl_wl[9:9] ; -wire [9:9] mux_1level_tapbuf_size2_9_configbus0_b; -assign mux_1level_tapbuf_size2_9_configbus0_b[9:9] = sram_blwl_blb[9:9] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_9_ (mux_1level_tapbuf_size2_9_inbus, chany_0__1__out_18_ , mux_1level_tapbuf_size2_9_sram_blwl_out[9:9] , -mux_1level_tapbuf_size2_9_sram_blwl_outb[9:9] ); -//----- SRAM bits for MUX[9], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_9_ (mux_1level_tapbuf_size2_9_sram_blwl_out[9:9] ,mux_1level_tapbuf_size2_9_sram_blwl_out[9:9] ,mux_1level_tapbuf_size2_9_sram_blwl_outb[9:9] ,mux_1level_tapbuf_size2_9_configbus0[9:9], mux_1level_tapbuf_size2_9_configbus1[9:9] , mux_1level_tapbuf_size2_9_configbus0_b[9:9] ); -wire [0:1] mux_1level_tapbuf_size2_10_inbus; -assign mux_1level_tapbuf_size2_10_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_10_inbus[1] = chanx_1__0__in_23_ ; -wire [10:10] mux_1level_tapbuf_size2_10_configbus0; -wire [10:10] mux_1level_tapbuf_size2_10_configbus1; -wire [10:10] mux_1level_tapbuf_size2_10_sram_blwl_out ; -wire [10:10] mux_1level_tapbuf_size2_10_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_10_configbus0[10:10] = sram_blwl_bl[10:10] ; -assign mux_1level_tapbuf_size2_10_configbus1[10:10] = sram_blwl_wl[10:10] ; -wire [10:10] mux_1level_tapbuf_size2_10_configbus0_b; -assign mux_1level_tapbuf_size2_10_configbus0_b[10:10] = sram_blwl_blb[10:10] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_10_ (mux_1level_tapbuf_size2_10_inbus, chany_0__1__out_20_ , mux_1level_tapbuf_size2_10_sram_blwl_out[10:10] , -mux_1level_tapbuf_size2_10_sram_blwl_outb[10:10] ); -//----- SRAM bits for MUX[10], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_10_ (mux_1level_tapbuf_size2_10_sram_blwl_out[10:10] ,mux_1level_tapbuf_size2_10_sram_blwl_out[10:10] ,mux_1level_tapbuf_size2_10_sram_blwl_outb[10:10] ,mux_1level_tapbuf_size2_10_configbus0[10:10], mux_1level_tapbuf_size2_10_configbus1[10:10] , mux_1level_tapbuf_size2_10_configbus0_b[10:10] ); -wire [0:1] mux_1level_tapbuf_size2_11_inbus; -assign mux_1level_tapbuf_size2_11_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_11_inbus[1] = chanx_1__0__in_25_ ; -wire [11:11] mux_1level_tapbuf_size2_11_configbus0; -wire [11:11] mux_1level_tapbuf_size2_11_configbus1; -wire [11:11] mux_1level_tapbuf_size2_11_sram_blwl_out ; -wire [11:11] mux_1level_tapbuf_size2_11_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_11_configbus0[11:11] = sram_blwl_bl[11:11] ; -assign mux_1level_tapbuf_size2_11_configbus1[11:11] = sram_blwl_wl[11:11] ; -wire [11:11] mux_1level_tapbuf_size2_11_configbus0_b; -assign mux_1level_tapbuf_size2_11_configbus0_b[11:11] = sram_blwl_blb[11:11] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_11_ (mux_1level_tapbuf_size2_11_inbus, chany_0__1__out_22_ , mux_1level_tapbuf_size2_11_sram_blwl_out[11:11] , -mux_1level_tapbuf_size2_11_sram_blwl_outb[11:11] ); -//----- SRAM bits for MUX[11], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_11_ (mux_1level_tapbuf_size2_11_sram_blwl_out[11:11] ,mux_1level_tapbuf_size2_11_sram_blwl_out[11:11] ,mux_1level_tapbuf_size2_11_sram_blwl_outb[11:11] ,mux_1level_tapbuf_size2_11_configbus0[11:11], mux_1level_tapbuf_size2_11_configbus1[11:11] , mux_1level_tapbuf_size2_11_configbus0_b[11:11] ); -wire [0:1] mux_1level_tapbuf_size2_12_inbus; -assign mux_1level_tapbuf_size2_12_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_12_inbus[1] = chanx_1__0__in_27_ ; -wire [12:12] mux_1level_tapbuf_size2_12_configbus0; -wire [12:12] mux_1level_tapbuf_size2_12_configbus1; -wire [12:12] mux_1level_tapbuf_size2_12_sram_blwl_out ; -wire [12:12] mux_1level_tapbuf_size2_12_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_12_configbus0[12:12] = sram_blwl_bl[12:12] ; -assign mux_1level_tapbuf_size2_12_configbus1[12:12] = sram_blwl_wl[12:12] ; -wire [12:12] mux_1level_tapbuf_size2_12_configbus0_b; -assign mux_1level_tapbuf_size2_12_configbus0_b[12:12] = sram_blwl_blb[12:12] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_12_ (mux_1level_tapbuf_size2_12_inbus, chany_0__1__out_24_ , mux_1level_tapbuf_size2_12_sram_blwl_out[12:12] , -mux_1level_tapbuf_size2_12_sram_blwl_outb[12:12] ); -//----- SRAM bits for MUX[12], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_12_ (mux_1level_tapbuf_size2_12_sram_blwl_out[12:12] ,mux_1level_tapbuf_size2_12_sram_blwl_out[12:12] ,mux_1level_tapbuf_size2_12_sram_blwl_outb[12:12] ,mux_1level_tapbuf_size2_12_configbus0[12:12], mux_1level_tapbuf_size2_12_configbus1[12:12] , mux_1level_tapbuf_size2_12_configbus0_b[12:12] ); -wire [0:1] mux_1level_tapbuf_size2_13_inbus; -assign mux_1level_tapbuf_size2_13_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_13_inbus[1] = chanx_1__0__in_29_ ; -wire [13:13] mux_1level_tapbuf_size2_13_configbus0; -wire [13:13] mux_1level_tapbuf_size2_13_configbus1; -wire [13:13] mux_1level_tapbuf_size2_13_sram_blwl_out ; -wire [13:13] mux_1level_tapbuf_size2_13_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_13_configbus0[13:13] = sram_blwl_bl[13:13] ; -assign mux_1level_tapbuf_size2_13_configbus1[13:13] = sram_blwl_wl[13:13] ; -wire [13:13] mux_1level_tapbuf_size2_13_configbus0_b; -assign mux_1level_tapbuf_size2_13_configbus0_b[13:13] = sram_blwl_blb[13:13] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_13_ (mux_1level_tapbuf_size2_13_inbus, chany_0__1__out_26_ , mux_1level_tapbuf_size2_13_sram_blwl_out[13:13] , -mux_1level_tapbuf_size2_13_sram_blwl_outb[13:13] ); -//----- SRAM bits for MUX[13], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_13_ (mux_1level_tapbuf_size2_13_sram_blwl_out[13:13] ,mux_1level_tapbuf_size2_13_sram_blwl_out[13:13] ,mux_1level_tapbuf_size2_13_sram_blwl_outb[13:13] ,mux_1level_tapbuf_size2_13_configbus0[13:13], mux_1level_tapbuf_size2_13_configbus1[13:13] , mux_1level_tapbuf_size2_13_configbus0_b[13:13] ); -wire [0:1] mux_1level_tapbuf_size2_14_inbus; -assign mux_1level_tapbuf_size2_14_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_14_inbus[1] = chanx_1__0__in_31_ ; -wire [14:14] mux_1level_tapbuf_size2_14_configbus0; -wire [14:14] mux_1level_tapbuf_size2_14_configbus1; -wire [14:14] mux_1level_tapbuf_size2_14_sram_blwl_out ; -wire [14:14] mux_1level_tapbuf_size2_14_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_14_configbus0[14:14] = sram_blwl_bl[14:14] ; -assign mux_1level_tapbuf_size2_14_configbus1[14:14] = sram_blwl_wl[14:14] ; -wire [14:14] mux_1level_tapbuf_size2_14_configbus0_b; -assign mux_1level_tapbuf_size2_14_configbus0_b[14:14] = sram_blwl_blb[14:14] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_14_ (mux_1level_tapbuf_size2_14_inbus, chany_0__1__out_28_ , mux_1level_tapbuf_size2_14_sram_blwl_out[14:14] , -mux_1level_tapbuf_size2_14_sram_blwl_outb[14:14] ); -//----- SRAM bits for MUX[14], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_14_ (mux_1level_tapbuf_size2_14_sram_blwl_out[14:14] ,mux_1level_tapbuf_size2_14_sram_blwl_out[14:14] ,mux_1level_tapbuf_size2_14_sram_blwl_outb[14:14] ,mux_1level_tapbuf_size2_14_configbus0[14:14], mux_1level_tapbuf_size2_14_configbus1[14:14] , mux_1level_tapbuf_size2_14_configbus0_b[14:14] ); -wire [0:1] mux_1level_tapbuf_size2_15_inbus; -assign mux_1level_tapbuf_size2_15_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_15_inbus[1] = chanx_1__0__in_33_ ; -wire [15:15] mux_1level_tapbuf_size2_15_configbus0; -wire [15:15] mux_1level_tapbuf_size2_15_configbus1; -wire [15:15] mux_1level_tapbuf_size2_15_sram_blwl_out ; -wire [15:15] mux_1level_tapbuf_size2_15_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_15_configbus0[15:15] = sram_blwl_bl[15:15] ; -assign mux_1level_tapbuf_size2_15_configbus1[15:15] = sram_blwl_wl[15:15] ; -wire [15:15] mux_1level_tapbuf_size2_15_configbus0_b; -assign mux_1level_tapbuf_size2_15_configbus0_b[15:15] = sram_blwl_blb[15:15] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_15_ (mux_1level_tapbuf_size2_15_inbus, chany_0__1__out_30_ , mux_1level_tapbuf_size2_15_sram_blwl_out[15:15] , -mux_1level_tapbuf_size2_15_sram_blwl_outb[15:15] ); -//----- SRAM bits for MUX[15], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_15_ (mux_1level_tapbuf_size2_15_sram_blwl_out[15:15] ,mux_1level_tapbuf_size2_15_sram_blwl_out[15:15] ,mux_1level_tapbuf_size2_15_sram_blwl_outb[15:15] ,mux_1level_tapbuf_size2_15_configbus0[15:15], mux_1level_tapbuf_size2_15_configbus1[15:15] , mux_1level_tapbuf_size2_15_configbus0_b[15:15] ); -wire [0:1] mux_1level_tapbuf_size2_16_inbus; -assign mux_1level_tapbuf_size2_16_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_16_inbus[1] = chanx_1__0__in_35_ ; -wire [16:16] mux_1level_tapbuf_size2_16_configbus0; -wire [16:16] mux_1level_tapbuf_size2_16_configbus1; -wire [16:16] mux_1level_tapbuf_size2_16_sram_blwl_out ; -wire [16:16] mux_1level_tapbuf_size2_16_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_16_configbus0[16:16] = sram_blwl_bl[16:16] ; -assign mux_1level_tapbuf_size2_16_configbus1[16:16] = sram_blwl_wl[16:16] ; -wire [16:16] mux_1level_tapbuf_size2_16_configbus0_b; -assign mux_1level_tapbuf_size2_16_configbus0_b[16:16] = sram_blwl_blb[16:16] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_16_ (mux_1level_tapbuf_size2_16_inbus, chany_0__1__out_32_ , mux_1level_tapbuf_size2_16_sram_blwl_out[16:16] , -mux_1level_tapbuf_size2_16_sram_blwl_outb[16:16] ); -//----- SRAM bits for MUX[16], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_16_ (mux_1level_tapbuf_size2_16_sram_blwl_out[16:16] ,mux_1level_tapbuf_size2_16_sram_blwl_out[16:16] ,mux_1level_tapbuf_size2_16_sram_blwl_outb[16:16] ,mux_1level_tapbuf_size2_16_configbus0[16:16], mux_1level_tapbuf_size2_16_configbus1[16:16] , mux_1level_tapbuf_size2_16_configbus0_b[16:16] ); -wire [0:1] mux_1level_tapbuf_size2_17_inbus; -assign mux_1level_tapbuf_size2_17_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_17_inbus[1] = chanx_1__0__in_37_ ; -wire [17:17] mux_1level_tapbuf_size2_17_configbus0; -wire [17:17] mux_1level_tapbuf_size2_17_configbus1; -wire [17:17] mux_1level_tapbuf_size2_17_sram_blwl_out ; -wire [17:17] mux_1level_tapbuf_size2_17_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_17_configbus0[17:17] = sram_blwl_bl[17:17] ; -assign mux_1level_tapbuf_size2_17_configbus1[17:17] = sram_blwl_wl[17:17] ; -wire [17:17] mux_1level_tapbuf_size2_17_configbus0_b; -assign mux_1level_tapbuf_size2_17_configbus0_b[17:17] = sram_blwl_blb[17:17] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_17_ (mux_1level_tapbuf_size2_17_inbus, chany_0__1__out_34_ , mux_1level_tapbuf_size2_17_sram_blwl_out[17:17] , -mux_1level_tapbuf_size2_17_sram_blwl_outb[17:17] ); -//----- SRAM bits for MUX[17], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_17_ (mux_1level_tapbuf_size2_17_sram_blwl_out[17:17] ,mux_1level_tapbuf_size2_17_sram_blwl_out[17:17] ,mux_1level_tapbuf_size2_17_sram_blwl_outb[17:17] ,mux_1level_tapbuf_size2_17_configbus0[17:17], mux_1level_tapbuf_size2_17_configbus1[17:17] , mux_1level_tapbuf_size2_17_configbus0_b[17:17] ); -wire [0:1] mux_1level_tapbuf_size2_18_inbus; -assign mux_1level_tapbuf_size2_18_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_18_inbus[1] = chanx_1__0__in_39_ ; -wire [18:18] mux_1level_tapbuf_size2_18_configbus0; -wire [18:18] mux_1level_tapbuf_size2_18_configbus1; -wire [18:18] mux_1level_tapbuf_size2_18_sram_blwl_out ; -wire [18:18] mux_1level_tapbuf_size2_18_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_18_configbus0[18:18] = sram_blwl_bl[18:18] ; -assign mux_1level_tapbuf_size2_18_configbus1[18:18] = sram_blwl_wl[18:18] ; -wire [18:18] mux_1level_tapbuf_size2_18_configbus0_b; -assign mux_1level_tapbuf_size2_18_configbus0_b[18:18] = sram_blwl_blb[18:18] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_18_ (mux_1level_tapbuf_size2_18_inbus, chany_0__1__out_36_ , mux_1level_tapbuf_size2_18_sram_blwl_out[18:18] , -mux_1level_tapbuf_size2_18_sram_blwl_outb[18:18] ); -//----- SRAM bits for MUX[18], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_18_ (mux_1level_tapbuf_size2_18_sram_blwl_out[18:18] ,mux_1level_tapbuf_size2_18_sram_blwl_out[18:18] ,mux_1level_tapbuf_size2_18_sram_blwl_outb[18:18] ,mux_1level_tapbuf_size2_18_configbus0[18:18], mux_1level_tapbuf_size2_18_configbus1[18:18] , mux_1level_tapbuf_size2_18_configbus0_b[18:18] ); -wire [0:1] mux_1level_tapbuf_size2_19_inbus; -assign mux_1level_tapbuf_size2_19_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_19_inbus[1] = chanx_1__0__in_41_ ; -wire [19:19] mux_1level_tapbuf_size2_19_configbus0; -wire [19:19] mux_1level_tapbuf_size2_19_configbus1; -wire [19:19] mux_1level_tapbuf_size2_19_sram_blwl_out ; -wire [19:19] mux_1level_tapbuf_size2_19_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_19_configbus0[19:19] = sram_blwl_bl[19:19] ; -assign mux_1level_tapbuf_size2_19_configbus1[19:19] = sram_blwl_wl[19:19] ; -wire [19:19] mux_1level_tapbuf_size2_19_configbus0_b; -assign mux_1level_tapbuf_size2_19_configbus0_b[19:19] = sram_blwl_blb[19:19] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_19_ (mux_1level_tapbuf_size2_19_inbus, chany_0__1__out_38_ , mux_1level_tapbuf_size2_19_sram_blwl_out[19:19] , -mux_1level_tapbuf_size2_19_sram_blwl_outb[19:19] ); -//----- SRAM bits for MUX[19], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_19_ (mux_1level_tapbuf_size2_19_sram_blwl_out[19:19] ,mux_1level_tapbuf_size2_19_sram_blwl_out[19:19] ,mux_1level_tapbuf_size2_19_sram_blwl_outb[19:19] ,mux_1level_tapbuf_size2_19_configbus0[19:19], mux_1level_tapbuf_size2_19_configbus1[19:19] , mux_1level_tapbuf_size2_19_configbus0_b[19:19] ); -wire [0:1] mux_1level_tapbuf_size2_20_inbus; -assign mux_1level_tapbuf_size2_20_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_20_inbus[1] = chanx_1__0__in_43_ ; -wire [20:20] mux_1level_tapbuf_size2_20_configbus0; -wire [20:20] mux_1level_tapbuf_size2_20_configbus1; -wire [20:20] mux_1level_tapbuf_size2_20_sram_blwl_out ; -wire [20:20] mux_1level_tapbuf_size2_20_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_20_configbus0[20:20] = sram_blwl_bl[20:20] ; -assign mux_1level_tapbuf_size2_20_configbus1[20:20] = sram_blwl_wl[20:20] ; -wire [20:20] mux_1level_tapbuf_size2_20_configbus0_b; -assign mux_1level_tapbuf_size2_20_configbus0_b[20:20] = sram_blwl_blb[20:20] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_20_ (mux_1level_tapbuf_size2_20_inbus, chany_0__1__out_40_ , mux_1level_tapbuf_size2_20_sram_blwl_out[20:20] , -mux_1level_tapbuf_size2_20_sram_blwl_outb[20:20] ); -//----- SRAM bits for MUX[20], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_20_ (mux_1level_tapbuf_size2_20_sram_blwl_out[20:20] ,mux_1level_tapbuf_size2_20_sram_blwl_out[20:20] ,mux_1level_tapbuf_size2_20_sram_blwl_outb[20:20] ,mux_1level_tapbuf_size2_20_configbus0[20:20], mux_1level_tapbuf_size2_20_configbus1[20:20] , mux_1level_tapbuf_size2_20_configbus0_b[20:20] ); -wire [0:1] mux_1level_tapbuf_size2_21_inbus; -assign mux_1level_tapbuf_size2_21_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_21_inbus[1] = chanx_1__0__in_45_ ; -wire [21:21] mux_1level_tapbuf_size2_21_configbus0; -wire [21:21] mux_1level_tapbuf_size2_21_configbus1; -wire [21:21] mux_1level_tapbuf_size2_21_sram_blwl_out ; -wire [21:21] mux_1level_tapbuf_size2_21_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_21_configbus0[21:21] = sram_blwl_bl[21:21] ; -assign mux_1level_tapbuf_size2_21_configbus1[21:21] = sram_blwl_wl[21:21] ; -wire [21:21] mux_1level_tapbuf_size2_21_configbus0_b; -assign mux_1level_tapbuf_size2_21_configbus0_b[21:21] = sram_blwl_blb[21:21] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_21_ (mux_1level_tapbuf_size2_21_inbus, chany_0__1__out_42_ , mux_1level_tapbuf_size2_21_sram_blwl_out[21:21] , -mux_1level_tapbuf_size2_21_sram_blwl_outb[21:21] ); -//----- SRAM bits for MUX[21], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_21_ (mux_1level_tapbuf_size2_21_sram_blwl_out[21:21] ,mux_1level_tapbuf_size2_21_sram_blwl_out[21:21] ,mux_1level_tapbuf_size2_21_sram_blwl_outb[21:21] ,mux_1level_tapbuf_size2_21_configbus0[21:21], mux_1level_tapbuf_size2_21_configbus1[21:21] , mux_1level_tapbuf_size2_21_configbus0_b[21:21] ); -wire [0:1] mux_1level_tapbuf_size2_22_inbus; -assign mux_1level_tapbuf_size2_22_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_22_inbus[1] = chanx_1__0__in_47_ ; -wire [22:22] mux_1level_tapbuf_size2_22_configbus0; -wire [22:22] mux_1level_tapbuf_size2_22_configbus1; -wire [22:22] mux_1level_tapbuf_size2_22_sram_blwl_out ; -wire [22:22] mux_1level_tapbuf_size2_22_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_22_configbus0[22:22] = sram_blwl_bl[22:22] ; -assign mux_1level_tapbuf_size2_22_configbus1[22:22] = sram_blwl_wl[22:22] ; -wire [22:22] mux_1level_tapbuf_size2_22_configbus0_b; -assign mux_1level_tapbuf_size2_22_configbus0_b[22:22] = sram_blwl_blb[22:22] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_22_ (mux_1level_tapbuf_size2_22_inbus, chany_0__1__out_44_ , mux_1level_tapbuf_size2_22_sram_blwl_out[22:22] , -mux_1level_tapbuf_size2_22_sram_blwl_outb[22:22] ); -//----- SRAM bits for MUX[22], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_22_ (mux_1level_tapbuf_size2_22_sram_blwl_out[22:22] ,mux_1level_tapbuf_size2_22_sram_blwl_out[22:22] ,mux_1level_tapbuf_size2_22_sram_blwl_outb[22:22] ,mux_1level_tapbuf_size2_22_configbus0[22:22], mux_1level_tapbuf_size2_22_configbus1[22:22] , mux_1level_tapbuf_size2_22_configbus0_b[22:22] ); -wire [0:1] mux_1level_tapbuf_size2_23_inbus; -assign mux_1level_tapbuf_size2_23_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_23_inbus[1] = chanx_1__0__in_49_ ; -wire [23:23] mux_1level_tapbuf_size2_23_configbus0; -wire [23:23] mux_1level_tapbuf_size2_23_configbus1; -wire [23:23] mux_1level_tapbuf_size2_23_sram_blwl_out ; -wire [23:23] mux_1level_tapbuf_size2_23_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_23_configbus0[23:23] = sram_blwl_bl[23:23] ; -assign mux_1level_tapbuf_size2_23_configbus1[23:23] = sram_blwl_wl[23:23] ; -wire [23:23] mux_1level_tapbuf_size2_23_configbus0_b; -assign mux_1level_tapbuf_size2_23_configbus0_b[23:23] = sram_blwl_blb[23:23] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_23_ (mux_1level_tapbuf_size2_23_inbus, chany_0__1__out_46_ , mux_1level_tapbuf_size2_23_sram_blwl_out[23:23] , -mux_1level_tapbuf_size2_23_sram_blwl_outb[23:23] ); -//----- SRAM bits for MUX[23], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_23_ (mux_1level_tapbuf_size2_23_sram_blwl_out[23:23] ,mux_1level_tapbuf_size2_23_sram_blwl_out[23:23] ,mux_1level_tapbuf_size2_23_sram_blwl_outb[23:23] ,mux_1level_tapbuf_size2_23_configbus0[23:23], mux_1level_tapbuf_size2_23_configbus1[23:23] , mux_1level_tapbuf_size2_23_configbus0_b[23:23] ); -wire [0:1] mux_1level_tapbuf_size2_24_inbus; -assign mux_1level_tapbuf_size2_24_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_24_inbus[1] = chanx_1__0__in_51_ ; -wire [24:24] mux_1level_tapbuf_size2_24_configbus0; -wire [24:24] mux_1level_tapbuf_size2_24_configbus1; -wire [24:24] mux_1level_tapbuf_size2_24_sram_blwl_out ; -wire [24:24] mux_1level_tapbuf_size2_24_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_24_configbus0[24:24] = sram_blwl_bl[24:24] ; -assign mux_1level_tapbuf_size2_24_configbus1[24:24] = sram_blwl_wl[24:24] ; -wire [24:24] mux_1level_tapbuf_size2_24_configbus0_b; -assign mux_1level_tapbuf_size2_24_configbus0_b[24:24] = sram_blwl_blb[24:24] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_24_ (mux_1level_tapbuf_size2_24_inbus, chany_0__1__out_48_ , mux_1level_tapbuf_size2_24_sram_blwl_out[24:24] , -mux_1level_tapbuf_size2_24_sram_blwl_outb[24:24] ); -//----- SRAM bits for MUX[24], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_24_ (mux_1level_tapbuf_size2_24_sram_blwl_out[24:24] ,mux_1level_tapbuf_size2_24_sram_blwl_out[24:24] ,mux_1level_tapbuf_size2_24_sram_blwl_outb[24:24] ,mux_1level_tapbuf_size2_24_configbus0[24:24], mux_1level_tapbuf_size2_24_configbus1[24:24] , mux_1level_tapbuf_size2_24_configbus0_b[24:24] ); -wire [0:1] mux_1level_tapbuf_size2_25_inbus; -assign mux_1level_tapbuf_size2_25_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_25_inbus[1] = chanx_1__0__in_53_ ; -wire [25:25] mux_1level_tapbuf_size2_25_configbus0; -wire [25:25] mux_1level_tapbuf_size2_25_configbus1; -wire [25:25] mux_1level_tapbuf_size2_25_sram_blwl_out ; -wire [25:25] mux_1level_tapbuf_size2_25_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_25_configbus0[25:25] = sram_blwl_bl[25:25] ; -assign mux_1level_tapbuf_size2_25_configbus1[25:25] = sram_blwl_wl[25:25] ; -wire [25:25] mux_1level_tapbuf_size2_25_configbus0_b; -assign mux_1level_tapbuf_size2_25_configbus0_b[25:25] = sram_blwl_blb[25:25] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_25_ (mux_1level_tapbuf_size2_25_inbus, chany_0__1__out_50_ , mux_1level_tapbuf_size2_25_sram_blwl_out[25:25] , -mux_1level_tapbuf_size2_25_sram_blwl_outb[25:25] ); -//----- SRAM bits for MUX[25], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_25_ (mux_1level_tapbuf_size2_25_sram_blwl_out[25:25] ,mux_1level_tapbuf_size2_25_sram_blwl_out[25:25] ,mux_1level_tapbuf_size2_25_sram_blwl_outb[25:25] ,mux_1level_tapbuf_size2_25_configbus0[25:25], mux_1level_tapbuf_size2_25_configbus1[25:25] , mux_1level_tapbuf_size2_25_configbus0_b[25:25] ); -wire [0:1] mux_1level_tapbuf_size2_26_inbus; -assign mux_1level_tapbuf_size2_26_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_26_inbus[1] = chanx_1__0__in_55_ ; -wire [26:26] mux_1level_tapbuf_size2_26_configbus0; -wire [26:26] mux_1level_tapbuf_size2_26_configbus1; -wire [26:26] mux_1level_tapbuf_size2_26_sram_blwl_out ; -wire [26:26] mux_1level_tapbuf_size2_26_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_26_configbus0[26:26] = sram_blwl_bl[26:26] ; -assign mux_1level_tapbuf_size2_26_configbus1[26:26] = sram_blwl_wl[26:26] ; -wire [26:26] mux_1level_tapbuf_size2_26_configbus0_b; -assign mux_1level_tapbuf_size2_26_configbus0_b[26:26] = sram_blwl_blb[26:26] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_26_ (mux_1level_tapbuf_size2_26_inbus, chany_0__1__out_52_ , mux_1level_tapbuf_size2_26_sram_blwl_out[26:26] , -mux_1level_tapbuf_size2_26_sram_blwl_outb[26:26] ); -//----- SRAM bits for MUX[26], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_26_ (mux_1level_tapbuf_size2_26_sram_blwl_out[26:26] ,mux_1level_tapbuf_size2_26_sram_blwl_out[26:26] ,mux_1level_tapbuf_size2_26_sram_blwl_outb[26:26] ,mux_1level_tapbuf_size2_26_configbus0[26:26], mux_1level_tapbuf_size2_26_configbus1[26:26] , mux_1level_tapbuf_size2_26_configbus0_b[26:26] ); -wire [0:1] mux_1level_tapbuf_size2_27_inbus; -assign mux_1level_tapbuf_size2_27_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_27_inbus[1] = chanx_1__0__in_57_ ; -wire [27:27] mux_1level_tapbuf_size2_27_configbus0; -wire [27:27] mux_1level_tapbuf_size2_27_configbus1; -wire [27:27] mux_1level_tapbuf_size2_27_sram_blwl_out ; -wire [27:27] mux_1level_tapbuf_size2_27_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_27_configbus0[27:27] = sram_blwl_bl[27:27] ; -assign mux_1level_tapbuf_size2_27_configbus1[27:27] = sram_blwl_wl[27:27] ; -wire [27:27] mux_1level_tapbuf_size2_27_configbus0_b; -assign mux_1level_tapbuf_size2_27_configbus0_b[27:27] = sram_blwl_blb[27:27] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_27_ (mux_1level_tapbuf_size2_27_inbus, chany_0__1__out_54_ , mux_1level_tapbuf_size2_27_sram_blwl_out[27:27] , -mux_1level_tapbuf_size2_27_sram_blwl_outb[27:27] ); -//----- SRAM bits for MUX[27], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_27_ (mux_1level_tapbuf_size2_27_sram_blwl_out[27:27] ,mux_1level_tapbuf_size2_27_sram_blwl_out[27:27] ,mux_1level_tapbuf_size2_27_sram_blwl_outb[27:27] ,mux_1level_tapbuf_size2_27_configbus0[27:27], mux_1level_tapbuf_size2_27_configbus1[27:27] , mux_1level_tapbuf_size2_27_configbus0_b[27:27] ); -wire [0:1] mux_1level_tapbuf_size2_28_inbus; -assign mux_1level_tapbuf_size2_28_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_28_inbus[1] = chanx_1__0__in_59_ ; -wire [28:28] mux_1level_tapbuf_size2_28_configbus0; -wire [28:28] mux_1level_tapbuf_size2_28_configbus1; -wire [28:28] mux_1level_tapbuf_size2_28_sram_blwl_out ; -wire [28:28] mux_1level_tapbuf_size2_28_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_28_configbus0[28:28] = sram_blwl_bl[28:28] ; -assign mux_1level_tapbuf_size2_28_configbus1[28:28] = sram_blwl_wl[28:28] ; -wire [28:28] mux_1level_tapbuf_size2_28_configbus0_b; -assign mux_1level_tapbuf_size2_28_configbus0_b[28:28] = sram_blwl_blb[28:28] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_28_ (mux_1level_tapbuf_size2_28_inbus, chany_0__1__out_56_ , mux_1level_tapbuf_size2_28_sram_blwl_out[28:28] , -mux_1level_tapbuf_size2_28_sram_blwl_outb[28:28] ); -//----- SRAM bits for MUX[28], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_28_ (mux_1level_tapbuf_size2_28_sram_blwl_out[28:28] ,mux_1level_tapbuf_size2_28_sram_blwl_out[28:28] ,mux_1level_tapbuf_size2_28_sram_blwl_outb[28:28] ,mux_1level_tapbuf_size2_28_configbus0[28:28], mux_1level_tapbuf_size2_28_configbus1[28:28] , mux_1level_tapbuf_size2_28_configbus0_b[28:28] ); -wire [0:1] mux_1level_tapbuf_size2_29_inbus; -assign mux_1level_tapbuf_size2_29_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_29_inbus[1] = chanx_1__0__in_61_ ; -wire [29:29] mux_1level_tapbuf_size2_29_configbus0; -wire [29:29] mux_1level_tapbuf_size2_29_configbus1; -wire [29:29] mux_1level_tapbuf_size2_29_sram_blwl_out ; -wire [29:29] mux_1level_tapbuf_size2_29_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_29_configbus0[29:29] = sram_blwl_bl[29:29] ; -assign mux_1level_tapbuf_size2_29_configbus1[29:29] = sram_blwl_wl[29:29] ; -wire [29:29] mux_1level_tapbuf_size2_29_configbus0_b; -assign mux_1level_tapbuf_size2_29_configbus0_b[29:29] = sram_blwl_blb[29:29] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_29_ (mux_1level_tapbuf_size2_29_inbus, chany_0__1__out_58_ , mux_1level_tapbuf_size2_29_sram_blwl_out[29:29] , -mux_1level_tapbuf_size2_29_sram_blwl_outb[29:29] ); -//----- SRAM bits for MUX[29], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_29_ (mux_1level_tapbuf_size2_29_sram_blwl_out[29:29] ,mux_1level_tapbuf_size2_29_sram_blwl_out[29:29] ,mux_1level_tapbuf_size2_29_sram_blwl_outb[29:29] ,mux_1level_tapbuf_size2_29_configbus0[29:29], mux_1level_tapbuf_size2_29_configbus1[29:29] , mux_1level_tapbuf_size2_29_configbus0_b[29:29] ); -wire [0:1] mux_1level_tapbuf_size2_30_inbus; -assign mux_1level_tapbuf_size2_30_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_30_inbus[1] = chanx_1__0__in_63_ ; -wire [30:30] mux_1level_tapbuf_size2_30_configbus0; -wire [30:30] mux_1level_tapbuf_size2_30_configbus1; -wire [30:30] mux_1level_tapbuf_size2_30_sram_blwl_out ; -wire [30:30] mux_1level_tapbuf_size2_30_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_30_configbus0[30:30] = sram_blwl_bl[30:30] ; -assign mux_1level_tapbuf_size2_30_configbus1[30:30] = sram_blwl_wl[30:30] ; -wire [30:30] mux_1level_tapbuf_size2_30_configbus0_b; -assign mux_1level_tapbuf_size2_30_configbus0_b[30:30] = sram_blwl_blb[30:30] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_30_ (mux_1level_tapbuf_size2_30_inbus, chany_0__1__out_60_ , mux_1level_tapbuf_size2_30_sram_blwl_out[30:30] , -mux_1level_tapbuf_size2_30_sram_blwl_outb[30:30] ); -//----- SRAM bits for MUX[30], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_30_ (mux_1level_tapbuf_size2_30_sram_blwl_out[30:30] ,mux_1level_tapbuf_size2_30_sram_blwl_out[30:30] ,mux_1level_tapbuf_size2_30_sram_blwl_outb[30:30] ,mux_1level_tapbuf_size2_30_configbus0[30:30], mux_1level_tapbuf_size2_30_configbus1[30:30] , mux_1level_tapbuf_size2_30_configbus0_b[30:30] ); -wire [0:1] mux_1level_tapbuf_size2_31_inbus; -assign mux_1level_tapbuf_size2_31_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_31_inbus[1] = chanx_1__0__in_65_ ; -wire [31:31] mux_1level_tapbuf_size2_31_configbus0; -wire [31:31] mux_1level_tapbuf_size2_31_configbus1; -wire [31:31] mux_1level_tapbuf_size2_31_sram_blwl_out ; -wire [31:31] mux_1level_tapbuf_size2_31_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_31_configbus0[31:31] = sram_blwl_bl[31:31] ; -assign mux_1level_tapbuf_size2_31_configbus1[31:31] = sram_blwl_wl[31:31] ; -wire [31:31] mux_1level_tapbuf_size2_31_configbus0_b; -assign mux_1level_tapbuf_size2_31_configbus0_b[31:31] = sram_blwl_blb[31:31] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_31_ (mux_1level_tapbuf_size2_31_inbus, chany_0__1__out_62_ , mux_1level_tapbuf_size2_31_sram_blwl_out[31:31] , -mux_1level_tapbuf_size2_31_sram_blwl_outb[31:31] ); -//----- SRAM bits for MUX[31], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_31_ (mux_1level_tapbuf_size2_31_sram_blwl_out[31:31] ,mux_1level_tapbuf_size2_31_sram_blwl_out[31:31] ,mux_1level_tapbuf_size2_31_sram_blwl_outb[31:31] ,mux_1level_tapbuf_size2_31_configbus0[31:31], mux_1level_tapbuf_size2_31_configbus1[31:31] , mux_1level_tapbuf_size2_31_configbus0_b[31:31] ); -wire [0:1] mux_1level_tapbuf_size2_32_inbus; -assign mux_1level_tapbuf_size2_32_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_32_inbus[1] = chanx_1__0__in_67_ ; -wire [32:32] mux_1level_tapbuf_size2_32_configbus0; -wire [32:32] mux_1level_tapbuf_size2_32_configbus1; -wire [32:32] mux_1level_tapbuf_size2_32_sram_blwl_out ; -wire [32:32] mux_1level_tapbuf_size2_32_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_32_configbus0[32:32] = sram_blwl_bl[32:32] ; -assign mux_1level_tapbuf_size2_32_configbus1[32:32] = sram_blwl_wl[32:32] ; -wire [32:32] mux_1level_tapbuf_size2_32_configbus0_b; -assign mux_1level_tapbuf_size2_32_configbus0_b[32:32] = sram_blwl_blb[32:32] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_32_ (mux_1level_tapbuf_size2_32_inbus, chany_0__1__out_64_ , mux_1level_tapbuf_size2_32_sram_blwl_out[32:32] , -mux_1level_tapbuf_size2_32_sram_blwl_outb[32:32] ); -//----- SRAM bits for MUX[32], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_32_ (mux_1level_tapbuf_size2_32_sram_blwl_out[32:32] ,mux_1level_tapbuf_size2_32_sram_blwl_out[32:32] ,mux_1level_tapbuf_size2_32_sram_blwl_outb[32:32] ,mux_1level_tapbuf_size2_32_configbus0[32:32], mux_1level_tapbuf_size2_32_configbus1[32:32] , mux_1level_tapbuf_size2_32_configbus0_b[32:32] ); -wire [0:1] mux_1level_tapbuf_size2_33_inbus; -assign mux_1level_tapbuf_size2_33_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_33_inbus[1] = chanx_1__0__in_69_ ; -wire [33:33] mux_1level_tapbuf_size2_33_configbus0; -wire [33:33] mux_1level_tapbuf_size2_33_configbus1; -wire [33:33] mux_1level_tapbuf_size2_33_sram_blwl_out ; -wire [33:33] mux_1level_tapbuf_size2_33_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_33_configbus0[33:33] = sram_blwl_bl[33:33] ; -assign mux_1level_tapbuf_size2_33_configbus1[33:33] = sram_blwl_wl[33:33] ; -wire [33:33] mux_1level_tapbuf_size2_33_configbus0_b; -assign mux_1level_tapbuf_size2_33_configbus0_b[33:33] = sram_blwl_blb[33:33] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_33_ (mux_1level_tapbuf_size2_33_inbus, chany_0__1__out_66_ , mux_1level_tapbuf_size2_33_sram_blwl_out[33:33] , -mux_1level_tapbuf_size2_33_sram_blwl_outb[33:33] ); -//----- SRAM bits for MUX[33], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_33_ (mux_1level_tapbuf_size2_33_sram_blwl_out[33:33] ,mux_1level_tapbuf_size2_33_sram_blwl_out[33:33] ,mux_1level_tapbuf_size2_33_sram_blwl_outb[33:33] ,mux_1level_tapbuf_size2_33_configbus0[33:33], mux_1level_tapbuf_size2_33_configbus1[33:33] , mux_1level_tapbuf_size2_33_configbus0_b[33:33] ); -wire [0:1] mux_1level_tapbuf_size2_34_inbus; -assign mux_1level_tapbuf_size2_34_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_34_inbus[1] = chanx_1__0__in_71_ ; -wire [34:34] mux_1level_tapbuf_size2_34_configbus0; -wire [34:34] mux_1level_tapbuf_size2_34_configbus1; -wire [34:34] mux_1level_tapbuf_size2_34_sram_blwl_out ; -wire [34:34] mux_1level_tapbuf_size2_34_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_34_configbus0[34:34] = sram_blwl_bl[34:34] ; -assign mux_1level_tapbuf_size2_34_configbus1[34:34] = sram_blwl_wl[34:34] ; -wire [34:34] mux_1level_tapbuf_size2_34_configbus0_b; -assign mux_1level_tapbuf_size2_34_configbus0_b[34:34] = sram_blwl_blb[34:34] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_34_ (mux_1level_tapbuf_size2_34_inbus, chany_0__1__out_68_ , mux_1level_tapbuf_size2_34_sram_blwl_out[34:34] , -mux_1level_tapbuf_size2_34_sram_blwl_outb[34:34] ); -//----- SRAM bits for MUX[34], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_34_ (mux_1level_tapbuf_size2_34_sram_blwl_out[34:34] ,mux_1level_tapbuf_size2_34_sram_blwl_out[34:34] ,mux_1level_tapbuf_size2_34_sram_blwl_outb[34:34] ,mux_1level_tapbuf_size2_34_configbus0[34:34], mux_1level_tapbuf_size2_34_configbus1[34:34] , mux_1level_tapbuf_size2_34_configbus0_b[34:34] ); -wire [0:1] mux_1level_tapbuf_size2_35_inbus; -assign mux_1level_tapbuf_size2_35_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_35_inbus[1] = chanx_1__0__in_73_ ; -wire [35:35] mux_1level_tapbuf_size2_35_configbus0; -wire [35:35] mux_1level_tapbuf_size2_35_configbus1; -wire [35:35] mux_1level_tapbuf_size2_35_sram_blwl_out ; -wire [35:35] mux_1level_tapbuf_size2_35_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_35_configbus0[35:35] = sram_blwl_bl[35:35] ; -assign mux_1level_tapbuf_size2_35_configbus1[35:35] = sram_blwl_wl[35:35] ; -wire [35:35] mux_1level_tapbuf_size2_35_configbus0_b; -assign mux_1level_tapbuf_size2_35_configbus0_b[35:35] = sram_blwl_blb[35:35] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_35_ (mux_1level_tapbuf_size2_35_inbus, chany_0__1__out_70_ , mux_1level_tapbuf_size2_35_sram_blwl_out[35:35] , -mux_1level_tapbuf_size2_35_sram_blwl_outb[35:35] ); -//----- SRAM bits for MUX[35], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_35_ (mux_1level_tapbuf_size2_35_sram_blwl_out[35:35] ,mux_1level_tapbuf_size2_35_sram_blwl_out[35:35] ,mux_1level_tapbuf_size2_35_sram_blwl_outb[35:35] ,mux_1level_tapbuf_size2_35_configbus0[35:35], mux_1level_tapbuf_size2_35_configbus1[35:35] , mux_1level_tapbuf_size2_35_configbus0_b[35:35] ); -wire [0:1] mux_1level_tapbuf_size2_36_inbus; -assign mux_1level_tapbuf_size2_36_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_36_inbus[1] = chanx_1__0__in_75_ ; -wire [36:36] mux_1level_tapbuf_size2_36_configbus0; -wire [36:36] mux_1level_tapbuf_size2_36_configbus1; -wire [36:36] mux_1level_tapbuf_size2_36_sram_blwl_out ; -wire [36:36] mux_1level_tapbuf_size2_36_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_36_configbus0[36:36] = sram_blwl_bl[36:36] ; -assign mux_1level_tapbuf_size2_36_configbus1[36:36] = sram_blwl_wl[36:36] ; -wire [36:36] mux_1level_tapbuf_size2_36_configbus0_b; -assign mux_1level_tapbuf_size2_36_configbus0_b[36:36] = sram_blwl_blb[36:36] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_36_ (mux_1level_tapbuf_size2_36_inbus, chany_0__1__out_72_ , mux_1level_tapbuf_size2_36_sram_blwl_out[36:36] , -mux_1level_tapbuf_size2_36_sram_blwl_outb[36:36] ); -//----- SRAM bits for MUX[36], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_36_ (mux_1level_tapbuf_size2_36_sram_blwl_out[36:36] ,mux_1level_tapbuf_size2_36_sram_blwl_out[36:36] ,mux_1level_tapbuf_size2_36_sram_blwl_outb[36:36] ,mux_1level_tapbuf_size2_36_configbus0[36:36], mux_1level_tapbuf_size2_36_configbus1[36:36] , mux_1level_tapbuf_size2_36_configbus0_b[36:36] ); -wire [0:1] mux_1level_tapbuf_size2_37_inbus; -assign mux_1level_tapbuf_size2_37_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_37_inbus[1] = chanx_1__0__in_77_ ; -wire [37:37] mux_1level_tapbuf_size2_37_configbus0; -wire [37:37] mux_1level_tapbuf_size2_37_configbus1; -wire [37:37] mux_1level_tapbuf_size2_37_sram_blwl_out ; -wire [37:37] mux_1level_tapbuf_size2_37_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_37_configbus0[37:37] = sram_blwl_bl[37:37] ; -assign mux_1level_tapbuf_size2_37_configbus1[37:37] = sram_blwl_wl[37:37] ; -wire [37:37] mux_1level_tapbuf_size2_37_configbus0_b; -assign mux_1level_tapbuf_size2_37_configbus0_b[37:37] = sram_blwl_blb[37:37] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_37_ (mux_1level_tapbuf_size2_37_inbus, chany_0__1__out_74_ , mux_1level_tapbuf_size2_37_sram_blwl_out[37:37] , -mux_1level_tapbuf_size2_37_sram_blwl_outb[37:37] ); -//----- SRAM bits for MUX[37], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_37_ (mux_1level_tapbuf_size2_37_sram_blwl_out[37:37] ,mux_1level_tapbuf_size2_37_sram_blwl_out[37:37] ,mux_1level_tapbuf_size2_37_sram_blwl_outb[37:37] ,mux_1level_tapbuf_size2_37_configbus0[37:37], mux_1level_tapbuf_size2_37_configbus1[37:37] , mux_1level_tapbuf_size2_37_configbus0_b[37:37] ); -wire [0:1] mux_1level_tapbuf_size2_38_inbus; -assign mux_1level_tapbuf_size2_38_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_38_inbus[1] = chanx_1__0__in_79_ ; -wire [38:38] mux_1level_tapbuf_size2_38_configbus0; -wire [38:38] mux_1level_tapbuf_size2_38_configbus1; -wire [38:38] mux_1level_tapbuf_size2_38_sram_blwl_out ; -wire [38:38] mux_1level_tapbuf_size2_38_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_38_configbus0[38:38] = sram_blwl_bl[38:38] ; -assign mux_1level_tapbuf_size2_38_configbus1[38:38] = sram_blwl_wl[38:38] ; -wire [38:38] mux_1level_tapbuf_size2_38_configbus0_b; -assign mux_1level_tapbuf_size2_38_configbus0_b[38:38] = sram_blwl_blb[38:38] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_38_ (mux_1level_tapbuf_size2_38_inbus, chany_0__1__out_76_ , mux_1level_tapbuf_size2_38_sram_blwl_out[38:38] , -mux_1level_tapbuf_size2_38_sram_blwl_outb[38:38] ); -//----- SRAM bits for MUX[38], level=1, select_path_id=1. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----0----- -sram6T_blwl sram_blwl_38_ (mux_1level_tapbuf_size2_38_sram_blwl_out[38:38] ,mux_1level_tapbuf_size2_38_sram_blwl_out[38:38] ,mux_1level_tapbuf_size2_38_sram_blwl_outb[38:38] ,mux_1level_tapbuf_size2_38_configbus0[38:38], mux_1level_tapbuf_size2_38_configbus1[38:38] , mux_1level_tapbuf_size2_38_configbus0_b[38:38] ); -wire [0:1] mux_1level_tapbuf_size2_39_inbus; -assign mux_1level_tapbuf_size2_39_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_39_inbus[1] = chanx_1__0__in_81_ ; -wire [39:39] mux_1level_tapbuf_size2_39_configbus0; -wire [39:39] mux_1level_tapbuf_size2_39_configbus1; -wire [39:39] mux_1level_tapbuf_size2_39_sram_blwl_out ; -wire [39:39] mux_1level_tapbuf_size2_39_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_39_configbus0[39:39] = sram_blwl_bl[39:39] ; -assign mux_1level_tapbuf_size2_39_configbus1[39:39] = sram_blwl_wl[39:39] ; -wire [39:39] mux_1level_tapbuf_size2_39_configbus0_b; -assign mux_1level_tapbuf_size2_39_configbus0_b[39:39] = sram_blwl_blb[39:39] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_39_ (mux_1level_tapbuf_size2_39_inbus, chany_0__1__out_78_ , mux_1level_tapbuf_size2_39_sram_blwl_out[39:39] , -mux_1level_tapbuf_size2_39_sram_blwl_outb[39:39] ); -//----- SRAM bits for MUX[39], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_39_ (mux_1level_tapbuf_size2_39_sram_blwl_out[39:39] ,mux_1level_tapbuf_size2_39_sram_blwl_out[39:39] ,mux_1level_tapbuf_size2_39_sram_blwl_outb[39:39] ,mux_1level_tapbuf_size2_39_configbus0[39:39], mux_1level_tapbuf_size2_39_configbus1[39:39] , mux_1level_tapbuf_size2_39_configbus0_b[39:39] ); -wire [0:1] mux_1level_tapbuf_size2_40_inbus; -assign mux_1level_tapbuf_size2_40_inbus[0] = grid_1__1__pin_0__3__43_; -assign mux_1level_tapbuf_size2_40_inbus[1] = chanx_1__0__in_83_ ; -wire [40:40] mux_1level_tapbuf_size2_40_configbus0; -wire [40:40] mux_1level_tapbuf_size2_40_configbus1; -wire [40:40] mux_1level_tapbuf_size2_40_sram_blwl_out ; -wire [40:40] mux_1level_tapbuf_size2_40_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_40_configbus0[40:40] = sram_blwl_bl[40:40] ; -assign mux_1level_tapbuf_size2_40_configbus1[40:40] = sram_blwl_wl[40:40] ; -wire [40:40] mux_1level_tapbuf_size2_40_configbus0_b; -assign mux_1level_tapbuf_size2_40_configbus0_b[40:40] = sram_blwl_blb[40:40] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_40_ (mux_1level_tapbuf_size2_40_inbus, chany_0__1__out_80_ , mux_1level_tapbuf_size2_40_sram_blwl_out[40:40] , -mux_1level_tapbuf_size2_40_sram_blwl_outb[40:40] ); -//----- SRAM bits for MUX[40], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_40_ (mux_1level_tapbuf_size2_40_sram_blwl_out[40:40] ,mux_1level_tapbuf_size2_40_sram_blwl_out[40:40] ,mux_1level_tapbuf_size2_40_sram_blwl_outb[40:40] ,mux_1level_tapbuf_size2_40_configbus0[40:40], mux_1level_tapbuf_size2_40_configbus1[40:40] , mux_1level_tapbuf_size2_40_configbus0_b[40:40] ); -wire [0:1] mux_1level_tapbuf_size2_41_inbus; -assign mux_1level_tapbuf_size2_41_inbus[0] = grid_1__1__pin_0__3__43_; -assign mux_1level_tapbuf_size2_41_inbus[1] = chanx_1__0__in_85_ ; -wire [41:41] mux_1level_tapbuf_size2_41_configbus0; -wire [41:41] mux_1level_tapbuf_size2_41_configbus1; -wire [41:41] mux_1level_tapbuf_size2_41_sram_blwl_out ; -wire [41:41] mux_1level_tapbuf_size2_41_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_41_configbus0[41:41] = sram_blwl_bl[41:41] ; -assign mux_1level_tapbuf_size2_41_configbus1[41:41] = sram_blwl_wl[41:41] ; -wire [41:41] mux_1level_tapbuf_size2_41_configbus0_b; -assign mux_1level_tapbuf_size2_41_configbus0_b[41:41] = sram_blwl_blb[41:41] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_41_ (mux_1level_tapbuf_size2_41_inbus, chany_0__1__out_82_ , mux_1level_tapbuf_size2_41_sram_blwl_out[41:41] , -mux_1level_tapbuf_size2_41_sram_blwl_outb[41:41] ); -//----- SRAM bits for MUX[41], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_41_ (mux_1level_tapbuf_size2_41_sram_blwl_out[41:41] ,mux_1level_tapbuf_size2_41_sram_blwl_out[41:41] ,mux_1level_tapbuf_size2_41_sram_blwl_outb[41:41] ,mux_1level_tapbuf_size2_41_configbus0[41:41], mux_1level_tapbuf_size2_41_configbus1[41:41] , mux_1level_tapbuf_size2_41_configbus0_b[41:41] ); -wire [0:1] mux_1level_tapbuf_size2_42_inbus; -assign mux_1level_tapbuf_size2_42_inbus[0] = grid_1__1__pin_0__3__43_; -assign mux_1level_tapbuf_size2_42_inbus[1] = chanx_1__0__in_87_ ; -wire [42:42] mux_1level_tapbuf_size2_42_configbus0; -wire [42:42] mux_1level_tapbuf_size2_42_configbus1; -wire [42:42] mux_1level_tapbuf_size2_42_sram_blwl_out ; -wire [42:42] mux_1level_tapbuf_size2_42_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_42_configbus0[42:42] = sram_blwl_bl[42:42] ; -assign mux_1level_tapbuf_size2_42_configbus1[42:42] = sram_blwl_wl[42:42] ; -wire [42:42] mux_1level_tapbuf_size2_42_configbus0_b; -assign mux_1level_tapbuf_size2_42_configbus0_b[42:42] = sram_blwl_blb[42:42] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_42_ (mux_1level_tapbuf_size2_42_inbus, chany_0__1__out_84_ , mux_1level_tapbuf_size2_42_sram_blwl_out[42:42] , -mux_1level_tapbuf_size2_42_sram_blwl_outb[42:42] ); -//----- SRAM bits for MUX[42], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_42_ (mux_1level_tapbuf_size2_42_sram_blwl_out[42:42] ,mux_1level_tapbuf_size2_42_sram_blwl_out[42:42] ,mux_1level_tapbuf_size2_42_sram_blwl_outb[42:42] ,mux_1level_tapbuf_size2_42_configbus0[42:42], mux_1level_tapbuf_size2_42_configbus1[42:42] , mux_1level_tapbuf_size2_42_configbus0_b[42:42] ); -wire [0:1] mux_1level_tapbuf_size2_43_inbus; -assign mux_1level_tapbuf_size2_43_inbus[0] = grid_1__1__pin_0__3__43_; -assign mux_1level_tapbuf_size2_43_inbus[1] = chanx_1__0__in_89_ ; -wire [43:43] mux_1level_tapbuf_size2_43_configbus0; -wire [43:43] mux_1level_tapbuf_size2_43_configbus1; -wire [43:43] mux_1level_tapbuf_size2_43_sram_blwl_out ; -wire [43:43] mux_1level_tapbuf_size2_43_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_43_configbus0[43:43] = sram_blwl_bl[43:43] ; -assign mux_1level_tapbuf_size2_43_configbus1[43:43] = sram_blwl_wl[43:43] ; -wire [43:43] mux_1level_tapbuf_size2_43_configbus0_b; -assign mux_1level_tapbuf_size2_43_configbus0_b[43:43] = sram_blwl_blb[43:43] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_43_ (mux_1level_tapbuf_size2_43_inbus, chany_0__1__out_86_ , mux_1level_tapbuf_size2_43_sram_blwl_out[43:43] , -mux_1level_tapbuf_size2_43_sram_blwl_outb[43:43] ); -//----- SRAM bits for MUX[43], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_43_ (mux_1level_tapbuf_size2_43_sram_blwl_out[43:43] ,mux_1level_tapbuf_size2_43_sram_blwl_out[43:43] ,mux_1level_tapbuf_size2_43_sram_blwl_outb[43:43] ,mux_1level_tapbuf_size2_43_configbus0[43:43], mux_1level_tapbuf_size2_43_configbus1[43:43] , mux_1level_tapbuf_size2_43_configbus0_b[43:43] ); -wire [0:1] mux_1level_tapbuf_size2_44_inbus; -assign mux_1level_tapbuf_size2_44_inbus[0] = grid_1__1__pin_0__3__43_; -assign mux_1level_tapbuf_size2_44_inbus[1] = chanx_1__0__in_91_ ; -wire [44:44] mux_1level_tapbuf_size2_44_configbus0; -wire [44:44] mux_1level_tapbuf_size2_44_configbus1; -wire [44:44] mux_1level_tapbuf_size2_44_sram_blwl_out ; -wire [44:44] mux_1level_tapbuf_size2_44_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_44_configbus0[44:44] = sram_blwl_bl[44:44] ; -assign mux_1level_tapbuf_size2_44_configbus1[44:44] = sram_blwl_wl[44:44] ; -wire [44:44] mux_1level_tapbuf_size2_44_configbus0_b; -assign mux_1level_tapbuf_size2_44_configbus0_b[44:44] = sram_blwl_blb[44:44] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_44_ (mux_1level_tapbuf_size2_44_inbus, chany_0__1__out_88_ , mux_1level_tapbuf_size2_44_sram_blwl_out[44:44] , -mux_1level_tapbuf_size2_44_sram_blwl_outb[44:44] ); -//----- SRAM bits for MUX[44], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_44_ (mux_1level_tapbuf_size2_44_sram_blwl_out[44:44] ,mux_1level_tapbuf_size2_44_sram_blwl_out[44:44] ,mux_1level_tapbuf_size2_44_sram_blwl_outb[44:44] ,mux_1level_tapbuf_size2_44_configbus0[44:44], mux_1level_tapbuf_size2_44_configbus1[44:44] , mux_1level_tapbuf_size2_44_configbus0_b[44:44] ); -wire [0:1] mux_1level_tapbuf_size2_45_inbus; -assign mux_1level_tapbuf_size2_45_inbus[0] = grid_1__1__pin_0__3__47_; -assign mux_1level_tapbuf_size2_45_inbus[1] = chanx_1__0__in_93_ ; -wire [45:45] mux_1level_tapbuf_size2_45_configbus0; -wire [45:45] mux_1level_tapbuf_size2_45_configbus1; -wire [45:45] mux_1level_tapbuf_size2_45_sram_blwl_out ; -wire [45:45] mux_1level_tapbuf_size2_45_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_45_configbus0[45:45] = sram_blwl_bl[45:45] ; -assign mux_1level_tapbuf_size2_45_configbus1[45:45] = sram_blwl_wl[45:45] ; -wire [45:45] mux_1level_tapbuf_size2_45_configbus0_b; -assign mux_1level_tapbuf_size2_45_configbus0_b[45:45] = sram_blwl_blb[45:45] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_45_ (mux_1level_tapbuf_size2_45_inbus, chany_0__1__out_90_ , mux_1level_tapbuf_size2_45_sram_blwl_out[45:45] , -mux_1level_tapbuf_size2_45_sram_blwl_outb[45:45] ); -//----- SRAM bits for MUX[45], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_45_ (mux_1level_tapbuf_size2_45_sram_blwl_out[45:45] ,mux_1level_tapbuf_size2_45_sram_blwl_out[45:45] ,mux_1level_tapbuf_size2_45_sram_blwl_outb[45:45] ,mux_1level_tapbuf_size2_45_configbus0[45:45], mux_1level_tapbuf_size2_45_configbus1[45:45] , mux_1level_tapbuf_size2_45_configbus0_b[45:45] ); -wire [0:1] mux_1level_tapbuf_size2_46_inbus; -assign mux_1level_tapbuf_size2_46_inbus[0] = grid_1__1__pin_0__3__47_; -assign mux_1level_tapbuf_size2_46_inbus[1] = chanx_1__0__in_95_ ; -wire [46:46] mux_1level_tapbuf_size2_46_configbus0; -wire [46:46] mux_1level_tapbuf_size2_46_configbus1; -wire [46:46] mux_1level_tapbuf_size2_46_sram_blwl_out ; -wire [46:46] mux_1level_tapbuf_size2_46_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_46_configbus0[46:46] = sram_blwl_bl[46:46] ; -assign mux_1level_tapbuf_size2_46_configbus1[46:46] = sram_blwl_wl[46:46] ; -wire [46:46] mux_1level_tapbuf_size2_46_configbus0_b; -assign mux_1level_tapbuf_size2_46_configbus0_b[46:46] = sram_blwl_blb[46:46] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_46_ (mux_1level_tapbuf_size2_46_inbus, chany_0__1__out_92_ , mux_1level_tapbuf_size2_46_sram_blwl_out[46:46] , -mux_1level_tapbuf_size2_46_sram_blwl_outb[46:46] ); -//----- SRAM bits for MUX[46], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_46_ (mux_1level_tapbuf_size2_46_sram_blwl_out[46:46] ,mux_1level_tapbuf_size2_46_sram_blwl_out[46:46] ,mux_1level_tapbuf_size2_46_sram_blwl_outb[46:46] ,mux_1level_tapbuf_size2_46_configbus0[46:46], mux_1level_tapbuf_size2_46_configbus1[46:46] , mux_1level_tapbuf_size2_46_configbus0_b[46:46] ); -wire [0:1] mux_1level_tapbuf_size2_47_inbus; -assign mux_1level_tapbuf_size2_47_inbus[0] = grid_1__1__pin_0__3__47_; -assign mux_1level_tapbuf_size2_47_inbus[1] = chanx_1__0__in_97_ ; -wire [47:47] mux_1level_tapbuf_size2_47_configbus0; -wire [47:47] mux_1level_tapbuf_size2_47_configbus1; -wire [47:47] mux_1level_tapbuf_size2_47_sram_blwl_out ; -wire [47:47] mux_1level_tapbuf_size2_47_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_47_configbus0[47:47] = sram_blwl_bl[47:47] ; -assign mux_1level_tapbuf_size2_47_configbus1[47:47] = sram_blwl_wl[47:47] ; -wire [47:47] mux_1level_tapbuf_size2_47_configbus0_b; -assign mux_1level_tapbuf_size2_47_configbus0_b[47:47] = sram_blwl_blb[47:47] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_47_ (mux_1level_tapbuf_size2_47_inbus, chany_0__1__out_94_ , mux_1level_tapbuf_size2_47_sram_blwl_out[47:47] , -mux_1level_tapbuf_size2_47_sram_blwl_outb[47:47] ); -//----- SRAM bits for MUX[47], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_47_ (mux_1level_tapbuf_size2_47_sram_blwl_out[47:47] ,mux_1level_tapbuf_size2_47_sram_blwl_out[47:47] ,mux_1level_tapbuf_size2_47_sram_blwl_outb[47:47] ,mux_1level_tapbuf_size2_47_configbus0[47:47], mux_1level_tapbuf_size2_47_configbus1[47:47] , mux_1level_tapbuf_size2_47_configbus0_b[47:47] ); -wire [0:1] mux_1level_tapbuf_size2_48_inbus; -assign mux_1level_tapbuf_size2_48_inbus[0] = grid_1__1__pin_0__3__47_; -assign mux_1level_tapbuf_size2_48_inbus[1] = chanx_1__0__in_99_ ; -wire [48:48] mux_1level_tapbuf_size2_48_configbus0; -wire [48:48] mux_1level_tapbuf_size2_48_configbus1; -wire [48:48] mux_1level_tapbuf_size2_48_sram_blwl_out ; -wire [48:48] mux_1level_tapbuf_size2_48_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_48_configbus0[48:48] = sram_blwl_bl[48:48] ; -assign mux_1level_tapbuf_size2_48_configbus1[48:48] = sram_blwl_wl[48:48] ; -wire [48:48] mux_1level_tapbuf_size2_48_configbus0_b; -assign mux_1level_tapbuf_size2_48_configbus0_b[48:48] = sram_blwl_blb[48:48] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_48_ (mux_1level_tapbuf_size2_48_inbus, chany_0__1__out_96_ , mux_1level_tapbuf_size2_48_sram_blwl_out[48:48] , -mux_1level_tapbuf_size2_48_sram_blwl_outb[48:48] ); -//----- SRAM bits for MUX[48], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_48_ (mux_1level_tapbuf_size2_48_sram_blwl_out[48:48] ,mux_1level_tapbuf_size2_48_sram_blwl_out[48:48] ,mux_1level_tapbuf_size2_48_sram_blwl_outb[48:48] ,mux_1level_tapbuf_size2_48_configbus0[48:48], mux_1level_tapbuf_size2_48_configbus1[48:48] , mux_1level_tapbuf_size2_48_configbus0_b[48:48] ); -wire [0:1] mux_1level_tapbuf_size2_49_inbus; -assign mux_1level_tapbuf_size2_49_inbus[0] = grid_1__1__pin_0__3__47_; -assign mux_1level_tapbuf_size2_49_inbus[1] = chanx_1__0__in_1_ ; -wire [49:49] mux_1level_tapbuf_size2_49_configbus0; -wire [49:49] mux_1level_tapbuf_size2_49_configbus1; -wire [49:49] mux_1level_tapbuf_size2_49_sram_blwl_out ; -wire [49:49] mux_1level_tapbuf_size2_49_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_49_configbus0[49:49] = sram_blwl_bl[49:49] ; -assign mux_1level_tapbuf_size2_49_configbus1[49:49] = sram_blwl_wl[49:49] ; -wire [49:49] mux_1level_tapbuf_size2_49_configbus0_b; -assign mux_1level_tapbuf_size2_49_configbus0_b[49:49] = sram_blwl_blb[49:49] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_49_ (mux_1level_tapbuf_size2_49_inbus, chany_0__1__out_98_ , mux_1level_tapbuf_size2_49_sram_blwl_out[49:49] , -mux_1level_tapbuf_size2_49_sram_blwl_outb[49:49] ); -//----- SRAM bits for MUX[49], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_49_ (mux_1level_tapbuf_size2_49_sram_blwl_out[49:49] ,mux_1level_tapbuf_size2_49_sram_blwl_out[49:49] ,mux_1level_tapbuf_size2_49_sram_blwl_outb[49:49] ,mux_1level_tapbuf_size2_49_configbus0[49:49], mux_1level_tapbuf_size2_49_configbus1[49:49] , mux_1level_tapbuf_size2_49_configbus0_b[49:49] ); -//----- right side Multiplexers ----- -wire [0:1] mux_1level_tapbuf_size2_50_inbus; -assign mux_1level_tapbuf_size2_50_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_50_inbus[1] = chany_0__1__in_99_ ; -wire [50:50] mux_1level_tapbuf_size2_50_configbus0; -wire [50:50] mux_1level_tapbuf_size2_50_configbus1; -wire [50:50] mux_1level_tapbuf_size2_50_sram_blwl_out ; -wire [50:50] mux_1level_tapbuf_size2_50_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_50_configbus0[50:50] = sram_blwl_bl[50:50] ; -assign mux_1level_tapbuf_size2_50_configbus1[50:50] = sram_blwl_wl[50:50] ; -wire [50:50] mux_1level_tapbuf_size2_50_configbus0_b; -assign mux_1level_tapbuf_size2_50_configbus0_b[50:50] = sram_blwl_blb[50:50] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_50_ (mux_1level_tapbuf_size2_50_inbus, chanx_1__0__out_0_ , mux_1level_tapbuf_size2_50_sram_blwl_out[50:50] , -mux_1level_tapbuf_size2_50_sram_blwl_outb[50:50] ); -//----- SRAM bits for MUX[50], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_50_ (mux_1level_tapbuf_size2_50_sram_blwl_out[50:50] ,mux_1level_tapbuf_size2_50_sram_blwl_out[50:50] ,mux_1level_tapbuf_size2_50_sram_blwl_outb[50:50] ,mux_1level_tapbuf_size2_50_configbus0[50:50], mux_1level_tapbuf_size2_50_configbus1[50:50] , mux_1level_tapbuf_size2_50_configbus0_b[50:50] ); -wire [0:1] mux_1level_tapbuf_size2_51_inbus; -assign mux_1level_tapbuf_size2_51_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_51_inbus[1] = chany_0__1__in_1_ ; -wire [51:51] mux_1level_tapbuf_size2_51_configbus0; -wire [51:51] mux_1level_tapbuf_size2_51_configbus1; -wire [51:51] mux_1level_tapbuf_size2_51_sram_blwl_out ; -wire [51:51] mux_1level_tapbuf_size2_51_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_51_configbus0[51:51] = sram_blwl_bl[51:51] ; -assign mux_1level_tapbuf_size2_51_configbus1[51:51] = sram_blwl_wl[51:51] ; -wire [51:51] mux_1level_tapbuf_size2_51_configbus0_b; -assign mux_1level_tapbuf_size2_51_configbus0_b[51:51] = sram_blwl_blb[51:51] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_51_ (mux_1level_tapbuf_size2_51_inbus, chanx_1__0__out_2_ , mux_1level_tapbuf_size2_51_sram_blwl_out[51:51] , -mux_1level_tapbuf_size2_51_sram_blwl_outb[51:51] ); -//----- SRAM bits for MUX[51], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_51_ (mux_1level_tapbuf_size2_51_sram_blwl_out[51:51] ,mux_1level_tapbuf_size2_51_sram_blwl_out[51:51] ,mux_1level_tapbuf_size2_51_sram_blwl_outb[51:51] ,mux_1level_tapbuf_size2_51_configbus0[51:51], mux_1level_tapbuf_size2_51_configbus1[51:51] , mux_1level_tapbuf_size2_51_configbus0_b[51:51] ); -wire [0:1] mux_1level_tapbuf_size2_52_inbus; -assign mux_1level_tapbuf_size2_52_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_52_inbus[1] = chany_0__1__in_3_ ; -wire [52:52] mux_1level_tapbuf_size2_52_configbus0; -wire [52:52] mux_1level_tapbuf_size2_52_configbus1; -wire [52:52] mux_1level_tapbuf_size2_52_sram_blwl_out ; -wire [52:52] mux_1level_tapbuf_size2_52_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_52_configbus0[52:52] = sram_blwl_bl[52:52] ; -assign mux_1level_tapbuf_size2_52_configbus1[52:52] = sram_blwl_wl[52:52] ; -wire [52:52] mux_1level_tapbuf_size2_52_configbus0_b; -assign mux_1level_tapbuf_size2_52_configbus0_b[52:52] = sram_blwl_blb[52:52] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_52_ (mux_1level_tapbuf_size2_52_inbus, chanx_1__0__out_4_ , mux_1level_tapbuf_size2_52_sram_blwl_out[52:52] , -mux_1level_tapbuf_size2_52_sram_blwl_outb[52:52] ); -//----- SRAM bits for MUX[52], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_52_ (mux_1level_tapbuf_size2_52_sram_blwl_out[52:52] ,mux_1level_tapbuf_size2_52_sram_blwl_out[52:52] ,mux_1level_tapbuf_size2_52_sram_blwl_outb[52:52] ,mux_1level_tapbuf_size2_52_configbus0[52:52], mux_1level_tapbuf_size2_52_configbus1[52:52] , mux_1level_tapbuf_size2_52_configbus0_b[52:52] ); -wire [0:1] mux_1level_tapbuf_size2_53_inbus; -assign mux_1level_tapbuf_size2_53_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_53_inbus[1] = chany_0__1__in_5_ ; -wire [53:53] mux_1level_tapbuf_size2_53_configbus0; -wire [53:53] mux_1level_tapbuf_size2_53_configbus1; -wire [53:53] mux_1level_tapbuf_size2_53_sram_blwl_out ; -wire [53:53] mux_1level_tapbuf_size2_53_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_53_configbus0[53:53] = sram_blwl_bl[53:53] ; -assign mux_1level_tapbuf_size2_53_configbus1[53:53] = sram_blwl_wl[53:53] ; -wire [53:53] mux_1level_tapbuf_size2_53_configbus0_b; -assign mux_1level_tapbuf_size2_53_configbus0_b[53:53] = sram_blwl_blb[53:53] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_53_ (mux_1level_tapbuf_size2_53_inbus, chanx_1__0__out_6_ , mux_1level_tapbuf_size2_53_sram_blwl_out[53:53] , -mux_1level_tapbuf_size2_53_sram_blwl_outb[53:53] ); -//----- SRAM bits for MUX[53], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_53_ (mux_1level_tapbuf_size2_53_sram_blwl_out[53:53] ,mux_1level_tapbuf_size2_53_sram_blwl_out[53:53] ,mux_1level_tapbuf_size2_53_sram_blwl_outb[53:53] ,mux_1level_tapbuf_size2_53_configbus0[53:53], mux_1level_tapbuf_size2_53_configbus1[53:53] , mux_1level_tapbuf_size2_53_configbus0_b[53:53] ); -wire [0:1] mux_1level_tapbuf_size2_54_inbus; -assign mux_1level_tapbuf_size2_54_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_54_inbus[1] = chany_0__1__in_7_ ; -wire [54:54] mux_1level_tapbuf_size2_54_configbus0; -wire [54:54] mux_1level_tapbuf_size2_54_configbus1; -wire [54:54] mux_1level_tapbuf_size2_54_sram_blwl_out ; -wire [54:54] mux_1level_tapbuf_size2_54_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_54_configbus0[54:54] = sram_blwl_bl[54:54] ; -assign mux_1level_tapbuf_size2_54_configbus1[54:54] = sram_blwl_wl[54:54] ; -wire [54:54] mux_1level_tapbuf_size2_54_configbus0_b; -assign mux_1level_tapbuf_size2_54_configbus0_b[54:54] = sram_blwl_blb[54:54] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_54_ (mux_1level_tapbuf_size2_54_inbus, chanx_1__0__out_8_ , mux_1level_tapbuf_size2_54_sram_blwl_out[54:54] , -mux_1level_tapbuf_size2_54_sram_blwl_outb[54:54] ); -//----- SRAM bits for MUX[54], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_54_ (mux_1level_tapbuf_size2_54_sram_blwl_out[54:54] ,mux_1level_tapbuf_size2_54_sram_blwl_out[54:54] ,mux_1level_tapbuf_size2_54_sram_blwl_outb[54:54] ,mux_1level_tapbuf_size2_54_configbus0[54:54], mux_1level_tapbuf_size2_54_configbus1[54:54] , mux_1level_tapbuf_size2_54_configbus0_b[54:54] ); -wire [0:1] mux_1level_tapbuf_size2_55_inbus; -assign mux_1level_tapbuf_size2_55_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_55_inbus[1] = chany_0__1__in_9_ ; -wire [55:55] mux_1level_tapbuf_size2_55_configbus0; -wire [55:55] mux_1level_tapbuf_size2_55_configbus1; -wire [55:55] mux_1level_tapbuf_size2_55_sram_blwl_out ; -wire [55:55] mux_1level_tapbuf_size2_55_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_55_configbus0[55:55] = sram_blwl_bl[55:55] ; -assign mux_1level_tapbuf_size2_55_configbus1[55:55] = sram_blwl_wl[55:55] ; -wire [55:55] mux_1level_tapbuf_size2_55_configbus0_b; -assign mux_1level_tapbuf_size2_55_configbus0_b[55:55] = sram_blwl_blb[55:55] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_55_ (mux_1level_tapbuf_size2_55_inbus, chanx_1__0__out_10_ , mux_1level_tapbuf_size2_55_sram_blwl_out[55:55] , -mux_1level_tapbuf_size2_55_sram_blwl_outb[55:55] ); -//----- SRAM bits for MUX[55], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_55_ (mux_1level_tapbuf_size2_55_sram_blwl_out[55:55] ,mux_1level_tapbuf_size2_55_sram_blwl_out[55:55] ,mux_1level_tapbuf_size2_55_sram_blwl_outb[55:55] ,mux_1level_tapbuf_size2_55_configbus0[55:55], mux_1level_tapbuf_size2_55_configbus1[55:55] , mux_1level_tapbuf_size2_55_configbus0_b[55:55] ); -wire [0:1] mux_1level_tapbuf_size2_56_inbus; -assign mux_1level_tapbuf_size2_56_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_56_inbus[1] = chany_0__1__in_11_ ; -wire [56:56] mux_1level_tapbuf_size2_56_configbus0; -wire [56:56] mux_1level_tapbuf_size2_56_configbus1; -wire [56:56] mux_1level_tapbuf_size2_56_sram_blwl_out ; -wire [56:56] mux_1level_tapbuf_size2_56_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_56_configbus0[56:56] = sram_blwl_bl[56:56] ; -assign mux_1level_tapbuf_size2_56_configbus1[56:56] = sram_blwl_wl[56:56] ; -wire [56:56] mux_1level_tapbuf_size2_56_configbus0_b; -assign mux_1level_tapbuf_size2_56_configbus0_b[56:56] = sram_blwl_blb[56:56] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_56_ (mux_1level_tapbuf_size2_56_inbus, chanx_1__0__out_12_ , mux_1level_tapbuf_size2_56_sram_blwl_out[56:56] , -mux_1level_tapbuf_size2_56_sram_blwl_outb[56:56] ); -//----- SRAM bits for MUX[56], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_56_ (mux_1level_tapbuf_size2_56_sram_blwl_out[56:56] ,mux_1level_tapbuf_size2_56_sram_blwl_out[56:56] ,mux_1level_tapbuf_size2_56_sram_blwl_outb[56:56] ,mux_1level_tapbuf_size2_56_configbus0[56:56], mux_1level_tapbuf_size2_56_configbus1[56:56] , mux_1level_tapbuf_size2_56_configbus0_b[56:56] ); -wire [0:1] mux_1level_tapbuf_size2_57_inbus; -assign mux_1level_tapbuf_size2_57_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_57_inbus[1] = chany_0__1__in_13_ ; -wire [57:57] mux_1level_tapbuf_size2_57_configbus0; -wire [57:57] mux_1level_tapbuf_size2_57_configbus1; -wire [57:57] mux_1level_tapbuf_size2_57_sram_blwl_out ; -wire [57:57] mux_1level_tapbuf_size2_57_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_57_configbus0[57:57] = sram_blwl_bl[57:57] ; -assign mux_1level_tapbuf_size2_57_configbus1[57:57] = sram_blwl_wl[57:57] ; -wire [57:57] mux_1level_tapbuf_size2_57_configbus0_b; -assign mux_1level_tapbuf_size2_57_configbus0_b[57:57] = sram_blwl_blb[57:57] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_57_ (mux_1level_tapbuf_size2_57_inbus, chanx_1__0__out_14_ , mux_1level_tapbuf_size2_57_sram_blwl_out[57:57] , -mux_1level_tapbuf_size2_57_sram_blwl_outb[57:57] ); -//----- SRAM bits for MUX[57], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_57_ (mux_1level_tapbuf_size2_57_sram_blwl_out[57:57] ,mux_1level_tapbuf_size2_57_sram_blwl_out[57:57] ,mux_1level_tapbuf_size2_57_sram_blwl_outb[57:57] ,mux_1level_tapbuf_size2_57_configbus0[57:57], mux_1level_tapbuf_size2_57_configbus1[57:57] , mux_1level_tapbuf_size2_57_configbus0_b[57:57] ); -wire [0:1] mux_1level_tapbuf_size2_58_inbus; -assign mux_1level_tapbuf_size2_58_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_58_inbus[1] = chany_0__1__in_15_ ; -wire [58:58] mux_1level_tapbuf_size2_58_configbus0; -wire [58:58] mux_1level_tapbuf_size2_58_configbus1; -wire [58:58] mux_1level_tapbuf_size2_58_sram_blwl_out ; -wire [58:58] mux_1level_tapbuf_size2_58_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_58_configbus0[58:58] = sram_blwl_bl[58:58] ; -assign mux_1level_tapbuf_size2_58_configbus1[58:58] = sram_blwl_wl[58:58] ; -wire [58:58] mux_1level_tapbuf_size2_58_configbus0_b; -assign mux_1level_tapbuf_size2_58_configbus0_b[58:58] = sram_blwl_blb[58:58] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_58_ (mux_1level_tapbuf_size2_58_inbus, chanx_1__0__out_16_ , mux_1level_tapbuf_size2_58_sram_blwl_out[58:58] , -mux_1level_tapbuf_size2_58_sram_blwl_outb[58:58] ); -//----- SRAM bits for MUX[58], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_58_ (mux_1level_tapbuf_size2_58_sram_blwl_out[58:58] ,mux_1level_tapbuf_size2_58_sram_blwl_out[58:58] ,mux_1level_tapbuf_size2_58_sram_blwl_outb[58:58] ,mux_1level_tapbuf_size2_58_configbus0[58:58], mux_1level_tapbuf_size2_58_configbus1[58:58] , mux_1level_tapbuf_size2_58_configbus0_b[58:58] ); -wire [0:1] mux_1level_tapbuf_size2_59_inbus; -assign mux_1level_tapbuf_size2_59_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_59_inbus[1] = chany_0__1__in_17_ ; -wire [59:59] mux_1level_tapbuf_size2_59_configbus0; -wire [59:59] mux_1level_tapbuf_size2_59_configbus1; -wire [59:59] mux_1level_tapbuf_size2_59_sram_blwl_out ; -wire [59:59] mux_1level_tapbuf_size2_59_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_59_configbus0[59:59] = sram_blwl_bl[59:59] ; -assign mux_1level_tapbuf_size2_59_configbus1[59:59] = sram_blwl_wl[59:59] ; -wire [59:59] mux_1level_tapbuf_size2_59_configbus0_b; -assign mux_1level_tapbuf_size2_59_configbus0_b[59:59] = sram_blwl_blb[59:59] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_59_ (mux_1level_tapbuf_size2_59_inbus, chanx_1__0__out_18_ , mux_1level_tapbuf_size2_59_sram_blwl_out[59:59] , -mux_1level_tapbuf_size2_59_sram_blwl_outb[59:59] ); -//----- SRAM bits for MUX[59], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_59_ (mux_1level_tapbuf_size2_59_sram_blwl_out[59:59] ,mux_1level_tapbuf_size2_59_sram_blwl_out[59:59] ,mux_1level_tapbuf_size2_59_sram_blwl_outb[59:59] ,mux_1level_tapbuf_size2_59_configbus0[59:59], mux_1level_tapbuf_size2_59_configbus1[59:59] , mux_1level_tapbuf_size2_59_configbus0_b[59:59] ); -wire [0:1] mux_1level_tapbuf_size2_60_inbus; -assign mux_1level_tapbuf_size2_60_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_60_inbus[1] = chany_0__1__in_19_ ; -wire [60:60] mux_1level_tapbuf_size2_60_configbus0; -wire [60:60] mux_1level_tapbuf_size2_60_configbus1; -wire [60:60] mux_1level_tapbuf_size2_60_sram_blwl_out ; -wire [60:60] mux_1level_tapbuf_size2_60_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_60_configbus0[60:60] = sram_blwl_bl[60:60] ; -assign mux_1level_tapbuf_size2_60_configbus1[60:60] = sram_blwl_wl[60:60] ; -wire [60:60] mux_1level_tapbuf_size2_60_configbus0_b; -assign mux_1level_tapbuf_size2_60_configbus0_b[60:60] = sram_blwl_blb[60:60] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_60_ (mux_1level_tapbuf_size2_60_inbus, chanx_1__0__out_20_ , mux_1level_tapbuf_size2_60_sram_blwl_out[60:60] , -mux_1level_tapbuf_size2_60_sram_blwl_outb[60:60] ); -//----- SRAM bits for MUX[60], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_60_ (mux_1level_tapbuf_size2_60_sram_blwl_out[60:60] ,mux_1level_tapbuf_size2_60_sram_blwl_out[60:60] ,mux_1level_tapbuf_size2_60_sram_blwl_outb[60:60] ,mux_1level_tapbuf_size2_60_configbus0[60:60], mux_1level_tapbuf_size2_60_configbus1[60:60] , mux_1level_tapbuf_size2_60_configbus0_b[60:60] ); -wire [0:1] mux_1level_tapbuf_size2_61_inbus; -assign mux_1level_tapbuf_size2_61_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_61_inbus[1] = chany_0__1__in_21_ ; -wire [61:61] mux_1level_tapbuf_size2_61_configbus0; -wire [61:61] mux_1level_tapbuf_size2_61_configbus1; -wire [61:61] mux_1level_tapbuf_size2_61_sram_blwl_out ; -wire [61:61] mux_1level_tapbuf_size2_61_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_61_configbus0[61:61] = sram_blwl_bl[61:61] ; -assign mux_1level_tapbuf_size2_61_configbus1[61:61] = sram_blwl_wl[61:61] ; -wire [61:61] mux_1level_tapbuf_size2_61_configbus0_b; -assign mux_1level_tapbuf_size2_61_configbus0_b[61:61] = sram_blwl_blb[61:61] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_61_ (mux_1level_tapbuf_size2_61_inbus, chanx_1__0__out_22_ , mux_1level_tapbuf_size2_61_sram_blwl_out[61:61] , -mux_1level_tapbuf_size2_61_sram_blwl_outb[61:61] ); -//----- SRAM bits for MUX[61], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_61_ (mux_1level_tapbuf_size2_61_sram_blwl_out[61:61] ,mux_1level_tapbuf_size2_61_sram_blwl_out[61:61] ,mux_1level_tapbuf_size2_61_sram_blwl_outb[61:61] ,mux_1level_tapbuf_size2_61_configbus0[61:61], mux_1level_tapbuf_size2_61_configbus1[61:61] , mux_1level_tapbuf_size2_61_configbus0_b[61:61] ); -wire [0:1] mux_1level_tapbuf_size2_62_inbus; -assign mux_1level_tapbuf_size2_62_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_62_inbus[1] = chany_0__1__in_23_ ; -wire [62:62] mux_1level_tapbuf_size2_62_configbus0; -wire [62:62] mux_1level_tapbuf_size2_62_configbus1; -wire [62:62] mux_1level_tapbuf_size2_62_sram_blwl_out ; -wire [62:62] mux_1level_tapbuf_size2_62_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_62_configbus0[62:62] = sram_blwl_bl[62:62] ; -assign mux_1level_tapbuf_size2_62_configbus1[62:62] = sram_blwl_wl[62:62] ; -wire [62:62] mux_1level_tapbuf_size2_62_configbus0_b; -assign mux_1level_tapbuf_size2_62_configbus0_b[62:62] = sram_blwl_blb[62:62] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_62_ (mux_1level_tapbuf_size2_62_inbus, chanx_1__0__out_24_ , mux_1level_tapbuf_size2_62_sram_blwl_out[62:62] , -mux_1level_tapbuf_size2_62_sram_blwl_outb[62:62] ); -//----- SRAM bits for MUX[62], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_62_ (mux_1level_tapbuf_size2_62_sram_blwl_out[62:62] ,mux_1level_tapbuf_size2_62_sram_blwl_out[62:62] ,mux_1level_tapbuf_size2_62_sram_blwl_outb[62:62] ,mux_1level_tapbuf_size2_62_configbus0[62:62], mux_1level_tapbuf_size2_62_configbus1[62:62] , mux_1level_tapbuf_size2_62_configbus0_b[62:62] ); -wire [0:1] mux_1level_tapbuf_size2_63_inbus; -assign mux_1level_tapbuf_size2_63_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_63_inbus[1] = chany_0__1__in_25_ ; -wire [63:63] mux_1level_tapbuf_size2_63_configbus0; -wire [63:63] mux_1level_tapbuf_size2_63_configbus1; -wire [63:63] mux_1level_tapbuf_size2_63_sram_blwl_out ; -wire [63:63] mux_1level_tapbuf_size2_63_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_63_configbus0[63:63] = sram_blwl_bl[63:63] ; -assign mux_1level_tapbuf_size2_63_configbus1[63:63] = sram_blwl_wl[63:63] ; -wire [63:63] mux_1level_tapbuf_size2_63_configbus0_b; -assign mux_1level_tapbuf_size2_63_configbus0_b[63:63] = sram_blwl_blb[63:63] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_63_ (mux_1level_tapbuf_size2_63_inbus, chanx_1__0__out_26_ , mux_1level_tapbuf_size2_63_sram_blwl_out[63:63] , -mux_1level_tapbuf_size2_63_sram_blwl_outb[63:63] ); -//----- SRAM bits for MUX[63], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_63_ (mux_1level_tapbuf_size2_63_sram_blwl_out[63:63] ,mux_1level_tapbuf_size2_63_sram_blwl_out[63:63] ,mux_1level_tapbuf_size2_63_sram_blwl_outb[63:63] ,mux_1level_tapbuf_size2_63_configbus0[63:63], mux_1level_tapbuf_size2_63_configbus1[63:63] , mux_1level_tapbuf_size2_63_configbus0_b[63:63] ); -wire [0:1] mux_1level_tapbuf_size2_64_inbus; -assign mux_1level_tapbuf_size2_64_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_64_inbus[1] = chany_0__1__in_27_ ; -wire [64:64] mux_1level_tapbuf_size2_64_configbus0; -wire [64:64] mux_1level_tapbuf_size2_64_configbus1; -wire [64:64] mux_1level_tapbuf_size2_64_sram_blwl_out ; -wire [64:64] mux_1level_tapbuf_size2_64_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_64_configbus0[64:64] = sram_blwl_bl[64:64] ; -assign mux_1level_tapbuf_size2_64_configbus1[64:64] = sram_blwl_wl[64:64] ; -wire [64:64] mux_1level_tapbuf_size2_64_configbus0_b; -assign mux_1level_tapbuf_size2_64_configbus0_b[64:64] = sram_blwl_blb[64:64] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_64_ (mux_1level_tapbuf_size2_64_inbus, chanx_1__0__out_28_ , mux_1level_tapbuf_size2_64_sram_blwl_out[64:64] , -mux_1level_tapbuf_size2_64_sram_blwl_outb[64:64] ); -//----- SRAM bits for MUX[64], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_64_ (mux_1level_tapbuf_size2_64_sram_blwl_out[64:64] ,mux_1level_tapbuf_size2_64_sram_blwl_out[64:64] ,mux_1level_tapbuf_size2_64_sram_blwl_outb[64:64] ,mux_1level_tapbuf_size2_64_configbus0[64:64], mux_1level_tapbuf_size2_64_configbus1[64:64] , mux_1level_tapbuf_size2_64_configbus0_b[64:64] ); -wire [0:1] mux_1level_tapbuf_size2_65_inbus; -assign mux_1level_tapbuf_size2_65_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_65_inbus[1] = chany_0__1__in_29_ ; -wire [65:65] mux_1level_tapbuf_size2_65_configbus0; -wire [65:65] mux_1level_tapbuf_size2_65_configbus1; -wire [65:65] mux_1level_tapbuf_size2_65_sram_blwl_out ; -wire [65:65] mux_1level_tapbuf_size2_65_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_65_configbus0[65:65] = sram_blwl_bl[65:65] ; -assign mux_1level_tapbuf_size2_65_configbus1[65:65] = sram_blwl_wl[65:65] ; -wire [65:65] mux_1level_tapbuf_size2_65_configbus0_b; -assign mux_1level_tapbuf_size2_65_configbus0_b[65:65] = sram_blwl_blb[65:65] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_65_ (mux_1level_tapbuf_size2_65_inbus, chanx_1__0__out_30_ , mux_1level_tapbuf_size2_65_sram_blwl_out[65:65] , -mux_1level_tapbuf_size2_65_sram_blwl_outb[65:65] ); -//----- SRAM bits for MUX[65], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_65_ (mux_1level_tapbuf_size2_65_sram_blwl_out[65:65] ,mux_1level_tapbuf_size2_65_sram_blwl_out[65:65] ,mux_1level_tapbuf_size2_65_sram_blwl_outb[65:65] ,mux_1level_tapbuf_size2_65_configbus0[65:65], mux_1level_tapbuf_size2_65_configbus1[65:65] , mux_1level_tapbuf_size2_65_configbus0_b[65:65] ); -wire [0:1] mux_1level_tapbuf_size2_66_inbus; -assign mux_1level_tapbuf_size2_66_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_66_inbus[1] = chany_0__1__in_31_ ; -wire [66:66] mux_1level_tapbuf_size2_66_configbus0; -wire [66:66] mux_1level_tapbuf_size2_66_configbus1; -wire [66:66] mux_1level_tapbuf_size2_66_sram_blwl_out ; -wire [66:66] mux_1level_tapbuf_size2_66_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_66_configbus0[66:66] = sram_blwl_bl[66:66] ; -assign mux_1level_tapbuf_size2_66_configbus1[66:66] = sram_blwl_wl[66:66] ; -wire [66:66] mux_1level_tapbuf_size2_66_configbus0_b; -assign mux_1level_tapbuf_size2_66_configbus0_b[66:66] = sram_blwl_blb[66:66] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_66_ (mux_1level_tapbuf_size2_66_inbus, chanx_1__0__out_32_ , mux_1level_tapbuf_size2_66_sram_blwl_out[66:66] , -mux_1level_tapbuf_size2_66_sram_blwl_outb[66:66] ); -//----- SRAM bits for MUX[66], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_66_ (mux_1level_tapbuf_size2_66_sram_blwl_out[66:66] ,mux_1level_tapbuf_size2_66_sram_blwl_out[66:66] ,mux_1level_tapbuf_size2_66_sram_blwl_outb[66:66] ,mux_1level_tapbuf_size2_66_configbus0[66:66], mux_1level_tapbuf_size2_66_configbus1[66:66] , mux_1level_tapbuf_size2_66_configbus0_b[66:66] ); -wire [0:1] mux_1level_tapbuf_size2_67_inbus; -assign mux_1level_tapbuf_size2_67_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_67_inbus[1] = chany_0__1__in_33_ ; -wire [67:67] mux_1level_tapbuf_size2_67_configbus0; -wire [67:67] mux_1level_tapbuf_size2_67_configbus1; -wire [67:67] mux_1level_tapbuf_size2_67_sram_blwl_out ; -wire [67:67] mux_1level_tapbuf_size2_67_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_67_configbus0[67:67] = sram_blwl_bl[67:67] ; -assign mux_1level_tapbuf_size2_67_configbus1[67:67] = sram_blwl_wl[67:67] ; -wire [67:67] mux_1level_tapbuf_size2_67_configbus0_b; -assign mux_1level_tapbuf_size2_67_configbus0_b[67:67] = sram_blwl_blb[67:67] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_67_ (mux_1level_tapbuf_size2_67_inbus, chanx_1__0__out_34_ , mux_1level_tapbuf_size2_67_sram_blwl_out[67:67] , -mux_1level_tapbuf_size2_67_sram_blwl_outb[67:67] ); -//----- SRAM bits for MUX[67], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_67_ (mux_1level_tapbuf_size2_67_sram_blwl_out[67:67] ,mux_1level_tapbuf_size2_67_sram_blwl_out[67:67] ,mux_1level_tapbuf_size2_67_sram_blwl_outb[67:67] ,mux_1level_tapbuf_size2_67_configbus0[67:67], mux_1level_tapbuf_size2_67_configbus1[67:67] , mux_1level_tapbuf_size2_67_configbus0_b[67:67] ); -wire [0:1] mux_1level_tapbuf_size2_68_inbus; -assign mux_1level_tapbuf_size2_68_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_68_inbus[1] = chany_0__1__in_35_ ; -wire [68:68] mux_1level_tapbuf_size2_68_configbus0; -wire [68:68] mux_1level_tapbuf_size2_68_configbus1; -wire [68:68] mux_1level_tapbuf_size2_68_sram_blwl_out ; -wire [68:68] mux_1level_tapbuf_size2_68_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_68_configbus0[68:68] = sram_blwl_bl[68:68] ; -assign mux_1level_tapbuf_size2_68_configbus1[68:68] = sram_blwl_wl[68:68] ; -wire [68:68] mux_1level_tapbuf_size2_68_configbus0_b; -assign mux_1level_tapbuf_size2_68_configbus0_b[68:68] = sram_blwl_blb[68:68] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_68_ (mux_1level_tapbuf_size2_68_inbus, chanx_1__0__out_36_ , mux_1level_tapbuf_size2_68_sram_blwl_out[68:68] , -mux_1level_tapbuf_size2_68_sram_blwl_outb[68:68] ); -//----- SRAM bits for MUX[68], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_68_ (mux_1level_tapbuf_size2_68_sram_blwl_out[68:68] ,mux_1level_tapbuf_size2_68_sram_blwl_out[68:68] ,mux_1level_tapbuf_size2_68_sram_blwl_outb[68:68] ,mux_1level_tapbuf_size2_68_configbus0[68:68], mux_1level_tapbuf_size2_68_configbus1[68:68] , mux_1level_tapbuf_size2_68_configbus0_b[68:68] ); -wire [0:1] mux_1level_tapbuf_size2_69_inbus; -assign mux_1level_tapbuf_size2_69_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_69_inbus[1] = chany_0__1__in_37_ ; -wire [69:69] mux_1level_tapbuf_size2_69_configbus0; -wire [69:69] mux_1level_tapbuf_size2_69_configbus1; -wire [69:69] mux_1level_tapbuf_size2_69_sram_blwl_out ; -wire [69:69] mux_1level_tapbuf_size2_69_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_69_configbus0[69:69] = sram_blwl_bl[69:69] ; -assign mux_1level_tapbuf_size2_69_configbus1[69:69] = sram_blwl_wl[69:69] ; -wire [69:69] mux_1level_tapbuf_size2_69_configbus0_b; -assign mux_1level_tapbuf_size2_69_configbus0_b[69:69] = sram_blwl_blb[69:69] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_69_ (mux_1level_tapbuf_size2_69_inbus, chanx_1__0__out_38_ , mux_1level_tapbuf_size2_69_sram_blwl_out[69:69] , -mux_1level_tapbuf_size2_69_sram_blwl_outb[69:69] ); -//----- SRAM bits for MUX[69], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_69_ (mux_1level_tapbuf_size2_69_sram_blwl_out[69:69] ,mux_1level_tapbuf_size2_69_sram_blwl_out[69:69] ,mux_1level_tapbuf_size2_69_sram_blwl_outb[69:69] ,mux_1level_tapbuf_size2_69_configbus0[69:69], mux_1level_tapbuf_size2_69_configbus1[69:69] , mux_1level_tapbuf_size2_69_configbus0_b[69:69] ); -wire [0:1] mux_1level_tapbuf_size2_70_inbus; -assign mux_1level_tapbuf_size2_70_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_70_inbus[1] = chany_0__1__in_39_ ; -wire [70:70] mux_1level_tapbuf_size2_70_configbus0; -wire [70:70] mux_1level_tapbuf_size2_70_configbus1; -wire [70:70] mux_1level_tapbuf_size2_70_sram_blwl_out ; -wire [70:70] mux_1level_tapbuf_size2_70_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_70_configbus0[70:70] = sram_blwl_bl[70:70] ; -assign mux_1level_tapbuf_size2_70_configbus1[70:70] = sram_blwl_wl[70:70] ; -wire [70:70] mux_1level_tapbuf_size2_70_configbus0_b; -assign mux_1level_tapbuf_size2_70_configbus0_b[70:70] = sram_blwl_blb[70:70] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_70_ (mux_1level_tapbuf_size2_70_inbus, chanx_1__0__out_40_ , mux_1level_tapbuf_size2_70_sram_blwl_out[70:70] , -mux_1level_tapbuf_size2_70_sram_blwl_outb[70:70] ); -//----- SRAM bits for MUX[70], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_70_ (mux_1level_tapbuf_size2_70_sram_blwl_out[70:70] ,mux_1level_tapbuf_size2_70_sram_blwl_out[70:70] ,mux_1level_tapbuf_size2_70_sram_blwl_outb[70:70] ,mux_1level_tapbuf_size2_70_configbus0[70:70], mux_1level_tapbuf_size2_70_configbus1[70:70] , mux_1level_tapbuf_size2_70_configbus0_b[70:70] ); -wire [0:1] mux_1level_tapbuf_size2_71_inbus; -assign mux_1level_tapbuf_size2_71_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_71_inbus[1] = chany_0__1__in_41_ ; -wire [71:71] mux_1level_tapbuf_size2_71_configbus0; -wire [71:71] mux_1level_tapbuf_size2_71_configbus1; -wire [71:71] mux_1level_tapbuf_size2_71_sram_blwl_out ; -wire [71:71] mux_1level_tapbuf_size2_71_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_71_configbus0[71:71] = sram_blwl_bl[71:71] ; -assign mux_1level_tapbuf_size2_71_configbus1[71:71] = sram_blwl_wl[71:71] ; -wire [71:71] mux_1level_tapbuf_size2_71_configbus0_b; -assign mux_1level_tapbuf_size2_71_configbus0_b[71:71] = sram_blwl_blb[71:71] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_71_ (mux_1level_tapbuf_size2_71_inbus, chanx_1__0__out_42_ , mux_1level_tapbuf_size2_71_sram_blwl_out[71:71] , -mux_1level_tapbuf_size2_71_sram_blwl_outb[71:71] ); -//----- SRAM bits for MUX[71], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_71_ (mux_1level_tapbuf_size2_71_sram_blwl_out[71:71] ,mux_1level_tapbuf_size2_71_sram_blwl_out[71:71] ,mux_1level_tapbuf_size2_71_sram_blwl_outb[71:71] ,mux_1level_tapbuf_size2_71_configbus0[71:71], mux_1level_tapbuf_size2_71_configbus1[71:71] , mux_1level_tapbuf_size2_71_configbus0_b[71:71] ); -wire [0:1] mux_1level_tapbuf_size2_72_inbus; -assign mux_1level_tapbuf_size2_72_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_72_inbus[1] = chany_0__1__in_43_ ; -wire [72:72] mux_1level_tapbuf_size2_72_configbus0; -wire [72:72] mux_1level_tapbuf_size2_72_configbus1; -wire [72:72] mux_1level_tapbuf_size2_72_sram_blwl_out ; -wire [72:72] mux_1level_tapbuf_size2_72_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_72_configbus0[72:72] = sram_blwl_bl[72:72] ; -assign mux_1level_tapbuf_size2_72_configbus1[72:72] = sram_blwl_wl[72:72] ; -wire [72:72] mux_1level_tapbuf_size2_72_configbus0_b; -assign mux_1level_tapbuf_size2_72_configbus0_b[72:72] = sram_blwl_blb[72:72] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_72_ (mux_1level_tapbuf_size2_72_inbus, chanx_1__0__out_44_ , mux_1level_tapbuf_size2_72_sram_blwl_out[72:72] , -mux_1level_tapbuf_size2_72_sram_blwl_outb[72:72] ); -//----- SRAM bits for MUX[72], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_72_ (mux_1level_tapbuf_size2_72_sram_blwl_out[72:72] ,mux_1level_tapbuf_size2_72_sram_blwl_out[72:72] ,mux_1level_tapbuf_size2_72_sram_blwl_outb[72:72] ,mux_1level_tapbuf_size2_72_configbus0[72:72], mux_1level_tapbuf_size2_72_configbus1[72:72] , mux_1level_tapbuf_size2_72_configbus0_b[72:72] ); -wire [0:1] mux_1level_tapbuf_size2_73_inbus; -assign mux_1level_tapbuf_size2_73_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_73_inbus[1] = chany_0__1__in_45_ ; -wire [73:73] mux_1level_tapbuf_size2_73_configbus0; -wire [73:73] mux_1level_tapbuf_size2_73_configbus1; -wire [73:73] mux_1level_tapbuf_size2_73_sram_blwl_out ; -wire [73:73] mux_1level_tapbuf_size2_73_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_73_configbus0[73:73] = sram_blwl_bl[73:73] ; -assign mux_1level_tapbuf_size2_73_configbus1[73:73] = sram_blwl_wl[73:73] ; -wire [73:73] mux_1level_tapbuf_size2_73_configbus0_b; -assign mux_1level_tapbuf_size2_73_configbus0_b[73:73] = sram_blwl_blb[73:73] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_73_ (mux_1level_tapbuf_size2_73_inbus, chanx_1__0__out_46_ , mux_1level_tapbuf_size2_73_sram_blwl_out[73:73] , -mux_1level_tapbuf_size2_73_sram_blwl_outb[73:73] ); -//----- SRAM bits for MUX[73], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_73_ (mux_1level_tapbuf_size2_73_sram_blwl_out[73:73] ,mux_1level_tapbuf_size2_73_sram_blwl_out[73:73] ,mux_1level_tapbuf_size2_73_sram_blwl_outb[73:73] ,mux_1level_tapbuf_size2_73_configbus0[73:73], mux_1level_tapbuf_size2_73_configbus1[73:73] , mux_1level_tapbuf_size2_73_configbus0_b[73:73] ); -wire [0:1] mux_1level_tapbuf_size2_74_inbus; -assign mux_1level_tapbuf_size2_74_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_74_inbus[1] = chany_0__1__in_47_ ; -wire [74:74] mux_1level_tapbuf_size2_74_configbus0; -wire [74:74] mux_1level_tapbuf_size2_74_configbus1; -wire [74:74] mux_1level_tapbuf_size2_74_sram_blwl_out ; -wire [74:74] mux_1level_tapbuf_size2_74_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_74_configbus0[74:74] = sram_blwl_bl[74:74] ; -assign mux_1level_tapbuf_size2_74_configbus1[74:74] = sram_blwl_wl[74:74] ; -wire [74:74] mux_1level_tapbuf_size2_74_configbus0_b; -assign mux_1level_tapbuf_size2_74_configbus0_b[74:74] = sram_blwl_blb[74:74] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_74_ (mux_1level_tapbuf_size2_74_inbus, chanx_1__0__out_48_ , mux_1level_tapbuf_size2_74_sram_blwl_out[74:74] , -mux_1level_tapbuf_size2_74_sram_blwl_outb[74:74] ); -//----- SRAM bits for MUX[74], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_74_ (mux_1level_tapbuf_size2_74_sram_blwl_out[74:74] ,mux_1level_tapbuf_size2_74_sram_blwl_out[74:74] ,mux_1level_tapbuf_size2_74_sram_blwl_outb[74:74] ,mux_1level_tapbuf_size2_74_configbus0[74:74], mux_1level_tapbuf_size2_74_configbus1[74:74] , mux_1level_tapbuf_size2_74_configbus0_b[74:74] ); -wire [0:1] mux_1level_tapbuf_size2_75_inbus; -assign mux_1level_tapbuf_size2_75_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_75_inbus[1] = chany_0__1__in_49_ ; -wire [75:75] mux_1level_tapbuf_size2_75_configbus0; -wire [75:75] mux_1level_tapbuf_size2_75_configbus1; -wire [75:75] mux_1level_tapbuf_size2_75_sram_blwl_out ; -wire [75:75] mux_1level_tapbuf_size2_75_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_75_configbus0[75:75] = sram_blwl_bl[75:75] ; -assign mux_1level_tapbuf_size2_75_configbus1[75:75] = sram_blwl_wl[75:75] ; -wire [75:75] mux_1level_tapbuf_size2_75_configbus0_b; -assign mux_1level_tapbuf_size2_75_configbus0_b[75:75] = sram_blwl_blb[75:75] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_75_ (mux_1level_tapbuf_size2_75_inbus, chanx_1__0__out_50_ , mux_1level_tapbuf_size2_75_sram_blwl_out[75:75] , -mux_1level_tapbuf_size2_75_sram_blwl_outb[75:75] ); -//----- SRAM bits for MUX[75], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_75_ (mux_1level_tapbuf_size2_75_sram_blwl_out[75:75] ,mux_1level_tapbuf_size2_75_sram_blwl_out[75:75] ,mux_1level_tapbuf_size2_75_sram_blwl_outb[75:75] ,mux_1level_tapbuf_size2_75_configbus0[75:75], mux_1level_tapbuf_size2_75_configbus1[75:75] , mux_1level_tapbuf_size2_75_configbus0_b[75:75] ); -wire [0:1] mux_1level_tapbuf_size2_76_inbus; -assign mux_1level_tapbuf_size2_76_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_76_inbus[1] = chany_0__1__in_51_ ; -wire [76:76] mux_1level_tapbuf_size2_76_configbus0; -wire [76:76] mux_1level_tapbuf_size2_76_configbus1; -wire [76:76] mux_1level_tapbuf_size2_76_sram_blwl_out ; -wire [76:76] mux_1level_tapbuf_size2_76_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_76_configbus0[76:76] = sram_blwl_bl[76:76] ; -assign mux_1level_tapbuf_size2_76_configbus1[76:76] = sram_blwl_wl[76:76] ; -wire [76:76] mux_1level_tapbuf_size2_76_configbus0_b; -assign mux_1level_tapbuf_size2_76_configbus0_b[76:76] = sram_blwl_blb[76:76] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_76_ (mux_1level_tapbuf_size2_76_inbus, chanx_1__0__out_52_ , mux_1level_tapbuf_size2_76_sram_blwl_out[76:76] , -mux_1level_tapbuf_size2_76_sram_blwl_outb[76:76] ); -//----- SRAM bits for MUX[76], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_76_ (mux_1level_tapbuf_size2_76_sram_blwl_out[76:76] ,mux_1level_tapbuf_size2_76_sram_blwl_out[76:76] ,mux_1level_tapbuf_size2_76_sram_blwl_outb[76:76] ,mux_1level_tapbuf_size2_76_configbus0[76:76], mux_1level_tapbuf_size2_76_configbus1[76:76] , mux_1level_tapbuf_size2_76_configbus0_b[76:76] ); -wire [0:1] mux_1level_tapbuf_size2_77_inbus; -assign mux_1level_tapbuf_size2_77_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_77_inbus[1] = chany_0__1__in_53_ ; -wire [77:77] mux_1level_tapbuf_size2_77_configbus0; -wire [77:77] mux_1level_tapbuf_size2_77_configbus1; -wire [77:77] mux_1level_tapbuf_size2_77_sram_blwl_out ; -wire [77:77] mux_1level_tapbuf_size2_77_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_77_configbus0[77:77] = sram_blwl_bl[77:77] ; -assign mux_1level_tapbuf_size2_77_configbus1[77:77] = sram_blwl_wl[77:77] ; -wire [77:77] mux_1level_tapbuf_size2_77_configbus0_b; -assign mux_1level_tapbuf_size2_77_configbus0_b[77:77] = sram_blwl_blb[77:77] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_77_ (mux_1level_tapbuf_size2_77_inbus, chanx_1__0__out_54_ , mux_1level_tapbuf_size2_77_sram_blwl_out[77:77] , -mux_1level_tapbuf_size2_77_sram_blwl_outb[77:77] ); -//----- SRAM bits for MUX[77], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_77_ (mux_1level_tapbuf_size2_77_sram_blwl_out[77:77] ,mux_1level_tapbuf_size2_77_sram_blwl_out[77:77] ,mux_1level_tapbuf_size2_77_sram_blwl_outb[77:77] ,mux_1level_tapbuf_size2_77_configbus0[77:77], mux_1level_tapbuf_size2_77_configbus1[77:77] , mux_1level_tapbuf_size2_77_configbus0_b[77:77] ); -wire [0:1] mux_1level_tapbuf_size2_78_inbus; -assign mux_1level_tapbuf_size2_78_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_78_inbus[1] = chany_0__1__in_55_ ; -wire [78:78] mux_1level_tapbuf_size2_78_configbus0; -wire [78:78] mux_1level_tapbuf_size2_78_configbus1; -wire [78:78] mux_1level_tapbuf_size2_78_sram_blwl_out ; -wire [78:78] mux_1level_tapbuf_size2_78_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_78_configbus0[78:78] = sram_blwl_bl[78:78] ; -assign mux_1level_tapbuf_size2_78_configbus1[78:78] = sram_blwl_wl[78:78] ; -wire [78:78] mux_1level_tapbuf_size2_78_configbus0_b; -assign mux_1level_tapbuf_size2_78_configbus0_b[78:78] = sram_blwl_blb[78:78] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_78_ (mux_1level_tapbuf_size2_78_inbus, chanx_1__0__out_56_ , mux_1level_tapbuf_size2_78_sram_blwl_out[78:78] , -mux_1level_tapbuf_size2_78_sram_blwl_outb[78:78] ); -//----- SRAM bits for MUX[78], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_78_ (mux_1level_tapbuf_size2_78_sram_blwl_out[78:78] ,mux_1level_tapbuf_size2_78_sram_blwl_out[78:78] ,mux_1level_tapbuf_size2_78_sram_blwl_outb[78:78] ,mux_1level_tapbuf_size2_78_configbus0[78:78], mux_1level_tapbuf_size2_78_configbus1[78:78] , mux_1level_tapbuf_size2_78_configbus0_b[78:78] ); -wire [0:1] mux_1level_tapbuf_size2_79_inbus; -assign mux_1level_tapbuf_size2_79_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_79_inbus[1] = chany_0__1__in_57_ ; -wire [79:79] mux_1level_tapbuf_size2_79_configbus0; -wire [79:79] mux_1level_tapbuf_size2_79_configbus1; -wire [79:79] mux_1level_tapbuf_size2_79_sram_blwl_out ; -wire [79:79] mux_1level_tapbuf_size2_79_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_79_configbus0[79:79] = sram_blwl_bl[79:79] ; -assign mux_1level_tapbuf_size2_79_configbus1[79:79] = sram_blwl_wl[79:79] ; -wire [79:79] mux_1level_tapbuf_size2_79_configbus0_b; -assign mux_1level_tapbuf_size2_79_configbus0_b[79:79] = sram_blwl_blb[79:79] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_79_ (mux_1level_tapbuf_size2_79_inbus, chanx_1__0__out_58_ , mux_1level_tapbuf_size2_79_sram_blwl_out[79:79] , -mux_1level_tapbuf_size2_79_sram_blwl_outb[79:79] ); -//----- SRAM bits for MUX[79], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_79_ (mux_1level_tapbuf_size2_79_sram_blwl_out[79:79] ,mux_1level_tapbuf_size2_79_sram_blwl_out[79:79] ,mux_1level_tapbuf_size2_79_sram_blwl_outb[79:79] ,mux_1level_tapbuf_size2_79_configbus0[79:79], mux_1level_tapbuf_size2_79_configbus1[79:79] , mux_1level_tapbuf_size2_79_configbus0_b[79:79] ); -wire [0:1] mux_1level_tapbuf_size2_80_inbus; -assign mux_1level_tapbuf_size2_80_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_80_inbus[1] = chany_0__1__in_59_ ; -wire [80:80] mux_1level_tapbuf_size2_80_configbus0; -wire [80:80] mux_1level_tapbuf_size2_80_configbus1; -wire [80:80] mux_1level_tapbuf_size2_80_sram_blwl_out ; -wire [80:80] mux_1level_tapbuf_size2_80_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_80_configbus0[80:80] = sram_blwl_bl[80:80] ; -assign mux_1level_tapbuf_size2_80_configbus1[80:80] = sram_blwl_wl[80:80] ; -wire [80:80] mux_1level_tapbuf_size2_80_configbus0_b; -assign mux_1level_tapbuf_size2_80_configbus0_b[80:80] = sram_blwl_blb[80:80] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_80_ (mux_1level_tapbuf_size2_80_inbus, chanx_1__0__out_60_ , mux_1level_tapbuf_size2_80_sram_blwl_out[80:80] , -mux_1level_tapbuf_size2_80_sram_blwl_outb[80:80] ); -//----- SRAM bits for MUX[80], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_80_ (mux_1level_tapbuf_size2_80_sram_blwl_out[80:80] ,mux_1level_tapbuf_size2_80_sram_blwl_out[80:80] ,mux_1level_tapbuf_size2_80_sram_blwl_outb[80:80] ,mux_1level_tapbuf_size2_80_configbus0[80:80], mux_1level_tapbuf_size2_80_configbus1[80:80] , mux_1level_tapbuf_size2_80_configbus0_b[80:80] ); -wire [0:1] mux_1level_tapbuf_size2_81_inbus; -assign mux_1level_tapbuf_size2_81_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_81_inbus[1] = chany_0__1__in_61_ ; -wire [81:81] mux_1level_tapbuf_size2_81_configbus0; -wire [81:81] mux_1level_tapbuf_size2_81_configbus1; -wire [81:81] mux_1level_tapbuf_size2_81_sram_blwl_out ; -wire [81:81] mux_1level_tapbuf_size2_81_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_81_configbus0[81:81] = sram_blwl_bl[81:81] ; -assign mux_1level_tapbuf_size2_81_configbus1[81:81] = sram_blwl_wl[81:81] ; -wire [81:81] mux_1level_tapbuf_size2_81_configbus0_b; -assign mux_1level_tapbuf_size2_81_configbus0_b[81:81] = sram_blwl_blb[81:81] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_81_ (mux_1level_tapbuf_size2_81_inbus, chanx_1__0__out_62_ , mux_1level_tapbuf_size2_81_sram_blwl_out[81:81] , -mux_1level_tapbuf_size2_81_sram_blwl_outb[81:81] ); -//----- SRAM bits for MUX[81], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_81_ (mux_1level_tapbuf_size2_81_sram_blwl_out[81:81] ,mux_1level_tapbuf_size2_81_sram_blwl_out[81:81] ,mux_1level_tapbuf_size2_81_sram_blwl_outb[81:81] ,mux_1level_tapbuf_size2_81_configbus0[81:81], mux_1level_tapbuf_size2_81_configbus1[81:81] , mux_1level_tapbuf_size2_81_configbus0_b[81:81] ); -wire [0:1] mux_1level_tapbuf_size2_82_inbus; -assign mux_1level_tapbuf_size2_82_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_82_inbus[1] = chany_0__1__in_63_ ; -wire [82:82] mux_1level_tapbuf_size2_82_configbus0; -wire [82:82] mux_1level_tapbuf_size2_82_configbus1; -wire [82:82] mux_1level_tapbuf_size2_82_sram_blwl_out ; -wire [82:82] mux_1level_tapbuf_size2_82_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_82_configbus0[82:82] = sram_blwl_bl[82:82] ; -assign mux_1level_tapbuf_size2_82_configbus1[82:82] = sram_blwl_wl[82:82] ; -wire [82:82] mux_1level_tapbuf_size2_82_configbus0_b; -assign mux_1level_tapbuf_size2_82_configbus0_b[82:82] = sram_blwl_blb[82:82] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_82_ (mux_1level_tapbuf_size2_82_inbus, chanx_1__0__out_64_ , mux_1level_tapbuf_size2_82_sram_blwl_out[82:82] , -mux_1level_tapbuf_size2_82_sram_blwl_outb[82:82] ); -//----- SRAM bits for MUX[82], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_82_ (mux_1level_tapbuf_size2_82_sram_blwl_out[82:82] ,mux_1level_tapbuf_size2_82_sram_blwl_out[82:82] ,mux_1level_tapbuf_size2_82_sram_blwl_outb[82:82] ,mux_1level_tapbuf_size2_82_configbus0[82:82], mux_1level_tapbuf_size2_82_configbus1[82:82] , mux_1level_tapbuf_size2_82_configbus0_b[82:82] ); -wire [0:1] mux_1level_tapbuf_size2_83_inbus; -assign mux_1level_tapbuf_size2_83_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_83_inbus[1] = chany_0__1__in_65_ ; -wire [83:83] mux_1level_tapbuf_size2_83_configbus0; -wire [83:83] mux_1level_tapbuf_size2_83_configbus1; -wire [83:83] mux_1level_tapbuf_size2_83_sram_blwl_out ; -wire [83:83] mux_1level_tapbuf_size2_83_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_83_configbus0[83:83] = sram_blwl_bl[83:83] ; -assign mux_1level_tapbuf_size2_83_configbus1[83:83] = sram_blwl_wl[83:83] ; -wire [83:83] mux_1level_tapbuf_size2_83_configbus0_b; -assign mux_1level_tapbuf_size2_83_configbus0_b[83:83] = sram_blwl_blb[83:83] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_83_ (mux_1level_tapbuf_size2_83_inbus, chanx_1__0__out_66_ , mux_1level_tapbuf_size2_83_sram_blwl_out[83:83] , -mux_1level_tapbuf_size2_83_sram_blwl_outb[83:83] ); -//----- SRAM bits for MUX[83], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_83_ (mux_1level_tapbuf_size2_83_sram_blwl_out[83:83] ,mux_1level_tapbuf_size2_83_sram_blwl_out[83:83] ,mux_1level_tapbuf_size2_83_sram_blwl_outb[83:83] ,mux_1level_tapbuf_size2_83_configbus0[83:83], mux_1level_tapbuf_size2_83_configbus1[83:83] , mux_1level_tapbuf_size2_83_configbus0_b[83:83] ); -wire [0:1] mux_1level_tapbuf_size2_84_inbus; -assign mux_1level_tapbuf_size2_84_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_84_inbus[1] = chany_0__1__in_67_ ; -wire [84:84] mux_1level_tapbuf_size2_84_configbus0; -wire [84:84] mux_1level_tapbuf_size2_84_configbus1; -wire [84:84] mux_1level_tapbuf_size2_84_sram_blwl_out ; -wire [84:84] mux_1level_tapbuf_size2_84_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_84_configbus0[84:84] = sram_blwl_bl[84:84] ; -assign mux_1level_tapbuf_size2_84_configbus1[84:84] = sram_blwl_wl[84:84] ; -wire [84:84] mux_1level_tapbuf_size2_84_configbus0_b; -assign mux_1level_tapbuf_size2_84_configbus0_b[84:84] = sram_blwl_blb[84:84] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_84_ (mux_1level_tapbuf_size2_84_inbus, chanx_1__0__out_68_ , mux_1level_tapbuf_size2_84_sram_blwl_out[84:84] , -mux_1level_tapbuf_size2_84_sram_blwl_outb[84:84] ); -//----- SRAM bits for MUX[84], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_84_ (mux_1level_tapbuf_size2_84_sram_blwl_out[84:84] ,mux_1level_tapbuf_size2_84_sram_blwl_out[84:84] ,mux_1level_tapbuf_size2_84_sram_blwl_outb[84:84] ,mux_1level_tapbuf_size2_84_configbus0[84:84], mux_1level_tapbuf_size2_84_configbus1[84:84] , mux_1level_tapbuf_size2_84_configbus0_b[84:84] ); -wire [0:1] mux_1level_tapbuf_size2_85_inbus; -assign mux_1level_tapbuf_size2_85_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_85_inbus[1] = chany_0__1__in_69_ ; -wire [85:85] mux_1level_tapbuf_size2_85_configbus0; -wire [85:85] mux_1level_tapbuf_size2_85_configbus1; -wire [85:85] mux_1level_tapbuf_size2_85_sram_blwl_out ; -wire [85:85] mux_1level_tapbuf_size2_85_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_85_configbus0[85:85] = sram_blwl_bl[85:85] ; -assign mux_1level_tapbuf_size2_85_configbus1[85:85] = sram_blwl_wl[85:85] ; -wire [85:85] mux_1level_tapbuf_size2_85_configbus0_b; -assign mux_1level_tapbuf_size2_85_configbus0_b[85:85] = sram_blwl_blb[85:85] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_85_ (mux_1level_tapbuf_size2_85_inbus, chanx_1__0__out_70_ , mux_1level_tapbuf_size2_85_sram_blwl_out[85:85] , -mux_1level_tapbuf_size2_85_sram_blwl_outb[85:85] ); -//----- SRAM bits for MUX[85], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_85_ (mux_1level_tapbuf_size2_85_sram_blwl_out[85:85] ,mux_1level_tapbuf_size2_85_sram_blwl_out[85:85] ,mux_1level_tapbuf_size2_85_sram_blwl_outb[85:85] ,mux_1level_tapbuf_size2_85_configbus0[85:85], mux_1level_tapbuf_size2_85_configbus1[85:85] , mux_1level_tapbuf_size2_85_configbus0_b[85:85] ); -wire [0:1] mux_1level_tapbuf_size2_86_inbus; -assign mux_1level_tapbuf_size2_86_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_86_inbus[1] = chany_0__1__in_71_ ; -wire [86:86] mux_1level_tapbuf_size2_86_configbus0; -wire [86:86] mux_1level_tapbuf_size2_86_configbus1; -wire [86:86] mux_1level_tapbuf_size2_86_sram_blwl_out ; -wire [86:86] mux_1level_tapbuf_size2_86_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_86_configbus0[86:86] = sram_blwl_bl[86:86] ; -assign mux_1level_tapbuf_size2_86_configbus1[86:86] = sram_blwl_wl[86:86] ; -wire [86:86] mux_1level_tapbuf_size2_86_configbus0_b; -assign mux_1level_tapbuf_size2_86_configbus0_b[86:86] = sram_blwl_blb[86:86] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_86_ (mux_1level_tapbuf_size2_86_inbus, chanx_1__0__out_72_ , mux_1level_tapbuf_size2_86_sram_blwl_out[86:86] , -mux_1level_tapbuf_size2_86_sram_blwl_outb[86:86] ); -//----- SRAM bits for MUX[86], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_86_ (mux_1level_tapbuf_size2_86_sram_blwl_out[86:86] ,mux_1level_tapbuf_size2_86_sram_blwl_out[86:86] ,mux_1level_tapbuf_size2_86_sram_blwl_outb[86:86] ,mux_1level_tapbuf_size2_86_configbus0[86:86], mux_1level_tapbuf_size2_86_configbus1[86:86] , mux_1level_tapbuf_size2_86_configbus0_b[86:86] ); -wire [0:1] mux_1level_tapbuf_size2_87_inbus; -assign mux_1level_tapbuf_size2_87_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_87_inbus[1] = chany_0__1__in_73_ ; -wire [87:87] mux_1level_tapbuf_size2_87_configbus0; -wire [87:87] mux_1level_tapbuf_size2_87_configbus1; -wire [87:87] mux_1level_tapbuf_size2_87_sram_blwl_out ; -wire [87:87] mux_1level_tapbuf_size2_87_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_87_configbus0[87:87] = sram_blwl_bl[87:87] ; -assign mux_1level_tapbuf_size2_87_configbus1[87:87] = sram_blwl_wl[87:87] ; -wire [87:87] mux_1level_tapbuf_size2_87_configbus0_b; -assign mux_1level_tapbuf_size2_87_configbus0_b[87:87] = sram_blwl_blb[87:87] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_87_ (mux_1level_tapbuf_size2_87_inbus, chanx_1__0__out_74_ , mux_1level_tapbuf_size2_87_sram_blwl_out[87:87] , -mux_1level_tapbuf_size2_87_sram_blwl_outb[87:87] ); -//----- SRAM bits for MUX[87], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_87_ (mux_1level_tapbuf_size2_87_sram_blwl_out[87:87] ,mux_1level_tapbuf_size2_87_sram_blwl_out[87:87] ,mux_1level_tapbuf_size2_87_sram_blwl_outb[87:87] ,mux_1level_tapbuf_size2_87_configbus0[87:87], mux_1level_tapbuf_size2_87_configbus1[87:87] , mux_1level_tapbuf_size2_87_configbus0_b[87:87] ); -wire [0:1] mux_1level_tapbuf_size2_88_inbus; -assign mux_1level_tapbuf_size2_88_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_88_inbus[1] = chany_0__1__in_75_ ; -wire [88:88] mux_1level_tapbuf_size2_88_configbus0; -wire [88:88] mux_1level_tapbuf_size2_88_configbus1; -wire [88:88] mux_1level_tapbuf_size2_88_sram_blwl_out ; -wire [88:88] mux_1level_tapbuf_size2_88_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_88_configbus0[88:88] = sram_blwl_bl[88:88] ; -assign mux_1level_tapbuf_size2_88_configbus1[88:88] = sram_blwl_wl[88:88] ; -wire [88:88] mux_1level_tapbuf_size2_88_configbus0_b; -assign mux_1level_tapbuf_size2_88_configbus0_b[88:88] = sram_blwl_blb[88:88] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_88_ (mux_1level_tapbuf_size2_88_inbus, chanx_1__0__out_76_ , mux_1level_tapbuf_size2_88_sram_blwl_out[88:88] , -mux_1level_tapbuf_size2_88_sram_blwl_outb[88:88] ); -//----- SRAM bits for MUX[88], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_88_ (mux_1level_tapbuf_size2_88_sram_blwl_out[88:88] ,mux_1level_tapbuf_size2_88_sram_blwl_out[88:88] ,mux_1level_tapbuf_size2_88_sram_blwl_outb[88:88] ,mux_1level_tapbuf_size2_88_configbus0[88:88], mux_1level_tapbuf_size2_88_configbus1[88:88] , mux_1level_tapbuf_size2_88_configbus0_b[88:88] ); -wire [0:1] mux_1level_tapbuf_size2_89_inbus; -assign mux_1level_tapbuf_size2_89_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_89_inbus[1] = chany_0__1__in_77_ ; -wire [89:89] mux_1level_tapbuf_size2_89_configbus0; -wire [89:89] mux_1level_tapbuf_size2_89_configbus1; -wire [89:89] mux_1level_tapbuf_size2_89_sram_blwl_out ; -wire [89:89] mux_1level_tapbuf_size2_89_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_89_configbus0[89:89] = sram_blwl_bl[89:89] ; -assign mux_1level_tapbuf_size2_89_configbus1[89:89] = sram_blwl_wl[89:89] ; -wire [89:89] mux_1level_tapbuf_size2_89_configbus0_b; -assign mux_1level_tapbuf_size2_89_configbus0_b[89:89] = sram_blwl_blb[89:89] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_89_ (mux_1level_tapbuf_size2_89_inbus, chanx_1__0__out_78_ , mux_1level_tapbuf_size2_89_sram_blwl_out[89:89] , -mux_1level_tapbuf_size2_89_sram_blwl_outb[89:89] ); -//----- SRAM bits for MUX[89], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_89_ (mux_1level_tapbuf_size2_89_sram_blwl_out[89:89] ,mux_1level_tapbuf_size2_89_sram_blwl_out[89:89] ,mux_1level_tapbuf_size2_89_sram_blwl_outb[89:89] ,mux_1level_tapbuf_size2_89_configbus0[89:89], mux_1level_tapbuf_size2_89_configbus1[89:89] , mux_1level_tapbuf_size2_89_configbus0_b[89:89] ); -wire [0:1] mux_1level_tapbuf_size2_90_inbus; -assign mux_1level_tapbuf_size2_90_inbus[0] = grid_1__1__pin_0__2__42_; -assign mux_1level_tapbuf_size2_90_inbus[1] = chany_0__1__in_79_ ; -wire [90:90] mux_1level_tapbuf_size2_90_configbus0; -wire [90:90] mux_1level_tapbuf_size2_90_configbus1; -wire [90:90] mux_1level_tapbuf_size2_90_sram_blwl_out ; -wire [90:90] mux_1level_tapbuf_size2_90_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_90_configbus0[90:90] = sram_blwl_bl[90:90] ; -assign mux_1level_tapbuf_size2_90_configbus1[90:90] = sram_blwl_wl[90:90] ; -wire [90:90] mux_1level_tapbuf_size2_90_configbus0_b; -assign mux_1level_tapbuf_size2_90_configbus0_b[90:90] = sram_blwl_blb[90:90] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_90_ (mux_1level_tapbuf_size2_90_inbus, chanx_1__0__out_80_ , mux_1level_tapbuf_size2_90_sram_blwl_out[90:90] , -mux_1level_tapbuf_size2_90_sram_blwl_outb[90:90] ); -//----- SRAM bits for MUX[90], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_90_ (mux_1level_tapbuf_size2_90_sram_blwl_out[90:90] ,mux_1level_tapbuf_size2_90_sram_blwl_out[90:90] ,mux_1level_tapbuf_size2_90_sram_blwl_outb[90:90] ,mux_1level_tapbuf_size2_90_configbus0[90:90], mux_1level_tapbuf_size2_90_configbus1[90:90] , mux_1level_tapbuf_size2_90_configbus0_b[90:90] ); -wire [0:1] mux_1level_tapbuf_size2_91_inbus; -assign mux_1level_tapbuf_size2_91_inbus[0] = grid_1__1__pin_0__2__42_; -assign mux_1level_tapbuf_size2_91_inbus[1] = chany_0__1__in_81_ ; -wire [91:91] mux_1level_tapbuf_size2_91_configbus0; -wire [91:91] mux_1level_tapbuf_size2_91_configbus1; -wire [91:91] mux_1level_tapbuf_size2_91_sram_blwl_out ; -wire [91:91] mux_1level_tapbuf_size2_91_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_91_configbus0[91:91] = sram_blwl_bl[91:91] ; -assign mux_1level_tapbuf_size2_91_configbus1[91:91] = sram_blwl_wl[91:91] ; -wire [91:91] mux_1level_tapbuf_size2_91_configbus0_b; -assign mux_1level_tapbuf_size2_91_configbus0_b[91:91] = sram_blwl_blb[91:91] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_91_ (mux_1level_tapbuf_size2_91_inbus, chanx_1__0__out_82_ , mux_1level_tapbuf_size2_91_sram_blwl_out[91:91] , -mux_1level_tapbuf_size2_91_sram_blwl_outb[91:91] ); -//----- SRAM bits for MUX[91], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_91_ (mux_1level_tapbuf_size2_91_sram_blwl_out[91:91] ,mux_1level_tapbuf_size2_91_sram_blwl_out[91:91] ,mux_1level_tapbuf_size2_91_sram_blwl_outb[91:91] ,mux_1level_tapbuf_size2_91_configbus0[91:91], mux_1level_tapbuf_size2_91_configbus1[91:91] , mux_1level_tapbuf_size2_91_configbus0_b[91:91] ); -wire [0:1] mux_1level_tapbuf_size2_92_inbus; -assign mux_1level_tapbuf_size2_92_inbus[0] = grid_1__1__pin_0__2__42_; -assign mux_1level_tapbuf_size2_92_inbus[1] = chany_0__1__in_83_ ; -wire [92:92] mux_1level_tapbuf_size2_92_configbus0; -wire [92:92] mux_1level_tapbuf_size2_92_configbus1; -wire [92:92] mux_1level_tapbuf_size2_92_sram_blwl_out ; -wire [92:92] mux_1level_tapbuf_size2_92_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_92_configbus0[92:92] = sram_blwl_bl[92:92] ; -assign mux_1level_tapbuf_size2_92_configbus1[92:92] = sram_blwl_wl[92:92] ; -wire [92:92] mux_1level_tapbuf_size2_92_configbus0_b; -assign mux_1level_tapbuf_size2_92_configbus0_b[92:92] = sram_blwl_blb[92:92] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_92_ (mux_1level_tapbuf_size2_92_inbus, chanx_1__0__out_84_ , mux_1level_tapbuf_size2_92_sram_blwl_out[92:92] , -mux_1level_tapbuf_size2_92_sram_blwl_outb[92:92] ); -//----- SRAM bits for MUX[92], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_92_ (mux_1level_tapbuf_size2_92_sram_blwl_out[92:92] ,mux_1level_tapbuf_size2_92_sram_blwl_out[92:92] ,mux_1level_tapbuf_size2_92_sram_blwl_outb[92:92] ,mux_1level_tapbuf_size2_92_configbus0[92:92], mux_1level_tapbuf_size2_92_configbus1[92:92] , mux_1level_tapbuf_size2_92_configbus0_b[92:92] ); -wire [0:1] mux_1level_tapbuf_size2_93_inbus; -assign mux_1level_tapbuf_size2_93_inbus[0] = grid_1__1__pin_0__2__42_; -assign mux_1level_tapbuf_size2_93_inbus[1] = chany_0__1__in_85_ ; -wire [93:93] mux_1level_tapbuf_size2_93_configbus0; -wire [93:93] mux_1level_tapbuf_size2_93_configbus1; -wire [93:93] mux_1level_tapbuf_size2_93_sram_blwl_out ; -wire [93:93] mux_1level_tapbuf_size2_93_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_93_configbus0[93:93] = sram_blwl_bl[93:93] ; -assign mux_1level_tapbuf_size2_93_configbus1[93:93] = sram_blwl_wl[93:93] ; -wire [93:93] mux_1level_tapbuf_size2_93_configbus0_b; -assign mux_1level_tapbuf_size2_93_configbus0_b[93:93] = sram_blwl_blb[93:93] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_93_ (mux_1level_tapbuf_size2_93_inbus, chanx_1__0__out_86_ , mux_1level_tapbuf_size2_93_sram_blwl_out[93:93] , -mux_1level_tapbuf_size2_93_sram_blwl_outb[93:93] ); -//----- SRAM bits for MUX[93], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_93_ (mux_1level_tapbuf_size2_93_sram_blwl_out[93:93] ,mux_1level_tapbuf_size2_93_sram_blwl_out[93:93] ,mux_1level_tapbuf_size2_93_sram_blwl_outb[93:93] ,mux_1level_tapbuf_size2_93_configbus0[93:93], mux_1level_tapbuf_size2_93_configbus1[93:93] , mux_1level_tapbuf_size2_93_configbus0_b[93:93] ); -wire [0:1] mux_1level_tapbuf_size2_94_inbus; -assign mux_1level_tapbuf_size2_94_inbus[0] = grid_1__1__pin_0__2__42_; -assign mux_1level_tapbuf_size2_94_inbus[1] = chany_0__1__in_87_ ; -wire [94:94] mux_1level_tapbuf_size2_94_configbus0; -wire [94:94] mux_1level_tapbuf_size2_94_configbus1; -wire [94:94] mux_1level_tapbuf_size2_94_sram_blwl_out ; -wire [94:94] mux_1level_tapbuf_size2_94_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_94_configbus0[94:94] = sram_blwl_bl[94:94] ; -assign mux_1level_tapbuf_size2_94_configbus1[94:94] = sram_blwl_wl[94:94] ; -wire [94:94] mux_1level_tapbuf_size2_94_configbus0_b; -assign mux_1level_tapbuf_size2_94_configbus0_b[94:94] = sram_blwl_blb[94:94] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_94_ (mux_1level_tapbuf_size2_94_inbus, chanx_1__0__out_88_ , mux_1level_tapbuf_size2_94_sram_blwl_out[94:94] , -mux_1level_tapbuf_size2_94_sram_blwl_outb[94:94] ); -//----- SRAM bits for MUX[94], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_94_ (mux_1level_tapbuf_size2_94_sram_blwl_out[94:94] ,mux_1level_tapbuf_size2_94_sram_blwl_out[94:94] ,mux_1level_tapbuf_size2_94_sram_blwl_outb[94:94] ,mux_1level_tapbuf_size2_94_configbus0[94:94], mux_1level_tapbuf_size2_94_configbus1[94:94] , mux_1level_tapbuf_size2_94_configbus0_b[94:94] ); -wire [0:1] mux_1level_tapbuf_size2_95_inbus; -assign mux_1level_tapbuf_size2_95_inbus[0] = grid_1__1__pin_0__2__46_; -assign mux_1level_tapbuf_size2_95_inbus[1] = chany_0__1__in_89_ ; -wire [95:95] mux_1level_tapbuf_size2_95_configbus0; -wire [95:95] mux_1level_tapbuf_size2_95_configbus1; -wire [95:95] mux_1level_tapbuf_size2_95_sram_blwl_out ; -wire [95:95] mux_1level_tapbuf_size2_95_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_95_configbus0[95:95] = sram_blwl_bl[95:95] ; -assign mux_1level_tapbuf_size2_95_configbus1[95:95] = sram_blwl_wl[95:95] ; -wire [95:95] mux_1level_tapbuf_size2_95_configbus0_b; -assign mux_1level_tapbuf_size2_95_configbus0_b[95:95] = sram_blwl_blb[95:95] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_95_ (mux_1level_tapbuf_size2_95_inbus, chanx_1__0__out_90_ , mux_1level_tapbuf_size2_95_sram_blwl_out[95:95] , -mux_1level_tapbuf_size2_95_sram_blwl_outb[95:95] ); -//----- SRAM bits for MUX[95], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_95_ (mux_1level_tapbuf_size2_95_sram_blwl_out[95:95] ,mux_1level_tapbuf_size2_95_sram_blwl_out[95:95] ,mux_1level_tapbuf_size2_95_sram_blwl_outb[95:95] ,mux_1level_tapbuf_size2_95_configbus0[95:95], mux_1level_tapbuf_size2_95_configbus1[95:95] , mux_1level_tapbuf_size2_95_configbus0_b[95:95] ); -wire [0:1] mux_1level_tapbuf_size2_96_inbus; -assign mux_1level_tapbuf_size2_96_inbus[0] = grid_1__1__pin_0__2__46_; -assign mux_1level_tapbuf_size2_96_inbus[1] = chany_0__1__in_91_ ; -wire [96:96] mux_1level_tapbuf_size2_96_configbus0; -wire [96:96] mux_1level_tapbuf_size2_96_configbus1; -wire [96:96] mux_1level_tapbuf_size2_96_sram_blwl_out ; -wire [96:96] mux_1level_tapbuf_size2_96_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_96_configbus0[96:96] = sram_blwl_bl[96:96] ; -assign mux_1level_tapbuf_size2_96_configbus1[96:96] = sram_blwl_wl[96:96] ; -wire [96:96] mux_1level_tapbuf_size2_96_configbus0_b; -assign mux_1level_tapbuf_size2_96_configbus0_b[96:96] = sram_blwl_blb[96:96] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_96_ (mux_1level_tapbuf_size2_96_inbus, chanx_1__0__out_92_ , mux_1level_tapbuf_size2_96_sram_blwl_out[96:96] , -mux_1level_tapbuf_size2_96_sram_blwl_outb[96:96] ); -//----- SRAM bits for MUX[96], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_96_ (mux_1level_tapbuf_size2_96_sram_blwl_out[96:96] ,mux_1level_tapbuf_size2_96_sram_blwl_out[96:96] ,mux_1level_tapbuf_size2_96_sram_blwl_outb[96:96] ,mux_1level_tapbuf_size2_96_configbus0[96:96], mux_1level_tapbuf_size2_96_configbus1[96:96] , mux_1level_tapbuf_size2_96_configbus0_b[96:96] ); -wire [0:1] mux_1level_tapbuf_size2_97_inbus; -assign mux_1level_tapbuf_size2_97_inbus[0] = grid_1__1__pin_0__2__46_; -assign mux_1level_tapbuf_size2_97_inbus[1] = chany_0__1__in_93_ ; -wire [97:97] mux_1level_tapbuf_size2_97_configbus0; -wire [97:97] mux_1level_tapbuf_size2_97_configbus1; -wire [97:97] mux_1level_tapbuf_size2_97_sram_blwl_out ; -wire [97:97] mux_1level_tapbuf_size2_97_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_97_configbus0[97:97] = sram_blwl_bl[97:97] ; -assign mux_1level_tapbuf_size2_97_configbus1[97:97] = sram_blwl_wl[97:97] ; -wire [97:97] mux_1level_tapbuf_size2_97_configbus0_b; -assign mux_1level_tapbuf_size2_97_configbus0_b[97:97] = sram_blwl_blb[97:97] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_97_ (mux_1level_tapbuf_size2_97_inbus, chanx_1__0__out_94_ , mux_1level_tapbuf_size2_97_sram_blwl_out[97:97] , -mux_1level_tapbuf_size2_97_sram_blwl_outb[97:97] ); -//----- SRAM bits for MUX[97], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_97_ (mux_1level_tapbuf_size2_97_sram_blwl_out[97:97] ,mux_1level_tapbuf_size2_97_sram_blwl_out[97:97] ,mux_1level_tapbuf_size2_97_sram_blwl_outb[97:97] ,mux_1level_tapbuf_size2_97_configbus0[97:97], mux_1level_tapbuf_size2_97_configbus1[97:97] , mux_1level_tapbuf_size2_97_configbus0_b[97:97] ); -wire [0:1] mux_1level_tapbuf_size2_98_inbus; -assign mux_1level_tapbuf_size2_98_inbus[0] = grid_1__1__pin_0__2__46_; -assign mux_1level_tapbuf_size2_98_inbus[1] = chany_0__1__in_95_ ; -wire [98:98] mux_1level_tapbuf_size2_98_configbus0; -wire [98:98] mux_1level_tapbuf_size2_98_configbus1; -wire [98:98] mux_1level_tapbuf_size2_98_sram_blwl_out ; -wire [98:98] mux_1level_tapbuf_size2_98_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_98_configbus0[98:98] = sram_blwl_bl[98:98] ; -assign mux_1level_tapbuf_size2_98_configbus1[98:98] = sram_blwl_wl[98:98] ; -wire [98:98] mux_1level_tapbuf_size2_98_configbus0_b; -assign mux_1level_tapbuf_size2_98_configbus0_b[98:98] = sram_blwl_blb[98:98] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_98_ (mux_1level_tapbuf_size2_98_inbus, chanx_1__0__out_96_ , mux_1level_tapbuf_size2_98_sram_blwl_out[98:98] , -mux_1level_tapbuf_size2_98_sram_blwl_outb[98:98] ); -//----- SRAM bits for MUX[98], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_98_ (mux_1level_tapbuf_size2_98_sram_blwl_out[98:98] ,mux_1level_tapbuf_size2_98_sram_blwl_out[98:98] ,mux_1level_tapbuf_size2_98_sram_blwl_outb[98:98] ,mux_1level_tapbuf_size2_98_configbus0[98:98], mux_1level_tapbuf_size2_98_configbus1[98:98] , mux_1level_tapbuf_size2_98_configbus0_b[98:98] ); -wire [0:1] mux_1level_tapbuf_size2_99_inbus; -assign mux_1level_tapbuf_size2_99_inbus[0] = grid_1__1__pin_0__2__46_; -assign mux_1level_tapbuf_size2_99_inbus[1] = chany_0__1__in_97_ ; -wire [99:99] mux_1level_tapbuf_size2_99_configbus0; -wire [99:99] mux_1level_tapbuf_size2_99_configbus1; -wire [99:99] mux_1level_tapbuf_size2_99_sram_blwl_out ; -wire [99:99] mux_1level_tapbuf_size2_99_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_99_configbus0[99:99] = sram_blwl_bl[99:99] ; -assign mux_1level_tapbuf_size2_99_configbus1[99:99] = sram_blwl_wl[99:99] ; -wire [99:99] mux_1level_tapbuf_size2_99_configbus0_b; -assign mux_1level_tapbuf_size2_99_configbus0_b[99:99] = sram_blwl_blb[99:99] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_99_ (mux_1level_tapbuf_size2_99_inbus, chanx_1__0__out_98_ , mux_1level_tapbuf_size2_99_sram_blwl_out[99:99] , -mux_1level_tapbuf_size2_99_sram_blwl_outb[99:99] ); -//----- SRAM bits for MUX[99], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_99_ (mux_1level_tapbuf_size2_99_sram_blwl_out[99:99] ,mux_1level_tapbuf_size2_99_sram_blwl_out[99:99] ,mux_1level_tapbuf_size2_99_sram_blwl_outb[99:99] ,mux_1level_tapbuf_size2_99_configbus0[99:99], mux_1level_tapbuf_size2_99_configbus1[99:99] , mux_1level_tapbuf_size2_99_configbus0_b[99:99] ); -//----- bottom side Multiplexers ----- -//----- left side Multiplexers ----- -endmodule -//----- END Verilog Module of Switch Box[0][0] ----- - diff --git a/examples/verilog_test_example_2/routing/sb_0_1.v b/examples/verilog_test_example_2/routing/sb_0_1.v deleted file mode 100644 index 344c68c18..000000000 --- a/examples/verilog_test_example_2/routing/sb_0_1.v +++ /dev/null @@ -1,1971 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Switch Block [0][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Switch Box[0][1] ----- -module sb_0__1_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -//----- Inputs/outputs of top side ----- -//----- Inputs/outputs of right side ----- - output chanx_1__1__out_0_, - input chanx_1__1__in_1_, - output chanx_1__1__out_2_, - input chanx_1__1__in_3_, - output chanx_1__1__out_4_, - input chanx_1__1__in_5_, - output chanx_1__1__out_6_, - input chanx_1__1__in_7_, - output chanx_1__1__out_8_, - input chanx_1__1__in_9_, - output chanx_1__1__out_10_, - input chanx_1__1__in_11_, - output chanx_1__1__out_12_, - input chanx_1__1__in_13_, - output chanx_1__1__out_14_, - input chanx_1__1__in_15_, - output chanx_1__1__out_16_, - input chanx_1__1__in_17_, - output chanx_1__1__out_18_, - input chanx_1__1__in_19_, - output chanx_1__1__out_20_, - input chanx_1__1__in_21_, - output chanx_1__1__out_22_, - input chanx_1__1__in_23_, - output chanx_1__1__out_24_, - input chanx_1__1__in_25_, - output chanx_1__1__out_26_, - input chanx_1__1__in_27_, - output chanx_1__1__out_28_, - input chanx_1__1__in_29_, - output chanx_1__1__out_30_, - input chanx_1__1__in_31_, - output chanx_1__1__out_32_, - input chanx_1__1__in_33_, - output chanx_1__1__out_34_, - input chanx_1__1__in_35_, - output chanx_1__1__out_36_, - input chanx_1__1__in_37_, - output chanx_1__1__out_38_, - input chanx_1__1__in_39_, - output chanx_1__1__out_40_, - input chanx_1__1__in_41_, - output chanx_1__1__out_42_, - input chanx_1__1__in_43_, - output chanx_1__1__out_44_, - input chanx_1__1__in_45_, - output chanx_1__1__out_46_, - input chanx_1__1__in_47_, - output chanx_1__1__out_48_, - input chanx_1__1__in_49_, - output chanx_1__1__out_50_, - input chanx_1__1__in_51_, - output chanx_1__1__out_52_, - input chanx_1__1__in_53_, - output chanx_1__1__out_54_, - input chanx_1__1__in_55_, - output chanx_1__1__out_56_, - input chanx_1__1__in_57_, - output chanx_1__1__out_58_, - input chanx_1__1__in_59_, - output chanx_1__1__out_60_, - input chanx_1__1__in_61_, - output chanx_1__1__out_62_, - input chanx_1__1__in_63_, - output chanx_1__1__out_64_, - input chanx_1__1__in_65_, - output chanx_1__1__out_66_, - input chanx_1__1__in_67_, - output chanx_1__1__out_68_, - input chanx_1__1__in_69_, - output chanx_1__1__out_70_, - input chanx_1__1__in_71_, - output chanx_1__1__out_72_, - input chanx_1__1__in_73_, - output chanx_1__1__out_74_, - input chanx_1__1__in_75_, - output chanx_1__1__out_76_, - input chanx_1__1__in_77_, - output chanx_1__1__out_78_, - input chanx_1__1__in_79_, - output chanx_1__1__out_80_, - input chanx_1__1__in_81_, - output chanx_1__1__out_82_, - input chanx_1__1__in_83_, - output chanx_1__1__out_84_, - input chanx_1__1__in_85_, - output chanx_1__1__out_86_, - input chanx_1__1__in_87_, - output chanx_1__1__out_88_, - input chanx_1__1__in_89_, - output chanx_1__1__out_90_, - input chanx_1__1__in_91_, - output chanx_1__1__out_92_, - input chanx_1__1__in_93_, - output chanx_1__1__out_94_, - input chanx_1__1__in_95_, - output chanx_1__1__out_96_, - input chanx_1__1__in_97_, - output chanx_1__1__out_98_, - input chanx_1__1__in_99_, -input grid_1__2__pin_0__2__1_, -input grid_1__2__pin_0__2__3_, -input grid_1__2__pin_0__2__5_, -input grid_1__2__pin_0__2__7_, -input grid_1__2__pin_0__2__9_, -input grid_1__2__pin_0__2__11_, -input grid_1__2__pin_0__2__13_, -input grid_1__2__pin_0__2__15_, -input grid_1__1__pin_0__0__40_, -input grid_1__1__pin_0__0__44_, -input grid_1__1__pin_0__0__48_, -//----- Inputs/outputs of bottom side ----- - input chany_0__1__in_0_, - output chany_0__1__out_1_, - input chany_0__1__in_2_, - output chany_0__1__out_3_, - input chany_0__1__in_4_, - output chany_0__1__out_5_, - input chany_0__1__in_6_, - output chany_0__1__out_7_, - input chany_0__1__in_8_, - output chany_0__1__out_9_, - input chany_0__1__in_10_, - output chany_0__1__out_11_, - input chany_0__1__in_12_, - output chany_0__1__out_13_, - input chany_0__1__in_14_, - output chany_0__1__out_15_, - input chany_0__1__in_16_, - output chany_0__1__out_17_, - input chany_0__1__in_18_, - output chany_0__1__out_19_, - input chany_0__1__in_20_, - output chany_0__1__out_21_, - input chany_0__1__in_22_, - output chany_0__1__out_23_, - input chany_0__1__in_24_, - output chany_0__1__out_25_, - input chany_0__1__in_26_, - output chany_0__1__out_27_, - input chany_0__1__in_28_, - output chany_0__1__out_29_, - input chany_0__1__in_30_, - output chany_0__1__out_31_, - input chany_0__1__in_32_, - output chany_0__1__out_33_, - input chany_0__1__in_34_, - output chany_0__1__out_35_, - input chany_0__1__in_36_, - output chany_0__1__out_37_, - input chany_0__1__in_38_, - output chany_0__1__out_39_, - input chany_0__1__in_40_, - output chany_0__1__out_41_, - input chany_0__1__in_42_, - output chany_0__1__out_43_, - input chany_0__1__in_44_, - output chany_0__1__out_45_, - input chany_0__1__in_46_, - output chany_0__1__out_47_, - input chany_0__1__in_48_, - output chany_0__1__out_49_, - input chany_0__1__in_50_, - output chany_0__1__out_51_, - input chany_0__1__in_52_, - output chany_0__1__out_53_, - input chany_0__1__in_54_, - output chany_0__1__out_55_, - input chany_0__1__in_56_, - output chany_0__1__out_57_, - input chany_0__1__in_58_, - output chany_0__1__out_59_, - input chany_0__1__in_60_, - output chany_0__1__out_61_, - input chany_0__1__in_62_, - output chany_0__1__out_63_, - input chany_0__1__in_64_, - output chany_0__1__out_65_, - input chany_0__1__in_66_, - output chany_0__1__out_67_, - input chany_0__1__in_68_, - output chany_0__1__out_69_, - input chany_0__1__in_70_, - output chany_0__1__out_71_, - input chany_0__1__in_72_, - output chany_0__1__out_73_, - input chany_0__1__in_74_, - output chany_0__1__out_75_, - input chany_0__1__in_76_, - output chany_0__1__out_77_, - input chany_0__1__in_78_, - output chany_0__1__out_79_, - input chany_0__1__in_80_, - output chany_0__1__out_81_, - input chany_0__1__in_82_, - output chany_0__1__out_83_, - input chany_0__1__in_84_, - output chany_0__1__out_85_, - input chany_0__1__in_86_, - output chany_0__1__out_87_, - input chany_0__1__in_88_, - output chany_0__1__out_89_, - input chany_0__1__in_90_, - output chany_0__1__out_91_, - input chany_0__1__in_92_, - output chany_0__1__out_93_, - input chany_0__1__in_94_, - output chany_0__1__out_95_, - input chany_0__1__in_96_, - output chany_0__1__out_97_, - input chany_0__1__in_98_, - output chany_0__1__out_99_, -input grid_1__1__pin_0__3__43_, -input grid_1__1__pin_0__3__47_, -input grid_0__1__pin_0__1__1_, -input grid_0__1__pin_0__1__3_, -input grid_0__1__pin_0__1__5_, -input grid_0__1__pin_0__1__7_, -input grid_0__1__pin_0__1__9_, -input grid_0__1__pin_0__1__11_, -input grid_0__1__pin_0__1__13_, -input grid_0__1__pin_0__1__15_, -//----- Inputs/outputs of left side ----- -input [100:209] sram_blwl_bl , -input [100:209] sram_blwl_wl , -input [100:209] sram_blwl_blb ); -//----- top side Multiplexers ----- -//----- right side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_100_inbus; -assign mux_1level_tapbuf_size3_100_inbus[0] = grid_1__1__pin_0__0__40_; -assign mux_1level_tapbuf_size3_100_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_100_inbus[2] = chany_0__1__in_96_ ; -wire [100:102] mux_1level_tapbuf_size3_100_configbus0; -wire [100:102] mux_1level_tapbuf_size3_100_configbus1; -wire [100:102] mux_1level_tapbuf_size3_100_sram_blwl_out ; -wire [100:102] mux_1level_tapbuf_size3_100_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_100_configbus0[100:102] = sram_blwl_bl[100:102] ; -assign mux_1level_tapbuf_size3_100_configbus1[100:102] = sram_blwl_wl[100:102] ; -wire [100:102] mux_1level_tapbuf_size3_100_configbus0_b; -assign mux_1level_tapbuf_size3_100_configbus0_b[100:102] = sram_blwl_blb[100:102] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_100_ (mux_1level_tapbuf_size3_100_inbus, chanx_1__1__out_0_ , mux_1level_tapbuf_size3_100_sram_blwl_out[100:102] , -mux_1level_tapbuf_size3_100_sram_blwl_outb[100:102] ); -//----- SRAM bits for MUX[100], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_100_ (mux_1level_tapbuf_size3_100_sram_blwl_out[100:100] ,mux_1level_tapbuf_size3_100_sram_blwl_out[100:100] ,mux_1level_tapbuf_size3_100_sram_blwl_outb[100:100] ,mux_1level_tapbuf_size3_100_configbus0[100:100], mux_1level_tapbuf_size3_100_configbus1[100:100] , mux_1level_tapbuf_size3_100_configbus0_b[100:100] ); -sram6T_blwl sram_blwl_101_ (mux_1level_tapbuf_size3_100_sram_blwl_out[101:101] ,mux_1level_tapbuf_size3_100_sram_blwl_out[101:101] ,mux_1level_tapbuf_size3_100_sram_blwl_outb[101:101] ,mux_1level_tapbuf_size3_100_configbus0[101:101], mux_1level_tapbuf_size3_100_configbus1[101:101] , mux_1level_tapbuf_size3_100_configbus0_b[101:101] ); -sram6T_blwl sram_blwl_102_ (mux_1level_tapbuf_size3_100_sram_blwl_out[102:102] ,mux_1level_tapbuf_size3_100_sram_blwl_out[102:102] ,mux_1level_tapbuf_size3_100_sram_blwl_outb[102:102] ,mux_1level_tapbuf_size3_100_configbus0[102:102], mux_1level_tapbuf_size3_100_configbus1[102:102] , mux_1level_tapbuf_size3_100_configbus0_b[102:102] ); -wire [0:2] mux_1level_tapbuf_size3_101_inbus; -assign mux_1level_tapbuf_size3_101_inbus[0] = grid_1__1__pin_0__0__40_; -assign mux_1level_tapbuf_size3_101_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_101_inbus[2] = chany_0__1__in_94_ ; -wire [103:105] mux_1level_tapbuf_size3_101_configbus0; -wire [103:105] mux_1level_tapbuf_size3_101_configbus1; -wire [103:105] mux_1level_tapbuf_size3_101_sram_blwl_out ; -wire [103:105] mux_1level_tapbuf_size3_101_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_101_configbus0[103:105] = sram_blwl_bl[103:105] ; -assign mux_1level_tapbuf_size3_101_configbus1[103:105] = sram_blwl_wl[103:105] ; -wire [103:105] mux_1level_tapbuf_size3_101_configbus0_b; -assign mux_1level_tapbuf_size3_101_configbus0_b[103:105] = sram_blwl_blb[103:105] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_101_ (mux_1level_tapbuf_size3_101_inbus, chanx_1__1__out_2_ , mux_1level_tapbuf_size3_101_sram_blwl_out[103:105] , -mux_1level_tapbuf_size3_101_sram_blwl_outb[103:105] ); -//----- SRAM bits for MUX[101], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_103_ (mux_1level_tapbuf_size3_101_sram_blwl_out[103:103] ,mux_1level_tapbuf_size3_101_sram_blwl_out[103:103] ,mux_1level_tapbuf_size3_101_sram_blwl_outb[103:103] ,mux_1level_tapbuf_size3_101_configbus0[103:103], mux_1level_tapbuf_size3_101_configbus1[103:103] , mux_1level_tapbuf_size3_101_configbus0_b[103:103] ); -sram6T_blwl sram_blwl_104_ (mux_1level_tapbuf_size3_101_sram_blwl_out[104:104] ,mux_1level_tapbuf_size3_101_sram_blwl_out[104:104] ,mux_1level_tapbuf_size3_101_sram_blwl_outb[104:104] ,mux_1level_tapbuf_size3_101_configbus0[104:104], mux_1level_tapbuf_size3_101_configbus1[104:104] , mux_1level_tapbuf_size3_101_configbus0_b[104:104] ); -sram6T_blwl sram_blwl_105_ (mux_1level_tapbuf_size3_101_sram_blwl_out[105:105] ,mux_1level_tapbuf_size3_101_sram_blwl_out[105:105] ,mux_1level_tapbuf_size3_101_sram_blwl_outb[105:105] ,mux_1level_tapbuf_size3_101_configbus0[105:105], mux_1level_tapbuf_size3_101_configbus1[105:105] , mux_1level_tapbuf_size3_101_configbus0_b[105:105] ); -wire [0:2] mux_1level_tapbuf_size3_102_inbus; -assign mux_1level_tapbuf_size3_102_inbus[0] = grid_1__1__pin_0__0__40_; -assign mux_1level_tapbuf_size3_102_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_102_inbus[2] = chany_0__1__in_92_ ; -wire [106:108] mux_1level_tapbuf_size3_102_configbus0; -wire [106:108] mux_1level_tapbuf_size3_102_configbus1; -wire [106:108] mux_1level_tapbuf_size3_102_sram_blwl_out ; -wire [106:108] mux_1level_tapbuf_size3_102_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_102_configbus0[106:108] = sram_blwl_bl[106:108] ; -assign mux_1level_tapbuf_size3_102_configbus1[106:108] = sram_blwl_wl[106:108] ; -wire [106:108] mux_1level_tapbuf_size3_102_configbus0_b; -assign mux_1level_tapbuf_size3_102_configbus0_b[106:108] = sram_blwl_blb[106:108] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_102_ (mux_1level_tapbuf_size3_102_inbus, chanx_1__1__out_4_ , mux_1level_tapbuf_size3_102_sram_blwl_out[106:108] , -mux_1level_tapbuf_size3_102_sram_blwl_outb[106:108] ); -//----- SRAM bits for MUX[102], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_106_ (mux_1level_tapbuf_size3_102_sram_blwl_out[106:106] ,mux_1level_tapbuf_size3_102_sram_blwl_out[106:106] ,mux_1level_tapbuf_size3_102_sram_blwl_outb[106:106] ,mux_1level_tapbuf_size3_102_configbus0[106:106], mux_1level_tapbuf_size3_102_configbus1[106:106] , mux_1level_tapbuf_size3_102_configbus0_b[106:106] ); -sram6T_blwl sram_blwl_107_ (mux_1level_tapbuf_size3_102_sram_blwl_out[107:107] ,mux_1level_tapbuf_size3_102_sram_blwl_out[107:107] ,mux_1level_tapbuf_size3_102_sram_blwl_outb[107:107] ,mux_1level_tapbuf_size3_102_configbus0[107:107], mux_1level_tapbuf_size3_102_configbus1[107:107] , mux_1level_tapbuf_size3_102_configbus0_b[107:107] ); -sram6T_blwl sram_blwl_108_ (mux_1level_tapbuf_size3_102_sram_blwl_out[108:108] ,mux_1level_tapbuf_size3_102_sram_blwl_out[108:108] ,mux_1level_tapbuf_size3_102_sram_blwl_outb[108:108] ,mux_1level_tapbuf_size3_102_configbus0[108:108], mux_1level_tapbuf_size3_102_configbus1[108:108] , mux_1level_tapbuf_size3_102_configbus0_b[108:108] ); -wire [0:2] mux_1level_tapbuf_size3_103_inbus; -assign mux_1level_tapbuf_size3_103_inbus[0] = grid_1__1__pin_0__0__40_; -assign mux_1level_tapbuf_size3_103_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_103_inbus[2] = chany_0__1__in_90_ ; -wire [109:111] mux_1level_tapbuf_size3_103_configbus0; -wire [109:111] mux_1level_tapbuf_size3_103_configbus1; -wire [109:111] mux_1level_tapbuf_size3_103_sram_blwl_out ; -wire [109:111] mux_1level_tapbuf_size3_103_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_103_configbus0[109:111] = sram_blwl_bl[109:111] ; -assign mux_1level_tapbuf_size3_103_configbus1[109:111] = sram_blwl_wl[109:111] ; -wire [109:111] mux_1level_tapbuf_size3_103_configbus0_b; -assign mux_1level_tapbuf_size3_103_configbus0_b[109:111] = sram_blwl_blb[109:111] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_103_ (mux_1level_tapbuf_size3_103_inbus, chanx_1__1__out_6_ , mux_1level_tapbuf_size3_103_sram_blwl_out[109:111] , -mux_1level_tapbuf_size3_103_sram_blwl_outb[109:111] ); -//----- SRAM bits for MUX[103], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_109_ (mux_1level_tapbuf_size3_103_sram_blwl_out[109:109] ,mux_1level_tapbuf_size3_103_sram_blwl_out[109:109] ,mux_1level_tapbuf_size3_103_sram_blwl_outb[109:109] ,mux_1level_tapbuf_size3_103_configbus0[109:109], mux_1level_tapbuf_size3_103_configbus1[109:109] , mux_1level_tapbuf_size3_103_configbus0_b[109:109] ); -sram6T_blwl sram_blwl_110_ (mux_1level_tapbuf_size3_103_sram_blwl_out[110:110] ,mux_1level_tapbuf_size3_103_sram_blwl_out[110:110] ,mux_1level_tapbuf_size3_103_sram_blwl_outb[110:110] ,mux_1level_tapbuf_size3_103_configbus0[110:110], mux_1level_tapbuf_size3_103_configbus1[110:110] , mux_1level_tapbuf_size3_103_configbus0_b[110:110] ); -sram6T_blwl sram_blwl_111_ (mux_1level_tapbuf_size3_103_sram_blwl_out[111:111] ,mux_1level_tapbuf_size3_103_sram_blwl_out[111:111] ,mux_1level_tapbuf_size3_103_sram_blwl_outb[111:111] ,mux_1level_tapbuf_size3_103_configbus0[111:111], mux_1level_tapbuf_size3_103_configbus1[111:111] , mux_1level_tapbuf_size3_103_configbus0_b[111:111] ); -wire [0:2] mux_1level_tapbuf_size3_104_inbus; -assign mux_1level_tapbuf_size3_104_inbus[0] = grid_1__1__pin_0__0__40_; -assign mux_1level_tapbuf_size3_104_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_104_inbus[2] = chany_0__1__in_88_ ; -wire [112:114] mux_1level_tapbuf_size3_104_configbus0; -wire [112:114] mux_1level_tapbuf_size3_104_configbus1; -wire [112:114] mux_1level_tapbuf_size3_104_sram_blwl_out ; -wire [112:114] mux_1level_tapbuf_size3_104_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_104_configbus0[112:114] = sram_blwl_bl[112:114] ; -assign mux_1level_tapbuf_size3_104_configbus1[112:114] = sram_blwl_wl[112:114] ; -wire [112:114] mux_1level_tapbuf_size3_104_configbus0_b; -assign mux_1level_tapbuf_size3_104_configbus0_b[112:114] = sram_blwl_blb[112:114] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_104_ (mux_1level_tapbuf_size3_104_inbus, chanx_1__1__out_8_ , mux_1level_tapbuf_size3_104_sram_blwl_out[112:114] , -mux_1level_tapbuf_size3_104_sram_blwl_outb[112:114] ); -//----- SRAM bits for MUX[104], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_112_ (mux_1level_tapbuf_size3_104_sram_blwl_out[112:112] ,mux_1level_tapbuf_size3_104_sram_blwl_out[112:112] ,mux_1level_tapbuf_size3_104_sram_blwl_outb[112:112] ,mux_1level_tapbuf_size3_104_configbus0[112:112], mux_1level_tapbuf_size3_104_configbus1[112:112] , mux_1level_tapbuf_size3_104_configbus0_b[112:112] ); -sram6T_blwl sram_blwl_113_ (mux_1level_tapbuf_size3_104_sram_blwl_out[113:113] ,mux_1level_tapbuf_size3_104_sram_blwl_out[113:113] ,mux_1level_tapbuf_size3_104_sram_blwl_outb[113:113] ,mux_1level_tapbuf_size3_104_configbus0[113:113], mux_1level_tapbuf_size3_104_configbus1[113:113] , mux_1level_tapbuf_size3_104_configbus0_b[113:113] ); -sram6T_blwl sram_blwl_114_ (mux_1level_tapbuf_size3_104_sram_blwl_out[114:114] ,mux_1level_tapbuf_size3_104_sram_blwl_out[114:114] ,mux_1level_tapbuf_size3_104_sram_blwl_outb[114:114] ,mux_1level_tapbuf_size3_104_configbus0[114:114], mux_1level_tapbuf_size3_104_configbus1[114:114] , mux_1level_tapbuf_size3_104_configbus0_b[114:114] ); -wire [0:1] mux_1level_tapbuf_size2_105_inbus; -assign mux_1level_tapbuf_size2_105_inbus[0] = grid_1__1__pin_0__0__44_; -assign mux_1level_tapbuf_size2_105_inbus[1] = chany_0__1__in_86_ ; -wire [115:115] mux_1level_tapbuf_size2_105_configbus0; -wire [115:115] mux_1level_tapbuf_size2_105_configbus1; -wire [115:115] mux_1level_tapbuf_size2_105_sram_blwl_out ; -wire [115:115] mux_1level_tapbuf_size2_105_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_105_configbus0[115:115] = sram_blwl_bl[115:115] ; -assign mux_1level_tapbuf_size2_105_configbus1[115:115] = sram_blwl_wl[115:115] ; -wire [115:115] mux_1level_tapbuf_size2_105_configbus0_b; -assign mux_1level_tapbuf_size2_105_configbus0_b[115:115] = sram_blwl_blb[115:115] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_105_ (mux_1level_tapbuf_size2_105_inbus, chanx_1__1__out_10_ , mux_1level_tapbuf_size2_105_sram_blwl_out[115:115] , -mux_1level_tapbuf_size2_105_sram_blwl_outb[115:115] ); -//----- SRAM bits for MUX[105], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_115_ (mux_1level_tapbuf_size2_105_sram_blwl_out[115:115] ,mux_1level_tapbuf_size2_105_sram_blwl_out[115:115] ,mux_1level_tapbuf_size2_105_sram_blwl_outb[115:115] ,mux_1level_tapbuf_size2_105_configbus0[115:115], mux_1level_tapbuf_size2_105_configbus1[115:115] , mux_1level_tapbuf_size2_105_configbus0_b[115:115] ); -wire [0:1] mux_1level_tapbuf_size2_106_inbus; -assign mux_1level_tapbuf_size2_106_inbus[0] = grid_1__1__pin_0__0__44_; -assign mux_1level_tapbuf_size2_106_inbus[1] = chany_0__1__in_84_ ; -wire [116:116] mux_1level_tapbuf_size2_106_configbus0; -wire [116:116] mux_1level_tapbuf_size2_106_configbus1; -wire [116:116] mux_1level_tapbuf_size2_106_sram_blwl_out ; -wire [116:116] mux_1level_tapbuf_size2_106_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_106_configbus0[116:116] = sram_blwl_bl[116:116] ; -assign mux_1level_tapbuf_size2_106_configbus1[116:116] = sram_blwl_wl[116:116] ; -wire [116:116] mux_1level_tapbuf_size2_106_configbus0_b; -assign mux_1level_tapbuf_size2_106_configbus0_b[116:116] = sram_blwl_blb[116:116] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_106_ (mux_1level_tapbuf_size2_106_inbus, chanx_1__1__out_12_ , mux_1level_tapbuf_size2_106_sram_blwl_out[116:116] , -mux_1level_tapbuf_size2_106_sram_blwl_outb[116:116] ); -//----- SRAM bits for MUX[106], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_116_ (mux_1level_tapbuf_size2_106_sram_blwl_out[116:116] ,mux_1level_tapbuf_size2_106_sram_blwl_out[116:116] ,mux_1level_tapbuf_size2_106_sram_blwl_outb[116:116] ,mux_1level_tapbuf_size2_106_configbus0[116:116], mux_1level_tapbuf_size2_106_configbus1[116:116] , mux_1level_tapbuf_size2_106_configbus0_b[116:116] ); -wire [0:1] mux_1level_tapbuf_size2_107_inbus; -assign mux_1level_tapbuf_size2_107_inbus[0] = grid_1__1__pin_0__0__44_; -assign mux_1level_tapbuf_size2_107_inbus[1] = chany_0__1__in_82_ ; -wire [117:117] mux_1level_tapbuf_size2_107_configbus0; -wire [117:117] mux_1level_tapbuf_size2_107_configbus1; -wire [117:117] mux_1level_tapbuf_size2_107_sram_blwl_out ; -wire [117:117] mux_1level_tapbuf_size2_107_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_107_configbus0[117:117] = sram_blwl_bl[117:117] ; -assign mux_1level_tapbuf_size2_107_configbus1[117:117] = sram_blwl_wl[117:117] ; -wire [117:117] mux_1level_tapbuf_size2_107_configbus0_b; -assign mux_1level_tapbuf_size2_107_configbus0_b[117:117] = sram_blwl_blb[117:117] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_107_ (mux_1level_tapbuf_size2_107_inbus, chanx_1__1__out_14_ , mux_1level_tapbuf_size2_107_sram_blwl_out[117:117] , -mux_1level_tapbuf_size2_107_sram_blwl_outb[117:117] ); -//----- SRAM bits for MUX[107], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_117_ (mux_1level_tapbuf_size2_107_sram_blwl_out[117:117] ,mux_1level_tapbuf_size2_107_sram_blwl_out[117:117] ,mux_1level_tapbuf_size2_107_sram_blwl_outb[117:117] ,mux_1level_tapbuf_size2_107_configbus0[117:117], mux_1level_tapbuf_size2_107_configbus1[117:117] , mux_1level_tapbuf_size2_107_configbus0_b[117:117] ); -wire [0:1] mux_1level_tapbuf_size2_108_inbus; -assign mux_1level_tapbuf_size2_108_inbus[0] = grid_1__1__pin_0__0__44_; -assign mux_1level_tapbuf_size2_108_inbus[1] = chany_0__1__in_80_ ; -wire [118:118] mux_1level_tapbuf_size2_108_configbus0; -wire [118:118] mux_1level_tapbuf_size2_108_configbus1; -wire [118:118] mux_1level_tapbuf_size2_108_sram_blwl_out ; -wire [118:118] mux_1level_tapbuf_size2_108_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_108_configbus0[118:118] = sram_blwl_bl[118:118] ; -assign mux_1level_tapbuf_size2_108_configbus1[118:118] = sram_blwl_wl[118:118] ; -wire [118:118] mux_1level_tapbuf_size2_108_configbus0_b; -assign mux_1level_tapbuf_size2_108_configbus0_b[118:118] = sram_blwl_blb[118:118] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_108_ (mux_1level_tapbuf_size2_108_inbus, chanx_1__1__out_16_ , mux_1level_tapbuf_size2_108_sram_blwl_out[118:118] , -mux_1level_tapbuf_size2_108_sram_blwl_outb[118:118] ); -//----- SRAM bits for MUX[108], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_118_ (mux_1level_tapbuf_size2_108_sram_blwl_out[118:118] ,mux_1level_tapbuf_size2_108_sram_blwl_out[118:118] ,mux_1level_tapbuf_size2_108_sram_blwl_outb[118:118] ,mux_1level_tapbuf_size2_108_configbus0[118:118], mux_1level_tapbuf_size2_108_configbus1[118:118] , mux_1level_tapbuf_size2_108_configbus0_b[118:118] ); -wire [0:1] mux_1level_tapbuf_size2_109_inbus; -assign mux_1level_tapbuf_size2_109_inbus[0] = grid_1__1__pin_0__0__44_; -assign mux_1level_tapbuf_size2_109_inbus[1] = chany_0__1__in_78_ ; -wire [119:119] mux_1level_tapbuf_size2_109_configbus0; -wire [119:119] mux_1level_tapbuf_size2_109_configbus1; -wire [119:119] mux_1level_tapbuf_size2_109_sram_blwl_out ; -wire [119:119] mux_1level_tapbuf_size2_109_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_109_configbus0[119:119] = sram_blwl_bl[119:119] ; -assign mux_1level_tapbuf_size2_109_configbus1[119:119] = sram_blwl_wl[119:119] ; -wire [119:119] mux_1level_tapbuf_size2_109_configbus0_b; -assign mux_1level_tapbuf_size2_109_configbus0_b[119:119] = sram_blwl_blb[119:119] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_109_ (mux_1level_tapbuf_size2_109_inbus, chanx_1__1__out_18_ , mux_1level_tapbuf_size2_109_sram_blwl_out[119:119] , -mux_1level_tapbuf_size2_109_sram_blwl_outb[119:119] ); -//----- SRAM bits for MUX[109], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_119_ (mux_1level_tapbuf_size2_109_sram_blwl_out[119:119] ,mux_1level_tapbuf_size2_109_sram_blwl_out[119:119] ,mux_1level_tapbuf_size2_109_sram_blwl_outb[119:119] ,mux_1level_tapbuf_size2_109_configbus0[119:119], mux_1level_tapbuf_size2_109_configbus1[119:119] , mux_1level_tapbuf_size2_109_configbus0_b[119:119] ); -wire [0:1] mux_1level_tapbuf_size2_110_inbus; -assign mux_1level_tapbuf_size2_110_inbus[0] = grid_1__1__pin_0__0__48_; -assign mux_1level_tapbuf_size2_110_inbus[1] = chany_0__1__in_76_ ; -wire [120:120] mux_1level_tapbuf_size2_110_configbus0; -wire [120:120] mux_1level_tapbuf_size2_110_configbus1; -wire [120:120] mux_1level_tapbuf_size2_110_sram_blwl_out ; -wire [120:120] mux_1level_tapbuf_size2_110_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_110_configbus0[120:120] = sram_blwl_bl[120:120] ; -assign mux_1level_tapbuf_size2_110_configbus1[120:120] = sram_blwl_wl[120:120] ; -wire [120:120] mux_1level_tapbuf_size2_110_configbus0_b; -assign mux_1level_tapbuf_size2_110_configbus0_b[120:120] = sram_blwl_blb[120:120] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_110_ (mux_1level_tapbuf_size2_110_inbus, chanx_1__1__out_20_ , mux_1level_tapbuf_size2_110_sram_blwl_out[120:120] , -mux_1level_tapbuf_size2_110_sram_blwl_outb[120:120] ); -//----- SRAM bits for MUX[110], level=1, select_path_id=1. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----0----- -sram6T_blwl sram_blwl_120_ (mux_1level_tapbuf_size2_110_sram_blwl_out[120:120] ,mux_1level_tapbuf_size2_110_sram_blwl_out[120:120] ,mux_1level_tapbuf_size2_110_sram_blwl_outb[120:120] ,mux_1level_tapbuf_size2_110_configbus0[120:120], mux_1level_tapbuf_size2_110_configbus1[120:120] , mux_1level_tapbuf_size2_110_configbus0_b[120:120] ); -wire [0:1] mux_1level_tapbuf_size2_111_inbus; -assign mux_1level_tapbuf_size2_111_inbus[0] = grid_1__1__pin_0__0__48_; -assign mux_1level_tapbuf_size2_111_inbus[1] = chany_0__1__in_74_ ; -wire [121:121] mux_1level_tapbuf_size2_111_configbus0; -wire [121:121] mux_1level_tapbuf_size2_111_configbus1; -wire [121:121] mux_1level_tapbuf_size2_111_sram_blwl_out ; -wire [121:121] mux_1level_tapbuf_size2_111_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_111_configbus0[121:121] = sram_blwl_bl[121:121] ; -assign mux_1level_tapbuf_size2_111_configbus1[121:121] = sram_blwl_wl[121:121] ; -wire [121:121] mux_1level_tapbuf_size2_111_configbus0_b; -assign mux_1level_tapbuf_size2_111_configbus0_b[121:121] = sram_blwl_blb[121:121] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_111_ (mux_1level_tapbuf_size2_111_inbus, chanx_1__1__out_22_ , mux_1level_tapbuf_size2_111_sram_blwl_out[121:121] , -mux_1level_tapbuf_size2_111_sram_blwl_outb[121:121] ); -//----- SRAM bits for MUX[111], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_121_ (mux_1level_tapbuf_size2_111_sram_blwl_out[121:121] ,mux_1level_tapbuf_size2_111_sram_blwl_out[121:121] ,mux_1level_tapbuf_size2_111_sram_blwl_outb[121:121] ,mux_1level_tapbuf_size2_111_configbus0[121:121], mux_1level_tapbuf_size2_111_configbus1[121:121] , mux_1level_tapbuf_size2_111_configbus0_b[121:121] ); -wire [0:1] mux_1level_tapbuf_size2_112_inbus; -assign mux_1level_tapbuf_size2_112_inbus[0] = grid_1__1__pin_0__0__48_; -assign mux_1level_tapbuf_size2_112_inbus[1] = chany_0__1__in_72_ ; -wire [122:122] mux_1level_tapbuf_size2_112_configbus0; -wire [122:122] mux_1level_tapbuf_size2_112_configbus1; -wire [122:122] mux_1level_tapbuf_size2_112_sram_blwl_out ; -wire [122:122] mux_1level_tapbuf_size2_112_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_112_configbus0[122:122] = sram_blwl_bl[122:122] ; -assign mux_1level_tapbuf_size2_112_configbus1[122:122] = sram_blwl_wl[122:122] ; -wire [122:122] mux_1level_tapbuf_size2_112_configbus0_b; -assign mux_1level_tapbuf_size2_112_configbus0_b[122:122] = sram_blwl_blb[122:122] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_112_ (mux_1level_tapbuf_size2_112_inbus, chanx_1__1__out_24_ , mux_1level_tapbuf_size2_112_sram_blwl_out[122:122] , -mux_1level_tapbuf_size2_112_sram_blwl_outb[122:122] ); -//----- SRAM bits for MUX[112], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_122_ (mux_1level_tapbuf_size2_112_sram_blwl_out[122:122] ,mux_1level_tapbuf_size2_112_sram_blwl_out[122:122] ,mux_1level_tapbuf_size2_112_sram_blwl_outb[122:122] ,mux_1level_tapbuf_size2_112_configbus0[122:122], mux_1level_tapbuf_size2_112_configbus1[122:122] , mux_1level_tapbuf_size2_112_configbus0_b[122:122] ); -wire [0:1] mux_1level_tapbuf_size2_113_inbus; -assign mux_1level_tapbuf_size2_113_inbus[0] = grid_1__1__pin_0__0__48_; -assign mux_1level_tapbuf_size2_113_inbus[1] = chany_0__1__in_70_ ; -wire [123:123] mux_1level_tapbuf_size2_113_configbus0; -wire [123:123] mux_1level_tapbuf_size2_113_configbus1; -wire [123:123] mux_1level_tapbuf_size2_113_sram_blwl_out ; -wire [123:123] mux_1level_tapbuf_size2_113_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_113_configbus0[123:123] = sram_blwl_bl[123:123] ; -assign mux_1level_tapbuf_size2_113_configbus1[123:123] = sram_blwl_wl[123:123] ; -wire [123:123] mux_1level_tapbuf_size2_113_configbus0_b; -assign mux_1level_tapbuf_size2_113_configbus0_b[123:123] = sram_blwl_blb[123:123] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_113_ (mux_1level_tapbuf_size2_113_inbus, chanx_1__1__out_26_ , mux_1level_tapbuf_size2_113_sram_blwl_out[123:123] , -mux_1level_tapbuf_size2_113_sram_blwl_outb[123:123] ); -//----- SRAM bits for MUX[113], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_123_ (mux_1level_tapbuf_size2_113_sram_blwl_out[123:123] ,mux_1level_tapbuf_size2_113_sram_blwl_out[123:123] ,mux_1level_tapbuf_size2_113_sram_blwl_outb[123:123] ,mux_1level_tapbuf_size2_113_configbus0[123:123], mux_1level_tapbuf_size2_113_configbus1[123:123] , mux_1level_tapbuf_size2_113_configbus0_b[123:123] ); -wire [0:1] mux_1level_tapbuf_size2_114_inbus; -assign mux_1level_tapbuf_size2_114_inbus[0] = grid_1__1__pin_0__0__48_; -assign mux_1level_tapbuf_size2_114_inbus[1] = chany_0__1__in_68_ ; -wire [124:124] mux_1level_tapbuf_size2_114_configbus0; -wire [124:124] mux_1level_tapbuf_size2_114_configbus1; -wire [124:124] mux_1level_tapbuf_size2_114_sram_blwl_out ; -wire [124:124] mux_1level_tapbuf_size2_114_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_114_configbus0[124:124] = sram_blwl_bl[124:124] ; -assign mux_1level_tapbuf_size2_114_configbus1[124:124] = sram_blwl_wl[124:124] ; -wire [124:124] mux_1level_tapbuf_size2_114_configbus0_b; -assign mux_1level_tapbuf_size2_114_configbus0_b[124:124] = sram_blwl_blb[124:124] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_114_ (mux_1level_tapbuf_size2_114_inbus, chanx_1__1__out_28_ , mux_1level_tapbuf_size2_114_sram_blwl_out[124:124] , -mux_1level_tapbuf_size2_114_sram_blwl_outb[124:124] ); -//----- SRAM bits for MUX[114], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_124_ (mux_1level_tapbuf_size2_114_sram_blwl_out[124:124] ,mux_1level_tapbuf_size2_114_sram_blwl_out[124:124] ,mux_1level_tapbuf_size2_114_sram_blwl_outb[124:124] ,mux_1level_tapbuf_size2_114_configbus0[124:124], mux_1level_tapbuf_size2_114_configbus1[124:124] , mux_1level_tapbuf_size2_114_configbus0_b[124:124] ); -wire [0:1] mux_1level_tapbuf_size2_115_inbus; -assign mux_1level_tapbuf_size2_115_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_115_inbus[1] = chany_0__1__in_66_ ; -wire [125:125] mux_1level_tapbuf_size2_115_configbus0; -wire [125:125] mux_1level_tapbuf_size2_115_configbus1; -wire [125:125] mux_1level_tapbuf_size2_115_sram_blwl_out ; -wire [125:125] mux_1level_tapbuf_size2_115_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_115_configbus0[125:125] = sram_blwl_bl[125:125] ; -assign mux_1level_tapbuf_size2_115_configbus1[125:125] = sram_blwl_wl[125:125] ; -wire [125:125] mux_1level_tapbuf_size2_115_configbus0_b; -assign mux_1level_tapbuf_size2_115_configbus0_b[125:125] = sram_blwl_blb[125:125] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_115_ (mux_1level_tapbuf_size2_115_inbus, chanx_1__1__out_30_ , mux_1level_tapbuf_size2_115_sram_blwl_out[125:125] , -mux_1level_tapbuf_size2_115_sram_blwl_outb[125:125] ); -//----- SRAM bits for MUX[115], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_125_ (mux_1level_tapbuf_size2_115_sram_blwl_out[125:125] ,mux_1level_tapbuf_size2_115_sram_blwl_out[125:125] ,mux_1level_tapbuf_size2_115_sram_blwl_outb[125:125] ,mux_1level_tapbuf_size2_115_configbus0[125:125], mux_1level_tapbuf_size2_115_configbus1[125:125] , mux_1level_tapbuf_size2_115_configbus0_b[125:125] ); -wire [0:1] mux_1level_tapbuf_size2_116_inbus; -assign mux_1level_tapbuf_size2_116_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_116_inbus[1] = chany_0__1__in_64_ ; -wire [126:126] mux_1level_tapbuf_size2_116_configbus0; -wire [126:126] mux_1level_tapbuf_size2_116_configbus1; -wire [126:126] mux_1level_tapbuf_size2_116_sram_blwl_out ; -wire [126:126] mux_1level_tapbuf_size2_116_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_116_configbus0[126:126] = sram_blwl_bl[126:126] ; -assign mux_1level_tapbuf_size2_116_configbus1[126:126] = sram_blwl_wl[126:126] ; -wire [126:126] mux_1level_tapbuf_size2_116_configbus0_b; -assign mux_1level_tapbuf_size2_116_configbus0_b[126:126] = sram_blwl_blb[126:126] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_116_ (mux_1level_tapbuf_size2_116_inbus, chanx_1__1__out_32_ , mux_1level_tapbuf_size2_116_sram_blwl_out[126:126] , -mux_1level_tapbuf_size2_116_sram_blwl_outb[126:126] ); -//----- SRAM bits for MUX[116], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_126_ (mux_1level_tapbuf_size2_116_sram_blwl_out[126:126] ,mux_1level_tapbuf_size2_116_sram_blwl_out[126:126] ,mux_1level_tapbuf_size2_116_sram_blwl_outb[126:126] ,mux_1level_tapbuf_size2_116_configbus0[126:126], mux_1level_tapbuf_size2_116_configbus1[126:126] , mux_1level_tapbuf_size2_116_configbus0_b[126:126] ); -wire [0:1] mux_1level_tapbuf_size2_117_inbus; -assign mux_1level_tapbuf_size2_117_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_117_inbus[1] = chany_0__1__in_62_ ; -wire [127:127] mux_1level_tapbuf_size2_117_configbus0; -wire [127:127] mux_1level_tapbuf_size2_117_configbus1; -wire [127:127] mux_1level_tapbuf_size2_117_sram_blwl_out ; -wire [127:127] mux_1level_tapbuf_size2_117_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_117_configbus0[127:127] = sram_blwl_bl[127:127] ; -assign mux_1level_tapbuf_size2_117_configbus1[127:127] = sram_blwl_wl[127:127] ; -wire [127:127] mux_1level_tapbuf_size2_117_configbus0_b; -assign mux_1level_tapbuf_size2_117_configbus0_b[127:127] = sram_blwl_blb[127:127] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_117_ (mux_1level_tapbuf_size2_117_inbus, chanx_1__1__out_34_ , mux_1level_tapbuf_size2_117_sram_blwl_out[127:127] , -mux_1level_tapbuf_size2_117_sram_blwl_outb[127:127] ); -//----- SRAM bits for MUX[117], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_127_ (mux_1level_tapbuf_size2_117_sram_blwl_out[127:127] ,mux_1level_tapbuf_size2_117_sram_blwl_out[127:127] ,mux_1level_tapbuf_size2_117_sram_blwl_outb[127:127] ,mux_1level_tapbuf_size2_117_configbus0[127:127], mux_1level_tapbuf_size2_117_configbus1[127:127] , mux_1level_tapbuf_size2_117_configbus0_b[127:127] ); -wire [0:1] mux_1level_tapbuf_size2_118_inbus; -assign mux_1level_tapbuf_size2_118_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_118_inbus[1] = chany_0__1__in_60_ ; -wire [128:128] mux_1level_tapbuf_size2_118_configbus0; -wire [128:128] mux_1level_tapbuf_size2_118_configbus1; -wire [128:128] mux_1level_tapbuf_size2_118_sram_blwl_out ; -wire [128:128] mux_1level_tapbuf_size2_118_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_118_configbus0[128:128] = sram_blwl_bl[128:128] ; -assign mux_1level_tapbuf_size2_118_configbus1[128:128] = sram_blwl_wl[128:128] ; -wire [128:128] mux_1level_tapbuf_size2_118_configbus0_b; -assign mux_1level_tapbuf_size2_118_configbus0_b[128:128] = sram_blwl_blb[128:128] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_118_ (mux_1level_tapbuf_size2_118_inbus, chanx_1__1__out_36_ , mux_1level_tapbuf_size2_118_sram_blwl_out[128:128] , -mux_1level_tapbuf_size2_118_sram_blwl_outb[128:128] ); -//----- SRAM bits for MUX[118], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_128_ (mux_1level_tapbuf_size2_118_sram_blwl_out[128:128] ,mux_1level_tapbuf_size2_118_sram_blwl_out[128:128] ,mux_1level_tapbuf_size2_118_sram_blwl_outb[128:128] ,mux_1level_tapbuf_size2_118_configbus0[128:128], mux_1level_tapbuf_size2_118_configbus1[128:128] , mux_1level_tapbuf_size2_118_configbus0_b[128:128] ); -wire [0:1] mux_1level_tapbuf_size2_119_inbus; -assign mux_1level_tapbuf_size2_119_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_119_inbus[1] = chany_0__1__in_58_ ; -wire [129:129] mux_1level_tapbuf_size2_119_configbus0; -wire [129:129] mux_1level_tapbuf_size2_119_configbus1; -wire [129:129] mux_1level_tapbuf_size2_119_sram_blwl_out ; -wire [129:129] mux_1level_tapbuf_size2_119_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_119_configbus0[129:129] = sram_blwl_bl[129:129] ; -assign mux_1level_tapbuf_size2_119_configbus1[129:129] = sram_blwl_wl[129:129] ; -wire [129:129] mux_1level_tapbuf_size2_119_configbus0_b; -assign mux_1level_tapbuf_size2_119_configbus0_b[129:129] = sram_blwl_blb[129:129] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_119_ (mux_1level_tapbuf_size2_119_inbus, chanx_1__1__out_38_ , mux_1level_tapbuf_size2_119_sram_blwl_out[129:129] , -mux_1level_tapbuf_size2_119_sram_blwl_outb[129:129] ); -//----- SRAM bits for MUX[119], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_129_ (mux_1level_tapbuf_size2_119_sram_blwl_out[129:129] ,mux_1level_tapbuf_size2_119_sram_blwl_out[129:129] ,mux_1level_tapbuf_size2_119_sram_blwl_outb[129:129] ,mux_1level_tapbuf_size2_119_configbus0[129:129], mux_1level_tapbuf_size2_119_configbus1[129:129] , mux_1level_tapbuf_size2_119_configbus0_b[129:129] ); -wire [0:1] mux_1level_tapbuf_size2_120_inbus; -assign mux_1level_tapbuf_size2_120_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_120_inbus[1] = chany_0__1__in_56_ ; -wire [130:130] mux_1level_tapbuf_size2_120_configbus0; -wire [130:130] mux_1level_tapbuf_size2_120_configbus1; -wire [130:130] mux_1level_tapbuf_size2_120_sram_blwl_out ; -wire [130:130] mux_1level_tapbuf_size2_120_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_120_configbus0[130:130] = sram_blwl_bl[130:130] ; -assign mux_1level_tapbuf_size2_120_configbus1[130:130] = sram_blwl_wl[130:130] ; -wire [130:130] mux_1level_tapbuf_size2_120_configbus0_b; -assign mux_1level_tapbuf_size2_120_configbus0_b[130:130] = sram_blwl_blb[130:130] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_120_ (mux_1level_tapbuf_size2_120_inbus, chanx_1__1__out_40_ , mux_1level_tapbuf_size2_120_sram_blwl_out[130:130] , -mux_1level_tapbuf_size2_120_sram_blwl_outb[130:130] ); -//----- SRAM bits for MUX[120], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_130_ (mux_1level_tapbuf_size2_120_sram_blwl_out[130:130] ,mux_1level_tapbuf_size2_120_sram_blwl_out[130:130] ,mux_1level_tapbuf_size2_120_sram_blwl_outb[130:130] ,mux_1level_tapbuf_size2_120_configbus0[130:130], mux_1level_tapbuf_size2_120_configbus1[130:130] , mux_1level_tapbuf_size2_120_configbus0_b[130:130] ); -wire [0:1] mux_1level_tapbuf_size2_121_inbus; -assign mux_1level_tapbuf_size2_121_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_121_inbus[1] = chany_0__1__in_54_ ; -wire [131:131] mux_1level_tapbuf_size2_121_configbus0; -wire [131:131] mux_1level_tapbuf_size2_121_configbus1; -wire [131:131] mux_1level_tapbuf_size2_121_sram_blwl_out ; -wire [131:131] mux_1level_tapbuf_size2_121_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_121_configbus0[131:131] = sram_blwl_bl[131:131] ; -assign mux_1level_tapbuf_size2_121_configbus1[131:131] = sram_blwl_wl[131:131] ; -wire [131:131] mux_1level_tapbuf_size2_121_configbus0_b; -assign mux_1level_tapbuf_size2_121_configbus0_b[131:131] = sram_blwl_blb[131:131] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_121_ (mux_1level_tapbuf_size2_121_inbus, chanx_1__1__out_42_ , mux_1level_tapbuf_size2_121_sram_blwl_out[131:131] , -mux_1level_tapbuf_size2_121_sram_blwl_outb[131:131] ); -//----- SRAM bits for MUX[121], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_131_ (mux_1level_tapbuf_size2_121_sram_blwl_out[131:131] ,mux_1level_tapbuf_size2_121_sram_blwl_out[131:131] ,mux_1level_tapbuf_size2_121_sram_blwl_outb[131:131] ,mux_1level_tapbuf_size2_121_configbus0[131:131], mux_1level_tapbuf_size2_121_configbus1[131:131] , mux_1level_tapbuf_size2_121_configbus0_b[131:131] ); -wire [0:1] mux_1level_tapbuf_size2_122_inbus; -assign mux_1level_tapbuf_size2_122_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_122_inbus[1] = chany_0__1__in_52_ ; -wire [132:132] mux_1level_tapbuf_size2_122_configbus0; -wire [132:132] mux_1level_tapbuf_size2_122_configbus1; -wire [132:132] mux_1level_tapbuf_size2_122_sram_blwl_out ; -wire [132:132] mux_1level_tapbuf_size2_122_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_122_configbus0[132:132] = sram_blwl_bl[132:132] ; -assign mux_1level_tapbuf_size2_122_configbus1[132:132] = sram_blwl_wl[132:132] ; -wire [132:132] mux_1level_tapbuf_size2_122_configbus0_b; -assign mux_1level_tapbuf_size2_122_configbus0_b[132:132] = sram_blwl_blb[132:132] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_122_ (mux_1level_tapbuf_size2_122_inbus, chanx_1__1__out_44_ , mux_1level_tapbuf_size2_122_sram_blwl_out[132:132] , -mux_1level_tapbuf_size2_122_sram_blwl_outb[132:132] ); -//----- SRAM bits for MUX[122], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_132_ (mux_1level_tapbuf_size2_122_sram_blwl_out[132:132] ,mux_1level_tapbuf_size2_122_sram_blwl_out[132:132] ,mux_1level_tapbuf_size2_122_sram_blwl_outb[132:132] ,mux_1level_tapbuf_size2_122_configbus0[132:132], mux_1level_tapbuf_size2_122_configbus1[132:132] , mux_1level_tapbuf_size2_122_configbus0_b[132:132] ); -wire [0:1] mux_1level_tapbuf_size2_123_inbus; -assign mux_1level_tapbuf_size2_123_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_123_inbus[1] = chany_0__1__in_50_ ; -wire [133:133] mux_1level_tapbuf_size2_123_configbus0; -wire [133:133] mux_1level_tapbuf_size2_123_configbus1; -wire [133:133] mux_1level_tapbuf_size2_123_sram_blwl_out ; -wire [133:133] mux_1level_tapbuf_size2_123_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_123_configbus0[133:133] = sram_blwl_bl[133:133] ; -assign mux_1level_tapbuf_size2_123_configbus1[133:133] = sram_blwl_wl[133:133] ; -wire [133:133] mux_1level_tapbuf_size2_123_configbus0_b; -assign mux_1level_tapbuf_size2_123_configbus0_b[133:133] = sram_blwl_blb[133:133] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_123_ (mux_1level_tapbuf_size2_123_inbus, chanx_1__1__out_46_ , mux_1level_tapbuf_size2_123_sram_blwl_out[133:133] , -mux_1level_tapbuf_size2_123_sram_blwl_outb[133:133] ); -//----- SRAM bits for MUX[123], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_133_ (mux_1level_tapbuf_size2_123_sram_blwl_out[133:133] ,mux_1level_tapbuf_size2_123_sram_blwl_out[133:133] ,mux_1level_tapbuf_size2_123_sram_blwl_outb[133:133] ,mux_1level_tapbuf_size2_123_configbus0[133:133], mux_1level_tapbuf_size2_123_configbus1[133:133] , mux_1level_tapbuf_size2_123_configbus0_b[133:133] ); -wire [0:1] mux_1level_tapbuf_size2_124_inbus; -assign mux_1level_tapbuf_size2_124_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_124_inbus[1] = chany_0__1__in_48_ ; -wire [134:134] mux_1level_tapbuf_size2_124_configbus0; -wire [134:134] mux_1level_tapbuf_size2_124_configbus1; -wire [134:134] mux_1level_tapbuf_size2_124_sram_blwl_out ; -wire [134:134] mux_1level_tapbuf_size2_124_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_124_configbus0[134:134] = sram_blwl_bl[134:134] ; -assign mux_1level_tapbuf_size2_124_configbus1[134:134] = sram_blwl_wl[134:134] ; -wire [134:134] mux_1level_tapbuf_size2_124_configbus0_b; -assign mux_1level_tapbuf_size2_124_configbus0_b[134:134] = sram_blwl_blb[134:134] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_124_ (mux_1level_tapbuf_size2_124_inbus, chanx_1__1__out_48_ , mux_1level_tapbuf_size2_124_sram_blwl_out[134:134] , -mux_1level_tapbuf_size2_124_sram_blwl_outb[134:134] ); -//----- SRAM bits for MUX[124], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_134_ (mux_1level_tapbuf_size2_124_sram_blwl_out[134:134] ,mux_1level_tapbuf_size2_124_sram_blwl_out[134:134] ,mux_1level_tapbuf_size2_124_sram_blwl_outb[134:134] ,mux_1level_tapbuf_size2_124_configbus0[134:134], mux_1level_tapbuf_size2_124_configbus1[134:134] , mux_1level_tapbuf_size2_124_configbus0_b[134:134] ); -wire [0:1] mux_1level_tapbuf_size2_125_inbus; -assign mux_1level_tapbuf_size2_125_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_125_inbus[1] = chany_0__1__in_46_ ; -wire [135:135] mux_1level_tapbuf_size2_125_configbus0; -wire [135:135] mux_1level_tapbuf_size2_125_configbus1; -wire [135:135] mux_1level_tapbuf_size2_125_sram_blwl_out ; -wire [135:135] mux_1level_tapbuf_size2_125_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_125_configbus0[135:135] = sram_blwl_bl[135:135] ; -assign mux_1level_tapbuf_size2_125_configbus1[135:135] = sram_blwl_wl[135:135] ; -wire [135:135] mux_1level_tapbuf_size2_125_configbus0_b; -assign mux_1level_tapbuf_size2_125_configbus0_b[135:135] = sram_blwl_blb[135:135] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_125_ (mux_1level_tapbuf_size2_125_inbus, chanx_1__1__out_50_ , mux_1level_tapbuf_size2_125_sram_blwl_out[135:135] , -mux_1level_tapbuf_size2_125_sram_blwl_outb[135:135] ); -//----- SRAM bits for MUX[125], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_135_ (mux_1level_tapbuf_size2_125_sram_blwl_out[135:135] ,mux_1level_tapbuf_size2_125_sram_blwl_out[135:135] ,mux_1level_tapbuf_size2_125_sram_blwl_outb[135:135] ,mux_1level_tapbuf_size2_125_configbus0[135:135], mux_1level_tapbuf_size2_125_configbus1[135:135] , mux_1level_tapbuf_size2_125_configbus0_b[135:135] ); -wire [0:1] mux_1level_tapbuf_size2_126_inbus; -assign mux_1level_tapbuf_size2_126_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_126_inbus[1] = chany_0__1__in_44_ ; -wire [136:136] mux_1level_tapbuf_size2_126_configbus0; -wire [136:136] mux_1level_tapbuf_size2_126_configbus1; -wire [136:136] mux_1level_tapbuf_size2_126_sram_blwl_out ; -wire [136:136] mux_1level_tapbuf_size2_126_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_126_configbus0[136:136] = sram_blwl_bl[136:136] ; -assign mux_1level_tapbuf_size2_126_configbus1[136:136] = sram_blwl_wl[136:136] ; -wire [136:136] mux_1level_tapbuf_size2_126_configbus0_b; -assign mux_1level_tapbuf_size2_126_configbus0_b[136:136] = sram_blwl_blb[136:136] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_126_ (mux_1level_tapbuf_size2_126_inbus, chanx_1__1__out_52_ , mux_1level_tapbuf_size2_126_sram_blwl_out[136:136] , -mux_1level_tapbuf_size2_126_sram_blwl_outb[136:136] ); -//----- SRAM bits for MUX[126], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_136_ (mux_1level_tapbuf_size2_126_sram_blwl_out[136:136] ,mux_1level_tapbuf_size2_126_sram_blwl_out[136:136] ,mux_1level_tapbuf_size2_126_sram_blwl_outb[136:136] ,mux_1level_tapbuf_size2_126_configbus0[136:136], mux_1level_tapbuf_size2_126_configbus1[136:136] , mux_1level_tapbuf_size2_126_configbus0_b[136:136] ); -wire [0:1] mux_1level_tapbuf_size2_127_inbus; -assign mux_1level_tapbuf_size2_127_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_127_inbus[1] = chany_0__1__in_42_ ; -wire [137:137] mux_1level_tapbuf_size2_127_configbus0; -wire [137:137] mux_1level_tapbuf_size2_127_configbus1; -wire [137:137] mux_1level_tapbuf_size2_127_sram_blwl_out ; -wire [137:137] mux_1level_tapbuf_size2_127_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_127_configbus0[137:137] = sram_blwl_bl[137:137] ; -assign mux_1level_tapbuf_size2_127_configbus1[137:137] = sram_blwl_wl[137:137] ; -wire [137:137] mux_1level_tapbuf_size2_127_configbus0_b; -assign mux_1level_tapbuf_size2_127_configbus0_b[137:137] = sram_blwl_blb[137:137] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_127_ (mux_1level_tapbuf_size2_127_inbus, chanx_1__1__out_54_ , mux_1level_tapbuf_size2_127_sram_blwl_out[137:137] , -mux_1level_tapbuf_size2_127_sram_blwl_outb[137:137] ); -//----- SRAM bits for MUX[127], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_137_ (mux_1level_tapbuf_size2_127_sram_blwl_out[137:137] ,mux_1level_tapbuf_size2_127_sram_blwl_out[137:137] ,mux_1level_tapbuf_size2_127_sram_blwl_outb[137:137] ,mux_1level_tapbuf_size2_127_configbus0[137:137], mux_1level_tapbuf_size2_127_configbus1[137:137] , mux_1level_tapbuf_size2_127_configbus0_b[137:137] ); -wire [0:1] mux_1level_tapbuf_size2_128_inbus; -assign mux_1level_tapbuf_size2_128_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_128_inbus[1] = chany_0__1__in_40_ ; -wire [138:138] mux_1level_tapbuf_size2_128_configbus0; -wire [138:138] mux_1level_tapbuf_size2_128_configbus1; -wire [138:138] mux_1level_tapbuf_size2_128_sram_blwl_out ; -wire [138:138] mux_1level_tapbuf_size2_128_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_128_configbus0[138:138] = sram_blwl_bl[138:138] ; -assign mux_1level_tapbuf_size2_128_configbus1[138:138] = sram_blwl_wl[138:138] ; -wire [138:138] mux_1level_tapbuf_size2_128_configbus0_b; -assign mux_1level_tapbuf_size2_128_configbus0_b[138:138] = sram_blwl_blb[138:138] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_128_ (mux_1level_tapbuf_size2_128_inbus, chanx_1__1__out_56_ , mux_1level_tapbuf_size2_128_sram_blwl_out[138:138] , -mux_1level_tapbuf_size2_128_sram_blwl_outb[138:138] ); -//----- SRAM bits for MUX[128], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_138_ (mux_1level_tapbuf_size2_128_sram_blwl_out[138:138] ,mux_1level_tapbuf_size2_128_sram_blwl_out[138:138] ,mux_1level_tapbuf_size2_128_sram_blwl_outb[138:138] ,mux_1level_tapbuf_size2_128_configbus0[138:138], mux_1level_tapbuf_size2_128_configbus1[138:138] , mux_1level_tapbuf_size2_128_configbus0_b[138:138] ); -wire [0:1] mux_1level_tapbuf_size2_129_inbus; -assign mux_1level_tapbuf_size2_129_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_129_inbus[1] = chany_0__1__in_38_ ; -wire [139:139] mux_1level_tapbuf_size2_129_configbus0; -wire [139:139] mux_1level_tapbuf_size2_129_configbus1; -wire [139:139] mux_1level_tapbuf_size2_129_sram_blwl_out ; -wire [139:139] mux_1level_tapbuf_size2_129_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_129_configbus0[139:139] = sram_blwl_bl[139:139] ; -assign mux_1level_tapbuf_size2_129_configbus1[139:139] = sram_blwl_wl[139:139] ; -wire [139:139] mux_1level_tapbuf_size2_129_configbus0_b; -assign mux_1level_tapbuf_size2_129_configbus0_b[139:139] = sram_blwl_blb[139:139] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_129_ (mux_1level_tapbuf_size2_129_inbus, chanx_1__1__out_58_ , mux_1level_tapbuf_size2_129_sram_blwl_out[139:139] , -mux_1level_tapbuf_size2_129_sram_blwl_outb[139:139] ); -//----- SRAM bits for MUX[129], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_139_ (mux_1level_tapbuf_size2_129_sram_blwl_out[139:139] ,mux_1level_tapbuf_size2_129_sram_blwl_out[139:139] ,mux_1level_tapbuf_size2_129_sram_blwl_outb[139:139] ,mux_1level_tapbuf_size2_129_configbus0[139:139], mux_1level_tapbuf_size2_129_configbus1[139:139] , mux_1level_tapbuf_size2_129_configbus0_b[139:139] ); -wire [0:1] mux_1level_tapbuf_size2_130_inbus; -assign mux_1level_tapbuf_size2_130_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_130_inbus[1] = chany_0__1__in_36_ ; -wire [140:140] mux_1level_tapbuf_size2_130_configbus0; -wire [140:140] mux_1level_tapbuf_size2_130_configbus1; -wire [140:140] mux_1level_tapbuf_size2_130_sram_blwl_out ; -wire [140:140] mux_1level_tapbuf_size2_130_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_130_configbus0[140:140] = sram_blwl_bl[140:140] ; -assign mux_1level_tapbuf_size2_130_configbus1[140:140] = sram_blwl_wl[140:140] ; -wire [140:140] mux_1level_tapbuf_size2_130_configbus0_b; -assign mux_1level_tapbuf_size2_130_configbus0_b[140:140] = sram_blwl_blb[140:140] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_130_ (mux_1level_tapbuf_size2_130_inbus, chanx_1__1__out_60_ , mux_1level_tapbuf_size2_130_sram_blwl_out[140:140] , -mux_1level_tapbuf_size2_130_sram_blwl_outb[140:140] ); -//----- SRAM bits for MUX[130], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_140_ (mux_1level_tapbuf_size2_130_sram_blwl_out[140:140] ,mux_1level_tapbuf_size2_130_sram_blwl_out[140:140] ,mux_1level_tapbuf_size2_130_sram_blwl_outb[140:140] ,mux_1level_tapbuf_size2_130_configbus0[140:140], mux_1level_tapbuf_size2_130_configbus1[140:140] , mux_1level_tapbuf_size2_130_configbus0_b[140:140] ); -wire [0:1] mux_1level_tapbuf_size2_131_inbus; -assign mux_1level_tapbuf_size2_131_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_131_inbus[1] = chany_0__1__in_34_ ; -wire [141:141] mux_1level_tapbuf_size2_131_configbus0; -wire [141:141] mux_1level_tapbuf_size2_131_configbus1; -wire [141:141] mux_1level_tapbuf_size2_131_sram_blwl_out ; -wire [141:141] mux_1level_tapbuf_size2_131_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_131_configbus0[141:141] = sram_blwl_bl[141:141] ; -assign mux_1level_tapbuf_size2_131_configbus1[141:141] = sram_blwl_wl[141:141] ; -wire [141:141] mux_1level_tapbuf_size2_131_configbus0_b; -assign mux_1level_tapbuf_size2_131_configbus0_b[141:141] = sram_blwl_blb[141:141] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_131_ (mux_1level_tapbuf_size2_131_inbus, chanx_1__1__out_62_ , mux_1level_tapbuf_size2_131_sram_blwl_out[141:141] , -mux_1level_tapbuf_size2_131_sram_blwl_outb[141:141] ); -//----- SRAM bits for MUX[131], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_141_ (mux_1level_tapbuf_size2_131_sram_blwl_out[141:141] ,mux_1level_tapbuf_size2_131_sram_blwl_out[141:141] ,mux_1level_tapbuf_size2_131_sram_blwl_outb[141:141] ,mux_1level_tapbuf_size2_131_configbus0[141:141], mux_1level_tapbuf_size2_131_configbus1[141:141] , mux_1level_tapbuf_size2_131_configbus0_b[141:141] ); -wire [0:1] mux_1level_tapbuf_size2_132_inbus; -assign mux_1level_tapbuf_size2_132_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_132_inbus[1] = chany_0__1__in_32_ ; -wire [142:142] mux_1level_tapbuf_size2_132_configbus0; -wire [142:142] mux_1level_tapbuf_size2_132_configbus1; -wire [142:142] mux_1level_tapbuf_size2_132_sram_blwl_out ; -wire [142:142] mux_1level_tapbuf_size2_132_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_132_configbus0[142:142] = sram_blwl_bl[142:142] ; -assign mux_1level_tapbuf_size2_132_configbus1[142:142] = sram_blwl_wl[142:142] ; -wire [142:142] mux_1level_tapbuf_size2_132_configbus0_b; -assign mux_1level_tapbuf_size2_132_configbus0_b[142:142] = sram_blwl_blb[142:142] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_132_ (mux_1level_tapbuf_size2_132_inbus, chanx_1__1__out_64_ , mux_1level_tapbuf_size2_132_sram_blwl_out[142:142] , -mux_1level_tapbuf_size2_132_sram_blwl_outb[142:142] ); -//----- SRAM bits for MUX[132], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_142_ (mux_1level_tapbuf_size2_132_sram_blwl_out[142:142] ,mux_1level_tapbuf_size2_132_sram_blwl_out[142:142] ,mux_1level_tapbuf_size2_132_sram_blwl_outb[142:142] ,mux_1level_tapbuf_size2_132_configbus0[142:142], mux_1level_tapbuf_size2_132_configbus1[142:142] , mux_1level_tapbuf_size2_132_configbus0_b[142:142] ); -wire [0:1] mux_1level_tapbuf_size2_133_inbus; -assign mux_1level_tapbuf_size2_133_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_133_inbus[1] = chany_0__1__in_30_ ; -wire [143:143] mux_1level_tapbuf_size2_133_configbus0; -wire [143:143] mux_1level_tapbuf_size2_133_configbus1; -wire [143:143] mux_1level_tapbuf_size2_133_sram_blwl_out ; -wire [143:143] mux_1level_tapbuf_size2_133_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_133_configbus0[143:143] = sram_blwl_bl[143:143] ; -assign mux_1level_tapbuf_size2_133_configbus1[143:143] = sram_blwl_wl[143:143] ; -wire [143:143] mux_1level_tapbuf_size2_133_configbus0_b; -assign mux_1level_tapbuf_size2_133_configbus0_b[143:143] = sram_blwl_blb[143:143] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_133_ (mux_1level_tapbuf_size2_133_inbus, chanx_1__1__out_66_ , mux_1level_tapbuf_size2_133_sram_blwl_out[143:143] , -mux_1level_tapbuf_size2_133_sram_blwl_outb[143:143] ); -//----- SRAM bits for MUX[133], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_143_ (mux_1level_tapbuf_size2_133_sram_blwl_out[143:143] ,mux_1level_tapbuf_size2_133_sram_blwl_out[143:143] ,mux_1level_tapbuf_size2_133_sram_blwl_outb[143:143] ,mux_1level_tapbuf_size2_133_configbus0[143:143], mux_1level_tapbuf_size2_133_configbus1[143:143] , mux_1level_tapbuf_size2_133_configbus0_b[143:143] ); -wire [0:1] mux_1level_tapbuf_size2_134_inbus; -assign mux_1level_tapbuf_size2_134_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_134_inbus[1] = chany_0__1__in_28_ ; -wire [144:144] mux_1level_tapbuf_size2_134_configbus0; -wire [144:144] mux_1level_tapbuf_size2_134_configbus1; -wire [144:144] mux_1level_tapbuf_size2_134_sram_blwl_out ; -wire [144:144] mux_1level_tapbuf_size2_134_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_134_configbus0[144:144] = sram_blwl_bl[144:144] ; -assign mux_1level_tapbuf_size2_134_configbus1[144:144] = sram_blwl_wl[144:144] ; -wire [144:144] mux_1level_tapbuf_size2_134_configbus0_b; -assign mux_1level_tapbuf_size2_134_configbus0_b[144:144] = sram_blwl_blb[144:144] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_134_ (mux_1level_tapbuf_size2_134_inbus, chanx_1__1__out_68_ , mux_1level_tapbuf_size2_134_sram_blwl_out[144:144] , -mux_1level_tapbuf_size2_134_sram_blwl_outb[144:144] ); -//----- SRAM bits for MUX[134], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_144_ (mux_1level_tapbuf_size2_134_sram_blwl_out[144:144] ,mux_1level_tapbuf_size2_134_sram_blwl_out[144:144] ,mux_1level_tapbuf_size2_134_sram_blwl_outb[144:144] ,mux_1level_tapbuf_size2_134_configbus0[144:144], mux_1level_tapbuf_size2_134_configbus1[144:144] , mux_1level_tapbuf_size2_134_configbus0_b[144:144] ); -wire [0:1] mux_1level_tapbuf_size2_135_inbus; -assign mux_1level_tapbuf_size2_135_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_135_inbus[1] = chany_0__1__in_26_ ; -wire [145:145] mux_1level_tapbuf_size2_135_configbus0; -wire [145:145] mux_1level_tapbuf_size2_135_configbus1; -wire [145:145] mux_1level_tapbuf_size2_135_sram_blwl_out ; -wire [145:145] mux_1level_tapbuf_size2_135_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_135_configbus0[145:145] = sram_blwl_bl[145:145] ; -assign mux_1level_tapbuf_size2_135_configbus1[145:145] = sram_blwl_wl[145:145] ; -wire [145:145] mux_1level_tapbuf_size2_135_configbus0_b; -assign mux_1level_tapbuf_size2_135_configbus0_b[145:145] = sram_blwl_blb[145:145] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_135_ (mux_1level_tapbuf_size2_135_inbus, chanx_1__1__out_70_ , mux_1level_tapbuf_size2_135_sram_blwl_out[145:145] , -mux_1level_tapbuf_size2_135_sram_blwl_outb[145:145] ); -//----- SRAM bits for MUX[135], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_145_ (mux_1level_tapbuf_size2_135_sram_blwl_out[145:145] ,mux_1level_tapbuf_size2_135_sram_blwl_out[145:145] ,mux_1level_tapbuf_size2_135_sram_blwl_outb[145:145] ,mux_1level_tapbuf_size2_135_configbus0[145:145], mux_1level_tapbuf_size2_135_configbus1[145:145] , mux_1level_tapbuf_size2_135_configbus0_b[145:145] ); -wire [0:1] mux_1level_tapbuf_size2_136_inbus; -assign mux_1level_tapbuf_size2_136_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_136_inbus[1] = chany_0__1__in_24_ ; -wire [146:146] mux_1level_tapbuf_size2_136_configbus0; -wire [146:146] mux_1level_tapbuf_size2_136_configbus1; -wire [146:146] mux_1level_tapbuf_size2_136_sram_blwl_out ; -wire [146:146] mux_1level_tapbuf_size2_136_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_136_configbus0[146:146] = sram_blwl_bl[146:146] ; -assign mux_1level_tapbuf_size2_136_configbus1[146:146] = sram_blwl_wl[146:146] ; -wire [146:146] mux_1level_tapbuf_size2_136_configbus0_b; -assign mux_1level_tapbuf_size2_136_configbus0_b[146:146] = sram_blwl_blb[146:146] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_136_ (mux_1level_tapbuf_size2_136_inbus, chanx_1__1__out_72_ , mux_1level_tapbuf_size2_136_sram_blwl_out[146:146] , -mux_1level_tapbuf_size2_136_sram_blwl_outb[146:146] ); -//----- SRAM bits for MUX[136], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_146_ (mux_1level_tapbuf_size2_136_sram_blwl_out[146:146] ,mux_1level_tapbuf_size2_136_sram_blwl_out[146:146] ,mux_1level_tapbuf_size2_136_sram_blwl_outb[146:146] ,mux_1level_tapbuf_size2_136_configbus0[146:146], mux_1level_tapbuf_size2_136_configbus1[146:146] , mux_1level_tapbuf_size2_136_configbus0_b[146:146] ); -wire [0:1] mux_1level_tapbuf_size2_137_inbus; -assign mux_1level_tapbuf_size2_137_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_137_inbus[1] = chany_0__1__in_22_ ; -wire [147:147] mux_1level_tapbuf_size2_137_configbus0; -wire [147:147] mux_1level_tapbuf_size2_137_configbus1; -wire [147:147] mux_1level_tapbuf_size2_137_sram_blwl_out ; -wire [147:147] mux_1level_tapbuf_size2_137_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_137_configbus0[147:147] = sram_blwl_bl[147:147] ; -assign mux_1level_tapbuf_size2_137_configbus1[147:147] = sram_blwl_wl[147:147] ; -wire [147:147] mux_1level_tapbuf_size2_137_configbus0_b; -assign mux_1level_tapbuf_size2_137_configbus0_b[147:147] = sram_blwl_blb[147:147] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_137_ (mux_1level_tapbuf_size2_137_inbus, chanx_1__1__out_74_ , mux_1level_tapbuf_size2_137_sram_blwl_out[147:147] , -mux_1level_tapbuf_size2_137_sram_blwl_outb[147:147] ); -//----- SRAM bits for MUX[137], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_147_ (mux_1level_tapbuf_size2_137_sram_blwl_out[147:147] ,mux_1level_tapbuf_size2_137_sram_blwl_out[147:147] ,mux_1level_tapbuf_size2_137_sram_blwl_outb[147:147] ,mux_1level_tapbuf_size2_137_configbus0[147:147], mux_1level_tapbuf_size2_137_configbus1[147:147] , mux_1level_tapbuf_size2_137_configbus0_b[147:147] ); -wire [0:1] mux_1level_tapbuf_size2_138_inbus; -assign mux_1level_tapbuf_size2_138_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_138_inbus[1] = chany_0__1__in_20_ ; -wire [148:148] mux_1level_tapbuf_size2_138_configbus0; -wire [148:148] mux_1level_tapbuf_size2_138_configbus1; -wire [148:148] mux_1level_tapbuf_size2_138_sram_blwl_out ; -wire [148:148] mux_1level_tapbuf_size2_138_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_138_configbus0[148:148] = sram_blwl_bl[148:148] ; -assign mux_1level_tapbuf_size2_138_configbus1[148:148] = sram_blwl_wl[148:148] ; -wire [148:148] mux_1level_tapbuf_size2_138_configbus0_b; -assign mux_1level_tapbuf_size2_138_configbus0_b[148:148] = sram_blwl_blb[148:148] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_138_ (mux_1level_tapbuf_size2_138_inbus, chanx_1__1__out_76_ , mux_1level_tapbuf_size2_138_sram_blwl_out[148:148] , -mux_1level_tapbuf_size2_138_sram_blwl_outb[148:148] ); -//----- SRAM bits for MUX[138], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_148_ (mux_1level_tapbuf_size2_138_sram_blwl_out[148:148] ,mux_1level_tapbuf_size2_138_sram_blwl_out[148:148] ,mux_1level_tapbuf_size2_138_sram_blwl_outb[148:148] ,mux_1level_tapbuf_size2_138_configbus0[148:148], mux_1level_tapbuf_size2_138_configbus1[148:148] , mux_1level_tapbuf_size2_138_configbus0_b[148:148] ); -wire [0:1] mux_1level_tapbuf_size2_139_inbus; -assign mux_1level_tapbuf_size2_139_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_139_inbus[1] = chany_0__1__in_18_ ; -wire [149:149] mux_1level_tapbuf_size2_139_configbus0; -wire [149:149] mux_1level_tapbuf_size2_139_configbus1; -wire [149:149] mux_1level_tapbuf_size2_139_sram_blwl_out ; -wire [149:149] mux_1level_tapbuf_size2_139_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_139_configbus0[149:149] = sram_blwl_bl[149:149] ; -assign mux_1level_tapbuf_size2_139_configbus1[149:149] = sram_blwl_wl[149:149] ; -wire [149:149] mux_1level_tapbuf_size2_139_configbus0_b; -assign mux_1level_tapbuf_size2_139_configbus0_b[149:149] = sram_blwl_blb[149:149] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_139_ (mux_1level_tapbuf_size2_139_inbus, chanx_1__1__out_78_ , mux_1level_tapbuf_size2_139_sram_blwl_out[149:149] , -mux_1level_tapbuf_size2_139_sram_blwl_outb[149:149] ); -//----- SRAM bits for MUX[139], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_149_ (mux_1level_tapbuf_size2_139_sram_blwl_out[149:149] ,mux_1level_tapbuf_size2_139_sram_blwl_out[149:149] ,mux_1level_tapbuf_size2_139_sram_blwl_outb[149:149] ,mux_1level_tapbuf_size2_139_configbus0[149:149], mux_1level_tapbuf_size2_139_configbus1[149:149] , mux_1level_tapbuf_size2_139_configbus0_b[149:149] ); -wire [0:1] mux_1level_tapbuf_size2_140_inbus; -assign mux_1level_tapbuf_size2_140_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_140_inbus[1] = chany_0__1__in_16_ ; -wire [150:150] mux_1level_tapbuf_size2_140_configbus0; -wire [150:150] mux_1level_tapbuf_size2_140_configbus1; -wire [150:150] mux_1level_tapbuf_size2_140_sram_blwl_out ; -wire [150:150] mux_1level_tapbuf_size2_140_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_140_configbus0[150:150] = sram_blwl_bl[150:150] ; -assign mux_1level_tapbuf_size2_140_configbus1[150:150] = sram_blwl_wl[150:150] ; -wire [150:150] mux_1level_tapbuf_size2_140_configbus0_b; -assign mux_1level_tapbuf_size2_140_configbus0_b[150:150] = sram_blwl_blb[150:150] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_140_ (mux_1level_tapbuf_size2_140_inbus, chanx_1__1__out_80_ , mux_1level_tapbuf_size2_140_sram_blwl_out[150:150] , -mux_1level_tapbuf_size2_140_sram_blwl_outb[150:150] ); -//----- SRAM bits for MUX[140], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_150_ (mux_1level_tapbuf_size2_140_sram_blwl_out[150:150] ,mux_1level_tapbuf_size2_140_sram_blwl_out[150:150] ,mux_1level_tapbuf_size2_140_sram_blwl_outb[150:150] ,mux_1level_tapbuf_size2_140_configbus0[150:150], mux_1level_tapbuf_size2_140_configbus1[150:150] , mux_1level_tapbuf_size2_140_configbus0_b[150:150] ); -wire [0:1] mux_1level_tapbuf_size2_141_inbus; -assign mux_1level_tapbuf_size2_141_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_141_inbus[1] = chany_0__1__in_14_ ; -wire [151:151] mux_1level_tapbuf_size2_141_configbus0; -wire [151:151] mux_1level_tapbuf_size2_141_configbus1; -wire [151:151] mux_1level_tapbuf_size2_141_sram_blwl_out ; -wire [151:151] mux_1level_tapbuf_size2_141_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_141_configbus0[151:151] = sram_blwl_bl[151:151] ; -assign mux_1level_tapbuf_size2_141_configbus1[151:151] = sram_blwl_wl[151:151] ; -wire [151:151] mux_1level_tapbuf_size2_141_configbus0_b; -assign mux_1level_tapbuf_size2_141_configbus0_b[151:151] = sram_blwl_blb[151:151] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_141_ (mux_1level_tapbuf_size2_141_inbus, chanx_1__1__out_82_ , mux_1level_tapbuf_size2_141_sram_blwl_out[151:151] , -mux_1level_tapbuf_size2_141_sram_blwl_outb[151:151] ); -//----- SRAM bits for MUX[141], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_151_ (mux_1level_tapbuf_size2_141_sram_blwl_out[151:151] ,mux_1level_tapbuf_size2_141_sram_blwl_out[151:151] ,mux_1level_tapbuf_size2_141_sram_blwl_outb[151:151] ,mux_1level_tapbuf_size2_141_configbus0[151:151], mux_1level_tapbuf_size2_141_configbus1[151:151] , mux_1level_tapbuf_size2_141_configbus0_b[151:151] ); -wire [0:1] mux_1level_tapbuf_size2_142_inbus; -assign mux_1level_tapbuf_size2_142_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_142_inbus[1] = chany_0__1__in_12_ ; -wire [152:152] mux_1level_tapbuf_size2_142_configbus0; -wire [152:152] mux_1level_tapbuf_size2_142_configbus1; -wire [152:152] mux_1level_tapbuf_size2_142_sram_blwl_out ; -wire [152:152] mux_1level_tapbuf_size2_142_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_142_configbus0[152:152] = sram_blwl_bl[152:152] ; -assign mux_1level_tapbuf_size2_142_configbus1[152:152] = sram_blwl_wl[152:152] ; -wire [152:152] mux_1level_tapbuf_size2_142_configbus0_b; -assign mux_1level_tapbuf_size2_142_configbus0_b[152:152] = sram_blwl_blb[152:152] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_142_ (mux_1level_tapbuf_size2_142_inbus, chanx_1__1__out_84_ , mux_1level_tapbuf_size2_142_sram_blwl_out[152:152] , -mux_1level_tapbuf_size2_142_sram_blwl_outb[152:152] ); -//----- SRAM bits for MUX[142], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_152_ (mux_1level_tapbuf_size2_142_sram_blwl_out[152:152] ,mux_1level_tapbuf_size2_142_sram_blwl_out[152:152] ,mux_1level_tapbuf_size2_142_sram_blwl_outb[152:152] ,mux_1level_tapbuf_size2_142_configbus0[152:152], mux_1level_tapbuf_size2_142_configbus1[152:152] , mux_1level_tapbuf_size2_142_configbus0_b[152:152] ); -wire [0:1] mux_1level_tapbuf_size2_143_inbus; -assign mux_1level_tapbuf_size2_143_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_143_inbus[1] = chany_0__1__in_10_ ; -wire [153:153] mux_1level_tapbuf_size2_143_configbus0; -wire [153:153] mux_1level_tapbuf_size2_143_configbus1; -wire [153:153] mux_1level_tapbuf_size2_143_sram_blwl_out ; -wire [153:153] mux_1level_tapbuf_size2_143_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_143_configbus0[153:153] = sram_blwl_bl[153:153] ; -assign mux_1level_tapbuf_size2_143_configbus1[153:153] = sram_blwl_wl[153:153] ; -wire [153:153] mux_1level_tapbuf_size2_143_configbus0_b; -assign mux_1level_tapbuf_size2_143_configbus0_b[153:153] = sram_blwl_blb[153:153] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_143_ (mux_1level_tapbuf_size2_143_inbus, chanx_1__1__out_86_ , mux_1level_tapbuf_size2_143_sram_blwl_out[153:153] , -mux_1level_tapbuf_size2_143_sram_blwl_outb[153:153] ); -//----- SRAM bits for MUX[143], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_153_ (mux_1level_tapbuf_size2_143_sram_blwl_out[153:153] ,mux_1level_tapbuf_size2_143_sram_blwl_out[153:153] ,mux_1level_tapbuf_size2_143_sram_blwl_outb[153:153] ,mux_1level_tapbuf_size2_143_configbus0[153:153], mux_1level_tapbuf_size2_143_configbus1[153:153] , mux_1level_tapbuf_size2_143_configbus0_b[153:153] ); -wire [0:1] mux_1level_tapbuf_size2_144_inbus; -assign mux_1level_tapbuf_size2_144_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_144_inbus[1] = chany_0__1__in_8_ ; -wire [154:154] mux_1level_tapbuf_size2_144_configbus0; -wire [154:154] mux_1level_tapbuf_size2_144_configbus1; -wire [154:154] mux_1level_tapbuf_size2_144_sram_blwl_out ; -wire [154:154] mux_1level_tapbuf_size2_144_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_144_configbus0[154:154] = sram_blwl_bl[154:154] ; -assign mux_1level_tapbuf_size2_144_configbus1[154:154] = sram_blwl_wl[154:154] ; -wire [154:154] mux_1level_tapbuf_size2_144_configbus0_b; -assign mux_1level_tapbuf_size2_144_configbus0_b[154:154] = sram_blwl_blb[154:154] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_144_ (mux_1level_tapbuf_size2_144_inbus, chanx_1__1__out_88_ , mux_1level_tapbuf_size2_144_sram_blwl_out[154:154] , -mux_1level_tapbuf_size2_144_sram_blwl_outb[154:154] ); -//----- SRAM bits for MUX[144], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_154_ (mux_1level_tapbuf_size2_144_sram_blwl_out[154:154] ,mux_1level_tapbuf_size2_144_sram_blwl_out[154:154] ,mux_1level_tapbuf_size2_144_sram_blwl_outb[154:154] ,mux_1level_tapbuf_size2_144_configbus0[154:154], mux_1level_tapbuf_size2_144_configbus1[154:154] , mux_1level_tapbuf_size2_144_configbus0_b[154:154] ); -wire [0:1] mux_1level_tapbuf_size2_145_inbus; -assign mux_1level_tapbuf_size2_145_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_145_inbus[1] = chany_0__1__in_6_ ; -wire [155:155] mux_1level_tapbuf_size2_145_configbus0; -wire [155:155] mux_1level_tapbuf_size2_145_configbus1; -wire [155:155] mux_1level_tapbuf_size2_145_sram_blwl_out ; -wire [155:155] mux_1level_tapbuf_size2_145_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_145_configbus0[155:155] = sram_blwl_bl[155:155] ; -assign mux_1level_tapbuf_size2_145_configbus1[155:155] = sram_blwl_wl[155:155] ; -wire [155:155] mux_1level_tapbuf_size2_145_configbus0_b; -assign mux_1level_tapbuf_size2_145_configbus0_b[155:155] = sram_blwl_blb[155:155] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_145_ (mux_1level_tapbuf_size2_145_inbus, chanx_1__1__out_90_ , mux_1level_tapbuf_size2_145_sram_blwl_out[155:155] , -mux_1level_tapbuf_size2_145_sram_blwl_outb[155:155] ); -//----- SRAM bits for MUX[145], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_155_ (mux_1level_tapbuf_size2_145_sram_blwl_out[155:155] ,mux_1level_tapbuf_size2_145_sram_blwl_out[155:155] ,mux_1level_tapbuf_size2_145_sram_blwl_outb[155:155] ,mux_1level_tapbuf_size2_145_configbus0[155:155], mux_1level_tapbuf_size2_145_configbus1[155:155] , mux_1level_tapbuf_size2_145_configbus0_b[155:155] ); -wire [0:1] mux_1level_tapbuf_size2_146_inbus; -assign mux_1level_tapbuf_size2_146_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_146_inbus[1] = chany_0__1__in_4_ ; -wire [156:156] mux_1level_tapbuf_size2_146_configbus0; -wire [156:156] mux_1level_tapbuf_size2_146_configbus1; -wire [156:156] mux_1level_tapbuf_size2_146_sram_blwl_out ; -wire [156:156] mux_1level_tapbuf_size2_146_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_146_configbus0[156:156] = sram_blwl_bl[156:156] ; -assign mux_1level_tapbuf_size2_146_configbus1[156:156] = sram_blwl_wl[156:156] ; -wire [156:156] mux_1level_tapbuf_size2_146_configbus0_b; -assign mux_1level_tapbuf_size2_146_configbus0_b[156:156] = sram_blwl_blb[156:156] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_146_ (mux_1level_tapbuf_size2_146_inbus, chanx_1__1__out_92_ , mux_1level_tapbuf_size2_146_sram_blwl_out[156:156] , -mux_1level_tapbuf_size2_146_sram_blwl_outb[156:156] ); -//----- SRAM bits for MUX[146], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_156_ (mux_1level_tapbuf_size2_146_sram_blwl_out[156:156] ,mux_1level_tapbuf_size2_146_sram_blwl_out[156:156] ,mux_1level_tapbuf_size2_146_sram_blwl_outb[156:156] ,mux_1level_tapbuf_size2_146_configbus0[156:156], mux_1level_tapbuf_size2_146_configbus1[156:156] , mux_1level_tapbuf_size2_146_configbus0_b[156:156] ); -wire [0:1] mux_1level_tapbuf_size2_147_inbus; -assign mux_1level_tapbuf_size2_147_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_147_inbus[1] = chany_0__1__in_2_ ; -wire [157:157] mux_1level_tapbuf_size2_147_configbus0; -wire [157:157] mux_1level_tapbuf_size2_147_configbus1; -wire [157:157] mux_1level_tapbuf_size2_147_sram_blwl_out ; -wire [157:157] mux_1level_tapbuf_size2_147_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_147_configbus0[157:157] = sram_blwl_bl[157:157] ; -assign mux_1level_tapbuf_size2_147_configbus1[157:157] = sram_blwl_wl[157:157] ; -wire [157:157] mux_1level_tapbuf_size2_147_configbus0_b; -assign mux_1level_tapbuf_size2_147_configbus0_b[157:157] = sram_blwl_blb[157:157] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_147_ (mux_1level_tapbuf_size2_147_inbus, chanx_1__1__out_94_ , mux_1level_tapbuf_size2_147_sram_blwl_out[157:157] , -mux_1level_tapbuf_size2_147_sram_blwl_outb[157:157] ); -//----- SRAM bits for MUX[147], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_157_ (mux_1level_tapbuf_size2_147_sram_blwl_out[157:157] ,mux_1level_tapbuf_size2_147_sram_blwl_out[157:157] ,mux_1level_tapbuf_size2_147_sram_blwl_outb[157:157] ,mux_1level_tapbuf_size2_147_configbus0[157:157], mux_1level_tapbuf_size2_147_configbus1[157:157] , mux_1level_tapbuf_size2_147_configbus0_b[157:157] ); -wire [0:1] mux_1level_tapbuf_size2_148_inbus; -assign mux_1level_tapbuf_size2_148_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_148_inbus[1] = chany_0__1__in_0_ ; -wire [158:158] mux_1level_tapbuf_size2_148_configbus0; -wire [158:158] mux_1level_tapbuf_size2_148_configbus1; -wire [158:158] mux_1level_tapbuf_size2_148_sram_blwl_out ; -wire [158:158] mux_1level_tapbuf_size2_148_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_148_configbus0[158:158] = sram_blwl_bl[158:158] ; -assign mux_1level_tapbuf_size2_148_configbus1[158:158] = sram_blwl_wl[158:158] ; -wire [158:158] mux_1level_tapbuf_size2_148_configbus0_b; -assign mux_1level_tapbuf_size2_148_configbus0_b[158:158] = sram_blwl_blb[158:158] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_148_ (mux_1level_tapbuf_size2_148_inbus, chanx_1__1__out_96_ , mux_1level_tapbuf_size2_148_sram_blwl_out[158:158] , -mux_1level_tapbuf_size2_148_sram_blwl_outb[158:158] ); -//----- SRAM bits for MUX[148], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_158_ (mux_1level_tapbuf_size2_148_sram_blwl_out[158:158] ,mux_1level_tapbuf_size2_148_sram_blwl_out[158:158] ,mux_1level_tapbuf_size2_148_sram_blwl_outb[158:158] ,mux_1level_tapbuf_size2_148_configbus0[158:158], mux_1level_tapbuf_size2_148_configbus1[158:158] , mux_1level_tapbuf_size2_148_configbus0_b[158:158] ); -wire [0:1] mux_1level_tapbuf_size2_149_inbus; -assign mux_1level_tapbuf_size2_149_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_149_inbus[1] = chany_0__1__in_98_ ; -wire [159:159] mux_1level_tapbuf_size2_149_configbus0; -wire [159:159] mux_1level_tapbuf_size2_149_configbus1; -wire [159:159] mux_1level_tapbuf_size2_149_sram_blwl_out ; -wire [159:159] mux_1level_tapbuf_size2_149_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_149_configbus0[159:159] = sram_blwl_bl[159:159] ; -assign mux_1level_tapbuf_size2_149_configbus1[159:159] = sram_blwl_wl[159:159] ; -wire [159:159] mux_1level_tapbuf_size2_149_configbus0_b; -assign mux_1level_tapbuf_size2_149_configbus0_b[159:159] = sram_blwl_blb[159:159] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_149_ (mux_1level_tapbuf_size2_149_inbus, chanx_1__1__out_98_ , mux_1level_tapbuf_size2_149_sram_blwl_out[159:159] , -mux_1level_tapbuf_size2_149_sram_blwl_outb[159:159] ); -//----- SRAM bits for MUX[149], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_159_ (mux_1level_tapbuf_size2_149_sram_blwl_out[159:159] ,mux_1level_tapbuf_size2_149_sram_blwl_out[159:159] ,mux_1level_tapbuf_size2_149_sram_blwl_outb[159:159] ,mux_1level_tapbuf_size2_149_configbus0[159:159], mux_1level_tapbuf_size2_149_configbus1[159:159] , mux_1level_tapbuf_size2_149_configbus0_b[159:159] ); -//----- bottom side Multiplexers ----- -wire [0:1] mux_1level_tapbuf_size2_150_inbus; -assign mux_1level_tapbuf_size2_150_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_150_inbus[1] = chanx_1__1__in_97_ ; -wire [160:160] mux_1level_tapbuf_size2_150_configbus0; -wire [160:160] mux_1level_tapbuf_size2_150_configbus1; -wire [160:160] mux_1level_tapbuf_size2_150_sram_blwl_out ; -wire [160:160] mux_1level_tapbuf_size2_150_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_150_configbus0[160:160] = sram_blwl_bl[160:160] ; -assign mux_1level_tapbuf_size2_150_configbus1[160:160] = sram_blwl_wl[160:160] ; -wire [160:160] mux_1level_tapbuf_size2_150_configbus0_b; -assign mux_1level_tapbuf_size2_150_configbus0_b[160:160] = sram_blwl_blb[160:160] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_150_ (mux_1level_tapbuf_size2_150_inbus, chany_0__1__out_1_ , mux_1level_tapbuf_size2_150_sram_blwl_out[160:160] , -mux_1level_tapbuf_size2_150_sram_blwl_outb[160:160] ); -//----- SRAM bits for MUX[150], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_160_ (mux_1level_tapbuf_size2_150_sram_blwl_out[160:160] ,mux_1level_tapbuf_size2_150_sram_blwl_out[160:160] ,mux_1level_tapbuf_size2_150_sram_blwl_outb[160:160] ,mux_1level_tapbuf_size2_150_configbus0[160:160], mux_1level_tapbuf_size2_150_configbus1[160:160] , mux_1level_tapbuf_size2_150_configbus0_b[160:160] ); -wire [0:1] mux_1level_tapbuf_size2_151_inbus; -assign mux_1level_tapbuf_size2_151_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_151_inbus[1] = chanx_1__1__in_95_ ; -wire [161:161] mux_1level_tapbuf_size2_151_configbus0; -wire [161:161] mux_1level_tapbuf_size2_151_configbus1; -wire [161:161] mux_1level_tapbuf_size2_151_sram_blwl_out ; -wire [161:161] mux_1level_tapbuf_size2_151_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_151_configbus0[161:161] = sram_blwl_bl[161:161] ; -assign mux_1level_tapbuf_size2_151_configbus1[161:161] = sram_blwl_wl[161:161] ; -wire [161:161] mux_1level_tapbuf_size2_151_configbus0_b; -assign mux_1level_tapbuf_size2_151_configbus0_b[161:161] = sram_blwl_blb[161:161] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_151_ (mux_1level_tapbuf_size2_151_inbus, chany_0__1__out_3_ , mux_1level_tapbuf_size2_151_sram_blwl_out[161:161] , -mux_1level_tapbuf_size2_151_sram_blwl_outb[161:161] ); -//----- SRAM bits for MUX[151], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_161_ (mux_1level_tapbuf_size2_151_sram_blwl_out[161:161] ,mux_1level_tapbuf_size2_151_sram_blwl_out[161:161] ,mux_1level_tapbuf_size2_151_sram_blwl_outb[161:161] ,mux_1level_tapbuf_size2_151_configbus0[161:161], mux_1level_tapbuf_size2_151_configbus1[161:161] , mux_1level_tapbuf_size2_151_configbus0_b[161:161] ); -wire [0:1] mux_1level_tapbuf_size2_152_inbus; -assign mux_1level_tapbuf_size2_152_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_152_inbus[1] = chanx_1__1__in_93_ ; -wire [162:162] mux_1level_tapbuf_size2_152_configbus0; -wire [162:162] mux_1level_tapbuf_size2_152_configbus1; -wire [162:162] mux_1level_tapbuf_size2_152_sram_blwl_out ; -wire [162:162] mux_1level_tapbuf_size2_152_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_152_configbus0[162:162] = sram_blwl_bl[162:162] ; -assign mux_1level_tapbuf_size2_152_configbus1[162:162] = sram_blwl_wl[162:162] ; -wire [162:162] mux_1level_tapbuf_size2_152_configbus0_b; -assign mux_1level_tapbuf_size2_152_configbus0_b[162:162] = sram_blwl_blb[162:162] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_152_ (mux_1level_tapbuf_size2_152_inbus, chany_0__1__out_5_ , mux_1level_tapbuf_size2_152_sram_blwl_out[162:162] , -mux_1level_tapbuf_size2_152_sram_blwl_outb[162:162] ); -//----- SRAM bits for MUX[152], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_162_ (mux_1level_tapbuf_size2_152_sram_blwl_out[162:162] ,mux_1level_tapbuf_size2_152_sram_blwl_out[162:162] ,mux_1level_tapbuf_size2_152_sram_blwl_outb[162:162] ,mux_1level_tapbuf_size2_152_configbus0[162:162], mux_1level_tapbuf_size2_152_configbus1[162:162] , mux_1level_tapbuf_size2_152_configbus0_b[162:162] ); -wire [0:1] mux_1level_tapbuf_size2_153_inbus; -assign mux_1level_tapbuf_size2_153_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_153_inbus[1] = chanx_1__1__in_91_ ; -wire [163:163] mux_1level_tapbuf_size2_153_configbus0; -wire [163:163] mux_1level_tapbuf_size2_153_configbus1; -wire [163:163] mux_1level_tapbuf_size2_153_sram_blwl_out ; -wire [163:163] mux_1level_tapbuf_size2_153_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_153_configbus0[163:163] = sram_blwl_bl[163:163] ; -assign mux_1level_tapbuf_size2_153_configbus1[163:163] = sram_blwl_wl[163:163] ; -wire [163:163] mux_1level_tapbuf_size2_153_configbus0_b; -assign mux_1level_tapbuf_size2_153_configbus0_b[163:163] = sram_blwl_blb[163:163] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_153_ (mux_1level_tapbuf_size2_153_inbus, chany_0__1__out_7_ , mux_1level_tapbuf_size2_153_sram_blwl_out[163:163] , -mux_1level_tapbuf_size2_153_sram_blwl_outb[163:163] ); -//----- SRAM bits for MUX[153], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_163_ (mux_1level_tapbuf_size2_153_sram_blwl_out[163:163] ,mux_1level_tapbuf_size2_153_sram_blwl_out[163:163] ,mux_1level_tapbuf_size2_153_sram_blwl_outb[163:163] ,mux_1level_tapbuf_size2_153_configbus0[163:163], mux_1level_tapbuf_size2_153_configbus1[163:163] , mux_1level_tapbuf_size2_153_configbus0_b[163:163] ); -wire [0:1] mux_1level_tapbuf_size2_154_inbus; -assign mux_1level_tapbuf_size2_154_inbus[0] = grid_0__1__pin_0__1__1_; -assign mux_1level_tapbuf_size2_154_inbus[1] = chanx_1__1__in_89_ ; -wire [164:164] mux_1level_tapbuf_size2_154_configbus0; -wire [164:164] mux_1level_tapbuf_size2_154_configbus1; -wire [164:164] mux_1level_tapbuf_size2_154_sram_blwl_out ; -wire [164:164] mux_1level_tapbuf_size2_154_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_154_configbus0[164:164] = sram_blwl_bl[164:164] ; -assign mux_1level_tapbuf_size2_154_configbus1[164:164] = sram_blwl_wl[164:164] ; -wire [164:164] mux_1level_tapbuf_size2_154_configbus0_b; -assign mux_1level_tapbuf_size2_154_configbus0_b[164:164] = sram_blwl_blb[164:164] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_154_ (mux_1level_tapbuf_size2_154_inbus, chany_0__1__out_9_ , mux_1level_tapbuf_size2_154_sram_blwl_out[164:164] , -mux_1level_tapbuf_size2_154_sram_blwl_outb[164:164] ); -//----- SRAM bits for MUX[154], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_164_ (mux_1level_tapbuf_size2_154_sram_blwl_out[164:164] ,mux_1level_tapbuf_size2_154_sram_blwl_out[164:164] ,mux_1level_tapbuf_size2_154_sram_blwl_outb[164:164] ,mux_1level_tapbuf_size2_154_configbus0[164:164], mux_1level_tapbuf_size2_154_configbus1[164:164] , mux_1level_tapbuf_size2_154_configbus0_b[164:164] ); -wire [0:1] mux_1level_tapbuf_size2_155_inbus; -assign mux_1level_tapbuf_size2_155_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_155_inbus[1] = chanx_1__1__in_87_ ; -wire [165:165] mux_1level_tapbuf_size2_155_configbus0; -wire [165:165] mux_1level_tapbuf_size2_155_configbus1; -wire [165:165] mux_1level_tapbuf_size2_155_sram_blwl_out ; -wire [165:165] mux_1level_tapbuf_size2_155_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_155_configbus0[165:165] = sram_blwl_bl[165:165] ; -assign mux_1level_tapbuf_size2_155_configbus1[165:165] = sram_blwl_wl[165:165] ; -wire [165:165] mux_1level_tapbuf_size2_155_configbus0_b; -assign mux_1level_tapbuf_size2_155_configbus0_b[165:165] = sram_blwl_blb[165:165] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_155_ (mux_1level_tapbuf_size2_155_inbus, chany_0__1__out_11_ , mux_1level_tapbuf_size2_155_sram_blwl_out[165:165] , -mux_1level_tapbuf_size2_155_sram_blwl_outb[165:165] ); -//----- SRAM bits for MUX[155], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_165_ (mux_1level_tapbuf_size2_155_sram_blwl_out[165:165] ,mux_1level_tapbuf_size2_155_sram_blwl_out[165:165] ,mux_1level_tapbuf_size2_155_sram_blwl_outb[165:165] ,mux_1level_tapbuf_size2_155_configbus0[165:165], mux_1level_tapbuf_size2_155_configbus1[165:165] , mux_1level_tapbuf_size2_155_configbus0_b[165:165] ); -wire [0:1] mux_1level_tapbuf_size2_156_inbus; -assign mux_1level_tapbuf_size2_156_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_156_inbus[1] = chanx_1__1__in_85_ ; -wire [166:166] mux_1level_tapbuf_size2_156_configbus0; -wire [166:166] mux_1level_tapbuf_size2_156_configbus1; -wire [166:166] mux_1level_tapbuf_size2_156_sram_blwl_out ; -wire [166:166] mux_1level_tapbuf_size2_156_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_156_configbus0[166:166] = sram_blwl_bl[166:166] ; -assign mux_1level_tapbuf_size2_156_configbus1[166:166] = sram_blwl_wl[166:166] ; -wire [166:166] mux_1level_tapbuf_size2_156_configbus0_b; -assign mux_1level_tapbuf_size2_156_configbus0_b[166:166] = sram_blwl_blb[166:166] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_156_ (mux_1level_tapbuf_size2_156_inbus, chany_0__1__out_13_ , mux_1level_tapbuf_size2_156_sram_blwl_out[166:166] , -mux_1level_tapbuf_size2_156_sram_blwl_outb[166:166] ); -//----- SRAM bits for MUX[156], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_166_ (mux_1level_tapbuf_size2_156_sram_blwl_out[166:166] ,mux_1level_tapbuf_size2_156_sram_blwl_out[166:166] ,mux_1level_tapbuf_size2_156_sram_blwl_outb[166:166] ,mux_1level_tapbuf_size2_156_configbus0[166:166], mux_1level_tapbuf_size2_156_configbus1[166:166] , mux_1level_tapbuf_size2_156_configbus0_b[166:166] ); -wire [0:1] mux_1level_tapbuf_size2_157_inbus; -assign mux_1level_tapbuf_size2_157_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_157_inbus[1] = chanx_1__1__in_83_ ; -wire [167:167] mux_1level_tapbuf_size2_157_configbus0; -wire [167:167] mux_1level_tapbuf_size2_157_configbus1; -wire [167:167] mux_1level_tapbuf_size2_157_sram_blwl_out ; -wire [167:167] mux_1level_tapbuf_size2_157_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_157_configbus0[167:167] = sram_blwl_bl[167:167] ; -assign mux_1level_tapbuf_size2_157_configbus1[167:167] = sram_blwl_wl[167:167] ; -wire [167:167] mux_1level_tapbuf_size2_157_configbus0_b; -assign mux_1level_tapbuf_size2_157_configbus0_b[167:167] = sram_blwl_blb[167:167] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_157_ (mux_1level_tapbuf_size2_157_inbus, chany_0__1__out_15_ , mux_1level_tapbuf_size2_157_sram_blwl_out[167:167] , -mux_1level_tapbuf_size2_157_sram_blwl_outb[167:167] ); -//----- SRAM bits for MUX[157], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_167_ (mux_1level_tapbuf_size2_157_sram_blwl_out[167:167] ,mux_1level_tapbuf_size2_157_sram_blwl_out[167:167] ,mux_1level_tapbuf_size2_157_sram_blwl_outb[167:167] ,mux_1level_tapbuf_size2_157_configbus0[167:167], mux_1level_tapbuf_size2_157_configbus1[167:167] , mux_1level_tapbuf_size2_157_configbus0_b[167:167] ); -wire [0:1] mux_1level_tapbuf_size2_158_inbus; -assign mux_1level_tapbuf_size2_158_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_158_inbus[1] = chanx_1__1__in_81_ ; -wire [168:168] mux_1level_tapbuf_size2_158_configbus0; -wire [168:168] mux_1level_tapbuf_size2_158_configbus1; -wire [168:168] mux_1level_tapbuf_size2_158_sram_blwl_out ; -wire [168:168] mux_1level_tapbuf_size2_158_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_158_configbus0[168:168] = sram_blwl_bl[168:168] ; -assign mux_1level_tapbuf_size2_158_configbus1[168:168] = sram_blwl_wl[168:168] ; -wire [168:168] mux_1level_tapbuf_size2_158_configbus0_b; -assign mux_1level_tapbuf_size2_158_configbus0_b[168:168] = sram_blwl_blb[168:168] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_158_ (mux_1level_tapbuf_size2_158_inbus, chany_0__1__out_17_ , mux_1level_tapbuf_size2_158_sram_blwl_out[168:168] , -mux_1level_tapbuf_size2_158_sram_blwl_outb[168:168] ); -//----- SRAM bits for MUX[158], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_168_ (mux_1level_tapbuf_size2_158_sram_blwl_out[168:168] ,mux_1level_tapbuf_size2_158_sram_blwl_out[168:168] ,mux_1level_tapbuf_size2_158_sram_blwl_outb[168:168] ,mux_1level_tapbuf_size2_158_configbus0[168:168], mux_1level_tapbuf_size2_158_configbus1[168:168] , mux_1level_tapbuf_size2_158_configbus0_b[168:168] ); -wire [0:1] mux_1level_tapbuf_size2_159_inbus; -assign mux_1level_tapbuf_size2_159_inbus[0] = grid_0__1__pin_0__1__3_; -assign mux_1level_tapbuf_size2_159_inbus[1] = chanx_1__1__in_79_ ; -wire [169:169] mux_1level_tapbuf_size2_159_configbus0; -wire [169:169] mux_1level_tapbuf_size2_159_configbus1; -wire [169:169] mux_1level_tapbuf_size2_159_sram_blwl_out ; -wire [169:169] mux_1level_tapbuf_size2_159_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_159_configbus0[169:169] = sram_blwl_bl[169:169] ; -assign mux_1level_tapbuf_size2_159_configbus1[169:169] = sram_blwl_wl[169:169] ; -wire [169:169] mux_1level_tapbuf_size2_159_configbus0_b; -assign mux_1level_tapbuf_size2_159_configbus0_b[169:169] = sram_blwl_blb[169:169] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_159_ (mux_1level_tapbuf_size2_159_inbus, chany_0__1__out_19_ , mux_1level_tapbuf_size2_159_sram_blwl_out[169:169] , -mux_1level_tapbuf_size2_159_sram_blwl_outb[169:169] ); -//----- SRAM bits for MUX[159], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_169_ (mux_1level_tapbuf_size2_159_sram_blwl_out[169:169] ,mux_1level_tapbuf_size2_159_sram_blwl_out[169:169] ,mux_1level_tapbuf_size2_159_sram_blwl_outb[169:169] ,mux_1level_tapbuf_size2_159_configbus0[169:169], mux_1level_tapbuf_size2_159_configbus1[169:169] , mux_1level_tapbuf_size2_159_configbus0_b[169:169] ); -wire [0:1] mux_1level_tapbuf_size2_160_inbus; -assign mux_1level_tapbuf_size2_160_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_160_inbus[1] = chanx_1__1__in_77_ ; -wire [170:170] mux_1level_tapbuf_size2_160_configbus0; -wire [170:170] mux_1level_tapbuf_size2_160_configbus1; -wire [170:170] mux_1level_tapbuf_size2_160_sram_blwl_out ; -wire [170:170] mux_1level_tapbuf_size2_160_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_160_configbus0[170:170] = sram_blwl_bl[170:170] ; -assign mux_1level_tapbuf_size2_160_configbus1[170:170] = sram_blwl_wl[170:170] ; -wire [170:170] mux_1level_tapbuf_size2_160_configbus0_b; -assign mux_1level_tapbuf_size2_160_configbus0_b[170:170] = sram_blwl_blb[170:170] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_160_ (mux_1level_tapbuf_size2_160_inbus, chany_0__1__out_21_ , mux_1level_tapbuf_size2_160_sram_blwl_out[170:170] , -mux_1level_tapbuf_size2_160_sram_blwl_outb[170:170] ); -//----- SRAM bits for MUX[160], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_170_ (mux_1level_tapbuf_size2_160_sram_blwl_out[170:170] ,mux_1level_tapbuf_size2_160_sram_blwl_out[170:170] ,mux_1level_tapbuf_size2_160_sram_blwl_outb[170:170] ,mux_1level_tapbuf_size2_160_configbus0[170:170], mux_1level_tapbuf_size2_160_configbus1[170:170] , mux_1level_tapbuf_size2_160_configbus0_b[170:170] ); -wire [0:1] mux_1level_tapbuf_size2_161_inbus; -assign mux_1level_tapbuf_size2_161_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_161_inbus[1] = chanx_1__1__in_75_ ; -wire [171:171] mux_1level_tapbuf_size2_161_configbus0; -wire [171:171] mux_1level_tapbuf_size2_161_configbus1; -wire [171:171] mux_1level_tapbuf_size2_161_sram_blwl_out ; -wire [171:171] mux_1level_tapbuf_size2_161_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_161_configbus0[171:171] = sram_blwl_bl[171:171] ; -assign mux_1level_tapbuf_size2_161_configbus1[171:171] = sram_blwl_wl[171:171] ; -wire [171:171] mux_1level_tapbuf_size2_161_configbus0_b; -assign mux_1level_tapbuf_size2_161_configbus0_b[171:171] = sram_blwl_blb[171:171] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_161_ (mux_1level_tapbuf_size2_161_inbus, chany_0__1__out_23_ , mux_1level_tapbuf_size2_161_sram_blwl_out[171:171] , -mux_1level_tapbuf_size2_161_sram_blwl_outb[171:171] ); -//----- SRAM bits for MUX[161], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_171_ (mux_1level_tapbuf_size2_161_sram_blwl_out[171:171] ,mux_1level_tapbuf_size2_161_sram_blwl_out[171:171] ,mux_1level_tapbuf_size2_161_sram_blwl_outb[171:171] ,mux_1level_tapbuf_size2_161_configbus0[171:171], mux_1level_tapbuf_size2_161_configbus1[171:171] , mux_1level_tapbuf_size2_161_configbus0_b[171:171] ); -wire [0:1] mux_1level_tapbuf_size2_162_inbus; -assign mux_1level_tapbuf_size2_162_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_162_inbus[1] = chanx_1__1__in_73_ ; -wire [172:172] mux_1level_tapbuf_size2_162_configbus0; -wire [172:172] mux_1level_tapbuf_size2_162_configbus1; -wire [172:172] mux_1level_tapbuf_size2_162_sram_blwl_out ; -wire [172:172] mux_1level_tapbuf_size2_162_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_162_configbus0[172:172] = sram_blwl_bl[172:172] ; -assign mux_1level_tapbuf_size2_162_configbus1[172:172] = sram_blwl_wl[172:172] ; -wire [172:172] mux_1level_tapbuf_size2_162_configbus0_b; -assign mux_1level_tapbuf_size2_162_configbus0_b[172:172] = sram_blwl_blb[172:172] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_162_ (mux_1level_tapbuf_size2_162_inbus, chany_0__1__out_25_ , mux_1level_tapbuf_size2_162_sram_blwl_out[172:172] , -mux_1level_tapbuf_size2_162_sram_blwl_outb[172:172] ); -//----- SRAM bits for MUX[162], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_172_ (mux_1level_tapbuf_size2_162_sram_blwl_out[172:172] ,mux_1level_tapbuf_size2_162_sram_blwl_out[172:172] ,mux_1level_tapbuf_size2_162_sram_blwl_outb[172:172] ,mux_1level_tapbuf_size2_162_configbus0[172:172], mux_1level_tapbuf_size2_162_configbus1[172:172] , mux_1level_tapbuf_size2_162_configbus0_b[172:172] ); -wire [0:1] mux_1level_tapbuf_size2_163_inbus; -assign mux_1level_tapbuf_size2_163_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_163_inbus[1] = chanx_1__1__in_71_ ; -wire [173:173] mux_1level_tapbuf_size2_163_configbus0; -wire [173:173] mux_1level_tapbuf_size2_163_configbus1; -wire [173:173] mux_1level_tapbuf_size2_163_sram_blwl_out ; -wire [173:173] mux_1level_tapbuf_size2_163_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_163_configbus0[173:173] = sram_blwl_bl[173:173] ; -assign mux_1level_tapbuf_size2_163_configbus1[173:173] = sram_blwl_wl[173:173] ; -wire [173:173] mux_1level_tapbuf_size2_163_configbus0_b; -assign mux_1level_tapbuf_size2_163_configbus0_b[173:173] = sram_blwl_blb[173:173] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_163_ (mux_1level_tapbuf_size2_163_inbus, chany_0__1__out_27_ , mux_1level_tapbuf_size2_163_sram_blwl_out[173:173] , -mux_1level_tapbuf_size2_163_sram_blwl_outb[173:173] ); -//----- SRAM bits for MUX[163], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_173_ (mux_1level_tapbuf_size2_163_sram_blwl_out[173:173] ,mux_1level_tapbuf_size2_163_sram_blwl_out[173:173] ,mux_1level_tapbuf_size2_163_sram_blwl_outb[173:173] ,mux_1level_tapbuf_size2_163_configbus0[173:173], mux_1level_tapbuf_size2_163_configbus1[173:173] , mux_1level_tapbuf_size2_163_configbus0_b[173:173] ); -wire [0:1] mux_1level_tapbuf_size2_164_inbus; -assign mux_1level_tapbuf_size2_164_inbus[0] = grid_0__1__pin_0__1__5_; -assign mux_1level_tapbuf_size2_164_inbus[1] = chanx_1__1__in_69_ ; -wire [174:174] mux_1level_tapbuf_size2_164_configbus0; -wire [174:174] mux_1level_tapbuf_size2_164_configbus1; -wire [174:174] mux_1level_tapbuf_size2_164_sram_blwl_out ; -wire [174:174] mux_1level_tapbuf_size2_164_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_164_configbus0[174:174] = sram_blwl_bl[174:174] ; -assign mux_1level_tapbuf_size2_164_configbus1[174:174] = sram_blwl_wl[174:174] ; -wire [174:174] mux_1level_tapbuf_size2_164_configbus0_b; -assign mux_1level_tapbuf_size2_164_configbus0_b[174:174] = sram_blwl_blb[174:174] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_164_ (mux_1level_tapbuf_size2_164_inbus, chany_0__1__out_29_ , mux_1level_tapbuf_size2_164_sram_blwl_out[174:174] , -mux_1level_tapbuf_size2_164_sram_blwl_outb[174:174] ); -//----- SRAM bits for MUX[164], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_174_ (mux_1level_tapbuf_size2_164_sram_blwl_out[174:174] ,mux_1level_tapbuf_size2_164_sram_blwl_out[174:174] ,mux_1level_tapbuf_size2_164_sram_blwl_outb[174:174] ,mux_1level_tapbuf_size2_164_configbus0[174:174], mux_1level_tapbuf_size2_164_configbus1[174:174] , mux_1level_tapbuf_size2_164_configbus0_b[174:174] ); -wire [0:1] mux_1level_tapbuf_size2_165_inbus; -assign mux_1level_tapbuf_size2_165_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_165_inbus[1] = chanx_1__1__in_67_ ; -wire [175:175] mux_1level_tapbuf_size2_165_configbus0; -wire [175:175] mux_1level_tapbuf_size2_165_configbus1; -wire [175:175] mux_1level_tapbuf_size2_165_sram_blwl_out ; -wire [175:175] mux_1level_tapbuf_size2_165_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_165_configbus0[175:175] = sram_blwl_bl[175:175] ; -assign mux_1level_tapbuf_size2_165_configbus1[175:175] = sram_blwl_wl[175:175] ; -wire [175:175] mux_1level_tapbuf_size2_165_configbus0_b; -assign mux_1level_tapbuf_size2_165_configbus0_b[175:175] = sram_blwl_blb[175:175] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_165_ (mux_1level_tapbuf_size2_165_inbus, chany_0__1__out_31_ , mux_1level_tapbuf_size2_165_sram_blwl_out[175:175] , -mux_1level_tapbuf_size2_165_sram_blwl_outb[175:175] ); -//----- SRAM bits for MUX[165], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_175_ (mux_1level_tapbuf_size2_165_sram_blwl_out[175:175] ,mux_1level_tapbuf_size2_165_sram_blwl_out[175:175] ,mux_1level_tapbuf_size2_165_sram_blwl_outb[175:175] ,mux_1level_tapbuf_size2_165_configbus0[175:175], mux_1level_tapbuf_size2_165_configbus1[175:175] , mux_1level_tapbuf_size2_165_configbus0_b[175:175] ); -wire [0:1] mux_1level_tapbuf_size2_166_inbus; -assign mux_1level_tapbuf_size2_166_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_166_inbus[1] = chanx_1__1__in_65_ ; -wire [176:176] mux_1level_tapbuf_size2_166_configbus0; -wire [176:176] mux_1level_tapbuf_size2_166_configbus1; -wire [176:176] mux_1level_tapbuf_size2_166_sram_blwl_out ; -wire [176:176] mux_1level_tapbuf_size2_166_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_166_configbus0[176:176] = sram_blwl_bl[176:176] ; -assign mux_1level_tapbuf_size2_166_configbus1[176:176] = sram_blwl_wl[176:176] ; -wire [176:176] mux_1level_tapbuf_size2_166_configbus0_b; -assign mux_1level_tapbuf_size2_166_configbus0_b[176:176] = sram_blwl_blb[176:176] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_166_ (mux_1level_tapbuf_size2_166_inbus, chany_0__1__out_33_ , mux_1level_tapbuf_size2_166_sram_blwl_out[176:176] , -mux_1level_tapbuf_size2_166_sram_blwl_outb[176:176] ); -//----- SRAM bits for MUX[166], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_176_ (mux_1level_tapbuf_size2_166_sram_blwl_out[176:176] ,mux_1level_tapbuf_size2_166_sram_blwl_out[176:176] ,mux_1level_tapbuf_size2_166_sram_blwl_outb[176:176] ,mux_1level_tapbuf_size2_166_configbus0[176:176], mux_1level_tapbuf_size2_166_configbus1[176:176] , mux_1level_tapbuf_size2_166_configbus0_b[176:176] ); -wire [0:1] mux_1level_tapbuf_size2_167_inbus; -assign mux_1level_tapbuf_size2_167_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_167_inbus[1] = chanx_1__1__in_63_ ; -wire [177:177] mux_1level_tapbuf_size2_167_configbus0; -wire [177:177] mux_1level_tapbuf_size2_167_configbus1; -wire [177:177] mux_1level_tapbuf_size2_167_sram_blwl_out ; -wire [177:177] mux_1level_tapbuf_size2_167_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_167_configbus0[177:177] = sram_blwl_bl[177:177] ; -assign mux_1level_tapbuf_size2_167_configbus1[177:177] = sram_blwl_wl[177:177] ; -wire [177:177] mux_1level_tapbuf_size2_167_configbus0_b; -assign mux_1level_tapbuf_size2_167_configbus0_b[177:177] = sram_blwl_blb[177:177] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_167_ (mux_1level_tapbuf_size2_167_inbus, chany_0__1__out_35_ , mux_1level_tapbuf_size2_167_sram_blwl_out[177:177] , -mux_1level_tapbuf_size2_167_sram_blwl_outb[177:177] ); -//----- SRAM bits for MUX[167], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_177_ (mux_1level_tapbuf_size2_167_sram_blwl_out[177:177] ,mux_1level_tapbuf_size2_167_sram_blwl_out[177:177] ,mux_1level_tapbuf_size2_167_sram_blwl_outb[177:177] ,mux_1level_tapbuf_size2_167_configbus0[177:177], mux_1level_tapbuf_size2_167_configbus1[177:177] , mux_1level_tapbuf_size2_167_configbus0_b[177:177] ); -wire [0:1] mux_1level_tapbuf_size2_168_inbus; -assign mux_1level_tapbuf_size2_168_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_168_inbus[1] = chanx_1__1__in_61_ ; -wire [178:178] mux_1level_tapbuf_size2_168_configbus0; -wire [178:178] mux_1level_tapbuf_size2_168_configbus1; -wire [178:178] mux_1level_tapbuf_size2_168_sram_blwl_out ; -wire [178:178] mux_1level_tapbuf_size2_168_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_168_configbus0[178:178] = sram_blwl_bl[178:178] ; -assign mux_1level_tapbuf_size2_168_configbus1[178:178] = sram_blwl_wl[178:178] ; -wire [178:178] mux_1level_tapbuf_size2_168_configbus0_b; -assign mux_1level_tapbuf_size2_168_configbus0_b[178:178] = sram_blwl_blb[178:178] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_168_ (mux_1level_tapbuf_size2_168_inbus, chany_0__1__out_37_ , mux_1level_tapbuf_size2_168_sram_blwl_out[178:178] , -mux_1level_tapbuf_size2_168_sram_blwl_outb[178:178] ); -//----- SRAM bits for MUX[168], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_178_ (mux_1level_tapbuf_size2_168_sram_blwl_out[178:178] ,mux_1level_tapbuf_size2_168_sram_blwl_out[178:178] ,mux_1level_tapbuf_size2_168_sram_blwl_outb[178:178] ,mux_1level_tapbuf_size2_168_configbus0[178:178], mux_1level_tapbuf_size2_168_configbus1[178:178] , mux_1level_tapbuf_size2_168_configbus0_b[178:178] ); -wire [0:1] mux_1level_tapbuf_size2_169_inbus; -assign mux_1level_tapbuf_size2_169_inbus[0] = grid_0__1__pin_0__1__7_; -assign mux_1level_tapbuf_size2_169_inbus[1] = chanx_1__1__in_59_ ; -wire [179:179] mux_1level_tapbuf_size2_169_configbus0; -wire [179:179] mux_1level_tapbuf_size2_169_configbus1; -wire [179:179] mux_1level_tapbuf_size2_169_sram_blwl_out ; -wire [179:179] mux_1level_tapbuf_size2_169_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_169_configbus0[179:179] = sram_blwl_bl[179:179] ; -assign mux_1level_tapbuf_size2_169_configbus1[179:179] = sram_blwl_wl[179:179] ; -wire [179:179] mux_1level_tapbuf_size2_169_configbus0_b; -assign mux_1level_tapbuf_size2_169_configbus0_b[179:179] = sram_blwl_blb[179:179] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_169_ (mux_1level_tapbuf_size2_169_inbus, chany_0__1__out_39_ , mux_1level_tapbuf_size2_169_sram_blwl_out[179:179] , -mux_1level_tapbuf_size2_169_sram_blwl_outb[179:179] ); -//----- SRAM bits for MUX[169], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_179_ (mux_1level_tapbuf_size2_169_sram_blwl_out[179:179] ,mux_1level_tapbuf_size2_169_sram_blwl_out[179:179] ,mux_1level_tapbuf_size2_169_sram_blwl_outb[179:179] ,mux_1level_tapbuf_size2_169_configbus0[179:179], mux_1level_tapbuf_size2_169_configbus1[179:179] , mux_1level_tapbuf_size2_169_configbus0_b[179:179] ); -wire [0:1] mux_1level_tapbuf_size2_170_inbus; -assign mux_1level_tapbuf_size2_170_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_170_inbus[1] = chanx_1__1__in_57_ ; -wire [180:180] mux_1level_tapbuf_size2_170_configbus0; -wire [180:180] mux_1level_tapbuf_size2_170_configbus1; -wire [180:180] mux_1level_tapbuf_size2_170_sram_blwl_out ; -wire [180:180] mux_1level_tapbuf_size2_170_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_170_configbus0[180:180] = sram_blwl_bl[180:180] ; -assign mux_1level_tapbuf_size2_170_configbus1[180:180] = sram_blwl_wl[180:180] ; -wire [180:180] mux_1level_tapbuf_size2_170_configbus0_b; -assign mux_1level_tapbuf_size2_170_configbus0_b[180:180] = sram_blwl_blb[180:180] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_170_ (mux_1level_tapbuf_size2_170_inbus, chany_0__1__out_41_ , mux_1level_tapbuf_size2_170_sram_blwl_out[180:180] , -mux_1level_tapbuf_size2_170_sram_blwl_outb[180:180] ); -//----- SRAM bits for MUX[170], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_180_ (mux_1level_tapbuf_size2_170_sram_blwl_out[180:180] ,mux_1level_tapbuf_size2_170_sram_blwl_out[180:180] ,mux_1level_tapbuf_size2_170_sram_blwl_outb[180:180] ,mux_1level_tapbuf_size2_170_configbus0[180:180], mux_1level_tapbuf_size2_170_configbus1[180:180] , mux_1level_tapbuf_size2_170_configbus0_b[180:180] ); -wire [0:1] mux_1level_tapbuf_size2_171_inbus; -assign mux_1level_tapbuf_size2_171_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_171_inbus[1] = chanx_1__1__in_55_ ; -wire [181:181] mux_1level_tapbuf_size2_171_configbus0; -wire [181:181] mux_1level_tapbuf_size2_171_configbus1; -wire [181:181] mux_1level_tapbuf_size2_171_sram_blwl_out ; -wire [181:181] mux_1level_tapbuf_size2_171_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_171_configbus0[181:181] = sram_blwl_bl[181:181] ; -assign mux_1level_tapbuf_size2_171_configbus1[181:181] = sram_blwl_wl[181:181] ; -wire [181:181] mux_1level_tapbuf_size2_171_configbus0_b; -assign mux_1level_tapbuf_size2_171_configbus0_b[181:181] = sram_blwl_blb[181:181] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_171_ (mux_1level_tapbuf_size2_171_inbus, chany_0__1__out_43_ , mux_1level_tapbuf_size2_171_sram_blwl_out[181:181] , -mux_1level_tapbuf_size2_171_sram_blwl_outb[181:181] ); -//----- SRAM bits for MUX[171], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_181_ (mux_1level_tapbuf_size2_171_sram_blwl_out[181:181] ,mux_1level_tapbuf_size2_171_sram_blwl_out[181:181] ,mux_1level_tapbuf_size2_171_sram_blwl_outb[181:181] ,mux_1level_tapbuf_size2_171_configbus0[181:181], mux_1level_tapbuf_size2_171_configbus1[181:181] , mux_1level_tapbuf_size2_171_configbus0_b[181:181] ); -wire [0:1] mux_1level_tapbuf_size2_172_inbus; -assign mux_1level_tapbuf_size2_172_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_172_inbus[1] = chanx_1__1__in_53_ ; -wire [182:182] mux_1level_tapbuf_size2_172_configbus0; -wire [182:182] mux_1level_tapbuf_size2_172_configbus1; -wire [182:182] mux_1level_tapbuf_size2_172_sram_blwl_out ; -wire [182:182] mux_1level_tapbuf_size2_172_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_172_configbus0[182:182] = sram_blwl_bl[182:182] ; -assign mux_1level_tapbuf_size2_172_configbus1[182:182] = sram_blwl_wl[182:182] ; -wire [182:182] mux_1level_tapbuf_size2_172_configbus0_b; -assign mux_1level_tapbuf_size2_172_configbus0_b[182:182] = sram_blwl_blb[182:182] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_172_ (mux_1level_tapbuf_size2_172_inbus, chany_0__1__out_45_ , mux_1level_tapbuf_size2_172_sram_blwl_out[182:182] , -mux_1level_tapbuf_size2_172_sram_blwl_outb[182:182] ); -//----- SRAM bits for MUX[172], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_182_ (mux_1level_tapbuf_size2_172_sram_blwl_out[182:182] ,mux_1level_tapbuf_size2_172_sram_blwl_out[182:182] ,mux_1level_tapbuf_size2_172_sram_blwl_outb[182:182] ,mux_1level_tapbuf_size2_172_configbus0[182:182], mux_1level_tapbuf_size2_172_configbus1[182:182] , mux_1level_tapbuf_size2_172_configbus0_b[182:182] ); -wire [0:1] mux_1level_tapbuf_size2_173_inbus; -assign mux_1level_tapbuf_size2_173_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_173_inbus[1] = chanx_1__1__in_51_ ; -wire [183:183] mux_1level_tapbuf_size2_173_configbus0; -wire [183:183] mux_1level_tapbuf_size2_173_configbus1; -wire [183:183] mux_1level_tapbuf_size2_173_sram_blwl_out ; -wire [183:183] mux_1level_tapbuf_size2_173_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_173_configbus0[183:183] = sram_blwl_bl[183:183] ; -assign mux_1level_tapbuf_size2_173_configbus1[183:183] = sram_blwl_wl[183:183] ; -wire [183:183] mux_1level_tapbuf_size2_173_configbus0_b; -assign mux_1level_tapbuf_size2_173_configbus0_b[183:183] = sram_blwl_blb[183:183] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_173_ (mux_1level_tapbuf_size2_173_inbus, chany_0__1__out_47_ , mux_1level_tapbuf_size2_173_sram_blwl_out[183:183] , -mux_1level_tapbuf_size2_173_sram_blwl_outb[183:183] ); -//----- SRAM bits for MUX[173], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_183_ (mux_1level_tapbuf_size2_173_sram_blwl_out[183:183] ,mux_1level_tapbuf_size2_173_sram_blwl_out[183:183] ,mux_1level_tapbuf_size2_173_sram_blwl_outb[183:183] ,mux_1level_tapbuf_size2_173_configbus0[183:183], mux_1level_tapbuf_size2_173_configbus1[183:183] , mux_1level_tapbuf_size2_173_configbus0_b[183:183] ); -wire [0:1] mux_1level_tapbuf_size2_174_inbus; -assign mux_1level_tapbuf_size2_174_inbus[0] = grid_0__1__pin_0__1__9_; -assign mux_1level_tapbuf_size2_174_inbus[1] = chanx_1__1__in_49_ ; -wire [184:184] mux_1level_tapbuf_size2_174_configbus0; -wire [184:184] mux_1level_tapbuf_size2_174_configbus1; -wire [184:184] mux_1level_tapbuf_size2_174_sram_blwl_out ; -wire [184:184] mux_1level_tapbuf_size2_174_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_174_configbus0[184:184] = sram_blwl_bl[184:184] ; -assign mux_1level_tapbuf_size2_174_configbus1[184:184] = sram_blwl_wl[184:184] ; -wire [184:184] mux_1level_tapbuf_size2_174_configbus0_b; -assign mux_1level_tapbuf_size2_174_configbus0_b[184:184] = sram_blwl_blb[184:184] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_174_ (mux_1level_tapbuf_size2_174_inbus, chany_0__1__out_49_ , mux_1level_tapbuf_size2_174_sram_blwl_out[184:184] , -mux_1level_tapbuf_size2_174_sram_blwl_outb[184:184] ); -//----- SRAM bits for MUX[174], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_184_ (mux_1level_tapbuf_size2_174_sram_blwl_out[184:184] ,mux_1level_tapbuf_size2_174_sram_blwl_out[184:184] ,mux_1level_tapbuf_size2_174_sram_blwl_outb[184:184] ,mux_1level_tapbuf_size2_174_configbus0[184:184], mux_1level_tapbuf_size2_174_configbus1[184:184] , mux_1level_tapbuf_size2_174_configbus0_b[184:184] ); -wire [0:1] mux_1level_tapbuf_size2_175_inbus; -assign mux_1level_tapbuf_size2_175_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_175_inbus[1] = chanx_1__1__in_47_ ; -wire [185:185] mux_1level_tapbuf_size2_175_configbus0; -wire [185:185] mux_1level_tapbuf_size2_175_configbus1; -wire [185:185] mux_1level_tapbuf_size2_175_sram_blwl_out ; -wire [185:185] mux_1level_tapbuf_size2_175_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_175_configbus0[185:185] = sram_blwl_bl[185:185] ; -assign mux_1level_tapbuf_size2_175_configbus1[185:185] = sram_blwl_wl[185:185] ; -wire [185:185] mux_1level_tapbuf_size2_175_configbus0_b; -assign mux_1level_tapbuf_size2_175_configbus0_b[185:185] = sram_blwl_blb[185:185] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_175_ (mux_1level_tapbuf_size2_175_inbus, chany_0__1__out_51_ , mux_1level_tapbuf_size2_175_sram_blwl_out[185:185] , -mux_1level_tapbuf_size2_175_sram_blwl_outb[185:185] ); -//----- SRAM bits for MUX[175], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_185_ (mux_1level_tapbuf_size2_175_sram_blwl_out[185:185] ,mux_1level_tapbuf_size2_175_sram_blwl_out[185:185] ,mux_1level_tapbuf_size2_175_sram_blwl_outb[185:185] ,mux_1level_tapbuf_size2_175_configbus0[185:185], mux_1level_tapbuf_size2_175_configbus1[185:185] , mux_1level_tapbuf_size2_175_configbus0_b[185:185] ); -wire [0:1] mux_1level_tapbuf_size2_176_inbus; -assign mux_1level_tapbuf_size2_176_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_176_inbus[1] = chanx_1__1__in_45_ ; -wire [186:186] mux_1level_tapbuf_size2_176_configbus0; -wire [186:186] mux_1level_tapbuf_size2_176_configbus1; -wire [186:186] mux_1level_tapbuf_size2_176_sram_blwl_out ; -wire [186:186] mux_1level_tapbuf_size2_176_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_176_configbus0[186:186] = sram_blwl_bl[186:186] ; -assign mux_1level_tapbuf_size2_176_configbus1[186:186] = sram_blwl_wl[186:186] ; -wire [186:186] mux_1level_tapbuf_size2_176_configbus0_b; -assign mux_1level_tapbuf_size2_176_configbus0_b[186:186] = sram_blwl_blb[186:186] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_176_ (mux_1level_tapbuf_size2_176_inbus, chany_0__1__out_53_ , mux_1level_tapbuf_size2_176_sram_blwl_out[186:186] , -mux_1level_tapbuf_size2_176_sram_blwl_outb[186:186] ); -//----- SRAM bits for MUX[176], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_186_ (mux_1level_tapbuf_size2_176_sram_blwl_out[186:186] ,mux_1level_tapbuf_size2_176_sram_blwl_out[186:186] ,mux_1level_tapbuf_size2_176_sram_blwl_outb[186:186] ,mux_1level_tapbuf_size2_176_configbus0[186:186], mux_1level_tapbuf_size2_176_configbus1[186:186] , mux_1level_tapbuf_size2_176_configbus0_b[186:186] ); -wire [0:1] mux_1level_tapbuf_size2_177_inbus; -assign mux_1level_tapbuf_size2_177_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_177_inbus[1] = chanx_1__1__in_43_ ; -wire [187:187] mux_1level_tapbuf_size2_177_configbus0; -wire [187:187] mux_1level_tapbuf_size2_177_configbus1; -wire [187:187] mux_1level_tapbuf_size2_177_sram_blwl_out ; -wire [187:187] mux_1level_tapbuf_size2_177_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_177_configbus0[187:187] = sram_blwl_bl[187:187] ; -assign mux_1level_tapbuf_size2_177_configbus1[187:187] = sram_blwl_wl[187:187] ; -wire [187:187] mux_1level_tapbuf_size2_177_configbus0_b; -assign mux_1level_tapbuf_size2_177_configbus0_b[187:187] = sram_blwl_blb[187:187] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_177_ (mux_1level_tapbuf_size2_177_inbus, chany_0__1__out_55_ , mux_1level_tapbuf_size2_177_sram_blwl_out[187:187] , -mux_1level_tapbuf_size2_177_sram_blwl_outb[187:187] ); -//----- SRAM bits for MUX[177], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_187_ (mux_1level_tapbuf_size2_177_sram_blwl_out[187:187] ,mux_1level_tapbuf_size2_177_sram_blwl_out[187:187] ,mux_1level_tapbuf_size2_177_sram_blwl_outb[187:187] ,mux_1level_tapbuf_size2_177_configbus0[187:187], mux_1level_tapbuf_size2_177_configbus1[187:187] , mux_1level_tapbuf_size2_177_configbus0_b[187:187] ); -wire [0:1] mux_1level_tapbuf_size2_178_inbus; -assign mux_1level_tapbuf_size2_178_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_178_inbus[1] = chanx_1__1__in_41_ ; -wire [188:188] mux_1level_tapbuf_size2_178_configbus0; -wire [188:188] mux_1level_tapbuf_size2_178_configbus1; -wire [188:188] mux_1level_tapbuf_size2_178_sram_blwl_out ; -wire [188:188] mux_1level_tapbuf_size2_178_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_178_configbus0[188:188] = sram_blwl_bl[188:188] ; -assign mux_1level_tapbuf_size2_178_configbus1[188:188] = sram_blwl_wl[188:188] ; -wire [188:188] mux_1level_tapbuf_size2_178_configbus0_b; -assign mux_1level_tapbuf_size2_178_configbus0_b[188:188] = sram_blwl_blb[188:188] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_178_ (mux_1level_tapbuf_size2_178_inbus, chany_0__1__out_57_ , mux_1level_tapbuf_size2_178_sram_blwl_out[188:188] , -mux_1level_tapbuf_size2_178_sram_blwl_outb[188:188] ); -//----- SRAM bits for MUX[178], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_188_ (mux_1level_tapbuf_size2_178_sram_blwl_out[188:188] ,mux_1level_tapbuf_size2_178_sram_blwl_out[188:188] ,mux_1level_tapbuf_size2_178_sram_blwl_outb[188:188] ,mux_1level_tapbuf_size2_178_configbus0[188:188], mux_1level_tapbuf_size2_178_configbus1[188:188] , mux_1level_tapbuf_size2_178_configbus0_b[188:188] ); -wire [0:1] mux_1level_tapbuf_size2_179_inbus; -assign mux_1level_tapbuf_size2_179_inbus[0] = grid_0__1__pin_0__1__11_; -assign mux_1level_tapbuf_size2_179_inbus[1] = chanx_1__1__in_39_ ; -wire [189:189] mux_1level_tapbuf_size2_179_configbus0; -wire [189:189] mux_1level_tapbuf_size2_179_configbus1; -wire [189:189] mux_1level_tapbuf_size2_179_sram_blwl_out ; -wire [189:189] mux_1level_tapbuf_size2_179_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_179_configbus0[189:189] = sram_blwl_bl[189:189] ; -assign mux_1level_tapbuf_size2_179_configbus1[189:189] = sram_blwl_wl[189:189] ; -wire [189:189] mux_1level_tapbuf_size2_179_configbus0_b; -assign mux_1level_tapbuf_size2_179_configbus0_b[189:189] = sram_blwl_blb[189:189] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_179_ (mux_1level_tapbuf_size2_179_inbus, chany_0__1__out_59_ , mux_1level_tapbuf_size2_179_sram_blwl_out[189:189] , -mux_1level_tapbuf_size2_179_sram_blwl_outb[189:189] ); -//----- SRAM bits for MUX[179], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_189_ (mux_1level_tapbuf_size2_179_sram_blwl_out[189:189] ,mux_1level_tapbuf_size2_179_sram_blwl_out[189:189] ,mux_1level_tapbuf_size2_179_sram_blwl_outb[189:189] ,mux_1level_tapbuf_size2_179_configbus0[189:189], mux_1level_tapbuf_size2_179_configbus1[189:189] , mux_1level_tapbuf_size2_179_configbus0_b[189:189] ); -wire [0:1] mux_1level_tapbuf_size2_180_inbus; -assign mux_1level_tapbuf_size2_180_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_180_inbus[1] = chanx_1__1__in_37_ ; -wire [190:190] mux_1level_tapbuf_size2_180_configbus0; -wire [190:190] mux_1level_tapbuf_size2_180_configbus1; -wire [190:190] mux_1level_tapbuf_size2_180_sram_blwl_out ; -wire [190:190] mux_1level_tapbuf_size2_180_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_180_configbus0[190:190] = sram_blwl_bl[190:190] ; -assign mux_1level_tapbuf_size2_180_configbus1[190:190] = sram_blwl_wl[190:190] ; -wire [190:190] mux_1level_tapbuf_size2_180_configbus0_b; -assign mux_1level_tapbuf_size2_180_configbus0_b[190:190] = sram_blwl_blb[190:190] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_180_ (mux_1level_tapbuf_size2_180_inbus, chany_0__1__out_61_ , mux_1level_tapbuf_size2_180_sram_blwl_out[190:190] , -mux_1level_tapbuf_size2_180_sram_blwl_outb[190:190] ); -//----- SRAM bits for MUX[180], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_190_ (mux_1level_tapbuf_size2_180_sram_blwl_out[190:190] ,mux_1level_tapbuf_size2_180_sram_blwl_out[190:190] ,mux_1level_tapbuf_size2_180_sram_blwl_outb[190:190] ,mux_1level_tapbuf_size2_180_configbus0[190:190], mux_1level_tapbuf_size2_180_configbus1[190:190] , mux_1level_tapbuf_size2_180_configbus0_b[190:190] ); -wire [0:1] mux_1level_tapbuf_size2_181_inbus; -assign mux_1level_tapbuf_size2_181_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_181_inbus[1] = chanx_1__1__in_35_ ; -wire [191:191] mux_1level_tapbuf_size2_181_configbus0; -wire [191:191] mux_1level_tapbuf_size2_181_configbus1; -wire [191:191] mux_1level_tapbuf_size2_181_sram_blwl_out ; -wire [191:191] mux_1level_tapbuf_size2_181_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_181_configbus0[191:191] = sram_blwl_bl[191:191] ; -assign mux_1level_tapbuf_size2_181_configbus1[191:191] = sram_blwl_wl[191:191] ; -wire [191:191] mux_1level_tapbuf_size2_181_configbus0_b; -assign mux_1level_tapbuf_size2_181_configbus0_b[191:191] = sram_blwl_blb[191:191] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_181_ (mux_1level_tapbuf_size2_181_inbus, chany_0__1__out_63_ , mux_1level_tapbuf_size2_181_sram_blwl_out[191:191] , -mux_1level_tapbuf_size2_181_sram_blwl_outb[191:191] ); -//----- SRAM bits for MUX[181], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_191_ (mux_1level_tapbuf_size2_181_sram_blwl_out[191:191] ,mux_1level_tapbuf_size2_181_sram_blwl_out[191:191] ,mux_1level_tapbuf_size2_181_sram_blwl_outb[191:191] ,mux_1level_tapbuf_size2_181_configbus0[191:191], mux_1level_tapbuf_size2_181_configbus1[191:191] , mux_1level_tapbuf_size2_181_configbus0_b[191:191] ); -wire [0:1] mux_1level_tapbuf_size2_182_inbus; -assign mux_1level_tapbuf_size2_182_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_182_inbus[1] = chanx_1__1__in_33_ ; -wire [192:192] mux_1level_tapbuf_size2_182_configbus0; -wire [192:192] mux_1level_tapbuf_size2_182_configbus1; -wire [192:192] mux_1level_tapbuf_size2_182_sram_blwl_out ; -wire [192:192] mux_1level_tapbuf_size2_182_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_182_configbus0[192:192] = sram_blwl_bl[192:192] ; -assign mux_1level_tapbuf_size2_182_configbus1[192:192] = sram_blwl_wl[192:192] ; -wire [192:192] mux_1level_tapbuf_size2_182_configbus0_b; -assign mux_1level_tapbuf_size2_182_configbus0_b[192:192] = sram_blwl_blb[192:192] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_182_ (mux_1level_tapbuf_size2_182_inbus, chany_0__1__out_65_ , mux_1level_tapbuf_size2_182_sram_blwl_out[192:192] , -mux_1level_tapbuf_size2_182_sram_blwl_outb[192:192] ); -//----- SRAM bits for MUX[182], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_192_ (mux_1level_tapbuf_size2_182_sram_blwl_out[192:192] ,mux_1level_tapbuf_size2_182_sram_blwl_out[192:192] ,mux_1level_tapbuf_size2_182_sram_blwl_outb[192:192] ,mux_1level_tapbuf_size2_182_configbus0[192:192], mux_1level_tapbuf_size2_182_configbus1[192:192] , mux_1level_tapbuf_size2_182_configbus0_b[192:192] ); -wire [0:1] mux_1level_tapbuf_size2_183_inbus; -assign mux_1level_tapbuf_size2_183_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_183_inbus[1] = chanx_1__1__in_31_ ; -wire [193:193] mux_1level_tapbuf_size2_183_configbus0; -wire [193:193] mux_1level_tapbuf_size2_183_configbus1; -wire [193:193] mux_1level_tapbuf_size2_183_sram_blwl_out ; -wire [193:193] mux_1level_tapbuf_size2_183_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_183_configbus0[193:193] = sram_blwl_bl[193:193] ; -assign mux_1level_tapbuf_size2_183_configbus1[193:193] = sram_blwl_wl[193:193] ; -wire [193:193] mux_1level_tapbuf_size2_183_configbus0_b; -assign mux_1level_tapbuf_size2_183_configbus0_b[193:193] = sram_blwl_blb[193:193] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_183_ (mux_1level_tapbuf_size2_183_inbus, chany_0__1__out_67_ , mux_1level_tapbuf_size2_183_sram_blwl_out[193:193] , -mux_1level_tapbuf_size2_183_sram_blwl_outb[193:193] ); -//----- SRAM bits for MUX[183], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_193_ (mux_1level_tapbuf_size2_183_sram_blwl_out[193:193] ,mux_1level_tapbuf_size2_183_sram_blwl_out[193:193] ,mux_1level_tapbuf_size2_183_sram_blwl_outb[193:193] ,mux_1level_tapbuf_size2_183_configbus0[193:193], mux_1level_tapbuf_size2_183_configbus1[193:193] , mux_1level_tapbuf_size2_183_configbus0_b[193:193] ); -wire [0:1] mux_1level_tapbuf_size2_184_inbus; -assign mux_1level_tapbuf_size2_184_inbus[0] = grid_0__1__pin_0__1__13_; -assign mux_1level_tapbuf_size2_184_inbus[1] = chanx_1__1__in_29_ ; -wire [194:194] mux_1level_tapbuf_size2_184_configbus0; -wire [194:194] mux_1level_tapbuf_size2_184_configbus1; -wire [194:194] mux_1level_tapbuf_size2_184_sram_blwl_out ; -wire [194:194] mux_1level_tapbuf_size2_184_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_184_configbus0[194:194] = sram_blwl_bl[194:194] ; -assign mux_1level_tapbuf_size2_184_configbus1[194:194] = sram_blwl_wl[194:194] ; -wire [194:194] mux_1level_tapbuf_size2_184_configbus0_b; -assign mux_1level_tapbuf_size2_184_configbus0_b[194:194] = sram_blwl_blb[194:194] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_184_ (mux_1level_tapbuf_size2_184_inbus, chany_0__1__out_69_ , mux_1level_tapbuf_size2_184_sram_blwl_out[194:194] , -mux_1level_tapbuf_size2_184_sram_blwl_outb[194:194] ); -//----- SRAM bits for MUX[184], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_194_ (mux_1level_tapbuf_size2_184_sram_blwl_out[194:194] ,mux_1level_tapbuf_size2_184_sram_blwl_out[194:194] ,mux_1level_tapbuf_size2_184_sram_blwl_outb[194:194] ,mux_1level_tapbuf_size2_184_configbus0[194:194], mux_1level_tapbuf_size2_184_configbus1[194:194] , mux_1level_tapbuf_size2_184_configbus0_b[194:194] ); -wire [0:1] mux_1level_tapbuf_size2_185_inbus; -assign mux_1level_tapbuf_size2_185_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_185_inbus[1] = chanx_1__1__in_27_ ; -wire [195:195] mux_1level_tapbuf_size2_185_configbus0; -wire [195:195] mux_1level_tapbuf_size2_185_configbus1; -wire [195:195] mux_1level_tapbuf_size2_185_sram_blwl_out ; -wire [195:195] mux_1level_tapbuf_size2_185_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_185_configbus0[195:195] = sram_blwl_bl[195:195] ; -assign mux_1level_tapbuf_size2_185_configbus1[195:195] = sram_blwl_wl[195:195] ; -wire [195:195] mux_1level_tapbuf_size2_185_configbus0_b; -assign mux_1level_tapbuf_size2_185_configbus0_b[195:195] = sram_blwl_blb[195:195] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_185_ (mux_1level_tapbuf_size2_185_inbus, chany_0__1__out_71_ , mux_1level_tapbuf_size2_185_sram_blwl_out[195:195] , -mux_1level_tapbuf_size2_185_sram_blwl_outb[195:195] ); -//----- SRAM bits for MUX[185], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_195_ (mux_1level_tapbuf_size2_185_sram_blwl_out[195:195] ,mux_1level_tapbuf_size2_185_sram_blwl_out[195:195] ,mux_1level_tapbuf_size2_185_sram_blwl_outb[195:195] ,mux_1level_tapbuf_size2_185_configbus0[195:195], mux_1level_tapbuf_size2_185_configbus1[195:195] , mux_1level_tapbuf_size2_185_configbus0_b[195:195] ); -wire [0:1] mux_1level_tapbuf_size2_186_inbus; -assign mux_1level_tapbuf_size2_186_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_186_inbus[1] = chanx_1__1__in_25_ ; -wire [196:196] mux_1level_tapbuf_size2_186_configbus0; -wire [196:196] mux_1level_tapbuf_size2_186_configbus1; -wire [196:196] mux_1level_tapbuf_size2_186_sram_blwl_out ; -wire [196:196] mux_1level_tapbuf_size2_186_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_186_configbus0[196:196] = sram_blwl_bl[196:196] ; -assign mux_1level_tapbuf_size2_186_configbus1[196:196] = sram_blwl_wl[196:196] ; -wire [196:196] mux_1level_tapbuf_size2_186_configbus0_b; -assign mux_1level_tapbuf_size2_186_configbus0_b[196:196] = sram_blwl_blb[196:196] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_186_ (mux_1level_tapbuf_size2_186_inbus, chany_0__1__out_73_ , mux_1level_tapbuf_size2_186_sram_blwl_out[196:196] , -mux_1level_tapbuf_size2_186_sram_blwl_outb[196:196] ); -//----- SRAM bits for MUX[186], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_196_ (mux_1level_tapbuf_size2_186_sram_blwl_out[196:196] ,mux_1level_tapbuf_size2_186_sram_blwl_out[196:196] ,mux_1level_tapbuf_size2_186_sram_blwl_outb[196:196] ,mux_1level_tapbuf_size2_186_configbus0[196:196], mux_1level_tapbuf_size2_186_configbus1[196:196] , mux_1level_tapbuf_size2_186_configbus0_b[196:196] ); -wire [0:1] mux_1level_tapbuf_size2_187_inbus; -assign mux_1level_tapbuf_size2_187_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_187_inbus[1] = chanx_1__1__in_23_ ; -wire [197:197] mux_1level_tapbuf_size2_187_configbus0; -wire [197:197] mux_1level_tapbuf_size2_187_configbus1; -wire [197:197] mux_1level_tapbuf_size2_187_sram_blwl_out ; -wire [197:197] mux_1level_tapbuf_size2_187_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_187_configbus0[197:197] = sram_blwl_bl[197:197] ; -assign mux_1level_tapbuf_size2_187_configbus1[197:197] = sram_blwl_wl[197:197] ; -wire [197:197] mux_1level_tapbuf_size2_187_configbus0_b; -assign mux_1level_tapbuf_size2_187_configbus0_b[197:197] = sram_blwl_blb[197:197] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_187_ (mux_1level_tapbuf_size2_187_inbus, chany_0__1__out_75_ , mux_1level_tapbuf_size2_187_sram_blwl_out[197:197] , -mux_1level_tapbuf_size2_187_sram_blwl_outb[197:197] ); -//----- SRAM bits for MUX[187], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_197_ (mux_1level_tapbuf_size2_187_sram_blwl_out[197:197] ,mux_1level_tapbuf_size2_187_sram_blwl_out[197:197] ,mux_1level_tapbuf_size2_187_sram_blwl_outb[197:197] ,mux_1level_tapbuf_size2_187_configbus0[197:197], mux_1level_tapbuf_size2_187_configbus1[197:197] , mux_1level_tapbuf_size2_187_configbus0_b[197:197] ); -wire [0:1] mux_1level_tapbuf_size2_188_inbus; -assign mux_1level_tapbuf_size2_188_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_188_inbus[1] = chanx_1__1__in_21_ ; -wire [198:198] mux_1level_tapbuf_size2_188_configbus0; -wire [198:198] mux_1level_tapbuf_size2_188_configbus1; -wire [198:198] mux_1level_tapbuf_size2_188_sram_blwl_out ; -wire [198:198] mux_1level_tapbuf_size2_188_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_188_configbus0[198:198] = sram_blwl_bl[198:198] ; -assign mux_1level_tapbuf_size2_188_configbus1[198:198] = sram_blwl_wl[198:198] ; -wire [198:198] mux_1level_tapbuf_size2_188_configbus0_b; -assign mux_1level_tapbuf_size2_188_configbus0_b[198:198] = sram_blwl_blb[198:198] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_188_ (mux_1level_tapbuf_size2_188_inbus, chany_0__1__out_77_ , mux_1level_tapbuf_size2_188_sram_blwl_out[198:198] , -mux_1level_tapbuf_size2_188_sram_blwl_outb[198:198] ); -//----- SRAM bits for MUX[188], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_198_ (mux_1level_tapbuf_size2_188_sram_blwl_out[198:198] ,mux_1level_tapbuf_size2_188_sram_blwl_out[198:198] ,mux_1level_tapbuf_size2_188_sram_blwl_outb[198:198] ,mux_1level_tapbuf_size2_188_configbus0[198:198], mux_1level_tapbuf_size2_188_configbus1[198:198] , mux_1level_tapbuf_size2_188_configbus0_b[198:198] ); -wire [0:1] mux_1level_tapbuf_size2_189_inbus; -assign mux_1level_tapbuf_size2_189_inbus[0] = grid_0__1__pin_0__1__15_; -assign mux_1level_tapbuf_size2_189_inbus[1] = chanx_1__1__in_19_ ; -wire [199:199] mux_1level_tapbuf_size2_189_configbus0; -wire [199:199] mux_1level_tapbuf_size2_189_configbus1; -wire [199:199] mux_1level_tapbuf_size2_189_sram_blwl_out ; -wire [199:199] mux_1level_tapbuf_size2_189_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_189_configbus0[199:199] = sram_blwl_bl[199:199] ; -assign mux_1level_tapbuf_size2_189_configbus1[199:199] = sram_blwl_wl[199:199] ; -wire [199:199] mux_1level_tapbuf_size2_189_configbus0_b; -assign mux_1level_tapbuf_size2_189_configbus0_b[199:199] = sram_blwl_blb[199:199] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_189_ (mux_1level_tapbuf_size2_189_inbus, chany_0__1__out_79_ , mux_1level_tapbuf_size2_189_sram_blwl_out[199:199] , -mux_1level_tapbuf_size2_189_sram_blwl_outb[199:199] ); -//----- SRAM bits for MUX[189], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_199_ (mux_1level_tapbuf_size2_189_sram_blwl_out[199:199] ,mux_1level_tapbuf_size2_189_sram_blwl_out[199:199] ,mux_1level_tapbuf_size2_189_sram_blwl_outb[199:199] ,mux_1level_tapbuf_size2_189_configbus0[199:199], mux_1level_tapbuf_size2_189_configbus1[199:199] , mux_1level_tapbuf_size2_189_configbus0_b[199:199] ); -wire [0:1] mux_1level_tapbuf_size2_190_inbus; -assign mux_1level_tapbuf_size2_190_inbus[0] = grid_1__1__pin_0__3__43_; -assign mux_1level_tapbuf_size2_190_inbus[1] = chanx_1__1__in_17_ ; -wire [200:200] mux_1level_tapbuf_size2_190_configbus0; -wire [200:200] mux_1level_tapbuf_size2_190_configbus1; -wire [200:200] mux_1level_tapbuf_size2_190_sram_blwl_out ; -wire [200:200] mux_1level_tapbuf_size2_190_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_190_configbus0[200:200] = sram_blwl_bl[200:200] ; -assign mux_1level_tapbuf_size2_190_configbus1[200:200] = sram_blwl_wl[200:200] ; -wire [200:200] mux_1level_tapbuf_size2_190_configbus0_b; -assign mux_1level_tapbuf_size2_190_configbus0_b[200:200] = sram_blwl_blb[200:200] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_190_ (mux_1level_tapbuf_size2_190_inbus, chany_0__1__out_81_ , mux_1level_tapbuf_size2_190_sram_blwl_out[200:200] , -mux_1level_tapbuf_size2_190_sram_blwl_outb[200:200] ); -//----- SRAM bits for MUX[190], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_200_ (mux_1level_tapbuf_size2_190_sram_blwl_out[200:200] ,mux_1level_tapbuf_size2_190_sram_blwl_out[200:200] ,mux_1level_tapbuf_size2_190_sram_blwl_outb[200:200] ,mux_1level_tapbuf_size2_190_configbus0[200:200], mux_1level_tapbuf_size2_190_configbus1[200:200] , mux_1level_tapbuf_size2_190_configbus0_b[200:200] ); -wire [0:1] mux_1level_tapbuf_size2_191_inbus; -assign mux_1level_tapbuf_size2_191_inbus[0] = grid_1__1__pin_0__3__43_; -assign mux_1level_tapbuf_size2_191_inbus[1] = chanx_1__1__in_15_ ; -wire [201:201] mux_1level_tapbuf_size2_191_configbus0; -wire [201:201] mux_1level_tapbuf_size2_191_configbus1; -wire [201:201] mux_1level_tapbuf_size2_191_sram_blwl_out ; -wire [201:201] mux_1level_tapbuf_size2_191_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_191_configbus0[201:201] = sram_blwl_bl[201:201] ; -assign mux_1level_tapbuf_size2_191_configbus1[201:201] = sram_blwl_wl[201:201] ; -wire [201:201] mux_1level_tapbuf_size2_191_configbus0_b; -assign mux_1level_tapbuf_size2_191_configbus0_b[201:201] = sram_blwl_blb[201:201] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_191_ (mux_1level_tapbuf_size2_191_inbus, chany_0__1__out_83_ , mux_1level_tapbuf_size2_191_sram_blwl_out[201:201] , -mux_1level_tapbuf_size2_191_sram_blwl_outb[201:201] ); -//----- SRAM bits for MUX[191], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_201_ (mux_1level_tapbuf_size2_191_sram_blwl_out[201:201] ,mux_1level_tapbuf_size2_191_sram_blwl_out[201:201] ,mux_1level_tapbuf_size2_191_sram_blwl_outb[201:201] ,mux_1level_tapbuf_size2_191_configbus0[201:201], mux_1level_tapbuf_size2_191_configbus1[201:201] , mux_1level_tapbuf_size2_191_configbus0_b[201:201] ); -wire [0:1] mux_1level_tapbuf_size2_192_inbus; -assign mux_1level_tapbuf_size2_192_inbus[0] = grid_1__1__pin_0__3__43_; -assign mux_1level_tapbuf_size2_192_inbus[1] = chanx_1__1__in_13_ ; -wire [202:202] mux_1level_tapbuf_size2_192_configbus0; -wire [202:202] mux_1level_tapbuf_size2_192_configbus1; -wire [202:202] mux_1level_tapbuf_size2_192_sram_blwl_out ; -wire [202:202] mux_1level_tapbuf_size2_192_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_192_configbus0[202:202] = sram_blwl_bl[202:202] ; -assign mux_1level_tapbuf_size2_192_configbus1[202:202] = sram_blwl_wl[202:202] ; -wire [202:202] mux_1level_tapbuf_size2_192_configbus0_b; -assign mux_1level_tapbuf_size2_192_configbus0_b[202:202] = sram_blwl_blb[202:202] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_192_ (mux_1level_tapbuf_size2_192_inbus, chany_0__1__out_85_ , mux_1level_tapbuf_size2_192_sram_blwl_out[202:202] , -mux_1level_tapbuf_size2_192_sram_blwl_outb[202:202] ); -//----- SRAM bits for MUX[192], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_202_ (mux_1level_tapbuf_size2_192_sram_blwl_out[202:202] ,mux_1level_tapbuf_size2_192_sram_blwl_out[202:202] ,mux_1level_tapbuf_size2_192_sram_blwl_outb[202:202] ,mux_1level_tapbuf_size2_192_configbus0[202:202], mux_1level_tapbuf_size2_192_configbus1[202:202] , mux_1level_tapbuf_size2_192_configbus0_b[202:202] ); -wire [0:1] mux_1level_tapbuf_size2_193_inbus; -assign mux_1level_tapbuf_size2_193_inbus[0] = grid_1__1__pin_0__3__43_; -assign mux_1level_tapbuf_size2_193_inbus[1] = chanx_1__1__in_11_ ; -wire [203:203] mux_1level_tapbuf_size2_193_configbus0; -wire [203:203] mux_1level_tapbuf_size2_193_configbus1; -wire [203:203] mux_1level_tapbuf_size2_193_sram_blwl_out ; -wire [203:203] mux_1level_tapbuf_size2_193_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_193_configbus0[203:203] = sram_blwl_bl[203:203] ; -assign mux_1level_tapbuf_size2_193_configbus1[203:203] = sram_blwl_wl[203:203] ; -wire [203:203] mux_1level_tapbuf_size2_193_configbus0_b; -assign mux_1level_tapbuf_size2_193_configbus0_b[203:203] = sram_blwl_blb[203:203] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_193_ (mux_1level_tapbuf_size2_193_inbus, chany_0__1__out_87_ , mux_1level_tapbuf_size2_193_sram_blwl_out[203:203] , -mux_1level_tapbuf_size2_193_sram_blwl_outb[203:203] ); -//----- SRAM bits for MUX[193], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_203_ (mux_1level_tapbuf_size2_193_sram_blwl_out[203:203] ,mux_1level_tapbuf_size2_193_sram_blwl_out[203:203] ,mux_1level_tapbuf_size2_193_sram_blwl_outb[203:203] ,mux_1level_tapbuf_size2_193_configbus0[203:203], mux_1level_tapbuf_size2_193_configbus1[203:203] , mux_1level_tapbuf_size2_193_configbus0_b[203:203] ); -wire [0:1] mux_1level_tapbuf_size2_194_inbus; -assign mux_1level_tapbuf_size2_194_inbus[0] = grid_1__1__pin_0__3__43_; -assign mux_1level_tapbuf_size2_194_inbus[1] = chanx_1__1__in_9_ ; -wire [204:204] mux_1level_tapbuf_size2_194_configbus0; -wire [204:204] mux_1level_tapbuf_size2_194_configbus1; -wire [204:204] mux_1level_tapbuf_size2_194_sram_blwl_out ; -wire [204:204] mux_1level_tapbuf_size2_194_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_194_configbus0[204:204] = sram_blwl_bl[204:204] ; -assign mux_1level_tapbuf_size2_194_configbus1[204:204] = sram_blwl_wl[204:204] ; -wire [204:204] mux_1level_tapbuf_size2_194_configbus0_b; -assign mux_1level_tapbuf_size2_194_configbus0_b[204:204] = sram_blwl_blb[204:204] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_194_ (mux_1level_tapbuf_size2_194_inbus, chany_0__1__out_89_ , mux_1level_tapbuf_size2_194_sram_blwl_out[204:204] , -mux_1level_tapbuf_size2_194_sram_blwl_outb[204:204] ); -//----- SRAM bits for MUX[194], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_204_ (mux_1level_tapbuf_size2_194_sram_blwl_out[204:204] ,mux_1level_tapbuf_size2_194_sram_blwl_out[204:204] ,mux_1level_tapbuf_size2_194_sram_blwl_outb[204:204] ,mux_1level_tapbuf_size2_194_configbus0[204:204], mux_1level_tapbuf_size2_194_configbus1[204:204] , mux_1level_tapbuf_size2_194_configbus0_b[204:204] ); -wire [0:1] mux_1level_tapbuf_size2_195_inbus; -assign mux_1level_tapbuf_size2_195_inbus[0] = grid_1__1__pin_0__3__47_; -assign mux_1level_tapbuf_size2_195_inbus[1] = chanx_1__1__in_7_ ; -wire [205:205] mux_1level_tapbuf_size2_195_configbus0; -wire [205:205] mux_1level_tapbuf_size2_195_configbus1; -wire [205:205] mux_1level_tapbuf_size2_195_sram_blwl_out ; -wire [205:205] mux_1level_tapbuf_size2_195_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_195_configbus0[205:205] = sram_blwl_bl[205:205] ; -assign mux_1level_tapbuf_size2_195_configbus1[205:205] = sram_blwl_wl[205:205] ; -wire [205:205] mux_1level_tapbuf_size2_195_configbus0_b; -assign mux_1level_tapbuf_size2_195_configbus0_b[205:205] = sram_blwl_blb[205:205] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_195_ (mux_1level_tapbuf_size2_195_inbus, chany_0__1__out_91_ , mux_1level_tapbuf_size2_195_sram_blwl_out[205:205] , -mux_1level_tapbuf_size2_195_sram_blwl_outb[205:205] ); -//----- SRAM bits for MUX[195], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_205_ (mux_1level_tapbuf_size2_195_sram_blwl_out[205:205] ,mux_1level_tapbuf_size2_195_sram_blwl_out[205:205] ,mux_1level_tapbuf_size2_195_sram_blwl_outb[205:205] ,mux_1level_tapbuf_size2_195_configbus0[205:205], mux_1level_tapbuf_size2_195_configbus1[205:205] , mux_1level_tapbuf_size2_195_configbus0_b[205:205] ); -wire [0:1] mux_1level_tapbuf_size2_196_inbus; -assign mux_1level_tapbuf_size2_196_inbus[0] = grid_1__1__pin_0__3__47_; -assign mux_1level_tapbuf_size2_196_inbus[1] = chanx_1__1__in_5_ ; -wire [206:206] mux_1level_tapbuf_size2_196_configbus0; -wire [206:206] mux_1level_tapbuf_size2_196_configbus1; -wire [206:206] mux_1level_tapbuf_size2_196_sram_blwl_out ; -wire [206:206] mux_1level_tapbuf_size2_196_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_196_configbus0[206:206] = sram_blwl_bl[206:206] ; -assign mux_1level_tapbuf_size2_196_configbus1[206:206] = sram_blwl_wl[206:206] ; -wire [206:206] mux_1level_tapbuf_size2_196_configbus0_b; -assign mux_1level_tapbuf_size2_196_configbus0_b[206:206] = sram_blwl_blb[206:206] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_196_ (mux_1level_tapbuf_size2_196_inbus, chany_0__1__out_93_ , mux_1level_tapbuf_size2_196_sram_blwl_out[206:206] , -mux_1level_tapbuf_size2_196_sram_blwl_outb[206:206] ); -//----- SRAM bits for MUX[196], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_206_ (mux_1level_tapbuf_size2_196_sram_blwl_out[206:206] ,mux_1level_tapbuf_size2_196_sram_blwl_out[206:206] ,mux_1level_tapbuf_size2_196_sram_blwl_outb[206:206] ,mux_1level_tapbuf_size2_196_configbus0[206:206], mux_1level_tapbuf_size2_196_configbus1[206:206] , mux_1level_tapbuf_size2_196_configbus0_b[206:206] ); -wire [0:1] mux_1level_tapbuf_size2_197_inbus; -assign mux_1level_tapbuf_size2_197_inbus[0] = grid_1__1__pin_0__3__47_; -assign mux_1level_tapbuf_size2_197_inbus[1] = chanx_1__1__in_3_ ; -wire [207:207] mux_1level_tapbuf_size2_197_configbus0; -wire [207:207] mux_1level_tapbuf_size2_197_configbus1; -wire [207:207] mux_1level_tapbuf_size2_197_sram_blwl_out ; -wire [207:207] mux_1level_tapbuf_size2_197_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_197_configbus0[207:207] = sram_blwl_bl[207:207] ; -assign mux_1level_tapbuf_size2_197_configbus1[207:207] = sram_blwl_wl[207:207] ; -wire [207:207] mux_1level_tapbuf_size2_197_configbus0_b; -assign mux_1level_tapbuf_size2_197_configbus0_b[207:207] = sram_blwl_blb[207:207] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_197_ (mux_1level_tapbuf_size2_197_inbus, chany_0__1__out_95_ , mux_1level_tapbuf_size2_197_sram_blwl_out[207:207] , -mux_1level_tapbuf_size2_197_sram_blwl_outb[207:207] ); -//----- SRAM bits for MUX[197], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_207_ (mux_1level_tapbuf_size2_197_sram_blwl_out[207:207] ,mux_1level_tapbuf_size2_197_sram_blwl_out[207:207] ,mux_1level_tapbuf_size2_197_sram_blwl_outb[207:207] ,mux_1level_tapbuf_size2_197_configbus0[207:207], mux_1level_tapbuf_size2_197_configbus1[207:207] , mux_1level_tapbuf_size2_197_configbus0_b[207:207] ); -wire [0:1] mux_1level_tapbuf_size2_198_inbus; -assign mux_1level_tapbuf_size2_198_inbus[0] = grid_1__1__pin_0__3__47_; -assign mux_1level_tapbuf_size2_198_inbus[1] = chanx_1__1__in_1_ ; -wire [208:208] mux_1level_tapbuf_size2_198_configbus0; -wire [208:208] mux_1level_tapbuf_size2_198_configbus1; -wire [208:208] mux_1level_tapbuf_size2_198_sram_blwl_out ; -wire [208:208] mux_1level_tapbuf_size2_198_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_198_configbus0[208:208] = sram_blwl_bl[208:208] ; -assign mux_1level_tapbuf_size2_198_configbus1[208:208] = sram_blwl_wl[208:208] ; -wire [208:208] mux_1level_tapbuf_size2_198_configbus0_b; -assign mux_1level_tapbuf_size2_198_configbus0_b[208:208] = sram_blwl_blb[208:208] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_198_ (mux_1level_tapbuf_size2_198_inbus, chany_0__1__out_97_ , mux_1level_tapbuf_size2_198_sram_blwl_out[208:208] , -mux_1level_tapbuf_size2_198_sram_blwl_outb[208:208] ); -//----- SRAM bits for MUX[198], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_208_ (mux_1level_tapbuf_size2_198_sram_blwl_out[208:208] ,mux_1level_tapbuf_size2_198_sram_blwl_out[208:208] ,mux_1level_tapbuf_size2_198_sram_blwl_outb[208:208] ,mux_1level_tapbuf_size2_198_configbus0[208:208], mux_1level_tapbuf_size2_198_configbus1[208:208] , mux_1level_tapbuf_size2_198_configbus0_b[208:208] ); -wire [0:1] mux_1level_tapbuf_size2_199_inbus; -assign mux_1level_tapbuf_size2_199_inbus[0] = grid_1__1__pin_0__3__47_; -assign mux_1level_tapbuf_size2_199_inbus[1] = chanx_1__1__in_99_ ; -wire [209:209] mux_1level_tapbuf_size2_199_configbus0; -wire [209:209] mux_1level_tapbuf_size2_199_configbus1; -wire [209:209] mux_1level_tapbuf_size2_199_sram_blwl_out ; -wire [209:209] mux_1level_tapbuf_size2_199_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_199_configbus0[209:209] = sram_blwl_bl[209:209] ; -assign mux_1level_tapbuf_size2_199_configbus1[209:209] = sram_blwl_wl[209:209] ; -wire [209:209] mux_1level_tapbuf_size2_199_configbus0_b; -assign mux_1level_tapbuf_size2_199_configbus0_b[209:209] = sram_blwl_blb[209:209] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_199_ (mux_1level_tapbuf_size2_199_inbus, chany_0__1__out_99_ , mux_1level_tapbuf_size2_199_sram_blwl_out[209:209] , -mux_1level_tapbuf_size2_199_sram_blwl_outb[209:209] ); -//----- SRAM bits for MUX[199], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_209_ (mux_1level_tapbuf_size2_199_sram_blwl_out[209:209] ,mux_1level_tapbuf_size2_199_sram_blwl_out[209:209] ,mux_1level_tapbuf_size2_199_sram_blwl_outb[209:209] ,mux_1level_tapbuf_size2_199_configbus0[209:209], mux_1level_tapbuf_size2_199_configbus1[209:209] , mux_1level_tapbuf_size2_199_configbus0_b[209:209] ); -//----- left side Multiplexers ----- -endmodule -//----- END Verilog Module of Switch Box[0][1] ----- - diff --git a/examples/verilog_test_example_2/routing/sb_1_0.v b/examples/verilog_test_example_2/routing/sb_1_0.v deleted file mode 100644 index 3158bf99b..000000000 --- a/examples/verilog_test_example_2/routing/sb_1_0.v +++ /dev/null @@ -1,1971 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Switch Block [1][0] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Switch Box[1][0] ----- -module sb_1__0_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -//----- Inputs/outputs of top side ----- - output chany_1__1__out_0_, - input chany_1__1__in_1_, - output chany_1__1__out_2_, - input chany_1__1__in_3_, - output chany_1__1__out_4_, - input chany_1__1__in_5_, - output chany_1__1__out_6_, - input chany_1__1__in_7_, - output chany_1__1__out_8_, - input chany_1__1__in_9_, - output chany_1__1__out_10_, - input chany_1__1__in_11_, - output chany_1__1__out_12_, - input chany_1__1__in_13_, - output chany_1__1__out_14_, - input chany_1__1__in_15_, - output chany_1__1__out_16_, - input chany_1__1__in_17_, - output chany_1__1__out_18_, - input chany_1__1__in_19_, - output chany_1__1__out_20_, - input chany_1__1__in_21_, - output chany_1__1__out_22_, - input chany_1__1__in_23_, - output chany_1__1__out_24_, - input chany_1__1__in_25_, - output chany_1__1__out_26_, - input chany_1__1__in_27_, - output chany_1__1__out_28_, - input chany_1__1__in_29_, - output chany_1__1__out_30_, - input chany_1__1__in_31_, - output chany_1__1__out_32_, - input chany_1__1__in_33_, - output chany_1__1__out_34_, - input chany_1__1__in_35_, - output chany_1__1__out_36_, - input chany_1__1__in_37_, - output chany_1__1__out_38_, - input chany_1__1__in_39_, - output chany_1__1__out_40_, - input chany_1__1__in_41_, - output chany_1__1__out_42_, - input chany_1__1__in_43_, - output chany_1__1__out_44_, - input chany_1__1__in_45_, - output chany_1__1__out_46_, - input chany_1__1__in_47_, - output chany_1__1__out_48_, - input chany_1__1__in_49_, - output chany_1__1__out_50_, - input chany_1__1__in_51_, - output chany_1__1__out_52_, - input chany_1__1__in_53_, - output chany_1__1__out_54_, - input chany_1__1__in_55_, - output chany_1__1__out_56_, - input chany_1__1__in_57_, - output chany_1__1__out_58_, - input chany_1__1__in_59_, - output chany_1__1__out_60_, - input chany_1__1__in_61_, - output chany_1__1__out_62_, - input chany_1__1__in_63_, - output chany_1__1__out_64_, - input chany_1__1__in_65_, - output chany_1__1__out_66_, - input chany_1__1__in_67_, - output chany_1__1__out_68_, - input chany_1__1__in_69_, - output chany_1__1__out_70_, - input chany_1__1__in_71_, - output chany_1__1__out_72_, - input chany_1__1__in_73_, - output chany_1__1__out_74_, - input chany_1__1__in_75_, - output chany_1__1__out_76_, - input chany_1__1__in_77_, - output chany_1__1__out_78_, - input chany_1__1__in_79_, - output chany_1__1__out_80_, - input chany_1__1__in_81_, - output chany_1__1__out_82_, - input chany_1__1__in_83_, - output chany_1__1__out_84_, - input chany_1__1__in_85_, - output chany_1__1__out_86_, - input chany_1__1__in_87_, - output chany_1__1__out_88_, - input chany_1__1__in_89_, - output chany_1__1__out_90_, - input chany_1__1__in_91_, - output chany_1__1__out_92_, - input chany_1__1__in_93_, - output chany_1__1__out_94_, - input chany_1__1__in_95_, - output chany_1__1__out_96_, - input chany_1__1__in_97_, - output chany_1__1__out_98_, - input chany_1__1__in_99_, -input grid_1__1__pin_0__1__41_, -input grid_1__1__pin_0__1__45_, -input grid_1__1__pin_0__1__49_, -input grid_2__1__pin_0__3__1_, -input grid_2__1__pin_0__3__3_, -input grid_2__1__pin_0__3__5_, -input grid_2__1__pin_0__3__7_, -input grid_2__1__pin_0__3__9_, -input grid_2__1__pin_0__3__11_, -input grid_2__1__pin_0__3__13_, -input grid_2__1__pin_0__3__15_, -//----- Inputs/outputs of right side ----- -//----- Inputs/outputs of bottom side ----- -//----- Inputs/outputs of left side ----- - input chanx_1__0__in_0_, - output chanx_1__0__out_1_, - input chanx_1__0__in_2_, - output chanx_1__0__out_3_, - input chanx_1__0__in_4_, - output chanx_1__0__out_5_, - input chanx_1__0__in_6_, - output chanx_1__0__out_7_, - input chanx_1__0__in_8_, - output chanx_1__0__out_9_, - input chanx_1__0__in_10_, - output chanx_1__0__out_11_, - input chanx_1__0__in_12_, - output chanx_1__0__out_13_, - input chanx_1__0__in_14_, - output chanx_1__0__out_15_, - input chanx_1__0__in_16_, - output chanx_1__0__out_17_, - input chanx_1__0__in_18_, - output chanx_1__0__out_19_, - input chanx_1__0__in_20_, - output chanx_1__0__out_21_, - input chanx_1__0__in_22_, - output chanx_1__0__out_23_, - input chanx_1__0__in_24_, - output chanx_1__0__out_25_, - input chanx_1__0__in_26_, - output chanx_1__0__out_27_, - input chanx_1__0__in_28_, - output chanx_1__0__out_29_, - input chanx_1__0__in_30_, - output chanx_1__0__out_31_, - input chanx_1__0__in_32_, - output chanx_1__0__out_33_, - input chanx_1__0__in_34_, - output chanx_1__0__out_35_, - input chanx_1__0__in_36_, - output chanx_1__0__out_37_, - input chanx_1__0__in_38_, - output chanx_1__0__out_39_, - input chanx_1__0__in_40_, - output chanx_1__0__out_41_, - input chanx_1__0__in_42_, - output chanx_1__0__out_43_, - input chanx_1__0__in_44_, - output chanx_1__0__out_45_, - input chanx_1__0__in_46_, - output chanx_1__0__out_47_, - input chanx_1__0__in_48_, - output chanx_1__0__out_49_, - input chanx_1__0__in_50_, - output chanx_1__0__out_51_, - input chanx_1__0__in_52_, - output chanx_1__0__out_53_, - input chanx_1__0__in_54_, - output chanx_1__0__out_55_, - input chanx_1__0__in_56_, - output chanx_1__0__out_57_, - input chanx_1__0__in_58_, - output chanx_1__0__out_59_, - input chanx_1__0__in_60_, - output chanx_1__0__out_61_, - input chanx_1__0__in_62_, - output chanx_1__0__out_63_, - input chanx_1__0__in_64_, - output chanx_1__0__out_65_, - input chanx_1__0__in_66_, - output chanx_1__0__out_67_, - input chanx_1__0__in_68_, - output chanx_1__0__out_69_, - input chanx_1__0__in_70_, - output chanx_1__0__out_71_, - input chanx_1__0__in_72_, - output chanx_1__0__out_73_, - input chanx_1__0__in_74_, - output chanx_1__0__out_75_, - input chanx_1__0__in_76_, - output chanx_1__0__out_77_, - input chanx_1__0__in_78_, - output chanx_1__0__out_79_, - input chanx_1__0__in_80_, - output chanx_1__0__out_81_, - input chanx_1__0__in_82_, - output chanx_1__0__out_83_, - input chanx_1__0__in_84_, - output chanx_1__0__out_85_, - input chanx_1__0__in_86_, - output chanx_1__0__out_87_, - input chanx_1__0__in_88_, - output chanx_1__0__out_89_, - input chanx_1__0__in_90_, - output chanx_1__0__out_91_, - input chanx_1__0__in_92_, - output chanx_1__0__out_93_, - input chanx_1__0__in_94_, - output chanx_1__0__out_95_, - input chanx_1__0__in_96_, - output chanx_1__0__out_97_, - input chanx_1__0__in_98_, - output chanx_1__0__out_99_, -input grid_1__1__pin_0__2__42_, -input grid_1__1__pin_0__2__46_, -input grid_1__0__pin_0__0__1_, -input grid_1__0__pin_0__0__3_, -input grid_1__0__pin_0__0__5_, -input grid_1__0__pin_0__0__7_, -input grid_1__0__pin_0__0__9_, -input grid_1__0__pin_0__0__11_, -input grid_1__0__pin_0__0__13_, -input grid_1__0__pin_0__0__15_, -input [210:319] sram_blwl_bl , -input [210:319] sram_blwl_wl , -input [210:319] sram_blwl_blb ); -//----- top side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_200_inbus; -assign mux_1level_tapbuf_size3_200_inbus[0] = grid_1__1__pin_0__1__41_; -assign mux_1level_tapbuf_size3_200_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_200_inbus[2] = chanx_1__0__in_0_ ; -wire [210:212] mux_1level_tapbuf_size3_200_configbus0; -wire [210:212] mux_1level_tapbuf_size3_200_configbus1; -wire [210:212] mux_1level_tapbuf_size3_200_sram_blwl_out ; -wire [210:212] mux_1level_tapbuf_size3_200_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_200_configbus0[210:212] = sram_blwl_bl[210:212] ; -assign mux_1level_tapbuf_size3_200_configbus1[210:212] = sram_blwl_wl[210:212] ; -wire [210:212] mux_1level_tapbuf_size3_200_configbus0_b; -assign mux_1level_tapbuf_size3_200_configbus0_b[210:212] = sram_blwl_blb[210:212] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_200_ (mux_1level_tapbuf_size3_200_inbus, chany_1__1__out_0_ , mux_1level_tapbuf_size3_200_sram_blwl_out[210:212] , -mux_1level_tapbuf_size3_200_sram_blwl_outb[210:212] ); -//----- SRAM bits for MUX[200], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_210_ (mux_1level_tapbuf_size3_200_sram_blwl_out[210:210] ,mux_1level_tapbuf_size3_200_sram_blwl_out[210:210] ,mux_1level_tapbuf_size3_200_sram_blwl_outb[210:210] ,mux_1level_tapbuf_size3_200_configbus0[210:210], mux_1level_tapbuf_size3_200_configbus1[210:210] , mux_1level_tapbuf_size3_200_configbus0_b[210:210] ); -sram6T_blwl sram_blwl_211_ (mux_1level_tapbuf_size3_200_sram_blwl_out[211:211] ,mux_1level_tapbuf_size3_200_sram_blwl_out[211:211] ,mux_1level_tapbuf_size3_200_sram_blwl_outb[211:211] ,mux_1level_tapbuf_size3_200_configbus0[211:211], mux_1level_tapbuf_size3_200_configbus1[211:211] , mux_1level_tapbuf_size3_200_configbus0_b[211:211] ); -sram6T_blwl sram_blwl_212_ (mux_1level_tapbuf_size3_200_sram_blwl_out[212:212] ,mux_1level_tapbuf_size3_200_sram_blwl_out[212:212] ,mux_1level_tapbuf_size3_200_sram_blwl_outb[212:212] ,mux_1level_tapbuf_size3_200_configbus0[212:212], mux_1level_tapbuf_size3_200_configbus1[212:212] , mux_1level_tapbuf_size3_200_configbus0_b[212:212] ); -wire [0:2] mux_1level_tapbuf_size3_201_inbus; -assign mux_1level_tapbuf_size3_201_inbus[0] = grid_1__1__pin_0__1__41_; -assign mux_1level_tapbuf_size3_201_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_201_inbus[2] = chanx_1__0__in_98_ ; -wire [213:215] mux_1level_tapbuf_size3_201_configbus0; -wire [213:215] mux_1level_tapbuf_size3_201_configbus1; -wire [213:215] mux_1level_tapbuf_size3_201_sram_blwl_out ; -wire [213:215] mux_1level_tapbuf_size3_201_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_201_configbus0[213:215] = sram_blwl_bl[213:215] ; -assign mux_1level_tapbuf_size3_201_configbus1[213:215] = sram_blwl_wl[213:215] ; -wire [213:215] mux_1level_tapbuf_size3_201_configbus0_b; -assign mux_1level_tapbuf_size3_201_configbus0_b[213:215] = sram_blwl_blb[213:215] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_201_ (mux_1level_tapbuf_size3_201_inbus, chany_1__1__out_2_ , mux_1level_tapbuf_size3_201_sram_blwl_out[213:215] , -mux_1level_tapbuf_size3_201_sram_blwl_outb[213:215] ); -//----- SRAM bits for MUX[201], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_213_ (mux_1level_tapbuf_size3_201_sram_blwl_out[213:213] ,mux_1level_tapbuf_size3_201_sram_blwl_out[213:213] ,mux_1level_tapbuf_size3_201_sram_blwl_outb[213:213] ,mux_1level_tapbuf_size3_201_configbus0[213:213], mux_1level_tapbuf_size3_201_configbus1[213:213] , mux_1level_tapbuf_size3_201_configbus0_b[213:213] ); -sram6T_blwl sram_blwl_214_ (mux_1level_tapbuf_size3_201_sram_blwl_out[214:214] ,mux_1level_tapbuf_size3_201_sram_blwl_out[214:214] ,mux_1level_tapbuf_size3_201_sram_blwl_outb[214:214] ,mux_1level_tapbuf_size3_201_configbus0[214:214], mux_1level_tapbuf_size3_201_configbus1[214:214] , mux_1level_tapbuf_size3_201_configbus0_b[214:214] ); -sram6T_blwl sram_blwl_215_ (mux_1level_tapbuf_size3_201_sram_blwl_out[215:215] ,mux_1level_tapbuf_size3_201_sram_blwl_out[215:215] ,mux_1level_tapbuf_size3_201_sram_blwl_outb[215:215] ,mux_1level_tapbuf_size3_201_configbus0[215:215], mux_1level_tapbuf_size3_201_configbus1[215:215] , mux_1level_tapbuf_size3_201_configbus0_b[215:215] ); -wire [0:2] mux_1level_tapbuf_size3_202_inbus; -assign mux_1level_tapbuf_size3_202_inbus[0] = grid_1__1__pin_0__1__41_; -assign mux_1level_tapbuf_size3_202_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_202_inbus[2] = chanx_1__0__in_96_ ; -wire [216:218] mux_1level_tapbuf_size3_202_configbus0; -wire [216:218] mux_1level_tapbuf_size3_202_configbus1; -wire [216:218] mux_1level_tapbuf_size3_202_sram_blwl_out ; -wire [216:218] mux_1level_tapbuf_size3_202_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_202_configbus0[216:218] = sram_blwl_bl[216:218] ; -assign mux_1level_tapbuf_size3_202_configbus1[216:218] = sram_blwl_wl[216:218] ; -wire [216:218] mux_1level_tapbuf_size3_202_configbus0_b; -assign mux_1level_tapbuf_size3_202_configbus0_b[216:218] = sram_blwl_blb[216:218] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_202_ (mux_1level_tapbuf_size3_202_inbus, chany_1__1__out_4_ , mux_1level_tapbuf_size3_202_sram_blwl_out[216:218] , -mux_1level_tapbuf_size3_202_sram_blwl_outb[216:218] ); -//----- SRAM bits for MUX[202], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_216_ (mux_1level_tapbuf_size3_202_sram_blwl_out[216:216] ,mux_1level_tapbuf_size3_202_sram_blwl_out[216:216] ,mux_1level_tapbuf_size3_202_sram_blwl_outb[216:216] ,mux_1level_tapbuf_size3_202_configbus0[216:216], mux_1level_tapbuf_size3_202_configbus1[216:216] , mux_1level_tapbuf_size3_202_configbus0_b[216:216] ); -sram6T_blwl sram_blwl_217_ (mux_1level_tapbuf_size3_202_sram_blwl_out[217:217] ,mux_1level_tapbuf_size3_202_sram_blwl_out[217:217] ,mux_1level_tapbuf_size3_202_sram_blwl_outb[217:217] ,mux_1level_tapbuf_size3_202_configbus0[217:217], mux_1level_tapbuf_size3_202_configbus1[217:217] , mux_1level_tapbuf_size3_202_configbus0_b[217:217] ); -sram6T_blwl sram_blwl_218_ (mux_1level_tapbuf_size3_202_sram_blwl_out[218:218] ,mux_1level_tapbuf_size3_202_sram_blwl_out[218:218] ,mux_1level_tapbuf_size3_202_sram_blwl_outb[218:218] ,mux_1level_tapbuf_size3_202_configbus0[218:218], mux_1level_tapbuf_size3_202_configbus1[218:218] , mux_1level_tapbuf_size3_202_configbus0_b[218:218] ); -wire [0:2] mux_1level_tapbuf_size3_203_inbus; -assign mux_1level_tapbuf_size3_203_inbus[0] = grid_1__1__pin_0__1__41_; -assign mux_1level_tapbuf_size3_203_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_203_inbus[2] = chanx_1__0__in_94_ ; -wire [219:221] mux_1level_tapbuf_size3_203_configbus0; -wire [219:221] mux_1level_tapbuf_size3_203_configbus1; -wire [219:221] mux_1level_tapbuf_size3_203_sram_blwl_out ; -wire [219:221] mux_1level_tapbuf_size3_203_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_203_configbus0[219:221] = sram_blwl_bl[219:221] ; -assign mux_1level_tapbuf_size3_203_configbus1[219:221] = sram_blwl_wl[219:221] ; -wire [219:221] mux_1level_tapbuf_size3_203_configbus0_b; -assign mux_1level_tapbuf_size3_203_configbus0_b[219:221] = sram_blwl_blb[219:221] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_203_ (mux_1level_tapbuf_size3_203_inbus, chany_1__1__out_6_ , mux_1level_tapbuf_size3_203_sram_blwl_out[219:221] , -mux_1level_tapbuf_size3_203_sram_blwl_outb[219:221] ); -//----- SRAM bits for MUX[203], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_219_ (mux_1level_tapbuf_size3_203_sram_blwl_out[219:219] ,mux_1level_tapbuf_size3_203_sram_blwl_out[219:219] ,mux_1level_tapbuf_size3_203_sram_blwl_outb[219:219] ,mux_1level_tapbuf_size3_203_configbus0[219:219], mux_1level_tapbuf_size3_203_configbus1[219:219] , mux_1level_tapbuf_size3_203_configbus0_b[219:219] ); -sram6T_blwl sram_blwl_220_ (mux_1level_tapbuf_size3_203_sram_blwl_out[220:220] ,mux_1level_tapbuf_size3_203_sram_blwl_out[220:220] ,mux_1level_tapbuf_size3_203_sram_blwl_outb[220:220] ,mux_1level_tapbuf_size3_203_configbus0[220:220], mux_1level_tapbuf_size3_203_configbus1[220:220] , mux_1level_tapbuf_size3_203_configbus0_b[220:220] ); -sram6T_blwl sram_blwl_221_ (mux_1level_tapbuf_size3_203_sram_blwl_out[221:221] ,mux_1level_tapbuf_size3_203_sram_blwl_out[221:221] ,mux_1level_tapbuf_size3_203_sram_blwl_outb[221:221] ,mux_1level_tapbuf_size3_203_configbus0[221:221], mux_1level_tapbuf_size3_203_configbus1[221:221] , mux_1level_tapbuf_size3_203_configbus0_b[221:221] ); -wire [0:2] mux_1level_tapbuf_size3_204_inbus; -assign mux_1level_tapbuf_size3_204_inbus[0] = grid_1__1__pin_0__1__41_; -assign mux_1level_tapbuf_size3_204_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_204_inbus[2] = chanx_1__0__in_92_ ; -wire [222:224] mux_1level_tapbuf_size3_204_configbus0; -wire [222:224] mux_1level_tapbuf_size3_204_configbus1; -wire [222:224] mux_1level_tapbuf_size3_204_sram_blwl_out ; -wire [222:224] mux_1level_tapbuf_size3_204_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_204_configbus0[222:224] = sram_blwl_bl[222:224] ; -assign mux_1level_tapbuf_size3_204_configbus1[222:224] = sram_blwl_wl[222:224] ; -wire [222:224] mux_1level_tapbuf_size3_204_configbus0_b; -assign mux_1level_tapbuf_size3_204_configbus0_b[222:224] = sram_blwl_blb[222:224] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_204_ (mux_1level_tapbuf_size3_204_inbus, chany_1__1__out_8_ , mux_1level_tapbuf_size3_204_sram_blwl_out[222:224] , -mux_1level_tapbuf_size3_204_sram_blwl_outb[222:224] ); -//----- SRAM bits for MUX[204], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_222_ (mux_1level_tapbuf_size3_204_sram_blwl_out[222:222] ,mux_1level_tapbuf_size3_204_sram_blwl_out[222:222] ,mux_1level_tapbuf_size3_204_sram_blwl_outb[222:222] ,mux_1level_tapbuf_size3_204_configbus0[222:222], mux_1level_tapbuf_size3_204_configbus1[222:222] , mux_1level_tapbuf_size3_204_configbus0_b[222:222] ); -sram6T_blwl sram_blwl_223_ (mux_1level_tapbuf_size3_204_sram_blwl_out[223:223] ,mux_1level_tapbuf_size3_204_sram_blwl_out[223:223] ,mux_1level_tapbuf_size3_204_sram_blwl_outb[223:223] ,mux_1level_tapbuf_size3_204_configbus0[223:223], mux_1level_tapbuf_size3_204_configbus1[223:223] , mux_1level_tapbuf_size3_204_configbus0_b[223:223] ); -sram6T_blwl sram_blwl_224_ (mux_1level_tapbuf_size3_204_sram_blwl_out[224:224] ,mux_1level_tapbuf_size3_204_sram_blwl_out[224:224] ,mux_1level_tapbuf_size3_204_sram_blwl_outb[224:224] ,mux_1level_tapbuf_size3_204_configbus0[224:224], mux_1level_tapbuf_size3_204_configbus1[224:224] , mux_1level_tapbuf_size3_204_configbus0_b[224:224] ); -wire [0:1] mux_1level_tapbuf_size2_205_inbus; -assign mux_1level_tapbuf_size2_205_inbus[0] = grid_1__1__pin_0__1__45_; -assign mux_1level_tapbuf_size2_205_inbus[1] = chanx_1__0__in_90_ ; -wire [225:225] mux_1level_tapbuf_size2_205_configbus0; -wire [225:225] mux_1level_tapbuf_size2_205_configbus1; -wire [225:225] mux_1level_tapbuf_size2_205_sram_blwl_out ; -wire [225:225] mux_1level_tapbuf_size2_205_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_205_configbus0[225:225] = sram_blwl_bl[225:225] ; -assign mux_1level_tapbuf_size2_205_configbus1[225:225] = sram_blwl_wl[225:225] ; -wire [225:225] mux_1level_tapbuf_size2_205_configbus0_b; -assign mux_1level_tapbuf_size2_205_configbus0_b[225:225] = sram_blwl_blb[225:225] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_205_ (mux_1level_tapbuf_size2_205_inbus, chany_1__1__out_10_ , mux_1level_tapbuf_size2_205_sram_blwl_out[225:225] , -mux_1level_tapbuf_size2_205_sram_blwl_outb[225:225] ); -//----- SRAM bits for MUX[205], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_225_ (mux_1level_tapbuf_size2_205_sram_blwl_out[225:225] ,mux_1level_tapbuf_size2_205_sram_blwl_out[225:225] ,mux_1level_tapbuf_size2_205_sram_blwl_outb[225:225] ,mux_1level_tapbuf_size2_205_configbus0[225:225], mux_1level_tapbuf_size2_205_configbus1[225:225] , mux_1level_tapbuf_size2_205_configbus0_b[225:225] ); -wire [0:1] mux_1level_tapbuf_size2_206_inbus; -assign mux_1level_tapbuf_size2_206_inbus[0] = grid_1__1__pin_0__1__45_; -assign mux_1level_tapbuf_size2_206_inbus[1] = chanx_1__0__in_88_ ; -wire [226:226] mux_1level_tapbuf_size2_206_configbus0; -wire [226:226] mux_1level_tapbuf_size2_206_configbus1; -wire [226:226] mux_1level_tapbuf_size2_206_sram_blwl_out ; -wire [226:226] mux_1level_tapbuf_size2_206_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_206_configbus0[226:226] = sram_blwl_bl[226:226] ; -assign mux_1level_tapbuf_size2_206_configbus1[226:226] = sram_blwl_wl[226:226] ; -wire [226:226] mux_1level_tapbuf_size2_206_configbus0_b; -assign mux_1level_tapbuf_size2_206_configbus0_b[226:226] = sram_blwl_blb[226:226] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_206_ (mux_1level_tapbuf_size2_206_inbus, chany_1__1__out_12_ , mux_1level_tapbuf_size2_206_sram_blwl_out[226:226] , -mux_1level_tapbuf_size2_206_sram_blwl_outb[226:226] ); -//----- SRAM bits for MUX[206], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_226_ (mux_1level_tapbuf_size2_206_sram_blwl_out[226:226] ,mux_1level_tapbuf_size2_206_sram_blwl_out[226:226] ,mux_1level_tapbuf_size2_206_sram_blwl_outb[226:226] ,mux_1level_tapbuf_size2_206_configbus0[226:226], mux_1level_tapbuf_size2_206_configbus1[226:226] , mux_1level_tapbuf_size2_206_configbus0_b[226:226] ); -wire [0:1] mux_1level_tapbuf_size2_207_inbus; -assign mux_1level_tapbuf_size2_207_inbus[0] = grid_1__1__pin_0__1__45_; -assign mux_1level_tapbuf_size2_207_inbus[1] = chanx_1__0__in_86_ ; -wire [227:227] mux_1level_tapbuf_size2_207_configbus0; -wire [227:227] mux_1level_tapbuf_size2_207_configbus1; -wire [227:227] mux_1level_tapbuf_size2_207_sram_blwl_out ; -wire [227:227] mux_1level_tapbuf_size2_207_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_207_configbus0[227:227] = sram_blwl_bl[227:227] ; -assign mux_1level_tapbuf_size2_207_configbus1[227:227] = sram_blwl_wl[227:227] ; -wire [227:227] mux_1level_tapbuf_size2_207_configbus0_b; -assign mux_1level_tapbuf_size2_207_configbus0_b[227:227] = sram_blwl_blb[227:227] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_207_ (mux_1level_tapbuf_size2_207_inbus, chany_1__1__out_14_ , mux_1level_tapbuf_size2_207_sram_blwl_out[227:227] , -mux_1level_tapbuf_size2_207_sram_blwl_outb[227:227] ); -//----- SRAM bits for MUX[207], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_227_ (mux_1level_tapbuf_size2_207_sram_blwl_out[227:227] ,mux_1level_tapbuf_size2_207_sram_blwl_out[227:227] ,mux_1level_tapbuf_size2_207_sram_blwl_outb[227:227] ,mux_1level_tapbuf_size2_207_configbus0[227:227], mux_1level_tapbuf_size2_207_configbus1[227:227] , mux_1level_tapbuf_size2_207_configbus0_b[227:227] ); -wire [0:1] mux_1level_tapbuf_size2_208_inbus; -assign mux_1level_tapbuf_size2_208_inbus[0] = grid_1__1__pin_0__1__45_; -assign mux_1level_tapbuf_size2_208_inbus[1] = chanx_1__0__in_84_ ; -wire [228:228] mux_1level_tapbuf_size2_208_configbus0; -wire [228:228] mux_1level_tapbuf_size2_208_configbus1; -wire [228:228] mux_1level_tapbuf_size2_208_sram_blwl_out ; -wire [228:228] mux_1level_tapbuf_size2_208_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_208_configbus0[228:228] = sram_blwl_bl[228:228] ; -assign mux_1level_tapbuf_size2_208_configbus1[228:228] = sram_blwl_wl[228:228] ; -wire [228:228] mux_1level_tapbuf_size2_208_configbus0_b; -assign mux_1level_tapbuf_size2_208_configbus0_b[228:228] = sram_blwl_blb[228:228] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_208_ (mux_1level_tapbuf_size2_208_inbus, chany_1__1__out_16_ , mux_1level_tapbuf_size2_208_sram_blwl_out[228:228] , -mux_1level_tapbuf_size2_208_sram_blwl_outb[228:228] ); -//----- SRAM bits for MUX[208], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_228_ (mux_1level_tapbuf_size2_208_sram_blwl_out[228:228] ,mux_1level_tapbuf_size2_208_sram_blwl_out[228:228] ,mux_1level_tapbuf_size2_208_sram_blwl_outb[228:228] ,mux_1level_tapbuf_size2_208_configbus0[228:228], mux_1level_tapbuf_size2_208_configbus1[228:228] , mux_1level_tapbuf_size2_208_configbus0_b[228:228] ); -wire [0:1] mux_1level_tapbuf_size2_209_inbus; -assign mux_1level_tapbuf_size2_209_inbus[0] = grid_1__1__pin_0__1__45_; -assign mux_1level_tapbuf_size2_209_inbus[1] = chanx_1__0__in_82_ ; -wire [229:229] mux_1level_tapbuf_size2_209_configbus0; -wire [229:229] mux_1level_tapbuf_size2_209_configbus1; -wire [229:229] mux_1level_tapbuf_size2_209_sram_blwl_out ; -wire [229:229] mux_1level_tapbuf_size2_209_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_209_configbus0[229:229] = sram_blwl_bl[229:229] ; -assign mux_1level_tapbuf_size2_209_configbus1[229:229] = sram_blwl_wl[229:229] ; -wire [229:229] mux_1level_tapbuf_size2_209_configbus0_b; -assign mux_1level_tapbuf_size2_209_configbus0_b[229:229] = sram_blwl_blb[229:229] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_209_ (mux_1level_tapbuf_size2_209_inbus, chany_1__1__out_18_ , mux_1level_tapbuf_size2_209_sram_blwl_out[229:229] , -mux_1level_tapbuf_size2_209_sram_blwl_outb[229:229] ); -//----- SRAM bits for MUX[209], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_229_ (mux_1level_tapbuf_size2_209_sram_blwl_out[229:229] ,mux_1level_tapbuf_size2_209_sram_blwl_out[229:229] ,mux_1level_tapbuf_size2_209_sram_blwl_outb[229:229] ,mux_1level_tapbuf_size2_209_configbus0[229:229], mux_1level_tapbuf_size2_209_configbus1[229:229] , mux_1level_tapbuf_size2_209_configbus0_b[229:229] ); -wire [0:1] mux_1level_tapbuf_size2_210_inbus; -assign mux_1level_tapbuf_size2_210_inbus[0] = grid_1__1__pin_0__1__49_; -assign mux_1level_tapbuf_size2_210_inbus[1] = chanx_1__0__in_80_ ; -wire [230:230] mux_1level_tapbuf_size2_210_configbus0; -wire [230:230] mux_1level_tapbuf_size2_210_configbus1; -wire [230:230] mux_1level_tapbuf_size2_210_sram_blwl_out ; -wire [230:230] mux_1level_tapbuf_size2_210_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_210_configbus0[230:230] = sram_blwl_bl[230:230] ; -assign mux_1level_tapbuf_size2_210_configbus1[230:230] = sram_blwl_wl[230:230] ; -wire [230:230] mux_1level_tapbuf_size2_210_configbus0_b; -assign mux_1level_tapbuf_size2_210_configbus0_b[230:230] = sram_blwl_blb[230:230] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_210_ (mux_1level_tapbuf_size2_210_inbus, chany_1__1__out_20_ , mux_1level_tapbuf_size2_210_sram_blwl_out[230:230] , -mux_1level_tapbuf_size2_210_sram_blwl_outb[230:230] ); -//----- SRAM bits for MUX[210], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_230_ (mux_1level_tapbuf_size2_210_sram_blwl_out[230:230] ,mux_1level_tapbuf_size2_210_sram_blwl_out[230:230] ,mux_1level_tapbuf_size2_210_sram_blwl_outb[230:230] ,mux_1level_tapbuf_size2_210_configbus0[230:230], mux_1level_tapbuf_size2_210_configbus1[230:230] , mux_1level_tapbuf_size2_210_configbus0_b[230:230] ); -wire [0:1] mux_1level_tapbuf_size2_211_inbus; -assign mux_1level_tapbuf_size2_211_inbus[0] = grid_1__1__pin_0__1__49_; -assign mux_1level_tapbuf_size2_211_inbus[1] = chanx_1__0__in_78_ ; -wire [231:231] mux_1level_tapbuf_size2_211_configbus0; -wire [231:231] mux_1level_tapbuf_size2_211_configbus1; -wire [231:231] mux_1level_tapbuf_size2_211_sram_blwl_out ; -wire [231:231] mux_1level_tapbuf_size2_211_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_211_configbus0[231:231] = sram_blwl_bl[231:231] ; -assign mux_1level_tapbuf_size2_211_configbus1[231:231] = sram_blwl_wl[231:231] ; -wire [231:231] mux_1level_tapbuf_size2_211_configbus0_b; -assign mux_1level_tapbuf_size2_211_configbus0_b[231:231] = sram_blwl_blb[231:231] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_211_ (mux_1level_tapbuf_size2_211_inbus, chany_1__1__out_22_ , mux_1level_tapbuf_size2_211_sram_blwl_out[231:231] , -mux_1level_tapbuf_size2_211_sram_blwl_outb[231:231] ); -//----- SRAM bits for MUX[211], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_231_ (mux_1level_tapbuf_size2_211_sram_blwl_out[231:231] ,mux_1level_tapbuf_size2_211_sram_blwl_out[231:231] ,mux_1level_tapbuf_size2_211_sram_blwl_outb[231:231] ,mux_1level_tapbuf_size2_211_configbus0[231:231], mux_1level_tapbuf_size2_211_configbus1[231:231] , mux_1level_tapbuf_size2_211_configbus0_b[231:231] ); -wire [0:1] mux_1level_tapbuf_size2_212_inbus; -assign mux_1level_tapbuf_size2_212_inbus[0] = grid_1__1__pin_0__1__49_; -assign mux_1level_tapbuf_size2_212_inbus[1] = chanx_1__0__in_76_ ; -wire [232:232] mux_1level_tapbuf_size2_212_configbus0; -wire [232:232] mux_1level_tapbuf_size2_212_configbus1; -wire [232:232] mux_1level_tapbuf_size2_212_sram_blwl_out ; -wire [232:232] mux_1level_tapbuf_size2_212_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_212_configbus0[232:232] = sram_blwl_bl[232:232] ; -assign mux_1level_tapbuf_size2_212_configbus1[232:232] = sram_blwl_wl[232:232] ; -wire [232:232] mux_1level_tapbuf_size2_212_configbus0_b; -assign mux_1level_tapbuf_size2_212_configbus0_b[232:232] = sram_blwl_blb[232:232] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_212_ (mux_1level_tapbuf_size2_212_inbus, chany_1__1__out_24_ , mux_1level_tapbuf_size2_212_sram_blwl_out[232:232] , -mux_1level_tapbuf_size2_212_sram_blwl_outb[232:232] ); -//----- SRAM bits for MUX[212], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_232_ (mux_1level_tapbuf_size2_212_sram_blwl_out[232:232] ,mux_1level_tapbuf_size2_212_sram_blwl_out[232:232] ,mux_1level_tapbuf_size2_212_sram_blwl_outb[232:232] ,mux_1level_tapbuf_size2_212_configbus0[232:232], mux_1level_tapbuf_size2_212_configbus1[232:232] , mux_1level_tapbuf_size2_212_configbus0_b[232:232] ); -wire [0:1] mux_1level_tapbuf_size2_213_inbus; -assign mux_1level_tapbuf_size2_213_inbus[0] = grid_1__1__pin_0__1__49_; -assign mux_1level_tapbuf_size2_213_inbus[1] = chanx_1__0__in_74_ ; -wire [233:233] mux_1level_tapbuf_size2_213_configbus0; -wire [233:233] mux_1level_tapbuf_size2_213_configbus1; -wire [233:233] mux_1level_tapbuf_size2_213_sram_blwl_out ; -wire [233:233] mux_1level_tapbuf_size2_213_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_213_configbus0[233:233] = sram_blwl_bl[233:233] ; -assign mux_1level_tapbuf_size2_213_configbus1[233:233] = sram_blwl_wl[233:233] ; -wire [233:233] mux_1level_tapbuf_size2_213_configbus0_b; -assign mux_1level_tapbuf_size2_213_configbus0_b[233:233] = sram_blwl_blb[233:233] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_213_ (mux_1level_tapbuf_size2_213_inbus, chany_1__1__out_26_ , mux_1level_tapbuf_size2_213_sram_blwl_out[233:233] , -mux_1level_tapbuf_size2_213_sram_blwl_outb[233:233] ); -//----- SRAM bits for MUX[213], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_233_ (mux_1level_tapbuf_size2_213_sram_blwl_out[233:233] ,mux_1level_tapbuf_size2_213_sram_blwl_out[233:233] ,mux_1level_tapbuf_size2_213_sram_blwl_outb[233:233] ,mux_1level_tapbuf_size2_213_configbus0[233:233], mux_1level_tapbuf_size2_213_configbus1[233:233] , mux_1level_tapbuf_size2_213_configbus0_b[233:233] ); -wire [0:1] mux_1level_tapbuf_size2_214_inbus; -assign mux_1level_tapbuf_size2_214_inbus[0] = grid_1__1__pin_0__1__49_; -assign mux_1level_tapbuf_size2_214_inbus[1] = chanx_1__0__in_72_ ; -wire [234:234] mux_1level_tapbuf_size2_214_configbus0; -wire [234:234] mux_1level_tapbuf_size2_214_configbus1; -wire [234:234] mux_1level_tapbuf_size2_214_sram_blwl_out ; -wire [234:234] mux_1level_tapbuf_size2_214_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_214_configbus0[234:234] = sram_blwl_bl[234:234] ; -assign mux_1level_tapbuf_size2_214_configbus1[234:234] = sram_blwl_wl[234:234] ; -wire [234:234] mux_1level_tapbuf_size2_214_configbus0_b; -assign mux_1level_tapbuf_size2_214_configbus0_b[234:234] = sram_blwl_blb[234:234] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_214_ (mux_1level_tapbuf_size2_214_inbus, chany_1__1__out_28_ , mux_1level_tapbuf_size2_214_sram_blwl_out[234:234] , -mux_1level_tapbuf_size2_214_sram_blwl_outb[234:234] ); -//----- SRAM bits for MUX[214], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_234_ (mux_1level_tapbuf_size2_214_sram_blwl_out[234:234] ,mux_1level_tapbuf_size2_214_sram_blwl_out[234:234] ,mux_1level_tapbuf_size2_214_sram_blwl_outb[234:234] ,mux_1level_tapbuf_size2_214_configbus0[234:234], mux_1level_tapbuf_size2_214_configbus1[234:234] , mux_1level_tapbuf_size2_214_configbus0_b[234:234] ); -wire [0:1] mux_1level_tapbuf_size2_215_inbus; -assign mux_1level_tapbuf_size2_215_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_215_inbus[1] = chanx_1__0__in_70_ ; -wire [235:235] mux_1level_tapbuf_size2_215_configbus0; -wire [235:235] mux_1level_tapbuf_size2_215_configbus1; -wire [235:235] mux_1level_tapbuf_size2_215_sram_blwl_out ; -wire [235:235] mux_1level_tapbuf_size2_215_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_215_configbus0[235:235] = sram_blwl_bl[235:235] ; -assign mux_1level_tapbuf_size2_215_configbus1[235:235] = sram_blwl_wl[235:235] ; -wire [235:235] mux_1level_tapbuf_size2_215_configbus0_b; -assign mux_1level_tapbuf_size2_215_configbus0_b[235:235] = sram_blwl_blb[235:235] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_215_ (mux_1level_tapbuf_size2_215_inbus, chany_1__1__out_30_ , mux_1level_tapbuf_size2_215_sram_blwl_out[235:235] , -mux_1level_tapbuf_size2_215_sram_blwl_outb[235:235] ); -//----- SRAM bits for MUX[215], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_235_ (mux_1level_tapbuf_size2_215_sram_blwl_out[235:235] ,mux_1level_tapbuf_size2_215_sram_blwl_out[235:235] ,mux_1level_tapbuf_size2_215_sram_blwl_outb[235:235] ,mux_1level_tapbuf_size2_215_configbus0[235:235], mux_1level_tapbuf_size2_215_configbus1[235:235] , mux_1level_tapbuf_size2_215_configbus0_b[235:235] ); -wire [0:1] mux_1level_tapbuf_size2_216_inbus; -assign mux_1level_tapbuf_size2_216_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_216_inbus[1] = chanx_1__0__in_68_ ; -wire [236:236] mux_1level_tapbuf_size2_216_configbus0; -wire [236:236] mux_1level_tapbuf_size2_216_configbus1; -wire [236:236] mux_1level_tapbuf_size2_216_sram_blwl_out ; -wire [236:236] mux_1level_tapbuf_size2_216_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_216_configbus0[236:236] = sram_blwl_bl[236:236] ; -assign mux_1level_tapbuf_size2_216_configbus1[236:236] = sram_blwl_wl[236:236] ; -wire [236:236] mux_1level_tapbuf_size2_216_configbus0_b; -assign mux_1level_tapbuf_size2_216_configbus0_b[236:236] = sram_blwl_blb[236:236] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_216_ (mux_1level_tapbuf_size2_216_inbus, chany_1__1__out_32_ , mux_1level_tapbuf_size2_216_sram_blwl_out[236:236] , -mux_1level_tapbuf_size2_216_sram_blwl_outb[236:236] ); -//----- SRAM bits for MUX[216], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_236_ (mux_1level_tapbuf_size2_216_sram_blwl_out[236:236] ,mux_1level_tapbuf_size2_216_sram_blwl_out[236:236] ,mux_1level_tapbuf_size2_216_sram_blwl_outb[236:236] ,mux_1level_tapbuf_size2_216_configbus0[236:236], mux_1level_tapbuf_size2_216_configbus1[236:236] , mux_1level_tapbuf_size2_216_configbus0_b[236:236] ); -wire [0:1] mux_1level_tapbuf_size2_217_inbus; -assign mux_1level_tapbuf_size2_217_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_217_inbus[1] = chanx_1__0__in_66_ ; -wire [237:237] mux_1level_tapbuf_size2_217_configbus0; -wire [237:237] mux_1level_tapbuf_size2_217_configbus1; -wire [237:237] mux_1level_tapbuf_size2_217_sram_blwl_out ; -wire [237:237] mux_1level_tapbuf_size2_217_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_217_configbus0[237:237] = sram_blwl_bl[237:237] ; -assign mux_1level_tapbuf_size2_217_configbus1[237:237] = sram_blwl_wl[237:237] ; -wire [237:237] mux_1level_tapbuf_size2_217_configbus0_b; -assign mux_1level_tapbuf_size2_217_configbus0_b[237:237] = sram_blwl_blb[237:237] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_217_ (mux_1level_tapbuf_size2_217_inbus, chany_1__1__out_34_ , mux_1level_tapbuf_size2_217_sram_blwl_out[237:237] , -mux_1level_tapbuf_size2_217_sram_blwl_outb[237:237] ); -//----- SRAM bits for MUX[217], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_237_ (mux_1level_tapbuf_size2_217_sram_blwl_out[237:237] ,mux_1level_tapbuf_size2_217_sram_blwl_out[237:237] ,mux_1level_tapbuf_size2_217_sram_blwl_outb[237:237] ,mux_1level_tapbuf_size2_217_configbus0[237:237], mux_1level_tapbuf_size2_217_configbus1[237:237] , mux_1level_tapbuf_size2_217_configbus0_b[237:237] ); -wire [0:1] mux_1level_tapbuf_size2_218_inbus; -assign mux_1level_tapbuf_size2_218_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_218_inbus[1] = chanx_1__0__in_64_ ; -wire [238:238] mux_1level_tapbuf_size2_218_configbus0; -wire [238:238] mux_1level_tapbuf_size2_218_configbus1; -wire [238:238] mux_1level_tapbuf_size2_218_sram_blwl_out ; -wire [238:238] mux_1level_tapbuf_size2_218_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_218_configbus0[238:238] = sram_blwl_bl[238:238] ; -assign mux_1level_tapbuf_size2_218_configbus1[238:238] = sram_blwl_wl[238:238] ; -wire [238:238] mux_1level_tapbuf_size2_218_configbus0_b; -assign mux_1level_tapbuf_size2_218_configbus0_b[238:238] = sram_blwl_blb[238:238] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_218_ (mux_1level_tapbuf_size2_218_inbus, chany_1__1__out_36_ , mux_1level_tapbuf_size2_218_sram_blwl_out[238:238] , -mux_1level_tapbuf_size2_218_sram_blwl_outb[238:238] ); -//----- SRAM bits for MUX[218], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_238_ (mux_1level_tapbuf_size2_218_sram_blwl_out[238:238] ,mux_1level_tapbuf_size2_218_sram_blwl_out[238:238] ,mux_1level_tapbuf_size2_218_sram_blwl_outb[238:238] ,mux_1level_tapbuf_size2_218_configbus0[238:238], mux_1level_tapbuf_size2_218_configbus1[238:238] , mux_1level_tapbuf_size2_218_configbus0_b[238:238] ); -wire [0:1] mux_1level_tapbuf_size2_219_inbus; -assign mux_1level_tapbuf_size2_219_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_219_inbus[1] = chanx_1__0__in_62_ ; -wire [239:239] mux_1level_tapbuf_size2_219_configbus0; -wire [239:239] mux_1level_tapbuf_size2_219_configbus1; -wire [239:239] mux_1level_tapbuf_size2_219_sram_blwl_out ; -wire [239:239] mux_1level_tapbuf_size2_219_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_219_configbus0[239:239] = sram_blwl_bl[239:239] ; -assign mux_1level_tapbuf_size2_219_configbus1[239:239] = sram_blwl_wl[239:239] ; -wire [239:239] mux_1level_tapbuf_size2_219_configbus0_b; -assign mux_1level_tapbuf_size2_219_configbus0_b[239:239] = sram_blwl_blb[239:239] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_219_ (mux_1level_tapbuf_size2_219_inbus, chany_1__1__out_38_ , mux_1level_tapbuf_size2_219_sram_blwl_out[239:239] , -mux_1level_tapbuf_size2_219_sram_blwl_outb[239:239] ); -//----- SRAM bits for MUX[219], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_239_ (mux_1level_tapbuf_size2_219_sram_blwl_out[239:239] ,mux_1level_tapbuf_size2_219_sram_blwl_out[239:239] ,mux_1level_tapbuf_size2_219_sram_blwl_outb[239:239] ,mux_1level_tapbuf_size2_219_configbus0[239:239], mux_1level_tapbuf_size2_219_configbus1[239:239] , mux_1level_tapbuf_size2_219_configbus0_b[239:239] ); -wire [0:1] mux_1level_tapbuf_size2_220_inbus; -assign mux_1level_tapbuf_size2_220_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_220_inbus[1] = chanx_1__0__in_60_ ; -wire [240:240] mux_1level_tapbuf_size2_220_configbus0; -wire [240:240] mux_1level_tapbuf_size2_220_configbus1; -wire [240:240] mux_1level_tapbuf_size2_220_sram_blwl_out ; -wire [240:240] mux_1level_tapbuf_size2_220_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_220_configbus0[240:240] = sram_blwl_bl[240:240] ; -assign mux_1level_tapbuf_size2_220_configbus1[240:240] = sram_blwl_wl[240:240] ; -wire [240:240] mux_1level_tapbuf_size2_220_configbus0_b; -assign mux_1level_tapbuf_size2_220_configbus0_b[240:240] = sram_blwl_blb[240:240] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_220_ (mux_1level_tapbuf_size2_220_inbus, chany_1__1__out_40_ , mux_1level_tapbuf_size2_220_sram_blwl_out[240:240] , -mux_1level_tapbuf_size2_220_sram_blwl_outb[240:240] ); -//----- SRAM bits for MUX[220], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_240_ (mux_1level_tapbuf_size2_220_sram_blwl_out[240:240] ,mux_1level_tapbuf_size2_220_sram_blwl_out[240:240] ,mux_1level_tapbuf_size2_220_sram_blwl_outb[240:240] ,mux_1level_tapbuf_size2_220_configbus0[240:240], mux_1level_tapbuf_size2_220_configbus1[240:240] , mux_1level_tapbuf_size2_220_configbus0_b[240:240] ); -wire [0:1] mux_1level_tapbuf_size2_221_inbus; -assign mux_1level_tapbuf_size2_221_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_221_inbus[1] = chanx_1__0__in_58_ ; -wire [241:241] mux_1level_tapbuf_size2_221_configbus0; -wire [241:241] mux_1level_tapbuf_size2_221_configbus1; -wire [241:241] mux_1level_tapbuf_size2_221_sram_blwl_out ; -wire [241:241] mux_1level_tapbuf_size2_221_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_221_configbus0[241:241] = sram_blwl_bl[241:241] ; -assign mux_1level_tapbuf_size2_221_configbus1[241:241] = sram_blwl_wl[241:241] ; -wire [241:241] mux_1level_tapbuf_size2_221_configbus0_b; -assign mux_1level_tapbuf_size2_221_configbus0_b[241:241] = sram_blwl_blb[241:241] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_221_ (mux_1level_tapbuf_size2_221_inbus, chany_1__1__out_42_ , mux_1level_tapbuf_size2_221_sram_blwl_out[241:241] , -mux_1level_tapbuf_size2_221_sram_blwl_outb[241:241] ); -//----- SRAM bits for MUX[221], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_241_ (mux_1level_tapbuf_size2_221_sram_blwl_out[241:241] ,mux_1level_tapbuf_size2_221_sram_blwl_out[241:241] ,mux_1level_tapbuf_size2_221_sram_blwl_outb[241:241] ,mux_1level_tapbuf_size2_221_configbus0[241:241], mux_1level_tapbuf_size2_221_configbus1[241:241] , mux_1level_tapbuf_size2_221_configbus0_b[241:241] ); -wire [0:1] mux_1level_tapbuf_size2_222_inbus; -assign mux_1level_tapbuf_size2_222_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_222_inbus[1] = chanx_1__0__in_56_ ; -wire [242:242] mux_1level_tapbuf_size2_222_configbus0; -wire [242:242] mux_1level_tapbuf_size2_222_configbus1; -wire [242:242] mux_1level_tapbuf_size2_222_sram_blwl_out ; -wire [242:242] mux_1level_tapbuf_size2_222_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_222_configbus0[242:242] = sram_blwl_bl[242:242] ; -assign mux_1level_tapbuf_size2_222_configbus1[242:242] = sram_blwl_wl[242:242] ; -wire [242:242] mux_1level_tapbuf_size2_222_configbus0_b; -assign mux_1level_tapbuf_size2_222_configbus0_b[242:242] = sram_blwl_blb[242:242] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_222_ (mux_1level_tapbuf_size2_222_inbus, chany_1__1__out_44_ , mux_1level_tapbuf_size2_222_sram_blwl_out[242:242] , -mux_1level_tapbuf_size2_222_sram_blwl_outb[242:242] ); -//----- SRAM bits for MUX[222], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_242_ (mux_1level_tapbuf_size2_222_sram_blwl_out[242:242] ,mux_1level_tapbuf_size2_222_sram_blwl_out[242:242] ,mux_1level_tapbuf_size2_222_sram_blwl_outb[242:242] ,mux_1level_tapbuf_size2_222_configbus0[242:242], mux_1level_tapbuf_size2_222_configbus1[242:242] , mux_1level_tapbuf_size2_222_configbus0_b[242:242] ); -wire [0:1] mux_1level_tapbuf_size2_223_inbus; -assign mux_1level_tapbuf_size2_223_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_223_inbus[1] = chanx_1__0__in_54_ ; -wire [243:243] mux_1level_tapbuf_size2_223_configbus0; -wire [243:243] mux_1level_tapbuf_size2_223_configbus1; -wire [243:243] mux_1level_tapbuf_size2_223_sram_blwl_out ; -wire [243:243] mux_1level_tapbuf_size2_223_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_223_configbus0[243:243] = sram_blwl_bl[243:243] ; -assign mux_1level_tapbuf_size2_223_configbus1[243:243] = sram_blwl_wl[243:243] ; -wire [243:243] mux_1level_tapbuf_size2_223_configbus0_b; -assign mux_1level_tapbuf_size2_223_configbus0_b[243:243] = sram_blwl_blb[243:243] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_223_ (mux_1level_tapbuf_size2_223_inbus, chany_1__1__out_46_ , mux_1level_tapbuf_size2_223_sram_blwl_out[243:243] , -mux_1level_tapbuf_size2_223_sram_blwl_outb[243:243] ); -//----- SRAM bits for MUX[223], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_243_ (mux_1level_tapbuf_size2_223_sram_blwl_out[243:243] ,mux_1level_tapbuf_size2_223_sram_blwl_out[243:243] ,mux_1level_tapbuf_size2_223_sram_blwl_outb[243:243] ,mux_1level_tapbuf_size2_223_configbus0[243:243], mux_1level_tapbuf_size2_223_configbus1[243:243] , mux_1level_tapbuf_size2_223_configbus0_b[243:243] ); -wire [0:1] mux_1level_tapbuf_size2_224_inbus; -assign mux_1level_tapbuf_size2_224_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_224_inbus[1] = chanx_1__0__in_52_ ; -wire [244:244] mux_1level_tapbuf_size2_224_configbus0; -wire [244:244] mux_1level_tapbuf_size2_224_configbus1; -wire [244:244] mux_1level_tapbuf_size2_224_sram_blwl_out ; -wire [244:244] mux_1level_tapbuf_size2_224_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_224_configbus0[244:244] = sram_blwl_bl[244:244] ; -assign mux_1level_tapbuf_size2_224_configbus1[244:244] = sram_blwl_wl[244:244] ; -wire [244:244] mux_1level_tapbuf_size2_224_configbus0_b; -assign mux_1level_tapbuf_size2_224_configbus0_b[244:244] = sram_blwl_blb[244:244] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_224_ (mux_1level_tapbuf_size2_224_inbus, chany_1__1__out_48_ , mux_1level_tapbuf_size2_224_sram_blwl_out[244:244] , -mux_1level_tapbuf_size2_224_sram_blwl_outb[244:244] ); -//----- SRAM bits for MUX[224], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_244_ (mux_1level_tapbuf_size2_224_sram_blwl_out[244:244] ,mux_1level_tapbuf_size2_224_sram_blwl_out[244:244] ,mux_1level_tapbuf_size2_224_sram_blwl_outb[244:244] ,mux_1level_tapbuf_size2_224_configbus0[244:244], mux_1level_tapbuf_size2_224_configbus1[244:244] , mux_1level_tapbuf_size2_224_configbus0_b[244:244] ); -wire [0:1] mux_1level_tapbuf_size2_225_inbus; -assign mux_1level_tapbuf_size2_225_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_225_inbus[1] = chanx_1__0__in_50_ ; -wire [245:245] mux_1level_tapbuf_size2_225_configbus0; -wire [245:245] mux_1level_tapbuf_size2_225_configbus1; -wire [245:245] mux_1level_tapbuf_size2_225_sram_blwl_out ; -wire [245:245] mux_1level_tapbuf_size2_225_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_225_configbus0[245:245] = sram_blwl_bl[245:245] ; -assign mux_1level_tapbuf_size2_225_configbus1[245:245] = sram_blwl_wl[245:245] ; -wire [245:245] mux_1level_tapbuf_size2_225_configbus0_b; -assign mux_1level_tapbuf_size2_225_configbus0_b[245:245] = sram_blwl_blb[245:245] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_225_ (mux_1level_tapbuf_size2_225_inbus, chany_1__1__out_50_ , mux_1level_tapbuf_size2_225_sram_blwl_out[245:245] , -mux_1level_tapbuf_size2_225_sram_blwl_outb[245:245] ); -//----- SRAM bits for MUX[225], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_245_ (mux_1level_tapbuf_size2_225_sram_blwl_out[245:245] ,mux_1level_tapbuf_size2_225_sram_blwl_out[245:245] ,mux_1level_tapbuf_size2_225_sram_blwl_outb[245:245] ,mux_1level_tapbuf_size2_225_configbus0[245:245], mux_1level_tapbuf_size2_225_configbus1[245:245] , mux_1level_tapbuf_size2_225_configbus0_b[245:245] ); -wire [0:1] mux_1level_tapbuf_size2_226_inbus; -assign mux_1level_tapbuf_size2_226_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_226_inbus[1] = chanx_1__0__in_48_ ; -wire [246:246] mux_1level_tapbuf_size2_226_configbus0; -wire [246:246] mux_1level_tapbuf_size2_226_configbus1; -wire [246:246] mux_1level_tapbuf_size2_226_sram_blwl_out ; -wire [246:246] mux_1level_tapbuf_size2_226_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_226_configbus0[246:246] = sram_blwl_bl[246:246] ; -assign mux_1level_tapbuf_size2_226_configbus1[246:246] = sram_blwl_wl[246:246] ; -wire [246:246] mux_1level_tapbuf_size2_226_configbus0_b; -assign mux_1level_tapbuf_size2_226_configbus0_b[246:246] = sram_blwl_blb[246:246] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_226_ (mux_1level_tapbuf_size2_226_inbus, chany_1__1__out_52_ , mux_1level_tapbuf_size2_226_sram_blwl_out[246:246] , -mux_1level_tapbuf_size2_226_sram_blwl_outb[246:246] ); -//----- SRAM bits for MUX[226], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_246_ (mux_1level_tapbuf_size2_226_sram_blwl_out[246:246] ,mux_1level_tapbuf_size2_226_sram_blwl_out[246:246] ,mux_1level_tapbuf_size2_226_sram_blwl_outb[246:246] ,mux_1level_tapbuf_size2_226_configbus0[246:246], mux_1level_tapbuf_size2_226_configbus1[246:246] , mux_1level_tapbuf_size2_226_configbus0_b[246:246] ); -wire [0:1] mux_1level_tapbuf_size2_227_inbus; -assign mux_1level_tapbuf_size2_227_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_227_inbus[1] = chanx_1__0__in_46_ ; -wire [247:247] mux_1level_tapbuf_size2_227_configbus0; -wire [247:247] mux_1level_tapbuf_size2_227_configbus1; -wire [247:247] mux_1level_tapbuf_size2_227_sram_blwl_out ; -wire [247:247] mux_1level_tapbuf_size2_227_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_227_configbus0[247:247] = sram_blwl_bl[247:247] ; -assign mux_1level_tapbuf_size2_227_configbus1[247:247] = sram_blwl_wl[247:247] ; -wire [247:247] mux_1level_tapbuf_size2_227_configbus0_b; -assign mux_1level_tapbuf_size2_227_configbus0_b[247:247] = sram_blwl_blb[247:247] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_227_ (mux_1level_tapbuf_size2_227_inbus, chany_1__1__out_54_ , mux_1level_tapbuf_size2_227_sram_blwl_out[247:247] , -mux_1level_tapbuf_size2_227_sram_blwl_outb[247:247] ); -//----- SRAM bits for MUX[227], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_247_ (mux_1level_tapbuf_size2_227_sram_blwl_out[247:247] ,mux_1level_tapbuf_size2_227_sram_blwl_out[247:247] ,mux_1level_tapbuf_size2_227_sram_blwl_outb[247:247] ,mux_1level_tapbuf_size2_227_configbus0[247:247], mux_1level_tapbuf_size2_227_configbus1[247:247] , mux_1level_tapbuf_size2_227_configbus0_b[247:247] ); -wire [0:1] mux_1level_tapbuf_size2_228_inbus; -assign mux_1level_tapbuf_size2_228_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_228_inbus[1] = chanx_1__0__in_44_ ; -wire [248:248] mux_1level_tapbuf_size2_228_configbus0; -wire [248:248] mux_1level_tapbuf_size2_228_configbus1; -wire [248:248] mux_1level_tapbuf_size2_228_sram_blwl_out ; -wire [248:248] mux_1level_tapbuf_size2_228_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_228_configbus0[248:248] = sram_blwl_bl[248:248] ; -assign mux_1level_tapbuf_size2_228_configbus1[248:248] = sram_blwl_wl[248:248] ; -wire [248:248] mux_1level_tapbuf_size2_228_configbus0_b; -assign mux_1level_tapbuf_size2_228_configbus0_b[248:248] = sram_blwl_blb[248:248] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_228_ (mux_1level_tapbuf_size2_228_inbus, chany_1__1__out_56_ , mux_1level_tapbuf_size2_228_sram_blwl_out[248:248] , -mux_1level_tapbuf_size2_228_sram_blwl_outb[248:248] ); -//----- SRAM bits for MUX[228], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_248_ (mux_1level_tapbuf_size2_228_sram_blwl_out[248:248] ,mux_1level_tapbuf_size2_228_sram_blwl_out[248:248] ,mux_1level_tapbuf_size2_228_sram_blwl_outb[248:248] ,mux_1level_tapbuf_size2_228_configbus0[248:248], mux_1level_tapbuf_size2_228_configbus1[248:248] , mux_1level_tapbuf_size2_228_configbus0_b[248:248] ); -wire [0:1] mux_1level_tapbuf_size2_229_inbus; -assign mux_1level_tapbuf_size2_229_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_229_inbus[1] = chanx_1__0__in_42_ ; -wire [249:249] mux_1level_tapbuf_size2_229_configbus0; -wire [249:249] mux_1level_tapbuf_size2_229_configbus1; -wire [249:249] mux_1level_tapbuf_size2_229_sram_blwl_out ; -wire [249:249] mux_1level_tapbuf_size2_229_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_229_configbus0[249:249] = sram_blwl_bl[249:249] ; -assign mux_1level_tapbuf_size2_229_configbus1[249:249] = sram_blwl_wl[249:249] ; -wire [249:249] mux_1level_tapbuf_size2_229_configbus0_b; -assign mux_1level_tapbuf_size2_229_configbus0_b[249:249] = sram_blwl_blb[249:249] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_229_ (mux_1level_tapbuf_size2_229_inbus, chany_1__1__out_58_ , mux_1level_tapbuf_size2_229_sram_blwl_out[249:249] , -mux_1level_tapbuf_size2_229_sram_blwl_outb[249:249] ); -//----- SRAM bits for MUX[229], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_249_ (mux_1level_tapbuf_size2_229_sram_blwl_out[249:249] ,mux_1level_tapbuf_size2_229_sram_blwl_out[249:249] ,mux_1level_tapbuf_size2_229_sram_blwl_outb[249:249] ,mux_1level_tapbuf_size2_229_configbus0[249:249], mux_1level_tapbuf_size2_229_configbus1[249:249] , mux_1level_tapbuf_size2_229_configbus0_b[249:249] ); -wire [0:1] mux_1level_tapbuf_size2_230_inbus; -assign mux_1level_tapbuf_size2_230_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_230_inbus[1] = chanx_1__0__in_40_ ; -wire [250:250] mux_1level_tapbuf_size2_230_configbus0; -wire [250:250] mux_1level_tapbuf_size2_230_configbus1; -wire [250:250] mux_1level_tapbuf_size2_230_sram_blwl_out ; -wire [250:250] mux_1level_tapbuf_size2_230_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_230_configbus0[250:250] = sram_blwl_bl[250:250] ; -assign mux_1level_tapbuf_size2_230_configbus1[250:250] = sram_blwl_wl[250:250] ; -wire [250:250] mux_1level_tapbuf_size2_230_configbus0_b; -assign mux_1level_tapbuf_size2_230_configbus0_b[250:250] = sram_blwl_blb[250:250] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_230_ (mux_1level_tapbuf_size2_230_inbus, chany_1__1__out_60_ , mux_1level_tapbuf_size2_230_sram_blwl_out[250:250] , -mux_1level_tapbuf_size2_230_sram_blwl_outb[250:250] ); -//----- SRAM bits for MUX[230], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_250_ (mux_1level_tapbuf_size2_230_sram_blwl_out[250:250] ,mux_1level_tapbuf_size2_230_sram_blwl_out[250:250] ,mux_1level_tapbuf_size2_230_sram_blwl_outb[250:250] ,mux_1level_tapbuf_size2_230_configbus0[250:250], mux_1level_tapbuf_size2_230_configbus1[250:250] , mux_1level_tapbuf_size2_230_configbus0_b[250:250] ); -wire [0:1] mux_1level_tapbuf_size2_231_inbus; -assign mux_1level_tapbuf_size2_231_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_231_inbus[1] = chanx_1__0__in_38_ ; -wire [251:251] mux_1level_tapbuf_size2_231_configbus0; -wire [251:251] mux_1level_tapbuf_size2_231_configbus1; -wire [251:251] mux_1level_tapbuf_size2_231_sram_blwl_out ; -wire [251:251] mux_1level_tapbuf_size2_231_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_231_configbus0[251:251] = sram_blwl_bl[251:251] ; -assign mux_1level_tapbuf_size2_231_configbus1[251:251] = sram_blwl_wl[251:251] ; -wire [251:251] mux_1level_tapbuf_size2_231_configbus0_b; -assign mux_1level_tapbuf_size2_231_configbus0_b[251:251] = sram_blwl_blb[251:251] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_231_ (mux_1level_tapbuf_size2_231_inbus, chany_1__1__out_62_ , mux_1level_tapbuf_size2_231_sram_blwl_out[251:251] , -mux_1level_tapbuf_size2_231_sram_blwl_outb[251:251] ); -//----- SRAM bits for MUX[231], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_251_ (mux_1level_tapbuf_size2_231_sram_blwl_out[251:251] ,mux_1level_tapbuf_size2_231_sram_blwl_out[251:251] ,mux_1level_tapbuf_size2_231_sram_blwl_outb[251:251] ,mux_1level_tapbuf_size2_231_configbus0[251:251], mux_1level_tapbuf_size2_231_configbus1[251:251] , mux_1level_tapbuf_size2_231_configbus0_b[251:251] ); -wire [0:1] mux_1level_tapbuf_size2_232_inbus; -assign mux_1level_tapbuf_size2_232_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_232_inbus[1] = chanx_1__0__in_36_ ; -wire [252:252] mux_1level_tapbuf_size2_232_configbus0; -wire [252:252] mux_1level_tapbuf_size2_232_configbus1; -wire [252:252] mux_1level_tapbuf_size2_232_sram_blwl_out ; -wire [252:252] mux_1level_tapbuf_size2_232_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_232_configbus0[252:252] = sram_blwl_bl[252:252] ; -assign mux_1level_tapbuf_size2_232_configbus1[252:252] = sram_blwl_wl[252:252] ; -wire [252:252] mux_1level_tapbuf_size2_232_configbus0_b; -assign mux_1level_tapbuf_size2_232_configbus0_b[252:252] = sram_blwl_blb[252:252] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_232_ (mux_1level_tapbuf_size2_232_inbus, chany_1__1__out_64_ , mux_1level_tapbuf_size2_232_sram_blwl_out[252:252] , -mux_1level_tapbuf_size2_232_sram_blwl_outb[252:252] ); -//----- SRAM bits for MUX[232], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_252_ (mux_1level_tapbuf_size2_232_sram_blwl_out[252:252] ,mux_1level_tapbuf_size2_232_sram_blwl_out[252:252] ,mux_1level_tapbuf_size2_232_sram_blwl_outb[252:252] ,mux_1level_tapbuf_size2_232_configbus0[252:252], mux_1level_tapbuf_size2_232_configbus1[252:252] , mux_1level_tapbuf_size2_232_configbus0_b[252:252] ); -wire [0:1] mux_1level_tapbuf_size2_233_inbus; -assign mux_1level_tapbuf_size2_233_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_233_inbus[1] = chanx_1__0__in_34_ ; -wire [253:253] mux_1level_tapbuf_size2_233_configbus0; -wire [253:253] mux_1level_tapbuf_size2_233_configbus1; -wire [253:253] mux_1level_tapbuf_size2_233_sram_blwl_out ; -wire [253:253] mux_1level_tapbuf_size2_233_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_233_configbus0[253:253] = sram_blwl_bl[253:253] ; -assign mux_1level_tapbuf_size2_233_configbus1[253:253] = sram_blwl_wl[253:253] ; -wire [253:253] mux_1level_tapbuf_size2_233_configbus0_b; -assign mux_1level_tapbuf_size2_233_configbus0_b[253:253] = sram_blwl_blb[253:253] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_233_ (mux_1level_tapbuf_size2_233_inbus, chany_1__1__out_66_ , mux_1level_tapbuf_size2_233_sram_blwl_out[253:253] , -mux_1level_tapbuf_size2_233_sram_blwl_outb[253:253] ); -//----- SRAM bits for MUX[233], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_253_ (mux_1level_tapbuf_size2_233_sram_blwl_out[253:253] ,mux_1level_tapbuf_size2_233_sram_blwl_out[253:253] ,mux_1level_tapbuf_size2_233_sram_blwl_outb[253:253] ,mux_1level_tapbuf_size2_233_configbus0[253:253], mux_1level_tapbuf_size2_233_configbus1[253:253] , mux_1level_tapbuf_size2_233_configbus0_b[253:253] ); -wire [0:1] mux_1level_tapbuf_size2_234_inbus; -assign mux_1level_tapbuf_size2_234_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_234_inbus[1] = chanx_1__0__in_32_ ; -wire [254:254] mux_1level_tapbuf_size2_234_configbus0; -wire [254:254] mux_1level_tapbuf_size2_234_configbus1; -wire [254:254] mux_1level_tapbuf_size2_234_sram_blwl_out ; -wire [254:254] mux_1level_tapbuf_size2_234_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_234_configbus0[254:254] = sram_blwl_bl[254:254] ; -assign mux_1level_tapbuf_size2_234_configbus1[254:254] = sram_blwl_wl[254:254] ; -wire [254:254] mux_1level_tapbuf_size2_234_configbus0_b; -assign mux_1level_tapbuf_size2_234_configbus0_b[254:254] = sram_blwl_blb[254:254] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_234_ (mux_1level_tapbuf_size2_234_inbus, chany_1__1__out_68_ , mux_1level_tapbuf_size2_234_sram_blwl_out[254:254] , -mux_1level_tapbuf_size2_234_sram_blwl_outb[254:254] ); -//----- SRAM bits for MUX[234], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_254_ (mux_1level_tapbuf_size2_234_sram_blwl_out[254:254] ,mux_1level_tapbuf_size2_234_sram_blwl_out[254:254] ,mux_1level_tapbuf_size2_234_sram_blwl_outb[254:254] ,mux_1level_tapbuf_size2_234_configbus0[254:254], mux_1level_tapbuf_size2_234_configbus1[254:254] , mux_1level_tapbuf_size2_234_configbus0_b[254:254] ); -wire [0:1] mux_1level_tapbuf_size2_235_inbus; -assign mux_1level_tapbuf_size2_235_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_235_inbus[1] = chanx_1__0__in_30_ ; -wire [255:255] mux_1level_tapbuf_size2_235_configbus0; -wire [255:255] mux_1level_tapbuf_size2_235_configbus1; -wire [255:255] mux_1level_tapbuf_size2_235_sram_blwl_out ; -wire [255:255] mux_1level_tapbuf_size2_235_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_235_configbus0[255:255] = sram_blwl_bl[255:255] ; -assign mux_1level_tapbuf_size2_235_configbus1[255:255] = sram_blwl_wl[255:255] ; -wire [255:255] mux_1level_tapbuf_size2_235_configbus0_b; -assign mux_1level_tapbuf_size2_235_configbus0_b[255:255] = sram_blwl_blb[255:255] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_235_ (mux_1level_tapbuf_size2_235_inbus, chany_1__1__out_70_ , mux_1level_tapbuf_size2_235_sram_blwl_out[255:255] , -mux_1level_tapbuf_size2_235_sram_blwl_outb[255:255] ); -//----- SRAM bits for MUX[235], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_255_ (mux_1level_tapbuf_size2_235_sram_blwl_out[255:255] ,mux_1level_tapbuf_size2_235_sram_blwl_out[255:255] ,mux_1level_tapbuf_size2_235_sram_blwl_outb[255:255] ,mux_1level_tapbuf_size2_235_configbus0[255:255], mux_1level_tapbuf_size2_235_configbus1[255:255] , mux_1level_tapbuf_size2_235_configbus0_b[255:255] ); -wire [0:1] mux_1level_tapbuf_size2_236_inbus; -assign mux_1level_tapbuf_size2_236_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_236_inbus[1] = chanx_1__0__in_28_ ; -wire [256:256] mux_1level_tapbuf_size2_236_configbus0; -wire [256:256] mux_1level_tapbuf_size2_236_configbus1; -wire [256:256] mux_1level_tapbuf_size2_236_sram_blwl_out ; -wire [256:256] mux_1level_tapbuf_size2_236_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_236_configbus0[256:256] = sram_blwl_bl[256:256] ; -assign mux_1level_tapbuf_size2_236_configbus1[256:256] = sram_blwl_wl[256:256] ; -wire [256:256] mux_1level_tapbuf_size2_236_configbus0_b; -assign mux_1level_tapbuf_size2_236_configbus0_b[256:256] = sram_blwl_blb[256:256] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_236_ (mux_1level_tapbuf_size2_236_inbus, chany_1__1__out_72_ , mux_1level_tapbuf_size2_236_sram_blwl_out[256:256] , -mux_1level_tapbuf_size2_236_sram_blwl_outb[256:256] ); -//----- SRAM bits for MUX[236], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_256_ (mux_1level_tapbuf_size2_236_sram_blwl_out[256:256] ,mux_1level_tapbuf_size2_236_sram_blwl_out[256:256] ,mux_1level_tapbuf_size2_236_sram_blwl_outb[256:256] ,mux_1level_tapbuf_size2_236_configbus0[256:256], mux_1level_tapbuf_size2_236_configbus1[256:256] , mux_1level_tapbuf_size2_236_configbus0_b[256:256] ); -wire [0:1] mux_1level_tapbuf_size2_237_inbus; -assign mux_1level_tapbuf_size2_237_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_237_inbus[1] = chanx_1__0__in_26_ ; -wire [257:257] mux_1level_tapbuf_size2_237_configbus0; -wire [257:257] mux_1level_tapbuf_size2_237_configbus1; -wire [257:257] mux_1level_tapbuf_size2_237_sram_blwl_out ; -wire [257:257] mux_1level_tapbuf_size2_237_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_237_configbus0[257:257] = sram_blwl_bl[257:257] ; -assign mux_1level_tapbuf_size2_237_configbus1[257:257] = sram_blwl_wl[257:257] ; -wire [257:257] mux_1level_tapbuf_size2_237_configbus0_b; -assign mux_1level_tapbuf_size2_237_configbus0_b[257:257] = sram_blwl_blb[257:257] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_237_ (mux_1level_tapbuf_size2_237_inbus, chany_1__1__out_74_ , mux_1level_tapbuf_size2_237_sram_blwl_out[257:257] , -mux_1level_tapbuf_size2_237_sram_blwl_outb[257:257] ); -//----- SRAM bits for MUX[237], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_257_ (mux_1level_tapbuf_size2_237_sram_blwl_out[257:257] ,mux_1level_tapbuf_size2_237_sram_blwl_out[257:257] ,mux_1level_tapbuf_size2_237_sram_blwl_outb[257:257] ,mux_1level_tapbuf_size2_237_configbus0[257:257], mux_1level_tapbuf_size2_237_configbus1[257:257] , mux_1level_tapbuf_size2_237_configbus0_b[257:257] ); -wire [0:1] mux_1level_tapbuf_size2_238_inbus; -assign mux_1level_tapbuf_size2_238_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_238_inbus[1] = chanx_1__0__in_24_ ; -wire [258:258] mux_1level_tapbuf_size2_238_configbus0; -wire [258:258] mux_1level_tapbuf_size2_238_configbus1; -wire [258:258] mux_1level_tapbuf_size2_238_sram_blwl_out ; -wire [258:258] mux_1level_tapbuf_size2_238_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_238_configbus0[258:258] = sram_blwl_bl[258:258] ; -assign mux_1level_tapbuf_size2_238_configbus1[258:258] = sram_blwl_wl[258:258] ; -wire [258:258] mux_1level_tapbuf_size2_238_configbus0_b; -assign mux_1level_tapbuf_size2_238_configbus0_b[258:258] = sram_blwl_blb[258:258] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_238_ (mux_1level_tapbuf_size2_238_inbus, chany_1__1__out_76_ , mux_1level_tapbuf_size2_238_sram_blwl_out[258:258] , -mux_1level_tapbuf_size2_238_sram_blwl_outb[258:258] ); -//----- SRAM bits for MUX[238], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_258_ (mux_1level_tapbuf_size2_238_sram_blwl_out[258:258] ,mux_1level_tapbuf_size2_238_sram_blwl_out[258:258] ,mux_1level_tapbuf_size2_238_sram_blwl_outb[258:258] ,mux_1level_tapbuf_size2_238_configbus0[258:258], mux_1level_tapbuf_size2_238_configbus1[258:258] , mux_1level_tapbuf_size2_238_configbus0_b[258:258] ); -wire [0:1] mux_1level_tapbuf_size2_239_inbus; -assign mux_1level_tapbuf_size2_239_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_239_inbus[1] = chanx_1__0__in_22_ ; -wire [259:259] mux_1level_tapbuf_size2_239_configbus0; -wire [259:259] mux_1level_tapbuf_size2_239_configbus1; -wire [259:259] mux_1level_tapbuf_size2_239_sram_blwl_out ; -wire [259:259] mux_1level_tapbuf_size2_239_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_239_configbus0[259:259] = sram_blwl_bl[259:259] ; -assign mux_1level_tapbuf_size2_239_configbus1[259:259] = sram_blwl_wl[259:259] ; -wire [259:259] mux_1level_tapbuf_size2_239_configbus0_b; -assign mux_1level_tapbuf_size2_239_configbus0_b[259:259] = sram_blwl_blb[259:259] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_239_ (mux_1level_tapbuf_size2_239_inbus, chany_1__1__out_78_ , mux_1level_tapbuf_size2_239_sram_blwl_out[259:259] , -mux_1level_tapbuf_size2_239_sram_blwl_outb[259:259] ); -//----- SRAM bits for MUX[239], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_259_ (mux_1level_tapbuf_size2_239_sram_blwl_out[259:259] ,mux_1level_tapbuf_size2_239_sram_blwl_out[259:259] ,mux_1level_tapbuf_size2_239_sram_blwl_outb[259:259] ,mux_1level_tapbuf_size2_239_configbus0[259:259], mux_1level_tapbuf_size2_239_configbus1[259:259] , mux_1level_tapbuf_size2_239_configbus0_b[259:259] ); -wire [0:1] mux_1level_tapbuf_size2_240_inbus; -assign mux_1level_tapbuf_size2_240_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_240_inbus[1] = chanx_1__0__in_20_ ; -wire [260:260] mux_1level_tapbuf_size2_240_configbus0; -wire [260:260] mux_1level_tapbuf_size2_240_configbus1; -wire [260:260] mux_1level_tapbuf_size2_240_sram_blwl_out ; -wire [260:260] mux_1level_tapbuf_size2_240_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_240_configbus0[260:260] = sram_blwl_bl[260:260] ; -assign mux_1level_tapbuf_size2_240_configbus1[260:260] = sram_blwl_wl[260:260] ; -wire [260:260] mux_1level_tapbuf_size2_240_configbus0_b; -assign mux_1level_tapbuf_size2_240_configbus0_b[260:260] = sram_blwl_blb[260:260] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_240_ (mux_1level_tapbuf_size2_240_inbus, chany_1__1__out_80_ , mux_1level_tapbuf_size2_240_sram_blwl_out[260:260] , -mux_1level_tapbuf_size2_240_sram_blwl_outb[260:260] ); -//----- SRAM bits for MUX[240], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_260_ (mux_1level_tapbuf_size2_240_sram_blwl_out[260:260] ,mux_1level_tapbuf_size2_240_sram_blwl_out[260:260] ,mux_1level_tapbuf_size2_240_sram_blwl_outb[260:260] ,mux_1level_tapbuf_size2_240_configbus0[260:260], mux_1level_tapbuf_size2_240_configbus1[260:260] , mux_1level_tapbuf_size2_240_configbus0_b[260:260] ); -wire [0:1] mux_1level_tapbuf_size2_241_inbus; -assign mux_1level_tapbuf_size2_241_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_241_inbus[1] = chanx_1__0__in_18_ ; -wire [261:261] mux_1level_tapbuf_size2_241_configbus0; -wire [261:261] mux_1level_tapbuf_size2_241_configbus1; -wire [261:261] mux_1level_tapbuf_size2_241_sram_blwl_out ; -wire [261:261] mux_1level_tapbuf_size2_241_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_241_configbus0[261:261] = sram_blwl_bl[261:261] ; -assign mux_1level_tapbuf_size2_241_configbus1[261:261] = sram_blwl_wl[261:261] ; -wire [261:261] mux_1level_tapbuf_size2_241_configbus0_b; -assign mux_1level_tapbuf_size2_241_configbus0_b[261:261] = sram_blwl_blb[261:261] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_241_ (mux_1level_tapbuf_size2_241_inbus, chany_1__1__out_82_ , mux_1level_tapbuf_size2_241_sram_blwl_out[261:261] , -mux_1level_tapbuf_size2_241_sram_blwl_outb[261:261] ); -//----- SRAM bits for MUX[241], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_261_ (mux_1level_tapbuf_size2_241_sram_blwl_out[261:261] ,mux_1level_tapbuf_size2_241_sram_blwl_out[261:261] ,mux_1level_tapbuf_size2_241_sram_blwl_outb[261:261] ,mux_1level_tapbuf_size2_241_configbus0[261:261], mux_1level_tapbuf_size2_241_configbus1[261:261] , mux_1level_tapbuf_size2_241_configbus0_b[261:261] ); -wire [0:1] mux_1level_tapbuf_size2_242_inbus; -assign mux_1level_tapbuf_size2_242_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_242_inbus[1] = chanx_1__0__in_16_ ; -wire [262:262] mux_1level_tapbuf_size2_242_configbus0; -wire [262:262] mux_1level_tapbuf_size2_242_configbus1; -wire [262:262] mux_1level_tapbuf_size2_242_sram_blwl_out ; -wire [262:262] mux_1level_tapbuf_size2_242_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_242_configbus0[262:262] = sram_blwl_bl[262:262] ; -assign mux_1level_tapbuf_size2_242_configbus1[262:262] = sram_blwl_wl[262:262] ; -wire [262:262] mux_1level_tapbuf_size2_242_configbus0_b; -assign mux_1level_tapbuf_size2_242_configbus0_b[262:262] = sram_blwl_blb[262:262] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_242_ (mux_1level_tapbuf_size2_242_inbus, chany_1__1__out_84_ , mux_1level_tapbuf_size2_242_sram_blwl_out[262:262] , -mux_1level_tapbuf_size2_242_sram_blwl_outb[262:262] ); -//----- SRAM bits for MUX[242], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_262_ (mux_1level_tapbuf_size2_242_sram_blwl_out[262:262] ,mux_1level_tapbuf_size2_242_sram_blwl_out[262:262] ,mux_1level_tapbuf_size2_242_sram_blwl_outb[262:262] ,mux_1level_tapbuf_size2_242_configbus0[262:262], mux_1level_tapbuf_size2_242_configbus1[262:262] , mux_1level_tapbuf_size2_242_configbus0_b[262:262] ); -wire [0:1] mux_1level_tapbuf_size2_243_inbus; -assign mux_1level_tapbuf_size2_243_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_243_inbus[1] = chanx_1__0__in_14_ ; -wire [263:263] mux_1level_tapbuf_size2_243_configbus0; -wire [263:263] mux_1level_tapbuf_size2_243_configbus1; -wire [263:263] mux_1level_tapbuf_size2_243_sram_blwl_out ; -wire [263:263] mux_1level_tapbuf_size2_243_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_243_configbus0[263:263] = sram_blwl_bl[263:263] ; -assign mux_1level_tapbuf_size2_243_configbus1[263:263] = sram_blwl_wl[263:263] ; -wire [263:263] mux_1level_tapbuf_size2_243_configbus0_b; -assign mux_1level_tapbuf_size2_243_configbus0_b[263:263] = sram_blwl_blb[263:263] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_243_ (mux_1level_tapbuf_size2_243_inbus, chany_1__1__out_86_ , mux_1level_tapbuf_size2_243_sram_blwl_out[263:263] , -mux_1level_tapbuf_size2_243_sram_blwl_outb[263:263] ); -//----- SRAM bits for MUX[243], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_263_ (mux_1level_tapbuf_size2_243_sram_blwl_out[263:263] ,mux_1level_tapbuf_size2_243_sram_blwl_out[263:263] ,mux_1level_tapbuf_size2_243_sram_blwl_outb[263:263] ,mux_1level_tapbuf_size2_243_configbus0[263:263], mux_1level_tapbuf_size2_243_configbus1[263:263] , mux_1level_tapbuf_size2_243_configbus0_b[263:263] ); -wire [0:1] mux_1level_tapbuf_size2_244_inbus; -assign mux_1level_tapbuf_size2_244_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_244_inbus[1] = chanx_1__0__in_12_ ; -wire [264:264] mux_1level_tapbuf_size2_244_configbus0; -wire [264:264] mux_1level_tapbuf_size2_244_configbus1; -wire [264:264] mux_1level_tapbuf_size2_244_sram_blwl_out ; -wire [264:264] mux_1level_tapbuf_size2_244_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_244_configbus0[264:264] = sram_blwl_bl[264:264] ; -assign mux_1level_tapbuf_size2_244_configbus1[264:264] = sram_blwl_wl[264:264] ; -wire [264:264] mux_1level_tapbuf_size2_244_configbus0_b; -assign mux_1level_tapbuf_size2_244_configbus0_b[264:264] = sram_blwl_blb[264:264] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_244_ (mux_1level_tapbuf_size2_244_inbus, chany_1__1__out_88_ , mux_1level_tapbuf_size2_244_sram_blwl_out[264:264] , -mux_1level_tapbuf_size2_244_sram_blwl_outb[264:264] ); -//----- SRAM bits for MUX[244], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_264_ (mux_1level_tapbuf_size2_244_sram_blwl_out[264:264] ,mux_1level_tapbuf_size2_244_sram_blwl_out[264:264] ,mux_1level_tapbuf_size2_244_sram_blwl_outb[264:264] ,mux_1level_tapbuf_size2_244_configbus0[264:264], mux_1level_tapbuf_size2_244_configbus1[264:264] , mux_1level_tapbuf_size2_244_configbus0_b[264:264] ); -wire [0:1] mux_1level_tapbuf_size2_245_inbus; -assign mux_1level_tapbuf_size2_245_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_245_inbus[1] = chanx_1__0__in_10_ ; -wire [265:265] mux_1level_tapbuf_size2_245_configbus0; -wire [265:265] mux_1level_tapbuf_size2_245_configbus1; -wire [265:265] mux_1level_tapbuf_size2_245_sram_blwl_out ; -wire [265:265] mux_1level_tapbuf_size2_245_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_245_configbus0[265:265] = sram_blwl_bl[265:265] ; -assign mux_1level_tapbuf_size2_245_configbus1[265:265] = sram_blwl_wl[265:265] ; -wire [265:265] mux_1level_tapbuf_size2_245_configbus0_b; -assign mux_1level_tapbuf_size2_245_configbus0_b[265:265] = sram_blwl_blb[265:265] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_245_ (mux_1level_tapbuf_size2_245_inbus, chany_1__1__out_90_ , mux_1level_tapbuf_size2_245_sram_blwl_out[265:265] , -mux_1level_tapbuf_size2_245_sram_blwl_outb[265:265] ); -//----- SRAM bits for MUX[245], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_265_ (mux_1level_tapbuf_size2_245_sram_blwl_out[265:265] ,mux_1level_tapbuf_size2_245_sram_blwl_out[265:265] ,mux_1level_tapbuf_size2_245_sram_blwl_outb[265:265] ,mux_1level_tapbuf_size2_245_configbus0[265:265], mux_1level_tapbuf_size2_245_configbus1[265:265] , mux_1level_tapbuf_size2_245_configbus0_b[265:265] ); -wire [0:1] mux_1level_tapbuf_size2_246_inbus; -assign mux_1level_tapbuf_size2_246_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_246_inbus[1] = chanx_1__0__in_8_ ; -wire [266:266] mux_1level_tapbuf_size2_246_configbus0; -wire [266:266] mux_1level_tapbuf_size2_246_configbus1; -wire [266:266] mux_1level_tapbuf_size2_246_sram_blwl_out ; -wire [266:266] mux_1level_tapbuf_size2_246_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_246_configbus0[266:266] = sram_blwl_bl[266:266] ; -assign mux_1level_tapbuf_size2_246_configbus1[266:266] = sram_blwl_wl[266:266] ; -wire [266:266] mux_1level_tapbuf_size2_246_configbus0_b; -assign mux_1level_tapbuf_size2_246_configbus0_b[266:266] = sram_blwl_blb[266:266] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_246_ (mux_1level_tapbuf_size2_246_inbus, chany_1__1__out_92_ , mux_1level_tapbuf_size2_246_sram_blwl_out[266:266] , -mux_1level_tapbuf_size2_246_sram_blwl_outb[266:266] ); -//----- SRAM bits for MUX[246], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_266_ (mux_1level_tapbuf_size2_246_sram_blwl_out[266:266] ,mux_1level_tapbuf_size2_246_sram_blwl_out[266:266] ,mux_1level_tapbuf_size2_246_sram_blwl_outb[266:266] ,mux_1level_tapbuf_size2_246_configbus0[266:266], mux_1level_tapbuf_size2_246_configbus1[266:266] , mux_1level_tapbuf_size2_246_configbus0_b[266:266] ); -wire [0:1] mux_1level_tapbuf_size2_247_inbus; -assign mux_1level_tapbuf_size2_247_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_247_inbus[1] = chanx_1__0__in_6_ ; -wire [267:267] mux_1level_tapbuf_size2_247_configbus0; -wire [267:267] mux_1level_tapbuf_size2_247_configbus1; -wire [267:267] mux_1level_tapbuf_size2_247_sram_blwl_out ; -wire [267:267] mux_1level_tapbuf_size2_247_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_247_configbus0[267:267] = sram_blwl_bl[267:267] ; -assign mux_1level_tapbuf_size2_247_configbus1[267:267] = sram_blwl_wl[267:267] ; -wire [267:267] mux_1level_tapbuf_size2_247_configbus0_b; -assign mux_1level_tapbuf_size2_247_configbus0_b[267:267] = sram_blwl_blb[267:267] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_247_ (mux_1level_tapbuf_size2_247_inbus, chany_1__1__out_94_ , mux_1level_tapbuf_size2_247_sram_blwl_out[267:267] , -mux_1level_tapbuf_size2_247_sram_blwl_outb[267:267] ); -//----- SRAM bits for MUX[247], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_267_ (mux_1level_tapbuf_size2_247_sram_blwl_out[267:267] ,mux_1level_tapbuf_size2_247_sram_blwl_out[267:267] ,mux_1level_tapbuf_size2_247_sram_blwl_outb[267:267] ,mux_1level_tapbuf_size2_247_configbus0[267:267], mux_1level_tapbuf_size2_247_configbus1[267:267] , mux_1level_tapbuf_size2_247_configbus0_b[267:267] ); -wire [0:1] mux_1level_tapbuf_size2_248_inbus; -assign mux_1level_tapbuf_size2_248_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_248_inbus[1] = chanx_1__0__in_4_ ; -wire [268:268] mux_1level_tapbuf_size2_248_configbus0; -wire [268:268] mux_1level_tapbuf_size2_248_configbus1; -wire [268:268] mux_1level_tapbuf_size2_248_sram_blwl_out ; -wire [268:268] mux_1level_tapbuf_size2_248_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_248_configbus0[268:268] = sram_blwl_bl[268:268] ; -assign mux_1level_tapbuf_size2_248_configbus1[268:268] = sram_blwl_wl[268:268] ; -wire [268:268] mux_1level_tapbuf_size2_248_configbus0_b; -assign mux_1level_tapbuf_size2_248_configbus0_b[268:268] = sram_blwl_blb[268:268] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_248_ (mux_1level_tapbuf_size2_248_inbus, chany_1__1__out_96_ , mux_1level_tapbuf_size2_248_sram_blwl_out[268:268] , -mux_1level_tapbuf_size2_248_sram_blwl_outb[268:268] ); -//----- SRAM bits for MUX[248], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_268_ (mux_1level_tapbuf_size2_248_sram_blwl_out[268:268] ,mux_1level_tapbuf_size2_248_sram_blwl_out[268:268] ,mux_1level_tapbuf_size2_248_sram_blwl_outb[268:268] ,mux_1level_tapbuf_size2_248_configbus0[268:268], mux_1level_tapbuf_size2_248_configbus1[268:268] , mux_1level_tapbuf_size2_248_configbus0_b[268:268] ); -wire [0:1] mux_1level_tapbuf_size2_249_inbus; -assign mux_1level_tapbuf_size2_249_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_249_inbus[1] = chanx_1__0__in_2_ ; -wire [269:269] mux_1level_tapbuf_size2_249_configbus0; -wire [269:269] mux_1level_tapbuf_size2_249_configbus1; -wire [269:269] mux_1level_tapbuf_size2_249_sram_blwl_out ; -wire [269:269] mux_1level_tapbuf_size2_249_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_249_configbus0[269:269] = sram_blwl_bl[269:269] ; -assign mux_1level_tapbuf_size2_249_configbus1[269:269] = sram_blwl_wl[269:269] ; -wire [269:269] mux_1level_tapbuf_size2_249_configbus0_b; -assign mux_1level_tapbuf_size2_249_configbus0_b[269:269] = sram_blwl_blb[269:269] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_249_ (mux_1level_tapbuf_size2_249_inbus, chany_1__1__out_98_ , mux_1level_tapbuf_size2_249_sram_blwl_out[269:269] , -mux_1level_tapbuf_size2_249_sram_blwl_outb[269:269] ); -//----- SRAM bits for MUX[249], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_269_ (mux_1level_tapbuf_size2_249_sram_blwl_out[269:269] ,mux_1level_tapbuf_size2_249_sram_blwl_out[269:269] ,mux_1level_tapbuf_size2_249_sram_blwl_outb[269:269] ,mux_1level_tapbuf_size2_249_configbus0[269:269], mux_1level_tapbuf_size2_249_configbus1[269:269] , mux_1level_tapbuf_size2_249_configbus0_b[269:269] ); -//----- right side Multiplexers ----- -//----- bottom side Multiplexers ----- -//----- left side Multiplexers ----- -wire [0:1] mux_1level_tapbuf_size2_250_inbus; -assign mux_1level_tapbuf_size2_250_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_250_inbus[1] = chany_1__1__in_1_ ; -wire [270:270] mux_1level_tapbuf_size2_250_configbus0; -wire [270:270] mux_1level_tapbuf_size2_250_configbus1; -wire [270:270] mux_1level_tapbuf_size2_250_sram_blwl_out ; -wire [270:270] mux_1level_tapbuf_size2_250_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_250_configbus0[270:270] = sram_blwl_bl[270:270] ; -assign mux_1level_tapbuf_size2_250_configbus1[270:270] = sram_blwl_wl[270:270] ; -wire [270:270] mux_1level_tapbuf_size2_250_configbus0_b; -assign mux_1level_tapbuf_size2_250_configbus0_b[270:270] = sram_blwl_blb[270:270] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_250_ (mux_1level_tapbuf_size2_250_inbus, chanx_1__0__out_1_ , mux_1level_tapbuf_size2_250_sram_blwl_out[270:270] , -mux_1level_tapbuf_size2_250_sram_blwl_outb[270:270] ); -//----- SRAM bits for MUX[250], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_270_ (mux_1level_tapbuf_size2_250_sram_blwl_out[270:270] ,mux_1level_tapbuf_size2_250_sram_blwl_out[270:270] ,mux_1level_tapbuf_size2_250_sram_blwl_outb[270:270] ,mux_1level_tapbuf_size2_250_configbus0[270:270], mux_1level_tapbuf_size2_250_configbus1[270:270] , mux_1level_tapbuf_size2_250_configbus0_b[270:270] ); -wire [0:1] mux_1level_tapbuf_size2_251_inbus; -assign mux_1level_tapbuf_size2_251_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_251_inbus[1] = chany_1__1__in_99_ ; -wire [271:271] mux_1level_tapbuf_size2_251_configbus0; -wire [271:271] mux_1level_tapbuf_size2_251_configbus1; -wire [271:271] mux_1level_tapbuf_size2_251_sram_blwl_out ; -wire [271:271] mux_1level_tapbuf_size2_251_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_251_configbus0[271:271] = sram_blwl_bl[271:271] ; -assign mux_1level_tapbuf_size2_251_configbus1[271:271] = sram_blwl_wl[271:271] ; -wire [271:271] mux_1level_tapbuf_size2_251_configbus0_b; -assign mux_1level_tapbuf_size2_251_configbus0_b[271:271] = sram_blwl_blb[271:271] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_251_ (mux_1level_tapbuf_size2_251_inbus, chanx_1__0__out_3_ , mux_1level_tapbuf_size2_251_sram_blwl_out[271:271] , -mux_1level_tapbuf_size2_251_sram_blwl_outb[271:271] ); -//----- SRAM bits for MUX[251], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_271_ (mux_1level_tapbuf_size2_251_sram_blwl_out[271:271] ,mux_1level_tapbuf_size2_251_sram_blwl_out[271:271] ,mux_1level_tapbuf_size2_251_sram_blwl_outb[271:271] ,mux_1level_tapbuf_size2_251_configbus0[271:271], mux_1level_tapbuf_size2_251_configbus1[271:271] , mux_1level_tapbuf_size2_251_configbus0_b[271:271] ); -wire [0:1] mux_1level_tapbuf_size2_252_inbus; -assign mux_1level_tapbuf_size2_252_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_252_inbus[1] = chany_1__1__in_97_ ; -wire [272:272] mux_1level_tapbuf_size2_252_configbus0; -wire [272:272] mux_1level_tapbuf_size2_252_configbus1; -wire [272:272] mux_1level_tapbuf_size2_252_sram_blwl_out ; -wire [272:272] mux_1level_tapbuf_size2_252_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_252_configbus0[272:272] = sram_blwl_bl[272:272] ; -assign mux_1level_tapbuf_size2_252_configbus1[272:272] = sram_blwl_wl[272:272] ; -wire [272:272] mux_1level_tapbuf_size2_252_configbus0_b; -assign mux_1level_tapbuf_size2_252_configbus0_b[272:272] = sram_blwl_blb[272:272] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_252_ (mux_1level_tapbuf_size2_252_inbus, chanx_1__0__out_5_ , mux_1level_tapbuf_size2_252_sram_blwl_out[272:272] , -mux_1level_tapbuf_size2_252_sram_blwl_outb[272:272] ); -//----- SRAM bits for MUX[252], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_272_ (mux_1level_tapbuf_size2_252_sram_blwl_out[272:272] ,mux_1level_tapbuf_size2_252_sram_blwl_out[272:272] ,mux_1level_tapbuf_size2_252_sram_blwl_outb[272:272] ,mux_1level_tapbuf_size2_252_configbus0[272:272], mux_1level_tapbuf_size2_252_configbus1[272:272] , mux_1level_tapbuf_size2_252_configbus0_b[272:272] ); -wire [0:1] mux_1level_tapbuf_size2_253_inbus; -assign mux_1level_tapbuf_size2_253_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_253_inbus[1] = chany_1__1__in_95_ ; -wire [273:273] mux_1level_tapbuf_size2_253_configbus0; -wire [273:273] mux_1level_tapbuf_size2_253_configbus1; -wire [273:273] mux_1level_tapbuf_size2_253_sram_blwl_out ; -wire [273:273] mux_1level_tapbuf_size2_253_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_253_configbus0[273:273] = sram_blwl_bl[273:273] ; -assign mux_1level_tapbuf_size2_253_configbus1[273:273] = sram_blwl_wl[273:273] ; -wire [273:273] mux_1level_tapbuf_size2_253_configbus0_b; -assign mux_1level_tapbuf_size2_253_configbus0_b[273:273] = sram_blwl_blb[273:273] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_253_ (mux_1level_tapbuf_size2_253_inbus, chanx_1__0__out_7_ , mux_1level_tapbuf_size2_253_sram_blwl_out[273:273] , -mux_1level_tapbuf_size2_253_sram_blwl_outb[273:273] ); -//----- SRAM bits for MUX[253], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_273_ (mux_1level_tapbuf_size2_253_sram_blwl_out[273:273] ,mux_1level_tapbuf_size2_253_sram_blwl_out[273:273] ,mux_1level_tapbuf_size2_253_sram_blwl_outb[273:273] ,mux_1level_tapbuf_size2_253_configbus0[273:273], mux_1level_tapbuf_size2_253_configbus1[273:273] , mux_1level_tapbuf_size2_253_configbus0_b[273:273] ); -wire [0:1] mux_1level_tapbuf_size2_254_inbus; -assign mux_1level_tapbuf_size2_254_inbus[0] = grid_1__0__pin_0__0__1_; -assign mux_1level_tapbuf_size2_254_inbus[1] = chany_1__1__in_93_ ; -wire [274:274] mux_1level_tapbuf_size2_254_configbus0; -wire [274:274] mux_1level_tapbuf_size2_254_configbus1; -wire [274:274] mux_1level_tapbuf_size2_254_sram_blwl_out ; -wire [274:274] mux_1level_tapbuf_size2_254_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_254_configbus0[274:274] = sram_blwl_bl[274:274] ; -assign mux_1level_tapbuf_size2_254_configbus1[274:274] = sram_blwl_wl[274:274] ; -wire [274:274] mux_1level_tapbuf_size2_254_configbus0_b; -assign mux_1level_tapbuf_size2_254_configbus0_b[274:274] = sram_blwl_blb[274:274] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_254_ (mux_1level_tapbuf_size2_254_inbus, chanx_1__0__out_9_ , mux_1level_tapbuf_size2_254_sram_blwl_out[274:274] , -mux_1level_tapbuf_size2_254_sram_blwl_outb[274:274] ); -//----- SRAM bits for MUX[254], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_274_ (mux_1level_tapbuf_size2_254_sram_blwl_out[274:274] ,mux_1level_tapbuf_size2_254_sram_blwl_out[274:274] ,mux_1level_tapbuf_size2_254_sram_blwl_outb[274:274] ,mux_1level_tapbuf_size2_254_configbus0[274:274], mux_1level_tapbuf_size2_254_configbus1[274:274] , mux_1level_tapbuf_size2_254_configbus0_b[274:274] ); -wire [0:1] mux_1level_tapbuf_size2_255_inbus; -assign mux_1level_tapbuf_size2_255_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_255_inbus[1] = chany_1__1__in_91_ ; -wire [275:275] mux_1level_tapbuf_size2_255_configbus0; -wire [275:275] mux_1level_tapbuf_size2_255_configbus1; -wire [275:275] mux_1level_tapbuf_size2_255_sram_blwl_out ; -wire [275:275] mux_1level_tapbuf_size2_255_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_255_configbus0[275:275] = sram_blwl_bl[275:275] ; -assign mux_1level_tapbuf_size2_255_configbus1[275:275] = sram_blwl_wl[275:275] ; -wire [275:275] mux_1level_tapbuf_size2_255_configbus0_b; -assign mux_1level_tapbuf_size2_255_configbus0_b[275:275] = sram_blwl_blb[275:275] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_255_ (mux_1level_tapbuf_size2_255_inbus, chanx_1__0__out_11_ , mux_1level_tapbuf_size2_255_sram_blwl_out[275:275] , -mux_1level_tapbuf_size2_255_sram_blwl_outb[275:275] ); -//----- SRAM bits for MUX[255], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_275_ (mux_1level_tapbuf_size2_255_sram_blwl_out[275:275] ,mux_1level_tapbuf_size2_255_sram_blwl_out[275:275] ,mux_1level_tapbuf_size2_255_sram_blwl_outb[275:275] ,mux_1level_tapbuf_size2_255_configbus0[275:275], mux_1level_tapbuf_size2_255_configbus1[275:275] , mux_1level_tapbuf_size2_255_configbus0_b[275:275] ); -wire [0:1] mux_1level_tapbuf_size2_256_inbus; -assign mux_1level_tapbuf_size2_256_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_256_inbus[1] = chany_1__1__in_89_ ; -wire [276:276] mux_1level_tapbuf_size2_256_configbus0; -wire [276:276] mux_1level_tapbuf_size2_256_configbus1; -wire [276:276] mux_1level_tapbuf_size2_256_sram_blwl_out ; -wire [276:276] mux_1level_tapbuf_size2_256_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_256_configbus0[276:276] = sram_blwl_bl[276:276] ; -assign mux_1level_tapbuf_size2_256_configbus1[276:276] = sram_blwl_wl[276:276] ; -wire [276:276] mux_1level_tapbuf_size2_256_configbus0_b; -assign mux_1level_tapbuf_size2_256_configbus0_b[276:276] = sram_blwl_blb[276:276] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_256_ (mux_1level_tapbuf_size2_256_inbus, chanx_1__0__out_13_ , mux_1level_tapbuf_size2_256_sram_blwl_out[276:276] , -mux_1level_tapbuf_size2_256_sram_blwl_outb[276:276] ); -//----- SRAM bits for MUX[256], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_276_ (mux_1level_tapbuf_size2_256_sram_blwl_out[276:276] ,mux_1level_tapbuf_size2_256_sram_blwl_out[276:276] ,mux_1level_tapbuf_size2_256_sram_blwl_outb[276:276] ,mux_1level_tapbuf_size2_256_configbus0[276:276], mux_1level_tapbuf_size2_256_configbus1[276:276] , mux_1level_tapbuf_size2_256_configbus0_b[276:276] ); -wire [0:1] mux_1level_tapbuf_size2_257_inbus; -assign mux_1level_tapbuf_size2_257_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_257_inbus[1] = chany_1__1__in_87_ ; -wire [277:277] mux_1level_tapbuf_size2_257_configbus0; -wire [277:277] mux_1level_tapbuf_size2_257_configbus1; -wire [277:277] mux_1level_tapbuf_size2_257_sram_blwl_out ; -wire [277:277] mux_1level_tapbuf_size2_257_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_257_configbus0[277:277] = sram_blwl_bl[277:277] ; -assign mux_1level_tapbuf_size2_257_configbus1[277:277] = sram_blwl_wl[277:277] ; -wire [277:277] mux_1level_tapbuf_size2_257_configbus0_b; -assign mux_1level_tapbuf_size2_257_configbus0_b[277:277] = sram_blwl_blb[277:277] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_257_ (mux_1level_tapbuf_size2_257_inbus, chanx_1__0__out_15_ , mux_1level_tapbuf_size2_257_sram_blwl_out[277:277] , -mux_1level_tapbuf_size2_257_sram_blwl_outb[277:277] ); -//----- SRAM bits for MUX[257], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_277_ (mux_1level_tapbuf_size2_257_sram_blwl_out[277:277] ,mux_1level_tapbuf_size2_257_sram_blwl_out[277:277] ,mux_1level_tapbuf_size2_257_sram_blwl_outb[277:277] ,mux_1level_tapbuf_size2_257_configbus0[277:277], mux_1level_tapbuf_size2_257_configbus1[277:277] , mux_1level_tapbuf_size2_257_configbus0_b[277:277] ); -wire [0:1] mux_1level_tapbuf_size2_258_inbus; -assign mux_1level_tapbuf_size2_258_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_258_inbus[1] = chany_1__1__in_85_ ; -wire [278:278] mux_1level_tapbuf_size2_258_configbus0; -wire [278:278] mux_1level_tapbuf_size2_258_configbus1; -wire [278:278] mux_1level_tapbuf_size2_258_sram_blwl_out ; -wire [278:278] mux_1level_tapbuf_size2_258_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_258_configbus0[278:278] = sram_blwl_bl[278:278] ; -assign mux_1level_tapbuf_size2_258_configbus1[278:278] = sram_blwl_wl[278:278] ; -wire [278:278] mux_1level_tapbuf_size2_258_configbus0_b; -assign mux_1level_tapbuf_size2_258_configbus0_b[278:278] = sram_blwl_blb[278:278] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_258_ (mux_1level_tapbuf_size2_258_inbus, chanx_1__0__out_17_ , mux_1level_tapbuf_size2_258_sram_blwl_out[278:278] , -mux_1level_tapbuf_size2_258_sram_blwl_outb[278:278] ); -//----- SRAM bits for MUX[258], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_278_ (mux_1level_tapbuf_size2_258_sram_blwl_out[278:278] ,mux_1level_tapbuf_size2_258_sram_blwl_out[278:278] ,mux_1level_tapbuf_size2_258_sram_blwl_outb[278:278] ,mux_1level_tapbuf_size2_258_configbus0[278:278], mux_1level_tapbuf_size2_258_configbus1[278:278] , mux_1level_tapbuf_size2_258_configbus0_b[278:278] ); -wire [0:1] mux_1level_tapbuf_size2_259_inbus; -assign mux_1level_tapbuf_size2_259_inbus[0] = grid_1__0__pin_0__0__3_; -assign mux_1level_tapbuf_size2_259_inbus[1] = chany_1__1__in_83_ ; -wire [279:279] mux_1level_tapbuf_size2_259_configbus0; -wire [279:279] mux_1level_tapbuf_size2_259_configbus1; -wire [279:279] mux_1level_tapbuf_size2_259_sram_blwl_out ; -wire [279:279] mux_1level_tapbuf_size2_259_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_259_configbus0[279:279] = sram_blwl_bl[279:279] ; -assign mux_1level_tapbuf_size2_259_configbus1[279:279] = sram_blwl_wl[279:279] ; -wire [279:279] mux_1level_tapbuf_size2_259_configbus0_b; -assign mux_1level_tapbuf_size2_259_configbus0_b[279:279] = sram_blwl_blb[279:279] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_259_ (mux_1level_tapbuf_size2_259_inbus, chanx_1__0__out_19_ , mux_1level_tapbuf_size2_259_sram_blwl_out[279:279] , -mux_1level_tapbuf_size2_259_sram_blwl_outb[279:279] ); -//----- SRAM bits for MUX[259], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_279_ (mux_1level_tapbuf_size2_259_sram_blwl_out[279:279] ,mux_1level_tapbuf_size2_259_sram_blwl_out[279:279] ,mux_1level_tapbuf_size2_259_sram_blwl_outb[279:279] ,mux_1level_tapbuf_size2_259_configbus0[279:279], mux_1level_tapbuf_size2_259_configbus1[279:279] , mux_1level_tapbuf_size2_259_configbus0_b[279:279] ); -wire [0:1] mux_1level_tapbuf_size2_260_inbus; -assign mux_1level_tapbuf_size2_260_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_260_inbus[1] = chany_1__1__in_81_ ; -wire [280:280] mux_1level_tapbuf_size2_260_configbus0; -wire [280:280] mux_1level_tapbuf_size2_260_configbus1; -wire [280:280] mux_1level_tapbuf_size2_260_sram_blwl_out ; -wire [280:280] mux_1level_tapbuf_size2_260_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_260_configbus0[280:280] = sram_blwl_bl[280:280] ; -assign mux_1level_tapbuf_size2_260_configbus1[280:280] = sram_blwl_wl[280:280] ; -wire [280:280] mux_1level_tapbuf_size2_260_configbus0_b; -assign mux_1level_tapbuf_size2_260_configbus0_b[280:280] = sram_blwl_blb[280:280] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_260_ (mux_1level_tapbuf_size2_260_inbus, chanx_1__0__out_21_ , mux_1level_tapbuf_size2_260_sram_blwl_out[280:280] , -mux_1level_tapbuf_size2_260_sram_blwl_outb[280:280] ); -//----- SRAM bits for MUX[260], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_280_ (mux_1level_tapbuf_size2_260_sram_blwl_out[280:280] ,mux_1level_tapbuf_size2_260_sram_blwl_out[280:280] ,mux_1level_tapbuf_size2_260_sram_blwl_outb[280:280] ,mux_1level_tapbuf_size2_260_configbus0[280:280], mux_1level_tapbuf_size2_260_configbus1[280:280] , mux_1level_tapbuf_size2_260_configbus0_b[280:280] ); -wire [0:1] mux_1level_tapbuf_size2_261_inbus; -assign mux_1level_tapbuf_size2_261_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_261_inbus[1] = chany_1__1__in_79_ ; -wire [281:281] mux_1level_tapbuf_size2_261_configbus0; -wire [281:281] mux_1level_tapbuf_size2_261_configbus1; -wire [281:281] mux_1level_tapbuf_size2_261_sram_blwl_out ; -wire [281:281] mux_1level_tapbuf_size2_261_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_261_configbus0[281:281] = sram_blwl_bl[281:281] ; -assign mux_1level_tapbuf_size2_261_configbus1[281:281] = sram_blwl_wl[281:281] ; -wire [281:281] mux_1level_tapbuf_size2_261_configbus0_b; -assign mux_1level_tapbuf_size2_261_configbus0_b[281:281] = sram_blwl_blb[281:281] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_261_ (mux_1level_tapbuf_size2_261_inbus, chanx_1__0__out_23_ , mux_1level_tapbuf_size2_261_sram_blwl_out[281:281] , -mux_1level_tapbuf_size2_261_sram_blwl_outb[281:281] ); -//----- SRAM bits for MUX[261], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_281_ (mux_1level_tapbuf_size2_261_sram_blwl_out[281:281] ,mux_1level_tapbuf_size2_261_sram_blwl_out[281:281] ,mux_1level_tapbuf_size2_261_sram_blwl_outb[281:281] ,mux_1level_tapbuf_size2_261_configbus0[281:281], mux_1level_tapbuf_size2_261_configbus1[281:281] , mux_1level_tapbuf_size2_261_configbus0_b[281:281] ); -wire [0:1] mux_1level_tapbuf_size2_262_inbus; -assign mux_1level_tapbuf_size2_262_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_262_inbus[1] = chany_1__1__in_77_ ; -wire [282:282] mux_1level_tapbuf_size2_262_configbus0; -wire [282:282] mux_1level_tapbuf_size2_262_configbus1; -wire [282:282] mux_1level_tapbuf_size2_262_sram_blwl_out ; -wire [282:282] mux_1level_tapbuf_size2_262_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_262_configbus0[282:282] = sram_blwl_bl[282:282] ; -assign mux_1level_tapbuf_size2_262_configbus1[282:282] = sram_blwl_wl[282:282] ; -wire [282:282] mux_1level_tapbuf_size2_262_configbus0_b; -assign mux_1level_tapbuf_size2_262_configbus0_b[282:282] = sram_blwl_blb[282:282] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_262_ (mux_1level_tapbuf_size2_262_inbus, chanx_1__0__out_25_ , mux_1level_tapbuf_size2_262_sram_blwl_out[282:282] , -mux_1level_tapbuf_size2_262_sram_blwl_outb[282:282] ); -//----- SRAM bits for MUX[262], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_282_ (mux_1level_tapbuf_size2_262_sram_blwl_out[282:282] ,mux_1level_tapbuf_size2_262_sram_blwl_out[282:282] ,mux_1level_tapbuf_size2_262_sram_blwl_outb[282:282] ,mux_1level_tapbuf_size2_262_configbus0[282:282], mux_1level_tapbuf_size2_262_configbus1[282:282] , mux_1level_tapbuf_size2_262_configbus0_b[282:282] ); -wire [0:1] mux_1level_tapbuf_size2_263_inbus; -assign mux_1level_tapbuf_size2_263_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_263_inbus[1] = chany_1__1__in_75_ ; -wire [283:283] mux_1level_tapbuf_size2_263_configbus0; -wire [283:283] mux_1level_tapbuf_size2_263_configbus1; -wire [283:283] mux_1level_tapbuf_size2_263_sram_blwl_out ; -wire [283:283] mux_1level_tapbuf_size2_263_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_263_configbus0[283:283] = sram_blwl_bl[283:283] ; -assign mux_1level_tapbuf_size2_263_configbus1[283:283] = sram_blwl_wl[283:283] ; -wire [283:283] mux_1level_tapbuf_size2_263_configbus0_b; -assign mux_1level_tapbuf_size2_263_configbus0_b[283:283] = sram_blwl_blb[283:283] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_263_ (mux_1level_tapbuf_size2_263_inbus, chanx_1__0__out_27_ , mux_1level_tapbuf_size2_263_sram_blwl_out[283:283] , -mux_1level_tapbuf_size2_263_sram_blwl_outb[283:283] ); -//----- SRAM bits for MUX[263], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_283_ (mux_1level_tapbuf_size2_263_sram_blwl_out[283:283] ,mux_1level_tapbuf_size2_263_sram_blwl_out[283:283] ,mux_1level_tapbuf_size2_263_sram_blwl_outb[283:283] ,mux_1level_tapbuf_size2_263_configbus0[283:283], mux_1level_tapbuf_size2_263_configbus1[283:283] , mux_1level_tapbuf_size2_263_configbus0_b[283:283] ); -wire [0:1] mux_1level_tapbuf_size2_264_inbus; -assign mux_1level_tapbuf_size2_264_inbus[0] = grid_1__0__pin_0__0__5_; -assign mux_1level_tapbuf_size2_264_inbus[1] = chany_1__1__in_73_ ; -wire [284:284] mux_1level_tapbuf_size2_264_configbus0; -wire [284:284] mux_1level_tapbuf_size2_264_configbus1; -wire [284:284] mux_1level_tapbuf_size2_264_sram_blwl_out ; -wire [284:284] mux_1level_tapbuf_size2_264_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_264_configbus0[284:284] = sram_blwl_bl[284:284] ; -assign mux_1level_tapbuf_size2_264_configbus1[284:284] = sram_blwl_wl[284:284] ; -wire [284:284] mux_1level_tapbuf_size2_264_configbus0_b; -assign mux_1level_tapbuf_size2_264_configbus0_b[284:284] = sram_blwl_blb[284:284] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_264_ (mux_1level_tapbuf_size2_264_inbus, chanx_1__0__out_29_ , mux_1level_tapbuf_size2_264_sram_blwl_out[284:284] , -mux_1level_tapbuf_size2_264_sram_blwl_outb[284:284] ); -//----- SRAM bits for MUX[264], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_284_ (mux_1level_tapbuf_size2_264_sram_blwl_out[284:284] ,mux_1level_tapbuf_size2_264_sram_blwl_out[284:284] ,mux_1level_tapbuf_size2_264_sram_blwl_outb[284:284] ,mux_1level_tapbuf_size2_264_configbus0[284:284], mux_1level_tapbuf_size2_264_configbus1[284:284] , mux_1level_tapbuf_size2_264_configbus0_b[284:284] ); -wire [0:1] mux_1level_tapbuf_size2_265_inbus; -assign mux_1level_tapbuf_size2_265_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_265_inbus[1] = chany_1__1__in_71_ ; -wire [285:285] mux_1level_tapbuf_size2_265_configbus0; -wire [285:285] mux_1level_tapbuf_size2_265_configbus1; -wire [285:285] mux_1level_tapbuf_size2_265_sram_blwl_out ; -wire [285:285] mux_1level_tapbuf_size2_265_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_265_configbus0[285:285] = sram_blwl_bl[285:285] ; -assign mux_1level_tapbuf_size2_265_configbus1[285:285] = sram_blwl_wl[285:285] ; -wire [285:285] mux_1level_tapbuf_size2_265_configbus0_b; -assign mux_1level_tapbuf_size2_265_configbus0_b[285:285] = sram_blwl_blb[285:285] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_265_ (mux_1level_tapbuf_size2_265_inbus, chanx_1__0__out_31_ , mux_1level_tapbuf_size2_265_sram_blwl_out[285:285] , -mux_1level_tapbuf_size2_265_sram_blwl_outb[285:285] ); -//----- SRAM bits for MUX[265], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_285_ (mux_1level_tapbuf_size2_265_sram_blwl_out[285:285] ,mux_1level_tapbuf_size2_265_sram_blwl_out[285:285] ,mux_1level_tapbuf_size2_265_sram_blwl_outb[285:285] ,mux_1level_tapbuf_size2_265_configbus0[285:285], mux_1level_tapbuf_size2_265_configbus1[285:285] , mux_1level_tapbuf_size2_265_configbus0_b[285:285] ); -wire [0:1] mux_1level_tapbuf_size2_266_inbus; -assign mux_1level_tapbuf_size2_266_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_266_inbus[1] = chany_1__1__in_69_ ; -wire [286:286] mux_1level_tapbuf_size2_266_configbus0; -wire [286:286] mux_1level_tapbuf_size2_266_configbus1; -wire [286:286] mux_1level_tapbuf_size2_266_sram_blwl_out ; -wire [286:286] mux_1level_tapbuf_size2_266_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_266_configbus0[286:286] = sram_blwl_bl[286:286] ; -assign mux_1level_tapbuf_size2_266_configbus1[286:286] = sram_blwl_wl[286:286] ; -wire [286:286] mux_1level_tapbuf_size2_266_configbus0_b; -assign mux_1level_tapbuf_size2_266_configbus0_b[286:286] = sram_blwl_blb[286:286] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_266_ (mux_1level_tapbuf_size2_266_inbus, chanx_1__0__out_33_ , mux_1level_tapbuf_size2_266_sram_blwl_out[286:286] , -mux_1level_tapbuf_size2_266_sram_blwl_outb[286:286] ); -//----- SRAM bits for MUX[266], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_286_ (mux_1level_tapbuf_size2_266_sram_blwl_out[286:286] ,mux_1level_tapbuf_size2_266_sram_blwl_out[286:286] ,mux_1level_tapbuf_size2_266_sram_blwl_outb[286:286] ,mux_1level_tapbuf_size2_266_configbus0[286:286], mux_1level_tapbuf_size2_266_configbus1[286:286] , mux_1level_tapbuf_size2_266_configbus0_b[286:286] ); -wire [0:1] mux_1level_tapbuf_size2_267_inbus; -assign mux_1level_tapbuf_size2_267_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_267_inbus[1] = chany_1__1__in_67_ ; -wire [287:287] mux_1level_tapbuf_size2_267_configbus0; -wire [287:287] mux_1level_tapbuf_size2_267_configbus1; -wire [287:287] mux_1level_tapbuf_size2_267_sram_blwl_out ; -wire [287:287] mux_1level_tapbuf_size2_267_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_267_configbus0[287:287] = sram_blwl_bl[287:287] ; -assign mux_1level_tapbuf_size2_267_configbus1[287:287] = sram_blwl_wl[287:287] ; -wire [287:287] mux_1level_tapbuf_size2_267_configbus0_b; -assign mux_1level_tapbuf_size2_267_configbus0_b[287:287] = sram_blwl_blb[287:287] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_267_ (mux_1level_tapbuf_size2_267_inbus, chanx_1__0__out_35_ , mux_1level_tapbuf_size2_267_sram_blwl_out[287:287] , -mux_1level_tapbuf_size2_267_sram_blwl_outb[287:287] ); -//----- SRAM bits for MUX[267], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_287_ (mux_1level_tapbuf_size2_267_sram_blwl_out[287:287] ,mux_1level_tapbuf_size2_267_sram_blwl_out[287:287] ,mux_1level_tapbuf_size2_267_sram_blwl_outb[287:287] ,mux_1level_tapbuf_size2_267_configbus0[287:287], mux_1level_tapbuf_size2_267_configbus1[287:287] , mux_1level_tapbuf_size2_267_configbus0_b[287:287] ); -wire [0:1] mux_1level_tapbuf_size2_268_inbus; -assign mux_1level_tapbuf_size2_268_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_268_inbus[1] = chany_1__1__in_65_ ; -wire [288:288] mux_1level_tapbuf_size2_268_configbus0; -wire [288:288] mux_1level_tapbuf_size2_268_configbus1; -wire [288:288] mux_1level_tapbuf_size2_268_sram_blwl_out ; -wire [288:288] mux_1level_tapbuf_size2_268_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_268_configbus0[288:288] = sram_blwl_bl[288:288] ; -assign mux_1level_tapbuf_size2_268_configbus1[288:288] = sram_blwl_wl[288:288] ; -wire [288:288] mux_1level_tapbuf_size2_268_configbus0_b; -assign mux_1level_tapbuf_size2_268_configbus0_b[288:288] = sram_blwl_blb[288:288] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_268_ (mux_1level_tapbuf_size2_268_inbus, chanx_1__0__out_37_ , mux_1level_tapbuf_size2_268_sram_blwl_out[288:288] , -mux_1level_tapbuf_size2_268_sram_blwl_outb[288:288] ); -//----- SRAM bits for MUX[268], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_288_ (mux_1level_tapbuf_size2_268_sram_blwl_out[288:288] ,mux_1level_tapbuf_size2_268_sram_blwl_out[288:288] ,mux_1level_tapbuf_size2_268_sram_blwl_outb[288:288] ,mux_1level_tapbuf_size2_268_configbus0[288:288], mux_1level_tapbuf_size2_268_configbus1[288:288] , mux_1level_tapbuf_size2_268_configbus0_b[288:288] ); -wire [0:1] mux_1level_tapbuf_size2_269_inbus; -assign mux_1level_tapbuf_size2_269_inbus[0] = grid_1__0__pin_0__0__7_; -assign mux_1level_tapbuf_size2_269_inbus[1] = chany_1__1__in_63_ ; -wire [289:289] mux_1level_tapbuf_size2_269_configbus0; -wire [289:289] mux_1level_tapbuf_size2_269_configbus1; -wire [289:289] mux_1level_tapbuf_size2_269_sram_blwl_out ; -wire [289:289] mux_1level_tapbuf_size2_269_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_269_configbus0[289:289] = sram_blwl_bl[289:289] ; -assign mux_1level_tapbuf_size2_269_configbus1[289:289] = sram_blwl_wl[289:289] ; -wire [289:289] mux_1level_tapbuf_size2_269_configbus0_b; -assign mux_1level_tapbuf_size2_269_configbus0_b[289:289] = sram_blwl_blb[289:289] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_269_ (mux_1level_tapbuf_size2_269_inbus, chanx_1__0__out_39_ , mux_1level_tapbuf_size2_269_sram_blwl_out[289:289] , -mux_1level_tapbuf_size2_269_sram_blwl_outb[289:289] ); -//----- SRAM bits for MUX[269], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_289_ (mux_1level_tapbuf_size2_269_sram_blwl_out[289:289] ,mux_1level_tapbuf_size2_269_sram_blwl_out[289:289] ,mux_1level_tapbuf_size2_269_sram_blwl_outb[289:289] ,mux_1level_tapbuf_size2_269_configbus0[289:289], mux_1level_tapbuf_size2_269_configbus1[289:289] , mux_1level_tapbuf_size2_269_configbus0_b[289:289] ); -wire [0:1] mux_1level_tapbuf_size2_270_inbus; -assign mux_1level_tapbuf_size2_270_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_270_inbus[1] = chany_1__1__in_61_ ; -wire [290:290] mux_1level_tapbuf_size2_270_configbus0; -wire [290:290] mux_1level_tapbuf_size2_270_configbus1; -wire [290:290] mux_1level_tapbuf_size2_270_sram_blwl_out ; -wire [290:290] mux_1level_tapbuf_size2_270_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_270_configbus0[290:290] = sram_blwl_bl[290:290] ; -assign mux_1level_tapbuf_size2_270_configbus1[290:290] = sram_blwl_wl[290:290] ; -wire [290:290] mux_1level_tapbuf_size2_270_configbus0_b; -assign mux_1level_tapbuf_size2_270_configbus0_b[290:290] = sram_blwl_blb[290:290] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_270_ (mux_1level_tapbuf_size2_270_inbus, chanx_1__0__out_41_ , mux_1level_tapbuf_size2_270_sram_blwl_out[290:290] , -mux_1level_tapbuf_size2_270_sram_blwl_outb[290:290] ); -//----- SRAM bits for MUX[270], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_290_ (mux_1level_tapbuf_size2_270_sram_blwl_out[290:290] ,mux_1level_tapbuf_size2_270_sram_blwl_out[290:290] ,mux_1level_tapbuf_size2_270_sram_blwl_outb[290:290] ,mux_1level_tapbuf_size2_270_configbus0[290:290], mux_1level_tapbuf_size2_270_configbus1[290:290] , mux_1level_tapbuf_size2_270_configbus0_b[290:290] ); -wire [0:1] mux_1level_tapbuf_size2_271_inbus; -assign mux_1level_tapbuf_size2_271_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_271_inbus[1] = chany_1__1__in_59_ ; -wire [291:291] mux_1level_tapbuf_size2_271_configbus0; -wire [291:291] mux_1level_tapbuf_size2_271_configbus1; -wire [291:291] mux_1level_tapbuf_size2_271_sram_blwl_out ; -wire [291:291] mux_1level_tapbuf_size2_271_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_271_configbus0[291:291] = sram_blwl_bl[291:291] ; -assign mux_1level_tapbuf_size2_271_configbus1[291:291] = sram_blwl_wl[291:291] ; -wire [291:291] mux_1level_tapbuf_size2_271_configbus0_b; -assign mux_1level_tapbuf_size2_271_configbus0_b[291:291] = sram_blwl_blb[291:291] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_271_ (mux_1level_tapbuf_size2_271_inbus, chanx_1__0__out_43_ , mux_1level_tapbuf_size2_271_sram_blwl_out[291:291] , -mux_1level_tapbuf_size2_271_sram_blwl_outb[291:291] ); -//----- SRAM bits for MUX[271], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_291_ (mux_1level_tapbuf_size2_271_sram_blwl_out[291:291] ,mux_1level_tapbuf_size2_271_sram_blwl_out[291:291] ,mux_1level_tapbuf_size2_271_sram_blwl_outb[291:291] ,mux_1level_tapbuf_size2_271_configbus0[291:291], mux_1level_tapbuf_size2_271_configbus1[291:291] , mux_1level_tapbuf_size2_271_configbus0_b[291:291] ); -wire [0:1] mux_1level_tapbuf_size2_272_inbus; -assign mux_1level_tapbuf_size2_272_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_272_inbus[1] = chany_1__1__in_57_ ; -wire [292:292] mux_1level_tapbuf_size2_272_configbus0; -wire [292:292] mux_1level_tapbuf_size2_272_configbus1; -wire [292:292] mux_1level_tapbuf_size2_272_sram_blwl_out ; -wire [292:292] mux_1level_tapbuf_size2_272_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_272_configbus0[292:292] = sram_blwl_bl[292:292] ; -assign mux_1level_tapbuf_size2_272_configbus1[292:292] = sram_blwl_wl[292:292] ; -wire [292:292] mux_1level_tapbuf_size2_272_configbus0_b; -assign mux_1level_tapbuf_size2_272_configbus0_b[292:292] = sram_blwl_blb[292:292] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_272_ (mux_1level_tapbuf_size2_272_inbus, chanx_1__0__out_45_ , mux_1level_tapbuf_size2_272_sram_blwl_out[292:292] , -mux_1level_tapbuf_size2_272_sram_blwl_outb[292:292] ); -//----- SRAM bits for MUX[272], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_292_ (mux_1level_tapbuf_size2_272_sram_blwl_out[292:292] ,mux_1level_tapbuf_size2_272_sram_blwl_out[292:292] ,mux_1level_tapbuf_size2_272_sram_blwl_outb[292:292] ,mux_1level_tapbuf_size2_272_configbus0[292:292], mux_1level_tapbuf_size2_272_configbus1[292:292] , mux_1level_tapbuf_size2_272_configbus0_b[292:292] ); -wire [0:1] mux_1level_tapbuf_size2_273_inbus; -assign mux_1level_tapbuf_size2_273_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_273_inbus[1] = chany_1__1__in_55_ ; -wire [293:293] mux_1level_tapbuf_size2_273_configbus0; -wire [293:293] mux_1level_tapbuf_size2_273_configbus1; -wire [293:293] mux_1level_tapbuf_size2_273_sram_blwl_out ; -wire [293:293] mux_1level_tapbuf_size2_273_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_273_configbus0[293:293] = sram_blwl_bl[293:293] ; -assign mux_1level_tapbuf_size2_273_configbus1[293:293] = sram_blwl_wl[293:293] ; -wire [293:293] mux_1level_tapbuf_size2_273_configbus0_b; -assign mux_1level_tapbuf_size2_273_configbus0_b[293:293] = sram_blwl_blb[293:293] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_273_ (mux_1level_tapbuf_size2_273_inbus, chanx_1__0__out_47_ , mux_1level_tapbuf_size2_273_sram_blwl_out[293:293] , -mux_1level_tapbuf_size2_273_sram_blwl_outb[293:293] ); -//----- SRAM bits for MUX[273], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_293_ (mux_1level_tapbuf_size2_273_sram_blwl_out[293:293] ,mux_1level_tapbuf_size2_273_sram_blwl_out[293:293] ,mux_1level_tapbuf_size2_273_sram_blwl_outb[293:293] ,mux_1level_tapbuf_size2_273_configbus0[293:293], mux_1level_tapbuf_size2_273_configbus1[293:293] , mux_1level_tapbuf_size2_273_configbus0_b[293:293] ); -wire [0:1] mux_1level_tapbuf_size2_274_inbus; -assign mux_1level_tapbuf_size2_274_inbus[0] = grid_1__0__pin_0__0__9_; -assign mux_1level_tapbuf_size2_274_inbus[1] = chany_1__1__in_53_ ; -wire [294:294] mux_1level_tapbuf_size2_274_configbus0; -wire [294:294] mux_1level_tapbuf_size2_274_configbus1; -wire [294:294] mux_1level_tapbuf_size2_274_sram_blwl_out ; -wire [294:294] mux_1level_tapbuf_size2_274_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_274_configbus0[294:294] = sram_blwl_bl[294:294] ; -assign mux_1level_tapbuf_size2_274_configbus1[294:294] = sram_blwl_wl[294:294] ; -wire [294:294] mux_1level_tapbuf_size2_274_configbus0_b; -assign mux_1level_tapbuf_size2_274_configbus0_b[294:294] = sram_blwl_blb[294:294] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_274_ (mux_1level_tapbuf_size2_274_inbus, chanx_1__0__out_49_ , mux_1level_tapbuf_size2_274_sram_blwl_out[294:294] , -mux_1level_tapbuf_size2_274_sram_blwl_outb[294:294] ); -//----- SRAM bits for MUX[274], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_294_ (mux_1level_tapbuf_size2_274_sram_blwl_out[294:294] ,mux_1level_tapbuf_size2_274_sram_blwl_out[294:294] ,mux_1level_tapbuf_size2_274_sram_blwl_outb[294:294] ,mux_1level_tapbuf_size2_274_configbus0[294:294], mux_1level_tapbuf_size2_274_configbus1[294:294] , mux_1level_tapbuf_size2_274_configbus0_b[294:294] ); -wire [0:1] mux_1level_tapbuf_size2_275_inbus; -assign mux_1level_tapbuf_size2_275_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_275_inbus[1] = chany_1__1__in_51_ ; -wire [295:295] mux_1level_tapbuf_size2_275_configbus0; -wire [295:295] mux_1level_tapbuf_size2_275_configbus1; -wire [295:295] mux_1level_tapbuf_size2_275_sram_blwl_out ; -wire [295:295] mux_1level_tapbuf_size2_275_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_275_configbus0[295:295] = sram_blwl_bl[295:295] ; -assign mux_1level_tapbuf_size2_275_configbus1[295:295] = sram_blwl_wl[295:295] ; -wire [295:295] mux_1level_tapbuf_size2_275_configbus0_b; -assign mux_1level_tapbuf_size2_275_configbus0_b[295:295] = sram_blwl_blb[295:295] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_275_ (mux_1level_tapbuf_size2_275_inbus, chanx_1__0__out_51_ , mux_1level_tapbuf_size2_275_sram_blwl_out[295:295] , -mux_1level_tapbuf_size2_275_sram_blwl_outb[295:295] ); -//----- SRAM bits for MUX[275], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_295_ (mux_1level_tapbuf_size2_275_sram_blwl_out[295:295] ,mux_1level_tapbuf_size2_275_sram_blwl_out[295:295] ,mux_1level_tapbuf_size2_275_sram_blwl_outb[295:295] ,mux_1level_tapbuf_size2_275_configbus0[295:295], mux_1level_tapbuf_size2_275_configbus1[295:295] , mux_1level_tapbuf_size2_275_configbus0_b[295:295] ); -wire [0:1] mux_1level_tapbuf_size2_276_inbus; -assign mux_1level_tapbuf_size2_276_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_276_inbus[1] = chany_1__1__in_49_ ; -wire [296:296] mux_1level_tapbuf_size2_276_configbus0; -wire [296:296] mux_1level_tapbuf_size2_276_configbus1; -wire [296:296] mux_1level_tapbuf_size2_276_sram_blwl_out ; -wire [296:296] mux_1level_tapbuf_size2_276_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_276_configbus0[296:296] = sram_blwl_bl[296:296] ; -assign mux_1level_tapbuf_size2_276_configbus1[296:296] = sram_blwl_wl[296:296] ; -wire [296:296] mux_1level_tapbuf_size2_276_configbus0_b; -assign mux_1level_tapbuf_size2_276_configbus0_b[296:296] = sram_blwl_blb[296:296] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_276_ (mux_1level_tapbuf_size2_276_inbus, chanx_1__0__out_53_ , mux_1level_tapbuf_size2_276_sram_blwl_out[296:296] , -mux_1level_tapbuf_size2_276_sram_blwl_outb[296:296] ); -//----- SRAM bits for MUX[276], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_296_ (mux_1level_tapbuf_size2_276_sram_blwl_out[296:296] ,mux_1level_tapbuf_size2_276_sram_blwl_out[296:296] ,mux_1level_tapbuf_size2_276_sram_blwl_outb[296:296] ,mux_1level_tapbuf_size2_276_configbus0[296:296], mux_1level_tapbuf_size2_276_configbus1[296:296] , mux_1level_tapbuf_size2_276_configbus0_b[296:296] ); -wire [0:1] mux_1level_tapbuf_size2_277_inbus; -assign mux_1level_tapbuf_size2_277_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_277_inbus[1] = chany_1__1__in_47_ ; -wire [297:297] mux_1level_tapbuf_size2_277_configbus0; -wire [297:297] mux_1level_tapbuf_size2_277_configbus1; -wire [297:297] mux_1level_tapbuf_size2_277_sram_blwl_out ; -wire [297:297] mux_1level_tapbuf_size2_277_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_277_configbus0[297:297] = sram_blwl_bl[297:297] ; -assign mux_1level_tapbuf_size2_277_configbus1[297:297] = sram_blwl_wl[297:297] ; -wire [297:297] mux_1level_tapbuf_size2_277_configbus0_b; -assign mux_1level_tapbuf_size2_277_configbus0_b[297:297] = sram_blwl_blb[297:297] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_277_ (mux_1level_tapbuf_size2_277_inbus, chanx_1__0__out_55_ , mux_1level_tapbuf_size2_277_sram_blwl_out[297:297] , -mux_1level_tapbuf_size2_277_sram_blwl_outb[297:297] ); -//----- SRAM bits for MUX[277], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_297_ (mux_1level_tapbuf_size2_277_sram_blwl_out[297:297] ,mux_1level_tapbuf_size2_277_sram_blwl_out[297:297] ,mux_1level_tapbuf_size2_277_sram_blwl_outb[297:297] ,mux_1level_tapbuf_size2_277_configbus0[297:297], mux_1level_tapbuf_size2_277_configbus1[297:297] , mux_1level_tapbuf_size2_277_configbus0_b[297:297] ); -wire [0:1] mux_1level_tapbuf_size2_278_inbus; -assign mux_1level_tapbuf_size2_278_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_278_inbus[1] = chany_1__1__in_45_ ; -wire [298:298] mux_1level_tapbuf_size2_278_configbus0; -wire [298:298] mux_1level_tapbuf_size2_278_configbus1; -wire [298:298] mux_1level_tapbuf_size2_278_sram_blwl_out ; -wire [298:298] mux_1level_tapbuf_size2_278_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_278_configbus0[298:298] = sram_blwl_bl[298:298] ; -assign mux_1level_tapbuf_size2_278_configbus1[298:298] = sram_blwl_wl[298:298] ; -wire [298:298] mux_1level_tapbuf_size2_278_configbus0_b; -assign mux_1level_tapbuf_size2_278_configbus0_b[298:298] = sram_blwl_blb[298:298] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_278_ (mux_1level_tapbuf_size2_278_inbus, chanx_1__0__out_57_ , mux_1level_tapbuf_size2_278_sram_blwl_out[298:298] , -mux_1level_tapbuf_size2_278_sram_blwl_outb[298:298] ); -//----- SRAM bits for MUX[278], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_298_ (mux_1level_tapbuf_size2_278_sram_blwl_out[298:298] ,mux_1level_tapbuf_size2_278_sram_blwl_out[298:298] ,mux_1level_tapbuf_size2_278_sram_blwl_outb[298:298] ,mux_1level_tapbuf_size2_278_configbus0[298:298], mux_1level_tapbuf_size2_278_configbus1[298:298] , mux_1level_tapbuf_size2_278_configbus0_b[298:298] ); -wire [0:1] mux_1level_tapbuf_size2_279_inbus; -assign mux_1level_tapbuf_size2_279_inbus[0] = grid_1__0__pin_0__0__11_; -assign mux_1level_tapbuf_size2_279_inbus[1] = chany_1__1__in_43_ ; -wire [299:299] mux_1level_tapbuf_size2_279_configbus0; -wire [299:299] mux_1level_tapbuf_size2_279_configbus1; -wire [299:299] mux_1level_tapbuf_size2_279_sram_blwl_out ; -wire [299:299] mux_1level_tapbuf_size2_279_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_279_configbus0[299:299] = sram_blwl_bl[299:299] ; -assign mux_1level_tapbuf_size2_279_configbus1[299:299] = sram_blwl_wl[299:299] ; -wire [299:299] mux_1level_tapbuf_size2_279_configbus0_b; -assign mux_1level_tapbuf_size2_279_configbus0_b[299:299] = sram_blwl_blb[299:299] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_279_ (mux_1level_tapbuf_size2_279_inbus, chanx_1__0__out_59_ , mux_1level_tapbuf_size2_279_sram_blwl_out[299:299] , -mux_1level_tapbuf_size2_279_sram_blwl_outb[299:299] ); -//----- SRAM bits for MUX[279], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_299_ (mux_1level_tapbuf_size2_279_sram_blwl_out[299:299] ,mux_1level_tapbuf_size2_279_sram_blwl_out[299:299] ,mux_1level_tapbuf_size2_279_sram_blwl_outb[299:299] ,mux_1level_tapbuf_size2_279_configbus0[299:299], mux_1level_tapbuf_size2_279_configbus1[299:299] , mux_1level_tapbuf_size2_279_configbus0_b[299:299] ); -wire [0:1] mux_1level_tapbuf_size2_280_inbus; -assign mux_1level_tapbuf_size2_280_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_280_inbus[1] = chany_1__1__in_41_ ; -wire [300:300] mux_1level_tapbuf_size2_280_configbus0; -wire [300:300] mux_1level_tapbuf_size2_280_configbus1; -wire [300:300] mux_1level_tapbuf_size2_280_sram_blwl_out ; -wire [300:300] mux_1level_tapbuf_size2_280_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_280_configbus0[300:300] = sram_blwl_bl[300:300] ; -assign mux_1level_tapbuf_size2_280_configbus1[300:300] = sram_blwl_wl[300:300] ; -wire [300:300] mux_1level_tapbuf_size2_280_configbus0_b; -assign mux_1level_tapbuf_size2_280_configbus0_b[300:300] = sram_blwl_blb[300:300] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_280_ (mux_1level_tapbuf_size2_280_inbus, chanx_1__0__out_61_ , mux_1level_tapbuf_size2_280_sram_blwl_out[300:300] , -mux_1level_tapbuf_size2_280_sram_blwl_outb[300:300] ); -//----- SRAM bits for MUX[280], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_300_ (mux_1level_tapbuf_size2_280_sram_blwl_out[300:300] ,mux_1level_tapbuf_size2_280_sram_blwl_out[300:300] ,mux_1level_tapbuf_size2_280_sram_blwl_outb[300:300] ,mux_1level_tapbuf_size2_280_configbus0[300:300], mux_1level_tapbuf_size2_280_configbus1[300:300] , mux_1level_tapbuf_size2_280_configbus0_b[300:300] ); -wire [0:1] mux_1level_tapbuf_size2_281_inbus; -assign mux_1level_tapbuf_size2_281_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_281_inbus[1] = chany_1__1__in_39_ ; -wire [301:301] mux_1level_tapbuf_size2_281_configbus0; -wire [301:301] mux_1level_tapbuf_size2_281_configbus1; -wire [301:301] mux_1level_tapbuf_size2_281_sram_blwl_out ; -wire [301:301] mux_1level_tapbuf_size2_281_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_281_configbus0[301:301] = sram_blwl_bl[301:301] ; -assign mux_1level_tapbuf_size2_281_configbus1[301:301] = sram_blwl_wl[301:301] ; -wire [301:301] mux_1level_tapbuf_size2_281_configbus0_b; -assign mux_1level_tapbuf_size2_281_configbus0_b[301:301] = sram_blwl_blb[301:301] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_281_ (mux_1level_tapbuf_size2_281_inbus, chanx_1__0__out_63_ , mux_1level_tapbuf_size2_281_sram_blwl_out[301:301] , -mux_1level_tapbuf_size2_281_sram_blwl_outb[301:301] ); -//----- SRAM bits for MUX[281], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_301_ (mux_1level_tapbuf_size2_281_sram_blwl_out[301:301] ,mux_1level_tapbuf_size2_281_sram_blwl_out[301:301] ,mux_1level_tapbuf_size2_281_sram_blwl_outb[301:301] ,mux_1level_tapbuf_size2_281_configbus0[301:301], mux_1level_tapbuf_size2_281_configbus1[301:301] , mux_1level_tapbuf_size2_281_configbus0_b[301:301] ); -wire [0:1] mux_1level_tapbuf_size2_282_inbus; -assign mux_1level_tapbuf_size2_282_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_282_inbus[1] = chany_1__1__in_37_ ; -wire [302:302] mux_1level_tapbuf_size2_282_configbus0; -wire [302:302] mux_1level_tapbuf_size2_282_configbus1; -wire [302:302] mux_1level_tapbuf_size2_282_sram_blwl_out ; -wire [302:302] mux_1level_tapbuf_size2_282_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_282_configbus0[302:302] = sram_blwl_bl[302:302] ; -assign mux_1level_tapbuf_size2_282_configbus1[302:302] = sram_blwl_wl[302:302] ; -wire [302:302] mux_1level_tapbuf_size2_282_configbus0_b; -assign mux_1level_tapbuf_size2_282_configbus0_b[302:302] = sram_blwl_blb[302:302] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_282_ (mux_1level_tapbuf_size2_282_inbus, chanx_1__0__out_65_ , mux_1level_tapbuf_size2_282_sram_blwl_out[302:302] , -mux_1level_tapbuf_size2_282_sram_blwl_outb[302:302] ); -//----- SRAM bits for MUX[282], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_302_ (mux_1level_tapbuf_size2_282_sram_blwl_out[302:302] ,mux_1level_tapbuf_size2_282_sram_blwl_out[302:302] ,mux_1level_tapbuf_size2_282_sram_blwl_outb[302:302] ,mux_1level_tapbuf_size2_282_configbus0[302:302], mux_1level_tapbuf_size2_282_configbus1[302:302] , mux_1level_tapbuf_size2_282_configbus0_b[302:302] ); -wire [0:1] mux_1level_tapbuf_size2_283_inbus; -assign mux_1level_tapbuf_size2_283_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_283_inbus[1] = chany_1__1__in_35_ ; -wire [303:303] mux_1level_tapbuf_size2_283_configbus0; -wire [303:303] mux_1level_tapbuf_size2_283_configbus1; -wire [303:303] mux_1level_tapbuf_size2_283_sram_blwl_out ; -wire [303:303] mux_1level_tapbuf_size2_283_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_283_configbus0[303:303] = sram_blwl_bl[303:303] ; -assign mux_1level_tapbuf_size2_283_configbus1[303:303] = sram_blwl_wl[303:303] ; -wire [303:303] mux_1level_tapbuf_size2_283_configbus0_b; -assign mux_1level_tapbuf_size2_283_configbus0_b[303:303] = sram_blwl_blb[303:303] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_283_ (mux_1level_tapbuf_size2_283_inbus, chanx_1__0__out_67_ , mux_1level_tapbuf_size2_283_sram_blwl_out[303:303] , -mux_1level_tapbuf_size2_283_sram_blwl_outb[303:303] ); -//----- SRAM bits for MUX[283], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_303_ (mux_1level_tapbuf_size2_283_sram_blwl_out[303:303] ,mux_1level_tapbuf_size2_283_sram_blwl_out[303:303] ,mux_1level_tapbuf_size2_283_sram_blwl_outb[303:303] ,mux_1level_tapbuf_size2_283_configbus0[303:303], mux_1level_tapbuf_size2_283_configbus1[303:303] , mux_1level_tapbuf_size2_283_configbus0_b[303:303] ); -wire [0:1] mux_1level_tapbuf_size2_284_inbus; -assign mux_1level_tapbuf_size2_284_inbus[0] = grid_1__0__pin_0__0__13_; -assign mux_1level_tapbuf_size2_284_inbus[1] = chany_1__1__in_33_ ; -wire [304:304] mux_1level_tapbuf_size2_284_configbus0; -wire [304:304] mux_1level_tapbuf_size2_284_configbus1; -wire [304:304] mux_1level_tapbuf_size2_284_sram_blwl_out ; -wire [304:304] mux_1level_tapbuf_size2_284_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_284_configbus0[304:304] = sram_blwl_bl[304:304] ; -assign mux_1level_tapbuf_size2_284_configbus1[304:304] = sram_blwl_wl[304:304] ; -wire [304:304] mux_1level_tapbuf_size2_284_configbus0_b; -assign mux_1level_tapbuf_size2_284_configbus0_b[304:304] = sram_blwl_blb[304:304] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_284_ (mux_1level_tapbuf_size2_284_inbus, chanx_1__0__out_69_ , mux_1level_tapbuf_size2_284_sram_blwl_out[304:304] , -mux_1level_tapbuf_size2_284_sram_blwl_outb[304:304] ); -//----- SRAM bits for MUX[284], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_304_ (mux_1level_tapbuf_size2_284_sram_blwl_out[304:304] ,mux_1level_tapbuf_size2_284_sram_blwl_out[304:304] ,mux_1level_tapbuf_size2_284_sram_blwl_outb[304:304] ,mux_1level_tapbuf_size2_284_configbus0[304:304], mux_1level_tapbuf_size2_284_configbus1[304:304] , mux_1level_tapbuf_size2_284_configbus0_b[304:304] ); -wire [0:1] mux_1level_tapbuf_size2_285_inbus; -assign mux_1level_tapbuf_size2_285_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_285_inbus[1] = chany_1__1__in_31_ ; -wire [305:305] mux_1level_tapbuf_size2_285_configbus0; -wire [305:305] mux_1level_tapbuf_size2_285_configbus1; -wire [305:305] mux_1level_tapbuf_size2_285_sram_blwl_out ; -wire [305:305] mux_1level_tapbuf_size2_285_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_285_configbus0[305:305] = sram_blwl_bl[305:305] ; -assign mux_1level_tapbuf_size2_285_configbus1[305:305] = sram_blwl_wl[305:305] ; -wire [305:305] mux_1level_tapbuf_size2_285_configbus0_b; -assign mux_1level_tapbuf_size2_285_configbus0_b[305:305] = sram_blwl_blb[305:305] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_285_ (mux_1level_tapbuf_size2_285_inbus, chanx_1__0__out_71_ , mux_1level_tapbuf_size2_285_sram_blwl_out[305:305] , -mux_1level_tapbuf_size2_285_sram_blwl_outb[305:305] ); -//----- SRAM bits for MUX[285], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_305_ (mux_1level_tapbuf_size2_285_sram_blwl_out[305:305] ,mux_1level_tapbuf_size2_285_sram_blwl_out[305:305] ,mux_1level_tapbuf_size2_285_sram_blwl_outb[305:305] ,mux_1level_tapbuf_size2_285_configbus0[305:305], mux_1level_tapbuf_size2_285_configbus1[305:305] , mux_1level_tapbuf_size2_285_configbus0_b[305:305] ); -wire [0:1] mux_1level_tapbuf_size2_286_inbus; -assign mux_1level_tapbuf_size2_286_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_286_inbus[1] = chany_1__1__in_29_ ; -wire [306:306] mux_1level_tapbuf_size2_286_configbus0; -wire [306:306] mux_1level_tapbuf_size2_286_configbus1; -wire [306:306] mux_1level_tapbuf_size2_286_sram_blwl_out ; -wire [306:306] mux_1level_tapbuf_size2_286_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_286_configbus0[306:306] = sram_blwl_bl[306:306] ; -assign mux_1level_tapbuf_size2_286_configbus1[306:306] = sram_blwl_wl[306:306] ; -wire [306:306] mux_1level_tapbuf_size2_286_configbus0_b; -assign mux_1level_tapbuf_size2_286_configbus0_b[306:306] = sram_blwl_blb[306:306] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_286_ (mux_1level_tapbuf_size2_286_inbus, chanx_1__0__out_73_ , mux_1level_tapbuf_size2_286_sram_blwl_out[306:306] , -mux_1level_tapbuf_size2_286_sram_blwl_outb[306:306] ); -//----- SRAM bits for MUX[286], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_306_ (mux_1level_tapbuf_size2_286_sram_blwl_out[306:306] ,mux_1level_tapbuf_size2_286_sram_blwl_out[306:306] ,mux_1level_tapbuf_size2_286_sram_blwl_outb[306:306] ,mux_1level_tapbuf_size2_286_configbus0[306:306], mux_1level_tapbuf_size2_286_configbus1[306:306] , mux_1level_tapbuf_size2_286_configbus0_b[306:306] ); -wire [0:1] mux_1level_tapbuf_size2_287_inbus; -assign mux_1level_tapbuf_size2_287_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_287_inbus[1] = chany_1__1__in_27_ ; -wire [307:307] mux_1level_tapbuf_size2_287_configbus0; -wire [307:307] mux_1level_tapbuf_size2_287_configbus1; -wire [307:307] mux_1level_tapbuf_size2_287_sram_blwl_out ; -wire [307:307] mux_1level_tapbuf_size2_287_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_287_configbus0[307:307] = sram_blwl_bl[307:307] ; -assign mux_1level_tapbuf_size2_287_configbus1[307:307] = sram_blwl_wl[307:307] ; -wire [307:307] mux_1level_tapbuf_size2_287_configbus0_b; -assign mux_1level_tapbuf_size2_287_configbus0_b[307:307] = sram_blwl_blb[307:307] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_287_ (mux_1level_tapbuf_size2_287_inbus, chanx_1__0__out_75_ , mux_1level_tapbuf_size2_287_sram_blwl_out[307:307] , -mux_1level_tapbuf_size2_287_sram_blwl_outb[307:307] ); -//----- SRAM bits for MUX[287], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_307_ (mux_1level_tapbuf_size2_287_sram_blwl_out[307:307] ,mux_1level_tapbuf_size2_287_sram_blwl_out[307:307] ,mux_1level_tapbuf_size2_287_sram_blwl_outb[307:307] ,mux_1level_tapbuf_size2_287_configbus0[307:307], mux_1level_tapbuf_size2_287_configbus1[307:307] , mux_1level_tapbuf_size2_287_configbus0_b[307:307] ); -wire [0:1] mux_1level_tapbuf_size2_288_inbus; -assign mux_1level_tapbuf_size2_288_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_288_inbus[1] = chany_1__1__in_25_ ; -wire [308:308] mux_1level_tapbuf_size2_288_configbus0; -wire [308:308] mux_1level_tapbuf_size2_288_configbus1; -wire [308:308] mux_1level_tapbuf_size2_288_sram_blwl_out ; -wire [308:308] mux_1level_tapbuf_size2_288_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_288_configbus0[308:308] = sram_blwl_bl[308:308] ; -assign mux_1level_tapbuf_size2_288_configbus1[308:308] = sram_blwl_wl[308:308] ; -wire [308:308] mux_1level_tapbuf_size2_288_configbus0_b; -assign mux_1level_tapbuf_size2_288_configbus0_b[308:308] = sram_blwl_blb[308:308] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_288_ (mux_1level_tapbuf_size2_288_inbus, chanx_1__0__out_77_ , mux_1level_tapbuf_size2_288_sram_blwl_out[308:308] , -mux_1level_tapbuf_size2_288_sram_blwl_outb[308:308] ); -//----- SRAM bits for MUX[288], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_308_ (mux_1level_tapbuf_size2_288_sram_blwl_out[308:308] ,mux_1level_tapbuf_size2_288_sram_blwl_out[308:308] ,mux_1level_tapbuf_size2_288_sram_blwl_outb[308:308] ,mux_1level_tapbuf_size2_288_configbus0[308:308], mux_1level_tapbuf_size2_288_configbus1[308:308] , mux_1level_tapbuf_size2_288_configbus0_b[308:308] ); -wire [0:1] mux_1level_tapbuf_size2_289_inbus; -assign mux_1level_tapbuf_size2_289_inbus[0] = grid_1__0__pin_0__0__15_; -assign mux_1level_tapbuf_size2_289_inbus[1] = chany_1__1__in_23_ ; -wire [309:309] mux_1level_tapbuf_size2_289_configbus0; -wire [309:309] mux_1level_tapbuf_size2_289_configbus1; -wire [309:309] mux_1level_tapbuf_size2_289_sram_blwl_out ; -wire [309:309] mux_1level_tapbuf_size2_289_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_289_configbus0[309:309] = sram_blwl_bl[309:309] ; -assign mux_1level_tapbuf_size2_289_configbus1[309:309] = sram_blwl_wl[309:309] ; -wire [309:309] mux_1level_tapbuf_size2_289_configbus0_b; -assign mux_1level_tapbuf_size2_289_configbus0_b[309:309] = sram_blwl_blb[309:309] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_289_ (mux_1level_tapbuf_size2_289_inbus, chanx_1__0__out_79_ , mux_1level_tapbuf_size2_289_sram_blwl_out[309:309] , -mux_1level_tapbuf_size2_289_sram_blwl_outb[309:309] ); -//----- SRAM bits for MUX[289], level=1, select_path_id=1. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----0----- -sram6T_blwl sram_blwl_309_ (mux_1level_tapbuf_size2_289_sram_blwl_out[309:309] ,mux_1level_tapbuf_size2_289_sram_blwl_out[309:309] ,mux_1level_tapbuf_size2_289_sram_blwl_outb[309:309] ,mux_1level_tapbuf_size2_289_configbus0[309:309], mux_1level_tapbuf_size2_289_configbus1[309:309] , mux_1level_tapbuf_size2_289_configbus0_b[309:309] ); -wire [0:1] mux_1level_tapbuf_size2_290_inbus; -assign mux_1level_tapbuf_size2_290_inbus[0] = grid_1__1__pin_0__2__42_; -assign mux_1level_tapbuf_size2_290_inbus[1] = chany_1__1__in_21_ ; -wire [310:310] mux_1level_tapbuf_size2_290_configbus0; -wire [310:310] mux_1level_tapbuf_size2_290_configbus1; -wire [310:310] mux_1level_tapbuf_size2_290_sram_blwl_out ; -wire [310:310] mux_1level_tapbuf_size2_290_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_290_configbus0[310:310] = sram_blwl_bl[310:310] ; -assign mux_1level_tapbuf_size2_290_configbus1[310:310] = sram_blwl_wl[310:310] ; -wire [310:310] mux_1level_tapbuf_size2_290_configbus0_b; -assign mux_1level_tapbuf_size2_290_configbus0_b[310:310] = sram_blwl_blb[310:310] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_290_ (mux_1level_tapbuf_size2_290_inbus, chanx_1__0__out_81_ , mux_1level_tapbuf_size2_290_sram_blwl_out[310:310] , -mux_1level_tapbuf_size2_290_sram_blwl_outb[310:310] ); -//----- SRAM bits for MUX[290], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_310_ (mux_1level_tapbuf_size2_290_sram_blwl_out[310:310] ,mux_1level_tapbuf_size2_290_sram_blwl_out[310:310] ,mux_1level_tapbuf_size2_290_sram_blwl_outb[310:310] ,mux_1level_tapbuf_size2_290_configbus0[310:310], mux_1level_tapbuf_size2_290_configbus1[310:310] , mux_1level_tapbuf_size2_290_configbus0_b[310:310] ); -wire [0:1] mux_1level_tapbuf_size2_291_inbus; -assign mux_1level_tapbuf_size2_291_inbus[0] = grid_1__1__pin_0__2__42_; -assign mux_1level_tapbuf_size2_291_inbus[1] = chany_1__1__in_19_ ; -wire [311:311] mux_1level_tapbuf_size2_291_configbus0; -wire [311:311] mux_1level_tapbuf_size2_291_configbus1; -wire [311:311] mux_1level_tapbuf_size2_291_sram_blwl_out ; -wire [311:311] mux_1level_tapbuf_size2_291_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_291_configbus0[311:311] = sram_blwl_bl[311:311] ; -assign mux_1level_tapbuf_size2_291_configbus1[311:311] = sram_blwl_wl[311:311] ; -wire [311:311] mux_1level_tapbuf_size2_291_configbus0_b; -assign mux_1level_tapbuf_size2_291_configbus0_b[311:311] = sram_blwl_blb[311:311] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_291_ (mux_1level_tapbuf_size2_291_inbus, chanx_1__0__out_83_ , mux_1level_tapbuf_size2_291_sram_blwl_out[311:311] , -mux_1level_tapbuf_size2_291_sram_blwl_outb[311:311] ); -//----- SRAM bits for MUX[291], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_311_ (mux_1level_tapbuf_size2_291_sram_blwl_out[311:311] ,mux_1level_tapbuf_size2_291_sram_blwl_out[311:311] ,mux_1level_tapbuf_size2_291_sram_blwl_outb[311:311] ,mux_1level_tapbuf_size2_291_configbus0[311:311], mux_1level_tapbuf_size2_291_configbus1[311:311] , mux_1level_tapbuf_size2_291_configbus0_b[311:311] ); -wire [0:1] mux_1level_tapbuf_size2_292_inbus; -assign mux_1level_tapbuf_size2_292_inbus[0] = grid_1__1__pin_0__2__42_; -assign mux_1level_tapbuf_size2_292_inbus[1] = chany_1__1__in_17_ ; -wire [312:312] mux_1level_tapbuf_size2_292_configbus0; -wire [312:312] mux_1level_tapbuf_size2_292_configbus1; -wire [312:312] mux_1level_tapbuf_size2_292_sram_blwl_out ; -wire [312:312] mux_1level_tapbuf_size2_292_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_292_configbus0[312:312] = sram_blwl_bl[312:312] ; -assign mux_1level_tapbuf_size2_292_configbus1[312:312] = sram_blwl_wl[312:312] ; -wire [312:312] mux_1level_tapbuf_size2_292_configbus0_b; -assign mux_1level_tapbuf_size2_292_configbus0_b[312:312] = sram_blwl_blb[312:312] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_292_ (mux_1level_tapbuf_size2_292_inbus, chanx_1__0__out_85_ , mux_1level_tapbuf_size2_292_sram_blwl_out[312:312] , -mux_1level_tapbuf_size2_292_sram_blwl_outb[312:312] ); -//----- SRAM bits for MUX[292], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_312_ (mux_1level_tapbuf_size2_292_sram_blwl_out[312:312] ,mux_1level_tapbuf_size2_292_sram_blwl_out[312:312] ,mux_1level_tapbuf_size2_292_sram_blwl_outb[312:312] ,mux_1level_tapbuf_size2_292_configbus0[312:312], mux_1level_tapbuf_size2_292_configbus1[312:312] , mux_1level_tapbuf_size2_292_configbus0_b[312:312] ); -wire [0:1] mux_1level_tapbuf_size2_293_inbus; -assign mux_1level_tapbuf_size2_293_inbus[0] = grid_1__1__pin_0__2__42_; -assign mux_1level_tapbuf_size2_293_inbus[1] = chany_1__1__in_15_ ; -wire [313:313] mux_1level_tapbuf_size2_293_configbus0; -wire [313:313] mux_1level_tapbuf_size2_293_configbus1; -wire [313:313] mux_1level_tapbuf_size2_293_sram_blwl_out ; -wire [313:313] mux_1level_tapbuf_size2_293_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_293_configbus0[313:313] = sram_blwl_bl[313:313] ; -assign mux_1level_tapbuf_size2_293_configbus1[313:313] = sram_blwl_wl[313:313] ; -wire [313:313] mux_1level_tapbuf_size2_293_configbus0_b; -assign mux_1level_tapbuf_size2_293_configbus0_b[313:313] = sram_blwl_blb[313:313] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_293_ (mux_1level_tapbuf_size2_293_inbus, chanx_1__0__out_87_ , mux_1level_tapbuf_size2_293_sram_blwl_out[313:313] , -mux_1level_tapbuf_size2_293_sram_blwl_outb[313:313] ); -//----- SRAM bits for MUX[293], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_313_ (mux_1level_tapbuf_size2_293_sram_blwl_out[313:313] ,mux_1level_tapbuf_size2_293_sram_blwl_out[313:313] ,mux_1level_tapbuf_size2_293_sram_blwl_outb[313:313] ,mux_1level_tapbuf_size2_293_configbus0[313:313], mux_1level_tapbuf_size2_293_configbus1[313:313] , mux_1level_tapbuf_size2_293_configbus0_b[313:313] ); -wire [0:1] mux_1level_tapbuf_size2_294_inbus; -assign mux_1level_tapbuf_size2_294_inbus[0] = grid_1__1__pin_0__2__42_; -assign mux_1level_tapbuf_size2_294_inbus[1] = chany_1__1__in_13_ ; -wire [314:314] mux_1level_tapbuf_size2_294_configbus0; -wire [314:314] mux_1level_tapbuf_size2_294_configbus1; -wire [314:314] mux_1level_tapbuf_size2_294_sram_blwl_out ; -wire [314:314] mux_1level_tapbuf_size2_294_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_294_configbus0[314:314] = sram_blwl_bl[314:314] ; -assign mux_1level_tapbuf_size2_294_configbus1[314:314] = sram_blwl_wl[314:314] ; -wire [314:314] mux_1level_tapbuf_size2_294_configbus0_b; -assign mux_1level_tapbuf_size2_294_configbus0_b[314:314] = sram_blwl_blb[314:314] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_294_ (mux_1level_tapbuf_size2_294_inbus, chanx_1__0__out_89_ , mux_1level_tapbuf_size2_294_sram_blwl_out[314:314] , -mux_1level_tapbuf_size2_294_sram_blwl_outb[314:314] ); -//----- SRAM bits for MUX[294], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_314_ (mux_1level_tapbuf_size2_294_sram_blwl_out[314:314] ,mux_1level_tapbuf_size2_294_sram_blwl_out[314:314] ,mux_1level_tapbuf_size2_294_sram_blwl_outb[314:314] ,mux_1level_tapbuf_size2_294_configbus0[314:314], mux_1level_tapbuf_size2_294_configbus1[314:314] , mux_1level_tapbuf_size2_294_configbus0_b[314:314] ); -wire [0:1] mux_1level_tapbuf_size2_295_inbus; -assign mux_1level_tapbuf_size2_295_inbus[0] = grid_1__1__pin_0__2__46_; -assign mux_1level_tapbuf_size2_295_inbus[1] = chany_1__1__in_11_ ; -wire [315:315] mux_1level_tapbuf_size2_295_configbus0; -wire [315:315] mux_1level_tapbuf_size2_295_configbus1; -wire [315:315] mux_1level_tapbuf_size2_295_sram_blwl_out ; -wire [315:315] mux_1level_tapbuf_size2_295_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_295_configbus0[315:315] = sram_blwl_bl[315:315] ; -assign mux_1level_tapbuf_size2_295_configbus1[315:315] = sram_blwl_wl[315:315] ; -wire [315:315] mux_1level_tapbuf_size2_295_configbus0_b; -assign mux_1level_tapbuf_size2_295_configbus0_b[315:315] = sram_blwl_blb[315:315] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_295_ (mux_1level_tapbuf_size2_295_inbus, chanx_1__0__out_91_ , mux_1level_tapbuf_size2_295_sram_blwl_out[315:315] , -mux_1level_tapbuf_size2_295_sram_blwl_outb[315:315] ); -//----- SRAM bits for MUX[295], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_315_ (mux_1level_tapbuf_size2_295_sram_blwl_out[315:315] ,mux_1level_tapbuf_size2_295_sram_blwl_out[315:315] ,mux_1level_tapbuf_size2_295_sram_blwl_outb[315:315] ,mux_1level_tapbuf_size2_295_configbus0[315:315], mux_1level_tapbuf_size2_295_configbus1[315:315] , mux_1level_tapbuf_size2_295_configbus0_b[315:315] ); -wire [0:1] mux_1level_tapbuf_size2_296_inbus; -assign mux_1level_tapbuf_size2_296_inbus[0] = grid_1__1__pin_0__2__46_; -assign mux_1level_tapbuf_size2_296_inbus[1] = chany_1__1__in_9_ ; -wire [316:316] mux_1level_tapbuf_size2_296_configbus0; -wire [316:316] mux_1level_tapbuf_size2_296_configbus1; -wire [316:316] mux_1level_tapbuf_size2_296_sram_blwl_out ; -wire [316:316] mux_1level_tapbuf_size2_296_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_296_configbus0[316:316] = sram_blwl_bl[316:316] ; -assign mux_1level_tapbuf_size2_296_configbus1[316:316] = sram_blwl_wl[316:316] ; -wire [316:316] mux_1level_tapbuf_size2_296_configbus0_b; -assign mux_1level_tapbuf_size2_296_configbus0_b[316:316] = sram_blwl_blb[316:316] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_296_ (mux_1level_tapbuf_size2_296_inbus, chanx_1__0__out_93_ , mux_1level_tapbuf_size2_296_sram_blwl_out[316:316] , -mux_1level_tapbuf_size2_296_sram_blwl_outb[316:316] ); -//----- SRAM bits for MUX[296], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_316_ (mux_1level_tapbuf_size2_296_sram_blwl_out[316:316] ,mux_1level_tapbuf_size2_296_sram_blwl_out[316:316] ,mux_1level_tapbuf_size2_296_sram_blwl_outb[316:316] ,mux_1level_tapbuf_size2_296_configbus0[316:316], mux_1level_tapbuf_size2_296_configbus1[316:316] , mux_1level_tapbuf_size2_296_configbus0_b[316:316] ); -wire [0:1] mux_1level_tapbuf_size2_297_inbus; -assign mux_1level_tapbuf_size2_297_inbus[0] = grid_1__1__pin_0__2__46_; -assign mux_1level_tapbuf_size2_297_inbus[1] = chany_1__1__in_7_ ; -wire [317:317] mux_1level_tapbuf_size2_297_configbus0; -wire [317:317] mux_1level_tapbuf_size2_297_configbus1; -wire [317:317] mux_1level_tapbuf_size2_297_sram_blwl_out ; -wire [317:317] mux_1level_tapbuf_size2_297_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_297_configbus0[317:317] = sram_blwl_bl[317:317] ; -assign mux_1level_tapbuf_size2_297_configbus1[317:317] = sram_blwl_wl[317:317] ; -wire [317:317] mux_1level_tapbuf_size2_297_configbus0_b; -assign mux_1level_tapbuf_size2_297_configbus0_b[317:317] = sram_blwl_blb[317:317] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_297_ (mux_1level_tapbuf_size2_297_inbus, chanx_1__0__out_95_ , mux_1level_tapbuf_size2_297_sram_blwl_out[317:317] , -mux_1level_tapbuf_size2_297_sram_blwl_outb[317:317] ); -//----- SRAM bits for MUX[297], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_317_ (mux_1level_tapbuf_size2_297_sram_blwl_out[317:317] ,mux_1level_tapbuf_size2_297_sram_blwl_out[317:317] ,mux_1level_tapbuf_size2_297_sram_blwl_outb[317:317] ,mux_1level_tapbuf_size2_297_configbus0[317:317], mux_1level_tapbuf_size2_297_configbus1[317:317] , mux_1level_tapbuf_size2_297_configbus0_b[317:317] ); -wire [0:1] mux_1level_tapbuf_size2_298_inbus; -assign mux_1level_tapbuf_size2_298_inbus[0] = grid_1__1__pin_0__2__46_; -assign mux_1level_tapbuf_size2_298_inbus[1] = chany_1__1__in_5_ ; -wire [318:318] mux_1level_tapbuf_size2_298_configbus0; -wire [318:318] mux_1level_tapbuf_size2_298_configbus1; -wire [318:318] mux_1level_tapbuf_size2_298_sram_blwl_out ; -wire [318:318] mux_1level_tapbuf_size2_298_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_298_configbus0[318:318] = sram_blwl_bl[318:318] ; -assign mux_1level_tapbuf_size2_298_configbus1[318:318] = sram_blwl_wl[318:318] ; -wire [318:318] mux_1level_tapbuf_size2_298_configbus0_b; -assign mux_1level_tapbuf_size2_298_configbus0_b[318:318] = sram_blwl_blb[318:318] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_298_ (mux_1level_tapbuf_size2_298_inbus, chanx_1__0__out_97_ , mux_1level_tapbuf_size2_298_sram_blwl_out[318:318] , -mux_1level_tapbuf_size2_298_sram_blwl_outb[318:318] ); -//----- SRAM bits for MUX[298], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_318_ (mux_1level_tapbuf_size2_298_sram_blwl_out[318:318] ,mux_1level_tapbuf_size2_298_sram_blwl_out[318:318] ,mux_1level_tapbuf_size2_298_sram_blwl_outb[318:318] ,mux_1level_tapbuf_size2_298_configbus0[318:318], mux_1level_tapbuf_size2_298_configbus1[318:318] , mux_1level_tapbuf_size2_298_configbus0_b[318:318] ); -wire [0:1] mux_1level_tapbuf_size2_299_inbus; -assign mux_1level_tapbuf_size2_299_inbus[0] = grid_1__1__pin_0__2__46_; -assign mux_1level_tapbuf_size2_299_inbus[1] = chany_1__1__in_3_ ; -wire [319:319] mux_1level_tapbuf_size2_299_configbus0; -wire [319:319] mux_1level_tapbuf_size2_299_configbus1; -wire [319:319] mux_1level_tapbuf_size2_299_sram_blwl_out ; -wire [319:319] mux_1level_tapbuf_size2_299_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_299_configbus0[319:319] = sram_blwl_bl[319:319] ; -assign mux_1level_tapbuf_size2_299_configbus1[319:319] = sram_blwl_wl[319:319] ; -wire [319:319] mux_1level_tapbuf_size2_299_configbus0_b; -assign mux_1level_tapbuf_size2_299_configbus0_b[319:319] = sram_blwl_blb[319:319] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_299_ (mux_1level_tapbuf_size2_299_inbus, chanx_1__0__out_99_ , mux_1level_tapbuf_size2_299_sram_blwl_out[319:319] , -mux_1level_tapbuf_size2_299_sram_blwl_outb[319:319] ); -//----- SRAM bits for MUX[299], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_319_ (mux_1level_tapbuf_size2_299_sram_blwl_out[319:319] ,mux_1level_tapbuf_size2_299_sram_blwl_out[319:319] ,mux_1level_tapbuf_size2_299_sram_blwl_outb[319:319] ,mux_1level_tapbuf_size2_299_configbus0[319:319], mux_1level_tapbuf_size2_299_configbus1[319:319] , mux_1level_tapbuf_size2_299_configbus0_b[319:319] ); -endmodule -//----- END Verilog Module of Switch Box[1][0] ----- - diff --git a/examples/verilog_test_example_2/routing/sb_1_1.v b/examples/verilog_test_example_2/routing/sb_1_1.v deleted file mode 100644 index 55c37da01..000000000 --- a/examples/verilog_test_example_2/routing/sb_1_1.v +++ /dev/null @@ -1,1987 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Switch Block [1][1] in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog Module of Switch Box[1][1] ----- -module sb_1__1_ ( - -//----- BEGIN Global ports ----- -input [0:0] zin, -input [0:0] clk, -input [0:0] Reset, -input [0:0] Set -//----- END Global ports ----- -, -//----- Inputs/outputs of top side ----- -//----- Inputs/outputs of right side ----- -//----- Inputs/outputs of bottom side ----- - input chany_1__1__in_0_, - output chany_1__1__out_1_, - input chany_1__1__in_2_, - output chany_1__1__out_3_, - input chany_1__1__in_4_, - output chany_1__1__out_5_, - input chany_1__1__in_6_, - output chany_1__1__out_7_, - input chany_1__1__in_8_, - output chany_1__1__out_9_, - input chany_1__1__in_10_, - output chany_1__1__out_11_, - input chany_1__1__in_12_, - output chany_1__1__out_13_, - input chany_1__1__in_14_, - output chany_1__1__out_15_, - input chany_1__1__in_16_, - output chany_1__1__out_17_, - input chany_1__1__in_18_, - output chany_1__1__out_19_, - input chany_1__1__in_20_, - output chany_1__1__out_21_, - input chany_1__1__in_22_, - output chany_1__1__out_23_, - input chany_1__1__in_24_, - output chany_1__1__out_25_, - input chany_1__1__in_26_, - output chany_1__1__out_27_, - input chany_1__1__in_28_, - output chany_1__1__out_29_, - input chany_1__1__in_30_, - output chany_1__1__out_31_, - input chany_1__1__in_32_, - output chany_1__1__out_33_, - input chany_1__1__in_34_, - output chany_1__1__out_35_, - input chany_1__1__in_36_, - output chany_1__1__out_37_, - input chany_1__1__in_38_, - output chany_1__1__out_39_, - input chany_1__1__in_40_, - output chany_1__1__out_41_, - input chany_1__1__in_42_, - output chany_1__1__out_43_, - input chany_1__1__in_44_, - output chany_1__1__out_45_, - input chany_1__1__in_46_, - output chany_1__1__out_47_, - input chany_1__1__in_48_, - output chany_1__1__out_49_, - input chany_1__1__in_50_, - output chany_1__1__out_51_, - input chany_1__1__in_52_, - output chany_1__1__out_53_, - input chany_1__1__in_54_, - output chany_1__1__out_55_, - input chany_1__1__in_56_, - output chany_1__1__out_57_, - input chany_1__1__in_58_, - output chany_1__1__out_59_, - input chany_1__1__in_60_, - output chany_1__1__out_61_, - input chany_1__1__in_62_, - output chany_1__1__out_63_, - input chany_1__1__in_64_, - output chany_1__1__out_65_, - input chany_1__1__in_66_, - output chany_1__1__out_67_, - input chany_1__1__in_68_, - output chany_1__1__out_69_, - input chany_1__1__in_70_, - output chany_1__1__out_71_, - input chany_1__1__in_72_, - output chany_1__1__out_73_, - input chany_1__1__in_74_, - output chany_1__1__out_75_, - input chany_1__1__in_76_, - output chany_1__1__out_77_, - input chany_1__1__in_78_, - output chany_1__1__out_79_, - input chany_1__1__in_80_, - output chany_1__1__out_81_, - input chany_1__1__in_82_, - output chany_1__1__out_83_, - input chany_1__1__in_84_, - output chany_1__1__out_85_, - input chany_1__1__in_86_, - output chany_1__1__out_87_, - input chany_1__1__in_88_, - output chany_1__1__out_89_, - input chany_1__1__in_90_, - output chany_1__1__out_91_, - input chany_1__1__in_92_, - output chany_1__1__out_93_, - input chany_1__1__in_94_, - output chany_1__1__out_95_, - input chany_1__1__in_96_, - output chany_1__1__out_97_, - input chany_1__1__in_98_, - output chany_1__1__out_99_, -input grid_2__1__pin_0__3__1_, -input grid_2__1__pin_0__3__3_, -input grid_2__1__pin_0__3__5_, -input grid_2__1__pin_0__3__7_, -input grid_2__1__pin_0__3__9_, -input grid_2__1__pin_0__3__11_, -input grid_2__1__pin_0__3__13_, -input grid_2__1__pin_0__3__15_, -input grid_1__1__pin_0__1__41_, -input grid_1__1__pin_0__1__45_, -input grid_1__1__pin_0__1__49_, -//----- Inputs/outputs of left side ----- - input chanx_1__1__in_0_, - output chanx_1__1__out_1_, - input chanx_1__1__in_2_, - output chanx_1__1__out_3_, - input chanx_1__1__in_4_, - output chanx_1__1__out_5_, - input chanx_1__1__in_6_, - output chanx_1__1__out_7_, - input chanx_1__1__in_8_, - output chanx_1__1__out_9_, - input chanx_1__1__in_10_, - output chanx_1__1__out_11_, - input chanx_1__1__in_12_, - output chanx_1__1__out_13_, - input chanx_1__1__in_14_, - output chanx_1__1__out_15_, - input chanx_1__1__in_16_, - output chanx_1__1__out_17_, - input chanx_1__1__in_18_, - output chanx_1__1__out_19_, - input chanx_1__1__in_20_, - output chanx_1__1__out_21_, - input chanx_1__1__in_22_, - output chanx_1__1__out_23_, - input chanx_1__1__in_24_, - output chanx_1__1__out_25_, - input chanx_1__1__in_26_, - output chanx_1__1__out_27_, - input chanx_1__1__in_28_, - output chanx_1__1__out_29_, - input chanx_1__1__in_30_, - output chanx_1__1__out_31_, - input chanx_1__1__in_32_, - output chanx_1__1__out_33_, - input chanx_1__1__in_34_, - output chanx_1__1__out_35_, - input chanx_1__1__in_36_, - output chanx_1__1__out_37_, - input chanx_1__1__in_38_, - output chanx_1__1__out_39_, - input chanx_1__1__in_40_, - output chanx_1__1__out_41_, - input chanx_1__1__in_42_, - output chanx_1__1__out_43_, - input chanx_1__1__in_44_, - output chanx_1__1__out_45_, - input chanx_1__1__in_46_, - output chanx_1__1__out_47_, - input chanx_1__1__in_48_, - output chanx_1__1__out_49_, - input chanx_1__1__in_50_, - output chanx_1__1__out_51_, - input chanx_1__1__in_52_, - output chanx_1__1__out_53_, - input chanx_1__1__in_54_, - output chanx_1__1__out_55_, - input chanx_1__1__in_56_, - output chanx_1__1__out_57_, - input chanx_1__1__in_58_, - output chanx_1__1__out_59_, - input chanx_1__1__in_60_, - output chanx_1__1__out_61_, - input chanx_1__1__in_62_, - output chanx_1__1__out_63_, - input chanx_1__1__in_64_, - output chanx_1__1__out_65_, - input chanx_1__1__in_66_, - output chanx_1__1__out_67_, - input chanx_1__1__in_68_, - output chanx_1__1__out_69_, - input chanx_1__1__in_70_, - output chanx_1__1__out_71_, - input chanx_1__1__in_72_, - output chanx_1__1__out_73_, - input chanx_1__1__in_74_, - output chanx_1__1__out_75_, - input chanx_1__1__in_76_, - output chanx_1__1__out_77_, - input chanx_1__1__in_78_, - output chanx_1__1__out_79_, - input chanx_1__1__in_80_, - output chanx_1__1__out_81_, - input chanx_1__1__in_82_, - output chanx_1__1__out_83_, - input chanx_1__1__in_84_, - output chanx_1__1__out_85_, - input chanx_1__1__in_86_, - output chanx_1__1__out_87_, - input chanx_1__1__in_88_, - output chanx_1__1__out_89_, - input chanx_1__1__in_90_, - output chanx_1__1__out_91_, - input chanx_1__1__in_92_, - output chanx_1__1__out_93_, - input chanx_1__1__in_94_, - output chanx_1__1__out_95_, - input chanx_1__1__in_96_, - output chanx_1__1__out_97_, - input chanx_1__1__in_98_, - output chanx_1__1__out_99_, -input grid_1__2__pin_0__2__1_, -input grid_1__2__pin_0__2__3_, -input grid_1__2__pin_0__2__5_, -input grid_1__2__pin_0__2__7_, -input grid_1__2__pin_0__2__9_, -input grid_1__2__pin_0__2__11_, -input grid_1__2__pin_0__2__13_, -input grid_1__2__pin_0__2__15_, -input grid_1__1__pin_0__0__40_, -input grid_1__1__pin_0__0__44_, -input grid_1__1__pin_0__0__48_, -input [320:439] sram_blwl_bl , -input [320:439] sram_blwl_wl , -input [320:439] sram_blwl_blb ); -//----- top side Multiplexers ----- -//----- right side Multiplexers ----- -//----- bottom side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_300_inbus; -assign mux_1level_tapbuf_size3_300_inbus[0] = grid_1__1__pin_0__1__41_; -assign mux_1level_tapbuf_size3_300_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_300_inbus[2] = chanx_1__1__in_2_ ; -wire [320:322] mux_1level_tapbuf_size3_300_configbus0; -wire [320:322] mux_1level_tapbuf_size3_300_configbus1; -wire [320:322] mux_1level_tapbuf_size3_300_sram_blwl_out ; -wire [320:322] mux_1level_tapbuf_size3_300_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_300_configbus0[320:322] = sram_blwl_bl[320:322] ; -assign mux_1level_tapbuf_size3_300_configbus1[320:322] = sram_blwl_wl[320:322] ; -wire [320:322] mux_1level_tapbuf_size3_300_configbus0_b; -assign mux_1level_tapbuf_size3_300_configbus0_b[320:322] = sram_blwl_blb[320:322] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_300_ (mux_1level_tapbuf_size3_300_inbus, chany_1__1__out_1_ , mux_1level_tapbuf_size3_300_sram_blwl_out[320:322] , -mux_1level_tapbuf_size3_300_sram_blwl_outb[320:322] ); -//----- SRAM bits for MUX[300], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_320_ (mux_1level_tapbuf_size3_300_sram_blwl_out[320:320] ,mux_1level_tapbuf_size3_300_sram_blwl_out[320:320] ,mux_1level_tapbuf_size3_300_sram_blwl_outb[320:320] ,mux_1level_tapbuf_size3_300_configbus0[320:320], mux_1level_tapbuf_size3_300_configbus1[320:320] , mux_1level_tapbuf_size3_300_configbus0_b[320:320] ); -sram6T_blwl sram_blwl_321_ (mux_1level_tapbuf_size3_300_sram_blwl_out[321:321] ,mux_1level_tapbuf_size3_300_sram_blwl_out[321:321] ,mux_1level_tapbuf_size3_300_sram_blwl_outb[321:321] ,mux_1level_tapbuf_size3_300_configbus0[321:321], mux_1level_tapbuf_size3_300_configbus1[321:321] , mux_1level_tapbuf_size3_300_configbus0_b[321:321] ); -sram6T_blwl sram_blwl_322_ (mux_1level_tapbuf_size3_300_sram_blwl_out[322:322] ,mux_1level_tapbuf_size3_300_sram_blwl_out[322:322] ,mux_1level_tapbuf_size3_300_sram_blwl_outb[322:322] ,mux_1level_tapbuf_size3_300_configbus0[322:322], mux_1level_tapbuf_size3_300_configbus1[322:322] , mux_1level_tapbuf_size3_300_configbus0_b[322:322] ); -wire [0:2] mux_1level_tapbuf_size3_301_inbus; -assign mux_1level_tapbuf_size3_301_inbus[0] = grid_1__1__pin_0__1__41_; -assign mux_1level_tapbuf_size3_301_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_301_inbus[2] = chanx_1__1__in_4_ ; -wire [323:325] mux_1level_tapbuf_size3_301_configbus0; -wire [323:325] mux_1level_tapbuf_size3_301_configbus1; -wire [323:325] mux_1level_tapbuf_size3_301_sram_blwl_out ; -wire [323:325] mux_1level_tapbuf_size3_301_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_301_configbus0[323:325] = sram_blwl_bl[323:325] ; -assign mux_1level_tapbuf_size3_301_configbus1[323:325] = sram_blwl_wl[323:325] ; -wire [323:325] mux_1level_tapbuf_size3_301_configbus0_b; -assign mux_1level_tapbuf_size3_301_configbus0_b[323:325] = sram_blwl_blb[323:325] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_301_ (mux_1level_tapbuf_size3_301_inbus, chany_1__1__out_3_ , mux_1level_tapbuf_size3_301_sram_blwl_out[323:325] , -mux_1level_tapbuf_size3_301_sram_blwl_outb[323:325] ); -//----- SRAM bits for MUX[301], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_323_ (mux_1level_tapbuf_size3_301_sram_blwl_out[323:323] ,mux_1level_tapbuf_size3_301_sram_blwl_out[323:323] ,mux_1level_tapbuf_size3_301_sram_blwl_outb[323:323] ,mux_1level_tapbuf_size3_301_configbus0[323:323], mux_1level_tapbuf_size3_301_configbus1[323:323] , mux_1level_tapbuf_size3_301_configbus0_b[323:323] ); -sram6T_blwl sram_blwl_324_ (mux_1level_tapbuf_size3_301_sram_blwl_out[324:324] ,mux_1level_tapbuf_size3_301_sram_blwl_out[324:324] ,mux_1level_tapbuf_size3_301_sram_blwl_outb[324:324] ,mux_1level_tapbuf_size3_301_configbus0[324:324], mux_1level_tapbuf_size3_301_configbus1[324:324] , mux_1level_tapbuf_size3_301_configbus0_b[324:324] ); -sram6T_blwl sram_blwl_325_ (mux_1level_tapbuf_size3_301_sram_blwl_out[325:325] ,mux_1level_tapbuf_size3_301_sram_blwl_out[325:325] ,mux_1level_tapbuf_size3_301_sram_blwl_outb[325:325] ,mux_1level_tapbuf_size3_301_configbus0[325:325], mux_1level_tapbuf_size3_301_configbus1[325:325] , mux_1level_tapbuf_size3_301_configbus0_b[325:325] ); -wire [0:2] mux_1level_tapbuf_size3_302_inbus; -assign mux_1level_tapbuf_size3_302_inbus[0] = grid_1__1__pin_0__1__41_; -assign mux_1level_tapbuf_size3_302_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_302_inbus[2] = chanx_1__1__in_6_ ; -wire [326:328] mux_1level_tapbuf_size3_302_configbus0; -wire [326:328] mux_1level_tapbuf_size3_302_configbus1; -wire [326:328] mux_1level_tapbuf_size3_302_sram_blwl_out ; -wire [326:328] mux_1level_tapbuf_size3_302_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_302_configbus0[326:328] = sram_blwl_bl[326:328] ; -assign mux_1level_tapbuf_size3_302_configbus1[326:328] = sram_blwl_wl[326:328] ; -wire [326:328] mux_1level_tapbuf_size3_302_configbus0_b; -assign mux_1level_tapbuf_size3_302_configbus0_b[326:328] = sram_blwl_blb[326:328] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_302_ (mux_1level_tapbuf_size3_302_inbus, chany_1__1__out_5_ , mux_1level_tapbuf_size3_302_sram_blwl_out[326:328] , -mux_1level_tapbuf_size3_302_sram_blwl_outb[326:328] ); -//----- SRAM bits for MUX[302], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_326_ (mux_1level_tapbuf_size3_302_sram_blwl_out[326:326] ,mux_1level_tapbuf_size3_302_sram_blwl_out[326:326] ,mux_1level_tapbuf_size3_302_sram_blwl_outb[326:326] ,mux_1level_tapbuf_size3_302_configbus0[326:326], mux_1level_tapbuf_size3_302_configbus1[326:326] , mux_1level_tapbuf_size3_302_configbus0_b[326:326] ); -sram6T_blwl sram_blwl_327_ (mux_1level_tapbuf_size3_302_sram_blwl_out[327:327] ,mux_1level_tapbuf_size3_302_sram_blwl_out[327:327] ,mux_1level_tapbuf_size3_302_sram_blwl_outb[327:327] ,mux_1level_tapbuf_size3_302_configbus0[327:327], mux_1level_tapbuf_size3_302_configbus1[327:327] , mux_1level_tapbuf_size3_302_configbus0_b[327:327] ); -sram6T_blwl sram_blwl_328_ (mux_1level_tapbuf_size3_302_sram_blwl_out[328:328] ,mux_1level_tapbuf_size3_302_sram_blwl_out[328:328] ,mux_1level_tapbuf_size3_302_sram_blwl_outb[328:328] ,mux_1level_tapbuf_size3_302_configbus0[328:328], mux_1level_tapbuf_size3_302_configbus1[328:328] , mux_1level_tapbuf_size3_302_configbus0_b[328:328] ); -wire [0:2] mux_1level_tapbuf_size3_303_inbus; -assign mux_1level_tapbuf_size3_303_inbus[0] = grid_1__1__pin_0__1__41_; -assign mux_1level_tapbuf_size3_303_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_303_inbus[2] = chanx_1__1__in_8_ ; -wire [329:331] mux_1level_tapbuf_size3_303_configbus0; -wire [329:331] mux_1level_tapbuf_size3_303_configbus1; -wire [329:331] mux_1level_tapbuf_size3_303_sram_blwl_out ; -wire [329:331] mux_1level_tapbuf_size3_303_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_303_configbus0[329:331] = sram_blwl_bl[329:331] ; -assign mux_1level_tapbuf_size3_303_configbus1[329:331] = sram_blwl_wl[329:331] ; -wire [329:331] mux_1level_tapbuf_size3_303_configbus0_b; -assign mux_1level_tapbuf_size3_303_configbus0_b[329:331] = sram_blwl_blb[329:331] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_303_ (mux_1level_tapbuf_size3_303_inbus, chany_1__1__out_7_ , mux_1level_tapbuf_size3_303_sram_blwl_out[329:331] , -mux_1level_tapbuf_size3_303_sram_blwl_outb[329:331] ); -//----- SRAM bits for MUX[303], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_329_ (mux_1level_tapbuf_size3_303_sram_blwl_out[329:329] ,mux_1level_tapbuf_size3_303_sram_blwl_out[329:329] ,mux_1level_tapbuf_size3_303_sram_blwl_outb[329:329] ,mux_1level_tapbuf_size3_303_configbus0[329:329], mux_1level_tapbuf_size3_303_configbus1[329:329] , mux_1level_tapbuf_size3_303_configbus0_b[329:329] ); -sram6T_blwl sram_blwl_330_ (mux_1level_tapbuf_size3_303_sram_blwl_out[330:330] ,mux_1level_tapbuf_size3_303_sram_blwl_out[330:330] ,mux_1level_tapbuf_size3_303_sram_blwl_outb[330:330] ,mux_1level_tapbuf_size3_303_configbus0[330:330], mux_1level_tapbuf_size3_303_configbus1[330:330] , mux_1level_tapbuf_size3_303_configbus0_b[330:330] ); -sram6T_blwl sram_blwl_331_ (mux_1level_tapbuf_size3_303_sram_blwl_out[331:331] ,mux_1level_tapbuf_size3_303_sram_blwl_out[331:331] ,mux_1level_tapbuf_size3_303_sram_blwl_outb[331:331] ,mux_1level_tapbuf_size3_303_configbus0[331:331], mux_1level_tapbuf_size3_303_configbus1[331:331] , mux_1level_tapbuf_size3_303_configbus0_b[331:331] ); -wire [0:2] mux_1level_tapbuf_size3_304_inbus; -assign mux_1level_tapbuf_size3_304_inbus[0] = grid_1__1__pin_0__1__41_; -assign mux_1level_tapbuf_size3_304_inbus[1] = grid_2__1__pin_0__3__15_; -assign mux_1level_tapbuf_size3_304_inbus[2] = chanx_1__1__in_10_ ; -wire [332:334] mux_1level_tapbuf_size3_304_configbus0; -wire [332:334] mux_1level_tapbuf_size3_304_configbus1; -wire [332:334] mux_1level_tapbuf_size3_304_sram_blwl_out ; -wire [332:334] mux_1level_tapbuf_size3_304_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_304_configbus0[332:334] = sram_blwl_bl[332:334] ; -assign mux_1level_tapbuf_size3_304_configbus1[332:334] = sram_blwl_wl[332:334] ; -wire [332:334] mux_1level_tapbuf_size3_304_configbus0_b; -assign mux_1level_tapbuf_size3_304_configbus0_b[332:334] = sram_blwl_blb[332:334] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_304_ (mux_1level_tapbuf_size3_304_inbus, chany_1__1__out_9_ , mux_1level_tapbuf_size3_304_sram_blwl_out[332:334] , -mux_1level_tapbuf_size3_304_sram_blwl_outb[332:334] ); -//----- SRAM bits for MUX[304], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_332_ (mux_1level_tapbuf_size3_304_sram_blwl_out[332:332] ,mux_1level_tapbuf_size3_304_sram_blwl_out[332:332] ,mux_1level_tapbuf_size3_304_sram_blwl_outb[332:332] ,mux_1level_tapbuf_size3_304_configbus0[332:332], mux_1level_tapbuf_size3_304_configbus1[332:332] , mux_1level_tapbuf_size3_304_configbus0_b[332:332] ); -sram6T_blwl sram_blwl_333_ (mux_1level_tapbuf_size3_304_sram_blwl_out[333:333] ,mux_1level_tapbuf_size3_304_sram_blwl_out[333:333] ,mux_1level_tapbuf_size3_304_sram_blwl_outb[333:333] ,mux_1level_tapbuf_size3_304_configbus0[333:333], mux_1level_tapbuf_size3_304_configbus1[333:333] , mux_1level_tapbuf_size3_304_configbus0_b[333:333] ); -sram6T_blwl sram_blwl_334_ (mux_1level_tapbuf_size3_304_sram_blwl_out[334:334] ,mux_1level_tapbuf_size3_304_sram_blwl_out[334:334] ,mux_1level_tapbuf_size3_304_sram_blwl_outb[334:334] ,mux_1level_tapbuf_size3_304_configbus0[334:334], mux_1level_tapbuf_size3_304_configbus1[334:334] , mux_1level_tapbuf_size3_304_configbus0_b[334:334] ); -wire [0:1] mux_1level_tapbuf_size2_305_inbus; -assign mux_1level_tapbuf_size2_305_inbus[0] = grid_1__1__pin_0__1__45_; -assign mux_1level_tapbuf_size2_305_inbus[1] = chanx_1__1__in_12_ ; -wire [335:335] mux_1level_tapbuf_size2_305_configbus0; -wire [335:335] mux_1level_tapbuf_size2_305_configbus1; -wire [335:335] mux_1level_tapbuf_size2_305_sram_blwl_out ; -wire [335:335] mux_1level_tapbuf_size2_305_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_305_configbus0[335:335] = sram_blwl_bl[335:335] ; -assign mux_1level_tapbuf_size2_305_configbus1[335:335] = sram_blwl_wl[335:335] ; -wire [335:335] mux_1level_tapbuf_size2_305_configbus0_b; -assign mux_1level_tapbuf_size2_305_configbus0_b[335:335] = sram_blwl_blb[335:335] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_305_ (mux_1level_tapbuf_size2_305_inbus, chany_1__1__out_11_ , mux_1level_tapbuf_size2_305_sram_blwl_out[335:335] , -mux_1level_tapbuf_size2_305_sram_blwl_outb[335:335] ); -//----- SRAM bits for MUX[305], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_335_ (mux_1level_tapbuf_size2_305_sram_blwl_out[335:335] ,mux_1level_tapbuf_size2_305_sram_blwl_out[335:335] ,mux_1level_tapbuf_size2_305_sram_blwl_outb[335:335] ,mux_1level_tapbuf_size2_305_configbus0[335:335], mux_1level_tapbuf_size2_305_configbus1[335:335] , mux_1level_tapbuf_size2_305_configbus0_b[335:335] ); -wire [0:1] mux_1level_tapbuf_size2_306_inbus; -assign mux_1level_tapbuf_size2_306_inbus[0] = grid_1__1__pin_0__1__45_; -assign mux_1level_tapbuf_size2_306_inbus[1] = chanx_1__1__in_14_ ; -wire [336:336] mux_1level_tapbuf_size2_306_configbus0; -wire [336:336] mux_1level_tapbuf_size2_306_configbus1; -wire [336:336] mux_1level_tapbuf_size2_306_sram_blwl_out ; -wire [336:336] mux_1level_tapbuf_size2_306_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_306_configbus0[336:336] = sram_blwl_bl[336:336] ; -assign mux_1level_tapbuf_size2_306_configbus1[336:336] = sram_blwl_wl[336:336] ; -wire [336:336] mux_1level_tapbuf_size2_306_configbus0_b; -assign mux_1level_tapbuf_size2_306_configbus0_b[336:336] = sram_blwl_blb[336:336] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_306_ (mux_1level_tapbuf_size2_306_inbus, chany_1__1__out_13_ , mux_1level_tapbuf_size2_306_sram_blwl_out[336:336] , -mux_1level_tapbuf_size2_306_sram_blwl_outb[336:336] ); -//----- SRAM bits for MUX[306], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_336_ (mux_1level_tapbuf_size2_306_sram_blwl_out[336:336] ,mux_1level_tapbuf_size2_306_sram_blwl_out[336:336] ,mux_1level_tapbuf_size2_306_sram_blwl_outb[336:336] ,mux_1level_tapbuf_size2_306_configbus0[336:336], mux_1level_tapbuf_size2_306_configbus1[336:336] , mux_1level_tapbuf_size2_306_configbus0_b[336:336] ); -wire [0:1] mux_1level_tapbuf_size2_307_inbus; -assign mux_1level_tapbuf_size2_307_inbus[0] = grid_1__1__pin_0__1__45_; -assign mux_1level_tapbuf_size2_307_inbus[1] = chanx_1__1__in_16_ ; -wire [337:337] mux_1level_tapbuf_size2_307_configbus0; -wire [337:337] mux_1level_tapbuf_size2_307_configbus1; -wire [337:337] mux_1level_tapbuf_size2_307_sram_blwl_out ; -wire [337:337] mux_1level_tapbuf_size2_307_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_307_configbus0[337:337] = sram_blwl_bl[337:337] ; -assign mux_1level_tapbuf_size2_307_configbus1[337:337] = sram_blwl_wl[337:337] ; -wire [337:337] mux_1level_tapbuf_size2_307_configbus0_b; -assign mux_1level_tapbuf_size2_307_configbus0_b[337:337] = sram_blwl_blb[337:337] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_307_ (mux_1level_tapbuf_size2_307_inbus, chany_1__1__out_15_ , mux_1level_tapbuf_size2_307_sram_blwl_out[337:337] , -mux_1level_tapbuf_size2_307_sram_blwl_outb[337:337] ); -//----- SRAM bits for MUX[307], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_337_ (mux_1level_tapbuf_size2_307_sram_blwl_out[337:337] ,mux_1level_tapbuf_size2_307_sram_blwl_out[337:337] ,mux_1level_tapbuf_size2_307_sram_blwl_outb[337:337] ,mux_1level_tapbuf_size2_307_configbus0[337:337], mux_1level_tapbuf_size2_307_configbus1[337:337] , mux_1level_tapbuf_size2_307_configbus0_b[337:337] ); -wire [0:1] mux_1level_tapbuf_size2_308_inbus; -assign mux_1level_tapbuf_size2_308_inbus[0] = grid_1__1__pin_0__1__45_; -assign mux_1level_tapbuf_size2_308_inbus[1] = chanx_1__1__in_18_ ; -wire [338:338] mux_1level_tapbuf_size2_308_configbus0; -wire [338:338] mux_1level_tapbuf_size2_308_configbus1; -wire [338:338] mux_1level_tapbuf_size2_308_sram_blwl_out ; -wire [338:338] mux_1level_tapbuf_size2_308_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_308_configbus0[338:338] = sram_blwl_bl[338:338] ; -assign mux_1level_tapbuf_size2_308_configbus1[338:338] = sram_blwl_wl[338:338] ; -wire [338:338] mux_1level_tapbuf_size2_308_configbus0_b; -assign mux_1level_tapbuf_size2_308_configbus0_b[338:338] = sram_blwl_blb[338:338] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_308_ (mux_1level_tapbuf_size2_308_inbus, chany_1__1__out_17_ , mux_1level_tapbuf_size2_308_sram_blwl_out[338:338] , -mux_1level_tapbuf_size2_308_sram_blwl_outb[338:338] ); -//----- SRAM bits for MUX[308], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_338_ (mux_1level_tapbuf_size2_308_sram_blwl_out[338:338] ,mux_1level_tapbuf_size2_308_sram_blwl_out[338:338] ,mux_1level_tapbuf_size2_308_sram_blwl_outb[338:338] ,mux_1level_tapbuf_size2_308_configbus0[338:338], mux_1level_tapbuf_size2_308_configbus1[338:338] , mux_1level_tapbuf_size2_308_configbus0_b[338:338] ); -wire [0:1] mux_1level_tapbuf_size2_309_inbus; -assign mux_1level_tapbuf_size2_309_inbus[0] = grid_1__1__pin_0__1__45_; -assign mux_1level_tapbuf_size2_309_inbus[1] = chanx_1__1__in_20_ ; -wire [339:339] mux_1level_tapbuf_size2_309_configbus0; -wire [339:339] mux_1level_tapbuf_size2_309_configbus1; -wire [339:339] mux_1level_tapbuf_size2_309_sram_blwl_out ; -wire [339:339] mux_1level_tapbuf_size2_309_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_309_configbus0[339:339] = sram_blwl_bl[339:339] ; -assign mux_1level_tapbuf_size2_309_configbus1[339:339] = sram_blwl_wl[339:339] ; -wire [339:339] mux_1level_tapbuf_size2_309_configbus0_b; -assign mux_1level_tapbuf_size2_309_configbus0_b[339:339] = sram_blwl_blb[339:339] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_309_ (mux_1level_tapbuf_size2_309_inbus, chany_1__1__out_19_ , mux_1level_tapbuf_size2_309_sram_blwl_out[339:339] , -mux_1level_tapbuf_size2_309_sram_blwl_outb[339:339] ); -//----- SRAM bits for MUX[309], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_339_ (mux_1level_tapbuf_size2_309_sram_blwl_out[339:339] ,mux_1level_tapbuf_size2_309_sram_blwl_out[339:339] ,mux_1level_tapbuf_size2_309_sram_blwl_outb[339:339] ,mux_1level_tapbuf_size2_309_configbus0[339:339], mux_1level_tapbuf_size2_309_configbus1[339:339] , mux_1level_tapbuf_size2_309_configbus0_b[339:339] ); -wire [0:1] mux_1level_tapbuf_size2_310_inbus; -assign mux_1level_tapbuf_size2_310_inbus[0] = grid_1__1__pin_0__1__49_; -assign mux_1level_tapbuf_size2_310_inbus[1] = chanx_1__1__in_22_ ; -wire [340:340] mux_1level_tapbuf_size2_310_configbus0; -wire [340:340] mux_1level_tapbuf_size2_310_configbus1; -wire [340:340] mux_1level_tapbuf_size2_310_sram_blwl_out ; -wire [340:340] mux_1level_tapbuf_size2_310_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_310_configbus0[340:340] = sram_blwl_bl[340:340] ; -assign mux_1level_tapbuf_size2_310_configbus1[340:340] = sram_blwl_wl[340:340] ; -wire [340:340] mux_1level_tapbuf_size2_310_configbus0_b; -assign mux_1level_tapbuf_size2_310_configbus0_b[340:340] = sram_blwl_blb[340:340] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_310_ (mux_1level_tapbuf_size2_310_inbus, chany_1__1__out_21_ , mux_1level_tapbuf_size2_310_sram_blwl_out[340:340] , -mux_1level_tapbuf_size2_310_sram_blwl_outb[340:340] ); -//----- SRAM bits for MUX[310], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_340_ (mux_1level_tapbuf_size2_310_sram_blwl_out[340:340] ,mux_1level_tapbuf_size2_310_sram_blwl_out[340:340] ,mux_1level_tapbuf_size2_310_sram_blwl_outb[340:340] ,mux_1level_tapbuf_size2_310_configbus0[340:340], mux_1level_tapbuf_size2_310_configbus1[340:340] , mux_1level_tapbuf_size2_310_configbus0_b[340:340] ); -wire [0:1] mux_1level_tapbuf_size2_311_inbus; -assign mux_1level_tapbuf_size2_311_inbus[0] = grid_1__1__pin_0__1__49_; -assign mux_1level_tapbuf_size2_311_inbus[1] = chanx_1__1__in_24_ ; -wire [341:341] mux_1level_tapbuf_size2_311_configbus0; -wire [341:341] mux_1level_tapbuf_size2_311_configbus1; -wire [341:341] mux_1level_tapbuf_size2_311_sram_blwl_out ; -wire [341:341] mux_1level_tapbuf_size2_311_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_311_configbus0[341:341] = sram_blwl_bl[341:341] ; -assign mux_1level_tapbuf_size2_311_configbus1[341:341] = sram_blwl_wl[341:341] ; -wire [341:341] mux_1level_tapbuf_size2_311_configbus0_b; -assign mux_1level_tapbuf_size2_311_configbus0_b[341:341] = sram_blwl_blb[341:341] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_311_ (mux_1level_tapbuf_size2_311_inbus, chany_1__1__out_23_ , mux_1level_tapbuf_size2_311_sram_blwl_out[341:341] , -mux_1level_tapbuf_size2_311_sram_blwl_outb[341:341] ); -//----- SRAM bits for MUX[311], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_341_ (mux_1level_tapbuf_size2_311_sram_blwl_out[341:341] ,mux_1level_tapbuf_size2_311_sram_blwl_out[341:341] ,mux_1level_tapbuf_size2_311_sram_blwl_outb[341:341] ,mux_1level_tapbuf_size2_311_configbus0[341:341], mux_1level_tapbuf_size2_311_configbus1[341:341] , mux_1level_tapbuf_size2_311_configbus0_b[341:341] ); -wire [0:1] mux_1level_tapbuf_size2_312_inbus; -assign mux_1level_tapbuf_size2_312_inbus[0] = grid_1__1__pin_0__1__49_; -assign mux_1level_tapbuf_size2_312_inbus[1] = chanx_1__1__in_26_ ; -wire [342:342] mux_1level_tapbuf_size2_312_configbus0; -wire [342:342] mux_1level_tapbuf_size2_312_configbus1; -wire [342:342] mux_1level_tapbuf_size2_312_sram_blwl_out ; -wire [342:342] mux_1level_tapbuf_size2_312_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_312_configbus0[342:342] = sram_blwl_bl[342:342] ; -assign mux_1level_tapbuf_size2_312_configbus1[342:342] = sram_blwl_wl[342:342] ; -wire [342:342] mux_1level_tapbuf_size2_312_configbus0_b; -assign mux_1level_tapbuf_size2_312_configbus0_b[342:342] = sram_blwl_blb[342:342] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_312_ (mux_1level_tapbuf_size2_312_inbus, chany_1__1__out_25_ , mux_1level_tapbuf_size2_312_sram_blwl_out[342:342] , -mux_1level_tapbuf_size2_312_sram_blwl_outb[342:342] ); -//----- SRAM bits for MUX[312], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_342_ (mux_1level_tapbuf_size2_312_sram_blwl_out[342:342] ,mux_1level_tapbuf_size2_312_sram_blwl_out[342:342] ,mux_1level_tapbuf_size2_312_sram_blwl_outb[342:342] ,mux_1level_tapbuf_size2_312_configbus0[342:342], mux_1level_tapbuf_size2_312_configbus1[342:342] , mux_1level_tapbuf_size2_312_configbus0_b[342:342] ); -wire [0:1] mux_1level_tapbuf_size2_313_inbus; -assign mux_1level_tapbuf_size2_313_inbus[0] = grid_1__1__pin_0__1__49_; -assign mux_1level_tapbuf_size2_313_inbus[1] = chanx_1__1__in_28_ ; -wire [343:343] mux_1level_tapbuf_size2_313_configbus0; -wire [343:343] mux_1level_tapbuf_size2_313_configbus1; -wire [343:343] mux_1level_tapbuf_size2_313_sram_blwl_out ; -wire [343:343] mux_1level_tapbuf_size2_313_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_313_configbus0[343:343] = sram_blwl_bl[343:343] ; -assign mux_1level_tapbuf_size2_313_configbus1[343:343] = sram_blwl_wl[343:343] ; -wire [343:343] mux_1level_tapbuf_size2_313_configbus0_b; -assign mux_1level_tapbuf_size2_313_configbus0_b[343:343] = sram_blwl_blb[343:343] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_313_ (mux_1level_tapbuf_size2_313_inbus, chany_1__1__out_27_ , mux_1level_tapbuf_size2_313_sram_blwl_out[343:343] , -mux_1level_tapbuf_size2_313_sram_blwl_outb[343:343] ); -//----- SRAM bits for MUX[313], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_343_ (mux_1level_tapbuf_size2_313_sram_blwl_out[343:343] ,mux_1level_tapbuf_size2_313_sram_blwl_out[343:343] ,mux_1level_tapbuf_size2_313_sram_blwl_outb[343:343] ,mux_1level_tapbuf_size2_313_configbus0[343:343], mux_1level_tapbuf_size2_313_configbus1[343:343] , mux_1level_tapbuf_size2_313_configbus0_b[343:343] ); -wire [0:1] mux_1level_tapbuf_size2_314_inbus; -assign mux_1level_tapbuf_size2_314_inbus[0] = grid_1__1__pin_0__1__49_; -assign mux_1level_tapbuf_size2_314_inbus[1] = chanx_1__1__in_30_ ; -wire [344:344] mux_1level_tapbuf_size2_314_configbus0; -wire [344:344] mux_1level_tapbuf_size2_314_configbus1; -wire [344:344] mux_1level_tapbuf_size2_314_sram_blwl_out ; -wire [344:344] mux_1level_tapbuf_size2_314_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_314_configbus0[344:344] = sram_blwl_bl[344:344] ; -assign mux_1level_tapbuf_size2_314_configbus1[344:344] = sram_blwl_wl[344:344] ; -wire [344:344] mux_1level_tapbuf_size2_314_configbus0_b; -assign mux_1level_tapbuf_size2_314_configbus0_b[344:344] = sram_blwl_blb[344:344] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_314_ (mux_1level_tapbuf_size2_314_inbus, chany_1__1__out_29_ , mux_1level_tapbuf_size2_314_sram_blwl_out[344:344] , -mux_1level_tapbuf_size2_314_sram_blwl_outb[344:344] ); -//----- SRAM bits for MUX[314], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_344_ (mux_1level_tapbuf_size2_314_sram_blwl_out[344:344] ,mux_1level_tapbuf_size2_314_sram_blwl_out[344:344] ,mux_1level_tapbuf_size2_314_sram_blwl_outb[344:344] ,mux_1level_tapbuf_size2_314_configbus0[344:344], mux_1level_tapbuf_size2_314_configbus1[344:344] , mux_1level_tapbuf_size2_314_configbus0_b[344:344] ); -wire [0:1] mux_1level_tapbuf_size2_315_inbus; -assign mux_1level_tapbuf_size2_315_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_315_inbus[1] = chanx_1__1__in_32_ ; -wire [345:345] mux_1level_tapbuf_size2_315_configbus0; -wire [345:345] mux_1level_tapbuf_size2_315_configbus1; -wire [345:345] mux_1level_tapbuf_size2_315_sram_blwl_out ; -wire [345:345] mux_1level_tapbuf_size2_315_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_315_configbus0[345:345] = sram_blwl_bl[345:345] ; -assign mux_1level_tapbuf_size2_315_configbus1[345:345] = sram_blwl_wl[345:345] ; -wire [345:345] mux_1level_tapbuf_size2_315_configbus0_b; -assign mux_1level_tapbuf_size2_315_configbus0_b[345:345] = sram_blwl_blb[345:345] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_315_ (mux_1level_tapbuf_size2_315_inbus, chany_1__1__out_31_ , mux_1level_tapbuf_size2_315_sram_blwl_out[345:345] , -mux_1level_tapbuf_size2_315_sram_blwl_outb[345:345] ); -//----- SRAM bits for MUX[315], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_345_ (mux_1level_tapbuf_size2_315_sram_blwl_out[345:345] ,mux_1level_tapbuf_size2_315_sram_blwl_out[345:345] ,mux_1level_tapbuf_size2_315_sram_blwl_outb[345:345] ,mux_1level_tapbuf_size2_315_configbus0[345:345], mux_1level_tapbuf_size2_315_configbus1[345:345] , mux_1level_tapbuf_size2_315_configbus0_b[345:345] ); -wire [0:1] mux_1level_tapbuf_size2_316_inbus; -assign mux_1level_tapbuf_size2_316_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_316_inbus[1] = chanx_1__1__in_34_ ; -wire [346:346] mux_1level_tapbuf_size2_316_configbus0; -wire [346:346] mux_1level_tapbuf_size2_316_configbus1; -wire [346:346] mux_1level_tapbuf_size2_316_sram_blwl_out ; -wire [346:346] mux_1level_tapbuf_size2_316_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_316_configbus0[346:346] = sram_blwl_bl[346:346] ; -assign mux_1level_tapbuf_size2_316_configbus1[346:346] = sram_blwl_wl[346:346] ; -wire [346:346] mux_1level_tapbuf_size2_316_configbus0_b; -assign mux_1level_tapbuf_size2_316_configbus0_b[346:346] = sram_blwl_blb[346:346] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_316_ (mux_1level_tapbuf_size2_316_inbus, chany_1__1__out_33_ , mux_1level_tapbuf_size2_316_sram_blwl_out[346:346] , -mux_1level_tapbuf_size2_316_sram_blwl_outb[346:346] ); -//----- SRAM bits for MUX[316], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_346_ (mux_1level_tapbuf_size2_316_sram_blwl_out[346:346] ,mux_1level_tapbuf_size2_316_sram_blwl_out[346:346] ,mux_1level_tapbuf_size2_316_sram_blwl_outb[346:346] ,mux_1level_tapbuf_size2_316_configbus0[346:346], mux_1level_tapbuf_size2_316_configbus1[346:346] , mux_1level_tapbuf_size2_316_configbus0_b[346:346] ); -wire [0:1] mux_1level_tapbuf_size2_317_inbus; -assign mux_1level_tapbuf_size2_317_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_317_inbus[1] = chanx_1__1__in_36_ ; -wire [347:347] mux_1level_tapbuf_size2_317_configbus0; -wire [347:347] mux_1level_tapbuf_size2_317_configbus1; -wire [347:347] mux_1level_tapbuf_size2_317_sram_blwl_out ; -wire [347:347] mux_1level_tapbuf_size2_317_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_317_configbus0[347:347] = sram_blwl_bl[347:347] ; -assign mux_1level_tapbuf_size2_317_configbus1[347:347] = sram_blwl_wl[347:347] ; -wire [347:347] mux_1level_tapbuf_size2_317_configbus0_b; -assign mux_1level_tapbuf_size2_317_configbus0_b[347:347] = sram_blwl_blb[347:347] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_317_ (mux_1level_tapbuf_size2_317_inbus, chany_1__1__out_35_ , mux_1level_tapbuf_size2_317_sram_blwl_out[347:347] , -mux_1level_tapbuf_size2_317_sram_blwl_outb[347:347] ); -//----- SRAM bits for MUX[317], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_347_ (mux_1level_tapbuf_size2_317_sram_blwl_out[347:347] ,mux_1level_tapbuf_size2_317_sram_blwl_out[347:347] ,mux_1level_tapbuf_size2_317_sram_blwl_outb[347:347] ,mux_1level_tapbuf_size2_317_configbus0[347:347], mux_1level_tapbuf_size2_317_configbus1[347:347] , mux_1level_tapbuf_size2_317_configbus0_b[347:347] ); -wire [0:1] mux_1level_tapbuf_size2_318_inbus; -assign mux_1level_tapbuf_size2_318_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_318_inbus[1] = chanx_1__1__in_38_ ; -wire [348:348] mux_1level_tapbuf_size2_318_configbus0; -wire [348:348] mux_1level_tapbuf_size2_318_configbus1; -wire [348:348] mux_1level_tapbuf_size2_318_sram_blwl_out ; -wire [348:348] mux_1level_tapbuf_size2_318_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_318_configbus0[348:348] = sram_blwl_bl[348:348] ; -assign mux_1level_tapbuf_size2_318_configbus1[348:348] = sram_blwl_wl[348:348] ; -wire [348:348] mux_1level_tapbuf_size2_318_configbus0_b; -assign mux_1level_tapbuf_size2_318_configbus0_b[348:348] = sram_blwl_blb[348:348] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_318_ (mux_1level_tapbuf_size2_318_inbus, chany_1__1__out_37_ , mux_1level_tapbuf_size2_318_sram_blwl_out[348:348] , -mux_1level_tapbuf_size2_318_sram_blwl_outb[348:348] ); -//----- SRAM bits for MUX[318], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_348_ (mux_1level_tapbuf_size2_318_sram_blwl_out[348:348] ,mux_1level_tapbuf_size2_318_sram_blwl_out[348:348] ,mux_1level_tapbuf_size2_318_sram_blwl_outb[348:348] ,mux_1level_tapbuf_size2_318_configbus0[348:348], mux_1level_tapbuf_size2_318_configbus1[348:348] , mux_1level_tapbuf_size2_318_configbus0_b[348:348] ); -wire [0:1] mux_1level_tapbuf_size2_319_inbus; -assign mux_1level_tapbuf_size2_319_inbus[0] = grid_2__1__pin_0__3__1_; -assign mux_1level_tapbuf_size2_319_inbus[1] = chanx_1__1__in_40_ ; -wire [349:349] mux_1level_tapbuf_size2_319_configbus0; -wire [349:349] mux_1level_tapbuf_size2_319_configbus1; -wire [349:349] mux_1level_tapbuf_size2_319_sram_blwl_out ; -wire [349:349] mux_1level_tapbuf_size2_319_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_319_configbus0[349:349] = sram_blwl_bl[349:349] ; -assign mux_1level_tapbuf_size2_319_configbus1[349:349] = sram_blwl_wl[349:349] ; -wire [349:349] mux_1level_tapbuf_size2_319_configbus0_b; -assign mux_1level_tapbuf_size2_319_configbus0_b[349:349] = sram_blwl_blb[349:349] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_319_ (mux_1level_tapbuf_size2_319_inbus, chany_1__1__out_39_ , mux_1level_tapbuf_size2_319_sram_blwl_out[349:349] , -mux_1level_tapbuf_size2_319_sram_blwl_outb[349:349] ); -//----- SRAM bits for MUX[319], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_349_ (mux_1level_tapbuf_size2_319_sram_blwl_out[349:349] ,mux_1level_tapbuf_size2_319_sram_blwl_out[349:349] ,mux_1level_tapbuf_size2_319_sram_blwl_outb[349:349] ,mux_1level_tapbuf_size2_319_configbus0[349:349], mux_1level_tapbuf_size2_319_configbus1[349:349] , mux_1level_tapbuf_size2_319_configbus0_b[349:349] ); -wire [0:1] mux_1level_tapbuf_size2_320_inbus; -assign mux_1level_tapbuf_size2_320_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_320_inbus[1] = chanx_1__1__in_42_ ; -wire [350:350] mux_1level_tapbuf_size2_320_configbus0; -wire [350:350] mux_1level_tapbuf_size2_320_configbus1; -wire [350:350] mux_1level_tapbuf_size2_320_sram_blwl_out ; -wire [350:350] mux_1level_tapbuf_size2_320_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_320_configbus0[350:350] = sram_blwl_bl[350:350] ; -assign mux_1level_tapbuf_size2_320_configbus1[350:350] = sram_blwl_wl[350:350] ; -wire [350:350] mux_1level_tapbuf_size2_320_configbus0_b; -assign mux_1level_tapbuf_size2_320_configbus0_b[350:350] = sram_blwl_blb[350:350] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_320_ (mux_1level_tapbuf_size2_320_inbus, chany_1__1__out_41_ , mux_1level_tapbuf_size2_320_sram_blwl_out[350:350] , -mux_1level_tapbuf_size2_320_sram_blwl_outb[350:350] ); -//----- SRAM bits for MUX[320], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_350_ (mux_1level_tapbuf_size2_320_sram_blwl_out[350:350] ,mux_1level_tapbuf_size2_320_sram_blwl_out[350:350] ,mux_1level_tapbuf_size2_320_sram_blwl_outb[350:350] ,mux_1level_tapbuf_size2_320_configbus0[350:350], mux_1level_tapbuf_size2_320_configbus1[350:350] , mux_1level_tapbuf_size2_320_configbus0_b[350:350] ); -wire [0:1] mux_1level_tapbuf_size2_321_inbus; -assign mux_1level_tapbuf_size2_321_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_321_inbus[1] = chanx_1__1__in_44_ ; -wire [351:351] mux_1level_tapbuf_size2_321_configbus0; -wire [351:351] mux_1level_tapbuf_size2_321_configbus1; -wire [351:351] mux_1level_tapbuf_size2_321_sram_blwl_out ; -wire [351:351] mux_1level_tapbuf_size2_321_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_321_configbus0[351:351] = sram_blwl_bl[351:351] ; -assign mux_1level_tapbuf_size2_321_configbus1[351:351] = sram_blwl_wl[351:351] ; -wire [351:351] mux_1level_tapbuf_size2_321_configbus0_b; -assign mux_1level_tapbuf_size2_321_configbus0_b[351:351] = sram_blwl_blb[351:351] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_321_ (mux_1level_tapbuf_size2_321_inbus, chany_1__1__out_43_ , mux_1level_tapbuf_size2_321_sram_blwl_out[351:351] , -mux_1level_tapbuf_size2_321_sram_blwl_outb[351:351] ); -//----- SRAM bits for MUX[321], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_351_ (mux_1level_tapbuf_size2_321_sram_blwl_out[351:351] ,mux_1level_tapbuf_size2_321_sram_blwl_out[351:351] ,mux_1level_tapbuf_size2_321_sram_blwl_outb[351:351] ,mux_1level_tapbuf_size2_321_configbus0[351:351], mux_1level_tapbuf_size2_321_configbus1[351:351] , mux_1level_tapbuf_size2_321_configbus0_b[351:351] ); -wire [0:1] mux_1level_tapbuf_size2_322_inbus; -assign mux_1level_tapbuf_size2_322_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_322_inbus[1] = chanx_1__1__in_46_ ; -wire [352:352] mux_1level_tapbuf_size2_322_configbus0; -wire [352:352] mux_1level_tapbuf_size2_322_configbus1; -wire [352:352] mux_1level_tapbuf_size2_322_sram_blwl_out ; -wire [352:352] mux_1level_tapbuf_size2_322_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_322_configbus0[352:352] = sram_blwl_bl[352:352] ; -assign mux_1level_tapbuf_size2_322_configbus1[352:352] = sram_blwl_wl[352:352] ; -wire [352:352] mux_1level_tapbuf_size2_322_configbus0_b; -assign mux_1level_tapbuf_size2_322_configbus0_b[352:352] = sram_blwl_blb[352:352] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_322_ (mux_1level_tapbuf_size2_322_inbus, chany_1__1__out_45_ , mux_1level_tapbuf_size2_322_sram_blwl_out[352:352] , -mux_1level_tapbuf_size2_322_sram_blwl_outb[352:352] ); -//----- SRAM bits for MUX[322], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_352_ (mux_1level_tapbuf_size2_322_sram_blwl_out[352:352] ,mux_1level_tapbuf_size2_322_sram_blwl_out[352:352] ,mux_1level_tapbuf_size2_322_sram_blwl_outb[352:352] ,mux_1level_tapbuf_size2_322_configbus0[352:352], mux_1level_tapbuf_size2_322_configbus1[352:352] , mux_1level_tapbuf_size2_322_configbus0_b[352:352] ); -wire [0:1] mux_1level_tapbuf_size2_323_inbus; -assign mux_1level_tapbuf_size2_323_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_323_inbus[1] = chanx_1__1__in_48_ ; -wire [353:353] mux_1level_tapbuf_size2_323_configbus0; -wire [353:353] mux_1level_tapbuf_size2_323_configbus1; -wire [353:353] mux_1level_tapbuf_size2_323_sram_blwl_out ; -wire [353:353] mux_1level_tapbuf_size2_323_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_323_configbus0[353:353] = sram_blwl_bl[353:353] ; -assign mux_1level_tapbuf_size2_323_configbus1[353:353] = sram_blwl_wl[353:353] ; -wire [353:353] mux_1level_tapbuf_size2_323_configbus0_b; -assign mux_1level_tapbuf_size2_323_configbus0_b[353:353] = sram_blwl_blb[353:353] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_323_ (mux_1level_tapbuf_size2_323_inbus, chany_1__1__out_47_ , mux_1level_tapbuf_size2_323_sram_blwl_out[353:353] , -mux_1level_tapbuf_size2_323_sram_blwl_outb[353:353] ); -//----- SRAM bits for MUX[323], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_353_ (mux_1level_tapbuf_size2_323_sram_blwl_out[353:353] ,mux_1level_tapbuf_size2_323_sram_blwl_out[353:353] ,mux_1level_tapbuf_size2_323_sram_blwl_outb[353:353] ,mux_1level_tapbuf_size2_323_configbus0[353:353], mux_1level_tapbuf_size2_323_configbus1[353:353] , mux_1level_tapbuf_size2_323_configbus0_b[353:353] ); -wire [0:1] mux_1level_tapbuf_size2_324_inbus; -assign mux_1level_tapbuf_size2_324_inbus[0] = grid_2__1__pin_0__3__3_; -assign mux_1level_tapbuf_size2_324_inbus[1] = chanx_1__1__in_50_ ; -wire [354:354] mux_1level_tapbuf_size2_324_configbus0; -wire [354:354] mux_1level_tapbuf_size2_324_configbus1; -wire [354:354] mux_1level_tapbuf_size2_324_sram_blwl_out ; -wire [354:354] mux_1level_tapbuf_size2_324_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_324_configbus0[354:354] = sram_blwl_bl[354:354] ; -assign mux_1level_tapbuf_size2_324_configbus1[354:354] = sram_blwl_wl[354:354] ; -wire [354:354] mux_1level_tapbuf_size2_324_configbus0_b; -assign mux_1level_tapbuf_size2_324_configbus0_b[354:354] = sram_blwl_blb[354:354] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_324_ (mux_1level_tapbuf_size2_324_inbus, chany_1__1__out_49_ , mux_1level_tapbuf_size2_324_sram_blwl_out[354:354] , -mux_1level_tapbuf_size2_324_sram_blwl_outb[354:354] ); -//----- SRAM bits for MUX[324], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_354_ (mux_1level_tapbuf_size2_324_sram_blwl_out[354:354] ,mux_1level_tapbuf_size2_324_sram_blwl_out[354:354] ,mux_1level_tapbuf_size2_324_sram_blwl_outb[354:354] ,mux_1level_tapbuf_size2_324_configbus0[354:354], mux_1level_tapbuf_size2_324_configbus1[354:354] , mux_1level_tapbuf_size2_324_configbus0_b[354:354] ); -wire [0:1] mux_1level_tapbuf_size2_325_inbus; -assign mux_1level_tapbuf_size2_325_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_325_inbus[1] = chanx_1__1__in_52_ ; -wire [355:355] mux_1level_tapbuf_size2_325_configbus0; -wire [355:355] mux_1level_tapbuf_size2_325_configbus1; -wire [355:355] mux_1level_tapbuf_size2_325_sram_blwl_out ; -wire [355:355] mux_1level_tapbuf_size2_325_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_325_configbus0[355:355] = sram_blwl_bl[355:355] ; -assign mux_1level_tapbuf_size2_325_configbus1[355:355] = sram_blwl_wl[355:355] ; -wire [355:355] mux_1level_tapbuf_size2_325_configbus0_b; -assign mux_1level_tapbuf_size2_325_configbus0_b[355:355] = sram_blwl_blb[355:355] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_325_ (mux_1level_tapbuf_size2_325_inbus, chany_1__1__out_51_ , mux_1level_tapbuf_size2_325_sram_blwl_out[355:355] , -mux_1level_tapbuf_size2_325_sram_blwl_outb[355:355] ); -//----- SRAM bits for MUX[325], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_355_ (mux_1level_tapbuf_size2_325_sram_blwl_out[355:355] ,mux_1level_tapbuf_size2_325_sram_blwl_out[355:355] ,mux_1level_tapbuf_size2_325_sram_blwl_outb[355:355] ,mux_1level_tapbuf_size2_325_configbus0[355:355], mux_1level_tapbuf_size2_325_configbus1[355:355] , mux_1level_tapbuf_size2_325_configbus0_b[355:355] ); -wire [0:1] mux_1level_tapbuf_size2_326_inbus; -assign mux_1level_tapbuf_size2_326_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_326_inbus[1] = chanx_1__1__in_54_ ; -wire [356:356] mux_1level_tapbuf_size2_326_configbus0; -wire [356:356] mux_1level_tapbuf_size2_326_configbus1; -wire [356:356] mux_1level_tapbuf_size2_326_sram_blwl_out ; -wire [356:356] mux_1level_tapbuf_size2_326_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_326_configbus0[356:356] = sram_blwl_bl[356:356] ; -assign mux_1level_tapbuf_size2_326_configbus1[356:356] = sram_blwl_wl[356:356] ; -wire [356:356] mux_1level_tapbuf_size2_326_configbus0_b; -assign mux_1level_tapbuf_size2_326_configbus0_b[356:356] = sram_blwl_blb[356:356] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_326_ (mux_1level_tapbuf_size2_326_inbus, chany_1__1__out_53_ , mux_1level_tapbuf_size2_326_sram_blwl_out[356:356] , -mux_1level_tapbuf_size2_326_sram_blwl_outb[356:356] ); -//----- SRAM bits for MUX[326], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_356_ (mux_1level_tapbuf_size2_326_sram_blwl_out[356:356] ,mux_1level_tapbuf_size2_326_sram_blwl_out[356:356] ,mux_1level_tapbuf_size2_326_sram_blwl_outb[356:356] ,mux_1level_tapbuf_size2_326_configbus0[356:356], mux_1level_tapbuf_size2_326_configbus1[356:356] , mux_1level_tapbuf_size2_326_configbus0_b[356:356] ); -wire [0:1] mux_1level_tapbuf_size2_327_inbus; -assign mux_1level_tapbuf_size2_327_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_327_inbus[1] = chanx_1__1__in_56_ ; -wire [357:357] mux_1level_tapbuf_size2_327_configbus0; -wire [357:357] mux_1level_tapbuf_size2_327_configbus1; -wire [357:357] mux_1level_tapbuf_size2_327_sram_blwl_out ; -wire [357:357] mux_1level_tapbuf_size2_327_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_327_configbus0[357:357] = sram_blwl_bl[357:357] ; -assign mux_1level_tapbuf_size2_327_configbus1[357:357] = sram_blwl_wl[357:357] ; -wire [357:357] mux_1level_tapbuf_size2_327_configbus0_b; -assign mux_1level_tapbuf_size2_327_configbus0_b[357:357] = sram_blwl_blb[357:357] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_327_ (mux_1level_tapbuf_size2_327_inbus, chany_1__1__out_55_ , mux_1level_tapbuf_size2_327_sram_blwl_out[357:357] , -mux_1level_tapbuf_size2_327_sram_blwl_outb[357:357] ); -//----- SRAM bits for MUX[327], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_357_ (mux_1level_tapbuf_size2_327_sram_blwl_out[357:357] ,mux_1level_tapbuf_size2_327_sram_blwl_out[357:357] ,mux_1level_tapbuf_size2_327_sram_blwl_outb[357:357] ,mux_1level_tapbuf_size2_327_configbus0[357:357], mux_1level_tapbuf_size2_327_configbus1[357:357] , mux_1level_tapbuf_size2_327_configbus0_b[357:357] ); -wire [0:1] mux_1level_tapbuf_size2_328_inbus; -assign mux_1level_tapbuf_size2_328_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_328_inbus[1] = chanx_1__1__in_58_ ; -wire [358:358] mux_1level_tapbuf_size2_328_configbus0; -wire [358:358] mux_1level_tapbuf_size2_328_configbus1; -wire [358:358] mux_1level_tapbuf_size2_328_sram_blwl_out ; -wire [358:358] mux_1level_tapbuf_size2_328_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_328_configbus0[358:358] = sram_blwl_bl[358:358] ; -assign mux_1level_tapbuf_size2_328_configbus1[358:358] = sram_blwl_wl[358:358] ; -wire [358:358] mux_1level_tapbuf_size2_328_configbus0_b; -assign mux_1level_tapbuf_size2_328_configbus0_b[358:358] = sram_blwl_blb[358:358] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_328_ (mux_1level_tapbuf_size2_328_inbus, chany_1__1__out_57_ , mux_1level_tapbuf_size2_328_sram_blwl_out[358:358] , -mux_1level_tapbuf_size2_328_sram_blwl_outb[358:358] ); -//----- SRAM bits for MUX[328], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_358_ (mux_1level_tapbuf_size2_328_sram_blwl_out[358:358] ,mux_1level_tapbuf_size2_328_sram_blwl_out[358:358] ,mux_1level_tapbuf_size2_328_sram_blwl_outb[358:358] ,mux_1level_tapbuf_size2_328_configbus0[358:358], mux_1level_tapbuf_size2_328_configbus1[358:358] , mux_1level_tapbuf_size2_328_configbus0_b[358:358] ); -wire [0:1] mux_1level_tapbuf_size2_329_inbus; -assign mux_1level_tapbuf_size2_329_inbus[0] = grid_2__1__pin_0__3__5_; -assign mux_1level_tapbuf_size2_329_inbus[1] = chanx_1__1__in_60_ ; -wire [359:359] mux_1level_tapbuf_size2_329_configbus0; -wire [359:359] mux_1level_tapbuf_size2_329_configbus1; -wire [359:359] mux_1level_tapbuf_size2_329_sram_blwl_out ; -wire [359:359] mux_1level_tapbuf_size2_329_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_329_configbus0[359:359] = sram_blwl_bl[359:359] ; -assign mux_1level_tapbuf_size2_329_configbus1[359:359] = sram_blwl_wl[359:359] ; -wire [359:359] mux_1level_tapbuf_size2_329_configbus0_b; -assign mux_1level_tapbuf_size2_329_configbus0_b[359:359] = sram_blwl_blb[359:359] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_329_ (mux_1level_tapbuf_size2_329_inbus, chany_1__1__out_59_ , mux_1level_tapbuf_size2_329_sram_blwl_out[359:359] , -mux_1level_tapbuf_size2_329_sram_blwl_outb[359:359] ); -//----- SRAM bits for MUX[329], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_359_ (mux_1level_tapbuf_size2_329_sram_blwl_out[359:359] ,mux_1level_tapbuf_size2_329_sram_blwl_out[359:359] ,mux_1level_tapbuf_size2_329_sram_blwl_outb[359:359] ,mux_1level_tapbuf_size2_329_configbus0[359:359], mux_1level_tapbuf_size2_329_configbus1[359:359] , mux_1level_tapbuf_size2_329_configbus0_b[359:359] ); -wire [0:1] mux_1level_tapbuf_size2_330_inbus; -assign mux_1level_tapbuf_size2_330_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_330_inbus[1] = chanx_1__1__in_62_ ; -wire [360:360] mux_1level_tapbuf_size2_330_configbus0; -wire [360:360] mux_1level_tapbuf_size2_330_configbus1; -wire [360:360] mux_1level_tapbuf_size2_330_sram_blwl_out ; -wire [360:360] mux_1level_tapbuf_size2_330_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_330_configbus0[360:360] = sram_blwl_bl[360:360] ; -assign mux_1level_tapbuf_size2_330_configbus1[360:360] = sram_blwl_wl[360:360] ; -wire [360:360] mux_1level_tapbuf_size2_330_configbus0_b; -assign mux_1level_tapbuf_size2_330_configbus0_b[360:360] = sram_blwl_blb[360:360] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_330_ (mux_1level_tapbuf_size2_330_inbus, chany_1__1__out_61_ , mux_1level_tapbuf_size2_330_sram_blwl_out[360:360] , -mux_1level_tapbuf_size2_330_sram_blwl_outb[360:360] ); -//----- SRAM bits for MUX[330], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_360_ (mux_1level_tapbuf_size2_330_sram_blwl_out[360:360] ,mux_1level_tapbuf_size2_330_sram_blwl_out[360:360] ,mux_1level_tapbuf_size2_330_sram_blwl_outb[360:360] ,mux_1level_tapbuf_size2_330_configbus0[360:360], mux_1level_tapbuf_size2_330_configbus1[360:360] , mux_1level_tapbuf_size2_330_configbus0_b[360:360] ); -wire [0:1] mux_1level_tapbuf_size2_331_inbus; -assign mux_1level_tapbuf_size2_331_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_331_inbus[1] = chanx_1__1__in_64_ ; -wire [361:361] mux_1level_tapbuf_size2_331_configbus0; -wire [361:361] mux_1level_tapbuf_size2_331_configbus1; -wire [361:361] mux_1level_tapbuf_size2_331_sram_blwl_out ; -wire [361:361] mux_1level_tapbuf_size2_331_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_331_configbus0[361:361] = sram_blwl_bl[361:361] ; -assign mux_1level_tapbuf_size2_331_configbus1[361:361] = sram_blwl_wl[361:361] ; -wire [361:361] mux_1level_tapbuf_size2_331_configbus0_b; -assign mux_1level_tapbuf_size2_331_configbus0_b[361:361] = sram_blwl_blb[361:361] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_331_ (mux_1level_tapbuf_size2_331_inbus, chany_1__1__out_63_ , mux_1level_tapbuf_size2_331_sram_blwl_out[361:361] , -mux_1level_tapbuf_size2_331_sram_blwl_outb[361:361] ); -//----- SRAM bits for MUX[331], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_361_ (mux_1level_tapbuf_size2_331_sram_blwl_out[361:361] ,mux_1level_tapbuf_size2_331_sram_blwl_out[361:361] ,mux_1level_tapbuf_size2_331_sram_blwl_outb[361:361] ,mux_1level_tapbuf_size2_331_configbus0[361:361], mux_1level_tapbuf_size2_331_configbus1[361:361] , mux_1level_tapbuf_size2_331_configbus0_b[361:361] ); -wire [0:1] mux_1level_tapbuf_size2_332_inbus; -assign mux_1level_tapbuf_size2_332_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_332_inbus[1] = chanx_1__1__in_66_ ; -wire [362:362] mux_1level_tapbuf_size2_332_configbus0; -wire [362:362] mux_1level_tapbuf_size2_332_configbus1; -wire [362:362] mux_1level_tapbuf_size2_332_sram_blwl_out ; -wire [362:362] mux_1level_tapbuf_size2_332_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_332_configbus0[362:362] = sram_blwl_bl[362:362] ; -assign mux_1level_tapbuf_size2_332_configbus1[362:362] = sram_blwl_wl[362:362] ; -wire [362:362] mux_1level_tapbuf_size2_332_configbus0_b; -assign mux_1level_tapbuf_size2_332_configbus0_b[362:362] = sram_blwl_blb[362:362] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_332_ (mux_1level_tapbuf_size2_332_inbus, chany_1__1__out_65_ , mux_1level_tapbuf_size2_332_sram_blwl_out[362:362] , -mux_1level_tapbuf_size2_332_sram_blwl_outb[362:362] ); -//----- SRAM bits for MUX[332], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_362_ (mux_1level_tapbuf_size2_332_sram_blwl_out[362:362] ,mux_1level_tapbuf_size2_332_sram_blwl_out[362:362] ,mux_1level_tapbuf_size2_332_sram_blwl_outb[362:362] ,mux_1level_tapbuf_size2_332_configbus0[362:362], mux_1level_tapbuf_size2_332_configbus1[362:362] , mux_1level_tapbuf_size2_332_configbus0_b[362:362] ); -wire [0:1] mux_1level_tapbuf_size2_333_inbus; -assign mux_1level_tapbuf_size2_333_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_333_inbus[1] = chanx_1__1__in_68_ ; -wire [363:363] mux_1level_tapbuf_size2_333_configbus0; -wire [363:363] mux_1level_tapbuf_size2_333_configbus1; -wire [363:363] mux_1level_tapbuf_size2_333_sram_blwl_out ; -wire [363:363] mux_1level_tapbuf_size2_333_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_333_configbus0[363:363] = sram_blwl_bl[363:363] ; -assign mux_1level_tapbuf_size2_333_configbus1[363:363] = sram_blwl_wl[363:363] ; -wire [363:363] mux_1level_tapbuf_size2_333_configbus0_b; -assign mux_1level_tapbuf_size2_333_configbus0_b[363:363] = sram_blwl_blb[363:363] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_333_ (mux_1level_tapbuf_size2_333_inbus, chany_1__1__out_67_ , mux_1level_tapbuf_size2_333_sram_blwl_out[363:363] , -mux_1level_tapbuf_size2_333_sram_blwl_outb[363:363] ); -//----- SRAM bits for MUX[333], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_363_ (mux_1level_tapbuf_size2_333_sram_blwl_out[363:363] ,mux_1level_tapbuf_size2_333_sram_blwl_out[363:363] ,mux_1level_tapbuf_size2_333_sram_blwl_outb[363:363] ,mux_1level_tapbuf_size2_333_configbus0[363:363], mux_1level_tapbuf_size2_333_configbus1[363:363] , mux_1level_tapbuf_size2_333_configbus0_b[363:363] ); -wire [0:1] mux_1level_tapbuf_size2_334_inbus; -assign mux_1level_tapbuf_size2_334_inbus[0] = grid_2__1__pin_0__3__7_; -assign mux_1level_tapbuf_size2_334_inbus[1] = chanx_1__1__in_70_ ; -wire [364:364] mux_1level_tapbuf_size2_334_configbus0; -wire [364:364] mux_1level_tapbuf_size2_334_configbus1; -wire [364:364] mux_1level_tapbuf_size2_334_sram_blwl_out ; -wire [364:364] mux_1level_tapbuf_size2_334_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_334_configbus0[364:364] = sram_blwl_bl[364:364] ; -assign mux_1level_tapbuf_size2_334_configbus1[364:364] = sram_blwl_wl[364:364] ; -wire [364:364] mux_1level_tapbuf_size2_334_configbus0_b; -assign mux_1level_tapbuf_size2_334_configbus0_b[364:364] = sram_blwl_blb[364:364] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_334_ (mux_1level_tapbuf_size2_334_inbus, chany_1__1__out_69_ , mux_1level_tapbuf_size2_334_sram_blwl_out[364:364] , -mux_1level_tapbuf_size2_334_sram_blwl_outb[364:364] ); -//----- SRAM bits for MUX[334], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_364_ (mux_1level_tapbuf_size2_334_sram_blwl_out[364:364] ,mux_1level_tapbuf_size2_334_sram_blwl_out[364:364] ,mux_1level_tapbuf_size2_334_sram_blwl_outb[364:364] ,mux_1level_tapbuf_size2_334_configbus0[364:364], mux_1level_tapbuf_size2_334_configbus1[364:364] , mux_1level_tapbuf_size2_334_configbus0_b[364:364] ); -wire [0:1] mux_1level_tapbuf_size2_335_inbus; -assign mux_1level_tapbuf_size2_335_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_335_inbus[1] = chanx_1__1__in_72_ ; -wire [365:365] mux_1level_tapbuf_size2_335_configbus0; -wire [365:365] mux_1level_tapbuf_size2_335_configbus1; -wire [365:365] mux_1level_tapbuf_size2_335_sram_blwl_out ; -wire [365:365] mux_1level_tapbuf_size2_335_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_335_configbus0[365:365] = sram_blwl_bl[365:365] ; -assign mux_1level_tapbuf_size2_335_configbus1[365:365] = sram_blwl_wl[365:365] ; -wire [365:365] mux_1level_tapbuf_size2_335_configbus0_b; -assign mux_1level_tapbuf_size2_335_configbus0_b[365:365] = sram_blwl_blb[365:365] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_335_ (mux_1level_tapbuf_size2_335_inbus, chany_1__1__out_71_ , mux_1level_tapbuf_size2_335_sram_blwl_out[365:365] , -mux_1level_tapbuf_size2_335_sram_blwl_outb[365:365] ); -//----- SRAM bits for MUX[335], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_365_ (mux_1level_tapbuf_size2_335_sram_blwl_out[365:365] ,mux_1level_tapbuf_size2_335_sram_blwl_out[365:365] ,mux_1level_tapbuf_size2_335_sram_blwl_outb[365:365] ,mux_1level_tapbuf_size2_335_configbus0[365:365], mux_1level_tapbuf_size2_335_configbus1[365:365] , mux_1level_tapbuf_size2_335_configbus0_b[365:365] ); -wire [0:1] mux_1level_tapbuf_size2_336_inbus; -assign mux_1level_tapbuf_size2_336_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_336_inbus[1] = chanx_1__1__in_74_ ; -wire [366:366] mux_1level_tapbuf_size2_336_configbus0; -wire [366:366] mux_1level_tapbuf_size2_336_configbus1; -wire [366:366] mux_1level_tapbuf_size2_336_sram_blwl_out ; -wire [366:366] mux_1level_tapbuf_size2_336_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_336_configbus0[366:366] = sram_blwl_bl[366:366] ; -assign mux_1level_tapbuf_size2_336_configbus1[366:366] = sram_blwl_wl[366:366] ; -wire [366:366] mux_1level_tapbuf_size2_336_configbus0_b; -assign mux_1level_tapbuf_size2_336_configbus0_b[366:366] = sram_blwl_blb[366:366] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_336_ (mux_1level_tapbuf_size2_336_inbus, chany_1__1__out_73_ , mux_1level_tapbuf_size2_336_sram_blwl_out[366:366] , -mux_1level_tapbuf_size2_336_sram_blwl_outb[366:366] ); -//----- SRAM bits for MUX[336], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_366_ (mux_1level_tapbuf_size2_336_sram_blwl_out[366:366] ,mux_1level_tapbuf_size2_336_sram_blwl_out[366:366] ,mux_1level_tapbuf_size2_336_sram_blwl_outb[366:366] ,mux_1level_tapbuf_size2_336_configbus0[366:366], mux_1level_tapbuf_size2_336_configbus1[366:366] , mux_1level_tapbuf_size2_336_configbus0_b[366:366] ); -wire [0:1] mux_1level_tapbuf_size2_337_inbus; -assign mux_1level_tapbuf_size2_337_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_337_inbus[1] = chanx_1__1__in_76_ ; -wire [367:367] mux_1level_tapbuf_size2_337_configbus0; -wire [367:367] mux_1level_tapbuf_size2_337_configbus1; -wire [367:367] mux_1level_tapbuf_size2_337_sram_blwl_out ; -wire [367:367] mux_1level_tapbuf_size2_337_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_337_configbus0[367:367] = sram_blwl_bl[367:367] ; -assign mux_1level_tapbuf_size2_337_configbus1[367:367] = sram_blwl_wl[367:367] ; -wire [367:367] mux_1level_tapbuf_size2_337_configbus0_b; -assign mux_1level_tapbuf_size2_337_configbus0_b[367:367] = sram_blwl_blb[367:367] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_337_ (mux_1level_tapbuf_size2_337_inbus, chany_1__1__out_75_ , mux_1level_tapbuf_size2_337_sram_blwl_out[367:367] , -mux_1level_tapbuf_size2_337_sram_blwl_outb[367:367] ); -//----- SRAM bits for MUX[337], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_367_ (mux_1level_tapbuf_size2_337_sram_blwl_out[367:367] ,mux_1level_tapbuf_size2_337_sram_blwl_out[367:367] ,mux_1level_tapbuf_size2_337_sram_blwl_outb[367:367] ,mux_1level_tapbuf_size2_337_configbus0[367:367], mux_1level_tapbuf_size2_337_configbus1[367:367] , mux_1level_tapbuf_size2_337_configbus0_b[367:367] ); -wire [0:1] mux_1level_tapbuf_size2_338_inbus; -assign mux_1level_tapbuf_size2_338_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_338_inbus[1] = chanx_1__1__in_78_ ; -wire [368:368] mux_1level_tapbuf_size2_338_configbus0; -wire [368:368] mux_1level_tapbuf_size2_338_configbus1; -wire [368:368] mux_1level_tapbuf_size2_338_sram_blwl_out ; -wire [368:368] mux_1level_tapbuf_size2_338_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_338_configbus0[368:368] = sram_blwl_bl[368:368] ; -assign mux_1level_tapbuf_size2_338_configbus1[368:368] = sram_blwl_wl[368:368] ; -wire [368:368] mux_1level_tapbuf_size2_338_configbus0_b; -assign mux_1level_tapbuf_size2_338_configbus0_b[368:368] = sram_blwl_blb[368:368] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_338_ (mux_1level_tapbuf_size2_338_inbus, chany_1__1__out_77_ , mux_1level_tapbuf_size2_338_sram_blwl_out[368:368] , -mux_1level_tapbuf_size2_338_sram_blwl_outb[368:368] ); -//----- SRAM bits for MUX[338], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_368_ (mux_1level_tapbuf_size2_338_sram_blwl_out[368:368] ,mux_1level_tapbuf_size2_338_sram_blwl_out[368:368] ,mux_1level_tapbuf_size2_338_sram_blwl_outb[368:368] ,mux_1level_tapbuf_size2_338_configbus0[368:368], mux_1level_tapbuf_size2_338_configbus1[368:368] , mux_1level_tapbuf_size2_338_configbus0_b[368:368] ); -wire [0:1] mux_1level_tapbuf_size2_339_inbus; -assign mux_1level_tapbuf_size2_339_inbus[0] = grid_2__1__pin_0__3__9_; -assign mux_1level_tapbuf_size2_339_inbus[1] = chanx_1__1__in_80_ ; -wire [369:369] mux_1level_tapbuf_size2_339_configbus0; -wire [369:369] mux_1level_tapbuf_size2_339_configbus1; -wire [369:369] mux_1level_tapbuf_size2_339_sram_blwl_out ; -wire [369:369] mux_1level_tapbuf_size2_339_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_339_configbus0[369:369] = sram_blwl_bl[369:369] ; -assign mux_1level_tapbuf_size2_339_configbus1[369:369] = sram_blwl_wl[369:369] ; -wire [369:369] mux_1level_tapbuf_size2_339_configbus0_b; -assign mux_1level_tapbuf_size2_339_configbus0_b[369:369] = sram_blwl_blb[369:369] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_339_ (mux_1level_tapbuf_size2_339_inbus, chany_1__1__out_79_ , mux_1level_tapbuf_size2_339_sram_blwl_out[369:369] , -mux_1level_tapbuf_size2_339_sram_blwl_outb[369:369] ); -//----- SRAM bits for MUX[339], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_369_ (mux_1level_tapbuf_size2_339_sram_blwl_out[369:369] ,mux_1level_tapbuf_size2_339_sram_blwl_out[369:369] ,mux_1level_tapbuf_size2_339_sram_blwl_outb[369:369] ,mux_1level_tapbuf_size2_339_configbus0[369:369], mux_1level_tapbuf_size2_339_configbus1[369:369] , mux_1level_tapbuf_size2_339_configbus0_b[369:369] ); -wire [0:1] mux_1level_tapbuf_size2_340_inbus; -assign mux_1level_tapbuf_size2_340_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_340_inbus[1] = chanx_1__1__in_82_ ; -wire [370:370] mux_1level_tapbuf_size2_340_configbus0; -wire [370:370] mux_1level_tapbuf_size2_340_configbus1; -wire [370:370] mux_1level_tapbuf_size2_340_sram_blwl_out ; -wire [370:370] mux_1level_tapbuf_size2_340_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_340_configbus0[370:370] = sram_blwl_bl[370:370] ; -assign mux_1level_tapbuf_size2_340_configbus1[370:370] = sram_blwl_wl[370:370] ; -wire [370:370] mux_1level_tapbuf_size2_340_configbus0_b; -assign mux_1level_tapbuf_size2_340_configbus0_b[370:370] = sram_blwl_blb[370:370] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_340_ (mux_1level_tapbuf_size2_340_inbus, chany_1__1__out_81_ , mux_1level_tapbuf_size2_340_sram_blwl_out[370:370] , -mux_1level_tapbuf_size2_340_sram_blwl_outb[370:370] ); -//----- SRAM bits for MUX[340], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_370_ (mux_1level_tapbuf_size2_340_sram_blwl_out[370:370] ,mux_1level_tapbuf_size2_340_sram_blwl_out[370:370] ,mux_1level_tapbuf_size2_340_sram_blwl_outb[370:370] ,mux_1level_tapbuf_size2_340_configbus0[370:370], mux_1level_tapbuf_size2_340_configbus1[370:370] , mux_1level_tapbuf_size2_340_configbus0_b[370:370] ); -wire [0:1] mux_1level_tapbuf_size2_341_inbus; -assign mux_1level_tapbuf_size2_341_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_341_inbus[1] = chanx_1__1__in_84_ ; -wire [371:371] mux_1level_tapbuf_size2_341_configbus0; -wire [371:371] mux_1level_tapbuf_size2_341_configbus1; -wire [371:371] mux_1level_tapbuf_size2_341_sram_blwl_out ; -wire [371:371] mux_1level_tapbuf_size2_341_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_341_configbus0[371:371] = sram_blwl_bl[371:371] ; -assign mux_1level_tapbuf_size2_341_configbus1[371:371] = sram_blwl_wl[371:371] ; -wire [371:371] mux_1level_tapbuf_size2_341_configbus0_b; -assign mux_1level_tapbuf_size2_341_configbus0_b[371:371] = sram_blwl_blb[371:371] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_341_ (mux_1level_tapbuf_size2_341_inbus, chany_1__1__out_83_ , mux_1level_tapbuf_size2_341_sram_blwl_out[371:371] , -mux_1level_tapbuf_size2_341_sram_blwl_outb[371:371] ); -//----- SRAM bits for MUX[341], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_371_ (mux_1level_tapbuf_size2_341_sram_blwl_out[371:371] ,mux_1level_tapbuf_size2_341_sram_blwl_out[371:371] ,mux_1level_tapbuf_size2_341_sram_blwl_outb[371:371] ,mux_1level_tapbuf_size2_341_configbus0[371:371], mux_1level_tapbuf_size2_341_configbus1[371:371] , mux_1level_tapbuf_size2_341_configbus0_b[371:371] ); -wire [0:1] mux_1level_tapbuf_size2_342_inbus; -assign mux_1level_tapbuf_size2_342_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_342_inbus[1] = chanx_1__1__in_86_ ; -wire [372:372] mux_1level_tapbuf_size2_342_configbus0; -wire [372:372] mux_1level_tapbuf_size2_342_configbus1; -wire [372:372] mux_1level_tapbuf_size2_342_sram_blwl_out ; -wire [372:372] mux_1level_tapbuf_size2_342_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_342_configbus0[372:372] = sram_blwl_bl[372:372] ; -assign mux_1level_tapbuf_size2_342_configbus1[372:372] = sram_blwl_wl[372:372] ; -wire [372:372] mux_1level_tapbuf_size2_342_configbus0_b; -assign mux_1level_tapbuf_size2_342_configbus0_b[372:372] = sram_blwl_blb[372:372] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_342_ (mux_1level_tapbuf_size2_342_inbus, chany_1__1__out_85_ , mux_1level_tapbuf_size2_342_sram_blwl_out[372:372] , -mux_1level_tapbuf_size2_342_sram_blwl_outb[372:372] ); -//----- SRAM bits for MUX[342], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_372_ (mux_1level_tapbuf_size2_342_sram_blwl_out[372:372] ,mux_1level_tapbuf_size2_342_sram_blwl_out[372:372] ,mux_1level_tapbuf_size2_342_sram_blwl_outb[372:372] ,mux_1level_tapbuf_size2_342_configbus0[372:372], mux_1level_tapbuf_size2_342_configbus1[372:372] , mux_1level_tapbuf_size2_342_configbus0_b[372:372] ); -wire [0:1] mux_1level_tapbuf_size2_343_inbus; -assign mux_1level_tapbuf_size2_343_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_343_inbus[1] = chanx_1__1__in_88_ ; -wire [373:373] mux_1level_tapbuf_size2_343_configbus0; -wire [373:373] mux_1level_tapbuf_size2_343_configbus1; -wire [373:373] mux_1level_tapbuf_size2_343_sram_blwl_out ; -wire [373:373] mux_1level_tapbuf_size2_343_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_343_configbus0[373:373] = sram_blwl_bl[373:373] ; -assign mux_1level_tapbuf_size2_343_configbus1[373:373] = sram_blwl_wl[373:373] ; -wire [373:373] mux_1level_tapbuf_size2_343_configbus0_b; -assign mux_1level_tapbuf_size2_343_configbus0_b[373:373] = sram_blwl_blb[373:373] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_343_ (mux_1level_tapbuf_size2_343_inbus, chany_1__1__out_87_ , mux_1level_tapbuf_size2_343_sram_blwl_out[373:373] , -mux_1level_tapbuf_size2_343_sram_blwl_outb[373:373] ); -//----- SRAM bits for MUX[343], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_373_ (mux_1level_tapbuf_size2_343_sram_blwl_out[373:373] ,mux_1level_tapbuf_size2_343_sram_blwl_out[373:373] ,mux_1level_tapbuf_size2_343_sram_blwl_outb[373:373] ,mux_1level_tapbuf_size2_343_configbus0[373:373], mux_1level_tapbuf_size2_343_configbus1[373:373] , mux_1level_tapbuf_size2_343_configbus0_b[373:373] ); -wire [0:1] mux_1level_tapbuf_size2_344_inbus; -assign mux_1level_tapbuf_size2_344_inbus[0] = grid_2__1__pin_0__3__11_; -assign mux_1level_tapbuf_size2_344_inbus[1] = chanx_1__1__in_90_ ; -wire [374:374] mux_1level_tapbuf_size2_344_configbus0; -wire [374:374] mux_1level_tapbuf_size2_344_configbus1; -wire [374:374] mux_1level_tapbuf_size2_344_sram_blwl_out ; -wire [374:374] mux_1level_tapbuf_size2_344_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_344_configbus0[374:374] = sram_blwl_bl[374:374] ; -assign mux_1level_tapbuf_size2_344_configbus1[374:374] = sram_blwl_wl[374:374] ; -wire [374:374] mux_1level_tapbuf_size2_344_configbus0_b; -assign mux_1level_tapbuf_size2_344_configbus0_b[374:374] = sram_blwl_blb[374:374] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_344_ (mux_1level_tapbuf_size2_344_inbus, chany_1__1__out_89_ , mux_1level_tapbuf_size2_344_sram_blwl_out[374:374] , -mux_1level_tapbuf_size2_344_sram_blwl_outb[374:374] ); -//----- SRAM bits for MUX[344], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_374_ (mux_1level_tapbuf_size2_344_sram_blwl_out[374:374] ,mux_1level_tapbuf_size2_344_sram_blwl_out[374:374] ,mux_1level_tapbuf_size2_344_sram_blwl_outb[374:374] ,mux_1level_tapbuf_size2_344_configbus0[374:374], mux_1level_tapbuf_size2_344_configbus1[374:374] , mux_1level_tapbuf_size2_344_configbus0_b[374:374] ); -wire [0:1] mux_1level_tapbuf_size2_345_inbus; -assign mux_1level_tapbuf_size2_345_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_345_inbus[1] = chanx_1__1__in_92_ ; -wire [375:375] mux_1level_tapbuf_size2_345_configbus0; -wire [375:375] mux_1level_tapbuf_size2_345_configbus1; -wire [375:375] mux_1level_tapbuf_size2_345_sram_blwl_out ; -wire [375:375] mux_1level_tapbuf_size2_345_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_345_configbus0[375:375] = sram_blwl_bl[375:375] ; -assign mux_1level_tapbuf_size2_345_configbus1[375:375] = sram_blwl_wl[375:375] ; -wire [375:375] mux_1level_tapbuf_size2_345_configbus0_b; -assign mux_1level_tapbuf_size2_345_configbus0_b[375:375] = sram_blwl_blb[375:375] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_345_ (mux_1level_tapbuf_size2_345_inbus, chany_1__1__out_91_ , mux_1level_tapbuf_size2_345_sram_blwl_out[375:375] , -mux_1level_tapbuf_size2_345_sram_blwl_outb[375:375] ); -//----- SRAM bits for MUX[345], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_375_ (mux_1level_tapbuf_size2_345_sram_blwl_out[375:375] ,mux_1level_tapbuf_size2_345_sram_blwl_out[375:375] ,mux_1level_tapbuf_size2_345_sram_blwl_outb[375:375] ,mux_1level_tapbuf_size2_345_configbus0[375:375], mux_1level_tapbuf_size2_345_configbus1[375:375] , mux_1level_tapbuf_size2_345_configbus0_b[375:375] ); -wire [0:1] mux_1level_tapbuf_size2_346_inbus; -assign mux_1level_tapbuf_size2_346_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_346_inbus[1] = chanx_1__1__in_94_ ; -wire [376:376] mux_1level_tapbuf_size2_346_configbus0; -wire [376:376] mux_1level_tapbuf_size2_346_configbus1; -wire [376:376] mux_1level_tapbuf_size2_346_sram_blwl_out ; -wire [376:376] mux_1level_tapbuf_size2_346_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_346_configbus0[376:376] = sram_blwl_bl[376:376] ; -assign mux_1level_tapbuf_size2_346_configbus1[376:376] = sram_blwl_wl[376:376] ; -wire [376:376] mux_1level_tapbuf_size2_346_configbus0_b; -assign mux_1level_tapbuf_size2_346_configbus0_b[376:376] = sram_blwl_blb[376:376] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_346_ (mux_1level_tapbuf_size2_346_inbus, chany_1__1__out_93_ , mux_1level_tapbuf_size2_346_sram_blwl_out[376:376] , -mux_1level_tapbuf_size2_346_sram_blwl_outb[376:376] ); -//----- SRAM bits for MUX[346], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_376_ (mux_1level_tapbuf_size2_346_sram_blwl_out[376:376] ,mux_1level_tapbuf_size2_346_sram_blwl_out[376:376] ,mux_1level_tapbuf_size2_346_sram_blwl_outb[376:376] ,mux_1level_tapbuf_size2_346_configbus0[376:376], mux_1level_tapbuf_size2_346_configbus1[376:376] , mux_1level_tapbuf_size2_346_configbus0_b[376:376] ); -wire [0:1] mux_1level_tapbuf_size2_347_inbus; -assign mux_1level_tapbuf_size2_347_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_347_inbus[1] = chanx_1__1__in_96_ ; -wire [377:377] mux_1level_tapbuf_size2_347_configbus0; -wire [377:377] mux_1level_tapbuf_size2_347_configbus1; -wire [377:377] mux_1level_tapbuf_size2_347_sram_blwl_out ; -wire [377:377] mux_1level_tapbuf_size2_347_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_347_configbus0[377:377] = sram_blwl_bl[377:377] ; -assign mux_1level_tapbuf_size2_347_configbus1[377:377] = sram_blwl_wl[377:377] ; -wire [377:377] mux_1level_tapbuf_size2_347_configbus0_b; -assign mux_1level_tapbuf_size2_347_configbus0_b[377:377] = sram_blwl_blb[377:377] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_347_ (mux_1level_tapbuf_size2_347_inbus, chany_1__1__out_95_ , mux_1level_tapbuf_size2_347_sram_blwl_out[377:377] , -mux_1level_tapbuf_size2_347_sram_blwl_outb[377:377] ); -//----- SRAM bits for MUX[347], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_377_ (mux_1level_tapbuf_size2_347_sram_blwl_out[377:377] ,mux_1level_tapbuf_size2_347_sram_blwl_out[377:377] ,mux_1level_tapbuf_size2_347_sram_blwl_outb[377:377] ,mux_1level_tapbuf_size2_347_configbus0[377:377], mux_1level_tapbuf_size2_347_configbus1[377:377] , mux_1level_tapbuf_size2_347_configbus0_b[377:377] ); -wire [0:1] mux_1level_tapbuf_size2_348_inbus; -assign mux_1level_tapbuf_size2_348_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_348_inbus[1] = chanx_1__1__in_98_ ; -wire [378:378] mux_1level_tapbuf_size2_348_configbus0; -wire [378:378] mux_1level_tapbuf_size2_348_configbus1; -wire [378:378] mux_1level_tapbuf_size2_348_sram_blwl_out ; -wire [378:378] mux_1level_tapbuf_size2_348_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_348_configbus0[378:378] = sram_blwl_bl[378:378] ; -assign mux_1level_tapbuf_size2_348_configbus1[378:378] = sram_blwl_wl[378:378] ; -wire [378:378] mux_1level_tapbuf_size2_348_configbus0_b; -assign mux_1level_tapbuf_size2_348_configbus0_b[378:378] = sram_blwl_blb[378:378] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_348_ (mux_1level_tapbuf_size2_348_inbus, chany_1__1__out_97_ , mux_1level_tapbuf_size2_348_sram_blwl_out[378:378] , -mux_1level_tapbuf_size2_348_sram_blwl_outb[378:378] ); -//----- SRAM bits for MUX[348], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_378_ (mux_1level_tapbuf_size2_348_sram_blwl_out[378:378] ,mux_1level_tapbuf_size2_348_sram_blwl_out[378:378] ,mux_1level_tapbuf_size2_348_sram_blwl_outb[378:378] ,mux_1level_tapbuf_size2_348_configbus0[378:378], mux_1level_tapbuf_size2_348_configbus1[378:378] , mux_1level_tapbuf_size2_348_configbus0_b[378:378] ); -wire [0:1] mux_1level_tapbuf_size2_349_inbus; -assign mux_1level_tapbuf_size2_349_inbus[0] = grid_2__1__pin_0__3__13_; -assign mux_1level_tapbuf_size2_349_inbus[1] = chanx_1__1__in_0_ ; -wire [379:379] mux_1level_tapbuf_size2_349_configbus0; -wire [379:379] mux_1level_tapbuf_size2_349_configbus1; -wire [379:379] mux_1level_tapbuf_size2_349_sram_blwl_out ; -wire [379:379] mux_1level_tapbuf_size2_349_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_349_configbus0[379:379] = sram_blwl_bl[379:379] ; -assign mux_1level_tapbuf_size2_349_configbus1[379:379] = sram_blwl_wl[379:379] ; -wire [379:379] mux_1level_tapbuf_size2_349_configbus0_b; -assign mux_1level_tapbuf_size2_349_configbus0_b[379:379] = sram_blwl_blb[379:379] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_349_ (mux_1level_tapbuf_size2_349_inbus, chany_1__1__out_99_ , mux_1level_tapbuf_size2_349_sram_blwl_out[379:379] , -mux_1level_tapbuf_size2_349_sram_blwl_outb[379:379] ); -//----- SRAM bits for MUX[349], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_379_ (mux_1level_tapbuf_size2_349_sram_blwl_out[379:379] ,mux_1level_tapbuf_size2_349_sram_blwl_out[379:379] ,mux_1level_tapbuf_size2_349_sram_blwl_outb[379:379] ,mux_1level_tapbuf_size2_349_configbus0[379:379], mux_1level_tapbuf_size2_349_configbus1[379:379] , mux_1level_tapbuf_size2_349_configbus0_b[379:379] ); -//----- left side Multiplexers ----- -wire [0:2] mux_1level_tapbuf_size3_350_inbus; -assign mux_1level_tapbuf_size3_350_inbus[0] = grid_1__1__pin_0__0__40_; -assign mux_1level_tapbuf_size3_350_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_350_inbus[2] = chany_1__1__in_98_ ; -wire [380:382] mux_1level_tapbuf_size3_350_configbus0; -wire [380:382] mux_1level_tapbuf_size3_350_configbus1; -wire [380:382] mux_1level_tapbuf_size3_350_sram_blwl_out ; -wire [380:382] mux_1level_tapbuf_size3_350_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_350_configbus0[380:382] = sram_blwl_bl[380:382] ; -assign mux_1level_tapbuf_size3_350_configbus1[380:382] = sram_blwl_wl[380:382] ; -wire [380:382] mux_1level_tapbuf_size3_350_configbus0_b; -assign mux_1level_tapbuf_size3_350_configbus0_b[380:382] = sram_blwl_blb[380:382] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_350_ (mux_1level_tapbuf_size3_350_inbus, chanx_1__1__out_1_ , mux_1level_tapbuf_size3_350_sram_blwl_out[380:382] , -mux_1level_tapbuf_size3_350_sram_blwl_outb[380:382] ); -//----- SRAM bits for MUX[350], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_380_ (mux_1level_tapbuf_size3_350_sram_blwl_out[380:380] ,mux_1level_tapbuf_size3_350_sram_blwl_out[380:380] ,mux_1level_tapbuf_size3_350_sram_blwl_outb[380:380] ,mux_1level_tapbuf_size3_350_configbus0[380:380], mux_1level_tapbuf_size3_350_configbus1[380:380] , mux_1level_tapbuf_size3_350_configbus0_b[380:380] ); -sram6T_blwl sram_blwl_381_ (mux_1level_tapbuf_size3_350_sram_blwl_out[381:381] ,mux_1level_tapbuf_size3_350_sram_blwl_out[381:381] ,mux_1level_tapbuf_size3_350_sram_blwl_outb[381:381] ,mux_1level_tapbuf_size3_350_configbus0[381:381], mux_1level_tapbuf_size3_350_configbus1[381:381] , mux_1level_tapbuf_size3_350_configbus0_b[381:381] ); -sram6T_blwl sram_blwl_382_ (mux_1level_tapbuf_size3_350_sram_blwl_out[382:382] ,mux_1level_tapbuf_size3_350_sram_blwl_out[382:382] ,mux_1level_tapbuf_size3_350_sram_blwl_outb[382:382] ,mux_1level_tapbuf_size3_350_configbus0[382:382], mux_1level_tapbuf_size3_350_configbus1[382:382] , mux_1level_tapbuf_size3_350_configbus0_b[382:382] ); -wire [0:2] mux_1level_tapbuf_size3_351_inbus; -assign mux_1level_tapbuf_size3_351_inbus[0] = grid_1__1__pin_0__0__40_; -assign mux_1level_tapbuf_size3_351_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_351_inbus[2] = chany_1__1__in_0_ ; -wire [383:385] mux_1level_tapbuf_size3_351_configbus0; -wire [383:385] mux_1level_tapbuf_size3_351_configbus1; -wire [383:385] mux_1level_tapbuf_size3_351_sram_blwl_out ; -wire [383:385] mux_1level_tapbuf_size3_351_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_351_configbus0[383:385] = sram_blwl_bl[383:385] ; -assign mux_1level_tapbuf_size3_351_configbus1[383:385] = sram_blwl_wl[383:385] ; -wire [383:385] mux_1level_tapbuf_size3_351_configbus0_b; -assign mux_1level_tapbuf_size3_351_configbus0_b[383:385] = sram_blwl_blb[383:385] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_351_ (mux_1level_tapbuf_size3_351_inbus, chanx_1__1__out_3_ , mux_1level_tapbuf_size3_351_sram_blwl_out[383:385] , -mux_1level_tapbuf_size3_351_sram_blwl_outb[383:385] ); -//----- SRAM bits for MUX[351], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_383_ (mux_1level_tapbuf_size3_351_sram_blwl_out[383:383] ,mux_1level_tapbuf_size3_351_sram_blwl_out[383:383] ,mux_1level_tapbuf_size3_351_sram_blwl_outb[383:383] ,mux_1level_tapbuf_size3_351_configbus0[383:383], mux_1level_tapbuf_size3_351_configbus1[383:383] , mux_1level_tapbuf_size3_351_configbus0_b[383:383] ); -sram6T_blwl sram_blwl_384_ (mux_1level_tapbuf_size3_351_sram_blwl_out[384:384] ,mux_1level_tapbuf_size3_351_sram_blwl_out[384:384] ,mux_1level_tapbuf_size3_351_sram_blwl_outb[384:384] ,mux_1level_tapbuf_size3_351_configbus0[384:384], mux_1level_tapbuf_size3_351_configbus1[384:384] , mux_1level_tapbuf_size3_351_configbus0_b[384:384] ); -sram6T_blwl sram_blwl_385_ (mux_1level_tapbuf_size3_351_sram_blwl_out[385:385] ,mux_1level_tapbuf_size3_351_sram_blwl_out[385:385] ,mux_1level_tapbuf_size3_351_sram_blwl_outb[385:385] ,mux_1level_tapbuf_size3_351_configbus0[385:385], mux_1level_tapbuf_size3_351_configbus1[385:385] , mux_1level_tapbuf_size3_351_configbus0_b[385:385] ); -wire [0:2] mux_1level_tapbuf_size3_352_inbus; -assign mux_1level_tapbuf_size3_352_inbus[0] = grid_1__1__pin_0__0__40_; -assign mux_1level_tapbuf_size3_352_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_352_inbus[2] = chany_1__1__in_2_ ; -wire [386:388] mux_1level_tapbuf_size3_352_configbus0; -wire [386:388] mux_1level_tapbuf_size3_352_configbus1; -wire [386:388] mux_1level_tapbuf_size3_352_sram_blwl_out ; -wire [386:388] mux_1level_tapbuf_size3_352_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_352_configbus0[386:388] = sram_blwl_bl[386:388] ; -assign mux_1level_tapbuf_size3_352_configbus1[386:388] = sram_blwl_wl[386:388] ; -wire [386:388] mux_1level_tapbuf_size3_352_configbus0_b; -assign mux_1level_tapbuf_size3_352_configbus0_b[386:388] = sram_blwl_blb[386:388] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_352_ (mux_1level_tapbuf_size3_352_inbus, chanx_1__1__out_5_ , mux_1level_tapbuf_size3_352_sram_blwl_out[386:388] , -mux_1level_tapbuf_size3_352_sram_blwl_outb[386:388] ); -//----- SRAM bits for MUX[352], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_386_ (mux_1level_tapbuf_size3_352_sram_blwl_out[386:386] ,mux_1level_tapbuf_size3_352_sram_blwl_out[386:386] ,mux_1level_tapbuf_size3_352_sram_blwl_outb[386:386] ,mux_1level_tapbuf_size3_352_configbus0[386:386], mux_1level_tapbuf_size3_352_configbus1[386:386] , mux_1level_tapbuf_size3_352_configbus0_b[386:386] ); -sram6T_blwl sram_blwl_387_ (mux_1level_tapbuf_size3_352_sram_blwl_out[387:387] ,mux_1level_tapbuf_size3_352_sram_blwl_out[387:387] ,mux_1level_tapbuf_size3_352_sram_blwl_outb[387:387] ,mux_1level_tapbuf_size3_352_configbus0[387:387], mux_1level_tapbuf_size3_352_configbus1[387:387] , mux_1level_tapbuf_size3_352_configbus0_b[387:387] ); -sram6T_blwl sram_blwl_388_ (mux_1level_tapbuf_size3_352_sram_blwl_out[388:388] ,mux_1level_tapbuf_size3_352_sram_blwl_out[388:388] ,mux_1level_tapbuf_size3_352_sram_blwl_outb[388:388] ,mux_1level_tapbuf_size3_352_configbus0[388:388], mux_1level_tapbuf_size3_352_configbus1[388:388] , mux_1level_tapbuf_size3_352_configbus0_b[388:388] ); -wire [0:2] mux_1level_tapbuf_size3_353_inbus; -assign mux_1level_tapbuf_size3_353_inbus[0] = grid_1__1__pin_0__0__40_; -assign mux_1level_tapbuf_size3_353_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_353_inbus[2] = chany_1__1__in_4_ ; -wire [389:391] mux_1level_tapbuf_size3_353_configbus0; -wire [389:391] mux_1level_tapbuf_size3_353_configbus1; -wire [389:391] mux_1level_tapbuf_size3_353_sram_blwl_out ; -wire [389:391] mux_1level_tapbuf_size3_353_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_353_configbus0[389:391] = sram_blwl_bl[389:391] ; -assign mux_1level_tapbuf_size3_353_configbus1[389:391] = sram_blwl_wl[389:391] ; -wire [389:391] mux_1level_tapbuf_size3_353_configbus0_b; -assign mux_1level_tapbuf_size3_353_configbus0_b[389:391] = sram_blwl_blb[389:391] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_353_ (mux_1level_tapbuf_size3_353_inbus, chanx_1__1__out_7_ , mux_1level_tapbuf_size3_353_sram_blwl_out[389:391] , -mux_1level_tapbuf_size3_353_sram_blwl_outb[389:391] ); -//----- SRAM bits for MUX[353], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_389_ (mux_1level_tapbuf_size3_353_sram_blwl_out[389:389] ,mux_1level_tapbuf_size3_353_sram_blwl_out[389:389] ,mux_1level_tapbuf_size3_353_sram_blwl_outb[389:389] ,mux_1level_tapbuf_size3_353_configbus0[389:389], mux_1level_tapbuf_size3_353_configbus1[389:389] , mux_1level_tapbuf_size3_353_configbus0_b[389:389] ); -sram6T_blwl sram_blwl_390_ (mux_1level_tapbuf_size3_353_sram_blwl_out[390:390] ,mux_1level_tapbuf_size3_353_sram_blwl_out[390:390] ,mux_1level_tapbuf_size3_353_sram_blwl_outb[390:390] ,mux_1level_tapbuf_size3_353_configbus0[390:390], mux_1level_tapbuf_size3_353_configbus1[390:390] , mux_1level_tapbuf_size3_353_configbus0_b[390:390] ); -sram6T_blwl sram_blwl_391_ (mux_1level_tapbuf_size3_353_sram_blwl_out[391:391] ,mux_1level_tapbuf_size3_353_sram_blwl_out[391:391] ,mux_1level_tapbuf_size3_353_sram_blwl_outb[391:391] ,mux_1level_tapbuf_size3_353_configbus0[391:391], mux_1level_tapbuf_size3_353_configbus1[391:391] , mux_1level_tapbuf_size3_353_configbus0_b[391:391] ); -wire [0:2] mux_1level_tapbuf_size3_354_inbus; -assign mux_1level_tapbuf_size3_354_inbus[0] = grid_1__1__pin_0__0__40_; -assign mux_1level_tapbuf_size3_354_inbus[1] = grid_1__2__pin_0__2__15_; -assign mux_1level_tapbuf_size3_354_inbus[2] = chany_1__1__in_6_ ; -wire [392:394] mux_1level_tapbuf_size3_354_configbus0; -wire [392:394] mux_1level_tapbuf_size3_354_configbus1; -wire [392:394] mux_1level_tapbuf_size3_354_sram_blwl_out ; -wire [392:394] mux_1level_tapbuf_size3_354_sram_blwl_outb ; -assign mux_1level_tapbuf_size3_354_configbus0[392:394] = sram_blwl_bl[392:394] ; -assign mux_1level_tapbuf_size3_354_configbus1[392:394] = sram_blwl_wl[392:394] ; -wire [392:394] mux_1level_tapbuf_size3_354_configbus0_b; -assign mux_1level_tapbuf_size3_354_configbus0_b[392:394] = sram_blwl_blb[392:394] ; -mux_1level_tapbuf_size3 mux_1level_tapbuf_size3_354_ (mux_1level_tapbuf_size3_354_inbus, chanx_1__1__out_9_ , mux_1level_tapbuf_size3_354_sram_blwl_out[392:394] , -mux_1level_tapbuf_size3_354_sram_blwl_outb[392:394] ); -//----- SRAM bits for MUX[354], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----100----- -sram6T_blwl sram_blwl_392_ (mux_1level_tapbuf_size3_354_sram_blwl_out[392:392] ,mux_1level_tapbuf_size3_354_sram_blwl_out[392:392] ,mux_1level_tapbuf_size3_354_sram_blwl_outb[392:392] ,mux_1level_tapbuf_size3_354_configbus0[392:392], mux_1level_tapbuf_size3_354_configbus1[392:392] , mux_1level_tapbuf_size3_354_configbus0_b[392:392] ); -sram6T_blwl sram_blwl_393_ (mux_1level_tapbuf_size3_354_sram_blwl_out[393:393] ,mux_1level_tapbuf_size3_354_sram_blwl_out[393:393] ,mux_1level_tapbuf_size3_354_sram_blwl_outb[393:393] ,mux_1level_tapbuf_size3_354_configbus0[393:393], mux_1level_tapbuf_size3_354_configbus1[393:393] , mux_1level_tapbuf_size3_354_configbus0_b[393:393] ); -sram6T_blwl sram_blwl_394_ (mux_1level_tapbuf_size3_354_sram_blwl_out[394:394] ,mux_1level_tapbuf_size3_354_sram_blwl_out[394:394] ,mux_1level_tapbuf_size3_354_sram_blwl_outb[394:394] ,mux_1level_tapbuf_size3_354_configbus0[394:394], mux_1level_tapbuf_size3_354_configbus1[394:394] , mux_1level_tapbuf_size3_354_configbus0_b[394:394] ); -wire [0:1] mux_1level_tapbuf_size2_355_inbus; -assign mux_1level_tapbuf_size2_355_inbus[0] = grid_1__1__pin_0__0__44_; -assign mux_1level_tapbuf_size2_355_inbus[1] = chany_1__1__in_8_ ; -wire [395:395] mux_1level_tapbuf_size2_355_configbus0; -wire [395:395] mux_1level_tapbuf_size2_355_configbus1; -wire [395:395] mux_1level_tapbuf_size2_355_sram_blwl_out ; -wire [395:395] mux_1level_tapbuf_size2_355_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_355_configbus0[395:395] = sram_blwl_bl[395:395] ; -assign mux_1level_tapbuf_size2_355_configbus1[395:395] = sram_blwl_wl[395:395] ; -wire [395:395] mux_1level_tapbuf_size2_355_configbus0_b; -assign mux_1level_tapbuf_size2_355_configbus0_b[395:395] = sram_blwl_blb[395:395] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_355_ (mux_1level_tapbuf_size2_355_inbus, chanx_1__1__out_11_ , mux_1level_tapbuf_size2_355_sram_blwl_out[395:395] , -mux_1level_tapbuf_size2_355_sram_blwl_outb[395:395] ); -//----- SRAM bits for MUX[355], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_395_ (mux_1level_tapbuf_size2_355_sram_blwl_out[395:395] ,mux_1level_tapbuf_size2_355_sram_blwl_out[395:395] ,mux_1level_tapbuf_size2_355_sram_blwl_outb[395:395] ,mux_1level_tapbuf_size2_355_configbus0[395:395], mux_1level_tapbuf_size2_355_configbus1[395:395] , mux_1level_tapbuf_size2_355_configbus0_b[395:395] ); -wire [0:1] mux_1level_tapbuf_size2_356_inbus; -assign mux_1level_tapbuf_size2_356_inbus[0] = grid_1__1__pin_0__0__44_; -assign mux_1level_tapbuf_size2_356_inbus[1] = chany_1__1__in_10_ ; -wire [396:396] mux_1level_tapbuf_size2_356_configbus0; -wire [396:396] mux_1level_tapbuf_size2_356_configbus1; -wire [396:396] mux_1level_tapbuf_size2_356_sram_blwl_out ; -wire [396:396] mux_1level_tapbuf_size2_356_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_356_configbus0[396:396] = sram_blwl_bl[396:396] ; -assign mux_1level_tapbuf_size2_356_configbus1[396:396] = sram_blwl_wl[396:396] ; -wire [396:396] mux_1level_tapbuf_size2_356_configbus0_b; -assign mux_1level_tapbuf_size2_356_configbus0_b[396:396] = sram_blwl_blb[396:396] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_356_ (mux_1level_tapbuf_size2_356_inbus, chanx_1__1__out_13_ , mux_1level_tapbuf_size2_356_sram_blwl_out[396:396] , -mux_1level_tapbuf_size2_356_sram_blwl_outb[396:396] ); -//----- SRAM bits for MUX[356], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_396_ (mux_1level_tapbuf_size2_356_sram_blwl_out[396:396] ,mux_1level_tapbuf_size2_356_sram_blwl_out[396:396] ,mux_1level_tapbuf_size2_356_sram_blwl_outb[396:396] ,mux_1level_tapbuf_size2_356_configbus0[396:396], mux_1level_tapbuf_size2_356_configbus1[396:396] , mux_1level_tapbuf_size2_356_configbus0_b[396:396] ); -wire [0:1] mux_1level_tapbuf_size2_357_inbus; -assign mux_1level_tapbuf_size2_357_inbus[0] = grid_1__1__pin_0__0__44_; -assign mux_1level_tapbuf_size2_357_inbus[1] = chany_1__1__in_12_ ; -wire [397:397] mux_1level_tapbuf_size2_357_configbus0; -wire [397:397] mux_1level_tapbuf_size2_357_configbus1; -wire [397:397] mux_1level_tapbuf_size2_357_sram_blwl_out ; -wire [397:397] mux_1level_tapbuf_size2_357_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_357_configbus0[397:397] = sram_blwl_bl[397:397] ; -assign mux_1level_tapbuf_size2_357_configbus1[397:397] = sram_blwl_wl[397:397] ; -wire [397:397] mux_1level_tapbuf_size2_357_configbus0_b; -assign mux_1level_tapbuf_size2_357_configbus0_b[397:397] = sram_blwl_blb[397:397] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_357_ (mux_1level_tapbuf_size2_357_inbus, chanx_1__1__out_15_ , mux_1level_tapbuf_size2_357_sram_blwl_out[397:397] , -mux_1level_tapbuf_size2_357_sram_blwl_outb[397:397] ); -//----- SRAM bits for MUX[357], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_397_ (mux_1level_tapbuf_size2_357_sram_blwl_out[397:397] ,mux_1level_tapbuf_size2_357_sram_blwl_out[397:397] ,mux_1level_tapbuf_size2_357_sram_blwl_outb[397:397] ,mux_1level_tapbuf_size2_357_configbus0[397:397], mux_1level_tapbuf_size2_357_configbus1[397:397] , mux_1level_tapbuf_size2_357_configbus0_b[397:397] ); -wire [0:1] mux_1level_tapbuf_size2_358_inbus; -assign mux_1level_tapbuf_size2_358_inbus[0] = grid_1__1__pin_0__0__44_; -assign mux_1level_tapbuf_size2_358_inbus[1] = chany_1__1__in_14_ ; -wire [398:398] mux_1level_tapbuf_size2_358_configbus0; -wire [398:398] mux_1level_tapbuf_size2_358_configbus1; -wire [398:398] mux_1level_tapbuf_size2_358_sram_blwl_out ; -wire [398:398] mux_1level_tapbuf_size2_358_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_358_configbus0[398:398] = sram_blwl_bl[398:398] ; -assign mux_1level_tapbuf_size2_358_configbus1[398:398] = sram_blwl_wl[398:398] ; -wire [398:398] mux_1level_tapbuf_size2_358_configbus0_b; -assign mux_1level_tapbuf_size2_358_configbus0_b[398:398] = sram_blwl_blb[398:398] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_358_ (mux_1level_tapbuf_size2_358_inbus, chanx_1__1__out_17_ , mux_1level_tapbuf_size2_358_sram_blwl_out[398:398] , -mux_1level_tapbuf_size2_358_sram_blwl_outb[398:398] ); -//----- SRAM bits for MUX[358], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_398_ (mux_1level_tapbuf_size2_358_sram_blwl_out[398:398] ,mux_1level_tapbuf_size2_358_sram_blwl_out[398:398] ,mux_1level_tapbuf_size2_358_sram_blwl_outb[398:398] ,mux_1level_tapbuf_size2_358_configbus0[398:398], mux_1level_tapbuf_size2_358_configbus1[398:398] , mux_1level_tapbuf_size2_358_configbus0_b[398:398] ); -wire [0:1] mux_1level_tapbuf_size2_359_inbus; -assign mux_1level_tapbuf_size2_359_inbus[0] = grid_1__1__pin_0__0__44_; -assign mux_1level_tapbuf_size2_359_inbus[1] = chany_1__1__in_16_ ; -wire [399:399] mux_1level_tapbuf_size2_359_configbus0; -wire [399:399] mux_1level_tapbuf_size2_359_configbus1; -wire [399:399] mux_1level_tapbuf_size2_359_sram_blwl_out ; -wire [399:399] mux_1level_tapbuf_size2_359_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_359_configbus0[399:399] = sram_blwl_bl[399:399] ; -assign mux_1level_tapbuf_size2_359_configbus1[399:399] = sram_blwl_wl[399:399] ; -wire [399:399] mux_1level_tapbuf_size2_359_configbus0_b; -assign mux_1level_tapbuf_size2_359_configbus0_b[399:399] = sram_blwl_blb[399:399] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_359_ (mux_1level_tapbuf_size2_359_inbus, chanx_1__1__out_19_ , mux_1level_tapbuf_size2_359_sram_blwl_out[399:399] , -mux_1level_tapbuf_size2_359_sram_blwl_outb[399:399] ); -//----- SRAM bits for MUX[359], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_399_ (mux_1level_tapbuf_size2_359_sram_blwl_out[399:399] ,mux_1level_tapbuf_size2_359_sram_blwl_out[399:399] ,mux_1level_tapbuf_size2_359_sram_blwl_outb[399:399] ,mux_1level_tapbuf_size2_359_configbus0[399:399], mux_1level_tapbuf_size2_359_configbus1[399:399] , mux_1level_tapbuf_size2_359_configbus0_b[399:399] ); -wire [0:1] mux_1level_tapbuf_size2_360_inbus; -assign mux_1level_tapbuf_size2_360_inbus[0] = grid_1__1__pin_0__0__48_; -assign mux_1level_tapbuf_size2_360_inbus[1] = chany_1__1__in_18_ ; -wire [400:400] mux_1level_tapbuf_size2_360_configbus0; -wire [400:400] mux_1level_tapbuf_size2_360_configbus1; -wire [400:400] mux_1level_tapbuf_size2_360_sram_blwl_out ; -wire [400:400] mux_1level_tapbuf_size2_360_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_360_configbus0[400:400] = sram_blwl_bl[400:400] ; -assign mux_1level_tapbuf_size2_360_configbus1[400:400] = sram_blwl_wl[400:400] ; -wire [400:400] mux_1level_tapbuf_size2_360_configbus0_b; -assign mux_1level_tapbuf_size2_360_configbus0_b[400:400] = sram_blwl_blb[400:400] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_360_ (mux_1level_tapbuf_size2_360_inbus, chanx_1__1__out_21_ , mux_1level_tapbuf_size2_360_sram_blwl_out[400:400] , -mux_1level_tapbuf_size2_360_sram_blwl_outb[400:400] ); -//----- SRAM bits for MUX[360], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_400_ (mux_1level_tapbuf_size2_360_sram_blwl_out[400:400] ,mux_1level_tapbuf_size2_360_sram_blwl_out[400:400] ,mux_1level_tapbuf_size2_360_sram_blwl_outb[400:400] ,mux_1level_tapbuf_size2_360_configbus0[400:400], mux_1level_tapbuf_size2_360_configbus1[400:400] , mux_1level_tapbuf_size2_360_configbus0_b[400:400] ); -wire [0:1] mux_1level_tapbuf_size2_361_inbus; -assign mux_1level_tapbuf_size2_361_inbus[0] = grid_1__1__pin_0__0__48_; -assign mux_1level_tapbuf_size2_361_inbus[1] = chany_1__1__in_20_ ; -wire [401:401] mux_1level_tapbuf_size2_361_configbus0; -wire [401:401] mux_1level_tapbuf_size2_361_configbus1; -wire [401:401] mux_1level_tapbuf_size2_361_sram_blwl_out ; -wire [401:401] mux_1level_tapbuf_size2_361_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_361_configbus0[401:401] = sram_blwl_bl[401:401] ; -assign mux_1level_tapbuf_size2_361_configbus1[401:401] = sram_blwl_wl[401:401] ; -wire [401:401] mux_1level_tapbuf_size2_361_configbus0_b; -assign mux_1level_tapbuf_size2_361_configbus0_b[401:401] = sram_blwl_blb[401:401] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_361_ (mux_1level_tapbuf_size2_361_inbus, chanx_1__1__out_23_ , mux_1level_tapbuf_size2_361_sram_blwl_out[401:401] , -mux_1level_tapbuf_size2_361_sram_blwl_outb[401:401] ); -//----- SRAM bits for MUX[361], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_401_ (mux_1level_tapbuf_size2_361_sram_blwl_out[401:401] ,mux_1level_tapbuf_size2_361_sram_blwl_out[401:401] ,mux_1level_tapbuf_size2_361_sram_blwl_outb[401:401] ,mux_1level_tapbuf_size2_361_configbus0[401:401], mux_1level_tapbuf_size2_361_configbus1[401:401] , mux_1level_tapbuf_size2_361_configbus0_b[401:401] ); -wire [0:1] mux_1level_tapbuf_size2_362_inbus; -assign mux_1level_tapbuf_size2_362_inbus[0] = grid_1__1__pin_0__0__48_; -assign mux_1level_tapbuf_size2_362_inbus[1] = chany_1__1__in_22_ ; -wire [402:402] mux_1level_tapbuf_size2_362_configbus0; -wire [402:402] mux_1level_tapbuf_size2_362_configbus1; -wire [402:402] mux_1level_tapbuf_size2_362_sram_blwl_out ; -wire [402:402] mux_1level_tapbuf_size2_362_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_362_configbus0[402:402] = sram_blwl_bl[402:402] ; -assign mux_1level_tapbuf_size2_362_configbus1[402:402] = sram_blwl_wl[402:402] ; -wire [402:402] mux_1level_tapbuf_size2_362_configbus0_b; -assign mux_1level_tapbuf_size2_362_configbus0_b[402:402] = sram_blwl_blb[402:402] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_362_ (mux_1level_tapbuf_size2_362_inbus, chanx_1__1__out_25_ , mux_1level_tapbuf_size2_362_sram_blwl_out[402:402] , -mux_1level_tapbuf_size2_362_sram_blwl_outb[402:402] ); -//----- SRAM bits for MUX[362], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_402_ (mux_1level_tapbuf_size2_362_sram_blwl_out[402:402] ,mux_1level_tapbuf_size2_362_sram_blwl_out[402:402] ,mux_1level_tapbuf_size2_362_sram_blwl_outb[402:402] ,mux_1level_tapbuf_size2_362_configbus0[402:402], mux_1level_tapbuf_size2_362_configbus1[402:402] , mux_1level_tapbuf_size2_362_configbus0_b[402:402] ); -wire [0:1] mux_1level_tapbuf_size2_363_inbus; -assign mux_1level_tapbuf_size2_363_inbus[0] = grid_1__1__pin_0__0__48_; -assign mux_1level_tapbuf_size2_363_inbus[1] = chany_1__1__in_24_ ; -wire [403:403] mux_1level_tapbuf_size2_363_configbus0; -wire [403:403] mux_1level_tapbuf_size2_363_configbus1; -wire [403:403] mux_1level_tapbuf_size2_363_sram_blwl_out ; -wire [403:403] mux_1level_tapbuf_size2_363_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_363_configbus0[403:403] = sram_blwl_bl[403:403] ; -assign mux_1level_tapbuf_size2_363_configbus1[403:403] = sram_blwl_wl[403:403] ; -wire [403:403] mux_1level_tapbuf_size2_363_configbus0_b; -assign mux_1level_tapbuf_size2_363_configbus0_b[403:403] = sram_blwl_blb[403:403] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_363_ (mux_1level_tapbuf_size2_363_inbus, chanx_1__1__out_27_ , mux_1level_tapbuf_size2_363_sram_blwl_out[403:403] , -mux_1level_tapbuf_size2_363_sram_blwl_outb[403:403] ); -//----- SRAM bits for MUX[363], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_403_ (mux_1level_tapbuf_size2_363_sram_blwl_out[403:403] ,mux_1level_tapbuf_size2_363_sram_blwl_out[403:403] ,mux_1level_tapbuf_size2_363_sram_blwl_outb[403:403] ,mux_1level_tapbuf_size2_363_configbus0[403:403], mux_1level_tapbuf_size2_363_configbus1[403:403] , mux_1level_tapbuf_size2_363_configbus0_b[403:403] ); -wire [0:1] mux_1level_tapbuf_size2_364_inbus; -assign mux_1level_tapbuf_size2_364_inbus[0] = grid_1__1__pin_0__0__48_; -assign mux_1level_tapbuf_size2_364_inbus[1] = chany_1__1__in_26_ ; -wire [404:404] mux_1level_tapbuf_size2_364_configbus0; -wire [404:404] mux_1level_tapbuf_size2_364_configbus1; -wire [404:404] mux_1level_tapbuf_size2_364_sram_blwl_out ; -wire [404:404] mux_1level_tapbuf_size2_364_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_364_configbus0[404:404] = sram_blwl_bl[404:404] ; -assign mux_1level_tapbuf_size2_364_configbus1[404:404] = sram_blwl_wl[404:404] ; -wire [404:404] mux_1level_tapbuf_size2_364_configbus0_b; -assign mux_1level_tapbuf_size2_364_configbus0_b[404:404] = sram_blwl_blb[404:404] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_364_ (mux_1level_tapbuf_size2_364_inbus, chanx_1__1__out_29_ , mux_1level_tapbuf_size2_364_sram_blwl_out[404:404] , -mux_1level_tapbuf_size2_364_sram_blwl_outb[404:404] ); -//----- SRAM bits for MUX[364], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_404_ (mux_1level_tapbuf_size2_364_sram_blwl_out[404:404] ,mux_1level_tapbuf_size2_364_sram_blwl_out[404:404] ,mux_1level_tapbuf_size2_364_sram_blwl_outb[404:404] ,mux_1level_tapbuf_size2_364_configbus0[404:404], mux_1level_tapbuf_size2_364_configbus1[404:404] , mux_1level_tapbuf_size2_364_configbus0_b[404:404] ); -wire [0:1] mux_1level_tapbuf_size2_365_inbus; -assign mux_1level_tapbuf_size2_365_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_365_inbus[1] = chany_1__1__in_28_ ; -wire [405:405] mux_1level_tapbuf_size2_365_configbus0; -wire [405:405] mux_1level_tapbuf_size2_365_configbus1; -wire [405:405] mux_1level_tapbuf_size2_365_sram_blwl_out ; -wire [405:405] mux_1level_tapbuf_size2_365_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_365_configbus0[405:405] = sram_blwl_bl[405:405] ; -assign mux_1level_tapbuf_size2_365_configbus1[405:405] = sram_blwl_wl[405:405] ; -wire [405:405] mux_1level_tapbuf_size2_365_configbus0_b; -assign mux_1level_tapbuf_size2_365_configbus0_b[405:405] = sram_blwl_blb[405:405] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_365_ (mux_1level_tapbuf_size2_365_inbus, chanx_1__1__out_31_ , mux_1level_tapbuf_size2_365_sram_blwl_out[405:405] , -mux_1level_tapbuf_size2_365_sram_blwl_outb[405:405] ); -//----- SRAM bits for MUX[365], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_405_ (mux_1level_tapbuf_size2_365_sram_blwl_out[405:405] ,mux_1level_tapbuf_size2_365_sram_blwl_out[405:405] ,mux_1level_tapbuf_size2_365_sram_blwl_outb[405:405] ,mux_1level_tapbuf_size2_365_configbus0[405:405], mux_1level_tapbuf_size2_365_configbus1[405:405] , mux_1level_tapbuf_size2_365_configbus0_b[405:405] ); -wire [0:1] mux_1level_tapbuf_size2_366_inbus; -assign mux_1level_tapbuf_size2_366_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_366_inbus[1] = chany_1__1__in_30_ ; -wire [406:406] mux_1level_tapbuf_size2_366_configbus0; -wire [406:406] mux_1level_tapbuf_size2_366_configbus1; -wire [406:406] mux_1level_tapbuf_size2_366_sram_blwl_out ; -wire [406:406] mux_1level_tapbuf_size2_366_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_366_configbus0[406:406] = sram_blwl_bl[406:406] ; -assign mux_1level_tapbuf_size2_366_configbus1[406:406] = sram_blwl_wl[406:406] ; -wire [406:406] mux_1level_tapbuf_size2_366_configbus0_b; -assign mux_1level_tapbuf_size2_366_configbus0_b[406:406] = sram_blwl_blb[406:406] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_366_ (mux_1level_tapbuf_size2_366_inbus, chanx_1__1__out_33_ , mux_1level_tapbuf_size2_366_sram_blwl_out[406:406] , -mux_1level_tapbuf_size2_366_sram_blwl_outb[406:406] ); -//----- SRAM bits for MUX[366], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_406_ (mux_1level_tapbuf_size2_366_sram_blwl_out[406:406] ,mux_1level_tapbuf_size2_366_sram_blwl_out[406:406] ,mux_1level_tapbuf_size2_366_sram_blwl_outb[406:406] ,mux_1level_tapbuf_size2_366_configbus0[406:406], mux_1level_tapbuf_size2_366_configbus1[406:406] , mux_1level_tapbuf_size2_366_configbus0_b[406:406] ); -wire [0:1] mux_1level_tapbuf_size2_367_inbus; -assign mux_1level_tapbuf_size2_367_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_367_inbus[1] = chany_1__1__in_32_ ; -wire [407:407] mux_1level_tapbuf_size2_367_configbus0; -wire [407:407] mux_1level_tapbuf_size2_367_configbus1; -wire [407:407] mux_1level_tapbuf_size2_367_sram_blwl_out ; -wire [407:407] mux_1level_tapbuf_size2_367_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_367_configbus0[407:407] = sram_blwl_bl[407:407] ; -assign mux_1level_tapbuf_size2_367_configbus1[407:407] = sram_blwl_wl[407:407] ; -wire [407:407] mux_1level_tapbuf_size2_367_configbus0_b; -assign mux_1level_tapbuf_size2_367_configbus0_b[407:407] = sram_blwl_blb[407:407] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_367_ (mux_1level_tapbuf_size2_367_inbus, chanx_1__1__out_35_ , mux_1level_tapbuf_size2_367_sram_blwl_out[407:407] , -mux_1level_tapbuf_size2_367_sram_blwl_outb[407:407] ); -//----- SRAM bits for MUX[367], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_407_ (mux_1level_tapbuf_size2_367_sram_blwl_out[407:407] ,mux_1level_tapbuf_size2_367_sram_blwl_out[407:407] ,mux_1level_tapbuf_size2_367_sram_blwl_outb[407:407] ,mux_1level_tapbuf_size2_367_configbus0[407:407], mux_1level_tapbuf_size2_367_configbus1[407:407] , mux_1level_tapbuf_size2_367_configbus0_b[407:407] ); -wire [0:1] mux_1level_tapbuf_size2_368_inbus; -assign mux_1level_tapbuf_size2_368_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_368_inbus[1] = chany_1__1__in_34_ ; -wire [408:408] mux_1level_tapbuf_size2_368_configbus0; -wire [408:408] mux_1level_tapbuf_size2_368_configbus1; -wire [408:408] mux_1level_tapbuf_size2_368_sram_blwl_out ; -wire [408:408] mux_1level_tapbuf_size2_368_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_368_configbus0[408:408] = sram_blwl_bl[408:408] ; -assign mux_1level_tapbuf_size2_368_configbus1[408:408] = sram_blwl_wl[408:408] ; -wire [408:408] mux_1level_tapbuf_size2_368_configbus0_b; -assign mux_1level_tapbuf_size2_368_configbus0_b[408:408] = sram_blwl_blb[408:408] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_368_ (mux_1level_tapbuf_size2_368_inbus, chanx_1__1__out_37_ , mux_1level_tapbuf_size2_368_sram_blwl_out[408:408] , -mux_1level_tapbuf_size2_368_sram_blwl_outb[408:408] ); -//----- SRAM bits for MUX[368], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_408_ (mux_1level_tapbuf_size2_368_sram_blwl_out[408:408] ,mux_1level_tapbuf_size2_368_sram_blwl_out[408:408] ,mux_1level_tapbuf_size2_368_sram_blwl_outb[408:408] ,mux_1level_tapbuf_size2_368_configbus0[408:408], mux_1level_tapbuf_size2_368_configbus1[408:408] , mux_1level_tapbuf_size2_368_configbus0_b[408:408] ); -wire [0:1] mux_1level_tapbuf_size2_369_inbus; -assign mux_1level_tapbuf_size2_369_inbus[0] = grid_1__2__pin_0__2__1_; -assign mux_1level_tapbuf_size2_369_inbus[1] = chany_1__1__in_36_ ; -wire [409:409] mux_1level_tapbuf_size2_369_configbus0; -wire [409:409] mux_1level_tapbuf_size2_369_configbus1; -wire [409:409] mux_1level_tapbuf_size2_369_sram_blwl_out ; -wire [409:409] mux_1level_tapbuf_size2_369_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_369_configbus0[409:409] = sram_blwl_bl[409:409] ; -assign mux_1level_tapbuf_size2_369_configbus1[409:409] = sram_blwl_wl[409:409] ; -wire [409:409] mux_1level_tapbuf_size2_369_configbus0_b; -assign mux_1level_tapbuf_size2_369_configbus0_b[409:409] = sram_blwl_blb[409:409] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_369_ (mux_1level_tapbuf_size2_369_inbus, chanx_1__1__out_39_ , mux_1level_tapbuf_size2_369_sram_blwl_out[409:409] , -mux_1level_tapbuf_size2_369_sram_blwl_outb[409:409] ); -//----- SRAM bits for MUX[369], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_409_ (mux_1level_tapbuf_size2_369_sram_blwl_out[409:409] ,mux_1level_tapbuf_size2_369_sram_blwl_out[409:409] ,mux_1level_tapbuf_size2_369_sram_blwl_outb[409:409] ,mux_1level_tapbuf_size2_369_configbus0[409:409], mux_1level_tapbuf_size2_369_configbus1[409:409] , mux_1level_tapbuf_size2_369_configbus0_b[409:409] ); -wire [0:1] mux_1level_tapbuf_size2_370_inbus; -assign mux_1level_tapbuf_size2_370_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_370_inbus[1] = chany_1__1__in_38_ ; -wire [410:410] mux_1level_tapbuf_size2_370_configbus0; -wire [410:410] mux_1level_tapbuf_size2_370_configbus1; -wire [410:410] mux_1level_tapbuf_size2_370_sram_blwl_out ; -wire [410:410] mux_1level_tapbuf_size2_370_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_370_configbus0[410:410] = sram_blwl_bl[410:410] ; -assign mux_1level_tapbuf_size2_370_configbus1[410:410] = sram_blwl_wl[410:410] ; -wire [410:410] mux_1level_tapbuf_size2_370_configbus0_b; -assign mux_1level_tapbuf_size2_370_configbus0_b[410:410] = sram_blwl_blb[410:410] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_370_ (mux_1level_tapbuf_size2_370_inbus, chanx_1__1__out_41_ , mux_1level_tapbuf_size2_370_sram_blwl_out[410:410] , -mux_1level_tapbuf_size2_370_sram_blwl_outb[410:410] ); -//----- SRAM bits for MUX[370], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_410_ (mux_1level_tapbuf_size2_370_sram_blwl_out[410:410] ,mux_1level_tapbuf_size2_370_sram_blwl_out[410:410] ,mux_1level_tapbuf_size2_370_sram_blwl_outb[410:410] ,mux_1level_tapbuf_size2_370_configbus0[410:410], mux_1level_tapbuf_size2_370_configbus1[410:410] , mux_1level_tapbuf_size2_370_configbus0_b[410:410] ); -wire [0:1] mux_1level_tapbuf_size2_371_inbus; -assign mux_1level_tapbuf_size2_371_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_371_inbus[1] = chany_1__1__in_40_ ; -wire [411:411] mux_1level_tapbuf_size2_371_configbus0; -wire [411:411] mux_1level_tapbuf_size2_371_configbus1; -wire [411:411] mux_1level_tapbuf_size2_371_sram_blwl_out ; -wire [411:411] mux_1level_tapbuf_size2_371_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_371_configbus0[411:411] = sram_blwl_bl[411:411] ; -assign mux_1level_tapbuf_size2_371_configbus1[411:411] = sram_blwl_wl[411:411] ; -wire [411:411] mux_1level_tapbuf_size2_371_configbus0_b; -assign mux_1level_tapbuf_size2_371_configbus0_b[411:411] = sram_blwl_blb[411:411] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_371_ (mux_1level_tapbuf_size2_371_inbus, chanx_1__1__out_43_ , mux_1level_tapbuf_size2_371_sram_blwl_out[411:411] , -mux_1level_tapbuf_size2_371_sram_blwl_outb[411:411] ); -//----- SRAM bits for MUX[371], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_411_ (mux_1level_tapbuf_size2_371_sram_blwl_out[411:411] ,mux_1level_tapbuf_size2_371_sram_blwl_out[411:411] ,mux_1level_tapbuf_size2_371_sram_blwl_outb[411:411] ,mux_1level_tapbuf_size2_371_configbus0[411:411], mux_1level_tapbuf_size2_371_configbus1[411:411] , mux_1level_tapbuf_size2_371_configbus0_b[411:411] ); -wire [0:1] mux_1level_tapbuf_size2_372_inbus; -assign mux_1level_tapbuf_size2_372_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_372_inbus[1] = chany_1__1__in_42_ ; -wire [412:412] mux_1level_tapbuf_size2_372_configbus0; -wire [412:412] mux_1level_tapbuf_size2_372_configbus1; -wire [412:412] mux_1level_tapbuf_size2_372_sram_blwl_out ; -wire [412:412] mux_1level_tapbuf_size2_372_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_372_configbus0[412:412] = sram_blwl_bl[412:412] ; -assign mux_1level_tapbuf_size2_372_configbus1[412:412] = sram_blwl_wl[412:412] ; -wire [412:412] mux_1level_tapbuf_size2_372_configbus0_b; -assign mux_1level_tapbuf_size2_372_configbus0_b[412:412] = sram_blwl_blb[412:412] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_372_ (mux_1level_tapbuf_size2_372_inbus, chanx_1__1__out_45_ , mux_1level_tapbuf_size2_372_sram_blwl_out[412:412] , -mux_1level_tapbuf_size2_372_sram_blwl_outb[412:412] ); -//----- SRAM bits for MUX[372], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_412_ (mux_1level_tapbuf_size2_372_sram_blwl_out[412:412] ,mux_1level_tapbuf_size2_372_sram_blwl_out[412:412] ,mux_1level_tapbuf_size2_372_sram_blwl_outb[412:412] ,mux_1level_tapbuf_size2_372_configbus0[412:412], mux_1level_tapbuf_size2_372_configbus1[412:412] , mux_1level_tapbuf_size2_372_configbus0_b[412:412] ); -wire [0:1] mux_1level_tapbuf_size2_373_inbus; -assign mux_1level_tapbuf_size2_373_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_373_inbus[1] = chany_1__1__in_44_ ; -wire [413:413] mux_1level_tapbuf_size2_373_configbus0; -wire [413:413] mux_1level_tapbuf_size2_373_configbus1; -wire [413:413] mux_1level_tapbuf_size2_373_sram_blwl_out ; -wire [413:413] mux_1level_tapbuf_size2_373_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_373_configbus0[413:413] = sram_blwl_bl[413:413] ; -assign mux_1level_tapbuf_size2_373_configbus1[413:413] = sram_blwl_wl[413:413] ; -wire [413:413] mux_1level_tapbuf_size2_373_configbus0_b; -assign mux_1level_tapbuf_size2_373_configbus0_b[413:413] = sram_blwl_blb[413:413] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_373_ (mux_1level_tapbuf_size2_373_inbus, chanx_1__1__out_47_ , mux_1level_tapbuf_size2_373_sram_blwl_out[413:413] , -mux_1level_tapbuf_size2_373_sram_blwl_outb[413:413] ); -//----- SRAM bits for MUX[373], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_413_ (mux_1level_tapbuf_size2_373_sram_blwl_out[413:413] ,mux_1level_tapbuf_size2_373_sram_blwl_out[413:413] ,mux_1level_tapbuf_size2_373_sram_blwl_outb[413:413] ,mux_1level_tapbuf_size2_373_configbus0[413:413], mux_1level_tapbuf_size2_373_configbus1[413:413] , mux_1level_tapbuf_size2_373_configbus0_b[413:413] ); -wire [0:1] mux_1level_tapbuf_size2_374_inbus; -assign mux_1level_tapbuf_size2_374_inbus[0] = grid_1__2__pin_0__2__3_; -assign mux_1level_tapbuf_size2_374_inbus[1] = chany_1__1__in_46_ ; -wire [414:414] mux_1level_tapbuf_size2_374_configbus0; -wire [414:414] mux_1level_tapbuf_size2_374_configbus1; -wire [414:414] mux_1level_tapbuf_size2_374_sram_blwl_out ; -wire [414:414] mux_1level_tapbuf_size2_374_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_374_configbus0[414:414] = sram_blwl_bl[414:414] ; -assign mux_1level_tapbuf_size2_374_configbus1[414:414] = sram_blwl_wl[414:414] ; -wire [414:414] mux_1level_tapbuf_size2_374_configbus0_b; -assign mux_1level_tapbuf_size2_374_configbus0_b[414:414] = sram_blwl_blb[414:414] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_374_ (mux_1level_tapbuf_size2_374_inbus, chanx_1__1__out_49_ , mux_1level_tapbuf_size2_374_sram_blwl_out[414:414] , -mux_1level_tapbuf_size2_374_sram_blwl_outb[414:414] ); -//----- SRAM bits for MUX[374], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_414_ (mux_1level_tapbuf_size2_374_sram_blwl_out[414:414] ,mux_1level_tapbuf_size2_374_sram_blwl_out[414:414] ,mux_1level_tapbuf_size2_374_sram_blwl_outb[414:414] ,mux_1level_tapbuf_size2_374_configbus0[414:414], mux_1level_tapbuf_size2_374_configbus1[414:414] , mux_1level_tapbuf_size2_374_configbus0_b[414:414] ); -wire [0:1] mux_1level_tapbuf_size2_375_inbus; -assign mux_1level_tapbuf_size2_375_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_375_inbus[1] = chany_1__1__in_48_ ; -wire [415:415] mux_1level_tapbuf_size2_375_configbus0; -wire [415:415] mux_1level_tapbuf_size2_375_configbus1; -wire [415:415] mux_1level_tapbuf_size2_375_sram_blwl_out ; -wire [415:415] mux_1level_tapbuf_size2_375_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_375_configbus0[415:415] = sram_blwl_bl[415:415] ; -assign mux_1level_tapbuf_size2_375_configbus1[415:415] = sram_blwl_wl[415:415] ; -wire [415:415] mux_1level_tapbuf_size2_375_configbus0_b; -assign mux_1level_tapbuf_size2_375_configbus0_b[415:415] = sram_blwl_blb[415:415] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_375_ (mux_1level_tapbuf_size2_375_inbus, chanx_1__1__out_51_ , mux_1level_tapbuf_size2_375_sram_blwl_out[415:415] , -mux_1level_tapbuf_size2_375_sram_blwl_outb[415:415] ); -//----- SRAM bits for MUX[375], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_415_ (mux_1level_tapbuf_size2_375_sram_blwl_out[415:415] ,mux_1level_tapbuf_size2_375_sram_blwl_out[415:415] ,mux_1level_tapbuf_size2_375_sram_blwl_outb[415:415] ,mux_1level_tapbuf_size2_375_configbus0[415:415], mux_1level_tapbuf_size2_375_configbus1[415:415] , mux_1level_tapbuf_size2_375_configbus0_b[415:415] ); -wire [0:1] mux_1level_tapbuf_size2_376_inbus; -assign mux_1level_tapbuf_size2_376_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_376_inbus[1] = chany_1__1__in_50_ ; -wire [416:416] mux_1level_tapbuf_size2_376_configbus0; -wire [416:416] mux_1level_tapbuf_size2_376_configbus1; -wire [416:416] mux_1level_tapbuf_size2_376_sram_blwl_out ; -wire [416:416] mux_1level_tapbuf_size2_376_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_376_configbus0[416:416] = sram_blwl_bl[416:416] ; -assign mux_1level_tapbuf_size2_376_configbus1[416:416] = sram_blwl_wl[416:416] ; -wire [416:416] mux_1level_tapbuf_size2_376_configbus0_b; -assign mux_1level_tapbuf_size2_376_configbus0_b[416:416] = sram_blwl_blb[416:416] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_376_ (mux_1level_tapbuf_size2_376_inbus, chanx_1__1__out_53_ , mux_1level_tapbuf_size2_376_sram_blwl_out[416:416] , -mux_1level_tapbuf_size2_376_sram_blwl_outb[416:416] ); -//----- SRAM bits for MUX[376], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_416_ (mux_1level_tapbuf_size2_376_sram_blwl_out[416:416] ,mux_1level_tapbuf_size2_376_sram_blwl_out[416:416] ,mux_1level_tapbuf_size2_376_sram_blwl_outb[416:416] ,mux_1level_tapbuf_size2_376_configbus0[416:416], mux_1level_tapbuf_size2_376_configbus1[416:416] , mux_1level_tapbuf_size2_376_configbus0_b[416:416] ); -wire [0:1] mux_1level_tapbuf_size2_377_inbus; -assign mux_1level_tapbuf_size2_377_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_377_inbus[1] = chany_1__1__in_52_ ; -wire [417:417] mux_1level_tapbuf_size2_377_configbus0; -wire [417:417] mux_1level_tapbuf_size2_377_configbus1; -wire [417:417] mux_1level_tapbuf_size2_377_sram_blwl_out ; -wire [417:417] mux_1level_tapbuf_size2_377_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_377_configbus0[417:417] = sram_blwl_bl[417:417] ; -assign mux_1level_tapbuf_size2_377_configbus1[417:417] = sram_blwl_wl[417:417] ; -wire [417:417] mux_1level_tapbuf_size2_377_configbus0_b; -assign mux_1level_tapbuf_size2_377_configbus0_b[417:417] = sram_blwl_blb[417:417] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_377_ (mux_1level_tapbuf_size2_377_inbus, chanx_1__1__out_55_ , mux_1level_tapbuf_size2_377_sram_blwl_out[417:417] , -mux_1level_tapbuf_size2_377_sram_blwl_outb[417:417] ); -//----- SRAM bits for MUX[377], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_417_ (mux_1level_tapbuf_size2_377_sram_blwl_out[417:417] ,mux_1level_tapbuf_size2_377_sram_blwl_out[417:417] ,mux_1level_tapbuf_size2_377_sram_blwl_outb[417:417] ,mux_1level_tapbuf_size2_377_configbus0[417:417], mux_1level_tapbuf_size2_377_configbus1[417:417] , mux_1level_tapbuf_size2_377_configbus0_b[417:417] ); -wire [0:1] mux_1level_tapbuf_size2_378_inbus; -assign mux_1level_tapbuf_size2_378_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_378_inbus[1] = chany_1__1__in_54_ ; -wire [418:418] mux_1level_tapbuf_size2_378_configbus0; -wire [418:418] mux_1level_tapbuf_size2_378_configbus1; -wire [418:418] mux_1level_tapbuf_size2_378_sram_blwl_out ; -wire [418:418] mux_1level_tapbuf_size2_378_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_378_configbus0[418:418] = sram_blwl_bl[418:418] ; -assign mux_1level_tapbuf_size2_378_configbus1[418:418] = sram_blwl_wl[418:418] ; -wire [418:418] mux_1level_tapbuf_size2_378_configbus0_b; -assign mux_1level_tapbuf_size2_378_configbus0_b[418:418] = sram_blwl_blb[418:418] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_378_ (mux_1level_tapbuf_size2_378_inbus, chanx_1__1__out_57_ , mux_1level_tapbuf_size2_378_sram_blwl_out[418:418] , -mux_1level_tapbuf_size2_378_sram_blwl_outb[418:418] ); -//----- SRAM bits for MUX[378], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_418_ (mux_1level_tapbuf_size2_378_sram_blwl_out[418:418] ,mux_1level_tapbuf_size2_378_sram_blwl_out[418:418] ,mux_1level_tapbuf_size2_378_sram_blwl_outb[418:418] ,mux_1level_tapbuf_size2_378_configbus0[418:418], mux_1level_tapbuf_size2_378_configbus1[418:418] , mux_1level_tapbuf_size2_378_configbus0_b[418:418] ); -wire [0:1] mux_1level_tapbuf_size2_379_inbus; -assign mux_1level_tapbuf_size2_379_inbus[0] = grid_1__2__pin_0__2__5_; -assign mux_1level_tapbuf_size2_379_inbus[1] = chany_1__1__in_56_ ; -wire [419:419] mux_1level_tapbuf_size2_379_configbus0; -wire [419:419] mux_1level_tapbuf_size2_379_configbus1; -wire [419:419] mux_1level_tapbuf_size2_379_sram_blwl_out ; -wire [419:419] mux_1level_tapbuf_size2_379_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_379_configbus0[419:419] = sram_blwl_bl[419:419] ; -assign mux_1level_tapbuf_size2_379_configbus1[419:419] = sram_blwl_wl[419:419] ; -wire [419:419] mux_1level_tapbuf_size2_379_configbus0_b; -assign mux_1level_tapbuf_size2_379_configbus0_b[419:419] = sram_blwl_blb[419:419] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_379_ (mux_1level_tapbuf_size2_379_inbus, chanx_1__1__out_59_ , mux_1level_tapbuf_size2_379_sram_blwl_out[419:419] , -mux_1level_tapbuf_size2_379_sram_blwl_outb[419:419] ); -//----- SRAM bits for MUX[379], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_419_ (mux_1level_tapbuf_size2_379_sram_blwl_out[419:419] ,mux_1level_tapbuf_size2_379_sram_blwl_out[419:419] ,mux_1level_tapbuf_size2_379_sram_blwl_outb[419:419] ,mux_1level_tapbuf_size2_379_configbus0[419:419], mux_1level_tapbuf_size2_379_configbus1[419:419] , mux_1level_tapbuf_size2_379_configbus0_b[419:419] ); -wire [0:1] mux_1level_tapbuf_size2_380_inbus; -assign mux_1level_tapbuf_size2_380_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_380_inbus[1] = chany_1__1__in_58_ ; -wire [420:420] mux_1level_tapbuf_size2_380_configbus0; -wire [420:420] mux_1level_tapbuf_size2_380_configbus1; -wire [420:420] mux_1level_tapbuf_size2_380_sram_blwl_out ; -wire [420:420] mux_1level_tapbuf_size2_380_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_380_configbus0[420:420] = sram_blwl_bl[420:420] ; -assign mux_1level_tapbuf_size2_380_configbus1[420:420] = sram_blwl_wl[420:420] ; -wire [420:420] mux_1level_tapbuf_size2_380_configbus0_b; -assign mux_1level_tapbuf_size2_380_configbus0_b[420:420] = sram_blwl_blb[420:420] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_380_ (mux_1level_tapbuf_size2_380_inbus, chanx_1__1__out_61_ , mux_1level_tapbuf_size2_380_sram_blwl_out[420:420] , -mux_1level_tapbuf_size2_380_sram_blwl_outb[420:420] ); -//----- SRAM bits for MUX[380], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_420_ (mux_1level_tapbuf_size2_380_sram_blwl_out[420:420] ,mux_1level_tapbuf_size2_380_sram_blwl_out[420:420] ,mux_1level_tapbuf_size2_380_sram_blwl_outb[420:420] ,mux_1level_tapbuf_size2_380_configbus0[420:420], mux_1level_tapbuf_size2_380_configbus1[420:420] , mux_1level_tapbuf_size2_380_configbus0_b[420:420] ); -wire [0:1] mux_1level_tapbuf_size2_381_inbus; -assign mux_1level_tapbuf_size2_381_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_381_inbus[1] = chany_1__1__in_60_ ; -wire [421:421] mux_1level_tapbuf_size2_381_configbus0; -wire [421:421] mux_1level_tapbuf_size2_381_configbus1; -wire [421:421] mux_1level_tapbuf_size2_381_sram_blwl_out ; -wire [421:421] mux_1level_tapbuf_size2_381_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_381_configbus0[421:421] = sram_blwl_bl[421:421] ; -assign mux_1level_tapbuf_size2_381_configbus1[421:421] = sram_blwl_wl[421:421] ; -wire [421:421] mux_1level_tapbuf_size2_381_configbus0_b; -assign mux_1level_tapbuf_size2_381_configbus0_b[421:421] = sram_blwl_blb[421:421] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_381_ (mux_1level_tapbuf_size2_381_inbus, chanx_1__1__out_63_ , mux_1level_tapbuf_size2_381_sram_blwl_out[421:421] , -mux_1level_tapbuf_size2_381_sram_blwl_outb[421:421] ); -//----- SRAM bits for MUX[381], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_421_ (mux_1level_tapbuf_size2_381_sram_blwl_out[421:421] ,mux_1level_tapbuf_size2_381_sram_blwl_out[421:421] ,mux_1level_tapbuf_size2_381_sram_blwl_outb[421:421] ,mux_1level_tapbuf_size2_381_configbus0[421:421], mux_1level_tapbuf_size2_381_configbus1[421:421] , mux_1level_tapbuf_size2_381_configbus0_b[421:421] ); -wire [0:1] mux_1level_tapbuf_size2_382_inbus; -assign mux_1level_tapbuf_size2_382_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_382_inbus[1] = chany_1__1__in_62_ ; -wire [422:422] mux_1level_tapbuf_size2_382_configbus0; -wire [422:422] mux_1level_tapbuf_size2_382_configbus1; -wire [422:422] mux_1level_tapbuf_size2_382_sram_blwl_out ; -wire [422:422] mux_1level_tapbuf_size2_382_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_382_configbus0[422:422] = sram_blwl_bl[422:422] ; -assign mux_1level_tapbuf_size2_382_configbus1[422:422] = sram_blwl_wl[422:422] ; -wire [422:422] mux_1level_tapbuf_size2_382_configbus0_b; -assign mux_1level_tapbuf_size2_382_configbus0_b[422:422] = sram_blwl_blb[422:422] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_382_ (mux_1level_tapbuf_size2_382_inbus, chanx_1__1__out_65_ , mux_1level_tapbuf_size2_382_sram_blwl_out[422:422] , -mux_1level_tapbuf_size2_382_sram_blwl_outb[422:422] ); -//----- SRAM bits for MUX[382], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_422_ (mux_1level_tapbuf_size2_382_sram_blwl_out[422:422] ,mux_1level_tapbuf_size2_382_sram_blwl_out[422:422] ,mux_1level_tapbuf_size2_382_sram_blwl_outb[422:422] ,mux_1level_tapbuf_size2_382_configbus0[422:422], mux_1level_tapbuf_size2_382_configbus1[422:422] , mux_1level_tapbuf_size2_382_configbus0_b[422:422] ); -wire [0:1] mux_1level_tapbuf_size2_383_inbus; -assign mux_1level_tapbuf_size2_383_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_383_inbus[1] = chany_1__1__in_64_ ; -wire [423:423] mux_1level_tapbuf_size2_383_configbus0; -wire [423:423] mux_1level_tapbuf_size2_383_configbus1; -wire [423:423] mux_1level_tapbuf_size2_383_sram_blwl_out ; -wire [423:423] mux_1level_tapbuf_size2_383_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_383_configbus0[423:423] = sram_blwl_bl[423:423] ; -assign mux_1level_tapbuf_size2_383_configbus1[423:423] = sram_blwl_wl[423:423] ; -wire [423:423] mux_1level_tapbuf_size2_383_configbus0_b; -assign mux_1level_tapbuf_size2_383_configbus0_b[423:423] = sram_blwl_blb[423:423] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_383_ (mux_1level_tapbuf_size2_383_inbus, chanx_1__1__out_67_ , mux_1level_tapbuf_size2_383_sram_blwl_out[423:423] , -mux_1level_tapbuf_size2_383_sram_blwl_outb[423:423] ); -//----- SRAM bits for MUX[383], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_423_ (mux_1level_tapbuf_size2_383_sram_blwl_out[423:423] ,mux_1level_tapbuf_size2_383_sram_blwl_out[423:423] ,mux_1level_tapbuf_size2_383_sram_blwl_outb[423:423] ,mux_1level_tapbuf_size2_383_configbus0[423:423], mux_1level_tapbuf_size2_383_configbus1[423:423] , mux_1level_tapbuf_size2_383_configbus0_b[423:423] ); -wire [0:1] mux_1level_tapbuf_size2_384_inbus; -assign mux_1level_tapbuf_size2_384_inbus[0] = grid_1__2__pin_0__2__7_; -assign mux_1level_tapbuf_size2_384_inbus[1] = chany_1__1__in_66_ ; -wire [424:424] mux_1level_tapbuf_size2_384_configbus0; -wire [424:424] mux_1level_tapbuf_size2_384_configbus1; -wire [424:424] mux_1level_tapbuf_size2_384_sram_blwl_out ; -wire [424:424] mux_1level_tapbuf_size2_384_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_384_configbus0[424:424] = sram_blwl_bl[424:424] ; -assign mux_1level_tapbuf_size2_384_configbus1[424:424] = sram_blwl_wl[424:424] ; -wire [424:424] mux_1level_tapbuf_size2_384_configbus0_b; -assign mux_1level_tapbuf_size2_384_configbus0_b[424:424] = sram_blwl_blb[424:424] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_384_ (mux_1level_tapbuf_size2_384_inbus, chanx_1__1__out_69_ , mux_1level_tapbuf_size2_384_sram_blwl_out[424:424] , -mux_1level_tapbuf_size2_384_sram_blwl_outb[424:424] ); -//----- SRAM bits for MUX[384], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_424_ (mux_1level_tapbuf_size2_384_sram_blwl_out[424:424] ,mux_1level_tapbuf_size2_384_sram_blwl_out[424:424] ,mux_1level_tapbuf_size2_384_sram_blwl_outb[424:424] ,mux_1level_tapbuf_size2_384_configbus0[424:424], mux_1level_tapbuf_size2_384_configbus1[424:424] , mux_1level_tapbuf_size2_384_configbus0_b[424:424] ); -wire [0:1] mux_1level_tapbuf_size2_385_inbus; -assign mux_1level_tapbuf_size2_385_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_385_inbus[1] = chany_1__1__in_68_ ; -wire [425:425] mux_1level_tapbuf_size2_385_configbus0; -wire [425:425] mux_1level_tapbuf_size2_385_configbus1; -wire [425:425] mux_1level_tapbuf_size2_385_sram_blwl_out ; -wire [425:425] mux_1level_tapbuf_size2_385_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_385_configbus0[425:425] = sram_blwl_bl[425:425] ; -assign mux_1level_tapbuf_size2_385_configbus1[425:425] = sram_blwl_wl[425:425] ; -wire [425:425] mux_1level_tapbuf_size2_385_configbus0_b; -assign mux_1level_tapbuf_size2_385_configbus0_b[425:425] = sram_blwl_blb[425:425] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_385_ (mux_1level_tapbuf_size2_385_inbus, chanx_1__1__out_71_ , mux_1level_tapbuf_size2_385_sram_blwl_out[425:425] , -mux_1level_tapbuf_size2_385_sram_blwl_outb[425:425] ); -//----- SRAM bits for MUX[385], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_425_ (mux_1level_tapbuf_size2_385_sram_blwl_out[425:425] ,mux_1level_tapbuf_size2_385_sram_blwl_out[425:425] ,mux_1level_tapbuf_size2_385_sram_blwl_outb[425:425] ,mux_1level_tapbuf_size2_385_configbus0[425:425], mux_1level_tapbuf_size2_385_configbus1[425:425] , mux_1level_tapbuf_size2_385_configbus0_b[425:425] ); -wire [0:1] mux_1level_tapbuf_size2_386_inbus; -assign mux_1level_tapbuf_size2_386_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_386_inbus[1] = chany_1__1__in_70_ ; -wire [426:426] mux_1level_tapbuf_size2_386_configbus0; -wire [426:426] mux_1level_tapbuf_size2_386_configbus1; -wire [426:426] mux_1level_tapbuf_size2_386_sram_blwl_out ; -wire [426:426] mux_1level_tapbuf_size2_386_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_386_configbus0[426:426] = sram_blwl_bl[426:426] ; -assign mux_1level_tapbuf_size2_386_configbus1[426:426] = sram_blwl_wl[426:426] ; -wire [426:426] mux_1level_tapbuf_size2_386_configbus0_b; -assign mux_1level_tapbuf_size2_386_configbus0_b[426:426] = sram_blwl_blb[426:426] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_386_ (mux_1level_tapbuf_size2_386_inbus, chanx_1__1__out_73_ , mux_1level_tapbuf_size2_386_sram_blwl_out[426:426] , -mux_1level_tapbuf_size2_386_sram_blwl_outb[426:426] ); -//----- SRAM bits for MUX[386], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_426_ (mux_1level_tapbuf_size2_386_sram_blwl_out[426:426] ,mux_1level_tapbuf_size2_386_sram_blwl_out[426:426] ,mux_1level_tapbuf_size2_386_sram_blwl_outb[426:426] ,mux_1level_tapbuf_size2_386_configbus0[426:426], mux_1level_tapbuf_size2_386_configbus1[426:426] , mux_1level_tapbuf_size2_386_configbus0_b[426:426] ); -wire [0:1] mux_1level_tapbuf_size2_387_inbus; -assign mux_1level_tapbuf_size2_387_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_387_inbus[1] = chany_1__1__in_72_ ; -wire [427:427] mux_1level_tapbuf_size2_387_configbus0; -wire [427:427] mux_1level_tapbuf_size2_387_configbus1; -wire [427:427] mux_1level_tapbuf_size2_387_sram_blwl_out ; -wire [427:427] mux_1level_tapbuf_size2_387_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_387_configbus0[427:427] = sram_blwl_bl[427:427] ; -assign mux_1level_tapbuf_size2_387_configbus1[427:427] = sram_blwl_wl[427:427] ; -wire [427:427] mux_1level_tapbuf_size2_387_configbus0_b; -assign mux_1level_tapbuf_size2_387_configbus0_b[427:427] = sram_blwl_blb[427:427] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_387_ (mux_1level_tapbuf_size2_387_inbus, chanx_1__1__out_75_ , mux_1level_tapbuf_size2_387_sram_blwl_out[427:427] , -mux_1level_tapbuf_size2_387_sram_blwl_outb[427:427] ); -//----- SRAM bits for MUX[387], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_427_ (mux_1level_tapbuf_size2_387_sram_blwl_out[427:427] ,mux_1level_tapbuf_size2_387_sram_blwl_out[427:427] ,mux_1level_tapbuf_size2_387_sram_blwl_outb[427:427] ,mux_1level_tapbuf_size2_387_configbus0[427:427], mux_1level_tapbuf_size2_387_configbus1[427:427] , mux_1level_tapbuf_size2_387_configbus0_b[427:427] ); -wire [0:1] mux_1level_tapbuf_size2_388_inbus; -assign mux_1level_tapbuf_size2_388_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_388_inbus[1] = chany_1__1__in_74_ ; -wire [428:428] mux_1level_tapbuf_size2_388_configbus0; -wire [428:428] mux_1level_tapbuf_size2_388_configbus1; -wire [428:428] mux_1level_tapbuf_size2_388_sram_blwl_out ; -wire [428:428] mux_1level_tapbuf_size2_388_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_388_configbus0[428:428] = sram_blwl_bl[428:428] ; -assign mux_1level_tapbuf_size2_388_configbus1[428:428] = sram_blwl_wl[428:428] ; -wire [428:428] mux_1level_tapbuf_size2_388_configbus0_b; -assign mux_1level_tapbuf_size2_388_configbus0_b[428:428] = sram_blwl_blb[428:428] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_388_ (mux_1level_tapbuf_size2_388_inbus, chanx_1__1__out_77_ , mux_1level_tapbuf_size2_388_sram_blwl_out[428:428] , -mux_1level_tapbuf_size2_388_sram_blwl_outb[428:428] ); -//----- SRAM bits for MUX[388], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_428_ (mux_1level_tapbuf_size2_388_sram_blwl_out[428:428] ,mux_1level_tapbuf_size2_388_sram_blwl_out[428:428] ,mux_1level_tapbuf_size2_388_sram_blwl_outb[428:428] ,mux_1level_tapbuf_size2_388_configbus0[428:428], mux_1level_tapbuf_size2_388_configbus1[428:428] , mux_1level_tapbuf_size2_388_configbus0_b[428:428] ); -wire [0:1] mux_1level_tapbuf_size2_389_inbus; -assign mux_1level_tapbuf_size2_389_inbus[0] = grid_1__2__pin_0__2__9_; -assign mux_1level_tapbuf_size2_389_inbus[1] = chany_1__1__in_76_ ; -wire [429:429] mux_1level_tapbuf_size2_389_configbus0; -wire [429:429] mux_1level_tapbuf_size2_389_configbus1; -wire [429:429] mux_1level_tapbuf_size2_389_sram_blwl_out ; -wire [429:429] mux_1level_tapbuf_size2_389_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_389_configbus0[429:429] = sram_blwl_bl[429:429] ; -assign mux_1level_tapbuf_size2_389_configbus1[429:429] = sram_blwl_wl[429:429] ; -wire [429:429] mux_1level_tapbuf_size2_389_configbus0_b; -assign mux_1level_tapbuf_size2_389_configbus0_b[429:429] = sram_blwl_blb[429:429] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_389_ (mux_1level_tapbuf_size2_389_inbus, chanx_1__1__out_79_ , mux_1level_tapbuf_size2_389_sram_blwl_out[429:429] , -mux_1level_tapbuf_size2_389_sram_blwl_outb[429:429] ); -//----- SRAM bits for MUX[389], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_429_ (mux_1level_tapbuf_size2_389_sram_blwl_out[429:429] ,mux_1level_tapbuf_size2_389_sram_blwl_out[429:429] ,mux_1level_tapbuf_size2_389_sram_blwl_outb[429:429] ,mux_1level_tapbuf_size2_389_configbus0[429:429], mux_1level_tapbuf_size2_389_configbus1[429:429] , mux_1level_tapbuf_size2_389_configbus0_b[429:429] ); -wire [0:1] mux_1level_tapbuf_size2_390_inbus; -assign mux_1level_tapbuf_size2_390_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_390_inbus[1] = chany_1__1__in_78_ ; -wire [430:430] mux_1level_tapbuf_size2_390_configbus0; -wire [430:430] mux_1level_tapbuf_size2_390_configbus1; -wire [430:430] mux_1level_tapbuf_size2_390_sram_blwl_out ; -wire [430:430] mux_1level_tapbuf_size2_390_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_390_configbus0[430:430] = sram_blwl_bl[430:430] ; -assign mux_1level_tapbuf_size2_390_configbus1[430:430] = sram_blwl_wl[430:430] ; -wire [430:430] mux_1level_tapbuf_size2_390_configbus0_b; -assign mux_1level_tapbuf_size2_390_configbus0_b[430:430] = sram_blwl_blb[430:430] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_390_ (mux_1level_tapbuf_size2_390_inbus, chanx_1__1__out_81_ , mux_1level_tapbuf_size2_390_sram_blwl_out[430:430] , -mux_1level_tapbuf_size2_390_sram_blwl_outb[430:430] ); -//----- SRAM bits for MUX[390], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_430_ (mux_1level_tapbuf_size2_390_sram_blwl_out[430:430] ,mux_1level_tapbuf_size2_390_sram_blwl_out[430:430] ,mux_1level_tapbuf_size2_390_sram_blwl_outb[430:430] ,mux_1level_tapbuf_size2_390_configbus0[430:430], mux_1level_tapbuf_size2_390_configbus1[430:430] , mux_1level_tapbuf_size2_390_configbus0_b[430:430] ); -wire [0:1] mux_1level_tapbuf_size2_391_inbus; -assign mux_1level_tapbuf_size2_391_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_391_inbus[1] = chany_1__1__in_80_ ; -wire [431:431] mux_1level_tapbuf_size2_391_configbus0; -wire [431:431] mux_1level_tapbuf_size2_391_configbus1; -wire [431:431] mux_1level_tapbuf_size2_391_sram_blwl_out ; -wire [431:431] mux_1level_tapbuf_size2_391_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_391_configbus0[431:431] = sram_blwl_bl[431:431] ; -assign mux_1level_tapbuf_size2_391_configbus1[431:431] = sram_blwl_wl[431:431] ; -wire [431:431] mux_1level_tapbuf_size2_391_configbus0_b; -assign mux_1level_tapbuf_size2_391_configbus0_b[431:431] = sram_blwl_blb[431:431] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_391_ (mux_1level_tapbuf_size2_391_inbus, chanx_1__1__out_83_ , mux_1level_tapbuf_size2_391_sram_blwl_out[431:431] , -mux_1level_tapbuf_size2_391_sram_blwl_outb[431:431] ); -//----- SRAM bits for MUX[391], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_431_ (mux_1level_tapbuf_size2_391_sram_blwl_out[431:431] ,mux_1level_tapbuf_size2_391_sram_blwl_out[431:431] ,mux_1level_tapbuf_size2_391_sram_blwl_outb[431:431] ,mux_1level_tapbuf_size2_391_configbus0[431:431], mux_1level_tapbuf_size2_391_configbus1[431:431] , mux_1level_tapbuf_size2_391_configbus0_b[431:431] ); -wire [0:1] mux_1level_tapbuf_size2_392_inbus; -assign mux_1level_tapbuf_size2_392_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_392_inbus[1] = chany_1__1__in_82_ ; -wire [432:432] mux_1level_tapbuf_size2_392_configbus0; -wire [432:432] mux_1level_tapbuf_size2_392_configbus1; -wire [432:432] mux_1level_tapbuf_size2_392_sram_blwl_out ; -wire [432:432] mux_1level_tapbuf_size2_392_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_392_configbus0[432:432] = sram_blwl_bl[432:432] ; -assign mux_1level_tapbuf_size2_392_configbus1[432:432] = sram_blwl_wl[432:432] ; -wire [432:432] mux_1level_tapbuf_size2_392_configbus0_b; -assign mux_1level_tapbuf_size2_392_configbus0_b[432:432] = sram_blwl_blb[432:432] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_392_ (mux_1level_tapbuf_size2_392_inbus, chanx_1__1__out_85_ , mux_1level_tapbuf_size2_392_sram_blwl_out[432:432] , -mux_1level_tapbuf_size2_392_sram_blwl_outb[432:432] ); -//----- SRAM bits for MUX[392], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_432_ (mux_1level_tapbuf_size2_392_sram_blwl_out[432:432] ,mux_1level_tapbuf_size2_392_sram_blwl_out[432:432] ,mux_1level_tapbuf_size2_392_sram_blwl_outb[432:432] ,mux_1level_tapbuf_size2_392_configbus0[432:432], mux_1level_tapbuf_size2_392_configbus1[432:432] , mux_1level_tapbuf_size2_392_configbus0_b[432:432] ); -wire [0:1] mux_1level_tapbuf_size2_393_inbus; -assign mux_1level_tapbuf_size2_393_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_393_inbus[1] = chany_1__1__in_84_ ; -wire [433:433] mux_1level_tapbuf_size2_393_configbus0; -wire [433:433] mux_1level_tapbuf_size2_393_configbus1; -wire [433:433] mux_1level_tapbuf_size2_393_sram_blwl_out ; -wire [433:433] mux_1level_tapbuf_size2_393_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_393_configbus0[433:433] = sram_blwl_bl[433:433] ; -assign mux_1level_tapbuf_size2_393_configbus1[433:433] = sram_blwl_wl[433:433] ; -wire [433:433] mux_1level_tapbuf_size2_393_configbus0_b; -assign mux_1level_tapbuf_size2_393_configbus0_b[433:433] = sram_blwl_blb[433:433] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_393_ (mux_1level_tapbuf_size2_393_inbus, chanx_1__1__out_87_ , mux_1level_tapbuf_size2_393_sram_blwl_out[433:433] , -mux_1level_tapbuf_size2_393_sram_blwl_outb[433:433] ); -//----- SRAM bits for MUX[393], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_433_ (mux_1level_tapbuf_size2_393_sram_blwl_out[433:433] ,mux_1level_tapbuf_size2_393_sram_blwl_out[433:433] ,mux_1level_tapbuf_size2_393_sram_blwl_outb[433:433] ,mux_1level_tapbuf_size2_393_configbus0[433:433], mux_1level_tapbuf_size2_393_configbus1[433:433] , mux_1level_tapbuf_size2_393_configbus0_b[433:433] ); -wire [0:1] mux_1level_tapbuf_size2_394_inbus; -assign mux_1level_tapbuf_size2_394_inbus[0] = grid_1__2__pin_0__2__11_; -assign mux_1level_tapbuf_size2_394_inbus[1] = chany_1__1__in_86_ ; -wire [434:434] mux_1level_tapbuf_size2_394_configbus0; -wire [434:434] mux_1level_tapbuf_size2_394_configbus1; -wire [434:434] mux_1level_tapbuf_size2_394_sram_blwl_out ; -wire [434:434] mux_1level_tapbuf_size2_394_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_394_configbus0[434:434] = sram_blwl_bl[434:434] ; -assign mux_1level_tapbuf_size2_394_configbus1[434:434] = sram_blwl_wl[434:434] ; -wire [434:434] mux_1level_tapbuf_size2_394_configbus0_b; -assign mux_1level_tapbuf_size2_394_configbus0_b[434:434] = sram_blwl_blb[434:434] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_394_ (mux_1level_tapbuf_size2_394_inbus, chanx_1__1__out_89_ , mux_1level_tapbuf_size2_394_sram_blwl_out[434:434] , -mux_1level_tapbuf_size2_394_sram_blwl_outb[434:434] ); -//----- SRAM bits for MUX[394], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_434_ (mux_1level_tapbuf_size2_394_sram_blwl_out[434:434] ,mux_1level_tapbuf_size2_394_sram_blwl_out[434:434] ,mux_1level_tapbuf_size2_394_sram_blwl_outb[434:434] ,mux_1level_tapbuf_size2_394_configbus0[434:434], mux_1level_tapbuf_size2_394_configbus1[434:434] , mux_1level_tapbuf_size2_394_configbus0_b[434:434] ); -wire [0:1] mux_1level_tapbuf_size2_395_inbus; -assign mux_1level_tapbuf_size2_395_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_395_inbus[1] = chany_1__1__in_88_ ; -wire [435:435] mux_1level_tapbuf_size2_395_configbus0; -wire [435:435] mux_1level_tapbuf_size2_395_configbus1; -wire [435:435] mux_1level_tapbuf_size2_395_sram_blwl_out ; -wire [435:435] mux_1level_tapbuf_size2_395_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_395_configbus0[435:435] = sram_blwl_bl[435:435] ; -assign mux_1level_tapbuf_size2_395_configbus1[435:435] = sram_blwl_wl[435:435] ; -wire [435:435] mux_1level_tapbuf_size2_395_configbus0_b; -assign mux_1level_tapbuf_size2_395_configbus0_b[435:435] = sram_blwl_blb[435:435] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_395_ (mux_1level_tapbuf_size2_395_inbus, chanx_1__1__out_91_ , mux_1level_tapbuf_size2_395_sram_blwl_out[435:435] , -mux_1level_tapbuf_size2_395_sram_blwl_outb[435:435] ); -//----- SRAM bits for MUX[395], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_435_ (mux_1level_tapbuf_size2_395_sram_blwl_out[435:435] ,mux_1level_tapbuf_size2_395_sram_blwl_out[435:435] ,mux_1level_tapbuf_size2_395_sram_blwl_outb[435:435] ,mux_1level_tapbuf_size2_395_configbus0[435:435], mux_1level_tapbuf_size2_395_configbus1[435:435] , mux_1level_tapbuf_size2_395_configbus0_b[435:435] ); -wire [0:1] mux_1level_tapbuf_size2_396_inbus; -assign mux_1level_tapbuf_size2_396_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_396_inbus[1] = chany_1__1__in_90_ ; -wire [436:436] mux_1level_tapbuf_size2_396_configbus0; -wire [436:436] mux_1level_tapbuf_size2_396_configbus1; -wire [436:436] mux_1level_tapbuf_size2_396_sram_blwl_out ; -wire [436:436] mux_1level_tapbuf_size2_396_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_396_configbus0[436:436] = sram_blwl_bl[436:436] ; -assign mux_1level_tapbuf_size2_396_configbus1[436:436] = sram_blwl_wl[436:436] ; -wire [436:436] mux_1level_tapbuf_size2_396_configbus0_b; -assign mux_1level_tapbuf_size2_396_configbus0_b[436:436] = sram_blwl_blb[436:436] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_396_ (mux_1level_tapbuf_size2_396_inbus, chanx_1__1__out_93_ , mux_1level_tapbuf_size2_396_sram_blwl_out[436:436] , -mux_1level_tapbuf_size2_396_sram_blwl_outb[436:436] ); -//----- SRAM bits for MUX[396], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_436_ (mux_1level_tapbuf_size2_396_sram_blwl_out[436:436] ,mux_1level_tapbuf_size2_396_sram_blwl_out[436:436] ,mux_1level_tapbuf_size2_396_sram_blwl_outb[436:436] ,mux_1level_tapbuf_size2_396_configbus0[436:436], mux_1level_tapbuf_size2_396_configbus1[436:436] , mux_1level_tapbuf_size2_396_configbus0_b[436:436] ); -wire [0:1] mux_1level_tapbuf_size2_397_inbus; -assign mux_1level_tapbuf_size2_397_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_397_inbus[1] = chany_1__1__in_92_ ; -wire [437:437] mux_1level_tapbuf_size2_397_configbus0; -wire [437:437] mux_1level_tapbuf_size2_397_configbus1; -wire [437:437] mux_1level_tapbuf_size2_397_sram_blwl_out ; -wire [437:437] mux_1level_tapbuf_size2_397_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_397_configbus0[437:437] = sram_blwl_bl[437:437] ; -assign mux_1level_tapbuf_size2_397_configbus1[437:437] = sram_blwl_wl[437:437] ; -wire [437:437] mux_1level_tapbuf_size2_397_configbus0_b; -assign mux_1level_tapbuf_size2_397_configbus0_b[437:437] = sram_blwl_blb[437:437] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_397_ (mux_1level_tapbuf_size2_397_inbus, chanx_1__1__out_95_ , mux_1level_tapbuf_size2_397_sram_blwl_out[437:437] , -mux_1level_tapbuf_size2_397_sram_blwl_outb[437:437] ); -//----- SRAM bits for MUX[397], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_437_ (mux_1level_tapbuf_size2_397_sram_blwl_out[437:437] ,mux_1level_tapbuf_size2_397_sram_blwl_out[437:437] ,mux_1level_tapbuf_size2_397_sram_blwl_outb[437:437] ,mux_1level_tapbuf_size2_397_configbus0[437:437], mux_1level_tapbuf_size2_397_configbus1[437:437] , mux_1level_tapbuf_size2_397_configbus0_b[437:437] ); -wire [0:1] mux_1level_tapbuf_size2_398_inbus; -assign mux_1level_tapbuf_size2_398_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_398_inbus[1] = chany_1__1__in_94_ ; -wire [438:438] mux_1level_tapbuf_size2_398_configbus0; -wire [438:438] mux_1level_tapbuf_size2_398_configbus1; -wire [438:438] mux_1level_tapbuf_size2_398_sram_blwl_out ; -wire [438:438] mux_1level_tapbuf_size2_398_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_398_configbus0[438:438] = sram_blwl_bl[438:438] ; -assign mux_1level_tapbuf_size2_398_configbus1[438:438] = sram_blwl_wl[438:438] ; -wire [438:438] mux_1level_tapbuf_size2_398_configbus0_b; -assign mux_1level_tapbuf_size2_398_configbus0_b[438:438] = sram_blwl_blb[438:438] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_398_ (mux_1level_tapbuf_size2_398_inbus, chanx_1__1__out_97_ , mux_1level_tapbuf_size2_398_sram_blwl_out[438:438] , -mux_1level_tapbuf_size2_398_sram_blwl_outb[438:438] ); -//----- SRAM bits for MUX[398], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_438_ (mux_1level_tapbuf_size2_398_sram_blwl_out[438:438] ,mux_1level_tapbuf_size2_398_sram_blwl_out[438:438] ,mux_1level_tapbuf_size2_398_sram_blwl_outb[438:438] ,mux_1level_tapbuf_size2_398_configbus0[438:438], mux_1level_tapbuf_size2_398_configbus1[438:438] , mux_1level_tapbuf_size2_398_configbus0_b[438:438] ); -wire [0:1] mux_1level_tapbuf_size2_399_inbus; -assign mux_1level_tapbuf_size2_399_inbus[0] = grid_1__2__pin_0__2__13_; -assign mux_1level_tapbuf_size2_399_inbus[1] = chany_1__1__in_96_ ; -wire [439:439] mux_1level_tapbuf_size2_399_configbus0; -wire [439:439] mux_1level_tapbuf_size2_399_configbus1; -wire [439:439] mux_1level_tapbuf_size2_399_sram_blwl_out ; -wire [439:439] mux_1level_tapbuf_size2_399_sram_blwl_outb ; -assign mux_1level_tapbuf_size2_399_configbus0[439:439] = sram_blwl_bl[439:439] ; -assign mux_1level_tapbuf_size2_399_configbus1[439:439] = sram_blwl_wl[439:439] ; -wire [439:439] mux_1level_tapbuf_size2_399_configbus0_b; -assign mux_1level_tapbuf_size2_399_configbus0_b[439:439] = sram_blwl_blb[439:439] ; -mux_1level_tapbuf_size2 mux_1level_tapbuf_size2_399_ (mux_1level_tapbuf_size2_399_inbus, chanx_1__1__out_99_ , mux_1level_tapbuf_size2_399_sram_blwl_out[439:439] , -mux_1level_tapbuf_size2_399_sram_blwl_outb[439:439] ); -//----- SRAM bits for MUX[399], level=1, select_path_id=0. ----- -//----- From LSB(LEFT) TO MSB (RIGHT) ----- -//-----1----- -sram6T_blwl sram_blwl_439_ (mux_1level_tapbuf_size2_399_sram_blwl_out[439:439] ,mux_1level_tapbuf_size2_399_sram_blwl_out[439:439] ,mux_1level_tapbuf_size2_399_sram_blwl_outb[439:439] ,mux_1level_tapbuf_size2_399_configbus0[439:439], mux_1level_tapbuf_size2_399_configbus1[439:439] , mux_1level_tapbuf_size2_399_configbus0_b[439:439] ); -endmodule -//----- END Verilog Module of Switch Box[1][1] ----- - diff --git a/examples/verilog_test_example_2/sub_module/decoders.v b/examples/verilog_test_example_2/sub_module/decoders.v deleted file mode 100644 index 518da443f..000000000 --- a/examples/verilog_test_example_2/sub_module/decoders.v +++ /dev/null @@ -1,40 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Verilog Decoders -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- BL Decoder convert 6 bits to binary 52 bits ----- -module bl_decoder6to52 ( -input wire enable, -input wire [5:0] addr_in, -input wire data_in, -output reg [0:51] addr_out -); -always@(addr_out,addr_in,enable, data_in) -begin - addr_out = 52'bz; - if (1'b1 == enable) begin - addr_out[addr_in] = data_in; - end -end -endmodule -//----- WL Decoder convert 6 bits to binary 52 bits ----- -module wl_decoder6to52 ( -input wire enable, -input wire [5:0] addr_in, -output reg [0:51] addr_out -); -always@(addr_out,addr_in,enable) -begin - addr_out = 52'b0; - if (1'b1 == enable) begin - addr_out[addr_in] = 1'b1; - end -end -endmodule diff --git a/examples/verilog_test_example_2/sub_module/inv_buf_passgate.v b/examples/verilog_test_example_2/sub_module/inv_buf_passgate.v deleted file mode 100644 index 8d2c9cf13..000000000 --- a/examples/verilog_test_example_2/sub_module/inv_buf_passgate.v +++ /dev/null @@ -1,45 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Essential gates -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//----- Verilog module for INVTX1 ----- -module INVTX1 ( -input in, -output out -); -assign out = ~in; -endmodule - -//----- Verilog module for buf4 ----- -module buf4 ( -input in, -output out -); -assign out = in; -endmodule - -//----- Verilog module for tap_buf4 ----- -module tap_buf4 ( -input in, -output out -); -assign out = ~in; -endmodule - -//----- Verilog module for TGATE ----- -module TGATE ( -input in, -input sel, -input selb, -output out -); -assign out = sel? in : 1'bz; -endmodule - diff --git a/examples/verilog_test_example_2/sub_module/luts.v b/examples/verilog_test_example_2/sub_module/luts.v deleted file mode 100644 index 6e2c8005c..000000000 --- a/examples/verilog_test_example_2/sub_module/luts.v +++ /dev/null @@ -1,23 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Look-Up Tables -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//-----LUT module, verilog_model_name=lut6 ----- -module lut6 (input wire [0:5] in, -output wire [0:0] out, -input wire [0:63] sram_out, -input wire [0:63] sram_outb -); - wire [0:5] in_b; - assign in_b = ~ in; - lut6_mux lut6_mux_0_ ( sram_out, out, in, in_b); -endmodule -//-----END LUT module, verilog_model_name=lut6 ----- - diff --git a/examples/verilog_test_example_2/sub_module/muxes.v b/examples/verilog_test_example_2/sub_module/muxes.v deleted file mode 100644 index 9dbae1baa..000000000 --- a/examples/verilog_test_example_2/sub_module/muxes.v +++ /dev/null @@ -1,387 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: MUXes used in FPGA -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//---- Structural Verilog for CMOS MUX basis module: mux_2level_tapbuf_size16_basis ----- -module mux_2level_tapbuf_size16_basis ( -input [0:3] in, -output out, -input [0:3] mem, -input [0:3] mem_inv); -//---- Structure-level description ----- - TGATE TGATE_0 (in[0], mem[0], mem_inv[0], out); - TGATE TGATE_1 (in[1], mem[1], mem_inv[1], out); - TGATE TGATE_2 (in[2], mem[2], mem_inv[2], out); - TGATE TGATE_3 (in[3], mem[3], mem_inv[3], out); -endmodule -//---- END Structural Verilog CMOS MUX basis module: mux_2level_tapbuf_size16_basis ----- - -//----- CMOS MUX info: spice_model_name=mux_2level_tapbuf, size=16, structure: multi-level ----- -module mux_2level_tapbuf_size16 (input wire [0:15] in, -output wire out, -input wire [0:7] sram, -input wire [0:7] sram_inv -); -wire [0:15] mux2_l2_in; -wire [0:3] mux2_l1_in; -wire [0:0] mux2_l0_in; -mux_2level_tapbuf_size16_basis mux_basis_no0 (mux2_l2_in[0:3], mux2_l1_in[0], sram[4:7], sram_inv[4:7] ); - -mux_2level_tapbuf_size16_basis mux_basis_no1 (mux2_l2_in[4:7], mux2_l1_in[1], sram[4:7], sram_inv[4:7] ); - -mux_2level_tapbuf_size16_basis mux_basis_no2 (mux2_l2_in[8:11], mux2_l1_in[2], sram[4:7], sram_inv[4:7] ); - -mux_2level_tapbuf_size16_basis mux_basis_no3 (mux2_l2_in[12:15], mux2_l1_in[3], sram[4:7], sram_inv[4:7] ); - -mux_2level_tapbuf_size16_basis mux_basis_no4 (mux2_l1_in[0:3], mux2_l0_in[0], sram[0:3], sram_inv[0:3] ); - -INVTX1 inv0 (in[0], mux2_l2_in[0]); -INVTX1 inv1 (in[1], mux2_l2_in[1]); -INVTX1 inv2 (in[2], mux2_l2_in[2]); -INVTX1 inv3 (in[3], mux2_l2_in[3]); -INVTX1 inv4 (in[4], mux2_l2_in[4]); -INVTX1 inv5 (in[5], mux2_l2_in[5]); -INVTX1 inv6 (in[6], mux2_l2_in[6]); -INVTX1 inv7 (in[7], mux2_l2_in[7]); -INVTX1 inv8 (in[8], mux2_l2_in[8]); -INVTX1 inv9 (in[9], mux2_l2_in[9]); -INVTX1 inv10 (in[10], mux2_l2_in[10]); -INVTX1 inv11 (in[11], mux2_l2_in[11]); -INVTX1 inv12 (in[12], mux2_l2_in[12]); -INVTX1 inv13 (in[13], mux2_l2_in[13]); -INVTX1 inv14 (in[14], mux2_l2_in[14]); -INVTX1 inv15 (in[15], mux2_l2_in[15]); -tap_buf4 buf_out (mux2_l0_in[0], out ); -endmodule -//----- END CMOS MUX info: spice_model_name=mux_2level_tapbuf, size=16 ----- - - -//---- Structural Verilog for CMOS MUX basis module: lut6_size64_basis ----- -module lut6_size64_basis ( -input [0:1] in, -output out, -input [0:0] mem, -input [0:0] mem_inv); -//---- Structure-level description ----- - TGATE TGATE_0 (in[0], mem[0], mem_inv[0], out); - TGATE TGATE_1 (in[1], mem_inv[0], mem[0], out); -endmodule -//---- END Structural Verilog CMOS MUX basis module: lut6_size64_basis ----- - -//------ CMOS MUX info: spice_model_name= lut6_MUX, size=64 ----- -module lut6_mux( -input wire [0:63] in, -output wire out, -input wire [0:5] sram, -input wire [0:5] sram_inv -); -wire [0:63] mux2_l6_in; -wire [0:31] mux2_l5_in; -wire [0:15] mux2_l4_in; -wire [0:7] mux2_l3_in; -wire [0:3] mux2_l2_in; -wire [0:1] mux2_l1_in; -wire [0:0] mux2_l0_in; -lut6_size64_basis mux_basis_no0 (mux2_l6_in[0:1], mux2_l5_in[0], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no1 (mux2_l6_in[2:3], mux2_l5_in[1], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no2 (mux2_l6_in[4:5], mux2_l5_in[2], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no3 (mux2_l6_in[6:7], mux2_l5_in[3], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no4 (mux2_l6_in[8:9], mux2_l5_in[4], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no5 (mux2_l6_in[10:11], mux2_l5_in[5], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no6 (mux2_l6_in[12:13], mux2_l5_in[6], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no7 (mux2_l6_in[14:15], mux2_l5_in[7], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no8 (mux2_l6_in[16:17], mux2_l5_in[8], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no9 (mux2_l6_in[18:19], mux2_l5_in[9], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no10 (mux2_l6_in[20:21], mux2_l5_in[10], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no11 (mux2_l6_in[22:23], mux2_l5_in[11], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no12 (mux2_l6_in[24:25], mux2_l5_in[12], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no13 (mux2_l6_in[26:27], mux2_l5_in[13], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no14 (mux2_l6_in[28:29], mux2_l5_in[14], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no15 (mux2_l6_in[30:31], mux2_l5_in[15], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no16 (mux2_l6_in[32:33], mux2_l5_in[16], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no17 (mux2_l6_in[34:35], mux2_l5_in[17], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no18 (mux2_l6_in[36:37], mux2_l5_in[18], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no19 (mux2_l6_in[38:39], mux2_l5_in[19], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no20 (mux2_l6_in[40:41], mux2_l5_in[20], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no21 (mux2_l6_in[42:43], mux2_l5_in[21], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no22 (mux2_l6_in[44:45], mux2_l5_in[22], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no23 (mux2_l6_in[46:47], mux2_l5_in[23], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no24 (mux2_l6_in[48:49], mux2_l5_in[24], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no25 (mux2_l6_in[50:51], mux2_l5_in[25], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no26 (mux2_l6_in[52:53], mux2_l5_in[26], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no27 (mux2_l6_in[54:55], mux2_l5_in[27], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no28 (mux2_l6_in[56:57], mux2_l5_in[28], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no29 (mux2_l6_in[58:59], mux2_l5_in[29], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no30 (mux2_l6_in[60:61], mux2_l5_in[30], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no31 (mux2_l6_in[62:63], mux2_l5_in[31], sram[0], sram_inv[0]); -lut6_size64_basis mux_basis_no32 (mux2_l5_in[0:1], mux2_l4_in[0], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no33 (mux2_l5_in[2:3], mux2_l4_in[1], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no34 (mux2_l5_in[4:5], mux2_l4_in[2], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no35 (mux2_l5_in[6:7], mux2_l4_in[3], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no36 (mux2_l5_in[8:9], mux2_l4_in[4], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no37 (mux2_l5_in[10:11], mux2_l4_in[5], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no38 (mux2_l5_in[12:13], mux2_l4_in[6], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no39 (mux2_l5_in[14:15], mux2_l4_in[7], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no40 (mux2_l5_in[16:17], mux2_l4_in[8], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no41 (mux2_l5_in[18:19], mux2_l4_in[9], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no42 (mux2_l5_in[20:21], mux2_l4_in[10], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no43 (mux2_l5_in[22:23], mux2_l4_in[11], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no44 (mux2_l5_in[24:25], mux2_l4_in[12], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no45 (mux2_l5_in[26:27], mux2_l4_in[13], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no46 (mux2_l5_in[28:29], mux2_l4_in[14], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no47 (mux2_l5_in[30:31], mux2_l4_in[15], sram[1], sram_inv[1]); -lut6_size64_basis mux_basis_no48 (mux2_l4_in[0:1], mux2_l3_in[0], sram[2], sram_inv[2]); -lut6_size64_basis mux_basis_no49 (mux2_l4_in[2:3], mux2_l3_in[1], sram[2], sram_inv[2]); -lut6_size64_basis mux_basis_no50 (mux2_l4_in[4:5], mux2_l3_in[2], sram[2], sram_inv[2]); -lut6_size64_basis mux_basis_no51 (mux2_l4_in[6:7], mux2_l3_in[3], sram[2], sram_inv[2]); -lut6_size64_basis mux_basis_no52 (mux2_l4_in[8:9], mux2_l3_in[4], sram[2], sram_inv[2]); -lut6_size64_basis mux_basis_no53 (mux2_l4_in[10:11], mux2_l3_in[5], sram[2], sram_inv[2]); -lut6_size64_basis mux_basis_no54 (mux2_l4_in[12:13], mux2_l3_in[6], sram[2], sram_inv[2]); -lut6_size64_basis mux_basis_no55 (mux2_l4_in[14:15], mux2_l3_in[7], sram[2], sram_inv[2]); -lut6_size64_basis mux_basis_no56 (mux2_l3_in[0:1], mux2_l2_in[0], sram[3], sram_inv[3]); -lut6_size64_basis mux_basis_no57 (mux2_l3_in[2:3], mux2_l2_in[1], sram[3], sram_inv[3]); -lut6_size64_basis mux_basis_no58 (mux2_l3_in[4:5], mux2_l2_in[2], sram[3], sram_inv[3]); -lut6_size64_basis mux_basis_no59 (mux2_l3_in[6:7], mux2_l2_in[3], sram[3], sram_inv[3]); -lut6_size64_basis mux_basis_no60 (mux2_l2_in[0:1], mux2_l1_in[0], sram[4], sram_inv[4]); -lut6_size64_basis mux_basis_no61 (mux2_l2_in[2:3], mux2_l1_in[1], sram[4], sram_inv[4]); -lut6_size64_basis mux_basis_no62 (mux2_l1_in[0:1], mux2_l0_in[0], sram[5], sram_inv[5]); -INVTX1 inv0 (in[0], mux2_l6_in[0]); -INVTX1 inv1 (in[1], mux2_l6_in[1]); -INVTX1 inv2 (in[2], mux2_l6_in[2]); -INVTX1 inv3 (in[3], mux2_l6_in[3]); -INVTX1 inv4 (in[4], mux2_l6_in[4]); -INVTX1 inv5 (in[5], mux2_l6_in[5]); -INVTX1 inv6 (in[6], mux2_l6_in[6]); -INVTX1 inv7 (in[7], mux2_l6_in[7]); -INVTX1 inv8 (in[8], mux2_l6_in[8]); -INVTX1 inv9 (in[9], mux2_l6_in[9]); -INVTX1 inv10 (in[10], mux2_l6_in[10]); -INVTX1 inv11 (in[11], mux2_l6_in[11]); -INVTX1 inv12 (in[12], mux2_l6_in[12]); -INVTX1 inv13 (in[13], mux2_l6_in[13]); -INVTX1 inv14 (in[14], mux2_l6_in[14]); -INVTX1 inv15 (in[15], mux2_l6_in[15]); -INVTX1 inv16 (in[16], mux2_l6_in[16]); -INVTX1 inv17 (in[17], mux2_l6_in[17]); -INVTX1 inv18 (in[18], mux2_l6_in[18]); -INVTX1 inv19 (in[19], mux2_l6_in[19]); -INVTX1 inv20 (in[20], mux2_l6_in[20]); -INVTX1 inv21 (in[21], mux2_l6_in[21]); -INVTX1 inv22 (in[22], mux2_l6_in[22]); -INVTX1 inv23 (in[23], mux2_l6_in[23]); -INVTX1 inv24 (in[24], mux2_l6_in[24]); -INVTX1 inv25 (in[25], mux2_l6_in[25]); -INVTX1 inv26 (in[26], mux2_l6_in[26]); -INVTX1 inv27 (in[27], mux2_l6_in[27]); -INVTX1 inv28 (in[28], mux2_l6_in[28]); -INVTX1 inv29 (in[29], mux2_l6_in[29]); -INVTX1 inv30 (in[30], mux2_l6_in[30]); -INVTX1 inv31 (in[31], mux2_l6_in[31]); -INVTX1 inv32 (in[32], mux2_l6_in[32]); -INVTX1 inv33 (in[33], mux2_l6_in[33]); -INVTX1 inv34 (in[34], mux2_l6_in[34]); -INVTX1 inv35 (in[35], mux2_l6_in[35]); -INVTX1 inv36 (in[36], mux2_l6_in[36]); -INVTX1 inv37 (in[37], mux2_l6_in[37]); -INVTX1 inv38 (in[38], mux2_l6_in[38]); -INVTX1 inv39 (in[39], mux2_l6_in[39]); -INVTX1 inv40 (in[40], mux2_l6_in[40]); -INVTX1 inv41 (in[41], mux2_l6_in[41]); -INVTX1 inv42 (in[42], mux2_l6_in[42]); -INVTX1 inv43 (in[43], mux2_l6_in[43]); -INVTX1 inv44 (in[44], mux2_l6_in[44]); -INVTX1 inv45 (in[45], mux2_l6_in[45]); -INVTX1 inv46 (in[46], mux2_l6_in[46]); -INVTX1 inv47 (in[47], mux2_l6_in[47]); -INVTX1 inv48 (in[48], mux2_l6_in[48]); -INVTX1 inv49 (in[49], mux2_l6_in[49]); -INVTX1 inv50 (in[50], mux2_l6_in[50]); -INVTX1 inv51 (in[51], mux2_l6_in[51]); -INVTX1 inv52 (in[52], mux2_l6_in[52]); -INVTX1 inv53 (in[53], mux2_l6_in[53]); -INVTX1 inv54 (in[54], mux2_l6_in[54]); -INVTX1 inv55 (in[55], mux2_l6_in[55]); -INVTX1 inv56 (in[56], mux2_l6_in[56]); -INVTX1 inv57 (in[57], mux2_l6_in[57]); -INVTX1 inv58 (in[58], mux2_l6_in[58]); -INVTX1 inv59 (in[59], mux2_l6_in[59]); -INVTX1 inv60 (in[60], mux2_l6_in[60]); -INVTX1 inv61 (in[61], mux2_l6_in[61]); -INVTX1 inv62 (in[62], mux2_l6_in[62]); -INVTX1 inv63 (in[63], mux2_l6_in[63]); -INVTX1 inv_out (mux2_l0_in[0], out ); -endmodule -//----- END CMOS MUX info: spice_model_name=lut6, size=64 ----- - - -//---- Structural Verilog for CMOS MUX basis module: mux_2level_size50_basis ----- -module mux_2level_size50_basis ( -input [0:7] in, -output out, -input [0:7] mem, -input [0:7] mem_inv); -//---- Structure-level description ----- - TGATE TGATE_0 (in[0], mem[0], mem_inv[0], out); - TGATE TGATE_1 (in[1], mem[1], mem_inv[1], out); - TGATE TGATE_2 (in[2], mem[2], mem_inv[2], out); - TGATE TGATE_3 (in[3], mem[3], mem_inv[3], out); - TGATE TGATE_4 (in[4], mem[4], mem_inv[4], out); - TGATE TGATE_5 (in[5], mem[5], mem_inv[5], out); - TGATE TGATE_6 (in[6], mem[6], mem_inv[6], out); - TGATE TGATE_7 (in[7], mem[7], mem_inv[7], out); -endmodule -//---- END Structural Verilog CMOS MUX basis module: mux_2level_size50_basis ----- - -//----- CMOS MUX info: spice_model_name=mux_2level, size=50, structure: multi-level ----- -module mux_2level_size50 (input wire [0:49] in, -output wire out, -input wire [0:15] sram, -input wire [0:15] sram_inv -); -wire [0:47] mux2_l2_in; -wire [0:7] mux2_l1_in; -wire [0:0] mux2_l0_in; -mux_2level_size50_basis mux_basis_no0 (mux2_l2_in[0:7], mux2_l1_in[0], sram[8:15], sram_inv[8:15] ); - -mux_2level_size50_basis mux_basis_no1 (mux2_l2_in[8:15], mux2_l1_in[1], sram[8:15], sram_inv[8:15] ); - -mux_2level_size50_basis mux_basis_no2 (mux2_l2_in[16:23], mux2_l1_in[2], sram[8:15], sram_inv[8:15] ); - -mux_2level_size50_basis mux_basis_no3 (mux2_l2_in[24:31], mux2_l1_in[3], sram[8:15], sram_inv[8:15] ); - -mux_2level_size50_basis mux_basis_no4 (mux2_l2_in[32:39], mux2_l1_in[4], sram[8:15], sram_inv[8:15] ); - -mux_2level_size50_basis mux_basis_no5 (mux2_l2_in[40:47], mux2_l1_in[5], sram[8:15], sram_inv[8:15] ); - -mux_2level_size50_basis mux_basis_no6 (mux2_l1_in[0:7], mux2_l0_in[0], sram[0:7], sram_inv[0:7] ); - -INVTX1 inv0 (in[0], mux2_l2_in[0]); -INVTX1 inv1 (in[1], mux2_l2_in[1]); -INVTX1 inv2 (in[2], mux2_l2_in[2]); -INVTX1 inv3 (in[3], mux2_l2_in[3]); -INVTX1 inv4 (in[4], mux2_l2_in[4]); -INVTX1 inv5 (in[5], mux2_l2_in[5]); -INVTX1 inv6 (in[6], mux2_l2_in[6]); -INVTX1 inv7 (in[7], mux2_l2_in[7]); -INVTX1 inv8 (in[8], mux2_l2_in[8]); -INVTX1 inv9 (in[9], mux2_l2_in[9]); -INVTX1 inv10 (in[10], mux2_l2_in[10]); -INVTX1 inv11 (in[11], mux2_l2_in[11]); -INVTX1 inv12 (in[12], mux2_l2_in[12]); -INVTX1 inv13 (in[13], mux2_l2_in[13]); -INVTX1 inv14 (in[14], mux2_l2_in[14]); -INVTX1 inv15 (in[15], mux2_l2_in[15]); -INVTX1 inv16 (in[16], mux2_l2_in[16]); -INVTX1 inv17 (in[17], mux2_l2_in[17]); -INVTX1 inv18 (in[18], mux2_l2_in[18]); -INVTX1 inv19 (in[19], mux2_l2_in[19]); -INVTX1 inv20 (in[20], mux2_l2_in[20]); -INVTX1 inv21 (in[21], mux2_l2_in[21]); -INVTX1 inv22 (in[22], mux2_l2_in[22]); -INVTX1 inv23 (in[23], mux2_l2_in[23]); -INVTX1 inv24 (in[24], mux2_l2_in[24]); -INVTX1 inv25 (in[25], mux2_l2_in[25]); -INVTX1 inv26 (in[26], mux2_l2_in[26]); -INVTX1 inv27 (in[27], mux2_l2_in[27]); -INVTX1 inv28 (in[28], mux2_l2_in[28]); -INVTX1 inv29 (in[29], mux2_l2_in[29]); -INVTX1 inv30 (in[30], mux2_l2_in[30]); -INVTX1 inv31 (in[31], mux2_l2_in[31]); -INVTX1 inv32 (in[32], mux2_l2_in[32]); -INVTX1 inv33 (in[33], mux2_l2_in[33]); -INVTX1 inv34 (in[34], mux2_l2_in[34]); -INVTX1 inv35 (in[35], mux2_l2_in[35]); -INVTX1 inv36 (in[36], mux2_l2_in[36]); -INVTX1 inv37 (in[37], mux2_l2_in[37]); -INVTX1 inv38 (in[38], mux2_l2_in[38]); -INVTX1 inv39 (in[39], mux2_l2_in[39]); -INVTX1 inv40 (in[40], mux2_l2_in[40]); -INVTX1 inv41 (in[41], mux2_l2_in[41]); -INVTX1 inv42 (in[42], mux2_l2_in[42]); -INVTX1 inv43 (in[43], mux2_l2_in[43]); -INVTX1 inv44 (in[44], mux2_l2_in[44]); -INVTX1 inv45 (in[45], mux2_l2_in[45]); -INVTX1 inv46 (in[46], mux2_l2_in[46]); -INVTX1 inv47 (in[47], mux2_l2_in[47]); -INVTX1 inv48 (in[48], mux2_l1_in[6]); -INVTX1 inv49 (in[49], mux2_l1_in[7]); -INVTX1 inv_out (mux2_l0_in[0], out ); -endmodule -//----- END CMOS MUX info: spice_model_name=mux_2level, size=50 ----- - - -//---- Structural Verilog for CMOS MUX basis module: mux_1level_tapbuf_size3_basis ----- -module mux_1level_tapbuf_size3_basis ( -input [0:2] in, -output out, -input [0:2] mem, -input [0:2] mem_inv); -//---- Structure-level description ----- - TGATE TGATE_0 (in[0], mem[0], mem_inv[0], out); - TGATE TGATE_1 (in[1], mem[1], mem_inv[1], out); - TGATE TGATE_2 (in[2], mem[2], mem_inv[2], out); -endmodule -//---- END Structural Verilog CMOS MUX basis module: mux_1level_tapbuf_size3_basis ----- - -//----- CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=3, structure: one-level ----- -module mux_1level_tapbuf_size3 (input wire [0:2] in, -output wire out, -input wire [0:2] sram, -input wire [0:2] sram_inv -); -wire [0:2] mux2_l1_in; -wire [0:0] mux2_l0_in; -mux_1level_tapbuf_size3_basis mux_basis ( -//----- MUX inputs ----- -mux2_l1_in[0:2], mux2_l0_in[0], -//----- SRAM ports ----- -sram[0:2], sram_inv[0:2] -); -INVTX1 inv0 (in[0], mux2_l1_in[0]); -INVTX1 inv1 (in[1], mux2_l1_in[1]); -INVTX1 inv2 (in[2], mux2_l1_in[2]); -tap_buf4 buf_out (mux2_l0_in[0], out ); -endmodule -//----- END CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=3 ----- - - -//---- Structural Verilog for CMOS MUX basis module: mux_1level_tapbuf_size2_basis ----- -module mux_1level_tapbuf_size2_basis ( -input [0:1] in, -output out, -input [0:0] mem, -input [0:0] mem_inv); -//---- Structure-level description ----- - TGATE TGATE_0 (in[0], mem[0], mem_inv[0], out); - TGATE TGATE_1 (in[1], mem_inv[0], mem[0], out); -endmodule -//---- END Structural Verilog CMOS MUX basis module: mux_1level_tapbuf_size2_basis ----- - -//----- CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=2, structure: one-level ----- -module mux_1level_tapbuf_size2 (input wire [0:1] in, -output wire out, -input wire [0:0] sram, -input wire [0:0] sram_inv -); -wire [0:1] mux2_l1_in; -wire [0:0] mux2_l0_in; -mux_1level_tapbuf_size2_basis mux_basis ( -//----- MUX inputs ----- -mux2_l1_in[0:1], mux2_l0_in[0], -//----- SRAM ports ----- -sram[0:0], sram_inv[0:0] -); -INVTX1 inv0 (in[0], mux2_l1_in[0]); -INVTX1 inv1 (in[1], mux2_l1_in[1]); -tap_buf4 buf_out (mux2_l0_in[0], out ); -endmodule -//----- END CMOS MUX info: spice_model_name=mux_1level_tapbuf, size=2 ----- - - diff --git a/examples/verilog_test_example_2/sub_module/wires.v b/examples/verilog_test_example_2/sub_module/wires.v deleted file mode 100644 index f75975d49..000000000 --- a/examples/verilog_test_example_2/sub_module/wires.v +++ /dev/null @@ -1,43 +0,0 @@ -//------------------------------------------- -// FPGA Synthesizable Verilog Netlist -// Description: Wires -// Author: Xifan TANG -// Organization: EPFL/IC/LSI -// Date: Thu Nov 15 14:26:09 2018 - -//------------------------------------------- -//----- Time scale ----- -`timescale 1ns / 1ps - -//-----Wire module, verilog_model_name=direct_interc ----- -module direct_interc ( -input wire in, output wire out); - assign out = in; -endmodule -//-----END Wire module, verilog_model_name=direct_interc ----- - -//----- Wire models for segments in routing ----- -//-----Wire module, verilog_model_name=chan_segment ----- -module chan_segment_seg0 ( -input wire in, output wire out, output wire mid_out); - assign out = in; - assign mid_out = in; -endmodule -//-----END Wire module, verilog_model_name=chan_segment ----- - -//-----Wire module, verilog_model_name=chan_segment ----- -module chan_segment_seg1 ( -input wire in, output wire out, output wire mid_out); - assign out = in; - assign mid_out = in; -endmodule -//-----END Wire module, verilog_model_name=chan_segment ----- - -//-----Wire module, verilog_model_name=chan_segment ----- -module chan_segment_seg2 ( -input wire in, output wire out, output wire mid_out); - assign out = in; - assign mid_out = in; -endmodule -//-----END Wire module, verilog_model_name=chan_segment ----- - diff --git a/tutorials/tutorial.md b/tutorials/tutorial.md new file mode 100644 index 000000000..1f71d7d41 --- /dev/null +++ b/tutorials/tutorial.md @@ -0,0 +1,66 @@ +#Tutorial + +This tutorial purpose it to clarify how to use: +1. The full flow using fpga_flow.pl script +2. Architecture customization + +Some keywords will be used during this tutorial: +- OPENFPGAPATHKEYWORD: it refer to OpenFPGA full path + +##1. FPGA flow + +OpenFPGA repository is organized as follow: + - abc: open source synthesys tool + - ace2: abc extension generating .act files + - vpr7_x2p: source of modified vpr + - yosys: opensource synthesys tool + +fpga_flow.pl is saved in OPENFPGAPATHKEYWORD/fpga_flow/scripts. If we look in this folder, we can find some other scripts as: + - pro_blif.pl: rewrite a blif which has only 3 members in a .latch module + - rewrite_path_in_file.pl: target a keyword in a file and replace it + +*Any script provides a help if launch without argument* + +fpga_flow.pl has dependencies which need to be configured. They are: + - configuration file, which provides dependencies path and flow type + - benchmark list file + +###Configuration file + +In this file paths have to be full path. Relative path could lead to errors. +The file is organized in 3 parts: + - dir_path: provides all the tools and repository path + - flow_conf: provides information on how the flow run + - csv_tags: *to complete* + +While empty the file is as follow: + +[dir_path] +script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts +benchmark_dir = *Path to the folder containing all sources of the design* +yosys_path = OPENFPGAPATHKEYWORD/yosys +odin2_path = not_used +cirkit_path = not_used +abc_path = OPENFPGAPATHKEYWORD/abc +abc_mccl_path = OPENFPGAPATHKEYWORD/abc +abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc +mpack1_path = not_used +m2net_path = not_used +mpack2_path = not_used +vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr +rpt_dir = *wherever tou want logs to be saved* +ace_path = OPENFPGAPATHKEYWORD/ace2 + +[flow_conf] +flow_type = yosys_vpr *to use verilog input* +vpr_arch = *wherever the architecture file is saved* +mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK +m2net_conf = not_used +mpack2_arch = not_used +power_tech_xml = *wherever the xml tech file is saved* + +[csv_tags] *to complete* +mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: +mpack2_tags = BLE Number:|BLE Fill Rate: +vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: +vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff From c1ae3059c45a62c5ea4e40165e6e2fc3dcfb2e4e Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 8 Jul 2019 10:32:39 -0600 Subject: [PATCH 41/84] Correct synthax error --- tutorials/tutorial.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tutorials/tutorial.md b/tutorials/tutorial.md index 1f71d7d41..fbe95d86b 100644 --- a/tutorials/tutorial.md +++ b/tutorials/tutorial.md @@ -1,4 +1,4 @@ -#Tutorial +# Tutorial This tutorial purpose it to clarify how to use: 1. The full flow using fpga_flow.pl script @@ -7,7 +7,7 @@ This tutorial purpose it to clarify how to use: Some keywords will be used during this tutorial: - OPENFPGAPATHKEYWORD: it refer to OpenFPGA full path -##1. FPGA flow +## 1. FPGA flow OpenFPGA repository is organized as follow: - abc: open source synthesys tool @@ -25,7 +25,7 @@ fpga_flow.pl has dependencies which need to be configured. They are: - configuration file, which provides dependencies path and flow type - benchmark list file -###Configuration file +### Configuration file In this file paths have to be full path. Relative path could lead to errors. The file is organized in 3 parts: From 9f16bb59982af0fb5e34fcbb323dd4f9faf048dc Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 8 Jul 2019 10:36:58 -0600 Subject: [PATCH 42/84] Synthax correction 2 -> new line --- tutorials/tutorial.md | 58 ++++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 28 deletions(-) diff --git a/tutorials/tutorial.md b/tutorials/tutorial.md index fbe95d86b..3c88959cf 100644 --- a/tutorials/tutorial.md +++ b/tutorials/tutorial.md @@ -27,7 +27,7 @@ fpga_flow.pl has dependencies which need to be configured. They are: ### Configuration file -In this file paths have to be full path. Relative path could lead to errors. +In this file paths have to be full path. Relative path could lead to errors.
The file is organized in 3 parts: - dir_path: provides all the tools and repository path - flow_conf: provides information on how the flow run @@ -35,32 +35,34 @@ The file is organized in 3 parts: While empty the file is as follow: -[dir_path] -script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts -benchmark_dir = *Path to the folder containing all sources of the design* -yosys_path = OPENFPGAPATHKEYWORD/yosys -odin2_path = not_used -cirkit_path = not_used -abc_path = OPENFPGAPATHKEYWORD/abc -abc_mccl_path = OPENFPGAPATHKEYWORD/abc -abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc -mpack1_path = not_used -m2net_path = not_used -mpack2_path = not_used -vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr -rpt_dir = *wherever tou want logs to be saved* -ace_path = OPENFPGAPATHKEYWORD/ace2 +[dir_path]
+script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts
+benchmark_dir = *Path to the folder containing all sources of the design*
+yosys_path = OPENFPGAPATHKEYWORD/yosys
+odin2_path = not_used
+cirkit_path = not_used
+abc_path = OPENFPGAPATHKEYWORD/abc
+abc_mccl_path = OPENFPGAPATHKEYWORD/abc
+abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc
+mpack1_path = not_used
+m2net_path = not_used
+mpack2_path = not_used
+vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr
+rpt_dir = *wherever tou want logs to be saved*
+ace_path = OPENFPGAPATHKEYWORD/ace2
+ +[flow_conf]
+flow_type = yosys_vpr *to use verilog input*
+vpr_arch = *wherever the architecture file is saved*
+mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
+m2net_conf = not_used
+mpack2_arch = not_used
+power_tech_xml = *wherever the xml tech file is saved*
+ +[csv_tags] *to complete*
+mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
+mpack2_tags = BLE Number:|BLE Fill Rate:
+vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
+vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff
-[flow_conf] -flow_type = yosys_vpr *to use verilog input* -vpr_arch = *wherever the architecture file is saved* -mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = not_used -mpack2_arch = not_used -power_tech_xml = *wherever the xml tech file is saved* -[csv_tags] *to complete* -mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: -mpack2_tags = BLE Number:|BLE Fill Rate: -vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: -vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff From f1ccf85bb93b64f75011caf02ef24d56b0efd9c6 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 8 Jul 2019 11:51:04 -0600 Subject: [PATCH 43/84] Update tutorial -> fpga_flow explanation --- tutorials/tutorial.md | 57 ++++++++++++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 17 deletions(-) diff --git a/tutorials/tutorial.md b/tutorials/tutorial.md index 3c88959cf..e933702a6 100644 --- a/tutorials/tutorial.md +++ b/tutorials/tutorial.md @@ -5,39 +5,49 @@ This tutorial purpose it to clarify how to use: 2. Architecture customization Some keywords will be used during this tutorial: -- OPENFPGAPATHKEYWORD: it refer to OpenFPGA full path +* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path + +### Folder organization + +OpenFPGA repository is organized as follow: +* **abc**: open source synthesys tool +* **ace2**: abc extension generating .act files +* **vpr7_x2p**: sources of modified vpr +* **yosys**: opensource synthesys tool +* **fpga_flow**: scripts and dependencies to run the complete flow ## 1. FPGA flow -OpenFPGA repository is organized as follow: - - abc: open source synthesys tool - - ace2: abc extension generating .act files - - vpr7_x2p: source of modified vpr - - yosys: opensource synthesys tool +The folder is organized as follow: +* **arch**: contains architectures description files +* **benchmarks**: contains Verilog and blif benchmarks + lists +* **configs**: contains configuration files to run fpga_flow.pl +* **scripts**: contains all the scripts required to run the flow +* **tech**: contains xml tech files for power estimation fpga_flow.pl is saved in OPENFPGAPATHKEYWORD/fpga_flow/scripts. If we look in this folder, we can find some other scripts as: - - pro_blif.pl: rewrite a blif which has only 3 members in a .latch module - - rewrite_path_in_file.pl: target a keyword in a file and replace it +* pro_blif.pl: rewrite a blif which has only 3 members in a .latch module +* rewrite_path_in_file.pl: target a keyword in a file and replace it *Any script provides a help if launch without argument* fpga_flow.pl has dependencies which need to be configured. They are: - - configuration file, which provides dependencies path and flow type - - benchmark list file +* configuration file, which provides dependencies path and flow type +* benchmark list file ### Configuration file In this file paths have to be full path. Relative path could lead to errors.
The file is organized in 3 parts: - - dir_path: provides all the tools and repository path - - flow_conf: provides information on how the flow run - - csv_tags: *to complete* +* dir_path: provides all the tools and repository path +* flow_conf: provides information on how the flow run +* csv_tags: *to complete* While empty the file is as follow: [dir_path]
script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts
-benchmark_dir = *Path to the folder containing all sources of the design*
+benchmark_dir = **
yosys_path = OPENFPGAPATHKEYWORD/yosys
odin2_path = not_used
cirkit_path = not_used
@@ -48,16 +58,16 @@ mpack1_path = not_used
m2net_path = not_used
mpack2_path = not_used
vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr
-rpt_dir = *wherever tou want logs to be saved*
+rpt_dir = **
ace_path = OPENFPGAPATHKEYWORD/ace2
[flow_conf]
flow_type = yosys_vpr *to use verilog input*
-vpr_arch = *wherever the architecture file is saved*
+vpr_arch = **
mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK
m2net_conf = not_used
mpack2_arch = not_used
-power_tech_xml = *wherever the xml tech file is saved*
+power_tech_xml = **
[csv_tags] *to complete*
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
@@ -65,4 +75,17 @@ mpack2_tags = BLE Number:|BLE Fill Rate:
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff
+*An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf* +### Benchmark list + +The benchmark folder contains 3 sub-folders: +* Blif: contains .blif and .act of benchmarks +* List: contains all benchmark list files +* Verilog: contains Verilog designs + +Blif and Verilog folders are organized by folders with name of projects. **Folder, top module and top module file must share the same name.**
+The benchmark list file can contain as many benchmark as available in a same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:
+top_module/*.v,; where is the number ofchannel/wire between each blocks. + +*An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt* From 8366f9e7b7a6b558816096998b06d0fd3b410c43 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 8 Jul 2019 16:18:08 -0600 Subject: [PATCH 44/84] Update tutorial --- fpga_flow/benchmarks/List/tuto_benchmark.txt | 2 ++ fpga_flow/configs/tutorial/tuto.conf | 30 +++++++++++++++++ fpga_flow/tuto_fpga_flow.sh | 31 +++++++++++++++++ tutorials/tutorial.md | 35 +++++++++++++++----- 4 files changed, 89 insertions(+), 9 deletions(-) create mode 100644 fpga_flow/benchmarks/List/tuto_benchmark.txt create mode 100644 fpga_flow/configs/tutorial/tuto.conf create mode 100644 fpga_flow/tuto_fpga_flow.sh diff --git a/fpga_flow/benchmarks/List/tuto_benchmark.txt b/fpga_flow/benchmarks/List/tuto_benchmark.txt new file mode 100644 index 000000000..8c59d3b57 --- /dev/null +++ b/fpga_flow/benchmarks/List/tuto_benchmark.txt @@ -0,0 +1,2 @@ +# Circuit Names, fixed routing channel width, +s298/*.v, 200 diff --git a/fpga_flow/configs/tutorial/tuto.conf b/fpga_flow/configs/tutorial/tuto.conf new file mode 100644 index 000000000..85104383a --- /dev/null +++ b/fpga_flow/configs/tutorial/tuto.conf @@ -0,0 +1,30 @@ +# Standard Configuration Example +[dir_path] +script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/ +benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC +yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys +odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe +cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit +abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc +abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc +abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc +mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1 +m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net +mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2 +vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr +rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial +ace_path = OPENFPGAPATHKEYWORD/ace2/ace + +[flow_conf] +flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr +vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml +mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK +m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +mpack2_arch = K6_pattern7_I24.arch +power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK + +[csv_tags] +mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: +mpack2_tags = BLE Number:|BLE Fill Rate: +vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles: +vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh new file mode 100644 index 000000000..7bfefb66d --- /dev/null +++ b/fpga_flow/tuto_fpga_flow.sh @@ -0,0 +1,31 @@ +#! /bin/bash +# Exit if error occurs +set -e +# Make sure a clear start +pwd_path="$PWD" +task_name="tuto" +config_file="$pwd_path/configs/tutorial/${task_name}.conf" +bench_txt="$pwd_path/benchmarks/List/tuto_benchmark.txt" +rpt_file="$pwd_path/csv_rpts/fpga_spice/${task_name}.csv" + +verilog_path="${pwd_path}/${task_name}_Verilog" + +ff_keyword="FFPATHKEYWORD" +ff_path="${pwd_path}/vpr7_x2p/vpr/Verilognetlists/ff.v" +dir_keyword="GENERATED_DIR_KEYWORD" + +rm -rf ${pwd_path}/results_OpenPithon +cd ${pwd_path}/scripts + +# Replace keyword in config and architecture files +perl rewrite_path_in_file -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file +perl rewrite_path_in_file -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file +perl rewrite_path_in_file -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file +perl rewrite_path_in_file -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file + + +# SRAM FPGA +# TT case +perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -end_flow_with_test + +echo "Netlists successfully generated and tested" diff --git a/tutorials/tutorial.md b/tutorials/tutorial.md index e933702a6..74e8d22ff 100644 --- a/tutorials/tutorial.md +++ b/tutorials/tutorial.md @@ -16,7 +16,7 @@ OpenFPGA repository is organized as follow: * **yosys**: opensource synthesys tool * **fpga_flow**: scripts and dependencies to run the complete flow -## 1. FPGA flow +## 1. FPGA flow The folder is organized as follow: * **arch**: contains architectures description files @@ -35,13 +35,13 @@ fpga_flow.pl has dependencies which need to be configured. They are: * configuration file, which provides dependencies path and flow type * benchmark list file -### Configuration file +### a. Configuration file In this file paths have to be full path. Relative path could lead to errors.
The file is organized in 3 parts: -* dir_path: provides all the tools and repository path -* flow_conf: provides information on how the flow run -* csv_tags: *to complete* +* **dir_path**: provides all the tools and repository path +* **flow_conf**: provides information on how the flow run +* **csv_tags**: *to complete* While empty the file is as follow: @@ -77,15 +77,32 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St *An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf* -### Benchmark list +### b. Benchmark list The benchmark folder contains 3 sub-folders: -* Blif: contains .blif and .act of benchmarks -* List: contains all benchmark list files -* Verilog: contains Verilog designs +* **Blif**: contains .blif and .act of benchmarks +* **List**: contains all benchmark list files +* **Verilog**: contains Verilog designs Blif and Verilog folders are organized by folders with name of projects. **Folder, top module and top module file must share the same name.**
The benchmark list file can contain as many benchmark as available in a same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:
top_module/*.v,; where is the number ofchannel/wire between each blocks. *An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt* + +### c. Running fpga_flow.pl + +Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".
+Few options are only in fpga_flow: +* -N: number of LUT per CLB +* -K: LUT size/ number of input +* -rpt : wherever fpga_flow will write its report +* -ace_d : specifies inputs average probability of switching +* -multi_thread : specifies number of core to use +* -end_flow_with_test: uses Icarus Verilog to verify generated netlist + +*An example of script can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh* + + + + From c3b34a6297a0ab1844d306cbf5ba264a4274b1e0 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 8 Jul 2019 16:26:29 -0600 Subject: [PATCH 45/84] Update font in tutorial --- tutorials/tutorial.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tutorials/tutorial.md b/tutorials/tutorial.md index 74e8d22ff..9769f05de 100644 --- a/tutorials/tutorial.md +++ b/tutorials/tutorial.md @@ -94,12 +94,12 @@ top_module/*.v,; where is the number ofchannel/wire betwe Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".
Few options are only in fpga_flow: -* -N: number of LUT per CLB -* -K: LUT size/ number of input -* -rpt : wherever fpga_flow will write its report -* -ace_d : specifies inputs average probability of switching -* -multi_thread : specifies number of core to use -* -end_flow_with_test: uses Icarus Verilog to verify generated netlist +* **-N**: number of LUT per CLB +* **-K**: LUT size/ number of input +* **-rpt **: specifies wherever fpga_flow will write its report +* **-ace_d **: specifies inputs average probability of switching +* **-multi_thread **: specifies number of core to use +* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist *An example of script can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh* From 5d5e09fcdb7baf7e9c3f7c8168ffaeecc45db7cb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 8 Jul 2019 17:12:36 -0600 Subject: [PATCH 46/84] minor fix in trying to accelerate the unique routing functions --- vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index 45c67fa33..dc76ff55d 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1338,10 +1338,10 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, /* For each switch block, determine the size of array */ for (size_t ix = 0; ix <= sb_range.get_x(); ++ix) { for (size_t iy = 0; iy <= sb_range.get_y(); ++iy) { - RRGSB rr_gsb = build_rr_gsb(sb_range, ix, iy, - LL_num_rr_nodes, LL_rr_node, - LL_rr_node_indices, - num_segments, LL_rr_indexed_data); + const RRGSB& rr_gsb = build_rr_gsb(sb_range, ix, iy, + LL_num_rr_nodes, LL_rr_node, + LL_rr_node_indices, + num_segments, LL_rr_indexed_data); /* sort drive_rr_nodes */ sort_rr_gsb_drive_rr_nodes(rr_gsb); /* Add to device_rr_gsb */ From 25f5bc7792c8f0772c0f3cd11884c94fc2fff1e2 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Tue, 9 Jul 2019 08:34:01 -0600 Subject: [PATCH 47/84] Latest version, not stable yet but close --- vpr7_x2p/libarchfpga/tags | 2507 +++++++++-------- .../verilog/verilog_compact_netlist.c | 29 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 116 +- .../SRC/fpga_x2p/verilog/verilog_pbtypes.h | 10 +- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 28 +- .../SRC/fpga_x2p/verilog/verilog_routing.c | 2 +- .../SRC/fpga_x2p/verilog/verilog_submodules.c | 2 +- .../verilog/verilog_top_netlist_utils.c | 25 +- .../vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 65 +- vpr7_x2p/vpr/regression_verilog.sh | 2 + 10 files changed, 1514 insertions(+), 1272 deletions(-) mode change 100644 => 100755 vpr7_x2p/vpr/regression_verilog.sh diff --git a/vpr7_x2p/libarchfpga/tags b/vpr7_x2p/libarchfpga/tags index cefe670d6..d71681de4 100644 --- a/vpr7_x2p/libarchfpga/tags +++ b/vpr7_x2p/libarchfpga/tags @@ -4,1186 +4,1327 @@ !_TAG_PROGRAM_NAME Exuberant Ctags // !_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ !_TAG_PROGRAM_VERSION 5.8 // -ABSOLUTE include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type -ARCH_TYPES_H include/arch_types.h 9;" d -Aspect include/physical_types.h /^ float Aspect;$/;" m struct:s_clb_grid -BI_DIRECTIONAL include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality -BOTTOM include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side -BOUNDARY include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -BUFSIZE include/util.h 23;" d -C include/arch_types_mrfpga.h /^ float C; $/;" m struct:s_memristor_inf -C include/arch_types_mrfpga.h /^ float C;$/;" m struct:s_buffer_inf -C include/physical_types.h /^ float C;$/;" m union:s_port_power::__anon3 -CAD_TYPES_H include/cad_types.h 5;" d -CHECK_RAND util.c 734;" d file: -CHUNK_SIZE util.c 208;" d file: -COL_REL include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -COL_REPEAT include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -COMPLETE_INTERC include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect -CONV include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -C_internal include/physical_types.h /^ float C_internal; \/*Internal capacitance of the pb *\/$/;" m struct:s_pb_type_power -C_ipin_cblock include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_arch -C_ipin_cblock include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_timing_inf -C_wire include/physical_types.h /^ float C_wire; \/* Wire capacitance (per meter) *\/$/;" m struct:s_clock_network -C_wire include/physical_types.h /^ float C_wire;$/;" m struct:s_pb_graph_pin_power -C_wire_local include/physical_types.h /^ float C_wire_local; \/* Capacitance of local interconnect (per meter) *\/$/;" m struct:s_power_arch -Chans include/physical_types.h /^ t_chan_width_dist Chans;$/;" m struct:s_arch -CheckElement read_xml_util.c /^void CheckElement(INP ezxml_t Node, INP const char *Name) {$/;" f -Cin include/physical_types.h /^ float Cin;$/;" m struct:s_switch_inf -Cmetal include/physical_types.h /^ float Cmetal;$/;" m struct:s_segment_inf -CountChildren read_xml_util.c /^extern int CountChildren(INP ezxml_t Node, INP const char *Name,$/;" f -CountTokens ReadLine.c /^int CountTokens(INP char **Tokens) {$/;" f -CountTokensInString read_xml_util.c /^extern void CountTokensInString(INP const char *Str, OUTP int *Num,$/;" f -Cout include/physical_types.h /^ float Cout;$/;" m struct:s_switch_inf -CreateModelLibrary read_xml_arch_file.c /^static void CreateModelLibrary(OUTP struct s_arch *arch) {$/;" f file: -Cseg_global include/arch_types_mrfpga.h /^ float Cseg_global;$/;" m struct:s_arch_mrfpga -DELTA include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -DIRECT_INTERC include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect -DRIVER include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type -Directs include/physical_types.h /^ t_direct_inf *Directs;$/;" m struct:s_arch -EMPTY_TYPE read_xml_arch_file.c /^static t_type_ptr EMPTY_TYPE = NULL;$/;" v file: -EMPTY_TYPE_INDEX include/read_xml_arch_file.h 15;" d -ERRTAG include/util.h 26;" d -ERR_PORT include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -EZXML_BUFSIZE include/ezxml.h 37;" d -EZXML_DUP include/ezxml.h 40;" d -EZXML_ERRL include/ezxml.h 41;" d -EZXML_NAMEM include/ezxml.h 38;" d -EZXML_NIL ezxml.c /^char *EZXML_NIL[] = { NULL }; \/* empty, null terminated array of strings *\/$/;" v -EZXML_NOMMAP ezxml.c 26;" d file: -EZXML_TXTM include/ezxml.h 39;" d -EZXML_WS ezxml.c 64;" d file: -E_ANNOT_PIN_TO_PIN_CAPACITANCE include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE,$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_CAPACITANCE_C include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE_C = 0$/;" e enum:e_pin_to_pin_capacitance_annotations -E_ANNOT_PIN_TO_PIN_CONSTANT include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format -E_ANNOT_PIN_TO_PIN_DELAY include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY = 0,$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_MAX include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MAX,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_MIN include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MIN = 0,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_THOLD include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_THOLD$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_DELAY_TSETUP include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_TSETUP,$/;" e enum:e_pin_to_pin_delay_annotations -E_ANNOT_PIN_TO_PIN_MATRIX include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format -E_ANNOT_PIN_TO_PIN_MODE_SELECT include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME = 0$/;" e enum:e_pin_to_pin_mode_select_annotations -E_ANNOT_PIN_TO_PIN_PACK_PATTERN include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN,$/;" e enum:e_pin_to_pin_annotation_type -E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME = 0$/;" e enum:e_pin_to_pin_pack_pattern_annotations -E_CUSTOM_PIN_DISTR include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr -E_SPREAD_PIN_DISTR include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr -EchoArch read_xml_arch_file.c /^void EchoArch(INP const char *EchoFile, INP const t_type_descriptor * Types,$/;" f -FALSE include/util.h /^ FALSE, TRUE$/;" e enum:__anon4 -FC_ABS read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: -FC_FRAC read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: -FC_FULL read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: -FF_size include/physical_types.h /^ float FF_size;$/;" m struct:s_power_arch -FILL include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type -FILL_TYPE read_xml_arch_file.c /^static t_type_ptr FILL_TYPE = NULL;$/;" v file: -FRACTIONAL include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type -FRAGMENT_THRESHOLD util.c 209;" d file: -FULL include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -Fc include/physical_types.h /^ float *Fc; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -Fc_type read_xml_arch_file.c /^enum Fc_type {$/;" g file: -FindElement read_xml_util.c /^ezxml_t FindElement(INP ezxml_t Parent, INP const char *Name,$/;" f -FindFirstElement read_xml_util.c /^ezxml_t FindFirstElement(INP ezxml_t Parent, INP const char *Name,$/;" f -FindProperty read_xml_util.c /^FindProperty(INP ezxml_t Parent, INP const char *Name, INP boolean Required) {$/;" f -FreeNode read_xml_util.c /^void FreeNode(INOUTP ezxml_t Node) {$/;" f -FreeSpice read_xml_spice_util.c /^void FreeSpice(t_spice* spice) {$/;" f -FreeSpiceMeasParams read_xml_spice_util.c /^void FreeSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f -FreeSpiceModel read_xml_spice_util.c /^void FreeSpiceModel(t_spice_model* spice_model) {$/;" f -FreeSpiceModelBuffer read_xml_spice_util.c /^void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer) {$/;" f -FreeSpiceModelNetlist read_xml_spice_util.c /^void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist) {$/;" f -FreeSpiceModelPassGateLogic read_xml_spice_util.c /^void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic) {$/;" f -FreeSpiceModelPort read_xml_spice_util.c /^void FreeSpiceModelPort(t_spice_model_port* spice_model_port) {$/;" f -FreeSpiceModelWireParam read_xml_spice_util.c /^void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param) {$/;" f -FreeSpiceMonteCarloParams read_xml_spice_util.c /^void FreeSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f -FreeSpiceMuxArch read_xml_spice_util.c /^void FreeSpiceMuxArch(t_spice_mux_arch* spice_mux_arch) {$/;" f -FreeSpiceParams read_xml_spice_util.c /^void FreeSpiceParams(t_spice_params* params) {$/;" f -FreeSpiceStimulateParams read_xml_spice_util.c /^void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f -FreeSpiceVariationParams read_xml_spice_util.c /^void FreeSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f -FreeSramInf read_xml_spice_util.c /^void FreeSramInf(t_sram_inf* sram_inf) {$/;" f -FreeSramInfOrgz read_xml_spice_util.c /^void FreeSramInfOrgz(t_sram_inf_orgz* sram_inf_orgz) {$/;" f -FreeTokens ReadLine.c /^void FreeTokens(INOUTP char ***TokensPtr) {$/;" f -Fs include/physical_types.h /^ int Fs;$/;" m struct:s_arch -GAUSSIAN include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -GetBooleanProperty read_xml_util.c /^extern boolean GetBooleanProperty(INP ezxml_t Parent, INP char *Name,$/;" f -GetFloatProperty read_xml_util.c /^extern float GetFloatProperty(INP ezxml_t Parent, INP char *Name,$/;" f -GetIntProperty read_xml_util.c /^extern int GetIntProperty(INP ezxml_t Parent, INP char *Name,$/;" f -GetNodeTokens read_xml_util.c /^GetNodeTokens(INP ezxml_t Node) {$/;" f -H include/physical_types.h /^ int H;$/;" m struct:s_clb_grid -IA util.c 731;" d file: -IC util.c 732;" d file: -IM util.c 733;" d file: -INOUTP include/util.h 21;" d -INOUT_PORT include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -INP include/util.h 19;" d -IN_PORT include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -IO_TYPE read_xml_arch_file.c /^static t_type_ptr IO_TYPE = NULL;$/;" v file: -IO_TYPE_INDEX include/read_xml_arch_file.h 16;" d -InitSpice read_xml_spice_util.c /^void InitSpice(t_spice* spice) {$/;" f -InitSpiceMeasParams read_xml_spice_util.c /^void InitSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f -InitSpiceMonteCarloParams read_xml_spice_util.c /^void InitSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f -InitSpiceParams read_xml_spice_util.c /^void InitSpiceParams(t_spice_params* params) {$/;" f -InitSpiceStimulateParams read_xml_spice_util.c /^void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f -InitSpiceVariationParams read_xml_spice_util.c /^void InitSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f -IsAuto include/physical_types.h /^ boolean IsAuto;$/;" m struct:s_clb_grid -IsWhitespace read_xml_util.c /^boolean IsWhitespace(char c) {$/;" f -LATCH_CLASS include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class -LEFT include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side -LINKEDLIST_H fpga_spice_include/linkedlist.h 2;" d -LOGIC_TYPES_H include/logic_types.h 10;" d -LUT_CLASS include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class -LUT_transistor_size include/physical_types.h /^ float LUT_transistor_size;$/;" m struct:s_power_arch -LookaheadNodeTokens read_xml_util.c /^LookaheadNodeTokens(INP ezxml_t Node) {$/;" f -MAX_CHANNEL_WIDTH include/arch_types.h 25;" d -MEMORY_CLASS include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class -MONO include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -MUX_INTERC include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect -NEM include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -NUM_MODELS_IN_LIBRARY include/read_xml_arch_file.h 14;" d -OPEN include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type -OUTP include/util.h 20;" d -OUT_PORT include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS -PB_PIN_CLOCK include/physical_types.h /^ PB_PIN_CLOCK$/;" e enum:e_pb_graph_pin_type -PB_PIN_INPAD include/physical_types.h /^ PB_PIN_INPAD,$/;" e enum:e_pb_graph_pin_type -PB_PIN_NORMAL include/physical_types.h /^ PB_PIN_NORMAL = 0,$/;" e enum:e_pb_graph_pin_type -PB_PIN_OUTPAD include/physical_types.h /^ PB_PIN_OUTPAD,$/;" e enum:e_pb_graph_pin_type -PB_PIN_SEQUENTIAL include/physical_types.h /^ PB_PIN_SEQUENTIAL,$/;" e enum:e_pb_graph_pin_type -PB_PIN_TERMINAL include/physical_types.h /^ PB_PIN_TERMINAL,$/;" e enum:e_pb_graph_pin_type -PCRAM_Pierre include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -PCRAM_Xie include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -PHYSICAL_TYPES_H include/physical_types.h 27;" d -PORTS include/logic_types.h /^enum PORTS {$/;" g -POWER_BUFFER_TYPE_ABSOLUTE_SIZE include/physical_types.h /^ POWER_BUFFER_TYPE_ABSOLUTE_SIZE$/;" e enum:__anon2 -POWER_BUFFER_TYPE_AUTO include/physical_types.h /^ POWER_BUFFER_TYPE_AUTO,$/;" e enum:__anon2 -POWER_BUFFER_TYPE_NONE include/physical_types.h /^ POWER_BUFFER_TYPE_NONE,$/;" e enum:__anon2 -POWER_BUFFER_TYPE_UNDEFINED include/physical_types.h /^ POWER_BUFFER_TYPE_UNDEFINED = 0,$/;" e enum:__anon2 -POWER_METHOD_ABSOLUTE include/physical_types.h /^ POWER_METHOD_ABSOLUTE \/* Dynamic: Aboslute, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_AUTO_SIZES include/physical_types.h /^ POWER_METHOD_AUTO_SIZES, \/* Transistor-level, auto-sized buffers\/wires *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_C_INTERNAL include/physical_types.h /^ POWER_METHOD_C_INTERNAL, \/* Dynamic: Equiv. Internal capacitance, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_IGNORE include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_SPECIFY_SIZES include/physical_types.h /^ POWER_METHOD_SPECIFY_SIZES, \/* Transistor-level, user-specified buffers\/wires *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_SUM_OF_CHILDREN include/physical_types.h /^ POWER_METHOD_SUM_OF_CHILDREN, \/* Ignore power of this PB, but consider children *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_TOGGLE_PINS include/physical_types.h /^ POWER_METHOD_TOGGLE_PINS, \/* Dynamic: Energy per pin toggle, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ -POWER_METHOD_UNDEFINED include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ -POWER_WIRE_TYPE_ABSOLUTE_LENGTH include/physical_types.h /^ POWER_WIRE_TYPE_ABSOLUTE_LENGTH,$/;" e enum:__anon1 -POWER_WIRE_TYPE_AUTO include/physical_types.h /^ POWER_WIRE_TYPE_AUTO$/;" e enum:__anon1 -POWER_WIRE_TYPE_C include/physical_types.h /^ POWER_WIRE_TYPE_C,$/;" e enum:__anon1 -POWER_WIRE_TYPE_IGNORED include/physical_types.h /^ POWER_WIRE_TYPE_IGNORED,$/;" e enum:__anon1 -POWER_WIRE_TYPE_RELATIVE_LENGTH include/physical_types.h /^ POWER_WIRE_TYPE_RELATIVE_LENGTH,$/;" e enum:__anon1 -POWER_WIRE_TYPE_UNDEFINED include/physical_types.h /^ POWER_WIRE_TYPE_UNDEFINED = 0,$/;" e enum:__anon1 -PULSE include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -PrintPb_types_rec read_xml_arch_file.c /^static void PrintPb_types_rec(INP FILE * Echo, INP const t_pb_type * pb_type,$/;" f file: -ProcessCB_SB read_xml_arch_file.c /^static void ProcessCB_SB(INOUTP ezxml_t Node, INOUTP boolean * list,$/;" f file: -ProcessChanWidthDistr read_xml_arch_file.c /^static void ProcessChanWidthDistr(INOUTP ezxml_t Node,$/;" f file: -ProcessChanWidthDistrDir read_xml_arch_file.c /^static void ProcessChanWidthDistrDir(INOUTP ezxml_t Node, OUTP t_chan * chan) {$/;" f file: -ProcessClocks read_xml_arch_file.c /^static void ProcessClocks(ezxml_t Parent, t_clock_arch * clocks) {$/;" f file: -ProcessComplexBlockProps read_xml_arch_file.c /^static void ProcessComplexBlockProps(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: -ProcessComplexBlocks read_xml_arch_file.c /^static void ProcessComplexBlocks(INOUTP ezxml_t Node,$/;" f file: -ProcessDevice read_xml_arch_file.c /^static void ProcessDevice(INOUTP ezxml_t Node, OUTP struct s_arch *arch,$/;" f file: -ProcessDirects read_xml_arch_file.c /^static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs,$/;" f file: -ProcessInterconnect read_xml_arch_file.c /^static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {$/;" f file: -ProcessLayout read_xml_arch_file.c /^static void ProcessLayout(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: -ProcessLutClass read_xml_arch_file.c /^void ProcessLutClass(INOUTP t_pb_type *lut_pb_type) {$/;" f -ProcessMemoryClass read_xml_arch_file.c /^static void ProcessMemoryClass(INOUTP t_pb_type *mem_pb_type) {$/;" f file: -ProcessMode read_xml_arch_file.c /^static void ProcessMode(INOUTP ezxml_t Parent, t_mode * mode,$/;" f file: -ProcessModels read_xml_arch_file.c /^static void ProcessModels(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: -ProcessMrFPGATiming read_xml_mrfpga.c /^void ProcessMrFPGATiming(INOUTP ezxml_t Cur, $/;" f -ProcessPb_Type read_xml_arch_file.c /^static void ProcessPb_Type(INOUTP ezxml_t Parent, t_pb_type * pb_type,$/;" f file: -ProcessPb_TypePort read_xml_arch_file.c /^static void ProcessPb_TypePort(INOUTP ezxml_t Parent, t_port * port,$/;" f file: -ProcessPb_TypePort_Power read_xml_arch_file.c /^static void ProcessPb_TypePort_Power(ezxml_t Parent, t_port * port,$/;" f file: -ProcessPb_TypePower read_xml_arch_file.c /^static void ProcessPb_TypePower(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: -ProcessPb_TypePowerEstMethod read_xml_arch_file.c /^static void ProcessPb_TypePowerEstMethod(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: -ProcessPb_TypePowerPinToggle read_xml_arch_file.c /^static void ProcessPb_TypePowerPinToggle(ezxml_t parent, t_pb_type * pb_type) {$/;" f file: -ProcessPinToPinAnnotations read_xml_arch_file.c /^static void ProcessPinToPinAnnotations(ezxml_t Parent,$/;" f file: -ProcessPower read_xml_arch_file.c /^static void ProcessPower( INOUTP ezxml_t parent,$/;" f file: -ProcessSegments read_xml_arch_file.c /^static void ProcessSegments(INOUTP ezxml_t Parent,$/;" f file: -ProcessSpiceMCVariationParams read_xml_spice.c /^static void ProcessSpiceMCVariationParams(ezxml_t Parent,$/;" f file: -ProcessSpiceMeasParams read_xml_spice.c /^static void ProcessSpiceMeasParams(ezxml_t Parent,$/;" f file: -ProcessSpiceModel read_xml_spice.c /^static void ProcessSpiceModel(ezxml_t Parent,$/;" f file: -ProcessSpiceModelBuffer read_xml_spice.c /^static void ProcessSpiceModelBuffer(ezxml_t Node,$/;" f file: -ProcessSpiceModelPassGateLogic read_xml_spice.c /^static void ProcessSpiceModelPassGateLogic(ezxml_t Node,$/;" f file: -ProcessSpiceModelPort read_xml_spice.c /^static void ProcessSpiceModelPort(ezxml_t Node,$/;" f file: -ProcessSpiceModelWireParam read_xml_spice.c /^static void ProcessSpiceModelWireParam(ezxml_t Parent,$/;" f file: -ProcessSpiceMonteCarloParams read_xml_spice.c /^static void ProcessSpiceMonteCarloParams(ezxml_t Parent, $/;" f file: -ProcessSpiceParams read_xml_spice.c /^static void ProcessSpiceParams(ezxml_t Parent,$/;" f file: -ProcessSpiceSRAM read_xml_spice.c /^void ProcessSpiceSRAM(INOUTP ezxml_t Node, OUTP struct s_arch* arch) {$/;" f -ProcessSpiceSRAMOrganization read_xml_spice.c /^void ProcessSpiceSRAMOrganization(INOUTP ezxml_t Node, $/;" f file: -ProcessSpiceSettings read_xml_spice.c /^void ProcessSpiceSettings(ezxml_t Parent,$/;" f -ProcessSpiceStimulateParams read_xml_spice.c /^static void ProcessSpiceStimulateParams(ezxml_t Parent,$/;" f file: -ProcessSpiceStimulateParamsRiseFall read_xml_spice.c /^static void ProcessSpiceStimulateParamsRiseFall(ezxml_t Parent,$/;" f file: -ProcessSpiceTechLibTransistors read_xml_spice.c /^static void ProcessSpiceTechLibTransistors(ezxml_t Parent,$/;" f file: -ProcessSpiceTransistorType read_xml_spice.c /^static void ProcessSpiceTransistorType(ezxml_t Parent,$/;" f file: -ProcessSwitchSegmentPatterns read_xml_arch_file.c /^static void ProcessSwitchSegmentPatterns(INOUTP ezxml_t Parent,$/;" f file: -ProcessSwitches read_xml_arch_file.c /^static void ProcessSwitches(INOUTP ezxml_t Parent,$/;" f file: -ProcessTechComp read_xml_mrfpga.c /^ProcessTechComp(INOUTP ezxml_t Node,$/;" f -ProcessTechHack read_xml_mrfpga.c /^ProcessTechHack(INOUTP ezxml_t Node,$/;" f -ProcessTechnology read_xml_mrfpga.c /^ProcessTechnology(INOUTP ezxml_t Node,$/;" f -ProcessWireBuffer read_xml_mrfpga.c /^ProcessWireBuffer(INOUTP ezxml_t Node,$/;" f -Process_Fc read_xml_arch_file.c /^static void Process_Fc(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: -ProcessmrFPGA read_xml_mrfpga.c /^ProcessmrFPGA(INOUTP ezxml_t Node,$/;" f -R include/arch_types_mrfpga.h /^ float R; $/;" m struct:s_memristor_inf -R include/arch_types_mrfpga.h /^ float R;$/;" m struct:s_buffer_inf -R include/physical_types.h /^ float R;$/;" m struct:s_switch_inf -READLINE_H include/ReadLine.h 2;" d -READ_XML_ARCH_FILE_H include/read_xml_arch_file.h 2;" d -READ_XML_UTIL_H include/read_xml_util.h 2;" d -RECEIVER include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type -RIGHT include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side -R_minW_nmos include/physical_types.h /^ float R_minW_nmos;$/;" m struct:s_arch -R_minW_pmos include/physical_types.h /^ float R_minW_pmos;$/;" m struct:s_arch -R_opin_cblock include/arch_types_mrfpga.h /^ float R_opin_cblock;$/;" m struct:s_arch_mrfpga -R_opin_cblock include/physical_types.h /^ float R_opin_cblock;$/;" m struct:s_timing_inf -ReadLineTokens ReadLine.c /^ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum) {$/;" f -Rmetal include/physical_types.h /^ float Rmetal;$/;" m struct:s_segment_inf -Rseg_global include/arch_types_mrfpga.h /^ float Rseg_global;$/;" m struct:s_arch_mrfpga -SBType include/physical_types.h /^ enum e_switch_block_type SBType;$/;" m struct:s_arch typeref:enum:s_arch::e_switch_block_type -SDCFile include/physical_types.h /^ char * SDCFile; \/* only here for convenience of passing to path_delay.c *\/$/;" m struct:s_timing_inf -SPICE_ABS fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type -SPICE_FRAC fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type -SPICE_LIB_ACADEMIA fpga_spice_include/spice_types.h /^ SPICE_LIB_INDUSTRY,SPICE_LIB_ACADEMIA$/;" e enum:e_spice_tech_lib_type -SPICE_LIB_INDUSTRY fpga_spice_include/spice_types.h /^ SPICE_LIB_INDUSTRY,SPICE_LIB_ACADEMIA$/;" e enum:e_spice_tech_lib_type -SPICE_MODEL_BUF_BUF fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_BUF$/;" e enum:e_spice_model_buffer_type -SPICE_MODEL_BUF_INV fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_INV, $/;" e enum:e_spice_model_buffer_type -SPICE_MODEL_CHAN_WIRE fpga_spice_include/spice_types.h /^ SPICE_MODEL_CHAN_WIRE, $/;" e enum:e_spice_model_type -SPICE_MODEL_DESIGN_CMOS fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_CMOS, $/;" e enum:e_spice_model_design_tech -SPICE_MODEL_DESIGN_RRAM fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_RRAM$/;" e enum:e_spice_model_design_tech -SPICE_MODEL_FF fpga_spice_include/spice_types.h /^ SPICE_MODEL_FF, $/;" e enum:e_spice_model_type -SPICE_MODEL_GND fpga_spice_include/spice_types.h /^ SPICE_MODEL_GND, $/;" e enum:e_spice_model_type -SPICE_MODEL_HARDLOGIC fpga_spice_include/spice_types.h /^ SPICE_MODEL_HARDLOGIC,$/;" e enum:e_spice_model_type -SPICE_MODEL_INVBUF fpga_spice_include/spice_types.h /^ SPICE_MODEL_INVBUF, $/;" e enum:e_spice_model_type -SPICE_MODEL_IOPAD fpga_spice_include/spice_types.h /^ SPICE_MODEL_IOPAD, $/;" e enum:e_spice_model_type -SPICE_MODEL_LUT fpga_spice_include/spice_types.h /^ SPICE_MODEL_LUT, $/;" e enum:e_spice_model_type -SPICE_MODEL_MUX fpga_spice_include/spice_types.h /^ SPICE_MODEL_MUX, $/;" e enum:e_spice_model_type -SPICE_MODEL_PASSGATE fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASSGATE $/;" e enum:e_spice_model_type -SPICE_MODEL_PASS_GATE_TRANSISTOR fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSMISSION, SPICE_MODEL_PASS_GATE_TRANSISTOR$/;" e enum:e_spice_model_pass_gate_logic_type -SPICE_MODEL_PASS_GATE_TRANSMISSION fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSMISSION, SPICE_MODEL_PASS_GATE_TRANSISTOR$/;" e enum:e_spice_model_pass_gate_logic_type -SPICE_MODEL_PORT_BL fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BL,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_BLB fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BLB,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_CLOCK fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_CLOCK, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_INOUT fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INOUT, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_INPUT fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INPUT, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_OUTPUT fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_OUTPUT, $/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_SRAM fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_SRAM,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_WL fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WL,$/;" e enum:e_spice_model_port_type -SPICE_MODEL_PORT_WLB fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WLB$/;" e enum:e_spice_model_port_type -SPICE_MODEL_SCFF fpga_spice_include/spice_types.h /^ SPICE_MODEL_SCFF,$/;" e enum:e_spice_model_type -SPICE_MODEL_SRAM fpga_spice_include/spice_types.h /^ SPICE_MODEL_SRAM, $/;" e enum:e_spice_model_type -SPICE_MODEL_STRUCTURE_CROSSBAR fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_CROSSBAR $/;" e enum:e_spice_model_structure -SPICE_MODEL_STRUCTURE_MULTILEVEL fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_MULTILEVEL, $/;" e enum:e_spice_model_structure -SPICE_MODEL_STRUCTURE_ONELEVEL fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_ONELEVEL, $/;" e enum:e_spice_model_structure -SPICE_MODEL_STRUCTURE_TREE fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_TREE, $/;" e enum:e_spice_model_structure -SPICE_MODEL_VDD fpga_spice_include/spice_types.h /^ SPICE_MODEL_VDD, $/;" e enum:e_spice_model_type -SPICE_MODEL_WIRE fpga_spice_include/spice_types.h /^ SPICE_MODEL_WIRE, $/;" e enum:e_spice_model_type -SPICE_SRAM_MEMORY_BANK fpga_spice_include/spice_types.h /^ SPICE_SRAM_MEMORY_BANK$/;" e enum:e_sram_orgz -SPICE_SRAM_SCAN_CHAIN fpga_spice_include/spice_types.h /^ SPICE_SRAM_SCAN_CHAIN,$/;" e enum:e_sram_orgz -SPICE_SRAM_STANDALONE fpga_spice_include/spice_types.h /^ SPICE_SRAM_STANDALONE,$/;" e enum:e_sram_orgz -SPICE_TRANS_IO_NMOS fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type -SPICE_TRANS_IO_PMOS fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type -SPICE_TRANS_NMOS fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type -SPICE_TRANS_PMOS fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, SPICE_TRANS_PMOS, SPICE_TRANS_IO_NMOS, SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type -STTRAM include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp -SUBSET include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -SWSEG_UNBUF_CB include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type -SWSEG_UNBUF_SB include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type -Segments include/physical_types.h /^ t_segment_inf * Segments;$/;" m struct:s_arch -SetupEmptyType read_xml_arch_file.c /^static void SetupEmptyType(void) {$/;" f file: -SetupGridLocations read_xml_arch_file.c /^static void SetupGridLocations(ezxml_t Locations, t_type_descriptor * Type) {$/;" f file: -SetupPinEquivalenceAutoDetect read_xml_arch_file.c /^void SetupPinEquivalenceAutoDetect(ezxml_t Parent, t_type_descriptor* Type) {$/;" f file: -SetupPinLocationsAndPinClasses read_xml_arch_file.c /^static void SetupPinLocationsAndPinClasses(ezxml_t Locations,$/;" f file: -Switches include/physical_types.h /^ struct s_switch_inf *Switches;$/;" m struct:s_arch typeref:struct:s_arch::s_switch_inf -SyncModelsPbTypes read_xml_arch_file.c /^static void SyncModelsPbTypes(INOUTP struct s_arch *arch,$/;" f file: -SyncModelsPbTypes_rec read_xml_arch_file.c /^static void SyncModelsPbTypes_rec(INOUTP struct s_arch *arch,$/;" f file: -TOKENS include/arch_types.h 19;" d -TOP include/physical_types.h /^ TOP = 0, RIGHT = 1, BOTTOM = 2, LEFT = 3$/;" e enum:e_side -TRUE include/util.h /^ FALSE, TRUE$/;" e enum:__anon4 -T_ipin_cblock include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_arch -T_ipin_cblock include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_timing_inf -T_opin_cblock include/arch_types_mrfpga.h /^ float T_opin_cblock;$/;" m struct:s_arch_mrfpga -T_opin_cblock include/physical_types.h /^ float T_opin_cblock;$/;" m struct:s_timing_inf -Tdel include/arch_types_mrfpga.h /^ float Tdel; $/;" m struct:s_memristor_inf -Tdel include/arch_types_mrfpga.h /^ float Tdel;$/;" m struct:s_buffer_inf -Tdel include/physical_types.h /^ float Tdel;$/;" m struct:s_switch_inf -UNDEFINED include/arch_types.h 22;" d -UNIFORM include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat -UNIVERSAL include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -UNI_DIRECTIONAL include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality -UNKNOWN_CLASS include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class -UTIL_H include/util.h 2;" d -UpdateAndCheckModels read_xml_arch_file.c /^static void UpdateAndCheckModels(INOUTP struct s_arch *arch) {$/;" f file: -VPR_VERSION include/arch_types.h 16;" d -W include/physical_types.h /^ int W;$/;" m struct:s_clb_grid -WARNTAG include/util.h 27;" d -WILTON include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type -WIRE_MODEL_PIE fpga_spice_include/spice_types.h /^ WIRE_MODEL_PIE,$/;" e enum:e_wire_model_type -WIRE_MODEL_T fpga_spice_include/spice_types.h /^ WIRE_MODEL_T$/;" e enum:e_wire_model_type -XmlReadArch read_xml_arch_file.c /^void XmlReadArch(INP const char *ArchFile, INP boolean timing_enabled,$/;" f -_EZXML_H include/ezxml.h 26;" d -abs_variation fpga_spice_include/spice_types.h /^ float abs_variation;$/;" m struct:s_spice_mc_variation_params -absolute_length include/physical_types.h /^ float absolute_length;$/;" m union:s_port_power::__anon3 -absolute_power_per_instance include/physical_types.h /^ t_power_usage absolute_power_per_instance; \/* User-provided absolute power per block *\/$/;" m struct:s_pb_type_power -accuracy fpga_spice_include/spice_types.h /^ float accuracy;$/;" m struct:s_spice_meas_params -accuracy_type fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type accuracy_type;$/;" m struct:s_spice_meas_params typeref:enum:s_spice_meas_params::e_spice_accuracy_type -addr fpga_spice_include/spice_types.h /^ int addr; \/* Address to write the value *\/$/;" m struct:s_conf_bit -advanced_rram_design fpga_spice_include/spice_types.h /^ boolean advanced_rram_design;$/;" m struct:s_spice_model_design_tech_info -alloc_and_load_default_child_for_pb_type read_xml_arch_file.c /^static void alloc_and_load_default_child_for_pb_type( INOUTP t_pb_type *pb_type,$/;" f file: -alloc_ivector_and_copy_int_list util.c /^void alloc_ivector_and_copy_int_list(t_linked_int ** list_head_ptr,$/;" f -alloc_matrix util.c /^alloc_matrix(int nrmin, int nrmax, int ncmin, int ncmax, size_t elsize) {$/;" f -alloc_matrix3 util.c /^alloc_matrix3(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f -alloc_matrix4 util.c /^alloc_matrix4(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f -annotations include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_interconnect -annotations include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_pb_type -arch_mrfpga include/physical_types.h /^ t_arch_mrfpga arch_mrfpga;$/;" m struct:s_arch -area fpga_spice_include/spice_types.h /^ float area; \/\/Xifan TANG$/;" m struct:s_sram_inf -area include/physical_types.h /^ float area;$/;" m struct:s_type_descriptor -attr include/ezxml.h /^ char ***attr; \/* default attributes *\/$/;" m struct:ezxml_root -attr include/ezxml.h /^ char **attr; \/* tag attributes { name, value, name, value, ... NULL } *\/$/;" m struct:ezxml -auto_select_sim_num_clk_cycle fpga_spice_include/spice_types.h /^ int auto_select_sim_num_clk_cycle;$/;" m struct:s_spice_meas_params -autosize_buffer include/physical_types.h /^ boolean autosize_buffer; \/* autosize clock buffers *\/$/;" m struct:s_clock_network -available_in_packing include/physical_types.h /^ int available_in_packing;$/;" m struct:s_mode -base_cost include/cad_types.h /^ float base_cost; \/* base cost of pattern eg. If a group of logical blocks match a pattern of smaller primitives, that is better than the same group using bigger primitives *\/$/;" m struct:s_pack_patterns -base_cost include/cad_types.h /^ float base_cost; \/* cost independant of current status of packing *\/$/;" m struct:s_cluster_placement_primitive -bl fpga_spice_include/spice_types.h /^ t_conf_bit* bl;$/;" m struct:s_conf_bit_info -blif_model include/physical_types.h /^ char *blif_model;$/;" m struct:s_pb_type -block_id include/cad_types.h /^ int block_id;$/;" m struct:s_pack_pattern_block -boolean include/util.h /^typedef int boolean;$/;" t -boolean include/util.h /^} boolean;$/;" t typeref:enum:__anon4 -buf_size include/physical_types.h /^ float buf_size;$/;" m struct:s_switch_inf -buffer_info fpga_spice_include/spice_types.h /^ t_spice_model_buffer* buffer_info;$/;" m struct:s_spice_model_design_tech_info -buffer_size include/physical_types.h /^ float buffer_size; \/* if not autosized, the clock buffer size *\/$/;" m struct:s_clock_network -buffer_size include/physical_types.h /^ float buffer_size;$/;" m struct:s_pb_graph_pin_power -buffer_size include/physical_types.h /^ float buffer_size;$/;" m struct:s_port_power -buffer_type include/physical_types.h /^ e_power_buffer_type buffer_type;$/;" m struct:s_port_power -buffered include/physical_types.h /^ boolean buffered;$/;" m struct:s_switch_inf -cap_val fpga_spice_include/spice_types.h /^ float cap_val; $/;" m struct:s_spice_model_wire_param -capacitance include/physical_types.h /^ float capacitance;$/;" m struct:s_pb_graph_edge -capacity include/physical_types.h /^ int capacity;$/;" m struct:s_type_descriptor -captab fpga_spice_include/spice_types.h /^ int captab;$/;" m struct:s_spice_params -cat_llists linkedlist.c /^t_llist* cat_llists(t_llist* head1,$/;" f -cb include/physical_types.h /^ boolean *cb;$/;" m struct:s_segment_inf -cb_len include/physical_types.h /^ int cb_len;$/;" m struct:s_segment_inf -cb_switches include/physical_types.h /^ t_switch_inf* cb_switches;$/;" m struct:s_arch -cb_type_descriptors read_xml_arch_file.c /^static struct s_type_descriptor *cb_type_descriptors;$/;" v typeref:struct:s_type_descriptor file: -cbx_index_high fpga_spice_include/spice_types.h /^ int** cbx_index_high;$/;" m struct:s_spice_model -cbx_index_low fpga_spice_include/spice_types.h /^ int** cbx_index_low;$/;" m struct:s_spice_model -cby_index_high fpga_spice_include/spice_types.h /^ int** cby_index_high;$/;" m struct:s_spice_model -cby_index_low fpga_spice_include/spice_types.h /^ int** cby_index_low;$/;" m struct:s_spice_model -chain_name include/physical_types.h /^ char *chain_name;$/;" m struct:s_port -chain_root_pin include/cad_types.h /^ t_pb_graph_pin *chain_root_pin; \/* pointer to logic block input pin that drives this chain from the preceding logic block *\/ $/;" m struct:s_pack_patterns -chan_length fpga_spice_include/spice_types.h /^ float chan_length;$/;" m struct:s_spice_transistor_type -chan_width_io include/physical_types.h /^ float chan_width_io;$/;" m struct:s_chan_width_dist -chan_x_dist include/physical_types.h /^ t_chan chan_x_dist;$/;" m struct:s_chan_width_dist -chan_y_dist include/physical_types.h /^ t_chan chan_y_dist;$/;" m struct:s_chan_width_dist -check_spice_models read_xml_spice.c /^static void check_spice_models(int num_spice_model,$/;" f file: -check_tech_lib read_xml_spice.c /^static void check_tech_lib(t_spice_tech_lib tech_lib, $/;" f file: -child include/ezxml.h /^ ezxml_t child; \/* head of sub tag list, NULL if none *\/$/;" m struct:ezxml -child_pb_graph_nodes include/physical_types.h /^ struct s_pb_graph_node ***child_pb_graph_nodes; \/* [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb-1] *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node -chunk_ptr_head include/util.h /^ struct s_linked_vptr *chunk_ptr_head; $/;" m struct:s_chunk typeref:struct:s_chunk::s_linked_vptr -class_inf include/physical_types.h /^ struct s_class *class_inf; \/* [0..num_class-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_class -class_type include/physical_types.h /^ enum e_pb_type_class class_type;$/;" m struct:s_pb_type typeref:enum:s_pb_type::e_pb_type_class -clb_grid include/physical_types.h /^ struct s_clb_grid clb_grid;$/;" m struct:s_arch typeref:struct:s_arch::s_clb_grid -clock include/physical_types.h /^ char * clock;$/;" m struct:s_pin_to_pin_annotation -clock_inf include/physical_types.h /^ t_clock_network *clock_inf; \/* Details about each clock *\/$/;" m struct:s_clock_arch -clock_pins include/physical_types.h /^ t_pb_graph_pin **clock_pins; \/* [0..num_clock_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node -clock_slew_fall_time fpga_spice_include/spice_types.h /^ float clock_slew_fall_time; $/;" m struct:s_spice_stimulate_params -clock_slew_fall_type fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -clock_slew_rise_time fpga_spice_include/spice_types.h /^ float clock_slew_rise_time; $/;" m struct:s_spice_stimulate_params -clock_slew_rise_type fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -clocks include/physical_types.h /^ t_clock_arch * clocks;$/;" m struct:s_arch -close ezxml.c 61;" d file: -cluster_placement_primitive include/physical_types.h /^ struct s_cluster_placement_primitive *cluster_placement_primitive; \/* pointer to indexing structure useful during packing stage *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_cluster_placement_primitive -cmos_variation fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params cmos_variation;$/;" m struct:s_spice_mc_params -cnt fpga_spice_include/spice_types.h /^ int cnt; \/* Used in mux_testbench only*\/$/;" m struct:s_spice_mux_model -cnt fpga_spice_include/spice_types.h /^ int cnt;$/;" m struct:s_spice_model -col_rel include/physical_types.h /^ float col_rel;$/;" m struct:s_grid_loc_def -conf_bit_head fpga_spice_include/spice_types.h /^ t_llist* conf_bit_head; $/;" m struct:s_sram_orgz_info -connections include/cad_types.h /^ struct s_pack_pattern_connections *connections; \/* linked list of connections of logic blocks in pattern *\/$/;" m struct:s_pack_pattern_block typeref:struct:s_pack_pattern_block::s_pack_pattern_connections -cont util.c /^static int cont; \/* line continued? *\/$/;" v file: -create_llist linkedlist.c /^t_llist* create_llist(int len) {$/;" f -cur include/ezxml.h /^ ezxml_t cur; \/* current xml tree insertion point *\/$/;" m struct:ezxml_root -current_random util.c /^static unsigned int current_random = 0;$/;" v file: -data include/util.h /^ int data;$/;" m struct:s_linked_int -data_vptr include/util.h /^ void *data_vptr;$/;" m struct:s_linked_vptr -dc include/physical_types.h /^ float dc;$/;" m struct:s_chan -default_mode_num_conf_bits include/physical_types.h /^ int default_mode_num_conf_bits;$/;" m struct:s_pb_type -default_mode_num_iopads include/physical_types.h /^ int default_mode_num_iopads;$/;" m struct:s_pb_type -default_mode_num_mode_bits include/physical_types.h /^ int default_mode_num_mode_bits;$/;" m struct:s_pb_type -default_mode_num_reserved_conf_bits include/physical_types.h /^ int default_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type -default_val fpga_spice_include/spice_types.h /^ int default_val;$/;" m struct:s_spice_model_port -define_idle_mode include/physical_types.h /^ int define_idle_mode; $/;" m struct:s_mode -define_physical_mode include/physical_types.h /^ int define_physical_mode; $/;" m struct:s_mode -delay_max include/physical_types.h /^ float delay_max;$/;" m struct:s_pb_graph_edge -delay_min include/physical_types.h /^ float delay_min;$/;" m struct:s_pb_graph_edge -delete_in_vptr_list util.c /^delete_in_vptr_list(struct s_linked_vptr *head) {$/;" f -dens include/physical_types.h /^ float dens; \/* Switching density of net assigned to this clock *\/$/;" m struct:s_clock_network -density fpga_spice_include/spice_types.h /^ float density;$/;" m struct:s_spice_net_info -depth include/physical_types.h /^ int depth; \/* depth of pb_type *\/$/;" m struct:s_pb_type -design_tech fpga_spice_include/spice_types.h /^ enum e_spice_model_design_tech design_tech;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_design_tech -design_tech_info fpga_spice_include/spice_types.h /^ t_spice_model_design_tech_info design_tech_info;$/;" m struct:s_spice_model -dir include/logic_types.h /^ enum PORTS dir; \/* port direction *\/$/;" m struct:s_model_ports typeref:enum:s_model_ports::PORTS -directionality include/physical_types.h /^ enum e_directionality directionality;$/;" m struct:s_segment_inf typeref:enum:s_segment_inf::e_directionality -dptr fpga_spice_include/linkedlist.h /^ void* dptr;$/;" m struct:s_llist -driver_pin include/physical_types.h /^ int driver_pin;$/;" m struct:s_pb_graph_edge -driver_set include/physical_types.h /^ int driver_set;$/;" m struct:s_pb_graph_edge -dump_structural_verilog fpga_spice_include/spice_types.h /^ boolean dump_structural_verilog;$/;" m struct:s_spice_model -dynamic include/physical_types.h /^ float dynamic;$/;" m struct:s_power_usage -e include/ezxml.h /^ char *e; \/* end of work area *\/$/;" m struct:ezxml_root -e_Fc_type include/physical_types.h /^enum e_Fc_type {$/;" g -e_directionality include/physical_types.h /^enum e_directionality {$/;" g -e_grid_loc_type include/physical_types.h /^enum e_grid_loc_type {$/;" g -e_interconnect include/physical_types.h /^enum e_interconnect {$/;" g -e_pb_graph_pin_type include/physical_types.h /^enum e_pb_graph_pin_type {$/;" g -e_pb_type_class include/physical_types.h /^enum e_pb_type_class {$/;" g -e_pin_location_distr include/physical_types.h /^enum e_pin_location_distr {$/;" g -e_pin_to_pin_annotation_format include/physical_types.h /^enum e_pin_to_pin_annotation_format {$/;" g -e_pin_to_pin_annotation_type include/physical_types.h /^enum e_pin_to_pin_annotation_type {$/;" g -e_pin_to_pin_capacitance_annotations include/physical_types.h /^enum e_pin_to_pin_capacitance_annotations {$/;" g -e_pin_to_pin_delay_annotations include/physical_types.h /^enum e_pin_to_pin_delay_annotations {$/;" g -e_pin_to_pin_mode_select_annotations include/physical_types.h /^enum e_pin_to_pin_mode_select_annotations {$/;" g -e_pin_to_pin_pack_pattern_annotations include/physical_types.h /^enum e_pin_to_pin_pack_pattern_annotations {$/;" g -e_pin_type include/physical_types.h /^enum e_pin_type {$/;" g -e_power_buffer_type include/physical_types.h /^} e_power_buffer_type;$/;" t typeref:enum:__anon2 -e_power_estimation_method include/physical_types.h /^typedef enum e_power_estimation_method_ e_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ -e_power_estimation_method_ include/physical_types.h /^enum e_power_estimation_method_ {$/;" g -e_power_wire_type include/physical_types.h /^} e_power_wire_type;$/;" t typeref:enum:__anon1 -e_side include/physical_types.h /^enum e_side {$/;" g -e_spice_accuracy_type fpga_spice_include/spice_types.h /^enum e_spice_accuracy_type {$/;" g -e_spice_model_buffer_type fpga_spice_include/spice_types.h /^enum e_spice_model_buffer_type {$/;" g -e_spice_model_design_tech fpga_spice_include/spice_types.h /^enum e_spice_model_design_tech {$/;" g -e_spice_model_pass_gate_logic_type fpga_spice_include/spice_types.h /^enum e_spice_model_pass_gate_logic_type {$/;" g -e_spice_model_port_type fpga_spice_include/spice_types.h /^enum e_spice_model_port_type {$/;" g -e_spice_model_structure fpga_spice_include/spice_types.h /^enum e_spice_model_structure {$/;" g -e_spice_model_type fpga_spice_include/spice_types.h /^enum e_spice_model_type {$/;" g -e_spice_tech_lib_type fpga_spice_include/spice_types.h /^enum e_spice_tech_lib_type {$/;" g -e_spice_trans_type fpga_spice_include/spice_types.h /^enum e_spice_trans_type {$/;" g -e_sram_orgz fpga_spice_include/spice_types.h /^enum e_sram_orgz {$/;" g -e_stat include/physical_types.h /^enum e_stat {$/;" g -e_switch_block_type include/physical_types.h /^enum e_switch_block_type {$/;" g -e_swseg_pattern_type include/physical_types.h /^enum e_swseg_pattern_type {$/;" g -e_tech_comp include/arch_types_mrfpga.h /^enum e_tech_comp { $/;" g -e_wire_model_type fpga_spice_include/spice_types.h /^enum e_wire_model_type {$/;" g -energy_per_toggle include/physical_types.h /^ float energy_per_toggle;$/;" m struct:s_port_power -ent include/ezxml.h /^ char **ent; \/* general entities (ampersand sequences) *\/$/;" m struct:ezxml_root -equivalent include/physical_types.h /^ boolean equivalent;$/;" m struct:s_port -err include/ezxml.h /^ char err[EZXML_ERRL]; \/* error string *\/$/;" m struct:ezxml_root -estimation_method include/physical_types.h /^ e_power_estimation_method estimation_method;$/;" m struct:s_pb_type_power -exist fpga_spice_include/spice_types.h /^ int exist;$/;" m struct:s_spice_model_buffer -ezxml include/ezxml.h /^struct ezxml {$/;" s -ezxml_add_child ezxml.c /^ezxml_t ezxml_add_child(ezxml_t xml, char *name, size_t off) {$/;" f -ezxml_add_child_d include/ezxml.h 149;" d -ezxml_ampencode ezxml.c /^ezxml_ampencode(const char *s, size_t len, char **dst, size_t * dlen,$/;" f file: -ezxml_attr ezxml.c /^ezxml_attr(ezxml_t xml, const char *attr) {$/;" f -ezxml_char_content ezxml.c /^static void ezxml_char_content(ezxml_root_t root, char *s,$/;" f file: -ezxml_child ezxml.c /^ezxml_t ezxml_child(ezxml_t xml, const char *name) {$/;" f -ezxml_close_tag ezxml.c /^static ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s) {$/;" f file: -ezxml_cut ezxml.c /^ezxml_t ezxml_cut(ezxml_t xml) {$/;" f -ezxml_decode ezxml.c /^ezxml_decode(char *s, char **ent, char t) {$/;" f file: -ezxml_ent_ok ezxml.c /^static int ezxml_ent_ok(char *name, char *s, char **ent) {$/;" f file: -ezxml_err ezxml.c /^static ezxml_t ezxml_err(ezxml_root_t root, char *s, const char *err, ...) {$/;" f file: -ezxml_error ezxml.c /^ezxml_error(ezxml_t xml) {$/;" f -ezxml_free ezxml.c /^void ezxml_free(ezxml_t xml) {$/;" f -ezxml_free_attr ezxml.c /^static void ezxml_free_attr(char **attr) {$/;" f file: -ezxml_get ezxml.c /^ezxml_t ezxml_get(ezxml_t xml, ...) {$/;" f -ezxml_idx ezxml.c /^ezxml_t ezxml_idx(ezxml_t xml, int idx) {$/;" f -ezxml_insert ezxml.c /^ezxml_t ezxml_insert(ezxml_t xml, ezxml_t dest, size_t off) {$/;" f -ezxml_internal_dtd ezxml.c /^static short ezxml_internal_dtd(ezxml_root_t root, char *s,$/;" f file: -ezxml_move include/ezxml.h 178;" d -ezxml_name include/ezxml.h 108;" d -ezxml_new ezxml.c /^ezxml_t ezxml_new(char *name) {$/;" f -ezxml_new_d include/ezxml.h 142;" d -ezxml_next include/ezxml.h 101;" d -ezxml_open_tag ezxml.c /^static void ezxml_open_tag(ezxml_root_t root, int line, char *name, char **attr) {$/;" f file: -ezxml_parse_fd ezxml.c /^ezxml_t ezxml_parse_fd(int fd) {$/;" f -ezxml_parse_file ezxml.c /^ezxml_t ezxml_parse_file(const char *file) {$/;" f -ezxml_parse_fp ezxml.c /^ezxml_t ezxml_parse_fp(FILE * fp) {$/;" f -ezxml_parse_str ezxml.c /^ezxml_t ezxml_parse_str(char *s, size_t len) {$/;" f -ezxml_pi ezxml.c /^ezxml_pi(ezxml_t xml, const char *target) {$/;" f -ezxml_proc_inst ezxml.c /^static void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len) {$/;" f file: -ezxml_remove include/ezxml.h 181;" d -ezxml_root include/ezxml.h /^struct ezxml_root { \/* additional data for the root tag *\/$/;" s -ezxml_root_t include/ezxml.h /^typedef struct ezxml_root *ezxml_root_t;$/;" t typeref:struct:ezxml_root -ezxml_set_attr ezxml.c /^ezxml_t ezxml_set_attr(ezxml_t xml, char *name, char *value) {$/;" f -ezxml_set_attr_d include/ezxml.h 164;" d -ezxml_set_flag ezxml.c /^ezxml_t ezxml_set_flag(ezxml_t xml, short flag) {$/;" f -ezxml_set_txt ezxml.c /^ezxml_t ezxml_set_txt(ezxml_t xml, char *txt) {$/;" f -ezxml_set_txt_d include/ezxml.h 156;" d -ezxml_str2utf8 ezxml.c /^ezxml_str2utf8(char **s, size_t * len) {$/;" f file: -ezxml_t include/ezxml.h /^typedef struct ezxml *ezxml_t;$/;" t typeref:struct:ezxml -ezxml_toxml ezxml.c /^ezxml_toxml(ezxml_t xml) {$/;" f -ezxml_toxml_r ezxml.c /^ezxml_toxml_r(ezxml_t xml, char **s, size_t * len, size_t * max, size_t start,$/;" f file: -ezxml_txt include/ezxml.h 111;" d -ezxml_vget ezxml.c /^ezxml_t ezxml_vget(ezxml_t xml, va_list ap) {$/;" f -f_per_stage fpga_spice_include/spice_types.h /^ int f_per_stage;$/;" m struct:s_spice_model_buffer -fan_in include/physical_types.h /^ int fan_in;$/;" m struct:s_interconnect -fan_out include/physical_types.h /^ int fan_out;$/;" m struct:s_interconnect -fast fpga_spice_include/spice_types.h /^ int fast;$/;" m struct:s_spice_params -file_exists util.c /^boolean file_exists(const char * filename) {$/;" f -file_line_number util.c /^int file_line_number; \/* file in line number being parsed *\/$/;" v -findPortByName read_xml_arch_file.c /^static t_port * findPortByName(const char * name, t_pb_type * pb_type,$/;" f file: -find_length_llist linkedlist.c /^int find_length_llist(t_llist* head) {$/;" f -flags include/ezxml.h /^ short flags; \/* additional information *\/$/;" m struct:ezxml -format include/physical_types.h /^ enum e_pin_to_pin_annotation_format format;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_format -frac_cb include/physical_types.h /^ float frac_cb;$/;" m struct:s_segment_inf -frac_sb include/physical_types.h /^ float frac_sb;$/;" m struct:s_segment_inf -free_chunk_memory util.c /^void free_chunk_memory(t_chunk *chunk_info) {$/;" f -free_int_list util.c /^void free_int_list(t_linked_int ** int_list_head_ptr) {$/;" f -free_ivec_matrix util.c /^void free_ivec_matrix(struct s_ivec **ivec_matrix, int nrmin, int nrmax,$/;" f -free_ivec_matrix3 util.c /^void free_ivec_matrix3(struct s_ivec ***ivec_matrix3, int nrmin, int nrmax,$/;" f -free_ivec_vector util.c /^void free_ivec_vector(struct s_ivec *ivec_vector, int nrmin, int nrmax) {$/;" f -free_llist linkedlist.c /^void free_llist(t_llist* head) {$/;" f -free_matrix util.c /^void free_matrix(void *vptr, int nrmin, int nrmax, int ncmin, size_t elsize) {$/;" f -free_matrix3 util.c /^void free_matrix3(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f -free_matrix4 util.c /^void free_matrix4(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f -freq fpga_spice_include/spice_types.h /^ float freq; $/;" m struct:s_spice_net_info -frequency include/physical_types.h /^ int frequency;$/;" m struct:s_segment_inf -from_block include/cad_types.h /^ t_pack_pattern_block *from_block;$/;" m struct:s_pack_pattern_connections -from_pin include/cad_types.h /^ t_pb_graph_pin *from_pin;$/;" m struct:s_pack_pattern_connections -from_pin include/physical_types.h /^ char *from_pin;$/;" m struct:s_direct_inf -grid_conf_bits_lsb fpga_spice_include/spice_types.h /^ int** grid_conf_bits_lsb;$/;" m struct:s_sram_orgz_info -grid_conf_bits_msb fpga_spice_include/spice_types.h /^ int** grid_conf_bits_msb;$/;" m struct:s_sram_orgz_info -grid_index_high fpga_spice_include/spice_types.h /^ int** grid_index_high;$/;" m struct:s_spice_model -grid_index_low fpga_spice_include/spice_types.h /^ int** grid_index_low;$/;" m struct:s_spice_model -grid_loc_def include/physical_types.h /^ struct s_grid_loc_def *grid_loc_def; \/* [0..num_def-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_grid_loc_def -grid_loc_type include/physical_types.h /^ enum e_grid_loc_type grid_loc_type;$/;" m struct:s_grid_loc_def typeref:enum:s_grid_loc_def::e_grid_loc_type -grid_logic_tile_area include/physical_types.h /^ float grid_logic_tile_area;$/;" m struct:s_arch -grid_reserved_conf_bits fpga_spice_include/spice_types.h /^ int** grid_reserved_conf_bits;$/;" m struct:s_sram_orgz_info -height include/physical_types.h /^ int height;$/;" m struct:s_type_descriptor -idle_mode_name include/physical_types.h /^ char* idle_mode_name;$/;" m struct:s_pb_type -include_netlist fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlist;$/;" m struct:s_spice_model -include_netlists fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlists; $/;" m struct:s_spice -included fpga_spice_include/spice_types.h /^ int included;$/;" m struct:s_spice_model_netlist -incremental_cost include/cad_types.h /^ float incremental_cost; \/* cost dependant on current status of packing *\/$/;" m struct:s_cluster_placement_primitive -index fpga_spice_include/spice_types.h /^ int index;$/;" m struct:s_conf_bit_info -index include/cad_types.h /^ int index; \/* array index for pattern*\/$/;" m struct:s_pack_patterns -index include/logic_types.h /^ int index; \/* indexing for array look-up *\/$/;" m struct:s_model_ports -index include/logic_types.h /^ int index;$/;" m struct:s_model -index include/physical_types.h /^ int index; \/* index of type descriptor in array (allows for index referencing) *\/$/;" m struct:s_type_descriptor -index include/physical_types.h /^ int index;$/;" m struct:s_mode -index include/physical_types.h /^ int index;$/;" m struct:s_port -index_in_top_tb fpga_spice_include/spice_types.h /^ int index_in_top_tb;$/;" m struct:s_conf_bit_info -infer_annotations include/physical_types.h /^ boolean infer_annotations;$/;" m struct:s_interconnect -infer_pattern include/physical_types.h /^ boolean infer_pattern; \/*If TRUE, infer pattern based on patterns connected to it*\/$/;" m struct:s_pb_graph_edge -init_arch_mrfpga read_xml_mrfpga.c /^void init_arch_mrfpga(t_arch_mrfpga* arch_mrfpga) {$/;" f -init_buffer_inf read_xml_mrfpga.c /^void init_buffer_inf(t_buffer_inf* buffer_inf) {$/;" f -init_memristor_inf read_xml_mrfpga.c /^void init_memristor_inf(t_memristor_inf* memristor_inf) {$/;" f -init_val fpga_spice_include/spice_types.h /^ int init_val;$/;" m struct:s_spice_net_info -inport_link_pin include/cad_types.h /^ int inport_link_pin; \/* applicable pin of chain input port *\/$/;" m struct:s_model_chain_pattern -input_buffer fpga_spice_include/spice_types.h /^ t_spice_model_buffer* input_buffer;$/;" m struct:s_spice_model -input_edges include/physical_types.h /^ struct s_pb_graph_edge** input_edges; \/* [0..num_input_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge -input_level fpga_spice_include/spice_types.h /^ int* input_level; \/* [0...num_input] *\/$/;" m struct:s_spice_mux_arch -input_link_port include/cad_types.h /^ t_model_ports *input_link_port; \/* pointer to port of chain input *\/$/;" m struct:s_model_chain_pattern -input_offset fpga_spice_include/spice_types.h /^ int* input_offset; \/* [0...num_input] *\/ $/;" m struct:s_spice_mux_arch -input_pin_class_size include/physical_types.h /^ int *input_pin_class_size; \/* Stores the number of pins that belong to a particular input pin class *\/$/;" m struct:s_pb_graph_node -input_pins include/physical_types.h /^ char * input_pins;$/;" m struct:s_pin_to_pin_annotation -input_pins include/physical_types.h /^ struct s_pb_graph_pin *** input_pins; \/\/ [0..num_input_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin -input_pins include/physical_types.h /^ t_pb_graph_pin **input_pins; \/* [0..num_input_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node -input_pins include/physical_types.h /^ t_pb_graph_pin **input_pins;$/;" m struct:s_pb_graph_edge -input_ports_eq_auto_detect include/physical_types.h /^ boolean input_ports_eq_auto_detect;$/;" m struct:s_type_descriptor -input_slew_fall_time fpga_spice_include/spice_types.h /^ float input_slew_fall_time; $/;" m struct:s_spice_stimulate_params -input_slew_fall_type fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -input_slew_rise_time fpga_spice_include/spice_types.h /^ float input_slew_rise_time; $/;" m struct:s_spice_stimulate_params -input_slew_rise_type fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type -input_string include/physical_types.h /^ char *input_string;$/;" m struct:s_interconnect -input_thres_pct_fall fpga_spice_include/spice_types.h /^ float input_thres_pct_fall;$/;" m struct:s_spice_meas_params -input_thres_pct_rise fpga_spice_include/spice_types.h /^ float input_thres_pct_rise;$/;" m struct:s_spice_meas_params -inputs include/logic_types.h /^ t_model_ports *inputs; \/* linked list of input\/clock ports *\/$/;" m struct:s_model -insert_in_int_list util.c /^insert_in_int_list(t_linked_int * head, int data,$/;" f -insert_in_vptr_list util.c /^insert_in_vptr_list(struct s_linked_vptr *head, void *vptr_to_add) {$/;" f -insert_llist_node linkedlist.c /^t_llist* insert_llist_node(t_llist* cur) {$/;" f -insert_llist_node_before_head linkedlist.c /^t_llist* insert_llist_node_before_head(t_llist* old_head) {$/;" f -insert_node_to_int_list util.c /^insert_node_to_int_list(struct s_linked_int *head, int int_to_add) {$/;" f -instances include/logic_types.h /^ void *instances;$/;" m struct:s_model -interconnect include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_interconnect_pins -interconnect include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_pb_graph_edge -interconnect include/physical_types.h /^ t_interconnect *interconnect;$/;" m struct:s_mode -interconnect_pins include/physical_types.h /^ t_interconnect_pins ** interconnect_pins; \/* [0..num_modes-1][0..num_interconnect_in_mode] *\/$/;" m struct:s_pb_graph_node -interconnect_power include/physical_types.h /^ t_interconnect_power * interconnect_power;$/;" m struct:s_interconnect -inv_spice_model fpga_spice_include/spice_types.h /^ t_spice_model* inv_spice_model;$/;" m struct:s_spice_model_port -inv_spice_model_name fpga_spice_include/spice_types.h /^ char* inv_spice_model_name;$/;" m struct:s_spice_model_port -io_vdd fpga_spice_include/spice_types.h /^ float io_vdd;$/;" m struct:s_spice_tech_lib -ipin_mux_trans_size include/physical_types.h /^ float ipin_mux_trans_size;$/;" m struct:s_arch -ipow util.c /^int ipow(int base, int exp) {$/;" f -is_Fc_frac include/physical_types.h /^ boolean *is_Fc_frac; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -is_Fc_full_flex include/physical_types.h /^ boolean *is_Fc_full_flex; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -is_accurate include/arch_types_mrfpga.h /^ boolean is_accurate;$/;" m struct:s_arch_mrfpga -is_block_optional include/cad_types.h /^ boolean *is_block_optional; \/* [0..num_blocks-1] is the block_id in this pattern mandatory or optional to form a molecule *\/$/;" m struct:s_pack_patterns -is_chain include/cad_types.h /^ boolean is_chain; \/* Does this pattern chain across logic blocks *\/$/;" m struct:s_pack_patterns -is_clock include/logic_types.h /^ boolean is_clock; \/* clock? *\/$/;" m struct:s_model_ports -is_clock include/physical_types.h /^ boolean is_clock;$/;" m struct:s_port -is_config_enable fpga_spice_include/spice_types.h /^ boolean is_config_enable;$/;" m struct:s_spice_model_port -is_default fpga_spice_include/spice_types.h /^ int is_default;$/;" m struct:s_spice_model -is_forced_connection include/physical_types.h /^ boolean is_forced_connection; \/* This output pin connects to one and only one input pin *\/$/;" m struct:s_pb_graph_pin -is_global fpga_spice_include/spice_types.h /^ boolean is_global;$/;" m struct:s_spice_model_port -is_global_pin include/physical_types.h /^ boolean *is_global_pin; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -is_isolation include/arch_types_mrfpga.h /^ boolean is_isolation;$/;" m struct:s_arch_mrfpga -is_junction include/arch_types_mrfpga.h /^ boolean is_junction;$/;" m struct:s_arch_mrfpga -is_mrFPGA include/arch_types_mrfpga.h /^ boolean is_mrFPGA;$/;" m struct:s_arch_mrfpga -is_non_clock_global include/logic_types.h /^ boolean is_non_clock_global; \/* not a clock but is a special, global, control signal (eg global asynchronous reset, etc) *\/$/;" m struct:s_model_ports -is_non_clock_global include/physical_types.h /^ boolean is_non_clock_global;$/;" m struct:s_port -is_opin_cblock_defined include/arch_types_mrfpga.h /^ int is_opin_cblock_defined;$/;" m struct:s_arch_mrfpga -is_prog fpga_spice_include/spice_types.h /^ boolean is_prog;$/;" m struct:s_spice_model_port -is_reset fpga_spice_include/spice_types.h /^ boolean is_reset;$/;" m struct:s_spice_model_port -is_set fpga_spice_include/spice_types.h /^ boolean is_set;$/;" m struct:s_spice_model_port -is_show_pass_trans include/arch_types_mrfpga.h /^ boolean is_show_pass_trans;$/;" m struct:s_arch_mrfpga -is_show_sram include/arch_types_mrfpga.h /^ boolean is_show_sram;$/;" m struct:s_arch_mrfpga -is_stack include/arch_types_mrfpga.h /^ boolean is_stack;$/;" m struct:s_arch_mrfpga -is_wire_buffer include/arch_types_mrfpga.h /^ boolean is_wire_buffer;$/;" m struct:s_arch_mrfpga -leakage include/physical_types.h /^ float leakage;$/;" m struct:s_power_usage -leakage_default_mode include/physical_types.h /^ int leakage_default_mode; \/* Default mode for leakage analysis, if block has no set mode *\/$/;" m struct:s_pb_type_power -len include/ezxml.h /^ size_t len; \/* length of allocated memory for mmap, -1 for malloc *\/$/;" m struct:ezxml_root -length include/physical_types.h /^ int length;$/;" m struct:s_segment_inf -level fpga_spice_include/spice_types.h /^ int level;$/;" m struct:s_spice_model_wire_param -limit_value util.c /^int limit_value(int cur, int max, const char *name) {$/;" f -line include/ezxml.h /^ int line;$/;" m struct:ezxml -line include/physical_types.h /^ int line;$/;" m struct:s_direct_inf -line_num include/physical_types.h /^ int line_num; \/* Interconnect is processed later, need to know what line number it messed up on to give proper error message *\/$/;" m struct:s_interconnect -line_num include/physical_types.h /^ int line_num; \/* used to report what line number this annotation is found in architecture file *\/$/;" m struct:s_pin_to_pin_annotation -list include/util.h /^ int *list;$/;" m struct:s_ivec -list_of_connectable_input_pin_ptrs include/physical_types.h /^ struct s_pb_graph_pin ***list_of_connectable_input_pin_ptrs; \/* [0..depth-1][0..num_connectable_primtive_input_pins-1] what input pins this output can connect to without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin -local_interc_factor include/physical_types.h /^ float local_interc_factor;$/;" m struct:s_power_arch -logical_effort_factor include/physical_types.h /^ float logical_effort_factor;$/;" m struct:s_power_arch -longline include/physical_types.h /^ boolean longline;$/;" m struct:s_segment_inf -lut_input_buffer fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_input_buffer;$/;" m struct:s_spice_model -m include/ezxml.h /^ char *m; \/* original xml string *\/$/;" m struct:ezxml_root -main ezxml.c /^main(int argc,$/;" f -main main.c /^int main(int argc, char **argv) {$/;" f -main_best_buffer_list include/arch_types_mrfpga.h /^ t_linked_int* main_best_buffer_list;$/;" m struct:s_arch_mrfpga -max_internal_delay include/physical_types.h /^ float max_internal_delay;$/;" m struct:s_pb_type -max_pins_per_side include/arch_types_mrfpga.h /^ int max_pins_per_side;$/;" m struct:s_arch_mrfpga -mc_params fpga_spice_include/spice_types.h /^ t_spice_mc_params mc_params;$/;" m struct:s_spice_params -mc_sim fpga_spice_include/spice_types.h /^ boolean mc_sim;$/;" m struct:s_spice_mc_params -meas_params fpga_spice_include/spice_types.h /^ t_spice_meas_params meas_params;$/;" m struct:s_spice_params -mem_avail include/util.h /^ int mem_avail; \/* number of bytes left in the current chunk *\/$/;" m struct:s_chunk -mem_bank_info fpga_spice_include/spice_types.h /^ t_mem_bank_info* mem_bank_info; \/* Only be allocated when orgz type is memory bank *\/$/;" m struct:s_sram_orgz_info -mem_model fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_mem_bank_info -mem_model fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_scff_info -mem_model fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_standalone_sram_info -memristor_inf include/arch_types_mrfpga.h /^ t_memristor_inf memristor_inf;$/;" m struct:s_arch_mrfpga -messagelogger include/util.h /^typedef unsigned char (*messagelogger)( TIO_MessageMode_t messageMode,$/;" t -min_size include/logic_types.h /^ int min_size; \/* minimum number of pins *\/$/;" m struct:s_model_ports -min_width fpga_spice_include/spice_types.h /^ float min_width;$/;" m struct:s_spice_transistor_type -mode_bits include/physical_types.h /^ char* mode_bits; \/* Mode bits to select *\/$/;" m struct:s_pb_type -mode_power include/physical_types.h /^ t_mode_power * mode_power;$/;" m struct:s_mode -mode_select fpga_spice_include/spice_types.h /^ boolean mode_select;$/;" m struct:s_spice_model_port -model include/cad_types.h /^ t_model *model; \/* block associated with chain *\/$/;" m struct:s_model_chain_pattern -model include/physical_types.h /^ t_model *model;$/;" m struct:s_pb_type -model_library include/physical_types.h /^ t_model *model_library;$/;" m struct:s_arch -model_name fpga_spice_include/spice_types.h /^ char* model_name;$/;" m struct:s_spice_transistor_type -model_netlist fpga_spice_include/spice_types.h /^ char* model_netlist; \/* SPICE netlist provided by user *\/$/;" m struct:s_spice_model -model_port include/physical_types.h /^ t_model_ports *model_port;$/;" m struct:s_port -model_ref fpga_spice_include/spice_types.h /^ char* model_ref;$/;" m struct:s_spice_tech_lib -models include/physical_types.h /^ t_model *models;$/;" m struct:s_arch -modes include/physical_types.h /^ t_mode *modes; \/* [0..num_modes-1] *\/$/;" m struct:s_pb_type -mux_num_level fpga_spice_include/spice_types.h /^ int mux_num_level;$/;" m struct:s_spice_model_design_tech_info -mux_trans_size include/physical_types.h /^ float mux_trans_size;$/;" m struct:s_switch_inf -mux_transistor_size include/physical_types.h /^ float mux_transistor_size;$/;" m struct:s_power_arch -my_atoi util.c /^int my_atoi(const char *str) {$/;" f -my_calloc util.c /^my_calloc(size_t nelem, size_t size) {$/;" f -my_chunk_malloc util.c /^my_chunk_malloc(size_t size, t_chunk *chunk_info) {$/;" f -my_fgets util.c /^my_fgets(char *buf, int max_size, FILE * fp) {$/;" f -my_fopen util.c /^my_fopen(const char *fname, const char *flag, int prompt) {$/;" f -my_frand util.c /^float my_frand(void) {$/;" f -my_free read_xml_spice_util.c /^void my_free(void* ptr) {$/;" f -my_irand util.c /^int my_irand(int imax) {$/;" f -my_malloc util.c /^my_malloc(size_t size) {$/;" f -my_realloc util.c /^my_realloc(void *ptr, size_t size) {$/;" f -my_srandom util.c /^void my_srandom(int seed) {$/;" f -my_strdup util.c /^my_strdup(const char *str) {$/;" f -my_strncpy util.c /^my_strncpy(char *dest, const char *src, size_t size) {$/;" f -my_strtok util.c /^my_strtok(char *ptr, const char *tokens, FILE * fp, char *buf) {$/;" f -name fpga_spice_include/spice_types.h /^ char* name;$/;" m struct:s_spice_model -name include/cad_types.h /^ char *name; \/* name of this chain of logic *\/$/;" m struct:s_model_chain_pattern -name include/cad_types.h /^ char *name; \/* name of this logic model pattern *\/$/;" m struct:s_pack_patterns -name include/ezxml.h /^ char *name; \/* tag name *\/$/;" m struct:ezxml -name include/logic_types.h /^ char *name; \/* name of this logic model *\/$/;" m struct:s_model -name include/logic_types.h /^ char *name; \/* name of this port *\/$/;" m struct:s_model_ports -name include/physical_types.h /^ char *name;$/;" m struct:s_direct_inf -name include/physical_types.h /^ char *name;$/;" m struct:s_interconnect -name include/physical_types.h /^ char *name;$/;" m struct:s_switch_inf -name include/physical_types.h /^ char *name;$/;" m struct:s_type_descriptor -name include/physical_types.h /^ char* name;$/;" m struct:s_mode -name include/physical_types.h /^ char* name;$/;" m struct:s_pb_type -name include/physical_types.h /^ char* name;$/;" m struct:s_port -nelem include/util.h /^ int nelem;$/;" m struct:s_ivec -next fpga_spice_include/linkedlist.h /^ t_llist* next;$/;" m struct:s_llist -next include/cad_types.h /^ struct s_model_chain_pattern *next; \/* next chain (linked list) *\/$/;" m struct:s_model_chain_pattern typeref:struct:s_model_chain_pattern::s_model_chain_pattern -next include/cad_types.h /^ struct s_pack_pattern_connections *next;$/;" m struct:s_pack_pattern_connections typeref:struct:s_pack_pattern_connections::s_pack_pattern_connections -next include/ezxml.h /^ ezxml_t next; \/* next tag with same name in this section at this depth *\/$/;" m struct:ezxml -next include/logic_types.h /^ struct s_model *next; \/* next model (linked list) *\/$/;" m struct:s_model typeref:struct:s_model::s_model -next include/logic_types.h /^ struct s_model_ports *next; \/* next port *\/$/;" m struct:s_model_ports typeref:struct:s_model_ports::s_model_ports -next include/util.h /^ struct s_linked_int *next;$/;" m struct:s_linked_int typeref:struct:s_linked_int::s_linked_int -next include/util.h /^ struct s_linked_vptr *next;$/;" m struct:s_linked_vptr typeref:struct:s_linked_vptr::s_linked_vptr -next_mem_loc_ptr include/util.h /^ char *next_mem_loc_ptr;\/* pointer to the first available (free) *$/;" m struct:s_chunk -next_primitive include/cad_types.h /^ struct s_cluster_placement_primitive *next_primitive;$/;" m struct:s_cluster_placement_primitive typeref:struct:s_cluster_placement_primitive::s_cluster_placement_primitive -nint include/util.h 24;" d -nmos_size fpga_spice_include/spice_types.h /^ float nmos_size;$/;" m struct:s_spice_model_pass_gate_logic -nominal_vdd fpga_spice_include/spice_types.h /^ float nominal_vdd;$/;" m struct:s_spice_tech_lib -num_annotations include/physical_types.h /^ int num_annotations;$/;" m struct:s_interconnect -num_annotations include/physical_types.h /^ int num_annotations;$/;" m struct:s_pb_type -num_bl fpga_spice_include/spice_types.h /^ int num_bl; \/* Number of Bit Lines in total *\/$/;" m struct:s_mem_bank_info -num_blocks include/cad_types.h /^ int num_blocks; \/* number of blocks in pattern *\/$/;" m struct:s_pack_patterns -num_cb_switch include/physical_types.h /^ int num_cb_switch;$/;" m struct:s_arch -num_class include/physical_types.h /^ int num_class;$/;" m struct:s_type_descriptor -num_clock_pins include/physical_types.h /^ int *num_clock_pins; \/* [0..num_clock_ports - 1] *\/$/;" m struct:s_pb_graph_node -num_clock_pins include/physical_types.h /^ int num_clock_pins;$/;" m struct:s_pb_type -num_clock_ports include/physical_types.h /^ int num_clock_ports;$/;" m struct:s_pb_graph_node -num_clocks fpga_spice_include/spice_types.h /^ int num_clocks;$/;" m struct:s_spice_stimulate_params -num_connectable_primtive_input_pins include/physical_types.h /^ int *num_connectable_primtive_input_pins; \/* [0..depth-1] number of input pins that this output pin can reach without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin -num_directs include/physical_types.h /^ int num_directs;$/;" m struct:s_arch -num_drivers include/physical_types.h /^ int num_drivers;$/;" m struct:s_type_descriptor -num_global_clocks include/physical_types.h /^ int num_global_clocks;$/;" m struct:s_clock_arch -num_grid_loc_def include/physical_types.h /^ int num_grid_loc_def;$/;" m struct:s_type_descriptor -num_include_netlist fpga_spice_include/spice_types.h /^ int num_include_netlist;$/;" m struct:s_spice -num_input fpga_spice_include/spice_types.h /^ int num_input;$/;" m struct:s_spice_mux_arch -num_input_basis fpga_spice_include/spice_types.h /^ int num_input_basis;$/;" m struct:s_spice_mux_arch -num_input_edges include/physical_types.h /^ int num_input_edges;$/;" m struct:s_pb_graph_pin -num_input_last_level fpga_spice_include/spice_types.h /^ int num_input_last_level;$/;" m struct:s_spice_mux_arch -num_input_per_level fpga_spice_include/spice_types.h /^ int* num_input_per_level; \/* [0...num_level] *\/$/;" m struct:s_spice_mux_arch -num_input_pin_class include/physical_types.h /^ int num_input_pin_class; \/* number of pin classes that this input pb_graph_node has *\/$/;" m struct:s_pb_graph_node -num_input_pins include/physical_types.h /^ int *num_input_pins; \/* [0..num_input_ports - 1] *\/$/;" m struct:s_pb_graph_node -num_input_pins include/physical_types.h /^ int num_input_pins; \/* inputs not including clock pins *\/$/;" m struct:s_pb_type -num_input_pins include/physical_types.h /^ int num_input_pins;$/;" m struct:s_pb_graph_edge -num_input_ports include/physical_types.h /^ int num_input_ports;$/;" m struct:s_interconnect_power -num_input_ports include/physical_types.h /^ int num_input_ports;$/;" m struct:s_pb_graph_node -num_interconnect include/physical_types.h /^ int num_interconnect;$/;" m struct:s_mode -num_level fpga_spice_include/spice_types.h /^ int num_level;$/;" m struct:s_spice_mux_arch -num_mc_points fpga_spice_include/spice_types.h /^ int num_mc_points;$/;" m struct:s_spice_mc_params -num_mem_bit fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_mem_bank_info -num_mem_bit fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_scff_info -num_mem_bit fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_standalone_sram_info -num_modes include/physical_types.h /^ int num_modes;$/;" m struct:s_pb_type -num_mux include/physical_types.h /^ int num_mux;$/;" m struct:s_interconnect -num_normal_switch include/arch_types_mrfpga.h /^ short num_normal_switch;$/;" m struct:s_arch_mrfpga -num_output_edges include/physical_types.h /^ int num_output_edges;$/;" m struct:s_pb_graph_pin -num_output_pin_class include/physical_types.h /^ int num_output_pin_class; \/* number of output pin classes that this pb_graph_node has *\/$/;" m struct:s_pb_graph_node -num_output_pins include/physical_types.h /^ int *num_output_pins; \/* [0..num_output_ports - 1] *\/$/;" m struct:s_pb_graph_node -num_output_pins include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_graph_edge -num_output_pins include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_type -num_output_ports include/physical_types.h /^ int num_output_ports;$/;" m struct:s_interconnect_power -num_output_ports include/physical_types.h /^ int num_output_ports;$/;" m struct:s_pb_graph_node -num_pack_patterns include/physical_types.h /^ int num_pack_patterns;$/;" m struct:s_pb_graph_edge -num_pb include/physical_types.h /^ int num_pb;$/;" m struct:s_pb_type -num_pb_type_children include/physical_types.h /^ int num_pb_type_children;$/;" m struct:s_mode -num_pin_loc_assignments include/physical_types.h /^ int **num_pin_loc_assignments; \/* [0..height-1][0..3] *\/$/;" m struct:s_type_descriptor -num_pin_timing include/physical_types.h /^ int num_pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin -num_pins include/physical_types.h /^ int num_pins;$/;" m struct:s_class -num_pins include/physical_types.h /^ int num_pins;$/;" m struct:s_port -num_pins include/physical_types.h /^ int num_pins;$/;" m struct:s_type_descriptor -num_pins_per_port include/physical_types.h /^ int num_pins_per_port;$/;" m struct:s_interconnect_power -num_port fpga_spice_include/spice_types.h /^ int num_port;$/;" m struct:s_spice_model -num_ports include/physical_types.h /^ int num_ports;$/;" m struct:s_pb_type -num_receivers include/physical_types.h /^ int num_receivers;$/;" m struct:s_type_descriptor -num_scff fpga_spice_include/spice_types.h /^ int num_scff; \/* Number of Scan-chain flip-flops *\/$/;" m struct:s_scff_info -num_segments include/physical_types.h /^ int num_segments;$/;" m struct:s_arch -num_sigma fpga_spice_include/spice_types.h /^ int num_sigma;$/;" m struct:s_spice_mc_variation_params -num_sim_clock_cycles fpga_spice_include/spice_types.h /^ int num_sim_clock_cycles;$/;" m struct:s_spicetb_info -num_spice_model fpga_spice_include/spice_types.h /^ int num_spice_model;$/;" m struct:s_spice -num_sram fpga_spice_include/spice_types.h /^ int num_sram; \/* Number of SRAMs in total *\/$/;" m struct:s_standalone_sram_info -num_switches include/physical_types.h /^ int num_switches;$/;" m struct:s_arch -num_swseg_pattern include/physical_types.h /^ int num_swseg_pattern;$/;" m struct:s_arch -num_transistor_type fpga_spice_include/spice_types.h /^ int num_transistor_type;$/;" m struct:s_spice_tech_lib -num_value_prop_pairs include/physical_types.h /^ int num_value_prop_pairs;$/;" m struct:s_pin_to_pin_annotation -num_wl fpga_spice_include/spice_types.h /^ int num_wl; \/* Number of Word Lines in total *\/$/;" m struct:s_mem_bank_info -off include/ezxml.h /^ size_t off; \/* tag offset from start of parent tag character content *\/$/;" m struct:ezxml -op_clock_freq fpga_spice_include/spice_types.h /^ float op_clock_freq; \/* Operation clock frequency*\/$/;" m struct:s_spice_stimulate_params -open ezxml.c 58;" d file: -opin_switch include/physical_types.h /^ short opin_switch;$/;" m struct:s_segment_inf -opin_to_cb include/physical_types.h /^ boolean opin_to_cb;$/;" m struct:s_type_descriptor -ordered include/ezxml.h /^ ezxml_t ordered; \/* next tag, same section and depth, in original order *\/$/;" m struct:ezxml -out_file_prefix util.c /^char *out_file_prefix = NULL;$/;" v -outport_link_pin include/cad_types.h /^ int outport_link_pin; \/* applicable pin of chain output port *\/$/;" m struct:s_model_chain_pattern -output_buffer fpga_spice_include/spice_types.h /^ t_spice_model_buffer* output_buffer;$/;" m struct:s_spice_model -output_edges include/physical_types.h /^ struct s_pb_graph_edge** output_edges; \/* [0..num_output_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge -output_link_port include/cad_types.h /^ t_model_ports *output_link_port; \/* pointer to port of chain output *\/$/;" m struct:s_model_chain_pattern -output_pin_class_size include/physical_types.h /^ int *output_pin_class_size; \/* Stores the number of pins that belong to a particular output pin class *\/$/;" m struct:s_pb_graph_node -output_pins include/physical_types.h /^ char * output_pins;$/;" m struct:s_pin_to_pin_annotation -output_pins include/physical_types.h /^ struct s_pb_graph_pin *** output_pins; \/\/ [0..num_output_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin -output_pins include/physical_types.h /^ t_pb_graph_pin **output_pins; \/* [0..num_output_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node -output_pins include/physical_types.h /^ t_pb_graph_pin **output_pins;$/;" m struct:s_pb_graph_edge -output_ports_eq_auto_detect include/physical_types.h /^ boolean output_ports_eq_auto_detect;$/;" m struct:s_type_descriptor -output_string include/physical_types.h /^ char *output_string;$/;" m struct:s_interconnect -output_thres_pct_fall fpga_spice_include/spice_types.h /^ float output_thres_pct_fall;$/;" m struct:s_spice_meas_params -output_thres_pct_rise fpga_spice_include/spice_types.h /^ float output_thres_pct_rise;$/;" m struct:s_spice_meas_params -outputs include/logic_types.h /^ t_model_ports *outputs; \/* linked list of output ports *\/$/;" m struct:s_model -pack_pattern_indices include/physical_types.h /^ int *pack_pattern_indices; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge -pack_pattern_names include/physical_types.h /^ char **pack_pattern_names; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge -parent include/ezxml.h /^ ezxml_t parent; \/* parent tag, NULL if current tag is root tag *\/$/;" m struct:ezxml -parent_mode include/physical_types.h /^ t_mode * parent_mode;$/;" m struct:s_interconnect -parent_mode include/physical_types.h /^ t_mode *parent_mode;$/;" m struct:s_pb_type -parent_mode_index include/physical_types.h /^ int parent_mode_index;$/;" m struct:s_interconnect -parent_node include/physical_types.h /^ struct s_pb_graph_node *parent_node;$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_node -parent_pb_graph_node include/physical_types.h /^ struct s_pb_graph_node *parent_pb_graph_node;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node -parent_pb_type include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type -parent_pb_type include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_port typeref:struct:s_port::s_pb_type -parent_pin_class include/physical_types.h /^ int *parent_pin_class; \/* [0..depth-1] the grouping of pins that this particular pin belongs to *\/$/;" m struct:s_pb_graph_pin -parent_spice_model fpga_spice_include/spice_types.h /^ t_spice_model* parent_spice_model;$/;" m struct:s_conf_bit_info -parent_spice_model_index fpga_spice_include/spice_types.h /^ int parent_spice_model_index;$/;" m struct:s_conf_bit_info -pass_gate_info fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_info;$/;" m struct:s_spice_model_design_tech_info -pass_gate_logic fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_logic;$/;" m struct:s_spice_model -path fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_model_netlist -path fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_tech_lib -pattern_index include/cad_types.h /^ int pattern_index; \/* index of pattern that this block is a part of *\/$/;" m struct:s_pack_pattern_block -pattern_length include/physical_types.h /^ int pattern_length;$/;" m struct:s_swseg_pattern_inf -patterns include/physical_types.h /^ boolean* patterns;$/;" m struct:s_swseg_pattern_inf -pb_graph_head include/physical_types.h /^ t_pb_graph_node *pb_graph_head;$/;" m struct:s_type_descriptor -pb_graph_node include/cad_types.h /^ t_pb_graph_node *pb_graph_node;$/;" m struct:s_cluster_placement_primitive -pb_node_power include/physical_types.h /^ t_pb_graph_node_power * pb_node_power;$/;" m struct:s_pb_graph_node -pb_type include/cad_types.h /^ const t_pb_type *pb_type; \/* pb_type that this block is an instance of *\/$/;" m struct:s_pack_pattern_block -pb_type include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_type -pb_type include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_pb_type -pb_type_children include/physical_types.h /^ struct s_pb_type *pb_type_children; \/* [0..num_child_pb_types] *\/$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type -pb_type_power include/physical_types.h /^ t_pb_type_power * pb_type_power;$/;" m struct:s_pb_type -pb_types include/logic_types.h /^ struct s_linked_vptr *pb_types; \/* Physical block types that implement this model *\/$/;" m struct:s_model typeref:struct:s_model::s_linked_vptr -peak include/physical_types.h /^ float peak;$/;" m struct:s_chan -period include/physical_types.h /^ float period; \/* Period of clock *\/$/;" m struct:s_clock_network -physical_mode_name include/physical_types.h /^ char* physical_mode_name;$/;" m struct:s_pb_type -physical_mode_num_conf_bits include/physical_types.h /^ int physical_mode_num_conf_bits;$/;" m struct:s_pb_type -physical_mode_num_iopads include/physical_types.h /^ int physical_mode_num_iopads;$/;" m struct:s_pb_type -physical_mode_num_reserved_conf_bits include/physical_types.h /^ int physical_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type -pi include/ezxml.h /^ char ***pi; \/* processing instructions *\/$/;" m struct:ezxml_root -pin_class include/physical_types.h /^ int *pin_class; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -pin_class include/physical_types.h /^ int pin_class;$/;" m struct:s_pb_graph_pin -pin_count_in_cluster include/physical_types.h /^ int pin_count_in_cluster;$/;" m struct:s_pb_graph_pin -pin_height include/physical_types.h /^ int *pin_height; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor -pin_index_per_side include/physical_types.h /^ int* pin_index_per_side;$/;" m struct:s_type_descriptor -pin_loc_assignments include/physical_types.h /^ char ****pin_loc_assignments; \/* [0..height-1][0..3][0..num_tokens-1][0..string_name] *\/$/;" m struct:s_type_descriptor -pin_location_distribution include/physical_types.h /^ enum e_pin_location_distr pin_location_distribution;$/;" m struct:s_type_descriptor typeref:enum:s_type_descriptor::e_pin_location_distr -pin_number include/physical_types.h /^ int pin_number;$/;" m struct:s_pb_graph_pin -pin_power include/physical_types.h /^ t_pb_graph_pin_power * pin_power;$/;" m struct:s_pb_graph_pin -pin_ptc_to_side include/physical_types.h /^ int* pin_ptc_to_side;$/;" m struct:s_type_descriptor -pin_timing include/physical_types.h /^ struct s_pb_graph_pin** pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin -pin_timing_del_max include/physical_types.h /^ float *pin_timing_del_max; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin -pin_toggle_initialized include/physical_types.h /^ boolean pin_toggle_initialized;$/;" m struct:s_port_power -pinlist include/physical_types.h /^ int *pinlist; \/* [0..num_pins - 1] *\/$/;" m struct:s_class -pinloc include/physical_types.h /^ int ***pinloc; \/* [0..height-1][0..3][0..num_pins-1] *\/$/;" m struct:s_type_descriptor -placement_index include/physical_types.h /^ int placement_index;$/;" m struct:s_pb_graph_node -pmos_size fpga_spice_include/spice_types.h /^ float pmos_size;$/;" m struct:s_spice_model_pass_gate_logic -pn_ratio fpga_spice_include/spice_types.h /^ float pn_ratio;$/;" m struct:s_spice_tech_lib -port include/physical_types.h /^ t_port *port;$/;" m struct:s_pb_graph_pin -port_class include/physical_types.h /^ char * port_class;$/;" m struct:s_port -port_index_by_type include/physical_types.h /^ int port_index_by_type;$/;" m struct:s_port -port_info_initialized include/physical_types.h /^ boolean port_info_initialized;$/;" m struct:s_interconnect_power -port_power include/physical_types.h /^ t_port_power * port_power;$/;" m struct:s_port -ports fpga_spice_include/spice_types.h /^ t_spice_model_port* ports;$/;" m struct:s_spice_model -ports include/physical_types.h /^ t_port *ports; \/* [0..num_ports] *\/$/;" m struct:s_pb_type -post fpga_spice_include/spice_types.h /^ int post;$/;" m struct:s_spice_params -power include/physical_types.h /^ t_power_arch * power;$/;" m struct:s_arch -power_buffer_size include/physical_types.h /^ float power_buffer_size;$/;" m struct:s_switch_inf -power_buffer_type include/physical_types.h /^ e_power_buffer_type power_buffer_type;$/;" m struct:s_switch_inf -power_gated fpga_spice_include/spice_types.h /^ boolean power_gated;$/;" m struct:s_spice_model_design_tech_info -power_method_inherited read_xml_arch_file.c /^e_power_estimation_method power_method_inherited($/;" f -power_usage include/physical_types.h /^ t_power_usage power_usage; \/* Power usage of this mode *\/$/;" m struct:s_mode_power -power_usage include/physical_types.h /^ t_power_usage power_usage; \/* Total power usage of this pb type *\/$/;" m struct:s_pb_type_power -power_usage include/physical_types.h /^ t_power_usage power_usage;$/;" m struct:s_interconnect_power -power_usage_bufs_wires include/physical_types.h /^ t_power_usage power_usage_bufs_wires; \/* Power dissipated in local buffers and wire switching (Subset of total power) *\/$/;" m struct:s_pb_type_power -prefix fpga_spice_include/spice_types.h /^ char* prefix; $/;" m struct:s_spice_model_port -prefix fpga_spice_include/spice_types.h /^ char* prefix; \/* Prefix when it show up in the spice netlist *\/$/;" m struct:s_spice_model -print_help main.c /^void print_help() {$/;" f -print_int_matrix3 util.c /^void print_int_matrix3(int ***vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f -priority include/physical_types.h /^ int priority;$/;" m struct:s_grid_loc_def -prob include/physical_types.h /^ float prob; \/* Static probability of net assigned to this clock *\/$/;" m struct:s_clock_network -probability fpga_spice_include/spice_types.h /^ float probability;$/;" m struct:s_spice_net_info -prog_clock_freq fpga_spice_include/spice_types.h /^ float prog_clock_freq; \/* Programming clock frequency, used during programming phase only *\/$/;" m struct:s_spice_stimulate_params -prop include/physical_types.h /^ int * prop; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation -pwh fpga_spice_include/spice_types.h /^ float pwh;$/;" m struct:s_spice_net_info -pwl fpga_spice_include/spice_types.h /^ float pwl;$/;" m struct:s_spice_net_info -read ezxml.c 59;" d file: -read_xml_spice include/physical_types.h /^ boolean read_xml_spice;$/;" m struct:s_arch -relative_length include/physical_types.h /^ float relative_length;$/;" m union:s_port_power::__anon3 -remove_llist_node linkedlist.c /^void remove_llist_node(t_llist* cur) { $/;" f -repeat include/physical_types.h /^ int repeat;$/;" m struct:s_grid_loc_def -res_val fpga_spice_include/spice_types.h /^ float res_val;$/;" m struct:s_spice_model_wire_param -reserved_bl fpga_spice_include/spice_types.h /^ int reserved_bl; \/* Number of reserved BLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info -reserved_wl fpga_spice_include/spice_types.h /^ int reserved_wl; \/* Number of reserved WLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info -reverse_llist linkedlist.c /^t_llist* reverse_llist(t_llist* head) {$/;" f -reverse_scaled include/physical_types.h /^ boolean reverse_scaled; \/* Scale by (1-prob) *\/$/;" m struct:s_port_power -roff fpga_spice_include/spice_types.h /^ float roff;$/;" m struct:s_spice_model_design_tech_info -ron fpga_spice_include/spice_types.h /^ float ron;$/;" m struct:s_spice_model_design_tech_info -root_block include/cad_types.h /^ t_pack_pattern_block *root_block; \/* root block used by this pattern *\/$/;" m struct:s_pack_patterns -rram_pass_tran_value include/arch_types_mrfpga.h /^ float rram_pass_tran_value;$/;" m struct:s_arch_mrfpga -rram_variation fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params rram_variation;$/;" m struct:s_spice_mc_params -s include/ezxml.h /^ char *s; \/* start of work area *\/$/;" m struct:ezxml_root -s_arch include/physical_types.h /^struct s_arch {$/;" s -s_arch_mrfpga include/arch_types_mrfpga.h /^struct s_arch_mrfpga {$/;" s -s_buffer_inf include/arch_types_mrfpga.h /^struct s_buffer_inf { $/;" s -s_chan include/physical_types.h /^typedef struct s_chan {$/;" s -s_chan_width_dist include/physical_types.h /^typedef struct s_chan_width_dist {$/;" s -s_chunk include/util.h /^typedef struct s_chunk {$/;" s -s_class include/physical_types.h /^struct s_class {$/;" s -s_clb_grid include/physical_types.h /^struct s_clb_grid {$/;" s -s_clock_arch include/physical_types.h /^struct s_clock_arch {$/;" s -s_clock_network include/physical_types.h /^struct s_clock_network {$/;" s -s_cluster_placement_primitive include/cad_types.h /^typedef struct s_cluster_placement_primitive {$/;" s -s_conf_bit fpga_spice_include/spice_types.h /^struct s_conf_bit {$/;" s -s_conf_bit_info fpga_spice_include/spice_types.h /^struct s_conf_bit_info {$/;" s -s_direct_inf include/physical_types.h /^typedef struct s_direct_inf {$/;" s -s_grid_loc_def include/physical_types.h /^typedef struct s_grid_loc_def {$/;" s -s_interconnect include/physical_types.h /^struct s_interconnect {$/;" s -s_interconnect_pins include/physical_types.h /^struct s_interconnect_pins {$/;" s -s_interconnect_power include/physical_types.h /^struct s_interconnect_power {$/;" s -s_ivec include/util.h /^typedef struct s_ivec {$/;" s -s_linked_int include/util.h /^typedef struct s_linked_int {$/;" s -s_linked_vptr include/util.h /^typedef struct s_linked_vptr {$/;" s -s_llist fpga_spice_include/linkedlist.h /^struct s_llist$/;" s -s_mem_bank_info fpga_spice_include/spice_types.h /^struct s_mem_bank_info {$/;" s -s_memristor_inf include/arch_types_mrfpga.h /^struct s_memristor_inf { $/;" s -s_mode include/physical_types.h /^struct s_mode {$/;" s -s_mode_power include/physical_types.h /^struct s_mode_power {$/;" s -s_model include/logic_types.h /^typedef struct s_model {$/;" s -s_model_chain_pattern include/cad_types.h /^typedef struct s_model_chain_pattern {$/;" s -s_model_ports include/logic_types.h /^typedef struct s_model_ports {$/;" s -s_pack_pattern_block include/cad_types.h /^typedef struct s_pack_pattern_block {$/;" s -s_pack_pattern_connections include/cad_types.h /^typedef struct s_pack_pattern_connections {$/;" s -s_pack_patterns include/cad_types.h /^typedef struct s_pack_patterns {$/;" s -s_pb_graph_edge include/physical_types.h /^struct s_pb_graph_edge {$/;" s -s_pb_graph_node include/physical_types.h /^struct s_pb_graph_node {$/;" s -s_pb_graph_node_power include/physical_types.h /^struct s_pb_graph_node_power {$/;" s -s_pb_graph_pin include/physical_types.h /^struct s_pb_graph_pin {$/;" s -s_pb_graph_pin_power include/physical_types.h /^struct s_pb_graph_pin_power {$/;" s -s_pb_type include/physical_types.h /^struct s_pb_type {$/;" s -s_pb_type_power include/physical_types.h /^struct s_pb_type_power {$/;" s -s_pin_to_pin_annotation include/physical_types.h /^struct s_pin_to_pin_annotation {$/;" s -s_port include/physical_types.h /^struct s_port {$/;" s -s_port_power include/physical_types.h /^struct s_port_power {$/;" s -s_power_arch include/physical_types.h /^struct s_power_arch {$/;" s -s_power_usage include/physical_types.h /^struct s_power_usage {$/;" s -s_reserved_syntax_char fpga_spice_include/spice_types.h /^struct s_reserved_syntax_char {$/;" s -s_scff_info fpga_spice_include/spice_types.h /^struct s_scff_info {$/;" s -s_segment_inf include/physical_types.h /^typedef struct s_segment_inf {$/;" s -s_spice fpga_spice_include/spice_types.h /^struct s_spice {$/;" s -s_spice_mc_params fpga_spice_include/spice_types.h /^struct s_spice_mc_params {$/;" s -s_spice_mc_variation_params fpga_spice_include/spice_types.h /^struct s_spice_mc_variation_params {$/;" s -s_spice_meas_params fpga_spice_include/spice_types.h /^struct s_spice_meas_params {$/;" s -s_spice_model fpga_spice_include/spice_types.h /^struct s_spice_model {$/;" s -s_spice_model_buffer fpga_spice_include/spice_types.h /^struct s_spice_model_buffer {$/;" s -s_spice_model_design_tech_info fpga_spice_include/spice_types.h /^struct s_spice_model_design_tech_info {$/;" s -s_spice_model_netlist fpga_spice_include/spice_types.h /^struct s_spice_model_netlist {$/;" s -s_spice_model_pass_gate_logic fpga_spice_include/spice_types.h /^struct s_spice_model_pass_gate_logic {$/;" s -s_spice_model_port fpga_spice_include/spice_types.h /^struct s_spice_model_port {$/;" s -s_spice_model_wire_param fpga_spice_include/spice_types.h /^struct s_spice_model_wire_param {$/;" s -s_spice_mux_arch fpga_spice_include/spice_types.h /^struct s_spice_mux_arch {$/;" s -s_spice_mux_model fpga_spice_include/spice_types.h /^struct s_spice_mux_model {$/;" s -s_spice_net_info fpga_spice_include/spice_types.h /^struct s_spice_net_info {$/;" s -s_spice_params fpga_spice_include/spice_types.h /^struct s_spice_params {$/;" s -s_spice_stimulate_params fpga_spice_include/spice_types.h /^struct s_spice_stimulate_params {$/;" s -s_spice_tech_lib fpga_spice_include/spice_types.h /^struct s_spice_tech_lib {$/;" s -s_spice_transistor_type fpga_spice_include/spice_types.h /^struct s_spice_transistor_type {$/;" s -s_spicetb_info fpga_spice_include/spice_types.h /^struct s_spicetb_info {$/;" s -s_sram_inf fpga_spice_include/spice_types.h /^struct s_sram_inf {$/;" s -s_sram_inf_orgz fpga_spice_include/spice_types.h /^struct s_sram_inf_orgz {$/;" s -s_sram_orgz_info fpga_spice_include/spice_types.h /^struct s_sram_orgz_info {$/;" s -s_standalone_sram_info fpga_spice_include/spice_types.h /^struct s_standalone_sram_info {$/;" s -s_switch_inf include/physical_types.h /^typedef struct s_switch_inf {$/;" s -s_swseg_pattern_inf include/physical_types.h /^struct s_swseg_pattern_inf {$/;" s -s_timing_inf include/physical_types.h /^typedef struct s_timing_inf {$/;" s -s_type_descriptor include/physical_types.h /^struct s_type_descriptor \/* TODO rename this. maybe physical type descriptor or complex logic block or physical logic block*\/$/;" s -sb include/physical_types.h /^ boolean *sb;$/;" m struct:s_segment_inf -sb_index_high fpga_spice_include/spice_types.h /^ int** sb_index_high;$/;" m struct:s_spice_model -sb_index_low fpga_spice_include/spice_types.h /^ int** sb_index_low;$/;" m struct:s_spice_model -sb_len include/physical_types.h /^ int sb_len;$/;" m struct:s_segment_inf -scaled_by_pin include/physical_types.h /^ t_pb_graph_pin * scaled_by_pin;$/;" m struct:s_pb_graph_pin_power -scaled_by_port include/physical_types.h /^ t_port * scaled_by_port;$/;" m struct:s_port_power -scaled_by_port_pin_idx include/physical_types.h /^ int scaled_by_port_pin_idx;$/;" m struct:s_port_power -scff_info fpga_spice_include/spice_types.h /^ t_scff_info* scff_info; \/* Only be allocated when orgz type is scan-chain *\/$/;" m struct:s_sram_orgz_info -scratch_pad include/physical_types.h /^ int scratch_pad; \/* temporary data structure useful to store traversal info *\/$/;" m struct:s_pb_graph_pin -search_in_int_list util.c /^t_linked_int* search_in_int_list(t_linked_int* int_list_head, $/;" f -search_llist_tail linkedlist.c /^t_llist* search_llist_tail(t_llist* head) {$/;" f -seg_direction_type include/physical_types.h /^ enum e_directionality seg_direction_type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_directionality -seg_length include/physical_types.h /^ int seg_length;$/;" m struct:s_swseg_pattern_inf -seg_switch include/physical_types.h /^ short seg_switch;$/;" m struct:s_segment_inf -sibling include/ezxml.h /^ ezxml_t sibling; \/* next tag with different name in same section and depth *\/$/;" m struct:ezxml -sim_clock_freq_slack fpga_spice_include/spice_types.h /^ float sim_clock_freq_slack;$/;" m struct:s_spice_stimulate_params -sim_num_clock_cycle fpga_spice_include/spice_types.h /^ int sim_num_clock_cycle; \/* Number of clock cycle in simulation *\/$/;" m struct:s_spice_meas_params -sim_temp fpga_spice_include/spice_types.h /^ int sim_temp; \/* Simulation Temperature*\/$/;" m struct:s_spice_params -size fpga_spice_include/spice_types.h /^ float size;$/;" m struct:s_spice_model_buffer -size fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_model_port -size fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_mux_model -size include/logic_types.h /^ int size; \/* maximum number of pins *\/$/;" m struct:s_model_ports -slew_fall fpga_spice_include/spice_types.h /^ float slew_fall;$/;" m struct:s_spice_net_info -slew_lower_thres_pct_fall fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_fall;$/;" m struct:s_spice_meas_params -slew_lower_thres_pct_rise fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_rise;$/;" m struct:s_spice_meas_params -slew_rise fpga_spice_include/spice_types.h /^ float slew_rise;$/;" m struct:s_spice_net_info -slew_upper_thres_pct_fall fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_fall;$/;" m struct:s_spice_meas_params -slew_upper_thres_pct_rise fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_rise;$/;" m struct:s_spice_meas_params -snprintf ezxml.c 57;" d file: -spice include/physical_types.h /^ t_spice* spice;$/;" m struct:s_arch -spice_model fpga_spice_include/spice_types.h /^ t_spice_model* spice_model; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz -spice_model fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_buffer -spice_model fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_pass_gate_logic -spice_model fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_port -spice_model fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_mux_model -spice_model include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_interconnect -spice_model include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_pb_type -spice_model include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_segment_inf -spice_model include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_switch_inf -spice_model_name fpga_spice_include/spice_types.h /^ char* spice_model_name; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz -spice_model_name fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_buffer -spice_model_name fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_pass_gate_logic -spice_model_name fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_port -spice_model_name include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_interconnect -spice_model_name include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_pb_type -spice_model_name include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_segment_inf -spice_model_name include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_switch_inf -spice_model_port include/physical_types.h /^ t_spice_model_port* spice_model_port;$/;" m struct:s_port -spice_models fpga_spice_include/spice_types.h /^ t_spice_model* spice_models;$/;" m struct:s_spice -spice_mux_arch fpga_spice_include/spice_types.h /^ t_spice_mux_arch* spice_mux_arch;$/;" m struct:s_spice_mux_model -spice_params fpga_spice_include/spice_types.h /^ t_spice_params spice_params;$/;" m struct:s_spice -spice_reserved fpga_spice_include/spice_types.h /^ boolean spice_reserved;$/;" m struct:s_reserved_syntax_char -spice_sram_inf_orgz fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* spice_sram_inf_orgz;$/;" m struct:s_sram_inf -spot_int_in_array util.c /^int spot_int_in_array(int array_len, int* array,$/;" f -sram_bit fpga_spice_include/spice_types.h /^ t_conf_bit* sram_bit;$/;" m struct:s_conf_bit_info -sram_inf include/physical_types.h /^ t_sram_inf sram_inf;$/;" m struct:s_arch -standalone include/ezxml.h /^ short standalone; \/* non-zero if *\/$/;" m struct:ezxml_root -standalone_sram_info fpga_spice_include/spice_types.h /^ t_standalone_sram_info* standalone_sram_info; \/* Only be allocated when orgz type is standalone *\/$/;" m struct:s_sram_orgz_info -start_col include/physical_types.h /^ int start_col;$/;" m struct:s_grid_loc_def -start_seg_switch include/arch_types_mrfpga.h /^ short start_seg_switch;$/;" m struct:s_arch_mrfpga -stimulate_params fpga_spice_include/spice_types.h /^ t_spice_stimulate_params stimulate_params;$/;" m struct:s_spice_params -structure fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_model_design_tech_info typeref:enum:s_spice_model_design_tech_info::e_spice_model_structure -structure fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_mux_arch typeref:enum:s_spice_mux_arch::e_spice_model_structure -structure include/physical_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_switch_inf typeref:enum:s_switch_inf::e_spice_model_structure -switch_num_level include/physical_types.h /^ int switch_num_level;$/;" m struct:s_switch_inf -swseg_patterns include/physical_types.h /^ t_swseg_pattern_inf* swseg_patterns;$/;" m struct:s_arch -syntax_char fpga_spice_include/spice_types.h /^ char syntax_char;$/;" m struct:s_reserved_syntax_char -t_arch include/physical_types.h /^typedef struct s_arch t_arch;$/;" t typeref:struct:s_arch -t_arch_mrfpga include/arch_types_mrfpga.h /^typedef struct s_arch_mrfpga t_arch_mrfpga;$/;" t typeref:struct:s_arch_mrfpga -t_buffer_inf include/arch_types_mrfpga.h /^typedef struct s_buffer_inf t_buffer_inf;$/;" t typeref:struct:s_buffer_inf -t_chan include/physical_types.h /^} t_chan;$/;" t typeref:struct:s_chan -t_chan_width_dist include/physical_types.h /^} t_chan_width_dist;$/;" t typeref:struct:s_chan_width_dist -t_chunk include/util.h /^} t_chunk;$/;" t typeref:struct:s_chunk -t_class include/physical_types.h /^typedef struct s_class t_class;$/;" t typeref:struct:s_class -t_clock_arch include/physical_types.h /^typedef struct s_clock_arch t_clock_arch;$/;" t typeref:struct:s_clock_arch -t_clock_network include/physical_types.h /^typedef struct s_clock_network t_clock_network;$/;" t typeref:struct:s_clock_network -t_cluster_placement_primitive include/cad_types.h /^} t_cluster_placement_primitive;$/;" t typeref:struct:s_cluster_placement_primitive -t_conf_bit fpga_spice_include/spice_types.h /^typedef struct s_conf_bit t_conf_bit;$/;" t typeref:struct:s_conf_bit -t_conf_bit_info fpga_spice_include/spice_types.h /^typedef struct s_conf_bit_info t_conf_bit_info;$/;" t typeref:struct:s_conf_bit_info -t_direct_inf include/physical_types.h /^} t_direct_inf;$/;" t typeref:struct:s_direct_inf -t_grid_loc_def include/physical_types.h /^} t_grid_loc_def;$/;" t typeref:struct:s_grid_loc_def -t_interconnect include/physical_types.h /^typedef struct s_interconnect t_interconnect;$/;" t typeref:struct:s_interconnect -t_interconnect_pins include/physical_types.h /^typedef struct s_interconnect_pins t_interconnect_pins;$/;" t typeref:struct:s_interconnect_pins -t_interconnect_power include/physical_types.h /^typedef struct s_interconnect_power t_interconnect_power;$/;" t typeref:struct:s_interconnect_power -t_ivec include/util.h /^} t_ivec;$/;" t typeref:struct:s_ivec -t_linked_int include/util.h /^} t_linked_int;$/;" t typeref:struct:s_linked_int -t_linked_vptr include/util.h /^} t_linked_vptr;$/;" t typeref:struct:s_linked_vptr -t_llist fpga_spice_include/linkedlist.h /^typedef struct s_llist t_llist;$/;" t typeref:struct:s_llist -t_mem_bank_info fpga_spice_include/spice_types.h /^typedef struct s_mem_bank_info t_mem_bank_info;$/;" t typeref:struct:s_mem_bank_info -t_memristor_inf include/arch_types_mrfpga.h /^typedef struct s_memristor_inf t_memristor_inf;$/;" t typeref:struct:s_memristor_inf -t_mode include/physical_types.h /^typedef struct s_mode t_mode;$/;" t typeref:struct:s_mode -t_mode_power include/physical_types.h /^typedef struct s_mode_power t_mode_power;$/;" t typeref:struct:s_mode_power -t_model include/logic_types.h /^} t_model;$/;" t typeref:struct:s_model -t_model_chain_pattern include/cad_types.h /^} t_model_chain_pattern;$/;" t typeref:struct:s_model_chain_pattern -t_model_ports include/logic_types.h /^} t_model_ports;$/;" t typeref:struct:s_model_ports -t_pack_pattern_block include/cad_types.h /^} t_pack_pattern_block;$/;" t typeref:struct:s_pack_pattern_block -t_pack_pattern_connections include/cad_types.h /^} t_pack_pattern_connections;$/;" t typeref:struct:s_pack_pattern_connections -t_pack_patterns include/cad_types.h /^} t_pack_patterns;$/;" t typeref:struct:s_pack_patterns -t_pb_graph_edge include/physical_types.h /^typedef struct s_pb_graph_edge t_pb_graph_edge;$/;" t typeref:struct:s_pb_graph_edge -t_pb_graph_node include/physical_types.h /^typedef struct s_pb_graph_node t_pb_graph_node;$/;" t typeref:struct:s_pb_graph_node -t_pb_graph_node_power include/physical_types.h /^typedef struct s_pb_graph_node_power t_pb_graph_node_power;$/;" t typeref:struct:s_pb_graph_node_power -t_pb_graph_pin include/physical_types.h /^typedef struct s_pb_graph_pin t_pb_graph_pin;$/;" t typeref:struct:s_pb_graph_pin -t_pb_graph_pin_power include/physical_types.h /^typedef struct s_pb_graph_pin_power t_pb_graph_pin_power;$/;" t typeref:struct:s_pb_graph_pin_power -t_pb_type include/physical_types.h /^typedef struct s_pb_type t_pb_type;$/;" t typeref:struct:s_pb_type -t_pb_type_power include/physical_types.h /^typedef struct s_pb_type_power t_pb_type_power;$/;" t typeref:struct:s_pb_type_power -t_pin_to_pin_annotation include/physical_types.h /^typedef struct s_pin_to_pin_annotation t_pin_to_pin_annotation;$/;" t typeref:struct:s_pin_to_pin_annotation -t_port include/physical_types.h /^typedef struct s_port t_port;$/;" t typeref:struct:s_port -t_port_power include/physical_types.h /^typedef struct s_port_power t_port_power;$/;" t typeref:struct:s_port_power -t_power_arch include/physical_types.h /^typedef struct s_power_arch t_power_arch;$/;" t typeref:struct:s_power_arch -t_power_estimation_method include/physical_types.h /^typedef enum e_power_estimation_method_ t_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ -t_power_usage include/physical_types.h /^typedef struct s_power_usage t_power_usage;$/;" t typeref:struct:s_power_usage -t_reserved_syntax_char fpga_spice_include/spice_types.h /^typedef struct s_reserved_syntax_char t_reserved_syntax_char;$/;" t typeref:struct:s_reserved_syntax_char -t_scff_info fpga_spice_include/spice_types.h /^typedef struct s_scff_info t_scff_info;$/;" t typeref:struct:s_scff_info -t_segment_inf include/physical_types.h /^} t_segment_inf;$/;" t typeref:struct:s_segment_inf -t_spice fpga_spice_include/spice_types.h /^typedef struct s_spice t_spice;$/;" t typeref:struct:s_spice -t_spice_mc_params fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_params t_spice_mc_params;$/;" t typeref:struct:s_spice_mc_params -t_spice_mc_variation_params fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_variation_params t_spice_mc_variation_params;$/;" t typeref:struct:s_spice_mc_variation_params -t_spice_meas_params fpga_spice_include/spice_types.h /^typedef struct s_spice_meas_params t_spice_meas_params;$/;" t typeref:struct:s_spice_meas_params -t_spice_model fpga_spice_include/spice_types.h /^typedef struct s_spice_model t_spice_model;$/;" t typeref:struct:s_spice_model -t_spice_model_buffer fpga_spice_include/spice_types.h /^typedef struct s_spice_model_buffer t_spice_model_buffer;$/;" t typeref:struct:s_spice_model_buffer -t_spice_model_design_tech_info fpga_spice_include/spice_types.h /^typedef struct s_spice_model_design_tech_info t_spice_model_design_tech_info;$/;" t typeref:struct:s_spice_model_design_tech_info -t_spice_model_netlist fpga_spice_include/spice_types.h /^typedef struct s_spice_model_netlist t_spice_model_netlist;$/;" t typeref:struct:s_spice_model_netlist -t_spice_model_pass_gate_logic fpga_spice_include/spice_types.h /^typedef struct s_spice_model_pass_gate_logic t_spice_model_pass_gate_logic;$/;" t typeref:struct:s_spice_model_pass_gate_logic -t_spice_model_port fpga_spice_include/spice_types.h /^typedef struct s_spice_model_port t_spice_model_port;$/;" t typeref:struct:s_spice_model_port -t_spice_model_wire_param fpga_spice_include/spice_types.h /^typedef struct s_spice_model_wire_param t_spice_model_wire_param;$/;" t typeref:struct:s_spice_model_wire_param -t_spice_mux_arch fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_arch t_spice_mux_arch;$/;" t typeref:struct:s_spice_mux_arch -t_spice_mux_model fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_model t_spice_mux_model;$/;" t typeref:struct:s_spice_mux_model -t_spice_net_info fpga_spice_include/spice_types.h /^typedef struct s_spice_net_info t_spice_net_info;$/;" t typeref:struct:s_spice_net_info -t_spice_params fpga_spice_include/spice_types.h /^typedef struct s_spice_params t_spice_params;$/;" t typeref:struct:s_spice_params -t_spice_stimulate_params fpga_spice_include/spice_types.h /^typedef struct s_spice_stimulate_params t_spice_stimulate_params;$/;" t typeref:struct:s_spice_stimulate_params -t_spice_tech_lib fpga_spice_include/spice_types.h /^typedef struct s_spice_tech_lib t_spice_tech_lib;$/;" t typeref:struct:s_spice_tech_lib -t_spice_transistor_type fpga_spice_include/spice_types.h /^typedef struct s_spice_transistor_type t_spice_transistor_type;$/;" t typeref:struct:s_spice_transistor_type -t_spicetb_info fpga_spice_include/spice_types.h /^typedef struct s_spicetb_info t_spicetb_info;$/;" t typeref:struct:s_spicetb_info -t_sram_inf fpga_spice_include/spice_types.h /^typedef struct s_sram_inf t_sram_inf;$/;" t typeref:struct:s_sram_inf -t_sram_inf_orgz fpga_spice_include/spice_types.h /^typedef struct s_sram_inf_orgz t_sram_inf_orgz;$/;" t typeref:struct:s_sram_inf_orgz -t_sram_orgz_info fpga_spice_include/spice_types.h /^typedef struct s_sram_orgz_info t_sram_orgz_info;$/;" t typeref:struct:s_sram_orgz_info -t_standalone_sram_info fpga_spice_include/spice_types.h /^typedef struct s_standalone_sram_info t_standalone_sram_info;$/;" t typeref:struct:s_standalone_sram_info -t_switch_block_type include/physical_types.h /^typedef enum e_switch_block_type t_switch_block_type;$/;" t typeref:enum:e_switch_block_type -t_switch_inf include/physical_types.h /^} t_switch_inf;$/;" t typeref:struct:s_switch_inf -t_swseg_pattern_inf include/physical_types.h /^typedef struct s_swseg_pattern_inf t_swseg_pattern_inf;$/;" t typeref:struct:s_swseg_pattern_inf -t_timing_inf include/physical_types.h /^} t_timing_inf;$/;" t typeref:struct:s_timing_inf -t_type_descriptor include/physical_types.h /^typedef struct s_type_descriptor t_type_descriptor;$/;" t typeref:struct:s_type_descriptor -t_type_ptr include/physical_types.h /^typedef const struct s_type_descriptor *t_type_ptr;$/;" t typeref:struct:s_type_descriptor -tap_buf_level fpga_spice_include/spice_types.h /^ int tap_buf_level;$/;" m struct:s_spice_model_buffer -tapered_buf fpga_spice_include/spice_types.h /^ int tapered_buf; \/*Valid only when this is a buffer*\/$/;" m struct:s_spice_model_buffer -tb_cnt fpga_spice_include/spice_types.h /^ int tb_cnt;$/;" m struct:s_spice_model -tb_name fpga_spice_include/spice_types.h /^ char* tb_name;$/;" m struct:s_spicetb_info -tech_comp include/arch_types_mrfpga.h /^ enum e_tech_comp tech_comp;$/;" m struct:s_arch_mrfpga typeref:enum:s_arch_mrfpga::e_tech_comp -tech_lib fpga_spice_include/spice_types.h /^ t_spice_tech_lib tech_lib;$/;" m struct:s_spice -temp_net_num include/physical_types.h /^ int temp_net_num;$/;" m struct:s_pb_graph_pin -temp_scratch_pad include/physical_types.h /^ void *temp_scratch_pad; \/* temporary data, useful for keeping track of things when traversing data structure *\/$/;" m struct:s_pb_graph_node -timing_analysis_enabled include/physical_types.h /^ boolean timing_analysis_enabled;$/;" m struct:s_timing_inf -to_block include/cad_types.h /^ t_pack_pattern_block *to_block;$/;" m struct:s_pack_pattern_connections -to_pin include/cad_types.h /^ t_pb_graph_pin *to_pin;$/;" m struct:s_pack_pattern_connections -to_pin include/physical_types.h /^ char *to_pin;$/;" m struct:s_direct_inf -total_pb_pins include/physical_types.h /^ int total_pb_pins; \/* only valid for top-level *\/$/;" m struct:s_pb_graph_node -transistor_cnt include/physical_types.h /^ float transistor_cnt;$/;" m struct:s_interconnect_power -transistor_cnt_buffers include/physical_types.h /^ float transistor_cnt_buffers;$/;" m struct:s_pb_graph_node_power -transistor_cnt_interc include/physical_types.h /^ float transistor_cnt_interc; \/* Total transistor size of the interconnect in this pb *\/$/;" m struct:s_pb_graph_node_power -transistor_cnt_pb_children include/physical_types.h /^ float transistor_cnt_pb_children; \/* Total transistor size of this pb *\/$/;" m struct:s_pb_graph_node_power -transistor_type fpga_spice_include/spice_types.h /^ char* transistor_type;$/;" m struct:s_spice_tech_lib -transistor_types fpga_spice_include/spice_types.h /^ t_spice_transistor_type* transistor_types;$/;" m struct:s_spice_tech_lib -transistors_per_SRAM_bit include/physical_types.h /^ float transistors_per_SRAM_bit;$/;" m struct:s_power_arch -tsu_tco include/physical_types.h /^ float tsu_tco; \/* For sequential logic elements, this is the setup time (if input) or clock-to-q time (if output) *\/$/;" m struct:s_pb_graph_pin -txt include/ezxml.h /^ char *txt; \/* tag character content, empty string if none *\/$/;" m struct:ezxml -type fpga_spice_include/spice_types.h /^ enum e_spice_model_buffer_type type;$/;" m struct:s_spice_model_buffer typeref:enum:s_spice_model_buffer::e_spice_model_buffer_type -type fpga_spice_include/spice_types.h /^ enum e_spice_model_pass_gate_logic_type type;$/;" m struct:s_spice_model_pass_gate_logic typeref:enum:s_spice_model_pass_gate_logic::e_spice_model_pass_gate_logic_type -type fpga_spice_include/spice_types.h /^ enum e_spice_model_port_type type;$/;" m struct:s_spice_model_port typeref:enum:s_spice_model_port::e_spice_model_port_type -type fpga_spice_include/spice_types.h /^ enum e_spice_model_type type;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_type -type fpga_spice_include/spice_types.h /^ enum e_spice_tech_lib_type type;$/;" m struct:s_spice_tech_lib typeref:enum:s_spice_tech_lib::e_spice_tech_lib_type -type fpga_spice_include/spice_types.h /^ enum e_spice_trans_type type;$/;" m struct:s_spice_transistor_type typeref:enum:s_spice_transistor_type::e_spice_trans_type -type fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_inf_orgz typeref:enum:s_sram_inf_orgz::e_sram_orgz -type fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_orgz_info typeref:enum:s_sram_orgz_info::e_sram_orgz -type fpga_spice_include/spice_types.h /^ enum e_wire_model_type type;$/;" m struct:s_spice_model_wire_param typeref:enum:s_spice_model_wire_param::e_wire_model_type -type include/physical_types.h /^ enum PORTS type;$/;" m struct:s_port typeref:enum:s_port::PORTS -type include/physical_types.h /^ enum e_interconnect type;$/;" m struct:s_interconnect typeref:enum:s_interconnect::e_interconnect -type include/physical_types.h /^ enum e_pb_graph_pin_type type; \/* Is a sequential logic element (TRUE), inpad\/outpad (TRUE), or neither (FALSE) *\/$/;" m struct:s_pb_graph_pin typeref:enum:s_pb_graph_pin::e_pb_graph_pin_type -type include/physical_types.h /^ enum e_pin_to_pin_annotation_type type;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_type -type include/physical_types.h /^ enum e_pin_type type;$/;" m struct:s_class typeref:enum:s_class::e_pin_type -type include/physical_types.h /^ enum e_stat type;$/;" m struct:s_chan typeref:enum:s_chan::e_stat -type include/physical_types.h /^ char* type;$/;" m struct:s_switch_inf -type include/physical_types.h /^ enum e_swseg_pattern_type type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_swseg_pattern_type -u include/ezxml.h /^ char *u; \/* UTF-8 conversion of string if original was UTF-16 *\/$/;" m struct:ezxml_root -unbuf_switch include/physical_types.h /^ short unbuf_switch;$/;" m struct:s_swseg_pattern_inf -used include/logic_types.h /^ int used;$/;" m struct:s_model -val fpga_spice_include/spice_types.h /^ int val; \/* binary value to be writtent: either 0 or 1 *\/$/;" m struct:s_conf_bit -valid include/cad_types.h /^ boolean valid;$/;" m struct:s_cluster_placement_primitive -value include/physical_types.h /^ char ** value; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation -variation_on fpga_spice_include/spice_types.h /^ boolean variation_on;$/;" m struct:s_spice_mc_variation_params -verilog_netlist fpga_spice_include/spice_types.h /^ char* verilog_netlist; \/* Verilog netlist provided by user *\/$/;" m struct:s_spice_model -verilog_reserved fpga_spice_include/spice_types.h /^ boolean verilog_reserved;$/;" m struct:s_reserved_syntax_char -verilog_sram_inf_orgz fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* verilog_sram_inf_orgz;$/;" m struct:s_sram_inf -vpr_crit_path_delay fpga_spice_include/spice_types.h /^ float vpr_crit_path_delay; \/* Reference operation clock frequency *\/$/;" m struct:s_spice_stimulate_params -vpr_printf util.c /^messagelogger vpr_printf = PrintHandlerMessage;$/;" v -width include/physical_types.h /^ float width;$/;" m struct:s_chan -wire include/physical_types.h /^ } wire;$/;" m struct:s_port_power typeref:union:s_port_power::__anon3 -wire_buffer_inf include/arch_types_mrfpga.h /^ t_buffer_inf wire_buffer_inf;$/;" m struct:s_arch_mrfpga -wire_param fpga_spice_include/spice_types.h /^ t_spice_model_wire_param* wire_param;$/;" m struct:s_spice_model -wire_switch include/physical_types.h /^ short wire_switch;$/;" m struct:s_segment_inf -wire_type include/physical_types.h /^ e_power_wire_type wire_type;$/;" m struct:s_port_power -wl fpga_spice_include/spice_types.h /^ t_conf_bit* wl;$/;" m struct:s_conf_bit_info -wprog_reset_nmos fpga_spice_include/spice_types.h /^ float wprog_reset_nmos;$/;" m struct:s_spice_model_design_tech_info -wprog_reset_pmos fpga_spice_include/spice_types.h /^ float wprog_reset_pmos;$/;" m struct:s_spice_model_design_tech_info -wprog_set_nmos fpga_spice_include/spice_types.h /^ float wprog_set_nmos;$/;" m struct:s_spice_model_design_tech_info -wprog_set_pmos fpga_spice_include/spice_types.h /^ float wprog_set_pmos;$/;" m struct:s_spice_model_design_tech_info -write ezxml.c 60;" d file: -x_offset include/physical_types.h /^ int x_offset;$/;" m struct:s_direct_inf -xml include/ezxml.h /^ struct ezxml xml; \/* is a super-struct built on top of ezxml struct *\/$/;" m struct:ezxml_root typeref:struct:ezxml_root::ezxml -xpeak include/physical_types.h /^ float xpeak;$/;" m struct:s_chan -y_offset include/physical_types.h /^ int y_offset;$/;" m struct:s_direct_inf -z_offset include/physical_types.h /^ int z_offset;$/;" m struct:s_direct_inf +ABSOLUTE SRC/include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type +ARCH_TYPES_H SRC/include/arch_types.h 9;" d +Aspect SRC/include/physical_types.h /^ float Aspect;$/;" m struct:s_clb_grid +BEST_CORNER SRC/fpga_spice_include/spice_types.h /^ BEST_CORNER,$/;" e enum:e_process_corner +BI_DIRECTIONAL SRC/include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality +BOTTOM SRC/include/sides.h /^ BOTTOM = 2, $/;" e enum:e_side +BOUNDARY SRC/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +BUFSIZE SRC/include/util.h 23;" d +C SRC/include/arch_types_mrfpga.h /^ float C; $/;" m struct:s_memristor_inf +C SRC/include/arch_types_mrfpga.h /^ float C;$/;" m struct:s_buffer_inf +C SRC/include/physical_types.h /^ float C;$/;" m union:s_port_power::__anon3 +CAD_TYPES_H SRC/include/cad_types.h 5;" d +CHECK_RAND SRC/util.c 734;" d file: +CHUNK_SIZE SRC/util.c 208;" d file: +COL_REL SRC/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +COL_REPEAT SRC/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +COMPLETE_INTERC SRC/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect +CONV SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +C_internal SRC/include/physical_types.h /^ float C_internal; \/*Internal capacitance of the pb *\/$/;" m struct:s_pb_type_power +C_ipin_cblock SRC/include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_arch +C_ipin_cblock SRC/include/physical_types.h /^ float C_ipin_cblock;$/;" m struct:s_timing_inf +C_wire SRC/include/physical_types.h /^ float C_wire; \/* Wire capacitance (per meter) *\/$/;" m struct:s_clock_network +C_wire SRC/include/physical_types.h /^ float C_wire;$/;" m struct:s_pb_graph_pin_power +C_wire_local SRC/include/physical_types.h /^ float C_wire_local; \/* Capacitance of local interconnect (per meter) *\/$/;" m struct:s_power_arch +Chans SRC/include/physical_types.h /^ t_chan_width_dist Chans;$/;" m struct:s_arch +CheckElement SRC/read_xml_util.c /^void CheckElement(INP ezxml_t Node, INP const char *Name) {$/;" f +Cin SRC/include/physical_types.h /^ float Cin;$/;" m struct:s_switch_inf +Cmetal SRC/include/physical_types.h /^ float Cmetal;$/;" m struct:s_segment_inf +CountChildren SRC/read_xml_util.c /^extern int CountChildren(INP ezxml_t Node, INP const char *Name,$/;" f +CountTokens SRC/ReadLine.c /^int CountTokens(INP char **Tokens) {$/;" f +CountTokensInString SRC/read_xml_util.c /^extern void CountTokensInString(INP const char *Str, OUTP int *Num,$/;" f +Cout SRC/include/physical_types.h /^ float Cout;$/;" m struct:s_switch_inf +CreateModelLibrary SRC/read_xml_arch_file.c /^static void CreateModelLibrary(OUTP struct s_arch *arch) {$/;" f file: +Cseg_global SRC/include/arch_types_mrfpga.h /^ float Cseg_global;$/;" m struct:s_arch_mrfpga +DELTA SRC/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +DIRECT_INTERC SRC/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect +DRIVER SRC/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type +Directs SRC/include/physical_types.h /^ t_direct_inf *Directs;$/;" m struct:s_arch +EMPTY_TYPE SRC/read_xml_arch_file.c /^static t_type_ptr EMPTY_TYPE = NULL;$/;" v file: +EMPTY_TYPE_INDEX SRC/include/read_xml_arch_file.h 15;" d +ERRTAG SRC/include/util.h 26;" d +ERR_PORT SRC/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +EZXML_BUFSIZE SRC/include/ezxml.h 37;" d +EZXML_DUP SRC/include/ezxml.h 40;" d +EZXML_ERRL SRC/include/ezxml.h 41;" d +EZXML_NAMEM SRC/include/ezxml.h 38;" d +EZXML_NIL SRC/ezxml.c /^char *EZXML_NIL[] = { NULL }; \/* empty, null terminated array of strings *\/$/;" v +EZXML_NOMMAP SRC/ezxml.c 26;" d file: +EZXML_TXTM SRC/include/ezxml.h 39;" d +EZXML_WS SRC/ezxml.c 64;" d file: +E_ANNOT_PIN_TO_PIN_CAPACITANCE SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE,$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_CAPACITANCE_C SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_CAPACITANCE_C = 0$/;" e enum:e_pin_to_pin_capacitance_annotations +E_ANNOT_PIN_TO_PIN_CONSTANT SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format +E_ANNOT_PIN_TO_PIN_DELAY SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY = 0,$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_MAX SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MAX,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_MIN SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_MIN = 0,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_THOLD SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_THOLD$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_DELAY_TSETUP SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_DELAY_TSETUP,$/;" e enum:e_pin_to_pin_delay_annotations +E_ANNOT_PIN_TO_PIN_MATRIX SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MATRIX = 0, E_ANNOT_PIN_TO_PIN_CONSTANT$/;" e enum:e_pin_to_pin_annotation_format +E_ANNOT_PIN_TO_PIN_MODE_SELECT SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_MODE_SELECT_MODE_NAME = 0$/;" e enum:e_pin_to_pin_mode_select_annotations +E_ANNOT_PIN_TO_PIN_PACK_PATTERN SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN,$/;" e enum:e_pin_to_pin_annotation_type +E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME SRC/include/physical_types.h /^ E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME = 0$/;" e enum:e_pin_to_pin_pack_pattern_annotations +E_CUSTOM_PIN_DISTR SRC/include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr +E_SPREAD_PIN_DISTR SRC/include/physical_types.h /^ E_SPREAD_PIN_DISTR = 1, E_CUSTOM_PIN_DISTR = 2$/;" e enum:e_pin_location_distr +EchoArch SRC/read_xml_arch_file.c /^void EchoArch(INP const char *EchoFile, INP const t_type_descriptor * Types,$/;" f +FALSE SRC/include/util.h /^ FALSE, TRUE$/;" e enum:__anon4 +FC_ABS SRC/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: +FC_FRAC SRC/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: +FC_FULL SRC/read_xml_arch_file.c /^ FC_ABS, FC_FRAC, FC_FULL$/;" e enum:Fc_type file: +FF_FE SRC/fpga_spice_include/spice_types.h /^ FF_RE, FF_FE$/;" e enum:e_spice_ff_trigger_type +FF_RE SRC/fpga_spice_include/spice_types.h /^ FF_RE, FF_FE$/;" e enum:e_spice_ff_trigger_type +FF_size SRC/include/physical_types.h /^ float FF_size;$/;" m struct:s_power_arch +FILL SRC/include/physical_types.h /^ BOUNDARY = 0, FILL, COL_REPEAT, COL_REL$/;" e enum:e_grid_loc_type +FILL_TYPE SRC/read_xml_arch_file.c /^static t_type_ptr FILL_TYPE = NULL;$/;" v file: +FRACTIONAL SRC/include/physical_types.h /^ ABSOLUTE, FRACTIONAL$/;" e enum:e_Fc_type +FRAGMENT_THRESHOLD SRC/util.c 209;" d file: +FULL SRC/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +Fc SRC/include/physical_types.h /^ float *Fc; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +Fc_type SRC/read_xml_arch_file.c /^enum Fc_type {$/;" g file: +FindElement SRC/read_xml_util.c /^ezxml_t FindElement(INP ezxml_t Parent, INP const char *Name,$/;" f +FindFirstElement SRC/read_xml_util.c /^ezxml_t FindFirstElement(INP ezxml_t Parent, INP const char *Name,$/;" f +FindProperty SRC/read_xml_util.c /^FindProperty(INP ezxml_t Parent, INP const char *Name, INP boolean Required) {$/;" f +FreeNode SRC/read_xml_util.c /^void FreeNode(INOUTP ezxml_t Node) {$/;" f +FreeSpice SRC/read_xml_spice_util.c /^void FreeSpice(t_spice* spice) {$/;" f +FreeSpiceMeasParams SRC/read_xml_spice_util.c /^void FreeSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f +FreeSpiceModel SRC/read_xml_spice_util.c /^void FreeSpiceModel(t_spice_model* spice_model) {$/;" f +FreeSpiceModelBuffer SRC/read_xml_spice_util.c /^void FreeSpiceModelBuffer(t_spice_model_buffer* spice_model_buffer) {$/;" f +FreeSpiceModelNetlist SRC/read_xml_spice_util.c /^void FreeSpiceModelNetlist(t_spice_model_netlist* spice_model_netlist) {$/;" f +FreeSpiceModelPassGateLogic SRC/read_xml_spice_util.c /^void FreeSpiceModelPassGateLogic(t_spice_model_pass_gate_logic* spice_model_pass_gate_logic) {$/;" f +FreeSpiceModelPort SRC/read_xml_spice_util.c /^void FreeSpiceModelPort(t_spice_model_port* spice_model_port) {$/;" f +FreeSpiceModelWireParam SRC/read_xml_spice_util.c /^void FreeSpiceModelWireParam(t_spice_model_wire_param* spice_model_wire_param) {$/;" f +FreeSpiceMonteCarloParams SRC/read_xml_spice_util.c /^void FreeSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f +FreeSpiceMuxArch SRC/read_xml_spice_util.c /^void FreeSpiceMuxArch(t_spice_mux_arch* spice_mux_arch) {$/;" f +FreeSpiceParams SRC/read_xml_spice_util.c /^void FreeSpiceParams(t_spice_params* params) {$/;" f +FreeSpiceStimulateParams SRC/read_xml_spice_util.c /^void FreeSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f +FreeSpiceVariationParams SRC/read_xml_spice_util.c /^void FreeSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f +FreeSramInf SRC/read_xml_spice_util.c /^void FreeSramInf(t_sram_inf* sram_inf) {$/;" f +FreeSramInfOrgz SRC/read_xml_spice_util.c /^void FreeSramInfOrgz(t_sram_inf_orgz* sram_inf_orgz) {$/;" f +FreeTokens SRC/ReadLine.c /^void FreeTokens(INOUTP char ***TokensPtr) {$/;" f +Fs SRC/include/physical_types.h /^ int Fs;$/;" m struct:s_arch +GAUSSIAN SRC/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +GetBooleanProperty SRC/read_xml_util.c /^extern boolean GetBooleanProperty(INP ezxml_t Parent, INP char *Name,$/;" f +GetFloatProperty SRC/read_xml_util.c /^extern float GetFloatProperty(INP ezxml_t Parent, INP char *Name,$/;" f +GetIntProperty SRC/read_xml_util.c /^extern int GetIntProperty(INP ezxml_t Parent, INP char *Name,$/;" f +GetNodeTokens SRC/read_xml_util.c /^GetNodeTokens(INP ezxml_t Node) {$/;" f +H SRC/include/physical_types.h /^ int H;$/;" m struct:s_clb_grid +IA SRC/util.c 731;" d file: +IC SRC/util.c 732;" d file: +IM SRC/util.c 733;" d file: +INOUTP SRC/include/util.h 21;" d +INOUT_PORT SRC/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +INP SRC/include/util.h 19;" d +INPUT2INPUT_INTERC SRC/fpga_spice_include/spice_types.h /^ INPUT2INPUT_INTERC, $/;" e enum:e_spice_pin2pin_interc_type +IN_PORT SRC/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +IO_TYPE SRC/read_xml_arch_file.c /^static t_type_ptr IO_TYPE = NULL;$/;" v file: +IO_TYPE_INDEX SRC/include/read_xml_arch_file.h 16;" d +InitSpice SRC/read_xml_spice_util.c /^void InitSpice(t_spice* spice) {$/;" f +InitSpiceMeasParams SRC/read_xml_spice_util.c /^void InitSpiceMeasParams(t_spice_meas_params* meas_params) {$/;" f +InitSpiceMonteCarloParams SRC/read_xml_spice_util.c /^void InitSpiceMonteCarloParams(t_spice_mc_params* mc_params) {$/;" f +InitSpiceParams SRC/read_xml_spice_util.c /^void InitSpiceParams(t_spice_params* params) {$/;" f +InitSpiceStimulateParams SRC/read_xml_spice_util.c /^void InitSpiceStimulateParams(t_spice_stimulate_params* stimulate_params) {$/;" f +InitSpiceVariationParams SRC/read_xml_spice_util.c /^void InitSpiceVariationParams(t_spice_mc_variation_params* mc_variation_params) {$/;" f +IsAuto SRC/include/physical_types.h /^ boolean IsAuto;$/;" m struct:s_clb_grid +IsWhitespace SRC/read_xml_util.c /^boolean IsWhitespace(char c) {$/;" f +LATCH_CLASS SRC/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +LEFT SRC/include/sides.h /^ LEFT = 3,$/;" e enum:e_side +LINKEDLIST_H SRC/fpga_spice_include/linkedlist.h 2;" d +LOGIC_TYPES_H SRC/include/logic_types.h 10;" d +LUT_CLASS SRC/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +LUT_transistor_size SRC/include/physical_types.h /^ float LUT_transistor_size;$/;" m struct:s_power_arch +LookaheadNodeTokens SRC/read_xml_util.c /^LookaheadNodeTokens(INP ezxml_t Node) {$/;" f +MAX_CHANNEL_WIDTH SRC/include/arch_types.h 25;" d +MEMORY_CLASS SRC/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +MONO SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +MUX_INTERC SRC/include/physical_types.h /^ COMPLETE_INTERC = 1, DIRECT_INTERC = 2, MUX_INTERC = 3$/;" e enum:e_interconnect +MY_FREE_FWD_H SRC/fpga_spice_include/my_free_fwd.h 2;" d +NEM SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +NUM_MODELS_IN_LIBRARY SRC/include/read_xml_arch_file.h 14;" d +NUM_SIDES SRC/include/sides.h /^ NUM_SIDES$/;" e enum:e_side +OPEN SRC/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type +OUTP SRC/include/util.h 20;" d +OUTPUT2OUTPUT_INTERC SRC/fpga_spice_include/spice_types.h /^ OUTPUT2OUTPUT_INTERC$/;" e enum:e_spice_pin2pin_interc_type +OUT_PORT SRC/include/logic_types.h /^ IN_PORT, OUT_PORT, INOUT_PORT, ERR_PORT$/;" e enum:PORTS +PB_PIN_CLOCK SRC/include/physical_types.h /^ PB_PIN_CLOCK$/;" e enum:e_pb_graph_pin_type +PB_PIN_INPAD SRC/include/physical_types.h /^ PB_PIN_INPAD,$/;" e enum:e_pb_graph_pin_type +PB_PIN_INPUT SRC/include/physical_types.h /^ PB_PIN_INPUT,$/;" e enum:e_pb_graph_pin_type +PB_PIN_NORMAL SRC/include/physical_types.h /^ PB_PIN_NORMAL = 0,$/;" e enum:e_pb_graph_pin_type +PB_PIN_OUTPAD SRC/include/physical_types.h /^ PB_PIN_OUTPAD,$/;" e enum:e_pb_graph_pin_type +PB_PIN_OUTPUT SRC/include/physical_types.h /^ PB_PIN_OUTPUT,$/;" e enum:e_pb_graph_pin_type +PB_PIN_SEQUENTIAL SRC/include/physical_types.h /^ PB_PIN_SEQUENTIAL,$/;" e enum:e_pb_graph_pin_type +PB_PIN_TERMINAL SRC/include/physical_types.h /^ PB_PIN_TERMINAL,$/;" e enum:e_pb_graph_pin_type +PCRAM_Pierre SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +PCRAM_Xie SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +PHYSICAL_TYPES_H SRC/include/physical_types.h 27;" d +PORTS SRC/include/logic_types.h /^enum PORTS {$/;" g +POWER_BUFFER_TYPE_ABSOLUTE_SIZE SRC/include/physical_types.h /^ POWER_BUFFER_TYPE_ABSOLUTE_SIZE$/;" e enum:__anon2 +POWER_BUFFER_TYPE_AUTO SRC/include/physical_types.h /^ POWER_BUFFER_TYPE_AUTO,$/;" e enum:__anon2 +POWER_BUFFER_TYPE_NONE SRC/include/physical_types.h /^ POWER_BUFFER_TYPE_NONE,$/;" e enum:__anon2 +POWER_BUFFER_TYPE_UNDEFINED SRC/include/physical_types.h /^ POWER_BUFFER_TYPE_UNDEFINED = 0,$/;" e enum:__anon2 +POWER_METHOD_ABSOLUTE SRC/include/physical_types.h /^ POWER_METHOD_ABSOLUTE \/* Dynamic: Aboslute, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_AUTO_SIZES SRC/include/physical_types.h /^ POWER_METHOD_AUTO_SIZES, \/* Transistor-level, auto-sized buffers\/wires *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_C_INTERNAL SRC/include/physical_types.h /^ POWER_METHOD_C_INTERNAL, \/* Dynamic: Equiv. Internal capacitance, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_IGNORE SRC/include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_SPECIFY_SIZES SRC/include/physical_types.h /^ POWER_METHOD_SPECIFY_SIZES, \/* Transistor-level, user-specified buffers\/wires *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_SUM_OF_CHILDREN SRC/include/physical_types.h /^ POWER_METHOD_SUM_OF_CHILDREN, \/* Ignore power of this PB, but consider children *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_TOGGLE_PINS SRC/include/physical_types.h /^ POWER_METHOD_TOGGLE_PINS, \/* Dynamic: Energy per pin toggle, Static: Absolute *\/$/;" e enum:e_power_estimation_method_ +POWER_METHOD_UNDEFINED SRC/include/physical_types.h /^ POWER_METHOD_UNDEFINED = 0, POWER_METHOD_IGNORE, \/* Ignore power of this PB, and all children PB *\/$/;" e enum:e_power_estimation_method_ +POWER_WIRE_TYPE_ABSOLUTE_LENGTH SRC/include/physical_types.h /^ POWER_WIRE_TYPE_ABSOLUTE_LENGTH,$/;" e enum:__anon1 +POWER_WIRE_TYPE_AUTO SRC/include/physical_types.h /^ POWER_WIRE_TYPE_AUTO$/;" e enum:__anon1 +POWER_WIRE_TYPE_C SRC/include/physical_types.h /^ POWER_WIRE_TYPE_C,$/;" e enum:__anon1 +POWER_WIRE_TYPE_IGNORED SRC/include/physical_types.h /^ POWER_WIRE_TYPE_IGNORED,$/;" e enum:__anon1 +POWER_WIRE_TYPE_RELATIVE_LENGTH SRC/include/physical_types.h /^ POWER_WIRE_TYPE_RELATIVE_LENGTH,$/;" e enum:__anon1 +POWER_WIRE_TYPE_UNDEFINED SRC/include/physical_types.h /^ POWER_WIRE_TYPE_UNDEFINED = 0,$/;" e enum:__anon1 +PULSE SRC/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +PrintPb_types_rec SRC/read_xml_arch_file.c /^static void PrintPb_types_rec(INP FILE * Echo, INP const t_pb_type * pb_type,$/;" f file: +ProcessCB_SB SRC/read_xml_arch_file.c /^static void ProcessCB_SB(INOUTP ezxml_t Node, INOUTP boolean * list,$/;" f file: +ProcessChanWidthDistr SRC/read_xml_arch_file.c /^static void ProcessChanWidthDistr(INOUTP ezxml_t Node,$/;" f file: +ProcessChanWidthDistrDir SRC/read_xml_arch_file.c /^static void ProcessChanWidthDistrDir(INOUTP ezxml_t Node, OUTP t_chan * chan) {$/;" f file: +ProcessClocks SRC/read_xml_arch_file.c /^static void ProcessClocks(ezxml_t Parent, t_clock_arch * clocks) {$/;" f file: +ProcessComplexBlockProps SRC/read_xml_arch_file.c /^static void ProcessComplexBlockProps(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: +ProcessComplexBlocks SRC/read_xml_arch_file.c /^static void ProcessComplexBlocks(INOUTP ezxml_t Node,$/;" f file: +ProcessDevice SRC/read_xml_arch_file.c /^static void ProcessDevice(INOUTP ezxml_t Node, OUTP struct s_arch *arch,$/;" f file: +ProcessDirects SRC/read_xml_arch_file.c /^static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs,$/;" f file: +ProcessInterconnect SRC/read_xml_arch_file.c /^static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) {$/;" f file: +ProcessLayout SRC/read_xml_arch_file.c /^static void ProcessLayout(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: +ProcessLutClass SRC/read_xml_arch_file.c /^void ProcessLutClass(INOUTP t_pb_type *lut_pb_type) {$/;" f +ProcessMemoryClass SRC/read_xml_arch_file.c /^static void ProcessMemoryClass(INOUTP t_pb_type *mem_pb_type) {$/;" f file: +ProcessMode SRC/read_xml_arch_file.c /^static void ProcessMode(INOUTP ezxml_t Parent, t_mode * mode,$/;" f file: +ProcessModels SRC/read_xml_arch_file.c /^static void ProcessModels(INOUTP ezxml_t Node, OUTP struct s_arch *arch) {$/;" f file: +ProcessMrFPGATiming SRC/read_xml_mrfpga.c /^void ProcessMrFPGATiming(INOUTP ezxml_t Cur, $/;" f +ProcessPb_Type SRC/read_xml_arch_file.c /^static void ProcessPb_Type(INOUTP ezxml_t Parent, t_pb_type * pb_type,$/;" f file: +ProcessPb_TypePort SRC/read_xml_arch_file.c /^static void ProcessPb_TypePort(INOUTP ezxml_t Parent, t_port * port,$/;" f file: +ProcessPb_TypePort_Power SRC/read_xml_arch_file.c /^static void ProcessPb_TypePort_Power(ezxml_t Parent, t_port * port,$/;" f file: +ProcessPb_TypePower SRC/read_xml_arch_file.c /^static void ProcessPb_TypePower(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: +ProcessPb_TypePowerEstMethod SRC/read_xml_arch_file.c /^static void ProcessPb_TypePowerEstMethod(ezxml_t Parent, t_pb_type * pb_type) {$/;" f file: +ProcessPb_TypePowerPinToggle SRC/read_xml_arch_file.c /^static void ProcessPb_TypePowerPinToggle(ezxml_t parent, t_pb_type * pb_type) {$/;" f file: +ProcessPinToPinAnnotations SRC/read_xml_arch_file.c /^static void ProcessPinToPinAnnotations(ezxml_t Parent,$/;" f file: +ProcessPower SRC/read_xml_arch_file.c /^static void ProcessPower( INOUTP ezxml_t parent,$/;" f file: +ProcessSegments SRC/read_xml_arch_file.c /^static void ProcessSegments(INOUTP ezxml_t Parent,$/;" f file: +ProcessSpiceMCVariationParams SRC/read_xml_spice.c /^static void ProcessSpiceMCVariationParams(ezxml_t Parent,$/;" f file: +ProcessSpiceMeasParams SRC/read_xml_spice.c /^static void ProcessSpiceMeasParams(ezxml_t Parent,$/;" f file: +ProcessSpiceModel SRC/read_xml_spice.c /^static void ProcessSpiceModel(ezxml_t Parent,$/;" f file: +ProcessSpiceModelBuffer SRC/read_xml_spice.c /^static void ProcessSpiceModelBuffer(ezxml_t Node,$/;" f file: +ProcessSpiceModelDelayInfo SRC/read_xml_spice.c /^void ProcessSpiceModelDelayInfo(ezxml_t Node, $/;" f file: +ProcessSpiceModelGate SRC/read_xml_spice.c /^static void ProcessSpiceModelGate(ezxml_t Node, $/;" f file: +ProcessSpiceModelLUT SRC/read_xml_spice.c /^static void ProcessSpiceModelLUT(ezxml_t Node, $/;" f file: +ProcessSpiceModelMUX SRC/read_xml_spice.c /^static void ProcessSpiceModelMUX(ezxml_t Node, $/;" f file: +ProcessSpiceModelPassGateLogic SRC/read_xml_spice.c /^static void ProcessSpiceModelPassGateLogic(ezxml_t Node,$/;" f file: +ProcessSpiceModelPort SRC/read_xml_spice.c /^static void ProcessSpiceModelPort(ezxml_t Node,$/;" f file: +ProcessSpiceModelPortLutOutputMask SRC/read_xml_spice.c /^static void ProcessSpiceModelPortLutOutputMask(ezxml_t Node,$/;" f file: +ProcessSpiceModelRRAM SRC/read_xml_spice.c /^static void ProcessSpiceModelRRAM(ezxml_t Node, $/;" f file: +ProcessSpiceModelWireParam SRC/read_xml_spice.c /^static void ProcessSpiceModelWireParam(ezxml_t Parent,$/;" f file: +ProcessSpiceMonteCarloParams SRC/read_xml_spice.c /^static void ProcessSpiceMonteCarloParams(ezxml_t Parent, $/;" f file: +ProcessSpiceParams SRC/read_xml_spice.c /^static void ProcessSpiceParams(ezxml_t Parent,$/;" f file: +ProcessSpiceSRAM SRC/read_xml_spice.c /^void ProcessSpiceSRAM(INOUTP ezxml_t Node, OUTP struct s_arch* arch) {$/;" f +ProcessSpiceSRAMOrganization SRC/read_xml_spice.c /^void ProcessSpiceSRAMOrganization(INOUTP ezxml_t Node, $/;" f file: +ProcessSpiceSettings SRC/read_xml_spice.c /^void ProcessSpiceSettings(ezxml_t Parent,$/;" f +ProcessSpiceStimulateParams SRC/read_xml_spice.c /^static void ProcessSpiceStimulateParams(ezxml_t Parent,$/;" f file: +ProcessSpiceStimulateParamsRiseFall SRC/read_xml_spice.c /^static void ProcessSpiceStimulateParamsRiseFall(ezxml_t Parent,$/;" f file: +ProcessSpiceTechLibTransistors SRC/read_xml_spice.c /^static void ProcessSpiceTechLibTransistors(ezxml_t Parent,$/;" f file: +ProcessSpiceTransistorType SRC/read_xml_spice.c /^static void ProcessSpiceTransistorType(ezxml_t Parent,$/;" f file: +ProcessSwitchSegmentPatterns SRC/read_xml_arch_file.c /^static void ProcessSwitchSegmentPatterns(INOUTP ezxml_t Parent,$/;" f file: +ProcessSwitches SRC/read_xml_arch_file.c /^static void ProcessSwitches(INOUTP ezxml_t Parent,$/;" f file: +ProcessTechComp SRC/read_xml_mrfpga.c /^ProcessTechComp(INOUTP ezxml_t Node,$/;" f +ProcessTechHack SRC/read_xml_mrfpga.c /^ProcessTechHack(INOUTP ezxml_t Node,$/;" f +ProcessTechnology SRC/read_xml_mrfpga.c /^ProcessTechnology(INOUTP ezxml_t Node,$/;" f +ProcessWireBuffer SRC/read_xml_mrfpga.c /^ProcessWireBuffer(INOUTP ezxml_t Node,$/;" f +Process_Fc SRC/read_xml_arch_file.c /^static void Process_Fc(ezxml_t Node, t_type_descriptor * Type) {$/;" f file: +ProcessmrFPGA SRC/read_xml_mrfpga.c /^ProcessmrFPGA(INOUTP ezxml_t Node,$/;" f +R SRC/include/arch_types_mrfpga.h /^ float R; $/;" m struct:s_memristor_inf +R SRC/include/arch_types_mrfpga.h /^ float R;$/;" m struct:s_buffer_inf +R SRC/include/physical_types.h /^ float R;$/;" m struct:s_switch_inf +READLINE_H SRC/include/ReadLine.h 2;" d +READ_XML_ARCH_FILE_H SRC/include/read_xml_arch_file.h 2;" d +READ_XML_SPICE_UTIL_H SRC/fpga_spice_include/read_xml_spice_util.h 2;" d +READ_XML_UTIL_H SRC/include/read_xml_util.h 2;" d +RECEIVER SRC/include/physical_types.h /^ OPEN = -1, DRIVER = 0, RECEIVER = 1$/;" e enum:e_pin_type +RIGHT SRC/include/sides.h /^ RIGHT = 1, $/;" e enum:e_side +R_minW_nmos SRC/include/physical_types.h /^ float R_minW_nmos;$/;" m struct:s_arch +R_minW_pmos SRC/include/physical_types.h /^ float R_minW_pmos;$/;" m struct:s_arch +R_opin_cblock SRC/include/arch_types_mrfpga.h /^ float R_opin_cblock;$/;" m struct:s_arch_mrfpga +R_opin_cblock SRC/include/physical_types.h /^ float R_opin_cblock;$/;" m struct:s_timing_inf +ReadLineTokens SRC/ReadLine.c /^ReadLineTokens(INOUTP FILE * InFile, INOUTP int *LineNum) {$/;" f +Rmetal SRC/include/physical_types.h /^ float Rmetal;$/;" m struct:s_segment_inf +Rseg_global SRC/include/arch_types_mrfpga.h /^ float Rseg_global;$/;" m struct:s_arch_mrfpga +SBType SRC/include/physical_types.h /^ enum e_switch_block_type SBType;$/;" m struct:s_arch typeref:enum:s_arch::e_switch_block_type +SDCFile SRC/include/physical_types.h /^ char * SDCFile; \/* only here for convenience of passing to path_delay.c *\/$/;" m struct:s_timing_inf +SIDES_H SRC/include/sides.h 2;" d +SPICE_ABS SRC/fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type +SPICE_CB_MUX_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_CB_MUX_TB, $/;" e enum:e_spice_tb_type +SPICE_CB_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_CB_TB,$/;" e enum:e_spice_tb_type +SPICE_FRAC SRC/fpga_spice_include/spice_types.h /^ SPICE_FRAC, SPICE_ABS$/;" e enum:e_spice_accuracy_type +SPICE_GRID_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_GRID_TB,$/;" e enum:e_spice_tb_type +SPICE_HARDLOGIC_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_HARDLOGIC_TB$/;" e enum:e_spice_tb_type +SPICE_IO_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_IO_TB,$/;" e enum:e_spice_tb_type +SPICE_LIB_ACADEMIA SRC/fpga_spice_include/spice_types.h /^ SPICE_LIB_ACADEMIA$/;" e enum:e_spice_tech_lib_type +SPICE_LIB_INDUSTRY SRC/fpga_spice_include/spice_types.h /^ SPICE_LIB_INDUSTRY,$/;" e enum:e_spice_tech_lib_type +SPICE_LUT_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_LUT_TB,$/;" e enum:e_spice_tb_type +SPICE_MODEL_BUF_BUF SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_BUF$/;" e enum:e_spice_model_buffer_type +SPICE_MODEL_BUF_INV SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_BUF_INV, $/;" e enum:e_spice_model_buffer_type +SPICE_MODEL_CHAN_WIRE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_CHAN_WIRE, $/;" e enum:e_spice_model_type +SPICE_MODEL_DELAY_FALL SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DELAY_FALL$/;" e enum:spice_model_delay_type +SPICE_MODEL_DELAY_RISE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DELAY_RISE, $/;" e enum:spice_model_delay_type +SPICE_MODEL_DESIGN_CMOS SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_CMOS, $/;" e enum:e_spice_model_design_tech +SPICE_MODEL_DESIGN_RRAM SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_DESIGN_RRAM$/;" e enum:e_spice_model_design_tech +SPICE_MODEL_FF SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_FF, $/;" e enum:e_spice_model_type +SPICE_MODEL_GATE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_GATE $/;" e enum:e_spice_model_type +SPICE_MODEL_GATE_AND SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_GATE_AND, $/;" e enum:e_spice_model_gate_type +SPICE_MODEL_GATE_OR SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_GATE_OR$/;" e enum:e_spice_model_gate_type +SPICE_MODEL_HARDLOGIC SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_HARDLOGIC,$/;" e enum:e_spice_model_type +SPICE_MODEL_INVBUF SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_INVBUF, $/;" e enum:e_spice_model_type +SPICE_MODEL_IOPAD SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_IOPAD, $/;" e enum:e_spice_model_type +SPICE_MODEL_LUT SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_LUT, $/;" e enum:e_spice_model_type +SPICE_MODEL_MUX SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_MUX, $/;" e enum:e_spice_model_type +SPICE_MODEL_PASSGATE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASSGATE, $/;" e enum:e_spice_model_type +SPICE_MODEL_PASS_GATE_TRANSISTOR SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSISTOR$/;" e enum:e_spice_model_pass_gate_logic_type +SPICE_MODEL_PASS_GATE_TRANSMISSION SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PASS_GATE_TRANSMISSION, $/;" e enum:e_spice_model_pass_gate_logic_type +SPICE_MODEL_PORT_BL SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BL,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_BLB SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_BLB,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_CLOCK SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_CLOCK, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_INOUT SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INOUT, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_INPUT SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_INPUT, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_OUTPUT SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_OUTPUT, $/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_SRAM SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_SRAM,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_WL SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WL,$/;" e enum:e_spice_model_port_type +SPICE_MODEL_PORT_WLB SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_PORT_WLB$/;" e enum:e_spice_model_port_type +SPICE_MODEL_SCFF SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_SCFF,$/;" e enum:e_spice_model_type +SPICE_MODEL_SRAM SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_SRAM, $/;" e enum:e_spice_model_type +SPICE_MODEL_STRUCTURE_CROSSBAR SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_CROSSBAR $/;" e enum:e_spice_model_structure +SPICE_MODEL_STRUCTURE_MULTILEVEL SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_MULTILEVEL, $/;" e enum:e_spice_model_structure +SPICE_MODEL_STRUCTURE_ONELEVEL SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_ONELEVEL, $/;" e enum:e_spice_model_structure +SPICE_MODEL_STRUCTURE_TREE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_STRUCTURE_TREE, $/;" e enum:e_spice_model_structure +SPICE_MODEL_WIRE SRC/fpga_spice_include/spice_types.h /^ SPICE_MODEL_WIRE, $/;" e enum:e_spice_model_type +SPICE_PB_MUX_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_PB_MUX_TB, $/;" e enum:e_spice_tb_type +SPICE_PB_PORT_CLOCK SRC/fpga_spice_include/spice_types.h /^ SPICE_PB_PORT_CLOCK$/;" e enum:e_spice_pb_port_type +SPICE_PB_PORT_INPUT SRC/fpga_spice_include/spice_types.h /^ SPICE_PB_PORT_INPUT,$/;" e enum:e_spice_pb_port_type +SPICE_PB_PORT_OUTPUT SRC/fpga_spice_include/spice_types.h /^ SPICE_PB_PORT_OUTPUT,$/;" e enum:e_spice_pb_port_type +SPICE_SB_MUX_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_SB_MUX_TB, $/;" e enum:e_spice_tb_type +SPICE_SB_TB SRC/fpga_spice_include/spice_types.h /^ SPICE_SB_TB,$/;" e enum:e_spice_tb_type +SPICE_SRAM_MEMORY_BANK SRC/fpga_spice_include/spice_types.h /^ SPICE_SRAM_MEMORY_BANK$/;" e enum:e_sram_orgz +SPICE_SRAM_SCAN_CHAIN SRC/fpga_spice_include/spice_types.h /^ SPICE_SRAM_SCAN_CHAIN,$/;" e enum:e_sram_orgz +SPICE_SRAM_STANDALONE SRC/fpga_spice_include/spice_types.h /^ SPICE_SRAM_STANDALONE,$/;" e enum:e_sram_orgz +SPICE_TRANS_IO_NMOS SRC/fpga_spice_include/spice_types.h /^ SPICE_TRANS_IO_NMOS, $/;" e enum:e_spice_trans_type +SPICE_TRANS_IO_PMOS SRC/fpga_spice_include/spice_types.h /^ SPICE_TRANS_IO_PMOS$/;" e enum:e_spice_trans_type +SPICE_TRANS_NMOS SRC/fpga_spice_include/spice_types.h /^ SPICE_TRANS_NMOS, $/;" e enum:e_spice_trans_type +SPICE_TRANS_PMOS SRC/fpga_spice_include/spice_types.h /^ SPICE_TRANS_PMOS, $/;" e enum:e_spice_trans_type +SPICE_TYPES_H SRC/fpga_spice_include/spice_types.h 2;" d +STTRAM SRC/include/arch_types_mrfpga.h /^ CONV = 0, MONO, STTRAM, PCRAM_Xie, PCRAM_Pierre, NEM $/;" e enum:e_tech_comp +SUBSET SRC/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +SWSEG_UNBUF_CB SRC/include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type +SWSEG_UNBUF_SB SRC/include/physical_types.h /^ SWSEG_UNBUF_SB, SWSEG_UNBUF_CB$/;" e enum:e_swseg_pattern_type +Segments SRC/include/physical_types.h /^ t_segment_inf * Segments;$/;" m struct:s_arch +SetupEmptyType SRC/read_xml_arch_file.c /^static void SetupEmptyType(void) {$/;" f file: +SetupGridLocations SRC/read_xml_arch_file.c /^static void SetupGridLocations(ezxml_t Locations, t_type_descriptor * Type) {$/;" f file: +SetupPinEquivalenceAutoDetect SRC/read_xml_arch_file.c /^void SetupPinEquivalenceAutoDetect(ezxml_t Parent, t_type_descriptor* Type) {$/;" f file: +SetupPinLocationsAndPinClasses SRC/read_xml_arch_file.c /^static void SetupPinLocationsAndPinClasses(ezxml_t Locations,$/;" f file: +Side SRC/include/sides.h /^class Side {$/;" c +Side SRC/sides.cpp /^Side::Side() {$/;" f class:Side +Side SRC/sides.cpp /^Side::Side(enum e_side side) {$/;" f class:Side +Side SRC/sides.cpp /^Side::Side(size_t side) { $/;" f class:Side +Switches SRC/include/physical_types.h /^ struct s_switch_inf *Switches;$/;" m struct:s_arch typeref:struct:s_arch::s_switch_inf +SyncModelsPbTypes SRC/read_xml_arch_file.c /^static void SyncModelsPbTypes(INOUTP struct s_arch *arch,$/;" f file: +SyncModelsPbTypes_rec SRC/read_xml_arch_file.c /^static void SyncModelsPbTypes_rec(INOUTP struct s_arch *arch,$/;" f file: +TOKENS SRC/include/arch_types.h 19;" d +TOP SRC/include/sides.h /^ TOP = 0, $/;" e enum:e_side +TRUE SRC/include/util.h /^ FALSE, TRUE$/;" e enum:__anon4 +TYPICAL_CORNER SRC/fpga_spice_include/spice_types.h /^ TYPICAL_CORNER,$/;" e enum:e_process_corner +T_ipin_cblock SRC/include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_arch +T_ipin_cblock SRC/include/physical_types.h /^ float T_ipin_cblock;$/;" m struct:s_timing_inf +T_opin_cblock SRC/include/arch_types_mrfpga.h /^ float T_opin_cblock;$/;" m struct:s_arch_mrfpga +T_opin_cblock SRC/include/physical_types.h /^ float T_opin_cblock;$/;" m struct:s_timing_inf +Tdel SRC/include/arch_types_mrfpga.h /^ float Tdel; $/;" m struct:s_memristor_inf +Tdel SRC/include/arch_types_mrfpga.h /^ float Tdel;$/;" m struct:s_buffer_inf +Tdel SRC/include/physical_types.h /^ float Tdel;$/;" m struct:s_switch_inf +UNDEFINED SRC/include/arch_types.h 22;" d +UNIFORM SRC/include/physical_types.h /^ UNIFORM, GAUSSIAN, PULSE, DELTA$/;" e enum:e_stat +UNIVERSAL SRC/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +UNI_DIRECTIONAL SRC/include/physical_types.h /^ UNI_DIRECTIONAL, BI_DIRECTIONAL$/;" e enum:e_directionality +UNKNOWN_CLASS SRC/include/physical_types.h /^ UNKNOWN_CLASS = 0, LUT_CLASS = 1, LATCH_CLASS = 2, MEMORY_CLASS = 3$/;" e enum:e_pb_type_class +UTIL_H SRC/include/util.h 2;" d +UpdateAndCheckModels SRC/read_xml_arch_file.c /^static void UpdateAndCheckModels(INOUTP struct s_arch *arch) {$/;" f file: +VPR_VERSION SRC/include/arch_types.h 16;" d +W SRC/include/physical_types.h /^ int W;$/;" m struct:s_clb_grid +WARNTAG SRC/include/util.h 27;" d +WILTON SRC/include/physical_types.h /^ SUBSET, WILTON, UNIVERSAL, FULL$/;" e enum:e_switch_block_type +WIRE_MODEL_PIE SRC/fpga_spice_include/spice_types.h /^ WIRE_MODEL_PIE,$/;" e enum:e_wire_model_type +WIRE_MODEL_T SRC/fpga_spice_include/spice_types.h /^ WIRE_MODEL_T$/;" e enum:e_wire_model_type +WORST_CORNER SRC/fpga_spice_include/spice_types.h /^ WORST_CORNER$/;" e enum:e_process_corner +XmlReadArch SRC/read_xml_arch_file.c /^void XmlReadArch(INP const char *ArchFile, INP boolean timing_enabled,$/;" f +_EZXML_H SRC/include/ezxml.h 26;" d +abs_variation SRC/fpga_spice_include/spice_types.h /^ float abs_variation;$/;" m struct:s_spice_mc_variation_params +absolute_length SRC/include/physical_types.h /^ float absolute_length;$/;" m union:s_port_power::__anon3 +absolute_power_per_instance SRC/include/physical_types.h /^ t_power_usage absolute_power_per_instance; \/* User-provided absolute power per block *\/$/;" m struct:s_pb_type_power +accuracy SRC/fpga_spice_include/spice_types.h /^ float accuracy;$/;" m struct:s_spice_meas_params +accuracy_type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type accuracy_type;$/;" m struct:s_spice_meas_params typeref:enum:s_spice_meas_params::e_spice_accuracy_type +add_const_input SRC/fpga_spice_include/spice_types.h /^ boolean add_const_input;$/;" m struct:s_spice_model_mux +addr SRC/fpga_spice_include/spice_types.h /^ int addr; \/* Address to write the value *\/$/;" m struct:s_conf_bit +advanced_rram_design SRC/fpga_spice_include/spice_types.h /^ boolean advanced_rram_design;$/;" m struct:s_spice_model_mux +alloc_and_load_default_child_for_pb_type SRC/read_xml_arch_file.c /^static void alloc_and_load_default_child_for_pb_type( INOUTP t_pb_type *pb_type,$/;" f file: +alloc_ivector_and_copy_int_list SRC/util.c /^void alloc_ivector_and_copy_int_list(t_linked_int ** list_head_ptr,$/;" f +alloc_matrix SRC/util.c /^alloc_matrix(int nrmin, int nrmax, int ncmin, int ncmax, size_t elsize) {$/;" f +alloc_matrix3 SRC/util.c /^alloc_matrix3(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f +alloc_matrix4 SRC/util.c /^alloc_matrix4(int nrmin, int nrmax, int ncmin, int ncmax, int ndmin, int ndmax,$/;" f +annotations SRC/include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_interconnect +annotations SRC/include/physical_types.h /^ t_pin_to_pin_annotation *annotations; \/* [0..num_annotations-1] *\/$/;" m struct:s_pb_type +arch_mrfpga SRC/include/physical_types.h /^ t_arch_mrfpga arch_mrfpga;$/;" m struct:s_arch +area SRC/fpga_spice_include/spice_types.h /^ float area; \/\/Xifan TANG$/;" m struct:s_sram_inf +area SRC/include/physical_types.h /^ float area;$/;" m struct:s_type_descriptor +attr SRC/include/ezxml.h /^ char ***attr; \/* default attributes *\/$/;" m struct:ezxml_root +attr SRC/include/ezxml.h /^ char **attr; \/* tag attributes { name, value, name, value, ... NULL } *\/$/;" m struct:ezxml +auto_select_sim_num_clk_cycle SRC/fpga_spice_include/spice_types.h /^ int auto_select_sim_num_clk_cycle;$/;" m struct:s_spice_meas_params +autosize_buffer SRC/include/physical_types.h /^ boolean autosize_buffer; \/* autosize clock buffers *\/$/;" m struct:s_clock_network +base_cost SRC/include/cad_types.h /^ float base_cost; \/* base cost of pattern eg. If a group of logical blocks match a pattern of smaller primitives, that is better than the same group using bigger primitives *\/$/;" m struct:s_pack_patterns +base_cost SRC/include/cad_types.h /^ float base_cost; \/* cost independant of current status of packing *\/$/;" m struct:s_cluster_placement_primitive +bl SRC/fpga_spice_include/spice_types.h /^ t_conf_bit* bl;$/;" m struct:s_conf_bit_info +blif_model SRC/include/physical_types.h /^ char *blif_model;$/;" m struct:s_pb_type +block_id SRC/include/cad_types.h /^ int block_id;$/;" m struct:s_pack_pattern_block +boolean SRC/include/util.h /^typedef int boolean;$/;" t +boolean SRC/include/util.h /^} boolean;$/;" t typeref:enum:__anon4 +buf_size SRC/include/physical_types.h /^ float buf_size;$/;" m struct:s_switch_inf +buffer_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* buffer_info;$/;" m struct:s_spice_model_design_tech_info +buffer_size SRC/include/physical_types.h /^ float buffer_size; \/* if not autosized, the clock buffer size *\/$/;" m struct:s_clock_network +buffer_size SRC/include/physical_types.h /^ float buffer_size;$/;" m struct:s_pb_graph_pin_power +buffer_size SRC/include/physical_types.h /^ float buffer_size;$/;" m struct:s_port_power +buffer_type SRC/include/physical_types.h /^ e_power_buffer_type buffer_type;$/;" m struct:s_port_power +buffered SRC/include/physical_types.h /^ boolean buffered;$/;" m struct:s_switch_inf +c_str SRC/sides.cpp /^const char* Side::c_str() const { $/;" f class:Side +cap_val SRC/fpga_spice_include/spice_types.h /^ float cap_val; $/;" m struct:s_spice_model_wire_param +capacitance SRC/include/physical_types.h /^ float capacitance;$/;" m struct:s_pb_graph_edge +capacity SRC/include/physical_types.h /^ int capacity;$/;" m struct:s_type_descriptor +captab SRC/fpga_spice_include/spice_types.h /^ int captab;$/;" m struct:s_spice_params +cat_llists SRC/linkedlist.c /^t_llist* cat_llists(t_llist* head1,$/;" f +cb SRC/include/physical_types.h /^ boolean *cb;$/;" m struct:s_segment_inf +cb_len SRC/include/physical_types.h /^ int cb_len;$/;" m struct:s_segment_inf +cb_switches SRC/include/physical_types.h /^ t_switch_inf* cb_switches;$/;" m struct:s_arch +cb_type_descriptors SRC/read_xml_arch_file.c /^static struct s_type_descriptor *cb_type_descriptors;$/;" v typeref:struct:s_type_descriptor file: +cbx_index_high SRC/fpga_spice_include/spice_types.h /^ int** cbx_index_high;$/;" m struct:s_spice_model +cbx_index_low SRC/fpga_spice_include/spice_types.h /^ int** cbx_index_low;$/;" m struct:s_spice_model +cby_index_high SRC/fpga_spice_include/spice_types.h /^ int** cby_index_high;$/;" m struct:s_spice_model +cby_index_low SRC/fpga_spice_include/spice_types.h /^ int** cby_index_low;$/;" m struct:s_spice_model +chain_name SRC/include/physical_types.h /^ char *chain_name;$/;" m struct:s_port +chain_root_pin SRC/include/cad_types.h /^ t_pb_graph_pin *chain_root_pin; \/* pointer to logic block input pin that drives this chain from the preceding logic block *\/ $/;" m struct:s_pack_patterns +chan_length SRC/fpga_spice_include/spice_types.h /^ float chan_length;$/;" m struct:s_spice_transistor_type +chan_width_io SRC/include/physical_types.h /^ float chan_width_io;$/;" m struct:s_chan_width_dist +chan_x_dist SRC/include/physical_types.h /^ t_chan chan_x_dist;$/;" m struct:s_chan_width_dist +chan_y_dist SRC/include/physical_types.h /^ t_chan chan_y_dist;$/;" m struct:s_chan_width_dist +check_dptr_exist_in_llist SRC/linkedlist.c /^boolean check_dptr_exist_in_llist(t_llist* head, void* data_ptr) {$/;" f +check_spice_models SRC/read_xml_spice.c /^static void check_spice_models(int num_spice_model,$/;" f file: +check_tech_lib SRC/read_xml_spice.c /^static void check_tech_lib(t_spice_tech_lib tech_lib, $/;" f file: +child SRC/include/ezxml.h /^ ezxml_t child; \/* head of sub tag list, NULL if none *\/$/;" m struct:ezxml +child_pb_graph_nodes SRC/include/physical_types.h /^ struct s_pb_graph_node ***child_pb_graph_nodes; \/* [0..num_modes-1][0..num_pb_type_in_mode-1][0..num_pb-1] *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node +chunk_ptr_head SRC/include/util.h /^ struct s_linked_vptr *chunk_ptr_head; $/;" m struct:s_chunk typeref:struct:s_chunk::s_linked_vptr +class_inf SRC/include/physical_types.h /^ struct s_class *class_inf; \/* [0..num_class-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_class +class_type SRC/include/physical_types.h /^ enum e_pb_type_class class_type;$/;" m struct:s_pb_type typeref:enum:s_pb_type::e_pb_type_class +clb_grid SRC/include/physical_types.h /^ struct s_clb_grid clb_grid;$/;" m struct:s_arch typeref:struct:s_arch::s_clb_grid +clock SRC/include/physical_types.h /^ char * clock;$/;" m struct:s_pin_to_pin_annotation +clock_inf SRC/include/physical_types.h /^ t_clock_network *clock_inf; \/* Details about each clock *\/$/;" m struct:s_clock_arch +clock_pins SRC/include/physical_types.h /^ t_pb_graph_pin **clock_pins; \/* [0..num_clock_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node +clock_slew_fall_time SRC/fpga_spice_include/spice_types.h /^ float clock_slew_fall_time; $/;" m struct:s_spice_stimulate_params +clock_slew_fall_type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +clock_slew_rise_time SRC/fpga_spice_include/spice_types.h /^ float clock_slew_rise_time; $/;" m struct:s_spice_stimulate_params +clock_slew_rise_type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type clock_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +clocks SRC/include/physical_types.h /^ t_clock_arch * clocks;$/;" m struct:s_arch +close SRC/ezxml.c 61;" d file: +cluster_placement_primitive SRC/include/physical_types.h /^ struct s_cluster_placement_primitive *cluster_placement_primitive; \/* pointer to indexing structure useful during packing stage *\/$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_cluster_placement_primitive +cmos_variation SRC/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params cmos_variation;$/;" m struct:s_spice_mc_params +cnt SRC/fpga_spice_include/spice_types.h /^ int cnt; \/* Used in mux_testbench only*\/$/;" m struct:s_spice_mux_model +cnt SRC/fpga_spice_include/spice_types.h /^ int cnt;$/;" m struct:s_spice_model +col_rel SRC/include/physical_types.h /^ float col_rel;$/;" m struct:s_grid_loc_def +conf_bit_head SRC/fpga_spice_include/spice_types.h /^ t_llist* conf_bit_head; $/;" m struct:s_sram_orgz_info +connections SRC/include/cad_types.h /^ struct s_pack_pattern_connections *connections; \/* linked list of connections of logic blocks in pattern *\/$/;" m struct:s_pack_pattern_block typeref:struct:s_pack_pattern_block::s_pack_pattern_connections +const_input_val SRC/fpga_spice_include/spice_types.h /^ int const_input_val;$/;" m struct:s_spice_model_mux +cont SRC/util.c /^static int cont; \/* line continued? *\/$/;" v file: +create_llist SRC/linkedlist.c /^t_llist* create_llist(int len) {$/;" f +cur SRC/include/ezxml.h /^ ezxml_t cur; \/* current xml tree insertion point *\/$/;" m struct:ezxml_root +current_random SRC/util.c /^static unsigned int current_random = 0;$/;" v file: +data SRC/include/util.h /^ int data;$/;" m struct:s_linked_int +data_vptr SRC/include/util.h /^ void *data_vptr;$/;" m struct:s_linked_vptr +dc SRC/include/physical_types.h /^ float dc;$/;" m struct:s_chan +default_mode_num_conf_bits SRC/include/physical_types.h /^ int default_mode_num_conf_bits;$/;" m struct:s_pb_type +default_mode_num_iopads SRC/include/physical_types.h /^ int default_mode_num_iopads;$/;" m struct:s_pb_type +default_mode_num_mode_bits SRC/include/physical_types.h /^ int default_mode_num_mode_bits;$/;" m struct:s_pb_type +default_mode_num_reserved_conf_bits SRC/include/physical_types.h /^ int default_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type +default_val SRC/fpga_spice_include/spice_types.h /^ int default_val;$/;" m struct:s_spice_model_port +define_idle_mode SRC/include/physical_types.h /^ int define_idle_mode; $/;" m struct:s_mode +define_physical_mode SRC/include/physical_types.h /^ int define_physical_mode; $/;" m struct:s_mode +delay_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_delay_info* delay_info;$/;" m struct:s_spice_model +delay_max SRC/include/physical_types.h /^ float delay_max;$/;" m struct:s_pb_graph_edge +delay_min SRC/include/physical_types.h /^ float delay_min;$/;" m struct:s_pb_graph_edge +delete_in_vptr_list SRC/util.c /^delete_in_vptr_list(struct s_linked_vptr *head) {$/;" f +dens SRC/include/physical_types.h /^ float dens; \/* Switching density of net assigned to this clock *\/$/;" m struct:s_clock_network +density SRC/fpga_spice_include/spice_types.h /^ float density;$/;" m struct:s_spice_net_info +depth SRC/include/physical_types.h /^ int depth; \/* depth of pb_type *\/$/;" m struct:s_pb_type +design_tech SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_design_tech design_tech;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_design_tech +design_tech_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_design_tech_info design_tech_info;$/;" m struct:s_spice_model +dir SRC/include/logic_types.h /^ enum PORTS dir; \/* port direction *\/$/;" m struct:s_model_ports typeref:enum:s_model_ports::PORTS +directionality SRC/include/physical_types.h /^ enum e_directionality directionality;$/;" m struct:s_segment_inf typeref:enum:s_segment_inf::e_directionality +disabled_in_packing SRC/include/physical_types.h /^ boolean disabled_in_packing;$/;" m struct:s_mode +dptr SRC/fpga_spice_include/linkedlist.h /^ void* dptr;$/;" m struct:s_llist +driver_pin SRC/include/physical_types.h /^ int driver_pin;$/;" m struct:s_pb_graph_edge +driver_set SRC/include/physical_types.h /^ int driver_set;$/;" m struct:s_pb_graph_edge +dump_explicit_port_map SRC/fpga_spice_include/spice_types.h /^ boolean dump_explicit_port_map;$/;" m struct:s_spice_model +dump_structural_verilog SRC/fpga_spice_include/spice_types.h /^ boolean dump_structural_verilog;$/;" m struct:s_spice_model +dynamic SRC/include/physical_types.h /^ float dynamic;$/;" m struct:s_power_usage +e SRC/include/ezxml.h /^ char *e; \/* end of work area *\/$/;" m struct:ezxml_root +e_Fc_type SRC/include/physical_types.h /^enum e_Fc_type {$/;" g +e_directionality SRC/include/physical_types.h /^enum e_directionality {$/;" g +e_grid_loc_type SRC/include/physical_types.h /^enum e_grid_loc_type {$/;" g +e_interconnect SRC/include/physical_types.h /^enum e_interconnect {$/;" g +e_pb_graph_pin_type SRC/include/physical_types.h /^enum e_pb_graph_pin_type {$/;" g +e_pb_type_class SRC/include/physical_types.h /^enum e_pb_type_class {$/;" g +e_pin_location_distr SRC/include/physical_types.h /^enum e_pin_location_distr {$/;" g +e_pin_to_pin_annotation_format SRC/include/physical_types.h /^enum e_pin_to_pin_annotation_format {$/;" g +e_pin_to_pin_annotation_type SRC/include/physical_types.h /^enum e_pin_to_pin_annotation_type {$/;" g +e_pin_to_pin_capacitance_annotations SRC/include/physical_types.h /^enum e_pin_to_pin_capacitance_annotations {$/;" g +e_pin_to_pin_delay_annotations SRC/include/physical_types.h /^enum e_pin_to_pin_delay_annotations {$/;" g +e_pin_to_pin_mode_select_annotations SRC/include/physical_types.h /^enum e_pin_to_pin_mode_select_annotations {$/;" g +e_pin_to_pin_pack_pattern_annotations SRC/include/physical_types.h /^enum e_pin_to_pin_pack_pattern_annotations {$/;" g +e_pin_type SRC/include/physical_types.h /^enum e_pin_type {$/;" g +e_power_buffer_type SRC/include/physical_types.h /^} e_power_buffer_type;$/;" t typeref:enum:__anon2 +e_power_estimation_method SRC/include/physical_types.h /^typedef enum e_power_estimation_method_ e_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ +e_power_estimation_method_ SRC/include/physical_types.h /^enum e_power_estimation_method_ {$/;" g +e_power_wire_type SRC/include/physical_types.h /^} e_power_wire_type;$/;" t typeref:enum:__anon1 +e_process_corner SRC/fpga_spice_include/spice_types.h /^enum e_process_corner {$/;" g +e_side SRC/include/sides.h /^enum e_side {$/;" g +e_spice_accuracy_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_accuracy_type {$/;" g +e_spice_ff_trigger_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_ff_trigger_type {$/;" g +e_spice_model_buffer_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_buffer_type {$/;" g +e_spice_model_design_tech SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_design_tech {$/;" g +e_spice_model_gate_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_gate_type {$/;" g +e_spice_model_pass_gate_logic_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_pass_gate_logic_type {$/;" g +e_spice_model_port_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_port_type {$/;" g +e_spice_model_structure SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_structure {$/;" g +e_spice_model_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_model_type {$/;" g +e_spice_pb_port_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_pb_port_type {$/;" g +e_spice_pin2pin_interc_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_pin2pin_interc_type {$/;" g +e_spice_tb_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_tb_type {$/;" g +e_spice_tech_lib_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_tech_lib_type {$/;" g +e_spice_trans_type SRC/fpga_spice_include/spice_types.h /^enum e_spice_trans_type {$/;" g +e_sram_orgz SRC/fpga_spice_include/spice_types.h /^enum e_sram_orgz {$/;" g +e_stat SRC/include/physical_types.h /^enum e_stat {$/;" g +e_switch_block_type SRC/include/physical_types.h /^enum e_switch_block_type {$/;" g +e_swseg_pattern_type SRC/include/physical_types.h /^enum e_swseg_pattern_type {$/;" g +e_tech_comp SRC/include/arch_types_mrfpga.h /^enum e_tech_comp { $/;" g +e_wire_model_type SRC/fpga_spice_include/spice_types.h /^enum e_wire_model_type {$/;" g +energy_per_toggle SRC/include/physical_types.h /^ float energy_per_toggle;$/;" m struct:s_port_power +ent SRC/include/ezxml.h /^ char **ent; \/* general entities (ampersand sequences) *\/$/;" m struct:ezxml_root +equivalent SRC/include/physical_types.h /^ boolean equivalent;$/;" m struct:s_port +err SRC/include/ezxml.h /^ char err[EZXML_ERRL]; \/* error string *\/$/;" m struct:ezxml_root +estimation_method SRC/include/physical_types.h /^ e_power_estimation_method estimation_method;$/;" m struct:s_pb_type_power +exist SRC/fpga_spice_include/spice_types.h /^ int exist;$/;" m struct:s_spice_model_buffer +ezxml SRC/include/ezxml.h /^struct ezxml {$/;" s +ezxml_add_child SRC/ezxml.c /^ezxml_t ezxml_add_child(ezxml_t xml, char *name, size_t off) {$/;" f +ezxml_add_child_d SRC/include/ezxml.h 149;" d +ezxml_ampencode SRC/ezxml.c /^ezxml_ampencode(const char *s, size_t len, char **dst, size_t * dlen,$/;" f file: +ezxml_attr SRC/ezxml.c /^ezxml_attr(ezxml_t xml, const char *attr) {$/;" f +ezxml_char_content SRC/ezxml.c /^static void ezxml_char_content(ezxml_root_t root, char *s,$/;" f file: +ezxml_child SRC/ezxml.c /^ezxml_t ezxml_child(ezxml_t xml, const char *name) {$/;" f +ezxml_close_tag SRC/ezxml.c /^static ezxml_t ezxml_close_tag(ezxml_root_t root, char *name, char *s) {$/;" f file: +ezxml_cut SRC/ezxml.c /^ezxml_t ezxml_cut(ezxml_t xml) {$/;" f +ezxml_decode SRC/ezxml.c /^ezxml_decode(char *s, char **ent, char t) {$/;" f file: +ezxml_ent_ok SRC/ezxml.c /^static int ezxml_ent_ok(char *name, char *s, char **ent) {$/;" f file: +ezxml_err SRC/ezxml.c /^static ezxml_t ezxml_err(ezxml_root_t root, char *s, const char *err, ...) {$/;" f file: +ezxml_error SRC/ezxml.c /^ezxml_error(ezxml_t xml) {$/;" f +ezxml_free SRC/ezxml.c /^void ezxml_free(ezxml_t xml) {$/;" f +ezxml_free_attr SRC/ezxml.c /^static void ezxml_free_attr(char **attr) {$/;" f file: +ezxml_get SRC/ezxml.c /^ezxml_t ezxml_get(ezxml_t xml, ...) {$/;" f +ezxml_idx SRC/ezxml.c /^ezxml_t ezxml_idx(ezxml_t xml, int idx) {$/;" f +ezxml_insert SRC/ezxml.c /^ezxml_t ezxml_insert(ezxml_t xml, ezxml_t dest, size_t off) {$/;" f +ezxml_internal_dtd SRC/ezxml.c /^static short ezxml_internal_dtd(ezxml_root_t root, char *s,$/;" f file: +ezxml_move SRC/include/ezxml.h 178;" d +ezxml_name SRC/include/ezxml.h 108;" d +ezxml_new SRC/ezxml.c /^ezxml_t ezxml_new(char *name) {$/;" f +ezxml_new_d SRC/include/ezxml.h 142;" d +ezxml_next SRC/include/ezxml.h 101;" d +ezxml_open_tag SRC/ezxml.c /^static void ezxml_open_tag(ezxml_root_t root, int line, char *name, char **attr) {$/;" f file: +ezxml_parse_fd SRC/ezxml.c /^ezxml_t ezxml_parse_fd(int fd) {$/;" f +ezxml_parse_file SRC/ezxml.c /^ezxml_t ezxml_parse_file(const char *file) {$/;" f +ezxml_parse_fp SRC/ezxml.c /^ezxml_t ezxml_parse_fp(FILE * fp) {$/;" f +ezxml_parse_str SRC/ezxml.c /^ezxml_t ezxml_parse_str(char *s, size_t len) {$/;" f +ezxml_pi SRC/ezxml.c /^ezxml_pi(ezxml_t xml, const char *target) {$/;" f +ezxml_proc_inst SRC/ezxml.c /^static void ezxml_proc_inst(ezxml_root_t root, char *s, size_t len) {$/;" f file: +ezxml_remove SRC/include/ezxml.h 181;" d +ezxml_root SRC/include/ezxml.h /^struct ezxml_root { \/* additional data for the root tag *\/$/;" s +ezxml_root_t SRC/include/ezxml.h /^typedef struct ezxml_root *ezxml_root_t;$/;" t typeref:struct:ezxml_root +ezxml_set_attr SRC/ezxml.c /^ezxml_t ezxml_set_attr(ezxml_t xml, char *name, char *value) {$/;" f +ezxml_set_attr_d SRC/include/ezxml.h 164;" d +ezxml_set_flag SRC/ezxml.c /^ezxml_t ezxml_set_flag(ezxml_t xml, short flag) {$/;" f +ezxml_set_txt SRC/ezxml.c /^ezxml_t ezxml_set_txt(ezxml_t xml, char *txt) {$/;" f +ezxml_set_txt_d SRC/include/ezxml.h 156;" d +ezxml_str2utf8 SRC/ezxml.c /^ezxml_str2utf8(char **s, size_t * len) {$/;" f file: +ezxml_t SRC/include/ezxml.h /^typedef struct ezxml *ezxml_t;$/;" t typeref:struct:ezxml +ezxml_toxml SRC/ezxml.c /^ezxml_toxml(ezxml_t xml) {$/;" f +ezxml_toxml_r SRC/ezxml.c /^ezxml_toxml_r(ezxml_t xml, char **s, size_t * len, size_t * max, size_t start,$/;" f file: +ezxml_txt SRC/include/ezxml.h 111;" d +ezxml_vget SRC/ezxml.c /^ezxml_t ezxml_vget(ezxml_t xml, va_list ap) {$/;" f +f_per_stage SRC/fpga_spice_include/spice_types.h /^ int f_per_stage;$/;" m struct:s_spice_model_buffer +fan_in SRC/include/physical_types.h /^ int fan_in;$/;" m struct:s_interconnect +fan_out SRC/include/physical_types.h /^ int fan_out;$/;" m struct:s_interconnect +fast SRC/fpga_spice_include/spice_types.h /^ int fast;$/;" m struct:s_spice_params +file_exists SRC/util.c /^boolean file_exists(const char * filename) {$/;" f +file_line_number SRC/util.c /^int file_line_number; \/* file in line number being parsed *\/$/;" v +findPortByName SRC/read_xml_arch_file.c /^static t_port * findPortByName(const char * name, t_pb_type * pb_type,$/;" f file: +find_length_llist SRC/linkedlist.c /^int find_length_llist(t_llist* head) {$/;" f +flags SRC/include/ezxml.h /^ short flags; \/* additional information *\/$/;" m struct:ezxml +format SRC/include/physical_types.h /^ enum e_pin_to_pin_annotation_format format;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_format +frac_cb SRC/include/physical_types.h /^ float frac_cb;$/;" m struct:s_segment_inf +frac_lut SRC/fpga_spice_include/spice_types.h /^ boolean frac_lut;$/;" m struct:s_spice_model_lut +frac_sb SRC/include/physical_types.h /^ float frac_sb;$/;" m struct:s_segment_inf +free_chunk_memory SRC/util.c /^void free_chunk_memory(t_chunk *chunk_info) {$/;" f +free_int_list SRC/util.c /^void free_int_list(t_linked_int ** int_list_head_ptr) {$/;" f +free_ivec_matrix SRC/util.c /^void free_ivec_matrix(struct s_ivec **ivec_matrix, int nrmin, int nrmax,$/;" f +free_ivec_matrix3 SRC/util.c /^void free_ivec_matrix3(struct s_ivec ***ivec_matrix3, int nrmin, int nrmax,$/;" f +free_ivec_vector SRC/util.c /^void free_ivec_vector(struct s_ivec *ivec_vector, int nrmin, int nrmax) {$/;" f +free_llist SRC/linkedlist.c /^void free_llist(t_llist* head) {$/;" f +free_matrix SRC/util.c /^void free_matrix(void *vptr, int nrmin, int nrmax, int ncmin, size_t elsize) {$/;" f +free_matrix3 SRC/util.c /^void free_matrix3(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f +free_matrix4 SRC/util.c /^void free_matrix4(void *vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f +freq SRC/fpga_spice_include/spice_types.h /^ float freq; $/;" m struct:s_spice_net_info +frequency SRC/include/physical_types.h /^ int frequency;$/;" m struct:s_segment_inf +from_block SRC/include/cad_types.h /^ t_pack_pattern_block *from_block;$/;" m struct:s_pack_pattern_connections +from_pin SRC/include/cad_types.h /^ t_pb_graph_pin *from_pin;$/;" m struct:s_pack_pattern_connections +from_pin SRC/include/physical_types.h /^ char *from_pin;$/;" m struct:s_direct_inf +from_port SRC/fpga_spice_include/spice_types.h /^ t_spice_model_port* from_port;$/;" m struct:s_spice_model_tedge +from_port_pin_number SRC/fpga_spice_include/spice_types.h /^ int from_port_pin_number;$/;" m struct:s_spice_model_tedge +gate_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_gate* gate_info;$/;" m struct:s_spice_model_design_tech_info +get_opposite SRC/sides.cpp /^enum e_side Side::get_opposite() const {$/;" f class:Side +get_rotate_clockwise SRC/sides.cpp /^enum e_side Side::get_rotate_clockwise() const {$/;" f class:Side +get_rotate_counterclockwise SRC/sides.cpp /^enum e_side Side::get_rotate_counterclockwise() const {$/;" f class:Side +get_side SRC/sides.cpp /^enum e_side Side::get_side() const { $/;" f class:Side +grid_conf_bits_lsb SRC/fpga_spice_include/spice_types.h /^ int** grid_conf_bits_lsb;$/;" m struct:s_sram_orgz_info +grid_conf_bits_msb SRC/fpga_spice_include/spice_types.h /^ int** grid_conf_bits_msb;$/;" m struct:s_sram_orgz_info +grid_index_high SRC/fpga_spice_include/spice_types.h /^ int** grid_index_high;$/;" m struct:s_spice_model +grid_index_low SRC/fpga_spice_include/spice_types.h /^ int** grid_index_low;$/;" m struct:s_spice_model +grid_loc_def SRC/include/physical_types.h /^ struct s_grid_loc_def *grid_loc_def; \/* [0..num_def-1] *\/$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_grid_loc_def +grid_loc_type SRC/include/physical_types.h /^ enum e_grid_loc_type grid_loc_type;$/;" m struct:s_grid_loc_def typeref:enum:s_grid_loc_def::e_grid_loc_type +grid_logic_tile_area SRC/include/physical_types.h /^ float grid_logic_tile_area;$/;" m struct:s_arch +grid_nx SRC/fpga_spice_include/spice_types.h /^ int grid_nx; \/* grid size *\/ $/;" m struct:s_sram_orgz_info +grid_ny SRC/fpga_spice_include/spice_types.h /^ int grid_ny;$/;" m struct:s_sram_orgz_info +grid_reserved_conf_bits SRC/fpga_spice_include/spice_types.h /^ int** grid_reserved_conf_bits;$/;" m struct:s_sram_orgz_info +height SRC/include/physical_types.h /^ int height;$/;" m struct:s_type_descriptor +idle_mode_name SRC/include/physical_types.h /^ char* idle_mode_name;$/;" m struct:s_pb_type +in_port_name SRC/fpga_spice_include/spice_types.h /^ char* in_port_name;$/;" m struct:s_spice_model_delay_info +include_netlist SRC/fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlist;$/;" m struct:s_spice_model +include_netlists SRC/fpga_spice_include/spice_types.h /^ t_spice_model_netlist* include_netlists; $/;" m struct:s_spice +included SRC/fpga_spice_include/spice_types.h /^ int included;$/;" m struct:s_spice_model_netlist +incremental_cost SRC/include/cad_types.h /^ float incremental_cost; \/* cost dependant on current status of packing *\/$/;" m struct:s_cluster_placement_primitive +index SRC/fpga_spice_include/spice_types.h /^ int index;$/;" m struct:s_conf_bit_info +index SRC/include/cad_types.h /^ int index; \/* array index for pattern*\/$/;" m struct:s_pack_patterns +index SRC/include/logic_types.h /^ int index; \/* indexing for array look-up *\/$/;" m struct:s_model_ports +index SRC/include/logic_types.h /^ int index;$/;" m struct:s_model +index SRC/include/physical_types.h /^ int index; \/* index of type descriptor in array (allows for index referencing) *\/$/;" m struct:s_type_descriptor +index SRC/include/physical_types.h /^ int index;$/;" m struct:s_mode +index SRC/include/physical_types.h /^ int index;$/;" m struct:s_port +index_in_top_tb SRC/fpga_spice_include/spice_types.h /^ int index_in_top_tb;$/;" m struct:s_conf_bit_info +infer_annotations SRC/include/physical_types.h /^ boolean infer_annotations;$/;" m struct:s_interconnect +infer_pattern SRC/include/physical_types.h /^ boolean infer_pattern; \/*If TRUE, infer pattern based on patterns connected to it*\/$/;" m struct:s_pb_graph_edge +init_arch_mrfpga SRC/read_xml_mrfpga.c /^void init_arch_mrfpga(t_arch_mrfpga* arch_mrfpga) {$/;" f +init_buffer_inf SRC/read_xml_mrfpga.c /^void init_buffer_inf(t_buffer_inf* buffer_inf) {$/;" f +init_memristor_inf SRC/read_xml_mrfpga.c /^void init_memristor_inf(t_memristor_inf* memristor_inf) {$/;" f +init_val SRC/fpga_spice_include/spice_types.h /^ int init_val;$/;" m struct:s_spice_net_info +inport_link_pin SRC/include/cad_types.h /^ int inport_link_pin; \/* applicable pin of chain input port *\/$/;" m struct:s_model_chain_pattern +input_buffer SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* input_buffer;$/;" m struct:s_spice_model +input_edges SRC/include/physical_types.h /^ struct s_pb_graph_edge** input_edges; \/* [0..num_input_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge +input_level SRC/fpga_spice_include/spice_types.h /^ int* input_level; \/* [0...num_input] *\/$/;" m struct:s_spice_mux_arch +input_link_port SRC/include/cad_types.h /^ t_model_ports *input_link_port; \/* pointer to port of chain input *\/$/;" m struct:s_model_chain_pattern +input_offset SRC/fpga_spice_include/spice_types.h /^ int* input_offset; \/* [0...num_input] *\/ $/;" m struct:s_spice_mux_arch +input_pin_class_size SRC/include/physical_types.h /^ int *input_pin_class_size; \/* Stores the number of pins that belong to a particular input pin class *\/$/;" m struct:s_pb_graph_node +input_pins SRC/include/physical_types.h /^ char * input_pins;$/;" m struct:s_pin_to_pin_annotation +input_pins SRC/include/physical_types.h /^ struct s_pb_graph_pin *** input_pins; \/\/ [0..num_input_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin +input_pins SRC/include/physical_types.h /^ t_pb_graph_pin **input_pins; \/* [0..num_input_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node +input_pins SRC/include/physical_types.h /^ t_pb_graph_pin **input_pins;$/;" m struct:s_pb_graph_edge +input_ports_eq_auto_detect SRC/include/physical_types.h /^ boolean input_ports_eq_auto_detect;$/;" m struct:s_type_descriptor +input_slew_fall_time SRC/fpga_spice_include/spice_types.h /^ float input_slew_fall_time; $/;" m struct:s_spice_stimulate_params +input_slew_fall_type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_fall_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +input_slew_rise_time SRC/fpga_spice_include/spice_types.h /^ float input_slew_rise_time; $/;" m struct:s_spice_stimulate_params +input_slew_rise_type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_accuracy_type input_slew_rise_type;$/;" m struct:s_spice_stimulate_params typeref:enum:s_spice_stimulate_params::e_spice_accuracy_type +input_string SRC/include/physical_types.h /^ char *input_string;$/;" m struct:s_interconnect +input_thres_pct_fall SRC/fpga_spice_include/spice_types.h /^ float input_thres_pct_fall;$/;" m struct:s_spice_meas_params +input_thres_pct_rise SRC/fpga_spice_include/spice_types.h /^ float input_thres_pct_rise;$/;" m struct:s_spice_meas_params +inputs SRC/include/logic_types.h /^ t_model_ports *inputs; \/* linked list of input\/clock ports *\/$/;" m struct:s_model +insert_in_int_list SRC/util.c /^insert_in_int_list(t_linked_int * head, int data,$/;" f +insert_in_vptr_list SRC/util.c /^insert_in_vptr_list(struct s_linked_vptr *head, void *vptr_to_add) {$/;" f +insert_llist_node SRC/linkedlist.c /^t_llist* insert_llist_node(t_llist* cur) {$/;" f +insert_llist_node_before_head SRC/linkedlist.c /^t_llist* insert_llist_node_before_head(t_llist* old_head) {$/;" f +insert_node_to_int_list SRC/util.c /^insert_node_to_int_list(struct s_linked_int *head, int int_to_add) {$/;" f +instances SRC/include/logic_types.h /^ void *instances;$/;" m struct:s_model +interconnect SRC/include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_interconnect_pins +interconnect SRC/include/physical_types.h /^ t_interconnect * interconnect;$/;" m struct:s_pb_graph_edge +interconnect SRC/include/physical_types.h /^ t_interconnect *interconnect;$/;" m struct:s_mode +interconnect_pins SRC/include/physical_types.h /^ t_interconnect_pins ** interconnect_pins; \/* [0..num_modes-1][0..num_interconnect_in_mode] *\/$/;" m struct:s_pb_graph_node +interconnect_power SRC/include/physical_types.h /^ t_interconnect_power * interconnect_power;$/;" m struct:s_interconnect +inv_prefix SRC/fpga_spice_include/spice_types.h /^ char* inv_prefix; $/;" m struct:s_spice_model_port +inv_spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* inv_spice_model;$/;" m struct:s_spice_model_port +inv_spice_model_name SRC/fpga_spice_include/spice_types.h /^ char* inv_spice_model_name;$/;" m struct:s_spice_model_port +io_vdd SRC/fpga_spice_include/spice_types.h /^ float io_vdd;$/;" m struct:s_spice_tech_lib +ipin_mux_trans_size SRC/include/physical_types.h /^ float ipin_mux_trans_size;$/;" m struct:s_arch +ipow SRC/util.c /^int ipow(int base, int exp) {$/;" f +is_Fc_frac SRC/include/physical_types.h /^ boolean *is_Fc_frac; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +is_Fc_full_flex SRC/include/physical_types.h /^ boolean *is_Fc_full_flex; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +is_accurate SRC/include/arch_types_mrfpga.h /^ boolean is_accurate;$/;" m struct:s_arch_mrfpga +is_block_optional SRC/include/cad_types.h /^ boolean *is_block_optional; \/* [0..num_blocks-1] is the block_id in this pattern mandatory or optional to form a molecule *\/$/;" m struct:s_pack_patterns +is_chain SRC/include/cad_types.h /^ boolean is_chain; \/* Does this pattern chain across logic blocks *\/$/;" m struct:s_pack_patterns +is_clock SRC/include/logic_types.h /^ boolean is_clock; \/* clock? *\/$/;" m struct:s_model_ports +is_clock SRC/include/physical_types.h /^ boolean is_clock;$/;" m struct:s_port +is_config_enable SRC/fpga_spice_include/spice_types.h /^ boolean is_config_enable;$/;" m struct:s_spice_model_port +is_default SRC/fpga_spice_include/spice_types.h /^ int is_default;$/;" m struct:s_spice_model +is_disabled SRC/include/physical_types.h /^ boolean is_disabled;$/;" m struct:s_pb_graph_edge +is_forced_connection SRC/include/physical_types.h /^ boolean is_forced_connection; \/* This output pin connects to one and only one input pin *\/$/;" m struct:s_pb_graph_pin +is_global SRC/fpga_spice_include/spice_types.h /^ boolean is_global;$/;" m struct:s_spice_model_port +is_global_pin SRC/include/physical_types.h /^ boolean *is_global_pin; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +is_isolation SRC/include/arch_types_mrfpga.h /^ boolean is_isolation;$/;" m struct:s_arch_mrfpga +is_junction SRC/include/arch_types_mrfpga.h /^ boolean is_junction;$/;" m struct:s_arch_mrfpga +is_mrFPGA SRC/include/arch_types_mrfpga.h /^ boolean is_mrFPGA;$/;" m struct:s_arch_mrfpga +is_non_clock_global SRC/include/logic_types.h /^ boolean is_non_clock_global; \/* not a clock but is a special, global, control signal (eg global asynchronous reset, etc) *\/$/;" m struct:s_model_ports +is_non_clock_global SRC/include/physical_types.h /^ boolean is_non_clock_global;$/;" m struct:s_port +is_opin_cblock_defined SRC/include/arch_types_mrfpga.h /^ int is_opin_cblock_defined;$/;" m struct:s_arch_mrfpga +is_prog SRC/fpga_spice_include/spice_types.h /^ boolean is_prog;$/;" m struct:s_spice_model_port +is_reset SRC/fpga_spice_include/spice_types.h /^ boolean is_reset;$/;" m struct:s_spice_model_port +is_set SRC/fpga_spice_include/spice_types.h /^ boolean is_set;$/;" m struct:s_spice_model_port +is_show_pass_trans SRC/include/arch_types_mrfpga.h /^ boolean is_show_pass_trans;$/;" m struct:s_arch_mrfpga +is_show_sram SRC/include/arch_types_mrfpga.h /^ boolean is_show_sram;$/;" m struct:s_arch_mrfpga +is_stack SRC/include/arch_types_mrfpga.h /^ boolean is_stack;$/;" m struct:s_arch_mrfpga +is_wire_buffer SRC/include/arch_types_mrfpga.h /^ boolean is_wire_buffer;$/;" m struct:s_arch_mrfpga +leakage SRC/include/physical_types.h /^ float leakage;$/;" m struct:s_power_usage +leakage_default_mode SRC/include/physical_types.h /^ int leakage_default_mode; \/* Default mode for leakage analysis, if block has no set mode *\/$/;" m struct:s_pb_type_power +len SRC/include/ezxml.h /^ size_t len; \/* length of allocated memory for mmap, -1 for malloc *\/$/;" m struct:ezxml_root +length SRC/include/physical_types.h /^ int length;$/;" m struct:s_segment_inf +level SRC/fpga_spice_include/spice_types.h /^ int level;$/;" m struct:s_spice_model_wire_param +lib_name SRC/fpga_spice_include/spice_types.h /^ char* lib_name; $/;" m struct:s_spice_model_port +limit_value SRC/util.c /^int limit_value(int cur, int max, const char *name) {$/;" f +line SRC/include/ezxml.h /^ int line;$/;" m struct:ezxml +line SRC/include/physical_types.h /^ int line;$/;" m struct:s_direct_inf +line_num SRC/include/physical_types.h /^ int line_num; \/* Interconnect is processed later, need to know what line number it messed up on to give proper error message *\/$/;" m struct:s_interconnect +line_num SRC/include/physical_types.h /^ int line_num; \/* used to report what line number this annotation is found in architecture file *\/$/;" m struct:s_pin_to_pin_annotation +list SRC/include/util.h /^ int *list;$/;" m struct:s_ivec +list_of_connectable_input_pin_ptrs SRC/include/physical_types.h /^ struct s_pb_graph_pin ***list_of_connectable_input_pin_ptrs; \/* [0..depth-1][0..num_connectable_primtive_input_pins-1] what input pins this output can connect to without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin +local_interc_factor SRC/include/physical_types.h /^ float local_interc_factor;$/;" m struct:s_power_arch +location_map SRC/fpga_spice_include/spice_types.h /^ char* location_map;$/;" m struct:s_spice_model_buffer +logical_effort_factor SRC/include/physical_types.h /^ float logical_effort_factor;$/;" m struct:s_power_arch +longline SRC/include/physical_types.h /^ boolean longline;$/;" m struct:s_segment_inf +loop_breaker_delay_after_max SRC/include/physical_types.h /^ char *loop_breaker_delay_after_max;$/;" m struct:s_interconnect +loop_breaker_delay_after_max SRC/include/physical_types.h /^ char* loop_breaker_delay_after_max;$/;" m struct:s_pb_graph_edge +loop_breaker_delay_after_min SRC/include/physical_types.h /^ char *loop_breaker_delay_after_min;$/;" m struct:s_interconnect +loop_breaker_delay_after_min SRC/include/physical_types.h /^ char* loop_breaker_delay_after_min;$/;" m struct:s_pb_graph_edge +loop_breaker_delay_before_max SRC/include/physical_types.h /^ char *loop_breaker_delay_before_max;$/;" m struct:s_interconnect +loop_breaker_delay_before_max SRC/include/physical_types.h /^ char* loop_breaker_delay_before_max;$/;" m struct:s_pb_graph_edge +loop_breaker_delay_before_min SRC/include/physical_types.h /^ char *loop_breaker_delay_before_min;$/;" m struct:s_interconnect +loop_breaker_delay_before_min SRC/include/physical_types.h /^ char* loop_breaker_delay_before_min;$/;" m struct:s_pb_graph_edge +loop_breaker_string SRC/include/physical_types.h /^ char *loop_breaker_string;$/;" m struct:s_interconnect +lut_frac_level SRC/fpga_spice_include/spice_types.h /^ int lut_frac_level;$/;" m struct:s_spice_model_port +lut_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_lut* lut_info;$/;" m struct:s_spice_model_design_tech_info +lut_input_buffer SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_input_buffer;$/;" m struct:s_spice_model +lut_input_inverter SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_input_inverter;$/;" m struct:s_spice_model +lut_intermediate_buffer SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* lut_intermediate_buffer;$/;" m struct:s_spice_model +lut_output_mask SRC/fpga_spice_include/spice_types.h /^ int* lut_output_mask;$/;" m struct:s_spice_model_port +m SRC/include/ezxml.h /^ char *m; \/* original xml string *\/$/;" m struct:ezxml_root +main SRC/ezxml.c /^main(int argc,$/;" f +main SRC/main.c /^int main(int argc, char **argv) {$/;" f +main_best_buffer_list SRC/include/arch_types_mrfpga.h /^ t_linked_int* main_best_buffer_list;$/;" m struct:s_arch_mrfpga +max_internal_delay SRC/include/physical_types.h /^ float max_internal_delay;$/;" m struct:s_pb_type +max_pins_per_side SRC/include/arch_types_mrfpga.h /^ int max_pins_per_side;$/;" m struct:s_arch_mrfpga +mc_params SRC/fpga_spice_include/spice_types.h /^ t_spice_mc_params mc_params;$/;" m struct:s_spice_params +mc_sim SRC/fpga_spice_include/spice_types.h /^ boolean mc_sim;$/;" m struct:s_spice_mc_params +meas_params SRC/fpga_spice_include/spice_types.h /^ t_spice_meas_params meas_params;$/;" m struct:s_spice_params +mem_avail SRC/include/util.h /^ int mem_avail; \/* number of bytes left in the current chunk *\/$/;" m struct:s_chunk +mem_bank_info SRC/fpga_spice_include/spice_types.h /^ t_mem_bank_info* mem_bank_info; \/* Only be allocated when orgz type is memory bank *\/$/;" m struct:s_sram_orgz_info +mem_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_mem_bank_info +mem_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_scff_info +mem_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* mem_model; \/* SPICE model of a memory bit *\/$/;" m struct:s_standalone_sram_info +memristor_inf SRC/include/arch_types_mrfpga.h /^ t_memristor_inf memristor_inf;$/;" m struct:s_arch_mrfpga +messagelogger SRC/include/util.h /^typedef unsigned char (*messagelogger)( TIO_MessageMode_t messageMode,$/;" t +min_size SRC/include/logic_types.h /^ int min_size; \/* minimum number of pins *\/$/;" m struct:s_model_ports +min_width SRC/fpga_spice_include/spice_types.h /^ float min_width;$/;" m struct:s_spice_transistor_type +mode_bits SRC/include/physical_types.h /^ char* mode_bits; \/* Mode bits to select *\/$/;" m struct:s_pb_type +mode_power SRC/include/physical_types.h /^ t_mode_power * mode_power;$/;" m struct:s_mode +mode_select SRC/fpga_spice_include/spice_types.h /^ boolean mode_select;$/;" m struct:s_spice_model_port +model SRC/include/cad_types.h /^ t_model *model; \/* block associated with chain *\/$/;" m struct:s_model_chain_pattern +model SRC/include/physical_types.h /^ t_model *model;$/;" m struct:s_pb_type +model_library SRC/include/physical_types.h /^ t_model *model_library;$/;" m struct:s_arch +model_name SRC/fpga_spice_include/spice_types.h /^ char* model_name;$/;" m struct:s_spice_transistor_type +model_netlist SRC/fpga_spice_include/spice_types.h /^ char* model_netlist; \/* SPICE netlist provided by user *\/$/;" m struct:s_spice_model +model_port SRC/include/physical_types.h /^ t_model_ports *model_port;$/;" m struct:s_port +model_ref SRC/fpga_spice_include/spice_types.h /^ char* model_ref;$/;" m struct:s_spice_tech_lib +models SRC/include/physical_types.h /^ t_model *models;$/;" m struct:s_arch +modes SRC/include/physical_types.h /^ t_mode *modes; \/* [0..num_modes-1] *\/$/;" m struct:s_pb_type +mux_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_mux* mux_info;$/;" m struct:s_spice_model_design_tech_info +mux_num_level SRC/fpga_spice_include/spice_types.h /^ int mux_num_level;$/;" m struct:s_spice_model_mux +mux_trans_size SRC/include/physical_types.h /^ float mux_trans_size;$/;" m struct:s_switch_inf +mux_transistor_size SRC/include/physical_types.h /^ float mux_transistor_size;$/;" m struct:s_power_arch +my_atoi SRC/util.c /^int my_atoi(const char *str) {$/;" f +my_calloc SRC/util.c /^my_calloc(size_t nelem, size_t size) {$/;" f +my_chunk_malloc SRC/util.c /^my_chunk_malloc(size_t size, t_chunk *chunk_info) {$/;" f +my_fgets SRC/util.c /^my_fgets(char *buf, int max_size, FILE * fp) {$/;" f +my_fopen SRC/util.c /^my_fopen(const char *fname, const char *flag, int prompt) {$/;" f +my_frand SRC/util.c /^float my_frand(void) {$/;" f +my_free SRC/read_xml_spice_util.c /^void my_free(void* ptr) {$/;" f +my_irand SRC/util.c /^int my_irand(int imax) {$/;" f +my_malloc SRC/util.c /^my_malloc(size_t size) {$/;" f +my_realloc SRC/util.c /^my_realloc(void *ptr, size_t size) {$/;" f +my_srandom SRC/util.c /^void my_srandom(int seed) {$/;" f +my_strdup SRC/util.c /^my_strdup(const char *str) {$/;" f +my_strncpy SRC/util.c /^my_strncpy(char *dest, const char *src, size_t size) {$/;" f +my_strtok SRC/util.c /^my_strtok(char *ptr, const char *tokens, FILE * fp, char *buf) {$/;" f +name SRC/fpga_spice_include/spice_types.h /^ char* name;$/;" m struct:s_spice_model +name SRC/include/cad_types.h /^ char *name; \/* name of this chain of logic *\/$/;" m struct:s_model_chain_pattern +name SRC/include/cad_types.h /^ char *name; \/* name of this logic model pattern *\/$/;" m struct:s_pack_patterns +name SRC/include/ezxml.h /^ char *name; \/* tag name *\/$/;" m struct:ezxml +name SRC/include/logic_types.h /^ char *name; \/* name of this logic model *\/$/;" m struct:s_model +name SRC/include/logic_types.h /^ char *name; \/* name of this port *\/$/;" m struct:s_model_ports +name SRC/include/physical_types.h /^ char *name;$/;" m struct:s_direct_inf +name SRC/include/physical_types.h /^ char *name;$/;" m struct:s_interconnect +name SRC/include/physical_types.h /^ char *name;$/;" m struct:s_switch_inf +name SRC/include/physical_types.h /^ char *name;$/;" m struct:s_type_descriptor +name SRC/include/physical_types.h /^ char* name;$/;" m struct:s_mode +name SRC/include/physical_types.h /^ char* name;$/;" m struct:s_pb_type +name SRC/include/physical_types.h /^ char* name;$/;" m struct:s_port +name_mux SRC/include/physical_types.h /^ char* name_mux;$/;" m struct:s_pb_graph_pin +nb_mux SRC/include/physical_types.h /^ int nb_mux;$/;" m struct:s_pb_graph_edge +nb_pin SRC/include/physical_types.h /^ int nb_pin;$/;" m struct:s_pb_graph_edge +nelem SRC/include/util.h /^ int nelem;$/;" m struct:s_ivec +next SRC/fpga_spice_include/linkedlist.h /^ t_llist* next;$/;" m struct:s_llist +next SRC/include/cad_types.h /^ struct s_model_chain_pattern *next; \/* next chain (linked list) *\/$/;" m struct:s_model_chain_pattern typeref:struct:s_model_chain_pattern::s_model_chain_pattern +next SRC/include/cad_types.h /^ struct s_pack_pattern_connections *next;$/;" m struct:s_pack_pattern_connections typeref:struct:s_pack_pattern_connections::s_pack_pattern_connections +next SRC/include/ezxml.h /^ ezxml_t next; \/* next tag with same name in this section at this depth *\/$/;" m struct:ezxml +next SRC/include/logic_types.h /^ struct s_model *next; \/* next model (linked list) *\/$/;" m struct:s_model typeref:struct:s_model::s_model +next SRC/include/logic_types.h /^ struct s_model_ports *next; \/* next port *\/$/;" m struct:s_model_ports typeref:struct:s_model_ports::s_model_ports +next SRC/include/util.h /^ struct s_linked_int *next;$/;" m struct:s_linked_int typeref:struct:s_linked_int::s_linked_int +next SRC/include/util.h /^ struct s_linked_vptr *next;$/;" m struct:s_linked_vptr typeref:struct:s_linked_vptr::s_linked_vptr +next_mem_loc_ptr SRC/include/util.h /^ char *next_mem_loc_ptr;\/* pointer to the first available (free) *$/;" m struct:s_chunk +next_primitive SRC/include/cad_types.h /^ struct s_cluster_placement_primitive *next_primitive;$/;" m struct:s_cluster_placement_primitive typeref:struct:s_cluster_placement_primitive::s_cluster_placement_primitive +nint SRC/include/util.h 24;" d +nmos_size SRC/fpga_spice_include/spice_types.h /^ float nmos_size;$/;" m struct:s_spice_model_pass_gate_logic +nominal_vdd SRC/fpga_spice_include/spice_types.h /^ float nominal_vdd;$/;" m struct:s_spice_tech_lib +num_annotations SRC/include/physical_types.h /^ int num_annotations;$/;" m struct:s_interconnect +num_annotations SRC/include/physical_types.h /^ int num_annotations;$/;" m struct:s_pb_type +num_bl SRC/fpga_spice_include/spice_types.h /^ int num_bl; \/* Number of Bit Lines in total *\/$/;" m struct:s_mem_bank_info +num_blocks SRC/include/cad_types.h /^ int num_blocks; \/* number of blocks in pattern *\/$/;" m struct:s_pack_patterns +num_cb_switch SRC/include/physical_types.h /^ int num_cb_switch;$/;" m struct:s_arch +num_class SRC/include/physical_types.h /^ int num_class;$/;" m struct:s_type_descriptor +num_clock_pins SRC/include/physical_types.h /^ int *num_clock_pins; \/* [0..num_clock_ports - 1] *\/$/;" m struct:s_pb_graph_node +num_clock_pins SRC/include/physical_types.h /^ int num_clock_pins;$/;" m struct:s_pb_type +num_clock_ports SRC/include/physical_types.h /^ int num_clock_ports;$/;" m struct:s_pb_graph_node +num_clocks SRC/fpga_spice_include/spice_types.h /^ int num_clocks;$/;" m struct:s_spice_stimulate_params +num_connectable_primtive_input_pins SRC/include/physical_types.h /^ int *num_connectable_primtive_input_pins; \/* [0..depth-1] number of input pins that this output pin can reach without exiting cluster at given depth *\/$/;" m struct:s_pb_graph_pin +num_data_input SRC/fpga_spice_include/spice_types.h /^ int num_data_input; \/* Inputs for multiplexing datapath signals*\/ $/;" m struct:s_spice_mux_arch +num_delay_info SRC/fpga_spice_include/spice_types.h /^ int num_delay_info;$/;" m struct:s_spice_model +num_directs SRC/include/physical_types.h /^ int num_directs;$/;" m struct:s_arch +num_drivers SRC/include/physical_types.h /^ int num_drivers;$/;" m struct:s_type_descriptor +num_global_clocks SRC/include/physical_types.h /^ int num_global_clocks;$/;" m struct:s_clock_arch +num_grid_loc_def SRC/include/physical_types.h /^ int num_grid_loc_def;$/;" m struct:s_type_descriptor +num_include_netlist SRC/fpga_spice_include/spice_types.h /^ int num_include_netlist;$/;" m struct:s_spice +num_input SRC/fpga_spice_include/spice_types.h /^ int num_input; \/* All Inputs including those connect to constant generator *\/$/;" m struct:s_spice_mux_arch +num_input_basis SRC/fpga_spice_include/spice_types.h /^ int num_input_basis;$/;" m struct:s_spice_mux_arch +num_input_edges SRC/include/physical_types.h /^ int num_input_edges;$/;" m struct:s_pb_graph_pin +num_input_last_level SRC/fpga_spice_include/spice_types.h /^ int num_input_last_level;$/;" m struct:s_spice_mux_arch +num_input_per_level SRC/fpga_spice_include/spice_types.h /^ int* num_input_per_level; \/* [0...num_level] *\/$/;" m struct:s_spice_mux_arch +num_input_pin_class SRC/include/physical_types.h /^ int num_input_pin_class; \/* number of pin classes that this input pb_graph_node has *\/$/;" m struct:s_pb_graph_node +num_input_pins SRC/include/physical_types.h /^ int *num_input_pins; \/* [0..num_input_ports - 1] *\/$/;" m struct:s_pb_graph_node +num_input_pins SRC/include/physical_types.h /^ int num_input_pins; \/* inputs not including clock pins *\/$/;" m struct:s_pb_type +num_input_pins SRC/include/physical_types.h /^ int num_input_pins;$/;" m struct:s_pb_graph_edge +num_input_ports SRC/include/physical_types.h /^ int num_input_ports;$/;" m struct:s_interconnect_power +num_input_ports SRC/include/physical_types.h /^ int num_input_ports;$/;" m struct:s_pb_graph_node +num_interconnect SRC/include/physical_types.h /^ int num_interconnect;$/;" m struct:s_mode +num_level SRC/fpga_spice_include/spice_types.h /^ int num_level;$/;" m struct:s_spice_mux_arch +num_mc_points SRC/fpga_spice_include/spice_types.h /^ int num_mc_points;$/;" m struct:s_spice_mc_params +num_mem_bit SRC/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_mem_bank_info +num_mem_bit SRC/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_scff_info +num_mem_bit SRC/fpga_spice_include/spice_types.h /^ int num_mem_bit; \/* Number of memory bits in total *\/$/;" m struct:s_standalone_sram_info +num_modes SRC/include/physical_types.h /^ int num_modes;$/;" m struct:s_pb_type +num_mux SRC/include/physical_types.h /^ int num_mux;$/;" m struct:s_interconnect +num_normal_switch SRC/include/arch_types_mrfpga.h /^ short num_normal_switch;$/;" m struct:s_arch_mrfpga +num_output_edges SRC/include/physical_types.h /^ int num_output_edges;$/;" m struct:s_pb_graph_pin +num_output_pin_class SRC/include/physical_types.h /^ int num_output_pin_class; \/* number of output pin classes that this pb_graph_node has *\/$/;" m struct:s_pb_graph_node +num_output_pins SRC/include/physical_types.h /^ int *num_output_pins; \/* [0..num_output_ports - 1] *\/$/;" m struct:s_pb_graph_node +num_output_pins SRC/include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_graph_edge +num_output_pins SRC/include/physical_types.h /^ int num_output_pins;$/;" m struct:s_pb_type +num_output_ports SRC/include/physical_types.h /^ int num_output_ports;$/;" m struct:s_interconnect_power +num_output_ports SRC/include/physical_types.h /^ int num_output_ports;$/;" m struct:s_pb_graph_node +num_pack_patterns SRC/include/physical_types.h /^ int num_pack_patterns;$/;" m struct:s_pb_graph_edge +num_pb SRC/include/physical_types.h /^ int num_pb;$/;" m struct:s_pb_type +num_pb_type_children SRC/include/physical_types.h /^ int num_pb_type_children;$/;" m struct:s_mode +num_pin_loc_assignments SRC/include/physical_types.h /^ int **num_pin_loc_assignments; \/* [0..height-1][0..3] *\/$/;" m struct:s_type_descriptor +num_pin_timing SRC/include/physical_types.h /^ int num_pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin +num_pins SRC/include/physical_types.h /^ int num_pins;$/;" m struct:s_class +num_pins SRC/include/physical_types.h /^ int num_pins;$/;" m struct:s_port +num_pins SRC/include/physical_types.h /^ int num_pins;$/;" m struct:s_type_descriptor +num_pins_per_port SRC/include/physical_types.h /^ int num_pins_per_port;$/;" m struct:s_interconnect_power +num_port SRC/fpga_spice_include/spice_types.h /^ int num_port;$/;" m struct:s_spice_model +num_ports SRC/include/physical_types.h /^ int num_ports;$/;" m struct:s_pb_type +num_receivers SRC/include/physical_types.h /^ int num_receivers;$/;" m struct:s_type_descriptor +num_scff SRC/fpga_spice_include/spice_types.h /^ int num_scff; \/* Number of Scan-chain flip-flops *\/$/;" m struct:s_scff_info +num_segments SRC/include/physical_types.h /^ int num_segments;$/;" m struct:s_arch +num_sigma SRC/fpga_spice_include/spice_types.h /^ int num_sigma;$/;" m struct:s_spice_mc_variation_params +num_sim_clock_cycles SRC/fpga_spice_include/spice_types.h /^ int num_sim_clock_cycles;$/;" m struct:s_spicetb_info +num_spice_model SRC/fpga_spice_include/spice_types.h /^ int num_spice_model;$/;" m struct:s_spice +num_sram SRC/fpga_spice_include/spice_types.h /^ int num_sram; \/* Number of SRAMs in total *\/$/;" m struct:s_standalone_sram_info +num_switches SRC/include/physical_types.h /^ int num_switches;$/;" m struct:s_arch +num_swseg_pattern SRC/include/physical_types.h /^ int num_swseg_pattern;$/;" m struct:s_arch +num_tedges SRC/fpga_spice_include/spice_types.h /^ int* num_tedges; \/* 1-D Array, show number of tedges of each pin *\/$/;" m struct:s_spice_model_port +num_transistor_type SRC/fpga_spice_include/spice_types.h /^ int num_transistor_type;$/;" m struct:s_spice_tech_lib +num_value_prop_pairs SRC/include/physical_types.h /^ int num_value_prop_pairs;$/;" m struct:s_pin_to_pin_annotation +num_wl SRC/fpga_spice_include/spice_types.h /^ int num_wl; \/* Number of Word Lines in total *\/$/;" m struct:s_mem_bank_info +off SRC/include/ezxml.h /^ size_t off; \/* tag offset from start of parent tag character content *\/$/;" m struct:ezxml +op_clock_freq SRC/fpga_spice_include/spice_types.h /^ float op_clock_freq; \/* Operation clock frequency*\/$/;" m struct:s_spice_stimulate_params +open SRC/ezxml.c 58;" d file: +opin_switch SRC/include/physical_types.h /^ short opin_switch;$/;" m struct:s_segment_inf +opin_to_cb SRC/include/physical_types.h /^ boolean opin_to_cb;$/;" m struct:s_type_descriptor +ordered SRC/include/ezxml.h /^ ezxml_t ordered; \/* next tag, same section and depth, in original order *\/$/;" m struct:ezxml +out_file_prefix SRC/util.c /^char *out_file_prefix = NULL;$/;" v +out_port_name SRC/fpga_spice_include/spice_types.h /^ char* out_port_name;$/;" m struct:s_spice_model_delay_info +outport_link_pin SRC/include/cad_types.h /^ int outport_link_pin; \/* applicable pin of chain output port *\/$/;" m struct:s_model_chain_pattern +output_buffer SRC/fpga_spice_include/spice_types.h /^ t_spice_model_buffer* output_buffer;$/;" m struct:s_spice_model +output_edges SRC/include/physical_types.h /^ struct s_pb_graph_edge** output_edges; \/* [0..num_output_edges] *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_edge +output_link_port SRC/include/cad_types.h /^ t_model_ports *output_link_port; \/* pointer to port of chain output *\/$/;" m struct:s_model_chain_pattern +output_pin_class_size SRC/include/physical_types.h /^ int *output_pin_class_size; \/* Stores the number of pins that belong to a particular output pin class *\/$/;" m struct:s_pb_graph_node +output_pins SRC/include/physical_types.h /^ char * output_pins;$/;" m struct:s_pin_to_pin_annotation +output_pins SRC/include/physical_types.h /^ struct s_pb_graph_pin *** output_pins; \/\/ [0..num_output_ports-1][0..num_pins_per_port-1]$/;" m struct:s_interconnect_pins typeref:struct:s_interconnect_pins::s_pb_graph_pin +output_pins SRC/include/physical_types.h /^ t_pb_graph_pin **output_pins; \/* [0..num_output_ports-1] [0..num_port_pins-1]*\/$/;" m struct:s_pb_graph_node +output_pins SRC/include/physical_types.h /^ t_pb_graph_pin **output_pins;$/;" m struct:s_pb_graph_edge +output_ports_eq_auto_detect SRC/include/physical_types.h /^ boolean output_ports_eq_auto_detect;$/;" m struct:s_type_descriptor +output_string SRC/include/physical_types.h /^ char *output_string;$/;" m struct:s_interconnect +output_thres_pct_fall SRC/fpga_spice_include/spice_types.h /^ float output_thres_pct_fall;$/;" m struct:s_spice_meas_params +output_thres_pct_rise SRC/fpga_spice_include/spice_types.h /^ float output_thres_pct_rise;$/;" m struct:s_spice_meas_params +outputs SRC/include/logic_types.h /^ t_model_ports *outputs; \/* linked list of output ports *\/$/;" m struct:s_model +pack_pattern_indices SRC/include/physical_types.h /^ int *pack_pattern_indices; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge +pack_pattern_names SRC/include/physical_types.h /^ char **pack_pattern_names; \/*[0..num_pack_patterns(of_edge)-1]*\/$/;" m struct:s_pb_graph_edge +parent SRC/include/ezxml.h /^ ezxml_t parent; \/* parent tag, NULL if current tag is root tag *\/$/;" m struct:ezxml +parent_mode SRC/include/physical_types.h /^ t_mode * parent_mode;$/;" m struct:s_interconnect +parent_mode SRC/include/physical_types.h /^ t_mode *parent_mode;$/;" m struct:s_pb_type +parent_mode_index SRC/include/physical_types.h /^ int parent_mode_index;$/;" m struct:s_interconnect +parent_node SRC/include/physical_types.h /^ struct s_pb_graph_node *parent_node;$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_node +parent_pb_graph_node SRC/include/physical_types.h /^ struct s_pb_graph_node *parent_pb_graph_node;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_graph_node +parent_pb_type SRC/include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type +parent_pb_type SRC/include/physical_types.h /^ struct s_pb_type *parent_pb_type;$/;" m struct:s_port typeref:struct:s_port::s_pb_type +parent_pin_class SRC/include/physical_types.h /^ int *parent_pin_class; \/* [0..depth-1] the grouping of pins that this particular pin belongs to *\/$/;" m struct:s_pb_graph_pin +parent_spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* parent_spice_model;$/;" m struct:s_conf_bit_info +parent_spice_model_index SRC/fpga_spice_include/spice_types.h /^ int parent_spice_model_index;$/;" m struct:s_conf_bit_info +pass_gate_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_info;$/;" m struct:s_spice_model_design_tech_info +pass_gate_logic SRC/fpga_spice_include/spice_types.h /^ t_spice_model_pass_gate_logic* pass_gate_logic;$/;" m struct:s_spice_model +path SRC/fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_model_netlist +path SRC/fpga_spice_include/spice_types.h /^ char* path;$/;" m struct:s_spice_tech_lib +pattern_index SRC/include/cad_types.h /^ int pattern_index; \/* index of pattern that this block is a part of *\/$/;" m struct:s_pack_pattern_block +pattern_length SRC/include/physical_types.h /^ int pattern_length;$/;" m struct:s_swseg_pattern_inf +patterns SRC/include/physical_types.h /^ boolean* patterns;$/;" m struct:s_swseg_pattern_inf +pb_graph_head SRC/include/physical_types.h /^ t_pb_graph_node *pb_graph_head;$/;" m struct:s_type_descriptor +pb_graph_node SRC/include/cad_types.h /^ t_pb_graph_node *pb_graph_node;$/;" m struct:s_cluster_placement_primitive +pb_node_power SRC/include/physical_types.h /^ t_pb_graph_node_power * pb_node_power;$/;" m struct:s_pb_graph_node +pb_type SRC/include/cad_types.h /^ const t_pb_type *pb_type; \/* pb_type that this block is an instance of *\/$/;" m struct:s_pack_pattern_block +pb_type SRC/include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_pb_graph_node typeref:struct:s_pb_graph_node::s_pb_type +pb_type SRC/include/physical_types.h /^ struct s_pb_type *pb_type;$/;" m struct:s_type_descriptor typeref:struct:s_type_descriptor::s_pb_type +pb_type_children SRC/include/physical_types.h /^ struct s_pb_type *pb_type_children; \/* [0..num_child_pb_types] *\/$/;" m struct:s_mode typeref:struct:s_mode::s_pb_type +pb_type_power SRC/include/physical_types.h /^ t_pb_type_power * pb_type_power;$/;" m struct:s_pb_type +pb_types SRC/include/logic_types.h /^ struct s_linked_vptr *pb_types; \/* Physical block types that implement this model *\/$/;" m struct:s_model typeref:struct:s_model::s_linked_vptr +peak SRC/include/physical_types.h /^ float peak;$/;" m struct:s_chan +period SRC/include/physical_types.h /^ float period; \/* Period of clock *\/$/;" m struct:s_clock_network +phy_mode_pin_rotate_offset_acc SRC/include/physical_types.h /^ int phy_mode_pin_rotate_offset_acc; \/* The pin number will rotate by an offset unit when mapping to physical modes *\/$/;" m struct:s_port +phy_pb_type SRC/include/physical_types.h /^ struct s_pb_type* phy_pb_type;$/;" m struct:s_pb_type typeref:struct:s_pb_type::s_pb_type +phy_pb_type_port SRC/include/physical_types.h /^ t_port* phy_pb_type_port;$/;" m struct:s_port +phy_pb_type_port_lsb SRC/include/physical_types.h /^ int phy_pb_type_port_lsb;$/;" m struct:s_port +phy_pb_type_port_msb SRC/include/physical_types.h /^ int phy_pb_type_port_msb;$/;" m struct:s_port +physical_mode_name SRC/include/physical_types.h /^ char* physical_mode_name;$/;" m struct:s_pb_type +physical_mode_num_conf_bits SRC/include/physical_types.h /^ int physical_mode_num_conf_bits;$/;" m struct:s_pb_type +physical_mode_num_iopads SRC/include/physical_types.h /^ int physical_mode_num_iopads;$/;" m struct:s_pb_type +physical_mode_num_reserved_conf_bits SRC/include/physical_types.h /^ int physical_mode_num_reserved_conf_bits;$/;" m struct:s_pb_type +physical_mode_pin SRC/include/physical_types.h /^ char* physical_mode_pin;$/;" m struct:s_port +physical_mode_pin_rotate_offset SRC/include/physical_types.h /^ int physical_mode_pin_rotate_offset; \/* The pin number will rotate by an offset unit when mapping to physical modes *\/$/;" m struct:s_port +physical_pb_graph_node SRC/include/physical_types.h /^ t_pb_graph_node* physical_pb_graph_node; \/* physical pb_graph_node *\/$/;" m struct:s_pb_graph_node +physical_pb_graph_pin SRC/include/physical_types.h /^ t_pb_graph_pin* physical_pb_graph_pin;$/;" m struct:s_pb_graph_pin +physical_pb_type_index_factor SRC/include/physical_types.h /^ float physical_pb_type_index_factor;$/;" m struct:s_pb_type +physical_pb_type_index_offset SRC/include/physical_types.h /^ int physical_pb_type_index_offset;$/;" m struct:s_pb_type +physical_pb_type_name SRC/include/physical_types.h /^ char* physical_pb_type_name;$/;" m struct:s_pb_type +pi SRC/include/ezxml.h /^ char ***pi; \/* processing instructions *\/$/;" m struct:ezxml_root +pin_class SRC/include/physical_types.h /^ int *pin_class; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +pin_class SRC/include/physical_types.h /^ int pin_class;$/;" m struct:s_pb_graph_pin +pin_count_in_cluster SRC/include/physical_types.h /^ int pin_count_in_cluster;$/;" m struct:s_pb_graph_pin +pin_height SRC/include/physical_types.h /^ int *pin_height; \/* [0..num_pins-1] *\/$/;" m struct:s_type_descriptor +pin_index_per_side SRC/include/physical_types.h /^ int* pin_index_per_side;$/;" m struct:s_type_descriptor +pin_loc_assignments SRC/include/physical_types.h /^ char ****pin_loc_assignments; \/* [0..height-1][0..3][0..num_tokens-1][0..string_name] *\/$/;" m struct:s_type_descriptor +pin_location_distribution SRC/include/physical_types.h /^ enum e_pin_location_distr pin_location_distribution;$/;" m struct:s_type_descriptor typeref:enum:s_type_descriptor::e_pin_location_distr +pin_number SRC/include/physical_types.h /^ int pin_number;$/;" m struct:s_pb_graph_pin +pin_power SRC/include/physical_types.h /^ t_pb_graph_pin_power * pin_power;$/;" m struct:s_pb_graph_pin +pin_ptc_to_side SRC/include/physical_types.h /^ int* pin_ptc_to_side;$/;" m struct:s_type_descriptor +pin_timing SRC/include/physical_types.h /^ struct s_pb_graph_pin** pin_timing; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin typeref:struct:s_pb_graph_pin::s_pb_graph_pin +pin_timing_del_max SRC/include/physical_types.h /^ float *pin_timing_del_max; \/* primitive ipin to opin timing *\/$/;" m struct:s_pb_graph_pin +pin_toggle_initialized SRC/include/physical_types.h /^ boolean pin_toggle_initialized;$/;" m struct:s_port_power +pinlist SRC/include/physical_types.h /^ int *pinlist; \/* [0..num_pins - 1] *\/$/;" m struct:s_class +pinloc SRC/include/physical_types.h /^ int ***pinloc; \/* [0..height-1][0..3][0..num_pins-1] *\/$/;" m struct:s_type_descriptor +placement_index SRC/include/physical_types.h /^ int placement_index;$/;" m struct:s_pb_graph_node +placement_index_in_top_node SRC/include/physical_types.h /^ int placement_index_in_top_node; \/* index at the top-level pb_graph node *\/$/;" m struct:s_pb_graph_node +pmos_size SRC/fpga_spice_include/spice_types.h /^ float pmos_size;$/;" m struct:s_spice_model_pass_gate_logic +pn_ratio SRC/fpga_spice_include/spice_types.h /^ float pn_ratio;$/;" m struct:s_spice_tech_lib +port SRC/include/physical_types.h /^ t_port *port;$/;" m struct:s_pb_graph_pin +port_class SRC/include/physical_types.h /^ char * port_class;$/;" m struct:s_port +port_index_by_type SRC/include/physical_types.h /^ int port_index_by_type;$/;" m struct:s_port +port_info_initialized SRC/include/physical_types.h /^ boolean port_info_initialized;$/;" m struct:s_interconnect_power +port_power SRC/include/physical_types.h /^ t_port_power * port_power;$/;" m struct:s_port +ports SRC/fpga_spice_include/spice_types.h /^ t_spice_model_port* ports;$/;" m struct:s_spice_model +ports SRC/include/physical_types.h /^ t_port *ports; \/* [0..num_ports] *\/$/;" m struct:s_pb_type +post SRC/fpga_spice_include/spice_types.h /^ int post;$/;" m struct:s_spice_params +power SRC/include/physical_types.h /^ t_power_arch * power;$/;" m struct:s_arch +power_buffer_size SRC/include/physical_types.h /^ float power_buffer_size;$/;" m struct:s_switch_inf +power_buffer_type SRC/include/physical_types.h /^ e_power_buffer_type power_buffer_type;$/;" m struct:s_switch_inf +power_gated SRC/fpga_spice_include/spice_types.h /^ boolean power_gated;$/;" m struct:s_spice_model_design_tech_info +power_method_inherited SRC/read_xml_arch_file.c /^e_power_estimation_method power_method_inherited($/;" f +power_usage SRC/include/physical_types.h /^ t_power_usage power_usage; \/* Power usage of this mode *\/$/;" m struct:s_mode_power +power_usage SRC/include/physical_types.h /^ t_power_usage power_usage; \/* Total power usage of this pb type *\/$/;" m struct:s_pb_type_power +power_usage SRC/include/physical_types.h /^ t_power_usage power_usage;$/;" m struct:s_interconnect_power +power_usage_bufs_wires SRC/include/physical_types.h /^ t_power_usage power_usage_bufs_wires; \/* Power dissipated in local buffers and wire switching (Subset of total power) *\/$/;" m struct:s_pb_type_power +prefix SRC/fpga_spice_include/spice_types.h /^ char* prefix; $/;" m struct:s_spice_model_port +prefix SRC/fpga_spice_include/spice_types.h /^ char* prefix; \/* Prefix when it show up in the spice netlist *\/$/;" m struct:s_spice_model +print_help SRC/main.c /^void print_help() {$/;" f +print_int_matrix3 SRC/util.c /^void print_int_matrix3(int ***vptr, int nrmin, int nrmax, int ncmin, int ncmax,$/;" f +priority SRC/include/physical_types.h /^ int priority;$/;" m struct:s_grid_loc_def +prob SRC/include/physical_types.h /^ float prob; \/* Static probability of net assigned to this clock *\/$/;" m struct:s_clock_network +probability SRC/fpga_spice_include/spice_types.h /^ float probability;$/;" m struct:s_spice_net_info +prog_clock_freq SRC/fpga_spice_include/spice_types.h /^ float prog_clock_freq; \/* Programming clock frequency, used during programming phase only *\/$/;" m struct:s_spice_stimulate_params +prop SRC/include/physical_types.h /^ int * prop; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation +pwh SRC/fpga_spice_include/spice_types.h /^ float pwh;$/;" m struct:s_spice_net_info +pwl SRC/fpga_spice_include/spice_types.h /^ float pwl;$/;" m struct:s_spice_net_info +read SRC/ezxml.c 59;" d file: +read_xml_spice SRC/include/physical_types.h /^ boolean read_xml_spice;$/;" m struct:s_arch +relative_length SRC/include/physical_types.h /^ float relative_length;$/;" m union:s_port_power::__anon3 +remove_llist_node SRC/linkedlist.c /^void remove_llist_node(t_llist* cur) { $/;" f +repeat SRC/include/physical_types.h /^ int repeat;$/;" m struct:s_grid_loc_def +res_val SRC/fpga_spice_include/spice_types.h /^ float res_val;$/;" m struct:s_spice_model_wire_param +reserved_bl SRC/fpga_spice_include/spice_types.h /^ int reserved_bl; \/* Number of reserved BLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info +reserved_wl SRC/fpga_spice_include/spice_types.h /^ int reserved_wl; \/* Number of reserved WLs shared by overall RRAM circuits *\/$/;" m struct:s_mem_bank_info +reverse_llist SRC/linkedlist.c /^t_llist* reverse_llist(t_llist* head) {$/;" f +reverse_scaled SRC/include/physical_types.h /^ boolean reverse_scaled; \/* Scale by (1-prob) *\/$/;" m struct:s_port_power +roff SRC/fpga_spice_include/spice_types.h /^ float roff;$/;" m struct:s_spice_model_rram +ron SRC/fpga_spice_include/spice_types.h /^ float ron;$/;" m struct:s_spice_model_rram +root_block SRC/include/cad_types.h /^ t_pack_pattern_block *root_block; \/* root block used by this pattern *\/$/;" m struct:s_pack_patterns +rotate_clockwise SRC/sides.cpp /^void Side::rotate_clockwise() {$/;" f class:Side +rotate_counterclockwise SRC/sides.cpp /^void Side::rotate_counterclockwise() {$/;" f class:Side +rr_node_index_physical_pb SRC/include/physical_types.h /^ int rr_node_index_physical_pb; \/* rr_node in the physical pb rr_graph*\/$/;" m struct:s_pb_graph_pin +rram_info SRC/fpga_spice_include/spice_types.h /^ t_spice_model_rram* rram_info;$/;" m struct:s_spice_model_design_tech_info +rram_pass_tran_value SRC/include/arch_types_mrfpga.h /^ float rram_pass_tran_value;$/;" m struct:s_arch_mrfpga +rram_variation SRC/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params rram_variation;$/;" m struct:s_spice_mc_params +s SRC/include/ezxml.h /^ char *s; \/* start of work area *\/$/;" m struct:ezxml_root +s_arch SRC/include/physical_types.h /^struct s_arch {$/;" s +s_arch_mrfpga SRC/include/arch_types_mrfpga.h /^struct s_arch_mrfpga {$/;" s +s_buffer_inf SRC/include/arch_types_mrfpga.h /^struct s_buffer_inf { $/;" s +s_chan SRC/include/physical_types.h /^typedef struct s_chan {$/;" s +s_chan_width_dist SRC/include/physical_types.h /^typedef struct s_chan_width_dist {$/;" s +s_chunk SRC/include/util.h /^typedef struct s_chunk {$/;" s +s_class SRC/include/physical_types.h /^struct s_class {$/;" s +s_clb_grid SRC/include/physical_types.h /^struct s_clb_grid {$/;" s +s_clock_arch SRC/include/physical_types.h /^struct s_clock_arch {$/;" s +s_clock_network SRC/include/physical_types.h /^struct s_clock_network {$/;" s +s_cluster_placement_primitive SRC/include/cad_types.h /^typedef struct s_cluster_placement_primitive {$/;" s +s_conf_bit SRC/fpga_spice_include/spice_types.h /^struct s_conf_bit {$/;" s +s_conf_bit_info SRC/fpga_spice_include/spice_types.h /^struct s_conf_bit_info {$/;" s +s_direct_inf SRC/include/physical_types.h /^typedef struct s_direct_inf {$/;" s +s_grid_loc_def SRC/include/physical_types.h /^typedef struct s_grid_loc_def {$/;" s +s_interconnect SRC/include/physical_types.h /^struct s_interconnect {$/;" s +s_interconnect_pins SRC/include/physical_types.h /^struct s_interconnect_pins {$/;" s +s_interconnect_power SRC/include/physical_types.h /^struct s_interconnect_power {$/;" s +s_ivec SRC/include/util.h /^typedef struct s_ivec {$/;" s +s_linked_int SRC/include/util.h /^typedef struct s_linked_int {$/;" s +s_linked_vptr SRC/include/util.h /^typedef struct s_linked_vptr {$/;" s +s_llist SRC/fpga_spice_include/linkedlist.h /^struct s_llist$/;" s +s_mem_bank_info SRC/fpga_spice_include/spice_types.h /^struct s_mem_bank_info {$/;" s +s_memristor_inf SRC/include/arch_types_mrfpga.h /^struct s_memristor_inf { $/;" s +s_mode SRC/include/physical_types.h /^struct s_mode {$/;" s +s_mode_power SRC/include/physical_types.h /^struct s_mode_power {$/;" s +s_model SRC/include/logic_types.h /^typedef struct s_model {$/;" s +s_model_chain_pattern SRC/include/cad_types.h /^typedef struct s_model_chain_pattern {$/;" s +s_model_ports SRC/include/logic_types.h /^typedef struct s_model_ports {$/;" s +s_pack_pattern_block SRC/include/cad_types.h /^typedef struct s_pack_pattern_block {$/;" s +s_pack_pattern_connections SRC/include/cad_types.h /^typedef struct s_pack_pattern_connections {$/;" s +s_pack_patterns SRC/include/cad_types.h /^typedef struct s_pack_patterns {$/;" s +s_pb_graph_edge SRC/include/physical_types.h /^struct s_pb_graph_edge {$/;" s +s_pb_graph_node SRC/include/physical_types.h /^struct s_pb_graph_node {$/;" s +s_pb_graph_node_power SRC/include/physical_types.h /^struct s_pb_graph_node_power {$/;" s +s_pb_graph_pin SRC/include/physical_types.h /^struct s_pb_graph_pin {$/;" s +s_pb_graph_pin_power SRC/include/physical_types.h /^struct s_pb_graph_pin_power {$/;" s +s_pb_type SRC/include/physical_types.h /^struct s_pb_type {$/;" s +s_pb_type_power SRC/include/physical_types.h /^struct s_pb_type_power {$/;" s +s_pin_to_pin_annotation SRC/include/physical_types.h /^struct s_pin_to_pin_annotation {$/;" s +s_port SRC/include/physical_types.h /^struct s_port {$/;" s +s_port_power SRC/include/physical_types.h /^struct s_port_power {$/;" s +s_power_arch SRC/include/physical_types.h /^struct s_power_arch {$/;" s +s_power_usage SRC/include/physical_types.h /^struct s_power_usage {$/;" s +s_reserved_syntax_char SRC/fpga_spice_include/spice_types.h /^struct s_reserved_syntax_char {$/;" s +s_scff_info SRC/fpga_spice_include/spice_types.h /^struct s_scff_info {$/;" s +s_segment_inf SRC/include/physical_types.h /^typedef struct s_segment_inf {$/;" s +s_spice SRC/fpga_spice_include/spice_types.h /^struct s_spice {$/;" s +s_spice_mc_params SRC/fpga_spice_include/spice_types.h /^struct s_spice_mc_params {$/;" s +s_spice_mc_variation_params SRC/fpga_spice_include/spice_types.h /^struct s_spice_mc_variation_params {$/;" s +s_spice_meas_params SRC/fpga_spice_include/spice_types.h /^struct s_spice_meas_params {$/;" s +s_spice_model SRC/fpga_spice_include/spice_types.h /^struct s_spice_model {$/;" s +s_spice_model_buffer SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_buffer {$/;" s +s_spice_model_delay_info SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_delay_info {$/;" s +s_spice_model_design_tech_info SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_design_tech_info {$/;" s +s_spice_model_gate SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_gate {$/;" s +s_spice_model_lut SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_lut {$/;" s +s_spice_model_mux SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_mux {$/;" s +s_spice_model_netlist SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_netlist {$/;" s +s_spice_model_pass_gate_logic SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_pass_gate_logic {$/;" s +s_spice_model_port SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_port {$/;" s +s_spice_model_rram SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_rram {$/;" s +s_spice_model_tedge SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_tedge {$/;" s +s_spice_model_wire_param SRC/fpga_spice_include/spice_types.h /^struct s_spice_model_wire_param {$/;" s +s_spice_mux_arch SRC/fpga_spice_include/spice_types.h /^struct s_spice_mux_arch {$/;" s +s_spice_mux_model SRC/fpga_spice_include/spice_types.h /^struct s_spice_mux_model {$/;" s +s_spice_net_info SRC/fpga_spice_include/spice_types.h /^struct s_spice_net_info {$/;" s +s_spice_params SRC/fpga_spice_include/spice_types.h /^struct s_spice_params {$/;" s +s_spice_stimulate_params SRC/fpga_spice_include/spice_types.h /^struct s_spice_stimulate_params {$/;" s +s_spice_tech_lib SRC/fpga_spice_include/spice_types.h /^struct s_spice_tech_lib {$/;" s +s_spice_transistor_type SRC/fpga_spice_include/spice_types.h /^struct s_spice_transistor_type {$/;" s +s_spicetb_info SRC/fpga_spice_include/spice_types.h /^struct s_spicetb_info {$/;" s +s_sram_inf SRC/fpga_spice_include/spice_types.h /^struct s_sram_inf {$/;" s +s_sram_inf_orgz SRC/fpga_spice_include/spice_types.h /^struct s_sram_inf_orgz {$/;" s +s_sram_orgz_info SRC/fpga_spice_include/spice_types.h /^struct s_sram_orgz_info {$/;" s +s_standalone_sram_info SRC/fpga_spice_include/spice_types.h /^struct s_standalone_sram_info {$/;" s +s_switch_inf SRC/include/physical_types.h /^typedef struct s_switch_inf {$/;" s +s_swseg_pattern_inf SRC/include/physical_types.h /^struct s_swseg_pattern_inf {$/;" s +s_timing_inf SRC/include/physical_types.h /^typedef struct s_timing_inf {$/;" s +s_type_descriptor SRC/include/physical_types.h /^struct s_type_descriptor \/* TODO rename this. maybe physical type descriptor or complex logic block or physical logic block*\/$/;" s +sb SRC/include/physical_types.h /^ boolean *sb;$/;" m struct:s_segment_inf +sb_index_high SRC/fpga_spice_include/spice_types.h /^ int** sb_index_high;$/;" m struct:s_spice_model +sb_index_low SRC/fpga_spice_include/spice_types.h /^ int** sb_index_low;$/;" m struct:s_spice_model +sb_len SRC/include/physical_types.h /^ int sb_len;$/;" m struct:s_segment_inf +scaled_by_pin SRC/include/physical_types.h /^ t_pb_graph_pin * scaled_by_pin;$/;" m struct:s_pb_graph_pin_power +scaled_by_port SRC/include/physical_types.h /^ t_port * scaled_by_port;$/;" m struct:s_port_power +scaled_by_port_pin_idx SRC/include/physical_types.h /^ int scaled_by_port_pin_idx;$/;" m struct:s_port_power +scff_info SRC/fpga_spice_include/spice_types.h /^ t_scff_info* scff_info; \/* Only be allocated when orgz type is scan-chain *\/$/;" m struct:s_sram_orgz_info +scratch_pad SRC/include/physical_types.h /^ int scratch_pad; \/* temporary data structure useful to store traversal info *\/$/;" m struct:s_pb_graph_pin +search_in_int_list SRC/util.c /^t_linked_int* search_in_int_list(t_linked_int* int_list_head, $/;" f +search_llist_tail SRC/linkedlist.c /^t_llist* search_llist_tail(t_llist* head) {$/;" f +seg_direction_type SRC/include/physical_types.h /^ enum e_directionality seg_direction_type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_directionality +seg_length SRC/include/physical_types.h /^ int seg_length;$/;" m struct:s_swseg_pattern_inf +seg_switch SRC/include/physical_types.h /^ short seg_switch;$/;" m struct:s_segment_inf +set_opposite SRC/sides.cpp /^void Side::set_opposite() { $/;" f class:Side +set_side SRC/sides.cpp /^void Side::set_side(enum e_side side) { $/;" f class:Side +set_side SRC/sides.cpp /^void Side::set_side(size_t side) { $/;" f class:Side +sibling SRC/include/ezxml.h /^ ezxml_t sibling; \/* next tag with different name in same section and depth *\/$/;" m struct:ezxml +side_ SRC/include/sides.h /^ enum e_side side_; $/;" m class:Side typeref:enum:Side::e_side +sim_clock_freq_slack SRC/fpga_spice_include/spice_types.h /^ float sim_clock_freq_slack;$/;" m struct:s_spice_stimulate_params +sim_num_clock_cycle SRC/fpga_spice_include/spice_types.h /^ int sim_num_clock_cycle; \/* Number of clock cycle in simulation *\/$/;" m struct:s_spice_meas_params +sim_temp SRC/fpga_spice_include/spice_types.h /^ int sim_temp; \/* Simulation Temperature*\/$/;" m struct:s_spice_params +size SRC/fpga_spice_include/spice_types.h /^ float size;$/;" m struct:s_spice_model_buffer +size SRC/fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_model_port +size SRC/fpga_spice_include/spice_types.h /^ int size;$/;" m struct:s_spice_mux_model +size SRC/include/logic_types.h /^ int size; \/* maximum number of pins *\/$/;" m struct:s_model_ports +slew_fall SRC/fpga_spice_include/spice_types.h /^ float slew_fall;$/;" m struct:s_spice_net_info +slew_lower_thres_pct_fall SRC/fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_fall;$/;" m struct:s_spice_meas_params +slew_lower_thres_pct_rise SRC/fpga_spice_include/spice_types.h /^ float slew_lower_thres_pct_rise;$/;" m struct:s_spice_meas_params +slew_rise SRC/fpga_spice_include/spice_types.h /^ float slew_rise;$/;" m struct:s_spice_net_info +slew_upper_thres_pct_fall SRC/fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_fall;$/;" m struct:s_spice_meas_params +slew_upper_thres_pct_rise SRC/fpga_spice_include/spice_types.h /^ float slew_upper_thres_pct_rise;$/;" m struct:s_spice_meas_params +snprintf SRC/ezxml.c 57;" d file: +spice SRC/include/physical_types.h /^ t_spice* spice;$/;" m struct:s_arch +spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz +spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_buffer +spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_pass_gate_logic +spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_model_port +spice_model SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_model;$/;" m struct:s_spice_mux_model +spice_model SRC/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_direct_inf +spice_model SRC/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_interconnect +spice_model SRC/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_pb_type +spice_model SRC/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_segment_inf +spice_model SRC/include/physical_types.h /^ t_spice_model* spice_model;$/;" m struct:s_switch_inf +spice_model_delay_type SRC/fpga_spice_include/spice_types.h /^enum spice_model_delay_type {$/;" g +spice_model_name SRC/fpga_spice_include/spice_types.h /^ char* spice_model_name; \/\/ Xifan TANG: Spice Support$/;" m struct:s_sram_inf_orgz +spice_model_name SRC/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_buffer +spice_model_name SRC/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_pass_gate_logic +spice_model_name SRC/fpga_spice_include/spice_types.h /^ char* spice_model_name;$/;" m struct:s_spice_model_port +spice_model_name SRC/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_direct_inf +spice_model_name SRC/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_interconnect +spice_model_name SRC/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_pb_type +spice_model_name SRC/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_segment_inf +spice_model_name SRC/include/physical_types.h /^ char* spice_model_name;$/;" m struct:s_switch_inf +spice_model_port SRC/include/physical_types.h /^ t_spice_model_port* spice_model_port;$/;" m struct:s_port +spice_model_sram_offset SRC/include/physical_types.h /^ int spice_model_sram_offset;$/;" m struct:s_interconnect +spice_model_sram_offset SRC/include/physical_types.h /^ int spice_model_sram_offset;$/;" m struct:s_pb_type +spice_models SRC/fpga_spice_include/spice_types.h /^ t_spice_model* spice_models;$/;" m struct:s_spice +spice_mux_arch SRC/fpga_spice_include/spice_types.h /^ t_spice_mux_arch* spice_mux_arch;$/;" m struct:s_spice_mux_model +spice_params SRC/fpga_spice_include/spice_types.h /^ t_spice_params spice_params;$/;" m struct:s_spice +spice_reserved SRC/fpga_spice_include/spice_types.h /^ boolean spice_reserved;$/;" m struct:s_reserved_syntax_char +spice_sram_inf_orgz SRC/fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* spice_sram_inf_orgz;$/;" m struct:s_sram_inf +spot_int_in_array SRC/util.c /^int spot_int_in_array(int array_len, int* array,$/;" f +sram_bit SRC/fpga_spice_include/spice_types.h /^ t_conf_bit* sram_bit;$/;" m struct:s_conf_bit_info +sram_inf SRC/include/physical_types.h /^ t_sram_inf sram_inf;$/;" m struct:s_arch +standalone SRC/include/ezxml.h /^ short standalone; \/* non-zero if *\/$/;" m struct:ezxml_root +standalone_sram_info SRC/fpga_spice_include/spice_types.h /^ t_standalone_sram_info* standalone_sram_info; \/* Only be allocated when orgz type is standalone *\/$/;" m struct:s_sram_orgz_info +start_col SRC/include/physical_types.h /^ int start_col;$/;" m struct:s_grid_loc_def +start_seg_switch SRC/include/arch_types_mrfpga.h /^ short start_seg_switch;$/;" m struct:s_arch_mrfpga +stimulate_params SRC/fpga_spice_include/spice_types.h /^ t_spice_stimulate_params stimulate_params;$/;" m struct:s_spice_params +structure SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_model_mux typeref:enum:s_spice_model_mux::e_spice_model_structure +structure SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_spice_mux_arch typeref:enum:s_spice_mux_arch::e_spice_model_structure +structure SRC/include/physical_types.h /^ enum e_spice_model_structure structure;$/;" m struct:s_switch_inf typeref:enum:s_switch_inf::e_spice_model_structure +switch_num_level SRC/include/physical_types.h /^ int switch_num_level;$/;" m struct:s_switch_inf +swseg_patterns SRC/include/physical_types.h /^ t_swseg_pattern_inf* swseg_patterns;$/;" m struct:s_arch +syntax_char SRC/fpga_spice_include/spice_types.h /^ char syntax_char;$/;" m struct:s_reserved_syntax_char +t_arch SRC/include/physical_types.h /^typedef struct s_arch t_arch;$/;" t typeref:struct:s_arch +t_arch_mrfpga SRC/include/arch_types_mrfpga.h /^typedef struct s_arch_mrfpga t_arch_mrfpga;$/;" t typeref:struct:s_arch_mrfpga +t_buffer_inf SRC/include/arch_types_mrfpga.h /^typedef struct s_buffer_inf t_buffer_inf;$/;" t typeref:struct:s_buffer_inf +t_chan SRC/include/physical_types.h /^} t_chan;$/;" t typeref:struct:s_chan +t_chan_width_dist SRC/include/physical_types.h /^} t_chan_width_dist;$/;" t typeref:struct:s_chan_width_dist +t_chunk SRC/include/util.h /^} t_chunk;$/;" t typeref:struct:s_chunk +t_class SRC/include/physical_types.h /^typedef struct s_class t_class;$/;" t typeref:struct:s_class +t_clock_arch SRC/include/physical_types.h /^typedef struct s_clock_arch t_clock_arch;$/;" t typeref:struct:s_clock_arch +t_clock_network SRC/include/physical_types.h /^typedef struct s_clock_network t_clock_network;$/;" t typeref:struct:s_clock_network +t_cluster_placement_primitive SRC/include/cad_types.h /^} t_cluster_placement_primitive;$/;" t typeref:struct:s_cluster_placement_primitive +t_conf_bit SRC/fpga_spice_include/spice_types.h /^typedef struct s_conf_bit t_conf_bit;$/;" t typeref:struct:s_conf_bit +t_conf_bit_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_conf_bit_info t_conf_bit_info;$/;" t typeref:struct:s_conf_bit_info +t_direct_inf SRC/include/physical_types.h /^} t_direct_inf;$/;" t typeref:struct:s_direct_inf +t_grid_loc_def SRC/include/physical_types.h /^} t_grid_loc_def;$/;" t typeref:struct:s_grid_loc_def +t_interconnect SRC/include/physical_types.h /^typedef struct s_interconnect t_interconnect;$/;" t typeref:struct:s_interconnect +t_interconnect_pins SRC/include/physical_types.h /^typedef struct s_interconnect_pins t_interconnect_pins;$/;" t typeref:struct:s_interconnect_pins +t_interconnect_power SRC/include/physical_types.h /^typedef struct s_interconnect_power t_interconnect_power;$/;" t typeref:struct:s_interconnect_power +t_ivec SRC/include/util.h /^} t_ivec;$/;" t typeref:struct:s_ivec +t_linked_int SRC/include/util.h /^} t_linked_int;$/;" t typeref:struct:s_linked_int +t_linked_vptr SRC/include/util.h /^} t_linked_vptr;$/;" t typeref:struct:s_linked_vptr +t_llist SRC/fpga_spice_include/linkedlist.h /^typedef struct s_llist t_llist;$/;" t typeref:struct:s_llist +t_mem_bank_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_mem_bank_info t_mem_bank_info;$/;" t typeref:struct:s_mem_bank_info +t_memristor_inf SRC/include/arch_types_mrfpga.h /^typedef struct s_memristor_inf t_memristor_inf;$/;" t typeref:struct:s_memristor_inf +t_mode SRC/include/physical_types.h /^typedef struct s_mode t_mode;$/;" t typeref:struct:s_mode +t_mode_power SRC/include/physical_types.h /^typedef struct s_mode_power t_mode_power;$/;" t typeref:struct:s_mode_power +t_model SRC/include/logic_types.h /^} t_model;$/;" t typeref:struct:s_model +t_model_chain_pattern SRC/include/cad_types.h /^} t_model_chain_pattern;$/;" t typeref:struct:s_model_chain_pattern +t_model_ports SRC/include/logic_types.h /^} t_model_ports;$/;" t typeref:struct:s_model_ports +t_pack_pattern_block SRC/include/cad_types.h /^} t_pack_pattern_block;$/;" t typeref:struct:s_pack_pattern_block +t_pack_pattern_connections SRC/include/cad_types.h /^} t_pack_pattern_connections;$/;" t typeref:struct:s_pack_pattern_connections +t_pack_patterns SRC/include/cad_types.h /^} t_pack_patterns;$/;" t typeref:struct:s_pack_patterns +t_pb_graph_edge SRC/include/physical_types.h /^typedef struct s_pb_graph_edge t_pb_graph_edge;$/;" t typeref:struct:s_pb_graph_edge +t_pb_graph_node SRC/include/physical_types.h /^typedef struct s_pb_graph_node t_pb_graph_node;$/;" t typeref:struct:s_pb_graph_node +t_pb_graph_node_power SRC/include/physical_types.h /^typedef struct s_pb_graph_node_power t_pb_graph_node_power;$/;" t typeref:struct:s_pb_graph_node_power +t_pb_graph_pin SRC/include/physical_types.h /^typedef struct s_pb_graph_pin t_pb_graph_pin;$/;" t typeref:struct:s_pb_graph_pin +t_pb_graph_pin_power SRC/include/physical_types.h /^typedef struct s_pb_graph_pin_power t_pb_graph_pin_power;$/;" t typeref:struct:s_pb_graph_pin_power +t_pb_type SRC/include/physical_types.h /^typedef struct s_pb_type t_pb_type;$/;" t typeref:struct:s_pb_type +t_pb_type_power SRC/include/physical_types.h /^typedef struct s_pb_type_power t_pb_type_power;$/;" t typeref:struct:s_pb_type_power +t_pin_to_pin_annotation SRC/include/physical_types.h /^typedef struct s_pin_to_pin_annotation t_pin_to_pin_annotation;$/;" t typeref:struct:s_pin_to_pin_annotation +t_port SRC/include/physical_types.h /^typedef struct s_port t_port;$/;" t typeref:struct:s_port +t_port_power SRC/include/physical_types.h /^typedef struct s_port_power t_port_power;$/;" t typeref:struct:s_port_power +t_power_arch SRC/include/physical_types.h /^typedef struct s_power_arch t_power_arch;$/;" t typeref:struct:s_power_arch +t_power_estimation_method SRC/include/physical_types.h /^typedef enum e_power_estimation_method_ t_power_estimation_method;$/;" t typeref:enum:e_power_estimation_method_ +t_power_usage SRC/include/physical_types.h /^typedef struct s_power_usage t_power_usage;$/;" t typeref:struct:s_power_usage +t_reserved_syntax_char SRC/fpga_spice_include/spice_types.h /^typedef struct s_reserved_syntax_char t_reserved_syntax_char;$/;" t typeref:struct:s_reserved_syntax_char +t_scff_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_scff_info t_scff_info;$/;" t typeref:struct:s_scff_info +t_segment_inf SRC/include/physical_types.h /^} t_segment_inf;$/;" t typeref:struct:s_segment_inf +t_spice SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice t_spice;$/;" t typeref:struct:s_spice +t_spice_mc_params SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_params t_spice_mc_params;$/;" t typeref:struct:s_spice_mc_params +t_spice_mc_variation_params SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_mc_variation_params t_spice_mc_variation_params;$/;" t typeref:struct:s_spice_mc_variation_params +t_spice_meas_params SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_meas_params t_spice_meas_params;$/;" t typeref:struct:s_spice_meas_params +t_spice_model SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model t_spice_model;$/;" t typeref:struct:s_spice_model +t_spice_model_buffer SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_buffer t_spice_model_buffer;$/;" t typeref:struct:s_spice_model_buffer +t_spice_model_delay_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_delay_info t_spice_model_delay_info;$/;" t typeref:struct:s_spice_model_delay_info +t_spice_model_design_tech_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_design_tech_info t_spice_model_design_tech_info;$/;" t typeref:struct:s_spice_model_design_tech_info +t_spice_model_gate SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_gate t_spice_model_gate;$/;" t typeref:struct:s_spice_model_gate +t_spice_model_lut SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_lut t_spice_model_lut;$/;" t typeref:struct:s_spice_model_lut +t_spice_model_mux SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_mux t_spice_model_mux;$/;" t typeref:struct:s_spice_model_mux +t_spice_model_netlist SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_netlist t_spice_model_netlist;$/;" t typeref:struct:s_spice_model_netlist +t_spice_model_pass_gate_logic SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_pass_gate_logic t_spice_model_pass_gate_logic;$/;" t typeref:struct:s_spice_model_pass_gate_logic +t_spice_model_port SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_port t_spice_model_port;$/;" t typeref:struct:s_spice_model_port +t_spice_model_rram SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_rram t_spice_model_rram;$/;" t typeref:struct:s_spice_model_rram +t_spice_model_tedge SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_tedge t_spice_model_tedge;$/;" t typeref:struct:s_spice_model_tedge +t_spice_model_wire_param SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_model_wire_param t_spice_model_wire_param;$/;" t typeref:struct:s_spice_model_wire_param +t_spice_mux_arch SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_arch t_spice_mux_arch;$/;" t typeref:struct:s_spice_mux_arch +t_spice_mux_model SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_mux_model t_spice_mux_model;$/;" t typeref:struct:s_spice_mux_model +t_spice_net_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_net_info t_spice_net_info;$/;" t typeref:struct:s_spice_net_info +t_spice_params SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_params t_spice_params;$/;" t typeref:struct:s_spice_params +t_spice_stimulate_params SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_stimulate_params t_spice_stimulate_params;$/;" t typeref:struct:s_spice_stimulate_params +t_spice_tech_lib SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_tech_lib t_spice_tech_lib;$/;" t typeref:struct:s_spice_tech_lib +t_spice_transistor_type SRC/fpga_spice_include/spice_types.h /^typedef struct s_spice_transistor_type t_spice_transistor_type;$/;" t typeref:struct:s_spice_transistor_type +t_spicetb_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_spicetb_info t_spicetb_info;$/;" t typeref:struct:s_spicetb_info +t_sram_inf SRC/fpga_spice_include/spice_types.h /^typedef struct s_sram_inf t_sram_inf;$/;" t typeref:struct:s_sram_inf +t_sram_inf_orgz SRC/fpga_spice_include/spice_types.h /^typedef struct s_sram_inf_orgz t_sram_inf_orgz;$/;" t typeref:struct:s_sram_inf_orgz +t_sram_orgz_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_sram_orgz_info t_sram_orgz_info;$/;" t typeref:struct:s_sram_orgz_info +t_standalone_sram_info SRC/fpga_spice_include/spice_types.h /^typedef struct s_standalone_sram_info t_standalone_sram_info;$/;" t typeref:struct:s_standalone_sram_info +t_switch_block_type SRC/include/physical_types.h /^typedef enum e_switch_block_type t_switch_block_type;$/;" t typeref:enum:e_switch_block_type +t_switch_inf SRC/include/physical_types.h /^} t_switch_inf;$/;" t typeref:struct:s_switch_inf +t_swseg_pattern_inf SRC/include/physical_types.h /^typedef struct s_swseg_pattern_inf t_swseg_pattern_inf;$/;" t typeref:struct:s_swseg_pattern_inf +t_timing_inf SRC/include/physical_types.h /^} t_timing_inf;$/;" t typeref:struct:s_timing_inf +t_type_descriptor SRC/include/physical_types.h /^typedef struct s_type_descriptor t_type_descriptor;$/;" t typeref:struct:s_type_descriptor +t_type_ptr SRC/include/physical_types.h /^typedef const struct s_type_descriptor *t_type_ptr;$/;" t typeref:struct:s_type_descriptor +tap_buf_level SRC/fpga_spice_include/spice_types.h /^ int tap_buf_level;$/;" m struct:s_spice_model_buffer +tapered_buf SRC/fpga_spice_include/spice_types.h /^ int tapered_buf; \/*Valid only when this is a buffer*\/$/;" m struct:s_spice_model_buffer +tb_cnt SRC/fpga_spice_include/spice_types.h /^ int tb_cnt;$/;" m struct:s_spice_model +tb_name SRC/fpga_spice_include/spice_types.h /^ char* tb_name;$/;" m struct:s_spicetb_info +tech_comp SRC/include/arch_types_mrfpga.h /^ enum e_tech_comp tech_comp;$/;" m struct:s_arch_mrfpga typeref:enum:s_arch_mrfpga::e_tech_comp +tech_lib SRC/fpga_spice_include/spice_types.h /^ t_spice_tech_lib tech_lib;$/;" m struct:s_spice +tedge SRC/fpga_spice_include/spice_types.h /^ t_spice_model_tedge*** tedge; \/* 3-D array, considering the each pin in this port, [pin_number][num_edges[iedge]] is an edge pointor *\/$/;" m struct:s_spice_model_port +temp_net_num SRC/include/physical_types.h /^ int temp_net_num;$/;" m struct:s_pb_graph_pin +temp_placement_index SRC/include/physical_types.h /^ int temp_placement_index;$/;" m struct:s_pb_type +temp_scratch_pad SRC/include/physical_types.h /^ void *temp_scratch_pad; \/* temporary data, useful for keeping track of things when traversing data structure *\/$/;" m struct:s_pb_graph_node +tfall SRC/fpga_spice_include/spice_types.h /^ float tfall; \/* Fall condition: delay *\/$/;" m struct:s_spice_model_tedge +tileable SRC/include/physical_types.h /^ bool tileable; \/* Xifan TANG: tileable rr_graph support *\/$/;" m struct:s_arch +timing_analysis_enabled SRC/include/physical_types.h /^ boolean timing_analysis_enabled;$/;" m struct:s_timing_inf +to_block SRC/include/cad_types.h /^ t_pack_pattern_block *to_block;$/;" m struct:s_pack_pattern_connections +to_pin SRC/include/cad_types.h /^ t_pb_graph_pin *to_pin;$/;" m struct:s_pack_pattern_connections +to_pin SRC/include/physical_types.h /^ char *to_pin;$/;" m struct:s_direct_inf +to_port SRC/fpga_spice_include/spice_types.h /^ t_spice_model_port* to_port;$/;" m struct:s_spice_model_tedge +to_port_pin_number SRC/fpga_spice_include/spice_types.h /^ int to_port_pin_number;$/;" m struct:s_spice_model_tedge +to_size_t SRC/sides.cpp /^size_t Side::to_size_t() const {$/;" f class:Side +to_string SRC/sides.cpp /^std::string Side::to_string() const { $/;" f class:Side +total_pb_pins SRC/include/physical_types.h /^ int total_pb_pins; \/* only valid for top-level *\/$/;" m struct:s_pb_graph_node +transistor_cnt SRC/include/physical_types.h /^ float transistor_cnt;$/;" m struct:s_interconnect_power +transistor_cnt_buffers SRC/include/physical_types.h /^ float transistor_cnt_buffers;$/;" m struct:s_pb_graph_node_power +transistor_cnt_interc SRC/include/physical_types.h /^ float transistor_cnt_interc; \/* Total transistor size of the interconnect in this pb *\/$/;" m struct:s_pb_graph_node_power +transistor_cnt_pb_children SRC/include/physical_types.h /^ float transistor_cnt_pb_children; \/* Total transistor size of this pb *\/$/;" m struct:s_pb_graph_node_power +transistor_type SRC/fpga_spice_include/spice_types.h /^ char* transistor_type;$/;" m struct:s_spice_tech_lib +transistor_types SRC/fpga_spice_include/spice_types.h /^ t_spice_transistor_type* transistor_types;$/;" m struct:s_spice_tech_lib +transistors_per_SRAM_bit SRC/include/physical_types.h /^ float transistors_per_SRAM_bit;$/;" m struct:s_power_arch +tri_state_map SRC/fpga_spice_include/spice_types.h /^ char* tri_state_map;$/;" m struct:s_spice_model_port +trise SRC/fpga_spice_include/spice_types.h /^ float trise; \/* Rise condition: delay *\/$/;" m struct:s_spice_model_tedge +tsu_tco SRC/include/physical_types.h /^ float tsu_tco; \/* For sequential logic elements, this is the setup time (if input) or clock-to-q time (if output) *\/$/;" m struct:s_pb_graph_pin +txt SRC/include/ezxml.h /^ char *txt; \/* tag character content, empty string if none *\/$/;" m struct:ezxml +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_buffer_type type;$/;" m struct:s_spice_model_buffer typeref:enum:s_spice_model_buffer::e_spice_model_buffer_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_gate_type type;$/;" m struct:s_spice_model_gate typeref:enum:s_spice_model_gate::e_spice_model_gate_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_pass_gate_logic_type type;$/;" m struct:s_spice_model_pass_gate_logic typeref:enum:s_spice_model_pass_gate_logic::e_spice_model_pass_gate_logic_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_port_type type;$/;" m struct:s_spice_model_port typeref:enum:s_spice_model_port::e_spice_model_port_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_model_type type;$/;" m struct:s_spice_model typeref:enum:s_spice_model::e_spice_model_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_tech_lib_type type;$/;" m struct:s_spice_tech_lib typeref:enum:s_spice_tech_lib::e_spice_tech_lib_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_spice_trans_type type;$/;" m struct:s_spice_transistor_type typeref:enum:s_spice_transistor_type::e_spice_trans_type +type SRC/fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_inf_orgz typeref:enum:s_sram_inf_orgz::e_sram_orgz +type SRC/fpga_spice_include/spice_types.h /^ enum e_sram_orgz type;$/;" m struct:s_sram_orgz_info typeref:enum:s_sram_orgz_info::e_sram_orgz +type SRC/fpga_spice_include/spice_types.h /^ enum e_wire_model_type type;$/;" m struct:s_spice_model_wire_param typeref:enum:s_spice_model_wire_param::e_wire_model_type +type SRC/fpga_spice_include/spice_types.h /^ enum spice_model_delay_type type;$/;" m struct:s_spice_model_delay_info typeref:enum:s_spice_model_delay_info::spice_model_delay_type +type SRC/include/physical_types.h /^ enum PORTS type;$/;" m struct:s_port typeref:enum:s_port::PORTS +type SRC/include/physical_types.h /^ enum e_interconnect type;$/;" m struct:s_interconnect typeref:enum:s_interconnect::e_interconnect +type SRC/include/physical_types.h /^ enum e_pb_graph_pin_type type; \/* Is a sequential logic element (TRUE), inpad\/outpad (TRUE), or neither (FALSE) *\/$/;" m struct:s_pb_graph_pin typeref:enum:s_pb_graph_pin::e_pb_graph_pin_type +type SRC/include/physical_types.h /^ enum e_pin_to_pin_annotation_type type;$/;" m struct:s_pin_to_pin_annotation typeref:enum:s_pin_to_pin_annotation::e_pin_to_pin_annotation_type +type SRC/include/physical_types.h /^ enum e_pin_type type;$/;" m struct:s_class typeref:enum:s_class::e_pin_type +type SRC/include/physical_types.h /^ enum e_stat type;$/;" m struct:s_chan typeref:enum:s_chan::e_stat +type SRC/include/physical_types.h /^ char* type;$/;" m struct:s_switch_inf +type SRC/include/physical_types.h /^ enum e_swseg_pattern_type type;$/;" m struct:s_swseg_pattern_inf typeref:enum:s_swseg_pattern_inf::e_swseg_pattern_type +u SRC/include/ezxml.h /^ char *u; \/* UTF-8 conversion of string if original was UTF-16 *\/$/;" m struct:ezxml_root +unbuf_switch SRC/include/physical_types.h /^ short unbuf_switch;$/;" m struct:s_swseg_pattern_inf +used SRC/include/logic_types.h /^ int used;$/;" m struct:s_model +val SRC/fpga_spice_include/spice_types.h /^ int val; \/* binary value to be writtent: either 0 or 1 *\/$/;" m struct:s_conf_bit +valid SRC/include/cad_types.h /^ boolean valid;$/;" m struct:s_cluster_placement_primitive +validate SRC/sides.cpp /^bool Side::validate() const {$/;" f class:Side +value SRC/fpga_spice_include/spice_types.h /^ char* value; $/;" m struct:s_spice_model_delay_info +value SRC/include/physical_types.h /^ char ** value; \/* [0..num_value_prop_pairs - 1] *\/$/;" m struct:s_pin_to_pin_annotation +variation_on SRC/fpga_spice_include/spice_types.h /^ boolean variation_on;$/;" m struct:s_spice_mc_variation_params +verilog_netlist SRC/fpga_spice_include/spice_types.h /^ char* verilog_netlist; \/* Verilog netlist provided by user *\/$/;" m struct:s_spice_model +verilog_reserved SRC/fpga_spice_include/spice_types.h /^ boolean verilog_reserved;$/;" m struct:s_reserved_syntax_char +verilog_sram_inf_orgz SRC/fpga_spice_include/spice_types.h /^ t_sram_inf_orgz* verilog_sram_inf_orgz;$/;" m struct:s_sram_inf +vpr_crit_path_delay SRC/fpga_spice_include/spice_types.h /^ float vpr_crit_path_delay; \/* Reference operation clock frequency *\/$/;" m struct:s_spice_stimulate_params +vpr_printf SRC/util.c /^messagelogger vpr_printf = PrintHandlerMessage;$/;" v +width SRC/include/physical_types.h /^ float width;$/;" m struct:s_chan +wire SRC/include/physical_types.h /^ } wire;$/;" m struct:s_port_power typeref:union:s_port_power::__anon3 +wire_buffer_inf SRC/include/arch_types_mrfpga.h /^ t_buffer_inf wire_buffer_inf;$/;" m struct:s_arch_mrfpga +wire_param SRC/fpga_spice_include/spice_types.h /^ t_spice_model_wire_param* wire_param;$/;" m struct:s_spice_model +wire_switch SRC/include/physical_types.h /^ short wire_switch;$/;" m struct:s_segment_inf +wire_type SRC/include/physical_types.h /^ e_power_wire_type wire_type;$/;" m struct:s_port_power +wire_variation SRC/fpga_spice_include/spice_types.h /^ t_spice_mc_variation_params wire_variation;$/;" m struct:s_spice_mc_params +wl SRC/fpga_spice_include/spice_types.h /^ t_conf_bit* wl;$/;" m struct:s_conf_bit_info +wprog_reset_nmos SRC/fpga_spice_include/spice_types.h /^ float wprog_reset_nmos;$/;" m struct:s_spice_model_rram +wprog_reset_pmos SRC/fpga_spice_include/spice_types.h /^ float wprog_reset_pmos;$/;" m struct:s_spice_model_rram +wprog_set_nmos SRC/fpga_spice_include/spice_types.h /^ float wprog_set_nmos;$/;" m struct:s_spice_model_rram +wprog_set_pmos SRC/fpga_spice_include/spice_types.h /^ float wprog_set_pmos;$/;" m struct:s_spice_model_rram +write SRC/ezxml.c 60;" d file: +x_offset SRC/include/physical_types.h /^ int x_offset;$/;" m struct:s_direct_inf +xml SRC/include/ezxml.h /^ struct ezxml xml; \/* is a super-struct built on top of ezxml struct *\/$/;" m struct:ezxml_root typeref:struct:ezxml_root::ezxml +xpeak SRC/include/physical_types.h /^ float xpeak;$/;" m struct:s_chan +y_offset SRC/include/physical_types.h /^ int y_offset;$/;" m struct:s_direct_inf +z_offset SRC/include/physical_types.h /^ int z_offset;$/;" m struct:s_direct_inf diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 7e1a0cd77..2e1b85236 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -378,7 +378,7 @@ void dump_compact_verilog_one_physical_block(t_sram_orgz_info* cur_sram_orgz_inf /* I/O PAD */ dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, 0, phy_block_type->capacity * phy_block_type->pb_type->physical_mode_num_iopads - 1, - VERILOG_PORT_INOUT, is_explicit_mapping); + VERILOG_PORT_INOUT, false); /* Print configuration ports */ /* Reserved configuration ports */ @@ -622,9 +622,9 @@ void dump_compact_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, } if (IO_TYPE == grid[ix][iy].type) { - dump_verilog_io_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE); + dump_verilog_io_grid_pins(fp, ix, iy, TRUE, border_side, FALSE, FALSE, is_explicit_mapping); } else { - dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE); + dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE, is_explicit_mapping); } /* IO PAD */ @@ -792,10 +792,20 @@ void dump_compact_verilog_defined_one_switch_box(t_sram_orgz_info* cur_sram_orgz fprintf(fp, "//----- %s side channel ports-----\n", side_manager.c_str()); for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) { - fprintf(fp, "%s,\n", + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), chan_coordinator.get_x(), chan_coordinator.get_y(), itrack, rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + } + fprintf(fp, "%s", + gen_verilog_routing_channel_one_pin_name(rr_sb.get_chan_node(side_manager.get_side(), itrack), + chan_coordinator.get_x(), chan_coordinator.get_y(), itrack, + rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))); + if (true == is_explicit_mapping) { + fprintf(fp, ")",itrack); + } + fprintf(fp, ",\n",itrack); } fprintf(fp, "//----- %s side inputs: CLB output pins -----\n", convert_side_index_to_string(side)); /* Dump OPINs of adjacent CLBs */ @@ -917,9 +927,16 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ fprintf(fp, "//----- %s side inputs: channel track middle outputs -----\n", convert_side_index_to_string(rr_gsb.get_cb_chan_side(cb_type))); for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { - fprintf(fp, "%s, ", + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack)); - fprintf(fp, "\n"); + } + fprintf(fp, "%s", + rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack)); + if (true == is_explicit_mapping) { + fprintf(fp, ")",itrack); + } + fprintf(fp, ",\n"); } std::vector cb_sides = rr_gsb.get_cb_ipin_sides(cb_type); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index a779ee550..6fa1ad6da 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -369,8 +369,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, pb_type_port->num_pins - 1, port_prefix, pb_type_port->name); } else { - if ((NULL != cur_pb_type->spice_model) - && (TRUE == dump_explicit_port_map)) { + if (TRUE == dump_explicit_port_map) { fprintf(fp, ".%s(", pb_type_port->spice_model_port->lib_name); } @@ -383,8 +382,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin)); } fprintf(fp, "}"); - if ((NULL != cur_pb_type->spice_model) - && (TRUE == dump_explicit_port_map)) { + if (TRUE == dump_explicit_port_map) { fprintf(fp, ")"); } } @@ -537,7 +535,8 @@ void dump_verilog_pb_type_ports(FILE* fp, t_pb_type* cur_pb_type, boolean dump_port_type, boolean dump_last_comma, - boolean require_explicit_port_map) { + boolean require_explicit_port_map, + bool is_full_name) { int iport, ipin; int num_pb_type_input_port = 0; t_port** pb_type_input_ports = NULL; @@ -588,18 +587,21 @@ void dump_verilog_pb_type_ports(FILE* fp, } if (TRUE == dump_port_type) { fprintf(fp, "inout wire "); - } else if ((NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + } else if (TRUE == require_explicit_port_map) { + if (false == is_full_name && NULL != cur_pb_type->spice_model) { fprintf(fp, ".%s(", pb_type_inout_ports[iport]->spice_model_port->lib_name); + } else { + /* fprintf(fp, ".%s(", + gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_inout_ports[iport], ipin)); */ + fprintf(fp, ".%s__%s_%d_(", + cur_pb_type->name, pb_type_inout_ports[iport]->name, ipin); + } } - fprintf(fp, "%s", + fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_inout_ports[iport], ipin)); - if ((FALSE == dump_port_type) - && (NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + if ((FALSE == dump_port_type) + && TRUE == require_explicit_port_map) { fprintf(fp, ") "); } /* Update the counter */ @@ -631,18 +633,21 @@ void dump_verilog_pb_type_ports(FILE* fp, } if (TRUE == dump_port_type) { fprintf(fp, "input wire "); - } else if ((NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + } else if (TRUE == require_explicit_port_map) { + if (false == is_full_name && NULL != cur_pb_type->spice_model) { fprintf(fp, ".%s(", pb_type_input_ports[iport]->spice_model_port->lib_name); + } else { + /* fprintf(fp, ".%s(", + gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_input_ports[iport], ipin)); */ + fprintf(fp, ".%s__%s_%d_(", + cur_pb_type->name, pb_type_input_ports[iport]->name, ipin); + } } fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_input_ports[iport], ipin)); if ((FALSE == dump_port_type) - && (NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + && TRUE == require_explicit_port_map) { fprintf(fp, ") "); } /* Update the counter */ @@ -673,18 +678,21 @@ void dump_verilog_pb_type_ports(FILE* fp, } if (TRUE == dump_port_type) { fprintf(fp, "output wire "); - } else if ((NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + } else if (TRUE == require_explicit_port_map) { + if (false == is_full_name && NULL != cur_pb_type->spice_model) { fprintf(fp, ".%s(", pb_type_output_ports[iport]->spice_model_port->lib_name); + } else { + /* fprintf(fp, ".%s(", + gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_output_ports[iport], ipin));*/ + fprintf(fp, ".%s__%s_%d_(", + cur_pb_type->name, pb_type_output_ports[iport]->name, ipin); + } } fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_output_ports[iport], ipin)); if ((FALSE == dump_port_type) - && (NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + && TRUE == require_explicit_port_map) { fprintf(fp, ") "); } /* Update the counter */ @@ -718,18 +726,19 @@ void dump_verilog_pb_type_ports(FILE* fp, } if (TRUE == dump_port_type) { fprintf(fp, "input wire "); - } else if ((NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + } else if (TRUE == require_explicit_port_map) { + if (false == is_full_name && NULL != cur_pb_type->spice_model) { fprintf(fp, ".%s(", pb_type_clk_ports[iport]->spice_model_port->lib_name); + } else { + fprintf(fp, ".%s__%s_%d_(", + cur_pb_type->name, pb_type_clk_ports[iport]->name, ipin); + } } fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(formatted_port_prefix, pb_type_clk_ports[iport], ipin)); if ((FALSE == dump_port_type) - && (NULL != cur_pb_type->spice_model) - && (TRUE == require_explicit_port_map) - && (TRUE == cur_pb_type->spice_model->dump_explicit_port_map)) { + && TRUE == require_explicit_port_map) { fprintf(fp, ") "); } /* Update the counter */ @@ -1501,7 +1510,7 @@ void dump_verilog_pb_graph_primitive_node(FILE* fp, fprintf(fp, "module %s (", subckt_name); /* subckt_port_name = format_verilog_node_prefix(subckt_name); */ /* Inputs, outputs, inouts, clocks */ - dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, TRUE, FALSE, FALSE); + dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, TRUE, FALSE, FALSE, false); /* SRAM ports */ fprintf(fp, ");\n"); /* Include the spice_model*/ @@ -1509,7 +1518,7 @@ void dump_verilog_pb_graph_primitive_node(FILE* fp, verilog_model->cnt++; /* Stats the number of verilog_model used*/ /* Make input, output, inout, clocks connected*/ /* IMPORTANT: (sequence of these ports should be changed!) */ - dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, FALSE, FALSE, TRUE); + dump_verilog_pb_type_ports(fp, subckt_name, 0, cur_pb_type, FALSE, FALSE, TRUE, true); fprintf(fp, ");"); /* Print end of subckt*/ fprintf(fp, "endmodule\n"); @@ -1735,12 +1744,12 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ",\n"); } /* Simplify the port prefix, make SPICE netlist readable */ - dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE, FALSE); + dump_verilog_pb_type_ports(fp, subckt_port_prefix, 0, cur_pb_type, TRUE, FALSE, FALSE, false); /* Print Input Pad and Output Pad */ dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, stamped_iopad_cnt, iopad_verilog_model->cnt - 1, - VERILOG_PORT_INOUT, is_explicit_mapping); + VERILOG_PORT_INOUT, false); /* Print Configuration ports */ /* sram_verilog_model->cnt should be updated because all the child pbs have been dumped * stamped_sram_cnt remains the old sram_verilog_model->cnt before all the child pbs are dumped @@ -1823,7 +1832,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, } else { if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model, - FALSE, TRUE, FALSE)) { + FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) { fprintf(fp, ",\n"); } } @@ -1840,7 +1849,13 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, /* Print inputs, outputs, inouts, clocks * NO SRAMs !!! They have already been fixed in the bottom level */ - dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, FALSE); + bool is_explicit_full_name = true; + if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){ + if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){ + is_explicit_full_name = false; + } + } + dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name); /* Print I/O pads */ dump_verilog_grid_common_port(fp, iopad_verilog_model, gio_inout_prefix, @@ -1871,7 +1886,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, dump_verilog_formal_verification_sram_ports(fp, cur_sram_orgz_info, stamped_sram_cnt, stamped_sram_cnt + child_pb_num_conf_bits - 1, - VERILOG_PORT_CONKT, false); + VERILOG_PORT_CONKT, is_explicit_mapping); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } @@ -2008,7 +2023,8 @@ void dump_verilog_grid_pins(FILE* fp, int y, boolean top_level, boolean dump_port_type, - boolean dump_last_comma) { + boolean dump_last_comma, + bool is_explicit_mapping) { int iheight, side, ipin, class_id; int side_pin_index; t_type_ptr type_descriptor = grid[x][y].type; @@ -2063,7 +2079,14 @@ void dump_verilog_grid_pins(FILE* fp, } } /* This pin appear at this side! */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s_height_%d__pin_%d_(", + convert_side_index_to_string(side), iheight, ipin); + } fprintf(fp, " %s", gen_verilog_grid_one_pin_name(x, y, iheight, side, ipin, top_level)); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* Update counter */ num_dumped_port++; side_pin_index++; @@ -2093,8 +2116,10 @@ void dump_verilog_grid_pins(FILE* fp, void dump_verilog_io_grid_pins(FILE* fp, int x, int y, boolean top_level, + int border_side, boolean dump_port_type, - boolean dump_last_comma) { + boolean dump_last_comma, + bool is_explicit_mapping) { int iheight, side, ipin; int side_pin_index; t_type_ptr type_descriptor = grid[x][y].type; @@ -2156,7 +2181,14 @@ void dump_verilog_io_grid_pins(FILE* fp, } } /* This pin appear at this side! */ + if (true == is_explicit_mapping) { + fprintf(fp, ".%s_height_%d__pin_%d_(", + convert_side_index_to_string(border_side), iheight, ipin); + } fprintf(fp, " %s", gen_verilog_grid_one_pin_name(x, y, iheight, side, ipin, top_level)); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* Update counter */ num_dumped_port++; side_pin_index++; @@ -2581,9 +2613,9 @@ void dump_verilog_physical_grid_blocks(t_sram_orgz_info* cur_sram_orgz_info, /* Pins */ /* Special Care for I/O grid */ if (IO_TYPE == grid[ix][iy].type) { - dump_verilog_io_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE); + dump_verilog_io_grid_pins(fp, ix, iy, FALSE, 0, TRUE, FALSE,is_explicit_mapping); } else { - dump_verilog_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE); + dump_verilog_grid_pins(fp, ix, iy, FALSE, TRUE, FALSE, is_explicit_mapping); } /* IO PAD */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h index 25ffcd85d..e7df65069 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.h @@ -32,7 +32,8 @@ void dump_verilog_pb_type_ports(FILE* fp, t_pb_type* cur_pb_type, boolean dump_port_type, boolean dump_last_comma, - boolean require_explicit_port_map); + boolean require_explicit_port_map, + bool is_full_name); void dump_verilog_dangling_des_pb_graph_pin_interc(FILE* fp, t_pb_graph_pin* des_pb_graph_pin, @@ -111,13 +112,16 @@ void dump_verilog_grid_pins(FILE* fp, int x, int y, boolean top_level, boolean dump_port_type, - boolean dump_last_comma); + boolean dump_last_comma, + bool is_explicit_mapping); void dump_verilog_io_grid_pins(FILE* fp, int x, int y, boolean top_level, + int border_side, boolean dump_port_type, - boolean dump_last_comma); + boolean dump_last_comma, + bool is_explicit_mapping); char* get_grid_block_subckt_name(int x, int y, diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index 3354a8938..24c46587b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -134,8 +134,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); /* print ports --> input ports */ - dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE); - + dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE, false); /* IOPADs requires a specical port to output */ if (SPICE_MODEL_IOPAD == verilog_model->type) { fprintf(fp, ",\n"); @@ -236,22 +235,21 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, /* assert */ num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); /* print ports --> input ports */ - dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, verilog_model->dump_explicit_port_map); - + dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping)); /* IOPADs requires a specical port to output */ if (SPICE_MODEL_IOPAD == verilog_model->type) { fprintf(fp, ",\n"); assert(1 == num_pad_port); assert(NULL != pad_ports[0]); /* Add explicit port mapping if required */ - if (TRUE == verilog_model->dump_explicit_port_map) { + if (true == is_explicit_mapping) { fprintf(fp, ".%s(", pad_ports[0]->lib_name); } /* Print inout port */ fprintf(fp, "%s%s[%d]", gio_inout_prefix, verilog_model->prefix, verilog_model->cnt); - if (TRUE == verilog_model->dump_explicit_port_map) { + if (true == is_explicit_mapping) { fprintf(fp, ")"); } fprintf(fp, ", "); @@ -265,7 +263,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, case SPICE_SRAM_SCAN_CHAIN: /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -275,7 +273,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 0, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { fprintf(fp, ")"); } @@ -286,7 +284,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ", "); /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -296,14 +294,14 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 1, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { fprintf(fp, ")"); } break; case SPICE_SRAM_MEMORY_BANK: /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -313,7 +311,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 0, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { fprintf(fp, ")"); } /* Check if we have an inverterd prefix */ @@ -323,7 +321,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ", "); /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -333,7 +331,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 1, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (TRUE == verilog_model->dump_explicit_port_map)) { + && (true == is_explicit_mapping)) { fprintf(fp, ")"); } break; @@ -531,7 +529,7 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ",\n"); } /* Print inputs, outputs, inouts, clocks, NO SRAMs*/ - dump_verilog_pb_type_ports(fp, port_prefix, 0, cur_pb_type, TRUE, TRUE, FALSE); + dump_verilog_pb_type_ports(fp, port_prefix, 0, cur_pb_type, TRUE, TRUE, FALSE, false); /* Print SRAM ports */ cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c index eced18e87..2203641fb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c @@ -2101,7 +2101,7 @@ void dump_verilog_routing_switch_box_unique_module(t_sram_orgz_info* cur_sram_or rr_gsb.get_sb_conf_bits_lsb(), rr_gsb.get_sb_conf_bits_msb(), VERILOG_PORT_INPUT, - is_explicit_mapping); + false); fprintf(fp, "\n"); fprintf(fp, "`endif\n"); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c index b91ffc3e6..e0f09aebd 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c @@ -3088,7 +3088,7 @@ void dump_verilog_submodule_one_lut(FILE* fp, input_port[0]->prefix); /* Connect MUX inverted configuration port to inverted LUT inputs */ if (true == is_explicit_mapping) { - fprintf(fp, "), sram_inv("); + fprintf(fp, "), .sram_inv("); } else { fprintf(fp, ", "); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c index f0edb1578..61e8981ae 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c @@ -396,9 +396,9 @@ void dump_verilog_defined_one_grid(t_sram_orgz_info* cur_sram_orgz_info, } if (IO_TYPE == grid[ix][iy].type) { - dump_verilog_io_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE); + dump_verilog_io_grid_pins(fp, ix, iy, TRUE, 0, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping)); } else { - dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE); + dump_verilog_grid_pins(fp, ix, iy, TRUE, FALSE, FALSE, is_explicit_mapping); } /* IO PAD */ @@ -1474,8 +1474,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->input_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_", convert_side_index_to_string(border_side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } side_pin_index++; dump_pin_cnt++; } @@ -1497,8 +1504,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->output_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_", convert_side_index_to_string(border_side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } side_pin_index++; dump_pin_cnt++; } @@ -1520,8 +1534,15 @@ void dump_compact_verilog_io_grid_block_subckt_pins(FILE* fp, if (0 < dump_pin_cnt) { fprintf(fp, ",\n"); } + if (true == is_explicit_mapping) { + fprintf(fp, ".%s (", + gen_verilog_one_pb_type_pin_name(chomp_verilog_prefix(top_pb_graph_node->pb_type->name), top_pb_graph_node->clock_pins[iport]->port, ipin)); + } fprintf(fp, "%s_height_%d__pin_%d_", convert_side_index_to_string(border_side), pin_height, grid_pin_index); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } side_pin_index++; dump_pin_cnt++; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index 90a010607..d2da736c1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -806,16 +806,14 @@ int rec_dump_verilog_spice_model_lib_global_ports(FILE* fp, cur_spice_model_port->lib_name); } else { /* Add explicit port mapping if required */ - if ((TRUE == require_explicit_port_map) - && (TRUE == cur_spice_model->dump_explicit_port_map)) { + if (TRUE == require_explicit_port_map) { fprintf(fp, ".%s(", cur_spice_model_port->lib_name); } fprintf(fp, "%s[0:%d]", cur_spice_model_port->lib_name, cur_spice_model_port->size - 1); - if ((TRUE == require_explicit_port_map) - && (TRUE == cur_spice_model->dump_explicit_port_map)) { + if (TRUE == require_explicit_port_map) { fprintf(fp, ")"); } } @@ -902,8 +900,7 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, cur_spice_model_port->prefix); } else { /* Add explicit port mapping if required */ - if ((TRUE == require_explicit_port_map) - && (TRUE == cur_spice_model->dump_explicit_port_map)) { + if (TRUE == require_explicit_port_map ) { fprintf(fp, ".%s(", /* cur_spice_model_port->lib_name); /* Old version*/ cur_spice_model_port->prefix); @@ -911,8 +908,7 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix, cur_spice_model_port->size - 1); - if ((TRUE == require_explicit_port_map) - && (TRUE == cur_spice_model->dump_explicit_port_map)) { + if (TRUE == require_explicit_port_map) { fprintf(fp, ")"); } } @@ -2736,9 +2732,15 @@ void dump_verilog_grid_common_port(FILE* fp, t_spice_model* cur_verilog_model, /*Malloc and generate the full name of port */ port_full_name = (char*)my_malloc(sizeof(char)*(strlen(general_port_prefix) + strlen(cur_verilog_model->prefix) + 1)); sprintf(port_full_name, "%s%s", general_port_prefix, cur_verilog_model->prefix); - fprintf(fp, ",\n"); + if (true == is_explicit_mapping) { + fprintf(fp, ".%s(", + port_full_name); + } dump_verilog_generic_port(fp, dump_port_type, port_full_name, msb, lsb); + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } /* Free */ /* Local variables such as port1_name and port2 name are automatically freed */ @@ -3099,6 +3101,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp, int num_bl_per_sram = 0; int num_wl_per_sram = 0; + int iport = 0; /* Check the file handler*/ if (NULL == fp) { @@ -3201,75 +3204,99 @@ void dump_verilog_mem_sram_submodule(FILE* fp, if (SPICE_MODEL_MUX == cur_verilog_model->type) { /* Input of Scan-chain DFF, should be connected to the output of its precedent */ if (true == is_explicit_mapping) { + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[0].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, -1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } - fprintf(fp, ", \n"); // + fprintf(fp, ", \n"); /* Output of Scan-chain DFF, should be connected to the output of its successor */ + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } if (true == is_explicit_mapping) { fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[1].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, 0, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } - fprintf(fp, ", \n"); // + fprintf(fp, ", \n"); + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } if (true == is_explicit_mapping) { fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[2].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info, cur_verilog_model, mux_size, lsb, msb, 1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } break; } /* Input of Scan-chain DFF, should be connected to the output of its precedent */ if (true == is_explicit_mapping) { + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[0].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, -1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } - fprintf(fp, ", \n"); // + fprintf(fp, ", \n"); /* Output of Scan-chain DFF, should be connected to the output of its successor */ if (true == is_explicit_mapping) { + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[1].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, 0, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } - fprintf(fp, ", \n"); // + fprintf(fp, ", \n"); if (true == is_explicit_mapping) { + while(TRUE == cur_sram_verilog_model->ports[iport].is_global) { + iport++; + } fprintf(fp, ".%s(", - cur_sram_verilog_model->ports[2].prefix); + cur_sram_verilog_model->ports[iport].prefix); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, lsb, msb, 1, VERILOG_PORT_CONKT); if (true == is_explicit_mapping) { + iport++; fprintf(fp, ")"); } break; diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh old mode 100644 new mode 100755 index 8007363cf..b31d5efa2 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -35,6 +35,8 @@ cd - # Run VPR ./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping +#/research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.blif --full_stats --nodisp --activity_file /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/benchmarks/Blif/Test_Modes/test_modes.act --fpga_verilog --fpga_verilog_dir /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/vpr7_x2p/vpr/test_modes_Verilog --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/benchmarks/Verilog/Test_Modes/test_modes.v --fpga_verilog_print_user_defined_template --route_chan_width 200 --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties /research/ece/lnis/USERS/chauviere/wk_Baudouin/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping + cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path cd - From 589f58b55ec6919c3c5da978ce9c375094692cad Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Tue, 9 Jul 2019 09:18:06 -0600 Subject: [PATCH 48/84] Regression test succeeded --- .../arch/template/k6_N10_sram_chain_HC_template.xml | 4 ++-- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c | 4 ++-- vpr7_x2p/vpr/VerilogNetlists/io.v | 10 +++++----- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml index 06e75d911..8dca26477 100644 --- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml @@ -336,8 +336,8 @@ - - + + diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 6fa1ad6da..25c162c48 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -1851,9 +1851,9 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info, */ bool is_explicit_full_name = true; if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){ - if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){ + /*if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){ is_explicit_full_name = false; - } + }TEST*/ } dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name); /* Print I/O pads */ diff --git a/vpr7_x2p/vpr/VerilogNetlists/io.v b/vpr7_x2p/vpr/VerilogNetlists/io.v index ab451b2b7..9fccdd23d 100644 --- a/vpr7_x2p/vpr/VerilogNetlists/io.v +++ b/vpr7_x2p/vpr/VerilogNetlists/io.v @@ -3,14 +3,14 @@ //------ Author: Xifan TANG -----// module iopad( //input zin, // Set output to be Z -input dout, // Data output -output din, // Data input +input outpad, // Data output +output inpad, // Data input inout pad, // bi-directional pad -input direction // enable signal to control direction of iopad +input en // enable signal to control direction of iopad //input direction_inv // enable signal to control direction of iopad ); //----- when direction enabled, the signal is propagated from pad to din - assign din = direction ? pad : 1'bz; + assign inpad = en ? pad : 1'bz; //----- when direction is disabled, the signal is propagated from dout to pad - assign pad = direction ? 1'bz : dout; + assign pad = en ? 1'bz : outpad; endmodule From 0da9e50b2047b7c69a249ee09b9bd765e45d40c2 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Tue, 9 Jul 2019 11:58:39 -0600 Subject: [PATCH 49/84] Modify readme --- README.md | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/README.md b/README.md index ed700daca..aa61fff7c 100644 --- a/README.md +++ b/README.md @@ -27,18 +27,11 @@ The different ways of compiling can be found in the **./compilation** folder. ## Documentation OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) includes tutorials, descriptions of the design flow, and tool options. -## Examples +## Tutorial -You can find in the folder **./examples**. This will help you get in touch with the software and test different configurations to see how FPGA-SPICE reacts to them. - -./example_x.sh allows to launch the script linked to example_x.xml and .blif. - -In all the examples, the CLBs are composed of LUTs, FFs and MUXs as a base. - -Example 1 shows a very basic design with only 4 inputs on the LUTs, a FF and a MUX in the CLB (only 1). It implements an inverter and allows the user to see the very core of the .xml file. - -Example 2 increases the complexity by having 3x3 CLBs and 4 slices per CLB. The slices provide a feedback to the input structure and input MUXs are added. +You can find in the folder **./tutorials**. This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them. +Through this tutorial users can learn how to use the flow and set the dependancies. From e86c9b9bfc1dcf67cddecd5b0adc1f7839f6cd3b Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Tue, 9 Jul 2019 14:28:14 -0600 Subject: [PATCH 50/84] Update tutorial, readme and docker --- Dockerfile | 2 -- README.md | 3 ++- run_local.bat | 3 +-- tutorials/building.md | 52 +++++++++++++++++++++++++++++++++++++++++++ tutorials/tutorial.md | 12 +++++----- 5 files changed, 60 insertions(+), 12 deletions(-) create mode 100644 tutorials/building.md diff --git a/Dockerfile b/Dockerfile index c573dbbee..f4581d845 100755 --- a/Dockerfile +++ b/Dockerfile @@ -5,6 +5,4 @@ RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default -RUN git clone https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA -RUN cd OpenFPGA && make diff --git a/README.md b/README.md index aa61fff7c..e408da414 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,8 @@ OpenFPGA is an extension to VPR. It is an IP Verilog Generator allowing reliable ## Compilation -The different ways of compiling can be found in the **./compilation** folder. +The different ways of compiling can be found in the **./compilation** folder.
+Dependancies and help using docker can be found at **./tutorials/building.md**. **Compilation steps:** 1. Create a folder named build in OpenPFGA repository (mkdir build && cd build) diff --git a/run_local.bat b/run_local.bat index 578f750ce..0a85df473 100755 --- a/run_local.bat +++ b/run_local.bat @@ -1,2 +1 @@ -docker run -it --rm -v "%cd%":/localfile -w="/localfile/vpr7_x2p/vpr" goreganesh/open_fpga ./go_ganesh.sh -pause +docker run -it --rm -v $PWD:/localfile -w="/localfile/vpr7_x2p/vpr" open_fpga bash diff --git a/tutorials/building.md b/tutorials/building.md new file mode 100644 index 000000000..f891378ad --- /dev/null +++ b/tutorials/building.md @@ -0,0 +1,52 @@ +# How to build? + +## Dependancies + +OpenFPGA requires all the dependancies listed below: +- autoconf +- automake +- bash +- bison +- build-essential +- cmake (version 3.X at least) +- ctags +- curl +- doxygen +- flex +- fontconfig +- g++-8 +- gcc-8 +- g++-4.9 +- gcc-4.9 +- gdb +- git +- gperf +- iverilog +- libcairo2-dev +- libevent-dev +- libfontconfig1-dev +- liblist-moreutils-perl +- libncurses5-dev +- libx11-dev +- libxft-dev +- libxml++2.6-dev +- perl +- python +- texinfo +- time +- valgrind +- zip +- qt5-default + +## Docker + +If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. It can be build using the commands: +- docker build . -t open_fpga +- ./run_local.bat + +## Building + +To build the tool you have to be in OpenFPGA folder and do: +- mkdir build && cd build +- cmake .. +- make OR make -j diff --git a/tutorials/tutorial.md b/tutorials/tutorial.md index 9769f05de..7cc76342f 100644 --- a/tutorials/tutorial.md +++ b/tutorials/tutorial.md @@ -29,7 +29,7 @@ fpga_flow.pl is saved in OPENFPGAPATHKEYWORD/fpga_flow/scripts. If we look in th * pro_blif.pl: rewrite a blif which has only 3 members in a .latch module * rewrite_path_in_file.pl: target a keyword in a file and replace it -*Any script provides a help if launch without argument* +*Any script provides help if launch without argument* fpga_flow.pl has dependencies which need to be configured. They are: * configuration file, which provides dependencies path and flow type @@ -84,9 +84,9 @@ The benchmark folder contains 3 sub-folders: * **List**: contains all benchmark list files * **Verilog**: contains Verilog designs -Blif and Verilog folders are organized by folders with name of projects. **Folder, top module and top module file must share the same name.**
-The benchmark list file can contain as many benchmark as available in a same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:
-top_module/*.v,; where is the number ofchannel/wire between each blocks. +Blif and Verilog folders are organized by folders with the name of projects. **Folder, top module and top module file must share the same name.**
+The benchmark list file can contain as many benchmarks as available in the same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:
+top_module/*.v,; where is the number of channel/wire between each block. *An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt* @@ -101,8 +101,6 @@ Few options are only in fpga_flow: * **-multi_thread **: specifies number of core to use * **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist -*An example of script can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh* - - +*An script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh* From 65f696c1d76508840952077b3056f736d5442668 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2019 17:41:20 -0600 Subject: [PATCH 51/84] fix critical bugs in rectangle floorplan --- .../device/rr_graph/tileable_rr_graph_builder.cpp | 13 +++++++++---- .../vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c | 8 +++++++- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 4 ++-- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h | 4 ++-- 4 files changed, 20 insertions(+), 9 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp index fe521ffa0..3d919ecc0 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp @@ -687,10 +687,15 @@ void alloc_rr_graph_fast_lookup(const DeviceCoordinator& device_size, if ((SOURCE == type) || (OPIN == type) ) { continue; } - rr_graph->rr_node_indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * device_size.get_x()); - for (size_t i = 0; i < device_size.get_x(); ++i) { - rr_graph->rr_node_indices[type][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * device_size.get_y()); - for (size_t j = 0; j < device_size.get_y(); ++j) { + DeviceCoordinator actual_device_size(device_size); + /* Special for CHANX: we use (y,x) in allocation */ + if (CHANX == type) { + actual_device_size.rotate(); + } + rr_graph->rr_node_indices[type] = (t_ivec **) my_malloc(sizeof(t_ivec *) * actual_device_size.get_x()); + for (size_t i = 0; i < actual_device_size.get_x(); ++i) { + rr_graph->rr_node_indices[type][i] = (t_ivec *) my_malloc(sizeof(t_ivec) * actual_device_size.get_y()); + for (size_t j = 0; j < actual_device_size.get_y(); ++j) { rr_graph->rr_node_indices[type][i][j].nelem = 0; rr_graph->rr_node_indices[type][i][j].list = NULL; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index dc76ff55d..315f4f5ff 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1354,6 +1354,12 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, "Backannotated %d switch blocks.\n", (nx + 1) * (ny + 1) ); + /* End time count */ + t_end = clock(); + + run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec); + if (TRUE == output_sb_xml) { create_dir_path(sb_xml_dir); @@ -1406,7 +1412,7 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, t_end = clock(); run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; - vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniqifying took %g seconds\n", run_time_sec); + vpr_printf(TIO_MESSAGE_INFO, "Routing architecture uniqifying took %g seconds\n\n", run_time_sec); return LL_device_rr_gsb; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index f0d59fd9b..42fc21c17 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -2598,7 +2598,7 @@ void DeviceRRGSB::reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator) } /* Resize rr_switch_block array is needed*/ -void DeviceRRGSB::resize_upon_need(DeviceCoordinator& coordinator) { +void DeviceRRGSB::resize_upon_need(const DeviceCoordinator& coordinator) { if (coordinator.get_x() + 1 > rr_gsb_.size()) { rr_gsb_.resize(coordinator.get_x() + 1); @@ -2622,7 +2622,7 @@ void DeviceRRGSB::resize_upon_need(DeviceCoordinator& coordinator) { } /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ -void DeviceRRGSB::add_rr_gsb(DeviceCoordinator& coordinator, +void DeviceRRGSB::add_rr_gsb(const DeviceCoordinator& coordinator, const RRGSB& rr_gsb) { /* Resize upon needs*/ resize_upon_need(coordinator); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index d95c08d75..e87ee78c6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -353,8 +353,8 @@ class DeviceRRGSB { void set_cb_conf_bits_msb(DeviceCoordinator& coordinator, t_rr_type cb_type, size_t conf_bits_msb); /* TODO: TOBE DEPRECATED!!! conf_bits should be initialized when creating a switch block!!! */ void reserve(DeviceCoordinator& coordinator); /* Pre-allocate the rr_switch_block array that the device requires */ void reserve_sb_unique_submodule_id(DeviceCoordinator& coordinator); /* Pre-allocate the rr_sb_unique_module_id matrix that the device requires */ - void resize_upon_need(DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */ - void add_rr_gsb(DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ + void resize_upon_need(const DeviceCoordinator& coordinator); /* Resize the rr_switch_block array if needed */ + void add_rr_gsb(const DeviceCoordinator& coordinator, const RRGSB& rr_gsb); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ void build_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ void clear(); /* clean the content */ private: /* Internal cleaners */ From edfe3144c3417b848fbd19157d474616814bbfc0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2019 20:28:01 -0600 Subject: [PATCH 52/84] update profiling, found where runtime is lost --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index 315f4f5ff..d625a5375 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1324,6 +1324,10 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, clock_t t_end; float run_time_sec; + clock_t t_start_profiling; + clock_t t_end_profiling; + float run_time_sec_profiling = 0.; + /* Start time count */ t_start = clock(); @@ -1342,8 +1346,15 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, LL_num_rr_nodes, LL_rr_node, LL_rr_node_indices, num_segments, LL_rr_indexed_data); + + /* For profiling */ + t_start_profiling = clock(); /* sort drive_rr_nodes */ sort_rr_gsb_drive_rr_nodes(rr_gsb); + /* End time count */ + t_end_profiling = clock(); + run_time_sec_profiling += (float)(t_end_profiling - t_start_profiling) / CLOCKS_PER_SEC; + /* Add to device_rr_gsb */ DeviceCoordinator sb_coordinator = rr_gsb.get_sb_coordinator(); LL_device_rr_gsb.add_rr_gsb(sb_coordinator, rr_gsb); @@ -1360,6 +1371,8 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; vpr_printf(TIO_MESSAGE_INFO, "Backannotation of Switch Block took %g seconds\n\n", run_time_sec); + vpr_printf(TIO_MESSAGE_INFO, "Edge sorting for Switch Block took %g seconds\n\n", run_time_sec_profiling); + if (TRUE == output_sb_xml) { create_dir_path(sb_xml_dir); From 57ae5dbbec48eecc277525b296eb8a5d6c1533fe Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 9 Jul 2019 20:47:52 -0600 Subject: [PATCH 53/84] bug fixing for rectangle FPGA sizes --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 064cb2623..8ea7f0f6b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -986,7 +986,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or /* Get X-channel CB coordinator */ const DeviceCoordinator cbx_coordinator = rr_gsb.get_cb_coordinator(CHANX); /* X - channels [1...nx][0..ny]*/ - if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_x())) + if ((TRUE == is_cb_exist(CHANX, cbx_coordinator.get_x(), cbx_coordinator.get_y())) &&(true == rr_gsb.is_cb_exist(CHANX))) { dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANX); } @@ -994,7 +994,7 @@ void dump_compact_verilog_defined_connection_boxes(t_sram_orgz_info* cur_sram_or /* Get X-channel CB coordinator */ const DeviceCoordinator cby_coordinator = rr_gsb.get_cb_coordinator(CHANY); /* Y - channels [1...ny][0..nx]*/ - if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_x())) + if ((TRUE == is_cb_exist(CHANY, cby_coordinator.get_x(), cby_coordinator.get_y())) &&(true == rr_gsb.is_cb_exist(CHANY))) { dump_compact_verilog_defined_one_connection_box(cur_sram_orgz_info, fp, rr_gsb, CHANY); } From 20ce020eb6ad17338c9d73a298903d518bb25469 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 10 Jul 2019 10:03:30 -0600 Subject: [PATCH 54/84] Tutorial rewrite draft 1 --- fpga_flow/tuto_fpga_flow.sh | 8 +- .../{tutorial.md => fpga_flow/how2use.md} | 56 +++++++------- tutorials/fpga_flow/options.md | 73 +++++++++++++++++++ tutorials/tutorial_index.md | 26 +++++++ 4 files changed, 128 insertions(+), 35 deletions(-) rename tutorials/{tutorial.md => fpga_flow/how2use.md} (78%) create mode 100644 tutorials/fpga_flow/options.md create mode 100644 tutorials/tutorial_index.md diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh index 7bfefb66d..c35e9cbf9 100644 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -18,10 +18,10 @@ rm -rf ${pwd_path}/results_OpenPithon cd ${pwd_path}/scripts # Replace keyword in config and architecture files -perl rewrite_path_in_file -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file -perl rewrite_path_in_file -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file -perl rewrite_path_in_file -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file -perl rewrite_path_in_file -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file +perl rewrite_path_in_file.pl -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file +perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file +perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file +perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file # SRAM FPGA diff --git a/tutorials/tutorial.md b/tutorials/fpga_flow/how2use.md similarity index 78% rename from tutorials/tutorial.md rename to tutorials/fpga_flow/how2use.md index 7cc76342f..b0547bf48 100644 --- a/tutorials/tutorial.md +++ b/tutorials/fpga_flow/how2use.md @@ -1,22 +1,31 @@ -# Tutorial +# FPGA flow -This tutorial purpose it to clarify how to use: -1. The full flow using fpga_flow.pl script -2. Architecture customization +This tutorial will help the user to understand how to use OpenFPGA flow.
+During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations). -Some keywords will be used during this tutorial: -* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path +## Running fpga_flow.pl -### Folder organization +A script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh. -OpenFPGA repository is organized as follow: -* **abc**: open source synthesys tool -* **ace2**: abc extension generating .act files -* **vpr7_x2p**: sources of modified vpr -* **yosys**: opensource synthesys tool -* **fpga_flow**: scripts and dependencies to run the complete flow +**Experiment**
+cd fpga_flow
+./tuto_fpga_flow.sh
-## 1. FPGA flow +**Explanation**
+By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.
+When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.
+The second one is **fpga_flow.pl**. This script launch OpenFPGA flow andcan be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md) + +Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".
+Few options are only in fpga_flow: +* **-N**: number of LUT per CLB +* **-K**: LUT size/ number of input +* **-rpt **: specifies wherever fpga_flow will write its report +* **-ace_d **: specifies inputs average probability of switching +* **-multi_thread **: specifies number of core to use +* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist + +** The folder is organized as follow: * **arch**: contains architectures description files @@ -35,7 +44,7 @@ fpga_flow.pl has dependencies which need to be configured. They are: * configuration file, which provides dependencies path and flow type * benchmark list file -### a. Configuration file +## Configuration file In this file paths have to be full path. Relative path could lead to errors.
The file is organized in 3 parts: @@ -77,7 +86,7 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St *An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf* -### b. Benchmark list +## Benchmark list The benchmark folder contains 3 sub-folders: * **Blif**: contains .blif and .act of benchmarks @@ -89,18 +98,3 @@ The benchmark list file can contain as many benchmarks as available in the same top_module/*.v,; where is the number of channel/wire between each block. *An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt* - -### c. Running fpga_flow.pl - -Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".
-Few options are only in fpga_flow: -* **-N**: number of LUT per CLB -* **-K**: LUT size/ number of input -* **-rpt **: specifies wherever fpga_flow will write its report -* **-ace_d **: specifies inputs average probability of switching -* **-multi_thread **: specifies number of core to use -* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist - -*An script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh* - - diff --git a/tutorials/fpga_flow/options.md b/tutorials/fpga_flow/options.md new file mode 100644 index 000000000..6f0b97366 --- /dev/null +++ b/tutorials/fpga_flow/options.md @@ -0,0 +1,73 @@ +# OpenFPGA flow options + +Usage -> **fpga_flow *-options * **
+Mandatory options:
+- -conf : *specify the basic configuration files for fpga_flow* +- -benchmark : *the configuration file contains benchmark file names* +- -rpt : *CSV file consists of data* +- -N : *N-LUT/Matrix* +Other Options:
+## General +- -matlab_rpt : *.m file consists of data compatible to matlab scripts. Specify the data name to be appeared in the script* +- -I : *Number of inputs of a CLB, mandatory when mpack1 flow is chosen* +- -K : *K-LUT, mandatory when standard flow is chosen* +- -M : *M-Matrix, mandatory when mpack1 flow is chosen* +- -power : *run power estimation oriented flow* +- -black_box_ace: *run activity estimation with black box support. It increase the power.* +- -remove_designs: *remove all the old results.* +- -multi_thread : *turn on the mutli-thread mode, specify the number of threads* +- -multi_task : *turn on the mutli-task mode* +- -parse_results_only : *only parse the flow results and write CSV report.* +- -debug : *debug mode* +- -help : *print usage* +## ODIN II +- -min_hard_adder_size: *min. size of hard adder in carry chain defined in Arch XML.(Default:1)* +- -mem_size: *size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen* +- -odin2_carry_chain_support: *turn on the carry_chain support only valid for VTR_MCCL/VTR_MIG_MCCL flow * +## ABC +- -abc_scl : *run ABC optimization for sequential circuits, mandatory when VTR flow is selected.* +- -abc_verilog_rewrite : *run ABC to convert a blif netlist to a Verilog netlist.* +## ACE +- -ace_p : *specify the default signal probablity of PIs in ACE2.* +- -ace_d : *specify the default signal density of PIs in ACE2.* +## VPR - Original Version +- -vpr_timing_pack_off : *turn off the timing-driven pack for vpr.* +- -vpr_place_clb_pin_remap: *turn on place_clb_pin_remap in VPR.* +- -vpr_max_router_iteration : *specify the max router iteration in VPR.* +- -vpr_route_breadthfirst : *use the breadth-first routing algorithm of VPR.* +- -vpr_use_tileable_route_chan_width: *turn on the conversion to tileable_route_chan_width in VPR.* +- -min_route_chan_width : *turn on routing with * min_route_chan_width.* +- -fix_route_chan_width : *turn on routing with a fixed route_chan_width, defined in benchmark configuration file.* +## VPR - FPGA-X2P Extension +- -vpr_fpga_x2p_rename_illegal_port : *turn on renaming illegal ports option of VPR FPGA SPICE* +- -vpr_fpga_x2p_signal_density_weight : *specify the option signal_density_weight of VPR FPGA SPICE* +- -vpr_fpga_x2p_sim_window_size : *specify the option sim_window_size of VPR FPGA SPICE* +- -vpr_fpga_x2p_compact_routing_hierarchy : *allow routing block modularization* +## VPR - FPGA-SPICE Extension +- -vpr_fpga_spice : *turn on SPICE netlists print-out in VPR, specify a task file* +- -vpr_fpga_spice_sim_mt_num : *specify the option sim_mt_num of VPR FPGA SPICE* +- -vpr_fpga_spice_print_component_tb : *print component-level testbenches in VPR FPGA SPICE* +- -vpr_fpga_spice_print_grid_tb : *print Grid-level testbenches in VPR FPGA SPICE* +- -vpr_fpga_spice_print_top_tb : *print full-chip testbench in VPR FPGA SPICE* +- -vpr_fpga_spice_leakage_only : *turn on leakage_only mode in VPR FPGA SPICE* +- -vpr_fpga_spice_parasitic_net_estimation_off : *turn off parasitic_net_estimation in VPR FPGA SPICE* +- -vpr_fpga_spice_testbench_load_extraction_off : *turn off testbench_load_extraction in VPR FPGA SPICE* +- -vpr_fpga_spice_simulator_path : *Specify simulator path* +## VPR - FPGA-Verilog Extension +- -vpr_fpga_verilog : *turn on Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog_dir : *provides the path where generated verilog files will be written* +- -vpr_fpga_verilog_include_timing : *turn on printing delay specification in Verilog files* +- -vpr_fpga_verilog_include_signal_init : *turn on printing signal initialization in Verilog files* +- -vpr_fpga_verilog_print_autocheck_top_testbench: *turn on printing autochecked top-level testbench for Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog_formal_verification_top_netlist : *turn on printing formal top Verilog files* +- -vpr_fpga_verilog_include_icarus_simulator : *Add syntax and definition required to use Icarus Verilog simulator* +- -vpr_fpga_verilog_print_user_defined_template : *Generates a template of hierarchy modules and their port mapping* +- -vpr_fpga_verilog_print_report_timing_tcl : *Generates tcl script useful for timing report generation* +- -vpr_fpga_verilog_report_timing_rpt_path : *Specify path for report timing* +- -vpr_fpga_verilog_print_sdc_pnr : *Generates sdc file to constraint Hardware P&R* +- -vpr_fpga_verilog_print_sdc_analysis : *Generates sdc file to do STA* +- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog_print_modelsim_autodeck : *turn on printing modelsim simulation script* +## VPR - FPGA-Bitstream Extension +- -vpr_fpga_bitstream_generator: *turn on FPGA-SPICE bitstream generator* diff --git a/tutorials/tutorial_index.md b/tutorials/tutorial_index.md new file mode 100644 index 000000000..c6013d6dc --- /dev/null +++ b/tutorials/tutorial_index.md @@ -0,0 +1,26 @@ +# Tutorial introduction + +OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.
+Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.

+These tutorials are organized as follow: +* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md) +* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md) +* Architecture modification + +## Folder organization + +OpenFPGA repository is organized as follow: +* **abc**: open source synthesys tool +* **ace2**: abc extension generating .act files +* **vpr7_x2p**: sources of modified vpr +* **yosys**: opensource synthesys tool +* **fpga_flow**: scripts and dependencies to run the complete flow + +## Tips and informations + +Some keywords will be used during this tutorial: +* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path + + + + From 905293820f887ecce61f2b7468e156e7a3b05f24 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 10 Jul 2019 10:37:05 -0600 Subject: [PATCH 55/84] Draft2 --- fpga_flow/configs/tutorial/tuto.conf | 34 ++++++++++++++-------------- fpga_flow/tuto_fpga_flow.sh | 3 ++- tutorials/fpga_flow/how2use.md | 6 +++-- tutorials/fpga_flow/options.md | 21 +++++++++-------- 4 files changed, 34 insertions(+), 30 deletions(-) mode change 100644 => 100755 fpga_flow/tuto_fpga_flow.sh diff --git a/fpga_flow/configs/tutorial/tuto.conf b/fpga_flow/configs/tutorial/tuto.conf index 85104383a..e154662e4 100644 --- a/fpga_flow/configs/tutorial/tuto.conf +++ b/fpga_flow/configs/tutorial/tuto.conf @@ -1,27 +1,27 @@ # Standard Configuration Example [dir_path] -script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/ -benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC -yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys -odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe -cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit -abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc -abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc -abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc -mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1 -m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net -mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2 -vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr -rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial -ace_path = OPENFPGAPATHKEYWORD/ace2/ace +script_base = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/scripts/ +benchmark_dir = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC +yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/yosys/yosys +odin2_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/odin2.exe +cirkit_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/cirkit +abc_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/yosys/yosys-abc +abc_mccl_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/abc_with_bb_support/abc +abc_with_bb_support_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/abc_with_bb_support/abc +mpack1_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/mpack1 +m2net_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/m2net +mpack2_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/mpack2 +vpr_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/vpr +rpt_dir = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/results_tutorial +ace_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/ace2/ace [flow_conf] flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr -vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml +vpr_arch = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +m2net_conf = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf mpack2_arch = K6_pattern7_I24.arch -power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK +power_tech_xml = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK [csv_tags] mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh old mode 100644 new mode 100755 index c35e9cbf9..f7655cb38 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -7,8 +7,9 @@ task_name="tuto" config_file="$pwd_path/configs/tutorial/${task_name}.conf" bench_txt="$pwd_path/benchmarks/List/tuto_benchmark.txt" rpt_file="$pwd_path/csv_rpts/fpga_spice/${task_name}.csv" - verilog_path="${pwd_path}/${task_name}_Verilog" +architecture_generated="${pwd_path}/arch/generated/k6_N10_sram_chain_HC.xml" +architecture_template="${pwd_path}/arch/template/k6_N10_sram_chain_HC_template.xml" ff_keyword="FFPATHKEYWORD" ff_path="${pwd_path}/vpr7_x2p/vpr/Verilognetlists/ff.v" diff --git a/tutorials/fpga_flow/how2use.md b/tutorials/fpga_flow/how2use.md index b0547bf48..a76fa8b9c 100644 --- a/tutorials/fpga_flow/how2use.md +++ b/tutorials/fpga_flow/how2use.md @@ -7,11 +7,13 @@ During this tutorial we consider the user start in the OpenFPGA folder and we'll A script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh. -**Experiment**
+### Experiment + cd fpga_flow
./tuto_fpga_flow.sh
-**Explanation**
+### Explanation + By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.
When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.
The second one is **fpga_flow.pl**. This script launch OpenFPGA flow andcan be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md) diff --git a/tutorials/fpga_flow/options.md b/tutorials/fpga_flow/options.md index 6f0b97366..ff5498d93 100644 --- a/tutorials/fpga_flow/options.md +++ b/tutorials/fpga_flow/options.md @@ -6,8 +6,9 @@ Mandatory options:
- -benchmark : *the configuration file contains benchmark file names* - -rpt : *CSV file consists of data* - -N : *N-LUT/Matrix* -Other Options:
-## General + +## Other Options: +### General - -matlab_rpt : *.m file consists of data compatible to matlab scripts. Specify the data name to be appeared in the script* - -I : *Number of inputs of a CLB, mandatory when mpack1 flow is chosen* - -K : *K-LUT, mandatory when standard flow is chosen* @@ -20,17 +21,17 @@ Other Options:
- -parse_results_only : *only parse the flow results and write CSV report.* - -debug : *debug mode* - -help : *print usage* -## ODIN II +### ODIN II - -min_hard_adder_size: *min. size of hard adder in carry chain defined in Arch XML.(Default:1)* - -mem_size: *size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen* - -odin2_carry_chain_support: *turn on the carry_chain support only valid for VTR_MCCL/VTR_MIG_MCCL flow * -## ABC +### ABC - -abc_scl : *run ABC optimization for sequential circuits, mandatory when VTR flow is selected.* - -abc_verilog_rewrite : *run ABC to convert a blif netlist to a Verilog netlist.* -## ACE +### ACE - -ace_p : *specify the default signal probablity of PIs in ACE2.* - -ace_d : *specify the default signal density of PIs in ACE2.* -## VPR - Original Version +### VPR - Original Version - -vpr_timing_pack_off : *turn off the timing-driven pack for vpr.* - -vpr_place_clb_pin_remap: *turn on place_clb_pin_remap in VPR.* - -vpr_max_router_iteration : *specify the max router iteration in VPR.* @@ -38,12 +39,12 @@ Other Options:
- -vpr_use_tileable_route_chan_width: *turn on the conversion to tileable_route_chan_width in VPR.* - -min_route_chan_width : *turn on routing with * min_route_chan_width.* - -fix_route_chan_width : *turn on routing with a fixed route_chan_width, defined in benchmark configuration file.* -## VPR - FPGA-X2P Extension +### VPR - FPGA-X2P Extension - -vpr_fpga_x2p_rename_illegal_port : *turn on renaming illegal ports option of VPR FPGA SPICE* - -vpr_fpga_x2p_signal_density_weight : *specify the option signal_density_weight of VPR FPGA SPICE* - -vpr_fpga_x2p_sim_window_size : *specify the option sim_window_size of VPR FPGA SPICE* - -vpr_fpga_x2p_compact_routing_hierarchy : *allow routing block modularization* -## VPR - FPGA-SPICE Extension +### VPR - FPGA-SPICE Extension - -vpr_fpga_spice : *turn on SPICE netlists print-out in VPR, specify a task file* - -vpr_fpga_spice_sim_mt_num : *specify the option sim_mt_num of VPR FPGA SPICE* - -vpr_fpga_spice_print_component_tb : *print component-level testbenches in VPR FPGA SPICE* @@ -53,7 +54,7 @@ Other Options:
- -vpr_fpga_spice_parasitic_net_estimation_off : *turn off parasitic_net_estimation in VPR FPGA SPICE* - -vpr_fpga_spice_testbench_load_extraction_off : *turn off testbench_load_extraction in VPR FPGA SPICE* - -vpr_fpga_spice_simulator_path : *Specify simulator path* -## VPR - FPGA-Verilog Extension +### VPR - FPGA-Verilog Extension - -vpr_fpga_verilog : *turn on Verilog Generator of VPR FPGA SPICE* - -vpr_fpga_verilog_dir : *provides the path where generated verilog files will be written* - -vpr_fpga_verilog_include_timing : *turn on printing delay specification in Verilog files* @@ -69,5 +70,5 @@ Other Options:
- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE* - -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE* - -vpr_fpga_verilog_print_modelsim_autodeck : *turn on printing modelsim simulation script* -## VPR - FPGA-Bitstream Extension +### VPR - FPGA-Bitstream Extension - -vpr_fpga_bitstream_generator: *turn on FPGA-SPICE bitstream generator* From cb782a0e9fdec08a2e64c48bdbd63132b8ae04a5 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 10 Jul 2019 11:00:36 -0600 Subject: [PATCH 56/84] Draft 3 --- tutorials/fpga_flow/folder_organization.md | 23 +++++++++++++++++++++ tutorials/fpga_flow/how2use.md | 24 ++-------------------- tutorials/fpga_flow/options.md | 9 ++++---- 3 files changed, 30 insertions(+), 26 deletions(-) create mode 100644 tutorials/fpga_flow/folder_organization.md diff --git a/tutorials/fpga_flow/folder_organization.md b/tutorials/fpga_flow/folder_organization.md new file mode 100644 index 000000000..07f630db8 --- /dev/null +++ b/tutorials/fpga_flow/folder_organization.md @@ -0,0 +1,23 @@ +# fpga_flow folder organization + +The fpga_flow folder is organized as follow: +* [**arch**]: contains architectures description files +* [**benchmarks**]: contains Verilog and blif benchmarks + lists +* [**configs**]: contains configuration files to run fpga_flow.pl +* [**scripts**]: contains all the scripts required to run the flow +* [**tech**]: contains xml tech files for power estimation + +## arch +In this folder are saved the architecture files. These files are Hardware description for the FPGA written in XML. This folder contains 3 sub-folders: +- **fpga_spice**: contains existing architecture ready to use. +- **template**: contains template architecture which contain keyword to replace +- **generated**: empty at the beginning, will host rewritten template + +## benchmarks +This folder contains benchmarks to implement in the FPGA. + +## configs + +## scripts + +## tech diff --git a/tutorials/fpga_flow/how2use.md b/tutorials/fpga_flow/how2use.md index a76fa8b9c..000aee364 100644 --- a/tutorials/fpga_flow/how2use.md +++ b/tutorials/fpga_flow/how2use.md @@ -1,7 +1,7 @@ # FPGA flow This tutorial will help the user to understand how to use OpenFPGA flow.
-During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations). +During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/folder_organization.md). ## Running fpga_flow.pl @@ -16,29 +16,9 @@ cd fpga_flow
By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.
When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.
-The second one is **fpga_flow.pl**. This script launch OpenFPGA flow andcan be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md) +The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md). In this example we activated all FPGA-Verilog options -Once the configuration is done, we can select which option we want to enable in fpga_flow. fpga_flow options don't exactly have the name of those listed in the [documentation](https://openfpga.readthedocs.io/en/master/fpga_verilog/command_line_usage.html "documentation"), which are used on the modifed version of vpr. Indeed, where vpr will take an option as "**--fpga_XXX**" fpgs_flow will call it "**-vpr_fpga_XXX**".
-Few options are only in fpga_flow: -* **-N**: number of LUT per CLB -* **-K**: LUT size/ number of input -* **-rpt **: specifies wherever fpga_flow will write its report -* **-ace_d **: specifies inputs average probability of switching -* **-multi_thread **: specifies number of core to use -* **-end_flow_with_test**: uses Icarus Verilog to verify generated netlist -** - -The folder is organized as follow: -* **arch**: contains architectures description files -* **benchmarks**: contains Verilog and blif benchmarks + lists -* **configs**: contains configuration files to run fpga_flow.pl -* **scripts**: contains all the scripts required to run the flow -* **tech**: contains xml tech files for power estimation - -fpga_flow.pl is saved in OPENFPGAPATHKEYWORD/fpga_flow/scripts. If we look in this folder, we can find some other scripts as: -* pro_blif.pl: rewrite a blif which has only 3 members in a .latch module -* rewrite_path_in_file.pl: target a keyword in a file and replace it *Any script provides help if launch without argument* diff --git a/tutorials/fpga_flow/options.md b/tutorials/fpga_flow/options.md index ff5498d93..38932d0c1 100644 --- a/tutorials/fpga_flow/options.md +++ b/tutorials/fpga_flow/options.md @@ -21,6 +21,7 @@ Mandatory options:
- -parse_results_only : *only parse the flow results and write CSV report.* - -debug : *debug mode* - -help : *print usage* +- -end_flow_with_test: *Uses Icarus Verilog simulator to verified bencmark implementation* ### ODIN II - -min_hard_adder_size: *min. size of hard adder in carry chain defined in Arch XML.(Default:1)* - -mem_size: *size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen* @@ -55,11 +56,11 @@ Mandatory options:
- -vpr_fpga_spice_testbench_load_extraction_off : *turn off testbench_load_extraction in VPR FPGA SPICE* - -vpr_fpga_spice_simulator_path : *Specify simulator path* ### VPR - FPGA-Verilog Extension -- -vpr_fpga_verilog : *turn on Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog : *turn on OpenFPGA Verilog Generator* - -vpr_fpga_verilog_dir : *provides the path where generated verilog files will be written* - -vpr_fpga_verilog_include_timing : *turn on printing delay specification in Verilog files* - -vpr_fpga_verilog_include_signal_init : *turn on printing signal initialization in Verilog files* -- -vpr_fpga_verilog_print_autocheck_top_testbench: *turn on printing autochecked top-level testbench for Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog_print_autocheck_top_testbench: *turn on printing autochecked top-level testbench for OpenFPGA Verilog Generator* - -vpr_fpga_verilog_formal_verification_top_netlist : *turn on printing formal top Verilog files* - -vpr_fpga_verilog_include_icarus_simulator : *Add syntax and definition required to use Icarus Verilog simulator* - -vpr_fpga_verilog_print_user_defined_template : *Generates a template of hierarchy modules and their port mapping* @@ -67,8 +68,8 @@ Mandatory options:
- -vpr_fpga_verilog_report_timing_rpt_path : *Specify path for report timing* - -vpr_fpga_verilog_print_sdc_pnr : *Generates sdc file to constraint Hardware P&R* - -vpr_fpga_verilog_print_sdc_analysis : *Generates sdc file to do STA* -- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE* -- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE* +- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for OpenFPGA Verilog Generator* +- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in OpenFPGA Verilog Generator* - -vpr_fpga_verilog_print_modelsim_autodeck : *turn on printing modelsim simulation script* ### VPR - FPGA-Bitstream Extension - -vpr_fpga_bitstream_generator: *turn on FPGA-SPICE bitstream generator* From 422ede761013bdb613564897bcc27a3a7fbf93e0 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 10 Jul 2019 12:17:07 -0600 Subject: [PATCH 57/84] Update tutorial draft 4 --- tutorials/building.md | 2 +- tutorials/fpga_flow/folder_organization.md | 9 ++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/tutorials/building.md b/tutorials/building.md index f891378ad..dfc0b8d0d 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -42,7 +42,7 @@ OpenFPGA requires all the dependancies listed below: If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. It can be build using the commands: - docker build . -t open_fpga -- ./run_local.bat +- docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/vpr7_x2p/vpr" open_fpga bash ## Building diff --git a/tutorials/fpga_flow/folder_organization.md b/tutorials/fpga_flow/folder_organization.md index 07f630db8..62cfcf69f 100644 --- a/tutorials/fpga_flow/folder_organization.md +++ b/tutorials/fpga_flow/folder_organization.md @@ -14,10 +14,17 @@ In this folder are saved the architecture files. These files are Hardware descri - **generated**: empty at the beginning, will host rewritten template ## benchmarks -This folder contains benchmarks to implement in the FPGA. +This folder contains benchmarks to implement in the FPGA. it's divided in 3 folders: +- **Blif**: Contains .blif and .act file to use in OpenFPGA. Benchmarks are divided in folder with the same name as the top module +- **Verilog**: Contains Verilog netlist of benchmarks to use in OpenFPGA. Each project is saved in a folder with the same name as the top module. +- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md#benchmark-list) ## configs +This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md#configuration-file) ## scripts +This folder contains scripts call by OpenFPGA flow. Some of them can be used out of the flow as **pro_blif.pl** and **rewrite_path_in_file.pl** which respectively rewrite a blif file with 3 members on a ".latch" module to let it have 5 and replace a keyword in a file.
+Any script provide help if call without argument. ## tech +This folder contains XML files describing the technology used. These files are used during power analysis. From b7f9831bd2fe10274740ec7ccaa536a8f26b0f53 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2019 13:08:03 -0600 Subject: [PATCH 58/84] add statistics for unique GSBs --- .../fpga_x2p/base/fpga_x2p_unique_routing.c | 11 ++- vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp | 75 +++++++++++++++++++ vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h | 8 ++ 3 files changed, 91 insertions(+), 3 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c index d625a5375..7217afd25 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_unique_routing.c @@ -1395,17 +1395,22 @@ DeviceRRGSB build_device_rr_gsb(boolean output_sb_xml, char* sb_xml_dir, /* Report number of unique CB Modules */ vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent connection blocks from %d X-channel connection blocks.\n", + "Detect %d unique connection blocks from %d X-channel connection blocks.\n", LL_device_rr_gsb.get_num_cb_unique_module(CHANX), (nx + 0) * (ny + 1) ); vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent connection blocks from %d Y-channel connection blocks.\n", + "Detect %d unique connection blocks from %d Y-channel connection blocks.\n", LL_device_rr_gsb.get_num_cb_unique_module(CHANY), (nx + 1) * (ny + 0) ); /* Report number of unique SB modules */ vpr_printf(TIO_MESSAGE_INFO, - "Detect %d independent switch blocks from %d switch blocks.\n", + "Detect %d unique switch blocks from %d switch blocks.\n", + LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) ); + + /* Report number of unique GSB modules */ + vpr_printf(TIO_MESSAGE_INFO, + "Detect %d unique GSBs from %d GSBs.\n", LL_device_rr_gsb.get_num_sb_unique_module(), (nx + 1) * (ny + 1) ); /* Report number of unique mirrors */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp index 42fc21c17..4330ca5cc 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.cpp @@ -2379,6 +2379,11 @@ size_t DeviceRRGSB::get_num_sb_unique_module() const { return sb_unique_module_.size(); } +/* get the number of unique mirrors of switch blocks */ +size_t DeviceRRGSB::get_num_gsb_unique_module() const { + return gsb_unique_module_.size(); +} + /* Get the submodule id of a SB */ size_t DeviceRRGSB::get_sb_unique_submodule_id(DeviceCoordinator& coordinator, enum e_side side, size_t seg_id) const { @@ -2565,6 +2570,8 @@ void DeviceRRGSB::set_sb_conf_bits_msb(DeviceCoordinator& coordinator, size_t co void DeviceRRGSB::reserve(DeviceCoordinator& coordinator) { rr_gsb_.resize(coordinator.get_x()); + gsb_unique_module_id_.resize(coordinator.get_x()); + sb_unique_submodule_id_.resize(coordinator.get_x()); sb_unique_module_id_.resize(coordinator.get_x()); @@ -2574,6 +2581,8 @@ void DeviceRRGSB::reserve(DeviceCoordinator& coordinator) { for (size_t x = 0; x < coordinator.get_x(); ++x) { rr_gsb_[x].resize(coordinator.get_y()); + gsb_unique_module_id_[x].resize(coordinator.get_y()); + sb_unique_submodule_id_[x].resize(coordinator.get_y()); sb_unique_module_id_[x].resize(coordinator.get_y()); @@ -2769,6 +2778,45 @@ void DeviceRRGSB::add_sb_unique_side_segment_submodule(DeviceCoordinator& coordi return; } +/* Find repeatable GSB block in the array */ +void DeviceRRGSB::build_gsb_unique_module() { + /* Make sure a clean start */ + clear_gsb_unique_module(); + + for (size_t ix = 0; ix < rr_gsb_.size(); ++ix) { + for (size_t iy = 0; iy < rr_gsb_[ix].size(); ++iy) { + bool is_unique_module = true; + DeviceCoordinator gsb_coordinator(ix, iy); + + /* Traverse the unique_mirror list and check it is an mirror of another */ + for (size_t id = 0; id < get_num_gsb_unique_module(); ++id) { + /* We have alreay built sb and cb unique module list + * We just need to check if the unique module id of SBs, CBX and CBY are the same or not + */ + const DeviceCoordinator& gsb_unique_module_coordinator = gsb_unique_module_[id]; + if ((sb_unique_module_id_[ix][iy] == sb_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()]) + && (cbx_unique_module_id_[ix][iy] == cbx_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()]) + && (cby_unique_module_id_[ix][iy] == cby_unique_module_id_[gsb_unique_module_coordinator.get_x()][gsb_unique_module_coordinator.get_y()])) { + /* This is a mirror, raise the flag and we finish */ + is_unique_module = false; + /* Record the id of unique mirror */ + gsb_unique_module_id_[ix][iy] = id; + break; + } + } + /* Add to list if this is a unique mirror*/ + if (true == is_unique_module) { + add_gsb_unique_module(gsb_coordinator); + /* Record the id of unique mirror */ + gsb_unique_module_id_[ix][iy] = get_num_gsb_unique_module() - 1; + } + } + } + return; +} + + + void DeviceRRGSB::build_unique_module() { build_segment_ids(); @@ -2777,6 +2825,8 @@ void DeviceRRGSB::build_unique_module() { build_cb_unique_module(CHANX); build_cb_unique_module(CHANY); + build_gsb_unique_module(); + return; } @@ -2797,6 +2847,11 @@ void DeviceRRGSB::add_sb_unique_side_submodule(DeviceCoordinator& coordinator, return; } +void DeviceRRGSB::add_gsb_unique_module(const DeviceCoordinator& coordinator) { + gsb_unique_module_.push_back(coordinator); + return; +} + void DeviceRRGSB::add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator) { assert (validate_cb_type(cb_type)); switch(cb_type) { @@ -2868,6 +2923,9 @@ void DeviceRRGSB::build_segment_ids() { void DeviceRRGSB::clear() { clear_gsb(); + clear_gsb_unique_module(); + clear_gsb_unique_module_id(); + /* clean unique module lists */ clear_cb_unique_module(CHANX); clear_cb_unique_module_id(CHANX); @@ -2893,6 +2951,15 @@ void DeviceRRGSB::clear_gsb() { return; } +void DeviceRRGSB::clear_gsb_unique_module_id() { + /* clean rr_switch_block array */ + for (size_t x = 0; x < rr_gsb_.size(); ++x) { + gsb_unique_module_id_[x].clear(); + } + return; +} + + void DeviceRRGSB::clear_sb_unique_module_id() { /* clean rr_switch_block array */ for (size_t x = 0; x < rr_gsb_.size(); ++x) { @@ -2950,6 +3017,14 @@ void DeviceRRGSB::clear_sb_unique_submodule() { return; } +/* clean the content related to unique_mirrors */ +void DeviceRRGSB::clear_gsb_unique_module() { + /* clean unique mirror */ + gsb_unique_module_.clear(); + + return; +} + /* clean the content related to unique_mirrors */ void DeviceRRGSB::clear_sb_unique_module() { /* clean unique mirror */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h index e87ee78c6..c6cb9978c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/rr_blocks.h @@ -330,6 +330,7 @@ class DeviceRRGSB { DeviceCoordinator get_gsb_range() const; /* get the max coordinator of the switch block array */ const RRGSB get_gsb(DeviceCoordinator& coordinator) const; /* Get a rr switch block in the array with a coordinator */ const RRGSB get_gsb(size_t x, size_t y) const; /* Get a rr switch block in the array with a coordinator */ + size_t get_num_gsb_unique_module() const; /* get the number of unique mirrors of GSB */ size_t get_num_sb_unique_submodule(enum e_side side, size_t seg_index) const; /* get the number of unique mirrors of switch blocks */ size_t get_num_sb_unique_module() const; /* get the number of unique mirrors of switch blocks */ size_t get_num_cb_unique_module(t_rr_type cb_type) const; /* get the number of unique mirrors of CBs */ @@ -365,6 +366,8 @@ class DeviceRRGSB { void clear_sb_unique_module_id(); /* clean the content */ void clear_sb_unique_submodule(); /* clean the content */ void clear_sb_unique_submodule_id(); /* clean the content */ + void clear_gsb_unique_module(); /* clean the content */ + void clear_gsb_unique_module_id(); /* clean the content */ void clear_segment_ids(); private: /* Validators */ bool validate_coordinator(DeviceCoordinator& coordinator) const; /* Validate if the (x,y) is the range of this device */ @@ -376,6 +379,7 @@ class DeviceRRGSB { bool validate_cb_type(t_rr_type cb_type) const; private: /* Internal builders */ void build_segment_ids(); /* build a map of segment_ids */ + void add_gsb_unique_module(const DeviceCoordinator& coordinator); void add_sb_unique_side_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side); void add_sb_unique_side_segment_submodule(DeviceCoordinator& coordinator, const RRGSB& rr_sb, enum e_side side, size_t seg_id); void add_cb_unique_module(t_rr_type cb_type, const DeviceCoordinator& coordinator); @@ -383,9 +387,13 @@ class DeviceRRGSB { void build_sb_unique_submodule(); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */ void build_sb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ void build_cb_unique_module(t_rr_type cb_type); /* Add a switch block to the array, which will automatically identify and update the lists of unique side module */ + void build_gsb_unique_module(); /* Add a switch block to the array, which will automatically identify and update the lists of unique mirrors and rotatable mirrors */ private: /* Internal Data */ std::vector< std::vector > rr_gsb_; + std::vector< std::vector > gsb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ + std::vector gsb_unique_module_; + std::vector< std::vector > sb_unique_module_id_; /* A map from rr_gsb to its unique mirror */ std::vector sb_unique_module_; From 0a978db8669e10c8d417b0bc141128a277e53f21 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Wed, 10 Jul 2019 14:16:34 -0600 Subject: [PATCH 59/84] Fix regression test --- .../verilog/verilog_compact_netlist.c | 21 +++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c index 2e1b85236..6f93f2142 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c @@ -928,13 +928,12 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ convert_side_index_to_string(rr_gsb.get_cb_chan_side(cb_type))); for (size_t itrack = 0; itrack < rr_gsb.get_cb_chan_width(cb_type); ++itrack) { if (true == is_explicit_mapping) { - fprintf(fp, ".%s (", - rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack)); + fprintf(fp, ".%s(", unique_mirror.gen_cb_verilog_routing_track_name(cb_type, itrack)); } fprintf(fp, "%s", rr_gsb.gen_cb_verilog_routing_track_name(cb_type, itrack)); if (true == is_explicit_mapping) { - fprintf(fp, ")",itrack); + fprintf(fp, ")"); } fprintf(fp, ",\n"); } @@ -949,12 +948,26 @@ void dump_compact_verilog_defined_one_connection_box(t_sram_orgz_info* cur_sram_ for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { t_rr_node* cur_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); /* Print each INPUT Pins of a grid */ + if (true == is_explicit_mapping) { + if (RIGHT == side_manager.get_side()) { + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x() + 1, unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + } else if (TOP == side_manager.get_side()) { + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + } else if (LEFT == side_manager.get_side()) { + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y() + 1, get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + } else if (BOTTOM == side_manager.get_side()) { + fprintf(fp, ".grid_%d__%d__pin_%d__%d__%d_ (", unique_mirror.get_sb_coordinator().get_x(), unique_mirror.get_sb_coordinator().get_y(), get_grid_pin_height(cur_ipin_node->xlow, cur_ipin_node->ylow,cur_ipin_node->ptc_num), rr_gsb.get_ipin_node_grid_side(cb_ipin_side,inode), cur_ipin_node->ptc_num); + } + } dump_verilog_grid_side_pin_with_given_index(fp, OPIN, cur_ipin_node->ptc_num, rr_gsb.get_ipin_node_grid_side(cb_ipin_side, inode), cur_ipin_node->xlow, cur_ipin_node->ylow, - FALSE, is_explicit_mapping); /* Do not specify direction of port */ + FALSE, false); /* Do not specify direction of port */ + if (true == is_explicit_mapping) { + fprintf(fp, ")"); + } fprintf(fp, ", \n"); } } From a47711203c41824029a430927c9e2d10f8dea7b8 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 10 Jul 2019 14:59:03 -0600 Subject: [PATCH 60/84] Tuto update draft 5 --- .../k6_N10_sram_chain_HC_template.xml | 2 +- fpga_flow/configs/tutorial/tuto.conf | 34 +++++++++---------- fpga_flow/tuto_fpga_flow.sh | 2 +- tutorials/fpga_flow/folder_organization.md | 10 +++--- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml index 0b2aa02f9..06e75d911 100644 --- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml @@ -150,7 +150,7 @@ - + diff --git a/fpga_flow/configs/tutorial/tuto.conf b/fpga_flow/configs/tutorial/tuto.conf index e154662e4..85104383a 100644 --- a/fpga_flow/configs/tutorial/tuto.conf +++ b/fpga_flow/configs/tutorial/tuto.conf @@ -1,27 +1,27 @@ # Standard Configuration Example [dir_path] -script_base = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/scripts/ -benchmark_dir = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/benchmarks/Verilog/MCNC -yosys_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/yosys/yosys -odin2_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/odin2.exe -cirkit_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/cirkit -abc_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/yosys/yosys-abc -abc_mccl_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/abc_with_bb_support/abc -abc_with_bb_support_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/abc_with_bb_support/abc -mpack1_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/mpack1 -m2net_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/m2net -mpack2_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/not_used_atm/mpack2 -vpr_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/vpr -rpt_dir = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/results_tutorial -ace_path = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/ace2/ace +script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts/ +benchmark_dir = OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/Verilog/MCNC +yosys_path = OPENFPGAPATHKEYWORD/yosys/yosys +odin2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/odin2.exe +cirkit_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/cirkit +abc_path = OPENFPGAPATHKEYWORD/yosys/yosys-abc +abc_mccl_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc +abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc_with_bb_support/abc +mpack1_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack1 +m2net_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/m2net +mpack2_path = OPENFPGAPATHKEYWORD/fpga_flow/not_used_atm/mpack2 +vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/vpr +rpt_dir = OPENFPGAPATHKEYWORD/fpga_flow/results_tutorial +ace_path = OPENFPGAPATHKEYWORD/ace2/ace [flow_conf] flow_type = yosys_vpr #standard|mpack2|mpack1|vtr_standard|vtr|yosys_vpr -vpr_arch = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml +vpr_arch = OPENFPGAPATHKEYWORD/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK -m2net_conf = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/m2net_conf/m2x2_SiNWFET.conf +m2net_conf = OPENFPGAPATHKEYWORD/fpga_flow/m2net_conf/m2x2_SiNWFET.conf mpack2_arch = K6_pattern7_I24.arch -power_tech_xml = /research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK +power_tech_xml = OPENFPGAPATHKEYWORD/fpga_flow/tech/PTM_45nm/45nm.xml # Use relative path under VPR folder is OK [csv_tags] mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf: diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh index f7655cb38..22b1ce943 100755 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -27,6 +27,6 @@ perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the # SRAM FPGA # TT case -perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -end_flow_with_test +perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_verilog_print_modelsim_autodeck $modelsim_ini_path -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test echo "Netlists successfully generated and tested" diff --git a/tutorials/fpga_flow/folder_organization.md b/tutorials/fpga_flow/folder_organization.md index 62cfcf69f..095325ad7 100644 --- a/tutorials/fpga_flow/folder_organization.md +++ b/tutorials/fpga_flow/folder_organization.md @@ -1,11 +1,11 @@ # fpga_flow folder organization The fpga_flow folder is organized as follow: -* [**arch**]: contains architectures description files -* [**benchmarks**]: contains Verilog and blif benchmarks + lists -* [**configs**]: contains configuration files to run fpga_flow.pl -* [**scripts**]: contains all the scripts required to run the flow -* [**tech**]: contains xml tech files for power estimation +* **arch**: contains architectures description files +* **benchmarks**: contains Verilog and blif benchmarks + lists +* **configs**: contains configuration files to run fpga_flow.pl +* **scripts**: contains all the scripts required to run the flow +* **tech**: contains xml tech files for power estimation ## arch In this folder are saved the architecture files. These files are Hardware description for the FPGA written in XML. This folder contains 3 sub-folders: From 206fc84a0eaf7e265194968cf4b08debf83a29e2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2019 15:12:51 -0600 Subject: [PATCH 61/84] minor fix in fpga_flow --- fpga_flow/scripts/fpga_flow.pl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 8ee3801a9..49eda2e33 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1790,7 +1790,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); # Remove previous route results if (-e $vpr_route) { - system(rm $vpr_route); + system("rm $vpr_route"); } # Keep increase min_chan_width until route success &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); From 9d7ae2f6ecfac2f2e598c15e17397b1e97784cab Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 10 Jul 2019 15:42:31 -0600 Subject: [PATCH 62/84] Update tutorial flow demo draft 6 --- README.md | 2 +- fpga_flow/scripts/fpga_flow.pl | 2 +- fpga_flow/tuto_fpga_flow.sh | 5 +++-- tutorials/building.md | 2 +- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/README.md b/README.md index e408da414..25891d747 100644 --- a/README.md +++ b/README.md @@ -14,7 +14,7 @@ Dependancies and help using docker can be found at **./tutorials/building.md**. **Compilation steps:** 1. Create a folder named build in OpenPFGA repository (mkdir build && cd build) -2. Create Makefile in this folder using cmake (cmake ..) +2. Create Makefile in this folder using cmake (cmake .. -DCMAKE_BUILD_TYPE=debug) 3. Compile the tool and its dependencies (make) *We currently implemented OpenFPGA for:* diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 8ee3801a9..49eda2e33 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1790,7 +1790,7 @@ sub run_vpr_in_flow($ $ $ $ $ $ $ $ $ $ $ $) { my ($fix_chan_width) = ($benchmarks_ptr->{$benchmark_file}->{fix_route_chan_width}); # Remove previous route results if (-e $vpr_route) { - system(rm $vpr_route); + system("rm $vpr_route"); } # Keep increase min_chan_width until route success &run_std_vpr($abc_blif_out,$benchmark,$vpr_arch,$vpr_net,$vpr_place,$vpr_route,$fix_chan_width,$vpr_log,$act_file); diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh index 22b1ce943..68c07ea73 100755 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -12,7 +12,7 @@ architecture_generated="${pwd_path}/arch/generated/k6_N10_sram_chain_HC.xml" architecture_template="${pwd_path}/arch/template/k6_N10_sram_chain_HC_template.xml" ff_keyword="FFPATHKEYWORD" -ff_path="${pwd_path}/vpr7_x2p/vpr/Verilognetlists/ff.v" +ff_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff.v" dir_keyword="GENERATED_DIR_KEYWORD" rm -rf ${pwd_path}/results_OpenPithon @@ -22,11 +22,12 @@ cd ${pwd_path}/scripts perl rewrite_path_in_file.pl -i $config_file # Replace OPENFPGAPATHKEYWORD in the config file perl rewrite_path_in_file.pl -i $architecture_template -o $architecture_generated # Replace OPENFPGAPATHKEYWORD in the architecture file perl rewrite_path_in_file.pl -i $architecture_generated -k $ff_keyword $ff_path # Set the ff path in the architecture file +echo "perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path" perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the define path in the ff.v file # SRAM FPGA # TT case -perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_verilog_print_modelsim_autodeck $modelsim_ini_path -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test +perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test echo "Netlists successfully generated and tested" diff --git a/tutorials/building.md b/tutorials/building.md index dfc0b8d0d..392a2dc62 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -48,5 +48,5 @@ If all these dependancies are not installed in your machine you can choose to us To build the tool you have to be in OpenFPGA folder and do: - mkdir build && cd build -- cmake .. +- cmake .. -DCMAKE_BUILD_TYPE=debug - make OR make -j From db9c4be9631ceca91cfa7db9db86795db5d57ae4 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 10 Jul 2019 16:00:22 -0600 Subject: [PATCH 63/84] Tuto flow v2 --- README.md | 2 +- tutorials/fpga_flow/how2use.md | 20 ++++++++------------ 2 files changed, 9 insertions(+), 13 deletions(-) diff --git a/README.md b/README.md index 25891d747..47621a371 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ OpenFPGA is an extension to VPR. It is an IP Verilog Generator allowing reliable ## Compilation The different ways of compiling can be found in the **./compilation** folder.
-Dependancies and help using docker can be found at **./tutorials/building.md**. +Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md). **Compilation steps:** 1. Create a folder named build in OpenPFGA repository (mkdir build && cd build) diff --git a/tutorials/fpga_flow/how2use.md b/tutorials/fpga_flow/how2use.md index 000aee364..27c9b1db6 100644 --- a/tutorials/fpga_flow/how2use.md +++ b/tutorials/fpga_flow/how2use.md @@ -16,15 +16,11 @@ cd fpga_flow
By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.
When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.
-The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md). In this example we activated all FPGA-Verilog options - - - -*Any script provides help if launch without argument* - -fpga_flow.pl has dependencies which need to be configured. They are: -* configuration file, which provides dependencies path and flow type -* benchmark list file +The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md).
+There is 3 important things to see: +- All FPGA-Verilog options have been activated +- fpga_flow.pl calls a configuration file through "config_file" variable +- fpga_flow.pl calls a list of benchmark to implement and test through "bench_txt" variable ## Configuration file @@ -60,13 +56,13 @@ m2net_conf = not_used
mpack2_arch = not_used
power_tech_xml = **
-[csv_tags] *to complete*
+[csv_tags]
mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:
mpack2_tags = BLE Number:|BLE Fill Rate:
vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:
vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff
-*An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf* +*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf* ## Benchmark list @@ -79,4 +75,4 @@ Blif and Verilog folders are organized by folders with the name of projects. **F The benchmark list file can contain as many benchmarks as available in the same folder targetted by "benchmark_dir" variable from the configuration file. It's written as:
top_module/*.v,; where is the number of channel/wire between each block. -*An example of this file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt* +*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt* From 3cd214ada2accdde17dfe76083f8d486ea0f80f8 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Wed, 10 Jul 2019 16:14:38 -0600 Subject: [PATCH 64/84] tuto flow v2.1 --- Dockerfile | 2 +- tutorials/building.md | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Dockerfile b/Dockerfile index f4581d845..4184f0f9c 100755 --- a/Dockerfile +++ b/Dockerfile @@ -3,6 +3,6 @@ FROM ubuntu:16.04 RUN apt-get update -qq -y RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev -RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default +RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default diff --git a/tutorials/building.md b/tutorials/building.md index 392a2dc62..9b8ffc791 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -42,7 +42,8 @@ OpenFPGA requires all the dependancies listed below: If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. It can be build using the commands: - docker build . -t open_fpga -- docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/vpr7_x2p/vpr" open_fpga bash +- docker run -it --rm -v $PWD:/localfile -w="/localfile/OpenFPGA/vpr7_x2p/vpr" open_fpga bash +[*docker download link*](https://www.docker.com/products/docker-desktop) ## Building From 31749fe62bb68f23826a038d7b2e87f8803d7340 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 10 Jul 2019 21:12:00 -0600 Subject: [PATCH 65/84] fix bugs in fpga_flow.pl --- fpga_flow/scripts/fpga_flow.pl | 4 ++-- vpr7_x2p/vpr/SRC/base/vpr_api.c | 36 ++++++++++++++++----------------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 49eda2e33..7d21875e9 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1318,7 +1318,7 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) my ($chan_width_opt) = (""); if (($fix_chan_width > 0)||($fix_chan_width == 0)) { - $chan_width_opt = "-route_chan_width $fix_chan_width"; + $chan_width_opt = "--route_chan_width $fix_chan_width"; } if ("on" eq $opt_ptr->{vpr_use_tileable_route_chan_width}) { $chan_width_opt = $chan_width_opt." --use_tileable_route_chan_width"; @@ -1569,7 +1569,7 @@ sub run_mpack2_vpr($ $ $ $ $ $ $) if (0 != $min_chan_width%2) { $min_chan_width += 1; } - $chan_width_opt = "-route_chan_width $min_chan_width"; + $chan_width_opt = "--route_chan_width $min_chan_width"; } chdir $vpr_dir; diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index c85dc934f..023b2df92 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -365,16 +365,16 @@ void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) { alloc_and_load_grid(num_instances_type); freeGrid(); - /* Xifan TANG: We need consider the length of carry-chain CLBs into account! */ - num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros); - /* find length of longest carry-chain logic blocks */ - max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros); - /* Free all the allocated structs */ - free_placement_macros_structs(); - for (imacro = 0; imacro < num_pl_macros; imacro ++) { - free(pl_macros[imacro].members); - } - free(pl_macros); + /* Xifan TANG: We need consider the length of carry-chain CLBs into account! */ + num_pl_macros = alloc_and_load_placement_macros(Arch.Directs, Arch.num_directs, &pl_macros); + /* find length of longest carry-chain logic blocks */ + max_len_chain_blocks = max_len_pl_macros(num_pl_macros, pl_macros); + /* Free all the allocated structs */ + free_placement_macros_structs(); + for (imacro = 0; imacro < num_pl_macros; imacro ++) { + free(pl_macros[imacro].members); + } + free(pl_macros); /* Test if netlist fits in grid */ fit = TRUE; @@ -384,14 +384,14 @@ void vpr_init_pre_place_and_route(INP t_vpr_setup vpr_setup, INP t_arch Arch) { break; } } - /* If the length of macros is longer than ny - 2, fitting should fail. - * Note: carry-chain logic blocks are placed only vertically in FPGA. - */ - if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) { - fit = FALSE; - vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n", - max_len_chain_blocks, ny); - } + /* If the length of macros is longer than ny - 2, fitting should fail. + * Note: carry-chain logic blocks are placed only vertically in FPGA. + */ + if ((TRUE == fit)&&(max_len_chain_blocks > (ny))) { + fit = FALSE; + vpr_printf(TIO_MESSAGE_INFO, "Carry-chain logic blocks length (%d) is larger than y (%d)!\n", + max_len_chain_blocks, ny); + } /* get next value */ if (!fit) { From c556b85d66a83cd426a4cdee60649c98c9845fdd Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Thu, 11 Jul 2019 10:10:30 -0600 Subject: [PATCH 66/84] Update docker instruction --- tutorials/building.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tutorials/building.md b/tutorials/building.md index 9b8ffc791..6439ee63c 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -42,7 +42,7 @@ OpenFPGA requires all the dependancies listed below: If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. It can be build using the commands: - docker build . -t open_fpga -- docker run -it --rm -v $PWD:/localfile -w="/localfile/OpenFPGA/vpr7_x2p/vpr" open_fpga bash +- docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash
[*docker download link*](https://www.docker.com/products/docker-desktop) ## Building From 346b6f3e8e9690c258c383951d3cc2eecb9475ec Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Thu, 11 Jul 2019 10:13:55 -0600 Subject: [PATCH 67/84] Update docker part in building.md --- README.md | 7 ++++--- tutorials/building.md | 2 +- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/README.md b/README.md index 47621a371..e3bb7fb39 100644 --- a/README.md +++ b/README.md @@ -13,9 +13,10 @@ The different ways of compiling can be found in the **./compilation** folder.
Date: Thu, 11 Jul 2019 14:44:30 -0600 Subject: [PATCH 68/84] Add explicit mapping option into fpga_flow --- fpga_flow/scripts/fpga_flow.pl | 5 +++++ fpga_flow/tuto_fpga_flow.sh | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 7d21875e9..a43a70a25 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -189,6 +189,7 @@ sub print_usage() print " \t-vpr_fpga_verilog_print_top_tb : turn on printing top-level testbench for Verilog Generator of VPR FPGA SPICE\n"; print " \t-vpr_fpga_verilog_print_input_blif_tb : turn on printing testbench for input blif file in Verilog Generator of VPR FPGA SPICE\n"; print " \t-vpr_fpga_verilog_print_modelsim_autodeck : turn on printing modelsim simulation script\n"; + print " \t-vpr_fpga_verilog_explicit_mapping\n"; print " [ VPR - FPGA-Bitstream Extension ] \n"; print " \t-vpr_fpga_bitstream_generator: turn on FPGA-SPICE bitstream generator\n"; exit(1); @@ -373,6 +374,7 @@ sub opts_read() &read_opt_into_hash("vpr_fpga_verilog_print_sdc_pnr","off","off"); &read_opt_into_hash("vpr_fpga_verilog_print_sdc_analysis","off","off"); &read_opt_into_hash("vpr_fpga_verilog_print_user_defined_template","off","off"); + &read_opt_into_hash("vpr_fpga_verilog_explicit_mapping","off","off"); # Regression test option &read_opt_into_hash("end_flow_with_test","off","off"); @@ -1420,6 +1422,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) if ("on" eq $opt_ptr->{vpr_fpga_verilog_print_sdc_analysis}) { $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_print_sdc_analysis"; } + if ("on" eq $opt_ptr->{vpr_fpga_verilog_explicit_mapping}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_explicit_mapping"; + } } # FPGA Bitstream Generator Options diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh index 68c07ea73..3ee86966a 100755 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -28,6 +28,6 @@ perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the # SRAM FPGA # TT case -perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test +perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping echo "Netlists successfully generated and tested" From 9c203ca4d28169c560650ceafcd13226475e8eeb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 11 Jul 2019 17:10:08 -0600 Subject: [PATCH 69/84] bug fixing in SDC generator --- fpga_flow/scripts/fpga_flow.pl | 22 ++++++++++++++++++- .../vpr/SRC/fpga_x2p/verilog/verilog_sdc.c | 13 +++++++++-- 2 files changed, 32 insertions(+), 3 deletions(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index a43a70a25..5e7a37c72 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -761,6 +761,8 @@ sub run_abc_fpgamap($ $ $) # Run ABC by FPGA-oriented synthesis sub run_abc_bb_fpgamap($ $ $) { my ($bm,$blif_out,$log) = @_; + my ($cmd_log) = ($log."cmd"); + # Get ABC path my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_with_bb_support_path}->{val}); my ($lut_num) = $opt_ptr->{K_val}; @@ -777,9 +779,26 @@ sub run_abc_bb_fpgamap($ $ $) { $dump_verilog = "write_verilog $bm.v"; } + # + # Create a local copy for the commands + # + my ($ABC_CMD_FH) = (FileHandle->new); + if ($ABC_CMD_FH->open("> $cmd_log")) { + print "INFO: auto generating cmds for ABC ($cmd_log) ...\n"; + } else { + die "ERROR: fail to auto generating cmds for ABC ($cmd_log) ...\n"; + } + # Output the standard format (refer to VTR_flow script) + print $ABC_CMD_FH "read $bm; resyn; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize sweep; write_hie $bm $blif_out; $dump_verilog; quit;\n"; + + close($ABC_CMD_FH); + + # Go to ABC directory and run FPGA with commands + print "Entering $abc_dir\n"; chdir $abc_dir; + # Run FPGA ABC - system("./$abc_name -c \"read $bm; resyn; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize sweep; write_hie $bm $blif_out; $dump_verilog; quit;\" > $log"); + system("./$abc_name -F $cmd_log > $log"); if (!(-e $blif_out)) { die "ERROR: Fail ABC_with_bb_support for benchmark $bm.\n"; @@ -789,6 +808,7 @@ sub run_abc_bb_fpgamap($ $ $) { die "ERROR: ABC verilog rewrite failed for benchmark $bm!\n"; } + print "Leaving $abc_dir\n"; chdir $cwd; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index a57ff6416..345c89954 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -667,10 +667,12 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp, } /* Check */ - assert ((INC_DIRECTION == src_rr_node->direction) - ||(DEC_DIRECTION == src_rr_node->direction)); + if (! ((CHANX == src_rr_node->type) ||(CHANY == src_rr_node->type))) assert ((CHANX == src_rr_node->type) ||(CHANY == src_rr_node->type)); + + assert ((INC_DIRECTION == src_rr_node->direction) + ||(DEC_DIRECTION == src_rr_node->direction)); assert (IPIN == des_rr_node->type); fprintf(fp, "set_max_delay"); @@ -928,6 +930,13 @@ void verilog_generate_sdc_constrain_one_cb(FILE* fp, for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) { t_rr_node* cur_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode); for (int iedge = 0; iedge < cur_ipin_node->num_drive_rr_nodes; iedge++) { + /* Skip the drivers that are not CHANX or CHANY. + * OPINs should be handled by directlist + */ + if ( (CHANX != cur_ipin_node->drive_rr_nodes[iedge]->type) + && (CHANY != cur_ipin_node->drive_rr_nodes[iedge]->type) ) { + continue; + } /* Get the switch delay */ int switch_id = cur_ipin_node->drive_switches[iedge]; float switch_delay = get_switch_sdc_tmax (&(switch_inf[switch_id])); From d0cd5a2bc108d6bb026f5cc95861a62be0eac5d2 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 11 Jul 2019 17:27:31 -0600 Subject: [PATCH 70/84] Hot fix --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c index d2da736c1..eef883b00 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c @@ -902,8 +902,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp, /* Add explicit port mapping if required */ if (TRUE == require_explicit_port_map ) { fprintf(fp, ".%s(", - /* cur_spice_model_port->lib_name); /* Old version*/ - cur_spice_model_port->prefix); + cur_spice_model_port->lib_name); + /*cur_spice_model_port->prefix);*/ } fprintf(fp, "%s[0:%d]", cur_spice_model_port->prefix, From c9b84f61c94fdb82997d0ddccc9702677e9ff371 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 11 Jul 2019 17:39:02 -0600 Subject: [PATCH 71/84] Hot fix --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index 25c162c48..b65b652d5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -373,7 +373,9 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, fprintf(fp, ".%s(", pb_type_port->spice_model_port->lib_name); } - fprintf(fp, "{"); + if (1 < pb_type_port_num_pins) { + fprintf(fp, "{"); + } for (int ipin = 0; ipin < pb_type_port->num_pins; ++ipin) { if (0 < ipin) { fprintf(fp, ", "); @@ -381,7 +383,9 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin)); } - fprintf(fp, "}"); + if (1 < pb_type_port_num_pins) { + fprintf(fp, "}"); + } if (TRUE == dump_explicit_port_map) { fprintf(fp, ")"); } From e633e3d17baeb3c5649e226d518ec80c8ae44a4a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 11 Jul 2019 19:40:58 -0600 Subject: [PATCH 72/84] update fpga_flow scripts to support vpr_only flow --- fpga_flow/scripts/fpga_flow.pl | 40 +++++++++++++++++++++++++++++++++- fpga_flow/scripts/pro_blif.pl | 1 + 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index 5e7a37c72..af547d78c 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -46,7 +46,8 @@ my @supported_flows = ("standard", "mpack1", "vtr", "vtr_standard", - "yosys_vpr"); + "yosys_vpr", + "vpr_only"); my %selected_flows; # Configuration file keywords list @@ -2024,6 +2025,34 @@ sub parse_yosys_vpr_flow_results($ $ $ $) return; } +sub run_vpr_only_flow($ $ $ $ $) +{ + my ($tag,$benchmark_file,$vpr_arch, $parse_results) = @_; + my ($benchmark, $rpt_dir,$prefix); + my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log); + + $benchmark = $benchmark_file; + $benchmark =~ s/\.blif$//g; + # Run Standard flow + $rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag"; + &generate_path($rpt_dir); + $prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_"; + + my ($input_blif) = ("$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif"); + my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log"); + + $vpr_net = "$prefix"."vpr.net"; + $vpr_place = "$prefix"."vpr.place"; + $vpr_route = "$prefix"."vpr.route"; + $vpr_log = "$prefix"."vpr.log"; + $vpr_reroute_log = "$prefix"."vpr_reroute.log"; + + &run_ace_in_flow($prefix, $input_blif, $act_file, $ace_new_blif, $ace_log); + + &run_vpr_in_flow($tag, $benchmark, $benchmark_file, $input_blif, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results); + + return; +} sub run_standard_flow($ $ $ $ $) { @@ -2748,6 +2777,8 @@ sub run_benchmark_selected_flow($ $ $) &run_mig_mccl_flow("mig_mccl",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); } elsif ($flow_type eq "yosys_vpr") { &run_yosys_vpr_flow("yosys_vpr",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, "classic", $parse_results); + } elsif ($flow_type eq "vpr_only") { + &run_vpr_only_flow("vpr_only",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results); } else { die "ERROR: unsupported flow type ($flow_type) is chosen!\n"; } @@ -2776,6 +2807,8 @@ sub parse_benchmark_selected_flow($ $) { &parse_standard_flow_results("mig_mccl", $benchmark, $conf_ptr->{flow_conf}->{vpr_arch}->{val}, "abc_black_box"); } elsif ($flow_type eq "yosys_vpr") { &parse_yosys_vpr_flow_results("yosys_vpr",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"abc_black_box"); + } elsif ($flow_type eq "vpr_only") { + &parse_standard_flow_results("vpr_only",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, "classic"); } else { die "ERROR: unsupported flow type ($flow_type) is chosen!\n"; } @@ -3567,6 +3600,11 @@ sub gen_csv_rpt($) print "INFO: writing yosys_vpr flow results ...\n"; &gen_csv_rpt_yosys_vpr_flow("yosys_vpr",$CSVFH); } + } elsif ($flow_type eq "vpr_only") { + if (1 == &check_flow_all_benchmarks_done("vpr_only")) { + print "INFO: writing vpr_only flow results ...\n"; + &gen_csv_rpt_standard_flow("vpr_only",$CSVFH); + } } else { die "ERROR: flow_type: $flow_type is not supported!\n"; } diff --git a/fpga_flow/scripts/pro_blif.pl b/fpga_flow/scripts/pro_blif.pl index d48bc54a5..40203e136 100755 --- a/fpga_flow/scripts/pro_blif.pl +++ b/fpga_flow/scripts/pro_blif.pl @@ -147,6 +147,7 @@ sub process_blifmodel($ $) { if ($temp eq $default_clk_name) { $have_default_clk = 1; $clk_num++; + print "Found 1 clock: $temp in @tokens\n"; last; } } From cffdebd9127fdc23a897af26010e892da463f3ee Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 11 Jul 2019 21:02:09 -0600 Subject: [PATCH 73/84] bug fixed for the tileable RR graph generator for heterogeneous blocks --- .../rr_graph/tileable_rr_graph_builder.cpp | 107 +++++++++++------- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 4 +- 2 files changed, 67 insertions(+), 44 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp index 3d919ecc0..2e520c0d9 100644 --- a/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp +++ b/vpr7_x2p/vpr/SRC/device/rr_graph/tileable_rr_graph_builder.cpp @@ -244,7 +244,7 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x(); rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x(); rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y(); - rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y(); + rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1; rr_graph->rr_node[*cur_node_id].ptc_num = opin_list[pin]; rr_graph->rr_node[*cur_node_id].capacity = 1; rr_graph->rr_node[*cur_node_id].occ = 0; @@ -253,6 +253,15 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator /* Switch info */ rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch; /* fill fast look-up table */ + /* If height > 1, we will update fast lookup to twice: + * 1. for the x, y + height. This enable fast fast look-up for node collection in rr_gsb + * 2. for the x, y. This enables fast lookup for SOURCE and SINK nodes drive/driven by the node + */ + load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, + rr_graph->rr_node[*cur_node_id].type, + rr_graph->rr_node[*cur_node_id].xlow, + rr_graph->rr_node[*cur_node_id].ylow + height, + rr_graph->rr_node[*cur_node_id].ptc_num); load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, rr_graph->rr_node[*cur_node_id].type, rr_graph->rr_node[*cur_node_id].xlow, @@ -269,7 +278,7 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x(); rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x(); rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y(); - rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y(); + rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1; rr_graph->rr_node[*cur_node_id].ptc_num = ipin_list[pin]; rr_graph->rr_node[*cur_node_id].capacity = 1; rr_graph->rr_node[*cur_node_id].occ = 0; @@ -278,6 +287,15 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator /* Switch info */ rr_graph->rr_node[*cur_node_id].driver_switch = wire_to_ipin_switch; /* fill fast look-up table */ + /* If height > 1, we will update fast lookup to twice: + * 1. for the x, y + height. This enable fast fast look-up for node collection in rr_gsb + * 2. for the x, y. This enables fast lookup for SOURCE and SINK nodes drive/driven by the node + */ + load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, + rr_graph->rr_node[*cur_node_id].type, + rr_graph->rr_node[*cur_node_id].xlow, + rr_graph->rr_node[*cur_node_id].ylow + height, + rr_graph->rr_node[*cur_node_id].ptc_num); load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, rr_graph->rr_node[*cur_node_id].type, rr_graph->rr_node[*cur_node_id].xlow, @@ -289,46 +307,44 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator } /* End of side enumeration */ } /* End of height enumeration */ - /* Walk through the height of each grid, + /* No need to Walk through the height of each grid, * get pins and configure the rr_nodes */ - for (int height = 0; height < cur_grid.type->height; ++height) { - /* Set a SOURCE or a SINK rr_node for each class */ - for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { - /* Set a SINK rr_node for the OPIN */ - if ( DRIVER == cur_grid.type->class_inf[iclass].type) { - rr_graph->rr_node[*cur_node_id].type = SOURCE; - } - if ( RECEIVER == cur_grid.type->class_inf[iclass].type) { - rr_graph->rr_node[*cur_node_id].type = SINK; - } - rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x(); - rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x(); - rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y(); - rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y(); - rr_graph->rr_node[*cur_node_id].ptc_num = iclass; - /* FIXME: need to confirm if the capacity should be the number of pins in this class*/ - rr_graph->rr_node[*cur_node_id].capacity = cur_grid.type->class_inf[iclass].num_pins; - rr_graph->rr_node[*cur_node_id].occ = 0; - /* cost index is a FIXED value for SOURCE and SINK */ - if (SOURCE == rr_graph->rr_node[*cur_node_id].type) { - rr_graph->rr_node[*cur_node_id].cost_index = SOURCE_COST_INDEX; - } - if (SINK == rr_graph->rr_node[*cur_node_id].type) { - rr_graph->rr_node[*cur_node_id].cost_index = SINK_COST_INDEX; - } - /* Switch info */ - rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch; - /* TODO: should we set pb_graph_pin here? */ - /* fill fast look-up table */ - load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, - rr_graph->rr_node[*cur_node_id].type, - rr_graph->rr_node[*cur_node_id].xlow, - rr_graph->rr_node[*cur_node_id].ylow, - rr_graph->rr_node[*cur_node_id].ptc_num); - /* Update node counter */ - (*cur_node_id)++; - } /* End of height enumeration */ - } /* End of pin_class enumeration */ + /* Set a SOURCE or a SINK rr_node for each class */ + for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) { + /* Set a SINK rr_node for the OPIN */ + if ( DRIVER == cur_grid.type->class_inf[iclass].type) { + rr_graph->rr_node[*cur_node_id].type = SOURCE; + } + if ( RECEIVER == cur_grid.type->class_inf[iclass].type) { + rr_graph->rr_node[*cur_node_id].type = SINK; + } + rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x(); + rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x(); + rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y(); + rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1; + rr_graph->rr_node[*cur_node_id].ptc_num = iclass; + /* FIXME: need to confirm if the capacity should be the number of pins in this class*/ + rr_graph->rr_node[*cur_node_id].capacity = cur_grid.type->class_inf[iclass].num_pins; + rr_graph->rr_node[*cur_node_id].occ = 0; + /* cost index is a FIXED value for SOURCE and SINK */ + if (SOURCE == rr_graph->rr_node[*cur_node_id].type) { + rr_graph->rr_node[*cur_node_id].cost_index = SOURCE_COST_INDEX; + } + if (SINK == rr_graph->rr_node[*cur_node_id].type) { + rr_graph->rr_node[*cur_node_id].cost_index = SINK_COST_INDEX; + } + /* Switch info */ + rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch; + /* TODO: should we set pb_graph_pin here? */ + /* fill fast look-up table */ + load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id, + rr_graph->rr_node[*cur_node_id].type, + rr_graph->rr_node[*cur_node_id].xlow, + rr_graph->rr_node[*cur_node_id].ylow, + rr_graph->rr_node[*cur_node_id].ptc_num); + /* Update node counter */ + (*cur_node_id)++; + } /* End of height enumeration */ return; } @@ -640,7 +656,7 @@ void load_rr_nodes_basic_info(t_rr_graph* rr_graph, || (OPIN == rr_graph->rr_node[inode].type) || (IPIN == rr_graph->rr_node[inode].type)); assert (rr_graph->rr_node[inode].xlow == rr_graph->rr_node[inode].xhigh); - assert (rr_graph->rr_node[inode].ylow == rr_graph->rr_node[inode].yhigh); + assert (rr_graph->rr_node[inode].ylow + grids[rr_graph->rr_node[inode].xlow][rr_graph->rr_node[inode].ylow].type->height - 1 == rr_graph->rr_node[inode].yhigh); } } @@ -993,6 +1009,13 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types, ***********************************************************************/ alloc_rr_graph_fast_lookup(device_size, &rr_graph); + /* FIXME: DEBUG CODES TO BE REMOVED + vpr_printf(TIO_MESSAGE_INFO, "estimated %lu SOURCE NODE.\n", num_rr_nodes_per_type[SOURCE]); + vpr_printf(TIO_MESSAGE_INFO, "estimated %lu SINK NODE.\n", num_rr_nodes_per_type[SINK]); + vpr_printf(TIO_MESSAGE_INFO, "estimated %lu OPIN NODE.\n", num_rr_nodes_per_type[OPIN]); + vpr_printf(TIO_MESSAGE_INFO, "estimated %lu IPIN NODE.\n", num_rr_nodes_per_type[IPIN]); + */ + load_rr_nodes_basic_info(&rr_graph, device_size, grids, device_chan_width, segment_infs, wire_to_ipin_switch, delayless_switch); diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index b65b652d5..9cd1f6f16 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -373,7 +373,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, fprintf(fp, ".%s(", pb_type_port->spice_model_port->lib_name); } - if (1 < pb_type_port_num_pins) { + if (1 < pb_type_port->num_pins) { fprintf(fp, "{"); } for (int ipin = 0; ipin < pb_type_port->num_pins; ++ipin) { @@ -383,7 +383,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin)); } - if (1 < pb_type_port_num_pins) { + if (1 < pb_type_port->num_pins) { fprintf(fp, "}"); } if (TRUE == dump_explicit_port_map) { From 1431ee2f8260f10278d53e664475bd8017022254 Mon Sep 17 00:00:00 2001 From: Baudouin Chauviere Date: Thu, 11 Jul 2019 22:09:34 -0600 Subject: [PATCH 74/84] Fix Explicit verilog --- vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c | 12 ++++++------ .../vpr/SRC/fpga_x2p/verilog/verilog_primitives.c | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index b65b652d5..f75e37f9b 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -373,7 +373,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, fprintf(fp, ".%s(", pb_type_port->spice_model_port->lib_name); } - if (1 < pb_type_port_num_pins) { + if (1 < pb_type_port->num_pins) { fprintf(fp, "{"); } for (int ipin = 0; ipin < pb_type_port->num_pins; ++ipin) { @@ -383,7 +383,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp, fprintf(fp, "%s", gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin)); } - if (1 < pb_type_port_num_pins) { + if (1 < pb_type_port->num_pins) { fprintf(fp, "}"); } if (TRUE == dump_explicit_port_map) { @@ -445,7 +445,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp, } } dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "inout", - pb_type_inout_ports[iport], dump_port_type, dump_explicit_port_map); + pb_type_inout_ports[iport], dump_port_type, TRUE); /* Update the counter */ num_dumped_port++; @@ -464,7 +464,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp, } } dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input", - pb_type_input_ports[iport], dump_port_type, dump_explicit_port_map); + pb_type_input_ports[iport], dump_port_type, TRUE); /* Update the counter */ num_dumped_port++; } @@ -482,7 +482,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp, } } dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "output", - pb_type_output_ports[iport], dump_port_type, dump_explicit_port_map); + pb_type_output_ports[iport], dump_port_type, TRUE); /* Update the counter */ num_dumped_port++; } @@ -501,7 +501,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp, } } dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input", - pb_type_clk_ports[iport], dump_port_type, dump_explicit_port_map); + pb_type_clk_ports[iport], dump_port_type, TRUE); /* Update the counter */ num_dumped_port++; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index 24c46587b..0855b6f3e 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -134,7 +134,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl); /* print ports --> input ports */ - dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE, false); + dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE, true); /* IOPADs requires a specical port to output */ if (SPICE_MODEL_IOPAD == verilog_model->type) { fprintf(fp, ",\n"); From e65cf9f5fdeb17dc29d0e4145d0d0d86fec0a789 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 12 Jul 2019 08:55:19 -0600 Subject: [PATCH 75/84] Update ERI-demo --- ERI_demo/ERI.sh | 6 +- ERI_demo/eri_demo.sh | 24 +- ERI_demo/my_eri_demo.sh | 42 ---- ERI_demo/pipelined_8b_adder.act | 95 -------- ERI_demo/pipelined_8b_adder.blif | 137 ----------- ERI_demo/pipelined_8b_adder.v | 63 ----- .../pipelined_8b_adder_formal_random_top_tb.v | 219 ------------------ fpga_flow/tuto_fpga_flow.sh | 2 +- vpr7_x2p/vpr/regression_verilog.sh | 2 +- 9 files changed, 15 insertions(+), 575 deletions(-) delete mode 100644 ERI_demo/my_eri_demo.sh delete mode 100644 ERI_demo/pipelined_8b_adder.act delete mode 100644 ERI_demo/pipelined_8b_adder.blif delete mode 100644 ERI_demo/pipelined_8b_adder.v delete mode 100644 ERI_demo/pipelined_8b_adder_formal_random_top_tb.v diff --git a/ERI_demo/ERI.sh b/ERI_demo/ERI.sh index 75211050a..cd812298c 100755 --- a/ERI_demo/ERI.sh +++ b/ERI_demo/ERI.sh @@ -5,7 +5,7 @@ my_pwd=$PWD fpga_flow_scripts=${my_pwd}/fpga_flow/scripts vpr_path=${my_pwd}/vpr7_x2p/vpr -benchmark="pipelined_8b_adder" +benchmark="test_modes" include_netlists="_include_netlists.v" compiled_file="compiled_$benchmark" tb_formal_postfix="_top_formal_verification_random_tb" @@ -45,5 +45,7 @@ if ["$result" = ""]; then fi else echo "Verification succeed" - cd $my_pwd fi + +gtkwave ${benchmark}_formal.vcd & +cd $my_pwd diff --git a/ERI_demo/eri_demo.sh b/ERI_demo/eri_demo.sh index 807c5110b..6974366a7 100644 --- a/ERI_demo/eri_demo.sh +++ b/ERI_demo/eri_demo.sh @@ -3,18 +3,18 @@ # Set variables # For FPGA-Verilog ONLY -benchmark="pipelined_8b_adder" +benchmark="test_modes" OpenFPGA_path="OPENFPGAPATHKEYWORD" verilog_output_dirname="${benchmark}_Verilog" verilog_output_dirpath="$vpr_path" tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" # VPR critical inputs -template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml" -arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml" -blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif" -act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act " -verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v" -vpr_route_chan_width="300" +template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml" +arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xml" +blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" +act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " +verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v" +vpr_route_chan_width="200" fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts" ff_path="$vpr_path/VerilogNetlists/ff.v" new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" @@ -23,15 +23,13 @@ ff_include_path="$verilog_output_dirpath/$verilog_output_dirname" arch_ff_keyword="FFPATHKEYWORD" tb_formal_ext="_formal_random_top_tb.v" formal_postfix="_top_formal_verification" -clk_unmapped="clk\[0:0\]" -clk_mapped="clk_fm" # Remove previous designs rm -rf $verilog_output_dirpath/$verilog_output_dirname mkdir ${OpenFPGA_path}/fpga_flow/arch/generated -#cd $fpga_flow_scripts +cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path @@ -39,14 +37,10 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd $vpr_path # Run VPR -./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --nodisp +./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping --nodisp cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path - -rm $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext} -perl rewrite_path_in_file.pl -i ${OpenFPGA_path}/ERI_demo/${benchmark}${tb_formal_ext} -o $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${tb_formal_ext} cd - -sed -i 's/^clk\[0:0\]/clk_fm/' $verilog_output_dirpath/$verilog_output_dirname/SRC/${benchmark}${formal_postfix}.v diff --git a/ERI_demo/my_eri_demo.sh b/ERI_demo/my_eri_demo.sh deleted file mode 100644 index 2e6220ba3..000000000 --- a/ERI_demo/my_eri_demo.sh +++ /dev/null @@ -1,42 +0,0 @@ -#!/bin/bash -# Example of how to run vpr - -# Set variables -# For FPGA-Verilog ONLY -benchmark="pipelined_32b_adder" -OpenFPGA_path="/research/ece/lnis/USERS/alacchi/Current_release/branch_multimode/OpenFPGA" -verilog_output_dirname="${benchmark}_Verilog" -verilog_output_dirpath="$vpr_path" -tech_file="${OpenFPGA_path}/fpga_flow/tech/PTM_45nm/45nm.xml" -# VPR critical inputs -template_arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/template/k6_N10_sram_chain_HC_DPRAM_template.xml" -arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC_DPRAM.xml" -blif_file="${OpenFPGA_path}/ERI_demo/$benchmark.blif" -act_file="${OpenFPGA_path}/ERI_demo/$benchmark.act " -verilog_reference="${OpenFPGA_path}/ERI_demo/$benchmark.v" -vpr_route_chan_width="300" -fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts" -ff_path="$vpr_path/VerilogNetlists/ff.v" -new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" -ff_keyword="GENERATED_DIR_KEYWORD" -ff_include_path="$verilog_output_dirpath/$verilog_output_dirname" -arch_ff_keyword="FFPATHKEYWORD" - -# Remove previous designs -#rm -rf $verilog_output_dirpath/$verilog_output_dirname - -mkdir ${OpenFPGA_path}/fpga_flow/arch/generated - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file -perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path - -# Move to vpr folder -cd $vpr_path - -# Run VPR -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator #--fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy - -cd $fpga_flow_scripts -perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path -cd - diff --git a/ERI_demo/pipelined_8b_adder.act b/ERI_demo/pipelined_8b_adder.act deleted file mode 100644 index c7a502a2d..000000000 --- a/ERI_demo/pipelined_8b_adder.act +++ /dev/null @@ -1,95 +0,0 @@ -clk 0.5 0.2 -wen 0.5 0.2 -wen_st0 0.5 0.2 -wen_st1 0.5 0.2 -ren 0.5 0.2 -raddr[0] 0.5 0.2 -raddr[1] 0.5 0.2 -raddr[2] 0.5 0.2 -raddr[3] 0.5 0.2 -raddr[4] 0.5 0.2 -raddr[5] 0.5 0.2 -waddr[0] 0.5 0.2 -waddr[1] 0.5 0.2 -waddr[2] 0.5 0.2 -waddr[3] 0.5 0.2 -waddr[4] 0.5 0.2 -waddr[5] 0.5 0.2 -waddr_st0[0] 0.5 0.2 -waddr_st0[1] 0.5 0.2 -waddr_st0[2] 0.5 0.2 -waddr_st0[3] 0.5 0.2 -waddr_st0[4] 0.5 0.2 -waddr_st0[5] 0.5 0.2 -waddr_st1[0] 0.5 0.2 -waddr_st1[1] 0.5 0.2 -waddr_st1[2] 0.5 0.2 -waddr_st1[3] 0.5 0.2 -waddr_st1[4] 0.5 0.2 -waddr_st1[5] 0.5 0.2 -a[0] 0.5 0.2 -a[1] 0.5 0.2 -a[2] 0.5 0.2 -a[3] 0.5 0.2 -a[4] 0.5 0.2 -a[5] 0.5 0.2 -a[6] 0.5 0.2 -a_st0[0] 0.5 0.2 -a_st0[1] 0.5 0.2 -a_st0[2] 0.5 0.2 -a_st0[3] 0.5 0.2 -a_st0[4] 0.5 0.2 -a_st0[5] 0.5 0.2 -a_st0[6] 0.5 0.2 -a_st1[0] 0.5 0.2 -a_st1[1] 0.5 0.2 -a_st1[2] 0.5 0.2 -a_st1[3] 0.5 0.2 -a_st1[4] 0.5 0.2 -a_st1[5] 0.5 0.2 -a_st1[6] 0.5 0.2 -b[0] 0.5 0.2 -b[1] 0.5 0.2 -b[2] 0.5 0.2 -b[3] 0.5 0.2 -b[4] 0.5 0.2 -b[5] 0.5 0.2 -b[6] 0.5 0.2 -b_st0[0] 0.5 0.2 -b_st0[1] 0.5 0.2 -b_st0[2] 0.5 0.2 -b_st0[3] 0.5 0.2 -b_st0[4] 0.5 0.2 -b_st0[5] 0.5 0.2 -b_st0[6] 0.5 0.2 -b_st1[0] 0.5 0.2 -b_st1[1] 0.5 0.2 -b_st1[2] 0.5 0.2 -b_st1[3] 0.5 0.2 -b_st1[4] 0.5 0.2 -b_st1[5] 0.5 0.2 -b_st1[6] 0.5 0.2 -q[0] 0.5 0.2 -q[1] 0.5 0.2 -q[2] 0.5 0.2 -q[3] 0.5 0.2 -q[4] 0.5 0.2 -q[5] 0.5 0.2 -q[6] 0.5 0.2 -q[7] 0.5 0.2 -AplusB[0] 0.5 0.2 -AplusB[1] 0.5 0.2 -AplusB[2] 0.5 0.2 -AplusB[3] 0.5 0.2 -AplusB[4] 0.5 0.2 -AplusB[5] 0.5 0.2 -AplusB[6] 0.5 0.2 -AplusB[7] 0.5 0.2 -cint01 0.5 0.2 -cint02 0.5 0.2 -cint03 0.5 0.2 -cint04 0.5 0.2 -cint05 0.5 0.2 -cint06 0.5 0.2 -cint07 0.5 0.2 -zero00 0 0 diff --git a/ERI_demo/pipelined_8b_adder.blif b/ERI_demo/pipelined_8b_adder.blif deleted file mode 100644 index 7f47b1661..000000000 --- a/ERI_demo/pipelined_8b_adder.blif +++ /dev/null @@ -1,137 +0,0 @@ -# Benchmark pipelined_32b_adder -.model pipelined_32b_adder -.inputs clk wen ren raddr[0] raddr[1] raddr[2] raddr[3] raddr[4] raddr[5] waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] a[0] a[1] a[2] a[3] a[4] a[5] a[6] b[0] b[1] b[2] b[3] b[4] b[5] b[6] -.outputs q[0] q[1] q[2] q[3] q[4] q[5] q[6] q[7] - -# Start pipeline -# Pipeline a -.subckt shift D=a[0] clk=clk Q=a_st0[0] -.subckt shift D=a_st0[0] clk=clk Q=a_st1[0] -.subckt shift D=a[1] clk=clk Q=a_st0[1] -.subckt shift D=a_st0[1] clk=clk Q=a_st1[1] -.subckt shift D=a[2] clk=clk Q=a_st0[2] -.subckt shift D=a_st0[2] clk=clk Q=a_st1[2] -.subckt shift D=a[3] clk=clk Q=a_st0[3] -.subckt shift D=a_st0[3] clk=clk Q=a_st1[3] -.subckt shift D=a[4] clk=clk Q=a_st0[4] -.subckt shift D=a_st0[4] clk=clk Q=a_st1[4] -.subckt shift D=a[5] clk=clk Q=a_st0[5] -.subckt shift D=a_st0[5] clk=clk Q=a_st1[5] -.subckt shift D=a[6] clk=clk Q=a_st0[6] -.subckt shift D=a_st0[6] clk=clk Q=a_st1[6] - -# Pipeline b -.subckt shift D=b[0] clk=clk Q=b_st0[0] -.subckt shift D=b_st0[0] clk=clk Q=b_st1[0] -.subckt shift D=b[1] clk=clk Q=b_st0[1] -.subckt shift D=b_st0[1] clk=clk Q=b_st1[1] -.subckt shift D=b[2] clk=clk Q=b_st0[2] -.subckt shift D=b_st0[2] clk=clk Q=b_st1[2] -.subckt shift D=b[3] clk=clk Q=b_st0[3] -.subckt shift D=b_st0[3] clk=clk Q=b_st1[3] -.subckt shift D=b[4] clk=clk Q=b_st0[4] -.subckt shift D=b_st0[4] clk=clk Q=b_st1[4] -.subckt shift D=b[5] clk=clk Q=b_st0[5] -.subckt shift D=b_st0[5] clk=clk Q=b_st1[5] -.subckt shift D=b[6] clk=clk Q=b_st0[6] -.subckt shift D=b_st0[6] clk=clk Q=b_st1[6] - -# Pipeline waddr -.subckt shift D=waddr[0] clk=clk Q=waddr_st0[0] -.subckt shift D=waddr_st0[0] clk=clk Q=waddr_st1[0] -.subckt shift D=waddr[1] clk=clk Q=waddr_st0[1] -.subckt shift D=waddr_st0[1] clk=clk Q=waddr_st1[1] -.subckt shift D=waddr[2] clk=clk Q=waddr_st0[2] -.subckt shift D=waddr_st0[2] clk=clk Q=waddr_st1[2] -.subckt shift D=waddr[3] clk=clk Q=waddr_st0[3] -.subckt shift D=waddr_st0[3] clk=clk Q=waddr_st1[3] -.subckt shift D=waddr[4] clk=clk Q=waddr_st0[4] -.subckt shift D=waddr_st0[4] clk=clk Q=waddr_st1[4] -.subckt shift D=waddr[5] clk=clk Q=waddr_st0[5] -.subckt shift D=waddr_st0[5] clk=clk Q=waddr_st1[5] -# Pipeline wen -.subckt shift D=wen clk=clk Q=wen_st0 -.subckt shift D=wen_st0 clk=clk Q=wen_st1 -# End pipeline - -# Start adder -.subckt adder a=a_st1[0] b=b_st1[0] cin=zero00 cout=cint01 sumout=AplusB[0] -.subckt adder a=a_st1[1] b=b_st1[1] cin=cint01 cout=cint02 sumout=AplusB[1] -.subckt adder a=a_st1[2] b=b_st1[2] cin=cint02 cout=cint03 sumout=AplusB[2] -.subckt adder a=a_st1[3] b=b_st1[3] cin=cint03 cout=cint04 sumout=AplusB[3] -.subckt adder a=a_st1[4] b=b_st1[4] cin=cint04 cout=cint05 sumout=AplusB[4] -.subckt adder a=a_st1[5] b=b_st1[5] cin=cint05 cout=cint06 sumout=AplusB[5] -.subckt adder a=a_st1[6] b=b_st1[6] cin=cint06 cout=cint07 sumout=AplusB[6] -.subckt adder a=zero00 b=zero00 cin=cint07 cout=unconn sumout=AplusB[7] -# End adder - -# Start DPRAM -.subckt dpram clk=clk wen=wen_st1 ren=ren \ -waddr[0]=waddr_st1[0] waddr[1]=waddr_st1[1] waddr[2]=waddr_st1[2] waddr[3]=waddr_st1[3] waddr[4]=waddr_st1[4] \ -waddr[5]=waddr_st1[5] waddr[6]=zero00 waddr[7]=zero00 waddr[8]=zero00 waddr[9]=zero00 waddr[10]==zero00 \ -raddr[0]=raddr[0] raddr[1]=raddr[1] raddr[2]=raddr[2] raddr[3]=raddr[3] raddr[4]=raddr[4] raddr[5]=raddr[5] \ -raddr[6]=zero00 raddr[7]=zero00 raddr[8]=zero00 raddr[9]=zero00 raddr[10]=zero00 \ -d_in[0]=AplusB[0] d_in[1]=AplusB[1] d_in[2]=AplusB[2] d_in[3]=AplusB[3] d_in[4]=AplusB[4] d_in[5]=AplusB[5] \ -d_in[6]=AplusB[6] d_in[7]=AplusB[7] d_in[8]=zero00 d_in[9]=zero00 d_in[10]=zero00 d_in[11]=zero00 \ -d_in[12]=zero00 d_in[13]=zero00 d_in[14]=zero00 d_in[15]=zero00 d_in[16]=zero00 d_in[17]=zero00 \ -d_in[18]=zero00 d_in[19]=zero00 d_in[20]=zero00 d_in[21]=zero00 d_in[22]=zero00 d_in[23]=zero00 \ -d_in[24]=zero00 d_in[25]=zero00 d_in[26]=zero00 d_in[27]=zero00 d_in[28]=zero00 d_in[29]=zero00 \ -d_in[30]=zero00 d_in[31]=zero00 \ -d_in[32]=zero00 d_in[33]=zero00 d_in[34]=zero00 d_in[35]=zero00 d_in[36]=zero00 d_in[37]=zero00 d_in[38]=zero00 d_in[39]=zero00 d_in[40]=zero00 d_in[41]=zero00 d_in[42]=zero00 d_in[43]=zero00 d_in[44]=zero00 d_in[45]=zero00 d_in[46]=zero00 d_in[47]=zero00 d_in[48]=zero00 d_in[49]=zero00 d_in[50]=zero00 d_in[51]=zero00 d_in[52]=zero00 d_in[53]=zero00 d_in[54]=zero00 d_in[55]=zero00 d_in[56]=zero00 d_in[57]=zero00 d_in[58]=zero00 d_in[59]=zero00 d_in[60]=zero00 d_in[61]=zero00 d_in[62]=zero00 d_in[63]=zero00 \ -d_out[0]=q[0] d_out[1]=q[1] d_out[2]=q[2] d_out[3]=q[3] d_out[4]=q[4] d_out[5]=q[5] \ -d_out[6]=q[6] d_out[7]=q[7] d_out[8]=unconn d_out[9]=unconn d_out[10]=unconn \ -d_out[11]=unconn d_out[12]=unconn d_out[13]=unconn d_out[14]=unconn d_out[15]=unconn \ -d_out[16]=unconn d_out[17]=unconn d_out[18]=unconn d_out[19]=unconn d_out[20]=unconn \ -d_out[21]=unconn d_out[22]=unconn d_out[23]=unconn d_out[24]=unconn d_out[25]=unconn \ -d_out[26]=unconn d_out[27]=unconn d_out[28]=unconn d_out[29]=unconn d_out[30]=unconn d_out[31]=unconn \ -d_out[32]=unconn d_out[33]=unconn d_out[34]=unconn d_out[35]=unconn d_out[36]=unconn d_out[37]=unconn d_out[38]=unconn d_out[39]=unconn d_out[40]=unconn d_out[41]=unconn d_out[42]=unconn d_out[43]=unconn d_out[44]=unconn d_out[45]=unconn d_out[46]=unconn d_out[47]=unconn d_out[48]=unconn d_out[49]=unconn d_out[50]=unconn d_out[51]=unconn d_out[52]=unconn d_out[53]=unconn d_out[54]=unconn d_out[55]=unconn d_out[56]=unconn d_out[57]=unconn d_out[58]=unconn d_out[59]=unconn d_out[60]=unconn d_out[61]=unconn d_out[62]=unconn d_out[63]=unconn -# End DPRAM - -# Start global variable -.names zero00 -0 -# End global variable - - -.end - -# Start blackbox definition -.model dpram -.inputs clk wen ren waddr[0] waddr[1] waddr[2] waddr[3] waddr[4] waddr[5] \ - waddr[6] waddr[7] waddr[8] waddr[9] waddr[10] raddr[0] raddr[1] raddr[2] \ - raddr[3] raddr[4] raddr[5] raddr[6] raddr[7] raddr[8] raddr[9] raddr[10] \ - d_in[0] d_in[1] d_in[2] d_in[3] d_in[4] d_in[5] d_in[6] d_in[7] d_in[8] \ - d_in[9] d_in[10] d_in[11] d_in[12] d_in[13] d_in[14] d_in[15] d_in[16] \ - d_in[17] d_in[18] d_in[19] d_in[20] d_in[21] d_in[22] d_in[23] d_in[24] \ - d_in[25] d_in[26] d_in[27] d_in[28] d_in[29] d_in[30] d_in[31] d_in[32] \ - d_in[33] d_in[34] d_in[35] d_in[36] d_in[37] d_in[38] d_in[39] d_in[40] \ - d_in[41] d_in[42] d_in[43] d_in[44] d_in[45] d_in[46] d_in[47] d_in[48] \ - d_in[49] d_in[50] d_in[51] d_in[52] d_in[53] d_in[54] d_in[55] d_in[56] \ - d_in[57] d_in[58] d_in[59] d_in[60] d_in[61] d_in[62] d_in[63] -.outputs d_out[0] d_out[1] d_out[2] d_out[3] d_out[4] d_out[5] d_out[6] \ - d_out[7] d_out[8] d_out[9] d_out[10] d_out[11] d_out[12] d_out[13] \ - d_out[14] d_out[15] d_out[16] d_out[17] d_out[18] d_out[19] d_out[20] \ - d_out[21] d_out[22] d_out[23] d_out[24] d_out[25] d_out[26] d_out[27] \ - d_out[28] d_out[29] d_out[30] d_out[31] d_out[32] d_out[33] d_out[34] \ - d_out[35] d_out[36] d_out[37] d_out[38] d_out[39] d_out[40] d_out[41] \ - d_out[42] d_out[43] d_out[44] d_out[45] d_out[46] d_out[47] d_out[48] \ - d_out[49] d_out[50] d_out[51] d_out[52] d_out[53] d_out[54] d_out[55] \ - d_out[56] d_out[57] d_out[58] d_out[59] d_out[60] d_out[61] d_out[62] \ - d_out[63] -.blackbox -.end - - -.model adder -.inputs a b cin -.outputs cout sumout -.blackbox -.end - - -.model shift -.inputs D clk -.outputs Q -.blackbox -.end -# End blackbox definition diff --git a/ERI_demo/pipelined_8b_adder.v b/ERI_demo/pipelined_8b_adder.v deleted file mode 100644 index 4d8e975cd..000000000 --- a/ERI_demo/pipelined_8b_adder.v +++ /dev/null @@ -1,63 +0,0 @@ -///////////////////////////////////// -// // -// ERI summit demo-benchmark // -// pipelined_8b_adder.v // -// by Aurelien // -// // -///////////////////////////////////// - -`timescale 1 ns/ 1 ps - -module pipelined_8b_adder( - clk, - raddr, - waddr, - ren, - wen, - a, - b, - q ); - - input clk; - input[5:0] raddr; - input[5:0] waddr; - input ren; - input wen; - input[6:0] a; - input[6:0] b; - output[7:0] q; - - reg[63:0] ram[7:0]; - reg[6:0] a_st0; - reg[6:0] a_st1; - reg[6:0] b_st0; - reg[6:0] b_st1; - reg[8:0] waddr_st0; - reg[8:0] waddr_st1; - reg wen_st0; - reg wen_st1; - reg[7:0] q_int; - - wire[7:0] AplusB; - - assign AplusB = a_st1 + b_st1; - assign q = q_int; - - always@(posedge clk) begin - waddr_st0 <= waddr; - waddr_st1 <= waddr_st0; - a_st0 <= a; - a_st1 <= a_st0; - b_st0 <= b; - b_st1 <= b_st0; - wen_st0 <= wen; - wen_st1 <= wen_st0; - if(wen_st1) begin - ram[waddr_st1] <= AplusB; - end - if(ren) begin - q_int <= ram[raddr]; - end - end - -endmodule diff --git a/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v b/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v deleted file mode 100644 index d43a5b694..000000000 --- a/ERI_demo/pipelined_8b_adder_formal_random_top_tb.v +++ /dev/null @@ -1,219 +0,0 @@ -`timescale 1 ns/ 100 ps - -`include "OPENFPGAPATHKEYWORD/ERI_demo/pipelined_8b_adder.v" - -module pipelined_8b_adder_top_formal_verification_random_tb(); - reg clk; - reg[5:0] raddr; - reg[5:0] waddr; - reg ren; - reg wen; - reg[6:0] a; - reg[6:0] b; - wire[7:0] q_gfpga; - wire[7:0] q_bench; - reg[7:0] q_flag; - - pipelined_8b_adder_top_formal_verification DUT( - .clk_fm (clk), - .raddr_0__fm (raddr[0]), - .raddr_1__fm (raddr[1]), - .raddr_2__fm (raddr[2]), - .raddr_3__fm (raddr[3]), - .raddr_4__fm (raddr[4]), - .raddr_5__fm (raddr[5]), - .waddr_0__fm (waddr[0]), - .waddr_1__fm (waddr[1]), - .waddr_2__fm (waddr[2]), - .waddr_3__fm (waddr[3]), - .waddr_4__fm (waddr[4]), - .waddr_5__fm (waddr[5]), - .ren_fm (ren), - .wen_fm (wen), - .a_0__fm (a[0]), - .a_1__fm (a[1]), - .a_2__fm (a[2]), - .a_3__fm (a[3]), - .a_4__fm (a[4]), - .a_5__fm (a[5]), - .a_6__fm (a[6]), - .b_0__fm (b[0]), - .b_1__fm (b[1]), - .b_2__fm (b[2]), - .b_3__fm (b[3]), - .b_4__fm (b[4]), - .b_5__fm (b[5]), - .b_6__fm (b[6]), - .out_q_0__fm (q_gfpga[0]), - .out_q_1__fm (q_gfpga[1]), - .out_q_2__fm (q_gfpga[2]), - .out_q_3__fm (q_gfpga[3]), - .out_q_4__fm (q_gfpga[4]), - .out_q_5__fm (q_gfpga[5]), - .out_q_6__fm (q_gfpga[6]), - .out_q_7__fm (q_gfpga[7]) - ); - - pipelined_8b_adder ref0( - .clk (clk), - .raddr (raddr), - .waddr (waddr), - .ren (ren), - .wen (wen), - .a (a), - .b (b), - .q (q_bench) - ); - - integer nb_error = 0; - integer count = 0; - integer lim_max = 64 - 1; - integer write_complete = 0; - -//----- Initialization - initial begin - clk <= 1'b0; - a <= 7'h00; - b <= 7'h00; - wen <= 1'b0; - ren <= 1'b0; - waddr <= 9'h000; - raddr <= 9'h000; - while(1) begin - #2.5 - clk <= !clk; - end - end - -//----- Input Stimulis - always@(negedge clk) begin - if(write_complete == 0) begin - wen <= 1'b1; - ren <= 1'b0; - count <= count + 1; - waddr <= waddr + 1; - if(count == lim_max) begin - write_complete = 1; - end - end else begin - wen <= $random; - ren <= $random; - waddr <= $random; - raddr <= $random; - end - a <= $random; - b <= $random; - end - - - always@(negedge clk) begin - if(!(q_gfpga[0] === q_bench[0]) && !(q_bench[0] === 1'bx)) begin - q_flag[0] <= 1'b1; - end else begin - q_flag[0] <= 1'b0; - end - if(!(q_gfpga[1] === q_bench[1]) && !(q_bench[1] === 1'bx)) begin - q_flag[1] <= 1'b1; - end else begin - q_flag[1] <= 1'b0; - end - if(!(q_gfpga[2] === q_bench[2]) && !(q_bench[2] === 1'bx)) begin - q_flag[2] <= 1'b1; - end else begin - q_flag[2] <= 1'b0; - end - if(!(q_gfpga[3] === q_bench[3]) && !(q_bench[3] === 1'bx)) begin - q_flag[3] <= 1'b1; - end else begin - q_flag[3] <= 1'b0; - end - if(!(q_gfpga[4] === q_bench[4]) && !(q_bench[4] === 1'bx)) begin - q_flag[4] <= 1'b1; - end else begin - q_flag[4] <= 1'b0; - end - if(!(q_gfpga[5] === q_bench[5]) && !(q_bench[5] === 1'bx)) begin - q_flag[5] <= 1'b1; - end else begin - q_flag[5] <= 1'b0; - end - if(!(q_gfpga[6] === q_bench[6]) && !(q_bench[6] === 1'bx)) begin - q_flag[6] <= 1'b1; - end else begin - q_flag[6] <= 1'b0; - end - if(!(q_gfpga[7] === q_bench[7]) && !(q_bench[7] === 1'bx)) begin - q_flag[7] <= 1'b1; - end else begin - q_flag[7] <= 1'b0; - end - end - - - always@(posedge q_flag[0]) begin - if(q_flag[0]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[0] at time = %t", $realtime); - end - end - always@(posedge q_flag[1]) begin - if(q_flag[1]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[1] at time = %t", $realtime); - end - end - always@(posedge q_flag[2]) begin - if(q_flag[2]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[2] at time = %t", $realtime); - end - end - always@(posedge q_flag[3]) begin - if(q_flag[3]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[3] at time = %t", $realtime); - end - end - always@(posedge q_flag[4]) begin - if(q_flag[4]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[4] at time = %t", $realtime); - end - end - always@(posedge q_flag[5]) begin - if(q_flag[5]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[5] at time = %t", $realtime); - end - end - always@(posedge q_flag[6]) begin - if(q_flag[6]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[6] at time = %t", $realtime); - end - end - always@(posedge q_flag[7]) begin - if(q_flag[7]) begin - nb_error = nb_error + 1; - $display("Mismatch on q_gfpga[7] at time = %t", $realtime); - end - end - - initial begin - $dumpfile("pipelined_8b_adder_formal.vcd"); - $dumpvars(1, pipelined_8b_adder_top_formal_verification_random_tb); - end - - initial begin - $timeformat(-9, 2, "ns", 20); - $display("Simulation start"); - #1500 // Can be changed by the user for his need - if(nb_error == 0) begin - $display("Simulation Succeed"); - end else begin - $display("Simulation Failed with %d error(s)", nb_error); - end - $finish; - end - -endmodule diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh index 3ee86966a..a1ca429d8 100755 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -28,6 +28,6 @@ perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the # SRAM FPGA # TT case -perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping +perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping -vpr_fpga_x2p_compact_routing_hierarchy echo "Netlists successfully generated and tested" diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index 8007363cf..c93eb7d49 100755 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd - # Run VPR -./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping +./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path From f0ecc51b514ec5e0c718ecf0fd1ac7a63a0a9fe1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Fri, 12 Jul 2019 10:38:20 -0600 Subject: [PATCH 76/84] bug fixing to resolve the conflicts between explicit port map and standard cell map --- .../vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c | 12 +-- .../SRC/fpga_x2p/verilog/verilog_pbtypes.c | 8 +- .../SRC/fpga_x2p/verilog/verilog_primitives.c | 86 +++++++++++-------- 3 files changed, 59 insertions(+), 47 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c index 28e3563cd..5212a83ee 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_utils.c @@ -736,7 +736,7 @@ t_block* search_mapped_block(int x, int y, int z) { assert((0 < x)||(0 == x)); assert((x < (nx + 1))||(x == (nx + 1))); assert((0 < y)||(0 == y)); - assert((x < (ny + 1))||(x == (ny + 1))); + assert((y < (ny + 1))||(y == (ny + 1))); /* Search all blocks*/ for (iblk = 0; iblk < num_blocks; iblk++) { @@ -3479,10 +3479,10 @@ int my_strlen_int(int input_int) { boolean my_bool_to_boolean(bool my_bool) { - if(true == my_bool) + if(true == my_bool) { return TRUE; - if(false == my_bool) - return FALSE; - vpr_printf(TIO_MESSAGE_ERROR,"Failure to convert bool to boolean. Parameter is neither true nor false.\n"); - exit(1); + } else { + assert (false == my_bool); + return FALSE; + } } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c index f75e37f9b..9cd1f6f16 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c @@ -445,7 +445,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp, } } dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "inout", - pb_type_inout_ports[iport], dump_port_type, TRUE); + pb_type_inout_ports[iport], dump_port_type, dump_explicit_port_map); /* Update the counter */ num_dumped_port++; @@ -464,7 +464,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp, } } dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input", - pb_type_input_ports[iport], dump_port_type, TRUE); + pb_type_input_ports[iport], dump_port_type, dump_explicit_port_map); /* Update the counter */ num_dumped_port++; } @@ -482,7 +482,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp, } } dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "output", - pb_type_output_ports[iport], dump_port_type, TRUE); + pb_type_output_ports[iport], dump_port_type, dump_explicit_port_map); /* Update the counter */ num_dumped_port++; } @@ -501,7 +501,7 @@ void dump_verilog_pb_type_bus_ports(FILE* fp, } } dump_verilog_pb_type_one_bus_port(fp, cur_pb_type, formatted_port_prefix, "input", - pb_type_clk_ports[iport], dump_port_type, TRUE); + pb_type_clk_ports[iport], dump_port_type, dump_explicit_port_map); /* Update the counter */ num_dumped_port++; } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c index 0855b6f3e..737917dfb 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c @@ -222,34 +222,41 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, "`endif\n"); } + /* Explicit port map support: turn it on when there is need for the full netlist or just standard cell */ + boolean subckt_require_explicit_port_map = FALSE; + if ( (TRUE == verilog_model->dump_explicit_port_map) || (true == is_explicit_mapping) ) { + subckt_require_explicit_port_map = TRUE; + } + /* Call the subckt*/ fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); fprintf(fp, "\n"); /* Only dump the global ports belonging to a spice_model * Disable recursive here ! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) { fprintf(fp, ",\n"); } /* assert */ num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); /* print ports --> input ports */ - dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping)); + dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, + subckt_require_explicit_port_map); /* IOPADs requires a specical port to output */ if (SPICE_MODEL_IOPAD == verilog_model->type) { fprintf(fp, ",\n"); assert(1 == num_pad_port); assert(NULL != pad_ports[0]); /* Add explicit port mapping if required */ - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ".%s(", pad_ports[0]->lib_name); } /* Print inout port */ fprintf(fp, "%s%s[%d]", gio_inout_prefix, verilog_model->prefix, verilog_model->cnt); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ")"); } fprintf(fp, ", "); @@ -263,7 +270,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, case SPICE_SRAM_SCAN_CHAIN: /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (true == is_explicit_mapping)) { + && (TRUE == subckt_require_explicit_port_map)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -273,7 +280,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 0, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (true == is_explicit_mapping)) { + && (true == subckt_require_explicit_port_map)) { fprintf(fp, ")"); } @@ -284,7 +291,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ", "); /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (true == is_explicit_mapping)) { + && (TRUE == subckt_require_explicit_port_map)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -294,14 +301,14 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 1, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (true == is_explicit_mapping)) { + && (TRUE == verilog_model->dump_explicit_port_map || is_explicit_mapping)) { fprintf(fp, ")"); } break; case SPICE_SRAM_MEMORY_BANK: /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (true == is_explicit_mapping)) { + && (TRUE == subckt_require_explicit_port_map)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -311,7 +318,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 0, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (true == is_explicit_mapping)) { + && (TRUE == subckt_require_explicit_port_map)) { fprintf(fp, ")"); } /* Check if we have an inverterd prefix */ @@ -321,7 +328,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, fprintf(fp, ", "); /* Add explicit port mapping if required */ if ( (0 < num_sram) - && (true == is_explicit_mapping)) { + && (TRUE == subckt_require_explicit_port_map)) { assert( 1 == num_sram_port); assert( NULL != sram_ports[0]); fprintf(fp, ".%s(", @@ -331,7 +338,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_sram - 1, 1, VERILOG_PORT_CONKT); if ( (0 < num_sram) - && (true == is_explicit_mapping)) { + && (TRUE == subckt_require_explicit_port_map)) { fprintf(fp, ")"); } break; @@ -594,6 +601,11 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1); cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info); + /* Explicit port map support: turn it on when there is need for the full netlist or just standard cell */ + boolean subckt_require_explicit_port_map = FALSE; + if ( (TRUE == verilog_model->dump_explicit_port_map) || (true == is_explicit_mapping) ) { + subckt_require_explicit_port_map = TRUE; + } /* Call LUT subckt*/ fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt); fprintf(fp, "\n"); @@ -602,13 +614,13 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, * Only dump the global ports belonging to a spice_model * DISABLE recursive here ! */ - if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) { + if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) { fprintf(fp, ",\n"); } /* Connect inputs*/ /* Connect outputs*/ fprintf(fp, "//----- Input and output ports -----\n"); - dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping)); + dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, subckt_require_explicit_port_map); fprintf(fp, "\n//----- SRAM ports -----\n"); /* check */ @@ -620,88 +632,88 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info, case SPICE_SRAM_STANDALONE: break; case SPICE_SRAM_SCAN_CHAIN: - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ".sram_out( "); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 0, VERILOG_PORT_CONKT); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ")"); } fprintf(fp, ", "); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ".sram_outb( "); } dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 1, VERILOG_PORT_CONKT); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ")"); } if (0 < num_mode_sram) { fprintf(fp, ", "); - if (true == is_explicit_mapping) { + } + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ".mode_out( "); } - dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, - cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, - 0, VERILOG_PORT_CONKT); - if (true == is_explicit_mapping) { + dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, + cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, + 0, VERILOG_PORT_CONKT); + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ")"); } fprintf(fp, ", "); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ".mode_outb( "); } - dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, - cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, - 1, VERILOG_PORT_CONKT); - if (true == is_explicit_mapping) { + dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, + cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, + 1, VERILOG_PORT_CONKT); + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ")"); } - } break; case SPICE_SRAM_MEMORY_BANK: - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ".sram_out( "); } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 0, VERILOG_PORT_CONKT); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ")"); } fprintf(fp, ", "); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ".sram_outb( "); } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram, cur_num_sram + num_lut_sram - 1, 1, VERILOG_PORT_CONKT); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ")"); } if (0 < num_mode_sram) { fprintf(fp, ", "); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ".mode_out( "); } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 0, VERILOG_PORT_CONKT); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ")"); } fprintf(fp, ", "); - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ".mode_outb( "); } dump_verilog_sram_one_outport(fp, cur_sram_orgz_info, cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1, 1, VERILOG_PORT_CONKT); } - if (true == is_explicit_mapping) { + if (TRUE == subckt_require_explicit_port_map) { fprintf(fp, ")"); } break; From d10cc34c9e671a083f4bcdd518ec4b4584ff0591 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 12 Jul 2019 14:56:08 -0600 Subject: [PATCH 77/84] Update Readme and tutorial --- Dockerfile | 2 +- README.md | 11 ++++++----- tutorials/building.md | 5 ++++- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/Dockerfile b/Dockerfile index 4184f0f9c..bcaff4c35 100755 --- a/Dockerfile +++ b/Dockerfile @@ -3,6 +3,6 @@ FROM ubuntu:16.04 RUN apt-get update -qq -y RUN apt-get -y install python3 python3-dev tcl tcl8.6-dev gawk libreadline-dev -RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default +RUN apt-get -y install autoconf automake bison build-essential cmake ctags curl doxygen flex fontconfig g++-4.9 gcc-4.9 gdb git gtkwave gperf iverilog libffi-dev libcairo2-dev libevent-dev libfontconfig1-dev liblist-moreutils-perl libncurses5-dev libx11-dev libxft-dev libxml++2.6-dev perl texinfo time valgrind zip qt5-default diff --git a/README.md b/README.md index e3bb7fb39..8429c4d78 100644 --- a/README.md +++ b/README.md @@ -5,11 +5,11 @@ ## Introduction -OpenFPGA is an extension to VPR. It is an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures. +The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification testbenches/scripts. OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.
## Compilation -The different ways of compiling can be found in the **./compilation** folder.
+The different ways of compiling can be found in the [**./compilation**](https://github.com/LNIS-Projects/OpenFPGA/tree/documentation/compilation) folder.
Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md). **Compilation steps:** @@ -20,7 +20,7 @@ Dependancies and help using docker can be found at [**./tutorials/building.md**] *We currently implemented OpenFPGA for:* -*1. Ubuntu 18.04* +*1. Ubuntu 16.04* *2. Red Hat 7.5* *3. MacOS High Sierra 10.13.4* @@ -31,9 +31,10 @@ OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) incl ## Tutorial -You can find in the folder **./tutorials**. This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them. +You can find in the folder [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/documentation/tutorials). This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them. -Through this tutorial users can learn how to use the flow and set the dependancies. +Through this tutorial users can learn how to use the flow and set the dependancies.
+The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md) will diff --git a/tutorials/building.md b/tutorials/building.md index 7f0666313..3e00855c9 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -40,7 +40,10 @@ OpenFPGA requires all the dependancies listed below: ## Docker -If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. It can be build using the commands: +If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. A container ready to use can be created with the following command: +- docker run -it --rm -v `pwd`:/localfile/OpenFPGA -w=โ€œ/localfile/OpenFPGArโ€ lnis-projects/open_fpga bash + +Or a container where you can build OpenFPGA yourself can be created with the following commands: - docker build . -t open_fpga - docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash
[*docker download link*](https://www.docker.com/products/docker-desktop) From 19ccbce9d07c4b4be776f173f7358195d7d4702e Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 12 Jul 2019 16:18:28 -0600 Subject: [PATCH 78/84] Rename option to use circuit_model rather than spice_model --- .../k6_N10_sram_chain_HC_template.xml | 218 +++++++++--------- vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c | 20 +- vpr7_x2p/libarchfpga/SRC/read_xml_spice.c | 30 +-- 3 files changed, 134 insertions(+), 134 deletions(-) diff --git a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml index 8dca26477..c4642ed55 100644 --- a/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml +++ b/fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml @@ -187,8 +187,8 @@ - - + + @@ -198,9 +198,9 @@ 10e-12 - - - + + + @@ -209,9 +209,9 @@ 10e-12 - - - + + + @@ -220,9 +220,9 @@ 10e-12 - - - + + + @@ -231,9 +231,9 @@ 10e-12 - - - + + + @@ -242,8 +242,8 @@ 10e-12 - - + + @@ -253,8 +253,8 @@ 10e-12 - - + + @@ -268,8 +268,8 @@ 10e-12 5e-12 5e-12 - - + + @@ -282,141 +282,141 @@ 10e-12 10e-12 - - + + - - + + - - + + - - + + - + - - + + - - + + - + - - + + - - + + - + - + - + - - - + + + - - + + - - - - - - - + + + + + + + - - - + + + - - - - - - - + + + + + + + - - + + - + - - - + + + - - + + - - - + + + - - + + - + - + - - + + - - + + - - - + + + - + - + - - - + + + @@ -456,7 +456,7 @@ - + @@ -473,25 +473,25 @@ 2.5x when looking up in Jeff's tables. Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps. This also leads to the switch being 46% of the total wire delay, which is reasonable. --> - + - + - + - + - + 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - + 1 1 1 1 1 1 1 1 1 @@ -515,7 +515,7 @@ - + @@ -616,7 +616,7 @@ - - + - + - + - + - + - + - + diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c index fde8b5472..d852e07dd 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_arch_file.c @@ -1052,9 +1052,9 @@ static void ProcessPb_Type(INOUTP ezxml_t Parent, t_pb_type * pb_type, * We should have a spice_model_name if this mode defines the transistor-level circuit design * Since this is a leaf node */ - pb_type->spice_model_name = my_strdup(FindProperty(Parent, "spice_model_name", FALSE)); + pb_type->spice_model_name = my_strdup(FindProperty(Parent, "circuit_model_name", FALSE)); pb_type->spice_model = NULL; - ezxml_set_attr(Parent, "spice_model_name", NULL); + ezxml_set_attr(Parent, "circuit_model_name", NULL); /* Multi-mode CLB support: * We can read the mode configuration bits if they are defined */ @@ -1400,7 +1400,7 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) { /* Xifan TANG: SPICE Support */ - Prop = FindProperty(Cur, "spice_model_name", FALSE); + Prop = FindProperty(Cur, "circuit_model_name", FALSE); /* Default spice_model will be define later*/ mode->interconnect[i].spice_model_name = my_strdup(Prop); mode->interconnect[i].spice_model = NULL; @@ -1408,7 +1408,7 @@ static void ProcessInterconnect(INOUTP ezxml_t Parent, t_mode * mode) { mode->interconnect[i].fan_in = 0; mode->interconnect[i].fan_out = 0; mode->interconnect[i].num_mux = 0; - ezxml_set_attr(Cur, "spice_model_name", NULL); + ezxml_set_attr(Cur, "circuit_model_name", NULL); /* Get sram offset */ mode->interconnect[i].spice_model_sram_offset = GetIntProperty(Cur, "spice_model_sram_offset", FALSE, 0); ezxml_set_attr(Cur, "spice_model_sram_offset", NULL); @@ -3250,9 +3250,9 @@ static void ProcessSegments(INOUTP ezxml_t Parent, (*Segs)[i].Rmetal = GetFloatProperty(Node, "Rmetal", timing_enabled, 0); (*Segs)[i].Cmetal = GetFloatProperty(Node, "Cmetal", timing_enabled, 0); /* Xifan TANG: SPICE Model Support*/ - (*Segs)[i].spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", FALSE)); + (*Segs)[i].spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", FALSE)); (*Segs)[i].spice_model = NULL; - ezxml_set_attr(Node, "spice_model_name", NULL); + ezxml_set_attr(Node, "circuit_model_name", NULL); /* Get Power info */ /* (*Segs)[i].Cmetal_per_m = GetFloatProperty(Node, "Cmetal_per_m", FALSE, @@ -3528,9 +3528,9 @@ static void ProcessSwitches(INOUTP ezxml_t Parent, FALSE, 1); /* Xifan TANG: Spice Model Support */ - (*Switches)[i].spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", FALSE)); + (*Switches)[i].spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", FALSE)); (*Switches)[i].spice_model = NULL; - ezxml_set_attr(Node, "spice_model_name", NULL); + ezxml_set_attr(Node, "circuit_model_name", NULL); /* Xifan TANG : Read in MUX structure*/ /* Default, we use tree */ structure_type = FindProperty(Node, "structure", FALSE); @@ -3643,9 +3643,9 @@ static void ProcessDirects(INOUTP ezxml_t Parent, OUTP t_direct_inf **Directs, /* Spice Model Support: Xifan TANG * We should have a spice_model_name for this direct connection */ - (*Directs)[i].spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", FALSE)); + (*Directs)[i].spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", FALSE)); (*Directs)[i].spice_model = NULL; - ezxml_set_attr(Node,"spice_model_name",NULL); + ezxml_set_attr(Node,"circuit_model_name",NULL); (*Directs)[i].line = Node->line; diff --git a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c index 82560c359..9e3a511bf 100644 --- a/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c +++ b/vpr7_x2p/libarchfpga/SRC/read_xml_spice.c @@ -451,8 +451,8 @@ static void ProcessSpiceModelBuffer(ezxml_t Node, read_spice_model = FALSE; } - buffer->spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", read_spice_model)); - ezxml_set_attr(Node, "spice_model_name", NULL); + buffer->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", read_spice_model)); + ezxml_set_attr(Node, "circuit_model_name", NULL); /*Find Type*/ Prop = my_strdup(FindProperty(Node, "topology", read_buf_info)); @@ -475,9 +475,9 @@ static void ProcessSpiceModelBuffer(ezxml_t Node, if (0 == strcmp(Prop,"on")) { buffer->tapered_buf = 1; /* Try to dig more properites ...*/ - buffer->tap_buf_level = GetIntProperty(Node, "tap_buf_level", TRUE, 1); + buffer->tap_buf_level = GetIntProperty(Node, "tap_drive_level", TRUE, 1); buffer->f_per_stage = GetIntProperty(Node, "f_per_stage", FALSE, 4); - ezxml_set_attr(Node, "tap_buf_level", NULL); + ezxml_set_attr(Node, "tap_drive_level", NULL); ezxml_set_attr(Node, "f_per_stage", NULL); } else if (0 == strcmp(FindProperty(Node,"tapered",TRUE),"off")) { buffer->tapered_buf = 0; @@ -752,16 +752,16 @@ static void ProcessSpiceModelPort(ezxml_t Node, ezxml_set_attr(Node, "is_config_enable", NULL); /* Check if this port is linked to another spice_model*/ - port->spice_model_name = my_strdup(FindProperty(Node,"spice_model_name",FALSE)); - ezxml_set_attr(Node, "spice_model_name", NULL); + port->spice_model_name = my_strdup(FindProperty(Node,"circuit_model_name",FALSE)); + ezxml_set_attr(Node, "circuit_model_name", NULL); /* For BL/WL, BLB/WLB ports, we need to get the spice_model for inverters */ if ((SPICE_MODEL_PORT_BL == port->type) ||(SPICE_MODEL_PORT_WL == port->type) ||(SPICE_MODEL_PORT_BLB == port->type) ||(SPICE_MODEL_PORT_WLB == port->type)) { - port->inv_spice_model_name = my_strdup(FindProperty(Node, "inv_spice_model_name", FALSE)); - ezxml_set_attr(Node, "inv_spice_model_name", NULL); + port->inv_spice_model_name = my_strdup(FindProperty(Node, "inv_circuit_model_name", FALSE)); + ezxml_set_attr(Node, "inv_circuit_model_name", NULL); } return; @@ -1042,8 +1042,8 @@ static void ProcessSpiceModel(ezxml_t Parent, if (Node) { spice_model->pass_gate_logic = (t_spice_model_pass_gate_logic*)my_malloc(sizeof(t_spice_model_pass_gate_logic)); /* Find spice_model_name */ - spice_model->pass_gate_logic->spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", TRUE)); - ezxml_set_attr(Node, "spice_model_name", NULL); + spice_model->pass_gate_logic->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", TRUE)); + ezxml_set_attr(Node, "circuit_model_name", NULL); FreeNode(Node); } else if ((SPICE_MODEL_MUX == spice_model->type) ||(SPICE_MODEL_LUT == spice_model->type)) { @@ -1106,9 +1106,9 @@ void ProcessSpiceSRAMOrganization(INOUTP ezxml_t Node, return; } - cur_sram_inf_orgz->spice_model_name = my_strdup(FindProperty(Node, "spice_model_name", required)); + cur_sram_inf_orgz->spice_model_name = my_strdup(FindProperty(Node, "circuit_model_name", required)); cur_sram_inf_orgz->spice_model = NULL; - ezxml_set_attr(Node, "spice_model_name", NULL); + ezxml_set_attr(Node, "circuit_model_name", NULL); /* read organization type*/ Prop = FindProperty(Node, "organization", required); @@ -1501,14 +1501,14 @@ void ProcessSpiceSettings(ezxml_t Parent, ProcessSpiceTechLibTransistors(Parent, &(spice->tech_lib)); /* module spice models*/ - Node = FindElement(Parent, "module_spice_models", FALSE); + Node = FindElement(Parent, "module_circuit_models", FALSE); if (Node) { - spice->num_spice_model = CountChildren(Node, "spice_model", 1); + spice->num_spice_model = CountChildren(Node, "circuit_model", 1); /*Alloc*/ spice->spice_models = (t_spice_model*)my_malloc(spice->num_spice_model*sizeof(t_spice_model)); /* Assign each found spice model*/ for (imodel = 0; imodel < spice->num_spice_model; imodel++) { - Cur = FindFirstElement(Node, "spice_model", TRUE); + Cur = FindFirstElement(Node, "circuit_model", TRUE); ProcessSpiceModel(Cur, &(spice->spice_models[imodel])); FreeNode(Cur); } From 1a5c5ff4a64a6d61245946fc1417393f7254b85a Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 12 Jul 2019 16:52:54 -0600 Subject: [PATCH 79/84] Update demo simulation result path --- ERI_demo/ERI.sh | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/ERI_demo/ERI.sh b/ERI_demo/ERI.sh index cd812298c..f585d90b2 100755 --- a/ERI_demo/ERI.sh +++ b/ERI_demo/ERI.sh @@ -3,13 +3,13 @@ # Set variables my_pwd=$PWD -fpga_flow_scripts=${my_pwd}/fpga_flow/scripts -vpr_path=${my_pwd}/vpr7_x2p/vpr +fpga_flow_scripts="${my_pwd}/fpga_flow/scripts" +vpr_path="${my_pwd}/vpr7_x2p/vpr" benchmark="test_modes" include_netlists="_include_netlists.v" compiled_file="compiled_$benchmark" tb_formal_postfix="_top_formal_verification_random_tb" -verilog_output_dirname="${vpr_path}${benchmark}_Verilog" +verilog_dirname="${vpr_path}/${benchmark}_Verilog" log_file="${benchmark}_sim.log" new_reg_sh="${PWD}/ERI_demo/my_eri_demo.sh" template_sh="${PWD}/ERI_demo/eri_demo.sh" @@ -28,7 +28,8 @@ cd $my_pwd # Start the script -> run the fpga generation -> run the simulation -> check the log file source $new_reg_sh # Leave us in vpr folder -iverilog -o $compiled_file $verilog_output_dirname/SRC/$benchmark$include_netlists -s $benchmark$tb_formal_postfix +cd $my_pwd +iverilog -o $compiled_file ${verilog_dirname}/SRC/${benchmark}${include_netlists} -s ${benchmark}${tb_formal_postfix} vvp $compiled_file -j 64 >> $log_file result=`grep "Succeed" $log_file` @@ -36,16 +37,13 @@ if ["$result" = ""]; then result=`grep "Failed" $log_file` if ["$result" = ""]; then echo "Unexpected error, Verification didn't run" - cd $my_pwd exit 1 else echo "Verification failed" - cd $my_pwd exit 2 fi else echo "Verification succeed" + gtkwave ${benchmark}_formal.vcd & fi -gtkwave ${benchmark}_formal.vcd & -cd $my_pwd From 1cf4e785024b16f9b24312c69dab00a1f65df678 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Mon, 15 Jul 2019 21:16:15 -0600 Subject: [PATCH 80/84] Update documentation and help --- README.md | 18 ++++++++---------- .../fpga_bitstream/command_line_usage.rst | 12 +++++++++++- .../source/fpga_verilog/command_line_usage.rst | 4 ---- tutorials/fpga_flow/folder_organization.md | 4 ++-- tutorials/fpga_flow/how2use.md | 4 ++-- tutorials/tutorial_index.md | 4 ++-- vpr7_x2p/vpr/SRC/base/OptionTokens.c | 2 +- vpr7_x2p/vpr/SRC/base/ReadOptions.c | 4 ++-- vpr7_x2p/vpr/SRC/base/vpr_api.c | 4 ++-- vpr7_x2p/vpr/regression_verilog.sh | 2 +- 10 files changed, 31 insertions(+), 27 deletions(-) diff --git a/README.md b/README.md index 8429c4d78..903cad90c 100644 --- a/README.md +++ b/README.md @@ -13,17 +13,15 @@ The different ways of compiling can be found in the [**./compilation**](https:// Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md). **Compilation steps:** -1. Clone the repository (git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA) -2. Create a folder named build in OpenPFGA repository (mkdir build && cd build) -3. Create Makefile in this folder using cmake (cmake .. -DCMAKE_BUILD_TYPE=debug) -4. Compile the tool and its dependencies (make) - -*We currently implemented OpenFPGA for:* - -*1. Ubuntu 16.04* -*2. Red Hat 7.5* -*3. MacOS High Sierra 10.13.4* +1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go into it* +2. mkdir build && cd build # *Create a folder named build in OpenPFGA repository* +3. cmake .. -DCMAKE_BUILD_TYPE=debug # *Create Makefile in this folder using cmake* +4. make # *Compile the tool and its dependencies* +*We currently implemented OpenFPGA for:*
+*1. Ubuntu 16.04*
+*2. Red Hat 7.5*
+*3. MacOS Mojiva 10.13.4*

*Please note that those were the versions we tested the software for. It might work with earlier versions and other distributions.* ## Documentation diff --git a/docs/source/fpga_bitstream/command_line_usage.rst b/docs/source/fpga_bitstream/command_line_usage.rst index 839ac7fa9..278bee494 100644 --- a/docs/source/fpga_bitstream/command_line_usage.rst +++ b/docs/source/fpga_bitstream/command_line_usage.rst @@ -1,4 +1,14 @@ Command-line Options for FPGA Bitstream Generator ================================================= -**Under Construction** \ No newline at end of file +All the command line options of FPGA-Bitstream can be shown by calling the help menu of VPR. Here are all the FPGA-Verilog-related options that you can find: + +FPGA-Verilog Supported Option:: + + --fpga_bitstream_generator + +.. csv-table:: Commmand-line Option of FPGA-Bitstream + :header: "Command Options", "Description" + :widths: 15, 30 + + "--fpga_bitstream_generator", "Turn on the FPGA-Bitstream and output a .bitstream file containing FPGA configuration." diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst index dfe34eaea..656b2ecef 100644 --- a/docs/source/fpga_verilog/command_line_usage.rst +++ b/docs/source/fpga_verilog/command_line_usage.rst @@ -21,7 +21,6 @@ FPGA-Verilog Supported Options:: :widths: 15, 30 "--fpga_verilog", "Turn on the FPGA-Verilog." -<<<<<<< HEAD "--fpga_verilog_dir ", "Specify the directory that all the Verilog files will be outputted to is the destination directory." "--fpga_verilog_include_timing", "Includes the timings found in the XML file." "--fpga_verilog_init_sim", "Initializes the simulation for ModelSim." @@ -30,7 +29,6 @@ FPGA-Verilog Supported Options:: "--fpga_verilog_print_top_testbench", "Print the full-chip-level testbench for the FPGA. Determines the type of autodeck." "--fpga_verilog_print_top_auto_testbench \ ", "Prints the testbench associated with the given benchmark. Determines the type of autodeck." -======= "--fpga_verilog_dir ", "Specify the directory where all the Verilog files will be outputted to. is the destination directory." "--fpga_verilog_include_timing", "Includes the timings found in the XML architecture description file." "--fpga_verilog_include_signal_init", "Set all nets to random value to be close of a real power-on case" @@ -46,8 +44,6 @@ FPGA-Verilog Supported Options:: "--fpga_verilog_print_sdc_pnr", "Generates SDC constraints to PNR" "--fpga_verilog_print_sdc_analysis", "Generates SDC to run timing analysis in PNR tool" "--fpga_verilog_print_user_defined_template", "Generates a template of hierarchy modules and their port mapping" - "", "" ->>>>>>> f56adc681567b73c7826228641e089482dffc009 .. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are: diff --git a/tutorials/fpga_flow/folder_organization.md b/tutorials/fpga_flow/folder_organization.md index 095325ad7..172f10782 100644 --- a/tutorials/fpga_flow/folder_organization.md +++ b/tutorials/fpga_flow/folder_organization.md @@ -17,10 +17,10 @@ In this folder are saved the architecture files. These files are Hardware descri This folder contains benchmarks to implement in the FPGA. it's divided in 3 folders: - **Blif**: Contains .blif and .act file to use in OpenFPGA. Benchmarks are divided in folder with the same name as the top module - **Verilog**: Contains Verilog netlist of benchmarks to use in OpenFPGA. Each project is saved in a folder with the same name as the top module. -- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md#benchmark-list) +- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#benchmark-list) ## configs -This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md#configuration-file) +This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#configuration-file) ## scripts This folder contains scripts call by OpenFPGA flow. Some of them can be used out of the flow as **pro_blif.pl** and **rewrite_path_in_file.pl** which respectively rewrite a blif file with 3 members on a ".latch" module to let it have 5 and replace a keyword in a file.
diff --git a/tutorials/fpga_flow/how2use.md b/tutorials/fpga_flow/how2use.md index 27c9b1db6..656953b3e 100644 --- a/tutorials/fpga_flow/how2use.md +++ b/tutorials/fpga_flow/how2use.md @@ -1,7 +1,7 @@ # FPGA flow This tutorial will help the user to understand how to use OpenFPGA flow.
-During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/folder_organization.md). +During this tutorial we consider the user start in the OpenFPGA folder and we'll use tips and informations provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/folder_organization.md). ## Running fpga_flow.pl @@ -16,7 +16,7 @@ cd fpga_flow
By running this script we took an architecture description file, generated its netlist, generated a bitstream to implement a benchmark on it and verified this implementation.
When you open this file you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allow us to make this tutorial generic by generating full path to dependancies.
-The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/options.md).
+The second one is **fpga_flow.pl**. This script launch OpenFPGA flow and can be used with a lot of [options](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/options.md).
There is 3 important things to see: - All FPGA-Verilog options have been activated - fpga_flow.pl calls a configuration file through "config_file" variable diff --git a/tutorials/tutorial_index.md b/tutorials/tutorial_index.md index c6013d6dc..8198fb6da 100644 --- a/tutorials/tutorial_index.md +++ b/tutorials/tutorial_index.md @@ -3,8 +3,8 @@ OpenFPGA an IP Verilog Generator allowing reliable and fast testing of homogeneous architectures.
Its main goal is to easily and efficiently generated a complete customizable FPGA. It uses a semi-custom design technic.

These tutorials are organized as follow: -* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md) -* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/fpga_flow/how2use.md) +* [Building the tool and his dependancies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md) +* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md) * Architecture modification ## Folder organization diff --git a/vpr7_x2p/vpr/SRC/base/OptionTokens.c b/vpr7_x2p/vpr/SRC/base/OptionTokens.c index a0d765a89..78b956ce3 100644 --- a/vpr7_x2p/vpr/SRC/base/OptionTokens.c +++ b/vpr7_x2p/vpr/SRC/base/OptionTokens.c @@ -102,7 +102,7 @@ struct s_TokenPair OptionBaseTokenList[] = { { "fpga_verilog_print_sdc_analysis", OT_FPGA_VERILOG_SYN_PRINT_SDC_ANALYSIS }, /* Specify the simulator path for Verilog netlists */ /* Xifan Tang: Bitstream generator */ { "fpga_bitstream_generator", OT_FPGA_BITSTREAM_GENERATOR }, /* turn on bitstream generator, and specify the output file */ - { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ + // { "fpga_bitstream_output_file", OT_FPGA_BITSTREAM_OUTPUT_FILE }, /* turn on bitstream generator, and specify the output file */ // AA: temporarily deprecated /* mrFPGA: Xifan TANG */ {"show_sram", OT_SHOW_SRAM}, {"show_pass_trans", OT_SHOW_PASS_TRANS}, diff --git a/vpr7_x2p/vpr/SRC/base/ReadOptions.c b/vpr7_x2p/vpr/SRC/base/ReadOptions.c index b90b90f4f..108e9d355 100644 --- a/vpr7_x2p/vpr/SRC/base/ReadOptions.c +++ b/vpr7_x2p/vpr/SRC/base/ReadOptions.c @@ -562,8 +562,8 @@ ProcessOption(INP char **Args, INOUTP t_options * Options) { /* Xifan TANG: Bitstream generator */ case OT_FPGA_BITSTREAM_GENERATOR: return Args; - case OT_FPGA_BITSTREAM_OUTPUT_FILE: - return ReadString(Args, &Options->fpga_bitstream_file); +// case OT_FPGA_BITSTREAM_OUTPUT_FILE: // AA: temporarily deprecated +// return ReadString(Args, &Options->fpga_bitstream_file); /* mrFPGA: Xifan TANG */ case OT_SHOW_SRAM: case OT_SHOW_PASS_TRANS: diff --git a/vpr7_x2p/vpr/SRC/base/vpr_api.c b/vpr7_x2p/vpr/SRC/base/vpr_api.c index 023b2df92..7d1730883 100644 --- a/vpr7_x2p/vpr/SRC/base/vpr_api.c +++ b/vpr7_x2p/vpr/SRC/base/vpr_api.c @@ -213,8 +213,8 @@ void vpr_print_usage(void) { vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_verilog_print_sdc_analysis\n"); /* Xifan Tang: Bitstream generator */ vpr_printf(TIO_MESSAGE_INFO, "Bitstream Generator Options:\n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator \n"); - vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_output_file \n"); + vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_generator\n"); +// vpr_printf(TIO_MESSAGE_INFO, "\t--fpga_bitstream_output_file \n"); // AA: temporarily deprecated } void vpr_init_file_handler() { diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index c93eb7d49..8007363cf 100755 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -33,7 +33,7 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path cd - # Run VPR -./vpr $arch_xml_file $blif_file --full_stats --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping +./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping cd $fpga_flow_scripts perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path From b810b5cab9457468cbca53dafc533f9558460da5 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Tue, 16 Jul 2019 07:04:45 -0600 Subject: [PATCH 81/84] fpga_flow bug fix + upload k8 architecture --- .../k8_N10_sram_chain_FC_template.xml | 1139 +++++++++++++++++ fpga_flow/scripts/fpga_flow.pl | 6 +- fpga_flow/tuto_fpga_flow.sh | 2 +- vpr7_x2p/vpr/regression_verilog.sh | 2 +- 4 files changed, 1144 insertions(+), 5 deletions(-) create mode 100644 fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml diff --git a/fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml b/fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml new file mode 100644 index 000000000..84d2c3ab3 --- /dev/null +++ b/fpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml @@ -0,0 +1,1139 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + + + + + + + + + 10e-12 0e-12 0e-12 + + + 10e-12 0e-12 0e-12 + + + + + + + + + + + 10e-12 + + + 10e-12 + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 1 + 1 1 + + + + 1 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga_flow/scripts/fpga_flow.pl b/fpga_flow/scripts/fpga_flow.pl index af547d78c..ffe793267 100644 --- a/fpga_flow/scripts/fpga_flow.pl +++ b/fpga_flow/scripts/fpga_flow.pl @@ -1358,9 +1358,6 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) if ("on" eq $opt_ptr->{vpr_fpga_x2p_sim_window_size}) { $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_sim_window_size $opt_ptr->{vpr_fpga_x2p_sim_window_size_val}"; } - if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) { - $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy"; - } if ("on" eq $opt_ptr->{vpr_fpga_spice_sim_mt_num}) { $vpr_spice_opts = $vpr_spice_opts." --fpga_spice_sim_mt_num $opt_ptr->{vpr_fpga_spice_sim_mt_num_val}"; } @@ -1446,6 +1443,9 @@ sub run_std_vpr($ $ $ $ $ $ $ $ $) if ("on" eq $opt_ptr->{vpr_fpga_verilog_explicit_mapping}) { $vpr_spice_opts = $vpr_spice_opts." --fpga_verilog_explicit_mapping"; } + if ("on" eq $opt_ptr->{vpr_fpga_x2p_compact_routing_hierarchy}) { + $vpr_spice_opts = $vpr_spice_opts." --fpga_x2p_compact_routing_hierarchy"; + } } # FPGA Bitstream Generator Options diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh index a1ca429d8..3ee86966a 100755 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -28,6 +28,6 @@ perl rewrite_path_in_file.pl -i $ff_path -k $dir_keyword $verilog_path # Set the # SRAM FPGA # TT case -perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping -vpr_fpga_x2p_compact_routing_hierarchy +perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -power -vpr_fpga_verilog_print_user_defined_template -vpr_fpga_verilog_print_report_timing_tcl -vpr_fpga_verilog_print_sdc_pnr -vpr_fpga_verilog_print_sdc_analysis -vpr_fpga_x2p_compact_routing_hierarchy -end_flow_with_test -vpr_fpga_verilog_explicit_mapping echo "Netlists successfully generated and tested" diff --git a/vpr7_x2p/vpr/regression_verilog.sh b/vpr7_x2p/vpr/regression_verilog.sh index 8007363cf..190ae5523 100755 --- a/vpr7_x2p/vpr/regression_verilog.sh +++ b/vpr7_x2p/vpr/regression_verilog.sh @@ -14,7 +14,7 @@ arch_xml_file="${OpenFPGA_path}/fpga_flow/arch/generated/k6_N10_sram_chain_HC.xm blif_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.blif" act_file="${OpenFPGA_path}/fpga_flow/benchmarks/Blif/Test_Modes/$benchmark.act " verilog_reference="${OpenFPGA_path}/fpga_flow/benchmarks/Verilog/Test_Modes/$benchmark.v" -vpr_route_chan_width="200" +vpr_route_chan_width="300" fpga_flow_script="${OpenFPGA_path}/fpga_flow/scripts" ff_path="$vpr_path/VerilogNetlists/ff.v" new_ff_path="$verilog_output_dirpath/$verilog_output_dirname/SRC/ff.v" From 3d079c942159b5d6dd9594785f1f6377e55aab65 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Tue, 16 Jul 2019 07:20:21 -0600 Subject: [PATCH 82/84] Add folder creation in tuto_fpga_flow.sh to ease the use --- fpga_flow/tuto_fpga_flow.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/fpga_flow/tuto_fpga_flow.sh b/fpga_flow/tuto_fpga_flow.sh index 3ee86966a..72cae371a 100755 --- a/fpga_flow/tuto_fpga_flow.sh +++ b/fpga_flow/tuto_fpga_flow.sh @@ -16,6 +16,9 @@ ff_path="${pwd_path}/../vpr7_x2p/vpr/VerilogNetlists/ff.v" dir_keyword="GENERATED_DIR_KEYWORD" rm -rf ${pwd_path}/results_OpenPithon + +cd ${pwd_path}/arch +mkdir generated # create folder to save rewritten architecture cd ${pwd_path}/scripts # Replace keyword in config and architecture files From a04555419a0d45bc2a92f0200fed9f71a6387ec7 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Tue, 16 Jul 2019 07:30:25 -0600 Subject: [PATCH 83/84] Typo fix --- tutorials/building.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tutorials/building.md b/tutorials/building.md index 3e00855c9..53a4f096d 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -41,7 +41,7 @@ OpenFPGA requires all the dependancies listed below: ## Docker If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. A container ready to use can be created with the following command: -- docker run -it --rm -v `pwd`:/localfile/OpenFPGA -w=โ€œ/localfile/OpenFPGArโ€ lnis-projects/open_fpga bash +- docker run -it --rm -v `pwd`:/localfile/OpenFPGA -w=โ€œ/localfile/OpenFPGAโ€ lnis-projects/open_fpga bash Or a container where you can build OpenFPGA yourself can be created with the following commands: - docker build . -t open_fpga From fe218fc207bd947fda19a177b7f58b1dc9549e58 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Tue, 16 Jul 2019 11:52:24 -0600 Subject: [PATCH 84/84] Tutorial update --- README.md | 10 ++++---- tutorials/building.md | 3 ++- tutorials/fpga_flow/how2use.md | 22 ++++++++++++++++-- .../architectures_schematics/frac_lut8.pdf | Bin 0 -> 77921 bytes .../architectures_schematics/fract_lut6.pdf | Bin 0 -> 63472 bytes 5 files changed, 26 insertions(+), 9 deletions(-) create mode 100644 tutorials/images/architectures_schematics/frac_lut8.pdf create mode 100644 tutorials/images/architectures_schematics/fract_lut6.pdf diff --git a/README.md b/README.md index 903cad90c..54247b5fd 100644 --- a/README.md +++ b/README.md @@ -9,8 +9,8 @@ The OpenFPGA framework is the **first open-source FPGA IP generator** supporting ## Compilation -The different ways of compiling can be found in the [**./compilation**](https://github.com/LNIS-Projects/OpenFPGA/tree/documentation/compilation) folder.
-Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md). +The different ways of compiling can be found in the [**./compilation**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/compilation) folder.
+Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md). **Compilation steps:** 1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go into it* @@ -29,10 +29,8 @@ OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) incl ## Tutorial -You can find in the folder [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/documentation/tutorials). This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them. +You can find in the folder [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/tutorials). This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them. Through this tutorial users can learn how to use the flow and set the dependancies.
-The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md) will - - +The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md) will guide you through trainings and explain folder oraganization as well as referencing tips and used keywords. diff --git a/tutorials/building.md b/tutorials/building.md index 53a4f096d..bc7bc28a9 100644 --- a/tutorials/building.md +++ b/tutorials/building.md @@ -41,7 +41,8 @@ OpenFPGA requires all the dependancies listed below: ## Docker If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. A container ready to use can be created with the following command: -- docker run -it --rm -v `pwd`:/localfile/OpenFPGA -w=โ€œ/localfile/OpenFPGAโ€ lnis-projects/open_fpga bash +- docker run lnis/open_fpga:release
+*Warning: This command is for quick testing. If you want to conserve your work you should certainly use other options as "-v".* Or a container where you can build OpenFPGA yourself can be created with the following commands: - docker build . -t open_fpga diff --git a/tutorials/fpga_flow/how2use.md b/tutorials/fpga_flow/how2use.md index 656953b3e..ab0a3f9f5 100644 --- a/tutorials/fpga_flow/how2use.md +++ b/tutorials/fpga_flow/how2use.md @@ -22,7 +22,7 @@ There is 3 important things to see: - fpga_flow.pl calls a configuration file through "config_file" variable - fpga_flow.pl calls a list of benchmark to implement and test through "bench_txt" variable -## Configuration file +### Configuration file In this file paths have to be full path. Relative path could lead to errors.
The file is organized in 3 parts: @@ -64,7 +64,7 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St *This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf* -## Benchmark list +### Benchmark list The benchmark folder contains 3 sub-folders: * **Blif**: contains .blif and .act of benchmarks @@ -76,3 +76,21 @@ The benchmark list file can contain as many benchmarks as available in the same top_module/*.v,; where is the number of channel/wire between each block. *This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt* + + +## Modifying flow +Once dependancies are understood, we can modify the flow by changing the architecture and the route channel width. + +### Experiment + +* cd OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial +* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto.conf +* cd OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List +* replace "200" with "300" in tuto_benchmark.txt +* cd OPENFPGAPATHKEYWORD/fpga_flow +* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto_fpga_flow.sh +* ./tuto_fpga_flow.sh + +### Explanation + +With this last experiment we replace the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/image/architectures_schematics/frac_lut6.pdf) with a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/image/architectures_schematics/frac_lut8.pdf), which means a 8-inputs fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs). This architecture provides more modes for the CLB and the crossbar changed from a half-connected to a fully connected, implying bigger multiplexor between the CLB and LUT inputs. These requirement in term of interconnection will lead to the increase in routing channel width. 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